// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright (c) 2023 AmadeusGhost <amadeus@jmu.edu.cn>
 */

/dts-v1/;

#include "rk3568-opc-h66k.dtsi"

/ {
	model = "HINLINK OPC-H69K Board";
	compatible = "hinlink,opc-h69k", "rockchip,rk3568";

	aliases {
		ethernet0 = &gmac1;
	};

	vcc5v0_ahci: vcc5v0-ahci-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&sata_pwr_en>;
		regulator-always-on;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-name = "vcc5v0_ahci";
		vin-supply = <&vcc5v0_sys>;
	};
};

&gmac1 {
	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
	assigned-clock-rates = <0>, <125000000>;
	clock_in_out = "output";
	phy-mode = "rgmii-id";
	pinctrl-names = "default";
	pinctrl-0 = <&gmac1m1_miim
		     &gmac1m1_tx_bus2
		     &gmac1m1_rx_bus2
		     &gmac1m1_rgmii_clk
		     &gmac1m1_rgmii_bus>;
	snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 20000 100000>;
	tx_delay = <0x4f>;
	rx_delay = <0x26>;
	phy-handle = <&rgmii_phy1>;
	status = "okay";
};

&mdio1 {
	rgmii_phy1: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x0>;
	};
};

&pinctrl {
	sata {
		sata_pwr_en: sata-pwr-en {
			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&sata0 {
	target-supply = <&vcc5v0_ahci>;
};

&vcc3v3_pcie {
	gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
};
