107 lines
3.5 KiB
Diff
107 lines
3.5 KiB
Diff
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From 8d4209ee0613dfea700bcfc2ecb6052dc9dc9956 Mon Sep 17 00:00:00 2001
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From: CanYang He <hcy@rock-chips.com>
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Date: Tue, 26 Dec 2017 10:19:46 +0800
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Subject: [PATCH] PM / devfreq: event: add support for rk3328 dfi
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This adds the necessary data for handling dfi on the rk3328.
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Change-Id: Id870f78dad3ddd6cb5771674a4e8905322f9e8ef
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Signed-off-by: CanYang He <hcy@rock-chips.com>
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---
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.../bindings/devfreq/event/rockchip-dfi.txt | 1 +
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drivers/devfreq/event/rockchip-dfi.c | 40 ++++++++++++++++++-
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2 files changed, 39 insertions(+), 2 deletions(-)
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--- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
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+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
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@@ -5,6 +5,7 @@ Required properties:
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- compatible: Should be one of the following.
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- "rockchip,rk3128-dfi" - for RK3128 SoCs.
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- "rockchip,rk3288-dfi" - for RK3288 SoCs.
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+ - "rockchip,rk3328-dfi" - for RK3328 SoCs.
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- "rockchip,rk3368-dfi" - for RK3368 SoCs.
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- "rockchip,rk3399-dfi" - for RK3399 SoCs.
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--- a/drivers/devfreq/event/rockchip-dfi.c
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+++ b/drivers/devfreq/event/rockchip-dfi.c
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@@ -36,6 +36,8 @@
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#define RK3288_LPDDR_SEL (0x10001 << 13)
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#define RK3288_DDR3_SEL (0x10000 << 13)
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+#define RK3328_GRF_OS_REG2 0x5d0
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+
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#define RK3368_GRF_DDRC0_CON0 0x600
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#define RK3368_GRF_SOC_STATUS5 0x494
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#define RK3368_GRF_SOC_STATUS6 0x498
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@@ -48,10 +50,10 @@
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#define MAX_DMC_NUM_CH 2
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#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
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#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
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-
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/* DDRMON_CTRL */
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#define DDRMON_CTRL 0x04
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-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
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+#define CLR_DDRMON_CTRL (0x3f0000 << 0)
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+#define DDR4_EN (0x10001 << 5)
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#define LPDDR4_EN (0x10001 << 4)
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#define HARDWARE_EN (0x10001 << 3)
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#define LPDDR3_EN (0x10001 << 2)
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@@ -68,6 +70,7 @@
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#define PMUGRF_OS_REG2 0x308
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enum {
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+ DDR4 = 0,
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DDR3 = 3,
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LPDDR3 = 6,
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LPDDR4 = 7,
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@@ -339,6 +342,8 @@ static void rockchip_dfi_start_hardware_
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writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
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else if (info->dram_type == LPDDR4)
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writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
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+ else if (info->dram_type == DDR4)
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+ writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
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/* enable count, use software mode */
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writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
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@@ -547,9 +552,40 @@ static __init int rockchip_dfi_init(stru
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return 0;
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}
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+static __init int rk3328_dfi_init(struct platform_device *pdev,
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+ struct rockchip_dfi *data,
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+ struct devfreq_event_desc *desc)
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+{
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+ struct device_node *np = pdev->dev.of_node, *node;
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+ struct resource *res;
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+ u32 val;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ data->regs = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(data->regs))
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+ return PTR_ERR(data->regs);
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+
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+ node = of_parse_phandle(np, "rockchip,grf", 0);
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+ if (node) {
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+ data->regmap_grf = syscon_node_to_regmap(node);
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+ if (IS_ERR(data->regmap_grf))
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+ return PTR_ERR(data->regmap_grf);
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+ }
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+
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+ regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
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+ data->dram_type = READ_DRAMTYPE_INFO(val);
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+ data->ch_msk = 1;
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+ data->clk = NULL;
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+
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+ desc->ops = &rockchip_dfi_ops;
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+
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+ return 0;
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+}
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+
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static const struct of_device_id rockchip_dfi_id_match[] = {
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{ .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
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{ .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
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+ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
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{ .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
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{ .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
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{ },
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