From 04b1bf934c94b3aa3097d348601efac1b2c2ba3f Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 7 Aug 2023 01:14:30 +0800 Subject: [PATCH] rockchip: revert rk3588 clk patches This causes clk driver panic. Signed-off-by: Tianling Shen --- ...2-clk-gate-export-clk_gate_endisable.patch | 48 ---- ...3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch | 72 ++++++ ...k-rockchip-add-support-for-gate-link.patch | 226 ------------------ ...ock-rk3588-export-PCLK_VO1GRF-clk-id.patch | 31 --- ...k3588-Adjust-the-GATE_LINK-parameter.patch | 191 --------------- 5 files changed, 72 insertions(+), 496 deletions(-) delete mode 100644 target/linux/rockchip/patches-6.1/111-02-clk-gate-export-clk_gate_endisable.patch create mode 100644 target/linux/rockchip/patches-6.1/111-02-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch delete mode 100644 target/linux/rockchip/patches-6.1/111-03-clk-rockchip-add-support-for-gate-link.patch delete mode 100644 target/linux/rockchip/patches-6.1/111-04-dt-bindings-clock-rk3588-export-PCLK_VO1GRF-clk-id.patch delete mode 100644 target/linux/rockchip/patches-6.1/111-05-clk-rockchip-rk3588-Adjust-the-GATE_LINK-parameter.patch diff --git a/target/linux/rockchip/patches-6.1/111-02-clk-gate-export-clk_gate_endisable.patch b/target/linux/rockchip/patches-6.1/111-02-clk-gate-export-clk_gate_endisable.patch deleted file mode 100644 index 8f87952a96..0000000000 --- a/target/linux/rockchip/patches-6.1/111-02-clk-gate-export-clk_gate_endisable.patch +++ /dev/null @@ -1,48 +0,0 @@ -From: Elaine Zhang -To: mturquette@baylibre.com, sboyd@kernel.org, - kever.yang@rock-chips.com, zhangqing@rock-chips.com, - heiko@sntech.de -Cc: linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, - linux-kernel@vger.kernel.org, huangtao@rock-chips.com -Subject: [PATCH v3 1/4] clk: gate: export clk_gate_endisable -Date: Wed, 2 Aug 2023 15:20:35 +0800 [thread overview] -Message-ID: <20230802072038.29996-2-zhangqing@rock-chips.com> (raw) -In-Reply-To: <20230802072038.29996-1-zhangqing@rock-chips.com> - -make clk_gate_endisable not static, export API for other use. - -Signed-off-by: Elaine Zhang ---- - drivers/clk/clk-gate.c | 3 ++- - include/linux/clk-provider.h | 1 + - 2 files changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/clk/clk-gate.c -+++ b/drivers/clk/clk-gate.c -@@ -53,7 +53,7 @@ static inline void clk_gate_writel(struc - * - * So, result is always: enable xor set2dis. - */ --static void clk_gate_endisable(struct clk_hw *hw, int enable) -+void clk_gate_endisable(struct clk_hw *hw, int enable) - { - struct clk_gate *gate = to_clk_gate(hw); - int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; -@@ -87,6 +87,7 @@ static void clk_gate_endisable(struct cl - else - __release(gate->lock); - } -+EXPORT_SYMBOL_GPL(clk_gate_endisable); - - static int clk_gate_enable(struct clk_hw *hw) - { ---- a/include/linux/clk-provider.h -+++ b/include/linux/clk-provider.h -@@ -609,6 +609,7 @@ struct clk *clk_register_gate(struct dev - void clk_unregister_gate(struct clk *clk); - void clk_hw_unregister_gate(struct clk_hw *hw); - int clk_gate_is_enabled(struct clk_hw *hw); -+void clk_gate_endisable(struct clk_hw *hw, int enable); - - struct clk_div_table { - unsigned int val; diff --git a/target/linux/rockchip/patches-6.1/111-02-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch b/target/linux/rockchip/patches-6.1/111-02-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch new file mode 100644 index 0000000000..f857261676 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/111-02-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch @@ -0,0 +1,72 @@ +From a8dc483b1653a2b99f9b63803b4575ba4a91d8d8 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 13 Jun 2023 16:45:05 +0200 +Subject: [PATCH] clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf + +Currently pclk_vo1grf is not exposed, but it should be referenced +from the vo1_grf syscon, which needs it enabled. That syscon will +be required for HDMI-RX functionality among other things. + +Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates +and need the VO's hclk enabled in addition to their parent clock. + +No Fixes tag has been added, since the logic requiring these clocks +is not yet upstream anyways. + +Signed-off-by: Sebastian Reichel +--- + drivers/clk/rockchip/clk-rk3588.c | 11 +++++------ + include/dt-bindings/clock/rockchip,rk3588-cru.h | 3 ++- + 2 files changed, 7 insertions(+), 7 deletions(-) + +--- a/drivers/clk/rockchip/clk-rk3588.c ++++ b/drivers/clk/rockchip/clk-rk3588.c +@@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588 + RK3588_CLKGATE_CON(56), 0, GFLAGS), + GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 1, GFLAGS), +- GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED, +- RK3588_CLKGATE_CON(55), 10, GFLAGS), + COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(56), 11, GFLAGS), +@@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588 + RK3588_CLKGATE_CON(60), 9, GFLAGS), + GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(60), 10, GFLAGS), +- GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED, +- RK3588_CLKGATE_CON(59), 12, GFLAGS), + GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(59), 14, GFLAGS), + GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0, +@@ -2447,12 +2443,15 @@ static struct rockchip_clk_branch rk3588 + GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), + GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), + GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), +- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), ++ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), + GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), +- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), ++ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), + GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), + GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), + GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), ++ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS), ++ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), ++ + }; + + static void __init rk3588_clk_init(struct device_node *np) +--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h ++++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h +@@ -733,8 +733,9 @@ + #define ACLK_AV1_PRE 718 + #define PCLK_AV1_PRE 719 + #define HCLK_SDIO_PRE 720 ++#define PCLK_VO1GRF 721 + +-#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1) ++#define CLK_NR_CLKS (PCLK_VO1GRF + 1) + + /* scmi-clocks indices */ + diff --git a/target/linux/rockchip/patches-6.1/111-03-clk-rockchip-add-support-for-gate-link.patch b/target/linux/rockchip/patches-6.1/111-03-clk-rockchip-add-support-for-gate-link.patch deleted file mode 100644 index 08c39cd875..0000000000 --- a/target/linux/rockchip/patches-6.1/111-03-clk-rockchip-add-support-for-gate-link.patch +++ /dev/null @@ -1,226 +0,0 @@ -From: Elaine Zhang -To: mturquette@baylibre.com, sboyd@kernel.org, - kever.yang@rock-chips.com, zhangqing@rock-chips.com, - heiko@sntech.de -Cc: linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, - linux-kernel@vger.kernel.org, huangtao@rock-chips.com -Subject: [PATCH v3 2/4] clk: rockchip: add support for gate link -Date: Wed, 2 Aug 2023 15:20:36 +0800 [thread overview] -Message-ID: <20230802072038.29996-3-zhangqing@rock-chips.com> (raw) -In-Reply-To: <20230802072038.29996-1-zhangqing@rock-chips.com> - -Recent Rockchip SoCs have a new hardware block called Native Interface -Unit (NIU), which gates clocks to devices behind them. These effectively -need two parent clocks. -Use GATE_LINK to handle this. - -Signed-off-by: Elaine Zhang ---- - drivers/clk/rockchip/Makefile | 1 + - drivers/clk/rockchip/clk-gate-link.c | 120 +++++++++++++++++++++++++++ - drivers/clk/rockchip/clk.c | 7 ++ - drivers/clk/rockchip/clk.h | 22 +++++ - 4 files changed, 150 insertions(+) - create mode 100644 drivers/clk/rockchip/clk-gate-link.c - ---- a/drivers/clk/rockchip/Makefile -+++ b/drivers/clk/rockchip/Makefile -@@ -13,6 +13,7 @@ clk-rockchip-y += clk-inverter.o - clk-rockchip-y += clk-mmc-phase.o - clk-rockchip-y += clk-muxgrf.o - clk-rockchip-y += clk-ddr.o -+clk-rockchip-y += clk-gate-link.o - clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o - - obj-$(CONFIG_CLK_PX30) += clk-px30.o ---- /dev/null -+++ b/drivers/clk/rockchip/clk-gate-link.c -@@ -0,0 +1,120 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2023 Fuzhou Rockchip Electronics Co., Ltd -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "clk.h" -+ -+/** -+ * struct clk_gate_link - gating link clock -+ * -+ * @gate: handle clk gate -+ * @link: links clk -+ */ -+struct clk_gate_link { -+ struct clk_gate gate; -+ struct clk *link; -+}; -+ -+#define to_clk_gate_link(_gate) container_of(_gate, struct clk_gate_link, gate) -+ -+static int clk_gate_link_enable(struct clk_hw *hw) -+{ -+ struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); -+ -+ clk_gate_endisable(hw, 1); -+ clk_enable(gate->link); -+ -+ return 0; -+} -+ -+static void clk_gate_link_disable(struct clk_hw *hw) -+{ -+ struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); -+ -+ clk_gate_endisable(hw, 0); -+ clk_disable(gate->link); -+} -+ -+static int clk_gate_link_is_enabled(struct clk_hw *hw) -+{ -+ return clk_gate_is_enabled(hw); -+} -+ -+int clk_gate_link_prepare(struct clk_hw *hw) -+{ -+ struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); -+ -+ return clk_prepare(gate->link); -+} -+ -+void clk_gate_link_unprepare(struct clk_hw *hw) -+{ -+ struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); -+ -+ clk_unprepare(gate->link); -+} -+ -+const struct clk_ops clk_gate_link_ops = { -+ .prepare = clk_gate_link_prepare, -+ .unprepare = clk_gate_link_unprepare, -+ .enable = clk_gate_link_enable, -+ .disable = clk_gate_link_disable, -+ .is_enabled = clk_gate_link_is_enabled, -+}; -+ -+struct clk *rockchip_clk_register_gate_link(struct rockchip_clk_provider *ctx, -+ const char *name, const char *parent_name, -+ unsigned int link_id, u8 flags, -+ void __iomem *gate_offset, u8 gate_shift, -+ u8 gate_flags, spinlock_t *lock) -+{ -+ struct clk_gate_link *gate_link; -+ struct clk_init_data init = {}; -+ struct clk **clks; -+ struct clk *clk_link; -+ -+ if (gate_flags & CLK_GATE_HIWORD_MASK) { -+ if (gate_shift > 15) { -+ pr_err("gate bit exceeds LOWORD field\n"); -+ return ERR_PTR(-ENOMEM); -+ } -+ } -+ -+ /* allocate the gate */ -+ gate_link = kzalloc(sizeof(*gate_link), GFP_KERNEL); -+ if (!gate_link) -+ return ERR_PTR(-ENOMEM); -+ -+ clks = ctx->clk_data.clks; -+ gate_link->link = clks[link_id]; -+ -+ init.name = name; -+ init.ops = &clk_gate_link_ops; -+ init.flags = flags; -+ init.parent_names = parent_name ? &parent_name : NULL; -+ init.num_parents = 1; -+ -+ /* struct clk_gate assignments */ -+ gate_link->gate.reg = gate_offset; -+ gate_link->gate.bit_idx = gate_shift; -+ gate_link->gate.flags = gate_flags; -+ gate_link->gate.lock = lock; -+ gate_link->gate.hw.init = &init; -+ -+ clk_link = clk_register(NULL, &gate_link->gate.hw); -+ if (IS_ERR(clk_link)) { -+ kfree(gate_link); -+ pr_err("%s clk_register field\n", name); -+ return ERR_CAST(clk_link); -+ } -+ -+ return clk_link; -+} -+EXPORT_SYMBOL_GPL(rockchip_clk_register_gate_link); ---- a/drivers/clk/rockchip/clk.c -+++ b/drivers/clk/rockchip/clk.c -@@ -510,6 +510,13 @@ void rockchip_clk_register_branches(stru - ctx->reg_base + list->gate_offset, - list->gate_shift, list->gate_flags, &ctx->lock); - break; -+ -+ case branch_gate_link: -+ clk = rockchip_clk_register_gate_link(ctx, list->name, -+ list->parent_names[0], list->link_id, flags, -+ ctx->reg_base + list->gate_offset, -+ list->gate_shift, list->gate_flags, &ctx->lock); -+ break; - case branch_composite: - clk = rockchip_clk_register_branch(list->name, - list->parent_names, list->num_parents, ---- a/drivers/clk/rockchip/clk.h -+++ b/drivers/clk/rockchip/clk.h -@@ -517,6 +517,7 @@ enum rockchip_clk_branch_type { - branch_divider, - branch_fraction_divider, - branch_gate, -+ branch_gate_link, - branch_mmc, - branch_inverter, - branch_factor, -@@ -529,6 +530,7 @@ struct rockchip_clk_branch { - enum rockchip_clk_branch_type branch_type; - const char *name; - const char *const *parent_names; -+ unsigned int link_id; - u8 num_parents; - unsigned long flags; - int muxdiv_offset; -@@ -842,6 +844,20 @@ struct rockchip_clk_branch { - .gate_flags = gf, \ - } - -+#define GATE_LINK(_id, cname, pname, _linkid, f, o, b, gf) \ -+ { \ -+ .id = _id, \ -+ .branch_type = branch_gate_link, \ -+ .name = cname, \ -+ .parent_names = (const char *[]){ pname }, \ -+ .num_parents = 1, \ -+ .link_id = _linkid, \ -+ .flags = f, \ -+ .gate_offset = o, \ -+ .gate_shift = b, \ -+ .gate_flags = gf, \ -+ } -+ - #define MMC(_id, cname, pname, offset, shift) \ - { \ - .id = _id, \ -@@ -1002,6 +1018,12 @@ struct clk *rockchip_clk_register_halfdi - unsigned long flags, - spinlock_t *lock); - -+struct clk *rockchip_clk_register_gate_link(struct rockchip_clk_provider *ctx, -+ const char *name, const char *parent_name, -+ unsigned int link_id, u8 flags, -+ void __iomem *gate_offset, u8 gate_shift, -+ u8 gate_flags, spinlock_t *lock); -+ - #ifdef CONFIG_RESET_CONTROLLER - void rockchip_register_softrst_lut(struct device_node *np, - const int *lookup_table, diff --git a/target/linux/rockchip/patches-6.1/111-04-dt-bindings-clock-rk3588-export-PCLK_VO1GRF-clk-id.patch b/target/linux/rockchip/patches-6.1/111-04-dt-bindings-clock-rk3588-export-PCLK_VO1GRF-clk-id.patch deleted file mode 100644 index 2811c5bf15..0000000000 --- a/target/linux/rockchip/patches-6.1/111-04-dt-bindings-clock-rk3588-export-PCLK_VO1GRF-clk-id.patch +++ /dev/null @@ -1,31 +0,0 @@ -From: Elaine Zhang -To: mturquette@baylibre.com, sboyd@kernel.org, - kever.yang@rock-chips.com, zhangqing@rock-chips.com, - heiko@sntech.de -Cc: linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, - linux-kernel@vger.kernel.org, huangtao@rock-chips.com -Subject: [PATCH v3 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id -Date: Wed, 2 Aug 2023 15:20:37 +0800 [thread overview] -Message-ID: <20230802072038.29996-4-zhangqing@rock-chips.com> (raw) -In-Reply-To: <20230802072038.29996-1-zhangqing@rock-chips.com> - -add PCLK_VO1GRF clk id. - -Signed-off-by: Elaine Zhang ---- - include/dt-bindings/clock/rockchip,rk3588-cru.h | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/include/dt-bindings/clock/rockchip,rk3588-cru.h -+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h -@@ -733,8 +733,9 @@ - #define ACLK_AV1_PRE 718 - #define PCLK_AV1_PRE 719 - #define HCLK_SDIO_PRE 720 -+#define PCLK_VO1GRF 721 - --#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1) -+#define CLK_NR_CLKS (PCLK_VO1GRF + 1) - - /* scmi-clocks indices */ - diff --git a/target/linux/rockchip/patches-6.1/111-05-clk-rockchip-rk3588-Adjust-the-GATE_LINK-parameter.patch b/target/linux/rockchip/patches-6.1/111-05-clk-rockchip-rk3588-Adjust-the-GATE_LINK-parameter.patch deleted file mode 100644 index cece0e5798..0000000000 --- a/target/linux/rockchip/patches-6.1/111-05-clk-rockchip-rk3588-Adjust-the-GATE_LINK-parameter.patch +++ /dev/null @@ -1,191 +0,0 @@ -From: Elaine Zhang -To: mturquette@baylibre.com, sboyd@kernel.org, - kever.yang@rock-chips.com, zhangqing@rock-chips.com, - heiko@sntech.de -Cc: linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, - linux-kernel@vger.kernel.org, huangtao@rock-chips.com -Subject: [PATCH v3 4/4] clk: rockchip: rk3588: Adjust the GATE_LINK parameter -Date: Wed, 2 Aug 2023 15:20:38 +0800 [thread overview] -Message-ID: <20230802072038.29996-5-zhangqing@rock-chips.com> (raw) -In-Reply-To: <20230802072038.29996-1-zhangqing@rock-chips.com> - -Export PCLK_VO1GRF clk id. -Using Id instead of name, if use name needs to use __clk_lookup(). -But __clk_lookup() is not exported and is not friendly for GKI. - -Signed-off-by: Elaine Zhang ---- - drivers/clk/rockchip/clk-rk3588.c | 110 ++++++++++++++++-------------- - 1 file changed, 59 insertions(+), 51 deletions(-) - ---- a/drivers/clk/rockchip/clk-rk3588.c -+++ b/drivers/clk/rockchip/clk-rk3588.c -@@ -12,28 +12,6 @@ - #include - #include "clk.h" - --/* -- * Recent Rockchip SoCs have a new hardware block called Native Interface -- * Unit (NIU), which gates clocks to devices behind them. These effectively -- * need two parent clocks. -- * -- * Downstream enables the linked clock via runtime PM whenever the gate is -- * enabled. This implementation uses separate clock nodes for each of the -- * linked gate clocks, which leaks parts of the clock tree into DT. -- * -- * The GATE_LINK macro instead takes the second parent via 'linkname', but -- * ignores the information. Once the clock framework is ready to handle it, the -- * information should be passed on here. But since these clocks are required to -- * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked -- * clocks critical until a better solution is available. This will waste some -- * power, but avoids leaking implementation details into DT or hanging the -- * system. -- */ --#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \ -- GATE(_id, cname, pname, f, o, b, gf) --#define RK3588_LINKED_CLK CLK_IS_CRITICAL -- -- - #define RK3588_GRF_SOC_STATUS0 0x600 - #define RK3588_PHYREF_ALT_GATE 0xc38 - -@@ -1456,7 +1434,7 @@ static struct rockchip_clk_branch rk3588 - COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, - RK3588_CLKGATE_CON(31), 0, GFLAGS), -- COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK, -+ COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, - RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, - RK3588_CLKGATE_CON(31), 1, GFLAGS), - GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, -@@ -1685,13 +1663,13 @@ static struct rockchip_clk_branch rk3588 - RK3588_CLKGATE_CON(42), 9, GFLAGS), - - /* vdpu */ -- COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK, -+ COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, - RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(44), 0, GFLAGS), - COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, - RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, - RK3588_CLKGATE_CON(44), 1, GFLAGS), -- COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, -+ COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, - RK3588_CLKGATE_CON(44), 2, GFLAGS), - COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, -@@ -1742,9 +1720,9 @@ static struct rockchip_clk_branch rk3588 - COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, - RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, - RK3588_CLKGATE_CON(47), 1, GFLAGS), -- GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK, -+ GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, - RK3588_CLKGATE_CON(47), 4, GFLAGS), -- GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK, -+ GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, - RK3588_CLKGATE_CON(47), 5, GFLAGS), - COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, - RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, -@@ -1754,10 +1732,10 @@ static struct rockchip_clk_branch rk3588 - RK3588_CLKGATE_CON(48), 6, GFLAGS), - - /* vi */ -- COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK, -+ COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, - RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(49), 0, GFLAGS), -- COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, -+ COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, - RK3588_CLKGATE_CON(49), 1, GFLAGS), - COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, -@@ -1929,10 +1907,10 @@ static struct rockchip_clk_branch rk3588 - COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, - RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(52), 0, GFLAGS), -- COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK, -+ COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, - RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, - RK3588_CLKGATE_CON(52), 1, GFLAGS), -- COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, -+ COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, - RK3588_CLKGATE_CON(52), 2, GFLAGS), - COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, -@@ -2433,26 +2411,56 @@ static struct rockchip_clk_branch rk3588 - GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, - RK3588_CLKGATE_CON(68), 2, GFLAGS), - -- GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), -- GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), -- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), -- GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), -- GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), -- GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), -- GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), -- GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), -- GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), -- GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), -- GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), -- GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), -- GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), -- GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), -- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), -- GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), -- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), -- GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), -- GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), -- GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), -+ /* -+ * Recent Rockchip SoCs have a new hardware block called Native Interface -+ * Unit (NIU), which gates clocks to devices behind them. These effectively -+ * need two parent clocks. -+ */ -+ GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, -+ RK3588_CLKGATE_CON(26), 6, GFLAGS), -+ GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, -+ RK3588_CLKGATE_CON(26), 8, GFLAGS), -+ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, 0, -+ RK3588_CLKGATE_CON(31), 2, GFLAGS), -+ GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, -+ RK3588_CLKGATE_CON(42), 2, GFLAGS), -+ GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, -+ RK3588_CLKGATE_CON(42), 3, GFLAGS), -+ GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", -+ ACLK_VDPU_ROOT, 0, -+ RK3588_CLKGATE_CON(44), 7, GFLAGS), -+ GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, -+ RK3588_CLKGATE_CON(44), 5, GFLAGS), -+ GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, -+ RK3588_CLKGATE_CON(48), 3, GFLAGS), -+ GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, -+ RK3588_CLKGATE_CON(48), 2, GFLAGS), -+ GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, -+ RK3588_CLKGATE_CON(40), 5, GFLAGS), -+ GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, -+ RK3588_CLKGATE_CON(40), 6, GFLAGS), -+ GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, -+ RK3588_CLKGATE_CON(41), 4, GFLAGS), -+ GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, -+ RK3588_CLKGATE_CON(41), 5, GFLAGS), -+ GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, -+ RK3588_CLKGATE_CON(55), 9, GFLAGS), -+ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, 0, -+ RK3588_CLKGATE_CON(55), 5, GFLAGS), -+ GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, -+ RK3588_CLKGATE_CON(59), 6, GFLAGS), -+ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, 0, -+ RK3588_CLKGATE_CON(59), 9, GFLAGS), -+ GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, -+ RK3588_CLKGATE_CON(68), 1, GFLAGS), -+ GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, -+ RK3588_CLKGATE_CON(68), 4, GFLAGS), -+ GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, -+ RK3588_CLKGATE_CON(75), 1, GFLAGS), -+ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, -+ RK3588_CLKGATE_CON(55), 10, GFLAGS), -+ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, -+ RK3588_CLKGATE_CON(59), 12, GFLAGS), - }; - - static void __init rk3588_clk_init(struct device_node *np)