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CN_SZTL 2019-12-11 23:19:21 +08:00
commit 062a94d677
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23 changed files with 550 additions and 268 deletions
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5
package/lean/luci-app-ssr-plus/luasrc/model/cbi/shadowsocksr/log.lua
View File

@ -2,7 +2,8 @@ local fs = require "nixio.fs"
local conffile = "/tmp/ssrpro.log"
f = SimpleForm("logview")
f.reset = false
f.submit = false
t = f:field(TextValue, "conf")
t.rmempty = true
t.rows = 20
@ -12,4 +13,4 @@ function t.cfgvalue()
end
t.readonly="readonly"
return f
return f

2
package/lean/luci-app-ssr-plus/root/etc/init.d/shadowsocksr
View File

@ -360,7 +360,7 @@ start_redir() {
lua /usr/share/shadowsocksr/gentrojanconfig.lua $GLOBAL_SERVER client 10801 > /var/etc/trojan-ssr-reudp.json
sed -i 's/\\//g' /var/etc/trojan-ssr-reudp.json
$ucmd --config /var/etc/trojan-ssr-reudp.json >/dev/null 2>&1 &
ipt2socks -U -4 -b 0.0.0.0 -s 127.0.0.1 -p 10801 -l $(uci_get_by_name $UDP_RELAY_SERVER local_port) >/dev/null 2>&1
ipt2socks -U -4 -b 0.0.0.0 -s 127.0.0.1 -p 10801 -l $(uci_get_by_name $UDP_RELAY_SERVER local_port) >/dev/null 2>&1 &
fi
fi

2
target/linux/gemini/Makefile
View File

@ -24,7 +24,7 @@ KERNELNAME:=zImage dtbs
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += \
kmod-usb-core kmod-usb-fotg210 \
kmod-usb-fotg210 \
kmod-usb-ledtrig-usbport \
kmod-leds-gpio kmod-ledtrig-heartbeat \
kmod-gpio-button-hotplug

6
target/linux/gemini/base-files/lib/preinit/05_set_ether_mac_gemini
View File

@ -17,7 +17,7 @@ set_ether_mac() {
if [ -n "$part" ]; then
DEVID="$(dd if=$part bs=1 skip=119508 count=7 2>/dev/null)"
if [ "$DEVID" = "dns-313" ]; then
MAC1="$(mtd_get_mac_binary RedBoot 119540)"
MAC1="$(mtd_get_mac_binary RedBoot 0x1d2f4)"
ip link set eth0 address "$MAC1" 2>/dev/null
return 0
fi
@ -30,8 +30,8 @@ set_ether_mac() {
if [ -n "$part" ] ; then
DEVID="$(dd if=$part bs=1 skip=81516 count=7 2>/dev/null)"
if [ "$DEVID" = "ILI9322" ] ; then
MAC1=$(mtd_get_mac_binary RedBoot 95040)
MAC2=$(mtd_get_mac_binary RedBoot 95046)
MAC1=$(mtd_get_mac_binary RedBoot 0x17340)
MAC2=$(mtd_get_mac_binary RedBoot 0x17346)
ip link set eth0 address "$MAC1" 2>/dev/null
ip link set eth1 address "$MAC2" 2>/dev/null
return 0

1
target/linux/gemini/config-4.19
View File

@ -146,6 +146,7 @@ CONFIG_DRM=y
CONFIG_DRM_BRIDGE=y
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_GEM_CMA_HELPER=y
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
CONFIG_DRM_KMS_CMA_HELPER=y

53
target/linux/gemini/image/Makefile
View File

@ -7,6 +7,10 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
define Build/copy-kernel.bin
$(call locked,$(MAKE) -C copy-kernel CROSS_COMPILE=$(TARGET_CROSS) O=$(KDIR),gemini-copy-kernel.bin)
endef
# Cook a "WRGG" image, this board is apparently one in the D-Link
# WRGG family and uses the exact same firmware format as other
# D-Link devices.
@ -76,18 +80,28 @@ endef
# Create the default image format used by the StorLink reference design
# SL93512r, Raidsonic NAS4220B and Itian Square One SQ201
# with the squashfs and overlay inside the "rd.gz" file.
# We pad it out to 6144K which is the size of the initramfs partition.
# with the squashfs and overlay inside the "application" partition.
#
# The "application" partition is just blank. You can put anything
# there when using OpenWRT. We just use that to create the
# "sysupgrade" firmware image.
# These devices have a hard-coded partition table that the boot loader
# constantly reflashes back, so we need to work around it like this:
#
# 0x000000120000-0x000000320000 : "Kern" - small copy routine and first
# part of the kernel goes here
# 0x000000320000-0x000000920000 : "Ramdisk" - second part of the kernel and
# some padding goes here
# 0x000000920000-0x000000f20000 : "Application" - rootfs goes here
define Build/storlink-default-images
mkdir -p $@.tmp
mv $@ $@.tmp/rd.gz
dd if=/dev/zero of=$@.tmp/hddapp.tgz bs=6144k count=1
cp $(IMAGE_KERNEL) $@.tmp/zImage
# "App" partition is the rootfs
mv $@ $@.tmp/hddapp.tgz
# 256 bytes copy routine
dd if=$(KDIR)/copy-kernel.bin of=$@.tmp/zImage
$(call Image/pad-to,$@.tmp/zImage,512)
# Copy first part of the kernel into zImage
dd if=$(IMAGE_KERNEL) of=$@.tmp/zImage bs=1 seek=512 count=2096640
# Put the rest of the kernel into the "ramdisk"
dd if=$(IMAGE_KERNEL) of=$@.tmp/rd.gz bs=1 skip=2096640 count=6144k conv=sync
cp ./ImageInfo-$(1) $@.tmp/ImageInfo
sed -i -e "s/DATESTR/`date +%Y%m%d $(if $(SOURCE_DATE_EPOCH),--date "@$(SOURCE_DATE_EPOCH)")`/g" $@.tmp/ImageInfo
@ -140,7 +154,8 @@ GEMINI_NAS_PACKAGES:=kmod-md-mod kmod-md-linear kmod-md-multipath \
# This will be flashed from OpenWrt userland anyways so we only need
# the minimum to make the boot loader happy.
define Device/dlink_dir-685
DEVICE_TITLE := D-Link DIR-685 Xtreme N Storage Router
DEVICE_VENDOR := D-Link
DEVICE_MODEL := DIR-685 Xtreme N Storage Router
DEVICE_DTS := gemini-dlink-dir-685
DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES) \
kmod-rt2800-pci
@ -152,7 +167,8 @@ endef
TARGET_DEVICES += dlink_dir-685
define Device/dlink_dns-313
DEVICE_TITLE := D-Link DNS-313 1-Bay Network Storage Enclosure
DEVICE_VENDOR := D-Link
DEVICE_MODEL := DNS-313 1-Bay Network Storage Enclosure
DEVICE_DTS := gemini-dlink-dns-313
DEVICE_TYPE := nas
DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES)
@ -165,6 +181,8 @@ TARGET_DEVICES += dlink_dns-313
# Default images setup used by the StorLink reference designs
define Device/storlink-reference
COMPILE := copy-kernel-$(1).bin
COMPILE/copy-kernel-$(1).bin := copy-kernel.bin
IMAGES := factory.bin
IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to 6144k | \
storlink-default-images $(1)
@ -173,7 +191,8 @@ endef
define Device/itian_sq201
$(Device/storlink-reference)
DEVICE_TITLE := ITian Square One SQ201
DEVICE_VENDOR := ITian
DEVICE_MODEL := Square One SQ201
DEVICE_DTS := gemini-sq201
DEVICE_PACKAGES += kmod-rt61-pci kmod-usb2-pci
endef
@ -181,7 +200,8 @@ TARGET_DEVICES += itian_sq201
define Device/raidsonic_ib-4220-b
$(Device/storlink-reference)
DEVICE_TITLE := Raidsonic NAS IB-4220-B
DEVICE_VENDOR := Raidsonic
DEVICE_MODEL := NAS IB-4220-B
DEVICE_DTS := gemini-nas4220b
DEVICE_TYPE := nas
endef
@ -189,7 +209,8 @@ TARGET_DEVICES += raidsonic_ib-4220-b
define Device/storlink_sl93512r
$(Device/storlink-reference)
DEVICE_TITLE := StorLink SL93512r
DEVICE_VENDOR := StorLink
DEVICE_MODEL := SL93512r
DEVICE_DTS := gemini-sl93512r
endef
TARGET_DEVICES += storlink_sl93512r
@ -204,7 +225,8 @@ TARGET_DEVICES += storlink_sl93512r
# and rootfs. It is expected that the OEM firmware adjusts the on flash
# partition table with the values defined in the image header.
define Device/wiliboard_wbd111
DEVICE_TITLE := Wiliboard WBD-111
DEVICE_VENDOR := Wiliboard
DEVICE_MODEL := WBD-111
DEVICE_DTS := gemini-wbd111
KERNEL := kernel-bin | append-dtb | wbd-nops
IMAGES := factory.bin
@ -212,7 +234,8 @@ define Device/wiliboard_wbd111
endef
define Device/wiliboard_wbd222
DEVICE_TITLE := Wiliboard WBD-222
DEVICE_VENDOR := Wiliboard
DEVICE_MODEL := WBD-222
DEVICE_DTS := gemini-wbd222
KERNEL := kernel-bin | append-dtb | wbd-nops
IMAGES := factory.bin

1
target/linux/gemini/image/copy-kernel/.gitignore vendored Normal file
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@ -0,0 +1 @@
copy-kernel.bin

38
target/linux/gemini/image/copy-kernel/Makefile Normal file
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@ -0,0 +1,38 @@
#
# Makefile for Gemin kernel copy stub
#
# Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License version 2 as published
# by the Free Software Foundation.
#
AS := $(CROSS_COMPILE)as
OBJCOPY := $(CROSS_COMPILE)objcopy
BIN_FLAGS := -O binary -S
SRC_DIR := $(CURDIR)/
OUT_DIR := $(if $(O),$(if $(patsubst %/,,$(O)),$(O)/,$(O)),$(SRC_DIR))
all: $(OUT_DIR)copy-kernel.bin
# Don't build dependencies, this may die if $(CC) isn't gcc
dep:
install:
$(OUT_DIR):
mkdir -p $(OUT_DIR)
$(OUT_DIR)%.o : $(SRC_DIR)%.S | $(OUT_DIR)
$(AS) $(ASFLAGS) -k -o $@ $<
$(OUT_DIR)%.bin: $(OUT_DIR)%.o
$(OBJCOPY) $(BIN_FLAGS) $< $@
mrproper: clean
clean:
rm -f $(OUT_DIR)copy-kernel.bin $(OUT_DIR)copy-kernel.o

45
target/linux/gemini/image/copy-kernel/copy-kernel.S Normal file
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@ -0,0 +1,45 @@
// Arm assembly to copy the Gemini kernel on Storlink reference
// designs and derived devices with the same flash layout and
// boot loader.
//
// This will execute at 0x01600000
//
// Copies the kernel from two fragments (originally zImage
// and initramdisk) to 0x00400000 making space for a kernel
// image of up to 8 MB except for these 512 bytes used for
// this bootstrap.
//
// 0x01600200 .. 0x017fffff -> 0x00400000 .. 0x005ffdff
// 0x00800000 .. 0x00dfffff -> 0x005ffe00 .. 0x00bffdff
// Memory used for this bootstrap
.equ BOOT_HEADROOM, 0x200
.global _start // Stand-alone assembly code
_start:
mov r1, #0x01600000
mov r2, #0x00400000
mov r3, #0x00200000
add r1, r1, #BOOT_HEADROOM
sub r3, r3, #BOOT_HEADROOM
copyloop1:
ldr r0, [r1]
str r0, [r2]
add r1, r1, #4
add r2, r2, #4
sub r3, r3, #4
cmp r3, #0
bne copyloop1
mov r1, #0x00800000
mov r3, #0x00600000
copyloop2:
ldr r0, [r1]
str r0, [r2]
add r1, r1, #4
add r2, r2, #4
sub r3, r3, #4
cmp r3, #0
bne copyloop2
mov r0, #0x00400000
// Let's go
mov pc, r0

2
target/linux/gemini/image/dns313_gen_hdd_img.sh
View File

@ -17,7 +17,7 @@ sect=63
# Create two empty partitions followed by the boot partition with
# the ./boot/zImage and then the rootfs partition.
set `ptgen -o $OUTPUT -h $head -s $sect -t 83 -n -p 0 -p 0 -p ${BOOTFSSIZE}M -p ${ROOTFSSIZE}M`
set $(ptgen -o $OUTPUT -h $head -s $sect -t 83 -n -p 0 -p 0 -p ${BOOTFSSIZE}M -p ${ROOTFSSIZE}M)
BOOTOFFSET="$(($1 / 512))"
BOOTSIZE="$(($2 / 512))"

19
target/linux/gemini/patches-4.19/0008-ARM-dts-Enable-Gemini-flash-access.patch
View File

@ -1,7 +1,7 @@
From 74631102645df8984acbdf67b731e4d437f27fed Mon Sep 17 00:00:00 2001
From 928681e6b46cb70317f7721aae8435ea89fcfd80 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Thu, 11 Oct 2018 20:06:23 +0200
Subject: [PATCH 08/18] ARM: dts: Enable Gemini flash access
Subject: [PATCH] ARM: dts: Enable Gemini flash access
Some Gemini platforms have a parallel NOR flash which conflicts
with use cases reusing some of the flash lines (such as CE1)
@ -16,9 +16,9 @@ access.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/gemini-dlink-dir-685.dts | 35 +++++++++++++++-------
arch/arm/boot/dts/gemini-sq201.dts | 31 ++++++++++---------
2 files changed, 41 insertions(+), 25 deletions(-)
arch/arm/boot/dts/gemini-dlink-dir-685.dts | 33 +++++++++++++++-------
arch/arm/boot/dts/gemini-sq201.dts | 31 +++++++++++---------
2 files changed, 40 insertions(+), 24 deletions(-)
--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
@ -84,15 +84,6 @@ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl-gmii {
mux {
function = "gmii";
@@ -430,7 +443,7 @@
};
display-controller@6a000000 {
- status = "okay";
+ status = "disabled";
port@0 {
reg = <0>;
--- a/arch/arm/boot/dts/gemini-sq201.dts
+++ b/arch/arm/boot/dts/gemini-sq201.dts
@@ -41,14 +41,12 @@

46
target/linux/gemini/patches-4.19/0011-ARM-dts-Fix-up-SQ201-flash-access.patch
View File

@ -19,50 +19,8 @@ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
};
chosen {
- bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
+ bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
- bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
+ bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait";
stdout-path = &uart0;
};
@@ -131,37 +131,10 @@
/* 16MB of flash */
reg = <0x30000000 0x01000000>;
- partition@0 {
- label = "RedBoot";
- reg = <0x00000000 0x00120000>;
- read-only;
- };
- partition@120000 {
- label = "Kernel";
- reg = <0x00120000 0x00200000>;
- };
- partition@320000 {
- label = "Ramdisk";
- reg = <0x00320000 0x00600000>;
- };
- partition@920000 {
- label = "Application";
- reg = <0x00920000 0x00600000>;
- };
- partition@f20000 {
- label = "VCTL";
- reg = <0x00f20000 0x00020000>;
- read-only;
- };
- partition@f40000 {
- label = "CurConf";
- reg = <0x00f40000 0x000a0000>;
- read-only;
- };
- partition@fe0000 {
- label = "FIS directory";
- reg = <0x00fe0000 0x00020000>;
- read-only;
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0xfe0000 */
+ fis-index-block = <0x1fc>;
};
};

6
target/linux/gemini/patches-4.19/0013-usb-host-fotg2-add-silicon-clock-handling.patch
View File

@ -36,7 +36,7 @@ ChangeLog v1->v2:
#include <asm/byteorder.h>
#include <asm/irq.h>
@@ -5596,7 +5597,7 @@ static int fotg210_hcd_probe(struct plat
@@ -5600,7 +5601,7 @@ static int fotg210_hcd_probe(struct plat
hcd->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(hcd->regs)) {
retval = PTR_ERR(hcd->regs);
@ -45,7 +45,7 @@ ChangeLog v1->v2:
}
hcd->rsrc_start = res->start;
@@ -5606,22 +5607,42 @@ static int fotg210_hcd_probe(struct plat
@@ -5610,22 +5611,42 @@ static int fotg210_hcd_probe(struct plat
fotg210->caps = hcd->regs;
@ -91,7 +91,7 @@ ChangeLog v1->v2:
usb_put_hcd(hcd);
fail_create_hcd:
dev_err(dev, "init %s fail, %d\n", dev_name(dev), retval);
@@ -5637,6 +5658,10 @@ static int fotg210_hcd_remove(struct pla
@@ -5641,6 +5662,10 @@ static int fotg210_hcd_remove(struct pla
{
struct device *dev = &pdev->dev;
struct usb_hcd *hcd = dev_get_drvdata(dev);

104
target/linux/gemini/patches-4.19/0022-RM-dts-gemini-Switch-to-redboot-partition-parsing.patch Normal file
View File

@ -0,0 +1,104 @@
From cad2161e64aca9e1c94fd11b0d0f7b53c9e80de0 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Fri, 12 Jul 2019 22:57:11 +0200
Subject: [PATCH 1/2] ARM: dts: gemini: Switch to redboot partition parsing
This switches the kernel to parse the Redboot partitions
in the SL93512r and the NAS4220B properly using the
right compatible string instead of using hard-coded
partitions.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/gemini-nas4220b.dts | 35 +++------------------------
arch/arm/boot/dts/gemini-sl93512r.dts | 35 +++------------------------
2 files changed, 8 insertions(+), 62 deletions(-)
--- a/arch/arm/boot/dts/gemini-nas4220b.dts
+++ b/arch/arm/boot/dts/gemini-nas4220b.dts
@@ -81,37 +81,10 @@
/* 16MB of flash */
reg = <0x30000000 0x01000000>;
- partition@0 {
- label = "RedBoot";
- reg = <0x00000000 0x00020000>;
- read-only;
- };
- partition@20000 {
- label = "Kernel";
- reg = <0x00020000 0x00300000>;
- };
- partition@320000 {
- label = "Ramdisk";
- reg = <0x00320000 0x00600000>;
- };
- partition@920000 {
- label = "Application";
- reg = <0x00920000 0x00600000>;
- };
- partition@f20000 {
- label = "VCTL";
- reg = <0x00f20000 0x00020000>;
- read-only;
- };
- partition@f40000 {
- label = "CurConf";
- reg = <0x00f40000 0x000a0000>;
- read-only;
- };
- partition@fe0000 {
- label = "FIS directory";
- reg = <0x00fe0000 0x00020000>;
- read-only;
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0xfe0000 */
+ fis-index-block = <0x1fc>;
};
};
--- a/arch/arm/boot/dts/gemini-sl93512r.dts
+++ b/arch/arm/boot/dts/gemini-sl93512r.dts
@@ -143,37 +143,10 @@
/* 16MB of flash */
reg = <0x30000000 0x01000000>;
- partition@0 {
- label = "BOOT";
- reg = <0x00000000 0x00020000>;
- read-only;
- };
- partition@120000 {
- label = "Kern";
- reg = <0x00020000 0x00300000>;
- };
- partition@320000 {
- label = "Ramdisk";
- reg = <0x00320000 0x00600000>;
- };
- partition@920000 {
- label = "Application";
- reg = <0x00920000 0x00600000>;
- };
- partition@f20000 {
- label = "VCTL";
- reg = <0x00f20000 0x00020000>;
- read-only;
- };
- partition@f40000 {
- label = "CurConf";
- reg = <0x00f40000 0x000a0000>;
- read-only;
- };
- partition@fe0000 {
- label = "FIS directory";
- reg = <0x00fe0000 0x00020000>;
- read-only;
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0xfe0000 */
+ fis-index-block = <0x1fc>;
};
};

36
target/linux/gemini/patches-4.19/0023-ARM-dts-gemini-Mount-root-from-mtdblock3.patch Normal file
View File

@ -0,0 +1,36 @@
From b40cd2116ea0ba3584db12ab9dab7e02dd1e3333 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Fri, 12 Jul 2019 22:59:39 +0200
Subject: [PATCH 2/2] ARM: dts: gemini: Mount root from mtdblock3
The third mtdblock device named "Application" is where we
want to mount our root filesystem.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/gemini-nas4220b.dts | 2 +-
arch/arm/boot/dts/gemini-sl93512r.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm/boot/dts/gemini-nas4220b.dts
+++ b/arch/arm/boot/dts/gemini-nas4220b.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "console=ttyS0,19200n8";
+ bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait";
stdout-path = &uart0;
};
--- a/arch/arm/boot/dts/gemini-sl93512r.dts
+++ b/arch/arm/boot/dts/gemini-sl93512r.dts
@@ -24,7 +24,7 @@
};
chosen {
- bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait";
+ bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait";
stdout-path = &uart0;
};

54
target/linux/gemini/patches-4.19/0024-ARM-dts-gemini-Fix-up-confused-pin-settings.patch Normal file
View File

@ -0,0 +1,54 @@
From 384ec5ed82845c2c81968743dde4a758f572c11b Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Sat, 13 Jul 2019 11:52:29 +0200
Subject: [PATCH] ARM: dts: gemini: Fix up confused pin settings
The SL93512r board has its pin muxing set up for the wrong
ASIC: SL3516 instead of SL3512 that it is using. Fix it
up and reference the right GPIO for the WPS button.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/gemini-sl93512r.dts | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
--- a/arch/arm/boot/dts/gemini-sl93512r.dts
+++ b/arch/arm/boot/dts/gemini-sl93512r.dts
@@ -36,8 +36,8 @@
wakeup-source;
linux,code = <KEY_WPS_BUTTON>;
label = "WPS";
- /* Conflict with NAND flash */
- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
+ /* Conflicts with TVC and extended flash */
+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
};
button-setup {
@@ -153,17 +153,20 @@
syscon: syscon@40000000 {
pinctrl {
/*
- * gpio0egrp cover line 16 used by HD LED
- * gpio0fgrp cover line 17, 18 used by wireless LED and reset button
- * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY
- * gpio0kgrp cover line 31 used by USB LED
+ * gpio0agrp cover line 0, used by WPS button
+ * gpio0fgrp cover line 16 used by HD LED
+ * gpio0ggrp cover line 17, 18 used by wireless LAN LED and
+ * reset button OR USB ID select on 17 and USB VBUS select
+ * on 18. (Confusing.)
+ * gpio0igrp cover line 21, 22 used by MDIO for Marvell PHY
*/
gpio0_default_pins: pinctrl-gpio0 {
mux {
function = "gpio0";
- groups = "gpio0egrp",
+ groups = "gpio0agrp",
"gpio0fgrp",
- "gpio0hgrp";
+ "gpio0ggrp",
+ "gpio0igrp";
};
};
/*

2
target/linux/mediatek/files-4.19/arch/arm/boot/dts/mt7629-lynx-rfb.dts
View File

@ -18,7 +18,7 @@
chosen {
stdout-path = "serial0:115200n8";
bootargs = "earlycon=uart8250,mmio32,0x11002000";
bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
};
gpio-keys {

1
target/linux/mediatek/mt7622/config-4.19
View File

@ -131,7 +131,6 @@ CONFIG_BT_LE=y
CONFIG_BT_MTKUART=y
CONFIG_BT_QCA=y
CONFIG_BUILD_BIN2C=y
CONFIG_CC_HAS_ASM_GOTO=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLOCK_THERMAL=y

8
target/linux/mediatek/mt7629/config-4.19
View File

@ -52,7 +52,6 @@ CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_CACHE_L2X0=y
CONFIG_CC_HAS_ASM_GOTO=y
# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CHR_DEV_SCH=y
@ -232,8 +231,10 @@ CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MT753X_GSW=y
CONFIG_MTD_MT81xx_NOR=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_MTK=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
@ -330,6 +331,11 @@ CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_MT65XX is not set
CONFIG_SPI_MTK_SNFI=y
CONFIG_SPARSE_IRQ=y
CONFIG_SRCU=y
CONFIG_STACKTRACE=y

199
target/linux/mediatek/patches-4.19/0101-pci-mediatek-backport-fix-pcie.patch
View File

@ -57,83 +57,7 @@
}
static void mtk_pcie_port_free(struct mtk_pcie_port *port)
@@ -394,75 +395,6 @@ static struct pci_ops mtk_pcie_ops_v2 =
.write = mtk_pcie_config_write,
};
-static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
-{
- struct mtk_pcie *pcie = port->pcie;
- struct resource *mem = &pcie->mem;
- const struct mtk_pcie_soc *soc = port->pcie->soc;
- u32 val;
- size_t size;
- int err;
-
- /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
- if (pcie->base) {
- val = readl(pcie->base + PCIE_SYS_CFG_V2);
- val |= PCIE_CSR_LTSSM_EN(port->slot) |
- PCIE_CSR_ASPM_L1_EN(port->slot);
- writel(val, pcie->base + PCIE_SYS_CFG_V2);
- }
-
- /* Assert all reset signals */
- writel(0, port->base + PCIE_RST_CTRL);
-
- /*
- * Enable PCIe link down reset, if link status changed from link up to
- * link down, this will reset MAC control registers and configuration
- * space.
- */
- writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
-
- /* De-assert PHY, PE, PIPE, MAC and configuration reset */
- val = readl(port->base + PCIE_RST_CTRL);
- val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
- PCIE_MAC_SRSTB | PCIE_CRSTB;
- writel(val, port->base + PCIE_RST_CTRL);
-
- /* Set up vendor ID and class code */
- if (soc->need_fix_class_id) {
- val = PCI_VENDOR_ID_MEDIATEK;
- writew(val, port->base + PCIE_CONF_VEND_ID);
-
- val = PCI_CLASS_BRIDGE_HOST;
- writew(val, port->base + PCIE_CONF_CLASS_ID);
- }
-
- /* 100ms timeout value should be enough for Gen1/2 training */
- err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
- !!(val & PCIE_PORT_LINKUP_V2), 20,
- 100 * USEC_PER_MSEC);
- if (err)
- return -ETIMEDOUT;
-
- /* Set INTx mask */
- val = readl(port->base + PCIE_INT_MASK);
- val &= ~INTX_MASK;
- writel(val, port->base + PCIE_INT_MASK);
-
- /* Set AHB to PCIe translation windows */
- size = mem->end - mem->start;
- val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
- writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
-
- val = upper_32_bits(mem->start);
- writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
-
- /* Set PCIe to AXI translation memory space.*/
- val = fls(0xffffffff) | WIN_ENABLE;
- writel(val, port->base + PCIE_AXI_WINDOW0);
-
- return 0;
-}
-
static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
{
struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
@@ -601,6 +533,27 @@ static void mtk_pcie_enable_msi(struct m
@@ -532,6 +533,27 @@ static void mtk_pcie_enable_msi(struct m
writel(val, port->base + PCIE_INT_MASK);
}
@ -161,7 +85,7 @@
static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
irq_hw_number_t hwirq)
{
@@ -630,6 +583,7 @@ static int mtk_pcie_init_irq_domain(stru
@@ -561,6 +583,7 @@ static int mtk_pcie_init_irq_domain(stru
port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
&intx_domain_ops, port);
@ -169,16 +93,7 @@
if (!port->irq_domain) {
dev_err(dev, "failed to get INTx IRQ domain\n");
return -ENODEV;
@@ -639,8 +593,6 @@ static int mtk_pcie_init_irq_domain(stru
ret = mtk_pcie_allocate_msi_domains(port);
if (ret)
return ret;
-
- mtk_pcie_enable_msi(port);
}
return 0;
@@ -693,7 +645,7 @@ static int mtk_pcie_setup_irq(struct mtk
@@ -622,7 +645,7 @@ static int mtk_pcie_setup_irq(struct mtk
struct mtk_pcie *pcie = port->pcie;
struct device *dev = pcie->dev;
struct platform_device *pdev = to_platform_device(dev);
@ -187,7 +102,7 @@
err = mtk_pcie_init_irq_domain(port, node);
if (err) {
@@ -701,8 +653,81 @@ static int mtk_pcie_setup_irq(struct mtk
@@ -630,8 +653,9 @@ static int mtk_pcie_setup_irq(struct mtk
return err;
}
@ -196,82 +111,10 @@
+ port->irq = platform_get_irq(pdev, port->slot);
+ irq_set_chained_handler_and_data(port->irq,
+ mtk_pcie_intr_handler, port);
+
+ return 0;
+}
+
+static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
+{
+ struct mtk_pcie *pcie = port->pcie;
+ struct resource *mem = &pcie->mem;
+ const struct mtk_pcie_soc *soc = port->pcie->soc;
+ u32 val;
+ size_t size;
+ int err;
+
+ /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
+ if (pcie->base) {
+ val = readl(pcie->base + PCIE_SYS_CFG_V2);
+ val |= PCIE_CSR_LTSSM_EN(port->slot) |
+ PCIE_CSR_ASPM_L1_EN(port->slot);
+ writel(val, pcie->base + PCIE_SYS_CFG_V2);
+ }
+
+ /* Assert all reset signals */
+ writel(0, port->base + PCIE_RST_CTRL);
+
+ /*
+ * Enable PCIe link down reset, if link status changed from link up to
+ * link down, this will reset MAC control registers and configuration
+ * space.
+ */
+ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
+
+ /* De-assert PHY, PE, PIPE, MAC and configuration reset */
+ val = readl(port->base + PCIE_RST_CTRL);
+ val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
+ PCIE_MAC_SRSTB | PCIE_CRSTB;
+ writel(val, port->base + PCIE_RST_CTRL);
+
+ /* Set up vendor ID and class code */
+ if (soc->need_fix_class_id) {
+ val = PCI_VENDOR_ID_MEDIATEK;
+ writew(val, port->base + PCIE_CONF_VEND_ID);
+
+ val = PCI_CLASS_BRIDGE_PCI;
+ writew(val, port->base + PCIE_CONF_CLASS_ID);
+ }
+
+ /* 100ms timeout value should be enough for Gen1/2 training */
+ err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
+ !!(val & PCIE_PORT_LINKUP_V2), 20,
+ 100 * USEC_PER_MSEC);
+ if (err)
+ return -ETIMEDOUT;
+
+ /* Set INTx mask */
+ val = readl(port->base + PCIE_INT_MASK);
+ val &= ~INTX_MASK;
+ writel(val, port->base + PCIE_INT_MASK);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ mtk_pcie_enable_msi(port);
+
+ /* Set AHB to PCIe translation windows */
+ size = mem->end - mem->start;
+ val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
+
+ val = upper_32_bits(mem->start);
+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
+
+ /* Set PCIe to AXI translation memory space.*/
+ val = fls(0xffffffff) | WIN_ENABLE;
+ writel(val, port->base + PCIE_AXI_WINDOW0);
return 0;
}
@@ -903,49 +928,29 @@ static int mtk_pcie_parse_port(struct mt
@@ -904,49 +928,29 @@ static int mtk_pcie_parse_port(struct mt
/* sys_ck might be divided into the following parts in some chips */
snprintf(name, sizeof(name), "ahb_ck%d", slot);
@ -336,7 +179,7 @@
snprintf(name, sizeof(name), "pcie-rst%d", slot);
port->reset = devm_reset_control_get_optional_exclusive(dev, name);
@@ -998,10 +1003,8 @@ static int mtk_pcie_subsys_powerup(struc
@@ -999,10 +1003,8 @@ static int mtk_pcie_subsys_powerup(struc
pcie->free_ck = NULL;
}
@ -349,7 +192,7 @@
/* enable top level clock */
err = clk_prepare_enable(pcie->free_ck);
@@ -1013,10 +1016,8 @@ static int mtk_pcie_subsys_powerup(struc
@@ -1014,10 +1016,8 @@ static int mtk_pcie_subsys_powerup(struc
return 0;
err_free_ck:
@ -362,10 +205,16 @@
return err;
}
@@ -1127,34 +1128,6 @@ static int mtk_pcie_request_resources(st
return 0;
}
@@ -1122,36 +1122,6 @@ static int mtk_pcie_request_resources(st
return err;
err = devm_pci_remap_iospace(dev, &pcie->pio, pcie->io.start);
- if (err)
- return err;
-
- return 0;
-}
-
-static int mtk_pcie_register_host(struct pci_host_bridge *host)
-{
- struct mtk_pcie *pcie = pci_host_bridge_priv(host);
@ -390,14 +239,10 @@
- pcie_bus_configure_settings(child);
-
- pci_bus_add_devices(host->bus);
-
- return 0;
-}
-
static int mtk_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1181,7 +1154,14 @@ static int mtk_pcie_probe(struct platfor
return 0;
}
@@ -1182,7 +1152,14 @@ static int mtk_pcie_probe(struct platfor
if (err)
goto put_resources;
@ -413,7 +258,7 @@
if (err)
goto put_resources;
@@ -1194,6 +1174,80 @@ put_resources:
@@ -1195,6 +1172,80 @@ put_resources:
return err;
}
@ -494,7 +339,7 @@
static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
.ops = &mtk_pcie_ops,
.startup = mtk_pcie_startup_port,
@@ -1222,10 +1276,13 @@ static const struct of_device_id mtk_pci
@@ -1223,10 +1274,13 @@ static const struct of_device_id mtk_pci
static struct platform_driver mtk_pcie_driver = {
.probe = mtk_pcie_probe,

176
target/linux/mediatek/patches-4.19/0307-spi-mem-Mediatek-Add-SPI-Nand-support-for-MT7629.patch Normal file
View File

@ -0,0 +1,176 @@
From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001
From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
Date: Thu, 6 Jun 2019 16:29:04 +0800
Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629
Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
---
arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/mt7629-lynx-rfb.dts | 45 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/mt7629.dtsi | 22 ++++++++++++++++
drivers/spi/spi-mtk-snfi.c | 12 +++++++++
3 files changed, 79 insertions(+)
--- a/arch/arm/boot/dts/mt7629-rfb.dts
+++ b/arch/arm/boot/dts/mt7629-rfb.dts
@@ -258,6 +258,51 @@
};
};
+&bch {
+ status = "okay";
+};
+
+&snfi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial_nand_pins>;
+ status = "okay";
+
+ spi_nand@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "Bootloader";
+ reg = <0x00000 0x0100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "Config";
+ reg = <0x100000 0x0040000>;
+ };
+
+ partition@140000 {
+ label = "factory";
+ reg = <0x140000 0x0080000>;
+ };
+
+ partition@1c0000 {
+ label = "firmware";
+ reg = <0x1c0000 0x1000000>;
+ };
+ };
+ };
+};
+
&spi {
pinctrl-names = "default";
pinctrl-0 = <&spi_pins>;
--- a/arch/arm/boot/dts/mt7629.dtsi
+++ b/arch/arm/boot/dts/mt7629.dtsi
@@ -259,6 +259,28 @@
status = "disabled";
};
+ bch: ecc@1100e000 {
+ compatible = "mediatek,mt7622-ecc";
+ reg = <0x1100e000 0x1000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFIECC_PD>;
+ clock-names = "nfiecc_clk";
+ status = "disabled";
+ };
+
+ snfi: spi@1100d000 {
+ compatible = "mediatek,mt7629-snfi";
+ reg = <0x1100d000 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "spi_clk";
+ ecc-engine = <&bch>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
spi: spi@1100a000 {
compatible = "mediatek,mt7629-spi",
"mediatek,mt7622-spi";
--- a/drivers/spi/spi-mtk-snfi.c
+++ b/drivers/spi/spi-mtk-snfi.c
@@ -1029,8 +1029,20 @@ static const struct mtk_snfi_caps snfi_m
.bad_mark_swap = 0,
};
+static const struct mtk_snfi_caps snfi_mt7629 = {
+ .spare_size = spare_size_mt7622,
+ .num_spare_size = 4,
+ .nand_sec_size = 512,
+ .nand_fdm_size = 8,
+ .nand_fdm_ecc_size = 1,
+ .ecc_parity_bits = 13,
+ .pageformat_spare_shift = 4,
+ .bad_mark_swap = 1,
+};
+
static const struct of_device_id mtk_snfi_id_table[] = {
{ .compatible = "mediatek,mt7622-snfi", .data = &snfi_mt7622, },
+ { .compatible = "mediatek,mt7629-snfi", .data = &snfi_mt7629, },
{ /* sentinel */ }
};
--- a/arch/arm/boot/dts/mt7629-lynx-rfb.dts
+++ b/arch/arm/boot/dts/mt7629-lynx-rfb.dts
@@ -281,6 +281,52 @@
};
};
+&bch {
+ status = "okay";
+};
+
+&snfi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial_nand_pins>;
+ status = "okay";
+
+ spi_nand@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "Bootloader";
+ reg = <0x00000 0x0100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "Config";
+ reg = <0x100000 0x0040000>;
+ };
+
+ partition@140000 {
+ label = "factory";
+ reg = <0x140000 0x0080000>;
+ };
+
+ partition@1c0000 {
+ label = "firmware";
+ reg = <0x1c0000 0x1000000>;
+ };
+
+ };
+ };
+};
+
&spi {
pinctrl-names = "default";
pinctrl-0 = <&spi_pins>;

5
target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts → target/linux/ramips/dts/XiaoYu-C5.dts
View File

@ -17,6 +17,11 @@
label-mac-device = &ethernet;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x1c000000>, <0x20000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,57600";
};

7
target/linux/ramips/image/mt7621.mk
View File

@ -131,10 +131,9 @@ endef
TARGET_DEVICES += mediatek_ap-mt7621a-v60
define Device/xiaoyu_xy-c5
MTK_SOC := mt7621
IMAGE_SIZE := 32448k
DEVICE_VENDOR := XiaoYu
DEVICE_MODEL := XY-C5
DTS := XiaoYu-C5
IMAGE_SIZE := $(ralink_default_fw_size_32M)
DEVICE_TITLE := XiaoYu_XY-C5
DEVICE_PACKAGES := kmod-ata-core kmod-ata-ahci kmod-usb3
endef
TARGET_DEVICES += xiaoyu_xy-c5