rockchip: refresh upstreamed patches

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>

target/linux/rockchip/patches-6.6/032-01-v6.10-phy-rockchip-add-usbdp-combo-phy-driver.patch

@@ -1,20 +1,7 @@
+From 2f70bbddeb457580cef3ceb574506083b9272188 Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <sebastian.reichel@collabora.com>
-To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
+Date: Tue, 9 Apr 2024 00:50:29 +0200
-	Kishon Vijay Abraham I <kishon@kernel.org>,
+Subject: [PATCH] phy: rockchip: add usbdp combo phy driver
-	linux-rockchip@lists.infradead.org,
-	linux-phy@lists.infradead.org
-Cc: Rob Herring <robh+dt@kernel.org>,
-	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
-	Conor Dooley <conor+dt@kernel.org>,
-	Frank Wang <frank.wang@rock-chips.com>,
-	Kever Yang <kever.yang@rock-chips.com>,
-	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
-	Sebastian Reichel <sebastian.reichel@collabora.com>,
-	kernel@collabora.com, Zhang Yubing <yubing.zhang@rock-chips.com>
-Subject: [PATCH v2 04/12] phy: rockchip: add usbdp combo phy driver
-Date: Tue, 13 Feb 2024 17:32:38 +0100	[thread overview]
-Message-ID: <20240213163609.44930-5-sebastian.reichel@collabora.com> (raw)
-In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
 
 This adds a new USBDP combo PHY with Samsung IP block driver.
 
@@ -36,11 +23,13 @@ Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
 Co-developed-by: Frank Wang <frank.wang@rock-chips.com>
 Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20240408225109.128953-3-sebastian.reichel@collabora.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
 ---
  drivers/phy/rockchip/Kconfig              |   12 +
  drivers/phy/rockchip/Makefile             |    1 +
- drivers/phy/rockchip/phy-rockchip-usbdp.c | 1639 +++++++++++++++++++++
+ drivers/phy/rockchip/phy-rockchip-usbdp.c | 1608 +++++++++++++++++++++
- 3 files changed, 1652 insertions(+)
+ 3 files changed, 1621 insertions(+)
  create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c
 
 --- a/drivers/phy/rockchip/Kconfig
@@ -70,27 +59,25 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +obj-$(CONFIG_PHY_ROCKCHIP_USBDP)	+= phy-rockchip-usbdp.o
 --- /dev/null
 +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
-@@ -0,0 +1,1639 @@
+@@ -0,0 +1,1608 @@
 +// SPDX-License-Identifier: GPL-2.0-or-later
 +/*
 + * Rockchip USBDP Combo PHY with Samsung IP block driver
 + *
-+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd
++ * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd
++ * Copyright (C) 2024 Collabora Ltd
 + */
 +
++#include <dt-bindings/phy/phy.h>
 +#include <linux/bitfield.h>
 +#include <linux/bits.h>
 +#include <linux/clk.h>
-+#include <linux/clk-provider.h>
 +#include <linux/delay.h>
 +#include <linux/gpio.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
 +#include <linux/mfd/syscon.h>
++#include <linux/mod_devicetable.h>
 +#include <linux/module.h>
 +#include <linux/mutex.h>
-+#include <linux/of.h>
 +#include <linux/phy/phy.h>
 +#include <linux/platform_device.h>
 +#include <linux/property.h>
@@ -172,12 +159,20 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +
 +struct rk_udphy_grf_reg {
 +	unsigned int	offset;
-+	unsigned int	bitend;
-+	unsigned int	bitstart;
 +	unsigned int	disable;
 +	unsigned int	enable;
 +};
 +
++#define _RK_UDPHY_GEN_GRF_REG(offset, mask, disable, enable) \
++{\
++	offset, \
++	FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \
++	FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \
++}
++
++#define RK_UDPHY_GEN_GRF_REG(offset, bitend, bitstart, disable, enable) \
++	_RK_UDPHY_GEN_GRF_REG(offset, GENMASK(bitend, bitstart), disable, enable)
++
 +struct rk_udphy_grf_cfg {
 +	/* u2phy-grf */
 +	struct rk_udphy_grf_reg	bvalid_phy_con;
@@ -261,6 +256,10 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +
 +	/* PHY const config */
 +	const struct rk_udphy_cfg *cfgs;
++
++	/* PHY devices */
++	struct phy *phy_dp;
++	struct phy *phy_u3;
 +};
 +
 +static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = {
@@ -480,13 +479,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +static inline int rk_udphy_grfreg_write(struct regmap *base,
 +					const struct rk_udphy_grf_reg *reg, bool en)
 +{
-+	u32 val, mask, tmp;
++	return regmap_write(base, reg->offset, en ? reg->enable : reg->disable);
-+
-+	tmp = en ? reg->enable : reg->disable;
-+	mask = GENMASK(reg->bitend, reg->bitstart);
-+	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
-+
-+	return regmap_write(base, reg->offset, val);
 +}
 +
 +static int rk_udphy_clk_init(struct rk_udphy *udphy, struct device *dev)
@@ -605,7 +598,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 + * ---------------------------------------------------------------------------
 + */
 +
-+static int rk_udphy_dplane_select(struct rk_udphy *udphy)
++static void rk_udphy_dplane_select(struct rk_udphy *udphy)
 +{
 +	const struct rk_udphy_cfg *cfg = udphy->cfgs;
 +	u32 value = 0;
@@ -615,12 +608,15 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +		value |= 2 << udphy->dp_lane_sel[2] * 2;
 +		value |= 3 << udphy->dp_lane_sel[3] * 2;
 +		fallthrough;
++
 +	case UDPHY_MODE_DP_USB:
 +		value |= 0 << udphy->dp_lane_sel[0] * 2;
 +		value |= 1 << udphy->dp_lane_sel[1] * 2;
 +		break;
++
 +	case UDPHY_MODE_USB:
 +		break;
++
 +	default:
 +		break;
 +	}
@@ -629,8 +625,6 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +		     ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) |
 +		     FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |
 +		     FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
-+
-+	return 0;
 +}
 +
 +static int rk_udphy_dplane_get(struct rk_udphy *udphy)
@@ -641,11 +635,12 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	case UDPHY_MODE_DP:
 +		dp_lanes = 4;
 +		break;
++
 +	case UDPHY_MODE_DP_USB:
 +		dp_lanes = 2;
 +		break;
++
 +	case UDPHY_MODE_USB:
-+		fallthrough;
 +	default:
 +		dp_lanes = 0;
 +		break;
@@ -654,7 +649,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	return dp_lanes;
 +}
 +
-+static int rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes)
++static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes)
 +{
 +	u32 val = 0;
 +	int i;
@@ -668,11 +663,9 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	if (!dp_lanes)
 +		regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
 +				   CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
-+
-+	return 0;
 +}
 +
-+static int rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd)
++static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd)
 +{
 +	const struct rk_udphy_cfg *cfg = udphy->cfgs;
 +
@@ -680,14 +673,12 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	udphy->dp_sink_hpd_cfg = hpd;
 +
 +	if (!udphy->dp_in_use)
-+		return 0;
++		return;
 +
 +	rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd);
-+
-+	return 0;
 +}
 +
-+static int rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy)
++static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy)
 +{
 +	if (udphy->flip) {
 +		udphy->dp_lane_sel[0] = 0;
@@ -718,8 +709,6 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	}
 +
 +	udphy->mode = UDPHY_MODE_DP_USB;
-+
-+	return 0;
 +}
 +
 +static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
@@ -788,6 +777,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +		if (ret)
 +			return ret;
 +		break;
++
 +	case 26000000:
 +		/* register default is 26MHz */
 +		ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_26m_refclk_cfg,
@@ -795,6 +785,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +		if (ret)
 +			return ret;
 +		break;
++
 +	default:
 +		dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate);
 +		return -EINVAL;
@@ -921,7 +912,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +
 +static int rk_udphy_setup(struct rk_udphy *udphy)
 +{
-+	int ret = 0;
++	int ret;
 +
 +	ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
 +	if (ret) {
@@ -939,12 +930,10 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	return 0;
 +}
 +
-+static int rk_udphy_disable(struct rk_udphy *udphy)
++static void rk_udphy_disable(struct rk_udphy *udphy)
 +{
 +	clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
 +	rk_udphy_reset_assert_all(udphy);
-+
-+	return 0;
 +}
 +
 +static int rk_udphy_parse_lane_mux_data(struct rk_udphy *udphy)
@@ -1058,11 +1047,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	if (ret)
 +		return ret;
 +
-+	ret = rk_udphy_reset_init(udphy, dev);
++	return rk_udphy_reset_init(udphy, dev);
-+	if (ret)
-+		return ret;
-+
-+	return 0;
 +}
 +
 +static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode)
@@ -1088,9 +1073,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +		if (udphy->mode == UDPHY_MODE_DP)
 +			rk_udphy_u3_port_disable(udphy, true);
 +
-+		ret = rk_udphy_disable(udphy);
++		rk_udphy_disable(udphy);
-+		if (ret)
-+			return ret;
 +		ret = rk_udphy_setup(udphy);
 +		if (ret)
 +			return ret;
@@ -1101,27 +1084,20 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	return 0;
 +}
 +
-+static int rk_udphy_power_off(struct rk_udphy *udphy, u8 mode)
++static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode)
 +{
-+	int ret;
-+
 +	if (!(udphy->mode & mode)) {
 +		dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
-+		return 0;
++		return;
 +	}
 +
 +	if (!udphy->status)
-+		return 0;
++		return;
 +
 +	udphy->status &= ~mode;
 +
-+	if (udphy->status == UDPHY_MODE_NONE) {
++	if (udphy->status == UDPHY_MODE_NONE)
-+		ret = rk_udphy_disable(udphy);
++		rk_udphy_disable(udphy);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return 0;
 +}
 +
 +static int rk_udphy_dp_phy_init(struct phy *phy)
@@ -1162,11 +1138,9 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	if (ret)
 +		goto unlock;
 +
-+	ret = rk_udphy_dplane_enable(udphy, dp_lanes);
++	rk_udphy_dplane_enable(udphy, dp_lanes);
-+	if (ret)
-+		goto unlock;
 +
-+	ret = rk_udphy_dplane_select(udphy);
++	rk_udphy_dplane_select(udphy);
 +
 +unlock:
 +	mutex_unlock(&udphy->mutex);
@@ -1182,18 +1156,13 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +static int rk_udphy_dp_phy_power_off(struct phy *phy)
 +{
 +	struct rk_udphy *udphy = phy_get_drvdata(phy);
-+	int ret;
 +
 +	mutex_lock(&udphy->mutex);
-+	ret = rk_udphy_dplane_enable(udphy, 0);
++	rk_udphy_dplane_enable(udphy, 0);
-+	if (ret)
++	rk_udphy_power_off(udphy, UDPHY_MODE_DP);
-+		goto unlock;
-+
-+	ret = rk_udphy_power_off(udphy, UDPHY_MODE_DP);
-+
-+unlock:
 +	mutex_unlock(&udphy->mutex);
-+	return ret;
++
++	return 0;
 +}
 +
 +static int rk_udphy_dp_phy_verify_link_rate(unsigned int link_rate)
@@ -1204,6 +1173,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	case 5400:
 +	case 8100:
 +		break;
++
 +	default:
 +		return -EINVAL;
 +	}
@@ -1228,6 +1198,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	case 4:
 +		/* valid lane count. */
 +		break;
++
 +	default:
 +		return -EINVAL;
 +	}
@@ -1300,15 +1271,19 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +		case 1620:
 +			udphy->bw = DP_BW_RBR;
 +			break;
++
 +		case 2700:
 +			udphy->bw = DP_BW_HBR;
 +			break;
++
 +		case 5400:
 +			udphy->bw = DP_BW_HBR2;
 +			break;
++
 +		case 8100:
 +			udphy->bw = DP_BW_HBR3;
 +			break;
++
 +		default:
 +			return -EINVAL;
 +		}
@@ -1342,6 +1317,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +						   FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV,
 +						   udphy->lane_mux_sel[lane]));
 +				break;
++
 +			case 5400:
 +			case 8100:
 +				regmap_update_bits(udphy->pma_regmap,
@@ -1371,7 +1347,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +static int rk_udphy_usb3_phy_init(struct phy *phy)
 +{
 +	struct rk_udphy *udphy = phy_get_drvdata(phy);
-+	int ret = 0;
++	int ret;
 +
 +	mutex_lock(&udphy->mutex);
 +	/* DP only or high-speed, disable U3 port */
@@ -1390,18 +1366,17 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +static int rk_udphy_usb3_phy_exit(struct phy *phy)
 +{
 +	struct rk_udphy *udphy = phy_get_drvdata(phy);
-+	int ret = 0;
 +
 +	mutex_lock(&udphy->mutex);
 +	/* DP only or high-speed */
 +	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
 +		goto unlock;
 +
-+	ret = rk_udphy_power_off(udphy, UDPHY_MODE_USB);
++	rk_udphy_power_off(udphy, UDPHY_MODE_USB);
 +
 +unlock:
 +	mutex_unlock(&udphy->mutex);
-+	return ret;
++	return 0;
 +}
 +
 +static const struct phy_ops rk_udphy_usb3_phy_ops = {
@@ -1420,7 +1395,6 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +
 +	switch (state->mode) {
 +	case TYPEC_DP_STATE_C:
-+		fallthrough;
 +	case TYPEC_DP_STATE_E:
 +		udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
 +		udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
@@ -1428,8 +1402,8 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +		udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
 +		mode = UDPHY_MODE_DP;
 +		break;
++
 +	case TYPEC_DP_STATE_D:
-+		fallthrough;
 +	default:
 +		if (udphy->flip) {
 +			udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
@@ -1496,25 +1470,6 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +					udphy);
 +}
 +
-+static u32 rk_udphy_dp_get_max_link_rate(struct rk_udphy *udphy,
-+					 struct fwnode_handle *np)
-+{
-+	u32 max_link_rate;
-+	int ret;
-+
-+	ret = fwnode_property_read_u32(np, "max-link-rate", &max_link_rate);
-+	if (ret)
-+		return 8100;
-+
-+	ret = rk_udphy_dp_phy_verify_link_rate(max_link_rate);
-+	if (ret) {
-+		dev_warn(udphy->dev, "invalid max-link-rate: %d\n", max_link_rate);
-+		max_link_rate = 8100;
-+	}
-+
-+	return max_link_rate;
-+}
-+
 +static const struct regmap_config rk_udphy_pma_regmap_cfg = {
 +	.reg_bits = 32,
 +	.reg_stride = 4,
@@ -1523,10 +1478,26 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	.max_register = 0x20dc,
 +};
 +
++static struct phy *rk_udphy_phy_xlate(struct device *dev, const struct of_phandle_args *args)
++{
++	struct rk_udphy *udphy = dev_get_drvdata(dev);
++
++	if (args->args_count == 0)
++		return ERR_PTR(-EINVAL);
++
++	switch (args->args[0]) {
++	case PHY_TYPE_USB3:
++		return udphy->phy_u3;
++	case PHY_TYPE_DP:
++		return udphy->phy_dp;
++	}
++
++	return ERR_PTR(-EINVAL);
++}
++
 +static int rk_udphy_probe(struct platform_device *pdev)
 +{
 +	struct device *dev = &pdev->dev;
-+	struct fwnode_handle *child;
 +	struct phy_provider *phy_provider;
 +	struct resource *res;
 +	struct rk_udphy *udphy;
@@ -1586,36 +1557,23 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +			return ret;
 +	}
 +
-+	fwnode_for_each_available_child_node(dev_fwnode(dev), child) {
++	udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops);
-+		const char *name = fwnode_get_name(child);
++	if (IS_ERR(udphy->phy_u3)) {
-+		const struct phy_ops *ops;
++		ret = PTR_ERR(udphy->phy_u3);
-+		struct phy *phy;
++		return dev_err_probe(dev, ret, "failed to create USB3 phy\n");
-+
-+		if (!strcmp(name, "dp-port")) {
-+			ops = &rk_udphy_dp_phy_ops;
-+		} else if (!strcmp(name, "usb3-port")) {
-+			ops = &rk_udphy_usb3_phy_ops;
-+		} else {
-+			/* e.g. ports node used by orientation switch */
-+			continue;
 +	}
++	phy_set_drvdata(udphy->phy_u3, udphy);
 +
-+		phy = devm_phy_create(dev, to_of_node(child), ops);
++	udphy->phy_dp = devm_phy_create(dev, dev->of_node, &rk_udphy_dp_phy_ops);
-+		if (IS_ERR(phy)) {
++	if (IS_ERR(udphy->phy_dp)) {
-+			fwnode_handle_put(child);
++		ret = PTR_ERR(udphy->phy_dp);
-+			ret = PTR_ERR(phy);
++		return dev_err_probe(dev, ret, "failed to create DP phy\n");
-+			return dev_err_probe(dev, ret, "failed to create phy: %pfwP\n", child);
 +	}
++	phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy));
++	udphy->phy_dp->attrs.max_link_rate = 8100;
++	phy_set_drvdata(udphy->phy_dp, udphy);
 +
-+		if (ops == &rk_udphy_dp_phy_ops) {
++	phy_provider = devm_of_phy_provider_register(dev, rk_udphy_phy_xlate);
-+			phy_set_bus_width(phy, rk_udphy_dplane_get(udphy));
-+			phy->attrs.max_link_rate = rk_udphy_dp_get_max_link_rate(udphy, child);
-+		}
-+
-+		phy_set_drvdata(phy, udphy);
-+	}
-+
-+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 +	if (IS_ERR(phy_provider)) {
 +		ret = PTR_ERR(phy_provider);
 +		return dev_err_probe(dev, ret, "failed to register phy provider\n");
@@ -1652,24 +1610,24 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	.rst_list = rk_udphy_rst_list,
 +	.grfcfg	= {
 +		/* u2phy-grf */
-+		.bvalid_phy_con		= { 0x0008, 1, 0, 0x2, 0x3 },
++		.bvalid_phy_con		= RK_UDPHY_GEN_GRF_REG(0x0008, 1, 0, 0x2, 0x3),
-+		.bvalid_grf_con		= { 0x0010, 3, 2, 0x2, 0x3 },
++		.bvalid_grf_con		= RK_UDPHY_GEN_GRF_REG(0x0010, 3, 2, 0x2, 0x3),
 +
 +		/* usb-grf */
-+		.usb3otg0_cfg		= { 0x001c, 15, 0, 0x1100, 0x0188 },
++		.usb3otg0_cfg		= RK_UDPHY_GEN_GRF_REG(0x001c, 15, 0, 0x1100, 0x0188),
-+		.usb3otg1_cfg		= { 0x0034, 15, 0, 0x1100, 0x0188 },
++		.usb3otg1_cfg		= RK_UDPHY_GEN_GRF_REG(0x0034, 15, 0, 0x1100, 0x0188),
 +
 +		/* usbdpphy-grf */
-+		.low_pwrn		= { 0x0004, 13, 13, 0, 1 },
++		.low_pwrn		= RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1),
-+		.rx_lfps		= { 0x0004, 14, 14, 0, 1 },
++		.rx_lfps		= RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1),
 +	},
 +	.vogrfcfg = {
 +		{
-+			.hpd_trigger	= { 0x0000, 11, 10, 1, 3 },
++			.hpd_trigger	= RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
 +			.dp_lane_reg	= 0x0000,
 +		},
 +		{
-+			.hpd_trigger	= { 0x0008, 11, 10, 1, 3 },
++			.hpd_trigger	= RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3),
 +			.dp_lane_reg	= 0x0008,
 +		},
 +	},

target/linux/rockchip/patches-6.6/032-02-v6.10-phy-rockchip-usbdp-fix-uninitialized-variable.patch

@@ -0,0 +1,35 @@
+From c9342d1a351ee1249fa98d936f756299a83d5684 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 16 Apr 2024 16:51:23 +0200
+Subject: [PATCH] phy: rockchip: usbdp: fix uninitialized variable
+
+The ret variable may not be initialized in rk_udphy_usb3_phy_init(), if
+the PHY is not using USB3 mode.
+
+Since the DisplayPort part is handled separately and the PHY does not
+support USB2 (which is routed to another PHY on Rockchip RK3588), the
+right exit code for this case is 0. Thus let's initialize the variable
+accordingly.
+
+Fixes: 2f70bbddeb457 ("phy: rockchip: add usbdp combo phy driver")
+Reported-by: kernel test robot <lkp@intel.com>
+Closes: https://lore.kernel.org/oe-kbuild-all/202404141048.qFAYDctQ-lkp@intel.com/
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Reviewed-by: Muhammad Usama Anjum <usama.anjum@collabora.com>
+Link: https://lore.kernel.org/r/20240416145233.94687-1-sebastian.reichel@collabora.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-usbdp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
++++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
+@@ -1285,7 +1285,7 @@ static const struct phy_ops rk_udphy_dp_
+ static int rk_udphy_usb3_phy_init(struct phy *phy)
+ {
+ 	struct rk_udphy *udphy = phy_get_drvdata(phy);
+-	int ret;
++	int ret = 0;
+ 
+ 	mutex_lock(&udphy->mutex);
+ 	/* DP only or high-speed, disable U3 port */

target/linux/rockchip/patches-6.6/032-03-v6.10-phy-rockchip-fix-CONFIG_TYPEC-dependency.patch

@@ -0,0 +1,43 @@
+From 9c79b779643e56d4253bd3ba6998c58c819943af Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Mon, 15 Apr 2024 19:42:25 +0200
+Subject: [PATCH] phy: rockchip: fix CONFIG_TYPEC dependency
+
+The newly added driver causes a warning about missing dependencies
+by selecting CONFIG_TYPEC unconditionally:
+
+WARNING: unmet direct dependencies detected for TYPEC
+  Depends on [n]: USB_SUPPORT [=n]
+  Selected by [y]:
+  - PHY_ROCKCHIP_USBDP [=y] && ARCH_ROCKCHIP [=y] && OF [=y]
+
+WARNING: unmet direct dependencies detected for USB_COMMON
+  Depends on [n]: USB_SUPPORT [=n]
+  Selected by [y]:
+  - EXTCON_RTK_TYPE_C [=y] && EXTCON [=y] && (ARCH_REALTEK [=y] || COMPILE_TEST [=y]) && TYPEC [=y]
+
+Since that is a user-visible option, it should not really be selected
+in the first place. Replace the 'select' with a 'depends on' as
+we have for similar drivers.
+
+Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20240415174241.77982-1-arnd@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/phy/rockchip/Kconfig
++++ b/drivers/phy/rockchip/Kconfig
+@@ -111,8 +111,8 @@ config PHY_ROCKCHIP_USB
+ config PHY_ROCKCHIP_USBDP
+ 	tristate "Rockchip USBDP COMBO PHY Driver"
+ 	depends on ARCH_ROCKCHIP && OF
++	depends on TYPEC
+ 	select GENERIC_PHY
+-	select TYPEC
+ 	help
+ 	  Enable this to support the Rockchip USB3.0/DP combo PHY with
+ 	  Samsung IP block. This is required for USB3 support on RK3588.

target/linux/rockchip/patches-6.6/032-04-v6.10-phy-rockchip-Fix-typo-in-function-names.patch

@@ -0,0 +1,79 @@
+From 9b6bfad9070a95d19973be17177e5d9220cbbf1f Mon Sep 17 00:00:00 2001
+From: Rick Wertenbroek <rick.wertenbroek@gmail.com>
+Date: Thu, 7 Mar 2024 10:53:18 +0100
+Subject: [PATCH] phy: rockchip: Fix typo in function names
+
+Several functions had "rochchip" instead of "rockchip" in their name.
+Replace "rochchip" by "rockchip".
+
+Signed-off-By: Rick Wertenbroek <rick.wertenbroek@gmail.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20240307095318.3651498-1-rick.wertenbroek@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c |  4 ++--
+ drivers/phy/rockchip/phy-rockchip-snps-pcie3.c     | 12 ++++++------
+ 2 files changed, 8 insertions(+), 8 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+@@ -245,7 +245,7 @@ static int rockchip_combphy_exit(struct
+ 	return 0;
+ }
+ 
+-static const struct phy_ops rochchip_combphy_ops = {
++static const struct phy_ops rockchip_combphy_ops = {
+ 	.init = rockchip_combphy_init,
+ 	.exit = rockchip_combphy_exit,
+ 	.owner = THIS_MODULE,
+@@ -352,7 +352,7 @@ static int rockchip_combphy_probe(struct
+ 		return ret;
+ 	}
+ 
+-	priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
++	priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops);
+ 	if (IS_ERR(priv->phy)) {
+ 		dev_err(dev, "failed to create combphy\n");
+ 		return PTR_ERR(priv->phy);
+--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
++++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+@@ -187,7 +187,7 @@ static const struct rockchip_p3phy_ops r
+ 	.phy_init = rockchip_p3phy_rk3588_init,
+ };
+ 
+-static int rochchip_p3phy_init(struct phy *phy)
++static int rockchip_p3phy_init(struct phy *phy)
+ {
+ 	struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
+ 	int ret;
+@@ -210,7 +210,7 @@ static int rochchip_p3phy_init(struct ph
+ 	return ret;
+ }
+ 
+-static int rochchip_p3phy_exit(struct phy *phy)
++static int rockchip_p3phy_exit(struct phy *phy)
+ {
+ 	struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
+ 
+@@ -219,9 +219,9 @@ static int rochchip_p3phy_exit(struct ph
+ 	return 0;
+ }
+ 
+-static const struct phy_ops rochchip_p3phy_ops = {
+-	.init = rochchip_p3phy_init,
+-	.exit = rochchip_p3phy_exit,
++static const struct phy_ops rockchip_p3phy_ops = {
++	.init = rockchip_p3phy_init,
++	.exit = rockchip_p3phy_exit,
+ 	.set_mode = rockchip_p3phy_set_mode,
+ 	.owner = THIS_MODULE,
+ };
+@@ -280,7 +280,7 @@ static int rockchip_p3phy_probe(struct p
+ 		return priv->num_lanes;
+ 	}
+ 
+-	priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
++	priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
+ 	if (IS_ERR(priv->phy)) {
+ 		dev_err(dev, "failed to create combphy\n");
+ 		return PTR_ERR(priv->phy);

target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-snps-pcie3-fix-bifurcation-on-rk3588.patch

@@ -0,0 +1,95 @@
+From f8020dfb311d2b6cf657668792aaa5fa8863a7dd Mon Sep 17 00:00:00 2001
+From: Michal Tomek <mtdev79b@gmail.com>
+Date: Thu, 4 Apr 2024 19:11:26 +0200
+Subject: [PATCH] phy: rockchip-snps-pcie3: fix bifurcation on rk3588
+
+So far all RK3588 boards use fully aggregated PCIe. CM3588 is one
+of the few boards using this feature and apparently it is broken.
+
+The PHY offers the following mapping options:
+
+  port 0 lane 0 - always mapped to controller 0 (4L)
+  port 0 lane 1 - to controller 0 or 2 (1L0)
+  port 1 lane 0 - to controller 0 or 1 (2L)
+  port 1 lane 1 - to controller 0, 1 or 3 (1L1)
+
+The data-lanes DT property maps these as follows:
+
+  0 = no controller (unsupported by the HW)
+  1 = 4L
+  2 = 2L
+  3 = 1L0
+  4 = 1L1
+
+That allows the following configurations with first column being the
+mainline data-lane mapping, second column being the downstream name,
+third column being PCIE3PHY_GRF_CMN_CON0 and PHP_GRF_PCIESEL register
+values and final column being the user visible lane setup:
+
+  <1 1 1 1> = AGGREG = [4 0] = x4 (aggregation)
+  <1 1 2 2> = NANBNB = [0 0] = x2 x2 (no bif.)
+  <1 3 2 2> = NANBBI = [1 1] = x2 x1x1 (bif. of port 0)
+  <1 1 2 4> = NABINB = [2 2] = x1x1 x2 (bif. of port 1)
+  <1 3 2 4> = NABIBI = [3 3] = x1x1 x1x1 (bif. of both ports)
+
+The driver currently does not program PHP_GRF_PCIESEL correctly, which
+is fixed by this patch. As a side-effect the new logic is much simpler
+than the old logic.
+
+Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3")
+Signed-off-by: Michal Tomek <mtdev79b@gmail.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Acked-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-1-9907136eeafd@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ .../phy/rockchip/phy-rockchip-snps-pcie3.c    | 24 +++++++------------
+ 1 file changed, 8 insertions(+), 16 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
++++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+@@ -132,7 +132,7 @@ static const struct rockchip_p3phy_ops r
+ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
+ {
+ 	u32 reg = 0;
+-	u8 mode = 0;
++	u8 mode = RK3588_LANE_AGGREGATION; /* default */
+ 	int ret;
+ 
+ 	/* Deassert PCIe PMA output clamp mode */
+@@ -140,28 +140,20 @@ static int rockchip_p3phy_rk3588_init(st
+ 
+ 	/* Set bifurcation if needed */
+ 	for (int i = 0; i < priv->num_lanes; i++) {
+-		if (!priv->lanes[i])
+-			mode |= (BIT(i) << 3);
+-
+ 		if (priv->lanes[i] > 1)
+-			mode |= (BIT(i) >> 1);
+-	}
+-
+-	if (!mode)
+-		reg = RK3588_LANE_AGGREGATION;
+-	else {
+-		if (mode & (BIT(0) | BIT(1)))
+-			reg |= RK3588_BIFURCATION_LANE_0_1;
+-
+-		if (mode & (BIT(2) | BIT(3)))
+-			reg |= RK3588_BIFURCATION_LANE_2_3;
++			mode &= ~RK3588_LANE_AGGREGATION;
++		if (priv->lanes[i] == 3)
++			mode |= RK3588_BIFURCATION_LANE_0_1;
++		if (priv->lanes[i] == 4)
++			mode |= RK3588_BIFURCATION_LANE_2_3;
+ 	}
+ 
++	reg = mode;
+ 	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
+ 
+ 	/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
+ 	if (!IS_ERR(priv->pipe_grf)) {
+-		reg = (mode & (BIT(6) | BIT(7))) >> 6;
++		reg = mode & 3;
+ 		if (reg)
+ 			regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
+ 				     (reg << 16) | reg);

target/linux/rockchip/patches-6.6/032-06-v6.10-phy-rockchip-snps-pcie3-fix-clearing-PHP_GRF_PCIESEL_CON.patch

@@ -0,0 +1,52 @@
+From 55491a5fa163bf15158f34f3650b3985f25622b9 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 4 Apr 2024 19:11:27 +0200
+Subject: [PATCH] phy: rockchip-snps-pcie3: fix clearing PHP_GRF_PCIESEL_CON
+ bits
+
+Currently the PCIe v3 PHY driver only sets the pcie1ln_sel bits, but
+does not clear them because of an incorrect write mask. This fixes up
+the issue by using a newly introduced constant for the write mask.
+
+While at it also introduces a proper GENMASK based constant for the
+PCIE30_PHY_MODE.
+
+Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3")
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-2-9907136eeafd@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
++++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+@@ -40,6 +40,8 @@
+ #define RK3588_BIFURCATION_LANE_0_1		BIT(0)
+ #define RK3588_BIFURCATION_LANE_2_3		BIT(1)
+ #define RK3588_LANE_AGGREGATION		BIT(2)
++#define RK3588_PCIE1LN_SEL_EN			(GENMASK(1, 0) << 16)
++#define RK3588_PCIE30_PHY_MODE_EN		(GENMASK(2, 0) << 16)
+ 
+ struct rockchip_p3phy_ops;
+ 
+@@ -149,14 +151,15 @@ static int rockchip_p3phy_rk3588_init(st
+ 	}
+ 
+ 	reg = mode;
+-	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
++	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
++		     RK3588_PCIE30_PHY_MODE_EN | reg);
+ 
+ 	/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
+ 	if (!IS_ERR(priv->pipe_grf)) {
+-		reg = mode & 3;
++		reg = mode & (RK3588_BIFURCATION_LANE_0_1 | RK3588_BIFURCATION_LANE_2_3);
+ 		if (reg)
+ 			regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
+-				     (reg << 16) | reg);
++				     RK3588_PCIE1LN_SEL_EN | reg);
+ 	}
+ 
+ 	reset_control_deassert(priv->p30phy);

target/linux/rockchip/patches-6.6/032-07-v6.10-phy-rockchip-snps-pcie3-add-support-for.patch

@@ -0,0 +1,106 @@
+From a1fe1eca0d8be69ccc1f3d615e5a529df1c82e66 Mon Sep 17 00:00:00 2001
+From: Niklas Cassel <cassel@kernel.org>
+Date: Fri, 12 Apr 2024 14:58:16 +0200
+Subject: [PATCH] phy: rockchip-snps-pcie3: add support for
+ rockchip,rx-common-refclk-mode
+
+>From the RK3588 Technical Reference Manual, Part1,
+section 6.19 PCIe3PHY_GRF Register Description:
+"rxX_cmn_refclk_mode"
+RX common reference clock mode for lane X. This mode should be enabled
+only when the far-end and near-end devices are running with a common
+reference clock.
+
+The hardware reset value for this field is 0x1 (enabled).
+Note that this register field is only available on RK3588, not on RK3568.
+
+The link training either fails or is highly unstable (link state will jump
+continuously between L0 and recovery) when this mode is enabled while
+using an endpoint running in Separate Reference Clock with No SSC (SRNS)
+mode or Separate Reference Clock with SSC (SRIS) mode.
+(Which is usually the case when using a real SoC as endpoint, e.g. the
+RK3588 PCIe controller can run in both Root Complex and Endpoint mode.)
+
+Add support for the device tree property rockchip,rx-common-refclk-mode,
+such that the PCIe PHY can be used in configurations where the Root
+Complex and Endpoint are not using a common reference clock.
+
+Signed-off-by: Niklas Cassel <cassel@kernel.org>
+Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ .../phy/rockchip/phy-rockchip-snps-pcie3.c    | 37 +++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
++++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+@@ -35,11 +35,17 @@
+ #define RK3588_PCIE3PHY_GRF_CMN_CON0		0x0
+ #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1	0x904
+ #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1	0xa04
++#define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1	0x1004
++#define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1	0x1104
++#define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1	0x2004
++#define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1	0x2104
+ #define RK3588_SRAM_INIT_DONE(reg)		(reg & BIT(0))
+ 
+ #define RK3588_BIFURCATION_LANE_0_1		BIT(0)
+ #define RK3588_BIFURCATION_LANE_2_3		BIT(1)
+ #define RK3588_LANE_AGGREGATION		BIT(2)
++#define RK3588_RX_CMN_REFCLK_MODE_EN		((BIT(7) << 16) |  BIT(7))
++#define RK3588_RX_CMN_REFCLK_MODE_DIS		(BIT(7) << 16)
+ #define RK3588_PCIE1LN_SEL_EN			(GENMASK(1, 0) << 16)
+ #define RK3588_PCIE30_PHY_MODE_EN		(GENMASK(2, 0) << 16)
+ 
+@@ -60,6 +66,7 @@ struct rockchip_p3phy_priv {
+ 	int num_clks;
+ 	int num_lanes;
+ 	u32 lanes[4];
++	u32 rx_cmn_refclk_mode[4];
+ };
+ 
+ struct rockchip_p3phy_ops {
+@@ -137,6 +144,19 @@ static int rockchip_p3phy_rk3588_init(st
+ 	u8 mode = RK3588_LANE_AGGREGATION; /* default */
+ 	int ret;
+ 
++	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1,
++		     priv->rx_cmn_refclk_mode[0] ? RK3588_RX_CMN_REFCLK_MODE_EN :
++		     RK3588_RX_CMN_REFCLK_MODE_DIS);
++	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1,
++		     priv->rx_cmn_refclk_mode[1] ? RK3588_RX_CMN_REFCLK_MODE_EN :
++		     RK3588_RX_CMN_REFCLK_MODE_DIS);
++	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1,
++		     priv->rx_cmn_refclk_mode[2] ? RK3588_RX_CMN_REFCLK_MODE_EN :
++		     RK3588_RX_CMN_REFCLK_MODE_DIS);
++	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1,
++		     priv->rx_cmn_refclk_mode[3] ? RK3588_RX_CMN_REFCLK_MODE_EN :
++		     RK3588_RX_CMN_REFCLK_MODE_DIS);
++
+ 	/* Deassert PCIe PMA output clamp mode */
+ 	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
+ 
+@@ -275,6 +295,23 @@ static int rockchip_p3phy_probe(struct p
+ 		return priv->num_lanes;
+ 	}
+ 
++	ret = of_property_read_variable_u32_array(dev->of_node,
++						  "rockchip,rx-common-refclk-mode",
++						  priv->rx_cmn_refclk_mode, 1,
++						  ARRAY_SIZE(priv->rx_cmn_refclk_mode));
++	/*
++	 * if no rockchip,rx-common-refclk-mode, assume enabled for all lanes in
++	 * order to be DT backwards compatible. (Since HW reset val is enabled.)
++	 */
++	if (ret == -EINVAL) {
++		for (int i = 0; i < ARRAY_SIZE(priv->rx_cmn_refclk_mode); i++)
++			priv->rx_cmn_refclk_mode[i] = 1;
++	} else if (ret < 0) {
++		dev_err(dev, "failed to read rockchip,rx-common-refclk-mode property %d\n",
++			ret);
++		return ret;
++	}
++
+ 	priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
+ 	if (IS_ERR(priv->phy)) {
+ 		dev_err(dev, "failed to create combphy\n");

target/linux/rockchip/patches-6.6/035-v6.7-usb-dwc3-add-optional-PHY-interface-clocks.patch

@@ -1,6 +1,6 @@
-From c686cce2ef2634168938e37caa2a0f8e1de65a94 Mon Sep 17 00:00:00 2001
+From 97789b93b792fc97ad4476b79e0f38ffa8e7e0ee Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Thu, 20 Jul 2023 18:59:37 +0200
+Date: Fri, 20 Oct 2023 16:11:41 +0200
 Subject: [PATCH] usb: dwc3: add optional PHY interface clocks
 
 On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
@@ -8,10 +8,13 @@ requires two extra clocks to be enabled. Without these extra clocks
 hot-plugging USB devices is broken.
 
 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
+Link: https://lore.kernel.org/r/20231020150022.48725-3-sebastian.reichel@collabora.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 ---
- drivers/usb/dwc3/core.c | 26 ++++++++++++++++++++++++++
+ drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++
  drivers/usb/dwc3/core.h |  4 ++++
- 2 files changed, 30 insertions(+)
+ 2 files changed, 32 insertions(+)
 
 --- a/drivers/usb/dwc3/core.c
 +++ b/drivers/usb/dwc3/core.c
@@ -45,25 +48,27 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  	clk_disable_unprepare(dwc->susp_clk);
  	clk_disable_unprepare(dwc->ref_clk);
  	clk_disable_unprepare(dwc->bus_clk);
-@@ -1834,6 +1848,18 @@ static int dwc3_get_clocks(struct dwc3 *
+@@ -1838,6 +1852,20 @@ static int dwc3_get_clocks(struct dwc3 *
- 			return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
- 					"could not get suspend clock\n");
  		}
-+
+ 	}
+ 
++	/* specific to Rockchip RK3588 */
 +	dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
 +	if (IS_ERR(dwc->utmi_clk)) {
 +		return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
 +				"could not get utmi clock\n");
 +	}
 +
++	/* specific to Rockchip RK3588 */
 +	dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
 +	if (IS_ERR(dwc->pipe_clk)) {
 +		return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
 +				"could not get pipe clock\n");
 +	}
++
+ 	return 0;
  }
  
- 	return 0;
 --- a/drivers/usb/dwc3/core.h
 +++ b/drivers/usb/dwc3/core.h
 @@ -996,6 +996,8 @@ struct dwc3_scratchpad_array {
@@ -75,7 +80,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
   * @reset: reset control
   * @regs: base address for our registers
   * @regs_size: address space size
-@@ -1165,6 +1167,8 @@ struct dwc3 {
+@@ -1166,6 +1168,8 @@ struct dwc3 {
  	struct clk		*bus_clk;
  	struct clk		*ref_clk;
  	struct clk		*susp_clk;

target/linux/rockchip/patches-6.6/050-13-v6.10-arm64-dts-rockchip-fix-usb2phy-nodename-for-rk3588.patch

@@ -1,25 +1,14 @@
+From 4e07a95f7402de092cd71b2cb96c69f85c98f251 Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <sebastian.reichel@collabora.com>
-To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
+Date: Tue, 9 Apr 2024 00:50:31 +0200
-	Kishon Vijay Abraham I <kishon@kernel.org>,
+Subject: [PATCH] arm64: dts: rockchip: fix usb2phy nodename for rk3588
-	linux-rockchip@lists.infradead.org,
-	linux-phy@lists.infradead.org
-Cc: Rob Herring <robh+dt@kernel.org>,
-	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
-	Conor Dooley <conor+dt@kernel.org>,
-	Frank Wang <frank.wang@rock-chips.com>,
-	Kever Yang <kever.yang@rock-chips.com>,
-	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
-	Sebastian Reichel <sebastian.reichel@collabora.com>,
-	kernel@collabora.com
-Subject: [PATCH v2 06/12] arm64: dts: rockchip: Fix usb2phy nodename for rk3588
-Date: Tue, 13 Feb 2024 17:32:40 +0100	[thread overview]
-Message-ID: <20240213163609.44930-7-sebastian.reichel@collabora.com> (raw)
-In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
 
 usb2-phy should be named usb2phy according to the DT binding,
 so let's fix it up accordingly.
 
 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20240408225109.128953-5-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 ---
  arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

target/linux/rockchip/patches-6.6/050-14-v6.10-arm64-dts-rockchip-reorder-usb2phy-properties-for-rk3588.patch

@@ -1,25 +1,14 @@
+From abe68e0ca71dddce0e5419e35507cb464d61870d Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <sebastian.reichel@collabora.com>
-To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
+Date: Tue, 9 Apr 2024 00:50:32 +0200
-	Kishon Vijay Abraham I <kishon@kernel.org>,
+Subject: [PATCH] arm64: dts: rockchip: reorder usb2phy properties for rk3588
-	linux-rockchip@lists.infradead.org,
-	linux-phy@lists.infradead.org
-Cc: Rob Herring <robh+dt@kernel.org>,
-	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
-	Conor Dooley <conor+dt@kernel.org>,
-	Frank Wang <frank.wang@rock-chips.com>,
-	Kever Yang <kever.yang@rock-chips.com>,
-	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
-	Sebastian Reichel <sebastian.reichel@collabora.com>,
-	kernel@collabora.com
-Subject: [PATCH v2 07/12] arm64: dts: rockchip: reorder usb2phy properties for rk3588
-Date: Tue, 13 Feb 2024 17:32:41 +0100	[thread overview]
-Message-ID: <20240213163609.44930-8-sebastian.reichel@collabora.com> (raw)
-In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
 
 Reorder common DT properties alphabetically for usb2phy, according
 to latest DT style rules.
 
 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 ---
  arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++--------
  1 file changed, 8 insertions(+), 8 deletions(-)

target/linux/rockchip/patches-6.6/050-15-v6.10-arm64-dts-rockchip-add-USBDP-phys-on-rk3588.patch

@@ -1,28 +1,17 @@
+From e18e5e8188f2671abf63abe7db5f21555705130f Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <sebastian.reichel@collabora.com>
-To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
+Date: Tue, 9 Apr 2024 00:50:33 +0200
-	Kishon Vijay Abraham I <kishon@kernel.org>,
+Subject: [PATCH] arm64: dts: rockchip: add USBDP phys on rk3588
-	linux-rockchip@lists.infradead.org,
-	linux-phy@lists.infradead.org
-Cc: Rob Herring <robh+dt@kernel.org>,
-	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
-	Conor Dooley <conor+dt@kernel.org>,
-	Frank Wang <frank.wang@rock-chips.com>,
-	Kever Yang <kever.yang@rock-chips.com>,
-	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
-	Sebastian Reichel <sebastian.reichel@collabora.com>,
-	kernel@collabora.com
-Subject: [PATCH v2 08/12] arm64: dts: rockchip: add USBDP phys on rk3588
-Date: Tue, 13 Feb 2024 17:32:42 +0100	[thread overview]
-Message-ID: <20240213163609.44930-9-sebastian.reichel@collabora.com> (raw)
-In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
 
 Add both USB3-DisplayPort PHYs to RK3588 SoC DT.
 
 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 ---
- arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 61 +++++++++++++++++++
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 52 +++++++++++++++++++
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 72 +++++++++++++++++++++++
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 63 +++++++++++++++++++++++
- 2 files changed, 133 insertions(+)
+ 2 files changed, 115 insertions(+)
 
 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -63,13 +52,14 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  	i2s8_8ch: i2s@fddc8000 {
  		compatible = "rockchip,rk3588-i2s-tdm";
  		reg = <0x0 0xfddc8000 0x0 0x1000>;
-@@ -310,6 +340,37 @@
+@@ -310,6 +340,28 @@
  		};
  	};
  
 +	usbdp_phy1: phy@fed90000 {
 +		compatible = "rockchip,rk3588-usbdp-phy";
 +		reg = <0x0 0xfed90000 0x0 0x10000>;
++		#phy-cells = <1>;
 +		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
 +			 <&cru CLK_USBDP_PHY1_IMMORTAL>,
 +			 <&cru PCLK_USBDPPHY1>,
@@ -86,16 +76,6 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +		rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
 +		rockchip,vo-grf = <&vo0_grf>;
 +		status = "disabled";
-+
-+		usbdp_phy1_dp: dp-port {
-+			#phy-cells = <0>;
-+			status = "disabled";
-+		};
-+
-+		usbdp_phy1_u3: usb3-port {
-+			#phy-cells = <0>;
-+			status = "disabled";
-+		};
 +	};
 +
  	combphy1_ps: phy@fee10000 {
@@ -164,13 +144,14 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  	usb2phy2_grf: syscon@fd5d8000 {
  		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
  		reg = <0x0 0xfd5d8000 0x0 0x4000>;
-@@ -2360,6 +2401,37 @@
+@@ -2360,6 +2401,28 @@
  		#dma-cells = <1>;
  	};
  
 +	usbdp_phy0: phy@fed80000 {
 +		compatible = "rockchip,rk3588-usbdp-phy";
 +		reg = <0x0 0xfed80000 0x0 0x10000>;
++		#phy-cells = <1>;
 +		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
 +			 <&cru CLK_USBDP_PHY0_IMMORTAL>,
 +			 <&cru PCLK_USBDPPHY0>,
@@ -187,16 +168,6 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +		rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
 +		rockchip,vo-grf = <&vo0_grf>;
 +		status = "disabled";
-+
-+		usbdp_phy0_dp: dp-port {
-+			#phy-cells = <0>;
-+			status = "disabled";
-+		};
-+
-+		usbdp_phy0_u3: usb3-port {
-+			#phy-cells = <0>;
-+			status = "disabled";
-+		};
 +	};
 +
  	combphy0_ps: phy@fee00000 {

target/linux/rockchip/patches-6.6/050-16-v6.10-arm64-dts-rockchip-add-USB3-DRD-controllers-on-rk3588.patch

@@ -1,24 +1,13 @@
+From 33f393a2a990e16f56931ca708295f31d2b44415 Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <sebastian.reichel@collabora.com>
-To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
+Date: Tue, 9 Apr 2024 00:50:34 +0200
-	Kishon Vijay Abraham I <kishon@kernel.org>,
+Subject: [PATCH] arm64: dts: rockchip: add USB3 DRD controllers on rk3588
-	linux-rockchip@lists.infradead.org,
-	linux-phy@lists.infradead.org
-Cc: Rob Herring <robh+dt@kernel.org>,
-	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
-	Conor Dooley <conor+dt@kernel.org>,
-	Frank Wang <frank.wang@rock-chips.com>,
-	Kever Yang <kever.yang@rock-chips.com>,
-	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
-	Sebastian Reichel <sebastian.reichel@collabora.com>,
-	kernel@collabora.com
-Subject: [PATCH v2 09/12] arm64: dts: rockchip: add USB3 DRD controllers on rk3588
-Date: Tue, 13 Feb 2024 17:32:43 +0100	[thread overview]
-Message-ID: <20240213163609.44930-10-sebastian.reichel@collabora.com> (raw)
-In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
 
 Add both USB3 dual-role controllers to the RK3588 devicetree.
 
 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 ---
  arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 20 ++++++++++++++++++++
  arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++++
@@ -38,7 +27,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +			 <&cru ACLK_USB3OTG1>;
 +		clock-names = "ref_clk", "suspend_clk", "bus_clk";
 +		dr_mode = "otg";
-+		phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
++		phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
 +		phy-names = "usb2-phy", "usb3-phy";
 +		phy_type = "utmi_wide";
 +		power-domains = <&power RK3588_PD_USB>;
@@ -67,7 +56,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +			 <&cru ACLK_USB3OTG0>;
 +		clock-names = "ref_clk", "suspend_clk", "bus_clk";
 +		dr_mode = "otg";
-+		phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
++		phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
 +		phy-names = "usb2-phy", "usb3-phy";
 +		phy_type = "utmi_wide";
 +		power-domains = <&power RK3588_PD_USB>;

target/linux/rockchip/patches-6.6/051-05-v6.10-arm64-dts-rockchip-add-USB3-to-rk3588-evb1.patch

@@ -1,28 +1,17 @@
+From b37146b5a555dd871cb0805446826ab2fc8d285a Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <sebastian.reichel@collabora.com>
-To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
+Date: Tue, 9 Apr 2024 00:50:35 +0200
-	Kishon Vijay Abraham I <kishon@kernel.org>,
+Subject: [PATCH] arm64: dts: rockchip: add USB3 to rk3588-evb1
-	linux-rockchip@lists.infradead.org,
-	linux-phy@lists.infradead.org
-Cc: Rob Herring <robh+dt@kernel.org>,
-	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
-	Conor Dooley <conor+dt@kernel.org>,
-	Frank Wang <frank.wang@rock-chips.com>,
-	Kever Yang <kever.yang@rock-chips.com>,
-	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
-	Sebastian Reichel <sebastian.reichel@collabora.com>,
-	kernel@collabora.com
-Subject: [PATCH v2 10/12] arm64: dts: rockchip: add USB3 to rk3588-evb1
-Date: Tue, 13 Feb 2024 17:32:44 +0100	[thread overview]
-Message-ID: <20240213163609.44930-11-sebastian.reichel@collabora.com> (raw)
-In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
 
 Add support for the board's USB3 connectors. It has 1x USB Type-A
 and 1x USB Type-C.
 
 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20240408225109.128953-9-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 ---
- .../boot/dts/rockchip/rk3588-evb1-v10.dts     | 151 ++++++++++++++++++
+ .../boot/dts/rockchip/rk3588-evb1-v10.dts     | 147 ++++++++++++++++++
- 1 file changed, 151 insertions(+)
+ 1 file changed, 147 insertions(+)
 
 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -34,26 +23,26 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  #include "rk3588.dtsi"
  
  / {
-@@ -166,6 +167,18 @@
+@@ -101,6 +102,18 @@
- 		regulator-max-microvolt = <5000000>;
+ 		vin-supply = <&avcc_1v8_s0>;
- 		vin-supply = <&vcc5v0_usbdcin>;
  	};
-+
+ 
-+	vbus5v0_typec: vbus5v0-typec {
++	vbus5v0_typec: vbus5v0-typec-regulator {
 +		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&typec5v_pwren>;
 +		regulator-name = "vbus5v0_typec";
 +		regulator-min-microvolt = <5000000>;
 +		regulator-max-microvolt = <5000000>;
-+		enable-active-high;
-+		gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
 +		vin-supply = <&vcc5v0_usb>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&typec5v_pwren>;
 +	};
- };
++
- 
+ 	vcc12v_dcin: vcc12v-dcin-regulator {
- &combphy0_ps {
+ 		compatible = "regulator-fixed";
-@@ -226,6 +239,56 @@
+ 		regulator-name = "vcc12v_dcin";
+@@ -226,6 +239,59 @@
  &i2c2 {
  	status = "okay";
  
@@ -71,13 +60,13 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +			compatible = "usb-c-connector";
 +			label = "USB-C";
 +			data-role = "dual";
-+			power-role = "dual";
-+			try-power-role = "source";
 +			op-sink-microwatt = <1000000>;
++			power-role = "dual";
 +			sink-pdos =
 +				<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
 +			source-pdos =
 +				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
++			try-power-role = "source";
 +
 +			ports {
 +				#address-cells = <1>;
@@ -85,6 +74,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +
 +				port@0 {
 +					reg = <0>;
++
 +					usbc0_orien_sw: endpoint {
 +						remote-endpoint = <&usbdp_phy0_orientation_switch>;
 +					};
@@ -92,6 +82,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +
 +				port@1 {
 +					reg = <1>;
++
 +					usbc0_role_sw: endpoint {
 +						remote-endpoint = <&dwc3_0_role_switch>;
 +					};
@@ -99,6 +90,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +
 +				port@2 {
 +					reg = <2>;
++
 +					dp_altmode_mux: endpoint {
 +						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
 +					};
@@ -110,24 +102,24 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  	hym8563: rtc@51 {
  		compatible = "haoyu,hym8563";
  		reg = <0x51>;
-@@ -312,6 +375,16 @@
+@@ -312,6 +378,16 @@
  			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
  		};
  	};
 +
 +	usb-typec {
-+		usbc0_int: usbc0-int {
-+			rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+
 +		typec5v_pwren: typec5v-pwren {
 +			rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
 +		};
++
++		usbc0_int: usbc0-int {
++			rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
 +	};
  };
  
  &pwm2 {
-@@ -944,6 +1017,22 @@
+@@ -944,6 +1020,22 @@
  	status = "okay";
  };
  
@@ -150,14 +142,14 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  &u2phy2 {
  	status = "okay";
  };
-@@ -982,3 +1071,65 @@
+@@ -982,3 +1074,58 @@
  &usb_host1_ohci {
  	status = "okay";
  };
 +
 +&usbdp_phy0 {
-+	orientation-switch;
 +	mode-switch;
++	orientation-switch;
 +	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
 +	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
 +	status = "okay";
@@ -178,10 +170,6 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	};
 +};
 +
-+&usbdp_phy0_u3 {
-+	status = "okay";
-+};
-+
 +&usbdp_phy1 {
 +	/*
 +	 * USBDP PHY1 is wired to a female USB3 Type-A connector. Additionally
@@ -193,10 +181,6 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	status = "okay";
 +};
 +
-+&usbdp_phy1_u3 {
-+	status = "okay";
-+};
-+
 +&usb_host0_xhci {
 +	dr_mode = "otg";
 +	usb-role-switch;
@@ -205,6 +189,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 +	port {
 +		#address-cells = <1>;
 +		#size-cells = <0>;
++
 +		dwc3_0_role_switch: endpoint@0 {
 +			reg = <0>;
 +			remote-endpoint = <&usbc0_role_sw>;

target/linux/rockchip/patches-6.6/052-02-v6.10-arm64-dts-rockchip-add-upper-USB3-port-to-rock-5a.patch

@@ -0,0 +1,56 @@
+From af7ec140ddc1815bc462109792d95bcad05cfbc4 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 9 Apr 2024 00:50:36 +0200
+Subject: [PATCH] arm64: dts: rockchip: add upper USB3 port to rock-5a
+
+Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from
+Radxa Rock 5 Model A. The lower one is already supported.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20240408225109.128953-10-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3588s-rock-5a.dts      | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -697,6 +697,14 @@
+ 	};
+ };
+ 
++&u2phy0 {
++	status = "okay";
++};
++
++&u2phy0_otg {
++	status = "okay";
++};
++
+ &u2phy2 {
+ 	status = "okay";
+ };
+@@ -720,6 +728,11 @@
+ 	status = "okay";
+ };
+ 
++&usbdp_phy0 {
++	status = "okay";
++	rockchip,dp-lane-mux = <2 3>;
++};
++
+ &usb_host0_ehci {
+ 	status = "okay";
+ 	pinctrl-names = "default";
+@@ -730,6 +743,11 @@
+ 	status = "okay";
+ };
+ 
++&usb_host0_xhci {
++	dr_mode = "host";
++	status = "okay";
++};
++
+ &usb_host1_ehci {
+ 	status = "okay";
+ };

target/linux/rockchip/patches-6.6/053-12-v6.10-arm64-dts-rockchip-add-lower-USB3-port-to-rock-5b.patch

@@ -0,0 +1,55 @@
+From 494532921aacb496529d544fedfdb3a7b43dfef0 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 9 Apr 2024 00:50:37 +0200
+Subject: [PATCH] arm64: dts: rockchip: add lower USB3 port to rock-5b
+
+Enable full support (XHCI, EHCI, OHCI) for the lower USB3 port from
+Radxa Rock 5 Model B. The upper one is already supported.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20240408225109.128953-11-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -743,6 +743,14 @@
+ 	status = "okay";
+ };
+ 
++&u2phy1 {
++	status = "okay";
++};
++
++&u2phy1_otg {
++	status = "okay";
++};
++
+ &u2phy2 {
+ 	status = "okay";
+ };
+@@ -762,6 +770,10 @@
+ 	status = "okay";
+ };
+ 
++&usbdp_phy1 {
++	status = "okay";
++};
++
+ &usb_host0_ehci {
+ 	status = "okay";
+ };
+@@ -778,6 +790,11 @@
+ 	status = "okay";
+ };
+ 
++&usb_host1_xhci {
++	dr_mode = "host";
++	status = "okay";
++};
++
+ &usb_host2_xhci {
+ 	status = "okay";
+ };

target/linux/rockchip/patches-6.6/053-13-v6.10-arm64-dts-rockchip-Correct-the-model-names-for-Radxa-ROCK.patch

@@ -0,0 +1,43 @@
+From 45e831033f7a00a14f64afa1e34c476a9ff0f9f0 Mon Sep 17 00:00:00 2001
+From: Dragan Simic <dsimic@manjaro.org>
+Date: Thu, 18 Apr 2024 18:26:20 +0200
+Subject: [PATCH] arm64: dts: rockchip: Correct the model names for Radxa ROCK
+ 5 boards
+
+Correct the descriptions of a few Radxa boards, according to the up-to-date
+documentation from Radxa and the detailed explanation from Naoki. [1]  To sum
+it up, the short naming, as specified by Radxa, is preferred.
+
+[1] https://lore.kernel.org/linux-rockchip/B26C732A4DCEA9B3+282b8775-601b-4d4a-a513-4924b7940076@radxa.com/
+
+Suggested-by: FUKAUMI Naoki <naoki@radxa.com>
+Signed-off-by: Dragan Simic <dsimic@manjaro.org>
+Link: https://lore.kernel.org/r/6931289a252dc2d6c7bfd2388835c5e98ba0d8c9.1713457260.git.dsimic@manjaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts  | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -7,7 +7,7 @@
+ #include "rk3588.dtsi"
+ 
+ / {
+-	model = "Radxa ROCK 5 Model B";
++	model = "Radxa ROCK 5B";
+ 	compatible = "radxa,rock-5b", "rockchip,rk3588";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -8,7 +8,7 @@
+ #include "rk3588s.dtsi"
+ 
+ / {
+-	model = "Radxa ROCK 5 Model A";
++	model = "Radxa ROCK 5A";
+ 	compatible = "radxa,rock-5a", "rockchip,rk3588s";
+ 
+ 	aliases {

target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch

@@ -484,7 +484,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 @@ -9,11 +9,16 @@
  
  / {
- 	model = "Radxa ROCK 5 Model A";
+ 	model = "Radxa ROCK 5A";
 -	compatible = "radxa,rock-5a", "rockchip,rk3588s";
 +	compatible = "radxa,rock-5a", "rockchip,rk3588";
  

target/linux/rockchip/patches-6.6/112-07-arm64-dts-rockchip-add-upper-USB3-port-to-rock-5a.patch

@@ -1,71 +0,0 @@
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
-	Kishon Vijay Abraham I <kishon@kernel.org>,
-	linux-rockchip@lists.infradead.org,
-	linux-phy@lists.infradead.org
-Cc: Rob Herring <robh+dt@kernel.org>,
-	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
-	Conor Dooley <conor+dt@kernel.org>,
-	Frank Wang <frank.wang@rock-chips.com>,
-	Kever Yang <kever.yang@rock-chips.com>,
-	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
-	Sebastian Reichel <sebastian.reichel@collabora.com>,
-	kernel@collabora.com
-Subject: [PATCH v2 11/12] arm64: dts: rockchip: add upper USB3 port to rock-5a
-Date: Tue, 13 Feb 2024 17:32:45 +0100	[thread overview]
-Message-ID: <20240213163609.44930-12-sebastian.reichel@collabora.com> (raw)
-In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
-
-Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from
-Radxa Rock 5 Model A. The lower one is already supported.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
----
- .../boot/dts/rockchip/rk3588s-rock-5a.dts     | 22 +++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -699,6 +699,14 @@
- 	};
- };
- 
-+&u2phy0 {
-+	status = "okay";
-+};
-+
-+&u2phy0_otg {
-+	status = "okay";
-+};
-+
- &u2phy2 {
- 	status = "okay";
- };
-@@ -722,6 +730,15 @@
- 	status = "okay";
- };
- 
-+&usbdp_phy0 {
-+	status = "okay";
-+	rockchip,dp-lane-mux = <2 3>;
-+};
-+
-+&usbdp_phy0_u3 {
-+	status = "okay";
-+};
-+
- &usb_host0_ehci {
- 	status = "okay";
- 	pinctrl-names = "default";
-@@ -732,6 +749,11 @@
- 	status = "okay";
- };
- 
-+&usb_host0_xhci {
-+	dr_mode = "host";
-+	status = "okay";
-+};
-+
- &usb_host1_ehci {
- 	status = "okay";
- };

target/linux/rockchip/patches-6.6/112-08-arm64-dts-rockchip-add-lower-USB3-port-to-rock-5b.patch

@@ -1,70 +0,0 @@
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
-	Kishon Vijay Abraham I <kishon@kernel.org>,
-	linux-rockchip@lists.infradead.org,
-	linux-phy@lists.infradead.org
-Cc: Rob Herring <robh+dt@kernel.org>,
-	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
-	Conor Dooley <conor+dt@kernel.org>,
-	Frank Wang <frank.wang@rock-chips.com>,
-	Kever Yang <kever.yang@rock-chips.com>,
-	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
-	Sebastian Reichel <sebastian.reichel@collabora.com>,
-	kernel@collabora.com
-Subject: [PATCH v2 12/12] arm64: dts: rockchip: add lower USB3 port to rock-5b
-Date: Tue, 13 Feb 2024 17:32:46 +0100	[thread overview]
-Message-ID: <20240213163609.44930-13-sebastian.reichel@collabora.com> (raw)
-In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
-
-Enable full support (XHCI, EHCI, OHCI) for the lower USB3 port from
-Radxa Rock 5 Model B. The upper one is already supported.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
----
- .../boot/dts/rockchip/rk3588-rock-5b.dts      | 21 +++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -745,6 +745,14 @@
- 	status = "okay";
- };
- 
-+&u2phy1 {
-+	status = "okay";
-+};
-+
-+&u2phy1_otg {
-+	status = "okay";
-+};
-+
- &u2phy2 {
- 	status = "okay";
- };
-@@ -764,6 +772,14 @@
- 	status = "okay";
- };
- 
-+&usbdp_phy1 {
-+	status = "okay";
-+};
-+
-+&usbdp_phy1_u3 {
-+	status = "okay";
-+};
-+
- &usb_host0_ehci {
- 	status = "okay";
- };
-@@ -780,6 +796,11 @@
- 	status = "okay";
- };
- 
-+&usb_host1_xhci {
-+	dr_mode = "host";
-+	status = "okay";
-+};
-+
- &usb_host2_xhci {
- 	status = "okay";
- };

target/linux/rockchip/patches-6.6/113-02-usb-typec-tcpm-avoid-graph-warning.patch

@@ -1,42 +0,0 @@
-From 2d51b382bcd4b05d944b55d483caac1fda338908 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Fri, 28 Jul 2023 16:43:16 +0200
-Subject: [PATCH] usb: typec: tcpm: avoid graph warning
-
-When using a devicetree as described in commit d56de8c9a17d ("usb:
-typec: tcpm: try to get role switch from tcpc fwnode"), the kernel
-will print an error when probing the TCPM driver, which looks
-similar to this:
-
-OF: graph: no port node found in /i2c@feac0000/usb-typec@22
-
-This is a false positive, since the code first tries to find a ports
-node for the device and only then checks the fwnode. Fix this by
-swapping the order.
-
-Note, that this will now generate a error message for devicetrees with
-a role-switch ports node directly in the TCPM node instead of in the
-connectors sub-node, before falling back to the legacy behaviour. These
-devicetrees generate warnings when being checked against the bindings,
-and should be fixed.
-
-Fixes: d56de8c9a17d ("usb: typec: tcpm: try to get role switch from tcpc fwnode")
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
----
- drivers/usb/typec/tcpm/tcpm.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/usb/typec/tcpm/tcpm.c
-+++ b/drivers/usb/typec/tcpm/tcpm.c
-@@ -6595,9 +6595,9 @@ struct tcpm_port *tcpm_register_port(str
- 	port->partner_desc.identity = &port->partner_ident;
- 	port->port_type = port->typec_caps.type;
- 
--	port->role_sw = usb_role_switch_get(port->dev);
-+	port->role_sw = fwnode_usb_role_switch_get(tcpc->fwnode);
- 	if (!port->role_sw)
--		port->role_sw = fwnode_usb_role_switch_get(tcpc->fwnode);
-+		port->role_sw = usb_role_switch_get(port->dev);
- 	if (IS_ERR(port->role_sw)) {
- 		err = PTR_ERR(port->role_sw);
- 		goto out_destroy_wq;

target/linux/rockchip/patches-6.6/121-01-arm64-dts-rockchip-rk3588-evb1-add-cpu-regulator-info.patch

@@ -35,7 +35,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  &gmac0 {
  	clock_in_out = "output";
  	phy-handle = <&rgmii_phy>;
-@@ -1051,6 +1066,10 @@
+@@ -1054,6 +1069,10 @@
  	status = "okay";
  };
  

target/linux/rockchip/patches-6.6/123-07-arm64-dts-rockchip-rk3588-rock5b-add-USB-C-support.patch

@@ -139,7 +139,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  &u2phy1 {
  	status = "okay";
  };
-@@ -788,6 +866,33 @@
+@@ -784,6 +862,33 @@
  	status = "okay";
  };
  
@@ -173,7 +173,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  &usb_host0_ehci {
  	status = "okay";
  };
-@@ -796,6 +901,20 @@
+@@ -792,6 +897,20 @@
  	status = "okay";
  };
  

target/linux/rockchip/patches-6.6/600-net-ethernet-r8169-add-LED-configuration-from-OF.patch

@@ -16,7 +16,7 @@
  	TxDescStartAddrLow	= 0x20,
  	TxDescStartAddrHigh	= 0x24,
  	TxHDescStartAddrLow	= 0x28,
-@@ -2181,6 +2183,22 @@ void r8169_apply_firmware(struct rtl8169
+@@ -2204,6 +2206,22 @@ void r8169_apply_firmware(struct rtl8169
  	}
  }
  
@@ -39,7 +39,7 @@
  static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
  {
  	/* Adjust EEE LED frequency */
-@@ -3321,6 +3339,7 @@ static void rtl_hw_start_8168h_1(struct
+@@ -3344,6 +3362,7 @@ static void rtl_hw_start_8168h_1(struct
  	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
  	r8168_mac_ocp_write(tp, 0xc094, 0x0000);
  	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
@@ -47,7 +47,7 @@
  }
  
  static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
-@@ -3672,6 +3691,7 @@ static void rtl_hw_start_8125b(struct rt
+@@ -3695,6 +3714,7 @@ static void rtl_hw_start_8125b(struct rt
  	rtl_set_def_aspm_entry_latency(tp);
  	rtl_ephy_init(tp, e_info_8125b);
  	rtl_hw_start_8125_common(tp);

target/linux/rockchip/patches-6.6/602-net-ethernet-r8169-add-devname-configuration-from-OF.patch

@@ -1,6 +1,6 @@
 --- a/drivers/net/ethernet/realtek/r8169_main.c
 +++ b/drivers/net/ethernet/realtek/r8169_main.c
-@@ -2183,6 +2183,22 @@ void r8169_apply_firmware(struct rtl8169
+@@ -2206,6 +2206,22 @@ void r8169_apply_firmware(struct rtl8169
  	}
  }
  
@@ -23,7 +23,7 @@
  static int rtl8169_led_configuration(struct rtl8169_private *tp)
  {
  	u32 led_data;
-@@ -3691,6 +3707,7 @@ static void rtl_hw_start_8125b(struct rt
+@@ -3714,6 +3730,7 @@ static void rtl_hw_start_8125b(struct rt
  	rtl_set_def_aspm_entry_latency(tp);
  	rtl_ephy_init(tp, e_info_8125b);
  	rtl_hw_start_8125_common(tp);

target/linux/rockchip/patches-6.6/700-phy-rockchip-snps-pcie3-rk3568-update-fw-when-init.patch

@@ -25,7 +25,7 @@ Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
  #define GRF_PCIE30PHY_CON6			0x18
  #define GRF_PCIE30PHY_CON9			0x24
  #define GRF_PCIE30PHY_DA_OCM			(BIT(15) | BIT(31))
-@@ -64,6 +65,10 @@ struct rockchip_p3phy_ops {
+@@ -73,6 +74,10 @@ struct rockchip_p3phy_ops {
  	int (*phy_init)(struct rockchip_p3phy_priv *priv);
  };
  
@@ -36,7 +36,7 @@ Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
  static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
  {
  	struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
-@@ -88,13 +93,14 @@ static int rockchip_p3phy_rk3568_init(st
+@@ -97,13 +102,14 @@ static int rockchip_p3phy_rk3568_init(st
  {
  	struct phy *phy = priv->phy;
  	bool bifurcation = false;
@@ -52,7 +52,7 @@ Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
  		dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
  		if (priv->lanes[i] > 1)
  			bifurcation = true;
-@@ -113,16 +119,35 @@ static int rockchip_p3phy_rk3568_init(st
+@@ -122,16 +128,35 @@ static int rockchip_p3phy_rk3568_init(st
  			     GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
  	}
  

target/linux/rockchip/patches-6.6/801-03-arm64-dts-rockchip-add-rng-node-for-rk3399.patch

@@ -13,7 +13,7 @@ Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
 
 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -2106,6 +2106,15 @@
+@@ -2114,6 +2114,15 @@
  		};
  	};
  

target/linux/rockchip/patches-6.6/805-arm64-dts-rockchip-add-rk3328-ddr-relate-node.patch

@@ -28,7 +28,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
  
  / {
  	compatible = "rockchip,rk3328";
-@@ -1025,6 +1026,78 @@
+@@ -1034,6 +1035,78 @@
  		status = "disabled";
  	};