rockchip: backport upstreamed cpufreq support
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
parent
7f2199ef6b
commit
095f52b437
@ -1,6 +1,5 @@
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CONFIG_64BIT=y
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CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
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# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set
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CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
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CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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@ -70,7 +69,6 @@ CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
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CONFIG_ARM_PSCI_FW=y
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CONFIG_ARM_RK3328_DMC_DEVFREQ=y
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# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
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CONFIG_ARM_ROCKCHIP_CPUFREQ=y
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CONFIG_ARM_SCMI_CPUFREQ=y
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CONFIG_ARM_SCMI_HAVE_SHMEM=y
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CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
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@ -88,7 +86,6 @@ CONFIG_ARM_SMMU=y
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CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
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# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
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CONFIG_ARM_SMMU_V3=y
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# CONFIG_ARM_SMMU_V3_PMU is not set
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# CONFIG_ARM_SMMU_V3_SVA is not set
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CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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@ -168,17 +168,14 @@
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&cpu_l0 {
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cpu-supply = <&vdd_cpu_lit_s0>;
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mem-supply = <&vdd_cpu_lit_mem_s0>;
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};
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&cpu_b0 {
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cpu-supply = <&vdd_cpu_big0_s0>;
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mem-supply = <&vdd_cpu_big0_mem_s0>;
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};
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&cpu_b2 {
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cpu-supply = <&vdd_cpu_big1_s0>;
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mem-supply = <&vdd_cpu_big1_mem_s0>;
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};
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&gmac1 {
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@ -211,7 +208,7 @@
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pinctrl-0 = <&i2c0m2_xfer>;
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status = "okay";
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vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 {
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vdd_cpu_big0_s0: regulator@42 {
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compatible = "rockchip,rk8602";
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reg = <0x42>;
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fcs,suspend-voltage-selector = <1>;
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@ -228,7 +225,7 @@
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};
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};
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vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 {
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vdd_cpu_big1_s0: regulator@43 {
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compatible = "rockchip,rk8603", "rockchip,rk8602";
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reg = <0x43>;
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fcs,suspend-voltage-selector = <1>;
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@ -18,8 +18,8 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -448,6 +448,27 @@
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reg = <0x0 0xfd58a000 0x0 0x10000>;
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@@ -443,6 +443,27 @@
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status = "disabled";
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};
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+ usb_host2_xhci: usb@fcd00000 {
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@ -43,6 +43,6 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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+ status = "disabled";
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+ };
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+
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sys_grf: syscon@fd58c000 {
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compatible = "rockchip,rk3588-sys-grf", "syscon";
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reg = <0x0 0xfd58c000 0x0 0x1000>;
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pmu1grf: syscon@fd58a000 {
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compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
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reg = <0x0 0xfd58a000 0x0 0x10000>;
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@ -16,7 +16,7 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -480,6 +480,62 @@
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@@ -501,6 +501,62 @@
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status = "disabled";
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};
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@ -39,105 +39,129 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
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@@ -436,50 +436,6 @@
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@@ -436,6 +436,62 @@
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};
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};
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- usb_host0_ehci: usb@fc800000 {
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- compatible = "rockchip,rk3588-ehci", "generic-ehci";
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- reg = <0x0 0xfc800000 0x0 0x40000>;
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- interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
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- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
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- phys = <&u2phy2_host>;
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- phy-names = "usb";
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- power-domains = <&power RK3588_PD_USB>;
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- status = "disabled";
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- };
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-
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- usb_host0_ohci: usb@fc840000 {
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- compatible = "rockchip,rk3588-ohci", "generic-ohci";
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- reg = <0x0 0xfc840000 0x0 0x40000>;
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- interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
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- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
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- phys = <&u2phy2_host>;
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- phy-names = "usb";
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- power-domains = <&power RK3588_PD_USB>;
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- status = "disabled";
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- };
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-
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- usb_host1_ehci: usb@fc880000 {
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- compatible = "rockchip,rk3588-ehci", "generic-ehci";
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- reg = <0x0 0xfc880000 0x0 0x40000>;
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- interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
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- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
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- phys = <&u2phy3_host>;
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- phy-names = "usb";
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- power-domains = <&power RK3588_PD_USB>;
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- status = "disabled";
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- };
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-
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- usb_host1_ohci: usb@fc8c0000 {
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- compatible = "rockchip,rk3588-ohci", "generic-ohci";
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- reg = <0x0 0xfc8c0000 0x0 0x40000>;
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- interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
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- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
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- phys = <&u2phy3_host>;
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- phy-names = "usb";
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- power-domains = <&power RK3588_PD_USB>;
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- status = "disabled";
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- };
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-
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gpu: gpu@fb000000 {
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compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
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reg = <0x0 0xfb000000 0x0 0x200000>;
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@@ -536,6 +492,50 @@
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};
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+ gpu: gpu@fb000000 {
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+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
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+ reg = <0x0 0xfb000000 0x0 0x200000>;
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+ #cooling-cells = <2>;
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+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
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+ assigned-clock-rates = <200000000>;
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+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
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+ <&cru CLK_GPU_STACKS>;
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+ clock-names = "core", "coregroup", "stacks";
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+ dynamic-power-coefficient = <2982>;
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+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
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+ interrupt-names = "job", "mmu", "gpu";
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+ operating-points-v2 = <&gpu_opp_table>;
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+ power-domains = <&power RK3588_PD_GPU>;
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+ status = "disabled";
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+
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+ gpu_opp_table: opp-table {
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+ compatible = "operating-points-v2";
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+
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+ opp-300000000 {
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+ opp-hz = /bits/ 64 <300000000>;
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+ opp-microvolt = <675000 675000 850000>;
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+ };
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+ opp-400000000 {
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+ opp-hz = /bits/ 64 <400000000>;
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+ opp-microvolt = <675000 675000 850000>;
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+ };
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+ opp-500000000 {
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+ opp-hz = /bits/ 64 <500000000>;
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+ opp-microvolt = <675000 675000 850000>;
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+ };
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+ opp-600000000 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt = <675000 675000 850000>;
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+ };
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+ opp-700000000 {
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+ opp-hz = /bits/ 64 <700000000>;
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+ opp-microvolt = <700000 700000 850000>;
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+ };
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+ opp-800000000 {
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+ opp-hz = /bits/ 64 <800000000>;
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+ opp-microvolt = <750000 750000 850000>;
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+ };
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+ opp-900000000 {
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+ opp-hz = /bits/ 64 <900000000>;
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+ opp-microvolt = <800000 800000 850000>;
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+ };
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+ opp-1000000000 {
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+ opp-hz = /bits/ 64 <1000000000>;
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+ opp-microvolt = <850000 850000 850000>;
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+ };
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+ };
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+ };
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+
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usb_host0_ehci: usb@fc800000 {
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compatible = "rockchip,rk3588-ehci", "generic-ehci";
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reg = <0x0 0xfc800000 0x0 0x40000>;
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@@ -501,62 +557,6 @@
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status = "disabled";
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};
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+ usb_host0_ehci: usb@fc800000 {
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+ compatible = "rockchip,rk3588-ehci", "generic-ehci";
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+ reg = <0x0 0xfc800000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
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+ phys = <&u2phy2_host>;
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+ phy-names = "usb";
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+ power-domains = <&power RK3588_PD_USB>;
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+ status = "disabled";
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+ };
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+
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+ usb_host0_ohci: usb@fc840000 {
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+ compatible = "rockchip,rk3588-ohci", "generic-ohci";
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+ reg = <0x0 0xfc840000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
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+ phys = <&u2phy2_host>;
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+ phy-names = "usb";
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+ power-domains = <&power RK3588_PD_USB>;
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+ status = "disabled";
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+ };
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+
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+ usb_host1_ehci: usb@fc880000 {
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+ compatible = "rockchip,rk3588-ehci", "generic-ehci";
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+ reg = <0x0 0xfc880000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
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+ phys = <&u2phy3_host>;
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+ phy-names = "usb";
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+ power-domains = <&power RK3588_PD_USB>;
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+ status = "disabled";
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+ };
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+
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+ usb_host1_ohci: usb@fc8c0000 {
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+ compatible = "rockchip,rk3588-ohci", "generic-ohci";
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+ reg = <0x0 0xfc8c0000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
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+ phys = <&u2phy3_host>;
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+ phy-names = "usb";
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+ power-domains = <&power RK3588_PD_USB>;
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+ status = "disabled";
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+ };
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+
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- gpu: gpu@fb000000 {
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- compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
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- reg = <0x0 0xfb000000 0x0 0x200000>;
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- #cooling-cells = <2>;
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- assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
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- assigned-clock-rates = <200000000>;
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- clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
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- <&cru CLK_GPU_STACKS>;
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- clock-names = "core", "coregroup", "stacks";
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- dynamic-power-coefficient = <2982>;
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- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
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- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
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- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
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- interrupt-names = "job", "mmu", "gpu";
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- operating-points-v2 = <&gpu_opp_table>;
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- power-domains = <&power RK3588_PD_GPU>;
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- status = "disabled";
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-
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- gpu_opp_table: opp-table {
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- compatible = "operating-points-v2";
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-
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- opp-300000000 {
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- opp-hz = /bits/ 64 <300000000>;
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- opp-microvolt = <675000 675000 850000>;
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- };
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- opp-400000000 {
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- opp-hz = /bits/ 64 <400000000>;
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- opp-microvolt = <675000 675000 850000>;
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- };
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- opp-500000000 {
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- opp-hz = /bits/ 64 <500000000>;
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- opp-microvolt = <675000 675000 850000>;
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- };
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- opp-600000000 {
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- opp-hz = /bits/ 64 <600000000>;
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- opp-microvolt = <675000 675000 850000>;
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- };
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- opp-700000000 {
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- opp-hz = /bits/ 64 <700000000>;
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- opp-microvolt = <700000 700000 850000>;
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- };
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- opp-800000000 {
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- opp-hz = /bits/ 64 <800000000>;
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- opp-microvolt = <750000 750000 850000>;
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- };
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- opp-900000000 {
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- opp-hz = /bits/ 64 <900000000>;
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- opp-microvolt = <800000 800000 850000>;
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- };
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- opp-1000000000 {
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- opp-hz = /bits/ 64 <1000000000>;
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- opp-microvolt = <850000 850000 850000>;
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- };
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- };
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- };
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-
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pmu1grf: syscon@fd58a000 {
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compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
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reg = <0x0 0xfd58a000 0x0 0x10000>;
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@ -41,7 +41,7 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -558,6 +558,30 @@
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@@ -579,6 +579,30 @@
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status = "disabled";
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};
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,193 @@
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From 510cd9e688453166b2bff3999ed21cac97385bb5 Mon Sep 17 00:00:00 2001
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From: Alexey Charkov <alchark@gmail.com>
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Date: Mon, 17 Jun 2024 22:28:51 +0400
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Subject: [PATCH] arm64: dts: rockchip: add thermal zones information on RK3588
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This includes the necessary device tree data to allow thermal
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monitoring on RK3588(s) using the on-chip TSADC device, along with
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trip points for automatic thermal management.
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Each of the CPU clusters (one for the little cores and two for
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the big cores) get a passive cooling trip point at 85C, which
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will trigger DVFS throttling of the respective cluster upon
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reaching a high temperature condition.
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All zones also have a critical trip point at 115C, which will
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trigger a reset.
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Signed-off-by: Alexey Charkov <alchark@gmail.com>
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Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-1-c1f5f3267f1e@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 153 ++++++++++++++++++
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1 file changed, 153 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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@@ -10,6 +10,7 @@
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/ata/ahci.h>
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+#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "rockchip,rk3588";
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@@ -2368,6 +2369,158 @@
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status = "disabled";
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};
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+ thermal_zones: thermal-zones {
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+ /* sensor near the center of the SoC */
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+ package_thermal: package-thermal {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsadc 0>;
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+
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+ trips {
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+ package_crit: package-crit {
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+ temperature = <115000>;
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+ hysteresis = <0>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+
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+ /* sensor between A76 cores 0 and 1 */
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+ bigcore0_thermal: bigcore0-thermal {
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+ polling-delay-passive = <100>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsadc 1>;
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+
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+ trips {
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+ bigcore0_alert: bigcore0-alert {
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+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+
|
||||
+ bigcore0_crit: bigcore0-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&bigcore0_alert>;
|
||||
+ cooling-device =
|
||||
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* sensor between A76 cores 2 and 3 */
|
||||
+ bigcore2_thermal: bigcore2-thermal {
|
||||
+ polling-delay-passive = <100>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 2>;
|
||||
+
|
||||
+ trips {
|
||||
+ bigcore2_alert: bigcore2-alert {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+
|
||||
+ bigcore2_crit: bigcore2-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&bigcore2_alert>;
|
||||
+ cooling-device =
|
||||
+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* sensor between the four A55 cores */
|
||||
+ little_core_thermal: littlecore-thermal {
|
||||
+ polling-delay-passive = <100>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 3>;
|
||||
+
|
||||
+ trips {
|
||||
+ littlecore_alert: littlecore-alert {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+
|
||||
+ littlecore_crit: littlecore-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&littlecore_alert>;
|
||||
+ cooling-device =
|
||||
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* sensor near the PD_CENTER power domain */
|
||||
+ center_thermal: center-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 4>;
|
||||
+
|
||||
+ trips {
|
||||
+ center_crit: center-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpu_thermal: gpu-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 5>;
|
||||
+
|
||||
+ trips {
|
||||
+ gpu_crit: gpu-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ npu_thermal: npu-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 6>;
|
||||
+
|
||||
+ trips {
|
||||
+ npu_crit: npu-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
tsadc: tsadc@fec00000 {
|
||||
compatible = "rockchip,rk3588-tsadc";
|
||||
reg = <0x0 0xfec00000 0x0 0x400>;
|
||||
@ -0,0 +1,50 @@
|
||||
From b78f87940a79321a444083aca46ac3e8e53d1a90 Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Mon, 17 Jun 2024 22:28:53 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add passive GPU cooling on RK3588
|
||||
|
||||
As the GPU support on RK3588 has been merged upstream, along with OPP
|
||||
values, add a corresponding cooling map for passive cooling using the GPU.
|
||||
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-3-c1f5f3267f1e@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 16 +++++++++++++++-
|
||||
1 file changed, 15 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -2493,17 +2493,31 @@
|
||||
};
|
||||
|
||||
gpu_thermal: gpu-thermal {
|
||||
- polling-delay-passive = <0>;
|
||||
+ polling-delay-passive = <100>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsadc 5>;
|
||||
|
||||
trips {
|
||||
+ gpu_alert: gpu-alert {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+
|
||||
gpu_crit: gpu-crit {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&gpu_alert>;
|
||||
+ cooling-device =
|
||||
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
npu_thermal: npu-thermal {
|
||||
@ -0,0 +1,205 @@
|
||||
From 276856db91b46eaa7a4c19226c096a9dc899a3e9 Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Mon, 17 Jun 2024 22:28:56 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588
|
||||
|
||||
By default the CPUs on RK3588 start up in a conservative performance
|
||||
mode. Add frequency and voltage mappings to the device tree to enable
|
||||
dynamic scaling via cpufreq.
|
||||
|
||||
OPP values are adapted from Radxa's downstream kernel for Rock 5B [1],
|
||||
stripping them down to the minimum frequency and voltage combinations
|
||||
as expected by the generic upstream cpufreq-dt driver, and also dropping
|
||||
those OPPs that don't differ in voltage but only in frequency (keeping
|
||||
the top frequency OPP in each case).
|
||||
|
||||
Note that this patch ignores voltage scaling for the CPU memory
|
||||
interface which the downstream kernel does through a custom cpufreq
|
||||
driver, and which is why the downstream version has two sets of voltage
|
||||
values for each OPP (the second one being meant for the memory
|
||||
interface supply regulator). This is done instead via regulator
|
||||
coupling between CPU and memory interface supplies on affected boards.
|
||||
|
||||
This has been tested on Rock 5B with u-boot 2023.11 compiled from
|
||||
Collabora's integration tree [2] with binary bl31 and appears to be
|
||||
stable both under active cooling and passive cooling (with throttling)
|
||||
|
||||
[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
[2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot
|
||||
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-6-c1f5f3267f1e@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 149 +++++++++++++++++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 1 +
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 +
|
||||
3 files changed, 151 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
|
||||
@@ -0,0 +1,149 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/ {
|
||||
+ cluster0_opp_table: opp-table-cluster0 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1008000000 {
|
||||
+ opp-hz = /bits/ 64 <1008000000>;
|
||||
+ opp-microvolt = <675000 675000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1200000000 {
|
||||
+ opp-hz = /bits/ 64 <1200000000>;
|
||||
+ opp-microvolt = <712500 712500 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <762500 762500 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ opp-suspend;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <850000 850000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <950000 950000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cluster1_opp_table: opp-table-cluster1 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1200000000 {
|
||||
+ opp-hz = /bits/ 64 <1200000000>;
|
||||
+ opp-microvolt = <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <725000 725000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <762500 762500 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <850000 850000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2016000000 {
|
||||
+ opp-hz = /bits/ 64 <2016000000>;
|
||||
+ opp-microvolt = <925000 925000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2208000000 {
|
||||
+ opp-hz = /bits/ 64 <2208000000>;
|
||||
+ opp-microvolt = <987500 987500 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2400000000 {
|
||||
+ opp-hz = /bits/ 64 <2400000000>;
|
||||
+ opp-microvolt = <1000000 1000000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cluster2_opp_table: opp-table-cluster2 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1200000000 {
|
||||
+ opp-hz = /bits/ 64 <1200000000>;
|
||||
+ opp-microvolt = <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <725000 725000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <762500 762500 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <850000 850000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2016000000 {
|
||||
+ opp-hz = /bits/ 64 <2016000000>;
|
||||
+ opp-microvolt = <925000 925000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2208000000 {
|
||||
+ opp-hz = /bits/ 64 <2208000000>;
|
||||
+ opp-microvolt = <987500 987500 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2400000000 {
|
||||
+ opp-hz = /bits/ 64 <2400000000>;
|
||||
+ opp-microvolt = <1000000 1000000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu_b0 {
|
||||
+ operating-points-v2 = <&cluster1_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b1 {
|
||||
+ operating-points-v2 = <&cluster1_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b2 {
|
||||
+ operating-points-v2 = <&cluster2_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b3 {
|
||||
+ operating-points-v2 = <&cluster2_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l0 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l1 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l2 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l3 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
||||
@@ -5,3 +5,4 @@
|
||||
*/
|
||||
|
||||
#include "rk3588-extra.dtsi"
|
||||
+#include "rk3588-opp.dtsi"
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -5,3 +5,4 @@
|
||||
*/
|
||||
|
||||
#include "rk3588-base.dtsi"
|
||||
+#include "rk3588-opp.dtsi"
|
||||
@ -0,0 +1,140 @@
|
||||
From 667885a6865832eb0678c7e02e47a3392f177ecb Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Mon, 17 Jun 2024 22:28:57 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588j
|
||||
|
||||
RK3588j is the 'industrial' variant of RK3588, and it uses a different
|
||||
set of OPPs both in terms of allowed frequencies and in terms of
|
||||
applicable voltages at each frequency setpoint.
|
||||
|
||||
Add the OPPs that apply to RK3588j (and apparently RK3588m too) to
|
||||
enable dynamic CPU frequency scaling.
|
||||
|
||||
OPP values are derived from Rockchip downstream sources [1] by taking
|
||||
only those OPPs which have the highest frequency for a given voltage
|
||||
level and dropping the rest (if they are included, the kernel complains
|
||||
at boot time about them being inefficient)
|
||||
|
||||
[1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-7-c1f5f3267f1e@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 108 ++++++++++++++++++++++
|
||||
1 file changed, 108 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
|
||||
@@ -5,3 +5,111 @@
|
||||
*/
|
||||
|
||||
#include "rk3588-extra.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ cluster0_opp_table: opp-table-cluster0 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <750000 750000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ opp-suspend;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <887500 887500 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1704000000 {
|
||||
+ opp-hz = /bits/ 64 <1704000000>;
|
||||
+ opp-microvolt = <937500 937500 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cluster1_opp_table: opp-table-cluster1 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <750000 750000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <787500 787500 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <875000 875000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2016000000 {
|
||||
+ opp-hz = /bits/ 64 <2016000000>;
|
||||
+ opp-microvolt = <950000 950000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cluster2_opp_table: opp-table-cluster2 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <750000 750000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <787500 787500 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <875000 875000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2016000000 {
|
||||
+ opp-hz = /bits/ 64 <2016000000>;
|
||||
+ opp-microvolt = <950000 950000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu_b0 {
|
||||
+ operating-points-v2 = <&cluster1_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b1 {
|
||||
+ operating-points-v2 = <&cluster1_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b2 {
|
||||
+ operating-points-v2 = <&cluster2_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b3 {
|
||||
+ operating-points-v2 = <&cluster2_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l0 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l1 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l2 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l3 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
@ -0,0 +1,177 @@
|
||||
From a7b2070505a2a09ea65fa0c8c480c97f62d1978d Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Mon, 17 Jun 2024 22:28:58 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: Split GPU OPPs of RK3588 and RK3588j
|
||||
|
||||
RK3588j uses a different set of OPPs for its GPU, both in terms of
|
||||
allowed frequencies and in terms of voltages.
|
||||
|
||||
Move the GPU OPPs table into per-variant .dtsi files to accommodate
|
||||
for this difference.
|
||||
|
||||
The table for RK3588j is adapted from Rockchip downstream sources [1],
|
||||
while RK3588 one is moved verbatim into the per-variant .dtsi file.
|
||||
The values provided for RK3588 in the downstream sources match those
|
||||
in the original commit.
|
||||
|
||||
[1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
|
||||
Fixes: 6fca4edb93d3 ("arm64: dts: rockchip: Add rk3588 GPU node")
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-8-c1f5f3267f1e@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 38 -----------------
|
||||
arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 41 +++++++++++++++++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 33 +++++++++++++++
|
||||
3 files changed, 74 insertions(+), 38 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -451,46 +451,8 @@
|
||||
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
- operating-points-v2 = <&gpu_opp_table>;
|
||||
power-domains = <&power RK3588_PD_GPU>;
|
||||
status = "disabled";
|
||||
-
|
||||
- gpu_opp_table: opp-table {
|
||||
- compatible = "operating-points-v2";
|
||||
-
|
||||
- opp-300000000 {
|
||||
- opp-hz = /bits/ 64 <300000000>;
|
||||
- opp-microvolt = <675000 675000 850000>;
|
||||
- };
|
||||
- opp-400000000 {
|
||||
- opp-hz = /bits/ 64 <400000000>;
|
||||
- opp-microvolt = <675000 675000 850000>;
|
||||
- };
|
||||
- opp-500000000 {
|
||||
- opp-hz = /bits/ 64 <500000000>;
|
||||
- opp-microvolt = <675000 675000 850000>;
|
||||
- };
|
||||
- opp-600000000 {
|
||||
- opp-hz = /bits/ 64 <600000000>;
|
||||
- opp-microvolt = <675000 675000 850000>;
|
||||
- };
|
||||
- opp-700000000 {
|
||||
- opp-hz = /bits/ 64 <700000000>;
|
||||
- opp-microvolt = <700000 700000 850000>;
|
||||
- };
|
||||
- opp-800000000 {
|
||||
- opp-hz = /bits/ 64 <800000000>;
|
||||
- opp-microvolt = <750000 750000 850000>;
|
||||
- };
|
||||
- opp-900000000 {
|
||||
- opp-hz = /bits/ 64 <900000000>;
|
||||
- opp-microvolt = <800000 800000 850000>;
|
||||
- };
|
||||
- opp-1000000000 {
|
||||
- opp-hz = /bits/ 64 <1000000000>;
|
||||
- opp-microvolt = <850000 850000 850000>;
|
||||
- };
|
||||
- };
|
||||
};
|
||||
|
||||
usb_host0_xhci: usb@fc000000 {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
|
||||
@@ -114,6 +114,43 @@
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ gpu_opp_table: opp-table {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ opp-300000000 {
|
||||
+ opp-hz = /bits/ 64 <300000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-400000000 {
|
||||
+ opp-hz = /bits/ 64 <400000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-500000000 {
|
||||
+ opp-hz = /bits/ 64 <500000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-700000000 {
|
||||
+ opp-hz = /bits/ 64 <700000000>;
|
||||
+ opp-microvolt = <700000 700000 850000>;
|
||||
+ };
|
||||
+ opp-800000000 {
|
||||
+ opp-hz = /bits/ 64 <800000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-900000000 {
|
||||
+ opp-hz = /bits/ 64 <900000000>;
|
||||
+ opp-microvolt = <800000 800000 850000>;
|
||||
+ };
|
||||
+ opp-1000000000 {
|
||||
+ opp-hz = /bits/ 64 <1000000000>;
|
||||
+ opp-microvolt = <850000 850000 850000>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
@@ -147,3 +184,7 @@
|
||||
&cpu_l3 {
|
||||
operating-points-v2 = <&cluster0_opp_table>;
|
||||
};
|
||||
+
|
||||
+&gpu {
|
||||
+ operating-points-v2 = <&gpu_opp_table>;
|
||||
+};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
|
||||
@@ -80,6 +80,35 @@
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ gpu_opp_table: opp-table {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ opp-300000000 {
|
||||
+ opp-hz = /bits/ 64 <300000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-400000000 {
|
||||
+ opp-hz = /bits/ 64 <400000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-500000000 {
|
||||
+ opp-hz = /bits/ 64 <500000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-700000000 {
|
||||
+ opp-hz = /bits/ 64 <700000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-850000000 {
|
||||
+ opp-hz = /bits/ 64 <800000000>;
|
||||
+ opp-microvolt = <787500 787500 850000>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
@@ -113,3 +142,7 @@
|
||||
&cpu_l3 {
|
||||
operating-points-v2 = <&cluster0_opp_table>;
|
||||
};
|
||||
+
|
||||
+&gpu {
|
||||
+ operating-points-v2 = <&gpu_opp_table>;
|
||||
+};
|
||||
@ -0,0 +1,45 @@
|
||||
From 00224650dd45e166ea6eb1593f5f064583963ccf Mon Sep 17 00:00:00 2001
|
||||
From: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Date: Sun, 23 Jun 2024 11:33:28 +0900
|
||||
Subject: [PATCH] arm64: dts: rockchip: add (but disabled) SFC node for Radxa
|
||||
ROCK 5A
|
||||
|
||||
This commit adds SFC node for Radxa ROCK 5A.
|
||||
|
||||
since sdhci and sfc on RK3588s share pins(i.e. exclusive), it cannot
|
||||
be enabled both nodes at the same time. so status = "okay" is omitted
|
||||
here.
|
||||
|
||||
you may be able to enable sfc (and disable sdhci) by fdt overlay.
|
||||
|
||||
SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.
|
||||
|
||||
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Link: https://lore.kernel.org/r/20240623023329.1044-2-naoki@radxa.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 13 +++++++++++++
|
||||
1 file changed, 13 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
@@ -376,6 +376,19 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&sfc {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&fspim0_pins>;
|
||||
+
|
||||
+ flash@0 {
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <104000000>;
|
||||
+ spi-rx-bus-width = <4>;
|
||||
+ spi-tx-bus-width = <1>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&spi2 {
|
||||
status = "okay";
|
||||
assigned-clocks = <&cru CLK_SPI2>;
|
||||
@ -0,0 +1,67 @@
|
||||
From 4a152231b050590af771fa3cc8462ed08b691a24 Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Mon, 17 Jun 2024 22:28:54 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: enable automatic fan control on Rock 5B
|
||||
|
||||
This links the PWM fan on Radxa Rock 5B as an active cooling device
|
||||
managed automatically by the thermal subsystem, with a target SoC
|
||||
temperature of 65C and a minimum-spin interval from 55C to 65C to
|
||||
ensure airflow when the system gets warm
|
||||
|
||||
Helped-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-4-c1f5f3267f1e@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588-rock-5b.dts | 32 ++++++++++++++++++-
|
||||
1 file changed, 31 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -52,7 +52,7 @@
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
- cooling-levels = <0 95 145 195 255>;
|
||||
+ cooling-levels = <0 120 150 180 210 240 255>;
|
||||
fan-supply = <&vcc5v0_sys>;
|
||||
pwms = <&pwm1 0 50000 0>;
|
||||
#cooling-cells = <2>;
|
||||
@@ -278,6 +278,36 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+&package_thermal {
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ trips {
|
||||
+ package_fan0: package-fan0 {
|
||||
+ temperature = <55000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "active";
|
||||
+ };
|
||||
+
|
||||
+ package_fan1: package-fan1 {
|
||||
+ temperature = <65000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "active";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map1 {
|
||||
+ trip = <&package_fan0>;
|
||||
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
|
||||
+ };
|
||||
+
|
||||
+ map2 {
|
||||
+ trip = <&package_fan1>;
|
||||
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
|
||||
&pcie2x1l0 {
|
||||
pinctrl-names = "default";
|
||||
@ -0,0 +1,39 @@
|
||||
From 9204a7ecca96403ee3d61c14cb9eb87ec89b0fcd Mon Sep 17 00:00:00 2001
|
||||
From: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Date: Sun, 23 Jun 2024 11:33:27 +0900
|
||||
Subject: [PATCH] arm64: dts: rockchip: add SFC support for Radxa ROCK 5B
|
||||
|
||||
This commit adds support for SPI NOR flash on Radxa ROCK 5B.
|
||||
|
||||
SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.
|
||||
|
||||
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Link: https://lore.kernel.org/r/20240623023329.1044-1-naoki@radxa.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 14 ++++++++++++++
|
||||
1 file changed, 14 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -442,6 +442,20 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&sfc {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&fspim2_pins>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ flash@0 {
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <104000000>;
|
||||
+ spi-rx-bus-width = <4>;
|
||||
+ spi-tx-bus-width = <1>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&uart6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>;
|
||||
@ -35,7 +35,7 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
no-sdio;
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -383,7 +383,6 @@
|
||||
@@ -413,7 +413,6 @@
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
|
||||
@ -0,0 +1,66 @@
|
||||
From 2f8064b9c4a012b4d4e8383818f13b682b6c156a Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Mon, 17 Jun 2024 22:28:52 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: enable thermal management on all RK3588
|
||||
boards
|
||||
|
||||
This enables the on-chip thermal monitoring sensor (TSADC) on all
|
||||
RK3588(s) boards that don't have it enabled yet. It provides temperature
|
||||
monitoring for the SoC and emergency thermal shutdowns, and is thus
|
||||
important to have in place before CPU DVFS is enabled, as high CPU
|
||||
operating performance points can overheat the chip quickly in the
|
||||
absence of thermal management.
|
||||
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-2-c1f5f3267f1e@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 4 ++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 ++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 4 ++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 4 ++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts | 4 ++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 4 ++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 4 ++++
|
||||
8 files changed, 32 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
|
||||
@@ -807,6 +807,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&tsadc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -786,6 +786,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&tsadc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2m0_xfer>;
|
||||
status = "okay";
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
@@ -709,6 +709,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&tsadc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -57,7 +57,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
status = "okay";
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -375,8 +375,7 @@
|
||||
@@ -405,8 +405,7 @@
|
||||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
@ -67,7 +67,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -388,7 +387,7 @@
|
||||
@@ -418,7 +417,7 @@
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
|
||||
@ -1,712 +0,0 @@
|
||||
From 8baebef8be9691a28f8efa284dfce9a5b9395130 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 18 Aug 2022 14:21:30 +0200
|
||||
Subject: [PATCH] cpufreq: rockchip: Introduce driver for rk3588
|
||||
|
||||
This is a heavily modified port from the downstream driver.
|
||||
Downstream used it for multiple rockchip generations, while
|
||||
upstream just used the generic cpufreq-dt driver so far. For
|
||||
rk3588 this is no longer good enough, since two regulators
|
||||
need to be controlled.
|
||||
|
||||
Also during shutdown the correct frequency needs to be configured
|
||||
for the big CPU cores to avoid a system hang when firmware tries
|
||||
to bring them up at reboot time.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
---
|
||||
drivers/cpufreq/Kconfig.arm | 10 +
|
||||
drivers/cpufreq/Makefile | 1 +
|
||||
drivers/cpufreq/cpufreq-dt-platdev.c | 2 +
|
||||
drivers/cpufreq/rockchip-cpufreq.c | 645 +++++++++++++++++++++++++++
|
||||
4 files changed, 658 insertions(+)
|
||||
create mode 100644 drivers/cpufreq/rockchip-cpufreq.c
|
||||
|
||||
--- a/drivers/cpufreq/Kconfig.arm
|
||||
+++ b/drivers/cpufreq/Kconfig.arm
|
||||
@@ -190,6 +190,16 @@ config ARM_RASPBERRYPI_CPUFREQ
|
||||
|
||||
If in doubt, say N.
|
||||
|
||||
+config ARM_ROCKCHIP_CPUFREQ
|
||||
+ tristate "Rockchip CPUfreq driver"
|
||||
+ depends on ARCH_ROCKCHIP && CPUFREQ_DT
|
||||
+ select PM_OPP
|
||||
+ help
|
||||
+ This adds the CPUFreq driver support for Rockchip SoCs,
|
||||
+ based on cpufreq-dt.
|
||||
+
|
||||
+ If in doubt, say N.
|
||||
+
|
||||
config ARM_S3C64XX_CPUFREQ
|
||||
bool "Samsung S3C64XX"
|
||||
depends on CPU_S3C6410
|
||||
--- a/drivers/cpufreq/Makefile
|
||||
+++ b/drivers/cpufreq/Makefile
|
||||
@@ -71,6 +71,7 @@ obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq
|
||||
obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o
|
||||
obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o
|
||||
obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) += raspberrypi-cpufreq.o
|
||||
+obj-$(CONFIG_ARM_ROCKCHIP_CPUFREQ) += rockchip-cpufreq.o
|
||||
obj-$(CONFIG_ARM_S3C64XX_CPUFREQ) += s3c64xx-cpufreq.o
|
||||
obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o
|
||||
obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o
|
||||
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
|
||||
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
|
||||
@@ -166,6 +166,8 @@ static const struct of_device_id blockli
|
||||
{ .compatible = "qcom,sm8450", },
|
||||
{ .compatible = "qcom,sm8550", },
|
||||
|
||||
+ { .compatible = "rockchip,rk3588", },
|
||||
+
|
||||
{ .compatible = "st,stih407", },
|
||||
{ .compatible = "st,stih410", },
|
||||
{ .compatible = "st,stih418", },
|
||||
--- /dev/null
|
||||
+++ b/drivers/cpufreq/rockchip-cpufreq.c
|
||||
@@ -0,0 +1,645 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-only
|
||||
+/*
|
||||
+ * Rockchip CPUFreq Driver. This is similar to the generic DT
|
||||
+ * cpufreq driver, but handles the following platform specific
|
||||
+ * quirks:
|
||||
+ *
|
||||
+ * * support for two regulators - one for the CPU core and one
|
||||
+ * for the memory interface
|
||||
+ * * reboot handler to setup the reboot frequency
|
||||
+ * * handling of read margin registers
|
||||
+ *
|
||||
+ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
|
||||
+ * Copyright (C) 2023 Collabora Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/cpu.h>
|
||||
+#include <linux/cpufreq.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_address.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/pm_opp.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/reboot.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/regulator/consumer.h>
|
||||
+
|
||||
+#include "cpufreq-dt.h"
|
||||
+
|
||||
+#define RK3588_MEMCFG_HSSPRF_LOW 0x20
|
||||
+#define RK3588_MEMCFG_HSDPRF_LOW 0x28
|
||||
+#define RK3588_MEMCFG_HSDPRF_HIGH 0x2c
|
||||
+#define RK3588_CPU_CTRL 0x30
|
||||
+
|
||||
+#define VOLT_RM_TABLE_END ~1
|
||||
+
|
||||
+static struct platform_device *cpufreq_pdev;
|
||||
+static LIST_HEAD(priv_list);
|
||||
+
|
||||
+struct volt_rm_table {
|
||||
+ uint32_t volt;
|
||||
+ uint32_t rm;
|
||||
+};
|
||||
+
|
||||
+struct rockchip_opp_info {
|
||||
+ const struct rockchip_opp_data *data;
|
||||
+ struct volt_rm_table *volt_rm_tbl;
|
||||
+ struct regmap *grf;
|
||||
+ u32 current_rm;
|
||||
+ u32 reboot_freq;
|
||||
+};
|
||||
+
|
||||
+struct private_data {
|
||||
+ struct list_head node;
|
||||
+
|
||||
+ cpumask_var_t cpus;
|
||||
+ struct device *cpu_dev;
|
||||
+ struct cpufreq_frequency_table *freq_table;
|
||||
+};
|
||||
+
|
||||
+struct rockchip_opp_data {
|
||||
+ int (*set_read_margin)(struct device *dev, struct rockchip_opp_info *opp_info,
|
||||
+ unsigned long volt);
|
||||
+};
|
||||
+
|
||||
+struct cluster_info {
|
||||
+ struct list_head list_head;
|
||||
+ struct rockchip_opp_info opp_info;
|
||||
+ cpumask_t cpus;
|
||||
+};
|
||||
+static LIST_HEAD(cluster_info_list);
|
||||
+
|
||||
+static int rk3588_cpu_set_read_margin(struct device *dev, struct rockchip_opp_info *opp_info,
|
||||
+ unsigned long volt)
|
||||
+{
|
||||
+ bool is_found = false;
|
||||
+ u32 rm;
|
||||
+ int i;
|
||||
+
|
||||
+ if (!opp_info->volt_rm_tbl)
|
||||
+ return 0;
|
||||
+
|
||||
+ for (i = 0; opp_info->volt_rm_tbl[i].rm != VOLT_RM_TABLE_END; i++) {
|
||||
+ if (volt >= opp_info->volt_rm_tbl[i].volt) {
|
||||
+ rm = opp_info->volt_rm_tbl[i].rm;
|
||||
+ is_found = true;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (!is_found)
|
||||
+ return 0;
|
||||
+ if (rm == opp_info->current_rm)
|
||||
+ return 0;
|
||||
+ if (!opp_info->grf)
|
||||
+ return 0;
|
||||
+
|
||||
+ dev_dbg(dev, "set rm to %d\n", rm);
|
||||
+ regmap_write(opp_info->grf, RK3588_MEMCFG_HSSPRF_LOW, 0x001c0000 | (rm << 2));
|
||||
+ regmap_write(opp_info->grf, RK3588_MEMCFG_HSDPRF_LOW, 0x003c0000 | (rm << 2));
|
||||
+ regmap_write(opp_info->grf, RK3588_MEMCFG_HSDPRF_HIGH, 0x003c0000 | (rm << 2));
|
||||
+ regmap_write(opp_info->grf, RK3588_CPU_CTRL, 0x00200020);
|
||||
+ udelay(1);
|
||||
+ regmap_write(opp_info->grf, RK3588_CPU_CTRL, 0x00200000);
|
||||
+
|
||||
+ opp_info->current_rm = rm;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct rockchip_opp_data rk3588_cpu_opp_data = {
|
||||
+ .set_read_margin = rk3588_cpu_set_read_margin,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id rockchip_cpufreq_of_match[] = {
|
||||
+ {
|
||||
+ .compatible = "rockchip,rk3588",
|
||||
+ .data = (void *)&rk3588_cpu_opp_data,
|
||||
+ },
|
||||
+ {},
|
||||
+};
|
||||
+
|
||||
+static struct cluster_info *rockchip_cluster_info_lookup(int cpu)
|
||||
+{
|
||||
+ struct cluster_info *cluster;
|
||||
+
|
||||
+ list_for_each_entry(cluster, &cluster_info_list, list_head) {
|
||||
+ if (cpumask_test_cpu(cpu, &cluster->cpus))
|
||||
+ return cluster;
|
||||
+ }
|
||||
+
|
||||
+ return NULL;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_cpufreq_set_volt(struct device *dev,
|
||||
+ struct regulator *reg,
|
||||
+ struct dev_pm_opp_supply *supply)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min,
|
||||
+ supply->u_volt, supply->u_volt_max);
|
||||
+ if (ret)
|
||||
+ dev_err(dev, "%s: failed to set voltage (%lu %lu %lu uV): %d\n",
|
||||
+ __func__, supply->u_volt_min, supply->u_volt,
|
||||
+ supply->u_volt_max, ret);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_cpufreq_set_read_margin(struct device *dev,
|
||||
+ struct rockchip_opp_info *opp_info,
|
||||
+ unsigned long volt)
|
||||
+{
|
||||
+ if (opp_info->data && opp_info->data->set_read_margin) {
|
||||
+ opp_info->data->set_read_margin(dev, opp_info, volt);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk_opp_config_regulators(struct device *dev,
|
||||
+ struct dev_pm_opp *old_opp, struct dev_pm_opp *new_opp,
|
||||
+ struct regulator **regulators, unsigned int count)
|
||||
+{
|
||||
+ struct dev_pm_opp_supply old_supplies[2];
|
||||
+ struct dev_pm_opp_supply new_supplies[2];
|
||||
+ struct regulator *vdd_reg = regulators[0];
|
||||
+ struct regulator *mem_reg = regulators[1];
|
||||
+ struct rockchip_opp_info *opp_info;
|
||||
+ struct cluster_info *cluster;
|
||||
+ int ret = 0;
|
||||
+ unsigned long old_freq = dev_pm_opp_get_freq(old_opp);
|
||||
+ unsigned long new_freq = dev_pm_opp_get_freq(new_opp);
|
||||
+
|
||||
+ /* We must have two regulators here */
|
||||
+ WARN_ON(count != 2);
|
||||
+
|
||||
+ ret = dev_pm_opp_get_supplies(old_opp, old_supplies);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = dev_pm_opp_get_supplies(new_opp, new_supplies);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ cluster = rockchip_cluster_info_lookup(dev->id);
|
||||
+ if (!cluster)
|
||||
+ return -EINVAL;
|
||||
+ opp_info = &cluster->opp_info;
|
||||
+
|
||||
+ if (new_freq >= old_freq) {
|
||||
+ ret = rockchip_cpufreq_set_volt(dev, mem_reg, &new_supplies[1]);
|
||||
+ if (ret)
|
||||
+ goto error;
|
||||
+ ret = rockchip_cpufreq_set_volt(dev, vdd_reg, &new_supplies[0]);
|
||||
+ if (ret)
|
||||
+ goto error;
|
||||
+ rockchip_cpufreq_set_read_margin(dev, opp_info, new_supplies[0].u_volt);
|
||||
+ } else {
|
||||
+ rockchip_cpufreq_set_read_margin(dev, opp_info, new_supplies[0].u_volt);
|
||||
+ ret = rockchip_cpufreq_set_volt(dev, vdd_reg, &new_supplies[0]);
|
||||
+ if (ret)
|
||||
+ goto error;
|
||||
+ ret = rockchip_cpufreq_set_volt(dev, mem_reg, &new_supplies[1]);
|
||||
+ if (ret)
|
||||
+ goto error;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+error:
|
||||
+ rockchip_cpufreq_set_read_margin(dev, opp_info, old_supplies[0].u_volt);
|
||||
+ rockchip_cpufreq_set_volt(dev, mem_reg, &old_supplies[1]);
|
||||
+ rockchip_cpufreq_set_volt(dev, vdd_reg, &old_supplies[0]);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static void rockchip_get_opp_data(const struct of_device_id *matches,
|
||||
+ struct rockchip_opp_info *info)
|
||||
+{
|
||||
+ const struct of_device_id *match;
|
||||
+ struct device_node *node;
|
||||
+
|
||||
+ node = of_find_node_by_path("/");
|
||||
+ match = of_match_node(matches, node);
|
||||
+ if (match && match->data)
|
||||
+ info->data = match->data;
|
||||
+ of_node_put(node);
|
||||
+}
|
||||
+
|
||||
+static int rockchip_get_volt_rm_table(struct device *dev, struct device_node *np,
|
||||
+ char *porp_name, struct volt_rm_table **table)
|
||||
+{
|
||||
+ struct volt_rm_table *rm_table;
|
||||
+ const struct property *prop;
|
||||
+ int count, i;
|
||||
+
|
||||
+ prop = of_find_property(np, porp_name, NULL);
|
||||
+ if (!prop)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ if (!prop->value)
|
||||
+ return -ENODATA;
|
||||
+
|
||||
+ count = of_property_count_u32_elems(np, porp_name);
|
||||
+ if (count < 0)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ if (count % 2)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ rm_table = devm_kzalloc(dev, sizeof(*rm_table) * (count / 2 + 1),
|
||||
+ GFP_KERNEL);
|
||||
+ if (!rm_table)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ for (i = 0; i < count / 2; i++) {
|
||||
+ of_property_read_u32_index(np, porp_name, 2 * i,
|
||||
+ &rm_table[i].volt);
|
||||
+ of_property_read_u32_index(np, porp_name, 2 * i + 1,
|
||||
+ &rm_table[i].rm);
|
||||
+ }
|
||||
+
|
||||
+ rm_table[i].volt = 0;
|
||||
+ rm_table[i].rm = VOLT_RM_TABLE_END;
|
||||
+
|
||||
+ *table = rm_table;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_cpufreq_reboot(struct notifier_block *notifier, unsigned long event, void *cmd)
|
||||
+{
|
||||
+ struct cluster_info *cluster;
|
||||
+ struct device *dev;
|
||||
+ int freq, ret, cpu;
|
||||
+
|
||||
+ if (event != SYS_RESTART)
|
||||
+ return NOTIFY_DONE;
|
||||
+
|
||||
+ for_each_possible_cpu(cpu) {
|
||||
+ cluster = rockchip_cluster_info_lookup(cpu);
|
||||
+ if (!cluster)
|
||||
+ continue;
|
||||
+
|
||||
+ dev = get_cpu_device(cpu);
|
||||
+ if (!dev)
|
||||
+ continue;
|
||||
+
|
||||
+ freq = cluster->opp_info.reboot_freq;
|
||||
+
|
||||
+ if (freq) {
|
||||
+ ret = dev_pm_opp_set_rate(dev, freq);
|
||||
+ if (ret)
|
||||
+ dev_err(dev, "Failed setting reboot freq for cpu %d to %d: %d\n",
|
||||
+ cpu, freq, ret);
|
||||
+ dev_pm_opp_remove_table(dev);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return NOTIFY_DONE;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_cpufreq_cluster_init(int cpu, struct cluster_info *cluster)
|
||||
+{
|
||||
+ struct rockchip_opp_info *opp_info = &cluster->opp_info;
|
||||
+ int reg_table_token = -EINVAL;
|
||||
+ int opp_table_token = -EINVAL;
|
||||
+ struct device_node *np;
|
||||
+ struct device *dev;
|
||||
+ const char * const reg_names[] = { "cpu", "mem", NULL };
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ dev = get_cpu_device(cpu);
|
||||
+ if (!dev)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ if (!of_find_property(dev->of_node, "cpu-supply", NULL))
|
||||
+ return -ENOENT;
|
||||
+
|
||||
+ np = of_parse_phandle(dev->of_node, "operating-points-v2", 0);
|
||||
+ if (!np) {
|
||||
+ dev_warn(dev, "OPP-v2 not supported\n");
|
||||
+ return -ENOENT;
|
||||
+ }
|
||||
+
|
||||
+ reg_table_token = dev_pm_opp_set_regulators(dev, reg_names);
|
||||
+ if (reg_table_token < 0) {
|
||||
+ ret = reg_table_token;
|
||||
+ dev_err_probe(dev, ret, "Failed to set opp regulators\n");
|
||||
+ goto np_err;
|
||||
+ }
|
||||
+
|
||||
+ ret = dev_pm_opp_of_get_sharing_cpus(dev, &cluster->cpus);
|
||||
+ if (ret) {
|
||||
+ dev_err_probe(dev, ret, "Failed to get sharing cpus\n");
|
||||
+ goto np_err;
|
||||
+ }
|
||||
+
|
||||
+ rockchip_get_opp_data(rockchip_cpufreq_of_match, opp_info);
|
||||
+ if (opp_info->data && opp_info->data->set_read_margin) {
|
||||
+ opp_info->current_rm = UINT_MAX;
|
||||
+ opp_info->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
|
||||
+ if (IS_ERR(opp_info->grf))
|
||||
+ opp_info->grf = NULL;
|
||||
+ rockchip_get_volt_rm_table(dev, np, "rockchip,volt-mem-read-margin", &opp_info->volt_rm_tbl);
|
||||
+
|
||||
+ of_property_read_u32(np, "rockchip,reboot-freq", &opp_info->reboot_freq);
|
||||
+ }
|
||||
+
|
||||
+ opp_table_token = dev_pm_opp_set_config_regulators(dev, rk_opp_config_regulators);
|
||||
+ if (opp_table_token < 0) {
|
||||
+ ret = opp_table_token;
|
||||
+ dev_err(dev, "Failed to set opp config regulators\n");
|
||||
+ goto reg_opp_table;
|
||||
+ }
|
||||
+
|
||||
+ of_node_put(np);
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+reg_opp_table:
|
||||
+ if (reg_table_token >= 0)
|
||||
+ dev_pm_opp_put_regulators(reg_table_token);
|
||||
+np_err:
|
||||
+ of_node_put(np);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static struct notifier_block rockchip_cpufreq_reboot_notifier = {
|
||||
+ .notifier_call = rockchip_cpufreq_reboot,
|
||||
+ .priority = 0,
|
||||
+};
|
||||
+
|
||||
+static struct freq_attr *cpufreq_rockchip_attr[] = {
|
||||
+ &cpufreq_freq_attr_scaling_available_freqs,
|
||||
+ NULL,
|
||||
+};
|
||||
+
|
||||
+static int cpufreq_online(struct cpufreq_policy *policy)
|
||||
+{
|
||||
+ /* We did light-weight tear down earlier, nothing to do here */
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int cpufreq_offline(struct cpufreq_policy *policy)
|
||||
+{
|
||||
+ /*
|
||||
+ * Preserve policy->driver_data and don't free resources on light-weight
|
||||
+ * tear down.
|
||||
+ */
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct private_data *rockchip_cpufreq_find_data(int cpu)
|
||||
+{
|
||||
+ struct private_data *priv;
|
||||
+
|
||||
+ list_for_each_entry(priv, &priv_list, node) {
|
||||
+ if (cpumask_test_cpu(cpu, priv->cpus))
|
||||
+ return priv;
|
||||
+ }
|
||||
+
|
||||
+ return NULL;
|
||||
+}
|
||||
+
|
||||
+static int cpufreq_init(struct cpufreq_policy *policy)
|
||||
+{
|
||||
+ struct private_data *priv;
|
||||
+ struct device *cpu_dev;
|
||||
+ struct clk *cpu_clk;
|
||||
+ unsigned int transition_latency;
|
||||
+ int ret;
|
||||
+
|
||||
+ priv = rockchip_cpufreq_find_data(policy->cpu);
|
||||
+ if (!priv) {
|
||||
+ pr_err("failed to find data for cpu%d\n", policy->cpu);
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ cpu_dev = priv->cpu_dev;
|
||||
+
|
||||
+ cpu_clk = clk_get(cpu_dev, NULL);
|
||||
+ if (IS_ERR(cpu_clk)) {
|
||||
+ ret = PTR_ERR(cpu_clk);
|
||||
+ dev_err(cpu_dev, "%s: failed to get clk: %d\n", __func__, ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev);
|
||||
+ if (!transition_latency)
|
||||
+ transition_latency = CPUFREQ_ETERNAL;
|
||||
+
|
||||
+ cpumask_copy(policy->cpus, priv->cpus);
|
||||
+ policy->driver_data = priv;
|
||||
+ policy->clk = cpu_clk;
|
||||
+ policy->freq_table = priv->freq_table;
|
||||
+ policy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu_dev) / 1000;
|
||||
+ policy->cpuinfo.transition_latency = transition_latency;
|
||||
+ policy->dvfs_possible_from_any_cpu = true;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int cpufreq_exit(struct cpufreq_policy *policy)
|
||||
+{
|
||||
+ clk_put(policy->clk);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int set_target(struct cpufreq_policy *policy, unsigned int index)
|
||||
+{
|
||||
+ struct private_data *priv = policy->driver_data;
|
||||
+ unsigned long freq = policy->freq_table[index].frequency;
|
||||
+
|
||||
+ return dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000);
|
||||
+}
|
||||
+
|
||||
+static struct cpufreq_driver rockchip_cpufreq_driver = {
|
||||
+ .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
|
||||
+ CPUFREQ_IS_COOLING_DEV |
|
||||
+ CPUFREQ_HAVE_GOVERNOR_PER_POLICY,
|
||||
+ .verify = cpufreq_generic_frequency_table_verify,
|
||||
+ .target_index = set_target,
|
||||
+ .get = cpufreq_generic_get,
|
||||
+ .init = cpufreq_init,
|
||||
+ .exit = cpufreq_exit,
|
||||
+ .online = cpufreq_online,
|
||||
+ .offline = cpufreq_offline,
|
||||
+ .register_em = cpufreq_register_em_with_opp,
|
||||
+ .name = "rockchip-cpufreq",
|
||||
+ .attr = cpufreq_rockchip_attr,
|
||||
+ .suspend = cpufreq_generic_suspend,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_cpufreq_init(struct device *dev, int cpu)
|
||||
+{
|
||||
+ struct private_data *priv;
|
||||
+ struct device *cpu_dev;
|
||||
+ int ret;
|
||||
+
|
||||
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ if (!alloc_cpumask_var(&priv->cpus, GFP_KERNEL))
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ cpumask_set_cpu(cpu, priv->cpus);
|
||||
+
|
||||
+ cpu_dev = get_cpu_device(cpu);
|
||||
+ if (!cpu_dev)
|
||||
+ return -EPROBE_DEFER;
|
||||
+ priv->cpu_dev = cpu_dev;
|
||||
+
|
||||
+ ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, priv->cpus);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = dev_pm_opp_of_cpumask_add_table(priv->cpus);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = dev_pm_opp_get_opp_count(cpu_dev);
|
||||
+ if (ret <= 0)
|
||||
+ return dev_err_probe(cpu_dev, -ENODEV, "OPP table can't be empty\n");
|
||||
+
|
||||
+ ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &priv->freq_table);
|
||||
+ if (ret)
|
||||
+ return dev_err_probe(cpu_dev, ret, "failed to init cpufreq table\n");
|
||||
+
|
||||
+ list_add(&priv->node, &priv_list);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void rockchip_cpufreq_free_list(void *data)
|
||||
+{
|
||||
+ struct cluster_info *cluster, *pos;
|
||||
+
|
||||
+ list_for_each_entry_safe(cluster, pos, &cluster_info_list, list_head) {
|
||||
+ list_del(&cluster->list_head);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int rockchip_cpufreq_init_list(struct device *dev)
|
||||
+{
|
||||
+ struct cluster_info *cluster;
|
||||
+ int cpu, ret;
|
||||
+
|
||||
+ for_each_possible_cpu(cpu) {
|
||||
+ cluster = rockchip_cluster_info_lookup(cpu);
|
||||
+ if (cluster)
|
||||
+ continue;
|
||||
+
|
||||
+ cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL);
|
||||
+ if (!cluster) {
|
||||
+ ret = -ENOMEM;
|
||||
+ goto release_cluster_info;
|
||||
+ }
|
||||
+
|
||||
+ ret = rockchip_cpufreq_cluster_init(cpu, cluster);
|
||||
+ if (ret) {
|
||||
+ dev_err_probe(dev, ret, "Failed to initialize dvfs info cpu%d\n", cpu);
|
||||
+ goto release_cluster_info;
|
||||
+ }
|
||||
+ list_add(&cluster->list_head, &cluster_info_list);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+release_cluster_info:
|
||||
+ rockchip_cpufreq_free_list(NULL);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static void rockchip_cpufreq_unregister(void *data)
|
||||
+{
|
||||
+ cpufreq_unregister_driver(&rockchip_cpufreq_driver);
|
||||
+}
|
||||
+
|
||||
+static int rockchip_cpufreq_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ int ret, cpu;
|
||||
+
|
||||
+ ret = rockchip_cpufreq_init_list(&pdev->dev);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = devm_add_action_or_reset(&pdev->dev, rockchip_cpufreq_free_list, NULL);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = devm_register_reboot_notifier(&pdev->dev, &rockchip_cpufreq_reboot_notifier);
|
||||
+ if (ret)
|
||||
+ return dev_err_probe(&pdev->dev, ret, "Failed to register reboot handler\n");
|
||||
+
|
||||
+ for_each_possible_cpu(cpu) {
|
||||
+ ret = rockchip_cpufreq_init(&pdev->dev, cpu);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = cpufreq_register_driver(&rockchip_cpufreq_driver);
|
||||
+ if (ret)
|
||||
+ return dev_err_probe(&pdev->dev, ret, "failed register driver\n");
|
||||
+
|
||||
+ ret = devm_add_action_or_reset(&pdev->dev, rockchip_cpufreq_unregister, NULL);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver rockchip_cpufreq_platdrv = {
|
||||
+ .driver = {
|
||||
+ .name = "rockchip-cpufreq",
|
||||
+ },
|
||||
+ .probe = rockchip_cpufreq_probe,
|
||||
+};
|
||||
+
|
||||
+static int __init rockchip_cpufreq_driver_init(void)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ if (!of_machine_is_compatible("rockchip,rk3588") &&
|
||||
+ !of_machine_is_compatible("rockchip,rk3588s")) {
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ ret = platform_driver_register(&rockchip_cpufreq_platdrv);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ cpufreq_pdev = platform_device_register_data(NULL, "rockchip-cpufreq", -1,
|
||||
+ NULL, 0);
|
||||
+ if (IS_ERR(cpufreq_pdev)) {
|
||||
+ pr_err("failed to register rockchip-cpufreq platform device\n");
|
||||
+ ret = PTR_ERR(cpufreq_pdev);
|
||||
+ goto unregister_platform_driver;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+unregister_platform_driver:
|
||||
+ platform_driver_unregister(&rockchip_cpufreq_platdrv);
|
||||
+ return ret;
|
||||
+}
|
||||
+module_init(rockchip_cpufreq_driver_init);
|
||||
+
|
||||
+static void __exit rockchip_cpufreq_driver_exit(void)
|
||||
+{
|
||||
+ platform_device_unregister(cpufreq_pdev);
|
||||
+ platform_driver_unregister(&rockchip_cpufreq_platdrv);
|
||||
+}
|
||||
+module_exit(rockchip_cpufreq_driver_exit)
|
||||
+
|
||||
+MODULE_AUTHOR("Finley Xiao <finley.xiao@rock-chips.com>");
|
||||
+MODULE_DESCRIPTION("Rockchip cpufreq driver");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
@ -1,555 +0,0 @@
|
||||
From 28ce8a074fe8944a0614dcde539456312f915113 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 4 Apr 2023 17:30:46 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3588: add cpu frequency scaling
|
||||
support
|
||||
|
||||
Add required bits for CPU frequency scaling to the Rockchip 3588
|
||||
devicetree. This is missing the 2.4 GHz operating point for the
|
||||
big cpu clusters, since that does not work well on all SoCs.
|
||||
Downstream has a driver for PVTM, which reduces the requested
|
||||
frequencies based on (among other things) silicon quality.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 452 ++++++++++++++++++++++
|
||||
1 file changed, 452 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -10,6 +10,7 @@
|
||||
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/ata/ahci.h>
|
||||
+#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3588";
|
||||
@@ -50,6 +51,215 @@
|
||||
spi4 = &spi4;
|
||||
};
|
||||
|
||||
+ cluster0_opp_table: opp-table-cluster0 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-408000000 {
|
||||
+ opp-hz = /bits/ 64 <408000000>;
|
||||
+ opp-microvolt = <750000 750000 950000>,
|
||||
+ <750000 750000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ opp-suspend;
|
||||
+ };
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt = <750000 750000 950000>,
|
||||
+ <750000 750000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-816000000 {
|
||||
+ opp-hz = /bits/ 64 <816000000>;
|
||||
+ opp-microvolt = <750000 750000 950000>,
|
||||
+ <750000 750000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1008000000 {
|
||||
+ opp-hz = /bits/ 64 <1008000000>;
|
||||
+ opp-microvolt = <750000 750000 950000>,
|
||||
+ <750000 750000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1200000000 {
|
||||
+ opp-hz = /bits/ 64 <1200000000>;
|
||||
+ opp-microvolt = <775000 775000 950000>,
|
||||
+ <775000 775000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <825000 825000 950000>,
|
||||
+ <825000 825000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <875000 875000 950000>,
|
||||
+ <875000 875000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <950000 950000 950000>,
|
||||
+ <950000 950000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cluster1_opp_table: opp-table-cluster1 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ rockchip,grf = <&bigcore0_grf>;
|
||||
+ rockchip,volt-mem-read-margin = <
|
||||
+ 855000 1
|
||||
+ 765000 2
|
||||
+ 675000 3
|
||||
+ 495000 4
|
||||
+ >;
|
||||
+
|
||||
+ rockchip,reboot-freq = <1800000000>;
|
||||
+
|
||||
+ opp-408000000 {
|
||||
+ opp-hz = /bits/ 64 <408000000>;
|
||||
+ opp-microvolt = <600000 600000 1000000>,
|
||||
+ <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ opp-suspend;
|
||||
+ };
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt = <600000 600000 1000000>,
|
||||
+ <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-816000000 {
|
||||
+ opp-hz = /bits/ 64 <816000000>;
|
||||
+ opp-microvolt = <600000 600000 1000000>,
|
||||
+ <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1008000000 {
|
||||
+ opp-hz = /bits/ 64 <1008000000>;
|
||||
+ opp-microvolt = <625000 625000 1000000>,
|
||||
+ <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1200000000 {
|
||||
+ opp-hz = /bits/ 64 <1200000000>;
|
||||
+ opp-microvolt = <650000 650000 1000000>,
|
||||
+ <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <675000 675000 1000000>,
|
||||
+ <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <700000 700000 1000000>,
|
||||
+ <700000 700000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <775000 775000 1000000>,
|
||||
+ <775000 775000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2016000000 {
|
||||
+ opp-hz = /bits/ 64 <2016000000>;
|
||||
+ opp-microvolt = <850000 850000 1000000>,
|
||||
+ <850000 850000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2208000000 {
|
||||
+ opp-hz = /bits/ 64 <2208000000>;
|
||||
+ opp-microvolt = <925000 925000 1000000>,
|
||||
+ <925000 925000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cluster2_opp_table: opp-table-cluster2 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ rockchip,grf = <&bigcore1_grf>;
|
||||
+ rockchip,volt-mem-read-margin = <
|
||||
+ 855000 1
|
||||
+ 765000 2
|
||||
+ 675000 3
|
||||
+ 495000 4
|
||||
+ >;
|
||||
+
|
||||
+ rockchip,reboot-freq = <1800000000>;
|
||||
+
|
||||
+ opp-408000000 {
|
||||
+ opp-hz = /bits/ 64 <408000000>;
|
||||
+ opp-microvolt = <600000 600000 1000000>,
|
||||
+ <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ opp-suspend;
|
||||
+ };
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt = <600000 600000 1000000>,
|
||||
+ <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-816000000 {
|
||||
+ opp-hz = /bits/ 64 <816000000>;
|
||||
+ opp-microvolt = <600000 600000 1000000>,
|
||||
+ <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1008000000 {
|
||||
+ opp-hz = /bits/ 64 <1008000000>;
|
||||
+ opp-microvolt = <625000 625000 1000000>,
|
||||
+ <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1200000000 {
|
||||
+ opp-hz = /bits/ 64 <1200000000>;
|
||||
+ opp-microvolt = <650000 650000 1000000>,
|
||||
+ <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <675000 675000 1000000>,
|
||||
+ <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <700000 700000 1000000>,
|
||||
+ <700000 700000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <775000 775000 1000000>,
|
||||
+ <775000 775000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2016000000 {
|
||||
+ opp-hz = /bits/ 64 <2016000000>;
|
||||
+ opp-microvolt = <850000 850000 1000000>,
|
||||
+ <850000 850000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2208000000 {
|
||||
+ opp-hz = /bits/ 64 <2208000000>;
|
||||
+ opp-microvolt = <925000 925000 1000000>,
|
||||
+ <925000 925000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@@ -96,6 +306,7 @@
|
||||
clocks = <&scmi_clk SCMI_CLK_CPUL>;
|
||||
assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
|
||||
assigned-clock-rates = <816000000>;
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-line-size = <64>;
|
||||
@@ -115,6 +326,7 @@
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <530>;
|
||||
clocks = <&scmi_clk SCMI_CLK_CPUL>;
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-line-size = <64>;
|
||||
@@ -134,6 +346,7 @@
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <530>;
|
||||
clocks = <&scmi_clk SCMI_CLK_CPUL>;
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-line-size = <64>;
|
||||
@@ -153,6 +366,7 @@
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <530>;
|
||||
clocks = <&scmi_clk SCMI_CLK_CPUL>;
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-line-size = <64>;
|
||||
@@ -174,6 +388,7 @@
|
||||
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
|
||||
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
|
||||
assigned-clock-rates = <816000000>;
|
||||
+ operating-points-v2 = <&cluster1_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-line-size = <64>;
|
||||
@@ -193,6 +408,7 @@
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
|
||||
+ operating-points-v2 = <&cluster1_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-line-size = <64>;
|
||||
@@ -214,6 +430,7 @@
|
||||
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
|
||||
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
|
||||
assigned-clock-rates = <816000000>;
|
||||
+ operating-points-v2 = <&cluster2_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-line-size = <64>;
|
||||
@@ -233,6 +450,7 @@
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
|
||||
+ operating-points-v2 = <&cluster2_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-line-size = <64>;
|
||||
@@ -399,6 +617,230 @@
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
+ thermal_zones: thermal-zones {
|
||||
+ soc_thermal: soc-thermal {
|
||||
+ polling-delay-passive = <20>; /* milliseconds */
|
||||
+ polling-delay = <1000>; /* milliseconds */
|
||||
+ sustainable-power = <2100>; /* milliwatts */
|
||||
+
|
||||
+ thermal-sensors = <&tsadc 0>;
|
||||
+ trips {
|
||||
+ trip-point-0 {
|
||||
+ temperature = <75000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ soc_target: trip-point-1 {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ trip-point-2 {
|
||||
+ /* millicelsius */
|
||||
+ temperature = <115000>;
|
||||
+ /* millicelsius */
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&soc_target>;
|
||||
+ cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ contribution = <1024>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ bigcore0_thermal: bigcore0-thermal {
|
||||
+ polling-delay-passive = <20>; /* milliseconds */
|
||||
+ polling-delay = <1000>; /* milliseconds */
|
||||
+ thermal-sensors = <&tsadc 1>;
|
||||
+
|
||||
+ trips {
|
||||
+ trip-point-0 {
|
||||
+ temperature = <75000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ b0_target: trip-point-1 {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ trip-point-2 {
|
||||
+ /* millicelsius */
|
||||
+ temperature = <115000>;
|
||||
+ /* millicelsius */
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&b0_target>;
|
||||
+ cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ contribution = <1024>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ bigcore1_thermal: bigcore1-thermal {
|
||||
+ polling-delay-passive = <20>; /* milliseconds */
|
||||
+ polling-delay = <1000>; /* milliseconds */
|
||||
+ thermal-sensors = <&tsadc 2>;
|
||||
+ trips {
|
||||
+ trip-point-0 {
|
||||
+ temperature = <75000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ b1_target: trip-point-1 {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ trip-point-2 {
|
||||
+ /* millicelsius */
|
||||
+ temperature = <115000>;
|
||||
+ /* millicelsius */
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&b1_target>;
|
||||
+ cooling-device = <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ contribution = <1024>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ little_core_thermal: littlecore-thermal {
|
||||
+ polling-delay-passive = <20>; /* milliseconds */
|
||||
+ polling-delay = <1000>; /* milliseconds */
|
||||
+ thermal-sensors = <&tsadc 3>;
|
||||
+ trips {
|
||||
+ trip-point-0 {
|
||||
+ temperature = <75000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ l0_target: trip-point-1 {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ trip-point-2 {
|
||||
+ /* millicelsius */
|
||||
+ temperature = <115000>;
|
||||
+ /* millicelsius */
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&l0_target>;
|
||||
+ cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ contribution = <1024>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ center_thermal: center-thermal {
|
||||
+ polling-delay-passive = <20>; /* milliseconds */
|
||||
+ polling-delay = <1000>; /* milliseconds */
|
||||
+ thermal-sensors = <&tsadc 4>;
|
||||
+ trips {
|
||||
+ trip-point-0 {
|
||||
+ temperature = <75000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ trip-point-1 {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ trip-point-2 {
|
||||
+ /* millicelsius */
|
||||
+ temperature = <115000>;
|
||||
+ /* millicelsius */
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpu_thermal: gpu-thermal {
|
||||
+ polling-delay-passive = <20>; /* milliseconds */
|
||||
+ polling-delay = <1000>; /* milliseconds */
|
||||
+ thermal-sensors = <&tsadc 5>;
|
||||
+ trips {
|
||||
+ trip-point-0 {
|
||||
+ temperature = <75000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ trip-point-1 {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ trip-point-2 {
|
||||
+ /* millicelsius */
|
||||
+ temperature = <115000>;
|
||||
+ /* millicelsius */
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ npu_thermal: npu-thermal {
|
||||
+ polling-delay-passive = <20>; /* milliseconds */
|
||||
+ polling-delay = <1000>; /* milliseconds */
|
||||
+ thermal-sensors = <&tsadc 6>;
|
||||
+ trips {
|
||||
+ trip-point-0 {
|
||||
+ temperature = <75000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ trip-point-1 {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ trip-point-2 {
|
||||
+ /* millicelsius */
|
||||
+ temperature = <115000>;
|
||||
+ /* millicelsius */
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
@@ -635,6 +1077,16 @@
|
||||
reg = <0x0 0xfd5ac000 0x0 0x4000>;
|
||||
};
|
||||
|
||||
+ bigcore0_grf: syscon@fd590000 {
|
||||
+ compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
|
||||
+ reg = <0x0 0xfd590000 0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ bigcore1_grf: syscon@fd592000 {
|
||||
+ compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
|
||||
+ reg = <0x0 0xfd592000 0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
php_grf: syscon@fd5b0000 {
|
||||
compatible = "rockchip,rk3588-php-grf", "syscon";
|
||||
reg = <0x0 0xfd5b0000 0x0 0x1000>;
|
||||
@ -1,22 +0,0 @@
|
||||
From efdf918a1667bf01b167eb98d582d75e14147903 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 25 May 2023 19:45:02 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: enable RK3588 tsadc by default
|
||||
|
||||
Enable the thermal ADC for all boards.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -2837,7 +2837,6 @@
|
||||
pinctrl-1 = <&tsadc_shut>;
|
||||
pinctrl-names = "gpio", "otpout";
|
||||
#thermal-sensor-cells = <1>;
|
||||
- status = "disabled";
|
||||
};
|
||||
|
||||
saradc: adc@fec10000 {
|
||||
@ -1,48 +0,0 @@
|
||||
From 44ab35d703a396c625ae90fcaa2777e4dcfd6c73 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 18 Aug 2022 14:35:46 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3588-evb1: add cpu regulator info
|
||||
|
||||
Add regulator information for the CPU and enable the thermal sensor
|
||||
to have working cpu frequency scaling.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588-evb1-v10.dts | 19 +++++++++++++++++++
|
||||
1 file changed, 19 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
|
||||
@@ -118,6 +118,21 @@
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
+&cpu_l0 {
|
||||
+ cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b0 {
|
||||
+ cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big0_mem_s0>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b2 {
|
||||
+ cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big1_mem_s0>;
|
||||
+};
|
||||
+
|
||||
&gmac0 {
|
||||
clock_in_out = "output";
|
||||
phy-handle = <&rgmii_phy>;
|
||||
@@ -825,6 +840,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&tsadc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2m0_xfer>;
|
||||
status = "okay";
|
||||
@ -1,58 +0,0 @@
|
||||
From a6000cf17b43c6e953c9f75bfc05ace3d2fd72fe Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 24 Jul 2023 15:18:39 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: rock5a: add cpu mem regulator info
|
||||
|
||||
Add the second supply regulator for the CPU cores, which is used
|
||||
for supplying the memory interface.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
@@ -123,34 +123,42 @@
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b2 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_b3 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
@ -1,58 +0,0 @@
|
||||
From 3b70b9529d63d21f0ed03c332d8877b63b968d10 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 24 Jul 2023 15:07:49 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: rock5b: add cpu mem regulator info
|
||||
|
||||
Add the second supply regulator for the CPU cores, which is used
|
||||
for supplying the memory interface.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -154,34 +154,42 @@
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b2 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_b3 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
@ -51,7 +51,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
};
|
||||
|
||||
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
|
||||
@@ -237,6 +248,61 @@
|
||||
@@ -229,6 +240,61 @@
|
||||
};
|
||||
};
|
||||
|
||||
@ -113,7 +113,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
&i2c6 {
|
||||
status = "okay";
|
||||
|
||||
@@ -366,6 +432,10 @@
|
||||
@@ -388,6 +454,10 @@
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
@ -124,7 +124,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
};
|
||||
};
|
||||
|
||||
@@ -758,6 +828,14 @@
|
||||
@@ -798,6 +868,14 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -139,7 +139,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -789,6 +867,29 @@
|
||||
@@ -829,6 +907,29 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -169,7 +169,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -797,6 +898,20 @@
|
||||
@@ -837,6 +938,20 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -1,45 +0,0 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
@@ -203,34 +203,42 @@
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b2 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_b3 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
+ mem-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
@ -29,7 +29,7 @@
|
||||
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc-1v1-nldo-s3";
|
||||
@@ -551,6 +573,10 @@
|
||||
@@ -543,6 +565,10 @@
|
||||
usbc0_int: usbc0-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
@ -40,7 +40,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
@@ -922,6 +948,11 @@
|
||||
@@ -914,6 +940,11 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -52,7 +52,7 @@
|
||||
&u2phy2_host {
|
||||
phy-supply = <&vdd_4g_3v3>;
|
||||
status = "okay";
|
||||
@@ -931,6 +962,10 @@
|
||||
@@ -923,6 +954,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -63,7 +63,7 @@
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -939,6 +974,10 @@
|
||||
@@ -931,6 +966,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -74,7 +74,7 @@
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -954,3 +993,7 @@
|
||||
@@ -946,3 +985,7 @@
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
@@ -421,6 +421,48 @@
|
||||
@@ -413,6 +413,48 @@
|
||||
source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
|
||||
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
|
||||
op-sink-microwatt = <1000000>;
|
||||
@ -49,7 +49,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
@@ -948,6 +990,10 @@
|
||||
@@ -940,6 +982,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -60,7 +60,7 @@
|
||||
&u2phy1_otg {
|
||||
phy-supply = <&vcc5v0_host_30>;
|
||||
status = "okay";
|
||||
@@ -962,6 +1008,10 @@
|
||||
@@ -954,6 +1000,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -71,7 +71,7 @@
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -974,6 +1024,29 @@
|
||||
@@ -966,6 +1016,29 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -101,7 +101,7 @@
|
||||
&usbdp_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -986,6 +1059,21 @@
|
||||
@@ -978,6 +1051,21 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -9,9 +9,9 @@ Change-Id: I050cc7f6398500e705b27c588948201e571817ea
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 18 ++++++++++++++++++
|
||||
1 file changed, 18 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -565,6 +565,12 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -348,6 +348,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -311,7 +311,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
@@ -530,6 +530,20 @@
|
||||
@@ -522,6 +522,20 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie2_0_rst>;
|
||||
status = "okay";
|
||||
@ -332,7 +332,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
};
|
||||
|
||||
&pcie2x1l1 {
|
||||
@@ -546,6 +560,20 @@
|
||||
@@ -538,6 +552,20 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie2_2_rst>;
|
||||
status = "okay";
|
||||
|
||||
@ -9,9 +9,9 @@ Change-Id: Ifb8964053daa6b593dd2c2c6a3b8caab8526e56d
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 +++++++++++
|
||||
1 file changed, 11 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -2258,6 +2258,16 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -1769,6 +1769,16 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -12,9 +12,9 @@ Change-Id: I49994529fcc209c2bc173c1abc497536fb920302
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -2262,7 +2262,7 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -1773,7 +1773,7 @@
|
||||
compatible = "rockchip,trngv1";
|
||||
reg = <0x0 0xfe378000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@ -1,28 +0,0 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -181,6 +181,12 @@
|
||||
<925000 925000 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
+ opp-2400000000 {
|
||||
+ opp-hz = /bits/ 64 <2400000000>;
|
||||
+ opp-microvolt = <1000000 1000000 1000000>,
|
||||
+ <1000000 1000000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
cluster2_opp_table: opp-table-cluster2 {
|
||||
@@ -258,6 +264,12 @@
|
||||
<925000 925000 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
+ opp-2400000000 {
|
||||
+ opp-hz = /bits/ 64 <2400000000>;
|
||||
+ opp-microvolt = <1000000 1000000 1000000>,
|
||||
+ <1000000 1000000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
cpus {
|
||||
Loading…
Reference in New Issue
Block a user