diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
index c5ca4d657b..fdae1f21a6 100644
--- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
+++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
@@ -69,6 +69,8 @@
 		compatible = "ethernet-phy-id001c.c916",
 			     "ethernet-phy-ieee802.3-c22";
 		reg = <0>;
+		pinctrl-0 = <&eth_phy0_reset_pin>;
+		pinctrl-names = "default";
 		reset-assert-us = <10000>;
 		reset-deassert-us = <50000>;
 		reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
@@ -80,12 +82,28 @@
 		compatible = "ethernet-phy-id001c.c916",
 			     "ethernet-phy-ieee802.3-c22";
 		reg = <0>;
+		pinctrl-0 = <&eth_phy1_reset_pin>;
+		pinctrl-names = "default";
 		reset-assert-us = <10000>;
 		reset-deassert-us = <50000>;
 		reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
 	};
 };
 
+&pinctrl {
+	gmac0 {
+		eth_phy0_reset_pin: eth-phy0-reset-pin {
+			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	gmac1 {
+		eth_phy1_reset_pin: eth-phy1-reset-pin {
+			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+};
+
 &sdhci {
 	bus-width = <8>;
 	max-frequency = <200000000>;
diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r6xs.dtsi b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r6xs.dtsi
index fd3acc75bd..570e89eb79 100644
--- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r6xs.dtsi
+++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r6xs.dtsi
@@ -25,7 +25,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&reset_button_pin>;
 
-		reset {
+		button-reset {
 			debounce-interval = <50>;
 			gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
 			label = "reset";