From 0d6e831f2ce450c15341e818f0c84d85e5259eec Mon Sep 17 00:00:00 2001 From: AmadeusGhost <42570690+AmadeusGhost@users.noreply.github.com> Date: Wed, 10 Feb 2021 12:20:23 +0800 Subject: [PATCH] sunxi: backport thermal sensor driver from upstream linux --- target/linux/sunxi/config-5.4 | 1 + .../files-5.4/drivers/thermal/sun8i_thermal.c | 654 ++++++++++++++++++ ...5.6-thermal_hwmon-Add-devres-wrapper.patch | 88 +++ ...mal-drivers-sun8i-Add-thermal-driver.patch | 61 ++ ...Add-thermal-sensor-and-thermal-zones.patch | 63 ++ ...Add-thermal-trip-points-cooling-maps.patch | 68 ++ ...er-h5-Add-thermal-sensor-and-thermal.patch | 52 ++ ...-allwinner-h5-Add-clock-to-CPU-cores.patch | 56 ++ ...lwinner-h5-Add-trip-and-cooling-maps.patch | 92 +++ ...U-Operating-Performance-Points-table.patch | 113 +++ 10 files changed, 1248 insertions(+) create mode 100644 target/linux/sunxi/files-5.4/drivers/thermal/sun8i_thermal.c create mode 100644 target/linux/sunxi/patches-5.4/011-v5.6-thermal_hwmon-Add-devres-wrapper.patch create mode 100644 target/linux/sunxi/patches-5.4/012-thermal-drivers-sun8i-Add-thermal-driver.patch create mode 100644 target/linux/sunxi/patches-5.4/013-ARM-dts-sun8i-h3-Add-thermal-sensor-and-thermal-zones.patch create mode 100644 target/linux/sunxi/patches-5.4/014-ARM-dts-sun8i-h3-Add-thermal-trip-points-cooling-maps.patch create mode 100644 target/linux/sunxi/patches-5.4/015-arm64-dts-allwinner-h5-Add-thermal-sensor-and-thermal.patch create mode 100644 target/linux/sunxi/patches-5.4/016-arm64-dts-allwinner-h5-Add-clock-to-CPU-cores.patch create mode 100644 target/linux/sunxi/patches-5.4/017-arm64-dts-allwinner-h5-Add-trip-and-cooling-maps.patch create mode 100644 target/linux/sunxi/patches-5.4/018-arm64-dts-allwinner-h5-Add-CPU-Operating-Performance-Points-table.patch diff --git a/target/linux/sunxi/config-5.4 b/target/linux/sunxi/config-5.4 index fba86b86ee..c28249f6f1 100644 --- a/target/linux/sunxi/config-5.4 +++ b/target/linux/sunxi/config-5.4 @@ -517,6 +517,7 @@ CONFIG_SUN8I_DE2_CCU=y CONFIG_SUN8I_H3_CCU=y CONFIG_SUN8I_R40_CCU=y CONFIG_SUN8I_R_CCU=y +CONFIG_SUN8I_THERMAL=y CONFIG_SUN8I_V3S_CCU=y CONFIG_SUN9I_A80_CCU=y CONFIG_SUNXI_CCU=y diff --git a/target/linux/sunxi/files-5.4/drivers/thermal/sun8i_thermal.c b/target/linux/sunxi/files-5.4/drivers/thermal/sun8i_thermal.c new file mode 100644 index 0000000000..8c80bd06dd --- /dev/null +++ b/target/linux/sunxi/files-5.4/drivers/thermal/sun8i_thermal.c @@ -0,0 +1,654 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Thermal sensor driver for Allwinner SOC + * Copyright (C) 2019 Yangtao Li + * + * Based on the work of Icenowy Zheng + * Based on the work of Ondrej Jirman + * Based on the work of Josef Gajdusek + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "thermal_hwmon.h" + +#define MAX_SENSOR_NUM 4 + +#define FT_TEMP_MASK GENMASK(11, 0) +#define TEMP_CALIB_MASK GENMASK(11, 0) +#define CALIBRATE_DEFAULT 0x800 + +#define SUN8I_THS_CTRL0 0x00 +#define SUN8I_THS_CTRL2 0x40 +#define SUN8I_THS_IC 0x44 +#define SUN8I_THS_IS 0x48 +#define SUN8I_THS_MFC 0x70 +#define SUN8I_THS_TEMP_CALIB 0x74 +#define SUN8I_THS_TEMP_DATA 0x80 + +#define SUN50I_THS_CTRL0 0x00 +#define SUN50I_H6_THS_ENABLE 0x04 +#define SUN50I_H6_THS_PC 0x08 +#define SUN50I_H6_THS_DIC 0x10 +#define SUN50I_H6_THS_DIS 0x20 +#define SUN50I_H6_THS_MFC 0x30 +#define SUN50I_H6_THS_TEMP_CALIB 0xa0 +#define SUN50I_H6_THS_TEMP_DATA 0xc0 + +#define SUN8I_THS_CTRL0_T_ACQ0(x) (GENMASK(15, 0) & (x)) +#define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16) +#define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8) + +#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16) +#define SUN50I_THS_FILTER_EN BIT(2) +#define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x)) +#define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12) +#define SUN50I_H6_THS_DATA_IRQ_STS(x) BIT(x) + +/* millidegree celsius */ + +struct tsensor { + struct ths_device *tmdev; + struct thermal_zone_device *tzd; + int id; +}; + +struct ths_thermal_chip { + bool has_mod_clk; + bool has_bus_clk_reset; + int sensor_num; + int offset; + int scale; + int ft_deviation; + int temp_data_base; + int (*calibrate)(struct ths_device *tmdev, + u16 *caldata, int callen); + int (*init)(struct ths_device *tmdev); + unsigned long (*irq_ack)(struct ths_device *tmdev); + int (*calc_temp)(struct ths_device *tmdev, + int id, int reg); +}; + +struct ths_device { + const struct ths_thermal_chip *chip; + struct device *dev; + struct regmap *regmap; + struct reset_control *reset; + struct clk *bus_clk; + struct clk *mod_clk; + struct tsensor sensor[MAX_SENSOR_NUM]; +}; + +/* Temp Unit: millidegree Celsius */ +static int sun8i_ths_calc_temp(struct ths_device *tmdev, + int id, int reg) +{ + return tmdev->chip->offset - (reg * tmdev->chip->scale / 10); +} + +static int sun50i_h5_calc_temp(struct ths_device *tmdev, + int id, int reg) +{ + if (reg >= 0x500) + return -1191 * reg / 10 + 223000; + else if (!id) + return -1452 * reg / 10 + 259000; + else + return -1590 * reg / 10 + 276000; +} + +static int sun8i_ths_get_temp(void *data, int *temp) +{ + struct tsensor *s = data; + struct ths_device *tmdev = s->tmdev; + int val = 0; + + regmap_read(tmdev->regmap, tmdev->chip->temp_data_base + + 0x4 * s->id, &val); + + /* ths have no data yet */ + if (!val) + return -EAGAIN; + + *temp = tmdev->chip->calc_temp(tmdev, s->id, val); + /* + * According to the original sdk, there are some platforms(rarely) + * that add a fixed offset value after calculating the temperature + * value. We can't simply put it on the formula for calculating the + * temperature above, because the formula for calculating the + * temperature above is also used when the sensor is calibrated. If + * do this, the correct calibration formula is hard to know. + */ + *temp += tmdev->chip->ft_deviation; + + return 0; +} + +static const struct thermal_zone_of_device_ops ths_ops = { + .get_temp = sun8i_ths_get_temp, +}; + +static const struct regmap_config config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, + .max_register = 0xfc, +}; + +static unsigned long sun8i_h3_irq_ack(struct ths_device *tmdev) +{ + unsigned long irq_bitmap = 0; + int i, state; + + regmap_read(tmdev->regmap, SUN8I_THS_IS, &state); + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + if (state & SUN8I_THS_DATA_IRQ_STS(i)) { + regmap_write(tmdev->regmap, SUN8I_THS_IS, + SUN8I_THS_DATA_IRQ_STS(i)); + bitmap_set(&irq_bitmap, i, 1); + } + } + + return irq_bitmap; +} + +static unsigned long sun50i_h6_irq_ack(struct ths_device *tmdev) +{ + unsigned long irq_bitmap = 0; + int i, state; + + regmap_read(tmdev->regmap, SUN50I_H6_THS_DIS, &state); + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + if (state & SUN50I_H6_THS_DATA_IRQ_STS(i)) { + regmap_write(tmdev->regmap, SUN50I_H6_THS_DIS, + SUN50I_H6_THS_DATA_IRQ_STS(i)); + bitmap_set(&irq_bitmap, i, 1); + } + } + + return irq_bitmap; +} + +static irqreturn_t sun8i_irq_thread(int irq, void *data) +{ + struct ths_device *tmdev = data; + unsigned long irq_bitmap = tmdev->chip->irq_ack(tmdev); + int i; + + for_each_set_bit(i, &irq_bitmap, tmdev->chip->sensor_num) { + thermal_zone_device_update(tmdev->sensor[i].tzd, + THERMAL_EVENT_UNSPECIFIED); + } + + return IRQ_HANDLED; +} + +static int sun8i_h3_ths_calibrate(struct ths_device *tmdev, + u16 *caldata, int callen) +{ + int i; + + if (!caldata[0] || callen < 2 * tmdev->chip->sensor_num) + return -EINVAL; + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + int offset = (i % 2) << 4; + + regmap_update_bits(tmdev->regmap, + SUN8I_THS_TEMP_CALIB + (4 * (i >> 1)), + 0xfff << offset, + caldata[i] << offset); + } + + return 0; +} + +static int sun50i_h6_ths_calibrate(struct ths_device *tmdev, + u16 *caldata, int callen) +{ + struct device *dev = tmdev->dev; + int i, ft_temp; + + if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num) + return -EINVAL; + + /* + * efuse layout: + * + * 0 11 16 32 + * +-------+-------+-------+ + * |temp| |sensor0|sensor1| + * +-------+-------+-------+ + * + * The calibration data on the H6 is the ambient temperature and + * sensor values that are filled during the factory test stage. + * + * The unit of stored FT temperature is 0.1 degreee celusis. + * + * We need to calculate a delta between measured and caluclated + * register values and this will become a calibration offset. + */ + ft_temp = (caldata[0] & FT_TEMP_MASK) * 100; + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK; + int cdata, offset; + int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg); + + /* + * Calibration data is CALIBRATE_DEFAULT - (calculated + * temperature from sensor reading at factory temperature + * minus actual factory temperature) * 14.88 (scale from + * temperature to register values) + */ + cdata = CALIBRATE_DEFAULT - + ((sensor_temp - ft_temp) * 10 / tmdev->chip->scale); + if (cdata & ~TEMP_CALIB_MASK) { + /* + * Calibration value more than 12-bit, but calibration + * register is 12-bit. In this case, ths hardware can + * still work without calibration, although the data + * won't be so accurate. + */ + dev_warn(dev, "sensor%d is not calibrated.\n", i); + continue; + } + + offset = (i % 2) * 16; + regmap_update_bits(tmdev->regmap, + SUN50I_H6_THS_TEMP_CALIB + (i / 2 * 4), + 0xfff << offset, + cdata << offset); + } + + return 0; +} + +static int sun8i_ths_calibrate(struct ths_device *tmdev) +{ + struct nvmem_cell *calcell; + struct device *dev = tmdev->dev; + u16 *caldata; + size_t callen; + int ret = 0; + + calcell = devm_nvmem_cell_get(dev, "calibration"); + if (IS_ERR(calcell)) { + if (PTR_ERR(calcell) == -EPROBE_DEFER) + return -EPROBE_DEFER; + /* + * Even if the external calibration data stored in sid is + * not accessible, the THS hardware can still work, although + * the data won't be so accurate. + * + * The default value of calibration register is 0x800 for + * every sensor, and the calibration value is usually 0x7xx + * or 0x8xx, so they won't be away from the default value + * for a lot. + * + * So here we do not return error if the calibartion data is + * not available, except the probe needs deferring. + */ + goto out; + } + + caldata = nvmem_cell_read(calcell, &callen); + if (IS_ERR(caldata)) { + ret = PTR_ERR(caldata); + goto out; + } + + tmdev->chip->calibrate(tmdev, caldata, callen); + + kfree(caldata); +out: + return ret; +} + +static int sun8i_ths_resource_init(struct ths_device *tmdev) +{ + struct device *dev = tmdev->dev; + struct platform_device *pdev = to_platform_device(dev); + void __iomem *base; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + tmdev->regmap = devm_regmap_init_mmio(dev, base, &config); + if (IS_ERR(tmdev->regmap)) + return PTR_ERR(tmdev->regmap); + + if (tmdev->chip->has_bus_clk_reset) { + tmdev->reset = devm_reset_control_get(dev, NULL); + if (IS_ERR(tmdev->reset)) + return PTR_ERR(tmdev->reset); + + tmdev->bus_clk = devm_clk_get(&pdev->dev, "bus"); + if (IS_ERR(tmdev->bus_clk)) + return PTR_ERR(tmdev->bus_clk); + } + + if (tmdev->chip->has_mod_clk) { + tmdev->mod_clk = devm_clk_get(&pdev->dev, "mod"); + if (IS_ERR(tmdev->mod_clk)) + return PTR_ERR(tmdev->mod_clk); + } + + ret = reset_control_deassert(tmdev->reset); + if (ret) + return ret; + + ret = clk_prepare_enable(tmdev->bus_clk); + if (ret) + goto assert_reset; + + ret = clk_set_rate(tmdev->mod_clk, 24000000); + if (ret) + goto bus_disable; + + ret = clk_prepare_enable(tmdev->mod_clk); + if (ret) + goto bus_disable; + + ret = sun8i_ths_calibrate(tmdev); + if (ret) + goto mod_disable; + + return 0; + +mod_disable: + clk_disable_unprepare(tmdev->mod_clk); +bus_disable: + clk_disable_unprepare(tmdev->bus_clk); +assert_reset: + reset_control_assert(tmdev->reset); + + return ret; +} + +static int sun8i_h3_thermal_init(struct ths_device *tmdev) +{ + int val; + + /* average over 4 samples */ + regmap_write(tmdev->regmap, SUN8I_THS_MFC, + SUN50I_THS_FILTER_EN | + SUN50I_THS_FILTER_TYPE(1)); + /* + * clkin = 24MHz + * filter_samples = 4 + * period = 0.25s + * + * x = period * clkin / 4096 / filter_samples - 1 + * = 365 + */ + val = GENMASK(7 + tmdev->chip->sensor_num, 8); + regmap_write(tmdev->regmap, SUN8I_THS_IC, + SUN50I_H6_THS_PC_TEMP_PERIOD(365) | val); + /* + * T_acq = 20us + * clkin = 24MHz + * + * x = T_acq * clkin - 1 + * = 479 + */ + regmap_write(tmdev->regmap, SUN8I_THS_CTRL0, + SUN8I_THS_CTRL0_T_ACQ0(479)); + val = GENMASK(tmdev->chip->sensor_num - 1, 0); + regmap_write(tmdev->regmap, SUN8I_THS_CTRL2, + SUN8I_THS_CTRL2_T_ACQ1(479) | val); + + return 0; +} + +/* + * Without this undocummented value, the returned temperatures would + * be higher than real ones by about 20C. + */ +#define SUN50I_H6_CTRL0_UNK 0x0000002f + +static int sun50i_h6_thermal_init(struct ths_device *tmdev) +{ + int val; + + /* + * T_acq = 20us + * clkin = 24MHz + * + * x = T_acq * clkin - 1 + * = 479 + */ + regmap_write(tmdev->regmap, SUN50I_THS_CTRL0, + SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479)); + /* average over 4 samples */ + regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC, + SUN50I_THS_FILTER_EN | + SUN50I_THS_FILTER_TYPE(1)); + /* + * clkin = 24MHz + * filter_samples = 4 + * period = 0.25s + * + * x = period * clkin / 4096 / filter_samples - 1 + * = 365 + */ + regmap_write(tmdev->regmap, SUN50I_H6_THS_PC, + SUN50I_H6_THS_PC_TEMP_PERIOD(365)); + /* enable sensor */ + val = GENMASK(tmdev->chip->sensor_num - 1, 0); + regmap_write(tmdev->regmap, SUN50I_H6_THS_ENABLE, val); + /* thermal data interrupt enable */ + val = GENMASK(tmdev->chip->sensor_num - 1, 0); + regmap_write(tmdev->regmap, SUN50I_H6_THS_DIC, val); + + return 0; +} + +static int sun8i_ths_register(struct ths_device *tmdev) +{ + int i; + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + tmdev->sensor[i].tmdev = tmdev; + tmdev->sensor[i].id = i; + tmdev->sensor[i].tzd = + devm_thermal_zone_of_sensor_register(tmdev->dev, + i, + &tmdev->sensor[i], + &ths_ops); + if (IS_ERR(tmdev->sensor[i].tzd)) + return PTR_ERR(tmdev->sensor[i].tzd); + + if (devm_thermal_add_hwmon_sysfs(tmdev->sensor[i].tzd)) + dev_warn(tmdev->dev, + "Failed to add hwmon sysfs attributes\n"); + } + + return 0; +} + +static int sun8i_ths_probe(struct platform_device *pdev) +{ + struct ths_device *tmdev; + struct device *dev = &pdev->dev; + int ret, irq; + + tmdev = devm_kzalloc(dev, sizeof(*tmdev), GFP_KERNEL); + if (!tmdev) + return -ENOMEM; + + tmdev->dev = dev; + tmdev->chip = of_device_get_match_data(&pdev->dev); + if (!tmdev->chip) + return -EINVAL; + + platform_set_drvdata(pdev, tmdev); + + ret = sun8i_ths_resource_init(tmdev); + if (ret) + return ret; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = tmdev->chip->init(tmdev); + if (ret) + return ret; + + ret = sun8i_ths_register(tmdev); + if (ret) + return ret; + + /* + * Avoid entering the interrupt handler, the thermal device is not + * registered yet, we deffer the registration of the interrupt to + * the end. + */ + ret = devm_request_threaded_irq(dev, irq, NULL, + sun8i_irq_thread, + IRQF_ONESHOT, "ths", tmdev); + if (ret) + return ret; + + return 0; +} + +static int sun8i_ths_remove(struct platform_device *pdev) +{ + struct ths_device *tmdev = platform_get_drvdata(pdev); + + clk_disable_unprepare(tmdev->mod_clk); + clk_disable_unprepare(tmdev->bus_clk); + reset_control_assert(tmdev->reset); + + return 0; +} + +static const struct ths_thermal_chip sun8i_a83t_ths = { + .sensor_num = 3, + .scale = 705, + .offset = 191668, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun8i_h3_ths = { + .sensor_num = 1, + .scale = 1211, + .offset = 217000, + .has_mod_clk = true, + .has_bus_clk_reset = true, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun8i_r40_ths = { + .sensor_num = 2, + .offset = 251086, + .scale = 1130, + .has_mod_clk = true, + .has_bus_clk_reset = true, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun50i_a64_ths = { + .sensor_num = 3, + .offset = 260890, + .scale = 1170, + .has_mod_clk = true, + .has_bus_clk_reset = true, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun50i_a100_ths = { + .sensor_num = 3, + .has_bus_clk_reset = true, + .ft_deviation = 8000, + .offset = 187744, + .scale = 672, + .temp_data_base = SUN50I_H6_THS_TEMP_DATA, + .calibrate = sun50i_h6_ths_calibrate, + .init = sun50i_h6_thermal_init, + .irq_ack = sun50i_h6_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun50i_h5_ths = { + .sensor_num = 2, + .has_mod_clk = true, + .has_bus_clk_reset = true, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun50i_h5_calc_temp, +}; + +static const struct ths_thermal_chip sun50i_h6_ths = { + .sensor_num = 2, + .has_bus_clk_reset = true, + .ft_deviation = 7000, + .offset = 187744, + .scale = 672, + .temp_data_base = SUN50I_H6_THS_TEMP_DATA, + .calibrate = sun50i_h6_ths_calibrate, + .init = sun50i_h6_thermal_init, + .irq_ack = sun50i_h6_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct of_device_id of_ths_match[] = { + { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, + { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, + { .compatible = "allwinner,sun8i-r40-ths", .data = &sun8i_r40_ths }, + { .compatible = "allwinner,sun50i-a64-ths", .data = &sun50i_a64_ths }, + { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths }, + { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths }, + { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, of_ths_match); + +static struct platform_driver ths_driver = { + .probe = sun8i_ths_probe, + .remove = sun8i_ths_remove, + .driver = { + .name = "sun8i-thermal", + .of_match_table = of_ths_match, + }, +}; +module_platform_driver(ths_driver); + +MODULE_DESCRIPTION("Thermal sensor driver for Allwinner SOC"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/sunxi/patches-5.4/011-v5.6-thermal_hwmon-Add-devres-wrapper.patch b/target/linux/sunxi/patches-5.4/011-v5.6-thermal_hwmon-Add-devres-wrapper.patch new file mode 100644 index 0000000000..5e817cd140 --- /dev/null +++ b/target/linux/sunxi/patches-5.4/011-v5.6-thermal_hwmon-Add-devres-wrapper.patch @@ -0,0 +1,88 @@ +From c7fc403e40b0ea18976a59e968c23439a80809e8 Mon Sep 17 00:00:00 2001 +From: Andrey Smirnov +Date: Tue, 10 Dec 2019 08:41:52 -0800 +Subject: [PATCH] thermal_hwmon: Add devres wrapper for + thermal_add_hwmon_sysfs() + +Add devres wrapper for thermal_add_hwmon_sysfs() to simplify driver +code. + +Signed-off-by: Andrey Smirnov +Reviewed-by: Daniel Lezcano +Tested-by: Lucas Stach +Cc: Chris Healy +Cc: Lucas Stach +Cc: Eduardo Valentin +Cc: Daniel Lezcano +Cc: Angus Ainslie (Purism) +Cc: linux-imx@nxp.com +Cc: linux-pm@vger.kernel.org +Cc: linux-kernel@vger.kernel.org +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20191210164153.10463-12-andrew.smirnov@gmail.com +--- + drivers/thermal/thermal_hwmon.c | 28 ++++++++++++++++++++++++++++ + drivers/thermal/thermal_hwmon.h | 7 +++++++ + 2 files changed, 35 insertions(+) + +diff --git a/drivers/thermal/thermal_hwmon.c b/drivers/thermal/thermal_hwmon.c +index dd5d8ee379287..c8d2620f2e427 100644 +--- a/drivers/thermal/thermal_hwmon.c ++++ b/drivers/thermal/thermal_hwmon.c +@@ -248,3 +248,31 @@ void thermal_remove_hwmon_sysfs(struct thermal_zone_device *tz) + kfree(hwmon); + } + EXPORT_SYMBOL_GPL(thermal_remove_hwmon_sysfs); ++ ++static void devm_thermal_hwmon_release(struct device *dev, void *res) ++{ ++ thermal_remove_hwmon_sysfs(*(struct thermal_zone_device **)res); ++} ++ ++int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz) ++{ ++ struct thermal_zone_device **ptr; ++ int ret; ++ ++ ptr = devres_alloc(devm_thermal_hwmon_release, sizeof(*ptr), ++ GFP_KERNEL); ++ if (!ptr) ++ return -ENOMEM; ++ ++ ret = thermal_add_hwmon_sysfs(tz); ++ if (ret) { ++ devres_free(ptr); ++ return ret; ++ } ++ ++ *ptr = tz; ++ devres_add(&tz->device, ptr); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(devm_thermal_add_hwmon_sysfs); +diff --git a/drivers/thermal/thermal_hwmon.h b/drivers/thermal/thermal_hwmon.h +index a160b9d62dd0a..1a9d65f6a6a8b 100644 +--- a/drivers/thermal/thermal_hwmon.h ++++ b/drivers/thermal/thermal_hwmon.h +@@ -17,6 +17,7 @@ + + #ifdef CONFIG_THERMAL_HWMON + int thermal_add_hwmon_sysfs(struct thermal_zone_device *tz); ++int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz); + void thermal_remove_hwmon_sysfs(struct thermal_zone_device *tz); + #else + static inline int +@@ -25,6 +26,12 @@ thermal_add_hwmon_sysfs(struct thermal_zone_device *tz) + return 0; + } + ++static inline int ++devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz) ++{ ++ return 0; ++} ++ + static inline void + thermal_remove_hwmon_sysfs(struct thermal_zone_device *tz) + { diff --git a/target/linux/sunxi/patches-5.4/012-thermal-drivers-sun8i-Add-thermal-driver.patch b/target/linux/sunxi/patches-5.4/012-thermal-drivers-sun8i-Add-thermal-driver.patch new file mode 100644 index 0000000000..e61d616a83 --- /dev/null +++ b/target/linux/sunxi/patches-5.4/012-thermal-drivers-sun8i-Add-thermal-driver.patch @@ -0,0 +1,61 @@ +From dccc5c3b6f30f27ed0f1bea82221e18face20bef Mon Sep 17 00:00:00 2001 +From: Yangtao Li +Date: Thu, 19 Dec 2019 09:28:17 -0800 +Subject: [PATCH] thermal/drivers/sun8i: Add thermal driver for + H6/H5/H3/A64/A83T/R40 + +This patch adds the support for allwinner thermal sensor, within +allwinner SoC. It will register sensors for thermal framework +and use device tree to bind cooling device. + +Signed-off-by: Yangtao Li +Signed-off-by: Ondrej Jirman +Signed-off-by: Vasily Khoruzhick +Acked-by: Maxime Ripard +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20191219172823.1652600-2-anarsoul@gmail.com +--- + MAINTAINERS | 8 + + drivers/thermal/Kconfig | 14 + + drivers/thermal/Makefile | 1 + + drivers/thermal/sun8i_thermal.c | 639 ++++++++++++++++++++++++++++++++ + 4 files changed, 662 insertions(+) + create mode 100644 drivers/thermal/sun8i_thermal.c + +diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig +index dc36941aef6e5..5a05db5438d60 100644 +--- a/drivers/thermal/Kconfig ++++ b/drivers/thermal/Kconfig +@@ -262,6 +262,20 @@ config SPEAR_THERMAL + Enable this to plug the SPEAr thermal sensor driver into the Linux + thermal framework. + ++config SUN8I_THERMAL ++ tristate "Allwinner sun8i thermal driver" ++ depends on ARCH_SUNXI || COMPILE_TEST ++ depends on HAS_IOMEM ++ depends on NVMEM ++ depends on OF ++ depends on RESET_CONTROLLER ++ help ++ Support for the sun8i thermal sensor driver into the Linux thermal ++ framework. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called sun8i-thermal. ++ + config ROCKCHIP_THERMAL + tristate "Rockchip thermal driver" + depends on ARCH_ROCKCHIP || COMPILE_TEST +diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile +index d502a597a7174..9fb88e26fb102 100644 +--- a/drivers/thermal/Makefile ++++ b/drivers/thermal/Makefile +@@ -31,6 +31,7 @@ thermal_sys-$(CONFIG_DEVFREQ_THERMAL) += devfreq_cooling.o + obj-y += broadcom/ + obj-$(CONFIG_THERMAL_MMIO) += thermal_mmio.o + obj-$(CONFIG_SPEAR_THERMAL) += spear_thermal.o ++obj-$(CONFIG_SUN8I_THERMAL) += sun8i_thermal.o + obj-$(CONFIG_ROCKCHIP_THERMAL) += rockchip_thermal.o + obj-$(CONFIG_RCAR_THERMAL) += rcar_thermal.o + obj-$(CONFIG_RCAR_GEN3_THERMAL) += rcar_gen3_thermal.o diff --git a/target/linux/sunxi/patches-5.4/013-ARM-dts-sun8i-h3-Add-thermal-sensor-and-thermal-zones.patch b/target/linux/sunxi/patches-5.4/013-ARM-dts-sun8i-h3-Add-thermal-sensor-and-thermal-zones.patch new file mode 100644 index 0000000000..4c87ba535f --- /dev/null +++ b/target/linux/sunxi/patches-5.4/013-ARM-dts-sun8i-h3-Add-thermal-sensor-and-thermal-zones.patch @@ -0,0 +1,63 @@ +From b37da9c8e62ef8ea14c19d40837dcd5beb8470e6 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Thu, 19 Dec 2019 09:28:20 -0800 +Subject: [PATCH] ARM: dts: sun8i-h3: Add thermal sensor and thermal zones + +There is just one sensor for the CPU. + +Signed-off-by: Ondrej Jirman +Signed-off-by: Vasily Khoruzhick +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/sun8i-h3.dtsi | 20 ++++++++++++++++++++ + arch/arm/boot/dts/sunxi-h3-h5.dtsi | 6 ++++++ + 2 files changed, 26 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi +index b4f1673df9ee0..20217e2ca4d3a 100644 +--- a/arch/arm/boot/dts/sun8i-h3.dtsi ++++ b/arch/arm/boot/dts/sun8i-h3.dtsi +@@ -186,6 +186,26 @@ + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; ++ ++ ths: thermal-sensor@1c25000 { ++ compatible = "allwinner,sun8i-h3-ths"; ++ reg = <0x01c25000 0x400>; ++ interrupts = ; ++ resets = <&ccu RST_BUS_THS>; ++ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; ++ clock-names = "bus", "mod"; ++ nvmem-cells = <&ths_calibration>; ++ nvmem-cell-names = "calibration"; ++ #thermal-sensor-cells = <0>; ++ }; ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 0>; ++ }; + }; + }; + +diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi +index 0afea59486c24..6e68ed8310159 100644 +--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi ++++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi +@@ -230,6 +230,12 @@ + sid: eeprom@1c14000 { + /* compatible is in per SoC .dtsi file */ + reg = <0x1c14000 0x400>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ ths_calibration: thermal-sensor-calibration@34 { ++ reg = <0x34 4>; ++ }; + }; + + usb_otg: usb@1c19000 { diff --git a/target/linux/sunxi/patches-5.4/014-ARM-dts-sun8i-h3-Add-thermal-trip-points-cooling-maps.patch b/target/linux/sunxi/patches-5.4/014-ARM-dts-sun8i-h3-Add-thermal-trip-points-cooling-maps.patch new file mode 100644 index 0000000000..b57f97368e --- /dev/null +++ b/target/linux/sunxi/patches-5.4/014-ARM-dts-sun8i-h3-Add-thermal-trip-points-cooling-maps.patch @@ -0,0 +1,68 @@ +From 7ad9f3d0cb2f2b886c068f99e791bd41ceb0677a Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Mon, 24 Feb 2020 17:54:46 +0100 +Subject: [PATCH] ARM: dts: sun8i-h3: Add thermal trip points/cooling maps +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This enables passive cooling by down-regulating CPU voltage +and frequency. + +For trip points, I used a slightly lowered values from the BSP +code. The critical temperature of 110°C from BSP code seemed +like a lot, so I rounded it off to 100°C. + +The critical trip point value is 30°C above the maximum recommended +ambient temperature (70°C) for the SoC from the datasheet, so there's +some headroom even at such a high ambient temperature. + +Signed-off-by: Ondrej Jirman +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/sun8i-h3.dtsi | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi +index 20217e2ca4d3a..e83aa6866e7ea 100644 +--- a/arch/arm/boot/dts/sun8i-h3.dtsi ++++ b/arch/arm/boot/dts/sun8i-h3.dtsi +@@ -41,6 +41,7 @@ + */ + + #include "sunxi-h3-h5.dtsi" ++#include + + / { + cpu0_opp_table: opp_table0 { +@@ -205,6 +206,30 @@ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; ++ ++ trips { ++ cpu_hot: cpu-hot { ++ temperature = <80000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_very_hot: cpu-very-hot { ++ temperature = <100000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ cpu-hot-limit { ++ trip = <&cpu_hot>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; + }; + }; + }; diff --git a/target/linux/sunxi/patches-5.4/015-arm64-dts-allwinner-h5-Add-thermal-sensor-and-thermal.patch b/target/linux/sunxi/patches-5.4/015-arm64-dts-allwinner-h5-Add-thermal-sensor-and-thermal.patch new file mode 100644 index 0000000000..10729bc010 --- /dev/null +++ b/target/linux/sunxi/patches-5.4/015-arm64-dts-allwinner-h5-Add-thermal-sensor-and-thermal.patch @@ -0,0 +1,52 @@ +From 9ad42557109a9db9ca16964352c3c045a775b018 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Thu, 19 Dec 2019 09:28:21 -0800 +Subject: [PATCH] arm64: dts: allwinner: h5: Add thermal sensor and thermal + zones + +There are two sensors, one for CPU, one for GPU. + +Signed-off-by: Ondrej Jirman +Signed-off-by: Vasily Khoruzhick +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 26 ++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +index 3e724788dd3e6..9893aa64dd0b9 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +@@ -174,6 +174,32 @@ + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; ++ ++ ths: thermal-sensor@1c25000 { ++ compatible = "allwinner,sun50i-h5-ths"; ++ reg = <0x01c25000 0x400>; ++ interrupts = ; ++ resets = <&ccu RST_BUS_THS>; ++ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; ++ clock-names = "bus", "mod"; ++ nvmem-cells = <&ths_calibration>; ++ nvmem-cell-names = "calibration"; ++ #thermal-sensor-cells = <1>; ++ }; ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 0>; ++ }; ++ ++ gpu_thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 1>; ++ }; + }; + }; + diff --git a/target/linux/sunxi/patches-5.4/016-arm64-dts-allwinner-h5-Add-clock-to-CPU-cores.patch b/target/linux/sunxi/patches-5.4/016-arm64-dts-allwinner-h5-Add-clock-to-CPU-cores.patch new file mode 100644 index 0000000000..4a16442673 --- /dev/null +++ b/target/linux/sunxi/patches-5.4/016-arm64-dts-allwinner-h5-Add-clock-to-CPU-cores.patch @@ -0,0 +1,56 @@ +From 5fa21c1354c93cb9fe8239545b17eee46e39dd69 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Sat, 18 Jul 2020 00:00:49 +0800 +Subject: [PATCH] arm64: dts: allwinner: h5: Add clock to CPU cores + +The ARM CPU cores are fed by the CPU clock from the CCU. Add a +reference to the clock for each CPU core, along with the clock +transition latency. + +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Maxime Ripard +Link: https://lore.kernel.org/r/20200717160053.31191-5-wens@kernel.org +--- + arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +index 4462a68c06815..09523f6011c5e 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +@@ -52,6 +52,8 @@ + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + cpu1: cpu@1 { +@@ -59,6 +61,8 @@ + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + cpu2: cpu@2 { +@@ -66,6 +70,8 @@ + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + cpu3: cpu@3 { +@@ -73,6 +79,8 @@ + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + diff --git a/target/linux/sunxi/patches-5.4/017-arm64-dts-allwinner-h5-Add-trip-and-cooling-maps.patch b/target/linux/sunxi/patches-5.4/017-arm64-dts-allwinner-h5-Add-trip-and-cooling-maps.patch new file mode 100644 index 0000000000..82dc8178e1 --- /dev/null +++ b/target/linux/sunxi/patches-5.4/017-arm64-dts-allwinner-h5-Add-trip-and-cooling-maps.patch @@ -0,0 +1,92 @@ +From d04f7bc8842c0d9951a5740480f864a4f82d6b63 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Sat, 18 Jul 2020 00:00:50 +0800 +Subject: [PATCH] arm64: dts: allwinner: h5: Add trip and cooling maps to CPU + thermal zones + +This enables passive cooling by down-regulating CPU voltage and frequency. +The trip points were copied from the H3. + +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Maxime Ripard +Link: https://lore.kernel.org/r/20200717160053.31191-6-wens@kernel.org +--- + arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 30 ++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +index 09523f6011c5e..6735e316a39c3 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +@@ -42,6 +42,8 @@ + + #include + ++#include ++ + / { + cpus { + #address-cells = <1>; +@@ -54,6 +56,7 @@ + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + + cpu1: cpu@1 { +@@ -63,6 +66,7 @@ + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + + cpu2: cpu@2 { +@@ -72,6 +76,7 @@ + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + + cpu3: cpu@3 { +@@ -81,6 +86,7 @@ + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + }; + +@@ -201,6 +207,30 @@ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; ++ ++ trips { ++ cpu_hot_trip: cpu-hot { ++ temperature = <80000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_very_hot_trip: cpu-very-hot { ++ temperature = <100000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ cpu-hot-limit { ++ trip = <&cpu_hot_trip>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; + }; + + gpu_thermal { diff --git a/target/linux/sunxi/patches-5.4/018-arm64-dts-allwinner-h5-Add-CPU-Operating-Performance-Points-table.patch b/target/linux/sunxi/patches-5.4/018-arm64-dts-allwinner-h5-Add-CPU-Operating-Performance-Points-table.patch new file mode 100644 index 0000000000..25292f438d --- /dev/null +++ b/target/linux/sunxi/patches-5.4/018-arm64-dts-allwinner-h5-Add-CPU-Operating-Performance-Points-table.patch @@ -0,0 +1,113 @@ +From 7240598ba4e6c477c6809dc019505cf366fdb7c0 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Sat, 18 Jul 2020 00:00:51 +0800 +Subject: [PATCH] arm64: dts: allwinner: h5: Add CPU Operating Performance + Points table + +Add an OPP (Operating Performance Points) table for the CPU cores for +boards to include to DVFS (Dynamic Voltage & Frequency Scaling) on the +H5. The table originates from Armbian, but the maximum voltage is raised +slightly to account for boards using slightly higher voltages. + +The table and tie in to the CPU cores are put in a separate dtsi file +that board files can include to opt in. Or they can define their own +tables if the standard one does not fit. + +This has been tested on the Libre Computer ALL-H3-CC-H5 and the Bananapi +M2+ v1.2 H5, both with adequate cooling. The former has a fixed 1.2V +regulator, while the latter has a GPIO controlled regulator switchable +between 1.1V and 1.3V. + +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Maxime Ripard +Link: https://lore.kernel.org/r/20200717160053.31191-7-wens@kernel.org +--- + .../boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi | 79 +++++++++++++++++++ + 1 file changed, 79 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi +new file mode 100644 +index 0000000000000..b2657201957eb +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi +@@ -0,0 +1,79 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2020 Chen-Yu Tsai ++ ++/ { ++ cpu_opp_table: cpu-opp-table { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <1000000 1000000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-648000000 { ++ opp-hz = /bits/ 64 <648000000>; ++ opp-microvolt = <1040000 1040000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <1080000 1080000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-912000000 { ++ opp-hz = /bits/ 64 <912000000>; ++ opp-microvolt = <1120000 1120000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-960000000 { ++ opp-hz = /bits/ 64 <960000000>; ++ opp-microvolt = <1160000 1160000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1200000 1200000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1056000000 { ++ opp-hz = /bits/ 64 <1056000000>; ++ opp-microvolt = <1240000 1240000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <1260000 1260000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1152000000 { ++ opp-hz = /bits/ 64 <1152000000>; ++ opp-microvolt = <1300000 1300000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ }; ++}; ++ ++&cpu0 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu1 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu2 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu3 { ++ operating-points-v2 = <&cpu_opp_table>; ++};