ipq40xx: 5.4: refresh patches
This commit is contained in:
AmadeusGhost
parent
d7ccf4a3dc
commit
138d9a3926
@ -1,111 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright (c) 2019 Mantas Pucka <mantas@8devices.com>
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// Copyright (c) 2019 Robert Marko <robimarko@gmail.com>
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//
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// Driver for IPQ4019 SD/MMC controller's I/O LDO voltage regulator
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/of_regulator.h>
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static const unsigned int ipq4019_vmmc_voltages[] = {
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1500000, 1800000, 2500000, 3000000,
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};
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static struct regulator_ops ipq4019_regulator_voltage_ops = {
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.list_voltage = regulator_list_voltage_table,
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.get_voltage_sel = regulator_get_voltage_sel_regmap,
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.set_voltage_sel = regulator_set_voltage_sel_regmap,
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};
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static struct regulator_desc vmmc_regulator = {
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.name = "vmmcq",
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.ops = &ipq4019_regulator_voltage_ops,
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.type = REGULATOR_VOLTAGE,
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.owner = THIS_MODULE,
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.volt_table = ipq4019_vmmc_voltages,
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.n_voltages = ARRAY_SIZE(ipq4019_vmmc_voltages),
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.vsel_reg = 0,
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.vsel_mask = 0x3,
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};
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const struct regmap_config ipq4019_vmmcq_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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};
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static int ipq4019_regulator_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct regulator_init_data *init_data;
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struct regulator_config cfg = {};
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struct regulator_dev *rdev;
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struct resource *res;
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struct regmap *rmap;
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void __iomem *base;
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init_data = of_get_regulator_init_data(dev, dev->of_node,
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&vmmc_regulator);
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if (!init_data)
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return -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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rmap = devm_regmap_init_mmio(dev, base, &ipq4019_vmmcq_regmap_config);
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if (IS_ERR(rmap))
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return PTR_ERR(rmap);
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cfg.dev = dev;
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cfg.init_data = init_data;
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cfg.of_node = dev->of_node;
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cfg.regmap = rmap;
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rdev = devm_regulator_register(dev, &vmmc_regulator, &cfg);
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if (IS_ERR(rdev)) {
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dev_err(dev, "Failed to register regulator: %ld\n",
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PTR_ERR(rdev));
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return PTR_ERR(rdev);
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}
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platform_set_drvdata(pdev, rdev);
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return 0;
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}
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static int ipq4019_regulator_remove(struct platform_device *pdev)
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{
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struct regulator_dev *rdev = platform_get_drvdata(pdev);
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regulator_unregister(rdev);
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return 0;
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}
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static const struct of_device_id regulator_ipq4019_of_match[] = {
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{ .compatible = "qcom,ipq4019-vqmmc-regulator", },
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{},
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};
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static struct platform_driver ipq4019_regulator_driver = {
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.probe = ipq4019_regulator_probe,
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.remove = ipq4019_regulator_remove,
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.driver = {
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.name = "regulator-vqmmc-ipq4019",
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(regulator_ipq4019_of_match),
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},
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};
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module_platform_driver(ipq4019_regulator_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Mantas Pucka <mantas@8devices.com>");
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MODULE_DESCRIPTION("IPQ4019 VQMMC voltage regulator");
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@ -26,7 +26,7 @@
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obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o
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--- /dev/null
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+++ b/drivers/net/phy/ar40xx.c
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@@ -0,0 +1,2123 @@
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@@ -0,0 +1,2122 @@
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+/*
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+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
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+ *
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@ -0,0 +1,205 @@
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diff --git a/drivers/net/ethernet/qualcomm/essedma/edma.c b/drivers/net/ethernet/qualcomm/essedma/edma.c
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index 724f355..7a16236 100644
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--- a/drivers/net/ethernet/qualcomm/essedma/edma.c
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+++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
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@@ -22,14 +22,6 @@ extern struct net_device *edma_netdev[EDMA_MAX_PORTID_SUPPORTED];
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bool edma_stp_rstp;
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u16 edma_ath_eth_type;
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-/* edma_skb_priority_offset()
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- * get edma skb priority
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- */
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-static unsigned int edma_skb_priority_offset(struct sk_buff *skb)
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-{
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- return (skb->priority >> 2) & 1;
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-}
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-
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/* edma_alloc_tx_ring()
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* Allocate Tx descriptors ring
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*/
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@@ -1014,13 +1006,14 @@ static inline u16 edma_tpd_available(struct edma_common_info *edma_cinfo,
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/* edma_tx_queue_get()
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* Get the starting number of the queue
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*/
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-static inline int edma_tx_queue_get(struct edma_adapter *adapter,
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+static inline int edma_tx_queue_get(struct edma_common_info *edma_cinfo, struct edma_adapter *adapter,
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struct sk_buff *skb, int txq_id)
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{
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/* skb->priority is used as an index to skb priority table
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* and based on packet priority, correspong queue is assigned.
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+ * FIXME we just simple use jiffies for time base balance
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*/
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- return adapter->tx_start_offset[txq_id] + edma_skb_priority_offset(skb);
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+ return adapter->tx_start_offset[txq_id] + (smp_processor_id() % edma_cinfo->num_txq_per_core_netdev);
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}
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/* edma_tx_update_hw_idx()
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@@ -1389,8 +1382,9 @@ netdev_tx_t edma_xmit(struct sk_buff *skb,
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}
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/* this will be one of the 4 TX queues exposed to linux kernel */
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- txq_id = skb_get_queue_mapping(skb);
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- queue_id = edma_tx_queue_get(adapter, skb, txq_id);
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+ /* XXX what if num_online_cpus() > EDMA_CPU_CORES_SUPPORTED */
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+ txq_id = ((jiffies >> 5) % (EDMA_CPU_CORES_SUPPORTED - 1) + smp_processor_id() + 1) % EDMA_CPU_CORES_SUPPORTED;
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+ queue_id = edma_tx_queue_get(edma_cinfo, adapter, skb, txq_id);
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etdr = edma_cinfo->tpd_ring[queue_id];
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nq = netdev_get_tx_queue(net_dev, txq_id);
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@@ -1871,8 +1865,8 @@ void edma_free_irqs(struct edma_adapter *adapter)
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int i, j;
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int k = ((edma_cinfo->num_rx_queues == 4) ? 1 : 2);
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- for (i = 0; i < CONFIG_NR_CPUS; i++) {
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- for (j = edma_cinfo->edma_percpu_info[i].tx_start; j < (edma_cinfo->edma_percpu_info[i].tx_start + 4); j++)
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+ for (i = 0; i < num_online_cpus() && i < EDMA_CPU_CORES_SUPPORTED; i++) {
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+ for (j = edma_cinfo->edma_percpu_info[i].tx_start; j < (edma_cinfo->edma_percpu_info[i].tx_start + edma_cinfo->num_txq_per_core); j++)
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free_irq(edma_cinfo->tx_irq[j], &edma_cinfo->edma_percpu_info[i]);
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for (j = edma_cinfo->edma_percpu_info[i].rx_start; j < (edma_cinfo->edma_percpu_info[i].rx_start + k); j++)
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diff --git a/drivers/net/ethernet/qualcomm/essedma/edma.h b/drivers/net/ethernet/qualcomm/essedma/edma.h
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index 015e5f5..abb0bd5 100644
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--- a/drivers/net/ethernet/qualcomm/essedma/edma.h
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+++ b/drivers/net/ethernet/qualcomm/essedma/edma.h
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@@ -324,6 +324,7 @@ struct edma_common_info {
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u32 from_cpu; /* from CPU TPD field */
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u32 num_rxq_per_core; /* Rx queues per core */
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u32 num_txq_per_core; /* Tx queues per core */
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+ u32 num_txq_per_core_netdev; /* Tx queues per core per netdev */
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u16 tx_ring_count; /* Tx ring count */
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u16 rx_ring_count; /* Rx ring*/
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u16 rx_head_buffer_len; /* rx buffer length */
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@@ -331,7 +332,7 @@ struct edma_common_info {
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u32 page_mode; /* Jumbo frame supported flag */
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u32 fraglist_mode; /* fraglist supported flag */
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struct edma_hw hw; /* edma hw specific structure */
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- struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */
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+ struct edma_per_cpu_queues_info edma_percpu_info[EDMA_CPU_CORES_SUPPORTED]; /* per cpu information */
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spinlock_t stats_lock; /* protect edma stats area for updation */
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struct timer_list edma_stats_timer;
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bool is_single_phy;
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@@ -401,7 +402,7 @@ struct edma_adapter {
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u32 link_state; /* phy link state */
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u32 phy_mdio_addr; /* PHY device address on MII interface */
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u32 poll_required; /* check if link polling is required */
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- u32 tx_start_offset[CONFIG_NR_CPUS]; /* tx queue start */
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+ u32 tx_start_offset[EDMA_CPU_CORES_SUPPORTED]; /* tx queue start */
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u32 default_vlan_tag; /* vlan tag */
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u32 dp_bitmap;
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uint8_t phy_id[MII_BUS_ID_SIZE + 3];
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diff --git a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
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index d53c63b..2d4770c 100644
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--- a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
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+++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
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@@ -719,11 +719,7 @@ static int edma_axi_probe(struct platform_device *pdev)
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int i, j, k, err = 0;
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int portid_bmp;
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int idx = 0, idx_mac = 0;
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-
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- if (CONFIG_NR_CPUS != EDMA_CPU_CORES_SUPPORTED) {
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- dev_err(&pdev->dev, "Invalid CPU Cores\n");
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- return -EINVAL;
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- }
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+ int netdev_group = 2;
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if ((num_rxq != 4) && (num_rxq != 8)) {
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dev_err(&pdev->dev, "Invalid RX queue, edma probe failed\n");
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@@ -747,7 +743,7 @@ static int edma_axi_probe(struct platform_device *pdev)
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/* Initialize the netdev array before allocation
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* to avoid double free
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*/
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- for (i = 0 ; i < edma_cinfo->num_gmac ; i++)
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+ for (i = 0 ; i < EDMA_MAX_PORTID_SUPPORTED; i++)
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edma_netdev[i] = NULL;
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for (i = 0 ; i < edma_cinfo->num_gmac ; i++) {
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@@ -768,8 +764,11 @@ static int edma_axi_probe(struct platform_device *pdev)
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/* Fill ring details */
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edma_cinfo->num_tx_queues = EDMA_MAX_TRANSMIT_QUEUE;
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- edma_cinfo->num_txq_per_core = (EDMA_MAX_TRANSMIT_QUEUE / 4);
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+ edma_cinfo->num_txq_per_core = (EDMA_MAX_TRANSMIT_QUEUE / num_online_cpus());
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+ edma_cinfo->num_txq_per_core_netdev = (EDMA_MAX_TRANSMIT_QUEUE / netdev_group / num_online_cpus());
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edma_cinfo->tx_ring_count = EDMA_TX_RING_SIZE;
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+ if (edma_cinfo->num_txq_per_core == 0)
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+ edma_cinfo->num_txq_per_core = 1;
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/* Update num rx queues based on module parameter */
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edma_cinfo->num_rx_queues = num_rxq;
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@@ -939,6 +938,13 @@ static int edma_axi_probe(struct platform_device *pdev)
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idx_mac++;
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}
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+ if (edma_cinfo->num_gmac == 1) {
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+ netdev_group = 1;
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+ edma_cinfo->num_txq_per_core_netdev = (EDMA_MAX_TRANSMIT_QUEUE / netdev_group / num_online_cpus());
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+ }
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+ if (edma_cinfo->num_txq_per_core_netdev == 0)
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+ edma_cinfo->num_txq_per_core_netdev = 1;
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+
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/* Populate the adapter structure register the netdevice */
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for (i = 0; i < edma_cinfo->num_gmac; i++) {
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int k, m;
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@@ -946,17 +952,16 @@ static int edma_axi_probe(struct platform_device *pdev)
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adapter[i] = netdev_priv(edma_netdev[i]);
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adapter[i]->netdev = edma_netdev[i];
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adapter[i]->pdev = pdev;
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- for (j = 0; j < CONFIG_NR_CPUS; j++) {
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- m = i % 2;
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- adapter[i]->tx_start_offset[j] =
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- ((j << EDMA_TX_CPU_START_SHIFT) + (m << 1));
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+ for (j = 0; j < num_online_cpus() && j < EDMA_CPU_CORES_SUPPORTED; j++) {
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+ m = i % netdev_group;
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+ adapter[i]->tx_start_offset[j] = j * edma_cinfo->num_txq_per_core + m * edma_cinfo->num_txq_per_core_netdev;
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/* Share the queues with available net-devices.
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* For instance , with 5 net-devices
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* eth0/eth2/eth4 will share q0,q1,q4,q5,q8,q9,q12,q13
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* and eth1/eth3 will get the remaining.
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*/
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for (k = adapter[i]->tx_start_offset[j]; k <
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- (adapter[i]->tx_start_offset[j] + 2); k++) {
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+ (adapter[i]->tx_start_offset[j] + edma_cinfo->num_txq_per_core_netdev); k++) {
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if (edma_fill_netdev(edma_cinfo, k, i, j)) {
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pr_err("Netdev overflow Error\n");
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goto err_register;
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@@ -1109,9 +1114,12 @@ static int edma_axi_probe(struct platform_device *pdev)
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/* populate per_core_info, do a napi_Add, request 16 TX irqs,
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* 8 RX irqs, do a napi enable
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*/
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- for (i = 0; i < CONFIG_NR_CPUS; i++) {
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+ for (i = 0; i < num_online_cpus() && i < EDMA_CPU_CORES_SUPPORTED; i++) {
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u8 rx_start;
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+ tx_mask[i] = (0xFFFF >> (16 - edma_cinfo->num_txq_per_core)) << (i * edma_cinfo->num_txq_per_core);
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+ tx_start[i] = i * edma_cinfo->num_txq_per_core;
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+
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edma_cinfo->edma_percpu_info[i].napi.state = 0;
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netif_napi_add(edma_netdev[0],
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@@ -1131,7 +1139,7 @@ static int edma_axi_probe(struct platform_device *pdev)
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/* Request irq per core */
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for (j = edma_cinfo->edma_percpu_info[i].tx_start;
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- j < tx_start[i] + 4; j++) {
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+ j < tx_start[i] + edma_cinfo->num_txq_per_core; j++) {
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sprintf(&edma_tx_irq[j][0], "edma_eth_tx%d", j);
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err = request_irq(edma_cinfo->tx_irq[j],
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edma_interrupt,
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@@ -1253,7 +1261,7 @@ static int edma_axi_probe(struct platform_device *pdev)
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#endif
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err_rmap_add_fail:
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edma_free_irqs(adapter[0]);
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- for (i = 0; i < CONFIG_NR_CPUS; i++)
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+ for (i = 0; i < num_online_cpus() && i < EDMA_CPU_CORES_SUPPORTED; i++)
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napi_disable(&edma_cinfo->edma_percpu_info[i].napi);
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err_reset:
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err_unregister_sysctl_tbl:
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@@ -1301,7 +1309,7 @@ static int edma_axi_remove(struct platform_device *pdev)
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unregister_netdev(edma_netdev[i]);
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edma_stop_rx_tx(hw);
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- for (i = 0; i < CONFIG_NR_CPUS; i++)
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+ for (i = 0; i < num_online_cpus() && i < EDMA_CPU_CORES_SUPPORTED; i++)
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napi_disable(&edma_cinfo->edma_percpu_info[i].napi);
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edma_irq_disable(edma_cinfo);
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@ -0,0 +1,54 @@
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diff --git a/drivers/net/ethernet/qualcomm/essedma/edma.c b/drivers/net/ethernet/qualcomm/essedma/edma.c
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index fc274c8..e9d12a4 100644
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--- a/drivers/net/ethernet/qualcomm/essedma/edma.c
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+++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
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@@ -2075,15 +2075,13 @@ int edma_poll(struct napi_struct *napi, int budget)
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int i, work_done = 0;
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u16 rx_pending_fill;
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- /* Store the Rx/Tx status by ANDing it with
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- * appropriate CPU RX?TX mask
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+ /* Store the Tx status by ANDing it with
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+ * appropriate CPU TX mask
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*/
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- edma_read_reg(EDMA_REG_RX_ISR, ®_data);
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- edma_percpu_info->rx_status |= reg_data & edma_percpu_info->rx_mask;
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- shadow_rx_status = edma_percpu_info->rx_status;
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edma_read_reg(EDMA_REG_TX_ISR, ®_data);
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edma_percpu_info->tx_status |= reg_data & edma_percpu_info->tx_mask;
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shadow_tx_status = edma_percpu_info->tx_status;
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+ edma_write_reg(EDMA_REG_TX_ISR, shadow_tx_status);
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/* Every core will have a start, which will be computed
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* in probe and stored in edma_percpu_info->tx_start variable.
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@@ -2098,6 +2096,14 @@ int edma_poll(struct napi_struct *napi, int budget)
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edma_percpu_info->tx_status &= ~(1 << queue_id);
|
||||
}
|
||||
|
||||
+ /* Store the Rx status by ANDing it with
|
||||
+ * appropriate CPU RX mask
|
||||
+ */
|
||||
+ edma_read_reg(EDMA_REG_RX_ISR, ®_data);
|
||||
+ edma_percpu_info->rx_status |= reg_data & edma_percpu_info->rx_mask;
|
||||
+ shadow_rx_status = edma_percpu_info->rx_status;
|
||||
+ edma_write_reg(EDMA_REG_RX_ISR, shadow_rx_status);
|
||||
+
|
||||
/* Every core will have a start, which will be computed
|
||||
* in probe and stored in edma_percpu_info->tx_start variable.
|
||||
* We will shift the status bit by tx_start to obtain
|
||||
@@ -2122,15 +2128,6 @@ int edma_poll(struct napi_struct *napi, int budget)
|
||||
}
|
||||
}
|
||||
|
||||
- /* Clear the status register, to avoid the interrupts to
|
||||
- * reoccur.This clearing of interrupt status register is
|
||||
- * done here as writing to status register only takes place
|
||||
- * once the producer/consumer index has been updated to
|
||||
- * reflect that the packet transmission/reception went fine.
|
||||
- */
|
||||
- edma_write_reg(EDMA_REG_RX_ISR, shadow_rx_status);
|
||||
- edma_write_reg(EDMA_REG_TX_ISR, shadow_tx_status);
|
||||
-
|
||||
/* If budget not fully consumed, exit the polling mode */
|
||||
if (likely(work_done < budget)) {
|
||||
napi_complete(napi);
|
||||
@ -1,26 +0,0 @@
|
||||
--- a/drivers/regulator/Kconfig
|
||||
+++ b/drivers/regulator/Kconfig
|
||||
@@ -334,6 +334,13 @@ config REGULATOR_HI655X
|
||||
This driver provides support for the voltage regulators of the
|
||||
Hisilicon Hi655x PMIC device.
|
||||
|
||||
+config REGULATOR_VQMMC_IPQ4019
|
||||
+ tristate "IPQ4019 VQMMC SD LDO regulator support"
|
||||
+ depends on ARCH_QCOM
|
||||
+ help
|
||||
+ This driver provides support for the VQMMC LDO I/0
|
||||
+ voltage regulator of the IPQ4019 SD/EMMC controller.
|
||||
+
|
||||
config REGULATOR_ISL9305
|
||||
tristate "Intersil ISL9305 regulator"
|
||||
depends on I2C
|
||||
--- a/drivers/regulator/Makefile
|
||||
+++ b/drivers/regulator/Makefile
|
||||
@@ -43,6 +43,7 @@ obj-$(CONFIG_REGULATOR_GPIO) += gpio-reg
|
||||
obj-$(CONFIG_REGULATOR_HI6421) += hi6421-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_HI6421V530) += hi6421v530-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_HI655X) += hi655x-regulator.o
|
||||
+obj-$(CONFIG_REGULATOR_VQMMC_IPQ4019) += ipq4019-vqmmc-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_ISL9305) += isl9305.o
|
||||
obj-$(CONFIG_REGULATOR_LM363X) += lm363x-regulator.o
|
||||
@ -1,33 +0,0 @@
|
||||
From beae4078c07d3cdc90473a2b35eb0d2b4f3c922c Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Sat, 14 Sep 2019 23:13:17 +0200
|
||||
Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI VQMMC LDO regulator node
|
||||
|
||||
IPQ4019 has a built in SD/eMMC controller which depends on
|
||||
VQMMC LDO regulator working.
|
||||
Since we have a driver for it lets add the appropriate node for it.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -216,6 +216,16 @@
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
+ vqmmc: regulator@1948000 {
|
||||
+ compatible = "qcom,ipq4019-vqmmc-regulator";
|
||||
+ reg = <0x01948000 0x4>;
|
||||
+ regulator-name = "vqmmc";
|
||||
+ regulator-min-microvolt = <1500000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-always-on;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
blsp_dma: dma@7884000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07884000 0x23000>;
|
||||
@ -1,41 +0,0 @@
|
||||
Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI controller node
|
||||
Date: Thu, 15 Aug 2019 19:28:23 +0200
|
||||
Message-Id: <20190815172823.12028-1-robimarko@gmail.com>
|
||||
X-Mailer: git-send-email 2.21.0
|
||||
MIME-Version: 1.0
|
||||
Sender: linux-arm-msm-owner@vger.kernel.org
|
||||
Precedence: bulk
|
||||
List-ID: <linux-arm-msm.vger.kernel.org>
|
||||
X-Mailing-List: linux-arm-msm@vger.kernel.org
|
||||
X-Virus-Scanned: ClamAV using ClamSMTP
|
||||
|
||||
IPQ4019 has a built in SD/eMMC controller which is supported by the
|
||||
SDHCI MSM driver, by the "qcom,sdhci-msm-v4" binding.
|
||||
So lets add the appropriate node for it.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -226,6 +226,18 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ sdhci: sdhci@7824900 {
|
||||
+ compatible = "qcom,sdhci-msm-v4";
|
||||
+ reg = <0x7824900 0x11c>, <0x7824000 0x800>;
|
||||
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "hc_irq", "pwr_irq";
|
||||
+ bus-width = <8>;
|
||||
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
|
||||
+ <&gcc GCC_DCD_XO_CLK>;
|
||||
+ clock-names = "core", "iface", "xo";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
blsp_dma: dma@7884000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07884000 0x23000>;
|
||||
@ -0,0 +1,82 @@
|
||||
From 42b508d91b7f51b054f383e3aa42089ccab9300d Mon Sep 17 00:00:00 2001
|
||||
From: Chen Minqiang <ptpt52@gmail.com>
|
||||
Date: Thu, 15 Mar 2018 05:33:46 +0800
|
||||
Subject: [PATCH] essedma: disable default vlan tagging
|
||||
|
||||
The essedma driver has its own unique take on VLAN management
|
||||
and its configuration. In the original SDK, each VLAN is
|
||||
assigned one virtual ethernet netdev.
|
||||
|
||||
However, this is non-standard. So, this patch does away
|
||||
with the default_vlan_tag property the driver is using
|
||||
and therefore forces the user to use the kernel's vlan
|
||||
feature.
|
||||
|
||||
This patch also removes the "qcom,poll_required = <1>;" from
|
||||
the essedma node.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
|
||||
Signed-off-by: Chen Minqiang <ptpt52@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 5 ++---
|
||||
drivers/net/ethernet/qualcomm/essedma/edma.c | 14 +++++---------
|
||||
2 files changed, 7 insertions(+), 12 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
index 3c4617f..7c3af8e 100644
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -598,8 +598,7 @@
|
||||
qcom,page-mode = <0>;
|
||||
qcom,rx_head_buf_size = <1540>;
|
||||
qcom,mdio_supported;
|
||||
- qcom,poll_required = <1>;
|
||||
- qcom,num_gmac = <2>;
|
||||
+ qcom,num_gmac = <1>;
|
||||
interrupts = <0 65 IRQ_TYPE_EDGE_RISING
|
||||
0 66 IRQ_TYPE_EDGE_RISING
|
||||
0 67 IRQ_TYPE_EDGE_RISING
|
||||
@@ -637,7 +636,7 @@
|
||||
|
||||
gmac0: gmac0 {
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
- vlan_tag = <1 0x1f>;
|
||||
+ vlan_tag = <1 0x3f>;
|
||||
};
|
||||
|
||||
gmac1: gmac1 {
|
||||
diff --git a/drivers/net/ethernet/qualcomm/essedma/edma.c b/drivers/net/ethernet/qualcomm/essedma/edma.c
|
||||
index 05f9ce9..a3c0d66 100644
|
||||
--- a/drivers/net/ethernet/qualcomm/essedma/edma.c
|
||||
+++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
|
||||
@@ -750,13 +750,11 @@ static void edma_rx_complete(struct edma_common_info *edma_cinfo,
|
||||
edma_receive_checksum(rd, skb);
|
||||
|
||||
/* Process VLAN HW acceleration indication provided by HW */
|
||||
- if (unlikely(adapter->default_vlan_tag != rd->rrd4)) {
|
||||
- vlan = rd->rrd4;
|
||||
- if (likely(rd->rrd7 & EDMA_RRD_CVLAN))
|
||||
- __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
|
||||
- else if (rd->rrd1 & EDMA_RRD_SVLAN)
|
||||
- __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), vlan);
|
||||
- }
|
||||
+ vlan = rd->rrd4;
|
||||
+ if (likely(rd->rrd7 & EDMA_RRD_CVLAN))
|
||||
+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
|
||||
+ else if (rd->rrd1 & EDMA_RRD_SVLAN)
|
||||
+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), vlan);
|
||||
|
||||
/* Update rx statistics */
|
||||
adapter->stats.rx_packets++;
|
||||
@@ -1434,8 +1432,6 @@ netdev_tx_t edma_xmit(struct sk_buff *skb,
|
||||
if (!adapter->edma_cinfo->is_single_phy) {
|
||||
if (unlikely(skb_vlan_tag_present(skb)))
|
||||
flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG;
|
||||
- else if (adapter->default_vlan_tag)
|
||||
- flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG;
|
||||
}
|
||||
|
||||
/* Check and mark checksum offload */
|
||||
--
|
||||
2.7.4
|
||||
|
||||
Loading…
Reference in New Issue
Block a user