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Merge Official Source

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2023-05-18 11:20:35 +08:00
commit 13c4817843
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
31 changed files with 902 additions and 329 deletions
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4
package/kernel/mac80211/Makefile
View File

@ -11,7 +11,7 @@ include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=mac80211
PKG_VERSION:=6.1.24
PKG_RELEASE:=1
PKG_RELEASE:=2
# PKG_SOURCE_URL:=@KERNEL/linux/kernel/projects/backports/stable/v5.15.58/
PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/
PKG_HASH:=5d39aca7e34c33cb9b3e366117b2e86841b7bdd37933679d6b1e61be6b150648
@ -342,6 +342,7 @@ define Build/Patch
$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath10k,ath10k/)
$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath11k,ath11k/)
$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/rt2x00,rt2x00/)
$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/mt7601u,mt7601u/)
$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/mwl,mwl/)
$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/brcm,brcm/)
$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/rtl,rtl/)
@ -357,6 +358,7 @@ define Quilt/Refresh/Package
$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath10k,ath10k/)
$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath11k,ath11k/)
$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/rt2x00,rt2x00/)
$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/mt7601u,mt7601u/)
$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/mwl,mwl/)
$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/brcm,brcm/)
$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/rtl,rtl/)

2
package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch
View File

@ -55,7 +55,7 @@
int ath9k_init_debug(struct ath_hw *ah)
{
struct ath_common *common = ath9k_hw_common(ah);
@@ -1432,6 +1479,8 @@ int ath9k_init_debug(struct ath_hw *ah)
@@ -1432,6 +1480,8 @@ int ath9k_init_debug(struct ath_hw *ah)
ath9k_tx99_init_debug(sc);
ath9k_cmn_spectral_init_debug(&sc->spec_priv, sc->debug.debugfs_phy);

4
package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch
View File

@ -1,6 +1,6 @@
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -1460,6 +1460,52 @@ static const struct file_operations fops
@@ -1461,6 +1461,52 @@ static const struct file_operations fops
.owner = THIS_MODULE
};
@ -53,7 +53,7 @@
int ath9k_init_debug(struct ath_hw *ah)
{
struct ath_common *common = ath9k_hw_common(ah);
@@ -1481,6 +1527,8 @@ int ath9k_init_debug(struct ath_hw *ah)
@@ -1482,6 +1528,8 @@ int ath9k_init_debug(struct ath_hw *ah)
debugfs_create_file("eeprom", S_IRUSR, sc->debug.debugfs_phy, sc,
&fops_eeprom);

4
package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch
View File

@ -192,7 +192,7 @@
#endif
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -1505,6 +1505,61 @@ static const struct file_operations fops
@@ -1506,6 +1506,61 @@ static const struct file_operations fops
.llseek = default_llseek,
};
@ -254,7 +254,7 @@
int ath9k_init_debug(struct ath_hw *ah)
{
@@ -1529,6 +1584,10 @@ int ath9k_init_debug(struct ath_hw *ah)
@@ -1530,6 +1585,10 @@ int ath9k_init_debug(struct ath_hw *ah)
&fops_eeprom);
debugfs_create_file("chanbw", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
sc, &fops_chanbw);

4
package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch
View File

@ -1,6 +1,6 @@
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -1561,6 +1561,50 @@ static const struct file_operations fops
@@ -1562,6 +1562,50 @@ static const struct file_operations fops
#endif
@ -51,7 +51,7 @@
int ath9k_init_debug(struct ath_hw *ah)
{
struct ath_common *common = ath9k_hw_common(ah);
@@ -1588,6 +1632,8 @@ int ath9k_init_debug(struct ath_hw *ah)
@@ -1589,6 +1633,8 @@ int ath9k_init_debug(struct ath_hw *ah)
debugfs_create_file("gpio_led", S_IWUSR,
sc->debug.debugfs_phy, sc, &fops_gpio_led);
#endif

55
package/kernel/mac80211/patches/mt7601u/001-wifi-mt7601u-update-firmware-path.patch Normal file
View File

@ -0,0 +1,55 @@
From patchwork Mon May 15 22:56:53 2023
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
X-Patchwork-Id: 13242309
X-Patchwork-Delegate: kvalo@adurom.com
Return-Path: <linux-wireless-owner@vger.kernel.org>
Date: Tue, 16 May 2023 00:56:53 +0200
From: Daniel Golle <daniel@makrotopia.org>
To: Jakub Kicinski <kuba@kernel.org>, Kalle Valo <kvalo@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Paolo Abeni <pabeni@redhat.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
linux-wireless@vger.kernel.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: [PATCH] wifi: mt7601u: update firmware path
Message-ID:
<fefcbf36f13873ae0d97438a0156b87e7e1ae64e.1684191377.git.daniel@makrotopia.org>
MIME-Version: 1.0
Content-Disposition: inline
Precedence: bulk
List-ID: <linux-wireless.vger.kernel.org>
X-Mailing-List: linux-wireless@vger.kernel.org
mt7601u.bin was moved to mediatek/ folder in linux-wireless via commit
8451c2b1 ("mt76xx: Move the old Mediatek WiFi firmware to mediatek")
and linux-firmware release 20230515.
Update the firmware path requested by the mt7601u driver to follow up
with the move of the file.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/wireless/mediatek/mt7601u/usb.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
base-commit: 0d9b41daa5907756a31772d8af8ac5ff25cf17c1
--- a/drivers/net/wireless/mediatek/mt7601u/usb.h
+++ b/drivers/net/wireless/mediatek/mt7601u/usb.h
@@ -8,7 +8,7 @@
#include "mt7601u.h"
-#define MT7601U_FIRMWARE "mt7601u.bin"
+#define MT7601U_FIRMWARE "mediatek/mt7601u.bin"
#define MT_VEND_REQ_MAX_RETRY 10
#define MT_VEND_REQ_TOUT_MS 300

20
package/kernel/mt76/Makefile
View File

@ -1,7 +1,7 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=mt76
PKG_RELEASE=5
PKG_RELEASE=1
PKG_LICENSE:=GPLv2
PKG_LICENSE_FILES:=
@ -503,6 +503,15 @@ define KernelPackage/mt7916-firmware/install
$(1)/lib/firmware/mediatek
endef
define KernelPackage/mt7981-firmware/install
$(INSTALL_DIR) $(1)/lib/firmware/mediatek
cp \
$(PKG_BUILD_DIR)/firmware/mt7981_wa.bin \
$(PKG_BUILD_DIR)/firmware/mt7981_wm.bin \
$(PKG_BUILD_DIR)/firmware/mt7981_rom_patch.bin \
$(1)/lib/firmware/mediatek
endef
define KernelPackage/mt7986-firmware/install
$(INSTALL_DIR) $(1)/lib/firmware/mediatek
cp \
@ -516,15 +525,6 @@ define KernelPackage/mt7986-firmware/install
$(1)/lib/firmware/mediatek
endef
define KernelPackage/mt7981-firmware/install
$(INSTALL_DIR) $(1)/lib/firmware/mediatek
cp \
$(PKG_BUILD_DIR)/firmware/mt7981_wa.bin \
$(PKG_BUILD_DIR)/firmware/mt7981_wm.bin \
$(PKG_BUILD_DIR)/firmware/mt7981_rom_patch.bin \
$(1)/lib/firmware/mediatek
endef
define KernelPackage/mt7921-firmware/install
$(INSTALL_DIR) $(1)/lib/firmware/mediatek
cp \

6
package/network/utils/iwinfo/Makefile
View File

@ -11,9 +11,9 @@ PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/iwinfo.git
PKG_SOURCE_DATE:=2023-02-06
PKG_SOURCE_VERSION:=c7eb8ebe33de2ff2d08064258edb047e5ac09f29
PKG_MIRROR_HASH:=f1124cf305710b0f04e2ea6dd42ba96ba4a3367da4d4afb4c19d5af9905b1cc2
PKG_SOURCE_DATE:=2023-05-17
PKG_SOURCE_VERSION:=c9f5c3f7b50d146f18be1458ab5591defc0af6da
PKG_MIRROR_HASH:=0d9263cbbe79d62966398af66b3b3ce7b58991da6b266f8f4ec2ec4be3d4ad97
PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
PKG_LICENSE:=GPL-2.0

16
target/linux/bmips/patches-5.15/100-irqchip-add-support-for-bcm6345-style-external-inter.patch
View File

@ -1,17 +1,17 @@
From cf908990d4a8ccdb73ee4484aa8cadad379ca314 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 30 Nov 2014 14:54:27 +0100
Subject: [PATCH 2/5] irqchip: add support for bcm6345-style external
interrupt controller
Subject: [PATCH] irqchip: add support for bcm6345-style external interrupt
controller
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
.../interrupt-controller/brcm,bcm6345-ext-intc.txt | 29 ++
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-bcm6345-ext.c | 287 ++++++++++++++++++++
include/linux/irqchip/irq-bcm6345-ext.h | 14 +
5 files changed, 335 insertions(+)
.../brcm,bcm6345-ext-intc.txt | 29 ++
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-bcm6345-ext.c | 280 ++++++++++++++++++
include/linux/irqchip/irq-bcm6345-ext.h | 14 +
5 files changed, 328 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
create mode 100644 drivers/irqchip/irq-bcm6345-ext.c
create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h

6
target/linux/bmips/patches-5.15/200-mips-bmips-automatically-detect-CPU-frequency.patch
View File

@ -1,7 +1,7 @@
From 0377ad93031d3e51c2afe44231241185f684b6af Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
Date: Fri, 5 Mar 2021 15:14:32 +0100
Subject: [PATCH 1/2] mips: bmips: automatically detect CPU frequency
Subject: [PATCH] mips: bmips: automatically detect CPU frequency
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
@ -10,8 +10,8 @@ Some BCM63xx SoCs support multiple CPU frequencies depending on HW config.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
arch/mips/bmips/setup.c | 198 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 191 insertions(+), 7 deletions(-)
arch/mips/bmips/setup.c | 197 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 190 insertions(+), 7 deletions(-)
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c

6
target/linux/bmips/patches-5.15/201-mips-bmips-automatically-detect-RAM-size.patch
View File

@ -1,7 +1,7 @@
From f9ee3f28ecb979c77423be965ef9dd313bdb9e9b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
Date: Mon, 8 Mar 2021 16:58:34 +0100
Subject: [PATCH 2/2] mips: bmips: automatically detect RAM size
Subject: [PATCH] mips: bmips: automatically detect RAM size
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
@ -10,8 +10,8 @@ Some devices have different amounts of RAM installed depending on HW revision.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
arch/mips/bmips/setup.c | 118 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
arch/mips/bmips/setup.c | 119 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 119 insertions(+)
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c

4
target/linux/bmips/patches-5.15/202-mips-bmips-tweak-Kconfig-options.patch
View File

@ -8,8 +8,8 @@ Content-Transfer-Encoding: 8bit
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/Kconfig | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig

91
target/linux/bmips/patches-5.15/210-macronix_nand_block_protection_support.patch
View File

@ -14,12 +14,97 @@ devices since it hangs the device.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
drivers/mtd/nand/raw/nand_macronix.c | 5 -----
1 file changed, 5 deletions(-)
drivers/mtd/nand/raw/nand_macronix.c | 72 ----------------------------
1 file changed, 72 deletions(-)
--- a/drivers/mtd/nand/raw/nand_macronix.c
+++ b/drivers/mtd/nand/raw/nand_macronix.c
@@ -323,7 +323,6 @@ static int macronix_nand_init(struct nan
@@ -12,10 +12,6 @@
#define MACRONIX_READ_RETRY_BIT BIT(0)
#define MACRONIX_NUM_READ_RETRY_MODES 6
-#define ONFI_FEATURE_ADDR_MXIC_PROTECTION 0xA0
-#define MXIC_BLOCK_PROTECTION_ALL_LOCK 0x38
-#define MXIC_BLOCK_PROTECTION_ALL_UNLOCK 0x0
-
#define ONFI_FEATURE_ADDR_MXIC_RANDOMIZER 0xB0
#define MACRONIX_RANDOMIZER_BIT BIT(1)
#define MACRONIX_RANDOMIZER_ENPGM BIT(0)
@@ -179,73 +175,6 @@ static void macronix_nand_fix_broken_get
ONFI_FEATURE_ADDR_TIMING_MODE, 1);
}
-/*
- * Macronix NAND supports Block Protection by Protectoin(PT) pin;
- * active high at power-on which protects the entire chip even the #WP is
- * disabled. Lock/unlock protection area can be partition according to
- * protection bits, i.e. upper 1/2 locked, upper 1/4 locked and so on.
- */
-static int mxic_nand_lock(struct nand_chip *chip, loff_t ofs, uint64_t len)
-{
- u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
- int ret;
-
- feature[0] = MXIC_BLOCK_PROTECTION_ALL_LOCK;
- nand_select_target(chip, 0);
- ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
- feature);
- nand_deselect_target(chip);
- if (ret)
- pr_err("%s all blocks failed\n", __func__);
-
- return ret;
-}
-
-static int mxic_nand_unlock(struct nand_chip *chip, loff_t ofs, uint64_t len)
-{
- u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
- int ret;
-
- feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
- nand_select_target(chip, 0);
- ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
- feature);
- nand_deselect_target(chip);
- if (ret)
- pr_err("%s all blocks failed\n", __func__);
-
- return ret;
-}
-
-static void macronix_nand_block_protection_support(struct nand_chip *chip)
-{
- u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
- int ret;
-
- bitmap_set(chip->parameters.get_feature_list,
- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
-
- feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
- nand_select_target(chip, 0);
- ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
- feature);
- nand_deselect_target(chip);
- if (ret || feature[0] != MXIC_BLOCK_PROTECTION_ALL_LOCK) {
- if (ret)
- pr_err("Block protection check failed\n");
-
- bitmap_clear(chip->parameters.get_feature_list,
- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
- return;
- }
-
- bitmap_set(chip->parameters.set_feature_list,
- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
-
- chip->ops.lock_area = mxic_nand_lock;
- chip->ops.unlock_area = mxic_nand_unlock;
-}
-
static int nand_power_down_op(struct nand_chip *chip)
{
int ret;
@@ -323,7 +252,6 @@ static int macronix_nand_init(struct nan
macronix_nand_fix_broken_get_timings(chip);
macronix_nand_onfi_init(chip);

154
target/linux/bmips/patches-5.15/211-drivers-mtd-nand-macronix-comment-unused-function.patch
View File

@ -1,154 +0,0 @@
From 00cf359b486a3d14c29014e9d57d92ab81972866 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Tue, 9 May 2023 14:03:08 +0200
Subject: [PATCH] drivers: mtd: nand: macronix: comment unused function
Comment unused function since macronix_nand_block_protection_support
cause booting problems.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/mtd/nand/raw/nand_macronix.c | 132 +++++++++++++--------------
1 file changed, 66 insertions(+), 66 deletions(-)
--- a/drivers/mtd/nand/raw/nand_macronix.c
+++ b/drivers/mtd/nand/raw/nand_macronix.c
@@ -179,72 +179,72 @@ static void macronix_nand_fix_broken_get
ONFI_FEATURE_ADDR_TIMING_MODE, 1);
}
-/*
- * Macronix NAND supports Block Protection by Protectoin(PT) pin;
- * active high at power-on which protects the entire chip even the #WP is
- * disabled. Lock/unlock protection area can be partition according to
- * protection bits, i.e. upper 1/2 locked, upper 1/4 locked and so on.
- */
-static int mxic_nand_lock(struct nand_chip *chip, loff_t ofs, uint64_t len)
-{
- u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
- int ret;
-
- feature[0] = MXIC_BLOCK_PROTECTION_ALL_LOCK;
- nand_select_target(chip, 0);
- ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
- feature);
- nand_deselect_target(chip);
- if (ret)
- pr_err("%s all blocks failed\n", __func__);
-
- return ret;
-}
-
-static int mxic_nand_unlock(struct nand_chip *chip, loff_t ofs, uint64_t len)
-{
- u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
- int ret;
-
- feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
- nand_select_target(chip, 0);
- ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
- feature);
- nand_deselect_target(chip);
- if (ret)
- pr_err("%s all blocks failed\n", __func__);
-
- return ret;
-}
-
-static void macronix_nand_block_protection_support(struct nand_chip *chip)
-{
- u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
- int ret;
-
- bitmap_set(chip->parameters.get_feature_list,
- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
-
- feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
- nand_select_target(chip, 0);
- ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
- feature);
- nand_deselect_target(chip);
- if (ret || feature[0] != MXIC_BLOCK_PROTECTION_ALL_LOCK) {
- if (ret)
- pr_err("Block protection check failed\n");
-
- bitmap_clear(chip->parameters.get_feature_list,
- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
- return;
- }
-
- bitmap_set(chip->parameters.set_feature_list,
- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
-
- chip->ops.lock_area = mxic_nand_lock;
- chip->ops.unlock_area = mxic_nand_unlock;
-}
+// /*
+// * Macronix NAND supports Block Protection by Protectoin(PT) pin;
+// * active high at power-on which protects the entire chip even the #WP is
+// * disabled. Lock/unlock protection area can be partition according to
+// * protection bits, i.e. upper 1/2 locked, upper 1/4 locked and so on.
+// */
+// static int mxic_nand_lock(struct nand_chip *chip, loff_t ofs, uint64_t len)
+// {
+// u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
+// int ret;
+
+// feature[0] = MXIC_BLOCK_PROTECTION_ALL_LOCK;
+// nand_select_target(chip, 0);
+// ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
+// feature);
+// nand_deselect_target(chip);
+// if (ret)
+// pr_err("%s all blocks failed\n", __func__);
+
+// return ret;
+// }
+
+// static int mxic_nand_unlock(struct nand_chip *chip, loff_t ofs, uint64_t len)
+// {
+// u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
+// int ret;
+
+// feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
+// nand_select_target(chip, 0);
+// ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
+// feature);
+// nand_deselect_target(chip);
+// if (ret)
+// pr_err("%s all blocks failed\n", __func__);
+
+// return ret;
+// }
+
+// static void macronix_nand_block_protection_support(struct nand_chip *chip)
+// {
+// u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
+// int ret;
+
+// bitmap_set(chip->parameters.get_feature_list,
+// ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
+
+// feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
+// nand_select_target(chip, 0);
+// ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
+// feature);
+// nand_deselect_target(chip);
+// if (ret || feature[0] != MXIC_BLOCK_PROTECTION_ALL_LOCK) {
+// if (ret)
+// pr_err("Block protection check failed\n");
+
+// bitmap_clear(chip->parameters.get_feature_list,
+// ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
+// return;
+// }
+
+// bitmap_set(chip->parameters.set_feature_list,
+// ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
+
+// chip->ops.lock_area = mxic_nand_lock;
+// chip->ops.unlock_area = mxic_nand_unlock;
+// }
static int nand_power_down_op(struct nand_chip *chip)
{

10
target/linux/bmips/patches-5.15/500-net-broadcom-add-BCM6368-enetsw-controller-driver.patch
View File

@ -1,7 +1,7 @@
From 590b60fb08cb1e70fe02d3f407c6b3dbe9ad06ff Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
Date: Mon, 1 Mar 2021 07:34:39 +0100
Subject: [PATCH 3/4] net: broadcom: add BCM6368 enetsw controller driver
Subject: [PATCH] net: broadcom: add BCM6368 enetsw controller driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
@ -11,11 +11,9 @@ SoCs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
drivers/net/ethernet/broadcom/Kconfig | 8 +
drivers/net/ethernet/broadcom/Makefile | 1 +
.../net/ethernet/broadcom/bcm6368-enetsw.c | 1111 +++++++++++++++++
3 files changed, 1120 insertions(+)
create mode 100644 drivers/net/ethernet/broadcom/bcm6368-enetsw.c
drivers/net/ethernet/broadcom/Kconfig | 8 ++++++++
drivers/net/ethernet/broadcom/Makefile | 1 +
2 files changed, 9 insertions(+)
--- a/drivers/net/ethernet/broadcom/Kconfig
+++ b/drivers/net/ethernet/broadcom/Kconfig

7
target/linux/bmips/patches-5.15/501-net-broadcom-add-BCM6348-enet-controller-driver.patch
View File

@ -10,10 +10,9 @@ This controller is present on BCM6338, BCM6348 and BCM6358 SoCs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
drivers/net/ethernet/broadcom/Kconfig | 8 +
drivers/net/ethernet/broadcom/Makefile | 1 +
3 files changed, 1120 insertions(+)
create mode 100644 drivers/net/ethernet/broadcom/bcm6368-enetsw.c
drivers/net/ethernet/broadcom/Kconfig | 8 ++++++++
drivers/net/ethernet/broadcom/Makefile | 1 +
2 files changed, 9 insertions(+)
--- a/drivers/net/ethernet/broadcom/Kconfig
+++ b/drivers/net/ethernet/broadcom/Kconfig

13
target/linux/bmips/patches-5.15/502-net-mdio-mux-bcm6368-allow-disabling.patch
View File

@ -1,3 +1,16 @@
From 21145a89c79a22c4fb719cce5a2f4e3373d39756 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
Date: Wed, 17 May 2023 18:16:46 +0200
Subject: [PATCH] net: mdio: mux-bcm6368: allow disabling for bmips
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
drivers/net/mdio/Kconfig | 1 -
1 file changed, 1 deletion(-)
--- a/drivers/net/mdio/Kconfig
+++ b/drivers/net/mdio/Kconfig
@@ -219,7 +219,6 @@ config MDIO_BUS_MUX_BCM6368

14
target/linux/bmips/patches-5.15/600-mips-bmips-add-pci-support.patch
View File

@ -1,3 +1,17 @@
From 7742c1ba191a005a1356ff89b5fe2279d6f0ec4d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
Date: Wed, 17 May 2023 18:18:43 +0200
Subject: [PATCH] mips: bmips: add PCI support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
arch/mips/Kconfig | 1 +
arch/mips/pci/Makefile | 1 +
2 files changed, 2 insertions(+)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -274,6 +274,7 @@ config BMIPS_GENERIC

14
target/linux/bmips/patches-5.15/601-pci-controllers-add-bcm6328-pcie-support.patch
View File

@ -1,3 +1,17 @@
From 49133041e0a5770decf1a25f575764d13a0d425c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
Date: Wed, 17 May 2023 18:20:10 +0200
Subject: [PATCH] pci: add bcm6328-pcie support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
drivers/pci/controller/Kconfig | 5 +++++
drivers/pci/controller/Makefile | 1 +
2 files changed, 6 insertions(+)
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -3,6 +3,11 @@

14
target/linux/bmips/patches-5.15/602-pci-controllers-add-bcm6318-pcie-support.patch
View File

@ -1,3 +1,17 @@
From cc3c30bdc98eabbaa07c64302eb5124a0f4a74f0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
Date: Wed, 17 May 2023 18:20:46 +0200
Subject: [PATCH] pci: add bcm6318-pcie support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
drivers/pci/controller/Kconfig | 5 +++++
drivers/pci/controller/Makefile | 1 +
2 files changed, 6 insertions(+)
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -3,6 +3,11 @@

14
target/linux/bmips/patches-5.15/603-pci-controllers-add-bcm6348-pci-support.patch
View File

@ -1,3 +1,17 @@
From 5e7813e5725d79d00e0988472c306490fc48b3e1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
Date: Wed, 17 May 2023 18:21:19 +0200
Subject: [PATCH] pci: add bcm6348-pci support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
drivers/pci/controller/Kconfig | 5 +++++
drivers/pci/controller/Makefile | 1 +
2 files changed, 6 insertions(+)
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -3,6 +3,11 @@

3
target/linux/bmips/patches-5.15/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch
View File

@ -13,8 +13,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
drivers/leds/Kconfig | 9 +++++++++
drivers/leds/Makefile | 1 +
drivers/spi/spidev.c | 2 ++
3 files changed, 12 insertions(+)
2 files changed, 10 insertions(+)
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig

8
target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface
View File

@ -1,11 +1,15 @@
set_preinit_iface() {
ip link set eth0 up
case $(board_name) in
glinet,gl-mt3000)
ip link set eth1 up
ifname=eth1
;;
ubnt,unifi-6-lr)
ip link set eth0 up
ifname=eth0
;;
*)
ip link set eth0 up
ifname=lan1
;;
esac

282
target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts Normal file
View File

@ -0,0 +1,282 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include "mt7981.dtsi"
/ {
model = "Cudy WR3000 v1";
compatible = "cudy,wr3000-v1", "mediatek,mt7981";
aliases {
ethernet0 = &gmac0;
label-mac-device = &lan1;
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_status;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
};
};
leds {
compatible = "gpio-leds";
led_status: led@0 {
label = "blue:status";
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
led@1 {
label = "blue:internet";
gpios = <&pio 11 GPIO_ACTIVE_LOW>;
};
led@2 {
label = "blue:wan";
gpios = <&pio 5 GPIO_ACTIVE_LOW>;
};
led@3 {
label = "blue:lan";
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
led@4 {
label = "blue:wifi2";
gpios = <&pio 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
led@5 {
label = "blue:wifi5";
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
};
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_bdinfo_de00>;
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
status = "disabled";
};
};
&mdio_bus {
switch: switch@0 {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
status = "disabled";
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_flash_pins>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@00000 {
label = "BL2";
reg = <0x00000 0x40000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x10000>;
read-only;
};
factory: partition@50000 {
label = "Factory";
reg = <0x50000 0x10000>;
read-only;
};
bdinfo: partition@60000 {
label = "bdinfo";
reg = <0x60000 0x10000>;
read-only;
};
partition@70000 {
label = "FIP";
reg = <0x70000 0x80000>;
read-only;
};
partition@f0000 {
compatible = "denx,fit";
label = "firmware";
reg = <0xf0000 0xf10000>;
};
};
};
};
&pio {
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
spi2_flash_pins: spi2-pins {
mux {
function = "spi";
groups = "spi2", "spi2_wp_hold";
};
conf-pu {
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
drive-strength = <8>;
bias-pull-up = <103>;
};
conf-pd {
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
drive-strength = <8>;
bias-pull-down = <103>;
};
};
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "wan";
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_bdinfo_de00>;
mac-address-increment = <1>;
};
lan1: port@1 {
reg = <1>;
label = "lan1";
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_bdinfo_de00>;
};
port@2 {
reg = <2>;
label = "lan2";
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_bdinfo_de00>;
};
port@3 {
reg = <3>;
label = "lan3";
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_bdinfo_de00>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&wifi {
status = "okay";
mediatek,mtd-eeprom = <&factory 0x0>;
};
&bdinfo {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_bdinfo_de00: macaddr@de00 {
reg = <0xde00 0x6>;
};
};

240
target/linux/mediatek/dts/mt7981b-glinet-gl-mt3000.dts Normal file
View File

@ -0,0 +1,240 @@
/dts-v1/;
#include "mt7981.dtsi"
/ {
model = "GL.iNet GL-MT3000";
compatible = "glinet,gl-mt3000", "mediatek,mt7981";
aliases {
led-boot = &led_lightblue;
led-failsafe = &led_lightblue;
led-running = &led_white;
led-upgrade = &led_lightblue;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
};
mode {
label = "mode";
linux,input-type = <EV_SW>;
linux,code = <BTN_0>;
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
led_lightblue: led@0 {
label = "blue:run";
gpios = <&pio 31 GPIO_ACTIVE_LOW>;
};
led_white: led@1 {
label = "white:system";
gpios = <&pio 30 GPIO_ACTIVE_LOW>;
};
};
fan_5v: regulator-fan-5v {
compatible = "regulator-fixed";
regulator-name = "fan";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 28 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
usb_vbus: regulator-usb-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
phy-handle = <&phy0>;
nvmem-cells = <&macaddr>;
nvmem-cell-names = "mac-address";
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "gmii";
phy-handle = <&int_gbe_phy>;
nvmem-cells = <&macaddr>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
};
};
&mdio_bus {
reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
reset-delay-us = <600>;
reset-post-delay-us = <20000>;
phy0: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&fan {
pwms = <&pwm 0 40000 0>;
fan-supply = <&fan_5v>;
interrupt-parent = <&pio>;
interrupts = <29 IRQ_TYPE_EDGE_RISING>;
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
status = "okay";
spi_nand: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-cal-enable;
spi-cal-mode = "read-data";
spi-cal-datalen = <7>;
spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
spi-cal-addrlen = <5>;
spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
mediatek,nmbm;
mediatek,bmt-max-ratio = <1>;
mediatek,bmt-max-reserved-blocks = <64>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x0100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x0200000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr: macaddr@a {
reg = <0xa 0x6>;
};
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x0200000>;
read-only;
};
partition@580000 {
label = "log";
reg = <0x580000 0x0040000>;
};
partition@5c0000 {
label = "ubi";
reg = <0x5c0000 0xf640000>;
compatible = "linux,ubi";
};
};
};
};
&pio {
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
pwm_pins: pwm0-pins {
mux {
function = "pwm";
groups = "pwm0_1";
};
};
};
&usb_phy {
status = "okay";
};
&xhci {
vbus-supply = <&usb_vbus>;
status = "okay";
};
&wifi {
mediatek,mtd-eeprom = <&factory 0x0>;
status = "okay";
};

3
target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
View File

@ -6,6 +6,9 @@ board=$(board_name)
board_config_update
case $board in
cudy,wr3000-v1)
ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan"
;;
livinet,zr-3020)
ucidef_set_led_netdev "internet" "INTERNET" "blue:internet" "wan"
ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan2g" "phy0-ap0"

6
target/linux/mediatek/filogic/base-files/etc/board.d/02_network
View File

@ -14,6 +14,12 @@ mediatek_setup_interfaces()
bananapi,bpi-r3)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 sfp2" "eth1 wan"
;;
cudy,wr3000-v1)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
;;
glinet,gl-mt3000)
ucidef_set_interfaces_lan_wan eth1 eth0
;;
livinet,zr-3020|\
qihoo,360-t7-stock|\
qihoo,360-t7-ubootmod)

8
target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
View File

@ -24,6 +24,14 @@ case "$board" in
[ "$PHYNBR" = "0" ] && macaddr_unsetbit $addr 6 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_setbit $addr 6 > /sys${DEVPATH}/macaddress
;;
cudy,wr3000-v1)
addr=$(mtd_get_mac_binary bdinfo 0xde00)
# Originally, phy0 is phy1 mac with LA bit set. However, this would conflict
# addresses on multiple VIFs with the other radio. Set LA bit and increment
# mac-address instead.
[ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress
;;
livinet,zr-3020)
addr=$(mtd_get_mac_ascii config2 wifi5gmac)
[ "$PHYNBR" = "1" ] && echo $macaddr > /sys${DEVPATH}/macaddress

3
target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
View File

@ -67,6 +67,9 @@ platform_do_upgrade() {
;;
esac
;;
cudy,wr3000-v1)
default_do_upgrade "$1"
;;
tplink,tl-xdr4288|\
tplink,tl-xdr6086|\
tplink,tl-xdr6088|\

68
target/linux/mediatek/image/filogic.mk
View File

@ -36,6 +36,36 @@ define Build/mt7986-gpt
rm $@.tmp
endef
metadata_gl_json = \
'{ $(if $(IMAGE_METADATA),$(IMAGE_METADATA)$(comma)) \
"metadata_version": "1.1", \
"compat_version": "$(call json_quote,$(compat_version))", \
$(if $(DEVICE_COMPAT_MESSAGE),"compat_message": "$(call json_quote,$(DEVICE_COMPAT_MESSAGE))"$(comma)) \
$(if $(filter-out 1.0,$(compat_version)),"new_supported_devices": \
[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma) \
"supported_devices": ["$(call json_quote,$(legacy_supported_message))"]$(comma)) \
$(if $(filter 1.0,$(compat_version)),"supported_devices":[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma)) \
"version": { \
"release": "$(call json_quote,$(VERSION_NUMBER))", \
"date": "$(shell TZ='Asia/Chongqing' date '+%Y%m%d%H%M%S')", \
"dist": "$(call json_quote,$(VERSION_DIST))", \
"version": "$(call json_quote,$(VERSION_NUMBER))", \
"revision": "$(call json_quote,$(REVISION))", \
"target": "$(call json_quote,$(TARGETID))", \
"board": "$(call json_quote,$(if $(BOARD_NAME),$(BOARD_NAME),$(DEVICE_NAME)))" \
}, \
"upgrade_control":"$(shell python3 $(TOPDIR)/make_gl_metadata.py)", \
"release_note":"$(shell sed ':a;N;s/\n/\\n/g;s/\r/\\r/g;ta' $(TOPDIR)/gl_release_note)" \
}'
define Build/append-gl-metadata
$(if $(SUPPORTED_DEVICES),-echo $(call metadata_gl_json,$(SUPPORTED_DEVICES)) | fwtool -I - $@)
[ ! -s "$(BUILD_KEY)" -o ! -s "$@" ] || { \
usign -S -m "$@" -s "$(BUILD_KEY)" -x "$@.sig" ;\
fwtool -S "$@.sig" "$@" ;\
}
endef
define Device/asus_tuf-ax4200
DEVICE_VENDOR := ASUS
DEVICE_MODEL := TUF-AX4200
@ -52,7 +82,6 @@ define Device/asus_tuf-ax4200
endef
TARGET_DEVICES += asus_tuf-ax4200
define Device/bananapi_bpi-r3
DEVICE_VENDOR := Bananapi
DEVICE_MODEL := BPi-R3
@ -100,6 +129,41 @@ define Device/bananapi_bpi-r3
endef
TARGET_DEVICES += bananapi_bpi-r3
define Device/cudy_wr3000-v1
DEVICE_VENDOR := Cudy
DEVICE_MODEL := WR3000
DEVICE_VARIANT := v1
DEVICE_DTS := mt7981b-cudy-wr3000-v1
DEVICE_DTS_DIR := ../dts
DEVICE_DTS_LOADADDR := 0x47000000
IMAGES := sysupgrade.bin
IMAGE_SIZE := 15424k
SUPPORTED_DEVICES += R31
KERNEL := kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
KERNEL_INITRAMFS := kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | pad-rootfs | check-size | append-metadata
DEVICE_PACKAGES := kmod-mt7981-firmware
endef
TARGET_DEVICES += cudy_wr3000-v1
define Device/glinet_gl-mt3000
DEVICE_VENDOR := GL.iNet
DEVICE_MODEL := GL-MT3000
DEVICE_DTS := mt7981b-glinet-gl-mt3000
DEVICE_DTS_DIR := ../dts
SUPPORTED_DEVICES += glinet,mt3000-snand
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-hwmon-pwmfan kmod-usb3
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 246272k
KERNEL_IN_UBI := 1
IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata
endef
TARGET_DEVICES += glinet_gl-mt3000
define Device/livinet_zr-3020
DEVICE_VENDOR := Livinet
DEVICE_MODEL := ZR-3020
@ -109,7 +173,7 @@ define Device/livinet_zr-3020
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 52216k
IMAGE_SIZE := 65536k
KERNEL_IN_UBI := 1
IMAGES += factory.bin
IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)

148
target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch
View File

@ -1,6 +1,6 @@
From 947b535ebfe161e1725f1030a09de10d1460371c Mon Sep 17 00:00:00 2001
From 73d20ebc21c562fbe79d02fa0fa38e095e716fa9 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Mon, 23 Jan 2023 20:47:34 +0000
Date: Wed, 19 Apr 2023 20:25:51 +0100
Subject: [PATCH] pwm: mediatek: Add support for MT7981
The PWM unit on MT7981 uses different register offsets than previous
@ -10,27 +10,20 @@ used for a temperature controlled fan.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/pwm/pwm-mediatek.c | 54 ++++++++++++++++++++++++++++++++------
1 file changed, 46 insertions(+), 8 deletions(-)
drivers/pwm/pwm-mediatek.c | 41 ++++++++++++++++++++++++++++++--------
1 file changed, 33 insertions(+), 8 deletions(-)
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -34,10 +34,14 @@
#define PWM_CLK_DIV_MAX 7
+#define REG_V1 1
+#define REG_V2 2
+
struct pwm_mediatek_of_data {
@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
unsigned int num_pwms;
bool pwm45_fixup;
bool has_ck_26m_sel;
+ u8 reg_ver;
+ const unsigned int *reg_offset;
};
/**
@@ -59,10 +63,14 @@ struct pwm_mediatek_chip {
@@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
const struct pwm_mediatek_of_data *soc;
};
@ -40,169 +33,86 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
};
+static const unsigned int mtk_pwm_reg_offset_v2[] = {
+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x1c0, 0x200, 0x0240
+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
+};
+
static inline struct pwm_mediatek_chip *
to_pwm_mediatek_chip(struct pwm_chip *chip)
{
@@ -111,7 +119,19 @@ static inline void pwm_mediatek_writel(s
@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s
unsigned int num, unsigned int offset,
u32 value)
{
- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
+ u32 pwm_offset;
+
+ switch (chip->soc->reg_ver) {
+ case REG_V2:
+ pwm_offset = mtk_pwm_reg_offset_v2[num];
+ break;
+
+ case REG_V1:
+ default:
+ pwm_offset = mtk_pwm_reg_offset_v1[num];
+ }
+
+ writel(value, chip->regs + pwm_offset + offset);
+ writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
}
static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
@@ -146,7 +166,7 @@ static int pwm_mediatek_config(struct pw
if (clkdiv > PWM_CLK_DIV_MAX) {
pwm_mediatek_clk_disable(chip, pwm);
- dev_err(chip->dev, "period %d not supported\n", period_ns);
+ dev_err(chip->dev, "period of %d ns not supported\n", period_ns);
return -EINVAL;
}
@@ -221,24 +241,20 @@ static int pwm_mediatek_probe(struct pla
if (IS_ERR(pc->regs))
return PTR_ERR(pc->regs);
- pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms,
+ pc->clk_pwms = devm_kmalloc_array(&pdev->dev, pc->soc->num_pwms,
sizeof(*pc->clk_pwms), GFP_KERNEL);
if (!pc->clk_pwms)
return -ENOMEM;
pc->clk_top = devm_clk_get(&pdev->dev, "top");
- if (IS_ERR(pc->clk_top)) {
- dev_err(&pdev->dev, "clock: top fail: %ld\n",
- PTR_ERR(pc->clk_top));
- return PTR_ERR(pc->clk_top);
- }
+ if (IS_ERR(pc->clk_top))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
+ "Failed to get top clock\n");
pc->clk_main = devm_clk_get(&pdev->dev, "main");
- if (IS_ERR(pc->clk_main)) {
- dev_err(&pdev->dev, "clock: main fail: %ld\n",
- PTR_ERR(pc->clk_main));
- return PTR_ERR(pc->clk_main);
- }
+ if (IS_ERR(pc->clk_main))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
+ "Failed to get main clock\n");
for (i = 0; i < pc->soc->num_pwms; i++) {
char name[8];
@@ -246,11 +262,9 @@ static int pwm_mediatek_probe(struct pla
snprintf(name, sizeof(name), "pwm%d", i + 1);
pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
- if (IS_ERR(pc->clk_pwms[i])) {
- dev_err(&pdev->dev, "clock: %s fail: %ld\n",
- name, PTR_ERR(pc->clk_pwms[i]));
- return PTR_ERR(pc->clk_pwms[i]);
- }
+ if (IS_ERR(pc->clk_pwms[i]))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
+ "Failed to get %s clock\n", name);
}
pc->chip.dev = &pdev->dev;
@@ -258,10 +272,8 @@ static int pwm_mediatek_probe(struct pla
pc->chip.npwm = pc->soc->num_pwms;
ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
- if (ret < 0) {
- dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
- return ret;
- }
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
return 0;
}
@@ -270,48 +282,63 @@ static const struct pwm_mediatek_of_data
@@ -270,48 +275,63 @@ static const struct pwm_mediatek_of_data
.num_pwms = 8,
.pwm45_fixup = false,
.has_ck_26m_sel = false,
+ .reg_ver = REG_V1,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct pwm_mediatek_of_data mt7622_pwm_data = {
.num_pwms = 6,
.pwm45_fixup = false,
.has_ck_26m_sel = true,
+ .reg_ver = REG_V1,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct pwm_mediatek_of_data mt7623_pwm_data = {
.num_pwms = 5,
.pwm45_fixup = true,
.has_ck_26m_sel = false,
+ .reg_ver = REG_V1,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct pwm_mediatek_of_data mt7628_pwm_data = {
.num_pwms = 4,
.pwm45_fixup = true,
.has_ck_26m_sel = false,
+ .reg_ver = REG_V1,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct pwm_mediatek_of_data mt7629_pwm_data = {
.num_pwms = 1,
.pwm45_fixup = false,
.has_ck_26m_sel = false,
+ .reg_ver = REG_V1,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
-static const struct pwm_mediatek_of_data mt8183_pwm_data = {
- .num_pwms = 4,
+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
+ .num_pwms = 3,
static const struct pwm_mediatek_of_data mt8183_pwm_data = {
.num_pwms = 4,
.pwm45_fixup = false,
.has_ck_26m_sel = true,
+ .reg_ver = REG_V2,
+ .reg_offset = mtk_pwm_reg_offset_v1,
+};
+
+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
+ .num_pwms = 3,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = true,
+ .reg_offset = mtk_pwm_reg_offset_v2,
};
static const struct pwm_mediatek_of_data mt7986_pwm_data = {
.num_pwms = 2,
.pwm45_fixup = false,
.has_ck_26m_sel = true,
+ .reg_ver = REG_V1,
+};
+
+static const struct pwm_mediatek_of_data mt8183_pwm_data = {
+ .num_pwms = 4,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = true,
+ .reg_ver = REG_V1,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct pwm_mediatek_of_data mt8516_pwm_data = {
.num_pwms = 5,
.pwm45_fixup = false,
.has_ck_26m_sel = true,
+ .reg_ver = REG_V1,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct of_device_id pwm_mediatek_of_match[] = {
@@ -320,6 +347,7 @@ static const struct of_device_id pwm_med
@@ -320,6 +340,7 @@ static const struct of_device_id pwm_med
{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },