From aa403a440ad81b3430759d951cee1754ba5e4722 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Tue, 18 Aug 2020 15:09:22 +0200 Subject: [PATCH 01/17] dnsmasq: abort dhcp_check on interface state Abort the dhcp-check based on the interface instead of the carrier state. In cases where the interface is up but the carrier is down, netifd won't cause a dnsmasq reload, thus dhcp won't become active on this interface. Signed-off-by: David Bauer --- package/network/services/dnsmasq/files/dnsmasq.init | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/network/services/dnsmasq/files/dnsmasq.init b/package/network/services/dnsmasq/files/dnsmasq.init index 932103d8b5..2d72bc6a28 100644 --- a/package/network/services/dnsmasq/files/dnsmasq.init +++ b/package/network/services/dnsmasq/files/dnsmasq.init @@ -106,9 +106,9 @@ dhcp_check() { [ -s "$stamp" ] && return $(cat "$stamp") - # If there's no carrier yet, skip this interface. + # If interface is down, skip it. # The init script will be called again once the link is up - case "$(devstatus "$ifname" | jsonfilter -e @.carrier)" in + case "$(devstatus "$ifname" | jsonfilter -e @.up)" in false) return 1;; esac From 14ae431c836d81830a510ebed0937d862491a058 Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Tue, 18 Aug 2020 22:25:38 +0200 Subject: [PATCH 02/17] lantiq: remove vmmc node from FritzBox 7412 dts As described in commit commit 891a7007598d ("lantiq: enable second VPE on Fritz!Box 7412"): The AVM Fritz!Box 7412 does not use the VMMC part of the Lantiq chip but rather a proprietary solution based on the DECT chip for the FXS ports. We can remove last traces of vmmc in dts. Signed-off-by: Aleksander Jan Bajkowski --- .../files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts index 43216d66be..fe02d53c83 100644 --- a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts @@ -212,7 +212,3 @@ }; }; }; - -&vmmc { - status = "okay"; -}; From eb531337a779a48a2d17bc66f0d222325d6c1563 Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Tue, 18 Aug 2020 13:49:15 +0200 Subject: [PATCH 03/17] ath79: add support for TP-Link TL-WR710N v2.1 This adds support for the TP-Link TL-WR710N v2.1. It is basically a re-issue of the v1.2. Specifications: SoC: Atheros AR9331 CPU: 400 MHz Flash: 8 MiB RAM: 32 MiB WiFi: 2.4 GHz b/g/n Ethernet: 2x 100M ports USB: 1x 2.0 The only difference from the v1 is the TP-Link hardware ID/revision. Attention: The TL-WR710N v2.0 (!) has only 4 MB flash and cannot be flashed with this image. It has a different TPLINK_HWREV, so accidental flashing of the factory image should be impossible without additional measures. Unfortunately, the v2.0 in ar71xx has the same board name, so sysupgrade from ar71xx v2.0 into ath79 v1/v2.1 will not be prevented, but will brick the device. Flashing instruction: Upload the factory image via the OEM firmware GUI upgrade mechanism. Further notes: To make implementation easier if somebody desires to port the 4M v2.0, this already creates two DTSI files. Signed-off-by: Adrian Schmutzler Tested-by: Fabian Eppig --- .../ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi | 39 ++++++ .../ath79/dts/ar9331_tplink_tl-wr710n-v1.dts | 118 +----------------- .../dts/ar9331_tplink_tl-wr710n-v2.1.dts | 9 ++ .../ath79/dts/ar9331_tplink_tl-wr710n.dtsi | 88 +++++++++++++ target/linux/ath79/image/generic-tp-link.mk | 12 ++ 5 files changed, 149 insertions(+), 117 deletions(-) create mode 100644 target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi create mode 100644 target/linux/ath79/dts/ar9331_tplink_tl-wr710n-v2.1.dts create mode 100644 target/linux/ath79/dts/ar9331_tplink_tl-wr710n.dtsi diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi new file mode 100644 index 0000000000..ffc98e6e1c --- /dev/null +++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "ar9331_tplink_tl-wr710n.dtsi" + +&spi { + status = "okay"; + + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + uboot: partition@0 { + reg = <0x0 0x20000>; + label = "u-boot"; + read-only; + }; + + partition@20000 { + compatible = "tplink,firmware"; + reg = <0x20000 0x7d0000>; + label = "firmware"; + }; + + art: partition@7f0000 { + reg = <0x7f0000 0x10000>; + label = "art"; + read-only; + }; + }; + }; +}; diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-v1.dts b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-v1.dts index 493dbfe7b6..634b56d3be 100644 --- a/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-v1.dts +++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-v1.dts @@ -1,125 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include -#include - -#include "ar9331.dtsi" +#include "ar9331_tplink_tl-wr710n-8m.dtsi" / { model = "TP-Link TL-WR710N v1"; compatible = "tplink,tl-wr710n-v1", "qca,ar9331"; - - aliases { - serial0 = &uart; - led-boot = &led_system; - led-failsafe = &led_system; - led-running = &led_system; - led-upgrade = &led_system; - label-mac-device = ð0; - }; - - keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - linux,code = ; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - debounce-interval = <60>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led_system: system { - label = "tl-wr710n:green:system"; - gpios = <&gpio 27 GPIO_ACTIVE_LOW>; - }; - }; - - reg_usb_vbus: regulator { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&spi { - status = "okay"; - num-cs = <1>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - uboot: partition@0 { - reg = <0x0 0x20000>; - label = "u-boot"; - read-only; - }; - - firmware: partition@20000 { - compatible = "tplink,firmware"; - reg = <0x20000 0x7d0000>; - label = "firmware"; - }; - - art: partition@7f0000 { - reg = <0x7f0000 0x10000>; - label = "art"; - read-only; - }; - }; - }; -}; - -ð0 { - status = "okay"; - - mtd-mac-address = <&uboot 0x1fc00>; - - gmac-config { - device = <&gmac>; - - switch-phy-addr-swap = <0>; - switch-phy-swap = <0>; - }; -}; - -ð1 { - status = "okay"; - - mtd-mac-address = <&uboot 0x1fc00>; - mtd-mac-address-increment = <(-1)>; -}; - -&uart { - status = "okay"; -}; - -&usb { - dr_mode = "host"; - vbus-supply = <®_usb_vbus>; - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; - -&wmac { - status = "okay"; - mtd-cal-data = <&art 0x1000>; - mtd-mac-address = <&uboot 0x1fc00>; }; diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-v2.1.dts b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-v2.1.dts new file mode 100644 index 0000000000..48d44000ee --- /dev/null +++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-v2.1.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "ar9331_tplink_tl-wr710n-8m.dtsi" + +/ { + model = "TP-Link TL-WR710N v2.1"; + compatible = "tplink,tl-wr710n-v2.1", "qca,ar9331"; +}; diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr710n.dtsi b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n.dtsi new file mode 100644 index 0000000000..e37c43f4a7 --- /dev/null +++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include + +#include "ar9331.dtsi" + +/ { + aliases { + serial0 = &uart; + led-boot = &led_system; + led-failsafe = &led_system; + led-running = &led_system; + led-upgrade = &led_system; + label-mac-device = ð0; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_system: system { + label = "tl-wr710n:green:system"; + gpios = <&gpio 27 GPIO_ACTIVE_LOW>; + }; + }; + + reg_usb_vbus: regulator { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð0 { + status = "okay"; + + mtd-mac-address = <&uboot 0x1fc00>; + + gmac-config { + device = <&gmac>; + + switch-phy-addr-swap = <0>; + switch-phy-swap = <0>; + }; +}; + +ð1 { + status = "okay"; + + mtd-mac-address = <&uboot 0x1fc00>; + mtd-mac-address-increment = <(-1)>; +}; + +&uart { + status = "okay"; +}; + +&usb { + status = "okay"; + + dr_mode = "host"; + vbus-supply = <®_usb_vbus>; +}; + +&usb_phy { + status = "okay"; +}; + +&wmac { + status = "okay"; + + mtd-cal-data = <&art 0x1000>; + mtd-mac-address = <&uboot 0x1fc00>; +}; diff --git a/target/linux/ath79/image/generic-tp-link.mk b/target/linux/ath79/image/generic-tp-link.mk index fdc94b738a..7128d853f8 100644 --- a/target/linux/ath79/image/generic-tp-link.mk +++ b/target/linux/ath79/image/generic-tp-link.mk @@ -625,6 +625,18 @@ define Device/tplink_tl-wr710n-v1 endef TARGET_DEVICES += tplink_tl-wr710n-v1 +define Device/tplink_tl-wr710n-v2.1 + $(Device/tplink-8mlzma) + SOC := ar9331 + DEVICE_MODEL := TL-WR710N + DEVICE_VARIANT := v2.1 + DEVICE_PACKAGES := kmod-usb-chipidea2 kmod-usb-ledtrig-usbport + TPLINK_HWID := 0x07100002 + TPLINK_HWREV := 0x2 + SUPPORTED_DEVICES += tl-wr710n +endef +TARGET_DEVICES += tplink_tl-wr710n-v2.1 + define Device/tplink_tl-wr810n-v1 $(Device/tplink-8mlzma) SOC := qca9531 From b0751d4c0f1227e9dc31c6e4c210476aa3be1b9c Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 15 Aug 2020 16:43:19 +0200 Subject: [PATCH 04/17] kernel: wpan: Add missing AUTOLOAD to load kernel module These kernel modules were not loaded automatically, fix this by adding the AUTOLOAD definition. Signed-off-by: Hauke Mehrtens --- package/kernel/linux/modules/wpan.mk | 3 +++ 1 file changed, 3 insertions(+) diff --git a/package/kernel/linux/modules/wpan.mk b/package/kernel/linux/modules/wpan.mk index 053fa1e4bf..1de7f39b66 100644 --- a/package/kernel/linux/modules/wpan.mk +++ b/package/kernel/linux/modules/wpan.mk @@ -88,6 +88,7 @@ define KernelPackage/at86rf230 CONFIG_SPI=y \ CONFIG_SPI_MASTER=y FILES:=$(LINUX_DIR)/drivers/net/ieee802154/at86rf230.ko + AUTOLOAD:=$(call AutoProbe,at86rf230) endef $(eval $(call KernelPackage,at86rf230)) @@ -100,6 +101,7 @@ define KernelPackage/mrf24j40 CONFIG_SPI=y \ CONFIG_SPI_MASTER=y FILES:=$(LINUX_DIR)/drivers/net/ieee802154/mrf24j40.ko + AUTOLOAD:=$(call AutoProbe,mrf24j40) endef $(eval $(call KernelPackage,mrf24j40)) @@ -112,6 +114,7 @@ define KernelPackage/cc2520 CONFIG_SPI=y \ CONFIG_SPI_MASTER=y FILES:=$(LINUX_DIR)/drivers/net/ieee802154/cc2520.ko + AUTOLOAD:=$(call AutoProbe,cc2520) endef $(eval $(call KernelPackage,cc2520)) From 5efe459012393dcaa0623225e1cb069cb326a66e Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 15 Aug 2020 16:44:23 +0200 Subject: [PATCH 05/17] kernel: wpan: Add kmod-ca8210 This device is found on the pistachio marduk board. Signed-off-by: Hauke Mehrtens --- package/kernel/linux/modules/wpan.mk | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/package/kernel/linux/modules/wpan.mk b/package/kernel/linux/modules/wpan.mk index 1de7f39b66..dab8a0cb71 100644 --- a/package/kernel/linux/modules/wpan.mk +++ b/package/kernel/linux/modules/wpan.mk @@ -119,6 +119,22 @@ endef $(eval $(call KernelPackage,cc2520)) + +define KernelPackage/ca8210 + SUBMENU:=$(WPAN_MENU) + TITLE:=CA8210 transceiver driver + DEPENDS:=+kmod-mac802154 + KCONFIG:=CONFIG_IEEE802154_CA8210 \ + CONFIG_SPI=y \ + CONFIG_SPI_MASTER=y \ + CONFIG_IEEE802154_CA8210_DEBUGFS=n + FILES:=$(LINUX_DIR)/drivers/net/ieee802154/ca8210.ko + AUTOLOAD:=$(call AutoProbe,ca8210) +endef + +$(eval $(call KernelPackage,ca8210)) + + define KernelPackage/ieee802154-6lowpan SUBMENU:=$(WPAN_MENU) TITLE:= 6LoWPAN support over IEEE-802.15.4 From aefa9d39c3f6caea2d464100686496120568e10a Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 15 Aug 2020 19:34:00 +0200 Subject: [PATCH 06/17] kernel: Add GigaDevice GD5F4GQ4xC SPI NAND flash This flash was found on the Imagination Technologies Creator Ci40 (Marduk). Signed-off-by: Hauke Mehrtens --- ...igadevice-Only-one-dummy-byte-in-QUA.patch | 39 +++++++++ ...46-mtd-spinand-gigadevice-Add-QE-Bit.patch | 67 ++++++++++++++ ...igadevice-Add-support-for-GD5F4GQ4xC.patch | 87 +++++++++++++++++++ 3 files changed, 193 insertions(+) create mode 100644 target/linux/generic/pending-5.4/445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch create mode 100644 target/linux/generic/pending-5.4/446-mtd-spinand-gigadevice-Add-QE-Bit.patch create mode 100644 target/linux/generic/pending-5.4/447-mtd-spinand-gigadevice-Add-support-for-GD5F4GQ4xC.patch diff --git a/target/linux/generic/pending-5.4/445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch b/target/linux/generic/pending-5.4/445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch new file mode 100644 index 0000000000..0391094d27 --- /dev/null +++ b/target/linux/generic/pending-5.4/445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch @@ -0,0 +1,39 @@ +From 5f312dcb38b8003d9711290366cd4b1def5daf3b Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 16 Aug 2020 14:43:35 +0200 +Subject: [PATCH v2 445/447] mtd: spinand: gigadevice: Only one dummy byte in + QUADIO + +The datasheet only lists one dummy byte in the 0xEH operation for the +following chips: +* GD5F1GQ4xExxG +* GD5F1GQ4xFxxG +* GD5F1GQ4UAYIG +* GD5F4GQ4UAYIG + +Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA") +Signed-off-by: Hauke Mehrtens +--- + drivers/mtd/nand/spi/gigadevice.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/mtd/nand/spi/gigadevice.c ++++ b/drivers/mtd/nand/spi/gigadevice.c +@@ -21,7 +21,7 @@ + #define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4) + + static SPINAND_OP_VARIANTS(read_cache_variants, +- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), +@@ -29,7 +29,7 @@ static SPINAND_OP_VARIANTS(read_cache_va + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + + static SPINAND_OP_VARIANTS(read_cache_variants_f, +- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0), diff --git a/target/linux/generic/pending-5.4/446-mtd-spinand-gigadevice-Add-QE-Bit.patch b/target/linux/generic/pending-5.4/446-mtd-spinand-gigadevice-Add-QE-Bit.patch new file mode 100644 index 0000000000..034cd2a8f0 --- /dev/null +++ b/target/linux/generic/pending-5.4/446-mtd-spinand-gigadevice-Add-QE-Bit.patch @@ -0,0 +1,67 @@ +From f72e99ada020a81e3e4ef79c0a83ede7e9d6c7b1 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 16 Aug 2020 14:42:17 +0200 +Subject: [PATCH v2 446/447] mtd: spinand: gigadevice: Add QE Bit + +The following GigaDevice chips have the QE BIT in the feature flags, I +checked the datasheets, but did not try this. +* GD5F1GQ4xExxG +* GD5F1GQ4xFxxG +* GD5F1GQ4UAYIG +* GD5F4GQ4UAYIG + +The Quad operations like 0xEB mention that the QE bit has to be set. + +Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA") +Signed-off-by: Hauke Mehrtens +--- + drivers/mtd/nand/spi/gigadevice.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/mtd/nand/spi/gigadevice.c ++++ b/drivers/mtd/nand/spi/gigadevice.c +@@ -201,7 +201,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), + SPINAND_INFO("GD5F2GQ4xA", 0xF2, +@@ -210,7 +210,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), + SPINAND_INFO("GD5F4GQ4xA", 0xF4, +@@ -219,7 +219,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), + SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, +@@ -228,7 +228,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, + gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148, +@@ -237,7 +237,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, + gd5fxgq4ufxxg_ecc_get_status)), + }; diff --git a/target/linux/generic/pending-5.4/447-mtd-spinand-gigadevice-Add-support-for-GD5F4GQ4xC.patch b/target/linux/generic/pending-5.4/447-mtd-spinand-gigadevice-Add-support-for-GD5F4GQ4xC.patch new file mode 100644 index 0000000000..e1fcb15d5a --- /dev/null +++ b/target/linux/generic/pending-5.4/447-mtd-spinand-gigadevice-Add-support-for-GD5F4GQ4xC.patch @@ -0,0 +1,87 @@ +From 30521ccfb4597f91b9e5c7967acef9c7c85e58a8 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Wed, 12 Aug 2020 22:50:26 +0200 +Subject: [PATCH v2 447/447] mtd: spinand: gigadevice: Add support for + GD5F4GQ4xC + +This adds support for the following 4GiB chips: +GD5F4GQ4RCYIG 1.8V +GD5F4GQ4UCYIG 3.3V + +The datasheet can be found here: +https://www.novitronic.ch/sixcms/media.php/2/DS-00173-GD5F4GQ4xCxIG-Rev1.574695.pdf + +The GD5F4GQ4UCYIGT (3.3V) version is used on the Imagination +Technologies Creator Ci40 (Marduk), the 1.8V version was not tested. + +This device only works in single SPI mode and not in dual or quad mode +for me on this board. + +Signed-off-by: Hauke Mehrtens +--- + drivers/mtd/nand/spi/gigadevice.c | 49 +++++++++++++++++++++++++++++++ + 1 file changed, 49 insertions(+) + +--- a/drivers/mtd/nand/spi/gigadevice.c ++++ b/drivers/mtd/nand/spi/gigadevice.c +@@ -132,6 +132,35 @@ static const struct mtd_ooblayout_ops gd + .free = gd5fxgq4_variant2_ooblayout_free, + }; + ++static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobregion) ++{ ++ if (section) ++ return -ERANGE; ++ ++ oobregion->offset = 128; ++ oobregion->length = 128; ++ ++ return 0; ++} ++ ++static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobregion) ++{ ++ if (section) ++ return -ERANGE; ++ ++ oobregion->offset = 1; ++ oobregion->length = 127; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = { ++ .ecc = gd5fxgq4xc_ooblayout_256_ecc, ++ .free = gd5fxgq4xc_ooblayout_256_free, ++}; ++ + static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, + u8 status) + { +@@ -222,6 +251,24 @@ static const struct spinand_info gigadev + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), ++ SPINAND_INFO("GD5F4GQ4RC", 0xa468, ++ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops, ++ gd5fxgq4ufxxg_ecc_get_status)), ++ SPINAND_INFO("GD5F4GQ4UC", 0xb468, ++ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops, ++ gd5fxgq4ufxxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), From 4291a0d58a506f4e2f32de7918c3fc72145053ce Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 9 Aug 2020 19:27:48 +0200 Subject: [PATCH 07/17] pistachio: Copy kernel 4.14 to 5.4 This only copies the patches and configuration without doing any modification to the files. Signed-off-by: Hauke Mehrtens --- target/linux/pistachio/config-5.4 | 354 +++++++++ ...ine-img-mdc-Handle-early-status-read.patch | 68 ++ ...mg-spfi-Implement-dual-and-quad-mode.patch | 198 +++++ ...-device-select-bits-for-SPFI-port-st.patch | 27 + ...-device-0-configuration-for-all-devi.patch | 64 ++ ...i-RX-maximum-burst-size-for-DMA-is-8.patch | 59 ++ ...g-spfi-finish-every-transfer-cleanly.patch | 120 +++ ...y-programming-min-delta-up-to-10-tim.patch | 66 ++ ...istachio-Fix-wrong-SDHost-card-speed.patch | 49 ++ ...-img-marduk-switch-mmc-to-1-bit-mode.patch | 47 ++ ...or-support-mtd-name-from-device-tree.patch | 34 + ...ength-of-ID-before-reading-bits-per-.patch | 33 + ...JEDEC-manufacturer-ID-for-Gigadevice.patch | 35 + ...413-mtd-Introduce-SPI-NAND-framework.patch | 707 ++++++++++++++++++ ...mtd-spi-nand-Support-Gigadevice-GD5F.patch | 524 +++++++++++++ ...TS-img-marduk-add-nor-partition-name.patch | 20 + ...S-img-marduk-add-nand-device-support.patch | 30 + 17 files changed, 2435 insertions(+) create mode 100644 target/linux/pistachio/config-5.4 create mode 100644 target/linux/pistachio/patches-5.4/101-dmaengine-img-mdc-Handle-early-status-read.patch create mode 100644 target/linux/pistachio/patches-5.4/102-spi-img-spfi-Implement-dual-and-quad-mode.patch create mode 100644 target/linux/pistachio/patches-5.4/103-spi-img-spfi-set-device-select-bits-for-SPFI-port-st.patch create mode 100644 target/linux/pistachio/patches-5.4/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch create mode 100644 target/linux/pistachio/patches-5.4/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch create mode 100644 target/linux/pistachio/patches-5.4/106-spi-img-spfi-finish-every-transfer-cleanly.patch create mode 100644 target/linux/pistachio/patches-5.4/107-clockevents-Retry-programming-min-delta-up-to-10-tim.patch create mode 100644 target/linux/pistachio/patches-5.4/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch create mode 100644 target/linux/pistachio/patches-5.4/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch create mode 100644 target/linux/pistachio/patches-5.4/401-mtd-nor-support-mtd-name-from-device-tree.patch create mode 100644 target/linux/pistachio/patches-5.4/411-mtd-nand-Check-length-of-ID-before-reading-bits-per-.patch create mode 100644 target/linux/pistachio/patches-5.4/412-mtd-nand-Add-JEDEC-manufacturer-ID-for-Gigadevice.patch create mode 100644 target/linux/pistachio/patches-5.4/413-mtd-Introduce-SPI-NAND-framework.patch create mode 100644 target/linux/pistachio/patches-5.4/414-mtd-spi-nand-Support-Gigadevice-GD5F.patch create mode 100644 target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-add-nor-partition-name.patch create mode 100644 target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-add-nand-device-support.patch diff --git a/target/linux/pistachio/config-5.4 b/target/linux/pistachio/config-5.4 new file mode 100644 index 0000000000..8b24b68a05 --- /dev/null +++ b/target/linux/pistachio/config-5.4 @@ -0,0 +1,354 @@ +CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +# CONFIG_ARCH_HAS_STRICT_KERNEL_RWX is not set +# CONFIG_ARCH_HAS_STRICT_MODULE_RWX is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BOARD_SCACHE=y +CONFIG_BOOT_ELF32=y +CONFIG_CEVT_R4K=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MIPS_GIC=y +CONFIG_CLKSRC_PISTACHIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_BOSTON is not set +CONFIG_CONNECTOR=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_PM=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRC16=y +CONFIG_CRC_CCITT=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CSRC_R4K=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_OF=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +# CONFIG_DWMAC_DWC_QOS_ETH is not set +CONFIG_DWMAC_GENERIC=y +CONFIG_EARLY_PRINTK=y +CONFIG_EARLY_PRINTK_8250=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FIXED_PHY=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_GRO_CELLS is not set +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_CBPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KVM=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HOTPLUG_CPU=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_IMG=y +CONFIG_IMGPDC_WDT=y +CONFIG_IMG_MDC_DMA=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_LEDS_PWM=y +CONFIG_LIBFDT=y +CONFIG_LKDTM=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACH_PISTACHIO=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0 +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CLOCK_VSYSCALL=y +CONFIG_MIPS_CM=y +# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_MIPS_CMDLINE_FROM_DTB is not set +CONFIG_MIPS_CPC=y +CONFIG_MIPS_CPS=y +# CONFIG_MIPS_CPS_CPUIDLE is not set +# CONFIG_MIPS_CPS_NS16550 is not set +CONFIG_MIPS_CPS_PM=y +CONFIG_MIPS_CPU_SCACHE=y +# CONFIG_MIPS_ELF_APPENDED_DTB is not set +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_MIPS_GIC=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_MT=y +CONFIG_MIPS_MT_FPAFF=y +CONFIG_MIPS_MT_SMP=y +CONFIG_MIPS_NO_APPENDED_DTB=y +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +# CONFIG_MIPS_RAW_APPENDED_DTB is not set +CONFIG_MIPS_SPRAM=y +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_DW=y +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_K3 is not set +CONFIG_MMC_DW_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NAND_DEVICES=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384 +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_FASTMAP=y +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NAMESPACES=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_NS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NLS=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_IOPORT_MAP is not set +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_PADATA=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +# CONFIG_PGTABLE_MAPPING is not set +CONFIG_PHYLIB=y +CONFIG_PHY_PISTACHIO_USB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_PISTACHIO=y +CONFIG_PISTACHIO_GPTIMER_CLKSRC=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_EVENTS=y +CONFIG_PROFILING=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PWM=y +CONFIG_PWM_IMG=y +CONFIG_PWM_SYSFS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RATIONAL=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_PISTACHIO=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_INFO=y +CONFIG_SCSI=y +CONFIG_SCSI_SPI_ATTRS=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_FSL is not set +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SPI=y +CONFIG_SPI_IMG_SPFI=y +CONFIG_SPI_MASTER=y +CONFIG_SRAM=y +CONFIG_SRCU=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_SWPHY=y +CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS_CPS=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_RELOCATABLE=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_COMMON=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_DUAL_ROLE=y +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USER_NS=y +CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y +CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WEAK_ORDERING=y +CONFIG_XPS=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSMALLOC=y +# CONFIG_ZSMALLOC_STAT is not set diff --git a/target/linux/pistachio/patches-5.4/101-dmaengine-img-mdc-Handle-early-status-read.patch b/target/linux/pistachio/patches-5.4/101-dmaengine-img-mdc-Handle-early-status-read.patch new file mode 100644 index 0000000000..92293f8796 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/101-dmaengine-img-mdc-Handle-early-status-read.patch @@ -0,0 +1,68 @@ +From a2dd154377c9aa6ddda00d39b8c7c334e4fa16ff Mon Sep 17 00:00:00 2001 +From: Damien Horsley +Date: Tue, 22 Mar 2016 12:46:09 +0000 +Subject: dmaengine: img-mdc: Handle early status read + +It is possible that mdc_tx_status may be called before the first +node has been read from memory. + +In this case, the residue value stored in the register is undefined. +Return the transfer size instead. + +Signed-off-by: Damien Horsley +--- + drivers/dma/img-mdc-dma.c | 40 ++++++++++++++++++++++++---------------- + 1 file changed, 24 insertions(+), 16 deletions(-) + +--- a/drivers/dma/img-mdc-dma.c ++++ b/drivers/dma/img-mdc-dma.c +@@ -620,25 +620,33 @@ static enum dma_status mdc_tx_status(str + (MDC_CMDS_PROCESSED_CMDS_DONE_MASK + 1); + + /* +- * If the command loaded event hasn't been processed yet, then +- * the difference above includes an extra command. ++ * If the first node has not yet been read from memory, ++ * the residue register value is undefined + */ +- if (!mdesc->cmd_loaded) +- cmds--; +- else +- cmds += mdesc->list_cmds_done; +- +- bytes = mdesc->list_xfer_size; +- ldesc = mdesc->list; +- for (i = 0; i < cmds; i++) { +- bytes -= ldesc->xfer_size + 1; +- ldesc = ldesc->next_desc; +- } +- if (ldesc) { +- if (residue != MDC_TRANSFER_SIZE_MASK) +- bytes -= ldesc->xfer_size - residue; ++ if (!mdesc->cmd_loaded && !cmds) { ++ bytes = mdesc->list_xfer_size; ++ } else { ++ /* ++ * If the command loaded event hasn't been processed yet, then ++ * the difference above includes an extra command. ++ */ ++ if (!mdesc->cmd_loaded) ++ cmds--; + else ++ cmds += mdesc->list_cmds_done; ++ ++ bytes = mdesc->list_xfer_size; ++ ldesc = mdesc->list; ++ for (i = 0; i < cmds; i++) { + bytes -= ldesc->xfer_size + 1; ++ ldesc = ldesc->next_desc; ++ } ++ if (ldesc) { ++ if (residue != MDC_TRANSFER_SIZE_MASK) ++ bytes -= ldesc->xfer_size - residue; ++ else ++ bytes -= ldesc->xfer_size + 1; ++ } + } + } + spin_unlock_irqrestore(&mchan->vc.lock, flags); diff --git a/target/linux/pistachio/patches-5.4/102-spi-img-spfi-Implement-dual-and-quad-mode.patch b/target/linux/pistachio/patches-5.4/102-spi-img-spfi-Implement-dual-and-quad-mode.patch new file mode 100644 index 0000000000..15a5d3c806 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/102-spi-img-spfi-Implement-dual-and-quad-mode.patch @@ -0,0 +1,198 @@ +From cd2a6af51553d38072cd31699b58d16ca6176ef5 Mon Sep 17 00:00:00 2001 +From: Ionela Voinescu +Date: Thu, 2 Feb 2017 16:46:14 +0000 +Subject: spi: img-spfi: Implement dual and quad mode + +For dual and quad modes to work the SPFI controller needs +to have information about command/address/dummy bytes in the +transaction register. This information is not relevant for +single mode, and therefore it can have any value in the +allowed range. Therefore, for any read or write transfers of less +than 8 bytes (cmd = 1 byte, addr up to 7 bytes), SPFI will be +configured, but not enabled (unless it is the last transfer in +the queue). The transfer will be enabled by the subsequent tranfer. +A pending transfer is determined by the content of the transaction +register: if command part is set and tsize is not. + +This way we ensure that for dual and quad transactions +the command request size will apear in the command/address part +of the transaction register, while the data size will be in +tsize, all data being sent/received in the same transaction (as +set up in the transaction register). + +Signed-off-by: Ionela Voinescu +Signed-off-by: Ezequiel Garcia +--- + drivers/spi/spi-img-spfi.c | 96 ++++++++++++++++++++++++++++++++++++++++------ + 1 file changed, 85 insertions(+), 11 deletions(-) + +--- a/drivers/spi/spi-img-spfi.c ++++ b/drivers/spi/spi-img-spfi.c +@@ -40,7 +40,8 @@ + #define SPFI_CONTROL_SOFT_RESET BIT(11) + #define SPFI_CONTROL_SEND_DMA BIT(10) + #define SPFI_CONTROL_GET_DMA BIT(9) +-#define SPFI_CONTROL_SE BIT(8) ++#define SPFI_CONTROL_SE BIT(8) ++#define SPFI_CONTROL_TX_RX BIT(1) + #define SPFI_CONTROL_TMODE_SHIFT 5 + #define SPFI_CONTROL_TMODE_MASK 0x7 + #define SPFI_CONTROL_TMODE_SINGLE 0 +@@ -51,6 +52,10 @@ + #define SPFI_TRANSACTION 0x18 + #define SPFI_TRANSACTION_TSIZE_SHIFT 16 + #define SPFI_TRANSACTION_TSIZE_MASK 0xffff ++#define SPFI_TRANSACTION_CMD_SHIFT 13 ++#define SPFI_TRANSACTION_CMD_MASK 0x7 ++#define SPFI_TRANSACTION_ADDR_SHIFT 10 ++#define SPFI_TRANSACTION_ADDR_MASK 0x7 + + #define SPFI_PORT_STATE 0x1c + #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20 +@@ -87,6 +92,7 @@ + */ + #define SPFI_32BIT_FIFO_SIZE 64 + #define SPFI_8BIT_FIFO_SIZE 16 ++#define SPFI_DATA_REQUEST_MAX_SIZE 8 + + struct img_spfi { + struct device *dev; +@@ -103,6 +109,8 @@ struct img_spfi { + struct dma_chan *tx_ch; + bool tx_dma_busy; + bool rx_dma_busy; ++ ++ bool complete; + }; + + struct img_spfi_device_data { +@@ -123,9 +131,11 @@ static inline void spfi_start(struct img + { + u32 val; + +- val = spfi_readl(spfi, SPFI_CONTROL); +- val |= SPFI_CONTROL_SPFI_EN; +- spfi_writel(spfi, val, SPFI_CONTROL); ++ if (spfi->complete) { ++ val = spfi_readl(spfi, SPFI_CONTROL); ++ val |= SPFI_CONTROL_SPFI_EN; ++ spfi_writel(spfi, val, SPFI_CONTROL); ++ } + } + + static inline void spfi_reset(struct img_spfi *spfi) +@@ -138,12 +148,21 @@ static int spfi_wait_all_done(struct img + { + unsigned long timeout = jiffies + msecs_to_jiffies(50); + ++ if (!(spfi->complete)) ++ return 0; ++ + while (time_before(jiffies, timeout)) { + u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); + + if (status & SPFI_INTERRUPT_ALLDONETRIG) { + spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG, + SPFI_INTERRUPT_CLEAR); ++ /* ++ * Disable SPFI for it not to interfere with ++ * pending transactions ++ */ ++ spfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL) ++ & ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL); + return 0; + } + cpu_relax(); +@@ -494,9 +513,32 @@ static void img_spfi_config(struct spi_m + struct spi_transfer *xfer) + { + struct img_spfi *spfi = spi_master_get_devdata(spi->master); +- u32 val, div; ++ u32 val, div, transact; ++ bool is_pending; + + /* ++ * For read or write transfers of less than 8 bytes (cmd = 1 byte, ++ * addr up to 7 bytes), SPFI will be configured, but not enabled ++ * (unless it is the last transfer in the queue).The transfer will ++ * be enabled by the subsequent transfer. ++ * A pending transfer is determined by the content of the ++ * transaction register: if command part is set and tsize ++ * is not ++ */ ++ transact = spfi_readl(spfi, SPFI_TRANSACTION); ++ is_pending = ((transact >> SPFI_TRANSACTION_CMD_SHIFT) & ++ SPFI_TRANSACTION_CMD_MASK) && ++ (!((transact >> SPFI_TRANSACTION_TSIZE_SHIFT) & ++ SPFI_TRANSACTION_TSIZE_MASK)); ++ ++ /* If there are no pending transactions it's OK to soft reset */ ++ if (!is_pending) { ++ /* Start the transaction from a known (reset) state */ ++ spfi_reset(spfi); ++ } ++ ++ /* ++ * Before anything else, set up parameters. + * output = spfi_clk * (BITCLK / 512), where BITCLK must be a + * power of 2 up to 128 + */ +@@ -509,20 +551,52 @@ static void img_spfi_config(struct spi_m + val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT; + spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select)); + +- spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT, +- SPFI_TRANSACTION); ++ if (!list_is_last(&xfer->transfer_list, &master->cur_msg->transfers) && ++ /* ++ * For duplex mode (both the tx and rx buffers are !NULL) the ++ * CMD, ADDR, and DUMMY byte parts of the transaction register ++ * should always be 0 and therefore the pending transfer ++ * technique cannot be used. ++ */ ++ (xfer->tx_buf) && (!xfer->rx_buf) && ++ (xfer->len <= SPFI_DATA_REQUEST_MAX_SIZE) && !is_pending) { ++ transact = (1 & SPFI_TRANSACTION_CMD_MASK) << ++ SPFI_TRANSACTION_CMD_SHIFT; ++ transact |= ((xfer->len - 1) & SPFI_TRANSACTION_ADDR_MASK) << ++ SPFI_TRANSACTION_ADDR_SHIFT; ++ spfi->complete = false; ++ } else { ++ spfi->complete = true; ++ if (is_pending) { ++ /* Keep setup from pending transfer */ ++ transact |= ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) << ++ SPFI_TRANSACTION_TSIZE_SHIFT); ++ } else { ++ transact = ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) << ++ SPFI_TRANSACTION_TSIZE_SHIFT); ++ } ++ } ++ spfi_writel(spfi, transact, SPFI_TRANSACTION); + + val = spfi_readl(spfi, SPFI_CONTROL); + val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA); +- if (xfer->tx_buf) ++ /* ++ * We set up send DMA for pending transfers also, as ++ * those are always send transfers ++ */ ++ if ((xfer->tx_buf) || is_pending) + val |= SPFI_CONTROL_SEND_DMA; +- if (xfer->rx_buf) ++ if (xfer->tx_buf) ++ val |= SPFI_CONTROL_TX_RX; ++ if (xfer->rx_buf) { + val |= SPFI_CONTROL_GET_DMA; ++ val &= ~SPFI_CONTROL_TX_RX; ++ } + val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT); +- if (xfer->tx_nbits == SPI_NBITS_DUAL && ++ if (xfer->tx_nbits == SPI_NBITS_DUAL || + xfer->rx_nbits == SPI_NBITS_DUAL) + val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT; +- else if (xfer->tx_nbits == SPI_NBITS_QUAD && ++ else if (xfer->tx_nbits == SPI_NBITS_QUAD || + xfer->rx_nbits == SPI_NBITS_QUAD) + val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT; + val |= SPFI_CONTROL_SE; diff --git a/target/linux/pistachio/patches-5.4/103-spi-img-spfi-set-device-select-bits-for-SPFI-port-st.patch b/target/linux/pistachio/patches-5.4/103-spi-img-spfi-set-device-select-bits-for-SPFI-port-st.patch new file mode 100644 index 0000000000..ba70348da9 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/103-spi-img-spfi-set-device-select-bits-for-SPFI-port-st.patch @@ -0,0 +1,27 @@ +From 145f5369510b86cd55c659388a26a0cc267f8874 Mon Sep 17 00:00:00 2001 +From: Ionela Voinescu +Date: Mon, 1 Feb 2016 10:58:08 +0000 +Subject: spi: img-spfi: set device select bits for SPFI port state + +Even if the chip select line is not controlled by the SPFI +hardware, the device select bits need to be set to specify +the chip select line in use for the hardware to know what +parameters to use for the current transfer. + +Signed-off-by: Ionela Voinescu +--- + drivers/spi/spi-img-spfi.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/spi/spi-img-spfi.c ++++ b/drivers/spi/spi-img-spfi.c +@@ -438,6 +438,9 @@ static int img_spfi_prepare(struct spi_m + u32 val; + + val = spfi_readl(spfi, SPFI_PORT_STATE); ++ val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << ++ SPFI_PORT_STATE_DEV_SEL_SHIFT); ++ val |= msg->spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT; + if (msg->spi->mode & SPI_CPHA) + val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select); + else diff --git a/target/linux/pistachio/patches-5.4/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch b/target/linux/pistachio/patches-5.4/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch new file mode 100644 index 0000000000..6c9e6b5a76 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch @@ -0,0 +1,64 @@ +From 905ee06a9966113fe51d6bad1819759cb30fd0bd Mon Sep 17 00:00:00 2001 +From: Ionela Voinescu +Date: Tue, 9 Feb 2016 10:18:31 +0000 +Subject: spi: img-spfi: use device 0 configuration for all devices + +Given that we control the chip select line externally +we can use only one parameter register (device 0 parameter +register) and one set of configuration bits (port configuration +bits for device 0) for all devices (all chip select lines). + +Signed-off-by: Ionela Voinescu +--- + drivers/spi/spi-img-spfi.c | 23 ++++++++++++++++------- + 1 file changed, 16 insertions(+), 7 deletions(-) + +--- a/drivers/spi/spi-img-spfi.c ++++ b/drivers/spi/spi-img-spfi.c +@@ -437,18 +437,23 @@ static int img_spfi_prepare(struct spi_m + struct img_spfi *spfi = spi_master_get_devdata(master); + u32 val; + ++ /* ++ * The chip select line is controlled externally so ++ * we can use the CS0 configuration for all devices ++ */ + val = spfi_readl(spfi, SPFI_PORT_STATE); ++ ++ /* 0 for device selection */ + val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << + SPFI_PORT_STATE_DEV_SEL_SHIFT); +- val |= msg->spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT; + if (msg->spi->mode & SPI_CPHA) +- val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select); ++ val |= SPFI_PORT_STATE_CK_PHASE(0); + else +- val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select); ++ val &= ~SPFI_PORT_STATE_CK_PHASE(0); + if (msg->spi->mode & SPI_CPOL) +- val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select); ++ val |= SPFI_PORT_STATE_CK_POL(0); + else +- val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select); ++ val &= ~SPFI_PORT_STATE_CK_POL(0); + spfi_writel(spfi, val, SPFI_PORT_STATE); + + return 0; +@@ -548,11 +553,15 @@ static void img_spfi_config(struct spi_m + div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz); + div = clamp(512 / (1 << get_count_order(div)), 1, 128); + +- val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select)); ++ /* ++ * The chip select line is controlled externally so ++ * we can use the CS0 parameters for all devices ++ */ ++ val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(0)); + val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK << + SPFI_DEVICE_PARAMETER_BITCLK_SHIFT); + val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT; +- spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select)); ++ spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(0)); + + if (!list_is_last(&xfer->transfer_list, &master->cur_msg->transfers) && + /* diff --git a/target/linux/pistachio/patches-5.4/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch b/target/linux/pistachio/patches-5.4/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch new file mode 100644 index 0000000000..0067b0ea4a --- /dev/null +++ b/target/linux/pistachio/patches-5.4/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch @@ -0,0 +1,59 @@ +From 56466f505f58f44b69feb7eaed3b506842800456 Mon Sep 17 00:00:00 2001 +From: Ionela Voinescu +Date: Tue, 1 Mar 2016 17:49:45 +0000 +Subject: spi: img-spfi: RX maximum burst size for DMA is 8 + +The depth of the FIFOs is 16 bytes. The DMA request line is tied +to the half full/empty (depending on the use of the TX or RX FIFO) +threshold. For the TX FIFO, if you set a burst size of 8 (equal to +half the depth) the first burst goes into FIFO without any issues, +but due the latency involved (the time the data leaves the DMA +engine to the time it arrives at the FIFO), the DMA might trigger +another burst of 8. But given that there is no space for 2 additonal +bursts of 8, this would result in a failure. Therefore, we have to +keep the burst size for TX to 4 to accomodate for an extra burst. + +For the read (RX) scenario, the DMA request line goes high when +there is at least 8 entries in the FIFO (half full), and we can +program the burst size to be 8 because the risk of accidental burst +does not exist. The DMA engine will not trigger another read until +the read data for all the burst it has sent out has been received. + +While here, move the burst size setting outside of the if/else branches +as they have the same value for both 8 and 32 bit data widths. + +Signed-off-by: Ionela Voinescu +--- + drivers/spi/spi-img-spfi.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/spi/spi-img-spfi.c ++++ b/drivers/spi/spi-img-spfi.c +@@ -346,12 +346,11 @@ static int img_spfi_start_dma(struct spi + if (xfer->len % 4 == 0) { + rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA; + rxconf.src_addr_width = 4; +- rxconf.src_maxburst = 4; + } else { + rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA; + rxconf.src_addr_width = 1; +- rxconf.src_maxburst = 4; + } ++ rxconf.src_maxburst = 8; + dmaengine_slave_config(spfi->rx_ch, &rxconf); + + rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl, +@@ -370,12 +369,11 @@ static int img_spfi_start_dma(struct spi + if (xfer->len % 4 == 0) { + txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA; + txconf.dst_addr_width = 4; +- txconf.dst_maxburst = 4; + } else { + txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA; + txconf.dst_addr_width = 1; +- txconf.dst_maxburst = 4; + } ++ txconf.dst_maxburst = 4; + dmaengine_slave_config(spfi->tx_ch, &txconf); + + txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl, diff --git a/target/linux/pistachio/patches-5.4/106-spi-img-spfi-finish-every-transfer-cleanly.patch b/target/linux/pistachio/patches-5.4/106-spi-img-spfi-finish-every-transfer-cleanly.patch new file mode 100644 index 0000000000..0f958314e3 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/106-spi-img-spfi-finish-every-transfer-cleanly.patch @@ -0,0 +1,120 @@ +From 5fcca3fd4b621d7b5bdeca18d36dfc6ca6cfe383 Mon Sep 17 00:00:00 2001 +From: Ionela Voinescu +Date: Wed, 10 Aug 2016 11:42:26 +0100 +Subject: spi: img-spfi: finish every transfer cleanly + +Before this change, the interrupt status bit that signaled +the end of a tranfers was cleared in the wait_all_done +function. That functionality triggered issues for DMA +duplex transactions where the wait function was called +twice, in both the TX and RX callbacks. + +In order to fix the issue, clear all interrupt data bits +at the end of a PIO transfer or at the end of both TX and RX +duplex transfers, if the transfer is not a pending tranfer +(command waiting for data). After that, the status register +is checked for new incoming data or new data requests to be +signaled. If SPFI finished cleanly, no new interrupt data +bits should be set. + +Signed-off-by: Ionela Voinescu +--- + drivers/spi/spi-img-spfi.c | 49 +++++++++++++++++++++++++++++++++------------- + 1 file changed, 35 insertions(+), 14 deletions(-) + +--- a/drivers/spi/spi-img-spfi.c ++++ b/drivers/spi/spi-img-spfi.c +@@ -83,6 +83,14 @@ + #define SPFI_INTERRUPT_SDE BIT(1) + #define SPFI_INTERRUPT_SDTRIG BIT(0) + ++#define SPFI_INTERRUPT_DATA_BITS (SPFI_INTERRUPT_SDHF |\ ++ SPFI_INTERRUPT_SDFUL |\ ++ SPFI_INTERRUPT_GDEX32BIT |\ ++ SPFI_INTERRUPT_GDHF |\ ++ SPFI_INTERRUPT_GDFUL |\ ++ SPFI_INTERRUPT_ALLDONETRIG |\ ++ SPFI_INTERRUPT_GDEX8BIT) ++ + /* + * There are four parallel FIFOs of 16 bytes each. The word buffer + * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an +@@ -144,6 +152,23 @@ static inline void spfi_reset(struct img + spfi_writel(spfi, 0, SPFI_CONTROL); + } + ++static inline void spfi_finish(struct img_spfi *spfi) ++{ ++ if (!(spfi->complete)) ++ return; ++ ++ /* Clear data bits as all transfers(TX and RX) have finished */ ++ spfi_writel(spfi, SPFI_INTERRUPT_DATA_BITS, SPFI_INTERRUPT_CLEAR); ++ if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) & SPFI_INTERRUPT_DATA_BITS) { ++ dev_err(spfi->dev, "SPFI did not finish transfer cleanly.\n"); ++ spfi_reset(spfi); ++ } ++ /* Disable SPFI for it not to interfere with pending transactions */ ++ spfi_writel(spfi, ++ spfi_readl(spfi, SPFI_CONTROL) & ~SPFI_CONTROL_SPFI_EN, ++ SPFI_CONTROL); ++} ++ + static int spfi_wait_all_done(struct img_spfi *spfi) + { + unsigned long timeout = jiffies + msecs_to_jiffies(50); +@@ -152,19 +177,9 @@ static int spfi_wait_all_done(struct img + return 0; + + while (time_before(jiffies, timeout)) { +- u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); +- +- if (status & SPFI_INTERRUPT_ALLDONETRIG) { +- spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG, +- SPFI_INTERRUPT_CLEAR); +- /* +- * Disable SPFI for it not to interfere with +- * pending transactions +- */ +- spfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL) +- & ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL); ++ if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) & ++ SPFI_INTERRUPT_ALLDONETRIG) + return 0; +- } + cpu_relax(); + } + +@@ -296,6 +311,8 @@ static int img_spfi_start_pio(struct spi + } + + ret = spfi_wait_all_done(spfi); ++ spfi_finish(spfi); ++ + if (ret < 0) + return ret; + +@@ -311,8 +328,10 @@ static void img_spfi_dma_rx_cb(void *dat + + spin_lock_irqsave(&spfi->lock, flags); + spfi->rx_dma_busy = false; +- if (!spfi->tx_dma_busy) ++ if (!spfi->tx_dma_busy) { ++ spfi_finish(spfi); + spi_finalize_current_transfer(spfi->master); ++ } + spin_unlock_irqrestore(&spfi->lock, flags); + } + +@@ -325,8 +344,10 @@ static void img_spfi_dma_tx_cb(void *dat + + spin_lock_irqsave(&spfi->lock, flags); + spfi->tx_dma_busy = false; +- if (!spfi->rx_dma_busy) ++ if (!spfi->rx_dma_busy) { ++ spfi_finish(spfi); + spi_finalize_current_transfer(spfi->master); ++ } + spin_unlock_irqrestore(&spfi->lock, flags); + } + diff --git a/target/linux/pistachio/patches-5.4/107-clockevents-Retry-programming-min-delta-up-to-10-tim.patch b/target/linux/pistachio/patches-5.4/107-clockevents-Retry-programming-min-delta-up-to-10-tim.patch new file mode 100644 index 0000000000..857823b783 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/107-clockevents-Retry-programming-min-delta-up-to-10-tim.patch @@ -0,0 +1,66 @@ +From b46f8c74afdd30cd52bfdcc2231470a0bab04416 Mon Sep 17 00:00:00 2001 +From: James Hogan +Date: Fri, 22 Apr 2016 18:22:45 +0100 +Subject: clockevents: Retry programming min delta up to 10 times + +Under virtualisation it is possible to get unexpected latency during a +clockevent device's set_next_event() callback which can make it return +-ETIME even for a delta based on min_delta_ns. + +The clockevents_program_min_delta() implementation for +CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=n doesn't handle retries when this +happens, nor does clockevents_program_event() or its callers when force +is true (for example hrtimer_reprogram()). This can result in hangs +until the clock event device does a full period. + +It isn't appropriate to use MIN_ADJUST in this case as occasional +hypervisor induced high latency will cause min_delta_ns to quickly +increase to the maximum. +Instead, borrow the retry pattern from the MIN_ADJUST case, but without +making adjustments. We retry up to 10 times before giving up. + +(picked https://patchwork.kernel.org/patch/8909491/) + +Signed-off-by: James Hogan +--- + kernel/time/clockevents.c | 26 +++++++++++++++++++------- + 1 file changed, 19 insertions(+), 7 deletions(-) + +--- a/kernel/time/clockevents.c ++++ b/kernel/time/clockevents.c +@@ -281,16 +281,28 @@ static int clockevents_program_min_delta + { + unsigned long long clc; + int64_t delta; ++ int i; + +- delta = dev->min_delta_ns; +- dev->next_event = ktime_add_ns(ktime_get(), delta); ++ for (i = 0;;) { ++ delta = dev->min_delta_ns; ++ dev->next_event = ktime_add_ns(ktime_get(), delta); + +- if (clockevent_state_shutdown(dev)) +- return 0; ++ if (clockevent_state_shutdown(dev)) ++ return 0; + +- dev->retries++; +- clc = ((unsigned long long) delta * dev->mult) >> dev->shift; +- return dev->set_next_event((unsigned long) clc, dev); ++ dev->retries++; ++ clc = ((unsigned long long) delta * dev->mult) >> dev->shift; ++ if (dev->set_next_event((unsigned long) clc, dev) == 0) ++ return 0; ++ ++ if (++i > 9) { ++ /* ++ * We tried 10 times to program the device with the ++ * given min_delta_ns. Get out of here. ++ */ ++ return -ETIME; ++ } ++ } + } + + #endif /* CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST */ diff --git a/target/linux/pistachio/patches-5.4/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch b/target/linux/pistachio/patches-5.4/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch new file mode 100644 index 0000000000..5329ad62d0 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch @@ -0,0 +1,49 @@ +From 3642843a06025ec333d7e92580cf52cb8db2a652 Mon Sep 17 00:00:00 2001 +From: Govindraj Raja +Date: Fri, 8 Jan 2016 16:36:07 +0000 +Subject: clk: pistachio: Fix wrong SDHost card speed + +The SDHost currently clocks the card 4x slower than it +should do, because there is fixed divide by 4 in the +sdhost wrapper that is not present in the clock tree. +To model this add a fixed divide by 4 clock node in +the SDHost clock path. + +This will ensure the right clock frequency is selected when +the mmc driver tries to configure frequency on card insert. + +Signed-off-by: Govindraj Raja +--- + drivers/clk/pistachio/clk-pistachio.c | 3 ++- + include/dt-bindings/clock/pistachio-clk.h | 1 + + 2 files changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/clk/pistachio/clk-pistachio.c ++++ b/drivers/clk/pistachio/clk-pistachio.c +@@ -44,7 +44,7 @@ static struct pistachio_gate pistachio_g + GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div", + 0x104, 22), + GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23), +- GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24), ++ GATE(CLK_SD_HOST, "sd_host", "sd_host_div4", 0x104, 24), + GATE(CLK_BT, "bt", "bt_div", 0x104, 25), + GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26), + GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27), +@@ -54,6 +54,7 @@ static struct pistachio_gate pistachio_g + static struct pistachio_fixed_factor pistachio_ffs[] __initdata = { + FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4), + FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8), ++ FIXED_FACTOR(CLK_SDHOST_DIV4, "sd_host_div4", "sd_host_div", 4), + }; + + static struct pistachio_div pistachio_divs[] __initdata = { +--- a/include/dt-bindings/clock/pistachio-clk.h ++++ b/include/dt-bindings/clock/pistachio-clk.h +@@ -21,6 +21,7 @@ + /* Fixed-factor clocks */ + #define CLK_WIFI_DIV4 16 + #define CLK_WIFI_DIV8 17 ++#define CLK_SDHOST_DIV4 18 + + /* Gate clocks */ + #define CLK_MIPS 32 diff --git a/target/linux/pistachio/patches-5.4/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch b/target/linux/pistachio/patches-5.4/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch new file mode 100644 index 0000000000..22fc42b988 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch @@ -0,0 +1,47 @@ +From 981c1d416af45eff207227aec106381ac23aac99 Mon Sep 17 00:00:00 2001 +From: Ian Pozella +Date: Mon, 20 Feb 2017 10:00:52 +0000 +Subject: MIPS: DTS: img: marduk: switch mmc to 1 bit mode + +The mmc block in Pistachio allows 1 to 8 data bits to be used. +Marduk uses 4 bits allowing the upper 4 bits to be allocated +to the Mikrobus ports. However these bits are still connected +internally meaning the mmc block recieves signals on all data lines +and seems the internal HW CRC checks get corrupted by this erroneous +data. + +We cannot control what data is sent on these lines because they go +to external ports. 1 bit mode does not exhibit the issue hence the +safe default is to use this. If a user knows that in their use case +they will not use the upper bits then they can set to 4 bit mode in +order to improve performance. + +Also make sure that the upper 4 bits don't get allocated to the mmc +driver (the default is to assign all 8 pins) so they can be allocated +to other drivers. Allocating all 4 despite setting 1 bit mode as this +matches what is there in hardware. + +Signed-off-by: Ian Pozella +--- + arch/mips/boot/dts/img/pistachio_marduk.dts | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -120,7 +120,7 @@ + + &sdhost { + status = "okay"; +- bus-width = <4>; ++ bus-width = <1>; + disable-wp; + }; + +@@ -130,6 +130,7 @@ + + &pin_sdhost_data { + drive-strength = <2>; ++ pins = "mfio17", "mfio18", "mfio19", "mfio20"; + }; + + &pwm { diff --git a/target/linux/pistachio/patches-5.4/401-mtd-nor-support-mtd-name-from-device-tree.patch b/target/linux/pistachio/patches-5.4/401-mtd-nor-support-mtd-name-from-device-tree.patch new file mode 100644 index 0000000000..065a0b77bc --- /dev/null +++ b/target/linux/pistachio/patches-5.4/401-mtd-nor-support-mtd-name-from-device-tree.patch @@ -0,0 +1,34 @@ +From f32bc2aa01edcba2f2ed5db151cf183eac9ef919 Mon Sep 17 00:00:00 2001 +From: Abhimanyu Vishwakarma +Date: Sat, 25 Feb 2017 16:42:50 +0000 +Subject: mtd: nor: support mtd name from device tree + +Signed-off-by: Abhimanyu Vishwakarma +--- + drivers/mtd/spi-nor/spi-nor.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -2671,6 +2671,7 @@ int spi_nor_scan(struct spi_nor *nor, co + struct device *dev = nor->dev; + struct mtd_info *mtd = &nor->mtd; + struct device_node *np = spi_nor_get_flash_node(nor); ++ const char __maybe_unused *of_mtd_name = NULL; + int ret; + int i; + +@@ -2746,7 +2747,12 @@ int spi_nor_scan(struct spi_nor *nor, co + spi_nor_wait_till_ready(nor); + } + +- if (!mtd->name) ++#ifdef CONFIG_MTD_OF_PARTS ++ of_property_read_string(np, "linux,mtd-name", &of_mtd_name); ++#endif ++ if (of_mtd_name) ++ mtd->name = of_mtd_name; ++ else if (!mtd->name) + mtd->name = dev_name(dev); + mtd->priv = nor; + mtd->type = MTD_NORFLASH; diff --git a/target/linux/pistachio/patches-5.4/411-mtd-nand-Check-length-of-ID-before-reading-bits-per-.patch b/target/linux/pistachio/patches-5.4/411-mtd-nand-Check-length-of-ID-before-reading-bits-per-.patch new file mode 100644 index 0000000000..3311de645f --- /dev/null +++ b/target/linux/pistachio/patches-5.4/411-mtd-nand-Check-length-of-ID-before-reading-bits-per-.patch @@ -0,0 +1,33 @@ +From 42ebff638003be18fab503b37de4ad7853244e95 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Sat, 25 Feb 2017 15:58:22 +0000 +Subject: mtd: nand: Check length of ID before reading bits per cell + +The table-based NAND identification currently reads the number +of bits per cell from the 3rd byte of the extended ID. This is done +for the so-called 'full ID' devices; i.e. devices that have a known +length ID. + +However, if the ID length is shorter than three, there's no 3rd byte, +and so it's wrong to read the bits per cell from there. Fix this by +adding a check for the ID length. + +(picked from http://lists.infradead.org/pipermail/linux-mtd/2014-December/056764.html) + +Signed-off-by: Ezequiel Garcia +--- + drivers/mtd/nand/nand_base.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/nand/nand_base.c ++++ b/drivers/mtd/nand/nand_base.c +@@ -3803,7 +3803,8 @@ static bool find_full_id_nand(struct nan + mtd->erasesize = type->erasesize; + mtd->oobsize = type->oobsize; + +- chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); ++ if (type->id_len > 2) ++ chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->chipsize = (uint64_t)type->chipsize << 20; + chip->options |= type->options; + chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); diff --git a/target/linux/pistachio/patches-5.4/412-mtd-nand-Add-JEDEC-manufacturer-ID-for-Gigadevice.patch b/target/linux/pistachio/patches-5.4/412-mtd-nand-Add-JEDEC-manufacturer-ID-for-Gigadevice.patch new file mode 100644 index 0000000000..a967124c81 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/412-mtd-nand-Add-JEDEC-manufacturer-ID-for-Gigadevice.patch @@ -0,0 +1,35 @@ +From a4bc33b205fd9b1db862f1e45173dba57b0fa57f Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Sat, 25 Feb 2017 15:43:09 +0000 +Subject: mtd: nand: Add JEDEC manufacturer ID for Gigadevice + +This commit adds Gigadevice to the list of manufacturer ID and name strings. + +(picked from http://lists.infradead.org/pipermail/linux-mtd/2014-December/056765.html) + +Signed-off-by: Ezequiel Garcia +--- + drivers/mtd/nand/nand_ids.c | 1 + + include/linux/mtd/rawnand.h | 1 + + 2 files changed, 2 insertions(+) + +--- a/drivers/mtd/nand/nand_ids.c ++++ b/drivers/mtd/nand/nand_ids.c +@@ -184,6 +184,7 @@ static const struct nand_manufacturer na + {NAND_MFR_SANDISK, "SanDisk"}, + {NAND_MFR_INTEL, "Intel"}, + {NAND_MFR_ATO, "ATO"}, ++ {NAND_MFR_GIGADEVICE, "Gigadevice"}, + {NAND_MFR_WINBOND, "Winbond"}, + }; + +--- a/include/linux/mtd/rawnand.h ++++ b/include/linux/mtd/rawnand.h +@@ -1014,6 +1014,7 @@ static inline void *nand_get_manufacture + #define NAND_MFR_SANDISK 0x45 + #define NAND_MFR_INTEL 0x89 + #define NAND_MFR_ATO 0x9b ++#define NAND_MFR_GIGADEVICE 0xc8 + #define NAND_MFR_WINBOND 0xef + + diff --git a/target/linux/pistachio/patches-5.4/413-mtd-Introduce-SPI-NAND-framework.patch b/target/linux/pistachio/patches-5.4/413-mtd-Introduce-SPI-NAND-framework.patch new file mode 100644 index 0000000000..d1189eeb8c --- /dev/null +++ b/target/linux/pistachio/patches-5.4/413-mtd-Introduce-SPI-NAND-framework.patch @@ -0,0 +1,707 @@ +From 082a89a78e29b15008284df90441747cb742f149 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Tue, 2 Dec 2014 09:58:52 -0300 +Subject: mtd: Introduce SPI NAND framework + +Add a new framework, to support SPI NAND devices. The framework registers +a NAND chip and handles the generic SPI NAND protocol, calling device-specific +hooks for each SPI NAND command. + +The following is the stack design, from userspace to hardware. This commit +adds the "SPI NAND core" layer. + + Userspace + ------------------ + MTD + ------------------ + NAND core + ------------------ + SPI NAND core + ------------------ + SPI NAND device + ------------------ + SPI core + ------------------ + SPI master + ------------------ + Hardware + +(based on http://lists.infradead.org/pipermail/linux-mtd/2014-December/056763.html) + +Signed-off-by: Ionela Voinescu +Signed-off-by: Ezequiel Garcia +Signed-off-by: Ian Pozella +--- + drivers/mtd/Kconfig | 2 + + drivers/mtd/Makefile | 1 + + drivers/mtd/spi-nand/Kconfig | 7 + + drivers/mtd/spi-nand/Makefile | 1 + + drivers/mtd/spi-nand/spi-nand-base.c | 566 +++++++++++++++++++++++++++++++++++ + include/linux/mtd/spi-nand.h | 54 ++++ + 6 files changed, 631 insertions(+) + create mode 100644 drivers/mtd/spi-nand/Kconfig + create mode 100644 drivers/mtd/spi-nand/Makefile + create mode 100644 drivers/mtd/spi-nand/spi-nand-base.c + create mode 100644 include/linux/mtd/spi-nand.h + +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -373,6 +373,8 @@ source "drivers/mtd/onenand/Kconfig" + + source "drivers/mtd/lpddr/Kconfig" + ++source "drivers/mtd/spi-nand/Kconfig" ++ + source "drivers/mtd/spi-nor/Kconfig" + + source "drivers/mtd/ubi/Kconfig" +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -37,6 +37,7 @@ inftl-objs := inftlcore.o inftlmount.o + + obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/ + ++obj-$(CONFIG_MTD_SPI_NAND) += spi-nand/ + obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ + obj-$(CONFIG_MTD_UBI) += ubi/ + +--- /dev/null ++++ b/drivers/mtd/spi-nand/Kconfig +@@ -0,0 +1,7 @@ ++menuconfig MTD_SPI_NAND ++ tristate "SPI NAND device support" ++ depends on MTD ++ select MTD_NAND ++ help ++ This is the framework for the SPI NAND. ++ +--- /dev/null ++++ b/drivers/mtd/spi-nand/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_MTD_SPI_NAND) += spi-nand-base.o +--- /dev/null ++++ b/drivers/mtd/spi-nand/spi-nand-base.c +@@ -0,0 +1,566 @@ ++/* ++ * Copyright (C) 2014 Imagination Technologies Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * Notes: ++ * 1. Erase and program operations need to call write_enable() first, ++ * to clear the enable bit. This bit is cleared automatically after ++ * the erase or program operation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Registers common to all devices */ ++#define SPI_NAND_LOCK_REG 0xa0 ++#define SPI_NAND_PROT_UNLOCK_ALL 0x0 ++ ++#define SPI_NAND_FEATURE_REG 0xb0 ++#define SPI_NAND_ECC_EN BIT(4) ++#define SPI_NAND_QUAD_EN BIT(0) ++ ++#define SPI_NAND_STATUS_REG 0xc0 ++#define SPI_NAND_STATUS_REG_ECC_MASK 0x3 ++#define SPI_NAND_STATUS_REG_ECC_SHIFT 4 ++#define SPI_NAND_STATUS_REG_PROG_FAIL BIT(3) ++#define SPI_NAND_STATUS_REG_ERASE_FAIL BIT(2) ++#define SPI_NAND_STATUS_REG_WREN BIT(1) ++#define SPI_NAND_STATUS_REG_BUSY BIT(0) ++ ++#define SPI_NAND_CMD_BUF_LEN 8 ++ ++/* Rewind and fill the buffer with 0xff */ ++static void spi_nand_clear_buffer(struct spi_nand *snand) ++{ ++ snand->buf_start = 0; ++ memset(snand->data_buf, 0xff, snand->buf_size); ++} ++ ++static int spi_nand_enable_ecc(struct spi_nand *snand) ++{ ++ int ret; ++ ++ ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); ++ if (ret) ++ return ret; ++ ++ snand->buf[0] |= SPI_NAND_ECC_EN; ++ ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); ++ if (ret) ++ return ret; ++ snand->ecc = true; ++ ++ return 0; ++} ++ ++static int spi_nand_disable_ecc(struct spi_nand *snand) ++{ ++ int ret; ++ ++ ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); ++ if (ret) ++ return ret; ++ ++ snand->buf[0] &= ~SPI_NAND_ECC_EN; ++ ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); ++ if (ret) ++ return ret; ++ snand->ecc = false; ++ ++ return 0; ++} ++ ++static int spi_nand_enable_quad(struct spi_nand *snand) ++{ ++ int ret; ++ ++ ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); ++ if (ret) ++ return ret; ++ ++ snand->buf[0] |= SPI_NAND_QUAD_EN; ++ ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++/* ++ * Wait until the status register busy bit is cleared. ++ * Returns a negatie errno on error or time out, and a non-negative status ++ * value if the device is ready. ++ */ ++static int spi_nand_wait_till_ready(struct spi_nand *snand) ++{ ++ unsigned long deadline = jiffies + msecs_to_jiffies(100); ++ bool timeout = false; ++ int ret; ++ ++ /* ++ * Perhaps we should set a different timeout for each ++ * operation (reset, read, write, erase). ++ */ ++ while (!timeout) { ++ if (time_after_eq(jiffies, deadline)) ++ timeout = true; ++ ++ ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf); ++ if (ret < 0) { ++ dev_err(snand->dev, "error reading status register\n"); ++ return ret; ++ } else if (!(snand->buf[0] & SPI_NAND_STATUS_REG_BUSY)) { ++ return snand->buf[0]; ++ } ++ ++ cond_resched(); ++ } ++ ++ dev_err(snand->dev, "operation timed out\n"); ++ ++ return -ETIMEDOUT; ++} ++ ++static int spi_nand_reset(struct spi_nand *snand) ++{ ++ int ret; ++ ++ ret = snand->reset(snand); ++ if (ret < 0) { ++ dev_err(snand->dev, "reset command failed\n"); ++ return ret; ++ } ++ ++ /* ++ * The NAND core won't wait after a device reset, so we need ++ * to do that here. ++ */ ++ ret = spi_nand_wait_till_ready(snand); ++ if (ret < 0) ++ return ret; ++ return 0; ++} ++ ++static int spi_nand_status(struct spi_nand *snand) ++{ ++ int ret, status; ++ ++ ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf); ++ if (ret < 0) { ++ dev_err(snand->dev, "error reading status register\n"); ++ return ret; ++ } ++ status = snand->buf[0]; ++ ++ /* Convert this into standard NAND_STATUS values */ ++ if (status & SPI_NAND_STATUS_REG_BUSY) ++ snand->buf[0] = 0; ++ else ++ snand->buf[0] = NAND_STATUS_READY; ++ ++ if (status & SPI_NAND_STATUS_REG_PROG_FAIL || ++ status & SPI_NAND_STATUS_REG_ERASE_FAIL) ++ snand->buf[0] |= NAND_STATUS_FAIL; ++ ++ /* ++ * Since we unlock the entire device at initialization, unconditionally ++ * set the WP bit to indicate it's not protected. ++ */ ++ snand->buf[0] |= NAND_STATUS_WP; ++ return 0; ++} ++ ++static int spi_nand_erase(struct spi_nand *snand, int page_addr) ++{ ++ int ret; ++ ++ ret = snand->write_enable(snand); ++ if (ret < 0) { ++ dev_err(snand->dev, "write enable command failed\n"); ++ return ret; ++ } ++ ++ ret = snand->block_erase(snand, page_addr); ++ if (ret < 0) { ++ dev_err(snand->dev, "block erase command failed\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int spi_nand_write(struct spi_nand *snand) ++{ ++ int ret; ++ ++ /* Enable quad mode */ ++ ret = spi_nand_enable_quad(snand); ++ if (ret) { ++ dev_err(snand->dev, "error %d enabling quad mode\n", ret); ++ return ret; ++ } ++ /* Store the page to cache */ ++ ret = snand->store_cache(snand, 0, snand->buf_size, snand->data_buf); ++ if (ret < 0) { ++ dev_err(snand->dev, "error %d storing page 0x%x to cache\n", ++ ret, snand->page_addr); ++ return ret; ++ } ++ ++ ret = snand->write_enable(snand); ++ if (ret < 0) { ++ dev_err(snand->dev, "write enable command failed\n"); ++ return ret; ++ } ++ ++ /* Get page from the device cache into our internal buffer */ ++ ret = snand->write_page(snand, snand->page_addr); ++ if (ret < 0) { ++ dev_err(snand->dev, "error %d reading page 0x%x from cache\n", ++ ret, snand->page_addr); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int spi_nand_read_id(struct spi_nand *snand) ++{ ++ int ret; ++ ++ ret = snand->read_id(snand, snand->data_buf); ++ if (ret < 0) { ++ dev_err(snand->dev, "error %d reading ID\n", ret); ++ return ret; ++ } ++ return 0; ++} ++ ++static int spi_nand_read_page(struct spi_nand *snand, unsigned int page_addr, ++ unsigned int page_offset, size_t length) ++{ ++ unsigned int corrected = 0, ecc_error = 0; ++ int ret; ++ ++ /* Load a page into the cache register */ ++ ret = snand->load_page(snand, page_addr); ++ if (ret < 0) { ++ dev_err(snand->dev, "error %d loading page 0x%x to cache\n", ++ ret, page_addr); ++ return ret; ++ } ++ ++ ret = spi_nand_wait_till_ready(snand); ++ if (ret < 0) ++ return ret; ++ ++ if (snand->ecc) { ++ snand->get_ecc_status(ret, &corrected, &ecc_error); ++ snand->bitflips = corrected; ++ ++ /* ++ * If there's an ECC error, print a message and notify MTD ++ * about it. Then complete the read, to load actual data on ++ * the buffer (instead of the status result). ++ */ ++ if (ecc_error) { ++ dev_err(snand->dev, ++ "internal ECC error reading page 0x%x\n", ++ page_addr); ++ snand->nand_chip.mtd.ecc_stats.failed++; ++ } else { ++ snand->nand_chip.mtd.ecc_stats.corrected += corrected; ++ } ++ } ++ ++ /* Enable quad mode */ ++ ret = spi_nand_enable_quad(snand); ++ if (ret) { ++ dev_err(snand->dev, "error %d enabling quad mode\n", ret); ++ return ret; ++ } ++ /* Get page from the device cache into our internal buffer */ ++ ret = snand->read_cache(snand, page_offset, length, snand->data_buf); ++ if (ret < 0) { ++ dev_err(snand->dev, "error %d reading page 0x%x from cache\n", ++ ret, page_addr); ++ return ret; ++ } ++ return 0; ++} ++ ++static u8 spi_nand_read_byte(struct mtd_info *mtd) ++{ ++ struct nand_chip *chip = mtd_to_nand(mtd); ++ struct spi_nand *snand = nand_get_controller_data(chip); ++ char val = 0xff; ++ ++ if (snand->buf_start < snand->buf_size) ++ val = snand->data_buf[snand->buf_start++]; ++ return val; ++} ++ ++static void spi_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) ++{ ++ struct nand_chip *chip = mtd_to_nand(mtd); ++ struct spi_nand *snand = nand_get_controller_data(chip); ++ size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start); ++ ++ memcpy(snand->data_buf + snand->buf_start, buf, n); ++ snand->buf_start += n; ++} ++ ++static void spi_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) ++{ ++ struct nand_chip *chip = mtd_to_nand(mtd); ++ struct spi_nand *snand = nand_get_controller_data(chip); ++ size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start); ++ ++ memcpy(buf, snand->data_buf + snand->buf_start, n); ++ snand->buf_start += n; ++} ++ ++static int spi_nand_write_page_hwecc(struct mtd_info *mtd, ++ struct nand_chip *chip, const uint8_t *buf, int oob_required, ++ int page) ++{ ++ chip->write_buf(mtd, buf, mtd->writesize); ++ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); ++ ++ return 0; ++} ++ ++static int spi_nand_read_page_hwecc(struct mtd_info *mtd, ++ struct nand_chip *chip, uint8_t *buf, int oob_required, ++ int page) ++{ ++ struct spi_nand *snand = nand_get_controller_data(chip); ++ ++ chip->read_buf(mtd, buf, mtd->writesize); ++ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); ++ ++ return snand->bitflips; ++} ++ ++static int spi_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) ++{ ++ struct spi_nand *snand = nand_get_controller_data(chip); ++ int ret; ++ ++ ret = spi_nand_wait_till_ready(snand); ++ ++ if (ret < 0) { ++ return NAND_STATUS_FAIL; ++ } else if (ret & SPI_NAND_STATUS_REG_PROG_FAIL) { ++ dev_err(snand->dev, "page program failed\n"); ++ return NAND_STATUS_FAIL; ++ } else if (ret & SPI_NAND_STATUS_REG_ERASE_FAIL) { ++ dev_err(snand->dev, "block erase failed\n"); ++ return NAND_STATUS_FAIL; ++ } ++ ++ return NAND_STATUS_READY; ++} ++ ++static void spi_nand_cmdfunc(struct mtd_info *mtd, unsigned int command, ++ int column, int page_addr) ++{ ++ struct nand_chip *chip = mtd_to_nand(mtd); ++ struct spi_nand *snand = nand_get_controller_data(chip); ++ ++ /* ++ * In case there's any unsupported command, let's make sure ++ * we don't keep garbage around in the buffer. ++ */ ++ if (command != NAND_CMD_PAGEPROG) { ++ spi_nand_clear_buffer(snand); ++ snand->page_addr = 0; ++ } ++ ++ switch (command) { ++ case NAND_CMD_READ0: ++ spi_nand_read_page(snand, page_addr, 0, mtd->writesize); ++ break; ++ case NAND_CMD_READOOB: ++ spi_nand_disable_ecc(snand); ++ spi_nand_read_page(snand, page_addr, mtd->writesize, ++ mtd->oobsize); ++ spi_nand_enable_ecc(snand); ++ break; ++ case NAND_CMD_READID: ++ spi_nand_read_id(snand); ++ break; ++ case NAND_CMD_ERASE1: ++ spi_nand_erase(snand, page_addr); ++ break; ++ case NAND_CMD_ERASE2: ++ /* There's nothing to do here, as the erase is one-step */ ++ break; ++ case NAND_CMD_SEQIN: ++ snand->buf_start = column; ++ snand->page_addr = page_addr; ++ break; ++ case NAND_CMD_PAGEPROG: ++ spi_nand_write(snand); ++ break; ++ case NAND_CMD_STATUS: ++ spi_nand_status(snand); ++ break; ++ case NAND_CMD_RESET: ++ spi_nand_reset(snand); ++ break; ++ default: ++ dev_err(&mtd->dev, "unknown command 0x%x\n", command); ++ } ++} ++ ++static void spi_nand_select_chip(struct mtd_info *mtd, int chip) ++{ ++ /* We need this to override the default */ ++} ++ ++int spi_nand_check(struct spi_nand *snand) ++{ ++ if (!snand->dev) ++ return -ENODEV; ++ if (!snand->read_cache) ++ return -ENODEV; ++ if (!snand->load_page) ++ return -ENODEV; ++ if (!snand->store_cache) ++ return -ENODEV; ++ if (!snand->write_page) ++ return -ENODEV; ++ if (!snand->write_reg) ++ return -ENODEV; ++ if (!snand->read_reg) ++ return -ENODEV; ++ if (!snand->block_erase) ++ return -ENODEV; ++ if (!snand->reset) ++ return -ENODEV; ++ if (!snand->write_enable) ++ return -ENODEV; ++ if (!snand->write_disable) ++ return -ENODEV; ++ if (!snand->get_ecc_status) ++ return -ENODEV; ++ return 0; ++} ++ ++int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids) ++{ ++ struct nand_chip *chip = &snand->nand_chip; ++ struct mtd_info *mtd = nand_to_mtd(chip); ++ struct device_node *np = snand->dev->of_node; ++ const char __maybe_unused *of_mtd_name = NULL; ++ int ret; ++ ++ /* Let's check all the hooks are in-place so we don't panic later */ ++ ret = spi_nand_check(snand); ++ if (ret) ++ return ret; ++ ++ nand_set_controller_data(chip, snand); ++ nand_set_flash_node(chip, np); ++ chip->read_buf = spi_nand_read_buf; ++ chip->write_buf = spi_nand_write_buf; ++ chip->read_byte = spi_nand_read_byte; ++ chip->cmdfunc = spi_nand_cmdfunc; ++ chip->waitfunc = spi_nand_waitfunc; ++ chip->select_chip = spi_nand_select_chip; ++ chip->options |= NAND_NO_SUBPAGE_WRITE; ++ chip->bits_per_cell = 1; ++ ++ mtd_set_ooblayout(mtd, snand->ooblayout); ++ chip->ecc.read_page = spi_nand_read_page_hwecc; ++ chip->ecc.write_page = spi_nand_write_page_hwecc; ++ chip->ecc.mode = NAND_ECC_HW; ++ ++ if (of_property_read_bool(np, "nand-on-flash-bbt")) ++ chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; ++ ++#ifdef CONFIG_MTD_OF_PARTS ++ of_property_read_string(np, "linux,mtd-name", &of_mtd_name); ++#endif ++ if (of_mtd_name) ++ mtd->name = of_mtd_name; ++ else ++ mtd->name = snand->name; ++ mtd->owner = THIS_MODULE; ++ ++ /* Allocate buffer to be used to read/write the internal registers */ ++ snand->buf = kmalloc(SPI_NAND_CMD_BUF_LEN, GFP_KERNEL); ++ if (!snand->buf) ++ return -ENOMEM; ++ ++ /* This is enabled at device power up but we'd better make sure */ ++ ret = spi_nand_enable_ecc(snand); ++ if (ret) ++ return ret; ++ ++ /* Preallocate buffer for flash identification (NAND_CMD_READID) */ ++ snand->buf_size = SPI_NAND_CMD_BUF_LEN; ++ snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL); ++ ++ ret = nand_scan_ident(mtd, 1, flash_ids); ++ if (ret) ++ return ret; ++ ++ /* ++ * SPI NAND has on-die ECC, which means we can correct as much as ++ * we are required to. This must be done after identification of ++ * the device. ++ */ ++ chip->ecc.strength = chip->ecc_strength_ds; ++ chip->ecc.size = chip->ecc_step_ds; ++ ++ /* ++ * Unlock all the device before calling nand_scan_tail. This is needed ++ * in case the in-flash bad block table needs to be created. ++ * We could override __nand_unlock(), but since it's not currently used ++ * by the NAND core we call this explicitly. ++ */ ++ snand->buf[0] = SPI_NAND_PROT_UNLOCK_ALL; ++ ret = snand->write_reg(snand, SPI_NAND_LOCK_REG, snand->buf); ++ if (ret) ++ return ret; ++ ++ /* Free the buffer and allocate a good one, to fit a page plus OOB */ ++ kfree(snand->data_buf); ++ ++ snand->buf_size = mtd->writesize + mtd->oobsize; ++ snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL); ++ if (!snand->data_buf) ++ return -ENOMEM; ++ ++ ret = nand_scan_tail(mtd); ++ if (ret) ++ return ret; ++ ++ return mtd_device_register(mtd, NULL, 0); ++} ++EXPORT_SYMBOL_GPL(spi_nand_register); ++ ++void spi_nand_unregister(struct spi_nand *snand) ++{ ++ kfree(snand->buf); ++ kfree(snand->data_buf); ++} ++EXPORT_SYMBOL_GPL(spi_nand_unregister); ++ ++MODULE_AUTHOR("Ezequiel Garcia "); ++MODULE_DESCRIPTION("Framework for SPI NAND"); ++MODULE_LICENSE("GPL v2"); +--- /dev/null ++++ b/include/linux/mtd/spi-nand.h +@@ -0,0 +1,54 @@ ++/* ++ * Copyright (C) 2014 Imagination Technologies Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ */ ++ ++#ifndef __LINUX_MTD_SPI_NAND_H ++#define __LINUX_MTD_SPI_NAND_H ++ ++#include ++#include ++ ++struct spi_nand { ++ struct nand_chip nand_chip; ++ struct device *dev; ++ const char *name; ++ ++ u8 *buf, *data_buf; ++ size_t buf_size; ++ off_t buf_start; ++ unsigned int page_addr; ++ unsigned int bitflips; ++ bool ecc; ++ struct mtd_ooblayout_ops *ooblayout; ++ ++ int (*reset)(struct spi_nand *snand); ++ int (*read_id)(struct spi_nand *snand, u8 *buf); ++ ++ int (*write_disable)(struct spi_nand *snand); ++ int (*write_enable)(struct spi_nand *snand); ++ ++ int (*read_reg)(struct spi_nand *snand, u8 opcode, u8 *buf); ++ int (*write_reg)(struct spi_nand *snand, u8 opcode, u8 *buf); ++ void (*get_ecc_status)(unsigned int status, ++ unsigned int *corrected, ++ unsigned int *ecc_errors); ++ ++ int (*store_cache)(struct spi_nand *snand, unsigned int page_offset, ++ size_t length, u8 *write_buf); ++ int (*write_page)(struct spi_nand *snand, unsigned int page_addr); ++ int (*load_page)(struct spi_nand *snand, unsigned int page_addr); ++ int (*read_cache)(struct spi_nand *snand, unsigned int page_offset, ++ size_t length, u8 *read_buf); ++ int (*block_erase)(struct spi_nand *snand, unsigned int page_addr); ++ ++ void *priv; ++}; ++ ++int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids); ++void spi_nand_unregister(struct spi_nand *snand); ++ ++#endif diff --git a/target/linux/pistachio/patches-5.4/414-mtd-spi-nand-Support-Gigadevice-GD5F.patch b/target/linux/pistachio/patches-5.4/414-mtd-spi-nand-Support-Gigadevice-GD5F.patch new file mode 100644 index 0000000000..1f1461061c --- /dev/null +++ b/target/linux/pistachio/patches-5.4/414-mtd-spi-nand-Support-Gigadevice-GD5F.patch @@ -0,0 +1,524 @@ +From 7723e59d483a883578115a73eb87eb7fff0ff724 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Tue, 28 Feb 2017 10:37:24 +0000 +Subject: mtd: spi-nand: Support Gigadevice GD5F + +This commit uses the recently introduced SPI NAND framework to support +the Gigadevice GD5F serial NAND device. + +The current support includes: + + * Page read and page program operations (using on-die ECC) + * Page out-of-band read + * Erase + * Reset + * Device status retrieval + * Device ID retrieval + +(based on http://lists.infradead.org/pipermail/linux-mtd/2014-December/056769.html) + +Signed-off-by: Ezequiel Garcia +Signed-off-by: Ian Pozella +--- + drivers/mtd/spi-nand/Kconfig | 10 + + drivers/mtd/spi-nand/Makefile | 1 + + drivers/mtd/spi-nand/spi-nand-device.c | 472 +++++++++++++++++++++++++++++++++ + 3 files changed, 483 insertions(+) + create mode 100644 drivers/mtd/spi-nand/spi-nand-device.c + +--- a/drivers/mtd/spi-nand/Kconfig ++++ b/drivers/mtd/spi-nand/Kconfig +@@ -5,3 +5,13 @@ menuconfig MTD_SPI_NAND + help + This is the framework for the SPI NAND. + ++if MTD_SPI_NAND ++ ++config MTD_SPI_NAND_DEVICES ++ tristate "Support for SPI NAND devices" ++ default y ++ depends on MTD_SPI_NAND ++ help ++ Select this option if you require support for SPI NAND devices. ++ ++endif # MTD_SPI_NAND +--- a/drivers/mtd/spi-nand/Makefile ++++ b/drivers/mtd/spi-nand/Makefile +@@ -1 +1,2 @@ + obj-$(CONFIG_MTD_SPI_NAND) += spi-nand-base.o ++obj-$(CONFIG_MTD_SPI_NAND_DEVICES) += spi-nand-device.o +--- /dev/null ++++ b/drivers/mtd/spi-nand/spi-nand-device.c +@@ -0,0 +1,472 @@ ++/* ++ * Copyright (C) 2014 Imagination Technologies Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * Notes: ++ * 1. We avoid using a stack-allocated buffer for SPI messages. Using ++ * a kmalloced buffer is probably better, given we shouldn't assume ++ * any particular usage by SPI core. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* SPI NAND commands */ ++#define SPI_NAND_WRITE_ENABLE 0x06 ++#define SPI_NAND_WRITE_DISABLE 0x04 ++#define SPI_NAND_GET_FEATURE 0x0f ++#define SPI_NAND_SET_FEATURE 0x1f ++#define SPI_NAND_PAGE_READ 0x13 ++#define SPI_NAND_READ_CACHE 0x03 ++#define SPI_NAND_FAST_READ_CACHE 0x0b ++#define SPI_NAND_READ_CACHE_X2 0x3b ++#define SPI_NAND_READ_CACHE_X4 0x6b ++#define SPI_NAND_READ_CACHE_DUAL_IO 0xbb ++#define SPI_NAND_READ_CACHE_QUAD_IO 0xeb ++#define SPI_NAND_READ_ID 0x9f ++#define SPI_NAND_PROGRAM_LOAD 0x02 ++#define SPI_NAND_PROGRAM_LOAD4 0x32 ++#define SPI_NAND_PROGRAM_EXEC 0x10 ++#define SPI_NAND_PROGRAM_LOAD_RANDOM 0x84 ++#define SPI_NAND_PROGRAM_LOAD_RANDOM4 0xc4 ++#define SPI_NAND_BLOCK_ERASE 0xd8 ++#define SPI_NAND_RESET 0xff ++ ++#define SPI_NAND_GD5F_READID_LEN 2 ++ ++#define SPI_NAND_GD5F_ECC_MASK (BIT(0) | BIT(1) | BIT(2)) ++#define SPI_NAND_GD5F_ECC_UNCORR (BIT(0) | BIT(1) | BIT(2)) ++#define SPI_NAND_GD5F_ECC_SHIFT 4 ++ ++static int spi_nand_gd5f_ooblayout_256_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobregion) ++{ ++ if (section) ++ return -ERANGE; ++ ++ oobregion->offset = 128; ++ oobregion->length = 128; ++ ++ return 0; ++} ++ ++static int spi_nand_gd5f_ooblayout_256_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobregion) ++{ ++ if (section) ++ return -ERANGE; ++ ++ oobregion->offset = 1; ++ oobregion->length = 127; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops spi_nand_gd5f_oob_256_ops = { ++ .ecc = spi_nand_gd5f_ooblayout_256_ecc, ++ .free = spi_nand_gd5f_ooblayout_256_free, ++}; ++ ++static struct nand_flash_dev spi_nand_flash_ids[] = { ++ { ++ .name = "SPI NAND 512MiB 3,3V", ++ .id = { NAND_MFR_GIGADEVICE, 0xb4 }, ++ .chipsize = 512, ++ .pagesize = SZ_4K, ++ .erasesize = SZ_256K, ++ .id_len = 2, ++ .oobsize = 256, ++ .ecc.strength_ds = 8, ++ .ecc.step_ds = 512, ++ }, ++ { ++ .name = "SPI NAND 512MiB 1,8V", ++ .id = { NAND_MFR_GIGADEVICE, 0xa4 }, ++ .chipsize = 512, ++ .pagesize = SZ_4K, ++ .erasesize = SZ_256K, ++ .id_len = 2, ++ .oobsize = 256, ++ .ecc.strength_ds = 8, ++ .ecc.step_ds = 512, ++ }, ++}; ++ ++enum spi_nand_device_variant { ++ SPI_NAND_GENERIC, ++ SPI_NAND_GD5F, ++}; ++ ++struct spi_nand_device_cmd { ++ ++ /* ++ * Command and address. I/O errors have been observed if a ++ * separate spi_transfer is used for command and address, ++ * so keep them together. ++ */ ++ u32 n_cmd; ++ u8 cmd[5]; ++ ++ /* Tx data */ ++ u32 n_tx; ++ u8 *tx_buf; ++ ++ /* Rx data */ ++ u32 n_rx; ++ u8 *rx_buf; ++ u8 rx_nbits; ++ u8 tx_nbits; ++}; ++ ++struct spi_nand_device { ++ struct spi_nand spi_nand; ++ struct spi_device *spi; ++ ++ struct spi_nand_device_cmd cmd; ++}; ++ ++static int spi_nand_send_command(struct spi_device *spi, ++ struct spi_nand_device_cmd *cmd) ++{ ++ struct spi_message message; ++ struct spi_transfer x[2]; ++ ++ if (!cmd->n_cmd) { ++ dev_err(&spi->dev, "cannot send an empty command\n"); ++ return -EINVAL; ++ } ++ ++ if (cmd->n_tx && cmd->n_rx) { ++ dev_err(&spi->dev, "cannot send and receive data at the same time\n"); ++ return -EINVAL; ++ } ++ ++ spi_message_init(&message); ++ memset(x, 0, sizeof(x)); ++ ++ /* Command and address */ ++ x[0].len = cmd->n_cmd; ++ x[0].tx_buf = cmd->cmd; ++ x[0].tx_nbits = cmd->tx_nbits; ++ spi_message_add_tail(&x[0], &message); ++ ++ /* Data to be transmitted */ ++ if (cmd->n_tx) { ++ x[1].len = cmd->n_tx; ++ x[1].tx_buf = cmd->tx_buf; ++ x[1].tx_nbits = cmd->tx_nbits; ++ spi_message_add_tail(&x[1], &message); ++ } ++ ++ /* Data to be received */ ++ if (cmd->n_rx) { ++ x[1].len = cmd->n_rx; ++ x[1].rx_buf = cmd->rx_buf; ++ x[1].rx_nbits = cmd->rx_nbits; ++ spi_message_add_tail(&x[1], &message); ++ } ++ ++ return spi_sync(spi, &message); ++} ++ ++static int spi_nand_device_reset(struct spi_nand *snand) ++{ ++ struct spi_nand_device *snand_dev = snand->priv; ++ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; ++ ++ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); ++ cmd->n_cmd = 1; ++ cmd->cmd[0] = SPI_NAND_RESET; ++ ++ dev_dbg(snand->dev, "%s\n", __func__); ++ ++ return spi_nand_send_command(snand_dev->spi, cmd); ++} ++ ++static int spi_nand_device_read_reg(struct spi_nand *snand, u8 opcode, u8 *buf) ++{ ++ struct spi_nand_device *snand_dev = snand->priv; ++ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; ++ ++ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); ++ cmd->n_cmd = 2; ++ cmd->cmd[0] = SPI_NAND_GET_FEATURE; ++ cmd->cmd[1] = opcode; ++ cmd->n_rx = 1; ++ cmd->rx_buf = buf; ++ ++ dev_dbg(snand->dev, "%s: reg 0%x\n", __func__, opcode); ++ ++ return spi_nand_send_command(snand_dev->spi, cmd); ++} ++ ++static int spi_nand_device_write_reg(struct spi_nand *snand, u8 opcode, u8 *buf) ++{ ++ struct spi_nand_device *snand_dev = snand->priv; ++ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; ++ ++ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); ++ cmd->n_cmd = 2; ++ cmd->cmd[0] = SPI_NAND_SET_FEATURE; ++ cmd->cmd[1] = opcode; ++ cmd->n_tx = 1; ++ cmd->tx_buf = buf; ++ ++ dev_dbg(snand->dev, "%s: reg 0%x\n", __func__, opcode); ++ ++ return spi_nand_send_command(snand_dev->spi, cmd); ++} ++ ++static int spi_nand_device_write_enable(struct spi_nand *snand) ++{ ++ struct spi_nand_device *snand_dev = snand->priv; ++ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; ++ ++ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); ++ cmd->n_cmd = 1; ++ cmd->cmd[0] = SPI_NAND_WRITE_ENABLE; ++ ++ dev_dbg(snand->dev, "%s\n", __func__); ++ ++ return spi_nand_send_command(snand_dev->spi, cmd); ++} ++ ++static int spi_nand_device_write_disable(struct spi_nand *snand) ++{ ++ struct spi_nand_device *snand_dev = snand->priv; ++ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; ++ ++ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); ++ cmd->n_cmd = 1; ++ cmd->cmd[0] = SPI_NAND_WRITE_DISABLE; ++ ++ dev_dbg(snand->dev, "%s\n", __func__); ++ ++ return spi_nand_send_command(snand_dev->spi, cmd); ++} ++ ++static int spi_nand_device_write_page(struct spi_nand *snand, ++ unsigned int page_addr) ++{ ++ struct spi_nand_device *snand_dev = snand->priv; ++ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; ++ ++ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); ++ cmd->n_cmd = 4; ++ cmd->cmd[0] = SPI_NAND_PROGRAM_EXEC; ++ cmd->cmd[1] = (u8)((page_addr & 0xff0000) >> 16); ++ cmd->cmd[2] = (u8)((page_addr & 0xff00) >> 8); ++ cmd->cmd[3] = (u8)(page_addr & 0xff); ++ ++ dev_dbg(snand->dev, "%s: page 0x%x\n", __func__, page_addr); ++ ++ return spi_nand_send_command(snand_dev->spi, cmd); ++} ++ ++static int spi_nand_device_store_cache(struct spi_nand *snand, ++ unsigned int page_offset, size_t length, ++ u8 *write_buf) ++{ ++ struct spi_nand_device *snand_dev = snand->priv; ++ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; ++ struct spi_device *spi = snand_dev->spi; ++ ++ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); ++ cmd->n_cmd = 3; ++ cmd->cmd[0] = spi->mode & SPI_TX_QUAD ? SPI_NAND_PROGRAM_LOAD4 : ++ SPI_NAND_PROGRAM_LOAD; ++ cmd->cmd[1] = (u8)((page_offset & 0xff00) >> 8); ++ cmd->cmd[2] = (u8)(page_offset & 0xff); ++ cmd->n_tx = length; ++ cmd->tx_buf = write_buf; ++ cmd->tx_nbits = spi->mode & SPI_TX_QUAD ? 4 : 1; ++ ++ dev_dbg(snand->dev, "%s: offset 0x%x\n", __func__, page_offset); ++ ++ return spi_nand_send_command(snand_dev->spi, cmd); ++} ++ ++static int spi_nand_device_load_page(struct spi_nand *snand, ++ unsigned int page_addr) ++{ ++ struct spi_nand_device *snand_dev = snand->priv; ++ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; ++ ++ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); ++ cmd->n_cmd = 4; ++ cmd->cmd[0] = SPI_NAND_PAGE_READ; ++ cmd->cmd[1] = (u8)((page_addr & 0xff0000) >> 16); ++ cmd->cmd[2] = (u8)((page_addr & 0xff00) >> 8); ++ cmd->cmd[3] = (u8)(page_addr & 0xff); ++ ++ dev_dbg(snand->dev, "%s: page 0x%x\n", __func__, page_addr); ++ ++ return spi_nand_send_command(snand_dev->spi, cmd); ++} ++ ++static int spi_nand_device_read_cache(struct spi_nand *snand, ++ unsigned int page_offset, size_t length, ++ u8 *read_buf) ++{ ++ struct spi_nand_device *snand_dev = snand->priv; ++ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; ++ struct spi_device *spi = snand_dev->spi; ++ ++ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); ++ if ((spi->mode & SPI_RX_DUAL) || (spi->mode & SPI_RX_QUAD)) ++ cmd->n_cmd = 5; ++ else ++ cmd->n_cmd = 4; ++ cmd->cmd[0] = (spi->mode & SPI_RX_QUAD) ? SPI_NAND_READ_CACHE_X4 : ++ ((spi->mode & SPI_RX_DUAL) ? SPI_NAND_READ_CACHE_X2 : ++ SPI_NAND_READ_CACHE); ++ cmd->cmd[1] = 0; /* dummy byte */ ++ cmd->cmd[2] = (u8)((page_offset & 0xff00) >> 8); ++ cmd->cmd[3] = (u8)(page_offset & 0xff); ++ cmd->cmd[4] = 0; /* dummy byte */ ++ cmd->n_rx = length; ++ cmd->rx_buf = read_buf; ++ cmd->rx_nbits = (spi->mode & SPI_RX_QUAD) ? 4 : ++ ((spi->mode & SPI_RX_DUAL) ? 2 : 1); ++ ++ dev_dbg(snand->dev, "%s: offset 0x%x\n", __func__, page_offset); ++ ++ return spi_nand_send_command(snand_dev->spi, cmd); ++} ++ ++static int spi_nand_device_block_erase(struct spi_nand *snand, ++ unsigned int page_addr) ++{ ++ struct spi_nand_device *snand_dev = snand->priv; ++ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; ++ ++ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); ++ cmd->n_cmd = 4; ++ cmd->cmd[0] = SPI_NAND_BLOCK_ERASE; ++ cmd->cmd[1] = (u8)((page_addr & 0xff0000) >> 16); ++ cmd->cmd[2] = (u8)((page_addr & 0xff00) >> 8); ++ cmd->cmd[3] = (u8)(page_addr & 0xff); ++ ++ dev_dbg(snand->dev, "%s: block 0x%x\n", __func__, page_addr); ++ ++ return spi_nand_send_command(snand_dev->spi, cmd); ++} ++ ++static int spi_nand_gd5f_read_id(struct spi_nand *snand, u8 *buf) ++{ ++ struct spi_nand_device *snand_dev = snand->priv; ++ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; ++ ++ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); ++ cmd->n_cmd = 1; ++ cmd->cmd[0] = SPI_NAND_READ_ID; ++ cmd->n_rx = SPI_NAND_GD5F_READID_LEN; ++ cmd->rx_buf = buf; ++ ++ dev_dbg(snand->dev, "%s\n", __func__); ++ ++ return spi_nand_send_command(snand_dev->spi, cmd); ++} ++ ++static void spi_nand_gd5f_ecc_status(unsigned int status, ++ unsigned int *corrected, ++ unsigned int *ecc_error) ++{ ++ unsigned int ecc_status = (status >> SPI_NAND_GD5F_ECC_SHIFT) & ++ SPI_NAND_GD5F_ECC_MASK; ++ ++ *ecc_error = (ecc_status == SPI_NAND_GD5F_ECC_UNCORR) ? 1 : 0; ++ if (*ecc_error == 0) ++ *corrected = (ecc_status > 1) ? (2 + ecc_status) : 0; ++} ++ ++static int spi_nand_device_probe(struct spi_device *spi) ++{ ++ enum spi_nand_device_variant variant; ++ struct spi_nand_device *priv; ++ struct spi_nand *snand; ++ int ret; ++ ++ priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ snand = &priv->spi_nand; ++ ++ snand->read_cache = spi_nand_device_read_cache; ++ snand->load_page = spi_nand_device_load_page; ++ snand->store_cache = spi_nand_device_store_cache; ++ snand->write_page = spi_nand_device_write_page; ++ snand->write_reg = spi_nand_device_write_reg; ++ snand->read_reg = spi_nand_device_read_reg; ++ snand->block_erase = spi_nand_device_block_erase; ++ snand->reset = spi_nand_device_reset; ++ snand->write_enable = spi_nand_device_write_enable; ++ snand->write_disable = spi_nand_device_write_disable; ++ snand->dev = &spi->dev; ++ snand->priv = priv; ++ ++ /* This'll mean we won't need to specify any specific compatible string ++ * for a given device, and instead just support spi-nand. ++ */ ++ variant = spi_get_device_id(spi)->driver_data; ++ switch (variant) { ++ case SPI_NAND_GD5F: ++ snand->read_id = spi_nand_gd5f_read_id; ++ snand->get_ecc_status = spi_nand_gd5f_ecc_status; ++ snand->ooblayout = &spi_nand_gd5f_oob_256_ops; ++ break; ++ default: ++ dev_err(snand->dev, "unknown device\n"); ++ return -ENODEV; ++ } ++ ++ spi_set_drvdata(spi, snand); ++ priv->spi = spi; ++ ++ ret = spi_nand_register(snand, spi_nand_flash_ids); ++ if (ret) ++ return ret; ++ return 0; ++} ++ ++static int spi_nand_device_remove(struct spi_device *spi) ++{ ++ struct spi_nand *snand = spi_get_drvdata(spi); ++ ++ spi_nand_unregister(snand); ++ ++ return 0; ++} ++ ++const struct spi_device_id spi_nand_id_table[] = { ++ { "spi-nand", SPI_NAND_GENERIC }, ++ { "gd5f", SPI_NAND_GD5F }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(spi, spi_nand_id_table); ++ ++static struct spi_driver spi_nand_device_driver = { ++ .driver = { ++ .name = "spi_nand_device", ++ .owner = THIS_MODULE, ++ }, ++ .id_table = spi_nand_id_table, ++ .probe = spi_nand_device_probe, ++ .remove = spi_nand_device_remove, ++}; ++module_spi_driver(spi_nand_device_driver); ++ ++MODULE_AUTHOR("Ezequiel Garcia "); ++MODULE_DESCRIPTION("SPI NAND device support"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-add-nor-partition-name.patch b/target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-add-nor-partition-name.patch new file mode 100644 index 0000000000..6af11eaa36 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-add-nor-partition-name.patch @@ -0,0 +1,20 @@ +From b5f49b448cd3c7ab930f1a53c88f739a86071df8 Mon Sep 17 00:00:00 2001 +From: Ian Pozella +Date: Mon, 20 Feb 2017 10:38:07 +0000 +Subject: MIPS: DTS: img: marduk: add nor partition name + +Signed-off-by: Ian Pozella +--- + arch/mips/boot/dts/img/pistachio_marduk.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -90,6 +90,7 @@ + compatible = "spansion,s25fl016k", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; ++ linux,mtd-name = "spi-nor"; + }; + }; + diff --git a/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-add-nand-device-support.patch b/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-add-nand-device-support.patch new file mode 100644 index 0000000000..bd03f08126 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-add-nand-device-support.patch @@ -0,0 +1,30 @@ +From c13cfb3a49cf1578bb85f19a7066f262503a39ba Mon Sep 17 00:00:00 2001 +From: Abhimanyu Vishwakarma +Date: Thu, 24 Nov 2016 19:26:46 +0530 +Subject: MIPS: DTS: img: marduk: add nand device support + +Signed-off-by: Abhimanyu Vishwakarma +--- + arch/mips/boot/dts/img/pistachio_marduk.dts | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -92,6 +92,17 @@ + spi-max-frequency = <50000000>; + linux,mtd-name = "spi-nor"; + }; ++ flash@1 { ++ compatible = "gigadevice,gd5f"; ++ reg = <1>; ++ spi-max-frequency = <50000000>; ++ nand-on-flash-bbt; ++ spi-rx-bus-width = <2>; ++ spi-tx-bus-width = <4>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ linux,mtd-name = "spi-nand"; ++ }; + }; + + &uart0 { From 3cd9219e5e16aa38606ea82e4fadb1e0f5f39743 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 9 Aug 2020 19:47:17 +0200 Subject: [PATCH 08/17] pistachio: Make patches and configuration apply on to of 5.4 This refreshes the patches, removes patches already applied upstream and removes the SPI NAND framework to use the upstream version. In addition it also refreshes the kernel configuration. Signed-off-by: Hauke Mehrtens --- target/linux/pistachio/Makefile | 1 + target/linux/pistachio/config-5.4 | 95 ++- ...ine-img-mdc-Handle-early-status-read.patch | 2 +- ...mg-spfi-Implement-dual-and-quad-mode.patch | 12 +- ...-device-select-bits-for-SPFI-port-st.patch | 27 - ...-device-0-configuration-for-all-devi.patch | 4 +- ...i-RX-maximum-burst-size-for-DMA-is-8.patch | 4 +- ...g-spfi-finish-every-transfer-cleanly.patch | 12 +- ...y-programming-min-delta-up-to-10-tim.patch | 66 -- ...istachio-Fix-wrong-SDHost-card-speed.patch | 6 +- ...-img-marduk-switch-mmc-to-1-bit-mode.patch | 4 +- ...or-support-mtd-name-from-device-tree.patch | 10 +- ...ength-of-ID-before-reading-bits-per-.patch | 33 - ...JEDEC-manufacturer-ID-for-Gigadevice.patch | 35 - ...413-mtd-Introduce-SPI-NAND-framework.patch | 707 ------------------ ...mtd-spi-nand-Support-Gigadevice-GD5F.patch | 524 ------------- ...TS-img-marduk-add-nor-partition-name.patch | 2 +- ...S-img-marduk-add-nand-device-support.patch | 4 +- 18 files changed, 89 insertions(+), 1459 deletions(-) delete mode 100644 target/linux/pistachio/patches-5.4/103-spi-img-spfi-set-device-select-bits-for-SPFI-port-st.patch delete mode 100644 target/linux/pistachio/patches-5.4/107-clockevents-Retry-programming-min-delta-up-to-10-tim.patch delete mode 100644 target/linux/pistachio/patches-5.4/411-mtd-nand-Check-length-of-ID-before-reading-bits-per-.patch delete mode 100644 target/linux/pistachio/patches-5.4/412-mtd-nand-Add-JEDEC-manufacturer-ID-for-Gigadevice.patch delete mode 100644 target/linux/pistachio/patches-5.4/413-mtd-Introduce-SPI-NAND-framework.patch delete mode 100644 target/linux/pistachio/patches-5.4/414-mtd-spi-nand-Support-Gigadevice-GD5F.patch diff --git a/target/linux/pistachio/Makefile b/target/linux/pistachio/Makefile index c13f63bd18..0bf04dcc56 100644 --- a/target/linux/pistachio/Makefile +++ b/target/linux/pistachio/Makefile @@ -14,6 +14,7 @@ CPU_TYPE:=24kc CPU_SUBTYPE:=24kf KERNEL_PATCHVER:=4.14 +KERNEL_TESTING_PATCHVER:=5.4 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/pistachio/config-5.4 b/target/linux/pistachio/config-5.4 index 8b24b68a05..c4637c1372 100644 --- a/target/linux/pistachio/config-5.4 +++ b/target/linux/pistachio/config-5.4 @@ -1,23 +1,21 @@ -CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_32BIT_OFF_T=y CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set -# CONFIG_ARCH_HAS_SG_CHAIN is not set -# CONFIG_ARCH_HAS_STRICT_KERNEL_RWX is not set -# CONFIG_ARCH_HAS_STRICT_MODULE_RWX is not set +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_ARCH_MMAP_RND_BITS_MAX=15 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_SD=y @@ -31,12 +29,13 @@ CONFIG_CLKSRC_PISTACHIO=y CONFIG_CLONE_BACKWARDS=y CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_BOSTON is not set +CONFIG_COMPAT_32BIT_TIME=y CONFIG_CONNECTOR=y CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_LOAD_STORE_LR=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y @@ -49,7 +48,6 @@ CONFIG_CPU_MIPSR2_IRQ_VI=y CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y CONFIG_CPU_PM=y CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_R4K_FPU=y CONFIG_CPU_RMAP=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HIGHMEM=y @@ -64,6 +62,8 @@ CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y @@ -74,34 +74,46 @@ CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_ZSTD=y CONFIG_CSRC_R4K=y CONFIG_DMADEVICES=y CONFIG_DMA_ENGINE=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y CONFIG_DMA_OF=y CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DTC=y -# CONFIG_DWMAC_DWC_QOS_ETH is not set CONFIG_DWMAC_GENERIC=y CONFIG_EARLY_PRINTK=y CONFIG_EARLY_PRINTK_8250=y +CONFIG_EFI_EARLYCON=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y CONFIG_FIXED_PHY=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y CONFIG_FS_POSIX_ACL=y +CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_IO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOMAP=y CONFIG_GENERIC_IRQ_CHIP=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_IPI=y CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PINCONF=y @@ -112,21 +124,18 @@ CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_IRQCHIP=y -# CONFIG_GRO_CELLS is not set CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HARDWARE_WATCHPOINTS=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_HAVE_ARCH_COMPILER_H=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_CBPF_JIT=y -CONFIG_HAVE_CC_STACKPROTECTOR=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_HAVE_CONTEXT_TRACKING=y @@ -134,27 +143,30 @@ CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_API_DEBUG=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FAST_GUP=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_VDSO=y CONFIG_HAVE_IDE=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_KVM=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y CONFIG_HAVE_MEMBLOCK_NODE_MAP=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_HAVE_NET_DSA=y CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HOTPLUG_CPU=y +CONFIG_HZ=250 +CONFIG_HZ_250=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_IMG=y @@ -171,6 +183,7 @@ CONFIG_JBD2=y CONFIG_LEDS_PWM=y CONFIG_LIBFDT=y CONFIG_LKDTM=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y @@ -179,11 +192,14 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0 CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y +CONFIG_MEMFD_CREATE=y CONFIG_MFD_SYSCON=y CONFIG_MICREL_PHY=y +CONFIG_MIGRATION=y CONFIG_MIPS=y CONFIG_MIPS_ASID_BITS=8 CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CBPF_JIT=y CONFIG_MIPS_CLOCK_VSYSCALL=y CONFIG_MIPS_CM=y # CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set @@ -192,37 +208,34 @@ CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y CONFIG_MIPS_CPC=y CONFIG_MIPS_CPS=y # CONFIG_MIPS_CPS_CPUIDLE is not set -# CONFIG_MIPS_CPS_NS16550 is not set +# CONFIG_MIPS_CPS_NS16550_BOOL is not set CONFIG_MIPS_CPS_PM=y CONFIG_MIPS_CPU_SCACHE=y # CONFIG_MIPS_ELF_APPENDED_DTB is not set CONFIG_MIPS_EXTERNAL_TIMER=y CONFIG_MIPS_GIC=y -# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MACHINE is not set CONFIG_MIPS_MT=y CONFIG_MIPS_MT_FPAFF=y CONFIG_MIPS_MT_SMP=y CONFIG_MIPS_NO_APPENDED_DTB=y +CONFIG_MIPS_NR_CPU_NR_MAP=4 CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y # CONFIG_MIPS_RAW_APPENDED_DTB is not set CONFIG_MIPS_SPRAM=y -# CONFIG_MIPS_VPE_LOADER is not set CONFIG_MMC=y CONFIG_MMC_BLOCK=y CONFIG_MMC_DW=y +# CONFIG_MMC_DW_BLUEFIELD is not set # CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set # CONFIG_MMC_DW_K3 is not set CONFIG_MMC_DW_PLTFM=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_CORE=y CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NAND_DEVICES=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384 @@ -242,7 +255,6 @@ CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y CONFIG_NO_HZ=y CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_IDLE=y -# CONFIG_NO_IOPORT_MAP is not set CONFIG_NR_CPUS=4 CONFIG_OF=y CONFIG_OF_ADDRESS=y @@ -250,14 +262,17 @@ CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_FLATTREE=y CONFIG_OF_GPIO=y CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y CONFIG_OF_NET=y CONFIG_PADATA=y +CONFIG_PAGE_POOL=y CONFIG_PCI_DRIVERS_LEGACY=y CONFIG_PERF_USE_VMALLOC=y CONFIG_PGTABLE_LEVELS=2 # CONFIG_PGTABLE_MAPPING is not set CONFIG_PHYLIB=y +CONFIG_PHYLINK=y CONFIG_PHY_PISTACHIO_USB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_PISTACHIO=y @@ -279,9 +294,7 @@ CONFIG_RATIONAL=y CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_RCU_STALL_COMMON=y CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y @@ -294,18 +307,22 @@ CONFIG_SCHED_INFO=y CONFIG_SCSI=y CONFIG_SCSI_SPI_ATTRS=y CONFIG_SERIAL_8250_DW=y -# CONFIG_SERIAL_8250_FSL is not set +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y CONFIG_SG_POOL=y CONFIG_SMP=y CONFIG_SMP_UP=y CONFIG_SPI=y CONFIG_SPI_IMG_SPFI=y CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y CONFIG_SRAM=y CONFIG_SRCU=y CONFIG_STMMAC_ETH=y CONFIG_STMMAC_PLATFORM=y +# CONFIG_STMMAC_SELFTESTS is not set CONFIG_SWPHY=y CONFIG_SYNC_R4K=y CONFIG_SYSCTL_EXCEPTION_TRACE=y @@ -321,6 +338,7 @@ CONFIG_SYS_SUPPORTS_RELOCATABLE=y CONFIG_SYS_SUPPORTS_SCHED_SMT=y CONFIG_SYS_SUPPORTS_SMP=y CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_TARGET_ISA_REV=2 CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y @@ -331,12 +349,12 @@ CONFIG_UBIFS_FS=y # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UBIFS_FS_ZSTD=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_COMMON=y CONFIG_USB_DWC2=y CONFIG_USB_DWC2_DUAL_ROLE=y -# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set CONFIG_USB_EHCI_HCD=y # CONFIG_USB_EHCI_HCD_PLATFORM is not set CONFIG_USB_GADGET=y @@ -348,7 +366,10 @@ CONFIG_USE_OF=y CONFIG_WATCHDOG_CORE=y CONFIG_WEAK_ORDERING=y CONFIG_XPS=y +CONFIG_XXHASH=y CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_INFLATE=y CONFIG_ZSMALLOC=y # CONFIG_ZSMALLOC_STAT is not set +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/pistachio/patches-5.4/101-dmaengine-img-mdc-Handle-early-status-read.patch b/target/linux/pistachio/patches-5.4/101-dmaengine-img-mdc-Handle-early-status-read.patch index 92293f8796..031a4e3e5e 100644 --- a/target/linux/pistachio/patches-5.4/101-dmaengine-img-mdc-Handle-early-status-read.patch +++ b/target/linux/pistachio/patches-5.4/101-dmaengine-img-mdc-Handle-early-status-read.patch @@ -16,7 +16,7 @@ Signed-off-by: Damien Horsley --- a/drivers/dma/img-mdc-dma.c +++ b/drivers/dma/img-mdc-dma.c -@@ -620,25 +620,33 @@ static enum dma_status mdc_tx_status(str +@@ -618,25 +618,33 @@ static enum dma_status mdc_tx_status(str (MDC_CMDS_PROCESSED_CMDS_DONE_MASK + 1); /* diff --git a/target/linux/pistachio/patches-5.4/102-spi-img-spfi-Implement-dual-and-quad-mode.patch b/target/linux/pistachio/patches-5.4/102-spi-img-spfi-Implement-dual-and-quad-mode.patch index 15a5d3c806..9966ae71a9 100644 --- a/target/linux/pistachio/patches-5.4/102-spi-img-spfi-Implement-dual-and-quad-mode.patch +++ b/target/linux/pistachio/patches-5.4/102-spi-img-spfi-Implement-dual-and-quad-mode.patch @@ -28,7 +28,7 @@ Signed-off-by: Ezequiel Garcia --- a/drivers/spi/spi-img-spfi.c +++ b/drivers/spi/spi-img-spfi.c -@@ -40,7 +40,8 @@ +@@ -37,7 +37,8 @@ #define SPFI_CONTROL_SOFT_RESET BIT(11) #define SPFI_CONTROL_SEND_DMA BIT(10) #define SPFI_CONTROL_GET_DMA BIT(9) @@ -38,7 +38,7 @@ Signed-off-by: Ezequiel Garcia #define SPFI_CONTROL_TMODE_SHIFT 5 #define SPFI_CONTROL_TMODE_MASK 0x7 #define SPFI_CONTROL_TMODE_SINGLE 0 -@@ -51,6 +52,10 @@ +@@ -48,6 +49,10 @@ #define SPFI_TRANSACTION 0x18 #define SPFI_TRANSACTION_TSIZE_SHIFT 16 #define SPFI_TRANSACTION_TSIZE_MASK 0xffff @@ -49,7 +49,7 @@ Signed-off-by: Ezequiel Garcia #define SPFI_PORT_STATE 0x1c #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20 -@@ -87,6 +92,7 @@ +@@ -84,6 +89,7 @@ */ #define SPFI_32BIT_FIFO_SIZE 64 #define SPFI_8BIT_FIFO_SIZE 16 @@ -57,7 +57,7 @@ Signed-off-by: Ezequiel Garcia struct img_spfi { struct device *dev; -@@ -103,6 +109,8 @@ struct img_spfi { +@@ -100,6 +106,8 @@ struct img_spfi { struct dma_chan *tx_ch; bool tx_dma_busy; bool rx_dma_busy; @@ -66,7 +66,7 @@ Signed-off-by: Ezequiel Garcia }; struct img_spfi_device_data { -@@ -123,9 +131,11 @@ static inline void spfi_start(struct img +@@ -120,9 +128,11 @@ static inline void spfi_start(struct img { u32 val; @@ -81,7 +81,7 @@ Signed-off-by: Ezequiel Garcia } static inline void spfi_reset(struct img_spfi *spfi) -@@ -138,12 +148,21 @@ static int spfi_wait_all_done(struct img +@@ -135,12 +145,21 @@ static int spfi_wait_all_done(struct img { unsigned long timeout = jiffies + msecs_to_jiffies(50); diff --git a/target/linux/pistachio/patches-5.4/103-spi-img-spfi-set-device-select-bits-for-SPFI-port-st.patch b/target/linux/pistachio/patches-5.4/103-spi-img-spfi-set-device-select-bits-for-SPFI-port-st.patch deleted file mode 100644 index ba70348da9..0000000000 --- a/target/linux/pistachio/patches-5.4/103-spi-img-spfi-set-device-select-bits-for-SPFI-port-st.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 145f5369510b86cd55c659388a26a0cc267f8874 Mon Sep 17 00:00:00 2001 -From: Ionela Voinescu -Date: Mon, 1 Feb 2016 10:58:08 +0000 -Subject: spi: img-spfi: set device select bits for SPFI port state - -Even if the chip select line is not controlled by the SPFI -hardware, the device select bits need to be set to specify -the chip select line in use for the hardware to know what -parameters to use for the current transfer. - -Signed-off-by: Ionela Voinescu ---- - drivers/spi/spi-img-spfi.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/spi/spi-img-spfi.c -+++ b/drivers/spi/spi-img-spfi.c -@@ -438,6 +438,9 @@ static int img_spfi_prepare(struct spi_m - u32 val; - - val = spfi_readl(spfi, SPFI_PORT_STATE); -+ val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << -+ SPFI_PORT_STATE_DEV_SEL_SHIFT); -+ val |= msg->spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT; - if (msg->spi->mode & SPI_CPHA) - val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select); - else diff --git a/target/linux/pistachio/patches-5.4/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch b/target/linux/pistachio/patches-5.4/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch index 6c9e6b5a76..9050dae187 100644 --- a/target/linux/pistachio/patches-5.4/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch +++ b/target/linux/pistachio/patches-5.4/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch @@ -15,7 +15,7 @@ Signed-off-by: Ionela Voinescu --- a/drivers/spi/spi-img-spfi.c +++ b/drivers/spi/spi-img-spfi.c -@@ -437,18 +437,23 @@ static int img_spfi_prepare(struct spi_m +@@ -434,18 +434,23 @@ static int img_spfi_prepare(struct spi_m struct img_spfi *spfi = spi_master_get_devdata(master); u32 val; @@ -44,7 +44,7 @@ Signed-off-by: Ionela Voinescu spfi_writel(spfi, val, SPFI_PORT_STATE); return 0; -@@ -548,11 +553,15 @@ static void img_spfi_config(struct spi_m +@@ -545,11 +550,15 @@ static void img_spfi_config(struct spi_m div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz); div = clamp(512 / (1 << get_count_order(div)), 1, 128); diff --git a/target/linux/pistachio/patches-5.4/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch b/target/linux/pistachio/patches-5.4/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch index 0067b0ea4a..182897cd5a 100644 --- a/target/linux/pistachio/patches-5.4/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch +++ b/target/linux/pistachio/patches-5.4/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch @@ -29,7 +29,7 @@ Signed-off-by: Ionela Voinescu --- a/drivers/spi/spi-img-spfi.c +++ b/drivers/spi/spi-img-spfi.c -@@ -346,12 +346,11 @@ static int img_spfi_start_dma(struct spi +@@ -343,12 +343,11 @@ static int img_spfi_start_dma(struct spi if (xfer->len % 4 == 0) { rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA; rxconf.src_addr_width = 4; @@ -43,7 +43,7 @@ Signed-off-by: Ionela Voinescu dmaengine_slave_config(spfi->rx_ch, &rxconf); rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl, -@@ -370,12 +369,11 @@ static int img_spfi_start_dma(struct spi +@@ -367,12 +366,11 @@ static int img_spfi_start_dma(struct spi if (xfer->len % 4 == 0) { txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA; txconf.dst_addr_width = 4; diff --git a/target/linux/pistachio/patches-5.4/106-spi-img-spfi-finish-every-transfer-cleanly.patch b/target/linux/pistachio/patches-5.4/106-spi-img-spfi-finish-every-transfer-cleanly.patch index 0f958314e3..cffb72ee33 100644 --- a/target/linux/pistachio/patches-5.4/106-spi-img-spfi-finish-every-transfer-cleanly.patch +++ b/target/linux/pistachio/patches-5.4/106-spi-img-spfi-finish-every-transfer-cleanly.patch @@ -24,7 +24,7 @@ Signed-off-by: Ionela Voinescu --- a/drivers/spi/spi-img-spfi.c +++ b/drivers/spi/spi-img-spfi.c -@@ -83,6 +83,14 @@ +@@ -80,6 +80,14 @@ #define SPFI_INTERRUPT_SDE BIT(1) #define SPFI_INTERRUPT_SDTRIG BIT(0) @@ -39,7 +39,7 @@ Signed-off-by: Ionela Voinescu /* * There are four parallel FIFOs of 16 bytes each. The word buffer * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an -@@ -144,6 +152,23 @@ static inline void spfi_reset(struct img +@@ -141,6 +149,23 @@ static inline void spfi_reset(struct img spfi_writel(spfi, 0, SPFI_CONTROL); } @@ -63,7 +63,7 @@ Signed-off-by: Ionela Voinescu static int spfi_wait_all_done(struct img_spfi *spfi) { unsigned long timeout = jiffies + msecs_to_jiffies(50); -@@ -152,19 +177,9 @@ static int spfi_wait_all_done(struct img +@@ -149,19 +174,9 @@ static int spfi_wait_all_done(struct img return 0; while (time_before(jiffies, timeout)) { @@ -85,7 +85,7 @@ Signed-off-by: Ionela Voinescu cpu_relax(); } -@@ -296,6 +311,8 @@ static int img_spfi_start_pio(struct spi +@@ -293,6 +308,8 @@ static int img_spfi_start_pio(struct spi } ret = spfi_wait_all_done(spfi); @@ -94,7 +94,7 @@ Signed-off-by: Ionela Voinescu if (ret < 0) return ret; -@@ -311,8 +328,10 @@ static void img_spfi_dma_rx_cb(void *dat +@@ -308,8 +325,10 @@ static void img_spfi_dma_rx_cb(void *dat spin_lock_irqsave(&spfi->lock, flags); spfi->rx_dma_busy = false; @@ -106,7 +106,7 @@ Signed-off-by: Ionela Voinescu spin_unlock_irqrestore(&spfi->lock, flags); } -@@ -325,8 +344,10 @@ static void img_spfi_dma_tx_cb(void *dat +@@ -322,8 +341,10 @@ static void img_spfi_dma_tx_cb(void *dat spin_lock_irqsave(&spfi->lock, flags); spfi->tx_dma_busy = false; diff --git a/target/linux/pistachio/patches-5.4/107-clockevents-Retry-programming-min-delta-up-to-10-tim.patch b/target/linux/pistachio/patches-5.4/107-clockevents-Retry-programming-min-delta-up-to-10-tim.patch deleted file mode 100644 index 857823b783..0000000000 --- a/target/linux/pistachio/patches-5.4/107-clockevents-Retry-programming-min-delta-up-to-10-tim.patch +++ /dev/null @@ -1,66 +0,0 @@ -From b46f8c74afdd30cd52bfdcc2231470a0bab04416 Mon Sep 17 00:00:00 2001 -From: James Hogan -Date: Fri, 22 Apr 2016 18:22:45 +0100 -Subject: clockevents: Retry programming min delta up to 10 times - -Under virtualisation it is possible to get unexpected latency during a -clockevent device's set_next_event() callback which can make it return --ETIME even for a delta based on min_delta_ns. - -The clockevents_program_min_delta() implementation for -CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=n doesn't handle retries when this -happens, nor does clockevents_program_event() or its callers when force -is true (for example hrtimer_reprogram()). This can result in hangs -until the clock event device does a full period. - -It isn't appropriate to use MIN_ADJUST in this case as occasional -hypervisor induced high latency will cause min_delta_ns to quickly -increase to the maximum. -Instead, borrow the retry pattern from the MIN_ADJUST case, but without -making adjustments. We retry up to 10 times before giving up. - -(picked https://patchwork.kernel.org/patch/8909491/) - -Signed-off-by: James Hogan ---- - kernel/time/clockevents.c | 26 +++++++++++++++++++------- - 1 file changed, 19 insertions(+), 7 deletions(-) - ---- a/kernel/time/clockevents.c -+++ b/kernel/time/clockevents.c -@@ -281,16 +281,28 @@ static int clockevents_program_min_delta - { - unsigned long long clc; - int64_t delta; -+ int i; - -- delta = dev->min_delta_ns; -- dev->next_event = ktime_add_ns(ktime_get(), delta); -+ for (i = 0;;) { -+ delta = dev->min_delta_ns; -+ dev->next_event = ktime_add_ns(ktime_get(), delta); - -- if (clockevent_state_shutdown(dev)) -- return 0; -+ if (clockevent_state_shutdown(dev)) -+ return 0; - -- dev->retries++; -- clc = ((unsigned long long) delta * dev->mult) >> dev->shift; -- return dev->set_next_event((unsigned long) clc, dev); -+ dev->retries++; -+ clc = ((unsigned long long) delta * dev->mult) >> dev->shift; -+ if (dev->set_next_event((unsigned long) clc, dev) == 0) -+ return 0; -+ -+ if (++i > 9) { -+ /* -+ * We tried 10 times to program the device with the -+ * given min_delta_ns. Get out of here. -+ */ -+ return -ETIME; -+ } -+ } - } - - #endif /* CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST */ diff --git a/target/linux/pistachio/patches-5.4/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch b/target/linux/pistachio/patches-5.4/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch index 5329ad62d0..6fddbe269a 100644 --- a/target/linux/pistachio/patches-5.4/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch +++ b/target/linux/pistachio/patches-5.4/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch @@ -20,7 +20,7 @@ Signed-off-by: Govindraj Raja --- a/drivers/clk/pistachio/clk-pistachio.c +++ b/drivers/clk/pistachio/clk-pistachio.c -@@ -44,7 +44,7 @@ static struct pistachio_gate pistachio_g +@@ -41,7 +41,7 @@ static struct pistachio_gate pistachio_g GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div", 0x104, 22), GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23), @@ -29,7 +29,7 @@ Signed-off-by: Govindraj Raja GATE(CLK_BT, "bt", "bt_div", 0x104, 25), GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26), GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27), -@@ -54,6 +54,7 @@ static struct pistachio_gate pistachio_g +@@ -51,6 +51,7 @@ static struct pistachio_gate pistachio_g static struct pistachio_fixed_factor pistachio_ffs[] __initdata = { FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4), FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8), @@ -39,7 +39,7 @@ Signed-off-by: Govindraj Raja static struct pistachio_div pistachio_divs[] __initdata = { --- a/include/dt-bindings/clock/pistachio-clk.h +++ b/include/dt-bindings/clock/pistachio-clk.h -@@ -21,6 +21,7 @@ +@@ -18,6 +18,7 @@ /* Fixed-factor clocks */ #define CLK_WIFI_DIV4 16 #define CLK_WIFI_DIV8 17 diff --git a/target/linux/pistachio/patches-5.4/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch b/target/linux/pistachio/patches-5.4/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch index 22fc42b988..cec424a0ce 100644 --- a/target/linux/pistachio/patches-5.4/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch +++ b/target/linux/pistachio/patches-5.4/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch @@ -28,7 +28,7 @@ Signed-off-by: Ian Pozella --- a/arch/mips/boot/dts/img/pistachio_marduk.dts +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts -@@ -120,7 +120,7 @@ +@@ -117,7 +117,7 @@ &sdhost { status = "okay"; @@ -37,7 +37,7 @@ Signed-off-by: Ian Pozella disable-wp; }; -@@ -130,6 +130,7 @@ +@@ -127,6 +127,7 @@ &pin_sdhost_data { drive-strength = <2>; diff --git a/target/linux/pistachio/patches-5.4/401-mtd-nor-support-mtd-name-from-device-tree.patch b/target/linux/pistachio/patches-5.4/401-mtd-nor-support-mtd-name-from-device-tree.patch index 065a0b77bc..5d2f9284ab 100644 --- a/target/linux/pistachio/patches-5.4/401-mtd-nor-support-mtd-name-from-device-tree.patch +++ b/target/linux/pistachio/patches-5.4/401-mtd-nor-support-mtd-name-from-device-tree.patch @@ -10,17 +10,17 @@ Signed-off-by: Abhimanyu Vishwakarma --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -2671,6 +2671,7 @@ int spi_nor_scan(struct spi_nor *nor, co - struct device *dev = nor->dev; +@@ -4931,6 +4931,7 @@ int spi_nor_scan(struct spi_nor *nor, co struct mtd_info *mtd = &nor->mtd; struct device_node *np = spi_nor_get_flash_node(nor); + struct spi_nor_flash_parameter *params = &nor->params; + const char __maybe_unused *of_mtd_name = NULL; int ret; int i; -@@ -2746,7 +2747,12 @@ int spi_nor_scan(struct spi_nor *nor, co - spi_nor_wait_till_ready(nor); - } +@@ -4993,7 +4994,12 @@ int spi_nor_scan(struct spi_nor *nor, co + /* Init flash parameters based on flash_info struct and SFDP */ + spi_nor_init_params(nor); - if (!mtd->name) +#ifdef CONFIG_MTD_OF_PARTS diff --git a/target/linux/pistachio/patches-5.4/411-mtd-nand-Check-length-of-ID-before-reading-bits-per-.patch b/target/linux/pistachio/patches-5.4/411-mtd-nand-Check-length-of-ID-before-reading-bits-per-.patch deleted file mode 100644 index 3311de645f..0000000000 --- a/target/linux/pistachio/patches-5.4/411-mtd-nand-Check-length-of-ID-before-reading-bits-per-.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 42ebff638003be18fab503b37de4ad7853244e95 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Sat, 25 Feb 2017 15:58:22 +0000 -Subject: mtd: nand: Check length of ID before reading bits per cell - -The table-based NAND identification currently reads the number -of bits per cell from the 3rd byte of the extended ID. This is done -for the so-called 'full ID' devices; i.e. devices that have a known -length ID. - -However, if the ID length is shorter than three, there's no 3rd byte, -and so it's wrong to read the bits per cell from there. Fix this by -adding a check for the ID length. - -(picked from http://lists.infradead.org/pipermail/linux-mtd/2014-December/056764.html) - -Signed-off-by: Ezequiel Garcia ---- - drivers/mtd/nand/nand_base.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/nand/nand_base.c -+++ b/drivers/mtd/nand/nand_base.c -@@ -3803,7 +3803,8 @@ static bool find_full_id_nand(struct nan - mtd->erasesize = type->erasesize; - mtd->oobsize = type->oobsize; - -- chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); -+ if (type->id_len > 2) -+ chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); - chip->chipsize = (uint64_t)type->chipsize << 20; - chip->options |= type->options; - chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); diff --git a/target/linux/pistachio/patches-5.4/412-mtd-nand-Add-JEDEC-manufacturer-ID-for-Gigadevice.patch b/target/linux/pistachio/patches-5.4/412-mtd-nand-Add-JEDEC-manufacturer-ID-for-Gigadevice.patch deleted file mode 100644 index a967124c81..0000000000 --- a/target/linux/pistachio/patches-5.4/412-mtd-nand-Add-JEDEC-manufacturer-ID-for-Gigadevice.patch +++ /dev/null @@ -1,35 +0,0 @@ -From a4bc33b205fd9b1db862f1e45173dba57b0fa57f Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Sat, 25 Feb 2017 15:43:09 +0000 -Subject: mtd: nand: Add JEDEC manufacturer ID for Gigadevice - -This commit adds Gigadevice to the list of manufacturer ID and name strings. - -(picked from http://lists.infradead.org/pipermail/linux-mtd/2014-December/056765.html) - -Signed-off-by: Ezequiel Garcia ---- - drivers/mtd/nand/nand_ids.c | 1 + - include/linux/mtd/rawnand.h | 1 + - 2 files changed, 2 insertions(+) - ---- a/drivers/mtd/nand/nand_ids.c -+++ b/drivers/mtd/nand/nand_ids.c -@@ -184,6 +184,7 @@ static const struct nand_manufacturer na - {NAND_MFR_SANDISK, "SanDisk"}, - {NAND_MFR_INTEL, "Intel"}, - {NAND_MFR_ATO, "ATO"}, -+ {NAND_MFR_GIGADEVICE, "Gigadevice"}, - {NAND_MFR_WINBOND, "Winbond"}, - }; - ---- a/include/linux/mtd/rawnand.h -+++ b/include/linux/mtd/rawnand.h -@@ -1014,6 +1014,7 @@ static inline void *nand_get_manufacture - #define NAND_MFR_SANDISK 0x45 - #define NAND_MFR_INTEL 0x89 - #define NAND_MFR_ATO 0x9b -+#define NAND_MFR_GIGADEVICE 0xc8 - #define NAND_MFR_WINBOND 0xef - - diff --git a/target/linux/pistachio/patches-5.4/413-mtd-Introduce-SPI-NAND-framework.patch b/target/linux/pistachio/patches-5.4/413-mtd-Introduce-SPI-NAND-framework.patch deleted file mode 100644 index d1189eeb8c..0000000000 --- a/target/linux/pistachio/patches-5.4/413-mtd-Introduce-SPI-NAND-framework.patch +++ /dev/null @@ -1,707 +0,0 @@ -From 082a89a78e29b15008284df90441747cb742f149 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 2 Dec 2014 09:58:52 -0300 -Subject: mtd: Introduce SPI NAND framework - -Add a new framework, to support SPI NAND devices. The framework registers -a NAND chip and handles the generic SPI NAND protocol, calling device-specific -hooks for each SPI NAND command. - -The following is the stack design, from userspace to hardware. This commit -adds the "SPI NAND core" layer. - - Userspace - ------------------ - MTD - ------------------ - NAND core - ------------------ - SPI NAND core - ------------------ - SPI NAND device - ------------------ - SPI core - ------------------ - SPI master - ------------------ - Hardware - -(based on http://lists.infradead.org/pipermail/linux-mtd/2014-December/056763.html) - -Signed-off-by: Ionela Voinescu -Signed-off-by: Ezequiel Garcia -Signed-off-by: Ian Pozella ---- - drivers/mtd/Kconfig | 2 + - drivers/mtd/Makefile | 1 + - drivers/mtd/spi-nand/Kconfig | 7 + - drivers/mtd/spi-nand/Makefile | 1 + - drivers/mtd/spi-nand/spi-nand-base.c | 566 +++++++++++++++++++++++++++++++++++ - include/linux/mtd/spi-nand.h | 54 ++++ - 6 files changed, 631 insertions(+) - create mode 100644 drivers/mtd/spi-nand/Kconfig - create mode 100644 drivers/mtd/spi-nand/Makefile - create mode 100644 drivers/mtd/spi-nand/spi-nand-base.c - create mode 100644 include/linux/mtd/spi-nand.h - ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -373,6 +373,8 @@ source "drivers/mtd/onenand/Kconfig" - - source "drivers/mtd/lpddr/Kconfig" - -+source "drivers/mtd/spi-nand/Kconfig" -+ - source "drivers/mtd/spi-nor/Kconfig" - - source "drivers/mtd/ubi/Kconfig" ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -37,6 +37,7 @@ inftl-objs := inftlcore.o inftlmount.o - - obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/ - -+obj-$(CONFIG_MTD_SPI_NAND) += spi-nand/ - obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ - obj-$(CONFIG_MTD_UBI) += ubi/ - ---- /dev/null -+++ b/drivers/mtd/spi-nand/Kconfig -@@ -0,0 +1,7 @@ -+menuconfig MTD_SPI_NAND -+ tristate "SPI NAND device support" -+ depends on MTD -+ select MTD_NAND -+ help -+ This is the framework for the SPI NAND. -+ ---- /dev/null -+++ b/drivers/mtd/spi-nand/Makefile -@@ -0,0 +1 @@ -+obj-$(CONFIG_MTD_SPI_NAND) += spi-nand-base.o ---- /dev/null -+++ b/drivers/mtd/spi-nand/spi-nand-base.c -@@ -0,0 +1,566 @@ -+/* -+ * Copyright (C) 2014 Imagination Technologies Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; version 2 of the License. -+ * -+ * Notes: -+ * 1. Erase and program operations need to call write_enable() first, -+ * to clear the enable bit. This bit is cleared automatically after -+ * the erase or program operation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Registers common to all devices */ -+#define SPI_NAND_LOCK_REG 0xa0 -+#define SPI_NAND_PROT_UNLOCK_ALL 0x0 -+ -+#define SPI_NAND_FEATURE_REG 0xb0 -+#define SPI_NAND_ECC_EN BIT(4) -+#define SPI_NAND_QUAD_EN BIT(0) -+ -+#define SPI_NAND_STATUS_REG 0xc0 -+#define SPI_NAND_STATUS_REG_ECC_MASK 0x3 -+#define SPI_NAND_STATUS_REG_ECC_SHIFT 4 -+#define SPI_NAND_STATUS_REG_PROG_FAIL BIT(3) -+#define SPI_NAND_STATUS_REG_ERASE_FAIL BIT(2) -+#define SPI_NAND_STATUS_REG_WREN BIT(1) -+#define SPI_NAND_STATUS_REG_BUSY BIT(0) -+ -+#define SPI_NAND_CMD_BUF_LEN 8 -+ -+/* Rewind and fill the buffer with 0xff */ -+static void spi_nand_clear_buffer(struct spi_nand *snand) -+{ -+ snand->buf_start = 0; -+ memset(snand->data_buf, 0xff, snand->buf_size); -+} -+ -+static int spi_nand_enable_ecc(struct spi_nand *snand) -+{ -+ int ret; -+ -+ ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); -+ if (ret) -+ return ret; -+ -+ snand->buf[0] |= SPI_NAND_ECC_EN; -+ ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); -+ if (ret) -+ return ret; -+ snand->ecc = true; -+ -+ return 0; -+} -+ -+static int spi_nand_disable_ecc(struct spi_nand *snand) -+{ -+ int ret; -+ -+ ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); -+ if (ret) -+ return ret; -+ -+ snand->buf[0] &= ~SPI_NAND_ECC_EN; -+ ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); -+ if (ret) -+ return ret; -+ snand->ecc = false; -+ -+ return 0; -+} -+ -+static int spi_nand_enable_quad(struct spi_nand *snand) -+{ -+ int ret; -+ -+ ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); -+ if (ret) -+ return ret; -+ -+ snand->buf[0] |= SPI_NAND_QUAD_EN; -+ ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+/* -+ * Wait until the status register busy bit is cleared. -+ * Returns a negatie errno on error or time out, and a non-negative status -+ * value if the device is ready. -+ */ -+static int spi_nand_wait_till_ready(struct spi_nand *snand) -+{ -+ unsigned long deadline = jiffies + msecs_to_jiffies(100); -+ bool timeout = false; -+ int ret; -+ -+ /* -+ * Perhaps we should set a different timeout for each -+ * operation (reset, read, write, erase). -+ */ -+ while (!timeout) { -+ if (time_after_eq(jiffies, deadline)) -+ timeout = true; -+ -+ ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf); -+ if (ret < 0) { -+ dev_err(snand->dev, "error reading status register\n"); -+ return ret; -+ } else if (!(snand->buf[0] & SPI_NAND_STATUS_REG_BUSY)) { -+ return snand->buf[0]; -+ } -+ -+ cond_resched(); -+ } -+ -+ dev_err(snand->dev, "operation timed out\n"); -+ -+ return -ETIMEDOUT; -+} -+ -+static int spi_nand_reset(struct spi_nand *snand) -+{ -+ int ret; -+ -+ ret = snand->reset(snand); -+ if (ret < 0) { -+ dev_err(snand->dev, "reset command failed\n"); -+ return ret; -+ } -+ -+ /* -+ * The NAND core won't wait after a device reset, so we need -+ * to do that here. -+ */ -+ ret = spi_nand_wait_till_ready(snand); -+ if (ret < 0) -+ return ret; -+ return 0; -+} -+ -+static int spi_nand_status(struct spi_nand *snand) -+{ -+ int ret, status; -+ -+ ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf); -+ if (ret < 0) { -+ dev_err(snand->dev, "error reading status register\n"); -+ return ret; -+ } -+ status = snand->buf[0]; -+ -+ /* Convert this into standard NAND_STATUS values */ -+ if (status & SPI_NAND_STATUS_REG_BUSY) -+ snand->buf[0] = 0; -+ else -+ snand->buf[0] = NAND_STATUS_READY; -+ -+ if (status & SPI_NAND_STATUS_REG_PROG_FAIL || -+ status & SPI_NAND_STATUS_REG_ERASE_FAIL) -+ snand->buf[0] |= NAND_STATUS_FAIL; -+ -+ /* -+ * Since we unlock the entire device at initialization, unconditionally -+ * set the WP bit to indicate it's not protected. -+ */ -+ snand->buf[0] |= NAND_STATUS_WP; -+ return 0; -+} -+ -+static int spi_nand_erase(struct spi_nand *snand, int page_addr) -+{ -+ int ret; -+ -+ ret = snand->write_enable(snand); -+ if (ret < 0) { -+ dev_err(snand->dev, "write enable command failed\n"); -+ return ret; -+ } -+ -+ ret = snand->block_erase(snand, page_addr); -+ if (ret < 0) { -+ dev_err(snand->dev, "block erase command failed\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int spi_nand_write(struct spi_nand *snand) -+{ -+ int ret; -+ -+ /* Enable quad mode */ -+ ret = spi_nand_enable_quad(snand); -+ if (ret) { -+ dev_err(snand->dev, "error %d enabling quad mode\n", ret); -+ return ret; -+ } -+ /* Store the page to cache */ -+ ret = snand->store_cache(snand, 0, snand->buf_size, snand->data_buf); -+ if (ret < 0) { -+ dev_err(snand->dev, "error %d storing page 0x%x to cache\n", -+ ret, snand->page_addr); -+ return ret; -+ } -+ -+ ret = snand->write_enable(snand); -+ if (ret < 0) { -+ dev_err(snand->dev, "write enable command failed\n"); -+ return ret; -+ } -+ -+ /* Get page from the device cache into our internal buffer */ -+ ret = snand->write_page(snand, snand->page_addr); -+ if (ret < 0) { -+ dev_err(snand->dev, "error %d reading page 0x%x from cache\n", -+ ret, snand->page_addr); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int spi_nand_read_id(struct spi_nand *snand) -+{ -+ int ret; -+ -+ ret = snand->read_id(snand, snand->data_buf); -+ if (ret < 0) { -+ dev_err(snand->dev, "error %d reading ID\n", ret); -+ return ret; -+ } -+ return 0; -+} -+ -+static int spi_nand_read_page(struct spi_nand *snand, unsigned int page_addr, -+ unsigned int page_offset, size_t length) -+{ -+ unsigned int corrected = 0, ecc_error = 0; -+ int ret; -+ -+ /* Load a page into the cache register */ -+ ret = snand->load_page(snand, page_addr); -+ if (ret < 0) { -+ dev_err(snand->dev, "error %d loading page 0x%x to cache\n", -+ ret, page_addr); -+ return ret; -+ } -+ -+ ret = spi_nand_wait_till_ready(snand); -+ if (ret < 0) -+ return ret; -+ -+ if (snand->ecc) { -+ snand->get_ecc_status(ret, &corrected, &ecc_error); -+ snand->bitflips = corrected; -+ -+ /* -+ * If there's an ECC error, print a message and notify MTD -+ * about it. Then complete the read, to load actual data on -+ * the buffer (instead of the status result). -+ */ -+ if (ecc_error) { -+ dev_err(snand->dev, -+ "internal ECC error reading page 0x%x\n", -+ page_addr); -+ snand->nand_chip.mtd.ecc_stats.failed++; -+ } else { -+ snand->nand_chip.mtd.ecc_stats.corrected += corrected; -+ } -+ } -+ -+ /* Enable quad mode */ -+ ret = spi_nand_enable_quad(snand); -+ if (ret) { -+ dev_err(snand->dev, "error %d enabling quad mode\n", ret); -+ return ret; -+ } -+ /* Get page from the device cache into our internal buffer */ -+ ret = snand->read_cache(snand, page_offset, length, snand->data_buf); -+ if (ret < 0) { -+ dev_err(snand->dev, "error %d reading page 0x%x from cache\n", -+ ret, page_addr); -+ return ret; -+ } -+ return 0; -+} -+ -+static u8 spi_nand_read_byte(struct mtd_info *mtd) -+{ -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct spi_nand *snand = nand_get_controller_data(chip); -+ char val = 0xff; -+ -+ if (snand->buf_start < snand->buf_size) -+ val = snand->data_buf[snand->buf_start++]; -+ return val; -+} -+ -+static void spi_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) -+{ -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct spi_nand *snand = nand_get_controller_data(chip); -+ size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start); -+ -+ memcpy(snand->data_buf + snand->buf_start, buf, n); -+ snand->buf_start += n; -+} -+ -+static void spi_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) -+{ -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct spi_nand *snand = nand_get_controller_data(chip); -+ size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start); -+ -+ memcpy(buf, snand->data_buf + snand->buf_start, n); -+ snand->buf_start += n; -+} -+ -+static int spi_nand_write_page_hwecc(struct mtd_info *mtd, -+ struct nand_chip *chip, const uint8_t *buf, int oob_required, -+ int page) -+{ -+ chip->write_buf(mtd, buf, mtd->writesize); -+ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); -+ -+ return 0; -+} -+ -+static int spi_nand_read_page_hwecc(struct mtd_info *mtd, -+ struct nand_chip *chip, uint8_t *buf, int oob_required, -+ int page) -+{ -+ struct spi_nand *snand = nand_get_controller_data(chip); -+ -+ chip->read_buf(mtd, buf, mtd->writesize); -+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); -+ -+ return snand->bitflips; -+} -+ -+static int spi_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) -+{ -+ struct spi_nand *snand = nand_get_controller_data(chip); -+ int ret; -+ -+ ret = spi_nand_wait_till_ready(snand); -+ -+ if (ret < 0) { -+ return NAND_STATUS_FAIL; -+ } else if (ret & SPI_NAND_STATUS_REG_PROG_FAIL) { -+ dev_err(snand->dev, "page program failed\n"); -+ return NAND_STATUS_FAIL; -+ } else if (ret & SPI_NAND_STATUS_REG_ERASE_FAIL) { -+ dev_err(snand->dev, "block erase failed\n"); -+ return NAND_STATUS_FAIL; -+ } -+ -+ return NAND_STATUS_READY; -+} -+ -+static void spi_nand_cmdfunc(struct mtd_info *mtd, unsigned int command, -+ int column, int page_addr) -+{ -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct spi_nand *snand = nand_get_controller_data(chip); -+ -+ /* -+ * In case there's any unsupported command, let's make sure -+ * we don't keep garbage around in the buffer. -+ */ -+ if (command != NAND_CMD_PAGEPROG) { -+ spi_nand_clear_buffer(snand); -+ snand->page_addr = 0; -+ } -+ -+ switch (command) { -+ case NAND_CMD_READ0: -+ spi_nand_read_page(snand, page_addr, 0, mtd->writesize); -+ break; -+ case NAND_CMD_READOOB: -+ spi_nand_disable_ecc(snand); -+ spi_nand_read_page(snand, page_addr, mtd->writesize, -+ mtd->oobsize); -+ spi_nand_enable_ecc(snand); -+ break; -+ case NAND_CMD_READID: -+ spi_nand_read_id(snand); -+ break; -+ case NAND_CMD_ERASE1: -+ spi_nand_erase(snand, page_addr); -+ break; -+ case NAND_CMD_ERASE2: -+ /* There's nothing to do here, as the erase is one-step */ -+ break; -+ case NAND_CMD_SEQIN: -+ snand->buf_start = column; -+ snand->page_addr = page_addr; -+ break; -+ case NAND_CMD_PAGEPROG: -+ spi_nand_write(snand); -+ break; -+ case NAND_CMD_STATUS: -+ spi_nand_status(snand); -+ break; -+ case NAND_CMD_RESET: -+ spi_nand_reset(snand); -+ break; -+ default: -+ dev_err(&mtd->dev, "unknown command 0x%x\n", command); -+ } -+} -+ -+static void spi_nand_select_chip(struct mtd_info *mtd, int chip) -+{ -+ /* We need this to override the default */ -+} -+ -+int spi_nand_check(struct spi_nand *snand) -+{ -+ if (!snand->dev) -+ return -ENODEV; -+ if (!snand->read_cache) -+ return -ENODEV; -+ if (!snand->load_page) -+ return -ENODEV; -+ if (!snand->store_cache) -+ return -ENODEV; -+ if (!snand->write_page) -+ return -ENODEV; -+ if (!snand->write_reg) -+ return -ENODEV; -+ if (!snand->read_reg) -+ return -ENODEV; -+ if (!snand->block_erase) -+ return -ENODEV; -+ if (!snand->reset) -+ return -ENODEV; -+ if (!snand->write_enable) -+ return -ENODEV; -+ if (!snand->write_disable) -+ return -ENODEV; -+ if (!snand->get_ecc_status) -+ return -ENODEV; -+ return 0; -+} -+ -+int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids) -+{ -+ struct nand_chip *chip = &snand->nand_chip; -+ struct mtd_info *mtd = nand_to_mtd(chip); -+ struct device_node *np = snand->dev->of_node; -+ const char __maybe_unused *of_mtd_name = NULL; -+ int ret; -+ -+ /* Let's check all the hooks are in-place so we don't panic later */ -+ ret = spi_nand_check(snand); -+ if (ret) -+ return ret; -+ -+ nand_set_controller_data(chip, snand); -+ nand_set_flash_node(chip, np); -+ chip->read_buf = spi_nand_read_buf; -+ chip->write_buf = spi_nand_write_buf; -+ chip->read_byte = spi_nand_read_byte; -+ chip->cmdfunc = spi_nand_cmdfunc; -+ chip->waitfunc = spi_nand_waitfunc; -+ chip->select_chip = spi_nand_select_chip; -+ chip->options |= NAND_NO_SUBPAGE_WRITE; -+ chip->bits_per_cell = 1; -+ -+ mtd_set_ooblayout(mtd, snand->ooblayout); -+ chip->ecc.read_page = spi_nand_read_page_hwecc; -+ chip->ecc.write_page = spi_nand_write_page_hwecc; -+ chip->ecc.mode = NAND_ECC_HW; -+ -+ if (of_property_read_bool(np, "nand-on-flash-bbt")) -+ chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; -+ -+#ifdef CONFIG_MTD_OF_PARTS -+ of_property_read_string(np, "linux,mtd-name", &of_mtd_name); -+#endif -+ if (of_mtd_name) -+ mtd->name = of_mtd_name; -+ else -+ mtd->name = snand->name; -+ mtd->owner = THIS_MODULE; -+ -+ /* Allocate buffer to be used to read/write the internal registers */ -+ snand->buf = kmalloc(SPI_NAND_CMD_BUF_LEN, GFP_KERNEL); -+ if (!snand->buf) -+ return -ENOMEM; -+ -+ /* This is enabled at device power up but we'd better make sure */ -+ ret = spi_nand_enable_ecc(snand); -+ if (ret) -+ return ret; -+ -+ /* Preallocate buffer for flash identification (NAND_CMD_READID) */ -+ snand->buf_size = SPI_NAND_CMD_BUF_LEN; -+ snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL); -+ -+ ret = nand_scan_ident(mtd, 1, flash_ids); -+ if (ret) -+ return ret; -+ -+ /* -+ * SPI NAND has on-die ECC, which means we can correct as much as -+ * we are required to. This must be done after identification of -+ * the device. -+ */ -+ chip->ecc.strength = chip->ecc_strength_ds; -+ chip->ecc.size = chip->ecc_step_ds; -+ -+ /* -+ * Unlock all the device before calling nand_scan_tail. This is needed -+ * in case the in-flash bad block table needs to be created. -+ * We could override __nand_unlock(), but since it's not currently used -+ * by the NAND core we call this explicitly. -+ */ -+ snand->buf[0] = SPI_NAND_PROT_UNLOCK_ALL; -+ ret = snand->write_reg(snand, SPI_NAND_LOCK_REG, snand->buf); -+ if (ret) -+ return ret; -+ -+ /* Free the buffer and allocate a good one, to fit a page plus OOB */ -+ kfree(snand->data_buf); -+ -+ snand->buf_size = mtd->writesize + mtd->oobsize; -+ snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL); -+ if (!snand->data_buf) -+ return -ENOMEM; -+ -+ ret = nand_scan_tail(mtd); -+ if (ret) -+ return ret; -+ -+ return mtd_device_register(mtd, NULL, 0); -+} -+EXPORT_SYMBOL_GPL(spi_nand_register); -+ -+void spi_nand_unregister(struct spi_nand *snand) -+{ -+ kfree(snand->buf); -+ kfree(snand->data_buf); -+} -+EXPORT_SYMBOL_GPL(spi_nand_unregister); -+ -+MODULE_AUTHOR("Ezequiel Garcia "); -+MODULE_DESCRIPTION("Framework for SPI NAND"); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/include/linux/mtd/spi-nand.h -@@ -0,0 +1,54 @@ -+/* -+ * Copyright (C) 2014 Imagination Technologies Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; version 2 of the License. -+ */ -+ -+#ifndef __LINUX_MTD_SPI_NAND_H -+#define __LINUX_MTD_SPI_NAND_H -+ -+#include -+#include -+ -+struct spi_nand { -+ struct nand_chip nand_chip; -+ struct device *dev; -+ const char *name; -+ -+ u8 *buf, *data_buf; -+ size_t buf_size; -+ off_t buf_start; -+ unsigned int page_addr; -+ unsigned int bitflips; -+ bool ecc; -+ struct mtd_ooblayout_ops *ooblayout; -+ -+ int (*reset)(struct spi_nand *snand); -+ int (*read_id)(struct spi_nand *snand, u8 *buf); -+ -+ int (*write_disable)(struct spi_nand *snand); -+ int (*write_enable)(struct spi_nand *snand); -+ -+ int (*read_reg)(struct spi_nand *snand, u8 opcode, u8 *buf); -+ int (*write_reg)(struct spi_nand *snand, u8 opcode, u8 *buf); -+ void (*get_ecc_status)(unsigned int status, -+ unsigned int *corrected, -+ unsigned int *ecc_errors); -+ -+ int (*store_cache)(struct spi_nand *snand, unsigned int page_offset, -+ size_t length, u8 *write_buf); -+ int (*write_page)(struct spi_nand *snand, unsigned int page_addr); -+ int (*load_page)(struct spi_nand *snand, unsigned int page_addr); -+ int (*read_cache)(struct spi_nand *snand, unsigned int page_offset, -+ size_t length, u8 *read_buf); -+ int (*block_erase)(struct spi_nand *snand, unsigned int page_addr); -+ -+ void *priv; -+}; -+ -+int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids); -+void spi_nand_unregister(struct spi_nand *snand); -+ -+#endif diff --git a/target/linux/pistachio/patches-5.4/414-mtd-spi-nand-Support-Gigadevice-GD5F.patch b/target/linux/pistachio/patches-5.4/414-mtd-spi-nand-Support-Gigadevice-GD5F.patch deleted file mode 100644 index 1f1461061c..0000000000 --- a/target/linux/pistachio/patches-5.4/414-mtd-spi-nand-Support-Gigadevice-GD5F.patch +++ /dev/null @@ -1,524 +0,0 @@ -From 7723e59d483a883578115a73eb87eb7fff0ff724 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 28 Feb 2017 10:37:24 +0000 -Subject: mtd: spi-nand: Support Gigadevice GD5F - -This commit uses the recently introduced SPI NAND framework to support -the Gigadevice GD5F serial NAND device. - -The current support includes: - - * Page read and page program operations (using on-die ECC) - * Page out-of-band read - * Erase - * Reset - * Device status retrieval - * Device ID retrieval - -(based on http://lists.infradead.org/pipermail/linux-mtd/2014-December/056769.html) - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Ian Pozella ---- - drivers/mtd/spi-nand/Kconfig | 10 + - drivers/mtd/spi-nand/Makefile | 1 + - drivers/mtd/spi-nand/spi-nand-device.c | 472 +++++++++++++++++++++++++++++++++ - 3 files changed, 483 insertions(+) - create mode 100644 drivers/mtd/spi-nand/spi-nand-device.c - ---- a/drivers/mtd/spi-nand/Kconfig -+++ b/drivers/mtd/spi-nand/Kconfig -@@ -5,3 +5,13 @@ menuconfig MTD_SPI_NAND - help - This is the framework for the SPI NAND. - -+if MTD_SPI_NAND -+ -+config MTD_SPI_NAND_DEVICES -+ tristate "Support for SPI NAND devices" -+ default y -+ depends on MTD_SPI_NAND -+ help -+ Select this option if you require support for SPI NAND devices. -+ -+endif # MTD_SPI_NAND ---- a/drivers/mtd/spi-nand/Makefile -+++ b/drivers/mtd/spi-nand/Makefile -@@ -1 +1,2 @@ - obj-$(CONFIG_MTD_SPI_NAND) += spi-nand-base.o -+obj-$(CONFIG_MTD_SPI_NAND_DEVICES) += spi-nand-device.o ---- /dev/null -+++ b/drivers/mtd/spi-nand/spi-nand-device.c -@@ -0,0 +1,472 @@ -+/* -+ * Copyright (C) 2014 Imagination Technologies Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; version 2 of the License. -+ * -+ * Notes: -+ * 1. We avoid using a stack-allocated buffer for SPI messages. Using -+ * a kmalloced buffer is probably better, given we shouldn't assume -+ * any particular usage by SPI core. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* SPI NAND commands */ -+#define SPI_NAND_WRITE_ENABLE 0x06 -+#define SPI_NAND_WRITE_DISABLE 0x04 -+#define SPI_NAND_GET_FEATURE 0x0f -+#define SPI_NAND_SET_FEATURE 0x1f -+#define SPI_NAND_PAGE_READ 0x13 -+#define SPI_NAND_READ_CACHE 0x03 -+#define SPI_NAND_FAST_READ_CACHE 0x0b -+#define SPI_NAND_READ_CACHE_X2 0x3b -+#define SPI_NAND_READ_CACHE_X4 0x6b -+#define SPI_NAND_READ_CACHE_DUAL_IO 0xbb -+#define SPI_NAND_READ_CACHE_QUAD_IO 0xeb -+#define SPI_NAND_READ_ID 0x9f -+#define SPI_NAND_PROGRAM_LOAD 0x02 -+#define SPI_NAND_PROGRAM_LOAD4 0x32 -+#define SPI_NAND_PROGRAM_EXEC 0x10 -+#define SPI_NAND_PROGRAM_LOAD_RANDOM 0x84 -+#define SPI_NAND_PROGRAM_LOAD_RANDOM4 0xc4 -+#define SPI_NAND_BLOCK_ERASE 0xd8 -+#define SPI_NAND_RESET 0xff -+ -+#define SPI_NAND_GD5F_READID_LEN 2 -+ -+#define SPI_NAND_GD5F_ECC_MASK (BIT(0) | BIT(1) | BIT(2)) -+#define SPI_NAND_GD5F_ECC_UNCORR (BIT(0) | BIT(1) | BIT(2)) -+#define SPI_NAND_GD5F_ECC_SHIFT 4 -+ -+static int spi_nand_gd5f_ooblayout_256_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ if (section) -+ return -ERANGE; -+ -+ oobregion->offset = 128; -+ oobregion->length = 128; -+ -+ return 0; -+} -+ -+static int spi_nand_gd5f_ooblayout_256_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ if (section) -+ return -ERANGE; -+ -+ oobregion->offset = 1; -+ oobregion->length = 127; -+ -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops spi_nand_gd5f_oob_256_ops = { -+ .ecc = spi_nand_gd5f_ooblayout_256_ecc, -+ .free = spi_nand_gd5f_ooblayout_256_free, -+}; -+ -+static struct nand_flash_dev spi_nand_flash_ids[] = { -+ { -+ .name = "SPI NAND 512MiB 3,3V", -+ .id = { NAND_MFR_GIGADEVICE, 0xb4 }, -+ .chipsize = 512, -+ .pagesize = SZ_4K, -+ .erasesize = SZ_256K, -+ .id_len = 2, -+ .oobsize = 256, -+ .ecc.strength_ds = 8, -+ .ecc.step_ds = 512, -+ }, -+ { -+ .name = "SPI NAND 512MiB 1,8V", -+ .id = { NAND_MFR_GIGADEVICE, 0xa4 }, -+ .chipsize = 512, -+ .pagesize = SZ_4K, -+ .erasesize = SZ_256K, -+ .id_len = 2, -+ .oobsize = 256, -+ .ecc.strength_ds = 8, -+ .ecc.step_ds = 512, -+ }, -+}; -+ -+enum spi_nand_device_variant { -+ SPI_NAND_GENERIC, -+ SPI_NAND_GD5F, -+}; -+ -+struct spi_nand_device_cmd { -+ -+ /* -+ * Command and address. I/O errors have been observed if a -+ * separate spi_transfer is used for command and address, -+ * so keep them together. -+ */ -+ u32 n_cmd; -+ u8 cmd[5]; -+ -+ /* Tx data */ -+ u32 n_tx; -+ u8 *tx_buf; -+ -+ /* Rx data */ -+ u32 n_rx; -+ u8 *rx_buf; -+ u8 rx_nbits; -+ u8 tx_nbits; -+}; -+ -+struct spi_nand_device { -+ struct spi_nand spi_nand; -+ struct spi_device *spi; -+ -+ struct spi_nand_device_cmd cmd; -+}; -+ -+static int spi_nand_send_command(struct spi_device *spi, -+ struct spi_nand_device_cmd *cmd) -+{ -+ struct spi_message message; -+ struct spi_transfer x[2]; -+ -+ if (!cmd->n_cmd) { -+ dev_err(&spi->dev, "cannot send an empty command\n"); -+ return -EINVAL; -+ } -+ -+ if (cmd->n_tx && cmd->n_rx) { -+ dev_err(&spi->dev, "cannot send and receive data at the same time\n"); -+ return -EINVAL; -+ } -+ -+ spi_message_init(&message); -+ memset(x, 0, sizeof(x)); -+ -+ /* Command and address */ -+ x[0].len = cmd->n_cmd; -+ x[0].tx_buf = cmd->cmd; -+ x[0].tx_nbits = cmd->tx_nbits; -+ spi_message_add_tail(&x[0], &message); -+ -+ /* Data to be transmitted */ -+ if (cmd->n_tx) { -+ x[1].len = cmd->n_tx; -+ x[1].tx_buf = cmd->tx_buf; -+ x[1].tx_nbits = cmd->tx_nbits; -+ spi_message_add_tail(&x[1], &message); -+ } -+ -+ /* Data to be received */ -+ if (cmd->n_rx) { -+ x[1].len = cmd->n_rx; -+ x[1].rx_buf = cmd->rx_buf; -+ x[1].rx_nbits = cmd->rx_nbits; -+ spi_message_add_tail(&x[1], &message); -+ } -+ -+ return spi_sync(spi, &message); -+} -+ -+static int spi_nand_device_reset(struct spi_nand *snand) -+{ -+ struct spi_nand_device *snand_dev = snand->priv; -+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; -+ -+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); -+ cmd->n_cmd = 1; -+ cmd->cmd[0] = SPI_NAND_RESET; -+ -+ dev_dbg(snand->dev, "%s\n", __func__); -+ -+ return spi_nand_send_command(snand_dev->spi, cmd); -+} -+ -+static int spi_nand_device_read_reg(struct spi_nand *snand, u8 opcode, u8 *buf) -+{ -+ struct spi_nand_device *snand_dev = snand->priv; -+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; -+ -+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); -+ cmd->n_cmd = 2; -+ cmd->cmd[0] = SPI_NAND_GET_FEATURE; -+ cmd->cmd[1] = opcode; -+ cmd->n_rx = 1; -+ cmd->rx_buf = buf; -+ -+ dev_dbg(snand->dev, "%s: reg 0%x\n", __func__, opcode); -+ -+ return spi_nand_send_command(snand_dev->spi, cmd); -+} -+ -+static int spi_nand_device_write_reg(struct spi_nand *snand, u8 opcode, u8 *buf) -+{ -+ struct spi_nand_device *snand_dev = snand->priv; -+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; -+ -+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); -+ cmd->n_cmd = 2; -+ cmd->cmd[0] = SPI_NAND_SET_FEATURE; -+ cmd->cmd[1] = opcode; -+ cmd->n_tx = 1; -+ cmd->tx_buf = buf; -+ -+ dev_dbg(snand->dev, "%s: reg 0%x\n", __func__, opcode); -+ -+ return spi_nand_send_command(snand_dev->spi, cmd); -+} -+ -+static int spi_nand_device_write_enable(struct spi_nand *snand) -+{ -+ struct spi_nand_device *snand_dev = snand->priv; -+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; -+ -+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); -+ cmd->n_cmd = 1; -+ cmd->cmd[0] = SPI_NAND_WRITE_ENABLE; -+ -+ dev_dbg(snand->dev, "%s\n", __func__); -+ -+ return spi_nand_send_command(snand_dev->spi, cmd); -+} -+ -+static int spi_nand_device_write_disable(struct spi_nand *snand) -+{ -+ struct spi_nand_device *snand_dev = snand->priv; -+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; -+ -+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); -+ cmd->n_cmd = 1; -+ cmd->cmd[0] = SPI_NAND_WRITE_DISABLE; -+ -+ dev_dbg(snand->dev, "%s\n", __func__); -+ -+ return spi_nand_send_command(snand_dev->spi, cmd); -+} -+ -+static int spi_nand_device_write_page(struct spi_nand *snand, -+ unsigned int page_addr) -+{ -+ struct spi_nand_device *snand_dev = snand->priv; -+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; -+ -+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); -+ cmd->n_cmd = 4; -+ cmd->cmd[0] = SPI_NAND_PROGRAM_EXEC; -+ cmd->cmd[1] = (u8)((page_addr & 0xff0000) >> 16); -+ cmd->cmd[2] = (u8)((page_addr & 0xff00) >> 8); -+ cmd->cmd[3] = (u8)(page_addr & 0xff); -+ -+ dev_dbg(snand->dev, "%s: page 0x%x\n", __func__, page_addr); -+ -+ return spi_nand_send_command(snand_dev->spi, cmd); -+} -+ -+static int spi_nand_device_store_cache(struct spi_nand *snand, -+ unsigned int page_offset, size_t length, -+ u8 *write_buf) -+{ -+ struct spi_nand_device *snand_dev = snand->priv; -+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; -+ struct spi_device *spi = snand_dev->spi; -+ -+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); -+ cmd->n_cmd = 3; -+ cmd->cmd[0] = spi->mode & SPI_TX_QUAD ? SPI_NAND_PROGRAM_LOAD4 : -+ SPI_NAND_PROGRAM_LOAD; -+ cmd->cmd[1] = (u8)((page_offset & 0xff00) >> 8); -+ cmd->cmd[2] = (u8)(page_offset & 0xff); -+ cmd->n_tx = length; -+ cmd->tx_buf = write_buf; -+ cmd->tx_nbits = spi->mode & SPI_TX_QUAD ? 4 : 1; -+ -+ dev_dbg(snand->dev, "%s: offset 0x%x\n", __func__, page_offset); -+ -+ return spi_nand_send_command(snand_dev->spi, cmd); -+} -+ -+static int spi_nand_device_load_page(struct spi_nand *snand, -+ unsigned int page_addr) -+{ -+ struct spi_nand_device *snand_dev = snand->priv; -+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; -+ -+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); -+ cmd->n_cmd = 4; -+ cmd->cmd[0] = SPI_NAND_PAGE_READ; -+ cmd->cmd[1] = (u8)((page_addr & 0xff0000) >> 16); -+ cmd->cmd[2] = (u8)((page_addr & 0xff00) >> 8); -+ cmd->cmd[3] = (u8)(page_addr & 0xff); -+ -+ dev_dbg(snand->dev, "%s: page 0x%x\n", __func__, page_addr); -+ -+ return spi_nand_send_command(snand_dev->spi, cmd); -+} -+ -+static int spi_nand_device_read_cache(struct spi_nand *snand, -+ unsigned int page_offset, size_t length, -+ u8 *read_buf) -+{ -+ struct spi_nand_device *snand_dev = snand->priv; -+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; -+ struct spi_device *spi = snand_dev->spi; -+ -+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); -+ if ((spi->mode & SPI_RX_DUAL) || (spi->mode & SPI_RX_QUAD)) -+ cmd->n_cmd = 5; -+ else -+ cmd->n_cmd = 4; -+ cmd->cmd[0] = (spi->mode & SPI_RX_QUAD) ? SPI_NAND_READ_CACHE_X4 : -+ ((spi->mode & SPI_RX_DUAL) ? SPI_NAND_READ_CACHE_X2 : -+ SPI_NAND_READ_CACHE); -+ cmd->cmd[1] = 0; /* dummy byte */ -+ cmd->cmd[2] = (u8)((page_offset & 0xff00) >> 8); -+ cmd->cmd[3] = (u8)(page_offset & 0xff); -+ cmd->cmd[4] = 0; /* dummy byte */ -+ cmd->n_rx = length; -+ cmd->rx_buf = read_buf; -+ cmd->rx_nbits = (spi->mode & SPI_RX_QUAD) ? 4 : -+ ((spi->mode & SPI_RX_DUAL) ? 2 : 1); -+ -+ dev_dbg(snand->dev, "%s: offset 0x%x\n", __func__, page_offset); -+ -+ return spi_nand_send_command(snand_dev->spi, cmd); -+} -+ -+static int spi_nand_device_block_erase(struct spi_nand *snand, -+ unsigned int page_addr) -+{ -+ struct spi_nand_device *snand_dev = snand->priv; -+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; -+ -+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); -+ cmd->n_cmd = 4; -+ cmd->cmd[0] = SPI_NAND_BLOCK_ERASE; -+ cmd->cmd[1] = (u8)((page_addr & 0xff0000) >> 16); -+ cmd->cmd[2] = (u8)((page_addr & 0xff00) >> 8); -+ cmd->cmd[3] = (u8)(page_addr & 0xff); -+ -+ dev_dbg(snand->dev, "%s: block 0x%x\n", __func__, page_addr); -+ -+ return spi_nand_send_command(snand_dev->spi, cmd); -+} -+ -+static int spi_nand_gd5f_read_id(struct spi_nand *snand, u8 *buf) -+{ -+ struct spi_nand_device *snand_dev = snand->priv; -+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd; -+ -+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd)); -+ cmd->n_cmd = 1; -+ cmd->cmd[0] = SPI_NAND_READ_ID; -+ cmd->n_rx = SPI_NAND_GD5F_READID_LEN; -+ cmd->rx_buf = buf; -+ -+ dev_dbg(snand->dev, "%s\n", __func__); -+ -+ return spi_nand_send_command(snand_dev->spi, cmd); -+} -+ -+static void spi_nand_gd5f_ecc_status(unsigned int status, -+ unsigned int *corrected, -+ unsigned int *ecc_error) -+{ -+ unsigned int ecc_status = (status >> SPI_NAND_GD5F_ECC_SHIFT) & -+ SPI_NAND_GD5F_ECC_MASK; -+ -+ *ecc_error = (ecc_status == SPI_NAND_GD5F_ECC_UNCORR) ? 1 : 0; -+ if (*ecc_error == 0) -+ *corrected = (ecc_status > 1) ? (2 + ecc_status) : 0; -+} -+ -+static int spi_nand_device_probe(struct spi_device *spi) -+{ -+ enum spi_nand_device_variant variant; -+ struct spi_nand_device *priv; -+ struct spi_nand *snand; -+ int ret; -+ -+ priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ snand = &priv->spi_nand; -+ -+ snand->read_cache = spi_nand_device_read_cache; -+ snand->load_page = spi_nand_device_load_page; -+ snand->store_cache = spi_nand_device_store_cache; -+ snand->write_page = spi_nand_device_write_page; -+ snand->write_reg = spi_nand_device_write_reg; -+ snand->read_reg = spi_nand_device_read_reg; -+ snand->block_erase = spi_nand_device_block_erase; -+ snand->reset = spi_nand_device_reset; -+ snand->write_enable = spi_nand_device_write_enable; -+ snand->write_disable = spi_nand_device_write_disable; -+ snand->dev = &spi->dev; -+ snand->priv = priv; -+ -+ /* This'll mean we won't need to specify any specific compatible string -+ * for a given device, and instead just support spi-nand. -+ */ -+ variant = spi_get_device_id(spi)->driver_data; -+ switch (variant) { -+ case SPI_NAND_GD5F: -+ snand->read_id = spi_nand_gd5f_read_id; -+ snand->get_ecc_status = spi_nand_gd5f_ecc_status; -+ snand->ooblayout = &spi_nand_gd5f_oob_256_ops; -+ break; -+ default: -+ dev_err(snand->dev, "unknown device\n"); -+ return -ENODEV; -+ } -+ -+ spi_set_drvdata(spi, snand); -+ priv->spi = spi; -+ -+ ret = spi_nand_register(snand, spi_nand_flash_ids); -+ if (ret) -+ return ret; -+ return 0; -+} -+ -+static int spi_nand_device_remove(struct spi_device *spi) -+{ -+ struct spi_nand *snand = spi_get_drvdata(spi); -+ -+ spi_nand_unregister(snand); -+ -+ return 0; -+} -+ -+const struct spi_device_id spi_nand_id_table[] = { -+ { "spi-nand", SPI_NAND_GENERIC }, -+ { "gd5f", SPI_NAND_GD5F }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(spi, spi_nand_id_table); -+ -+static struct spi_driver spi_nand_device_driver = { -+ .driver = { -+ .name = "spi_nand_device", -+ .owner = THIS_MODULE, -+ }, -+ .id_table = spi_nand_id_table, -+ .probe = spi_nand_device_probe, -+ .remove = spi_nand_device_remove, -+}; -+module_spi_driver(spi_nand_device_driver); -+ -+MODULE_AUTHOR("Ezequiel Garcia "); -+MODULE_DESCRIPTION("SPI NAND device support"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-add-nor-partition-name.patch b/target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-add-nor-partition-name.patch index 6af11eaa36..a8d021373b 100644 --- a/target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-add-nor-partition-name.patch +++ b/target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-add-nor-partition-name.patch @@ -10,7 +10,7 @@ Signed-off-by: Ian Pozella --- a/arch/mips/boot/dts/img/pistachio_marduk.dts +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts -@@ -90,6 +90,7 @@ +@@ -87,6 +87,7 @@ compatible = "spansion,s25fl016k", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; diff --git a/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-add-nand-device-support.patch b/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-add-nand-device-support.patch index bd03f08126..d95f1af94d 100644 --- a/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-add-nand-device-support.patch +++ b/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-add-nand-device-support.patch @@ -10,12 +10,12 @@ Signed-off-by: Abhimanyu Vishwakarma --- a/arch/mips/boot/dts/img/pistachio_marduk.dts +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts -@@ -92,6 +92,17 @@ +@@ -89,6 +89,17 @@ spi-max-frequency = <50000000>; linux,mtd-name = "spi-nor"; }; + flash@1 { -+ compatible = "gigadevice,gd5f"; ++ compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <50000000>; + nand-on-flash-bbt; From bdc7d9691d8d60364f40505d44346e5fa6374f66 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Wed, 12 Aug 2020 00:52:36 +0200 Subject: [PATCH 09/17] pistachio: Fix Null pointer access in pwm-img.c This fixes a crash when booting the board. Signed-off-by: Hauke Mehrtens --- ...img-Fix-null-pointer-access-in-probe.patch | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 target/linux/pistachio/patches-5.4/150-pwm-img-Fix-null-pointer-access-in-probe.patch diff --git a/target/linux/pistachio/patches-5.4/150-pwm-img-Fix-null-pointer-access-in-probe.patch b/target/linux/pistachio/patches-5.4/150-pwm-img-Fix-null-pointer-access-in-probe.patch new file mode 100644 index 0000000000..d5c573c75c --- /dev/null +++ b/target/linux/pistachio/patches-5.4/150-pwm-img-Fix-null-pointer-access-in-probe.patch @@ -0,0 +1,42 @@ +From 502396fe598126ffd91f962d53a507aa6c7276fc Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sat, 15 Aug 2020 16:37:43 +0200 +Subject: [PATCH v2] pwm: img: Fix null pointer access in probe + +dev_get_drvdata() is called in img_pwm_runtime_resume() before the +driver data is set. +When pm_runtime_enabled() returns false in img_pwm_probe() it calls +img_pwm_runtime_resume() which results in a null pointer access. + +This patch fixes the problem by setting the driver data earlier in the +img_pwm_probe() function. + +This crash was seen when booting the Imagination Technologies Creator +Ci40 (Marduk) with kernel 5.4 in OpenWrt. + +Fixes: e690ae526216 ("pwm: img: Add runtime PM") +Signed-off-by: Hauke Mehrtens +Acked-by: Lee Jones +--- + drivers/pwm/pwm-img.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/pwm/pwm-img.c ++++ b/drivers/pwm/pwm-img.c +@@ -277,6 +277,8 @@ static int img_pwm_probe(struct platform + return PTR_ERR(pwm->pwm_clk); + } + ++ platform_set_drvdata(pdev, pwm); ++ + pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(&pdev->dev); +@@ -313,7 +315,6 @@ static int img_pwm_probe(struct platform + goto err_suspend; + } + +- platform_set_drvdata(pdev, pwm); + return 0; + + err_suspend: From d2b63647cc7a9ee0cfbcd08123e9fb60c32d7a6c Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Thu, 13 Aug 2020 00:45:12 +0200 Subject: [PATCH 10/17] pistachio: Add mtd device name from dts Parse the "linux,mtd-name" property also for SPI NAND flashes. Signed-off-by: Hauke Mehrtens --- ...or-support-mtd-name-from-device-tree.patch | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/linux/pistachio/patches-5.4/401-mtd-nor-support-mtd-name-from-device-tree.patch b/target/linux/pistachio/patches-5.4/401-mtd-nor-support-mtd-name-from-device-tree.patch index 5d2f9284ab..4b600d7e8a 100644 --- a/target/linux/pistachio/patches-5.4/401-mtd-nor-support-mtd-name-from-device-tree.patch +++ b/target/linux/pistachio/patches-5.4/401-mtd-nor-support-mtd-name-from-device-tree.patch @@ -32,3 +32,23 @@ Signed-off-by: Abhimanyu Vishwakarma mtd->name = dev_name(dev); mtd->priv = nor; mtd->type = MTD_NORFLASH; +--- a/drivers/mtd/mtdcore.c ++++ b/drivers/mtd/mtdcore.c +@@ -778,6 +778,17 @@ out_error: + */ + static void mtd_set_dev_defaults(struct mtd_info *mtd) + { ++#ifdef CONFIG_MTD_OF_PARTS ++ const char __maybe_unused *of_mtd_name = NULL; ++ struct device_node *np; ++ ++ np = mtd_get_of_node(mtd); ++ if (np && !mtd->name) { ++ of_property_read_string(np, "linux,mtd-name", &of_mtd_name); ++ if (of_mtd_name) ++ mtd->name = of_mtd_name; ++ } else ++#endif + if (mtd->dev.parent) { + if (!mtd->owner && mtd->dev.parent->driver) + mtd->owner = mtd->dev.parent->driver->owner; From 0d81afe3dfc4901831765c358151751da9f7178e Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 15 Aug 2020 16:42:29 +0200 Subject: [PATCH 11/17] pistachio: Add extra devices to dts file This adds some extra devices to the DTS file. Signed-off-by: Hauke Mehrtens --- ...PS-DTS-img-marduk-Add-SPI-NAND-flash.patch | 30 +++++++ ...mg-marduk-Add-Cascoda-CA8210-6LoWPAN.patch | 43 ++++++++++ ...S-img-marduk-add-nand-device-support.patch | 30 ------- ...-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch | 81 +++++++++++++++++++ ...S-DTS-img-marduk-Add-partition-name.patch} | 17 ++-- 5 files changed, 166 insertions(+), 35 deletions(-) create mode 100644 target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-Add-SPI-NAND-flash.patch create mode 100644 target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-Add-Cascoda-CA8210-6LoWPAN.patch delete mode 100644 target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-add-nand-device-support.patch create mode 100644 target/linux/pistachio/patches-5.4/903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch rename target/linux/pistachio/patches-5.4/{901-MIPS-DTS-img-marduk-add-nor-partition-name.patch => 904-MIPS-DTS-img-marduk-Add-partition-name.patch} (51%) diff --git a/target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-Add-SPI-NAND-flash.patch b/target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-Add-SPI-NAND-flash.patch new file mode 100644 index 0000000000..cd97e38e00 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-Add-SPI-NAND-flash.patch @@ -0,0 +1,30 @@ +From 0023c706f7e0f0f02bd48a63a2f3c04c839532ae Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sat, 15 Aug 2020 16:04:53 +0200 +Subject: [PATCH 901/904] MIPS: DTS: img: marduk: Add SPI NAND flash + +Add Gigadevice GD5F4GQ4UCYIGT SPI NAND flash to the device tree. + +The NAND flash chip is connected with quad SPI, but reading currently +fails in quad SPI mode. + +Signed-off-by: Hauke Mehrtens +--- + arch/mips/boot/dts/img/pistachio_marduk.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -88,6 +88,12 @@ + reg = <0>; + spi-max-frequency = <50000000>; + }; ++ ++ flash@1 { ++ compatible = "spi-nand"; ++ reg = <1>; ++ spi-max-frequency = <50000000>; ++ }; + }; + + &uart0 { diff --git a/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-Add-Cascoda-CA8210-6LoWPAN.patch b/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-Add-Cascoda-CA8210-6LoWPAN.patch new file mode 100644 index 0000000000..af1882e287 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-Add-Cascoda-CA8210-6LoWPAN.patch @@ -0,0 +1,43 @@ +From b7700154d75e8d7c9a2022f09c2d5430137606fa Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sat, 15 Aug 2020 16:05:25 +0200 +Subject: [PATCH 902/904] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN + +Add Cascoda CA8210 6LoWPAN controller to device tree. + +Signed-off-by: Hauke Mehrtens +--- + arch/mips/boot/dts/img/pistachio_marduk.dts | 22 +++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -75,6 +75,28 @@ + VDD-supply = <&internal_dac_supply>; + }; + ++&spfi0 { ++ status = "okay"; ++ pinctrl-0 = <&spim0_pins>, <&spim0_cs0_alt_pin>, <&spim0_cs2_alt_pin>, <&spim0_cs3_alt_pin>, <&spim0_cs4_alt_pin>; ++ pinctrl-names = "default"; ++ ++ cs-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>, <&gpio0 2 GPIO_ACTIVE_HIGH>, ++ <&gpio1 12 GPIO_ACTIVE_HIGH>, <&gpio1 13 GPIO_ACTIVE_HIGH>; ++ ++ ca8210: ca8210@0 { ++ status = "okay"; ++ compatible = "cascoda,ca8210"; ++ reg = <0>; ++ spi-max-frequency = <4000000>; ++ spi-cpol; ++ reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; ++ irq-gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; ++ extclock-enable; ++ extclock-freq = <16000000>; ++ extclock-gpio = <2>; ++ }; ++}; ++ + &spfi1 { + status = "okay"; + diff --git a/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-add-nand-device-support.patch b/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-add-nand-device-support.patch deleted file mode 100644 index d95f1af94d..0000000000 --- a/target/linux/pistachio/patches-5.4/902-MIPS-DTS-img-marduk-add-nand-device-support.patch +++ /dev/null @@ -1,30 +0,0 @@ -From c13cfb3a49cf1578bb85f19a7066f262503a39ba Mon Sep 17 00:00:00 2001 -From: Abhimanyu Vishwakarma -Date: Thu, 24 Nov 2016 19:26:46 +0530 -Subject: MIPS: DTS: img: marduk: add nand device support - -Signed-off-by: Abhimanyu Vishwakarma ---- - arch/mips/boot/dts/img/pistachio_marduk.dts | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/arch/mips/boot/dts/img/pistachio_marduk.dts -+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts -@@ -89,6 +89,17 @@ - spi-max-frequency = <50000000>; - linux,mtd-name = "spi-nor"; - }; -+ flash@1 { -+ compatible = "spi-nand"; -+ reg = <1>; -+ spi-max-frequency = <50000000>; -+ nand-on-flash-bbt; -+ spi-rx-bus-width = <2>; -+ spi-tx-bus-width = <4>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ linux,mtd-name = "spi-nand"; -+ }; - }; - - &uart0 { diff --git a/target/linux/pistachio/patches-5.4/903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch b/target/linux/pistachio/patches-5.4/903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch new file mode 100644 index 0000000000..0814658998 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch @@ -0,0 +1,81 @@ +From ad4eba0c36ce8af6ab9ea1bc163e4c1ac7c271c3 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sat, 15 Aug 2020 16:09:02 +0200 +Subject: [PATCH 903/904] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW + +Add NXP SC16IS752IPW SPI-UART controller to device tree. + +This controller drives 2 UARTs and 7 LEDs on the board. + +Signed-off-by: Hauke Mehrtens +--- + arch/mips/boot/dts/img/pistachio_marduk.dts | 51 +++++++++++++++++++++ + 1 file changed, 51 insertions(+) + +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -46,6 +46,46 @@ + regulator-max-microvolt = <1800000>; + }; + ++ /* EXT clock from ca8210 is fed to sc16is752 */ ++ ca8210_ext_clk: ca8210-ext-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <16000000>; ++ clock-output-names = "ca8210_ext_clock"; ++ }; ++ ++ gpioleds { ++ compatible = "gpio-leds"; ++ user1 { ++ label = "marduk:red:user1"; ++ gpios = <&sc16is752 0 GPIO_ACTIVE_LOW>; ++ }; ++ user2 { ++ label = "marduk:red:user2"; ++ gpios = <&sc16is752 1 GPIO_ACTIVE_LOW>; ++ }; ++ user3 { ++ label = "marduk:red:user3"; ++ gpios = <&sc16is752 2 GPIO_ACTIVE_LOW>; ++ }; ++ user4 { ++ label = "marduk:red:user4"; ++ gpios = <&sc16is752 3 GPIO_ACTIVE_LOW>; ++ }; ++ user5 { ++ label = "marduk:red:user5"; ++ gpios = <&sc16is752 4 GPIO_ACTIVE_LOW>; ++ }; ++ user6 { ++ label = "marduk:red:user6"; ++ gpios = <&sc16is752 5 GPIO_ACTIVE_LOW>; ++ }; ++ user7 { ++ label = "marduk:red:user7"; ++ gpios = <&sc16is752 6 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ + leds { + compatible = "pwm-leds"; + heartbeat { +@@ -95,6 +135,17 @@ + extclock-freq = <16000000>; + extclock-gpio = <2>; + }; ++ ++ sc16is752: sc16is752@1 { ++ compatible = "nxp,sc16is752"; ++ reg = <1>; ++ clocks = <&ca8210_ext_clk>; ++ spi-max-frequency = <4000000>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; + }; + + &spfi1 { diff --git a/target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-add-nor-partition-name.patch b/target/linux/pistachio/patches-5.4/904-MIPS-DTS-img-marduk-Add-partition-name.patch similarity index 51% rename from target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-add-nor-partition-name.patch rename to target/linux/pistachio/patches-5.4/904-MIPS-DTS-img-marduk-Add-partition-name.patch index a8d021373b..ce41c67461 100644 --- a/target/linux/pistachio/patches-5.4/901-MIPS-DTS-img-marduk-add-nor-partition-name.patch +++ b/target/linux/pistachio/patches-5.4/904-MIPS-DTS-img-marduk-Add-partition-name.patch @@ -1,20 +1,27 @@ -From b5f49b448cd3c7ab930f1a53c88f739a86071df8 Mon Sep 17 00:00:00 2001 +From ff0e950b605047bf50d470023e0fb2fc2003a0f0 Mon Sep 17 00:00:00 2001 From: Ian Pozella Date: Mon, 20 Feb 2017 10:38:07 +0000 -Subject: MIPS: DTS: img: marduk: add nor partition name +Subject: [PATCH 904/904] MIPS: DTS: img: marduk: Add partition name Signed-off-by: Ian Pozella --- - arch/mips/boot/dts/img/pistachio_marduk.dts | 1 + - 1 file changed, 1 insertion(+) + arch/mips/boot/dts/img/pistachio_marduk.dts | 2 ++ + 1 file changed, 2 insertions(+) --- a/arch/mips/boot/dts/img/pistachio_marduk.dts +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts -@@ -87,6 +87,7 @@ +@@ -160,12 +160,14 @@ compatible = "spansion,s25fl016k", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; + linux,mtd-name = "spi-nor"; }; + + flash@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <50000000>; ++ linux,mtd-name = "spi-nand"; + }; }; From 3f07a06b3b1c88d41ac08b48ba83daeb9b1b65a3 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 15 Aug 2020 16:45:16 +0200 Subject: [PATCH 12/17] pistachio: Add SC16IS7XX device driver This device is used to control extra UARTs and LEDs on the board. Signed-off-by: Hauke Mehrtens --- target/linux/pistachio/config-5.4 | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/linux/pistachio/config-5.4 b/target/linux/pistachio/config-5.4 index c4637c1372..d1e1acaead 100644 --- a/target/linux/pistachio/config-5.4 +++ b/target/linux/pistachio/config-5.4 @@ -180,6 +180,7 @@ CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y CONFIG_JBD2=y +CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y CONFIG_LIBFDT=y CONFIG_LKDTM=y @@ -295,6 +296,7 @@ CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_RCU_STALL_COMMON=y CONFIG_REGMAP=y CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y @@ -310,6 +312,10 @@ CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SC16IS7XX=y +CONFIG_SERIAL_SC16IS7XX_CORE=y +# CONFIG_SERIAL_SC16IS7XX_I2C is not set +CONFIG_SERIAL_SC16IS7XX_SPI=y CONFIG_SGL_ALLOC=y CONFIG_SG_POOL=y CONFIG_SMP=y From 5fa0e32698056d474f8661e0f76b783a95630f67 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Fri, 21 Aug 2020 11:04:57 +0200 Subject: [PATCH 13/17] pistachio: Add kmod-ca8210 wpan-tools by default A ca8210 chip is soldered onto the board, add the driver by default. Signed-off-by: Hauke Mehrtens --- target/linux/pistachio/image/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/pistachio/image/Makefile b/target/linux/pistachio/image/Makefile index 61f5c55237..564bda1acb 100644 --- a/target/linux/pistachio/image/Makefile +++ b/target/linux/pistachio/image/Makefile @@ -32,7 +32,7 @@ define Device/marduk DEVICE_DTS := img/pistachio_marduk BLOCKSIZE := 256KiB PAGESIZE := 4KiB - DEVICE_PACKAGES := kmod-tpm-i2c-infineon + DEVICE_PACKAGES := kmod-tpm-i2c-infineon kmod-ca8210 wpan-tools endef TARGET_DEVICES += marduk From 2549d1dd77e7bb51756910c037f4459f9ddc3948 Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Thu, 20 Aug 2020 22:18:40 +0200 Subject: [PATCH 14/17] pistachio: use vendor_model scheme for device/image name This uses the vendor_model scheme for the device/image name in order to make this consistent to most other targets. Signed-off-by: Adrian Schmutzler --- target/linux/pistachio/image/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/pistachio/image/Makefile b/target/linux/pistachio/image/Makefile index 564bda1acb..5d2e42f139 100644 --- a/target/linux/pistachio/image/Makefile +++ b/target/linux/pistachio/image/Makefile @@ -23,7 +23,7 @@ define Device/Default IMAGE/sysupgrade.tar := sysupgrade-tar endef -define Device/marduk +define Device/img_creator-ci40 DEVICE_VENDOR := Imagination Technologies DEVICE_MODEL := Creator Ci40 (VL-62899) DEVICE_ALT0_VENDOR := Imagination Technologies @@ -35,7 +35,7 @@ define Device/marduk DEVICE_PACKAGES := kmod-tpm-i2c-infineon kmod-ca8210 wpan-tools endef -TARGET_DEVICES += marduk +TARGET_DEVICES += img_creator-ci40 $(eval $(call BuildImage)) From 373d4cc3605196c93cee18cfcfbd70f80c87cf8c Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Thu, 20 Aug 2020 22:18:41 +0200 Subject: [PATCH 15/17] pistachio: use generic diag.sh Remove local diag.sh in favor of generic one and add the required led-* aliases to DTS. Signed-off-by: Adrian Schmutzler --- target/linux/pistachio/base-files/etc/diag.sh | 30 ------------------- ...-MIPS-DTS-img-marduk-Add-led-aliases.patch | 27 +++++++++++++++++ 2 files changed, 27 insertions(+), 30 deletions(-) delete mode 100755 target/linux/pistachio/base-files/etc/diag.sh create mode 100644 target/linux/pistachio/patches-5.4/905-MIPS-DTS-img-marduk-Add-led-aliases.patch diff --git a/target/linux/pistachio/base-files/etc/diag.sh b/target/linux/pistachio/base-files/etc/diag.sh deleted file mode 100755 index ed69d43385..0000000000 --- a/target/linux/pistachio/base-files/etc/diag.sh +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/sh -# -# Copyright (C) 2017 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -. /lib/functions/leds.sh - -status_led="marduk:red:heartbeat" - -set_state() { - - case "$1" in - preinit) - status_led_blink_preinit - ;; - failsafe) - status_led_blink_failsafe - ;; - upgrade | \ - preinit_regular) - status_led_blink_preinit_regular - ;; - done) - status_led_on - ;; - esac -} diff --git a/target/linux/pistachio/patches-5.4/905-MIPS-DTS-img-marduk-Add-led-aliases.patch b/target/linux/pistachio/patches-5.4/905-MIPS-DTS-img-marduk-Add-led-aliases.patch new file mode 100644 index 0000000000..c6cf5acbb8 --- /dev/null +++ b/target/linux/pistachio/patches-5.4/905-MIPS-DTS-img-marduk-Add-led-aliases.patch @@ -0,0 +1,27 @@ +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -19,6 +19,11 @@ + ethernet0 = &enet; + spi0 = &spfi0; + spi1 = &spfi1; ++ ++ led-boot = &led_heartbeat; ++ led-failsafe = &led_heartbeat; ++ led-running = &led_heartbeat; ++ led-upgrade = &led_heartbeat; + }; + + chosen { +@@ -88,11 +93,10 @@ + + leds { + compatible = "pwm-leds"; +- heartbeat { ++ led_heartbeat: heartbeat { + label = "marduk:red:heartbeat"; + pwms = <&pwm 3 300000>; + max-brightness = <255>; +- linux,default-trigger = "heartbeat"; + }; + }; + From 734a8c46e7037075d712e3d3844467672d0f91c9 Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Fri, 14 Aug 2020 12:01:31 +0200 Subject: [PATCH 16/17] ramips: remove legacy ethernet driver components for mt7621 The mt7621 subtarget has been switched to DSA quite a while ago and seems to run sufficiently fine. Build with older kernels than 5.4 has been disabled directly during the kernel bump, so our local ethernet driver is unused in master since then. Therefore, let's remove the mt7621-specific parts of "our" ethernet driver, so we don't have to maintain them and it's obvious to everybody that they are not used anymore. This also drops the offloading components as this was specifically implemented to depend on mt7621. Signed-off-by: Adrian Schmutzler --- .../files/drivers/net/ethernet/ralink/Kconfig | 16 +- .../drivers/net/ethernet/ralink/Makefile | 4 - .../drivers/net/ethernet/ralink/gsw_mt7621.c | 275 --------- .../drivers/net/ethernet/ralink/mtk_debugfs.c | 115 ---- .../drivers/net/ethernet/ralink/mtk_eth_soc.c | 42 +- .../drivers/net/ethernet/ralink/mtk_offload.c | 540 ------------------ .../drivers/net/ethernet/ralink/mtk_offload.h | 260 --------- .../drivers/net/ethernet/ralink/soc_mt7621.c | 187 ------ 8 files changed, 6 insertions(+), 1433 deletions(-) delete mode 100644 target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7621.c delete mode 100644 target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_debugfs.c delete mode 100644 target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_offload.c delete mode 100644 target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_offload.h delete mode 100644 target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7621.c diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/Kconfig b/target/linux/ramips/files/drivers/net/ethernet/ralink/Kconfig index 51cace5333..26e5e6d73e 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/Kconfig +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/Kconfig @@ -27,23 +27,15 @@ config NET_RALINK_MT7620 bool "MT7620" depends on MIPS && SOC_MT7620 -config NET_RALINK_MT7621 - bool "MT7621" - depends on MIPS && SOC_MT7621 - endchoice -config NET_RALINK_OFFLOAD - def_bool NET_RALINK_SOC - depends on NET_RALINK_MT7621 - config NET_RALINK_HW_QOS def_bool NET_RALINK_SOC depends on NET_RALINK_MT7623 config NET_RALINK_MDIO def_bool NET_RALINK_SOC - depends on (NET_RALINK_RT2880 || NET_RALINK_RT3883 || NET_RALINK_MT7620 || NET_RALINK_MT7621) + depends on (NET_RALINK_RT2880 || NET_RALINK_RT3883 || NET_RALINK_MT7620) select PHYLIB config NET_RALINK_MDIO_RT2880 @@ -53,7 +45,7 @@ config NET_RALINK_MDIO_RT2880 config NET_RALINK_MDIO_MT7620 def_bool NET_RALINK_SOC - depends on (NET_RALINK_MT7620 || NET_RALINK_MT7621) + depends on NET_RALINK_MT7620 select NET_RALINK_MDIO config NET_RALINK_ESW_RT3050 @@ -63,8 +55,4 @@ config NET_RALINK_ESW_RT3050 config NET_RALINK_GSW_MT7620 def_tristate NET_RALINK_SOC depends on NET_RALINK_MT7620 - -config NET_RALINK_GSW_MT7621 - def_tristate NET_RALINK_SOC - depends on NET_RALINK_MT7621 endif diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/Makefile b/target/linux/ramips/files/drivers/net/ethernet/ralink/Makefile index eba21643b2..79d2dbfef9 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/Makefile +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/Makefile @@ -8,15 +8,11 @@ ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o ralink-eth-$(CONFIG_NET_RALINK_MDIO_MT7620) += mdio_mt7620.o -ralink-eth-$(CONFIG_NET_RALINK_OFFLOAD) += mtk_offload.o mtk_debugfs.o - ralink-eth-$(CONFIG_NET_RALINK_RT2880) += soc_rt2880.o ralink-eth-$(CONFIG_NET_RALINK_RT3050) += soc_rt3050.o ralink-eth-$(CONFIG_NET_RALINK_RT3883) += soc_rt3883.o ralink-eth-$(CONFIG_NET_RALINK_MT7620) += soc_mt7620.o -ralink-eth-$(CONFIG_NET_RALINK_MT7621) += soc_mt7621.o obj-$(CONFIG_NET_RALINK_ESW_RT3050) += esw_rt3050.o obj-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620.o mt7530.o -obj-$(CONFIG_NET_RALINK_GSW_MT7621) += gsw_mt7621.o mt7530.o obj-$(CONFIG_NET_RALINK_SOC) += ralink-eth.o diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7621.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7621.c deleted file mode 100644 index 232bcd8cf4..0000000000 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7621.c +++ /dev/null @@ -1,275 +0,0 @@ -/* This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Copyright (C) 2009-2015 John Crispin - * Copyright (C) 2009-2015 Felix Fietkau - * Copyright (C) 2013-2015 Michael Lee - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include "mtk_eth_soc.h" -#include "gsw_mt7620.h" - -void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg) -{ - iowrite32(val, gsw->base + reg); -} - -u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg) -{ - return ioread32(gsw->base + reg); -} - -static irqreturn_t gsw_interrupt_mt7621(int irq, void *_priv) -{ - struct fe_priv *priv = (struct fe_priv *)_priv; - struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv; - u32 reg, i; - - reg = mt7530_mdio_r32(gsw, 0x700c); - mt7530_mdio_w32(gsw, 0x700c, reg); - - for (i = 0; i < 5; i++) - if (reg & BIT(i)) { - unsigned int link; - - link = mt7530_mdio_r32(gsw, - 0x3008 + (i * 0x100)) & 0x1; - - if (link != priv->link[i]) { - priv->link[i] = link; - if (link) - netdev_info(priv->netdev, - "port %d link up\n", i); - else - netdev_info(priv->netdev, - "port %d link down\n", i); - } - } - - mt7620_handle_carrier(priv); - - return IRQ_HANDLED; -} - -static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np) -{ - u32 i; - u32 val; - - /* wardware reset the switch */ - fe_reset(RST_CTRL_MCM); - mdelay(10); - - /* reduce RGMII2 PAD driving strength */ - rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO); - - /* gpio mux - RGMII1=Normal mode */ - rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE); - - /* set GMAC1 RGMII mode */ - rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1); - - /* enable MDIO to control MT7530 */ - rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE); - - /* turn off all PHYs */ - for (i = 0; i <= 4; i++) { - val = _mt7620_mii_read(gsw, i, 0x0); - val |= BIT(11); - _mt7620_mii_write(gsw, i, 0x0, val); - } - - /* reset the switch */ - mt7530_mdio_w32(gsw, 0x7000, 0x3); - usleep_range(10, 20); - - /* (GE1, Force 1000M/FD, FC OFF, MAX_RX_LENGTH 1536) */ - mtk_switch_w32(gsw, 0x2305e30b, GSW_REG_MAC_P0_MCR); - mt7530_mdio_w32(gsw, 0x3600, 0x5e30b); - - /* (GE2, Link down) */ - mtk_switch_w32(gsw, 0x8000, GSW_REG_MAC_P1_MCR); - - /* Set switch max RX frame length to 2k */ - mt7530_mdio_w32(gsw, GSW_REG_GMACCR, 0x3F0B); - - /* Enable Port 6, P5 as GMAC5, P5 disable */ - val = mt7530_mdio_r32(gsw, 0x7804); - val &= ~BIT(8); - val |= BIT(6) | BIT(13) | BIT(16); - mt7530_mdio_w32(gsw, 0x7804, val); - - val = rt_sysc_r32(0x10); - val = (val >> 6) & 0x7; - if (val >= 6) { - /* 25Mhz Xtal - do nothing */ - } else if (val >= 3) { - /* 40Mhz */ - - /* disable MT7530 core clock */ - _mt7620_mii_write(gsw, 0, 13, 0x1f); - _mt7620_mii_write(gsw, 0, 14, 0x410); - _mt7620_mii_write(gsw, 0, 13, 0x401f); - _mt7620_mii_write(gsw, 0, 14, 0x0); - - /* disable MT7530 PLL */ - _mt7620_mii_write(gsw, 0, 13, 0x1f); - _mt7620_mii_write(gsw, 0, 14, 0x40d); - _mt7620_mii_write(gsw, 0, 13, 0x401f); - _mt7620_mii_write(gsw, 0, 14, 0x2020); - - /* for MT7530 core clock = 500Mhz */ - _mt7620_mii_write(gsw, 0, 13, 0x1f); - _mt7620_mii_write(gsw, 0, 14, 0x40e); - _mt7620_mii_write(gsw, 0, 13, 0x401f); - _mt7620_mii_write(gsw, 0, 14, 0x119); - - /* enable MT7530 PLL */ - _mt7620_mii_write(gsw, 0, 13, 0x1f); - _mt7620_mii_write(gsw, 0, 14, 0x40d); - _mt7620_mii_write(gsw, 0, 13, 0x401f); - _mt7620_mii_write(gsw, 0, 14, 0x2820); - - usleep_range(20, 40); - - /* enable MT7530 core clock */ - _mt7620_mii_write(gsw, 0, 13, 0x1f); - _mt7620_mii_write(gsw, 0, 14, 0x410); - _mt7620_mii_write(gsw, 0, 13, 0x401f); - } else { - /* 20Mhz Xtal - TODO */ - } - - /* RGMII */ - _mt7620_mii_write(gsw, 0, 14, 0x1); - - /* set MT7530 central align */ - val = mt7530_mdio_r32(gsw, 0x7830); - val &= ~BIT(0); - val |= BIT(1); - mt7530_mdio_w32(gsw, 0x7830, val); - val = mt7530_mdio_r32(gsw, 0x7a40); - val &= ~BIT(30); - mt7530_mdio_w32(gsw, 0x7a40, val); - mt7530_mdio_w32(gsw, 0x7a78, 0x855); - - /* delay setting for 10/1000M */ - mt7530_mdio_w32(gsw, 0x7b00, 0x102); - mt7530_mdio_w32(gsw, 0x7b04, 0x14); - - /* lower Tx Driving*/ - mt7530_mdio_w32(gsw, 0x7a54, 0x44); - mt7530_mdio_w32(gsw, 0x7a5c, 0x44); - mt7530_mdio_w32(gsw, 0x7a64, 0x44); - mt7530_mdio_w32(gsw, 0x7a6c, 0x44); - mt7530_mdio_w32(gsw, 0x7a74, 0x44); - mt7530_mdio_w32(gsw, 0x7a7c, 0x44); - - /* turn on all PHYs */ - for (i = 0; i <= 4; i++) { - val = _mt7620_mii_read(gsw, i, 0); - val &= ~BIT(11); - _mt7620_mii_write(gsw, i, 0, val); - } - - /* enable irq */ - mt7530_mdio_w32(gsw, 0x7008, 0x1f); - val = mt7530_mdio_r32(gsw, 0x7808); - val |= 3 << 16; - mt7530_mdio_w32(gsw, 0x7808, val); -} - -static const struct of_device_id mediatek_gsw_match[] = { - { .compatible = "mediatek,mt7621-gsw" }, - {}, -}; -MODULE_DEVICE_TABLE(of, mediatek_gsw_match); - -int mtk_gsw_init(struct fe_priv *priv) -{ - struct device_node *np = priv->switch_np; - struct platform_device *pdev = of_find_device_by_node(np); - struct mt7620_gsw *gsw; - - if (!pdev) - return -ENODEV; - - if (!of_device_is_compatible(np, mediatek_gsw_match->compatible)) - return -EINVAL; - - gsw = platform_get_drvdata(pdev); - priv->soc->swpriv = gsw; - - if (gsw->irq) { - request_irq(gsw->irq, gsw_interrupt_mt7621, 0, - "gsw", priv); - disable_irq(gsw->irq); - } - - mt7621_hw_init(gsw, np); - - if (gsw->irq) - enable_irq(gsw->irq); - - return 0; -} - -static int mt7621_gsw_probe(struct platform_device *pdev) -{ - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - struct mt7620_gsw *gsw; - - gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL); - if (!gsw) - return -ENOMEM; - - gsw->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(gsw->base)) - return PTR_ERR(gsw->base); - - gsw->dev = &pdev->dev; - gsw->irq = platform_get_irq(pdev, 0); - - platform_set_drvdata(pdev, gsw); - - return 0; -} - -static int mt7621_gsw_remove(struct platform_device *pdev) -{ - platform_set_drvdata(pdev, NULL); - - return 0; -} - -static struct platform_driver gsw_driver = { - .probe = mt7621_gsw_probe, - .remove = mt7621_gsw_remove, - .driver = { - .name = "mt7621-gsw", - .owner = THIS_MODULE, - .of_match_table = mediatek_gsw_match, - }, -}; - -module_platform_driver(gsw_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("John Crispin "); -MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7621 SoC"); -MODULE_VERSION(MTK_FE_DRV_VERSION); diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_debugfs.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_debugfs.c deleted file mode 100644 index 2938119e89..0000000000 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_debugfs.c +++ /dev/null @@ -1,115 +0,0 @@ -/* This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Copyright (C) 2014-2016 Sean Wang - * Copyright (C) 2016-2017 John Crispin - */ - -#include "mtk_offload.h" - -static const char *mtk_foe_entry_state_str[] = { - "INVALID", - "UNBIND", - "BIND", - "FIN" -}; - -static const char *mtk_foe_packet_type_str[] = { - "IPV4_HNAPT", - "IPV4_HNAT", - "IPV6_1T_ROUTE", - "IPV4_DSLITE", - "IPV6_3T_ROUTE", - "IPV6_5T_ROUTE", - "IPV6_6RD", -}; - -#define IPV4_HNAPT 0 -#define IPV4_HNAT 1 -#define IS_IPV4_HNAPT(x) (((x)->bfib1.pkt_type == IPV4_HNAPT) ? 1: 0) -struct mtk_eth *_eth; -#define es(entry) (mtk_foe_entry_state_str[entry->bfib1.state]) -//#define ei(entry, end) (MTK_PPE_TBL_SZ - (int)(end - entry)) -#define ei(entry, end) (MTK_PPE_ENTRY_CNT - (int)(end - entry)) -#define pt(entry) (mtk_foe_packet_type_str[entry->ipv4_hnapt.bfib1.pkt_type]) - -static int mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private) -{ - struct mtk_eth *eth = _eth; - struct mtk_foe_entry *entry, *end; - int i = 0; - - entry = eth->foe_table; - end = eth->foe_table + MTK_PPE_ENTRY_CNT; - - while (entry < end) { - if (IS_IPV4_HNAPT(entry)) { - __be32 saddr = htonl(entry->ipv4_hnapt.sip); - __be32 daddr = htonl(entry->ipv4_hnapt.dip); - __be32 nsaddr = htonl(entry->ipv4_hnapt.new_sip); - __be32 ndaddr = htonl(entry->ipv4_hnapt.new_dip); - unsigned char h_dest[ETH_ALEN]; - unsigned char h_source[ETH_ALEN]; - - *((u32*) h_source) = swab32(entry->ipv4_hnapt.smac_hi); - *((u16*) &h_source[4]) = swab16(entry->ipv4_hnapt.smac_lo); - *((u32*) h_dest) = swab32(entry->ipv4_hnapt.dmac_hi); - *((u16*) &h_dest[4]) = swab16(entry->ipv4_hnapt.dmac_lo); - seq_printf(m, - "(%x)0x%05x|state=%s|type=%s|" - "%pI4:%d->%pI4:%d=>%pI4:%d->%pI4:%d|%pM=>%pM|" - "etype=0x%04x|info1=0x%x|info2=0x%x|" - "vlan1=%d|vlan2=%d\n", - i, - ei(entry, end), es(entry), pt(entry), - &saddr, entry->ipv4_hnapt.sport, - &daddr, entry->ipv4_hnapt.dport, - &nsaddr, entry->ipv4_hnapt.new_sport, - &ndaddr, entry->ipv4_hnapt.new_dport, h_source, - h_dest, ntohs(entry->ipv4_hnapt.etype), - entry->ipv4_hnapt.info_blk1, - entry->ipv4_hnapt.info_blk2, - entry->ipv4_hnapt.vlan1, - entry->ipv4_hnapt.vlan2); - } else - seq_printf(m, "0x%05x state=%s\n", - ei(entry, end), es(entry)); - entry++; - i++; - } - - return 0; -} - -static int mtk_ppe_debugfs_foe_open(struct inode *inode, struct file *file) -{ - return single_open(file, mtk_ppe_debugfs_foe_show, file->private_data); -} - -static const struct file_operations mtk_ppe_debugfs_foe_fops = { - .open = mtk_ppe_debugfs_foe_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -int mtk_ppe_debugfs_init(struct mtk_eth *eth) -{ - struct dentry *root; - - _eth = eth; - - root = debugfs_create_dir("mtk_ppe", NULL); - if (!root) - return -ENOMEM; - - debugfs_create_file("all_entry", S_IRUGO, root, eth, &mtk_ppe_debugfs_foe_fops); - - return 0; -} diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c index 358a8fc16d..62c186dbd6 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c @@ -960,18 +960,11 @@ static int fe_poll_rx(struct napi_struct *napi, int budget, __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), RX_DMA_VID(trxd.rxd3)); -#ifdef CONFIG_NET_RALINK_OFFLOAD - if (mtk_offload_check_rx(priv, skb, trxd.rxd4) == 0) { -#endif - stats->rx_packets++; - stats->rx_bytes += pktlen; + stats->rx_packets++; + stats->rx_bytes += pktlen; + + napi_gro_receive(napi, skb); - napi_gro_receive(napi, skb); -#ifdef CONFIG_NET_RALINK_OFFLOAD - } else { - dev_kfree_skb(skb); - } -#endif ring->rx_data[idx] = new_data; rxd->rxd1 = (unsigned int)dma_addr; @@ -1308,9 +1301,6 @@ static int fe_open(struct net_device *dev) napi_enable(&priv->rx_napi); fe_int_enable(priv->soc->tx_int | priv->soc->rx_int); netif_start_queue(dev); -#ifdef CONFIG_NET_RALINK_OFFLOAD - mtk_ppe_probe(priv); -#endif return 0; } @@ -1347,10 +1337,6 @@ static int fe_stop(struct net_device *dev) fe_free_dma(priv); -#ifdef CONFIG_NET_RALINK_OFFLOAD - mtk_ppe_remove(priv); -#endif - return 0; } @@ -1511,23 +1497,6 @@ static int fe_change_mtu(struct net_device *dev, int new_mtu) return fe_open(dev); } -#ifdef CONFIG_NET_RALINK_OFFLOAD -static int -fe_flow_offload(enum flow_offload_type type, struct flow_offload *flow, - struct flow_offload_hw_path *src, - struct flow_offload_hw_path *dest) -{ - struct fe_priv *priv; - - if (src->dev != dest->dev) - return -EINVAL; - - priv = netdev_priv(src->dev); - - return mtk_flow_offload(priv, type, flow, src, dest); -} -#endif - static const struct net_device_ops fe_netdev_ops = { .ndo_init = fe_init, .ndo_uninit = fe_uninit, @@ -1545,9 +1514,6 @@ static const struct net_device_ops fe_netdev_ops = { #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = fe_poll_controller, #endif -#ifdef CONFIG_NET_RALINK_OFFLOAD - .ndo_flow_offload = fe_flow_offload, -#endif }; static void fe_reset_pending(struct fe_priv *priv) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_offload.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_offload.c deleted file mode 100644 index 2fd424f6e3..0000000000 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_offload.c +++ /dev/null @@ -1,540 +0,0 @@ -/* This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Copyright (C) 2018 John Crispin - */ - -#include "mtk_offload.h" - -#define INVALID 0 -#define UNBIND 1 -#define BIND 2 -#define FIN 3 - -#define IPV4_HNAPT 0 -#define IPV4_HNAT 1 - -static u32 -mtk_flow_hash_v4(struct flow_offload_tuple *tuple) -{ - u32 ports = ntohs(tuple->src_port) << 16 | ntohs(tuple->dst_port); - u32 src = ntohl(tuple->dst_v4.s_addr); - u32 dst = ntohl(tuple->src_v4.s_addr); - u32 hash = (ports & src) | ((~ports) & dst); - u32 hash_23_0 = hash & 0xffffff; - u32 hash_31_24 = hash & 0xff000000; - - hash = ports ^ src ^ dst ^ ((hash_23_0 << 8) | (hash_31_24 >> 24)); - hash = ((hash & 0xffff0000) >> 16 ) ^ (hash & 0xfffff); - hash &= 0x7ff; - hash *= 2;; - - return hash; -} - -static int -mtk_foe_prepare_v4(struct mtk_foe_entry *entry, - struct flow_offload_tuple *tuple, - struct flow_offload_tuple *dest_tuple, - struct flow_offload_hw_path *src, - struct flow_offload_hw_path *dest) -{ - int is_mcast = !!is_multicast_ether_addr(dest->eth_dest); - - if (tuple->l4proto == IPPROTO_UDP) - entry->ipv4_hnapt.bfib1.udp = 1; - - entry->ipv4_hnapt.etype = htons(ETH_P_IP); - entry->ipv4_hnapt.bfib1.pkt_type = IPV4_HNAPT; - entry->ipv4_hnapt.iblk2.fqos = 0; - entry->ipv4_hnapt.bfib1.ttl = 1; - entry->ipv4_hnapt.bfib1.cah = 1; - entry->ipv4_hnapt.bfib1.ka = 1; - entry->ipv4_hnapt.iblk2.mcast = is_mcast; - entry->ipv4_hnapt.iblk2.dscp = 0; - entry->ipv4_hnapt.iblk2.port_mg = 0x3f; - entry->ipv4_hnapt.iblk2.port_ag = 0x1f; -#ifdef CONFIG_NET_RALINK_HW_QOS - entry->ipv4_hnapt.iblk2.qid = 1; - entry->ipv4_hnapt.iblk2.fqos = 1; -#endif -#ifdef CONFIG_RALINK - entry->ipv4_hnapt.iblk2.dp = 1; - if ((dest->flags & FLOW_OFFLOAD_PATH_VLAN) && (dest->vlan_id > 1)) - entry->ipv4_hnapt.iblk2.qid += 8; -#else - entry->ipv4_hnapt.iblk2.dp = (dest->dev->name[3] - '0') + 1; -#endif - - entry->ipv4_hnapt.sip = ntohl(tuple->src_v4.s_addr); - entry->ipv4_hnapt.dip = ntohl(tuple->dst_v4.s_addr); - entry->ipv4_hnapt.sport = ntohs(tuple->src_port); - entry->ipv4_hnapt.dport = ntohs(tuple->dst_port); - - entry->ipv4_hnapt.new_sip = ntohl(dest_tuple->dst_v4.s_addr); - entry->ipv4_hnapt.new_dip = ntohl(dest_tuple->src_v4.s_addr); - entry->ipv4_hnapt.new_sport = ntohs(dest_tuple->dst_port); - entry->ipv4_hnapt.new_dport = ntohs(dest_tuple->src_port); - - entry->bfib1.state = BIND; - - if (dest->flags & FLOW_OFFLOAD_PATH_PPPOE) { - entry->bfib1.psn = 1; - entry->ipv4_hnapt.etype = htons(ETH_P_PPP_SES); - entry->ipv4_hnapt.pppoe_id = dest->pppoe_sid; - } - - if (dest->flags & FLOW_OFFLOAD_PATH_VLAN) { - entry->ipv4_hnapt.vlan1 = dest->vlan_id; - entry->bfib1.vlan_layer = 1; - - switch (dest->vlan_proto) { - case htons(ETH_P_8021Q): - entry->ipv4_hnapt.bfib1.vpm = 1; - break; - case htons(ETH_P_8021AD): - entry->ipv4_hnapt.bfib1.vpm = 2; - break; - default: - return -EINVAL; - } - } - - return 0; -} - -static void -mtk_foe_set_mac(struct mtk_foe_entry *entry, u8 *smac, u8 *dmac) -{ - entry->ipv4_hnapt.dmac_hi = swab32(*((u32*) dmac)); - entry->ipv4_hnapt.dmac_lo = swab16(*((u16*) &dmac[4])); - entry->ipv4_hnapt.smac_hi = swab32(*((u32*) smac)); - entry->ipv4_hnapt.smac_lo = swab16(*((u16*) &smac[4])); -} - -static int -mtk_check_entry_available(struct mtk_eth *eth, u32 hash) -{ - struct mtk_foe_entry entry = ((struct mtk_foe_entry *)eth->foe_table)[hash]; - - return (entry.bfib1.state == BIND)? 0:1; -} - -static void -mtk_foe_write(struct mtk_eth *eth, u32 hash, - struct mtk_foe_entry *entry) -{ - struct mtk_foe_entry *table = (struct mtk_foe_entry *)eth->foe_table; - - memcpy(&table[hash], entry, sizeof(*entry)); -} - -int mtk_flow_offload(struct mtk_eth *eth, - enum flow_offload_type type, - struct flow_offload *flow, - struct flow_offload_hw_path *src, - struct flow_offload_hw_path *dest) -{ - struct flow_offload_tuple *otuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple; - struct flow_offload_tuple *rtuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple; - u32 time_stamp = mtk_r32(eth, 0x0010) & (0x7fff); - u32 ohash, rhash; - struct mtk_foe_entry orig = { - .bfib1.time_stamp = time_stamp, - .bfib1.psn = 0, - }; - struct mtk_foe_entry reply = { - .bfib1.time_stamp = time_stamp, - .bfib1.psn = 0, - }; - - if (otuple->l4proto != IPPROTO_TCP && otuple->l4proto != IPPROTO_UDP) - return -EINVAL; - - if (type == FLOW_OFFLOAD_DEL) { - flow = NULL; - synchronize_rcu(); - return 0; - } - - switch (otuple->l3proto) { - case AF_INET: - if (mtk_foe_prepare_v4(&orig, otuple, rtuple, src, dest) || - mtk_foe_prepare_v4(&reply, rtuple, otuple, dest, src)) - return -EINVAL; - - ohash = mtk_flow_hash_v4(otuple); - rhash = mtk_flow_hash_v4(rtuple); - break; - - case AF_INET6: - return -EINVAL; - - default: - return -EINVAL; - } - - /* Two-way hash: when hash collision occurs, the hash value will be shifted to the next position. */ - if (!mtk_check_entry_available(eth, ohash)){ - if (!mtk_check_entry_available(eth, ohash + 1)) - return -EINVAL; - ohash += 1; - } - if (!mtk_check_entry_available(eth, rhash)){ - if (!mtk_check_entry_available(eth, rhash + 1)) - return -EINVAL; - rhash += 1; - } - - mtk_foe_set_mac(&orig, dest->eth_src, dest->eth_dest); - mtk_foe_set_mac(&reply, src->eth_src, src->eth_dest); - mtk_foe_write(eth, ohash, &orig); - mtk_foe_write(eth, rhash, &reply); - rcu_assign_pointer(eth->foe_flow_table[ohash], flow); - rcu_assign_pointer(eth->foe_flow_table[rhash], flow); - - return 0; -} - -#ifdef CONFIG_NET_RALINK_HW_QOS - -#define QDMA_TX_SCH_TX 0x1a14 - -static void mtk_ppe_scheduler(struct mtk_eth *eth, int id, u32 rate) -{ - int exp = 0, shift = 0; - u32 reg = mtk_r32(eth, QDMA_TX_SCH_TX); - u32 val = 0; - - if (rate) - val = BIT(11); - - while (rate > 127) { - rate /= 10; - exp++; - } - - val |= (rate & 0x7f) << 4; - val |= exp & 0xf; - if (id) - shift = 16; - reg &= ~(0xffff << shift); - reg |= val << shift; - mtk_w32(eth, val, QDMA_TX_SCH_TX); -} - -#define QTX_CFG(x) (0x1800 + (x * 0x10)) -#define QTX_SCH(x) (0x1804 + (x * 0x10)) - -static void mtk_ppe_queue(struct mtk_eth *eth, int id, int sched, int weight, int resv, u32 min_rate, u32 max_rate) -{ - int max_exp = 0, min_exp = 0; - u32 reg; - - if (id >= 16) - return; - - reg = mtk_r32(eth, QTX_SCH(id)); - reg &= 0x70000000; - - if (sched) - reg |= BIT(31); - - if (min_rate) - reg |= BIT(27); - - if (max_rate) - reg |= BIT(11); - - while (max_rate > 127) { - max_rate /= 10; - max_exp++; - } - - while (min_rate > 127) { - min_rate /= 10; - min_exp++; - } - - reg |= (min_rate & 0x7f) << 20; - reg |= (min_exp & 0xf) << 16; - reg |= (weight & 0xf) << 12; - reg |= (max_rate & 0x7f) << 4; - reg |= max_exp & 0xf; - mtk_w32(eth, reg, QTX_SCH(id)); - - resv &= 0xff; - reg = mtk_r32(eth, QTX_CFG(id)); - reg &= 0xffff0000; - reg |= (resv << 8) | resv; - mtk_w32(eth, reg, QTX_CFG(id)); -} -#endif - -static int mtk_init_foe_table(struct mtk_eth *eth) -{ - if (eth->foe_table) - return 0; - - eth->foe_flow_table = devm_kcalloc(eth->dev, MTK_PPE_ENTRY_CNT, - sizeof(*eth->foe_flow_table), - GFP_KERNEL); - if (!eth->foe_flow_table) - return -EINVAL; - - /* map the FOE table */ - eth->foe_table = dmam_alloc_coherent(eth->dev, MTK_PPE_TBL_SZ, - ð->foe_table_phys, GFP_KERNEL); - if (!eth->foe_table) { - dev_err(eth->dev, "failed to allocate foe table\n"); - kfree(eth->foe_flow_table); - return -ENOMEM; - } - - - return 0; -} - -static int mtk_ppe_start(struct mtk_eth *eth) -{ - int ret; - - ret = mtk_init_foe_table(eth); - if (ret) - return ret; - - /* tell the PPE about the tables base address */ - mtk_w32(eth, eth->foe_table_phys, MTK_REG_PPE_TB_BASE); - - /* flush the table */ - memset(eth->foe_table, 0, MTK_PPE_TBL_SZ); - - /* setup hashing */ - mtk_m32(eth, - MTK_PPE_TB_CFG_HASH_MODE_MASK | MTK_PPE_TB_CFG_TBL_SZ_MASK, - MTK_PPE_TB_CFG_HASH_MODE1 | MTK_PPE_TB_CFG_TBL_SZ_4K, - MTK_REG_PPE_TB_CFG); - - /* set the default hashing seed */ - mtk_w32(eth, MTK_PPE_HASH_SEED, MTK_REG_PPE_HASH_SEED); - - /* each foe entry is 64bytes and is setup by cpu forwarding*/ - mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_TB_CFG_ENTRY_SZ_MASK | - MTK_PPE_TB_CFG_SMA_MASK, - MTK_PPE_TB_CFG_ENTRY_SZ_64B | MTK_PPE_TB_CFG_SMA_FWD_CPU, - MTK_REG_PPE_TB_CFG); - - /* set ip proto */ - mtk_w32(eth, 0xFFFFFFFF, MTK_REG_PPE_IP_PROT_CHK); - - /* setup caching */ - mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL); - mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE, MTK_PPE_CAH_CTRL_EN, - MTK_REG_PPE_CAH_CTRL); - - /* enable FOE */ - mtk_m32(eth, 0, MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN | - MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN | - MTK_PPE_FLOW_CFG_IPV4_GREK_EN, - MTK_REG_PPE_FLOW_CFG); - - /* setup flow entry un/bind aging */ - mtk_m32(eth, 0, - MTK_PPE_TB_CFG_UNBD_AGE | MTK_PPE_TB_CFG_NTU_AGE | - MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE | - MTK_PPE_TB_CFG_TCP_AGE, - MTK_REG_PPE_TB_CFG); - - mtk_m32(eth, MTK_PPE_UNB_AGE_MNP_MASK | MTK_PPE_UNB_AGE_DLTA_MASK, - MTK_PPE_UNB_AGE_MNP | MTK_PPE_UNB_AGE_DLTA, - MTK_REG_PPE_UNB_AGE); - mtk_m32(eth, MTK_PPE_BND_AGE0_NTU_DLTA_MASK | - MTK_PPE_BND_AGE0_UDP_DLTA_MASK, - MTK_PPE_BND_AGE0_NTU_DLTA | MTK_PPE_BND_AGE0_UDP_DLTA, - MTK_REG_PPE_BND_AGE0); - mtk_m32(eth, MTK_PPE_BND_AGE1_FIN_DLTA_MASK | - MTK_PPE_BND_AGE1_TCP_DLTA_MASK, - MTK_PPE_BND_AGE1_FIN_DLTA | MTK_PPE_BND_AGE1_TCP_DLTA, - MTK_REG_PPE_BND_AGE1); - - /* setup flow entry keep alive */ - mtk_m32(eth, MTK_PPE_TB_CFG_KA_MASK, MTK_PPE_TB_CFG_KA, - MTK_REG_PPE_TB_CFG); - mtk_w32(eth, MTK_PPE_KA_UDP | MTK_PPE_KA_TCP | MTK_PPE_KA_T, MTK_REG_PPE_KA); - - /* setup flow entry rate limit */ - mtk_w32(eth, (0x3fff << 16) | 0x3fff, MTK_REG_PPE_BIND_LMT_0); - mtk_w32(eth, MTK_PPE_NTU_KA | 0x3fff, MTK_REG_PPE_BIND_LMT_1); - mtk_m32(eth, MTK_PPE_BNDR_RATE_MASK, 1, MTK_REG_PPE_BNDR); - - /* enable the PPE */ - mtk_m32(eth, 0, MTK_PPE_GLO_CFG_EN, MTK_REG_PPE_GLO_CFG); - -#ifdef CONFIG_RALINK - /* set the default forwarding port to QDMA */ - mtk_w32(eth, 0x0, MTK_REG_PPE_DFT_CPORT); -#else - /* set the default forwarding port to QDMA */ - mtk_w32(eth, 0x55555555, MTK_REG_PPE_DFT_CPORT); -#endif - - /* allow packets with TTL=0 */ - mtk_m32(eth, MTK_PPE_GLO_CFG_TTL0_DROP, 0, MTK_REG_PPE_GLO_CFG); - - /* send all traffic from gmac to the ppe */ - mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(0)); - mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(1)); - - dev_info(eth->dev, "PPE started\n"); - -#ifdef CONFIG_NET_RALINK_HW_QOS - mtk_ppe_scheduler(eth, 0, 500000); - mtk_ppe_scheduler(eth, 1, 500000); - mtk_ppe_queue(eth, 0, 0, 7, 32, 250000, 0); - mtk_ppe_queue(eth, 1, 0, 7, 32, 250000, 0); - mtk_ppe_queue(eth, 8, 1, 7, 32, 250000, 0); - mtk_ppe_queue(eth, 9, 1, 7, 32, 250000, 0); -#endif - - return 0; -} - -static int mtk_ppe_busy_wait(struct mtk_eth *eth) -{ - unsigned long t_start = jiffies; - u32 r = 0; - - while (1) { - r = mtk_r32(eth, MTK_REG_PPE_GLO_CFG); - if (!(r & MTK_PPE_GLO_CFG_BUSY)) - return 0; - if (time_after(jiffies, t_start + HZ)) - break; - usleep_range(10, 20); - } - - dev_err(eth->dev, "ppe: table busy timeout - resetting\n"); - reset_control_reset(eth->rst_ppe); - - return -ETIMEDOUT; -} - -static int mtk_ppe_stop(struct mtk_eth *eth) -{ - u32 r1 = 0, r2 = 0; - int i; - - /* discard all traffic while we disable the PPE */ - mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(0)); - mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(1)); - - if (mtk_ppe_busy_wait(eth)) - return -ETIMEDOUT; - - /* invalidate all flow table entries */ - for (i = 0; i < MTK_PPE_ENTRY_CNT; i++) - eth->foe_table[i].bfib1.state = FOE_STATE_INVALID; - - /* disable caching */ - mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL); - mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_CAH_CTRL_EN, 0, - MTK_REG_PPE_CAH_CTRL); - - /* flush cache has to be ahead of hnat diable --*/ - mtk_m32(eth, MTK_PPE_GLO_CFG_EN, 0, MTK_REG_PPE_GLO_CFG); - - /* disable FOE */ - mtk_m32(eth, - MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN | - MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN | - MTK_PPE_FLOW_CFG_FUC_FOE | MTK_PPE_FLOW_CFG_FMC_FOE, - 0, MTK_REG_PPE_FLOW_CFG); - - /* disable FOE aging */ - mtk_m32(eth, 0, - MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE | - MTK_PPE_TB_CFG_TCP_AGE | MTK_PPE_TB_CFG_UNBD_AGE | - MTK_PPE_TB_CFG_NTU_AGE, MTK_REG_PPE_TB_CFG); - - r1 = mtk_r32(eth, 0x100); - r2 = mtk_r32(eth, 0x10c); - - dev_info(eth->dev, "0x100 = 0x%x, 0x10c = 0x%x\n", r1, r2); - - if (((r1 & 0xff00) >> 0x8) >= (r1 & 0xff) || - ((r1 & 0xff00) >> 0x8) >= (r2 & 0xff)) { - dev_info(eth->dev, "reset pse\n"); - mtk_w32(eth, 0x1, 0x4); - } - - /* set the foe entry base address to 0 */ - mtk_w32(eth, 0, MTK_REG_PPE_TB_BASE); - - if (mtk_ppe_busy_wait(eth)) - return -ETIMEDOUT; - - /* send all traffic back to the DMA engine */ -#ifdef CONFIG_RALINK - mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(0)); - mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(1)); -#else - mtk_m32(eth, 0xffff, 0x5555, MTK_GDMA_FWD_CFG(0)); - mtk_m32(eth, 0xffff, 0x5555, MTK_GDMA_FWD_CFG(1)); -#endif - return 0; -} - -static void mtk_offload_keepalive(struct fe_priv *eth, unsigned int hash) -{ - struct flow_offload *flow; - - rcu_read_lock(); - flow = rcu_dereference(eth->foe_flow_table[hash]); - if (flow) - flow->timeout = jiffies + 30 * HZ; - rcu_read_unlock(); -} - -int mtk_offload_check_rx(struct fe_priv *eth, struct sk_buff *skb, u32 rxd4) -{ - unsigned int hash; - - switch (FIELD_GET(MTK_RXD4_CPU_REASON, rxd4)) { - case MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR: - case MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR: - case MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR: - hash = FIELD_GET(MTK_RXD4_FOE_ENTRY, rxd4); - mtk_offload_keepalive(eth, hash); - return -1; - case MTK_CPU_REASON_PACKET_SAMPLING: - return -1; - default: - return 0; - } -} - -int mtk_ppe_probe(struct mtk_eth *eth) -{ - int err; - - err = mtk_ppe_start(eth); - if (err) - return err; - - err = mtk_ppe_debugfs_init(eth); - if (err) - return err; - - return 0; -} - -void mtk_ppe_remove(struct mtk_eth *eth) -{ - mtk_ppe_stop(eth); -} diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_offload.h b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_offload.h deleted file mode 100644 index f714c90f92..0000000000 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_offload.h +++ /dev/null @@ -1,260 +0,0 @@ -/* This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Copyright (C) 2014-2016 Sean Wang - * Copyright (C) 2016-2017 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mtk_eth_soc.h" - -#ifdef CONFIG_RALINK -/* ramips compat */ -#define mtk_eth fe_priv -#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) -#define mtk_m32 fe_m32 - -static inline u32 -mtk_r32(struct mtk_eth *eth, u32 reg) -{ - return fe_r32(reg); -} - -static inline void -mtk_w32(struct mtk_eth *eth, u32 val, u32 reg) -{ - fe_w32(val, reg); -} -#endif - -#define MTK_REG_PPE_GLO_CFG 0xe00 -#define MTK_PPE_GLO_CFG_BUSY BIT(31) -#define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4) -#define MTK_PPE_GLO_CFG_EN BIT(0) - -#define MTK_REG_PPE_FLOW_CFG 0xe04 -#define MTK_PPE_FLOW_CFG_IPV4_GREK_EN BIT(19) -#define MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN BIT(17) -#define MTK_PPE_FLOW_CFG_IPV4_NAPT_EN BIT(13) -#define MTK_PPE_FLOW_CFG_IPV4_NAT_EN BIT(12) -#define MTK_PPE_FLOW_CFG_FUC_FOE BIT(2) -#define MTK_PPE_FLOW_CFG_FMC_FOE BIT(1) - -#define MTK_REG_PPE_IP_PROT_CHK 0xe08 - -#define MTK_REG_PPE_TB_BASE 0xe20 - -#define MTK_REG_PPE_BNDR 0xe28 -#define MTK_PPE_BNDR_RATE_MASK 0xffff - -#define MTK_REG_PPE_BIND_LMT_0 0xe2C - -#define MTK_REG_PPE_BIND_LMT_1 0xe30 -#define MTK_PPE_NTU_KA BIT(16) - -#define MTK_REG_PPE_KA 0xe34 -#define MTK_PPE_KA_T BIT(0) -#define MTK_PPE_KA_TCP BIT(16) -#define MTK_PPE_KA_UDP BIT(24) - -#define MTK_REG_PPE_UNB_AGE 0xe38 -#define MTK_PPE_UNB_AGE_MNP_MASK (0xffff << 16) -#define MTK_PPE_UNB_AGE_MNP (1000 << 16) -#define MTK_PPE_UNB_AGE_DLTA_MASK 0xff -#define MTK_PPE_UNB_AGE_DLTA 3 - -#define MTK_REG_PPE_BND_AGE0 0xe3c -#define MTK_PPE_BND_AGE0_NTU_DLTA_MASK (0xffff << 16) -#define MTK_PPE_BND_AGE0_NTU_DLTA (5 << 16) -#define MTK_PPE_BND_AGE0_UDP_DLTA_MASK 0xffff -#define MTK_PPE_BND_AGE0_UDP_DLTA 5 - -#define MTK_REG_PPE_BND_AGE1 0xe40 -#define MTK_PPE_BND_AGE1_FIN_DLTA_MASK (0xffff << 16) -#define MTK_PPE_BND_AGE1_FIN_DLTA (5 << 16) -#define MTK_PPE_BND_AGE1_TCP_DLTA_MASK 0xffff -#define MTK_PPE_BND_AGE1_TCP_DLTA 5 - -#define MTK_REG_PPE_DFT_CPORT 0xe48 - -#define MTK_REG_PPE_TB_CFG 0xe1c -#define MTK_PPE_TB_CFG_X_MODE_MASK (3 << 18) -#define MTK_PPE_TB_CFG_HASH_MODE1 BIT(14) -#define MTK_PPE_TB_CFG_HASH_MODE_MASK (0x3 << 14) -#define MTK_PPE_TB_CFG_KA (3 << 12) -#define MTK_PPE_TB_CFG_KA_MASK (0x3 << 12) -#define MTK_PPE_TB_CFG_FIN_AGE BIT(11) -#define MTK_PPE_TB_CFG_UDP_AGE BIT(10) -#define MTK_PPE_TB_CFG_TCP_AGE BIT(9) -#define MTK_PPE_TB_CFG_UNBD_AGE BIT(8) -#define MTK_PPE_TB_CFG_NTU_AGE BIT(7) -#define MTK_PPE_TB_CFG_SMA_FWD_CPU (0x3 << 4) -#define MTK_PPE_TB_CFG_SMA_MASK (0x3 << 4) -#define MTK_PPE_TB_CFG_ENTRY_SZ_64B 0 -#define MTK_PPE_TB_CFG_ENTRY_SZ_MASK BIT(3) -#define MTK_PPE_TB_CFG_TBL_SZ_4K 2 -#define MTK_PPE_TB_CFG_TBL_SZ_MASK 0x7 - -#define MTK_REG_PPE_HASH_SEED 0xe44 -#define MTK_PPE_HASH_SEED 0x12345678 - - -#define MTK_REG_PPE_CAH_CTRL 0xf20 -#define MTK_PPE_CAH_CTRL_X_MODE BIT(9) -#define MTK_PPE_CAH_CTRL_EN BIT(0) - -struct mtk_foe_unbind_info_blk { - u32 time_stamp:8; - u32 pcnt:16; /* packet count */ - u32 preb:1; - u32 pkt_type:3; - u32 state:2; - u32 udp:1; - u32 sta:1; /* static entry */ -} __attribute__ ((packed)); - -struct mtk_foe_bind_info_blk { - u32 time_stamp:15; - u32 ka:1; /* keep alive */ - u32 vlan_layer:3; - u32 psn:1; /* egress packet has PPPoE session */ -#ifdef CONFIG_RALINK - u32 vpm:2; /* 0:ethertype remark, 1:0x8100(CR default) */ -#else - u32 vpm:1; /* 0:ethertype remark, 1:0x8100(CR default) */ - u32 ps:1; /* packet sampling */ -#endif - u32 cah:1; /* cacheable flag */ - u32 rmt:1; /* remove tunnel ip header (6rd/dslite only) */ - u32 ttl:1; - u32 pkt_type:3; - u32 state:2; - u32 udp:1; - u32 sta:1; /* static entry */ -} __attribute__ ((packed)); - -struct mtk_foe_info_blk2 { - u32 qid:4; /* QID in Qos Port */ - u32 fqos:1; /* force to PSE QoS port */ - u32 dp:3; /* force to PSE port x - 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP */ - u32 mcast:1; /* multicast this packet to CPU */ - u32 pcpl:1; /* OSBN */ - u32 mlen:1; /* 0:post 1:pre packet length in meter */ - u32 alen:1; /* 0:post 1:pre packet length in accounting */ - u32 port_mg:6; /* port meter group */ - u32 port_ag:6; /* port account group */ - u32 dscp:8; /* DSCP value */ -} __attribute__ ((packed)); - -struct mtk_foe_ipv4_hnapt { - union { - struct mtk_foe_bind_info_blk bfib1; - struct mtk_foe_unbind_info_blk udib1; - u32 info_blk1; - }; - u32 sip; - u32 dip; - u16 dport; - u16 sport; - union { - struct mtk_foe_info_blk2 iblk2; - u32 info_blk2; - }; - u32 new_sip; - u32 new_dip; - u16 new_dport; - u16 new_sport; - u32 resv1; - u32 resv2; - u32 resv3:26; - u32 act_dp:6; /* UDF */ - u16 vlan1; - u16 etype; - u32 dmac_hi; - u16 vlan2; - u16 dmac_lo; - u32 smac_hi; - u16 pppoe_id; - u16 smac_lo; -} __attribute__ ((packed)); - -struct mtk_foe_entry { - union { - struct mtk_foe_unbind_info_blk udib1; - struct mtk_foe_bind_info_blk bfib1; - struct mtk_foe_ipv4_hnapt ipv4_hnapt; - }; -}; - -enum mtk_foe_entry_state { - FOE_STATE_INVALID = 0, - FOE_STATE_UNBIND = 1, - FOE_STATE_BIND = 2, - FOE_STATE_FIN = 3 -}; - - -#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) -#define MTK_RXD4_CPU_REASON GENMASK(18, 14) -#define MTK_RXD4_SRC_PORT GENMASK(21, 19) -#define MTK_RXD4_ALG GENMASK(31, 22) - -enum mtk_foe_cpu_reason { - MTK_CPU_REASON_TTL_EXCEEDED = 0x02, - MTK_CPU_REASON_OPTION_HEADER = 0x03, - MTK_CPU_REASON_NO_FLOW = 0x07, - MTK_CPU_REASON_IPV4_FRAG = 0x08, - MTK_CPU_REASON_IPV4_DSLITE_FRAG = 0x09, - MTK_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP = 0x0a, - MTK_CPU_REASON_IPV6_6RD_NO_TCP_UDP = 0x0b, - MTK_CPU_REASON_TCP_FIN_SYN_RST = 0x0c, - MTK_CPU_REASON_UN_HIT = 0x0d, - MTK_CPU_REASON_HIT_UNBIND = 0x0e, - MTK_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f, - MTK_CPU_REASON_HIT_BIND_TCP_FIN = 0x10, - MTK_CPU_REASON_HIT_TTL_1 = 0x11, - MTK_CPU_REASON_HIT_BIND_VLAN_VIOLATION = 0x12, - MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR = 0x13, - MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR = 0x14, - MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR = 0x15, - MTK_CPU_REASON_HIT_BIND_FORCE_CPU = 0x16, - MTK_CPU_REASON_TUNNEL_OPTION_HEADER = 0x17, - MTK_CPU_REASON_MULTICAST_TO_CPU = 0x18, - MTK_CPU_REASON_MULTICAST_TO_GMAC1_CPU = 0x19, - MTK_CPU_REASON_HIT_PRE_BIND = 0x1a, - MTK_CPU_REASON_PACKET_SAMPLING = 0x1b, - MTK_CPU_REASON_EXCEED_MTU = 0x1c, - MTK_CPU_REASON_PPE_BYPASS = 0x1e, - MTK_CPU_REASON_INVALID = 0x1f, -}; - - -/* our table size is 4K */ -#define MTK_PPE_ENTRY_CNT 0x1000 -#define MTK_PPE_TBL_SZ \ - (MTK_PPE_ENTRY_CNT * sizeof(struct mtk_foe_entry)) - -int mtk_ppe_debugfs_init(struct mtk_eth *eth); - - diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7621.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7621.c deleted file mode 100644 index 26a198fa2b..0000000000 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7621.c +++ /dev/null @@ -1,187 +0,0 @@ -/* This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Copyright (C) 2009-2015 John Crispin - * Copyright (C) 2009-2015 Felix Fietkau - * Copyright (C) 2013-2015 Michael Lee - */ - -#include -#include -#include -#include - -#include - -#include "mtk_eth_soc.h" -#include "gsw_mt7620.h" -#include "mt7530.h" -#include "mdio.h" - -#define MT7620A_CDMA_CSG_CFG 0x400 -#define MT7621_CDMP_IG_CTRL (MT7620A_CDMA_CSG_CFG + 0x00) -#define MT7621_CDMP_EG_CTRL (MT7620A_CDMA_CSG_CFG + 0x04) -#define MT7621_RESET_FE BIT(6) -#define MT7621_L4_VALID BIT(24) - -#define MT7621_TX_DMA_UDF BIT(19) -#define MT7621_TX_DMA_FPORT BIT(25) - -#define CDMA_ICS_EN BIT(2) -#define CDMA_UCS_EN BIT(1) -#define CDMA_TCS_EN BIT(0) - -#define GDMA_ICS_EN BIT(22) -#define GDMA_TCS_EN BIT(21) -#define GDMA_UCS_EN BIT(20) - -/* frame engine counters */ -#define MT7621_REG_MIB_OFFSET 0x2000 -#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00) -#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400) -#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40) - -#define GSW_REG_GDMA1_MAC_ADRL 0x508 -#define GSW_REG_GDMA1_MAC_ADRH 0x50C - -#define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04) -#define MT7620_FE_INT_STATUS2 (FE_FE_OFFSET + 0x08) - -/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29) - * but after test it should be BIT(13). - */ -#define MT7620_FE_GDM1_AF BIT(13) -#define MT7621_FE_GDM1_AF BIT(28) -#define MT7621_FE_GDM2_AF BIT(29) - -static const u16 mt7621_reg_table[FE_REG_COUNT] = { - [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, - [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, - [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, - [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0, - [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0, - [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0, - [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0, - [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0, - [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0, - [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0, - [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0, - [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE, - [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS, - [FE_REG_FE_DMA_VID_BASE] = 0, - [FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT, - [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL, - [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2, -}; - -static int mt7621_gsw_config(struct fe_priv *priv) -{ - if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f)) - mt7530_probe(priv->dev, NULL, priv->mii_bus, 1); - - return 0; -} - -static void mt7621_fe_reset(void) -{ - fe_reset(MT7621_RESET_FE); -} - -static void mt7621_rxcsum_config(bool enable) -{ - if (enable) - fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | - GDMA_TCS_EN | GDMA_UCS_EN), - MT7620A_GDMA1_FWD_CFG); - else - fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN | - GDMA_TCS_EN | GDMA_UCS_EN), - MT7620A_GDMA1_FWD_CFG); -} - -static void mt7621_rxvlan_config(bool enable) -{ - if (enable) - fe_w32(1, MT7621_CDMP_EG_CTRL); - else - fe_w32(0, MT7621_CDMP_EG_CTRL); -} - -static int mt7621_fwd_config(struct fe_priv *priv) -{ - struct net_device *dev = priv_netdev(priv); - - fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, - MT7620A_GDMA1_FWD_CFG); - - /* mt7621 doesn't have txcsum config */ - mt7621_rxcsum_config((dev->features & NETIF_F_RXCSUM)); - mt7621_rxvlan_config(dev->features & NETIF_F_HW_VLAN_CTAG_RX); - - return 0; -} - -static void mt7621_tx_dma(struct fe_tx_dma *txd) -{ - txd->txd4 = MT7621_TX_DMA_FPORT; -} - -static void mt7621_init_data(struct fe_soc_data *data, - struct net_device *netdev) -{ - struct fe_priv *priv = netdev_priv(netdev); - - priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET | - FE_FLAG_RX_SG_DMA | FE_FLAG_NAPI_WEIGHT | - FE_FLAG_HAS_SWITCH | FE_FLAG_JUMBO_FRAME; - - netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | - NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | - NETIF_F_SG | NETIF_F_TSO | - NETIF_F_TSO6 | NETIF_F_IPV6_CSUM | - NETIF_F_TSO_MANGLEID; -} - -static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac) -{ - unsigned long flags; - - spin_lock_irqsave(&priv->page_lock, flags); - fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH); - fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], - GSW_REG_GDMA1_MAC_ADRL); - spin_unlock_irqrestore(&priv->page_lock, flags); -} - -static struct fe_soc_data mt7621_data = { - .init_data = mt7621_init_data, - .reset_fe = mt7621_fe_reset, - .set_mac = mt7621_set_mac, - .fwd_config = mt7621_fwd_config, - .tx_dma = mt7621_tx_dma, - .switch_init = mtk_gsw_init, - .switch_config = mt7621_gsw_config, - .reg_table = mt7621_reg_table, - .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS, - .rx_int = RT5350_RX_DONE_INT, - .tx_int = RT5350_TX_DONE_INT, - .status_int = (MT7621_FE_GDM1_AF | MT7621_FE_GDM2_AF), - .checksum_bit = MT7621_L4_VALID, - .has_carrier = mt7620_has_carrier, - .mdio_read = mt7620_mdio_read, - .mdio_write = mt7620_mdio_write, - .mdio_adjust_link = mt7620_mdio_link_adjust, -}; - -const struct of_device_id of_fe_match[] = { - { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, - {}, -}; - -MODULE_DEVICE_TABLE(of, of_fe_match); From 010682067b65847c8d9c3637b7c8afa9f93b2e08 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Fri, 21 Aug 2020 18:06:50 +0200 Subject: [PATCH 17/17] mac80211: add missing return code checks in AQL improvements Fixes throughput issues with some drivers (e.g. ath10k) Signed-off-by: Felix Fietkau --- ...211-factor-out-code-to-look-up-the-average-pack.patch | 5 +++-- ...211-improve-AQL-aggregation-estimation-for-low-.patch | 9 +++++---- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/package/kernel/mac80211/patches/subsys/312-mac80211-factor-out-code-to-look-up-the-average-pack.patch b/package/kernel/mac80211/patches/subsys/312-mac80211-factor-out-code-to-look-up-the-average-pack.patch index 105bbe2529..06db852c30 100644 --- a/package/kernel/mac80211/patches/subsys/312-mac80211-factor-out-code-to-look-up-the-average-pack.patch +++ b/package/kernel/mac80211/patches/subsys/312-mac80211-factor-out-code-to-look-up-the-average-pack.patch @@ -104,7 +104,7 @@ Signed-off-by: Felix Fietkau } EXPORT_SYMBOL_GPL(ieee80211_calc_rx_airtime); -@@ -530,46 +546,56 @@ static bool ieee80211_fill_rate_info(str +@@ -530,46 +546,57 @@ static bool ieee80211_fill_rate_info(str return false; } @@ -179,7 +179,8 @@ Signed-off-by: Felix Fietkau +{ + struct ieee80211_rx_status stat; + -+ ieee80211_fill_rx_status(&stat, hw, rate, ri, band, len); ++ if (ieee80211_fill_rx_status(&stat, hw, rate, ri, band, len)) ++ return 0; + return ieee80211_calc_rx_airtime(hw, &stat, len); } diff --git a/package/kernel/mac80211/patches/subsys/313-mac80211-improve-AQL-aggregation-estimation-for-low-.patch b/package/kernel/mac80211/patches/subsys/313-mac80211-improve-AQL-aggregation-estimation-for-low-.patch index 565d9bec43..7f7c75db59 100644 --- a/package/kernel/mac80211/patches/subsys/313-mac80211-improve-AQL-aggregation-estimation-for-low-.patch +++ b/package/kernel/mac80211/patches/subsys/313-mac80211-improve-AQL-aggregation-estimation-for-low-.patch @@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/airtime.c +++ b/net/mac80211/airtime.c -@@ -646,27 +646,40 @@ u32 ieee80211_calc_expected_tx_airtime(s +@@ -647,27 +647,41 @@ u32 ieee80211_calc_expected_tx_airtime(s if (pubsta) { struct sta_info *sta = container_of(pubsta, struct sta_info, sta); @@ -26,11 +26,12 @@ Signed-off-by: Felix Fietkau - if (!(rate->flags & (IEEE80211_TX_RC_VHT_MCS | - IEEE80211_TX_RC_MCS))) - ampdu = false; -+ ieee80211_fill_rx_status(&stat, hw, rate, ri, band, len); -+ ++ if (ieee80211_fill_rx_status(&stat, hw, rate, ri, band, len)) ++ return 0; + + if (stat.encoding == RX_ENC_LEGACY || !ampdu) + return ieee80211_calc_rx_airtime(hw, &stat, len); - ++ + duration = ieee80211_get_rate_duration(hw, &stat, &overhead); /* * Assume that HT/VHT transmission on any AC except VO will