Merge Official Source

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2022-01-03 14:06:23 +08:00
commit 1a9640e7d6
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
94 changed files with 3323 additions and 262 deletions

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@ -6,11 +6,11 @@ ifdef CONFIG_TESTING_KERNEL
KERNEL_PATCHVER:=$(KERNEL_TESTING_PATCHVER)
endif
LINUX_VERSION-5.4 = .167
LINUX_VERSION-5.10 = .88
LINUX_VERSION-5.4 = .169
LINUX_VERSION-5.10 = .89
LINUX_KERNEL_HASH-5.4.167 = b4e43116217ee02009aba7eab3081e64560b81ce42bc6096fcd81257f470a5a7
LINUX_KERNEL_HASH-5.10.88 = 6f8631b6c382a2b0cfeff1e5f8805c8e1cfbe8d714b6e65f5bb79733c99068eb
LINUX_KERNEL_HASH-5.4.169 = 554382d95f71afd5f9b49292eb5d1cbe3be1a0bad22d21487c9e6d506ee01a19
LINUX_KERNEL_HASH-5.10.89 = 92218b1a4a18f1cb9ec07d2b7fce41577452aa552c54c25b6d5fe9b4b543bb30
remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))

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@ -25,7 +25,8 @@ define Host/Compile
$(MAKE) -C \
$(HOST_BUILD_DIR)/tools/fiptool \
CFLAGS="$(HOST_CFLAGS)" \
LDFLAGS="$(HOST_LDFLAGS)"
LDFLAGS="$(HOST_LDFLAGS)" \
HOSTCCFLAGS="$(HOST_CFLAGS)"
$(MAKE) -C \
$(HOST_BUILD_DIR)/tools/nxp \
CFLAGS="$(HOST_CFLAGS)"

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@ -19,6 +19,7 @@ globalscale,sheevaplug|\
iom,ix2-200|\
linksys,e4200-v2|\
linksys,ea4500|\
netgear,readynas-duo-v2|\
raidsonic,ib-nas62x0|\
seagate,dockstar|\
zyxel,nsa310b|\

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@ -9,14 +9,14 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=binutils
PKG_VERSION:=2.37
PKG_RELEASE:=1
PKG_RELEASE:=2
PKG_SOURCE_URL:=@GNU/binutils
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_VERSION:=$(PKG_VERSION)
PKG_HASH:=820d9724f020a3e69cb337893a0b63c2db161dadcb0e06fc11dc29eb1e84a32c
PKG_FIXUP:=autoreconf
PKG_FIXUP:=patch-libtool
PKG_LIBTOOL_PATHS:=. gas bfd opcodes gprof binutils ld libiberty gold intl
PKG_REMOVE_FILES:=libtool.m4
PKG_INSTALL:=1

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@ -138,6 +138,21 @@ endef
$(eval $(call KernelPackage,hwmon-f71882fg))
define KernelPackage/hwmon-g762
TITLE:=G762/G763 fan speed PWM controller support
KCONFIG:=CONFIG_SENSORS_G762
FILES:=$(LINUX_DIR)/drivers/hwmon/g762.ko
AUTOLOAD:=$(call AutoProbe,g762)
$(call AddDepends/hwmon,+kmod-i2c-core)
endef
define KernelPackage/hwmon-g762/description
Kernel module for Global Mixed-mode Technology Inc G762 and G763 fan speed PWM controller chips.
endef
$(eval $(call KernelPackage,hwmon-g762))
define KernelPackage/hwmon-ina209
TITLE:=INA209 monitoring support
KCONFIG:=CONFIG_SENSORS_INA209

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@ -9,9 +9,9 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=openssl
PKG_BASE:=1.1.1
PKG_BUGFIX:=l
PKG_BUGFIX:=m
PKG_VERSION:=$(PKG_BASE)$(PKG_BUGFIX)
PKG_RELEASE:=2
PKG_RELEASE:=1
PKG_USE_MIPS16:=0
ENGINES_DIR=engines-1.1
@ -28,7 +28,7 @@ PKG_SOURCE_URL:= \
ftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/ \
ftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/old/$(PKG_BASE)/
PKG_HASH:=0b7a3e5e59c34827fe0c3a74b7ec8baef302b98fa80088d7f9153aa16fa76bd1
PKG_HASH:=f89199be8b23ca45fc7cb9f1d8d3ee67312318286ad030f5316aca6462db6c96
PKG_LICENSE:=OpenSSL
PKG_LICENSE_FILES:=LICENSE

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@ -1,7 +1,7 @@
From 34ab13b7d8e3e723adb60be8142e38b7c9cd382a Mon Sep 17 00:00:00 2001
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Andy Polyakov <appro@openssl.org>
Date: Sun, 5 May 2019 18:25:50 +0200
Subject: [PATCH] crypto/perlasm/ppc-xlate.pl: add linux64v2 flavour
Subject: crypto/perlasm/ppc-xlate.pl: add linux64v2 flavour
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
@ -14,12 +14,8 @@ endian nowadays (Adélie Linux, Void Linux, possibly Gentoo, etc.)
Reviewed-by: Paul Dale <paul.dale@oracle.com>
Reviewed-by: Richard Levitte <levitte@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/8883)
---
crypto/perlasm/ppc-xlate.pl | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/crypto/perlasm/ppc-xlate.pl b/crypto/perlasm/ppc-xlate.pl
index e52f2f6ea6..5fcd0526df 100755
--- a/crypto/perlasm/ppc-xlate.pl
+++ b/crypto/perlasm/ppc-xlate.pl
@@ -49,7 +49,7 @@ my $globl = sub {
@ -49,7 +45,7 @@ index e52f2f6ea6..5fcd0526df 100755
my $mtspr = sub {
my ($f,$idx,$ra) = @_;
if ($idx == 256 && $no_vrsave) {
@@ -320,7 +320,7 @@ while($line=<>) {
@@ -318,7 +318,7 @@ while($line=<>) {
if ($label) {
my $xlated = ($GLOBALS{$label} or $label);
print "$xlated:";
@ -58,6 +54,3 @@ index e52f2f6ea6..5fcd0526df 100755
if ($TYPES{$label} =~ /function/) {
printf "\n.localentry %s,0\n",$xlated;
}
--
2.31.1

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@ -12,7 +12,7 @@ diff --git a/Configure b/Configure
index 5a699836f3..74d057c219 100755
--- a/Configure
+++ b/Configure
@@ -1545,7 +1545,9 @@ unless ($disabled{"crypto-mdebug-backtrace"})
@@ -1548,7 +1548,9 @@ unless ($disabled{"crypto-mdebug-backtrace"})
unless ($disabled{afalgeng}) {
$config{afalgeng}="";

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@ -55,6 +55,10 @@ config WOLFSSL_HAS_OPENVPN
bool "Include OpenVPN support"
default n
config WOLFSSL_ALT_NAMES
bool "Include SAN (Subject Alternative Name) support"
default y
config WOLFSSL_HAS_DEVCRYPTO
bool

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@ -32,7 +32,7 @@ PKG_CONFIG_DEPENDS:=\
CONFIG_WOLFSSL_HAS_ECC25519 CONFIG_WOLFSSL_HAS_OCSP \
CONFIG_WOLFSSL_HAS_SESSION_TICKET CONFIG_WOLFSSL_HAS_TLSV10 \
CONFIG_WOLFSSL_HAS_TLSV13 CONFIG_WOLFSSL_HAS_WPAS CONFIG_WOLFSSL_HAS_CERTGEN \
CONFIG_WOLFSSL_HAS_OPENVPN
CONFIG_WOLFSSL_HAS_OPENVPN CONFIG_WOLFSSL_ALT_NAMES
PKG_ABI_VERSION=$(patsubst %-stable,%,$(PKG_VERSION)).$(call version_abbrev,$(call confvar,$(PKG_CONFIG_DEPENDS)))
@ -64,7 +64,8 @@ TARGET_CFLAGS += \
-fomit-frame-pointer \
-flto \
-DFP_MAX_BITS=8192 \
-DWOLFSSL_ALT_CERT_CHAINS
-DWOLFSSL_ALT_CERT_CHAINS \
$(if $(CONFIG_WOLFSSL_ALT_NAMES),-DWOLFSSL_ALT_NAMES)
TARGET_LDFLAGS += -flto

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@ -12,7 +12,7 @@
else
--- a/hostapd/ctrl_iface.c
+++ b/hostapd/ctrl_iface.c
@@ -3569,6 +3569,7 @@ static int hostapd_ctrl_iface_receive_pr
@@ -3570,6 +3570,7 @@ static int hostapd_ctrl_iface_receive_pr
reply_size);
} else if (os_strcmp(buf, "STATUS-DRIVER") == 0) {
reply_len = hostapd_drv_status(hapd, reply, reply_size);
@ -20,7 +20,7 @@
} else if (os_strcmp(buf, "MIB") == 0) {
reply_len = ieee802_11_get_mib(hapd, reply, reply_size);
if (reply_len >= 0) {
@@ -3610,6 +3611,7 @@ static int hostapd_ctrl_iface_receive_pr
@@ -3611,6 +3612,7 @@ static int hostapd_ctrl_iface_receive_pr
} else if (os_strncmp(buf, "STA-NEXT ", 9) == 0) {
reply_len = hostapd_ctrl_iface_sta_next(hapd, buf + 9, reply,
reply_size);

View File

@ -31,7 +31,7 @@
};
enum hostapd_chan_status {
@@ -154,6 +155,7 @@ struct hostapd_data {
@@ -169,6 +170,7 @@ struct hostapd_data {
struct hostapd_iface *iface;
struct hostapd_config *iconf;
struct hostapd_bss_config *conf;
@ -39,7 +39,7 @@
int interface_added; /* virtual interface added for this BSS */
unsigned int started:1;
unsigned int disabled:1;
@@ -610,6 +612,7 @@ hostapd_alloc_bss_data(struct hostapd_if
@@ -628,6 +630,7 @@ hostapd_alloc_bss_data(struct hostapd_if
struct hostapd_bss_config *bss);
int hostapd_setup_interface(struct hostapd_iface *iface);
int hostapd_setup_interface_complete(struct hostapd_iface *iface, int err);
@ -515,7 +515,7 @@
--- a/src/ap/wnm_ap.c
+++ b/src/ap/wnm_ap.c
@@ -441,7 +441,8 @@ static void ieee802_11_rx_bss_trans_mgmt
@@ -442,7 +442,8 @@ static void ieee802_11_rx_bss_trans_mgmt
wpa_hexdump(MSG_DEBUG, "WNM: BSS Transition Candidate List Entries",
pos, end - pos);
@ -525,7 +525,7 @@
}
@@ -463,7 +464,7 @@ static void ieee802_11_rx_bss_trans_mgmt
@@ -464,7 +465,7 @@ static void ieee802_11_rx_bss_trans_mgmt
size_t len)
{
u8 dialog_token, status_code, bss_termination_delay;
@ -534,7 +534,7 @@
int enabled = hapd->conf->bss_transition;
struct sta_info *sta;
@@ -510,6 +511,7 @@ static void ieee802_11_rx_bss_trans_mgmt
@@ -511,6 +512,7 @@ static void ieee802_11_rx_bss_trans_mgmt
wpa_printf(MSG_DEBUG, "WNM: not enough room for Target BSSID field");
return;
}
@ -542,7 +542,7 @@
sta->agreed_to_steer = 1;
eloop_cancel_timeout(ap_sta_reset_steer_flag_timer, hapd, sta);
eloop_register_timeout(2, 0, ap_sta_reset_steer_flag_timer,
@@ -529,6 +531,10 @@ static void ieee802_11_rx_bss_trans_mgmt
@@ -530,6 +532,10 @@ static void ieee802_11_rx_bss_trans_mgmt
MAC2STR(addr), status_code, bss_termination_delay);
}

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@ -156,7 +156,7 @@
struct hostapd_config * (*config_read_cb)(const char *config_fname);
int (*ctrl_iface_init)(struct hostapd_data *hapd);
void (*ctrl_iface_deinit)(struct hostapd_data *hapd);
@@ -156,6 +156,7 @@ struct hostapd_data {
@@ -171,6 +171,7 @@ struct hostapd_data {
struct hostapd_config *iconf;
struct hostapd_bss_config *conf;
struct hostapd_ubus_bss ubus;
@ -164,7 +164,7 @@
int interface_added; /* virtual interface added for this BSS */
unsigned int started:1;
unsigned int disabled:1;
@@ -604,7 +605,7 @@ struct hostapd_iface {
@@ -622,7 +623,7 @@ struct hostapd_iface {
int hostapd_for_each_interface(struct hapd_interfaces *interfaces,
int (*cb)(struct hostapd_iface *iface,
void *ctx), void *ctx);

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@ -17,7 +17,7 @@
} else if (os_strcmp(buf, "extended_key_id") == 0) {
--- a/src/ap/hostapd.h
+++ b/src/ap/hostapd.h
@@ -648,6 +648,7 @@ void hostapd_cleanup_cs_params(struct ho
@@ -666,6 +666,7 @@ void hostapd_cleanup_cs_params(struct ho
void hostapd_periodic_iface(struct hostapd_iface *iface);
int hostapd_owe_trans_get_info(struct hostapd_data *hapd);
void hostapd_ocv_check_csa_sa_query(void *eloop_ctx, void *timeout_ctx);

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@ -0,0 +1,18 @@
--- a/Makefile
+++ b/Makefile
@@ -53,14 +53,13 @@ restool: $(OBJ)
%.1: %.md
pandoc --standalone --to man $^ -o $@
-install: restool scripts/ls-main scripts/ls-append-dpl scripts/ls-debug scripts/restool_completion.sh $(MANPAGE)
+install: restool scripts/ls-main scripts/ls-append-dpl scripts/ls-debug scripts/restool_completion.sh
install -D -m 755 restool $(DESTDIR)$(bindir)/restool
install -D -m 755 scripts/ls-main $(DESTDIR)$(bindir)/ls-main
install -D -m 755 scripts/ls-append-dpl $(DESTDIR)$(bindir)/ls-append-dpl
install -D -m 755 scripts/ls-debug $(DESTDIR)$(bindir)/ls-debug
$(foreach symlink, $(RESTOOL_SCRIPT_SYMLINKS), sh -c "cd $(DESTDIR)$(bindir) && ln -sf ls-main $(symlink)" ;)
install -D -m 755 scripts/restool_completion.sh $(DESTDIR)$(bindir_completion)/restool
- install -m 0644 -D $(MANPAGE) $(call get_manpage_destination,$(MANPAGE))
clean:
rm -f $(OBJ) $(MANPAGE) \

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@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=nftables
PKG_VERSION:=1.0.1
PKG_RELEASE:=1
PKG_RELEASE:=2
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://netfilter.org/projects/$(PKG_NAME)/files

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@ -0,0 +1,44 @@
From 07af4429241c9832a613cb8620331ac54257d9df Mon Sep 17 00:00:00 2001
From: Stijn Tintel <stijn@linux-ipv6.be>
Date: Tue, 21 Dec 2021 12:40:25 +0200
Subject: [PATCH] parser: allow quoted string in flowtable_expr_member
Devices with interface names starting with a digit can not be configured
in flowtables. Trying to do so throws the following error:
Error: syntax error, unexpected number, expecting comma or '}'
devices = { eth0, 6in4-wan6 };
This is however a perfectly valid interface name. Solve the issue by
allowing the use of quoted strings.
Suggested-by: Jo-Philipp Wich <jo@mein.io>
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
src/parser_bison.y | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/parser_bison.y b/src/parser_bison.y
index 16607bb7..1136ab91 100644
--- a/src/parser_bison.y
+++ b/src/parser_bison.y
@@ -2151,7 +2151,14 @@ flowtable_list_expr : flowtable_expr_member
| flowtable_list_expr COMMA opt_newline
;
-flowtable_expr_member : STRING
+flowtable_expr_member : QUOTED_STRING
+ {
+ $$ = constant_expr_alloc(&@$, &string_type,
+ BYTEORDER_HOST_ENDIAN,
+ strlen($1) * BITS_PER_BYTE, $1);
+ xfree($1);
+ }
+ | STRING
{
$$ = constant_expr_alloc(&@$, &string_type,
BYTEORDER_HOST_ENDIAN,
--
2.33.1

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@ -12,6 +12,8 @@ PKG_USE_MIPS16:=0
PKG_MAINTAINER:=Paul Spooren <mail@aparcar.org>
PKG_CONFIG_DEPENDS:=CONFIG_WOLFSSL_ALT_NAMES
include $(INCLUDE_DIR)/package.mk
define Package/px5g-wolfssl

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@ -203,8 +203,23 @@ int selfsigned(WC_RNG *rng, char **arg) {
strncpy(newCert.subject.org, val, CTC_NAME_SIZE);
else if (!strcmp(key, "OU"))
strncpy(newCert.subject.unit, val, CTC_NAME_SIZE);
else if (!strcmp(key, "CN"))
else if (!strcmp(key, "CN")) {
strncpy(newCert.subject.commonName, val, CTC_NAME_SIZE);
#ifdef WOLFSSL_ALT_NAMES
if(strlen(val) + 2 > 256) {
fprintf(stderr, "error: CN is too long: %s\n", val);
return 1;
}
newCert.altNames[0] = 0x30; //Sequence with one element
newCert.altNames[1] = strlen(val) + 2; // Length of entire sequence
newCert.altNames[2] = 0x82; //8 - String, 2 - DNS Name
newCert.altNames[3] = strlen(val); //DNS Name length
memcpy(newCert.altNames + 4, val, strlen(val)); //DNS Name
newCert.altNamesSz = strlen(val) + 4;
#endif
}
else if (!strcmp(key, "EMAIL"))
strncpy(newCert.subject.email, val, CTC_NAME_SIZE);
else
@ -216,6 +231,9 @@ int selfsigned(WC_RNG *rng, char **arg) {
}
newCert.daysValid = days;
newCert.keyUsage = KEYUSE_DIGITAL_SIG | KEYUSE_CONTENT_COMMIT | KEYUSE_KEY_ENCIPHER;
newCert.extKeyUsage = EXTKEYUSE_SERVER_AUTH;
gen_key(rng, &ecKey, &rsaKey, type, keySz, exp, curve);
write_key(&ecKey, &rsaKey, type, keySz, keypath, pem);

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@ -4,7 +4,7 @@ use strict;
use warnings;
use Cwd;
my (%targets, %architectures);
my (%targets, %architectures, %kernels);
$ENV{'TOPDIR'} = Cwd::getcwd();
@ -13,7 +13,7 @@ sub parse_targetinfo {
my ($target_dir, $subtarget) = @_;
if (open M, "make -C '$target_dir' --no-print-directory DUMP=1 TARGET_BUILD=1 SUBTARGET='$subtarget' |") {
my ($target_name, $target_arch, @target_features);
my ($target_name, $target_arch, $target_kernel, $target_testing_kernel, @target_features);
while (defined(my $line = readline M)) {
chomp $line;
@ -23,19 +23,32 @@ sub parse_targetinfo {
elsif ($line =~ /^Target-Arch-Packages: (.+)$/) {
$target_arch = $1;
}
elsif ($line =~ /^Linux-Version: (\d\.\d+)\.\d+$/) {
$target_kernel = $1;
}
elsif ($line =~ /^Linux-Testing-Version: (\d\.\d+)\.\d+$/) {
$target_testing_kernel = $1;
}
elsif ($line =~ /^Target-Features: (.+)$/) {
@target_features = split /\s+/, $1;
}
elsif ($line =~ /^@\@$/) {
if ($target_name && $target_arch &&
if ($target_name && $target_arch && $target_kernel &&
!grep { $_ eq 'broken' or $_ eq 'source-only' } @target_features) {
$targets{$target_name} = $target_arch;
$architectures{$target_arch} ||= [];
push @{$architectures{$target_arch}}, $target_name;
$kernels{$target_name} ||= [];
push @{$kernels{$target_name}}, $target_kernel;
if ($target_testing_kernel) {
push @{$kernels{$target_name}}, $target_testing_kernel;
}
}
undef $target_name;
undef $target_arch;
undef $target_kernel;
undef $target_testing_kernel;
@target_features = ();
}
}
@ -85,7 +98,14 @@ elsif (@ARGV == 1 && $ARGV[0] eq 'architectures') {
printf "%s %s\n", $target_arch, join ' ', @{$architectures{$target_arch}};
}
}
elsif (@ARGV == 1 && $ARGV[0] eq 'kernels') {
get_targetinfo();
foreach my $target_name (sort keys %targets) {
printf "%s %s\n", $target_name, join ' ', @{$kernels{$target_name}};
}
}
else {
print "Usage: $0 targets\n";
print "Usage: $0 architectures\n";
print "Usage: $0 kernels\n";
}

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@ -60,8 +60,8 @@
reg = <0x18030000 0x100>;
#phy-cells = <0>;
reset-names = "usb-phy", "usb-suspend-override";
resets = <&rst 4>, <&rst 3>;
reset-names = "usb-phy-analog", "usb-phy", "usb-suspend-override";
resets = <&rst 11>, <&rst 4>, <&rst 3>;
status = "disabled";
};

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@ -14,9 +14,7 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/mtd/mtd.h>
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
#include <linux/mtd/nand.h>
#endif
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
@ -722,11 +720,7 @@ static void ar934x_nfc_cmdfunc(struct nand_chip *nand, unsigned int command,
break;
case NAND_CMD_PAGEPROG:
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
#else
if (nand->ecc.mode == NAND_ECC_HW) {
#endif
/* the data is already written */
break;
}
@ -1334,29 +1328,15 @@ static int ar934x_nfc_attach_chip(struct nand_chip *nand)
if (mtd->writesize == 2048)
nand->options |= NAND_NO_SUBPAGE_WRITE;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
#else
if (nand->ecc.mode == NAND_ECC_HW) {
#endif
ret = ar934x_nfc_setup_hwecc(nfc);
if (ret)
return ret;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
} else if (nand->ecc.engine_type != NAND_ECC_ENGINE_TYPE_SOFT) {
dev_err(dev, "unknown ECC mode %d\n", nand->ecc.engine_type);
#else
} else if (nand->ecc.mode != NAND_ECC_SOFT) {
dev_err(dev, "unknown ECC mode %d\n", nand->ecc.mode);
#endif
return -EINVAL;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
} else if ((nand->ecc.algo != NAND_ECC_ALGO_BCH) &&
(nand->ecc.algo != NAND_ECC_ALGO_HAMMING)) {
#else
} else if ((nand->ecc.algo != NAND_ECC_BCH) &&
(nand->ecc.algo != NAND_ECC_HAMMING)) {
#endif
dev_err(dev, "unknown software ECC algo %d\n", nand->ecc.algo);
return -EINVAL;
}
@ -1445,11 +1425,7 @@ static int ar934x_nfc_probe(struct platform_device *pdev)
nand->legacy.read_byte = ar934x_nfc_read_byte;
nand->legacy.write_buf = ar934x_nfc_write_buf;
nand->legacy.read_buf = ar934x_nfc_read_buf;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; /* default */
#else
nand->ecc.mode = NAND_ECC_HW; /* default */
#endif
nand->priv = nfc;
platform_set_drvdata(pdev, nfc);
@ -1489,12 +1465,8 @@ static int ar934x_nfc_remove(struct platform_device *pdev)
nfc = platform_get_drvdata(pdev);
if (nfc) {
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
mtd_device_unregister(nand_to_mtd(&nfc->nand_chip));
nand_cleanup(&nfc->nand_chip);
#else
nand_release(&nfc->nand_chip);
#endif
ar934x_nfc_free_buf(nfc);
}

View File

@ -188,13 +188,8 @@ static int rb4xx_nand_probe(struct platform_device *pdev)
if (mtd->writesize == 512)
mtd_set_ooblayout(mtd, &rb4xx_nand_ecclayout_ops);
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
nand->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
nand->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
#else
nand->chip.ecc.mode = NAND_ECC_SOFT;
nand->chip.ecc.algo = NAND_ECC_HAMMING;
#endif
nand->chip.options = NAND_NO_SUBPAGE_WRITE;
nand->chip.priv = nand;
@ -211,12 +206,8 @@ static int rb4xx_nand_probe(struct platform_device *pdev)
ret = mtd_device_register(mtd, NULL, 0);
if (ret) {
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
mtd_device_unregister(nand_to_mtd(&nand->chip));
nand_cleanup(&nand->chip);
#else
nand_release(&nand->chip);
#endif
return ret;
}
@ -227,12 +218,8 @@ static int rb4xx_nand_remove(struct platform_device *pdev)
{
struct rb4xx_nand *nand = platform_get_drvdata(pdev);
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
mtd_device_unregister(nand_to_mtd(&nand->chip));
nand_cleanup(&nand->chip);
#else
nand_release(&nand->chip);
#endif
mtd_device_unregister(nand_to_mtd(&nand->chip));
nand_cleanup(&nand->chip);
return 0;
}

View File

@ -254,12 +254,8 @@ static void rb91x_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
static void rb91x_nand_release(struct rb91x_nand_drvdata *drvdata)
{
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
mtd_device_unregister(nand_to_mtd(&drvdata->chip));
nand_cleanup(&drvdata->chip);
#else
nand_release(&drvdata->chip);
#endif
}
static int rb91x_nand_probe(struct platform_device *pdev)
@ -304,13 +300,8 @@ static int rb91x_nand_probe(struct platform_device *pdev)
drvdata->chip.legacy.read_buf = rb91x_nand_read_buf;
drvdata->chip.legacy.chip_delay = 25;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
drvdata->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
drvdata->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
#else
drvdata->chip.ecc.mode = NAND_ECC_SOFT;
drvdata->chip.ecc.algo = NAND_ECC_HAMMING;
#endif
drvdata->chip.options = NAND_NO_SUBPAGE_WRITE;
r = nand_scan(&drvdata->chip, 1);

View File

@ -178,11 +178,7 @@ struct ag71xx {
struct phy_device *phy_dev;
void *phy_priv;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10,0)
phy_interface_t phy_if_mode;
#else
int phy_if_mode;
#endif
unsigned int link;
unsigned int speed;

View File

@ -1198,11 +1198,7 @@ static void ag71xx_oom_timer_handler(struct timer_list *t)
napi_schedule(&ag->napi);
}
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0)
static void ag71xx_tx_timeout(struct net_device *dev, unsigned int txqueue)
#else
static void ag71xx_tx_timeout(struct net_device *dev)
#endif
{
struct ag71xx *ag = netdev_priv(dev);
@ -1679,13 +1675,8 @@ static int ag71xx_probe(struct platform_device *pdev)
eth_random_addr(dev->dev_addr);
}
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10,0)
err = of_get_phy_mode(np, &ag->phy_if_mode);
if (err < 0) {
#else
ag->phy_if_mode = of_get_phy_mode(np);
if (ag->phy_if_mode < 0) {
#endif
dev_err(&pdev->dev, "missing phy-mode property in DT\n");
return ag->phy_if_mode;
}

View File

@ -21,7 +21,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -50,7 +50,8 @@ static const struct flash_info macronix_
@@ -51,7 +51,8 @@ static const struct flash_info macronix_
{ "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
{ "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },

View File

@ -527,24 +527,27 @@ $(eval $(call KernelPackage,sound-soc-hifiberry-dac))
define KernelPackage/sound-soc-hifiberry-dacplus
TITLE:=Support for HifiBerry DAC+ / DAC+ Pro
TITLE:=Support for HifiBerry DAC+ / DAC+ Pro / Amp2
KCONFIG:= \
CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS \
CONFIG_SND_SOC_PCM512x
CONFIG_SND_SOC_PCM512x \
CONFIG_SND_SOC_PCM512x_I2C
FILES:= \
$(LINUX_DIR)/drivers/clk/clk-hifiberry-dacpro.ko \
$(LINUX_DIR)/sound/soc/bcm/snd-soc-hifiberry-dacplus.ko \
$(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko
$(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \
$(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko
AUTOLOAD:=$(call AutoLoad,68,clk-hifiberry-dacpro snd-soc-pcm512x \
snd-soc-hifiberry-dacplus)
snd-soc-pcm512x-i2c snd-soc-hifiberry-dacplus)
DEPENDS:= \
kmod-sound-soc-bcm2835-i2s \
+kmod-i2c-bcm2835
+kmod-i2c-bcm2835 \
+kmod-regmap-i2c
$(call AddDepends/sound)
endef
define KernelPackage/sound-soc-hifiberry-dacplus/description
This package contains support for HifiBerry DAC+ / DAC+ Pro
This package contains support for HifiBerry DAC+ / DAC+ Pro / Amp2
endef
$(eval $(call KernelPackage,sound-soc-hifiberry-dacplus))

View File

@ -14,7 +14,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/net/usb/lan78xx.c
+++ b/drivers/net/usb/lan78xx.c
@@ -2461,6 +2461,11 @@ static int lan78xx_reset(struct lan78xx_
@@ -2463,6 +2463,11 @@ static int lan78xx_reset(struct lan78xx_
int ret = 0;
unsigned long timeout;
u8 sig;
@ -26,7 +26,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
ret = lan78xx_read_reg(dev, HW_CFG, &buf);
buf |= HW_CFG_LRST_;
@@ -2514,6 +2519,9 @@ static int lan78xx_reset(struct lan78xx_
@@ -2516,6 +2521,9 @@ static int lan78xx_reset(struct lan78xx_
ret = lan78xx_read_reg(dev, HW_CFG, &buf);
buf |= HW_CFG_MEF_;
@ -36,7 +36,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
ret = lan78xx_write_reg(dev, HW_CFG, buf);
ret = lan78xx_read_reg(dev, USB_CFG0, &buf);
@@ -2569,6 +2577,9 @@ static int lan78xx_reset(struct lan78xx_
@@ -2571,6 +2579,9 @@ static int lan78xx_reset(struct lan78xx_
buf |= MAC_CR_AUTO_DUPLEX_ | MAC_CR_AUTO_SPEED_;
}
}

View File

@ -15,7 +15,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/net/usb/lan78xx.c
+++ b/drivers/net/usb/lan78xx.c
@@ -2643,6 +2643,22 @@ static int lan78xx_open(struct net_devic
@@ -2645,6 +2645,22 @@ static int lan78xx_open(struct net_devic
netif_dbg(dev, ifup, dev->net, "phy initialised successfully");

View File

@ -21,7 +21,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
--- a/drivers/net/usb/lan78xx.c
+++ b/drivers/net/usb/lan78xx.c
@@ -425,6 +425,15 @@ static int msg_level = -1;
@@ -427,6 +427,15 @@ static int msg_level = -1;
module_param(msg_level, int, 0);
MODULE_PARM_DESC(msg_level, "Override default message level");
@ -37,7 +37,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
static int lan78xx_read_reg(struct lan78xx_net *dev, u32 index, u32 *data)
{
u32 *buf = kmalloc(sizeof(u32), GFP_KERNEL);
@@ -2925,8 +2934,14 @@ static int lan78xx_bind(struct lan78xx_n
@@ -2927,8 +2936,14 @@ static int lan78xx_bind(struct lan78xx_n
if (DEFAULT_RX_CSUM_ENABLE)
dev->net->features |= NETIF_F_RXCSUM;

View File

@ -16,7 +16,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/net/usb/lan78xx.c
+++ b/drivers/net/usb/lan78xx.c
@@ -2175,6 +2175,22 @@ static int lan78xx_phy_init(struct lan78
@@ -2177,6 +2177,22 @@ static int lan78xx_phy_init(struct lan78
mii_adv_to_linkmode_adv_t(fc, mii_adv);
linkmode_or(phydev->advertising, fc, phydev->advertising);
@ -39,7 +39,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
if (phydev->mdio.dev.of_node) {
u32 reg;
int len;
@@ -2652,22 +2668,6 @@ static int lan78xx_open(struct net_devic
@@ -2654,22 +2670,6 @@ static int lan78xx_open(struct net_devic
netif_dbg(dev, ifup, dev->net, "phy initialised successfully");

View File

@ -16,7 +16,7 @@ See: https://github.com/raspberrypi/linux/issues/2447
--- a/drivers/net/usb/lan78xx.c
+++ b/drivers/net/usb/lan78xx.c
@@ -434,6 +434,11 @@ static bool enable_tso;
@@ -436,6 +436,11 @@ static bool enable_tso;
module_param(enable_tso, bool, 0644);
MODULE_PARM_DESC(enable_tso, "Enables TCP segmentation offload");
@ -28,7 +28,7 @@ See: https://github.com/raspberrypi/linux/issues/2447
static int lan78xx_read_reg(struct lan78xx_net *dev, u32 index, u32 *data)
{
u32 *buf = kmalloc(sizeof(u32), GFP_KERNEL);
@@ -3768,7 +3773,13 @@ static int lan78xx_probe(struct usb_inte
@@ -3770,7 +3775,13 @@ static int lan78xx_probe(struct usb_inte
netdev->max_mtu = MAX_SINGLE_PACKET_SIZE;
netif_set_gso_max_size(netdev, MAX_SINGLE_PACKET_SIZE - MAX_HEADER);

View File

@ -15,7 +15,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/net/usb/lan78xx.c
+++ b/drivers/net/usb/lan78xx.c
@@ -2180,7 +2180,7 @@ static int lan78xx_phy_init(struct lan78
@@ -2182,7 +2182,7 @@ static int lan78xx_phy_init(struct lan78
mii_adv_to_linkmode_adv_t(fc, mii_adv);
linkmode_or(phydev->advertising, fc, phydev->advertising);

View File

@ -12,7 +12,7 @@ in both dwc_otg and in ipv6 processing.
--- a/drivers/net/usb/lan78xx.c
+++ b/drivers/net/usb/lan78xx.c
@@ -3169,7 +3169,7 @@ static int rx_submit(struct lan78xx_net
@@ -3171,7 +3171,7 @@ static int rx_submit(struct lan78xx_net
size_t size = dev->rx_urb_size;
int ret = 0;

View File

@ -14,7 +14,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -1300,7 +1300,7 @@ static int bcm2835_pinctrl_probe(struct
@@ -1314,7 +1314,7 @@ static int bcm2835_pinctrl_probe(struct
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
@ -22,4 +22,4 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+ err = devm_gpiochip_add_data(dev, &pc->gpio_chip, pc);
if (err) {
dev_err(dev, "could not add GPIO chip\n");
return err;
pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);

View File

@ -1,78 +0,0 @@
From 069990e0b524a7acdcfef0505913ee20401fec5a Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 6 Jan 2020 14:05:42 +0000
Subject: [PATCH] pinctrl: bcm2835: Change init order for gpio hogs
pinctrl-bcm2835 is a combined pinctrl/gpio driver. Currently the gpio
side is registered first, but this breaks gpio hogs (which are
configured during gpiochip_add_data). Part of the hog initialisation
is a call to pinctrl_gpio_request, and since the pinctrl driver hasn't
yet been registered this results in an -EPROBE_DEFER from which it can
never recover.
Change the initialisation sequence to register the pinctrl driver
first.
See: https://www.raspberrypi.org/forums/viewtopic.php?f=107&t=260600
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 29 +++++++++++++++------------
1 file changed, 16 insertions(+), 13 deletions(-)
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -1244,6 +1244,18 @@ static int bcm2835_pinctrl_probe(struct
raw_spin_lock_init(&pc->irq_lock[i]);
}
+ pc->pctl_desc = *pdata->pctl_desc;
+ pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
+ if (IS_ERR(pc->pctl_dev)) {
+ gpiochip_remove(&pc->gpio_chip);
+ return PTR_ERR(pc->pctl_dev);
+ }
+
+ pc->gpio_range = *pdata->gpio_range;
+ pc->gpio_range.base = pc->gpio_chip.base;
+ pc->gpio_range.gc = &pc->gpio_chip;
+ pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
+
girq = &pc->gpio_chip.irq;
girq->chip = &bcm2835_gpio_irq_chip;
girq->parent_handler = bcm2835_gpio_irq_handler;
@@ -1251,8 +1263,10 @@ static int bcm2835_pinctrl_probe(struct
girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
sizeof(*girq->parents),
GFP_KERNEL);
- if (!girq->parents)
+ if (!girq->parents) {
+ pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
return -ENOMEM;
+ }
if (is_7211) {
pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
@@ -1303,21 +1317,10 @@ static int bcm2835_pinctrl_probe(struct
err = devm_gpiochip_add_data(dev, &pc->gpio_chip, pc);
if (err) {
dev_err(dev, "could not add GPIO chip\n");
+ pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
return err;
}
- pc->pctl_desc = *pdata->pctl_desc;
- pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
- if (IS_ERR(pc->pctl_dev)) {
- gpiochip_remove(&pc->gpio_chip);
- return PTR_ERR(pc->pctl_dev);
- }
-
- pc->gpio_range = *pdata->gpio_range;
- pc->gpio_range.base = pc->gpio_chip.base;
- pc->gpio_range.gc = &pc->gpio_chip;
- pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
-
return 0;
}

View File

@ -20,7 +20,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
--- a/drivers/net/usb/lan78xx.c
+++ b/drivers/net/usb/lan78xx.c
@@ -1181,6 +1181,9 @@ static int lan78xx_link_reset(struct lan
@@ -1183,6 +1183,9 @@ static int lan78xx_link_reset(struct lan
if (unlikely(ret < 0))
return -EIO;

View File

@ -0,0 +1,27 @@
From 1027a42c25cbf8cfc4ade6503c5110aae04866af Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Daniel=20Gonz=C3=A1lez=20Cabanelas?= <dgcbueu@gmail.com>
Date: Fri, 16 Oct 2020 20:22:37 +0200
Subject: [PATCH] power: reset: linkstation-poweroff: add missing put_device()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The of_mdio_find_bus() takes a reference to the underlying device
structure, we should release that reference using a put_device() call.
Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
---
drivers/power/reset/linkstation-poweroff.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/power/reset/linkstation-poweroff.c
+++ b/drivers/power/reset/linkstation-poweroff.c
@@ -113,6 +113,7 @@ static int __init linkstation_poweroff_i
return -EPROBE_DEFER;
phydev = phy_find_first(bus);
+ put_device(&bus->dev);
if (!phydev)
return -EPROBE_DEFER;

View File

@ -0,0 +1,52 @@
From 02d6fdecb9c38de19065f6bed8d5214556fd061d Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Thu, 4 Nov 2021 16:00:40 +0100
Subject: regmap: allow to define reg_update_bits for no bus configuration
Some device requires a special handling for reg_update_bits and can't use
the normal regmap read write logic. An example is when locking is
handled by the device and rmw operations requires to do atomic operations.
Allow to declare a dedicated function in regmap_config for
reg_update_bits in no bus configuration.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20211104150040.1260-1-ansuelsmth@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
drivers/base/regmap/regmap.c | 1 +
include/linux/regmap.h | 7 +++++++
2 files changed, 8 insertions(+)
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -841,6 +841,7 @@ struct regmap *__regmap_init(struct devi
if (!bus) {
map->reg_read = config->reg_read;
map->reg_write = config->reg_write;
+ map->reg_update_bits = config->reg_update_bits;
map->defer_caching = false;
goto skip_format_initialization;
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -289,6 +289,11 @@ typedef void (*regmap_unlock)(void *);
* read operation on a bus such as SPI, I2C, etc. Most of the
* devices do not need this.
* @reg_write: Same as above for writing.
+ * @reg_update_bits: Optional callback that if filled will be used to perform
+ * all the update_bits(rmw) operation. Should only be provided
+ * if the function require special handling with lock and reg
+ * handling and the operation cannot be represented as a simple
+ * update_bits operation on a bus such as SPI, I2C, etc.
* @fast_io: Register IO is fast. Use a spinlock instead of a mutex
* to perform locking. This field is ignored if custom lock/unlock
* functions are used (see fields lock/unlock of struct regmap_config).
@@ -366,6 +371,8 @@ struct regmap_config {
int (*reg_read)(void *context, unsigned int reg, unsigned int *val);
int (*reg_write)(void *context, unsigned int reg, unsigned int val);
+ int (*reg_update_bits)(void *context, unsigned int reg,
+ unsigned int mask, unsigned int val);
bool fast_io;

View File

@ -819,7 +819,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
if (is_valid_ether_addr(hw_mac_addr)) {
--- a/drivers/net/ethernet/marvell/prestera/prestera_main.c
+++ b/drivers/net/ethernet/marvell/prestera/prestera_main.c
@@ -462,20 +462,17 @@ static int prestera_switch_set_base_mac_
@@ -466,20 +466,17 @@ static int prestera_switch_set_base_mac_
{
struct device_node *base_mac_np;
struct device_node *np;

View File

@ -0,0 +1,48 @@
From 3b00a07c2443745d62babfe08dbb2ad8e649526e Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Fri, 19 Nov 2021 03:03:49 +0100
Subject: [PATCH] net: dsa: qca8k: fix internal delay applied to the wrong PAD
config
With SGMII phy the internal delay is always applied to the PAD0 config.
This is caused by the falling edge configuration that hardcode the reg
to PAD0 (as the falling edge bits are present only in PAD0 reg)
Move the delay configuration before the reg overwrite to correctly apply
the delay.
Fixes: cef08115846e ("net: dsa: qca8k: set internal delay also for sgmii")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca8k.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1433,6 +1433,12 @@ qca8k_phylink_mac_config(struct dsa_swit
qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
+ /* From original code is reported port instability as SGMII also
+ * require delay set. Apply advised values here or take them from DT.
+ */
+ if (state->interface == PHY_INTERFACE_MODE_SGMII)
+ qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
+
/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
* falling edge is set writing in the PORT0 PAD reg
*/
@@ -1455,12 +1461,6 @@ qca8k_phylink_mac_config(struct dsa_swit
QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
val);
- /* From original code is reported port instability as SGMII also
- * require delay set. Apply advised values here or take them from DT.
- */
- if (state->interface == PHY_INTERFACE_MODE_SGMII)
- qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
-
break;
default:
dev_err(ds->dev, "xMII mode %s not supported for port %d\n",

View File

@ -0,0 +1,46 @@
From 65258b9d8cde45689bdc86ca39b50f01f983733b Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Fri, 19 Nov 2021 03:03:50 +0100
Subject: [PATCH] net: dsa: qca8k: fix MTU calculation
qca8k has a global MTU, so its tracking the MTU per port to make sure
that the largest MTU gets applied.
Since it uses the frame size instead of MTU the driver MTU change function
will then add the size of Ethernet header and checksum on top of MTU.
The driver currently populates the per port MTU size as Ethernet frame
length + checksum which equals 1518.
The issue is that then MTU change function will go through all of the
ports, find the largest MTU and apply the Ethernet header + checksum on
top of it again, so for a desired MTU of 1500 you will end up with 1536.
This is obviously incorrect, so to correct it populate the per port struct
MTU with just the MTU and not include the Ethernet header + checksum size
as those will be added by the MTU change function.
Fixes: f58d2598cf70 ("net: dsa: qca8k: implement the port MTU callbacks")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca8k.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1256,8 +1256,12 @@ qca8k_setup(struct dsa_switch *ds)
/* Set initial MTU for every port.
* We have only have a general MTU setting. So track
* every port and set the max across all port.
+ * Set per port MTU to 1500 as the MTU change function
+ * will add the overhead and if its set to 1518 then it
+ * will apply the overhead again and we will end up with
+ * MTU of 1536 instead of 1518
*/
- priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;
+ priv->port_mtu[i] = ETH_DATA_LEN;
}
/* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */

View File

@ -0,0 +1,29 @@
From b9133f3ef5a2659730cf47a74bd0a9259f1cf8ff Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 22 Nov 2021 16:23:40 +0100
Subject: net: dsa: qca8k: remove redundant check in parse_port_config
The very next check for port 0 and 6 already makes sure we don't go out
of bounds with the ports_config delay table.
Remove the redundant check.
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca8k.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -983,7 +983,7 @@ qca8k_parse_port_config(struct qca8k_pri
u32 delay;
/* We have 2 CPU port. Check them */
- for (port = 0; port < QCA8K_NUM_PORTS && cpu_port_index < QCA8K_NUM_CPU_PORTS; port++) {
+ for (port = 0; port < QCA8K_NUM_PORTS; port++) {
/* Skip every other port */
if (port != 0 && port != 6)
continue;

View File

@ -0,0 +1,508 @@
From 90ae68bfc2ffcb54a4ba4f64edbeb84a80cbb57c Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 22 Nov 2021 16:23:41 +0100
Subject: net: dsa: qca8k: convert to GENMASK/FIELD_PREP/FIELD_GET
Convert and try to standardize bit fields using
GENMASK/FIELD_PREP/FIELD_GET macros. Rework some logic to support the
standard macro and tidy things up. No functional change intended.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca8k.c | 98 +++++++++++++++----------------
drivers/net/dsa/qca8k.h | 153 ++++++++++++++++++++++++++----------------------
2 files changed, 130 insertions(+), 121 deletions(-)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -9,6 +9,7 @@
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/netdevice.h>
+#include <linux/bitfield.h>
#include <net/dsa.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
@@ -319,18 +320,18 @@ qca8k_fdb_read(struct qca8k_priv *priv,
}
/* vid - 83:72 */
- fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
+ fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);
/* aging - 67:64 */
- fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
+ fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]);
/* portmask - 54:48 */
- fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
+ fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]);
/* mac - 47:0 */
- fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
- fdb->mac[1] = reg[1] & 0xff;
- fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
- fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
- fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
- fdb->mac[5] = reg[0] & 0xff;
+ fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]);
+ fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]);
+ fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]);
+ fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]);
+ fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]);
+ fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]);
return 0;
}
@@ -343,18 +344,18 @@ qca8k_fdb_write(struct qca8k_priv *priv,
int i;
/* vid - 83:72 */
- reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
+ reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);
/* aging - 67:64 */
- reg[2] |= aging & QCA8K_ATU_STATUS_M;
+ reg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging);
/* portmask - 54:48 */
- reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
+ reg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask);
/* mac - 47:0 */
- reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
- reg[1] |= mac[1];
- reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
- reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
- reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
- reg[0] |= mac[5];
+ reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]);
+ reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]);
+ reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]);
+ reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]);
+ reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]);
+ reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);
/* load the array into the ARL table */
for (i = 0; i < 3; i++)
@@ -372,7 +373,7 @@ qca8k_fdb_access(struct qca8k_priv *priv
reg |= cmd;
if (port >= 0) {
reg |= QCA8K_ATU_FUNC_PORT_EN;
- reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
+ reg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port);
}
/* Write the function register triggering the table access */
@@ -454,7 +455,7 @@ qca8k_vlan_access(struct qca8k_priv *pri
/* Set the command and VLAN index */
reg = QCA8K_VTU_FUNC1_BUSY;
reg |= cmd;
- reg |= vid << QCA8K_VTU_FUNC1_VID_S;
+ reg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid);
/* Write the function register triggering the table access */
ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
@@ -500,13 +501,11 @@ qca8k_vlan_add(struct qca8k_priv *priv,
if (ret < 0)
goto out;
reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
- reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
+ reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
if (untagged)
- reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<
- QCA8K_VTU_FUNC0_EG_MODE_S(port);
+ reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port);
else
- reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
- QCA8K_VTU_FUNC0_EG_MODE_S(port);
+ reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port);
ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
if (ret)
@@ -534,15 +533,13 @@ qca8k_vlan_del(struct qca8k_priv *priv,
ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
if (ret < 0)
goto out;
- reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
- reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
- QCA8K_VTU_FUNC0_EG_MODE_S(port);
+ reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
+ reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port);
/* Check if we're the last member to be removed */
del = true;
for (i = 0; i < QCA8K_NUM_PORTS; i++) {
- mask = QCA8K_VTU_FUNC0_EG_MODE_NOT;
- mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);
+ mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
if ((reg & mask) != mask) {
del = false;
@@ -1014,7 +1011,7 @@ qca8k_parse_port_config(struct qca8k_pri
mode == PHY_INTERFACE_MODE_RGMII_TXID)
delay = 1;
- if (delay > QCA8K_MAX_DELAY) {
+ if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {
dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
delay = 3;
}
@@ -1030,7 +1027,7 @@ qca8k_parse_port_config(struct qca8k_pri
mode == PHY_INTERFACE_MODE_RGMII_RXID)
delay = 2;
- if (delay > QCA8K_MAX_DELAY) {
+ if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {
dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
delay = 3;
}
@@ -1141,8 +1138,8 @@ qca8k_setup(struct dsa_switch *ds)
/* Enable QCA header mode on all cpu ports */
if (dsa_is_cpu_port(ds, i)) {
ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
+ FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
+ FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
if (ret) {
dev_err(priv->dev, "failed enabling QCA header mode");
return ret;
@@ -1159,10 +1156,10 @@ qca8k_setup(struct dsa_switch *ds)
* for igmp, unknown, multicast and broadcast packet
*/
ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
- BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
- BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
- BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
- BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
if (ret)
return ret;
@@ -1180,8 +1177,6 @@ qca8k_setup(struct dsa_switch *ds)
/* Individual user ports get connected to CPU port only */
if (dsa_is_user_port(ds, i)) {
- int shift = 16 * (i % 2);
-
ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
QCA8K_PORT_LOOKUP_MEMBER,
BIT(cpu_port));
@@ -1198,8 +1193,8 @@ qca8k_setup(struct dsa_switch *ds)
* default egress vid
*/
ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
- 0xfff << shift,
- QCA8K_PORT_VID_DEF << shift);
+ QCA8K_EGREES_VLAN_PORT_MASK(i),
+ QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));
if (ret)
return ret;
@@ -1246,7 +1241,7 @@ qca8k_setup(struct dsa_switch *ds)
QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
QCA8K_PORT_HOL_CTRL1_WRED_EN;
qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
- QCA8K_PORT_HOL_CTRL1_ING_BUF |
+ QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
QCA8K_PORT_HOL_CTRL1_WRED_EN,
@@ -1269,8 +1264,8 @@ qca8k_setup(struct dsa_switch *ds)
mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
- QCA8K_GLOBAL_FC_GOL_XON_THRES_S |
- QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S,
+ QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
+ QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
mask);
}
@@ -1918,11 +1913,11 @@ qca8k_port_vlan_filtering(struct dsa_swi
if (vlan_filtering) {
qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
- QCA8K_PORT_LOOKUP_VLAN_MODE,
+ QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
} else {
qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
- QCA8K_PORT_LOOKUP_VLAN_MODE,
+ QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
}
@@ -1953,11 +1948,9 @@ qca8k_port_vlan_add(struct dsa_switch *d
dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
if (pvid) {
- int shift = 16 * (port % 2);
-
qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
- 0xfff << shift,
- vlan->vid_end << shift);
+ QCA8K_EGREES_VLAN_PORT_MASK(port),
+ QCA8K_EGREES_VLAN_PORT(port, vlan->vid_end));
qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
QCA8K_PORT_VLAN_CVID(vlan->vid_end) |
QCA8K_PORT_VLAN_SVID(vlan->vid_end));
@@ -2050,7 +2043,7 @@ static int qca8k_read_switch_id(struct q
if (ret < 0)
return -ENODEV;
- id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);
+ id = QCA8K_MASK_CTRL_DEVICE_ID(val);
if (id != data->id) {
dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id);
return -ENODEV;
@@ -2059,7 +2052,7 @@ static int qca8k_read_switch_id(struct q
priv->switch_id = id;
/* Save revision to communicate to the internal PHY driver */
- priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK);
+ priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val);
return 0;
}
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -30,9 +30,9 @@
/* Global control registers */
#define QCA8K_REG_MASK_CTRL 0x000
#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
-#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0)
+#define QCA8K_MASK_CTRL_REV_ID(x) FIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x)
#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
-#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
+#define QCA8K_MASK_CTRL_DEVICE_ID(x) FIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x)
#define QCA8K_REG_PORT0_PAD_CTRL 0x004
#define QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN BIT(31)
#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19)
@@ -41,12 +41,11 @@
#define QCA8K_REG_PORT6_PAD_CTRL 0x00c
#define QCA8K_PORT_PAD_RGMII_EN BIT(26)
#define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22)
-#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22)
+#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x)
#define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20)
-#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20)
+#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x)
#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25)
#define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
-#define QCA8K_MAX_DELAY 3
#define QCA8K_PORT_PAD_SGMII_EN BIT(7)
#define QCA8K_REG_PWS 0x010
#define QCA8K_PWS_POWER_ON_SEL BIT(31)
@@ -68,10 +67,12 @@
#define QCA8K_MDIO_MASTER_READ BIT(27)
#define QCA8K_MDIO_MASTER_WRITE 0
#define QCA8K_MDIO_MASTER_SUP_PRE BIT(26)
-#define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21)
-#define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16)
-#define QCA8K_MDIO_MASTER_DATA(x) (x)
+#define QCA8K_MDIO_MASTER_PHY_ADDR_MASK GENMASK(25, 21)
+#define QCA8K_MDIO_MASTER_PHY_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x)
+#define QCA8K_MDIO_MASTER_REG_ADDR_MASK GENMASK(20, 16)
+#define QCA8K_MDIO_MASTER_REG_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x)
#define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
+#define QCA8K_MDIO_MASTER_DATA(x) FIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x)
#define QCA8K_MDIO_MASTER_MAX_PORTS 5
#define QCA8K_MDIO_MASTER_MAX_REG 32
#define QCA8K_GOL_MAC_ADDR0 0x60
@@ -93,9 +94,7 @@
#define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
#define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
-#define QCA8K_PORT_HDR_CTRL_RX_S 2
#define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
-#define QCA8K_PORT_HDR_CTRL_TX_S 0
#define QCA8K_PORT_HDR_CTRL_ALL 2
#define QCA8K_PORT_HDR_CTRL_MGMT 1
#define QCA8K_PORT_HDR_CTRL_NONE 0
@@ -105,10 +104,11 @@
#define QCA8K_SGMII_EN_TX BIT(3)
#define QCA8K_SGMII_EN_SD BIT(4)
#define QCA8K_SGMII_CLK125M_DELAY BIT(7)
-#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23))
-#define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
-#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
-#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
+#define QCA8K_SGMII_MODE_CTRL_MASK GENMASK(23, 22)
+#define QCA8K_SGMII_MODE_CTRL(x) FIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x)
+#define QCA8K_SGMII_MODE_CTRL_BASEX QCA8K_SGMII_MODE_CTRL(0x0)
+#define QCA8K_SGMII_MODE_CTRL_PHY QCA8K_SGMII_MODE_CTRL(0x1)
+#define QCA8K_SGMII_MODE_CTRL_MAC QCA8K_SGMII_MODE_CTRL(0x2)
/* MAC_PWR_SEL registers */
#define QCA8K_REG_MAC_PWR_SEL 0x0e4
@@ -121,100 +121,115 @@
/* ACL registers */
#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
-#define QCA8K_PORT_VLAN_CVID(x) (x << 16)
-#define QCA8K_PORT_VLAN_SVID(x) x
+#define QCA8K_PORT_VLAN_CVID_MASK GENMASK(27, 16)
+#define QCA8K_PORT_VLAN_CVID(x) FIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x)
+#define QCA8K_PORT_VLAN_SVID_MASK GENMASK(11, 0)
+#define QCA8K_PORT_VLAN_SVID(x) FIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x)
#define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
#define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
#define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
/* Lookup registers */
#define QCA8K_REG_ATU_DATA0 0x600
-#define QCA8K_ATU_ADDR2_S 24
-#define QCA8K_ATU_ADDR3_S 16
-#define QCA8K_ATU_ADDR4_S 8
+#define QCA8K_ATU_ADDR2_MASK GENMASK(31, 24)
+#define QCA8K_ATU_ADDR3_MASK GENMASK(23, 16)
+#define QCA8K_ATU_ADDR4_MASK GENMASK(15, 8)
+#define QCA8K_ATU_ADDR5_MASK GENMASK(7, 0)
#define QCA8K_REG_ATU_DATA1 0x604
-#define QCA8K_ATU_PORT_M 0x7f
-#define QCA8K_ATU_PORT_S 16
-#define QCA8K_ATU_ADDR0_S 8
+#define QCA8K_ATU_PORT_MASK GENMASK(22, 16)
+#define QCA8K_ATU_ADDR0_MASK GENMASK(15, 8)
+#define QCA8K_ATU_ADDR1_MASK GENMASK(7, 0)
#define QCA8K_REG_ATU_DATA2 0x608
-#define QCA8K_ATU_VID_M 0xfff
-#define QCA8K_ATU_VID_S 8
-#define QCA8K_ATU_STATUS_M 0xf
+#define QCA8K_ATU_VID_MASK GENMASK(19, 8)
+#define QCA8K_ATU_STATUS_MASK GENMASK(3, 0)
#define QCA8K_ATU_STATUS_STATIC 0xf
#define QCA8K_REG_ATU_FUNC 0x60c
#define QCA8K_ATU_FUNC_BUSY BIT(31)
#define QCA8K_ATU_FUNC_PORT_EN BIT(14)
#define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
#define QCA8K_ATU_FUNC_FULL BIT(12)
-#define QCA8K_ATU_FUNC_PORT_M 0xf
-#define QCA8K_ATU_FUNC_PORT_S 8
+#define QCA8K_ATU_FUNC_PORT_MASK GENMASK(11, 8)
#define QCA8K_REG_VTU_FUNC0 0x610
#define QCA8K_VTU_FUNC0_VALID BIT(20)
#define QCA8K_VTU_FUNC0_IVL_EN BIT(19)
-#define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
-#define QCA8K_VTU_FUNC0_EG_MODE_MASK 3
-#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0
-#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1
-#define QCA8K_VTU_FUNC0_EG_MODE_TAG 2
-#define QCA8K_VTU_FUNC0_EG_MODE_NOT 3
+/* QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(17, 4)
+ * It does contain VLAN_MODE for each port [5:4] for port0,
+ * [7:6] for port1 ... [17:16] for port6. Use virtual port
+ * define to handle this.
+ */
+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i) (4 + (_i) * 2)
+#define QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(1, 0)
+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i) (GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
+#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0)
+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
+#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1)
+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
+#define QCA8K_VTU_FUNC0_EG_MODE_TAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2)
+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
+#define QCA8K_VTU_FUNC0_EG_MODE_NOT FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3)
+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i) (QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
#define QCA8K_REG_VTU_FUNC1 0x614
#define QCA8K_VTU_FUNC1_BUSY BIT(31)
-#define QCA8K_VTU_FUNC1_VID_S 16
+#define QCA8K_VTU_FUNC1_VID_MASK GENMASK(27, 16)
#define QCA8K_VTU_FUNC1_FULL BIT(4)
#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
-#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24
-#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16
-#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8
-#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
+#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24)
+#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16)
+#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK GENMASK(14, 8)
+#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK GENMASK(6, 0)
#define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
#define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
-#define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8)
-#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8)
-#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8)
-#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8)
-#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8)
+#define QCA8K_PORT_LOOKUP_VLAN_MODE_MASK GENMASK(9, 8)
+#define QCA8K_PORT_LOOKUP_VLAN_MODE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x)
+#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE QCA8K_PORT_LOOKUP_VLAN_MODE(0x0)
+#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK QCA8K_PORT_LOOKUP_VLAN_MODE(0x1)
+#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK QCA8K_PORT_LOOKUP_VLAN_MODE(0x2)
+#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE QCA8K_PORT_LOOKUP_VLAN_MODE(0x3)
#define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
-#define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
-#define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16)
-#define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16)
-#define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16)
-#define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16)
-#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
+#define QCA8K_PORT_LOOKUP_STATE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x)
+#define QCA8K_PORT_LOOKUP_STATE_DISABLED QCA8K_PORT_LOOKUP_STATE(0x0)
+#define QCA8K_PORT_LOOKUP_STATE_BLOCKING QCA8K_PORT_LOOKUP_STATE(0x1)
+#define QCA8K_PORT_LOOKUP_STATE_LISTENING QCA8K_PORT_LOOKUP_STATE(0x2)
+#define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3)
+#define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4)
#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
#define QCA8K_REG_GLOBAL_FC_THRESH 0x800
-#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16)
-#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16)
-#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0)
-#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0)
+#define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK GENMASK(24, 16)
+#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)
+#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK GENMASK(8, 0)
+#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x)
#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
-#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0)
-#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0)
-#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4)
-#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4)
-#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8)
-#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8)
-#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12)
-#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12)
-#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16)
-#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16)
-#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20)
-#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20)
-#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24)
-#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24)
+#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK GENMASK(3, 0)
+#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x)
+#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK GENMASK(7, 4)
+#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x)
+#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK GENMASK(11, 8)
+#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x)
+#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK GENMASK(15, 12)
+#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x)
+#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK GENMASK(19, 16)
+#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x)
+#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK GENMASK(23, 20)
+#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x)
+#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK GENMASK(29, 24)
+#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x)
#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
-#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0)
-#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0)
+#define QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK GENMASK(3, 0)
+#define QCA8K_PORT_HOL_CTRL1_ING(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x)
#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8)
#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
/* Pkt edit registers */
+#define QCA8K_EGREES_VLAN_PORT_SHIFT(_i) (16 * ((_i) % 2))
+#define QCA8K_EGREES_VLAN_PORT_MASK(_i) (GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
+#define QCA8K_EGREES_VLAN_PORT(_i, x) ((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
#define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
/* L3 registers */

View File

@ -0,0 +1,25 @@
From 994c28b6f971fa5db8ae977daea37eee87d93d51 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 22 Nov 2021 16:23:42 +0100
Subject: net: dsa: qca8k: remove extra mutex_init in qca8k_setup
Mutex is already init in sw_probe. Remove the extra init in qca8k_setup.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca8k.c | 2 --
1 file changed, 2 deletions(-)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1086,8 +1086,6 @@ qca8k_setup(struct dsa_switch *ds)
if (ret)
return ret;
- mutex_init(&priv->reg_mutex);
-
/* Start by setting up the register mapping */
priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
&qca8k_regmap_config);

View File

@ -0,0 +1,46 @@
From 36b8af12f424e7a7f60a935c60a0fd4aa0822378 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 22 Nov 2021 16:23:43 +0100
Subject: net: dsa: qca8k: move regmap init in probe and set it mandatory
In preparation for regmap conversion, move regmap init in the probe
function and make it mandatory as any read/write/rmw operation will be
converted to regmap API.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca8k.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1086,12 +1086,6 @@ qca8k_setup(struct dsa_switch *ds)
if (ret)
return ret;
- /* Start by setting up the register mapping */
- priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
- &qca8k_regmap_config);
- if (IS_ERR(priv->regmap))
- dev_warn(priv->dev, "regmap initialization failed");
-
ret = qca8k_setup_mdio_bus(priv);
if (ret)
return ret;
@@ -2085,6 +2079,14 @@ qca8k_sw_probe(struct mdio_device *mdiod
gpiod_set_value_cansleep(priv->reset_gpio, 0);
}
+ /* Start by setting up the register mapping */
+ priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv,
+ &qca8k_regmap_config);
+ if (IS_ERR(priv->regmap)) {
+ dev_err(priv->dev, "regmap initialization failed");
+ return PTR_ERR(priv->regmap);
+ }
+
/* Check the detected switch id */
ret = qca8k_read_switch_id(priv);
if (ret)

View File

@ -0,0 +1,249 @@
From 8b5f3f29a81a71934d004e21a1292c1148b05926 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 22 Nov 2021 16:23:44 +0100
Subject: net: dsa: qca8k: initial conversion to regmap helper
Convert any qca8k set/clear/pool to regmap helper and add
missing config to regmap_config struct.
Read/write/rmw operation are reworked to use the regmap helper
internally to keep the delta of this patch low. These additional
function will then be dropped when the code split will be proposed.
Ipq40xx SoC have the internal switch based on the qca8k regmap but use
mmio for read/write/rmw operation instead of mdio.
In preparation for the support of this internal switch, convert the
driver to regmap API to later split the driver to common and specific
code. The overhead introduced by the use of regamp API is marginal as the
internal mdio will bypass it by using its direct access and regmap will be
used only by configuration functions or fdb access.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca8k.c | 107 +++++++++++++++++++++---------------------------
1 file changed, 47 insertions(+), 60 deletions(-)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -10,6 +10,7 @@
#include <linux/phy.h>
#include <linux/netdevice.h>
#include <linux/bitfield.h>
+#include <linux/regmap.h>
#include <net/dsa.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
@@ -152,6 +153,25 @@ qca8k_set_page(struct mii_bus *bus, u16
static int
qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
{
+ return regmap_read(priv->regmap, reg, val);
+}
+
+static int
+qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
+{
+ return regmap_write(priv->regmap, reg, val);
+}
+
+static int
+qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
+{
+ return regmap_update_bits(priv->regmap, reg, mask, write_val);
+}
+
+static int
+qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
+{
+ struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
struct mii_bus *bus = priv->bus;
u16 r1, r2, page;
int ret;
@@ -172,8 +192,9 @@ exit:
}
static int
-qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
+qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
{
+ struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
struct mii_bus *bus = priv->bus;
u16 r1, r2, page;
int ret;
@@ -194,8 +215,9 @@ exit:
}
static int
-qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
+qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)
{
+ struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
struct mii_bus *bus = priv->bus;
u16 r1, r2, page;
u32 val;
@@ -223,34 +245,6 @@ exit:
return ret;
}
-static int
-qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
-{
- return qca8k_rmw(priv, reg, 0, val);
-}
-
-static int
-qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
-{
- return qca8k_rmw(priv, reg, val, 0);
-}
-
-static int
-qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
-{
- struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
-
- return qca8k_read(priv, reg, val);
-}
-
-static int
-qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
-{
- struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
-
- return qca8k_write(priv, reg, val);
-}
-
static const struct regmap_range qca8k_readable_ranges[] = {
regmap_reg_range(0x0000, 0x00e4), /* Global control */
regmap_reg_range(0x0100, 0x0168), /* EEE control */
@@ -282,26 +276,19 @@ static struct regmap_config qca8k_regmap
.max_register = 0x16ac, /* end MIB - Port6 range */
.reg_read = qca8k_regmap_read,
.reg_write = qca8k_regmap_write,
+ .reg_update_bits = qca8k_regmap_update_bits,
.rd_table = &qca8k_readable_table,
+ .disable_locking = true, /* Locking is handled by qca8k read/write */
+ .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */
};
static int
qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
{
- int ret, ret1;
u32 val;
- ret = read_poll_timeout(qca8k_read, ret1, !(val & mask),
- 0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
- priv, reg, &val);
-
- /* Check if qca8k_read has failed for a different reason
- * before returning -ETIMEDOUT
- */
- if (ret < 0 && ret1 < 0)
- return ret1;
-
- return ret;
+ return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0,
+ QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC);
}
static int
@@ -568,7 +555,7 @@ qca8k_mib_init(struct qca8k_priv *priv)
int ret;
mutex_lock(&priv->reg_mutex);
- ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
+ ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
if (ret)
goto exit;
@@ -576,7 +563,7 @@ qca8k_mib_init(struct qca8k_priv *priv)
if (ret)
goto exit;
- ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
+ ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
if (ret)
goto exit;
@@ -597,9 +584,9 @@ qca8k_port_set_status(struct qca8k_priv
mask |= QCA8K_PORT_STATUS_LINK_AUTO;
if (enable)
- qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
+ regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
else
- qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
+ regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
}
static u32
@@ -861,8 +848,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *
* a dt-overlay and driver reload changed the configuration
*/
- return qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
- QCA8K_MDIO_MASTER_EN);
+ return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL,
+ QCA8K_MDIO_MASTER_EN);
}
/* Check if the devicetree declare the port:phy mapping */
@@ -1099,16 +1086,16 @@ qca8k_setup(struct dsa_switch *ds)
return ret;
/* Make sure MAC06 is disabled */
- ret = qca8k_reg_clear(priv, QCA8K_REG_PORT0_PAD_CTRL,
- QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
+ ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,
+ QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
if (ret) {
dev_err(priv->dev, "failed disabling MAC06 exchange");
return ret;
}
/* Enable CPU Port */
- ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
- QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
+ ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
+ QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
if (ret) {
dev_err(priv->dev, "failed enabling CPU port");
return ret;
@@ -1176,8 +1163,8 @@ qca8k_setup(struct dsa_switch *ds)
return ret;
/* Enable ARP Auto-learning by default */
- ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
- QCA8K_PORT_LOOKUP_LEARN);
+ ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i),
+ QCA8K_PORT_LOOKUP_LEARN);
if (ret)
return ret;
@@ -1745,9 +1732,9 @@ qca8k_port_bridge_join(struct dsa_switch
/* Add this port to the portvlan mask of the other ports
* in the bridge
*/
- ret = qca8k_reg_set(priv,
- QCA8K_PORT_LOOKUP_CTRL(i),
- BIT(port));
+ ret = regmap_set_bits(priv->regmap,
+ QCA8K_PORT_LOOKUP_CTRL(i),
+ BIT(port));
if (ret)
return ret;
if (i != port)
@@ -1777,9 +1764,9 @@ qca8k_port_bridge_leave(struct dsa_switc
/* Remove this port to the portvlan mask of the other ports
* in the bridge
*/
- qca8k_reg_clear(priv,
- QCA8K_PORT_LOOKUP_CTRL(i),
- BIT(port));
+ regmap_clear_bits(priv->regmap,
+ QCA8K_PORT_LOOKUP_CTRL(i),
+ BIT(port));
}
/* Set the cpu port to be the only one in the portvlan mask of

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@ -0,0 +1,120 @@
From c126f118b330ccf0db0dda4a4bd6c729865a205f Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 22 Nov 2021 16:23:45 +0100
Subject: net: dsa: qca8k: add additional MIB counter and make it dynamic
We are currently missing 2 additionals MIB counter present in QCA833x
switch.
QC832x switch have 39 MIB counter and QCA833X have 41 MIB counter.
Add the additional MIB counter and rework the MIB function to print the
correct supported counter from the match_data struct.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca8k.c | 23 ++++++++++++++++++++---
drivers/net/dsa/qca8k.h | 4 ++++
2 files changed, 24 insertions(+), 3 deletions(-)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -70,6 +70,8 @@ static const struct qca8k_mib_desc ar832
MIB_DESC(1, 0x9c, "TxExcDefer"),
MIB_DESC(1, 0xa0, "TxDefer"),
MIB_DESC(1, 0xa4, "TxLateCol"),
+ MIB_DESC(1, 0xa8, "RXUnicast"),
+ MIB_DESC(1, 0xac, "TXUnicast"),
};
/* The 32bit switch registers are accessed indirectly. To achieve this we need
@@ -1605,12 +1607,16 @@ qca8k_phylink_mac_link_up(struct dsa_swi
static void
qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
{
+ const struct qca8k_match_data *match_data;
+ struct qca8k_priv *priv = ds->priv;
int i;
if (stringset != ETH_SS_STATS)
return;
- for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
+ match_data = of_device_get_match_data(priv->dev);
+
+ for (i = 0; i < match_data->mib_count; i++)
strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
ETH_GSTRING_LEN);
}
@@ -1620,12 +1626,15 @@ qca8k_get_ethtool_stats(struct dsa_switc
uint64_t *data)
{
struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
+ const struct qca8k_match_data *match_data;
const struct qca8k_mib_desc *mib;
u32 reg, i, val;
u32 hi = 0;
int ret;
- for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
+ match_data = of_device_get_match_data(priv->dev);
+
+ for (i = 0; i < match_data->mib_count; i++) {
mib = &ar8327_mib[i];
reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
@@ -1648,10 +1657,15 @@ qca8k_get_ethtool_stats(struct dsa_switc
static int
qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
{
+ const struct qca8k_match_data *match_data;
+ struct qca8k_priv *priv = ds->priv;
+
if (sset != ETH_SS_STATS)
return 0;
- return ARRAY_SIZE(ar8327_mib);
+ match_data = of_device_get_match_data(priv->dev);
+
+ return match_data->mib_count;
}
static int
@@ -2146,14 +2160,17 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
static const struct qca8k_match_data qca8327 = {
.id = QCA8K_ID_QCA8327,
.reduced_package = true,
+ .mib_count = QCA8K_QCA832X_MIB_COUNT,
};
static const struct qca8k_match_data qca8328 = {
.id = QCA8K_ID_QCA8327,
+ .mib_count = QCA8K_QCA832X_MIB_COUNT,
};
static const struct qca8k_match_data qca833x = {
.id = QCA8K_ID_QCA8337,
+ .mib_count = QCA8K_QCA833X_MIB_COUNT,
};
static const struct of_device_id qca8k_of_match[] = {
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -21,6 +21,9 @@
#define PHY_ID_QCA8337 0x004dd036
#define QCA8K_ID_QCA8337 0x13
+#define QCA8K_QCA832X_MIB_COUNT 39
+#define QCA8K_QCA833X_MIB_COUNT 41
+
#define QCA8K_BUSY_WAIT_TIMEOUT 2000
#define QCA8K_NUM_FDB_RECORDS 2048
@@ -279,6 +282,7 @@ struct ar8xxx_port_status {
struct qca8k_match_data {
u8 id;
bool reduced_package;
+ u8 mib_count;
};
enum {

View File

@ -0,0 +1,53 @@
From 4592538bfb0d5d3c3c8a1d7071724d081412ac91 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 22 Nov 2021 16:23:46 +0100
Subject: net: dsa: qca8k: add support for port fast aging
The switch supports fast aging by flushing any rule in the ARL
table for a specific port.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca8k.c | 11 +++++++++++
drivers/net/dsa/qca8k.h | 1 +
2 files changed, 12 insertions(+)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1790,6 +1790,16 @@ qca8k_port_bridge_leave(struct dsa_switc
QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));
}
+static void
+qca8k_port_fast_age(struct dsa_switch *ds, int port)
+{
+ struct qca8k_priv *priv = ds->priv;
+
+ mutex_lock(&priv->reg_mutex);
+ qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port);
+ mutex_unlock(&priv->reg_mutex);
+}
+
static int
qca8k_port_enable(struct dsa_switch *ds, int port,
struct phy_device *phy)
@@ -2005,6 +2015,7 @@ static const struct dsa_switch_ops qca8k
.port_stp_state_set = qca8k_port_stp_state_set,
.port_bridge_join = qca8k_port_bridge_join,
.port_bridge_leave = qca8k_port_bridge_leave,
+ .port_fast_age = qca8k_port_fast_age,
.port_fdb_add = qca8k_port_fdb_add,
.port_fdb_del = qca8k_port_fdb_del,
.port_fdb_dump = qca8k_port_fdb_dump,
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -262,6 +262,7 @@ enum qca8k_fdb_cmd {
QCA8K_FDB_FLUSH = 1,
QCA8K_FDB_LOAD = 2,
QCA8K_FDB_PURGE = 3,
+ QCA8K_FDB_FLUSH_PORT = 5,
QCA8K_FDB_NEXT = 6,
QCA8K_FDB_SEARCH = 7,
};

View File

@ -0,0 +1,78 @@
From 6a3bdc5209f45d2af83aa92433ab6e5cf2297aa4 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 22 Nov 2021 16:23:47 +0100
Subject: net: dsa: qca8k: add set_ageing_time support
qca8k support setting ageing time in step of 7s. Add support for it and
set the max value accepted of 7645m.
Documentation talks about support for 10000m but that values doesn't
make sense as the value doesn't match the max value in the reg.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca8k.c | 25 +++++++++++++++++++++++++
drivers/net/dsa/qca8k.h | 3 +++
2 files changed, 28 insertions(+)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1261,6 +1261,10 @@ qca8k_setup(struct dsa_switch *ds)
/* We don't have interrupts for link changes, so we need to poll */
ds->pcs_poll = true;
+ /* Set min a max ageing value supported */
+ ds->ageing_time_min = 7000;
+ ds->ageing_time_max = 458745000;
+
return 0;
}
@@ -1801,6 +1805,26 @@ qca8k_port_fast_age(struct dsa_switch *d
}
static int
+qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
+{
+ struct qca8k_priv *priv = ds->priv;
+ unsigned int secs = msecs / 1000;
+ u32 val;
+
+ /* AGE_TIME reg is set in 7s step */
+ val = secs / 7;
+
+ /* Handle case with 0 as val to NOT disable
+ * learning
+ */
+ if (!val)
+ val = 1;
+
+ return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, QCA8K_ATU_AGE_TIME_MASK,
+ QCA8K_ATU_AGE_TIME(val));
+}
+
+static int
qca8k_port_enable(struct dsa_switch *ds, int port,
struct phy_device *phy)
{
@@ -2006,6 +2030,7 @@ static const struct dsa_switch_ops qca8k
.get_strings = qca8k_get_strings,
.get_ethtool_stats = qca8k_get_ethtool_stats,
.get_sset_count = qca8k_get_sset_count,
+ .set_ageing_time = qca8k_set_ageing_time,
.get_mac_eee = qca8k_get_mac_eee,
.set_mac_eee = qca8k_set_mac_eee,
.port_enable = qca8k_port_enable,
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -175,6 +175,9 @@
#define QCA8K_VTU_FUNC1_BUSY BIT(31)
#define QCA8K_VTU_FUNC1_VID_MASK GENMASK(27, 16)
#define QCA8K_VTU_FUNC1_FULL BIT(4)
+#define QCA8K_REG_ATU_CTRL 0x618
+#define QCA8K_ATU_AGE_TIME_MASK GENMASK(15, 0)
+#define QCA8K_ATU_AGE_TIME(x) FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624

View File

@ -0,0 +1,142 @@
From ba8f870dfa635113ce6e8095a5eb1835ecde2e9e Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 22 Nov 2021 16:23:48 +0100
Subject: net: dsa: qca8k: add support for mdb_add/del
Add support for mdb add/del function. The ARL table is used to insert
the rule. The rule will be searched, deleted and reinserted with the
port mask updated. The function will check if the rule has to be updated
or insert directly with no deletion of the old rule.
If every port is removed from the port mask, the rule is removed.
The rule is set STATIC in the ARL table (aka it doesn't age) to not be
flushed by fast age function.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca8k.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -436,6 +436,81 @@ qca8k_fdb_flush(struct qca8k_priv *priv)
}
static int
+qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask,
+ const u8 *mac, u16 vid)
+{
+ struct qca8k_fdb fdb = { 0 };
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+
+ qca8k_fdb_write(priv, vid, 0, mac, 0);
+ ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);
+ if (ret < 0)
+ goto exit;
+
+ ret = qca8k_fdb_read(priv, &fdb);
+ if (ret < 0)
+ goto exit;
+
+ /* Rule exist. Delete first */
+ if (!fdb.aging) {
+ ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
+ if (ret)
+ goto exit;
+ }
+
+ /* Add port to fdb portmask */
+ fdb.port_mask |= port_mask;
+
+ qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);
+ ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+ return ret;
+}
+
+static int
+qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask,
+ const u8 *mac, u16 vid)
+{
+ struct qca8k_fdb fdb = { 0 };
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+
+ qca8k_fdb_write(priv, vid, 0, mac, 0);
+ ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);
+ if (ret < 0)
+ goto exit;
+
+ /* Rule doesn't exist. Why delete? */
+ if (!fdb.aging) {
+ ret = -EINVAL;
+ goto exit;
+ }
+
+ ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
+ if (ret)
+ goto exit;
+
+ /* Only port in the rule is this port. Don't re insert */
+ if (fdb.port_mask == port_mask)
+ goto exit;
+
+ /* Remove port from port mask */
+ fdb.port_mask &= ~port_mask;
+
+ qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);
+ ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+ return ret;
+}
+
+static int
qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
{
u32 reg;
@@ -1929,6 +2004,28 @@ qca8k_port_fdb_dump(struct dsa_switch *d
return 0;
}
+static void
+qca8k_port_mdb_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb)
+{
+ struct qca8k_priv *priv = ds->priv;
+ const u8 *addr = mdb->addr;
+ u16 vid = mdb->vid;
+
+ qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid);
+}
+
+static int
+qca8k_port_mdb_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb)
+{
+ struct qca8k_priv *priv = ds->priv;
+ const u8 *addr = mdb->addr;
+ u16 vid = mdb->vid;
+
+ return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid);
+}
+
static int
qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
struct switchdev_trans *trans)
@@ -2044,6 +2141,8 @@ static const struct dsa_switch_ops qca8k
.port_fdb_add = qca8k_port_fdb_add,
.port_fdb_del = qca8k_port_fdb_del,
.port_fdb_dump = qca8k_port_fdb_dump,
+ .port_mdb_add = qca8k_port_mdb_add,
+ .port_mdb_del = qca8k_port_mdb_del,
.port_vlan_filtering = qca8k_port_vlan_filtering,
.port_vlan_prepare = qca8k_port_vlan_prepare,
.port_vlan_add = qca8k_port_vlan_add,

View File

@ -0,0 +1,199 @@
From a7f79f99541eff4e6bcae0014eb08d3019337565 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Daniel=20Gonz=C3=A1lez=20Cabanelas?= <dgcbueu@gmail.com>
Date: Wed, 15 Jul 2020 15:35:14 +0200
Subject: [PATCH] power: reset: add driver for LinkStation power off
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Some Buffalo LinkStations perform the power off operation, at restart
time, depending on the state of an output pin (LED2/INTn) at the ethernet
PHY. This pin is also used to wake the machine when a WoL packet is
received by the PHY.
The driver is required by the Buffalo LinkStation LS421DE (ARM MVEBU),
and other models. Without it, the board remains forever halted if a
power off command is executed, unless the PSU is disconnected and
connected again.
Add the driver to provide the power off function and also make the WoL
feature to be available.
Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/power/reset/Kconfig | 11 ++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/linkstation-poweroff.c | 136 +++++++++++++++++++++
3 files changed, 148 insertions(+)
create mode 100644 drivers/power/reset/linkstation-poweroff.c
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -99,6 +99,17 @@ config POWER_RESET_HISI
help
Reboot support for Hisilicon boards.
+config POWER_RESET_LINKSTATION
+ tristate "Buffalo LinkStation power-off driver"
+ depends on ARCH_MVEBU || COMPILE_TEST
+ depends on OF_MDIO && PHYLIB
+ help
+ This driver supports turning off some Buffalo LinkStations by
+ setting an output pin at the ethernet PHY to the correct state.
+ It also makes the device compatible with the WoL function.
+
+ Say Y here if you have a Buffalo LinkStation LS421D/E.
+
config POWER_RESET_MSM
bool "Qualcomm MSM power-off driver"
depends on ARCH_QCOM
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_POWER_RESET_GEMINI_POWEROFF
obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
obj-$(CONFIG_POWER_RESET_GPIO_RESTART) += gpio-restart.o
obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o
+obj-${CONFIG_POWER_RESET_LINKSTATION} += linkstation-poweroff.o
obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
obj-$(CONFIG_POWER_RESET_QCOM_PON) += qcom-pon.o
obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o
--- /dev/null
+++ b/drivers/power/reset/linkstation-poweroff.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * LinkStation power off restart driver
+ * Copyright (C) 2020 Daniel González Cabanelas <dgcbueu@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/notifier.h>
+#include <linux/of.h>
+#include <linux/of_mdio.h>
+#include <linux/of_platform.h>
+#include <linux/reboot.h>
+#include <linux/phy.h>
+
+/* Defines from the eth phy Marvell driver */
+#define MII_MARVELL_COPPER_PAGE 0
+#define MII_MARVELL_LED_PAGE 3
+#define MII_MARVELL_WOL_PAGE 17
+#define MII_MARVELL_PHY_PAGE 22
+
+#define MII_PHY_LED_CTRL 16
+#define MII_88E1318S_PHY_LED_TCR 18
+#define MII_88E1318S_PHY_WOL_CTRL 16
+#define MII_M1011_IEVENT 19
+
+#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
+#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
+#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
+#define LED2_FORCE_ON (0x8 << 8)
+#define LEDMASK GENMASK(11,8)
+
+static struct phy_device *phydev;
+
+static void mvphy_reg_intn(u16 data)
+{
+ int rc = 0, saved_page;
+
+ saved_page = phy_select_page(phydev, MII_MARVELL_LED_PAGE);
+ if (saved_page < 0)
+ goto err;
+
+ /* Force manual LED2 control to let INTn work */
+ __phy_modify(phydev, MII_PHY_LED_CTRL, LEDMASK, LED2_FORCE_ON);
+
+ /* Set the LED[2]/INTn pin to the required state */
+ __phy_modify(phydev, MII_88E1318S_PHY_LED_TCR,
+ MII_88E1318S_PHY_LED_TCR_FORCE_INT,
+ MII_88E1318S_PHY_LED_TCR_INTn_ENABLE | data);
+
+ if (!data) {
+ /* Clear interrupts to ensure INTn won't be holded in high state */
+ __phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_MARVELL_COPPER_PAGE);
+ __phy_read(phydev, MII_M1011_IEVENT);
+
+ /* If WOL was enabled and a magic packet was received before powering
+ * off, we won't be able to wake up by sending another magic packet.
+ * Clear WOL status.
+ */
+ __phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_MARVELL_WOL_PAGE);
+ __phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL,
+ MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
+ }
+err:
+ rc = phy_restore_page(phydev, saved_page, rc);
+ if (rc < 0)
+ dev_err(&phydev->mdio.dev, "Write register failed, %d\n", rc);
+}
+
+static int linkstation_reboot_notifier(struct notifier_block *nb,
+ unsigned long action, void *unused)
+{
+ if (action == SYS_RESTART)
+ mvphy_reg_intn(MII_88E1318S_PHY_LED_TCR_FORCE_INT);
+
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block linkstation_reboot_nb = {
+ .notifier_call = linkstation_reboot_notifier,
+};
+
+static void linkstation_poweroff(void)
+{
+ unregister_reboot_notifier(&linkstation_reboot_nb);
+ mvphy_reg_intn(0);
+
+ kernel_restart("Power off");
+}
+
+static const struct of_device_id ls_poweroff_of_match[] = {
+ { .compatible = "buffalo,ls421d" },
+ { .compatible = "buffalo,ls421de" },
+ { },
+};
+
+static int __init linkstation_poweroff_init(void)
+{
+ struct mii_bus *bus;
+ struct device_node *dn;
+
+ dn = of_find_matching_node(NULL, ls_poweroff_of_match);
+ if (!dn)
+ return -ENODEV;
+ of_node_put(dn);
+
+ dn = of_find_node_by_name(NULL, "mdio");
+ if (!dn)
+ return -ENODEV;
+
+ bus = of_mdio_find_bus(dn);
+ of_node_put(dn);
+ if (!bus)
+ return -EPROBE_DEFER;
+
+ phydev = phy_find_first(bus);
+ if (!phydev)
+ return -EPROBE_DEFER;
+
+ register_reboot_notifier(&linkstation_reboot_nb);
+ pm_power_off = linkstation_poweroff;
+
+ return 0;
+}
+
+static void __exit linkstation_poweroff_exit(void)
+{
+ pm_power_off = NULL;
+ unregister_reboot_notifier(&linkstation_reboot_nb);
+}
+
+module_init(linkstation_poweroff_init);
+module_exit(linkstation_poweroff_exit);
+
+MODULE_AUTHOR("Daniel González Cabanelas <dgcbueu@gmail.com>");
+MODULE_DESCRIPTION("LinkStation power off driver");
+MODULE_LICENSE("GPL v2");

View File

@ -0,0 +1,27 @@
From 1027a42c25cbf8cfc4ade6503c5110aae04866af Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Daniel=20Gonz=C3=A1lez=20Cabanelas?= <dgcbueu@gmail.com>
Date: Fri, 16 Oct 2020 20:22:37 +0200
Subject: [PATCH] power: reset: linkstation-poweroff: add missing put_device()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The of_mdio_find_bus() takes a reference to the underlying device
structure, we should release that reference using a put_device() call.
Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
---
drivers/power/reset/linkstation-poweroff.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/power/reset/linkstation-poweroff.c
+++ b/drivers/power/reset/linkstation-poweroff.c
@@ -113,6 +113,7 @@ static int __init linkstation_poweroff_i
return -EPROBE_DEFER;
phydev = phy_find_first(bus);
+ put_device(&bus->dev);
if (!phydev)
return -EPROBE_DEFER;

View File

@ -334,7 +334,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
}
--- a/drivers/net/ethernet/broadcom/bcmsysport.c
+++ b/drivers/net/ethernet/broadcom/bcmsysport.c
@@ -2420,7 +2420,6 @@ static int bcm_sysport_probe(struct plat
@@ -2423,7 +2423,6 @@ static int bcm_sysport_probe(struct plat
struct bcm_sysport_priv *priv;
struct device_node *dn;
struct net_device *dev;
@ -342,7 +342,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
u32 txq, rxq;
int ret;
@@ -2502,12 +2501,10 @@ static int bcm_sysport_probe(struct plat
@@ -2505,12 +2504,10 @@ static int bcm_sysport_probe(struct plat
}
/* Initialize netdevice members */

View File

@ -4150,6 +4150,7 @@ CONFIG_POSIX_TIMERS=y
# CONFIG_POWER_RESET_BRCMSTB is not set
# CONFIG_POWER_RESET_GPIO is not set
# CONFIG_POWER_RESET_GPIO_RESTART is not set
# CONFIG_POWER_RESET_LINKSTATION is not set
# CONFIG_POWER_RESET_LTC2952 is not set
# CONFIG_POWER_RESET_PIIX4_POWEROFF is not set
# CONFIG_POWER_RESET_RESTART is not set

View File

@ -116,7 +116,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/property.h>
@@ -3296,3 +3297,5 @@ static int __init regmap_initcall(void)
@@ -3297,3 +3298,5 @@ static int __init regmap_initcall(void)
return 0;
}
postcore_initcall(regmap_initcall);

View File

@ -0,0 +1,34 @@
From 8bf2ce6ea4ee840b70f55a27f80e1cd308051b13 Mon Sep 17 00:00:00 2001
From: Nick Hainke <vincent@systemli.org>
Date: Mon, 27 Dec 2021 00:38:13 +0100
Subject: [PATCH 1/2] mtd: spi-nor: locking support for MX25L6405D
Macronix MX25L6405D supports locking with four block-protection bits.
Currently, the driver only sets three bits. If the bootloader does not
sustain the flash chip in an unlocked state, the flash might be
non-writeable. Add the corresponding flag to enable locking support with
four bits in the status register.
Tested on Nanostation M2 XM.
Similar to commit 7ea40b54e83b ("mtd: spi-nor: enable locking support for
MX25L12805D")
Signed-off-by: David Bauer <mail@david-bauer.net>
Signed-off-by: Nick Hainke <vincent@systemli.org>
---
drivers/mtd/spi-nor/macronix.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -42,7 +42,8 @@ static const struct flash_info macronix_
{ "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
- { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
+ { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K |
+ SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
{ "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
{ "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ |

View File

@ -0,0 +1,30 @@
From 245224608b5368c10407da07557e546743d3c489 Mon Sep 17 00:00:00 2001
From: Nick Hainke <vincent@systemli.org>
Date: Mon, 27 Dec 2021 09:33:13 +0100
Subject: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
Macronix flash chips seem to consist of only one status register.
These chips will not work with the "16-bit Write Status (01h) Command".
Disable SNOR_F_HAS_16BIT_SR for all Macronix chips.
Tested with MX25L6405D.
Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on
lock()/unlock()")
Signed-off-by: David Bauer <mail@david-bauer.net>
Signed-off-by: Nick Hainke <vincent@systemli.org>
---
drivers/mtd/spi-nor/macronix.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -94,6 +94,7 @@ static void macronix_default_init(struct
{
nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
nor->flags |= SNOR_F_HAS_LOCK;
}

View File

@ -41,7 +41,7 @@ ChangeLog v1->v2:
#include "libata.h"
#include "libata-transport.h"
@@ -4579,6 +4580,34 @@ int ata_scsi_add_hosts(struct ata_host *
@@ -4590,6 +4591,34 @@ int ata_scsi_add_hosts(struct ata_host *
return rc;
}
@ -76,7 +76,7 @@ ChangeLog v1->v2:
void ata_scsi_scan_host(struct ata_port *ap, int sync)
{
int tries = 5;
@@ -4604,6 +4633,7 @@ void ata_scsi_scan_host(struct ata_port
@@ -4615,6 +4644,7 @@ void ata_scsi_scan_host(struct ata_port
NULL);
if (!IS_ERR(sdev)) {
dev->sdev = sdev;

View File

@ -37,7 +37,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
depends on ARCH_MOXART || COMPILE_TEST
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium
@@ -49,6 +49,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium
obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o

View File

@ -1,6 +1,6 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -584,6 +584,13 @@ config XILINX_GMII2RGMII
@@ -580,6 +580,13 @@ config XILINX_GMII2RGMII
the Reduced Gigabit Media Independent Interface(RGMII) between
Ethernet physical media devices and the Gigabit Ethernet controller.
@ -16,7 +16,7 @@
config MICREL_KS8995MA
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -69,6 +69,7 @@ ifdef CONFIG_HWMON
@@ -68,6 +68,7 @@ ifdef CONFIG_HWMON
aquantia-objs += aquantia_hwmon.o
endif
obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o

View File

@ -25,7 +25,7 @@ Signed-off-by: Robert Marko <robert.marko@sartura.hr>
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -537,6 +537,12 @@ config NXP_TJA11XX_PHY
@@ -533,6 +533,12 @@ config NXP_TJA11XX_PHY
---help---
Currently supports the NXP TJA1100 and TJA1101 PHY.
@ -40,7 +40,7 @@ Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---help---
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -103,6 +103,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc.o
@@ -102,6 +102,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o

View File

@ -186,6 +186,9 @@
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot_pages_size = <0x1200000>;
partitions {
compatible = "qcom,smem-part";
};

View File

@ -22,6 +22,7 @@ ctera,c200-v1|\
globalscale,sheevaplug|\
iom,iconnect-1.1|\
iom,ix2-200|\
netgear,readynas-duo-v2|\
raidsonic,ib-nas62x0|\
seagate,blackarmor-nas220|\
seagate,dockstar|\
@ -30,6 +31,9 @@ seagate,goflexnet|\
zyxel,nsa310s)
ucidef_set_interface_lan "eth0" "dhcp"
;;
endian,4i-edge-200)
ucidef_set_interface_lan "port1 port2 port3 port4 eth1"
;;
linksys,e4200-v2|\
linksys,ea3500|\
linksys,ea4500)

View File

@ -3,7 +3,7 @@
START=98
boot() {
# configuring (lm85/lm63) onboard temp/fan controller to run the fan on its own
# configuring onboard temp/fan controller to run the fan on its own
# for more information, please read https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface
case $(board_name) in
@ -18,6 +18,10 @@ boot() {
path_to_hwmon='/sys/class/hwmon/hwmon0'
echo 2 > "$path_to_hwmon/pwm1_enable" # fan is on pwm1
;;
netgear,readynas-duo-v2)
path_to_hwmon='/sys/class/hwmon/hwmon0'
echo 1200 > "$path_to_hwmon/fan1_target" # set target rpm
;;
seagate,blackarmor-nas220)
path_to_hwmon='/sys/devices/platform/ocp@f1000000/f1011000.i2c/i2c-0/0-002e/hwmon/hwmon0'
# adt7476 fan control chip. 3 temp sensors. Set to 1/4 speed at 35C and max speed at 48C.

View File

@ -19,6 +19,14 @@ preinit_set_mac_address() {
ip link set dev dmz address $(macaddr_add $mac 8) 2>/dev/null
ip link set dev dsl address $(macaddr_add $mac 9) 2>/dev/null
;;
endian,4i-edge-200)
mac=$(cat /sys/class/net/eth0/address)
ip link set dev port1 address $mac 2>/dev/null
ip link set dev port2 address $(macaddr_add $mac 1) 2>/dev/null
ip link set dev port3 address $(macaddr_add $mac 2) 2>/dev/null
ip link set dev port4 address $(macaddr_add $mac 3) 2>/dev/null
;;
esac
}

View File

@ -4,7 +4,18 @@ RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
REQUIRE_IMAGE_METADATA=1
platform_check_image() {
return 0
local board="$(board_name)"
case "$board" in
netgear,readynas-duo-v2)
# let's store how rootfs is mounted
cp /proc/mounts /tmp/mounts
return 0
;;
*)
return 0
;;
esac
}
platform_do_upgrade() {

View File

@ -221,6 +221,7 @@ CONFIG_PINCTRL_SX150X=y
CONFIG_PLAT_ORION=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_LINKSTATION=y
# CONFIG_POWER_RESET_QNAP is not set
CONFIG_POWER_SUPPLY=y
CONFIG_RATIONAL=y

View File

@ -219,6 +219,7 @@ CONFIG_PINCTRL_SX150X=y
CONFIG_PLAT_ORION=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_LINKSTATION=y
# CONFIG_POWER_RESET_QNAP is not set
CONFIG_POWER_SUPPLY=y
CONFIG_RATIONAL=y

View File

@ -0,0 +1,219 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Endian 4i Edge 200 Board Description
* Note: Endian UTM Mini is hardware clone of Endian Edge 200
* Copyright 2021 Pawel Dembicki <paweldembicki@gmail.com>
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6281.dtsi"
/ {
model = "Endian 4i Edge 200";
compatible = "endian,4i-edge-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>;
};
aliases {
led-boot = &led_status_green;
led-failsafe = &led_status_orange;
led-running = &led_status_green;
led-upgrade = &led_status_orange;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = &uart0;
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&pmx_led49 &pmx_led35 &pmx_led34>;
pinctrl-names = "default";
led_status_green: status_green {
label = "green:status";
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
};
led_status_orange: status_orange {
label = "orange:status";
gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
sdcard {
label = "orange:sdcard";
gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
};
};
&eth0 {
status = "okay";
};
&eth0port {
speed = <1000>;
duplex = <1>;
};
&eth1 {
status = "okay";
};
&eth1port {
phy-handle = <&ethphyb>;
};
&mdio {
status = "okay";
ethphyb: ethernet-phy@b {
reg = <0x0b>;
marvell,reg-init =
/* link-activity, bi-color mode 4 */
<3 0x10 0xfff0 0xf>; /* Reg 3,16 <- 0xzzzf */
};
switch0: switch@11 {
compatible = "marvell,mv88e6085";
reg = <0x11>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "port1";
};
port@1 {
reg = <1>;
label = "port2";
};
port@2 {
reg = <2>;
label = "port3";
};
port@3 {
reg = <3>;
label = "port4";
};
port@5 {
reg = <5>;
label = "cpu";
phy-mode = "rgmii-id";
ethernet = <&eth0port>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
&nand {
status = "okay";
pinctrl-0 = <&pmx_nand>;
pinctrl-names = "default";
partition@0 {
label = "u-boot";
reg = <0x00000000 0x000a0000>;
read-only;
};
partition@a0000 {
label = "u-boot-env";
reg = <0x000a0000 0x00060000>;
read-only;
};
partition@100000 {
label = "kernel";
reg = <0x00100000 0x00400000>;
};
partition@500000 {
label = "ubi";
reg = <0x00500000 0x1fb00000>;
};
};
&pciec {
status = "okay";
};
&pcie0 {
status = "okay";
};
&pinctrl {
pinctrl-0 = <&pmx_sysrst>;
pinctrl-names = "default";
pmx_sysrst: pmx-sysrst {
marvell,pins = "mpp6";
marvell,function = "sysrst";
};
pmx_sdio_cd: pmx-sdio-cd {
marvell,pins = "mpp28";
marvell,function = "gpio";
};
pmx_led34: pmx_led34 {
marvell,pins = "mpp34";
marvell,function = "gpio";
};
pmx_led35: pmx_led35 {
marvell,pins = "mpp35";
marvell,function = "gpio";
};
pmx_led49: pmx_led49 {
marvell,pins = "mpp49";
marvell,function = "gpio";
};
};
&rtc {
status = "okay";
};
&sata_phy0 {
status = "disabled";
};
&sata_phy1 {
status = "disabled";
};
&sdio {
pinctrl-0 = <&pmx_sdio_cd>;
pinctrl-names = "default";
status = "okay";
cd-gpios = <&gpio0 28 9>;
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
};

View File

@ -140,6 +140,17 @@ define Device/ctera_c200-v1
endef
TARGET_DEVICES += ctera_c200-v1
define Device/endian_4i-edge-200
DEVICE_VENDOR := Endian
DEVICE_MODEL := 4i Edge 200
DEVICE_ALT0_VENDOR := Endian
DEVICE_ALT0_MODEL := UTM Mini Firewall
DEVICE_PACKAGES := kmod-ath9k kmod-mvsdio wpad-basic-wolfssl
KERNEL_SIZE := 4096k
IMAGES := sysupgrade.bin
endef
TARGET_DEVICES += endian_4i-edge-200
define Device/globalscale_sheevaplug
DEVICE_VENDOR := Globalscale
DEVICE_MODEL := Sheevaplug
@ -212,6 +223,18 @@ define Device/linksys_ea4500
endef
TARGET_DEVICES += linksys_ea4500
define Device/netgear_readynas-duo-v2
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := ReadyNAS Duo
DEVICE_VARIANT := v2
DEVICE_DTS := kirkwood-netgear_readynas_duo_v2
KERNEL_IN_UBI :=
IMAGES := sysupgrade.bin
DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 \
kmod-gpio-button-hotplug kmod-hwmon-g762 kmod-rtc-rs5c372a kmod-usb3
endef
TARGET_DEVICES += netgear_readynas-duo-v2
define Device/raidsonic_ib-nas62x0
DEVICE_VENDOR := RaidSonic
DEVICE_MODEL := ICY BOX IB-NAS62x0

View File

@ -0,0 +1,76 @@
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -19,6 +19,13 @@
reg = <0x00000000 0x10000000>;
};
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
stdout-path = &uart0;
@@ -115,7 +122,7 @@
&pmx_led_blue_backup >;
pinctrl-names = "default";
- power_led {
+ led_power: power_led {
label = "status:blue:power_led";
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
default-state = "keep";
@@ -129,11 +136,13 @@
disk1_led {
label = "status:blue:disk1_led";
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "ata1";
};
disk2_led {
label = "status:blue:disk2_led";
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "ata2";
};
backup_led {
@@ -150,7 +159,13 @@
power-button {
label = "Power Button";
- linux,code = <KEY_POWER>;
+ /* Power button and INT pin from PHY are both connected
+ * to this GPIO. Every network restart causes PHY restart
+ * and button is pressed. It's difficult to use it as
+ * KEY_POWER without changes in kernel (or netifd) so
+ * the button is configured as regular one.
+ */
+ linux,code = <BTN_1>;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
@@ -208,18 +223,13 @@
};
partition@200000 {
- label = "uImage";
+ label = "kernel";
reg = <0x0200000 0x600000>;
};
partition@800000 {
- label = "minirootfs";
- reg = <0x0800000 0x1000000>;
- };
-
- partition@1800000 {
- label = "jffs2";
- reg = <0x1800000 0x6800000>;
+ label = "ubi";
+ reg = <0x0800000 0x7800000>;
};
};

View File

@ -0,0 +1,106 @@
From 11cab9f5cd9390cd83747e579957c8f5b807c09c Mon Sep 17 00:00:00 2001
From: Pawel Dembicki <paweldembicki@gmail.com>
Date: Fri, 18 Jun 2021 12:37:27 +0200
Subject: [PATCH 1/2] power: reset: linkstation-poweroff: prepare for new
devices
This commit prepare driver for another device support.
New power_off_cfg structure describes two most important things: name of
mdio bus and pointer to register setting function. It allow to add new
device with different mdio bus node and other phy register config.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
---
drivers/power/reset/linkstation-poweroff.c | 35 ++++++++++++++++++----
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/power/reset/linkstation-poweroff.c b/drivers/power/reset/linkstation-poweroff.c
index f1e843df0e16..8691cf98600d 100644
--- a/drivers/power/reset/linkstation-poweroff.c
+++ b/drivers/power/reset/linkstation-poweroff.c
@@ -29,11 +29,21 @@
#define LED2_FORCE_ON (0x8 << 8)
#define LEDMASK GENMASK(11,8)
+struct power_off_cfg {
+ char *mdio_node_name;
+ void (*phy_set_reg)(bool restart);
+};
+
static struct phy_device *phydev;
+static const struct power_off_cfg *cfg;
-static void mvphy_reg_intn(u16 data)
+static void linkstation_mvphy_reg_intn(bool restart)
{
int rc = 0, saved_page;
+ u16 data = 0;
+
+ if(restart)
+ data = MII_88E1318S_PHY_LED_TCR_FORCE_INT;
saved_page = phy_select_page(phydev, MII_MARVELL_LED_PAGE);
if (saved_page < 0)
@@ -66,11 +76,16 @@ static void mvphy_reg_intn(u16 data)
dev_err(&phydev->mdio.dev, "Write register failed, %d\n", rc);
}
+static const struct power_off_cfg linkstation_power_off_cfg = {
+ .mdio_node_name = "mdio",
+ .phy_set_reg = linkstation_mvphy_reg_intn,
+};
+
static int linkstation_reboot_notifier(struct notifier_block *nb,
unsigned long action, void *unused)
{
if (action == SYS_RESTART)
- mvphy_reg_intn(MII_88E1318S_PHY_LED_TCR_FORCE_INT);
+ cfg->phy_set_reg(true);
return NOTIFY_DONE;
}
@@ -82,14 +97,18 @@ static struct notifier_block linkstation_reboot_nb = {
static void linkstation_poweroff(void)
{
unregister_reboot_notifier(&linkstation_reboot_nb);
- mvphy_reg_intn(0);
+ cfg->phy_set_reg(false);
kernel_restart("Power off");
}
static const struct of_device_id ls_poweroff_of_match[] = {
- { .compatible = "buffalo,ls421d" },
- { .compatible = "buffalo,ls421de" },
+ { .compatible = "buffalo,ls421d",
+ .data = &linkstation_power_off_cfg,
+ },
+ { .compatible = "buffalo,ls421de",
+ .data = &linkstation_power_off_cfg,
+ },
{ },
};
@@ -97,13 +116,17 @@ static int __init linkstation_poweroff_init(void)
{
struct mii_bus *bus;
struct device_node *dn;
+ const struct of_device_id *match;
dn = of_find_matching_node(NULL, ls_poweroff_of_match);
if (!dn)
return -ENODEV;
of_node_put(dn);
- dn = of_find_node_by_name(NULL, "mdio");
+ match = of_match_node(ls_poweroff_of_match, dn);
+ cfg = match->data;
+
+ dn = of_find_node_by_name(NULL, cfg->mdio_node_name);
if (!dn)
return -ENODEV;
--
2.25.1

View File

@ -0,0 +1,102 @@
From a2d9c86df8d12646f5bf66920e4f1e6d940cfc62 Mon Sep 17 00:00:00 2001
From: Pawel Dembicki <paweldembicki@gmail.com>
Date: Fri, 18 Jun 2021 13:25:33 +0200
Subject: [PATCH 2/2] power: reset: linkstation-poweroff: add new device
This commit introduces support for NETGEAR ReadyNAS Duo v2.
This device use bit 4 of LED[2:0] Polarity Control Register to indicate
AC Power loss.
For more details about AC loss detection in NETGEAR ReadyNAS Duo v2,
please look at the file:
RND_5.3.13_WW.src/u-boot/board/mv_feroceon/mv_hal/usibootup/usibootup.c
from Netgear GPL sources.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
---
drivers/power/reset/linkstation-poweroff.c | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/power/reset/linkstation-poweroff.c b/drivers/power/reset/linkstation-poweroff.c
index 8691cf98600d..2a92b6052cac 100644
--- a/drivers/power/reset/linkstation-poweroff.c
+++ b/drivers/power/reset/linkstation-poweroff.c
@@ -19,6 +19,7 @@
#define MII_MARVELL_PHY_PAGE 22
#define MII_PHY_LED_CTRL 16
+#define MII_PHY_LED_POL_CTRL 17
#define MII_88E1318S_PHY_LED_TCR 18
#define MII_88E1318S_PHY_WOL_CTRL 16
#define MII_M1011_IEVENT 19
@@ -29,6 +30,8 @@
#define LED2_FORCE_ON (0x8 << 8)
#define LEDMASK GENMASK(11,8)
+#define MII_88E1318S_PHY_LED_POL_LED2 BIT(4)
+
struct power_off_cfg {
char *mdio_node_name;
void (*phy_set_reg)(bool restart);
@@ -76,11 +79,48 @@ static void linkstation_mvphy_reg_intn(bool restart)
dev_err(&phydev->mdio.dev, "Write register failed, %d\n", rc);
}
+static void readynas_mvphy_set_reg(bool restart)
+{
+ int rc = 0, saved_page;
+ u16 data = 0;
+
+ if(restart)
+ data = MII_88E1318S_PHY_LED_POL_LED2;
+
+ saved_page = phy_select_page(phydev, MII_MARVELL_LED_PAGE);
+ if (saved_page < 0)
+ goto err;
+
+ /* Set the LED[2].0 Polarity bit to the required state */
+ __phy_modify(phydev, MII_PHY_LED_POL_CTRL,
+ MII_88E1318S_PHY_LED_POL_LED2, data);
+
+ if (!data) {
+
+ /* If WOL was enabled and a magic packet was received before powering
+ * off, we won't be able to wake up by sending another magic packet.
+ * Clear WOL status.
+ */
+ __phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_MARVELL_WOL_PAGE);
+ __phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL,
+ MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
+ }
+err:
+ rc = phy_restore_page(phydev, saved_page, rc);
+ if (rc < 0)
+ dev_err(&phydev->mdio.dev, "Write register failed, %d\n", rc);
+}
+
static const struct power_off_cfg linkstation_power_off_cfg = {
.mdio_node_name = "mdio",
.phy_set_reg = linkstation_mvphy_reg_intn,
};
+static const struct power_off_cfg readynas_power_off_cfg = {
+ .mdio_node_name = "mdio-bus",
+ .phy_set_reg = readynas_mvphy_set_reg,
+};
+
static int linkstation_reboot_notifier(struct notifier_block *nb,
unsigned long action, void *unused)
{
@@ -109,6 +149,9 @@ static const struct of_device_id ls_poweroff_of_match[] = {
{ .compatible = "buffalo,ls421de",
.data = &linkstation_power_off_cfg,
},
+ { .compatible = "netgear,readynas-duo-v2",
+ .data = &readynas_power_off_cfg,
+ },
{ },
};
--
2.25.1

View File

@ -0,0 +1,76 @@
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -19,6 +19,13 @@
reg = <0x00000000 0x10000000>;
};
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
stdout-path = &uart0;
@@ -115,7 +122,7 @@
&pmx_led_blue_backup >;
pinctrl-names = "default";
- power_led {
+ led_power: power_led {
label = "status:blue:power_led";
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
default-state = "keep";
@@ -129,11 +136,13 @@
disk1_led {
label = "status:blue:disk1_led";
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "ata1";
};
disk2_led {
label = "status:blue:disk2_led";
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "ata2";
};
backup_led {
@@ -150,7 +159,13 @@
power-button {
label = "Power Button";
- linux,code = <KEY_POWER>;
+ /* Power button and INT pin from PHY are both connected
+ * to this GPIO. Every network restart causes PHY restart
+ * and button is pressed. It's difficult to use it as
+ * KEY_POWER without changes in kernel (or netifd) so
+ * the button is configured as regular one.
+ */
+ linux,code = <BTN_1>;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
@@ -208,18 +223,13 @@
};
partition@200000 {
- label = "uImage";
+ label = "kernel";
reg = <0x0200000 0x600000>;
};
partition@800000 {
- label = "minirootfs";
- reg = <0x0800000 0x1000000>;
- };
-
- partition@1800000 {
- label = "jffs2";
- reg = <0x1800000 0x6800000>;
+ label = "ubi";
+ reg = <0x0800000 0x7800000>;
};
};

View File

@ -0,0 +1,106 @@
From 11cab9f5cd9390cd83747e579957c8f5b807c09c Mon Sep 17 00:00:00 2001
From: Pawel Dembicki <paweldembicki@gmail.com>
Date: Fri, 18 Jun 2021 12:37:27 +0200
Subject: [PATCH 1/2] power: reset: linkstation-poweroff: prepare for new
devices
This commit prepare driver for another device support.
New power_off_cfg structure describes two most important things: name of
mdio bus and pointer to register setting function. It allow to add new
device with different mdio bus node and other phy register config.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
---
drivers/power/reset/linkstation-poweroff.c | 35 ++++++++++++++++++----
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/power/reset/linkstation-poweroff.c b/drivers/power/reset/linkstation-poweroff.c
index f1e843df0e16..8691cf98600d 100644
--- a/drivers/power/reset/linkstation-poweroff.c
+++ b/drivers/power/reset/linkstation-poweroff.c
@@ -29,11 +29,21 @@
#define LED2_FORCE_ON (0x8 << 8)
#define LEDMASK GENMASK(11,8)
+struct power_off_cfg {
+ char *mdio_node_name;
+ void (*phy_set_reg)(bool restart);
+};
+
static struct phy_device *phydev;
+static const struct power_off_cfg *cfg;
-static void mvphy_reg_intn(u16 data)
+static void linkstation_mvphy_reg_intn(bool restart)
{
int rc = 0, saved_page;
+ u16 data = 0;
+
+ if(restart)
+ data = MII_88E1318S_PHY_LED_TCR_FORCE_INT;
saved_page = phy_select_page(phydev, MII_MARVELL_LED_PAGE);
if (saved_page < 0)
@@ -66,11 +76,16 @@ static void mvphy_reg_intn(u16 data)
dev_err(&phydev->mdio.dev, "Write register failed, %d\n", rc);
}
+static const struct power_off_cfg linkstation_power_off_cfg = {
+ .mdio_node_name = "mdio",
+ .phy_set_reg = linkstation_mvphy_reg_intn,
+};
+
static int linkstation_reboot_notifier(struct notifier_block *nb,
unsigned long action, void *unused)
{
if (action == SYS_RESTART)
- mvphy_reg_intn(MII_88E1318S_PHY_LED_TCR_FORCE_INT);
+ cfg->phy_set_reg(true);
return NOTIFY_DONE;
}
@@ -82,14 +97,18 @@ static struct notifier_block linkstation_reboot_nb = {
static void linkstation_poweroff(void)
{
unregister_reboot_notifier(&linkstation_reboot_nb);
- mvphy_reg_intn(0);
+ cfg->phy_set_reg(false);
kernel_restart("Power off");
}
static const struct of_device_id ls_poweroff_of_match[] = {
- { .compatible = "buffalo,ls421d" },
- { .compatible = "buffalo,ls421de" },
+ { .compatible = "buffalo,ls421d",
+ .data = &linkstation_power_off_cfg,
+ },
+ { .compatible = "buffalo,ls421de",
+ .data = &linkstation_power_off_cfg,
+ },
{ },
};
@@ -97,13 +116,17 @@ static int __init linkstation_poweroff_init(void)
{
struct mii_bus *bus;
struct device_node *dn;
+ const struct of_device_id *match;
dn = of_find_matching_node(NULL, ls_poweroff_of_match);
if (!dn)
return -ENODEV;
of_node_put(dn);
- dn = of_find_node_by_name(NULL, "mdio");
+ match = of_match_node(ls_poweroff_of_match, dn);
+ cfg = match->data;
+
+ dn = of_find_node_by_name(NULL, cfg->mdio_node_name);
if (!dn)
return -ENODEV;
--
2.25.1

View File

@ -0,0 +1,102 @@
From a2d9c86df8d12646f5bf66920e4f1e6d940cfc62 Mon Sep 17 00:00:00 2001
From: Pawel Dembicki <paweldembicki@gmail.com>
Date: Fri, 18 Jun 2021 13:25:33 +0200
Subject: [PATCH 2/2] power: reset: linkstation-poweroff: add new device
This commit introduces support for NETGEAR ReadyNAS Duo v2.
This device use bit 4 of LED[2:0] Polarity Control Register to indicate
AC Power loss.
For more details about AC loss detection in NETGEAR ReadyNAS Duo v2,
please look at the file:
RND_5.3.13_WW.src/u-boot/board/mv_feroceon/mv_hal/usibootup/usibootup.c
from Netgear GPL sources.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
---
drivers/power/reset/linkstation-poweroff.c | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/power/reset/linkstation-poweroff.c b/drivers/power/reset/linkstation-poweroff.c
index 8691cf98600d..2a92b6052cac 100644
--- a/drivers/power/reset/linkstation-poweroff.c
+++ b/drivers/power/reset/linkstation-poweroff.c
@@ -19,6 +19,7 @@
#define MII_MARVELL_PHY_PAGE 22
#define MII_PHY_LED_CTRL 16
+#define MII_PHY_LED_POL_CTRL 17
#define MII_88E1318S_PHY_LED_TCR 18
#define MII_88E1318S_PHY_WOL_CTRL 16
#define MII_M1011_IEVENT 19
@@ -29,6 +30,8 @@
#define LED2_FORCE_ON (0x8 << 8)
#define LEDMASK GENMASK(11,8)
+#define MII_88E1318S_PHY_LED_POL_LED2 BIT(4)
+
struct power_off_cfg {
char *mdio_node_name;
void (*phy_set_reg)(bool restart);
@@ -76,11 +79,48 @@ static void linkstation_mvphy_reg_intn(bool restart)
dev_err(&phydev->mdio.dev, "Write register failed, %d\n", rc);
}
+static void readynas_mvphy_set_reg(bool restart)
+{
+ int rc = 0, saved_page;
+ u16 data = 0;
+
+ if(restart)
+ data = MII_88E1318S_PHY_LED_POL_LED2;
+
+ saved_page = phy_select_page(phydev, MII_MARVELL_LED_PAGE);
+ if (saved_page < 0)
+ goto err;
+
+ /* Set the LED[2].0 Polarity bit to the required state */
+ __phy_modify(phydev, MII_PHY_LED_POL_CTRL,
+ MII_88E1318S_PHY_LED_POL_LED2, data);
+
+ if (!data) {
+
+ /* If WOL was enabled and a magic packet was received before powering
+ * off, we won't be able to wake up by sending another magic packet.
+ * Clear WOL status.
+ */
+ __phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_MARVELL_WOL_PAGE);
+ __phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL,
+ MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
+ }
+err:
+ rc = phy_restore_page(phydev, saved_page, rc);
+ if (rc < 0)
+ dev_err(&phydev->mdio.dev, "Write register failed, %d\n", rc);
+}
+
static const struct power_off_cfg linkstation_power_off_cfg = {
.mdio_node_name = "mdio",
.phy_set_reg = linkstation_mvphy_reg_intn,
};
+static const struct power_off_cfg readynas_power_off_cfg = {
+ .mdio_node_name = "mdio-bus",
+ .phy_set_reg = readynas_mvphy_set_reg,
+};
+
static int linkstation_reboot_notifier(struct notifier_block *nb,
unsigned long action, void *unused)
{
@@ -109,6 +149,9 @@ static const struct of_device_id ls_poweroff_of_match[] = {
{ .compatible = "buffalo,ls421de",
.data = &linkstation_power_off_cfg,
},
+ { .compatible = "netgear,readynas-duo-v2",
+ .data = &readynas_power_off_cfg,
+ },
{ },
};
--
2.25.1

View File

@ -22,7 +22,7 @@ Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -367,6 +367,16 @@ config AT803X_PHY
@@ -363,6 +363,16 @@ config AT803X_PHY
---help---
Currently supports the AT8030 and AT8035 model

View File

@ -15,7 +15,7 @@ Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -475,6 +475,11 @@ config ICPLUS_PHY
@@ -471,6 +471,11 @@ config ICPLUS_PHY
---help---
Currently supports the IP175C and IP1001 PHYs.
@ -29,7 +29,7 @@ Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
---help---
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o
@@ -86,6 +86,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o
obj-$(CONFIG_DP83867_PHY) += dp83867.o
obj-$(CONFIG_FIXED_PHY) += fixed_phy.o
obj-$(CONFIG_ICPLUS_PHY) += icplus.o

View File

@ -0,0 +1,202 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "mt7620a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
compatible = "wevo,air-duo", "ralink,mt7620a-soc";
model = "WeVO AIR DUO";
aliases {
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_status;
label-mac-device = &ethernet;
};
leds {
compatible = "gpio-leds";
led_status: led-0 {
label = "blue:status";
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
};
led-1 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WPS;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&gpio1 {
status = "okay";
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "config";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_4: macaddr@4 {
reg = <0x4 0x6>;
};
};
partition@50000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x50000 0xeb0000>;
};
partition@f00000 {
label = "db";
reg = <0xf00000 0x100000>;
read-only;
};
};
};
};
&state_default {
gpio {
groups = "i2c", "uartf", "spi refclk";
function = "gpio";
};
};
&ethernet {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins &mdio_pins>;
nvmem-cells = <&macaddr_factory_4>;
nvmem-cell-names = "mac-address";
port@5 {
status = "okay";
mediatek,fixed-link = <1000 1 1 1>;
phy-mode = "rgmii";
};
mdio-bus {
status = "okay";
ethernet-phy@0 {
reg = <0>;
phy-mode = "rgmii";
};
ethernet-phy@1 {
reg = <1>;
phy-mode = "rgmii";
};
ethernet-phy@2 {
reg = <2>;
phy-mode = "rgmii";
};
ethernet-phy@3 {
reg = <3>;
phy-mode = "rgmii";
};
ethernet-phy@4 {
reg = <4>;
phy-mode = "rgmii";
};
ethernet-phy@1f {
reg = <0x1f>;
phy-mode = "rgmii";
};
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};
&pcie {
status = "okay";
};
&pcie0 {
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x8000>;
ieee80211-freq-limit = <5000000 6000000>;
led {
led-sources = <2>;
led-active-low;
};
};
};
&wmac {
pinctrl-names = "default";
pinctrl-0 = <&wled_pins>;
ralink,mtd-eeprom = <&factory 0x0>;
};

View File

@ -0,0 +1,172 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "mt7621.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
compatible = "iptime,a3004t", "mediatek,mt7621-soc";
model = "ipTIME A3004T";
aliases {
led-boot = &led_cpu;
led-failsafe = &led_cpu;
led-running = &led_cpu;
led-upgrade = &led_cpu;
};
leds {
compatible = "gpio-leds";
led_cpu: led-0 {
label = "amber:cpu";
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_CPU;
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
};
led-1 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_WLAN;
function-enumerator = <0>;
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0radio";
};
led-2 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_WLAN;
function-enumerator = <1>;
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1radio";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&nand {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "config";
reg = <0x80000 0x20000>;
read-only;
};
factory: partition@a0000 {
label = "factory";
reg = <0xa0000 0x20000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_4: macaddr@4 {
reg = <0x4 0x6>;
};
macaddr_factory_8004: macaddr@8004 {
reg = <0x8004 0x6>;
};
};
partition@140000 {
label = "firmware";
reg = <0x140000 0x7e40000>;
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x400000>;
};
partition@400000 {
label = "ubi";
reg = <0x400000 0x7a40000>;
};
};
};
};
&gmac0 {
nvmem-cells = <&macaddr_factory_4>;
nvmem-cell-names = "mac-address";
mac-address-increment = <(3)>;
};
&switch0 {
ports {
port@0 {
status = "okay";
label = "wan";
nvmem-cells = <&macaddr_factory_4>;
nvmem-cell-names = "mac-address";
mac-address-increment = <(1)>;
};
port@1 {
status = "okay";
label = "lan4";
};
port@2 {
status = "okay";
label = "lan3";
};
port@3 {
status = "okay";
label = "lan2";
};
port@4 {
status = "okay";
label = "lan1";
};
};
};
&pcie {
status = "okay";
};
&pcie0 {
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x0>;
};
};
&state_default {
gpio {
groups = "i2c", "jtag", "wdt";
function = "gpio";
};
};

View File

@ -0,0 +1,121 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "mt7621.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
compatible = "iptime,t5004", "mediatek,mt7621-soc";
model = "ipTIME T5004";
aliases {
led-boot = &led_cpu;
led-failsafe = &led_cpu;
led-running = &led_cpu;
led-upgrade = &led_cpu;
};
leds {
compatible = "gpio-leds";
led_cpu: led-0 {
label = "blue:cpu";
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_CPU;
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&nand {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "config";
reg = <0x80000 0xc0000>;
read-only;
};
partition@140000 {
label = "firmware";
reg = <0x140000 0x7e40000>;
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x400000>;
};
partition@400000 {
label = "ubi";
reg = <0x400000 0x7a40000>;
};
};
};
};
&state_default {
gpio {
groups = "i2c", "wdt";
function = "gpio";
};
};
&switch0 {
ports {
port@0 {
status = "okay";
label = "wan";
};
port@1 {
status = "okay";
label = "lan4";
};
port@2 {
status = "okay";
label = "lan3";
};
port@3 {
status = "okay";
label = "lan2";
};
port@4 {
status = "okay";
label = "lan1";
};
};
};
&xhci {
status = "disabled";
};

View File

@ -822,7 +822,7 @@ static int aw9523_init_gpiochip(struct aw9523 *awi, unsigned int npins)
gpiochip->parent = dev;
gpiochip->of_node = dev->of_node;
gpiochip->owner = THIS_MODULE;
gpiochip->can_sleep = false;
gpiochip->can_sleep = true;
return 0;
}

View File

@ -1162,6 +1162,17 @@ define Device/wavlink_wl-wn579x3
endef
TARGET_DEVICES += wavlink_wl-wn579x3
define Device/wevo_air-duo
SOC := mt7620a
IMAGE_SIZE := 15040k
UIMAGE_NAME := AIR DUO(0.0.0)
KERNEL_INITRAMFS_SUFFIX := .upload
DEVICE_VENDOR := WeVO
DEVICE_MODEL := AIR DUO
DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci kmod-usb-storage-uas
endef
TARGET_DEVICES += wevo_air-duo
define Device/wrtnode_wrtnode
SOC := mt7620n
IMAGE_SIZE := 16064k

View File

@ -162,6 +162,8 @@ define Device/asus_rt-ac57u
$(Device/dsa-migration)
DEVICE_VENDOR := ASUS
DEVICE_MODEL := RT-AC57U
DEVICE_ALT0_VENDOR := ASUS
DEVICE_ALT0_MODEL := RT-AC1200GU
IMAGE_SIZE := 16064k
DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 \
kmod-usb-ledtrig-usbport
@ -767,6 +769,23 @@ define Device/iptime_a3004ns-dual
endef
TARGET_DEVICES += iptime_a3004ns-dual
define Device/iptime_a3004t
$(Device/dsa-migration)
$(Device/uimage-lzma-loader)
BLOCKSIZE := 128k
PAGESIZE := 2048
FILESYSTEMS := squashfs
KERNEL_SIZE := 4096k
IMAGE_SIZE := 129280k
UIMAGE_NAME := a3004t
UBINIZE_OPTS := -E 5
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
DEVICE_VENDOR := ipTIME
DEVICE_MODEL := A3004T
DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3
endef
TARGET_DEVICES += iptime_a3004t
define Device/iptime_a6ns-m
$(Device/dsa-migration)
IMAGE_SIZE := 16128k
@ -788,6 +807,21 @@ define Device/iptime_a8004t
endef
TARGET_DEVICES += iptime_a8004t
define Device/iptime_t5004
$(Device/dsa-migration)
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_SIZE := 4096k
IMAGE_SIZE := 129280k
UBINIZE_OPTS := -E 5
UIMAGE_NAME := t5004
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
DEVICE_VENDOR := ipTIME
DEVICE_MODEL := T5004
DEVICE_PACKAGES := -wpad-basic-wolfssl
endef
TARGET_DEVICES += iptime_t5004
define Device/jcg_jhr-ac876m
$(Device/dsa-migration)
IMAGE_SIZE := 16064k

View File

@ -186,7 +186,8 @@ ramips_setup_interfaces()
;;
linksys,e1700|\
netis,wf2770|\
ralink,mt7620a-mt7530-evb)
ralink,mt7620a-mt7530-evb|\
wevo,air-duo)
ucidef_add_switch "switch0"
ucidef_add_switch_attr "switch0" "enable" "false"
ucidef_add_switch "switch1" \
@ -350,6 +351,7 @@ ramips_setup_macs()
lenovo,newifi-y1s|\
ohyeah,oy-0001|\
wavlink,wl-wn530hg4|\
wevo,air-duo|\
youku,yk-l1|\
youku,yk-l1c)
wan_mac=$(mtd_get_mac_binary factory 0x2e)

View File

@ -135,6 +135,10 @@ ramips_setup_macs()
wan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr)
label_mac=$wan_mac
;;
iptime,t5004)
lan_mac=$(mtd_get_mac_ascii config ethaddr)
wan_mac=$(macaddr_add "$lan_mac" 1)
;;
jcg,y2|\
wavlink,wl-wn531a6|\
winstars,ws-wn583a6|\

View File

@ -58,6 +58,8 @@ platform_do_upgrade() {
dlink,dir-2660-a1|\
dlink,dir-853-a3|\
hiwifi,hc5962|\
iptime,a3004t|\
iptime,t5004|\
jcg,q20|\
linksys,e5600|\
linksys,ea7300-v1|\

View File

@ -1,6 +1,6 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -540,6 +540,12 @@ config REALTEK_PHY
@@ -536,6 +536,12 @@ config REALTEK_PHY
---help---
Supports the Realtek 821x PHY.
@ -15,7 +15,7 @@
---help---
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -102,6 +102,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o
@@ -101,6 +101,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
obj-$(CONFIG_REALTEK_PHY) += realtek.o

View File

@ -1,32 +0,0 @@
From 4f45f9f370a5bc6a43a7a166f10b3a30ca21353c Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Wed, 17 Nov 2021 10:36:31 +0100
Subject: [PATCH v2] arm64: dts: allwinner: orangepi-zero-plus: fix PHY mode
Orange Pi Zero Plus uses a Realtek RTL8211E RGMII Gigabit PHY, but its
currently set to plain RGMII mode meaning that it doesn't introduce
delays.
With this setup, TX packets are completely lost and changing the mode to
RGMII-ID so the PHY will add delays internally fixes the issue.
Fixes: a7affb13b271 ("arm64: allwinner: H5: Add Xunlong Orange Pi Zero Plus")
Tested-by: Ron Goossens <rgoossens@gmail.com>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Tested-by: Samuel Holland <samuel@sholland.org>
---
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
@@ -69,7 +69,7 @@
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
};

View File

@ -18,9 +18,19 @@ roqos-roqos-core-rc10)
ucidef_set_interfaces_lan_wan "eth1" "eth0"
;;
sophos-sg-105r1|sophos-xg-105r1| \
sophos-sg-105r2|sophos-xg-105r2)
sophos-sg-105Wr1|sophos-xg-105Wr1| \
sophos-sg-105r2|sophos-xg-105r2| \
sophos-sg-105Wr2|sophos-xg-105Wr2| \
sophos-sg-115r1|sophos-xg-115r1| \
sophos-sg-115Wr1|sophos-xg-115Wr1| \
sophos-sg-115r2|sophos-xg-115r2| \
sophos-sg-115Wr2|sophos-xg-115Wr2)
ucidef_set_interfaces_lan_wan "eth0 eth2 eth3" "eth1"
;;
sophos-sg-125r1|sophos-xg-125r1| \
sophos-sg-125Wr1|sophos-xg-125Wr1| \
sophos-sg-125r2|sophos-xg-125r2| \
sophos-sg-125Wr2|sophos-xg-125Wr2| \
sophos-sg-135r1|sophos-xg-135r1| \
sophos-sg-135Wr1|sophos-xg-135Wr1| \
sophos-sg-135r2|sophos-xg-135r2| \

View File

@ -26,7 +26,7 @@ do_sysinfo_x86() {
local product_version
product_version="$(cat /sys/devices/virtual/dmi/id/product_version 2>/dev/null)"
case "$product_version" in
105*|135*)
105*|115*|125*|135*)
product="${product}-${product_version}"
break
;;

View File

@ -7,14 +7,14 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=cmake
PKG_VERSION:=3.22.0
PKG_VERSION:=3.22.1
PKG_RELEASE:=1
PKG_CPE_ID:=cpe:/a:kitware:cmake
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/Kitware/CMake/releases/download/v$(PKG_VERSION)/ \
https://cmake.org/files/v3.19/
PKG_HASH:=998c7ba34778d2dfdb3df8a695469e24b11e2bfa21fbe41b361a3f45e1c9345e
PKG_HASH:=0e998229549d7b3f368703d20e248e7ee1f853910d42704aa87918c213ea82c0
HOST_BUILD_PARALLEL:=1
HOST_CONFIGURE_PARALLEL:=1