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rockchip: add LED configuration for FastRhino R68S

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
(cherry picked from commit 7564d4123a)
This commit is contained in:
Tianling Shen 2023-08-23 12:45:07 +08:00
parent 5a6a452a74
commit 1f92f2faf4
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
2 changed files with 18 additions and 9 deletions
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2
target/linux/rockchip/patches-5.15/105-nanopi-r4s-sd-signalling.patch
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@ -22,7 +22,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
status = "okay";
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
@@ -132,6 +132,11 @@
@@ -119,6 +119,11 @@
status = "disabled";
};

25
target/linux/rockchip/patches-5.15/103-arm64-rockchip-add-OF-node-for-eth.patch → target/linux/rockchip/patches-5.15/610-arm64-rockchip-add-OF-node-for-eth.patch
View File

@ -24,7 +24,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
+};
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -401,9 +401,11 @@
@@ -405,9 +405,11 @@
#size-cells = <0>;
/* Second port is for USB 3.0 */
@ -104,10 +104,22 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
@@ -88,6 +90,34 @@
@@ -76,6 +78,7 @@
reg = <0>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-names = "default";
+ realtek,led-data = <0x6d60>;
};
};
@@ -85,6 +88,35 @@
reg = <0>;
pinctrl-0 = <&eth_phy1_reset_pin>;
pinctrl-names = "default";
+ realtek,led-data = <0x6d60>;
+ };
+};
+
+&pcie3x1 {
+ pcie@0,0 {
+ reg = <0x00100000 0 0 0 0>;
@ -133,9 +145,6 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
+ reg = <0x000000 0 0 0 0>;
+ label = "eth2";
+ };
+ };
+};
+
&pinctrl {
gmac0 {
eth_phy0_reset_pin: eth-phy0-reset-pin {
};
};