diff --git a/target/linux/generic/backport-5.15/791-v6.6-11-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch b/target/linux/generic/backport-5.15/791-v6.6-11-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch new file mode 100644 index 0000000000..010ca9b68a --- /dev/null +++ b/target/linux/generic/backport-5.15/791-v6.6-11-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch @@ -0,0 +1,170 @@ +From 7a561e9351ae7e3fb1f08584d40b49c1e55dde60 Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Thu, 20 Jul 2023 19:15:09 +0800 +Subject: [PATCH] net: phy: motorcomm: Add pad drive strength cfg support + +The motorcomm phy (YT8531) supports the ability to adjust the drive +strength of the rx_clk/rx_data, and the default strength may not be +suitable for all boards. So add configurable options to better match +the boards.(e.g. StarFive VisionFive 2) + +When we configure the drive strength, we need to read the current +LDO voltage value to ensure that it is a legal value at that LDO +voltage. + +Reviewed-by: Hal Feng +Signed-off-by: Samin Guo +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/phy/motorcomm.c | 118 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 118 insertions(+) + +--- a/drivers/net/phy/motorcomm.c ++++ b/drivers/net/phy/motorcomm.c +@@ -163,6 +163,10 @@ + + #define YT8521_CHIP_CONFIG_REG 0xA001 + #define YT8521_CCR_SW_RST BIT(15) ++#define YT8531_RGMII_LDO_VOL_MASK GENMASK(5, 4) ++#define YT8531_LDO_VOL_3V3 0x0 ++#define YT8531_LDO_VOL_1V8 0x2 ++ + /* 1b0 disable 1.9ns rxc clock delay *default* + * 1b1 enable 1.9ns rxc clock delay + */ +@@ -236,6 +240,12 @@ + */ + #define YTPHY_WCR_TYPE_PULSE BIT(0) + ++#define YTPHY_PAD_DRIVE_STRENGTH_REG 0xA010 ++#define YT8531_RGMII_RXC_DS_MASK GENMASK(15, 13) ++#define YT8531_RGMII_RXD_DS_HI_MASK BIT(12) /* Bit 2 of rxd_ds */ ++#define YT8531_RGMII_RXD_DS_LOW_MASK GENMASK(5, 4) /* Bit 1/0 of rxd_ds */ ++#define YT8531_RGMII_RX_DS_DEFAULT 0x3 ++ + #define YTPHY_SYNCE_CFG_REG 0xA012 + #define YT8521_SCR_SYNCE_ENABLE BIT(5) + /* 1b0 output 25m clock +@@ -835,6 +845,110 @@ static int ytphy_rgmii_clk_delay_config_ + } + + /** ++ * struct ytphy_ldo_vol_map - map a current value to a register value ++ * @vol: ldo voltage ++ * @ds: value in the register ++ * @cur: value in device configuration ++ */ ++struct ytphy_ldo_vol_map { ++ u32 vol; ++ u32 ds; ++ u32 cur; ++}; ++ ++static const struct ytphy_ldo_vol_map yt8531_ldo_vol[] = { ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 0, .cur = 1200}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 1, .cur = 2100}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 2, .cur = 2700}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 3, .cur = 2910}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 4, .cur = 3110}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 5, .cur = 3600}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 6, .cur = 3970}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 7, .cur = 4350}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 0, .cur = 3070}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 1, .cur = 4080}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 2, .cur = 4370}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 3, .cur = 4680}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 4, .cur = 5020}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 5, .cur = 5450}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 6, .cur = 5740}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 7, .cur = 6140}, ++}; ++ ++static u32 yt8531_get_ldo_vol(struct phy_device *phydev) ++{ ++ u32 val; ++ ++ val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); ++ val = FIELD_GET(YT8531_RGMII_LDO_VOL_MASK, val); ++ ++ return val <= YT8531_LDO_VOL_1V8 ? val : YT8531_LDO_VOL_1V8; ++} ++ ++static int yt8531_get_ds_map(struct phy_device *phydev, u32 cur) ++{ ++ u32 vol; ++ int i; ++ ++ vol = yt8531_get_ldo_vol(phydev); ++ for (i = 0; i < ARRAY_SIZE(yt8531_ldo_vol); i++) { ++ if (yt8531_ldo_vol[i].vol == vol && yt8531_ldo_vol[i].cur == cur) ++ return yt8531_ldo_vol[i].ds; ++ } ++ ++ return -EINVAL; ++} ++ ++static int yt8531_set_ds(struct phy_device *phydev) ++{ ++ struct device_node *node = phydev->mdio.dev.of_node; ++ u32 ds_field_low, ds_field_hi, val; ++ int ret, ds; ++ ++ /* set rgmii rx clk driver strength */ ++ if (!of_property_read_u32(node, "motorcomm,rx-clk-drv-microamp", &val)) { ++ ds = yt8531_get_ds_map(phydev, val); ++ if (ds < 0) ++ return dev_err_probe(&phydev->mdio.dev, ds, ++ "No matching current value was found.\n"); ++ } else { ++ ds = YT8531_RGMII_RX_DS_DEFAULT; ++ } ++ ++ ret = ytphy_modify_ext_with_lock(phydev, ++ YTPHY_PAD_DRIVE_STRENGTH_REG, ++ YT8531_RGMII_RXC_DS_MASK, ++ FIELD_PREP(YT8531_RGMII_RXC_DS_MASK, ds)); ++ if (ret < 0) ++ return ret; ++ ++ /* set rgmii rx data driver strength */ ++ if (!of_property_read_u32(node, "motorcomm,rx-data-drv-microamp", &val)) { ++ ds = yt8531_get_ds_map(phydev, val); ++ if (ds < 0) ++ return dev_err_probe(&phydev->mdio.dev, ds, ++ "No matching current value was found.\n"); ++ } else { ++ ds = YT8531_RGMII_RX_DS_DEFAULT; ++ } ++ ++ ds_field_hi = FIELD_GET(BIT(2), ds); ++ ds_field_hi = FIELD_PREP(YT8531_RGMII_RXD_DS_HI_MASK, ds_field_hi); ++ ++ ds_field_low = FIELD_GET(GENMASK(1, 0), ds); ++ ds_field_low = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW_MASK, ds_field_low); ++ ++ ret = ytphy_modify_ext_with_lock(phydev, ++ YTPHY_PAD_DRIVE_STRENGTH_REG, ++ YT8531_RGMII_RXD_DS_LOW_MASK | YT8531_RGMII_RXD_DS_HI_MASK, ++ ds_field_low | ds_field_hi); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++/** + * yt8521_probe() - read chip config then set suitable polling_mode + * @phydev: a pointer to a &struct phy_device + * +@@ -1518,6 +1632,10 @@ static int yt8531_config_init(struct phy + return ret; + } + ++ ret = yt8531_set_ds(phydev); ++ if (ret < 0) ++ return ret; ++ + return 0; + } + diff --git a/target/linux/generic/backport-6.1/791-v6.6-11-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch b/target/linux/generic/backport-6.1/791-v6.6-11-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch new file mode 100644 index 0000000000..010ca9b68a --- /dev/null +++ b/target/linux/generic/backport-6.1/791-v6.6-11-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch @@ -0,0 +1,170 @@ +From 7a561e9351ae7e3fb1f08584d40b49c1e55dde60 Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Thu, 20 Jul 2023 19:15:09 +0800 +Subject: [PATCH] net: phy: motorcomm: Add pad drive strength cfg support + +The motorcomm phy (YT8531) supports the ability to adjust the drive +strength of the rx_clk/rx_data, and the default strength may not be +suitable for all boards. So add configurable options to better match +the boards.(e.g. StarFive VisionFive 2) + +When we configure the drive strength, we need to read the current +LDO voltage value to ensure that it is a legal value at that LDO +voltage. + +Reviewed-by: Hal Feng +Signed-off-by: Samin Guo +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/phy/motorcomm.c | 118 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 118 insertions(+) + +--- a/drivers/net/phy/motorcomm.c ++++ b/drivers/net/phy/motorcomm.c +@@ -163,6 +163,10 @@ + + #define YT8521_CHIP_CONFIG_REG 0xA001 + #define YT8521_CCR_SW_RST BIT(15) ++#define YT8531_RGMII_LDO_VOL_MASK GENMASK(5, 4) ++#define YT8531_LDO_VOL_3V3 0x0 ++#define YT8531_LDO_VOL_1V8 0x2 ++ + /* 1b0 disable 1.9ns rxc clock delay *default* + * 1b1 enable 1.9ns rxc clock delay + */ +@@ -236,6 +240,12 @@ + */ + #define YTPHY_WCR_TYPE_PULSE BIT(0) + ++#define YTPHY_PAD_DRIVE_STRENGTH_REG 0xA010 ++#define YT8531_RGMII_RXC_DS_MASK GENMASK(15, 13) ++#define YT8531_RGMII_RXD_DS_HI_MASK BIT(12) /* Bit 2 of rxd_ds */ ++#define YT8531_RGMII_RXD_DS_LOW_MASK GENMASK(5, 4) /* Bit 1/0 of rxd_ds */ ++#define YT8531_RGMII_RX_DS_DEFAULT 0x3 ++ + #define YTPHY_SYNCE_CFG_REG 0xA012 + #define YT8521_SCR_SYNCE_ENABLE BIT(5) + /* 1b0 output 25m clock +@@ -835,6 +845,110 @@ static int ytphy_rgmii_clk_delay_config_ + } + + /** ++ * struct ytphy_ldo_vol_map - map a current value to a register value ++ * @vol: ldo voltage ++ * @ds: value in the register ++ * @cur: value in device configuration ++ */ ++struct ytphy_ldo_vol_map { ++ u32 vol; ++ u32 ds; ++ u32 cur; ++}; ++ ++static const struct ytphy_ldo_vol_map yt8531_ldo_vol[] = { ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 0, .cur = 1200}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 1, .cur = 2100}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 2, .cur = 2700}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 3, .cur = 2910}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 4, .cur = 3110}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 5, .cur = 3600}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 6, .cur = 3970}, ++ {.vol = YT8531_LDO_VOL_1V8, .ds = 7, .cur = 4350}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 0, .cur = 3070}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 1, .cur = 4080}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 2, .cur = 4370}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 3, .cur = 4680}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 4, .cur = 5020}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 5, .cur = 5450}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 6, .cur = 5740}, ++ {.vol = YT8531_LDO_VOL_3V3, .ds = 7, .cur = 6140}, ++}; ++ ++static u32 yt8531_get_ldo_vol(struct phy_device *phydev) ++{ ++ u32 val; ++ ++ val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); ++ val = FIELD_GET(YT8531_RGMII_LDO_VOL_MASK, val); ++ ++ return val <= YT8531_LDO_VOL_1V8 ? val : YT8531_LDO_VOL_1V8; ++} ++ ++static int yt8531_get_ds_map(struct phy_device *phydev, u32 cur) ++{ ++ u32 vol; ++ int i; ++ ++ vol = yt8531_get_ldo_vol(phydev); ++ for (i = 0; i < ARRAY_SIZE(yt8531_ldo_vol); i++) { ++ if (yt8531_ldo_vol[i].vol == vol && yt8531_ldo_vol[i].cur == cur) ++ return yt8531_ldo_vol[i].ds; ++ } ++ ++ return -EINVAL; ++} ++ ++static int yt8531_set_ds(struct phy_device *phydev) ++{ ++ struct device_node *node = phydev->mdio.dev.of_node; ++ u32 ds_field_low, ds_field_hi, val; ++ int ret, ds; ++ ++ /* set rgmii rx clk driver strength */ ++ if (!of_property_read_u32(node, "motorcomm,rx-clk-drv-microamp", &val)) { ++ ds = yt8531_get_ds_map(phydev, val); ++ if (ds < 0) ++ return dev_err_probe(&phydev->mdio.dev, ds, ++ "No matching current value was found.\n"); ++ } else { ++ ds = YT8531_RGMII_RX_DS_DEFAULT; ++ } ++ ++ ret = ytphy_modify_ext_with_lock(phydev, ++ YTPHY_PAD_DRIVE_STRENGTH_REG, ++ YT8531_RGMII_RXC_DS_MASK, ++ FIELD_PREP(YT8531_RGMII_RXC_DS_MASK, ds)); ++ if (ret < 0) ++ return ret; ++ ++ /* set rgmii rx data driver strength */ ++ if (!of_property_read_u32(node, "motorcomm,rx-data-drv-microamp", &val)) { ++ ds = yt8531_get_ds_map(phydev, val); ++ if (ds < 0) ++ return dev_err_probe(&phydev->mdio.dev, ds, ++ "No matching current value was found.\n"); ++ } else { ++ ds = YT8531_RGMII_RX_DS_DEFAULT; ++ } ++ ++ ds_field_hi = FIELD_GET(BIT(2), ds); ++ ds_field_hi = FIELD_PREP(YT8531_RGMII_RXD_DS_HI_MASK, ds_field_hi); ++ ++ ds_field_low = FIELD_GET(GENMASK(1, 0), ds); ++ ds_field_low = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW_MASK, ds_field_low); ++ ++ ret = ytphy_modify_ext_with_lock(phydev, ++ YTPHY_PAD_DRIVE_STRENGTH_REG, ++ YT8531_RGMII_RXD_DS_LOW_MASK | YT8531_RGMII_RXD_DS_HI_MASK, ++ ds_field_low | ds_field_hi); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++/** + * yt8521_probe() - read chip config then set suitable polling_mode + * @phydev: a pointer to a &struct phy_device + * +@@ -1518,6 +1632,10 @@ static int yt8531_config_init(struct phy + return ret; + } + ++ ret = yt8531_set_ds(phydev); ++ if (ret < 0) ++ return ret; ++ + return 0; + } + diff --git a/target/linux/rockchip/patches-6.1/039-01-v6.4-usb-typec-tcpm-try-to-get-role-switch-from-tcpc-fwnode.patch b/target/linux/rockchip/patches-6.1/039-01-v6.4-usb-typec-tcpm-try-to-get-role-switch-from-tcpc-fwnode.patch index a3f8a08795..b083e8373b 100644 --- a/target/linux/rockchip/patches-6.1/039-01-v6.4-usb-typec-tcpm-try-to-get-role-switch-from-tcpc-fwnode.patch +++ b/target/linux/rockchip/patches-6.1/039-01-v6.4-usb-typec-tcpm-try-to-get-role-switch-from-tcpc-fwnode.patch @@ -43,7 +43,7 @@ Signed-off-by: Greg Kroah-Hartman --- a/drivers/usb/typec/tcpm/tcpm.c +++ b/drivers/usb/typec/tcpm/tcpm.c -@@ -6586,6 +6586,8 @@ struct tcpm_port *tcpm_register_port(str +@@ -6595,6 +6595,8 @@ struct tcpm_port *tcpm_register_port(str port->port_type = port->typec_caps.type; port->role_sw = usb_role_switch_get(port->dev); diff --git a/target/linux/rockchip/patches-6.1/113-01-usb-dwc3-add-optional-PHY-interface-clocks.patch b/target/linux/rockchip/patches-6.1/113-01-usb-dwc3-add-optional-PHY-interface-clocks.patch index 65007d9cf9..f1904f91b1 100644 --- a/target/linux/rockchip/patches-6.1/113-01-usb-dwc3-add-optional-PHY-interface-clocks.patch +++ b/target/linux/rockchip/patches-6.1/113-01-usb-dwc3-add-optional-PHY-interface-clocks.patch @@ -45,7 +45,7 @@ Signed-off-by: Sebastian Reichel clk_disable_unprepare(dwc->susp_clk); clk_disable_unprepare(dwc->ref_clk); clk_disable_unprepare(dwc->bus_clk); -@@ -1875,6 +1889,18 @@ static int dwc3_probe(struct platform_de +@@ -1963,6 +1977,18 @@ static int dwc3_probe(struct platform_de goto put_usb_psy; } } @@ -66,7 +66,7 @@ Signed-off-by: Sebastian Reichel ret = reset_control_deassert(dwc->reset); --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h -@@ -986,6 +986,8 @@ struct dwc3_scratchpad_array { +@@ -991,6 +991,8 @@ struct dwc3_scratchpad_array { * @bus_clk: clock for accessing the registers * @ref_clk: reference clock * @susp_clk: clock used when the SS phy is in low power (S3) state @@ -75,7 +75,7 @@ Signed-off-by: Sebastian Reichel * @reset: reset control * @regs: base address for our registers * @regs_size: address space size -@@ -1150,6 +1152,8 @@ struct dwc3 { +@@ -1159,6 +1161,8 @@ struct dwc3 { struct clk *bus_clk; struct clk *ref_clk; struct clk *susp_clk; diff --git a/target/linux/rockchip/patches-6.1/113-02-usb-typec-tcpm-avoid-graph-warning.patch b/target/linux/rockchip/patches-6.1/113-02-usb-typec-tcpm-avoid-graph-warning.patch index 85b0016517..81f74ebc58 100644 --- a/target/linux/rockchip/patches-6.1/113-02-usb-typec-tcpm-avoid-graph-warning.patch +++ b/target/linux/rockchip/patches-6.1/113-02-usb-typec-tcpm-avoid-graph-warning.patch @@ -28,7 +28,7 @@ Signed-off-by: Sebastian Reichel --- a/drivers/usb/typec/tcpm/tcpm.c +++ b/drivers/usb/typec/tcpm/tcpm.c -@@ -6585,9 +6585,9 @@ struct tcpm_port *tcpm_register_port(str +@@ -6594,9 +6594,9 @@ struct tcpm_port *tcpm_register_port(str port->partner_desc.identity = &port->partner_ident; port->port_type = port->typec_caps.type; diff --git a/target/linux/rockchip/patches-6.1/501-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-6.1/501-mmc-core-set-initial-signal-voltage-on-power-off.patch index 9b1f0bb0aa..d462899007 100644 --- a/target/linux/rockchip/patches-6.1/501-mmc-core-set-initial-signal-voltage-on-power-off.patch +++ b/target/linux/rockchip/patches-6.1/501-mmc-core-set-initial-signal-voltage-on-power-off.patch @@ -24,7 +24,7 @@ Signed-off-by: Jonas Karlman --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c -@@ -1366,6 +1366,8 @@ void mmc_power_off(struct mmc_host *host +@@ -1371,6 +1371,8 @@ void mmc_power_off(struct mmc_host *host mmc_pwrseq_power_off(host); diff --git a/target/linux/rockchip/patches-6.1/600-net-ethernet-r8169-add-LED-configuration-from-OF.patch b/target/linux/rockchip/patches-6.1/600-net-ethernet-r8169-add-LED-configuration-from-OF.patch index 88c53c9094..d8be6d735a 100644 --- a/target/linux/rockchip/patches-6.1/600-net-ethernet-r8169-add-LED-configuration-from-OF.patch +++ b/target/linux/rockchip/patches-6.1/600-net-ethernet-r8169-add-LED-configuration-from-OF.patch @@ -16,7 +16,7 @@ TxDescStartAddrLow = 0x20, TxDescStartAddrHigh = 0x24, TxHDescStartAddrLow = 0x28, -@@ -2096,6 +2098,22 @@ void r8169_apply_firmware(struct rtl8169 +@@ -2111,6 +2113,22 @@ void r8169_apply_firmware(struct rtl8169 } } @@ -39,7 +39,7 @@ static void rtl8168_config_eee_mac(struct rtl8169_private *tp) { /* Adjust EEE LED frequency */ -@@ -3242,6 +3260,8 @@ static void rtl_hw_start_8168h_1(struct +@@ -3255,6 +3273,8 @@ static void rtl_hw_start_8168h_1(struct r8168_mac_ocp_write(tp, 0xc094, 0x0000); r8168_mac_ocp_write(tp, 0xc09e, 0x0000); @@ -48,7 +48,7 @@ rtl_hw_aspm_clkreq_enable(tp, true); } -@@ -3614,6 +3634,8 @@ static void rtl_hw_start_8125b(struct rt +@@ -3627,6 +3647,8 @@ static void rtl_hw_start_8125b(struct rt rtl_ephy_init(tp, e_info_8125b); rtl_hw_start_8125_common(tp); diff --git a/target/linux/rockchip/patches-6.1/601-net-phy-motorcomm-add-LED-configuration-for-yt85xx.patch b/target/linux/rockchip/patches-6.1/601-net-phy-motorcomm-add-LED-configuration-for-yt85xx.patch index d175abe3b1..bf7ae5d26f 100644 --- a/target/linux/rockchip/patches-6.1/601-net-phy-motorcomm-add-LED-configuration-for-yt85xx.patch +++ b/target/linux/rockchip/patches-6.1/601-net-phy-motorcomm-add-LED-configuration-for-yt85xx.patch @@ -1,6 +1,6 @@ --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c -@@ -224,6 +224,12 @@ +@@ -228,6 +228,12 @@ #define YTPHY_WCR_INTR_SEL BIT(6) #define YTPHY_WCR_ENABLE BIT(3) @@ -13,7 +13,7 @@ /* 2b00 84ms * 2b01 168ms *default* * 2b10 336ms -@@ -1450,6 +1456,27 @@ static int yt8521_resume(struct phy_devi +@@ -1564,6 +1570,27 @@ static int yt8521_resume(struct phy_devi return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0); } @@ -21,7 +21,7 @@ +{ + struct device_node *node = phydev->mdio.dev.of_node; + u32 led_data[YTPHY_LED_NUM_CONFIG]; -+ int ret; ++ int ret; + + ret = of_property_read_u32_array(node, "motorcomm,led-data", + led_data, YTPHY_LED_NUM_CONFIG); @@ -41,7 +41,7 @@ /** * yt8521_config_init() - called to initialize the PHY * @phydev: a pointer to a &struct phy_device -@@ -1488,6 +1515,10 @@ static int yt8521_config_init(struct phy +@@ -1602,6 +1629,10 @@ static int yt8521_config_init(struct phy if (ret < 0) goto err_restore_page; } @@ -52,9 +52,9 @@ err_restore_page: return phy_restore_page(phydev, old_page, ret); } -@@ -1519,7 +1550,7 @@ static int yt8531_config_init(struct phy - return ret; - } +@@ -1637,7 +1668,7 @@ static int yt8531_config_init(struct phy + if (ret < 0) + return ret; - return 0; + return ytphy_config_led(phydev); diff --git a/target/linux/rockchip/patches-6.1/602-net-ethernet-r8169-add-devname-configuration-from-OF.patch b/target/linux/rockchip/patches-6.1/602-net-ethernet-r8169-add-devname-configuration-from-OF.patch index 4947739c4c..bddc4f3d02 100644 --- a/target/linux/rockchip/patches-6.1/602-net-ethernet-r8169-add-devname-configuration-from-OF.patch +++ b/target/linux/rockchip/patches-6.1/602-net-ethernet-r8169-add-devname-configuration-from-OF.patch @@ -1,6 +1,6 @@ --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c -@@ -2098,6 +2098,22 @@ void r8169_apply_firmware(struct rtl8169 +@@ -2113,6 +2113,22 @@ void r8169_apply_firmware(struct rtl8169 } } @@ -23,7 +23,7 @@ static int rtl8169_led_configuration(struct rtl8169_private *tp) { u32 led_data; -@@ -3634,6 +3650,7 @@ static void rtl_hw_start_8125b(struct rt +@@ -3647,6 +3663,7 @@ static void rtl_hw_start_8125b(struct rt rtl_ephy_init(tp, e_info_8125b); rtl_hw_start_8125_common(tp); diff --git a/target/linux/rockchip/patches-6.1/603-net-ethernet-stmmac-add-devname-configuration-from-OF.patch b/target/linux/rockchip/patches-6.1/603-net-ethernet-stmmac-add-devname-configuration-from-OF.patch index ab1f9647b2..04013c14a7 100644 --- a/target/linux/rockchip/patches-6.1/603-net-ethernet-stmmac-add-devname-configuration-from-OF.patch +++ b/target/linux/rockchip/patches-6.1/603-net-ethernet-stmmac-add-devname-configuration-from-OF.patch @@ -1,6 +1,6 @@ --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -7085,6 +7085,7 @@ int stmmac_dvr_probe(struct device *devi +@@ -7086,6 +7086,7 @@ int stmmac_dvr_probe(struct device *devi { struct net_device *ndev = NULL; struct stmmac_priv *priv; @@ -8,7 +8,7 @@ u32 rxq; int i, ret = 0; -@@ -7093,6 +7094,9 @@ int stmmac_dvr_probe(struct device *devi +@@ -7094,6 +7095,9 @@ int stmmac_dvr_probe(struct device *devi if (!ndev) return -ENOMEM;