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Merge Official Source

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2024-02-14 12:49:25 +08:00
commit 251169853d
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
14 changed files with 344 additions and 175 deletions
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11
package/base-files/files/lib/functions/uci-defaults.sh
View File

@ -654,6 +654,17 @@ ucidef_set_ntpserver() {
json_select ..
}
ucidef_set_poe() {
json_select_object poe
json_add_string "budget" "$1"
json_select_array ports
for port in $2; do
json_add_string "" "$port"
done
json_select ..
json_select ..
}
ucidef_add_wlan() {
local path="$1"; shift

4
package/devel/binutils/Makefile
View File

@ -8,13 +8,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=binutils
PKG_VERSION:=2.41
PKG_VERSION:=2.42
PKG_RELEASE:=1
PKG_SOURCE_URL:=@GNU/binutils
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_VERSION:=$(PKG_VERSION)
PKG_HASH:=ae9a5789e23459e59606e6714723f2d3ffc31c03174191ef0d015bdf06007450
PKG_HASH:=f6e4d41fd5fc778b06b7891457b3620da5ecea1006c6a4a41ae998109f85a800
PKG_FIXUP:=patch-libtool
PKG_LIBTOOL_PATHS:=. gas bfd opcodes gprof gprofng binutils ld libiberty gold intl libctf libsframe

10
package/devel/binutils/patches/001-replace-attribute_const.patch
View File

@ -28,8 +28,8 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
unsigned int *ecx ATTRIBUTE_UNUSED, unsigned int *edx ATTRIBUTE_UNUSED)
--- a/gprofng/libcollector/unwind.c
+++ b/gprofng/libcollector/unwind.c
@@ -233,7 +233,7 @@ memory_error_func (int status ATTRIBUTE_
#elif ARCH(Aarch64)
@@ -237,7 +237,7 @@ typedef uint64_t __u64;
#define FILL_CONTEXT(context) \
{ CALL_UTIL (getcontext) (context); \
- context->uc_mcontext.sp = (__u64) __builtin_frame_address(0); \
@ -37,7 +37,7 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
}
#endif /* ARCH() */
@@ -4579,11 +4579,11 @@ stack_unwind (char *buf, int size, void
@@ -4583,11 +4583,11 @@ stack_unwind (char *buf, int size, void
if (buf && bptr && eptr && context && size + mode > 0)
getByteInstruction ((unsigned char *) eptr);
int ind = 0;
@ -54,7 +54,7 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
unsigned long tbgn = 0;
unsigned long tend = 0;
@@ -4594,7 +4594,7 @@ stack_unwind (char *buf, int size, void
@@ -4598,7 +4598,7 @@ stack_unwind (char *buf, int size, void
{
stack_base = sp + 0x100000;
if (stack_base < sp) // overflow
@ -63,7 +63,7 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
}
DprintfT (SP_DUMP_UNWIND,
"unwind.c:%d stack_unwind %2d pc=0x%llx sp=0x%llx stack_base=0x%llx\n",
@@ -4625,17 +4625,17 @@ stack_unwind (char *buf, int size, void
@@ -4629,17 +4629,17 @@ stack_unwind (char *buf, int size, void
__LINE__, (unsigned long) sp);
break;
}

4
package/libs/libxml2/Makefile
View File

@ -1,12 +1,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=libxml2
PKG_VERSION:=2.12.4
PKG_VERSION:=2.12.5
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNOME/libxml2/$(basename $(PKG_VERSION))
PKG_HASH:=497360e423cf0bd99eacdb7c6215dea92e6d6e89ee940393c2bae0e77cb9b7d0
PKG_HASH:=a972796696afd38073e0f59c283c3a2f5a560b5268b4babc391b286166526b21
PKG_LICENSE:=MIT
PKG_LICENSE_FILES:=COPYING

3
package/network/config/wifi-scripts/files/usr/share/hostap/wifi-detect.uc
View File

@ -39,8 +39,9 @@ function cleanup() {
}
function wiphy_get_entry(phy, path) {
let wlan = board_data.wlan;
board_data.wlan ??= {};
let wlan = board_data.wlan;
for (let name in wlan)
if (wlan[name].path == path)
return wlan[name];

6
package/utils/ucode/Makefile
View File

@ -12,9 +12,9 @@ PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/jow-/ucode.git
PKG_SOURCE_DATE:=2023-11-30
PKG_SOURCE_VERSION:=6e89b89e95bbb140bbff5ab72b8c9632727bf6a6
PKG_MIRROR_HASH:=20ba99f8c2591b581cdf0245dd40301e517659193cddaa3a3888125fcc85b2aa
PKG_SOURCE_DATE:=2024-02-13
PKG_SOURCE_VERSION:=3f9811d2f7b730f1f1d030872ae1def7e8349be6
PKG_MIRROR_HASH:=b05cdaa6ecaf8c4b79e67551085c5580d09c5940304b5837a859324abbb26e94
PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
PKG_LICENSE:=ISC

143
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
View File

@ -31,11 +31,12 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a73";
enable-method = "psci";
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
@ -44,10 +45,10 @@
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a73";
enable-method = "psci";
reg = <0x1>;
device_type = "cpu";
enable-method = "psci";
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
@ -56,10 +57,10 @@
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a73";
enable-method = "psci";
reg = <0x2>;
device_type = "cpu";
enable-method = "psci";
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
@ -68,10 +69,10 @@
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a73";
enable-method = "psci";
reg = <0x3>;
device_type = "cpu";
enable-method = "psci";
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
@ -82,18 +83,22 @@
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <850000>;
};
opp01 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <850000>;
};
opp02 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <850000>;
};
opp03 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <900000>;
@ -104,18 +109,22 @@
cci_opp: opp_table_cci {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <480000000>;
opp-microvolt = <850000>;
};
opp01 {
opp-hz = /bits/ 64 <660000000>;
opp-microvolt = <850000>;
};
opp02 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <850000>;
};
opp03 {
opp-hz = /bits/ 64 <1080000000>;
opp-microvolt = <900000>;
@ -136,8 +145,8 @@
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
compatible = "arm,psci-0.2";
method = "smc";
};
reg_1p8v: regulator-1p8v {
@ -159,9 +168,9 @@
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
secmon_reserved: secmon@43000000 {
@ -171,23 +180,22 @@
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
#address-cells = <2>;
#size-cells = <2>;
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, /* GICD */
<0 0x0c080000 0 0x200000>, /* GICR */
<0 0x0c400000 0 0x2000>, /* GICC */
<0 0x0c410000 0 0x1000>, /* GICH */
<0 0x0c420000 0 0x2000>; /* GICV */
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
};
phyfw: phy-firmware@f000000 {
@ -227,12 +235,12 @@
pio: pinctrl@1001f000 {
compatible = "mediatek,mt7988-pinctrl", "syscon";
reg = <0 0x1001f000 0 0x1000>,
<0 0x11c10000 0 0x1000>,
<0 0x11d00000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11e00000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
<0 0x11c10000 0 0x1000>,
<0 0x11d00000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11e00000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio_base", "iocfg_tr_base",
"iocfg_br_base", "iocfg_rb_base",
"iocfg_lb_base", "iocfg_tl_base", "eint";
@ -682,12 +690,12 @@
lvts: lvts@1100a000 {
compatible = "mediatek,mt7988-lvts";
#thermal-sensor-cells = <1>;
reg = <0 0x1100a000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
clock-names = "lvts_clk";
nvmem-cells = <&lvts_calibration>;
nvmem-cell-names = "e_data1";
#thermal-sensor-cells = <1>;
};
ssusb0: usb@11190000 {
@ -795,18 +803,16 @@
compatible = "mediatek,mt7988-pcie",
"mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x11280000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <3>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x00 0x20000000 0x00
0x20000000 0x00 0x00200000>,
<0x82000000 0x00 0x20200000 0x00
0x20200000 0x00 0x07e00000>;
device_type = "pci";
linux,pci-domain = <3>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
@ -815,17 +821,18 @@
"top_133m";
pinctrl-names = "default";
pinctrl-0 = <&pcie2_pins>;
status = "disabled";
phys = <&xphyu3port0 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc2 0>,
<0 0 0 2 &pcie_intc2 1>,
<0 0 0 3 &pcie_intc2 2>,
<0 0 0 4 &pcie_intc2 3>;
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie_intc2: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
@ -837,18 +844,16 @@
compatible = "mediatek,mt7988-pcie",
"mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x11290000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <2>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x00 0x28000000 0x00
0x28000000 0x00 0x00200000>,
<0x82000000 0x00 0x28200000 0x00
0x28200000 0x00 0x07e00000>;
device_type = "pci";
linux,pci-domain = <2>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
@ -857,14 +862,16 @@
"top_133m";
pinctrl-names = "default";
pinctrl-0 = <&pcie3_pins>;
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc3 0>,
<0 0 0 2 &pcie_intc3 1>,
<0 0 0 3 &pcie_intc3 2>,
<0 0 0 4 &pcie_intc3 3>;
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie_intc3: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
@ -876,18 +883,16 @@
compatible = "mediatek,mt7988-pcie",
"mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x11300000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <0>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x00 0x30000000 0x00
0x30000000 0x00 0x00200000>,
<0x82000000 0x00 0x30200000 0x00
0x30200000 0x00 0x07e00000>;
device_type = "pci";
linux,pci-domain = <0>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
@ -896,14 +901,16 @@
"top_133m";
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie_intc0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
@ -915,18 +922,16 @@
compatible = "mediatek,mt7988-pcie",
"mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x11310000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <1>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x00 0x38000000 0x00
0x38000000 0x00 0x00200000>,
<0x82000000 0x00 0x38200000 0x00
0x38200000 0x00 0x07e00000>;
device_type = "pci";
linux,pci-domain = <1>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
@ -935,14 +940,16 @@
"top_133m";
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie_intc1: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
@ -953,16 +960,18 @@
tphy: tphy@11c50000 {
compatible = "mediatek,mt7988",
"mediatek,generic-tphy-v2";
ranges;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
tphyu2port0: usb-phy@11c50000 {
reg = <0 0x11c50000 0 0x700>;
clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
clock-names = "ref";
#phy-cells = <1>;
};
tphyu3port0: usb-phy@11c50700 {
reg = <0 0x11c50700 0 0x900>;
clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
@ -986,9 +995,9 @@
xphy: xphy@11e10000 {
compatible = "mediatek,mt7988",
"mediatek,xsphy";
ranges;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
xphyu2port0: usb-phy@11e10000 {
@ -1038,35 +1047,38 @@
lvts_calibration: calib@918 {
reg = <0x918 0x28>;
};
phy_calibration_p0: calib@940 {
reg = <0x940 0x10>;
};
phy_calibration_p1: calib@954 {
reg = <0x954 0x10>;
};
phy_calibration_p2: calib@968 {
reg = <0x968 0x10>;
};
phy_calibration_p3: calib@97c {
reg = <0x97c 0x10>;
};
cpufreq_calibration: calib@278 {
reg = <0x278 0x1>;
};
};
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7988-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
};
switch: switch@15020000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7988-switch";
reg = <0 0x15020000 0 0x8000>;
interrupt-controller;
@ -1074,6 +1086,8 @@
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ethrst 0>;
#address-cells = <1>;
#size-cells = <1>;
ports {
#address-cells = <1>;
@ -1352,8 +1366,8 @@
/* internal 2.5G PHY */
int_2p5g_phy: ethernet-phy@15 {
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
reg = <15>;
phy-mode = "internal";
};
};
@ -1376,6 +1390,7 @@
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&lvts 0>;
trips {
cpu_trip_crit: crit {
temperature = <125000>;

143
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
View File

@ -31,11 +31,12 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a73";
enable-method = "psci";
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
@ -44,10 +45,10 @@
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a73";
enable-method = "psci";
reg = <0x1>;
device_type = "cpu";
enable-method = "psci";
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
@ -56,10 +57,10 @@
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a73";
enable-method = "psci";
reg = <0x2>;
device_type = "cpu";
enable-method = "psci";
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
@ -68,10 +69,10 @@
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a73";
enable-method = "psci";
reg = <0x3>;
device_type = "cpu";
enable-method = "psci";
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
@ -82,18 +83,22 @@
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <850000>;
};
opp01 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <850000>;
};
opp02 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <850000>;
};
opp03 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <900000>;
@ -104,18 +109,22 @@
cci_opp: opp_table_cci {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <480000000>;
opp-microvolt = <850000>;
};
opp01 {
opp-hz = /bits/ 64 <660000000>;
opp-microvolt = <850000>;
};
opp02 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <850000>;
};
opp03 {
opp-hz = /bits/ 64 <1080000000>;
opp-microvolt = <900000>;
@ -136,8 +145,8 @@
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
compatible = "arm,psci-0.2";
method = "smc";
};
reg_1p8v: regulator-1p8v {
@ -159,9 +168,9 @@
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
secmon_reserved: secmon@43000000 {
@ -171,23 +180,22 @@
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
#address-cells = <2>;
#size-cells = <2>;
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, /* GICD */
<0 0x0c080000 0 0x200000>, /* GICR */
<0 0x0c400000 0 0x2000>, /* GICC */
<0 0x0c410000 0 0x1000>, /* GICH */
<0 0x0c420000 0 0x2000>; /* GICV */
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
};
phyfw: phy-firmware@f000000 {
@ -227,12 +235,12 @@
pio: pinctrl@1001f000 {
compatible = "mediatek,mt7988-pinctrl", "syscon";
reg = <0 0x1001f000 0 0x1000>,
<0 0x11c10000 0 0x1000>,
<0 0x11d00000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11e00000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
<0 0x11c10000 0 0x1000>,
<0 0x11d00000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11e00000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio_base", "iocfg_tr_base",
"iocfg_br_base", "iocfg_rb_base",
"iocfg_lb_base", "iocfg_tl_base", "eint";
@ -682,12 +690,12 @@
lvts: lvts@1100a000 {
compatible = "mediatek,mt7988-lvts";
#thermal-sensor-cells = <1>;
reg = <0 0x1100a000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
clock-names = "lvts_clk";
nvmem-cells = <&lvts_calibration>;
nvmem-cell-names = "e_data1";
#thermal-sensor-cells = <1>;
};
ssusb0: usb@11190000 {
@ -795,18 +803,16 @@
compatible = "mediatek,mt7988-pcie",
"mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x11280000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <3>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x00 0x20000000 0x00
0x20000000 0x00 0x00200000>,
<0x82000000 0x00 0x20200000 0x00
0x20200000 0x00 0x07e00000>;
device_type = "pci";
linux,pci-domain = <3>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
@ -815,17 +821,18 @@
"top_133m";
pinctrl-names = "default";
pinctrl-0 = <&pcie2_pins>;
status = "disabled";
phys = <&xphyu3port0 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc2 0>,
<0 0 0 2 &pcie_intc2 1>,
<0 0 0 3 &pcie_intc2 2>,
<0 0 0 4 &pcie_intc2 3>;
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie_intc2: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
@ -837,18 +844,16 @@
compatible = "mediatek,mt7988-pcie",
"mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x11290000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <2>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x00 0x28000000 0x00
0x28000000 0x00 0x00200000>,
<0x82000000 0x00 0x28200000 0x00
0x28200000 0x00 0x07e00000>;
device_type = "pci";
linux,pci-domain = <2>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
@ -857,14 +862,16 @@
"top_133m";
pinctrl-names = "default";
pinctrl-0 = <&pcie3_pins>;
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc3 0>,
<0 0 0 2 &pcie_intc3 1>,
<0 0 0 3 &pcie_intc3 2>,
<0 0 0 4 &pcie_intc3 3>;
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie_intc3: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
@ -876,18 +883,16 @@
compatible = "mediatek,mt7988-pcie",
"mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x11300000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <0>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x00 0x30000000 0x00
0x30000000 0x00 0x00200000>,
<0x82000000 0x00 0x30200000 0x00
0x30200000 0x00 0x07e00000>;
device_type = "pci";
linux,pci-domain = <0>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
@ -896,14 +901,16 @@
"top_133m";
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie_intc0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
@ -915,18 +922,16 @@
compatible = "mediatek,mt7988-pcie",
"mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x11310000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <1>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x00 0x38000000 0x00
0x38000000 0x00 0x00200000>,
<0x82000000 0x00 0x38200000 0x00
0x38200000 0x00 0x07e00000>;
device_type = "pci";
linux,pci-domain = <1>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
@ -935,14 +940,16 @@
"top_133m";
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie_intc1: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
@ -953,16 +960,18 @@
tphy: tphy@11c50000 {
compatible = "mediatek,mt7988",
"mediatek,generic-tphy-v2";
ranges;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
tphyu2port0: usb-phy@11c50000 {
reg = <0 0x11c50000 0 0x700>;
clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
clock-names = "ref";
#phy-cells = <1>;
};
tphyu3port0: usb-phy@11c50700 {
reg = <0 0x11c50700 0 0x900>;
clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
@ -986,9 +995,9 @@
xphy: xphy@11e10000 {
compatible = "mediatek,mt7988",
"mediatek,xsphy";
ranges;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
xphyu2port0: usb-phy@11e10000 {
@ -1038,35 +1047,38 @@
lvts_calibration: calib@918 {
reg = <0x918 0x28>;
};
phy_calibration_p0: calib@940 {
reg = <0x940 0x10>;
};
phy_calibration_p1: calib@954 {
reg = <0x954 0x10>;
};
phy_calibration_p2: calib@968 {
reg = <0x968 0x10>;
};
phy_calibration_p3: calib@97c {
reg = <0x97c 0x10>;
};
cpufreq_calibration: calib@278 {
reg = <0x278 0x1>;
};
};
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7988-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
};
switch: switch@15020000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7988-switch";
reg = <0 0x15020000 0 0x8000>;
interrupt-controller;
@ -1074,6 +1086,8 @@
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ethrst 0>;
#address-cells = <1>;
#size-cells = <1>;
ports {
#address-cells = <1>;
@ -1352,8 +1366,8 @@
/* internal 2.5G PHY */
int_2p5g_phy: ethernet-phy@15 {
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
reg = <15>;
phy-mode = "internal";
};
};
@ -1376,6 +1390,7 @@
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&lvts 0>;
trips {
cpu_trip_crit: crit {
temperature = <125000>;

2
target/linux/omap/Makefile
View File

@ -12,7 +12,7 @@ CPU_TYPE:=cortex-a8
CPU_SUBTYPE:=vfpv3
SUBTARGETS:=generic
KERNEL_PATCHVER:=5.15
KERNEL_PATCHVER:=6.1
KERNELNAME:=zImage dtbs

36
target/linux/omap/config-5.15 → target/linux/omap/config-6.1
View File

@ -27,13 +27,12 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_ARM_CRYPTO=y
CONFIG_ARM_ERRATA_430973=y
CONFIG_ARM_ERRATA_720789=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_ARM_ERRATA_775420=y
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_HAS_GROUP_RELOCS=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
@ -65,6 +64,9 @@ CONFIG_BLK_PM=y
CONFIG_BOUNCE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_CACHE_L2X0=y
CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CEC_CORE=y
# CONFIG_CHARGER_TPS65217 is not set
CONFIG_CLKSRC_MMIO=y
@ -87,9 +89,12 @@ CONFIG_CMDLINE_FROM_BOOTLOADER=y
CONFIG_COMMON_CLK=y
# CONFIG_COMMON_CLK_PALMAS is not set
# CONFIG_COMMON_CLK_TI_ADPLL is not set
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONFIGFS_FS=y
CONFIG_CONNECTOR=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CONTIG_ALLOC=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
@ -117,6 +122,7 @@ CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
@ -158,7 +164,9 @@ CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_RNG=y
@ -174,19 +182,17 @@ CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA512_ARM=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DDR=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DM9000=y
# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
CONFIG_DMADEVICES=y
CONFIG_DMA_CMA=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OMAP=y
CONFIG_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DNS_RESOLVER=y
@ -195,6 +201,7 @@ CONFIG_DRM_BRIDGE=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_NOMODESET=y
CONFIG_DRM_OMAP=y
CONFIG_DRM_PANEL=y
CONFIG_DRM_PANEL_BRIDGE=y
@ -213,6 +220,7 @@ CONFIG_DT_IDLE_STATES=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_93CX6=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_EXTCON_PALMAS=y
@ -229,6 +237,8 @@ CONFIG_FS_MBCACHE=y
CONFIG_FS_POSIX_ACL=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
@ -270,7 +280,6 @@ CONFIG_GPIO_TWL4030=y
CONFIG_GPIO_TWL6040=y
CONFIG_GRACE_PERIOD=y
CONFIG_GRO_CELLS=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
@ -298,6 +307,7 @@ CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_RARP=y
CONFIG_IRQCHIP=y
CONFIG_IRQSTACKS=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
@ -408,6 +418,7 @@ CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
@ -433,8 +444,8 @@ CONFIG_OMAP4_DSS_HDMI=y
CONFIG_OMAP4_DSS_HDMI_CEC=y
CONFIG_OMAP4_THERMAL=y
CONFIG_OMAP5_DSS_HDMI=y
CONFIG_OMAP_32K_TIMER=y
CONFIG_OMAP_CONTROL_PHY=y
CONFIG_OMAP_DM_SYSTIMER=y
CONFIG_OMAP_DM_TIMER=y
CONFIG_OMAP_GPMC=y
# CONFIG_OMAP_GPMC_DEBUG is not set
@ -443,7 +454,6 @@ CONFIG_OMAP_INTERCONNECT=y
CONFIG_OMAP_INTERCONNECT_BARRIER=y
CONFIG_OMAP_IRQCHIP=y
CONFIG_OMAP_OCP2SCP=y
CONFIG_OMAP_RESET_CLOCKS=y
# CONFIG_OMAP_SSI is not set
CONFIG_OMAP_USB2=y
CONFIG_OMAP_WATCHDOG=y
@ -453,9 +463,13 @@ CONFIG_OUTER_CACHE_SYNC=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
# CONFIG_PHY_DM816X_USB is not set
CONFIG_PHY_TI_GMII_SEL=y
CONFIG_PINCTRL=y
@ -473,6 +487,7 @@ CONFIG_POWER_AVS_OMAP=y
CONFIG_POWER_AVS_OMAP_CLASS3=y
CONFIG_POWER_SUPPLY=y
CONFIG_PPS=y
CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PRINTK_TIME=y
CONFIG_PRINT_QUOTA_WARNING=y
CONFIG_PROC_EVENTS=y
@ -486,10 +501,12 @@ CONFIG_PWM_TIECAP=y
CONFIG_PWM_TIEHRPWM=y
# CONFIG_PWM_TWL is not set
# CONFIG_PWM_TWL_LED is not set
CONFIG_QCOM_NET_PHYLIB=y
CONFIG_QFMT_V2=y
CONFIG_QUOTA=y
CONFIG_QUOTACTL=y
CONFIG_QUOTA_TREE=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
@ -592,6 +609,7 @@ CONFIG_SOC_BUS=y
CONFIG_SOC_HAS_OMAP2_SDRC=y
CONFIG_SOC_OMAP3430=y
# CONFIG_SOC_TI81XX is not set
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
@ -618,6 +636,7 @@ CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
@ -687,5 +706,6 @@ CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

49
target/linux/realtek/base-files/etc/board.d/02_network
View File

@ -3,25 +3,26 @@
. /lib/functions/uci-defaults.sh
. /lib/functions/system.sh
ucidef_set_poe() {
json_select_object poe
json_add_string "budget" "$1"
json_select_array ports
for port in $2; do
if [ -n "$3" -a -n "$(expr "$3" : "\(.\+[[:space:]]\)\{0,1\}$port\([[:space:]].*\|\$\)")" ]; then
continue # skip ports passed via $3
fi
json_add_string "" "$port"
done
json_select ..
json_select ..
_filter_port_list_ordered() {
local ports="$1"
local excluded="$2"
local sort_opts="$3"
echo $ports $excluded | xargs -n1 basename | sort -V $sort_opts | uniq -u | xargs
}
filter_port_list() {
_filter_port_list_ordered "$1" "$2"
}
filter_port_list_reverse() {
_filter_port_list_ordered "$1" "$2" "-r"
}
board=$(board_name)
board_config_update
lan_list=$(ls -1 -v -d /sys/class/net/lan* | xargs -n1 basename | xargs)
lan_list_rev=$(ls -1 -v -d -r /sys/class/net/lan* | xargs -n1 basename | xargs)
ucidef_set_bridge_device switch
ucidef_set_interface_lan "$lan_list"
@ -70,35 +71,35 @@ done
case $board in
d-link,dgs-1210-10mp-f)
ucidef_set_poe 130 "$lan_list" "lan9 lan10"
ucidef_set_poe 130 "$(filter_port_list "$lan_list" "lan9 lan10")"
;;
d-link,dgs-1210-10p)
ucidef_set_poe 65 "$lan_list" "lan9 lan10"
ucidef_set_poe 65 "$(filter_port_list "$lan_list" "lan9 lan10")"
;;
d-link,dgs-1210-28mp-f)
ucidef_set_poe 370 "lan8 lan7 lan6 lan5 lan4 lan3 lan2 lan1 lan16 lan15 lan14 lan13 lan12 lan11 lan10 lan9 lan24 lan23
lan22 lan21 lan20 lan19 lan18 lan17" "lan25 lan26 lan27 lan28"
lan22 lan21 lan20 lan19 lan18 lan17"
;;
engenius,ews2910p)
ucidef_set_poe 60 "$lan_list" "lan9 lan10"
ucidef_set_poe 60 "$(filter_port_list "$lan_list" "lan9 lan10")"
;;
hpe,1920-8g-poe-65w)
ucidef_set_poe 65 "$lan_list_rev" "lan9 lan10"
ucidef_set_poe 65 "$(filter_port_list_reversed "$lan_list" "lan9 lan10")"
;;
hpe,1920-8g-poe-180w)
ucidef_set_poe 180 "$lan_list_rev" "lan9 lan10"
ucidef_set_poe 180 "$(filter_port_list_reversed "$lan_list" "lan9 lan10")"
;;
netgear,gs110tpp-v1)
ucidef_set_poe 130 "$lan_list" "lan9 lan10"
ucidef_set_poe 130 "$(filter_port_list "$lan_list" "lan9 lan10")"
;;
netgear,gs110tup-v1)
ucidef_set_poe 240 "$lan_list" "lan9 lan10"
ucidef_set_poe 240 "$(filter_port_list "$lan_list" "lan9 lan10")"
;;
netgear,gs310tp-v1)
ucidef_set_poe 55 "$lan_list" "lan9 lan10"
ucidef_set_poe 55 "$(filter_port_list "$lan_list" "lan9 lan10")"
;;
zyxel,gs1900-10hp)
ucidef_set_poe 77 "$lan_list" "lan9 lan10"
ucidef_set_poe 77 "$(filter_port_list "$lan_list" "lan9 lan10")"
;;
zyxel,gs1900-8hp-v1|\
zyxel,gs1900-8hp-v2)
@ -106,7 +107,7 @@ zyxel,gs1900-8hp-v2)
;;
zyxel,gs1900-24hp-v1|\
zyxel,gs1900-24hp-v2)
ucidef_set_poe 170 "$lan_list" "lan25 lan26"
ucidef_set_poe 170 "$(filter_port_list "$lan_list" "lan25 lan26")"
;;
esac

105
target/linux/realtek/dts-5.15/rtl9302_zyxel_xgs1250-12.dts
View File

@ -6,6 +6,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "zyxel,xgs1250-12", "realtek,rtl838x-soc";
@ -70,6 +71,107 @@
// (5G, 10/100) (10G, 5G, 2.5G)
led_set2 = <0x0a20 0x0a01>; // LED set 2: 1000MBit, 10GBit
};
thermal-zones {
phy24-thermal {
/* Poll every 10 seconds */
polling-delay-passive = <10000>;
polling-delay = <10000>;
thermal-sensors = <&phy24>;
trips {
phy24_trip0: phy24-trip0 {
/* At 80 degrees turn on fan */
temperature = <80000>;
hysteresis = <1000>;
type = "active";
};
phy24_trip1: phy24-trip1 {
/* At 108 degrees phys exceed spec */
temperature = <108000>;
hysteresis = <5000>;
type = "critical";
};
};
cooling-maps {
map {
trip = <&phy24_trip0>;
cooling-device = <&chassis_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
phy25-thermal {
/* Poll every 10 seconds */
polling-delay-passive = <10000>;
polling-delay = <10000>;
thermal-sensors = <&phy25>;
trips {
phy25_trip0: phy25-trip0 {
/* At 80 degrees turn on fan */
temperature = <80000>;
hysteresis = <1000>;
type = "active";
};
phy25_trip1: phy25-trip1 {
/* At 108 degrees phys exceed spec */
temperature = <108000>;
hysteresis = <5000>;
type = "critical";
};
};
cooling-maps {
map {
trip = <&phy25_trip0>;
cooling-device = <&chassis_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
phy26-thermal {
/* Poll every 10 seconds */
polling-delay-passive = <10000>;
polling-delay = <10000>;
thermal-sensors = <&phy26>;
trips {
phy26_trip0: phy26-trip0 {
/* At 80 degrees turn on fan */
temperature = <80000>;
hysteresis = <1000>;
type = "active";
};
phy26_trip1: phy26-trip1 {
/* At 108 degrees phys exceed spec */
temperature = <108000>;
hysteresis = <5000>;
type = "critical";
};
};
cooling-maps {
map {
trip = <&phy26_trip0>;
cooling-device = <&chassis_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
/* YEN SUN TECHNOLOGY FD122510LL-N fan */
chassis_fan: gpio-fan {
compatible = "gpio-fan";
gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = <0 0
7000 1>;
#cooling-cells = <2>;
};
};
&spi0 {
@ -180,6 +282,7 @@
sds = < 6 >;
// Disabled because we do not know how to bring up again
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
#thermal-sensor-cells = <0>;
};
phy25: ethernet-phy@25 {
@ -189,6 +292,7 @@
sds = < 7 >;
// Disabled because we do not know how to bring up again
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
#thermal-sensor-cells = <0>;
};
phy26: ethernet-phy@26 {
@ -198,6 +302,7 @@
sds = < 8 >;
// Disabled because we do not know how to bring up again
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
#thermal-sensor-cells = <0>;
};
/* SFP Ports */

1
target/linux/realtek/image/rtl930x.mk
View File

@ -6,6 +6,7 @@ define Device/zyxel_xgs1250-12
ZYXEL_VERS := ABWE
DEVICE_VENDOR := Zyxel
DEVICE_MODEL := XGS1250-12
DEVICE_PACKAGES := kmod-hwmon-gpiofan kmod-thermal
IMAGE_SIZE := 13312k
KERNEL_INITRAMFS := \
kernel-bin | \

2
target/linux/sunxi/patches-6.1/119-arm64-dts-allwinner-h616-Add-CPU-Operating-Performance-Po.patch
View File

@ -119,7 +119,7 @@ Signed-off-by: Martin Botka <martin.botka@somainline.org>
+
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1100000 1100000 1100000>;
+ opp-microvolt = <1100000 1100000 1200000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };