From 15acde674c76504e023a525506a2e248e9aecd24 Mon Sep 17 00:00:00 2001 From: Stijn Tintel Date: Fri, 28 Jul 2023 22:40:34 +0300 Subject: [PATCH 1/9] xdp-tools: disable stack protector for BPF programs When building xdp-tools with CONFIG_USE_LLVM_HOST=y, on a host that enabled stack protector by default in Clang, compilation fails with the following error: CLANG xdp-dispatcher.o clang-16: error: ignoring '-fstack-protector-strong' option as it is not currently supported for target 'bpfeb' [-Werror,-Woption-ignored] Add -fno-stack-protector to BPF_CFLAGS to fix this. Signed-off-by: Stijn Tintel --- package/network/utils/xdp-tools/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/network/utils/xdp-tools/Makefile b/package/network/utils/xdp-tools/Makefile index 3cc7980cf6..dba775e4ea 100644 --- a/package/network/utils/xdp-tools/Makefile +++ b/package/network/utils/xdp-tools/Makefile @@ -94,7 +94,7 @@ MAKE_VARS += \ define Build/Configure $(call Build/Configure/Default) - echo "BPF_CFLAGS += -I$(BPF_HEADERS_DIR)/tools/lib" >> $(PKG_BUILD_DIR)/config.mk + echo "BPF_CFLAGS += -I$(BPF_HEADERS_DIR)/tools/lib -fno-stack-protector" >> $(PKG_BUILD_DIR)/config.mk endef define Build/InstallDev From 2a5c7bf6213cc12d4ae6b7bce5d777b3518a89c1 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 1 Aug 2023 18:04:24 +0100 Subject: [PATCH 2/9] kernel: netdevices: add driver for Marvell 10G Ethernet PHYs Package kernel module for Marvell 10G Ethernet PHYs found also in many 10G/1G/100M/10M RJ-45 SFP+ modules. Signed-off-by: Daniel Golle --- package/kernel/linux/modules/netdevices.mk | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk index 33e7f1bc30..ec6741712e 100644 --- a/package/kernel/linux/modules/netdevices.mk +++ b/package/kernel/linux/modules/netdevices.mk @@ -308,6 +308,24 @@ endef $(eval $(call KernelPackage,phy-marvell)) +define KernelPackage/phy-marvell-10g + SUBMENU:=$(NETWORK_DEVICES_MENU) + TITLE:=Marvell 10 Gigabit Ethernet PHY driver + KCONFIG:=CONFIG_MARVELL_10G_PHY + DEPENDS:=+kmod-libphy + FILES:=$(LINUX_DIR)/drivers/net/phy/marvell10g.ko + AUTOLOAD:=$(call AutoLoad,18,marvell10g) +endef + +define KernelPackage/phy-marvell/description + Supports Marvell 10 Gigabit Ethernet PHYs: + * 88E2110 + * 88E2111 + * 88x3310 + * 88x3340 +endef + +$(eval $(call KernelPackage,phy-marvell-10g)) define KernelPackage/phy-realtek SUBMENU:=$(NETWORK_DEVICES_MENU) From 36d0aa9c2db0f74614b04a152fb092bcc74afb8e Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 1 Aug 2023 00:04:56 +0100 Subject: [PATCH 3/9] mediatek: filogic: sync pinctrl-mt7988 with MediaTek SDK Update pinctrl driver for the MT7988 with driver from mtk-openwrt-feeds. Signed-off-by: Daniel Golle --- .../drivers/pinctrl/mediatek/pinctrl-mt7988.c | 415 +++++++++++++----- .../drivers/pinctrl/mediatek/pinctrl-mt7988.c | 382 +++++++++++----- 2 files changed, 583 insertions(+), 214 deletions(-) diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c index 80a7e19f7a..49c0be1bba 100644 --- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -46,37 +46,53 @@ static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { }; static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x30, 0x10, 13, 1), - PIN_FIELD_BASE(2, 3, 5, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1), PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), - PIN_FIELD_BASE(13, 14, 1, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(15, 16, 5, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(17, 18, 5, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1), + + PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0x50, 0x10, 21, 1), + PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1), PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0x50, 0x10, 25, 1), + PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1), PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0x50, 0x10, 29, 1), + PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1), PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1), PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), @@ -86,17 +102,31 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1), PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0x40, 0x10, 14, 1), + + PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1), PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), - PIN_FIELD_BASE(58, 60, 1, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1), PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), - PIN_FIELD_BASE(64, 68, 1, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(69, 70, 5, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(71, 72, 5, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1), + + PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), @@ -104,42 +134,61 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), - PIN_FIELD_BASE(80, 81, 1, 0x40, 0x10, 18, 1), - PIN_FIELD_BASE(82, 83, 1, 0x40, 0x10, 16, 1), + + PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1), + PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1), + PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1), + PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1), }; static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0xc0, 0x10, 13, 1), - PIN_FIELD_BASE(2, 3, 5, 0xc0, 0x10, 11, 1), + PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1), + PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1), + PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1), PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0xc0, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1), + PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1), + PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), - PIN_FIELD_BASE(13, 14, 1, 0xe0, 0x10, 1, 1), - PIN_FIELD_BASE(15, 16, 5, 0xc0, 0x10, 7, 1), - PIN_FIELD_BASE(17, 18, 5, 0xc0, 0x10, 3, 1), + PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1), + PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1), + + PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1), + PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1), + PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0x140, 0x10, 21, 1), + PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1), PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0x140, 0x10, 25, 1), + PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1), PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0x140, 0x10, 29, 1), + PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1), PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0x140, 0x10, 0, 1), + PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1), PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), @@ -149,17 +198,31 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0x140, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1), PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0xe0, 0x10, 14, 1), + + PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1), + PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1), PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), - PIN_FIELD_BASE(58, 60, 1, 0xe0, 0x10, 4, 1), + PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1), + PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1), + PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1), PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), - PIN_FIELD_BASE(64, 68, 1, 0xe0, 0x10, 8, 1), - PIN_FIELD_BASE(69, 70, 5, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(71, 72, 5, 0xc0, 0x10, 5, 1), + PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1), + PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1), + PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1), + PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1), + PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1), + + PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1), + PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1), + PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1), + PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), @@ -167,8 +230,11 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), - PIN_FIELD_BASE(80, 81, 1, 0xe0, 0x10, 18, 1), - PIN_FIELD_BASE(82, 83, 1, 0xe0, 0x10, 16, 1), + + PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1), + PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1), + PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1), + PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1), }; static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { @@ -176,8 +242,11 @@ static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(13, 14, 1, 0x70, 0x10, 0, 1), + + PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1), PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), @@ -190,11 +259,19 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(13, 14, 1, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(15, 16, 5, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(17, 18, 5, 0x40, 0x10, 0, 1), + + PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1), + + PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(71, 72, 5, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), @@ -203,26 +280,37 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { }; static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(2, 3, 5, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3), PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(5, 6, 5, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(13, 14, 1, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(25, 26, 3, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3), PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(28, 30, 3, 0x20, 0x10, 15, 3), + PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3), + PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3), + PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3), PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), @@ -232,7 +320,8 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(40, 41, 3, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3), PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), @@ -242,17 +331,29 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(51, 53, 3, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3), PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), - PIN_FIELD_BASE(55, 56, 1, 0x10, 0x10, 12, 3), + + PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3), PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(58, 60, 1, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3), PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(64, 65, 1, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(66, 68, 1, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(69, 70, 5, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3), + + PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), @@ -260,35 +361,49 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(80, 81, 1, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(82, 83, 1, 0x10, 0x10, 18, 3), + + PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3), + PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3), + PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3), }; static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(2, 3, 5, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1), PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), + PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1), PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0x70, 0x10, 25, 1), + PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1), PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0x70, 0x10, 29, 1), + PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1), PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1), PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), @@ -298,46 +413,73 @@ static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1), PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0x60, 0x10, 12, 1), + + PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1), + PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1), PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), - PIN_FIELD_BASE(58, 60, 1, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1), PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(64, 68, 1, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(69, 70, 5, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1), + PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1), + PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1), + + PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(80, 81, 1, 0x60, 0x10, 16, 1), - PIN_FIELD_BASE(82, 83, 1, 0x60, 0x10, 14, 1), + + PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1), + PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1), + PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1), + PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1), }; static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(2, 3, 5, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1), + PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1), PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), + PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0x90, 0x10, 21, 1), + PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1), PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0x90, 0x10, 25, 1), + PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1), PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0x90, 0x10, 29, 1), + PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1), PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1), PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), @@ -347,46 +489,73 @@ static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0x90, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1), PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0x80, 0x10, 12, 1), + + PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1), + PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1), PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), - PIN_FIELD_BASE(58, 60, 1, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1), PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), - PIN_FIELD_BASE(64, 68, 1, 0x80, 0x10, 6, 1), - PIN_FIELD_BASE(69, 70, 5, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1), + PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1), + PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1), + PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1), + PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1), + + PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(80, 81, 1, 0x80, 0x10, 16, 1), - PIN_FIELD_BASE(82, 83, 1, 0x80, 0x10, 14, 1), + + PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1), + PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1), + PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1), + PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1), }; static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(2, 3, 5, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1), + PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1), PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), + PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0xb0, 0x10, 21, 1), + PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1), PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0xb0, 0x10, 25, 1), + PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1), PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0xb0, 0x10, 29, 1), + PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1), PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0xb0, 0x10, 0, 1), + PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1), PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), @@ -396,19 +565,35 @@ static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0xb0, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1), PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0x90, 0x10, 12, 1), + + PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1), + PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1), PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), - PIN_FIELD_BASE(58, 60, 1, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1), PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(64, 68, 1, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(69, 70, 5, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1), + + PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(80, 81, 1, 0x90, 0x10, 16, 1), - PIN_FIELD_BASE(82, 83, 1, 0x90, 0x10, 14, 1), + + PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1), + PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1), + PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1), + PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1), }; static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { @@ -1096,20 +1281,20 @@ static const struct group_desc mt7988_groups[] = { /* Joint those groups owning the same capability in user point of view which * allows that people tend to use through the device tree. */ -static const char *mt7988_jtag_groups[] = { +static const char * const mt7988_jtag_groups[] = { "tops_jtag0_0", "wo0_jtag", "wo1_jtag", "wo2_jtag", "jtag", "tops_jtag0_1", }; -static const char *mt7988_int_usxgmii_groups[] = { +static const char * const mt7988_int_usxgmii_groups[] = { "int_usxgmii", }; -static const char *mt7988_pwm_groups[] = { +static const char * const mt7988_pwm_groups[] = { "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7" }; -static const char *mt7988_dfd_groups[] = { +static const char * const mt7988_dfd_groups[] = { "dfd", }; -static const char *mt7988_i2c_groups[] = { +static const char * const mt7988_i2c_groups[] = { "xfi_phy0_i2c0", "xfi_phy1_i2c0", "xfi_phy_pll_i2c0", @@ -1134,13 +1319,13 @@ static const char *mt7988_i2c_groups[] = { "i2c2_0", "i2c2_1", }; -static const char *mt7988_ethernet_groups[] = { +static const char * const mt7988_ethernet_groups[] = { "mdc_mdio0", "2p5g_ext_mdio", "gbe_ext_mdio", "mdc_mdio1", }; -static const char *mt7988_pcie_groups[] = { +static const char * const mt7988_pcie_groups[] = { "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", @@ -1150,18 +1335,18 @@ static const char *mt7988_pcie_groups[] = { "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", "pcie_clk_req_n0_1" }; -static const char *mt7988_pmic_groups[] = { +static const char * const mt7988_pmic_groups[] = { "pmic", }; -static const char *mt7988_wdt_groups[] = { +static const char * const mt7988_wdt_groups[] = { "watchdog", }; -static const char *mt7988_spi_groups[] = { +static const char * const mt7988_spi_groups[] = { "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", }; -static const char *mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", +static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", "emmc_51" }; -static const char *mt7988_uart_groups[] = { +static const char * const mt7988_uart_groups[] = { "uart2", "tops_uart0_0", "uart2_0", @@ -1183,18 +1368,18 @@ static const char *mt7988_uart_groups[] = { "net_wo1_uart_txd_1", "net_wo2_uart_txd_1", }; -static const char *mt7988_udi_groups[] = { +static const char * const mt7988_udi_groups[] = { "udi", }; -static const char *mt7988_audio_groups[] = { +static const char * const mt7988_audio_groups[] = { "i2s", "pcm", }; -static const char *mt7988_led_groups[] = { +static const char * const mt7988_led_groups[] = { "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", "wf5g_led0", "wf5g_led1", }; -static const char *mt7988_usb_groups[] = { +static const char * const mt7988_usb_groups[] = { "drv_vbus", "drv_vbus_p1", }; @@ -1226,7 +1411,7 @@ static const struct mtk_eint_hw mt7988_eint_hw = { .db_cnt = 16, }; -static const char *mt7988_pinctrl_register_base_names[] = { +static const char * const mt7988_pinctrl_register_base_names[] = { "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", }; diff --git a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c index da0269ed7a..49c0be1bba 100644 --- a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -46,37 +46,53 @@ static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { }; static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x30, 0x10, 13, 1), - PIN_FIELD_BASE(2, 3, 5, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1), PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), - PIN_FIELD_BASE(13, 14, 1, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(15, 16, 5, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(17, 18, 5, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1), + + PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0x50, 0x10, 21, 1), + PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1), PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0x50, 0x10, 25, 1), + PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1), PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0x50, 0x10, 29, 1), + PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1), PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1), PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), @@ -86,17 +102,31 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1), PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0x40, 0x10, 14, 1), + + PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1), PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), - PIN_FIELD_BASE(58, 60, 1, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1), PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), - PIN_FIELD_BASE(64, 68, 1, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(69, 70, 5, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(71, 72, 5, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1), + + PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), @@ -104,42 +134,61 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), - PIN_FIELD_BASE(80, 81, 1, 0x40, 0x10, 18, 1), - PIN_FIELD_BASE(82, 83, 1, 0x40, 0x10, 16, 1), + + PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1), + PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1), + PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1), + PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1), }; static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0xc0, 0x10, 13, 1), - PIN_FIELD_BASE(2, 3, 5, 0xc0, 0x10, 11, 1), + PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1), + PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1), + PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1), PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0xc0, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1), + PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1), + PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), - PIN_FIELD_BASE(13, 14, 1, 0xe0, 0x10, 1, 1), - PIN_FIELD_BASE(15, 16, 5, 0xc0, 0x10, 7, 1), - PIN_FIELD_BASE(17, 18, 5, 0xc0, 0x10, 3, 1), + PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1), + PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1), + + PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1), + PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1), + PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0x140, 0x10, 21, 1), + PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1), PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0x140, 0x10, 25, 1), + PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1), PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0x140, 0x10, 29, 1), + PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1), PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0x140, 0x10, 0, 1), + PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1), PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), @@ -149,17 +198,31 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0x140, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1), PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0xe0, 0x10, 14, 1), + + PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1), + PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1), PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), - PIN_FIELD_BASE(58, 60, 1, 0xe0, 0x10, 4, 1), + PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1), + PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1), + PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1), PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), - PIN_FIELD_BASE(64, 68, 1, 0xe0, 0x10, 8, 1), - PIN_FIELD_BASE(69, 70, 5, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(71, 72, 5, 0xc0, 0x10, 5, 1), + PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1), + PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1), + PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1), + PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1), + PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1), + + PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1), + PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1), + PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1), + PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), @@ -167,8 +230,11 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), - PIN_FIELD_BASE(80, 81, 1, 0xe0, 0x10, 18, 1), - PIN_FIELD_BASE(82, 83, 1, 0xe0, 0x10, 16, 1), + + PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1), + PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1), + PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1), + PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1), }; static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { @@ -176,8 +242,11 @@ static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(13, 14, 1, 0x70, 0x10, 0, 1), + + PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1), PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), @@ -190,11 +259,19 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(13, 14, 1, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(15, 16, 5, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(17, 18, 5, 0x40, 0x10, 0, 1), + + PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1), + + PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(71, 72, 5, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), @@ -203,26 +280,37 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { }; static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(2, 3, 5, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3), PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(5, 6, 5, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(13, 14, 1, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(25, 26, 3, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3), PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(28, 30, 3, 0x20, 0x10, 15, 3), + PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3), + PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3), + PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3), PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), @@ -232,7 +320,8 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(40, 41, 3, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3), PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), @@ -242,17 +331,29 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(51, 53, 3, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3), PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), - PIN_FIELD_BASE(55, 56, 1, 0x10, 0x10, 12, 3), + + PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3), PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(58, 60, 1, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3), PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(64, 65, 1, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(66, 68, 1, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(69, 70, 5, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3), + + PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), @@ -260,35 +361,49 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(80, 81, 1, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(82, 83, 1, 0x10, 0x10, 18, 3), + + PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3), + PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3), + PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3), }; static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(2, 3, 5, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1), PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), + PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1), PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0x70, 0x10, 25, 1), + PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1), PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0x70, 0x10, 29, 1), + PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1), PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1), PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), @@ -298,46 +413,73 @@ static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1), PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0x60, 0x10, 12, 1), + + PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1), + PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1), PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), - PIN_FIELD_BASE(58, 60, 1, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1), PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(64, 68, 1, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(69, 70, 5, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1), + PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1), + PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1), + + PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(80, 81, 1, 0x60, 0x10, 16, 1), - PIN_FIELD_BASE(82, 83, 1, 0x60, 0x10, 14, 1), + + PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1), + PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1), + PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1), + PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1), }; static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(2, 3, 5, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1), + PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1), PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), + PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0x90, 0x10, 21, 1), + PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1), PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0x90, 0x10, 25, 1), + PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1), PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0x90, 0x10, 29, 1), + PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1), PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1), PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), @@ -347,46 +489,73 @@ static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0x90, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1), PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0x80, 0x10, 12, 1), + + PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1), + PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1), PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), - PIN_FIELD_BASE(58, 60, 1, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1), PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), - PIN_FIELD_BASE(64, 68, 1, 0x80, 0x10, 6, 1), - PIN_FIELD_BASE(69, 70, 5, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1), + PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1), + PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1), + PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1), + PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1), + + PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(80, 81, 1, 0x80, 0x10, 16, 1), - PIN_FIELD_BASE(82, 83, 1, 0x80, 0x10, 14, 1), + + PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1), + PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1), + PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1), + PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1), }; static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(2, 3, 5, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1), + PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1), PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), + PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0xb0, 0x10, 21, 1), + PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1), PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0xb0, 0x10, 25, 1), + PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1), PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0xb0, 0x10, 29, 1), + PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1), PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0xb0, 0x10, 0, 1), + PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1), PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), @@ -396,19 +565,35 @@ static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0xb0, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1), PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0x90, 0x10, 12, 1), + + PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1), + PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1), PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), - PIN_FIELD_BASE(58, 60, 1, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1), PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(64, 68, 1, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(69, 70, 5, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1), + + PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(80, 81, 1, 0x90, 0x10, 16, 1), - PIN_FIELD_BASE(82, 83, 1, 0x90, 0x10, 14, 1), + + PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1), + PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1), + PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1), + PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1), }; static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { @@ -1279,4 +1464,3 @@ static int __init mt7988_pinctrl_init(void) return platform_driver_register(&mt7988_pinctrl_driver); } arch_initcall(mt7988_pinctrl_init); - From 64b99802a61a477ed23fc1f3426fb19d1bc0c6f3 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 1 Aug 2023 00:08:56 +0100 Subject: [PATCH 4/9] mediatek: filogic: update MT7988 device tree * move ethernet to mt7988a.dtsi * move switch definition to mt7988a.dtsi * add PHY LEDs Signed-off-by: Daniel Golle --- .../mediatek/mt7988a-dsa-10g-spim-nand.dts | 245 +++++-------- .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 321 +++++++++++++++++- .../mediatek/mt7988a-dsa-10g-spim-nand.dts | 245 +++++-------- .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 321 +++++++++++++++++- 4 files changed, 794 insertions(+), 338 deletions(-) diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts index e204dc4f16..27ef19c46d 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "mt7988a-rfb-spim-nand.dtsi" #include +#include / { model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; @@ -29,173 +30,105 @@ pinctrl-0 = <&mdio0_pins>; pinctrl-names = "default"; status = "okay"; +}; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; +&gmac0 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + phy-mode = "internal"; + phy-connection-type = "internal"; + phy = <&int_2p5g_phy>; +}; + +&gmac2 { + status = "okay"; + phy-mode = "usxgmii"; + phy-connection-type = "usxgmii"; + phy = <&phy8>; +}; + +&mdio_bus { + /* external Aquantia AQR113C */ + phy0: ethernet-phy@0 { reg = <0>; - phy-mode = "internal"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 72 1>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; }; - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "internal"; - phy-connection-type = "internal"; - phy = <&phy15>; + /* external Aquantia AQR113C */ + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 71 1>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; }; - gmac2: mac@2 { - compatible = "mediatek,eth-mac"; - reg = <2>; - phy-mode = "10gbase-kr"; - phy-connection-type = "10gbase-kr"; - phy = <&phy8>; + /* external Maxlinear GPY211C */ + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; }; - mdio0: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 72 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Aquantia AQR113C */ - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 71 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Maxlinear GPY211C */ - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - - /* external Maxlinear GPY211C */ - phy13: ethernet-phy@13 { - reg = <13>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - - /* internal 2.5G PHY */ - phy15: ethernet-phy@15 { - reg = <15>; - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "internal"; - }; + /* external Maxlinear GPY211C */ + phy13: ethernet-phy@13 { + reg = <13>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; }; }; +&int_2p5g_phy { + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; +}; + &switch { status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - phy-mode = "internal"; - phy-handle = <&gsw_phy0>; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-mode = "internal"; - phy-handle = <&gsw_phy1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-mode = "internal"; - phy-handle = <&gsw_phy2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; - phy-mode = "internal"; - phy-handle = <&gsw_phy3>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "internal"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - mediatek,pio = <&pio>; - - gsw_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <0>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; - nvmem-cells = <&phy_calibration_p0>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <1>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; - nvmem-cells = <&phy_calibration_p1>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <2>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; - nvmem-cells = <&phy_calibration_p2>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy3: ethernet-phy@3 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <3>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; - nvmem-cells = <&phy_calibration_p3>; - nvmem-cell-names = "phy-cal-data"; - }; - }; +}; + +&gsw_phy0 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe0_led0_pins>; +}; + +&gsw_phy0_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy1 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe1_led0_pins>; +}; + +&gsw_phy1_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy2 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe2_led0_pins>; +}; + +&gsw_phy2_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy3 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe3_led0_pins>; +}; + +&gsw_phy3_led0 { + status = "okay"; + color = ; }; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 94aa8251bd..462218c65d 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -4,12 +4,13 @@ * Author: Sam.Shih */ -#include -#include -#include -#include #include +#include +#include +#include +#include #include +#include #include / { @@ -144,9 +145,9 @@ #size-cells = <2>; ranges; - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; + reg = <0 0x43000000 0 0x50000>; no-map; }; }; @@ -228,7 +229,7 @@ "iocfg_lb_base", "iocfg_tl_base", "eint"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 83>; + gpio-ranges = <&pio 0 0 84>; interrupt-controller; interrupts = ; interrupt-parent = <&gic>; @@ -260,47 +261,131 @@ }; }; - i2c2_pins: i2c2-pins-g0 { + i2c1_sfp_pins: i2c1-sfp-pins-g0 { + mux { + function = "i2c"; + groups = "i2c1_sfp"; + }; + }; + + i2c2_pins: i2c2-pins { + mux { + function = "i2c"; + groups = "i2c2"; + }; + }; + + i2c2_0_pins: i2c2-pins-g0 { + mux { + function = "i2c"; + groups = "i2c2_0"; + }; + }; + + i2c2_1_pins: i2c2-pins-g1 { mux { function = "i2c"; groups = "i2c2_1"; }; }; - gbe0_led0_pins: gbe0-pins { + gbe0_led0_pins: gbe0-led0-pins { mux { function = "led"; groups = "gbe0_led0"; }; }; - gbe1_led0_pins: gbe1-pins { + gbe1_led0_pins: gbe1-led0-pins { mux { function = "led"; groups = "gbe1_led0"; }; }; - gbe2_led0_pins: gbe2-pins { + gbe2_led0_pins: gbe2-led0-pins { mux { function = "led"; groups = "gbe2_led0"; }; }; - gbe3_led0_pins: gbe3-pins { + gbe3_led0_pins: gbe3-led0-pins { mux { function = "led"; groups = "gbe3_led0"; }; }; - i2p5gbe_led0_pins: 2p5gbe-pins { + gbe0_led1_pins: gbe0-led1-pins { + mux { + function = "led"; + groups = "gbe0_led1"; + }; + }; + + gbe1_led1_pins: gbe1-led1-pins { + mux { + function = "led"; + groups = "gbe1_led1"; + }; + }; + + gbe2_led1_pins: gbe2-led1-pins { + mux { + function = "led"; + groups = "gbe2_led1"; + }; + }; + + gbe3_led1_pins: gbe3-led1-pins { + mux { + function = "led"; + groups = "gbe3_led1"; + }; + }; + + i2p5gbe_led0_pins: 2p5gbe-led0-pins { mux { function = "led"; groups = "2p5gbe_led0"; }; }; + + i2p5gbe_led1_pins: 2p5gbe-led1-pins { + mux { + function = "led"; + groups = "2p5gbe_led1"; + }; + }; + + mmc0_pins_emmc_45: mmc0-pins-emmc-45 { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + + mmc0_pins_emmc_51: mmc0-pins-emmc-51 { + mux { + function = "flash"; + groups = "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-pins-sdcard { + mux { + function = "flash"; + groups = "sdcard"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; }; sgmiisys0: syscon@10060000 { @@ -380,6 +465,8 @@ <&infracfg CLK_INFRA_MUX_UART0_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, <&topckgen CLK_TOP_UART_SEL>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; status = "disabled"; }; @@ -645,6 +732,29 @@ status = "disabled"; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc", + "mediatek,mt7981-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11D60000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_MSDC400>, + <&infracfg CLK_INFRA_MSDC2_HCK>, + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, + <&topckgen CLK_TOP_EMMC_400M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, + <&apmixedsys CLK_APMIXED_MSDCPLL>; + clock-names = "source", + "hclk", + "axi_cg", + "ahb_cg"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + tphy: tphy@11c50000 { compatible = "mediatek,mt7988", "mediatek,generic-tphy-v2"; @@ -747,6 +857,157 @@ interrupt-parent = <&gic>; interrupts = ; resets = <ðrst 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-mode = "internal"; + phy-handle = <&gsw_phy0>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&gsw_phy1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&gsw_phy2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&gsw_phy3>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + mediatek,pio = <&pio>; + + gsw_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <0>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p0>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy0_led0: gsw-phy0-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy0_led1: gsw-phy0-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + + gsw_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <1>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p1>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy1_led0: gsw-phy1-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy1_led1: gsw-phy1-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + + gsw_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <2>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p2>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy2_led0: gsw-phy2-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy2_led1: gsw-phy2-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + + gsw_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <3>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p3>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy3_led0: gsw-phy3-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy3_led1: gsw-phy3-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + }; }; ethwarp: syscon@15031000 { @@ -843,6 +1104,40 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + }; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@15 { + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; + }; + }; }; }; }; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts index e204dc4f16..27ef19c46d 100644 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "mt7988a-rfb-spim-nand.dtsi" #include +#include / { model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; @@ -29,173 +30,105 @@ pinctrl-0 = <&mdio0_pins>; pinctrl-names = "default"; status = "okay"; +}; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; +&gmac0 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + phy-mode = "internal"; + phy-connection-type = "internal"; + phy = <&int_2p5g_phy>; +}; + +&gmac2 { + status = "okay"; + phy-mode = "usxgmii"; + phy-connection-type = "usxgmii"; + phy = <&phy8>; +}; + +&mdio_bus { + /* external Aquantia AQR113C */ + phy0: ethernet-phy@0 { reg = <0>; - phy-mode = "internal"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 72 1>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; }; - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "internal"; - phy-connection-type = "internal"; - phy = <&phy15>; + /* external Aquantia AQR113C */ + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 71 1>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; }; - gmac2: mac@2 { - compatible = "mediatek,eth-mac"; - reg = <2>; - phy-mode = "10gbase-kr"; - phy-connection-type = "10gbase-kr"; - phy = <&phy8>; + /* external Maxlinear GPY211C */ + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; }; - mdio0: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 72 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Aquantia AQR113C */ - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 71 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Maxlinear GPY211C */ - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - - /* external Maxlinear GPY211C */ - phy13: ethernet-phy@13 { - reg = <13>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - - /* internal 2.5G PHY */ - phy15: ethernet-phy@15 { - reg = <15>; - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "internal"; - }; + /* external Maxlinear GPY211C */ + phy13: ethernet-phy@13 { + reg = <13>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; }; }; +&int_2p5g_phy { + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; +}; + &switch { status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - phy-mode = "internal"; - phy-handle = <&gsw_phy0>; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-mode = "internal"; - phy-handle = <&gsw_phy1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-mode = "internal"; - phy-handle = <&gsw_phy2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; - phy-mode = "internal"; - phy-handle = <&gsw_phy3>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "internal"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - mediatek,pio = <&pio>; - - gsw_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <0>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; - nvmem-cells = <&phy_calibration_p0>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <1>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; - nvmem-cells = <&phy_calibration_p1>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <2>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; - nvmem-cells = <&phy_calibration_p2>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy3: ethernet-phy@3 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <3>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; - nvmem-cells = <&phy_calibration_p3>; - nvmem-cell-names = "phy-cal-data"; - }; - }; +}; + +&gsw_phy0 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe0_led0_pins>; +}; + +&gsw_phy0_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy1 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe1_led0_pins>; +}; + +&gsw_phy1_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy2 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe2_led0_pins>; +}; + +&gsw_phy2_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy3 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe3_led0_pins>; +}; + +&gsw_phy3_led0 { + status = "okay"; + color = ; }; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 94aa8251bd..462218c65d 100644 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -4,12 +4,13 @@ * Author: Sam.Shih */ -#include -#include -#include -#include #include +#include +#include +#include +#include #include +#include #include / { @@ -144,9 +145,9 @@ #size-cells = <2>; ranges; - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; + reg = <0 0x43000000 0 0x50000>; no-map; }; }; @@ -228,7 +229,7 @@ "iocfg_lb_base", "iocfg_tl_base", "eint"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 83>; + gpio-ranges = <&pio 0 0 84>; interrupt-controller; interrupts = ; interrupt-parent = <&gic>; @@ -260,47 +261,131 @@ }; }; - i2c2_pins: i2c2-pins-g0 { + i2c1_sfp_pins: i2c1-sfp-pins-g0 { + mux { + function = "i2c"; + groups = "i2c1_sfp"; + }; + }; + + i2c2_pins: i2c2-pins { + mux { + function = "i2c"; + groups = "i2c2"; + }; + }; + + i2c2_0_pins: i2c2-pins-g0 { + mux { + function = "i2c"; + groups = "i2c2_0"; + }; + }; + + i2c2_1_pins: i2c2-pins-g1 { mux { function = "i2c"; groups = "i2c2_1"; }; }; - gbe0_led0_pins: gbe0-pins { + gbe0_led0_pins: gbe0-led0-pins { mux { function = "led"; groups = "gbe0_led0"; }; }; - gbe1_led0_pins: gbe1-pins { + gbe1_led0_pins: gbe1-led0-pins { mux { function = "led"; groups = "gbe1_led0"; }; }; - gbe2_led0_pins: gbe2-pins { + gbe2_led0_pins: gbe2-led0-pins { mux { function = "led"; groups = "gbe2_led0"; }; }; - gbe3_led0_pins: gbe3-pins { + gbe3_led0_pins: gbe3-led0-pins { mux { function = "led"; groups = "gbe3_led0"; }; }; - i2p5gbe_led0_pins: 2p5gbe-pins { + gbe0_led1_pins: gbe0-led1-pins { + mux { + function = "led"; + groups = "gbe0_led1"; + }; + }; + + gbe1_led1_pins: gbe1-led1-pins { + mux { + function = "led"; + groups = "gbe1_led1"; + }; + }; + + gbe2_led1_pins: gbe2-led1-pins { + mux { + function = "led"; + groups = "gbe2_led1"; + }; + }; + + gbe3_led1_pins: gbe3-led1-pins { + mux { + function = "led"; + groups = "gbe3_led1"; + }; + }; + + i2p5gbe_led0_pins: 2p5gbe-led0-pins { mux { function = "led"; groups = "2p5gbe_led0"; }; }; + + i2p5gbe_led1_pins: 2p5gbe-led1-pins { + mux { + function = "led"; + groups = "2p5gbe_led1"; + }; + }; + + mmc0_pins_emmc_45: mmc0-pins-emmc-45 { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + + mmc0_pins_emmc_51: mmc0-pins-emmc-51 { + mux { + function = "flash"; + groups = "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-pins-sdcard { + mux { + function = "flash"; + groups = "sdcard"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; }; sgmiisys0: syscon@10060000 { @@ -380,6 +465,8 @@ <&infracfg CLK_INFRA_MUX_UART0_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, <&topckgen CLK_TOP_UART_SEL>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; status = "disabled"; }; @@ -645,6 +732,29 @@ status = "disabled"; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc", + "mediatek,mt7981-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11D60000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_MSDC400>, + <&infracfg CLK_INFRA_MSDC2_HCK>, + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, + <&topckgen CLK_TOP_EMMC_400M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, + <&apmixedsys CLK_APMIXED_MSDCPLL>; + clock-names = "source", + "hclk", + "axi_cg", + "ahb_cg"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + tphy: tphy@11c50000 { compatible = "mediatek,mt7988", "mediatek,generic-tphy-v2"; @@ -747,6 +857,157 @@ interrupt-parent = <&gic>; interrupts = ; resets = <ðrst 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-mode = "internal"; + phy-handle = <&gsw_phy0>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&gsw_phy1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&gsw_phy2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&gsw_phy3>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + mediatek,pio = <&pio>; + + gsw_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <0>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p0>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy0_led0: gsw-phy0-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy0_led1: gsw-phy0-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + + gsw_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <1>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p1>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy1_led0: gsw-phy1-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy1_led1: gsw-phy1-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + + gsw_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <2>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p2>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy2_led0: gsw-phy2-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy2_led1: gsw-phy2-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + + gsw_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <3>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p3>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy3_led0: gsw-phy3-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy3_led1: gsw-phy3-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + }; }; ethwarp: syscon@15031000 { @@ -843,6 +1104,40 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + }; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@15 { + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; + }; + }; }; }; }; From b8be20c7e81de2894df8fa2b361c39bc723e4cb5 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Thu, 3 Aug 2023 18:47:15 +0200 Subject: [PATCH 5/9] hostapd: fix unused device removal on DBDC devices Check the phy before removing unrelated netdevs on the same hw device Reported-by: Hartmut Birr Signed-off-by: Felix Fietkau --- package/network/services/hostapd/files/wdev.uc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/package/network/services/hostapd/files/wdev.uc b/package/network/services/hostapd/files/wdev.uc index 9701af125a..896f5261fb 100644 --- a/package/network/services/hostapd/files/wdev.uc +++ b/package/network/services/hostapd/files/wdev.uc @@ -1,7 +1,7 @@ #!/usr/bin/env ucode 'use strict'; import { vlist_new, is_equal, wdev_create, wdev_remove } from "/usr/share/hostap/common.uc"; -import { readfile, writefile, basename, glob } from "fs"; +import { readfile, writefile, basename, readlink, glob } from "fs"; let keep_devices = {}; let phy = shift(ARGV); @@ -106,6 +106,9 @@ function add_existing(phy, config) if (config[wdev]) continue; + if (basename(readlink(`/sys/class/net/${wdev}/phy80211`)) != phy) + continue; + if (trim(readfile(`/sys/class/net/${wdev}/operstate`)) == "down") config[wdev] = {}; } From 1eb67cb0704a61f49d9be9f88aecbce1d881f8c9 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Thu, 3 Aug 2023 23:30:25 +0100 Subject: [PATCH 6/9] mediatek: filogic: restore non-const type in pinctrl-mt7988 driver When building with Linux 5.15 the 'const' type results in warnings. Restore the original non-const type in those cases. Fixes: 36d0aa9c2d ("mediatek: filogic: sync pinctrl-mt7988 with MediaTek SDK") Signed-off-by: Daniel Golle --- .../drivers/pinctrl/mediatek/pinctrl-mt7988.c | 34 +++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c index 49c0be1bba..659c83e997 100644 --- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -1281,20 +1281,20 @@ static const struct group_desc mt7988_groups[] = { /* Joint those groups owning the same capability in user point of view which * allows that people tend to use through the device tree. */ -static const char * const mt7988_jtag_groups[] = { +static const char *mt7988_jtag_groups[] = { "tops_jtag0_0", "wo0_jtag", "wo1_jtag", "wo2_jtag", "jtag", "tops_jtag0_1", }; -static const char * const mt7988_int_usxgmii_groups[] = { +static const char *mt7988_int_usxgmii_groups[] = { "int_usxgmii", }; -static const char * const mt7988_pwm_groups[] = { +static const char *mt7988_pwm_groups[] = { "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7" }; -static const char * const mt7988_dfd_groups[] = { +static const char *mt7988_dfd_groups[] = { "dfd", }; -static const char * const mt7988_i2c_groups[] = { +static const char *mt7988_i2c_groups[] = { "xfi_phy0_i2c0", "xfi_phy1_i2c0", "xfi_phy_pll_i2c0", @@ -1319,13 +1319,13 @@ static const char * const mt7988_i2c_groups[] = { "i2c2_0", "i2c2_1", }; -static const char * const mt7988_ethernet_groups[] = { +static const char *mt7988_ethernet_groups[] = { "mdc_mdio0", "2p5g_ext_mdio", "gbe_ext_mdio", "mdc_mdio1", }; -static const char * const mt7988_pcie_groups[] = { +static const char *mt7988_pcie_groups[] = { "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", @@ -1335,18 +1335,18 @@ static const char * const mt7988_pcie_groups[] = { "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", "pcie_clk_req_n0_1" }; -static const char * const mt7988_pmic_groups[] = { +static const char *mt7988_pmic_groups[] = { "pmic", }; -static const char * const mt7988_wdt_groups[] = { +static const char *mt7988_wdt_groups[] = { "watchdog", }; -static const char * const mt7988_spi_groups[] = { +static const char *mt7988_spi_groups[] = { "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", }; -static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", +static const char *mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", "emmc_51" }; -static const char * const mt7988_uart_groups[] = { +static const char *mt7988_uart_groups[] = { "uart2", "tops_uart0_0", "uart2_0", @@ -1368,18 +1368,18 @@ static const char * const mt7988_uart_groups[] = { "net_wo1_uart_txd_1", "net_wo2_uart_txd_1", }; -static const char * const mt7988_udi_groups[] = { +static const char *mt7988_udi_groups[] = { "udi", }; -static const char * const mt7988_audio_groups[] = { +static const char *mt7988_audio_groups[] = { "i2s", "pcm", }; -static const char * const mt7988_led_groups[] = { +static const char *mt7988_led_groups[] = { "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", "wf5g_led0", "wf5g_led1", }; -static const char * const mt7988_usb_groups[] = { +static const char *mt7988_usb_groups[] = { "drv_vbus", "drv_vbus_p1", }; @@ -1411,7 +1411,7 @@ static const struct mtk_eint_hw mt7988_eint_hw = { .db_cnt = 16, }; -static const char * const mt7988_pinctrl_register_base_names[] = { +static const char *mt7988_pinctrl_register_base_names[] = { "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", }; From f98dc5aa43e9d84b8ceef9414fd4f92e05c418d7 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 5 Aug 2023 01:55:11 +0200 Subject: [PATCH 7/9] CI: generilize S3 secret keys name and rename to proper name Generilize S3 secret keys and rename to make them not platform specific. Signed-off-by: Christian Marangi --- .github/workflows/kernel.yml | 4 ++-- .github/workflows/packages.yml | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/kernel.yml b/.github/workflows/kernel.yml index 87b8a14293..a96ece8709 100644 --- a/.github/workflows/kernel.yml +++ b/.github/workflows/kernel.yml @@ -35,6 +35,6 @@ jobs: packages: read actions: write secrets: - s3_access_key: ${{ secrets.GCS_S3_ACCESS_KEY }} - s3_secret_key: ${{ secrets.GCS_S3_SECRET_KEY }} + ccache_s3_access_key: ${{ secrets.CCACHE_S3_ACCESS_KEY }} + ccache_s3_secret_key: ${{ secrets.CCACHE_S3_SECRET_KEY }} uses: openwrt/actions-shared-workflows/.github/workflows/kernel.yml@main diff --git a/.github/workflows/packages.yml b/.github/workflows/packages.yml index 07621dcb4a..d9251ed2a0 100644 --- a/.github/workflows/packages.yml +++ b/.github/workflows/packages.yml @@ -35,6 +35,6 @@ jobs: packages: read actions: write secrets: - s3_access_key: ${{ secrets.GCS_S3_ACCESS_KEY }} - s3_secret_key: ${{ secrets.GCS_S3_SECRET_KEY }} + ccache_s3_access_key: ${{ secrets.CCACHE_S3_ACCESS_KEY }} + ccache_s3_secret_key: ${{ secrets.CCACHE_S3_SECRET_KEY }} uses: openwrt/actions-shared-workflows/.github/workflows/packages.yml@main From 881235c713fae8692190178561af4eb2dee4ead1 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 5 Aug 2023 01:58:29 +0200 Subject: [PATCH 8/9] CI: provide new required secret for S3 endpoint and bucket name Provide new required secret for S3 endpoint and bucket name to permit an easier migration to new services. Signed-off-by: Christian Marangi --- .github/workflows/kernel.yml | 2 ++ .github/workflows/packages.yml | 2 ++ 2 files changed, 4 insertions(+) diff --git a/.github/workflows/kernel.yml b/.github/workflows/kernel.yml index a96ece8709..43c610ab4f 100644 --- a/.github/workflows/kernel.yml +++ b/.github/workflows/kernel.yml @@ -35,6 +35,8 @@ jobs: packages: read actions: write secrets: + ccache_s3_endpoint: ${{ secrets.CCACHE_S3_ENDPOINT }} + ccache_s3_bucket: ${{ secrets.CCACHE_S3_BUCKET }} ccache_s3_access_key: ${{ secrets.CCACHE_S3_ACCESS_KEY }} ccache_s3_secret_key: ${{ secrets.CCACHE_S3_SECRET_KEY }} uses: openwrt/actions-shared-workflows/.github/workflows/kernel.yml@main diff --git a/.github/workflows/packages.yml b/.github/workflows/packages.yml index d9251ed2a0..f061c1cd37 100644 --- a/.github/workflows/packages.yml +++ b/.github/workflows/packages.yml @@ -35,6 +35,8 @@ jobs: packages: read actions: write secrets: + ccache_s3_endpoint: ${{ secrets.CCACHE_S3_ENDPOINT }} + ccache_s3_bucket: ${{ secrets.CCACHE_S3_BUCKET }} ccache_s3_access_key: ${{ secrets.CCACHE_S3_ACCESS_KEY }} ccache_s3_secret_key: ${{ secrets.CCACHE_S3_SECRET_KEY }} uses: openwrt/actions-shared-workflows/.github/workflows/packages.yml@main From 7e7eb5312d7810084547bb54a4b6867c2da08182 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Fri, 9 Jun 2023 13:39:52 +0200 Subject: [PATCH 9/9] mediatek: add support for Acer Predator W6 Hardware -------- SOC: MediaTek MT7986A RAM: 1GB DDR4 FLASH: 4GB eMMC WiFi: 2x2 2.4 GHz 802.11 b/g/n/ax MT7916 DBDC 4x4 5 GHz 802.11 a/n/ac/ax MT7986 2x2 6 GHz 802.11ax MT7916 DBDC ETH: 4x LAN 1Gbit/s (MT7531) 1x WAN 2.5Gbit/s (GPY211) BTN: RESET, WPS LED: Antenna LEDs (GPIO) Mood-LED (Kinetic KTD2601) - unsupported UART: Header nest to USB port - 3V3 115200 8N1 [BUTTON] GND - RX - TX [USB] Installation ------------ 1. Connect to the device using serial console. 2. Interrupt the Autoboot process when promted by sending '0' twice. 3. Serve the OpenWrt initramfs image using TFTP at 192.168.1.66. Name the image "predator.bin" and conenct the TFTP server to the routers LAN port. 4. Configure U-Boot to allow loading unsigned images from MMC $ setenv bootcmd 'mmc read 0x40000000 0x00004400 0x0010000; fdt addr $(fdtcontroladdr); fdt rm /signature; bootm 0x40000000'; saveenv 5. Transfer the image from U-Boot $ setenv serverip 192.168.1.66; setenv ipaddr 192.168.1.1; tftpboot 0x46000000 predator.bin; fdt addr $(fdtcontroladdr); fdt rm /signature; bootm 6. Wait for OpenWrt to boot 7. Transfer the OpenWrt sysupgrade image to the router using scp. 8. Install OpenWrt using sysupgrade. Signed-off-by: David Bauer --- .../mediatek/dts/mt7986a-acer-predator-w6.dts | 503 ++++++++++++++++++ .../filogic/base-files/etc/board.d/02_network | 3 + .../etc/hotplug.d/firmware/11-mt76-caldata | 14 + .../etc/hotplug.d/ieee80211/11_fix_wifi_mac | 6 + .../lib/preinit/05_extract_factory_data.sh | 25 + .../base-files/lib/preinit/10_fix_eth_mac.sh | 8 + .../base-files/lib/upgrade/platform.sh | 5 + target/linux/mediatek/image/filogic.mk | 15 + 8 files changed, 579 insertions(+) create mode 100644 target/linux/mediatek/dts/mt7986a-acer-predator-w6.dts create mode 100644 target/linux/mediatek/filogic/base-files/lib/preinit/05_extract_factory_data.sh diff --git a/target/linux/mediatek/dts/mt7986a-acer-predator-w6.dts b/target/linux/mediatek/dts/mt7986a-acer-predator-w6.dts new file mode 100644 index 0000000000..35a2c30bb4 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-acer-predator-w6.dts @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + model = "Acer Predator W6"; + compatible = "acer,predator-w6", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "dm-mod.create=\"dm-verity,,,ro,0 31544 verity 1 PARTLABEL=rootfs PARTLABEL=rootfs 4096 4096 3943 3944 sha256 2f969fa9e9e4e20b37746f22633e85b178f5db7c143e11f92733a704299cc933 2dd56e34b15c6c84573cf26c4392028421061d2c808975217b45e9a5b49d2087\" rootfstype=squashfs,ext4 rootwait root=/dev/mmcblk0p6 fstools_ignore_partname=1"; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + + factory { + label = "factory"; + linux,code = ; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; + + + leds { + compatible = "gpio-leds"; + + led_status: led@0 { + label = "ant0:red"; + gpios = <&pio 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@1 { + label = "ant0:green"; + gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@2 { + label = "ant0:blue"; + gpios = <&pio 36 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@3 { + label = "ant1:red"; + gpios = <&pio 35 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@4 { + label = "ant1:green"; + gpios = <&pio 34 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@5 { + label = "ant1:blue"; + gpios = <&pio 33 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@6 { + label = "ant2:red"; + gpios = <&pio 38 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@7 { + label = "ant2:green"; + gpios = <&pio 37 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@8 { + label = "ant2:blue"; + gpios = <&pio 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@9 { + label = "ant3:red"; + gpios = <&pio 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@10 { + label = "ant3:green"; + gpios = <&pio 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@11 { + label = "ant3:blue"; + gpios = <&pio 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@12 { + label = "ant4:red"; + gpios = <&pio 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@13 { + label = "ant4:green"; + gpios = <&pio 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@14 { + label = "ant4:blue"; + gpios = <&pio 32 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@15 { + label = "ant5:red"; + gpios = <&pio 45 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@16 { + label = "ant5:green"; + gpios = <&pio 44 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@17 { + label = "ant5:blue"; + gpios = <&pio 43 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + /* LAN */ + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + /* WAN */ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + phy-handle = <&phy6>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <6>; + + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + + /* LED0: nc ; LED1: nc ; LED2: Amber ; LED3: Green */ + mxl,led-config = <0x0 0x0 0x370 0x80>; + }; + + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; +}; + +&pio { + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_pereset"; + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "game"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy@0 { + reg = <0>; + + mediatek,led-config = < + 0x21 0x8009 /* BASIC_CTRL */ + 0x22 0x0c00 /* ON_DURATION */ + 0x23 0x1400 /* BLINK_DURATION */ + 0x24 0xc001 /* LED0_ON_CTRL */ + 0x25 0x0000 /* LED0_BLINK_CTRL */ + 0x26 0xc007 /* LED1_ON_CTRL */ + 0x27 0x003f /* LED1_BLINK_CTRL */ + >; + }; + + phy@1 { + reg = <1>; + + mediatek,led-config = < + 0x21 0x8009 /* BASIC_CTRL */ + 0x22 0x0c00 /* ON_DURATION */ + 0x23 0x1400 /* BLINK_DURATION */ + 0x24 0xc001 /* LED0_ON_CTRL */ + 0x25 0x0000 /* LED0_BLINK_CTRL */ + 0x26 0xc007 /* LED1_ON_CTRL */ + 0x27 0x003f /* LED1_BLINK_CTRL */ + >; + }; + + phy@2 { + reg = <2>; + + mediatek,led-config = < + 0x21 0x8009 /* BASIC_CTRL */ + 0x22 0x0c00 /* ON_DURATION */ + 0x23 0x1400 /* BLINK_DURATION */ + 0x24 0xc001 /* LED0_ON_CTRL */ + 0x25 0x0000 /* LED0_BLINK_CTRL */ + 0x26 0xc007 /* LED1_ON_CTRL */ + 0x27 0x003f /* LED1_BLINK_CTRL */ + >; + }; + + phy@3 { + reg = <3>; + + mediatek,led-config = < + 0x21 0x8009 /* BASIC_CTRL */ + 0x22 0x0c00 /* ON_DURATION */ + 0x23 0x1400 /* BLINK_DURATION */ + 0x24 0xc001 /* LED0_ON_CTRL */ + 0x25 0x0000 /* LED0_BLINK_CTRL */ + 0x26 0xc007 /* LED1_ON_CTRL */ + 0x27 0x003f /* LED1_BLINK_CTRL */ + >; + }; + }; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; + +&trng { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <0x08>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 51903eeace..4013c149f1 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -8,6 +8,9 @@ mediatek_setup_interfaces() local board="$1" case $board in + acer,predator-w6) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 game" eth1 + ;; asus,tuf-ax4200) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1 ;; diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata index 0fe4c69988..c3d7c09974 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata @@ -7,6 +7,20 @@ board=$(board_name) case "$FIRMWARE" in +"mediatek/mt7916_eeprom.bin") + case "$board" in + acer,predator-w6) + caldata_extract_mmc "factory" 0xA0000 0x1000 + ;; + esac + ;; +"mediatek/mt7986_eeprom_mt7976.bin") + case "$board" in + acer,predator-w6) + caldata_extract_mmc "factory" 0x0 0x1000 + ;; + esac + ;; "mediatek/mt7986_eeprom_mt7976_dbdc.bin") case "$board" in asus,tuf-ax4200) diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 3620e3a6fb..ebf76640c8 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -10,6 +10,12 @@ PHYNBR=${DEVPATH##*/phy} board=$(board_name) case "$board" in + acer,predator-w6) + key_path="/var/qcidata/data" + [ "$PHYNBR" = "0" ] && cat $key_path/2gMAC > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && cat $key_path/6gMAC > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "2" ] && cat $key_path/5gMAC > /sys${DEVPATH}/macaddress + ;; asus,tuf-ax4200) CI_UBIPART="UBI_DEV" addr=$(mtd_get_mac_binary_ubi "Factory" 0x4) diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/05_extract_factory_data.sh b/target/linux/mediatek/filogic/base-files/lib/preinit/05_extract_factory_data.sh new file mode 100644 index 0000000000..87287a7d1c --- /dev/null +++ b/target/linux/mediatek/filogic/base-files/lib/preinit/05_extract_factory_data.sh @@ -0,0 +1,25 @@ +. /lib/functions/system.sh + +predator_w6_factory_extract() { + local mmc_part + + mmc_part="$(find_mmc_part qcidata)" + + mkdir -p /var/qcidata/data + mkdir -p /var/qcidata/mount + + mount -r "$mmc_part" /var/qcidata/mount + + cp /var/qcidata/mount/factory/*MAC "/var/qcidata/data/" + umount "/var/qcidata/mount" +} + +preinit_extract_factory() { + case $(board_name) in + acer,predator-w6) + predator_w6_factory_extract + ;; + esac +} + +boot_hook_add preinit_main preinit_extract_factory diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh b/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh index cfddd9cedc..69d0ab6c60 100644 --- a/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh +++ b/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh @@ -2,6 +2,14 @@ preinit_set_mac_address() { case $(board_name) in + acer,predator-w6) + key_path="/var/qcidata/data" + ip link set dev lan1 address "$(cat $key_path/LANMAC)" + ip link set dev lan2 address "$(cat $key_path/LANMAC)" + ip link set dev lan3 address "$(cat $key_path/LANMAC)" + ip link set dev game address "$(cat $key_path/LANMAC)" + ip link set dev eth1 address "$(cat $key_path/WANMAC)" + ;; asus,tuf-ax4200) CI_UBIPART="UBI_DEV" addr=$(mtd_get_mac_binary_ubi "Factory" 0x4) diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 858e11ff00..b0585284ca 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -51,6 +51,11 @@ platform_do_upgrade() { local board=$(board_name) case "$board" in + acer,predator-w6) + CI_KERNPART="kernel" + CI_ROOTPART="rootfs" + emmc_do_upgrade "$1" + ;; asus,tuf-ax4200) CI_UBIPART="UBI_DEV" CI_KERNPART="linux" diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index d79e929901..e008c23c0a 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -98,6 +98,21 @@ define Device/asus_tuf-ax4200 endef TARGET_DEVICES += asus_tuf-ax4200 +define Device/acer_predator-w6 + DEVICE_VENDOR := Acer + DEVICE_MODEL := Predator W6 + DEVICE_DTS := mt7986a-acer-predator-w6 + DEVICE_DTS_DIR := ../dts + DEVICE_DTS_LOADADDR := 0x47000000 + DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware kmod-mt7916-firmware mt7986-wo-firmware + IMAGES := sysupgrade.bin + KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += acer_predator-w6 + define Device/bananapi_bpi-r3 DEVICE_VENDOR := Bananapi DEVICE_MODEL := BPi-R3