From f0cc5f6c0a72b7da9ed5915cf561e2f81d514c68 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sun, 13 Sep 2020 09:34:37 +0200 Subject: [PATCH 01/15] ramips/mediatek: improve GRO performance, fix PPE packet parsing Backport upstream changes to initialize GDM settings and reset PPE Allow GMAC to recognize the special tag to fix PPE packet parsing Improve GRO performance by passing PPE L4 hash as skb hash Signed-off-by: Felix Fietkau --- ...atek-Integrate-GDM-PSE-setup-operat.patch} | 46 +++++------- ...iatek-Refine-the-timing-of-GDM-PSE-s.patch | 45 +++++++++++ ...diatek-Enable-GDM-GDMA_DROP_ALL-mode.patch | 33 ++++++++ ...rnet-mtk_eth_soc-fix-rx-vlan-offload.patch | 2 +- ..._eth_soc-use-larger-burst-size-for-q.patch | 2 +- ..._eth_soc-implement-dynamic-interrupt.patch | 20 ++--- ..._eth_soc-cache-hardware-pointer-of-l.patch | 4 +- ...k_eth_soc-fix-parsing-packets-in-GDM.patch | 75 +++++++++++++++++++ ..._eth_soc-set-PPE-flow-hash-as-skb-ha.patch | 23 ++++++ .../mediatek/patches-5.4/0999-hnat.patch | 26 +++---- ..._eth_soc-add-support-for-coherent-DM.patch | 6 +- 11 files changed, 223 insertions(+), 59 deletions(-) rename target/linux/{mediatek/patches-5.4/1000-eth-gdm-config-backport.patch => generic/backport-5.4/760-net-ethernet-mediatek-Integrate-GDM-PSE-setup-operat.patch} (65%) create mode 100644 target/linux/generic/backport-5.4/761-net-ethernet-mediatek-Refine-the-timing-of-GDM-PSE-s.patch create mode 100644 target/linux/generic/backport-5.4/762-net-ethernet-mediatek-Enable-GDM-GDMA_DROP_ALL-mode.patch create mode 100644 target/linux/generic/pending-5.4/770-13-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch create mode 100644 target/linux/generic/pending-5.4/770-14-net-ethernet-mtk_eth_soc-set-PPE-flow-hash-as-skb-ha.patch diff --git a/target/linux/mediatek/patches-5.4/1000-eth-gdm-config-backport.patch b/target/linux/generic/backport-5.4/760-net-ethernet-mediatek-Integrate-GDM-PSE-setup-operat.patch similarity index 65% rename from target/linux/mediatek/patches-5.4/1000-eth-gdm-config-backport.patch rename to target/linux/generic/backport-5.4/760-net-ethernet-mediatek-Integrate-GDM-PSE-setup-operat.patch index a2acadfd90..4df1fd2677 100644 --- a/target/linux/mediatek/patches-5.4/1000-eth-gdm-config-backport.patch +++ b/target/linux/generic/backport-5.4/760-net-ethernet-mediatek-Integrate-GDM-PSE-setup-operat.patch @@ -1,6 +1,16 @@ +From: MarkLee +Date: Wed, 13 Nov 2019 10:38:42 +0800 +Subject: [PATCH] net: ethernet: mediatek: Integrate GDM/PSE setup operations + +Integrate GDM/PSE setup operations into single function "mtk_gdm_config" + +Signed-off-by: MarkLee +Signed-off-by: David S. Miller +--- + --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2240,6 +2240,31 @@ static int mtk_start_dma(struct mtk_eth +@@ -2211,6 +2211,28 @@ static int mtk_start_dma(struct mtk_eth return 0; } @@ -8,9 +18,6 @@ +{ + int i; + -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) -+ return; -+ + for (i = 0; i < MTK_MAC_COUNT; i++) { + u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); + @@ -32,26 +39,8 @@ static int mtk_open(struct net_device *dev) { struct mtk_mac *mac = netdev_priv(dev); -@@ -2260,6 +2285,8 @@ static int mtk_open(struct net_device *d - if (err) - return err; - -+ mtk_gdm_config(eth, MTK_GDMA_TO_PDMA); -+ - napi_enable(ð->tx_napi); - napi_enable(ð->rx_napi); - mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); -@@ -2315,6 +2342,8 @@ static int mtk_stop(struct net_device *d - if (!refcount_dec_and_test(ð->dma_refcnt)) - return 0; - -+ mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); -+ - mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); - mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); - napi_disable(ð->tx_napi); -@@ -2498,8 +2527,6 @@ static int mtk_hw_init(struct mtk_eth *e - /* disable delay and normal interrupt */ +@@ -2406,8 +2428,6 @@ static int mtk_hw_init(struct mtk_eth *e + mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); mtk_tx_irq_disable(eth, ~0); mtk_rx_irq_disable(eth, ~0); - mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); @@ -59,7 +48,7 @@ /* FE int grouping */ mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); -@@ -2508,19 +2535,6 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -2416,18 +2436,7 @@ static int mtk_hw_init(struct mtk_eth *e mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); @@ -75,18 +64,17 @@ - /* setup the mac dma */ - mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); - } -- ++ mtk_gdm_config(eth, MTK_GDMA_TO_PDMA); + return 0; - err_disable_pm: --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -85,6 +85,8 @@ +@@ -84,6 +84,7 @@ #define MTK_GDMA_ICS_EN BIT(22) #define MTK_GDMA_TCS_EN BIT(21) #define MTK_GDMA_UCS_EN BIT(20) +#define MTK_GDMA_TO_PDMA 0x0 -+#define MTK_GDMA_DROP_ALL 0x7777 /* Unicast Filter MAC Address Register - Low */ #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) diff --git a/target/linux/generic/backport-5.4/761-net-ethernet-mediatek-Refine-the-timing-of-GDM-PSE-s.patch b/target/linux/generic/backport-5.4/761-net-ethernet-mediatek-Refine-the-timing-of-GDM-PSE-s.patch new file mode 100644 index 0000000000..cdcd6a1a33 --- /dev/null +++ b/target/linux/generic/backport-5.4/761-net-ethernet-mediatek-Refine-the-timing-of-GDM-PSE-s.patch @@ -0,0 +1,45 @@ +From: MarkLee +Date: Wed, 13 Nov 2019 10:38:43 +0800 +Subject: [PATCH] net: ethernet: mediatek: Refine the timing of GDM/PSE setup + +Refine the timing of GDM/PSE setup, move it from mtk_hw_init +to mtk_open. This is recommended by the mt762x HW design to +do GDM/PSE setup only after PDMA has been started. + +We exclude mt7628 in mtk_gdm_config function since it is a old IP +and there is no GDM/PSE block on it. + +Signed-off-by: MarkLee +Signed-off-by: David S. Miller +--- + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -2215,6 +2215,9 @@ static void mtk_gdm_config(struct mtk_et + { + int i; + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) ++ return; ++ + for (i = 0; i < MTK_MAC_COUNT; i++) { + u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); + +@@ -2253,6 +2256,8 @@ static int mtk_open(struct net_device *d + if (err) + return err; + ++ mtk_gdm_config(eth, MTK_GDMA_TO_PDMA); ++ + napi_enable(ð->tx_napi); + napi_enable(ð->rx_napi); + mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); +@@ -2436,8 +2441,6 @@ static int mtk_hw_init(struct mtk_eth *e + mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); + mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); + +- mtk_gdm_config(eth, MTK_GDMA_TO_PDMA); +- + return 0; + + err_disable_pm: diff --git a/target/linux/generic/backport-5.4/762-net-ethernet-mediatek-Enable-GDM-GDMA_DROP_ALL-mode.patch b/target/linux/generic/backport-5.4/762-net-ethernet-mediatek-Enable-GDM-GDMA_DROP_ALL-mode.patch new file mode 100644 index 0000000000..b8c40ef665 --- /dev/null +++ b/target/linux/generic/backport-5.4/762-net-ethernet-mediatek-Enable-GDM-GDMA_DROP_ALL-mode.patch @@ -0,0 +1,33 @@ +From: MarkLee +Date: Wed, 13 Nov 2019 10:38:44 +0800 +Subject: [PATCH] net: ethernet: mediatek: Enable GDM GDMA_DROP_ALL mode + +Enable GDM GDMA_DROP_ALL mode to drop all packet during the +stop operation. This is recommended by the mt762x HW design +to drop all packet from GMAC before stopping PDMA. + +Signed-off-by: MarkLee +Signed-off-by: David S. Miller +--- + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -2310,6 +2310,8 @@ static int mtk_stop(struct net_device *d + if (!refcount_dec_and_test(ð->dma_refcnt)) + return 0; + ++ mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); ++ + mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); + mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); + napi_disable(ð->tx_napi); +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -85,6 +85,7 @@ + #define MTK_GDMA_TCS_EN BIT(21) + #define MTK_GDMA_UCS_EN BIT(20) + #define MTK_GDMA_TO_PDMA 0x0 ++#define MTK_GDMA_DROP_ALL 0x7777 + + /* Unicast Filter MAC Address Register - Low */ + #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) diff --git a/target/linux/generic/pending-5.4/770-02-net-ethernet-mtk_eth_soc-fix-rx-vlan-offload.patch b/target/linux/generic/pending-5.4/770-02-net-ethernet-mtk_eth_soc-fix-rx-vlan-offload.patch index 899bc41c93..e17877028f 100644 --- a/target/linux/generic/pending-5.4/770-02-net-ethernet-mtk_eth_soc-fix-rx-vlan-offload.patch +++ b/target/linux/generic/pending-5.4/770-02-net-ethernet-mtk_eth_soc-fix-rx-vlan-offload.patch @@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau skb_record_rx_queue(skb, 0); --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -293,6 +293,7 @@ +@@ -295,6 +295,7 @@ #define RX_DMA_LSO BIT(30) #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) diff --git a/target/linux/generic/pending-5.4/770-04-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-q.patch b/target/linux/generic/pending-5.4/770-04-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-q.patch index b066d35d2e..e135f27f95 100644 --- a/target/linux/generic/pending-5.4/770-04-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-q.patch +++ b/target/linux/generic/pending-5.4/770-04-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-q.patch @@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau MTK_QDMA_GLO_CFG); --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -195,7 +195,7 @@ +@@ -197,7 +197,7 @@ #define MTK_RX_BT_32DWORDS (3 << 11) #define MTK_NDP_CO_PRO BIT(10) #define MTK_TX_WB_DDONE BIT(6) diff --git a/target/linux/generic/pending-5.4/770-06-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch b/target/linux/generic/pending-5.4/770-06-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch index 4372029423..8720ab503c 100644 --- a/target/linux/generic/pending-5.4/770-06-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch +++ b/target/linux/generic/pending-5.4/770-06-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch @@ -95,7 +95,7 @@ Signed-off-by: Felix Fietkau if (likely(napi_schedule_prep(ð->tx_napi))) { __napi_schedule(ð->tx_napi); mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); -@@ -2282,6 +2299,9 @@ static int mtk_stop(struct net_device *d +@@ -2311,6 +2328,9 @@ static int mtk_stop(struct net_device *d napi_disable(ð->tx_napi); napi_disable(ð->rx_napi); @@ -105,7 +105,7 @@ Signed-off-by: Felix Fietkau if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); -@@ -2331,6 +2351,64 @@ err_disable_clks: +@@ -2360,6 +2380,64 @@ err_disable_clks: return ret; } @@ -170,7 +170,7 @@ Signed-off-by: Felix Fietkau static int mtk_hw_init(struct mtk_eth *eth) { int i, val, ret; -@@ -2352,9 +2430,6 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -2381,9 +2459,6 @@ static int mtk_hw_init(struct mtk_eth *e goto err_disable_pm; } @@ -180,7 +180,7 @@ Signed-off-by: Felix Fietkau /* disable delay and normal interrupt */ mtk_tx_irq_disable(eth, ~0); mtk_rx_irq_disable(eth, ~0); -@@ -2393,11 +2468,10 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -2422,11 +2497,10 @@ static int mtk_hw_init(struct mtk_eth *e /* Enable RX VLan Offloading */ mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); @@ -193,8 +193,8 @@ Signed-off-by: Felix Fietkau - mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); mtk_tx_irq_disable(eth, ~0); mtk_rx_irq_disable(eth, ~0); - mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); -@@ -2916,6 +2990,13 @@ static int mtk_probe(struct platform_dev + +@@ -2930,6 +3004,13 @@ static int mtk_probe(struct platform_dev spin_lock_init(ð->page_lock); spin_lock_init(ð->tx_irq_lock); spin_lock_init(ð->rx_irq_lock); @@ -218,7 +218,7 @@ Signed-off-by: Felix Fietkau #define MTK_QDMA_PAGE_SIZE 2048 #define MTK_MAX_RX_LENGTH 1536 -@@ -129,13 +130,18 @@ +@@ -131,13 +132,18 @@ /* PDMA Delay Interrupt Register */ #define MTK_PDMA_DELAY_INT 0xa0c @@ -242,7 +242,7 @@ Signed-off-by: Felix Fietkau /* PDMA Interrupt Status Register */ #define MTK_PDMA_INT_STATUS 0xa20 -@@ -217,6 +223,7 @@ +@@ -219,6 +225,7 @@ /* QDMA Interrupt Status Register */ #define MTK_QDMA_INT_STATUS 0x1A18 #define MTK_RX_DONE_DLY BIT(30) @@ -250,7 +250,7 @@ Signed-off-by: Felix Fietkau #define MTK_RX_DONE_INT3 BIT(19) #define MTK_RX_DONE_INT2 BIT(18) #define MTK_RX_DONE_INT1 BIT(17) -@@ -226,8 +233,7 @@ +@@ -228,8 +235,7 @@ #define MTK_TX_DONE_INT1 BIT(1) #define MTK_TX_DONE_INT0 BIT(0) #define MTK_RX_DONE_INT MTK_RX_DONE_DLY @@ -260,7 +260,7 @@ Signed-off-by: Felix Fietkau /* QDMA Interrupt grouping registers */ #define MTK_QDMA_INT_GRP1 0x1a20 -@@ -890,6 +896,18 @@ struct mtk_eth { +@@ -892,6 +898,18 @@ struct mtk_eth { const struct mtk_soc_data *soc; diff --git a/target/linux/generic/pending-5.4/770-08-net-ethernet-mtk_eth_soc-cache-hardware-pointer-of-l.patch b/target/linux/generic/pending-5.4/770-08-net-ethernet-mtk_eth_soc-cache-hardware-pointer-of-l.patch index 29dfd932e7..a7231d826c 100644 --- a/target/linux/generic/pending-5.4/770-08-net-ethernet-mtk_eth_soc-cache-hardware-pointer-of-l.patch +++ b/target/linux/generic/pending-5.4/770-08-net-ethernet-mtk_eth_soc-cache-hardware-pointer-of-l.patch @@ -49,7 +49,7 @@ Signed-off-by: Felix Fietkau } else { --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -622,6 +622,7 @@ struct mtk_tx_buf { +@@ -624,6 +624,7 @@ struct mtk_tx_buf { * @phys: The physical addr of tx_buf * @next_free: Pointer to the next free descriptor * @last_free: Pointer to the last free descriptor @@ -57,7 +57,7 @@ Signed-off-by: Felix Fietkau * @thresh: The threshold of minimum amount of free descriptors * @free_count: QDMA uses a linked list. Track how many free descriptors * are present -@@ -632,6 +633,7 @@ struct mtk_tx_ring { +@@ -634,6 +635,7 @@ struct mtk_tx_ring { dma_addr_t phys; struct mtk_tx_dma *next_free; struct mtk_tx_dma *last_free; diff --git a/target/linux/generic/pending-5.4/770-13-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch b/target/linux/generic/pending-5.4/770-13-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch new file mode 100644 index 0000000000..36a52bbc06 --- /dev/null +++ b/target/linux/generic/pending-5.4/770-13-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch @@ -0,0 +1,75 @@ +From: Felix Fietkau +Date: Sun, 13 Sep 2020 08:17:02 +0200 +Subject: [PATCH] net: ethernet: mtk_eth_soc: fix parsing packets in GDM + +When using DSA, set the special tag in GDM ingress control to allow the MAC +to parse packets properly earlier. This affects rx DMA source port reporting. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + #include "mtk_eth_soc.h" + +@@ -1240,12 +1241,14 @@ static int mtk_poll_rx(struct napi_struc + u8 *data, *new_data; + struct mtk_rx_dma *rxd, trxd; + int done = 0, bytes = 0; ++ bool uses_dsa = eth->netdev[0] && netdev_uses_dsa(eth->netdev[0]); + + while (done < budget) { + struct net_device *netdev; + unsigned int pktlen; + dma_addr_t dma_addr; + int mac; ++ u16 hash; + + ring = mtk_get_rx_ring(eth); + if (unlikely(!ring)) +@@ -1259,13 +1262,13 @@ static int mtk_poll_rx(struct napi_struc + break; + + /* find out which mac the packet come from. values start at 1 */ +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) + mac = 0; +- } else { +- mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & +- RX_DMA_FPORT_MASK; +- mac--; +- } ++ else if (uses_dsa) ++ mac = !(trxd.rxd4 >> 22); ++ else ++ mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & ++ RX_DMA_FPORT_MASK) - 1; + + if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || + !eth->netdev[mac])) +@@ -2247,6 +2250,9 @@ static void mtk_gdm_config(struct mtk_et + + val |= config; + ++ if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0])) ++ val |= MTK_GDMA_SPECIAL_TAG; ++ + mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); + } + /* Reset and enable PSE */ +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -82,6 +82,7 @@ + + /* GDM Exgress Control Register */ + #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) ++#define MTK_GDMA_SPECIAL_TAG BIT(24) + #define MTK_GDMA_ICS_EN BIT(22) + #define MTK_GDMA_TCS_EN BIT(21) + #define MTK_GDMA_UCS_EN BIT(20) diff --git a/target/linux/generic/pending-5.4/770-14-net-ethernet-mtk_eth_soc-set-PPE-flow-hash-as-skb-ha.patch b/target/linux/generic/pending-5.4/770-14-net-ethernet-mtk_eth_soc-set-PPE-flow-hash-as-skb-ha.patch new file mode 100644 index 0000000000..384af9d21d --- /dev/null +++ b/target/linux/generic/pending-5.4/770-14-net-ethernet-mtk_eth_soc-set-PPE-flow-hash-as-skb-ha.patch @@ -0,0 +1,23 @@ +From: Felix Fietkau +Date: Sun, 13 Sep 2020 08:27:24 +0200 +Subject: [PATCH] net: ethernet: mtk_eth_soc: set PPE flow hash as skb hash + if present + +This improves GRO performance + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -1318,6 +1318,10 @@ static int mtk_poll_rx(struct napi_struc + skb->protocol = eth_type_trans(skb, netdev); + bytes += pktlen; + ++ hash = trxd.rxd4 & GENMASK(13, 0); ++ if (hash != GENMASK(13, 0)) ++ skb_set_hash(skb, hash, PKT_HASH_TYPE_L4); ++ + if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && + (trxd.rxd2 & RX_DMA_VTAG)) + __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), diff --git a/target/linux/mediatek/patches-5.4/0999-hnat.patch b/target/linux/mediatek/patches-5.4/0999-hnat.patch index 50850a906e..685c741043 100644 --- a/target/linux/mediatek/patches-5.4/0999-hnat.patch +++ b/target/linux/mediatek/patches-5.4/0999-hnat.patch @@ -144,10 +144,10 @@ #include +#include +#include + #include #include "mtk_eth_soc.h" - -@@ -1320,8 +1322,16 @@ static int mtk_poll_rx(struct napi_struc +@@ -1327,8 +1329,16 @@ static int mtk_poll_rx(struct napi_struc (trxd.rxd2 & RX_DMA_VTAG)) __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), RX_DMA_VID(trxd.rxd3)); @@ -166,7 +166,7 @@ skip_rx: ring->data[idx] = new_data; -@@ -2255,6 +2265,9 @@ static int mtk_open(struct net_device *d +@@ -2292,6 +2302,9 @@ static int mtk_open(struct net_device *d mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); refcount_set(ð->dma_refcnt, 1); @@ -176,7 +176,7 @@ } else refcount_inc(ð->dma_refcnt); -@@ -2316,6 +2329,9 @@ static int mtk_stop(struct net_device *d +@@ -2355,6 +2368,9 @@ static int mtk_stop(struct net_device *d mtk_dma_free(eth); @@ -186,7 +186,7 @@ return 0; } -@@ -2829,6 +2845,27 @@ static int mtk_set_rxnfc(struct net_devi +@@ -2853,6 +2869,27 @@ static int mtk_set_rxnfc(struct net_devi return ret; } @@ -214,7 +214,7 @@ static const struct ethtool_ops mtk_ethtool_ops = { .get_link_ksettings = mtk_get_link_ksettings, .set_link_ksettings = mtk_set_link_ksettings, -@@ -2860,6 +2897,9 @@ static const struct net_device_ops mtk_n +@@ -2884,6 +2921,9 @@ static const struct net_device_ops mtk_n #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = mtk_poll_controller, #endif @@ -224,7 +224,7 @@ }; static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) -@@ -3202,6 +3242,7 @@ static const struct mtk_soc_data mt7622_ +@@ -3226,6 +3266,7 @@ static const struct mtk_soc_data mt7622_ .hw_features = MTK_HW_FEATURES, .required_clks = MT7622_CLKS_BITMAP, .required_pctl = false, @@ -234,7 +234,7 @@ static const struct mtk_soc_data mt7623_data = { --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -787,6 +787,13 @@ enum mkt_eth_capabilities { +@@ -790,6 +790,13 @@ enum mkt_eth_capabilities { MTK_MUX_U3_GMAC2_TO_QPHY | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) @@ -248,7 +248,7 @@ /* struct mtk_eth_data - This is the structure holding all differences * among various plaforms * @ana_rgc3: The offset for register ANA_RGC3 related to -@@ -804,6 +811,7 @@ struct mtk_soc_data { +@@ -807,6 +814,7 @@ struct mtk_soc_data { u32 required_clks; bool required_pctl; netdev_features_t hw_features; @@ -256,7 +256,7 @@ }; /* currently no SoC has more than 2 macs */ -@@ -829,6 +837,23 @@ struct mtk_sgmii { +@@ -832,6 +840,23 @@ struct mtk_sgmii { u32 ana_rgc3; }; @@ -280,7 +280,7 @@ /* struct mtk_eth - This is the main datasructure for holding the state * of the driver * @dev: The device pointer -@@ -914,6 +939,16 @@ struct mtk_eth { +@@ -917,6 +942,16 @@ struct mtk_eth { u32 tx_int_status_reg; u32 rx_dma_l4_valid; int ip_align; @@ -297,7 +297,7 @@ }; /* struct mtk_mac - the structure that holds the info about the MACs of the -@@ -946,6 +981,7 @@ void mtk_stats_update_mac(struct mtk_mac +@@ -949,6 +984,7 @@ void mtk_stats_update_mac(struct mtk_mac void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); u32 mtk_r32(struct mtk_eth *eth, unsigned reg); @@ -305,7 +305,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, u32 ana_rgc3); -@@ -958,4 +994,13 @@ int mtk_gmac_sgmii_path_setup(struct mtk +@@ -961,4 +997,13 @@ int mtk_gmac_sgmii_path_setup(struct mtk int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); diff --git a/target/linux/mediatek/patches-5.4/1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch b/target/linux/mediatek/patches-5.4/1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch index cc104927d8..ed9aecdf74 100644 --- a/target/linux/mediatek/patches-5.4/1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch +++ b/target/linux/mediatek/patches-5.4/1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch @@ -37,7 +37,7 @@ Signed-off-by: Felix Fietkau #include #include #include -@@ -2476,6 +2477,12 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -2486,6 +2487,12 @@ static int mtk_hw_init(struct mtk_eth *e if (ret) goto err_disable_pm; @@ -50,7 +50,7 @@ Signed-off-by: Felix Fietkau if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { ret = device_reset(eth->dev); if (ret) { -@@ -3078,6 +3085,16 @@ static int mtk_probe(struct platform_dev +@@ -3088,6 +3095,16 @@ static int mtk_probe(struct platform_dev } } @@ -69,7 +69,7 @@ Signed-off-by: Felix Fietkau GFP_KERNEL); --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -425,6 +425,11 @@ +@@ -426,6 +426,11 @@ #define RSTCTRL_FE BIT(6) #define RSTCTRL_PPE BIT(31) From 6f2c95f0cf0519631adb5100ab71f908a2968cca Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sun, 13 Sep 2020 18:49:26 +0800 Subject: [PATCH 02/15] ramips: mt7621: pbr-m1: add pcie reset for asm1061 this board has a pcie to sata bridge connected to pcie2 with a separated pcie reset on gpio7. add reset-gpios and corresponding pinctrl nodes into dts. Signed-off-by: Chuanhong Guo --- target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts b/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts index 6b4d3b35d4..1e17eadde1 100644 --- a/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts +++ b/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts @@ -144,8 +144,20 @@ }; }; +&pinctrl { + uart3_gpio: uart3-gpio { + uart3 { + groups = "uart3"; + function = "gpio"; + }; + }; +}; + &pcie { status = "okay"; + pinctrl-0 = <&pcie_pins>, <&uart3_gpio>; + reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>, + <&gpio 7 GPIO_ACTIVE_LOW>; }; &pcie0 { From 8126521e11b4da3c3fa79feb794646068dbaa4b1 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sun, 13 Sep 2020 18:53:25 +0800 Subject: [PATCH 03/15] ramips: mt7621: pbr-m1: increase SPI clock to 50MHz Signed-off-by: Chuanhong Guo --- target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts b/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts index 1e17eadde1..15b717616e 100644 --- a/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts +++ b/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts @@ -109,7 +109,8 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <10000000>; + spi-max-frequency = <50000000>; + m25p,fast-read; broken-flash-reset; partitions { From 2188ef954ee32ec0b24674f07634f39ecf63c38e Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sun, 13 Sep 2020 18:57:11 +0800 Subject: [PATCH 04/15] ramips: mt7621: pbr-m1: fix firmware size This board is equipped with Winbond W25Q256FV 32M SPI-NOR. Fix partition size for that. Signed-off-by: Chuanhong Guo --- target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts | 2 +- target/linux/ramips/image/mt7621.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts b/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts index 15b717616e..beaa380818 100644 --- a/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts +++ b/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts @@ -139,7 +139,7 @@ partition@50000 { compatible = "denx,uimage"; label = "firmware"; - reg = <0x50000 0xfb0000>; + reg = <0x50000 0x1fb0000>; }; }; }; diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk index 46516b3e40..78629563ee 100644 --- a/target/linux/ramips/image/mt7621.mk +++ b/target/linux/ramips/image/mt7621.mk @@ -333,7 +333,7 @@ TARGET_DEVICES += d-team_newifi-d2 define Device/d-team_pbr-m1 $(Device/dsa-migration) - IMAGE_SIZE := 16064k + IMAGE_SIZE := 32448k DEVICE_VENDOR := PandoraBox DEVICE_MODEL := PBR-M1 DEVICE_PACKAGES := kmod-ata-ahci kmod-mt7603 kmod-mt76x2 kmod-sdhci-mt7620 \ From 04d3b517dc3301e0148a2ce811ffc136568b04bd Mon Sep 17 00:00:00 2001 From: Klaus Kudielka Date: Fri, 27 Dec 2019 19:15:31 +0100 Subject: [PATCH 05/15] uboot-envtools: mvebu: update uci defaults for Turris Omnia On the Turris Omnia 2019, u-boot environment is located at 0xF0000, instead of 0xC0000. The switch happened with u-boot-omnia package version 2019-04-2 (May 10, 2019). Check the installed u-boot release, and set the default accordingly. Signed-off-by: Klaus Kudielka [bump PKG_RELEASE, use lower case for hex offset] Signed-off-by: Adrian Schmutzler --- package/boot/uboot-envtools/Makefile | 2 +- package/boot/uboot-envtools/files/mvebu | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/package/boot/uboot-envtools/Makefile b/package/boot/uboot-envtools/Makefile index 7d464f8d08..473704053c 100644 --- a/package/boot/uboot-envtools/Makefile +++ b/package/boot/uboot-envtools/Makefile @@ -10,7 +10,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=uboot-envtools PKG_DISTNAME:=u-boot PKG_VERSION:=2020.04 -PKG_RELEASE:=3 +PKG_RELEASE:=4 PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:= \ diff --git a/package/boot/uboot-envtools/files/mvebu b/package/boot/uboot-envtools/files/mvebu index 8ed1f87ead..1d3b79b962 100644 --- a/package/boot/uboot-envtools/files/mvebu +++ b/package/boot/uboot-envtools/files/mvebu @@ -15,7 +15,11 @@ board=$(board_name) case "$board" in cznic,turris-omnia) - ubootenv_add_uci_config "/dev/mtd0" "0xC0000" "0x10000" "0x40000" + if grep -q 'U-Boot 2015.10-rc2' /dev/mtd0; then + ubootenv_add_uci_config "/dev/mtd0" "0xc0000" "0x10000" "0x40000" + else + ubootenv_add_uci_config "/dev/mtd0" "0xf0000" "0x10000" "0x10000" + fi ;; glinet,gl-mv1000) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x8000" "0x8000" "1" From a9790dff532e154a93b12abaeccd7889d9159791 Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Mon, 31 Aug 2020 19:46:35 +0200 Subject: [PATCH 06/15] cns3xxx: drop target This target has not been updated to 5.4 yet, and the only person trying it (Koen) decided to retreat based on the following reasons: - The target is not DT-aware at all - The huge amount of effort required - The SoC itself reached EoL at Cavium for some time now - Upstream removed some important parts as it's also slowly getting EoL over there - The commercial product that used this will fade out shortly - The amount of download for this binary suggest that the target is not that popular Since nobody has picked up the work since then, and this is the last remaining 4.19-only target, finally drop it now. Signed-off-by: Adrian Schmutzler --- package/kernel/hwmon-gsc/Makefile | 2 +- target/linux/cns3xxx/Makefile | 28 - .../cns3xxx/base-files/etc/init.d/netdev-cpu | 21 - .../linux/cns3xxx/base-files/lib/cns3xxx.sh | 26 - .../cns3xxx/base-files/lib/preinit/01_sysinfo | 7 - .../base-files/lib/upgrade/platform.sh | 19 - target/linux/cns3xxx/config-4.19 | 368 ----- .../files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S | 87 -- .../files/arch/arm/mach-cns3xxx/gpio.c | 292 ---- .../files/arch/arm/mach-cns3xxx/headsmp.S | 41 - .../files/arch/arm/mach-cns3xxx/hotplug.c | 130 -- .../arch/arm/mach-cns3xxx/include/mach/gpio.h | 17 - .../arch/arm/mach-cns3xxx/include/mach/smp.h | 8 - .../files/arch/arm/mach-cns3xxx/laguna.c | 1123 -------------- .../files/arch/arm/mach-cns3xxx/platsmp.c | 327 ---- .../files/drivers/i2c/busses/i2c-cns3xxx.c | 374 ----- .../files/drivers/net/ethernet/cavium/Kconfig | 24 - .../drivers/net/ethernet/cavium/Makefile | 5 - .../drivers/net/ethernet/cavium/cns3xxx_eth.c | 1325 ----------------- .../cns3xxx/files/drivers/spi/spi-cns3xxx.c | 448 ------ .../include/linux/platform_data/cns3xxx.h | 26 - target/linux/cns3xxx/image/Makefile | 44 - .../000-cns3xxx_arch_include.patch | 9 - .../001-arm_openwrt_machtypes.patch | 10 - ...-arm_introduce-dma-fiq-irq-broadcast.patch | 80 - .../patches-4.19/020-watchdog_support.patch | 184 --- .../patches-4.19/025-smp_support.patch | 30 - .../cns3xxx/patches-4.19/030-pcie_clock.patch | 11 - .../patches-4.19/040-fiq_support.patch | 40 - .../cns3xxx/patches-4.19/045-twd_base.patch | 43 - .../cns3xxx/patches-4.19/055-pcie_io.patch | 19 - .../cns3xxx/patches-4.19/060-pcie_abort.patch | 109 -- .../patches-4.19/065-pcie_skip_inactive.patch | 11 - .../patches-4.19/070-i2c_support.patch | 31 - .../patches-4.19/075-spi_support.patch | 51 - .../patches-4.19/080-sata_support.patch | 40 - .../cns3xxx/patches-4.19/090-timers.patch | 105 -- .../093-add-virt-pci-io-mapping.patch | 41 - .../patches-4.19/095-gpio_support.patch | 67 - .../097-l2x0_cmdline_disable.patch | 69 - .../patches-4.19/100-laguna_support.patch | 46 - .../101-laguna_sdhci_card_detect.patch | 14 - .../110-pci_isolated_interrupts.patch | 95 -- ...-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch | 23 - .../200-broadcom_phy_reinit.patch | 15 - .../patches-4.19/210-dwc2_defaults.patch | 63 - 46 files changed, 1 insertion(+), 5947 deletions(-) delete mode 100644 target/linux/cns3xxx/Makefile delete mode 100755 target/linux/cns3xxx/base-files/etc/init.d/netdev-cpu delete mode 100644 target/linux/cns3xxx/base-files/lib/cns3xxx.sh delete mode 100644 target/linux/cns3xxx/base-files/lib/preinit/01_sysinfo delete mode 100644 target/linux/cns3xxx/base-files/lib/upgrade/platform.sh delete mode 100644 target/linux/cns3xxx/config-4.19 delete mode 100644 target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S delete mode 100644 target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c delete mode 100644 target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S delete mode 100644 target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/hotplug.c delete mode 100644 target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/gpio.h delete mode 100644 target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/smp.h delete mode 100644 target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c delete mode 100644 target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c delete mode 100644 target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c delete mode 100644 target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Kconfig delete mode 100644 target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Makefile delete mode 100644 target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c delete mode 100644 target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c delete mode 100644 target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h delete mode 100644 target/linux/cns3xxx/image/Makefile delete mode 100644 target/linux/cns3xxx/patches-4.19/000-cns3xxx_arch_include.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/001-arm_openwrt_machtypes.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/010-arm_introduce-dma-fiq-irq-broadcast.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/020-watchdog_support.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/025-smp_support.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/030-pcie_clock.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/040-fiq_support.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/045-twd_base.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/055-pcie_io.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/060-pcie_abort.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/065-pcie_skip_inactive.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/070-i2c_support.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/075-spi_support.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/080-sata_support.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/090-timers.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/093-add-virt-pci-io-mapping.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/095-gpio_support.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/097-l2x0_cmdline_disable.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/100-laguna_support.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/101-laguna_sdhci_card_detect.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/110-pci_isolated_interrupts.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch delete mode 100644 target/linux/cns3xxx/patches-4.19/200-broadcom_phy_reinit.patch delete mode 100644 target/linux/cns3xxx/patches-4.19/210-dwc2_defaults.patch diff --git a/package/kernel/hwmon-gsc/Makefile b/package/kernel/hwmon-gsc/Makefile index 95f6fab4c0..8cf4e0ee79 100644 --- a/package/kernel/hwmon-gsc/Makefile +++ b/package/kernel/hwmon-gsc/Makefile @@ -8,7 +8,7 @@ include $(INCLUDE_DIR)/package.mk define KernelPackage/hwmon-gsc SUBMENU:=Hardware Monitoring Support - DEPENDS:=@TARGET_imx6||TARGET_cns3xxx +kmod-hwmon-core +kmod-i2c-core + DEPENDS:=@TARGET_imx6 +kmod-hwmon-core +kmod-i2c-core TITLE:=Driver for the Gateworks System Controller AUTOLOAD:=$(call AutoLoad,60,gsc) FILES:=$(PKG_BUILD_DIR)/gsc.ko diff --git a/target/linux/cns3xxx/Makefile b/target/linux/cns3xxx/Makefile deleted file mode 100644 index 04df322b64..0000000000 --- a/target/linux/cns3xxx/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# Copyright (C) 2010-2012 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=arm -BOARD:=cns3xxx -BOARDNAME:=Cavium Networks Econa CNS3xxx -FEATURES:=squashfs fpu gpio pcie usb usbgadget -CPU_TYPE:=mpcore -CPU_SUBTYPE:=vfp -KERNEL_PATCHVER:=4.19 - -define Target/Description - Build images for Cavium Networks Econa CNS3xxx based boards, - eg. the Gateworks Laguna family -endef - -include $(INCLUDE_DIR)/target.mk - -KERNELNAME:=zImage - -DEFAULT_PACKAGES += kmod-ath9k kmod-usb2 wpad-basic-wolfssl - -$(eval $(call BuildTarget)) diff --git a/target/linux/cns3xxx/base-files/etc/init.d/netdev-cpu b/target/linux/cns3xxx/base-files/etc/init.d/netdev-cpu deleted file mode 100755 index 3a2a57bc1e..0000000000 --- a/target/linux/cns3xxx/base-files/etc/init.d/netdev-cpu +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/sh /etc/rc.common - -START=99 - -get_irq() { - local name="$1" - grep -m 1 "$name" /proc/interrupts | cut -d: -f1 | sed 's, *,,' -} - -set_irq_affinity() { - local name="$1" - local val="$2" - local irq="$(get_irq "$name")" - [ -n "$irq" ] || return - echo "$val" > "/proc/irq/$irq/smp_affinity" -} - -start() { - set_irq_affinity gig_switch 2 - set_irq_affinity gig_stat 2 -} diff --git a/target/linux/cns3xxx/base-files/lib/cns3xxx.sh b/target/linux/cns3xxx/base-files/lib/cns3xxx.sh deleted file mode 100644 index ec694c4f7a..0000000000 --- a/target/linux/cns3xxx/base-files/lib/cns3xxx.sh +++ /dev/null @@ -1,26 +0,0 @@ -CNS3XXX_BOARD_NAME= -CNS3XXX_MODEL= - -cns3xxx_board_detect() { - local machine - local name - - machine=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /Hardware/ {print $2}' /proc/cpuinfo) - - case "$machine" in - "Gateworks Corporation Laguna"*) - name="laguna" - ;; - *) - name="generic"; - ;; - esac - - [ -z "$CNS3XXX_BOARD_NAME" ] && CNS3XXX_BOARD_NAME="$name" - [ -z "$CNS3XXX_MODEL" ] && CNS3XXX_MODEL="$machine" - - [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" - - echo "$CNS3XXX_BOARD_NAME" > /tmp/sysinfo/board_name - echo "$CNS3XXX_MODEL" > /tmp/sysinfo/model -} diff --git a/target/linux/cns3xxx/base-files/lib/preinit/01_sysinfo b/target/linux/cns3xxx/base-files/lib/preinit/01_sysinfo deleted file mode 100644 index 155fee42e0..0000000000 --- a/target/linux/cns3xxx/base-files/lib/preinit/01_sysinfo +++ /dev/null @@ -1,7 +0,0 @@ -do_sysinfo_cns3xxx() { - . /lib/cns3xxx.sh - - cns3xxx_board_detect -} - -boot_hook_add preinit_main do_sysinfo_cns3xxx diff --git a/target/linux/cns3xxx/base-files/lib/upgrade/platform.sh b/target/linux/cns3xxx/base-files/lib/upgrade/platform.sh deleted file mode 100644 index 58dd6d7590..0000000000 --- a/target/linux/cns3xxx/base-files/lib/upgrade/platform.sh +++ /dev/null @@ -1,19 +0,0 @@ -PART_NAME=firmware - -CI_BLKSZ=65536 - -platform_check_image() { - local magic="$(get_magic_long "$1")" - - [ "$#" -gt 1 ] && return 1 - - [ "$magic" != "27051956" ] && { - echo "Invalid image type." - return 1 - } - return 0 -} - -platform_do_upgrade() { - default_do_upgrade "$1" -} diff --git a/target/linux/cns3xxx/config-4.19 b/target/linux/cns3xxx/config-4.19 deleted file mode 100644 index 9b9aea461b..0000000000 --- a/target/linux/cns3xxx/config-4.19 +++ /dev/null @@ -1,368 +0,0 @@ -# CONFIG_AIO is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_CNS3XXX=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_KCOV=y -CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_ARCH_HAS_PHYS_TO_DMA=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ATA=y -CONFIG_ATAGS=y -# CONFIG_ATA_SFF is not set -CONFIG_ATA_VERBOSE_ERROR=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BCM_NET_PHYLIB=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BROADCOM_PHY=y -CONFIG_CACHE_L2X0=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="console=ttyS0,115200" -CONFIG_CMDLINE_FORCE=y -CONFIG_CNS3XXX_ETH=y -CONFIG_COMMON_CLK=y -CONFIG_COREDUMP=y -CONFIG_CPU_32v6=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_ABRT_EV6=y -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V6=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_PABRT_V6=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V6=y -CONFIG_CPU_V6K=y -CONFIG_CRASH_DUMP=y -CONFIG_CRC_CCITT=m -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEBUG_USER is not set -CONFIG_DMA_CACHE_FIQ_BROADCAST=y -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -CONFIG_ELF_CORE=y -CONFIG_FIQ=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GLOB=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARM_SCU=y -CONFIG_HAVE_ARM_TWD=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_SMP=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HWMON=y -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_CNS3XXX=y -# CONFIG_INITRAMFS_FORCE is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IPV6=y -CONFIG_IPV6_MROUTE=y -CONFIG_IPV6_MULTIPLE_TABLES=y -# CONFIG_IPV6_PIMSM_V2 is not set -CONFIG_IPV6_SUBTREES=y -CONFIG_IP_MROUTE_COMMON=y -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_UNCOMPRESSED=y -CONFIG_LEDS_GPIO=y -# CONFIG_LEDS_TRIGGER_NETDEV is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -# CONFIG_MACH_CNS3420VB is not set -CONFIG_MACH_GW2388=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGHT_HAVE_PCI=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_CNS3XXX=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -# CONFIG_MMC_TIFM_SD is not set -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MPCORE_WATCHDOG=y -CONFIG_MTD_M25P80=y -# CONFIG_MTD_OF_PARTS is not set -CONFIG_MTD_PHYSMAP=y -# CONFIG_MTD_PHYSMAP_OF is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_ADVANCED=y -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_MARK=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_NAT=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_TARGET_REDIRECT=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_RTCACHE=m -CONFIG_NF_DEFRAG_IPV4=m -CONFIG_NF_DEFRAG_IPV6=m -CONFIG_NF_LOG_COMMON=m -CONFIG_NF_LOG_IPV4=m -CONFIG_NF_LOG_IPV6=m -CONFIG_NF_NAT=m -CONFIG_NF_NAT_IPV4=m -CONFIG_NF_NAT_NEEDED=y -CONFIG_NF_NAT_REDIRECT=y -CONFIG_NF_REJECT_IPV4=m -CONFIG_NF_REJECT_IPV6=m -CONFIG_NLS=y -CONFIG_NO_BOOTMEM=y -CONFIG_NR_CPUS=2 -CONFIG_NTP_PPS=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -# CONFIG_PCI_V3_SEMI is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PL310_ERRATA_588369=y -CONFIG_PL310_ERRATA_727915=y -CONFIG_PL310_ERRATA_753970=y -CONFIG_PL310_ERRATA_769419=y -CONFIG_PPP=m -CONFIG_PPPOE=m -CONFIG_PPP_ASYNC=m -CONFIG_PPS=y -CONFIG_PPS_CLIENT_GPIO=y -CONFIG_PRINTK_TIME=y -CONFIG_PROC_VMCORE=y -CONFIG_RAID_ATTRS=y -CONFIG_RATIONAL=y -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_REFCOUNT_FULL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_SPI=y -CONFIG_RELAY=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1672=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_SCSI=y -CONFIG_SENSORS_AD7418=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SG_POOL=y -CONFIG_SLHC=m -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_CNS3XXX=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRCU=y -# CONFIG_STAGING is not set -CONFIG_SWPHY=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_CNS3XXX_EHCI=y -CONFIG_USB_CNS3XXX_OHCI=y -CONFIG_USB_COMMON=y -CONFIG_USB_DWC2=y -CONFIG_USB_DWC2_HOST=y -# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_GADGET=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -# CONFIG_USB_ROLE_SWITCH is not set -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_XPS=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S deleted file mode 100644 index b1155ef570..0000000000 --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2012 Gateworks Corporation - * Chris Lang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include - -#define D_CACHE_LINE_SIZE 32 - - .text - -/* - * R8 - DMA Start Address - * R9 - DMA Length - * R10 - DMA Direction - * R11 - DMA type - * R12 - fiq_buffer Address -*/ - - .global cns3xxx_fiq_end -ENTRY(cns3xxx_fiq_start) - str r8, [r13] - - ldmia r12, {r8, r9, r10} - and r11, r10, #0x3000000 - and r10, r10, #0xff - - teq r11, #0x1000000 - beq cns3xxx_dma_map_area - teq r11, #0x2000000 - beq cns3xxx_dma_unmap_area - /* fall through */ -cns3xxx_dma_flush_range: - bic r8, r8, #D_CACHE_LINE_SIZE - 1 -1: - mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line - add r8, r8, #D_CACHE_LINE_SIZE - cmp r8, r9 - blo 1b - /* fall through */ -cns3xxx_fiq_exit: - mov r8, #0 - str r8, [r12, #8] - mcr p15, 0, r8, c7, c10, 4 @ drain write buffer - subs pc, lr, #4 - -cns3xxx_dma_map_area: - add r9, r9, r8 - teq r10, #DMA_FROM_DEVICE - beq cns3xxx_dma_inv_range - teq r10, #DMA_TO_DEVICE - bne cns3xxx_dma_flush_range - /* fall through */ -cns3xxx_dma_clean_range: - bic r8, r8, #D_CACHE_LINE_SIZE - 1 -1: - mcr p15, 0, r8, c7, c10, 1 @ clean D line - add r8, r8, #D_CACHE_LINE_SIZE - cmp r8, r9 - blo 1b - b cns3xxx_fiq_exit - -cns3xxx_dma_unmap_area: - add r9, r9, r8 - teq r10, #DMA_TO_DEVICE - beq cns3xxx_fiq_exit - /* fall through */ -cns3xxx_dma_inv_range: - tst r8, #D_CACHE_LINE_SIZE - 1 - bic r8, r8, #D_CACHE_LINE_SIZE - 1 - mcrne p15, 0, r8, c7, c10, 1 @ clean D line - tst r9, #D_CACHE_LINE_SIZE - 1 - bic r9, r9, #D_CACHE_LINE_SIZE - 1 - mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line -1: - mcr p15, 0, r8, c7, c6, 1 @ invalidate D line - add r8, r8, #D_CACHE_LINE_SIZE - cmp r8, r9 - blo 1b - b cns3xxx_fiq_exit - -cns3xxx_fiq_end: diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c deleted file mode 100644 index bdf930a79e..0000000000 --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright 2012 Gateworks Corporation - * Chris Lang - * Tim Harvey - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* - * Registers - */ -#define GPIO_INPUT 0x04 -#define GPIO_DIR 0x08 -#define GPIO_SET 0x10 -#define GPIO_CLEAR 0x14 -#define GPIO_INTERRUPT_ENABLE 0x20 -#define GPIO_INTERRUPT_RAW_STATUS 0x24 -#define GPIO_INTERRUPT_MASKED_STATUS 0x28 -#define GPIO_INTERRUPT_MASK 0x2C -#define GPIO_INTERRUPT_CLEAR 0x30 -#define GPIO_INTERRUPT_TRIGGER_METHOD 0x34 -#define GPIO_INTERRUPT_TRIGGER_BOTH_EDGES 0x38 -#define GPIO_INTERRUPT_TRIGGER_TYPE 0x3C - -#define GPIO_INTERRUPT_TRIGGER_METHOD_EDGE 0 -#define GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL 1 -#define GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE 0 -#define GPIO_INTERRUPT_TRIGGER_EDGE_BOTH 1 -#define GPIO_INTERRUPT_TRIGGER_TYPE_RISING 0 -#define GPIO_INTERRUPT_TRIGGER_TYPE_FALLING 1 -#define GPIO_INTERRUPT_TRIGGER_TYPE_HIGH 0 -#define GPIO_INTERRUPT_TRIGGER_TYPE_LOW 1 - -struct cns3xxx_gpio_chip { - struct gpio_chip chip; - struct irq_domain *domain; - spinlock_t lock; - void __iomem *base; -}; - -static struct cns3xxx_gpio_chip cns3xxx_gpio_chips[2]; -static int cns3xxx_gpio_chip_count; - -static inline void -__set_direction(struct cns3xxx_gpio_chip *cchip, unsigned pin, int input) -{ - u32 reg; - - reg = __raw_readl(cchip->base + GPIO_DIR); - if (input) - reg &= ~(1 << pin); - else - reg |= (1 << pin); - __raw_writel(reg, cchip->base + GPIO_DIR); -} - -/* - * GENERIC_GPIO primatives - */ -static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned pin) -{ - struct cns3xxx_gpio_chip *cchip = - container_of(chip, struct cns3xxx_gpio_chip, chip); - unsigned long flags; - - spin_lock_irqsave(&cchip->lock, flags); - __set_direction(cchip, pin, 1); - spin_unlock_irqrestore(&cchip->lock, flags); - - return 0; -} - -static int cns3xxx_gpio_get(struct gpio_chip *chip, unsigned pin) -{ - struct cns3xxx_gpio_chip *cchip = - container_of(chip, struct cns3xxx_gpio_chip, chip); - int val; - - val = ((__raw_readl(cchip->base + GPIO_INPUT) >> pin) & 0x1); - - return val; -} - -static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int level) -{ - struct cns3xxx_gpio_chip *cchip = - container_of(chip, struct cns3xxx_gpio_chip, chip); - unsigned long flags; - - spin_lock_irqsave(&cchip->lock, flags); - if (level) - __raw_writel(1 << pin, cchip->base + GPIO_SET); - else - __raw_writel(1 << pin, cchip->base + GPIO_CLEAR); - __set_direction(cchip, pin, 0); - spin_unlock_irqrestore(&cchip->lock, flags); - - return 0; -} - -static void cns3xxx_gpio_set(struct gpio_chip *chip, unsigned pin, - int level) -{ - struct cns3xxx_gpio_chip *cchip = - container_of(chip, struct cns3xxx_gpio_chip, chip); - - if (level) - __raw_writel(1 << pin, cchip->base + GPIO_SET); - else - __raw_writel(1 << pin, cchip->base + GPIO_CLEAR); -} - -static int cns3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned pin) -{ - struct cns3xxx_gpio_chip *cchip = - container_of(chip, struct cns3xxx_gpio_chip, chip); - - return irq_find_mapping(cchip->domain, pin); -} - - -/* - * IRQ support - */ - -/* one interrupt per GPIO controller (GPIOA/GPIOB) - * this is called in task context, with IRQs enabled - */ -static void cns3xxx_gpio_irq_handler(struct irq_desc *desc) -{ - struct cns3xxx_gpio_chip *cchip = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - u16 i; - u32 reg; - - chained_irq_enter(chip, desc); /* mask and ack the base interrupt */ - - /* see which pin(s) triggered the interrupt */ - reg = __raw_readl(cchip->base + GPIO_INTERRUPT_RAW_STATUS); - for (i = 0; i < 32; i++) { - if (reg & (1 << i)) { - /* let the generic IRQ layer handle an interrupt */ - generic_handle_irq(irq_find_mapping(cchip->domain, i)); - } - } - - chained_irq_exit(chip, desc); /* unmask the base interrupt */ -} - -static int cns3xxx_gpio_irq_set_type(struct irq_data *d, u32 irqtype) -{ - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - struct cns3xxx_gpio_chip *cchip = gc->private; - u32 gpio = d->hwirq; - unsigned long flags; - u32 method, edges, type; - - spin_lock_irqsave(&cchip->lock, flags); - method = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD); - edges = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES); - type = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE); - method &= ~(1 << gpio); - edges &= ~(1 << gpio); - type &= ~(1 << gpio); - - switch(irqtype) { - case IRQ_TYPE_EDGE_RISING: - method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio); - edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio); - type |= (GPIO_INTERRUPT_TRIGGER_TYPE_RISING << gpio); - break; - case IRQ_TYPE_EDGE_FALLING: - method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio); - edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio); - type |= (GPIO_INTERRUPT_TRIGGER_TYPE_FALLING << gpio); - break; - case IRQ_TYPE_EDGE_BOTH: - method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio); - edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_BOTH << gpio); - break; - case IRQ_TYPE_LEVEL_LOW: - method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio); - type |= (GPIO_INTERRUPT_TRIGGER_TYPE_LOW << gpio); - break; - case IRQ_TYPE_LEVEL_HIGH: - method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio); - type |= (GPIO_INTERRUPT_TRIGGER_TYPE_HIGH << gpio); - break; - default: - printk(KERN_WARNING "No irq type\n"); - spin_unlock_irqrestore(&cchip->lock, flags); - return -EINVAL; - } - - __raw_writel(method, cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD); - __raw_writel(edges, cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES); - __raw_writel(type, cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE); - spin_unlock_irqrestore(&cchip->lock, flags); - - if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) - irq_set_handler_locked(d, handle_level_irq); - else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) - irq_set_handler_locked(d, handle_edge_irq); - - return 0; -} - -void __init cns3xxx_gpio_init(int gpio_base, int ngpio, - u32 base, int irq, int secondary_irq_base) -{ - struct cns3xxx_gpio_chip *cchip; - struct irq_chip_generic *gc; - struct irq_chip_type *ct; - char gc_label[16]; - int irq_base; - - if (cns3xxx_gpio_chip_count == ARRAY_SIZE(cns3xxx_gpio_chips)) - return; - - snprintf(gc_label, sizeof(gc_label), "cns3xxx_gpio%d", - cns3xxx_gpio_chip_count); - - cchip = cns3xxx_gpio_chips + cns3xxx_gpio_chip_count; - cchip->chip.label = kstrdup(gc_label, GFP_KERNEL); - cchip->chip.direction_input = cns3xxx_gpio_direction_input; - cchip->chip.get = cns3xxx_gpio_get; - cchip->chip.direction_output = cns3xxx_gpio_direction_output; - cchip->chip.set = cns3xxx_gpio_set; - cchip->chip.to_irq = cns3xxx_gpio_to_irq; - cchip->chip.base = gpio_base; - cchip->chip.ngpio = ngpio; - cchip->chip.can_sleep = 0; - spin_lock_init(&cchip->lock); - cchip->base = (void __iomem *)base; - - BUG_ON(gpiochip_add(&cchip->chip) < 0); - cns3xxx_gpio_chip_count++; - - /* clear GPIO interrupts */ - __raw_writel(0xffff, cchip->base + GPIO_INTERRUPT_CLEAR); - - irq_base = irq_alloc_descs(-1, secondary_irq_base, ngpio, - numa_node_id()); - if (irq_base < 0) - goto out_irqdesc_free; - - cchip->domain = irq_domain_add_legacy(NULL, ngpio, irq_base, 0, - &irq_domain_simple_ops, NULL); - if (!cchip->domain) - goto out_irqdesc_free; - - /* - * IRQ chip init - */ - gc = irq_alloc_generic_chip("cns3xxx_gpio_irq", 1, irq_base, - cchip->base, handle_edge_irq); - - gc->private = cchip; - - ct = gc->chip_types; - ct->type = IRQ_TYPE_EDGE_FALLING; - ct->regs.ack = GPIO_INTERRUPT_CLEAR; - ct->chip.irq_ack = irq_gc_ack_set_bit; - ct->regs.mask = GPIO_INTERRUPT_ENABLE; - ct->chip.irq_enable = irq_gc_mask_set_bit; - ct->chip.irq_disable = irq_gc_mask_clr_bit; - ct->chip.irq_set_type = cns3xxx_gpio_irq_set_type; - ct->handler = handle_edge_irq; - - irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, - IRQ_NOREQUEST, 0); - irq_set_chained_handler(irq, cns3xxx_gpio_irq_handler); - irq_set_handler_data(irq, cchip); - - return; - -out_irqdesc_free: - irq_free_descs(irq_base, ngpio); -} diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S deleted file mode 100644 index f0da8ec0a5..0000000000 --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S +++ /dev/null @@ -1,41 +0,0 @@ -/* - * linux/arch/arm/mach-cns3xxx/headsmp.S - * - * Cloned from linux/arch/arm/plat-versatile/headsmp.S - * - * Copyright (c) 2003 ARM Limited - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include - -/* - * CNS3XXX specific entry point for secondary CPUs. This provides - * a "holding pen" into which all secondary cores are held until we're - * ready for them to initialise. - */ -ENTRY(cns3xxx_secondary_startup) - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 -pen: ldr r7, [r6] - cmp r7, r0 - bne pen - - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup -ENDPROC(cns3xxx_secondary_startup) - - .align 2 -1: .long . - .long pen_release diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/hotplug.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/hotplug.c deleted file mode 100644 index be0d499a38..0000000000 --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/hotplug.c +++ /dev/null @@ -1,130 +0,0 @@ -/* linux arch/arm/mach-cns3xxx/hotplug.c - * - * Cloned from linux/arch/arm/mach-realview/hotplug.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include - -#include - -extern volatile int pen_release; - -static inline void cpu_enter_lowpower(void) -{ - unsigned int v; - - flush_cache_all(); - asm volatile( - " mcr p15, 0, %1, c7, c5, 0\n" - " mcr p15, 0, %1, c7, c10, 4\n" - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, %3\n" - " mcr p15, 0, %0, c1, c0, 1\n" - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "r" (0), "Ir" (CR_C), "Ir" (0x40) - : "cc"); -} - -static inline void cpu_leave_lowpower(void) -{ - unsigned int v; - - asm volatile( - "mrc p15, 0, %0, c1, c0, 0\n" - " orr %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - " mrc p15, 0, %0, c1, c0, 1\n" - " orr %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (CR_C), "Ir" (0x40) - : "cc"); -} - -static inline void platform_do_lowpower(unsigned int cpu, int *spurious) -{ - /* - * there is no power-control hardware on this platform, so all - * we can do is put the core into WFI; this is safe as the calling - * code will have already disabled interrupts - */ - for (;;) { - /* - * here's the WFI - */ - asm(".word 0xe320f003\n" - : - : - : "memory", "cc"); - - if (pen_release == cpu) { - /* - * OK, proper wakeup, we're done - */ - break; - } - - /* - * Getting here, means that we have come out of WFI without - * having been woken up - this shouldn't happen - * - * Just note it happening - when we're woken, we can report - * its occurrence. - */ - (*spurious)++; - } -} - -int platform_cpu_kill(unsigned int cpu) -{ - return 1; -} - -/* - * platform-specific code to shutdown a CPU - * - * Called with IRQs disabled - */ -void platform_cpu_die(unsigned int cpu) -{ - int spurious = 0; - - /* - * we're ready for shutdown now, so do it - */ - cpu_enter_lowpower(); - platform_do_lowpower(cpu, &spurious); - - /* - * bring this CPU back into the world of cache - * coherency, and then restore interrupts - */ - cpu_leave_lowpower(); - - if (spurious) - pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); -} - -int platform_cpu_disable(unsigned int cpu) -{ - /* - * we don't allow CPU 0 to be shutdown (it is still too special - * e.g. clock tick interrupts) - */ - return cpu == 0 ? -EPERM : 0; -} diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/gpio.h b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/gpio.h deleted file mode 100644 index 8c66748ac9..0000000000 --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/gpio.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * arch/arm/mach-cns3xxx/include/mach/gpio.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - */ -#ifndef __ASM_ARCH_CNS3XXX_GPIO_H -#define __ASM_ARCH_CNS3XXX_GPIO_H - -#include - -extern void __init cns3xxx_gpio_init(int gpio_base, int ngpio, - u32 base, int irq, int secondary_irq_base); - -#endif diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/smp.h b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/smp.h deleted file mode 100644 index e5bc56823e..0000000000 --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/smp.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __MACH_SMP_H -#define __MACH_SMP_H - -extern void smp_dma_map_area(const void *, size_t, int); -extern void smp_dma_unmap_area(const void *, size_t, int); -extern void smp_dma_flush_range(const void *, const void *); - -#endif diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c deleted file mode 100644 index bee7348266..0000000000 --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c +++ /dev/null @@ -1,1123 +0,0 @@ -/* - * Gateworks Corporation Laguna Platform - * - * Copyright 2000 Deep Blue Solutions Ltd - * Copyright 2008 ARM Limited - * Copyright 2008 Cavium Networks - * Scott Shu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - * Copyright 2011 Gateworks Corporation - * Chris Lang - * Copyright 2012-2013 Gateworks Corporation - * Tim Harvey - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "core.h" -#include "devices.h" -#include "cns3xxx.h" -#include "pm.h" - -#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) - -// Config 1 Bitmap -#define ETH0_LOAD BIT(0) -#define ETH1_LOAD BIT(1) -#define ETH2_LOAD BIT(2) -#define SATA0_LOAD BIT(3) -#define SATA1_LOAD BIT(4) -#define PCM_LOAD BIT(5) -#define I2S_LOAD BIT(6) -#define SPI0_LOAD BIT(7) -#define SPI1_LOAD BIT(8) -#define PCIE0_LOAD BIT(9) -#define PCIE1_LOAD BIT(10) -#define USB0_LOAD BIT(11) -#define USB1_LOAD BIT(12) -#define USB1_ROUTE BIT(13) -#define SD_LOAD BIT(14) -#define UART0_LOAD BIT(15) -#define UART1_LOAD BIT(16) -#define UART2_LOAD BIT(17) -#define MPCI0_LOAD BIT(18) -#define MPCI1_LOAD BIT(19) -#define MPCI2_LOAD BIT(20) -#define MPCI3_LOAD BIT(21) -#define FP_BUT_LOAD BIT(22) -#define FP_BUT_HEADER_LOAD BIT(23) -#define FP_LED_LOAD BIT(24) -#define FP_LED_HEADER_LOAD BIT(25) -#define FP_TAMPER_LOAD BIT(26) -#define HEADER_33V_LOAD BIT(27) -#define SATA_POWER_LOAD BIT(28) -#define FP_POWER_LOAD BIT(29) -#define GPIO_HEADER_LOAD BIT(30) -#define GSP_BAT_LOAD BIT(31) - -// Config 2 Bitmap -#define FAN_LOAD BIT(0) -#define SPI_FLASH_LOAD BIT(1) -#define NOR_FLASH_LOAD BIT(2) -#define GPS_LOAD BIT(3) -#define SUPPLY_5V_LOAD BIT(6) -#define SUPPLY_33V_LOAD BIT(7) - -struct laguna_board_info { - char model[16]; - u32 config_bitmap; - u32 config2_bitmap; - u8 nor_flash_size; - u8 spi_flash_size; -}; - -static struct laguna_board_info laguna_info __initdata; - -/* - * NOR Flash - */ -static struct mtd_partition laguna_nor_partitions[] = { - { - .name = "uboot", - .offset = 0, - .size = SZ_256K, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - }, { - .name = "firmware", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct physmap_flash_data laguna_nor_pdata = { - .width = 2, - .parts = laguna_nor_partitions, - .nr_parts = ARRAY_SIZE(laguna_nor_partitions), -}; - -static struct resource laguna_nor_res = { - .start = CNS3XXX_FLASH_BASE, - .end = CNS3XXX_FLASH_BASE + SZ_128M - 1, - .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, -}; - -static struct platform_device laguna_nor_pdev = { - .name = "physmap-flash", - .id = 0, - .resource = &laguna_nor_res, - .num_resources = 1, - .dev = { - .platform_data = &laguna_nor_pdata, - }, -}; - -/* - * SPI - */ -static struct mtd_partition laguna_spi_partitions[] = { - { - .name = "uboot", - .offset = 0, - .size = SZ_256K, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_256K, - }, { - .name = "firmware", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct flash_platform_data laguna_spi_pdata = { - .parts = laguna_spi_partitions, - .nr_parts = ARRAY_SIZE(laguna_spi_partitions), -}; - -static struct spi_board_info __initdata laguna_spi_devices[] = { - { - .modalias = "m25p80", - .platform_data = &laguna_spi_pdata, - .max_speed_hz = 50000000, - .bus_num = 1, - .chip_select = 0, - }, -}; - -static struct resource laguna_spi_resource = { - .start = CNS3XXX_SSP_BASE + 0x40, - .end = CNS3XXX_SSP_BASE + 0x6f, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device laguna_spi_controller = { - .name = "cns3xxx_spi", - .resource = &laguna_spi_resource, - .num_resources = 1, -}; - -/* - * LED's - */ -static struct gpio_led laguna_gpio_leds[] = { - { - .name = "user1", /* Green Led */ - .gpio = 115, - .active_low = 1, - },{ - .name = "user2", /* Red Led */ - .gpio = 114, - .active_low = 1, - },{ - .name = "pwr1", /* Green Led */ - .gpio = 116, - .active_low = 1, - },{ - .name = "pwr2", /* Yellow Led */ - .gpio = 117, - .active_low = 1, - },{ - .name = "txd1", /* Green Led */ - .gpio = 118, - .active_low = 1, - },{ - .name = "txd2", /* Yellow Led */ - .gpio = 119, - .active_low = 1, - },{ - .name = "rxd1", /* Green Led */ - .gpio = 120, - .active_low = 1, - },{ - .name = "rxd2", /* Yellow Led */ - .gpio = 121, - .active_low = 1, - },{ - .name = "ser1", /* Green Led */ - .gpio = 122, - .active_low = 1, - },{ - .name = "ser2", /* Yellow Led */ - .gpio = 123, - .active_low = 1, - },{ - .name = "enet1", /* Green Led */ - .gpio = 124, - .active_low = 1, - },{ - .name = "enet2", /* Yellow Led */ - .gpio = 125, - .active_low = 1, - },{ - .name = "sig1_1", /* Green Led */ - .gpio = 126, - .active_low = 1, - },{ - .name = "sig1_2", /* Yellow Led */ - .gpio = 127, - .active_low = 1, - },{ - .name = "sig2_1", /* Green Led */ - .gpio = 128, - .active_low = 1, - },{ - .name = "sig2_2", /* Yellow Led */ - .gpio = 129, - .active_low = 1, - },{ - .name = "sig3_1", /* Green Led */ - .gpio = 130, - .active_low = 1, - },{ - .name = "sig3_2", /* Yellow Led */ - .gpio = 131, - .active_low = 1, - },{ - .name = "net1", /*Green Led */ - .gpio = 109, - .active_low = 1, - },{ - .name = "net2", /* Red Led */ - .gpio = 110, - .active_low = 1, - },{ - .name = "mod1", /* Green Led */ - .gpio = 111, - .active_low = 1, - },{ - .name = "mod2", /* Red Led */ - .gpio = 112, - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data laguna_gpio_leds_data = { - .num_leds = 22, - .leds = laguna_gpio_leds, -}; - -static struct platform_device laguna_gpio_leds_device = { - .name = "leds-gpio", - .id = PLATFORM_DEVID_NONE, - .dev.platform_data = &laguna_gpio_leds_data, -}; - -/* - * Ethernet - */ -static struct cns3xxx_plat_info laguna_net_data = { - .ports = 0, - .phy = { - 0, - 1, - 2, - }, -}; - -static struct resource laguna_net_resource[] = { - { - .name = "eth0_mem", - .start = CNS3XXX_SWITCH_BASE, - .end = CNS3XXX_SWITCH_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM - }, { - .name = "eth_rx", - .start = IRQ_CNS3XXX_SW_R0RXC, - .end = IRQ_CNS3XXX_SW_R0RXC, - .flags = IORESOURCE_IRQ - }, { - .name = "eth_stat", - .start = IRQ_CNS3XXX_SW_STATUS, - .end = IRQ_CNS3XXX_SW_STATUS, - .flags = IORESOURCE_IRQ - } -}; - -static u64 laguna_net_dmamask = DMA_BIT_MASK(32); -static struct platform_device laguna_net_device = { - .name = "cns3xxx_eth", - .id = 0, - .resource = laguna_net_resource, - .num_resources = ARRAY_SIZE(laguna_net_resource), - .dev = { - .dma_mask = &laguna_net_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &laguna_net_data, - } -}; - -/* - * UART - */ -static void __init laguna_early_serial_setup(void) -{ -#ifdef CONFIG_SERIAL_8250_CONSOLE - static struct uart_port laguna_serial_port = { - .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT, - .mapbase = CNS3XXX_UART0_BASE, - .irq = IRQ_CNS3XXX_UART0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, - .regshift = 2, - .uartclk = 24000000, - .line = 0, - .type = PORT_16550A, - .fifosize = 16, - }; - - early_serial_setup(&laguna_serial_port); -#endif -} - -static struct resource laguna_uart_resources[] = { - { - .start = CNS3XXX_UART0_BASE, - .end = CNS3XXX_UART0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM - },{ - .start = CNS3XXX_UART1_BASE, - .end = CNS3XXX_UART1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM - },{ - .start = CNS3XXX_UART2_BASE, - .end = CNS3XXX_UART2_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM - }, -}; - -static struct plat_serial8250_port laguna_uart_data[] = { - { - .mapbase = (CNS3XXX_UART0_BASE), - .irq = IRQ_CNS3XXX_UART0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_IOREMAP, - .regshift = 2, - .uartclk = 24000000, - .type = PORT_16550A, - },{ - .mapbase = (CNS3XXX_UART1_BASE), - .irq = IRQ_CNS3XXX_UART1, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_IOREMAP, - .regshift = 2, - .uartclk = 24000000, - .type = PORT_16550A, - },{ - .mapbase = (CNS3XXX_UART2_BASE), - .irq = IRQ_CNS3XXX_UART2, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_IOREMAP, - .regshift = 2, - .uartclk = 24000000, - .type = PORT_16550A, - }, - { }, -}; - -static struct platform_device laguna_uart = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = laguna_uart_data, - .num_resources = 3, - .resource = laguna_uart_resources -}; - -/* - * USB - */ -static struct resource cns3xxx_usb_ehci_resources[] = { - [0] = { - .start = CNS3XXX_USB_BASE, - .end = CNS3XXX_USB_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_USB_EHCI, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32); - -static int csn3xxx_usb_power_on(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - * - * Set USB AHB INCR length to 16 - */ - if (atomic_inc_return(&usb_pwr_ref) == 1) { - cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); - cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); - cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); - __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), - MISC_CHIP_CONFIG_REG); - } - - return 0; -} - -static void csn3xxx_usb_power_off(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - */ - if (atomic_dec_return(&usb_pwr_ref) == 0) - cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); -} - -static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static struct platform_device cns3xxx_usb_ehci_device = { - .name = "ehci-platform", - .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources), - .resource = cns3xxx_usb_ehci_resources, - .dev = { - .dma_mask = &cns3xxx_usb_ehci_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &cns3xxx_usb_ehci_pdata, - }, -}; - -static struct resource cns3xxx_usb_ohci_resources[] = { - [0] = { - .start = CNS3XXX_USB_OHCI_BASE, - .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_USB_OHCI, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32); - -static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { - .num_ports = 1, - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static struct platform_device cns3xxx_usb_ohci_device = { - .name = "ohci-platform", - .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources), - .resource = cns3xxx_usb_ohci_resources, - .dev = { - .dma_mask = &cns3xxx_usb_ohci_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &cns3xxx_usb_ohci_pdata, - }, -}; - -static struct resource cns3xxx_usb_otg_resources[] = { - [0] = { - .start = CNS3XXX_USBOTG_BASE, - .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_USB_OTG, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device cns3xxx_usb_otg_device = { - .name = "dwc2", - .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources), - .resource = cns3xxx_usb_otg_resources, - .dev = { - .dma_mask = &cns3xxx_usb_otg_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -/* - * I2C - */ -static struct resource laguna_i2c_resource[] = { - { - .start = CNS3XXX_SSP_BASE + 0x20, - .end = CNS3XXX_SSP_BASE + 0x3f, - .flags = IORESOURCE_MEM, - },{ - .start = IRQ_CNS3XXX_I2C, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device laguna_i2c_controller = { - .name = "cns3xxx-i2c", - .num_resources = 2, - .resource = laguna_i2c_resource, -}; - -static struct nvmem_device *at24_nvmem; - -static void at24_setup(struct nvmem_device *mem_acc, void *context) -{ - char buf[16]; - - at24_nvmem = mem_acc; - - /* Read MAC addresses */ - if (nvmem_device_read(at24_nvmem, 0x100, 6, buf) == 6) - memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN); - if (nvmem_device_read(at24_nvmem, 0x106, 6, buf) == 6) - memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN); - if (nvmem_device_read(at24_nvmem, 0x10C, 6, buf) == 6) - memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN); - if (nvmem_device_read(at24_nvmem, 0x112, 6, buf) == 6) - memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN); - - /* Read out Model Information */ - if (nvmem_device_read(at24_nvmem, 0x130, 16, buf) == 16) - memcpy(&laguna_info.model, buf, 16); - if (nvmem_device_read(at24_nvmem, 0x140, 1, buf) == 1) - memcpy(&laguna_info.nor_flash_size, buf, 1); - if (nvmem_device_read(at24_nvmem, 0x141, 1, buf) == 1) - memcpy(&laguna_info.spi_flash_size, buf, 1); - if (nvmem_device_read(at24_nvmem, 0x142, 4, buf) == 4) - memcpy(&laguna_info.config_bitmap, buf, 4); - if (nvmem_device_read(at24_nvmem, 0x146, 4, buf) == 4) - memcpy(&laguna_info.config2_bitmap, buf, 4); -}; - -static struct at24_platform_data laguna_eeprom_info = { - .byte_len = 1024, - .page_size = 16, - .flags = AT24_FLAG_READONLY, - .setup = at24_setup, -}; - -static struct pca953x_platform_data laguna_pca_data = { - .gpio_base = 100, - .irq_base = -1, -}; - -static struct pca953x_platform_data laguna_pca2_data = { - .gpio_base = 116, - .irq_base = -1, -}; - -static struct i2c_board_info __initdata laguna_i2c_devices[] = { - { - I2C_BOARD_INFO("pca9555", 0x23), - .platform_data = &laguna_pca_data, - },{ - I2C_BOARD_INFO("pca9555", 0x27), - .platform_data = &laguna_pca2_data, - },{ - I2C_BOARD_INFO("gsp", 0x29), - },{ - I2C_BOARD_INFO ("24c08",0x50), - .platform_data = &laguna_eeprom_info, - },{ - I2C_BOARD_INFO("ds1672", 0x68), - }, -}; - -/* - * Watchdog - */ - -static struct resource laguna_watchdog_resources[] = { - [0] = { - .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog - .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device laguna_watchdog = { - .name = "mpcore_wdt", - .id = PLATFORM_DEVID_NONE, - .num_resources = ARRAY_SIZE(laguna_watchdog_resources), - .resource = laguna_watchdog_resources, -}; - -/* - * GPS PPS - */ -static struct pps_gpio_platform_data laguna_pps_data = { - .gpio_pin = 0, - .gpio_label = "GPS_PPS", - .assert_falling_edge = 0, - .capture_clear = 0, -}; - -static struct platform_device laguna_pps_device = { - .name = "pps-gpio", - .id = PLATFORM_DEVID_NONE, - .dev.platform_data = &laguna_pps_data, -}; - -/* - * GPIO - */ - -static struct gpio laguna_gpio_gw2391[] = { - { 0, GPIOF_IN , "*GPS_PPS" }, - { 1, GPIOF_IN , "*GSC_IRQ#" }, - { 2, GPIOF_IN , "*USB_FAULT#" }, - { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" }, - { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" }, - { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" }, - { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" }, - { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" }, - { 100, GPIOF_IN , "*USER_PB#" }, - { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" }, - { 108, GPIOF_IN , "DIO0" }, - { 109, GPIOF_IN , "DIO1" }, - { 110, GPIOF_IN , "DIO2" }, - { 111, GPIOF_IN , "DIO3" }, - { 112, GPIOF_IN , "DIO4" }, -}; - -static struct gpio laguna_gpio_gw2388[] = { - { 0, GPIOF_IN , "*GPS_PPS" }, - { 1, GPIOF_IN , "*GSC_IRQ#" }, - { 3, GPIOF_IN , "*USB_FAULT#" }, - { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" }, - { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, - { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, - { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" }, - { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" }, - { 108, GPIOF_IN , "DIO0" }, - { 109, GPIOF_IN , "DIO1" }, - { 110, GPIOF_IN , "DIO2" }, - { 111, GPIOF_IN , "DIO3" }, - { 112, GPIOF_IN , "DIO4" }, -}; - -static struct gpio laguna_gpio_gw2387[] = { - { 0, GPIOF_IN , "*GPS_PPS" }, - { 1, GPIOF_IN , "*GSC_IRQ#" }, - { 2, GPIOF_IN , "*USB_FAULT#" }, - { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" }, - { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" }, - { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, - { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, - { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" }, - { 100, GPIOF_IN , "*USER_PB#" }, - { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" }, - { 108, GPIOF_IN , "DIO0" }, - { 109, GPIOF_IN , "DIO1" }, - { 110, GPIOF_IN , "DIO2" }, - { 111, GPIOF_IN , "DIO3" }, - { 112, GPIOF_IN , "DIO4" }, - { 113, GPIOF_IN , "DIO5" }, -}; - -static struct gpio laguna_gpio_gw2386[] = { - { 0, GPIOF_IN , "*GPS_PPS" }, - { 2, GPIOF_IN , "*USB_FAULT#" }, - { 6, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" }, - { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, - { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, - { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" }, - { 108, GPIOF_IN , "DIO0" }, - { 109, GPIOF_IN , "DIO1" }, - { 110, GPIOF_IN , "DIO2" }, - { 111, GPIOF_IN , "DIO3" }, - { 112, GPIOF_IN , "DIO4" }, - { 113, GPIOF_IN , "DIO5" }, -}; - -static struct gpio laguna_gpio_gw2385[] = { - { 0, GPIOF_IN , "*GSC_IRQ#" }, - { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" }, - { 2, GPIOF_IN , "*USB_HST_FAULT#" }, - { 5, GPIOF_IN , "*USB_OTG_FAULT#" }, - { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" }, - { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, - { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, - { 9, GPIOF_OUT_INIT_LOW , "*SER_EN" }, - { 10, GPIOF_IN, "*USER_PB#" }, - { 11, GPIOF_OUT_INIT_HIGH, "*PERST#" }, - { 100, GPIOF_IN , "*USER_PB#" }, - { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" }, -}; - -static struct gpio laguna_gpio_gw2384[] = { - { 0, GPIOF_IN , "*GSC_IRQ#" }, - { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" }, - { 2, GPIOF_IN , "*USB_HST_FAULT#" }, - { 5, GPIOF_IN , "*USB_OTG_FAULT#" }, - { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" }, - { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, - { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, - { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" }, - { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" }, - { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" }, - { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" }, - { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" }, - { 100, GPIOF_IN , "*USER_PB#" }, - { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" }, - { 108, GPIOF_IN , "J9_DIOGSC0" }, -}; - -static struct gpio laguna_gpio_gw2383[] = { - { 0, GPIOF_IN , "*GPS_PPS" }, - { 1, GPIOF_IN , "*GSC_IRQ#" }, - { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" }, - { 3, GPIOF_IN , "GPIO0" }, - { 8, GPIOF_IN , "GPIO1" }, - { 100, GPIOF_IN , "DIO0" }, - { 101, GPIOF_IN , "DIO1" }, - { 108, GPIOF_IN , "*USER_PB#" }, -}; - -static struct gpio laguna_gpio_gw2382[] = { - { 0, GPIOF_IN , "*GPS_PPS" }, - { 1, GPIOF_IN , "*GSC_IRQ#" }, - { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" }, - { 3, GPIOF_IN , "GPIO0" }, - { 4, GPIOF_IN , "GPIO1" }, - { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" }, - { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" }, - { 100, GPIOF_IN , "DIO0" }, - { 101, GPIOF_IN , "DIO1" }, - { 108, GPIOF_IN , "*USER_PB#" }, -}; - -static struct gpio laguna_gpio_gw2380[] = { - { 0, GPIOF_IN , "*GPS_PPS" }, - { 1, GPIOF_IN , "*GSC_IRQ#" }, - { 3, GPIOF_IN , "GPIO0" }, - { 8, GPIOF_IN , "GPIO1" }, - { 100, GPIOF_IN , "DIO0" }, - { 101, GPIOF_IN , "DIO1" }, - { 102, GPIOF_IN , "DIO2" }, - { 103, GPIOF_IN , "DIO3" }, - { 108, GPIOF_IN , "*USER_PB#" }, -}; - -/* - * Initialization - */ -static void __init laguna_init(void) -{ - struct clk *clk; - u32 __iomem *reg; - - clk = clk_register_fixed_rate(NULL, "cpu", NULL, - CLK_IGNORE_UNUSED, - cns3xxx_cpu_clock() * (1000000 / 8)); - clk_register_clkdev(clk, "cpu", NULL); - - platform_device_register(&laguna_watchdog); - - platform_device_register(&laguna_i2c_controller); - - /* Set I2C 0-3 drive strength to 21 mA */ - reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B; - *reg |= 0x300; - - /* Enable SCL/SDA for I2C */ - reg = MISC_GPIOB_PIN_ENABLE_REG; - *reg |= BIT(12) | BIT(13); - - /* Enable MMC/SD pins */ - *reg |= BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11); - - cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C); - cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C); - cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C); - - cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C)); - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C)); - - i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices)); - - pm_power_off = cns3xxx_power_off; -} - -static struct map_desc laguna_io_desc[] __initdata = { - { - .virtual = CNS3XXX_UART0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static void __init laguna_map_io(void) -{ - cns3xxx_map_io(); - iotable_init(ARRAY_AND_SIZE(laguna_io_desc)); - laguna_early_serial_setup(); -} - -static int laguna_register_gpio(struct gpio *array, size_t num) -{ - int i, err, ret; - - ret = 0; - for (i = 0; i < num; i++, array++) { - const char *label = array->label; - if (label[0] == '*') - label++; - err = gpio_request_one(array->gpio, array->flags, label); - if (err) - ret = err; - else { - err = gpio_export(array->gpio, array->label[0] != '*'); - } - } - return ret; -} - -/* allow disabling of external isolated PCIe IRQs */ -static int cns3xxx_pciextirq = 1; -static int __init cns3xxx_pciextirq_disable(char *s) -{ - cns3xxx_pciextirq = 0; - return 1; -} -__setup("noextirq", cns3xxx_pciextirq_disable); - -static int __init laguna_pcie_init_irq(void) -{ - u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004); - u32 reg = (__raw_readl(mem) >> 26) & 0xf; - int irqs[] = { - IRQ_CNS3XXX_EXTERNAL_PIN0, - IRQ_CNS3XXX_EXTERNAL_PIN1, - IRQ_CNS3XXX_EXTERNAL_PIN2, - 154, - }; - - if (!machine_is_gw2388()) - return 0; - - /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */ - if (cns3xxx_pciextirq && reg != 1) - cns3xxx_pciextirq = 0; - - if (cns3xxx_pciextirq) { - printk("laguna: using isolated PCI interrupts:" - " irq%d/irq%d/irq%d/irq%d\n", - irqs[0], irqs[1], irqs[2], irqs[3]); - cns3xxx_pcie_set_irqs(0, irqs); - } else { - printk("laguna: using shared PCI interrupts: irq%d\n", - IRQ_CNS3XXX_PCIE0_DEVICE); - } - - return 0; -} -subsys_initcall(laguna_pcie_init_irq); - -static int __init laguna_model_setup(void) -{ - u32 __iomem *mem; - u32 reg; - - if (!machine_is_gw2388()) - return 0; - - printk("Running on Gateworks Laguna %s\n", laguna_info.model); - cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA, - NR_IRQS_CNS3XXX); - - /* - * If pcie external interrupts are supported and desired - * configure IRQ types and configure pin function. - * Note that cns3xxx_pciextirq is enabled by default, but can be - * unset via the 'noextirq' kernel param or by laguna_pcie_init() if - * the baseboard model does not support this hardware feature. - */ - if (cns3xxx_pciextirq) { - mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018); - reg = __raw_readl(mem); - /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */ - reg &= ~0x3c000000; - reg |= 0x38000000; - __raw_writel(reg, mem); - - cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, - IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32); - - irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH); - irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH); - irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH); - } else { - cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, - IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32); - } - - if (strncmp(laguna_info.model, "GW", 2) == 0) { - if (laguna_info.config_bitmap & ETH0_LOAD) - laguna_net_data.ports |= BIT(0); - if (laguna_info.config_bitmap & ETH1_LOAD) - laguna_net_data.ports |= BIT(1); - if (laguna_info.config_bitmap & ETH2_LOAD) - laguna_net_data.ports |= BIT(2); - if (laguna_net_data.ports) - platform_device_register(&laguna_net_device); - - if ((laguna_info.config_bitmap & SATA0_LOAD) || - (laguna_info.config_bitmap & SATA1_LOAD)) - cns3xxx_ahci_init(); - - if (laguna_info.config_bitmap & (USB0_LOAD)) { - cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); - - /* DRVVBUS pins share with GPIOA */ - mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014); - reg = __raw_readl(mem); - reg |= 0x8; - __raw_writel(reg, mem); - - /* Enable OTG */ - mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808); - reg = __raw_readl(mem); - reg &= ~(1 << 10); - __raw_writel(reg, mem); - - platform_device_register(&cns3xxx_usb_otg_device); - } - - if (laguna_info.config_bitmap & (USB1_LOAD)) { - platform_device_register(&cns3xxx_usb_ehci_device); - platform_device_register(&cns3xxx_usb_ohci_device); - } - - if (laguna_info.config_bitmap & (SD_LOAD)) - cns3xxx_sdhci_init(); - - if (laguna_info.config_bitmap & (UART0_LOAD)) - laguna_uart.num_resources = 1; - if (laguna_info.config_bitmap & (UART1_LOAD)) - laguna_uart.num_resources = 2; - if (laguna_info.config_bitmap & (UART2_LOAD)) - laguna_uart.num_resources = 3; - platform_device_register(&laguna_uart); - - if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) { - laguna_nor_partitions[2].size = - (SZ_4M << laguna_info.nor_flash_size) - - laguna_nor_partitions[2].offset; - laguna_nor_res.end = CNS3XXX_FLASH_BASE + - laguna_nor_partitions[2].offset + - laguna_nor_partitions[2].size - 1; - platform_device_register(&laguna_nor_pdev); - } - - if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) { - laguna_spi_partitions[2].size = - (SZ_2M << laguna_info.spi_flash_size) - - laguna_spi_partitions[2].offset; - spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices)); - } - - if ((laguna_info.config_bitmap & SPI0_LOAD) || - (laguna_info.config_bitmap & SPI1_LOAD)) - platform_device_register(&laguna_spi_controller); - - if (laguna_info.config2_bitmap & GPS_LOAD) - platform_device_register(&laguna_pps_device); - - /* - * Do any model specific setup not known by the bitmap by matching - * the first 6 characters of the model name - */ - - if ( (strncmp(laguna_info.model, "GW2388", 6) == 0) - || (strncmp(laguna_info.model, "GW2389", 6) == 0) ) - { - // configure GPIO's - laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388)); - // configure LED's - laguna_gpio_leds_data.num_leds = 2; - } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) { - // configure GPIO's - laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387)); - // configure LED's - laguna_gpio_leds_data.num_leds = 2; - } else if (strncmp(laguna_info.model, "GW2386", 6) == 0) { - // configure GPIO's - laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2386)); - // configure LED's - laguna_gpio_leds_data.num_leds = 2; - } else if (strncmp(laguna_info.model, "GW2385", 6) == 0) { - // configure GPIO's - laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2385)); - // configure LED's - laguna_gpio_leds[0].gpio = 115; - laguna_gpio_leds[1].gpio = 12; - laguna_gpio_leds[1].name = "red"; - laguna_gpio_leds[1].active_low = 0, - laguna_gpio_leds[2].gpio = 14; - laguna_gpio_leds[2].name = "green"; - laguna_gpio_leds[2].active_low = 0, - laguna_gpio_leds[3].gpio = 15; - laguna_gpio_leds[3].name = "blue"; - laguna_gpio_leds[3].active_low = 0, - laguna_gpio_leds_data.num_leds = 4; - } else if ( (strncmp(laguna_info.model, "GW2384", 6) == 0) - || (strncmp(laguna_info.model, "GW2394", 6) == 0) ) - { - // configure GPIO's - laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384)); - // configure LED's - laguna_gpio_leds_data.num_leds = 1; - } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) { - // configure GPIO's - laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383)); - // configure LED's - laguna_gpio_leds[0].gpio = 107; - laguna_gpio_leds_data.num_leds = 1; - } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) { - // configure GPIO's - laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382)); - // configure LED's - laguna_gpio_leds[0].gpio = 107; - laguna_gpio_leds_data.num_leds = 1; - } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) { - // configure GPIO's - laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380)); - // configure LED's - laguna_gpio_leds[0].gpio = 107; - laguna_gpio_leds[1].gpio = 106; - laguna_gpio_leds_data.num_leds = 2; - } else if ( (strncmp(laguna_info.model, "GW2391", 6) == 0) - || (strncmp(laguna_info.model, "GW2393", 6) == 0) ) - { - // configure GPIO's - laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391)); - // configure LED's - laguna_gpio_leds_data.num_leds = 2; - } - platform_device_register(&laguna_gpio_leds_device); - } else { - // Do some defaults here, not sure what yet - } - return 0; -} -late_initcall(laguna_model_setup); - -MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform") - .smp = smp_ops(cns3xxx_smp_ops), - .atag_offset = 0x100, - .map_io = laguna_map_io, - .init_irq = cns3xxx_init_irq, - .init_time = cns3xxx_timer_init, - .init_machine = laguna_init, - .init_late = cns3xxx_pcie_init_late, - .restart = cns3xxx_restart, -MACHINE_END diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c deleted file mode 100644 index cb81d1e752..0000000000 --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c +++ /dev/null @@ -1,327 +0,0 @@ -/* - * linux/arch/arm/mach-cns3xxx/platsmp.c - * - * Copyright (C) 2002 ARM Ltd. - * Copyright 2012 Gateworks Corporation - * Chris Lang - * Tim Harvey - * - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include "cns3xxx.h" - -static struct fiq_handler fh = { - .name = "cns3xxx-fiq" -}; - -struct fiq_req { - union { - struct { - const void *addr; - size_t size; - } map; - struct { - const void *addr; - size_t size; - } unmap; - struct { - const void *start; - const void *end; - } flush; - }; - volatile uint flags; - void __iomem *reg; -} ____cacheline_aligned; - -extern unsigned int fiq_number[2]; - -DEFINE_PER_CPU(struct fiq_req, fiq_data); - -#define FIQ_ENABLED 0x80000000 -#define FIQ_GENERATE 0x00010000 -#define CNS3XXX_MAP_AREA 0x01000000 -#define CNS3XXX_UNMAP_AREA 0x02000000 -#define CNS3XXX_FLUSH_RANGE 0x03000000 - -extern void cns3xxx_secondary_startup(void); -extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end; - -#define SCU_CPU_STATUS 0x08 -static void __iomem *scu_base; - -static inline void cns3xxx_set_fiq_regs(unsigned int cpu) -{ - struct pt_regs FIQ_regs; - struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu); - - FIQ_regs.ARM_r8 = 0; - FIQ_regs.ARM_ip = (unsigned int)fiq_req; - FIQ_regs.ARM_sp = (int) MISC_FIQ_CPU(!cpu); - fiq_req->reg = MISC_FIQ_CPU(!cpu); - - set_fiq_regs(&FIQ_regs); -} - -static void __init cns3xxx_init_fiq(void) -{ - void *fiqhandler_start; - unsigned int fiqhandler_length; - int ret; - - fiqhandler_start = &cns3xxx_fiq_start; - fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start; - - ret = claim_fiq(&fh); - if (ret) - return; - - set_fiq_handler(fiqhandler_start, fiqhandler_length); -} - - -/* - * Write pen_release in a way that is guaranteed to be visible to all - * observers, irrespective of whether they're taking part in coherency - * or not. This is necessary for the hotplug code to work reliably. - */ -static void write_pen_release(int val) -{ - pen_release = val; - smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); -} - -static DEFINE_SPINLOCK(boot_lock); - -static void cns3xxx_secondary_init(unsigned int cpu) -{ - /* - * Setup Secondary Core FIQ regs - */ - cns3xxx_set_fiq_regs(1); - - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(-1); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -static int cns3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * Set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * The secondary processor is waiting to be released from - * the holding pen - release it, then wait for it to flag - * that it has been released by resetting pen_release. - * - * Note that "pen_release" is the hardware CPU ID, whereas - * "cpu" is Linux's internal ID. - */ - write_pen_release(cpu); - - /* - * Send the secondary CPU a soft interrupt, thereby causing - * the boot monitor to read the system wide flags register, - * and branch to the address found there. - */ - arch_send_wakeup_ipi_mask(cpumask_of(cpu));; - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - smp_rmb(); - if (pen_release == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return pen_release != -1 ? -ENOSYS : 0; -} - -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -static void __init cns3xxx_smp_init_cpus(void) -{ - unsigned int i, ncores; - unsigned int status; - - scu_base = (void __iomem *) CNS3XXX_TC11MP_SCU_BASE_VIRT; - - /* for CNS3xxx SCU_CPU_STATUS must be examined instead of SCU_CONFIGURATION - * used in scu_get_core_count - */ - status = __raw_readl(scu_base + SCU_CPU_STATUS); - for (i = 0; i < NR_CPUS+1; i++) { - if (((status >> (i*2)) & 0x3) == 0) - set_cpu_possible(i, true); - else - break; - } - ncores = i; -} - -static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus) -{ - /* - * enable SCU - */ - scu_enable(scu_base); - - /* - * Write the address of secondary startup into the - * system-wide flags register. The boot monitor waits - * until it receives a soft interrupt, and then the - * secondary CPU branches to this address. - */ - __raw_writel(virt_to_phys(cns3xxx_secondary_startup), - (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600)); - - /* - * Setup FIQ's for main cpu - */ - cns3xxx_init_fiq(); - cns3xxx_set_fiq_regs(0); -} - -extern void v6_dma_map_area(const void *, size_t, int); -extern void v6_dma_unmap_area(const void *, size_t, int); -extern void v6_dma_flush_range(const void *, const void *); -extern void v6_flush_kern_dcache_area(void *, size_t); - -void fiq_dma_map_area(const void *addr, size_t size, int dir) -{ - unsigned long flags; - struct fiq_req *req; - - raw_local_irq_save(flags); - /* currently, not possible to take cpu0 down, so only check cpu1 */ - if (!cpu_online(1)) { - raw_local_irq_restore(flags); - v6_dma_map_area(addr, size, dir); - return; - } - - req = this_cpu_ptr(&fiq_data); - req->map.addr = addr; - req->map.size = size; - req->flags = dir | CNS3XXX_MAP_AREA; - smp_mb(); - - writel_relaxed(FIQ_GENERATE, req->reg); - - v6_dma_map_area(addr, size, dir); - while (req->flags) - barrier(); - - raw_local_irq_restore(flags); -} - -void fiq_dma_unmap_area(const void *addr, size_t size, int dir) -{ - unsigned long flags; - struct fiq_req *req; - - raw_local_irq_save(flags); - /* currently, not possible to take cpu0 down, so only check cpu1 */ - if (!cpu_online(1)) { - raw_local_irq_restore(flags); - v6_dma_unmap_area(addr, size, dir); - return; - } - - req = this_cpu_ptr(&fiq_data); - req->unmap.addr = addr; - req->unmap.size = size; - req->flags = dir | CNS3XXX_UNMAP_AREA; - smp_mb(); - - writel_relaxed(FIQ_GENERATE, req->reg); - - v6_dma_unmap_area(addr, size, dir); - while (req->flags) - barrier(); - - raw_local_irq_restore(flags); -} - -void fiq_dma_flush_range(const void *start, const void *end) -{ - unsigned long flags; - struct fiq_req *req; - - raw_local_irq_save(flags); - /* currently, not possible to take cpu0 down, so only check cpu1 */ - if (!cpu_online(1)) { - raw_local_irq_restore(flags); - v6_dma_flush_range(start, end); - return; - } - - req = this_cpu_ptr(&fiq_data); - - req->flush.start = start; - req->flush.end = end; - req->flags = CNS3XXX_FLUSH_RANGE; - smp_mb(); - - writel_relaxed(FIQ_GENERATE, req->reg); - - v6_dma_flush_range(start, end); - - while (req->flags) - barrier(); - - raw_local_irq_restore(flags); -} - -void fiq_flush_kern_dcache_area(void *addr, size_t size) -{ - fiq_dma_flush_range(addr, addr + size); -} - -struct smp_operations cns3xxx_smp_ops __initdata = { - .smp_init_cpus = cns3xxx_smp_init_cpus, - .smp_prepare_cpus = cns3xxx_smp_prepare_cpus, - .smp_secondary_init = cns3xxx_secondary_init, - .smp_boot_secondary = cns3xxx_boot_secondary, -}; diff --git a/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c b/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c deleted file mode 100644 index 7acff37d26..0000000000 --- a/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c +++ /dev/null @@ -1,374 +0,0 @@ -/* - * Cavium CNS3xxx I2C Host Controller - * - * Copyright 2010 Cavium Network - * Copyright 2012 Gateworks Corporation - * Chris Lang - * Tim Harvey - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * We need the memory map - */ - -#define I2C_MEM_MAP_ADDR(x) (i2c->base + x) -#define I2C_MEM_MAP_VALUE(x) (*((unsigned int volatile*)I2C_MEM_MAP_ADDR(x))) - -#define I2C_CONTROLLER_REG I2C_MEM_MAP_VALUE(0x00) -#define I2C_TIME_OUT_REG I2C_MEM_MAP_VALUE(0x04) -#define I2C_SLAVE_ADDRESS_REG I2C_MEM_MAP_VALUE(0x08) -#define I2C_WRITE_DATA_REG I2C_MEM_MAP_VALUE(0x0C) -#define I2C_READ_DATA_REG I2C_MEM_MAP_VALUE(0x10) -#define I2C_INTERRUPT_STATUS_REG I2C_MEM_MAP_VALUE(0x14) -#define I2C_INTERRUPT_ENABLE_REG I2C_MEM_MAP_VALUE(0x18) -#define I2C_TWI_OUT_DLY_REG I2C_MEM_MAP_VALUE(0x1C) - -#define I2C_BUS_ERROR_FLAG (0x1) -#define I2C_ACTION_DONE_FLAG (0x2) - -#define CNS3xxx_I2C_ENABLE() (I2C_CONTROLLER_REG) |= ((unsigned int)0x1 << 31) -#define CNS3xxx_I2C_DISABLE() (I2C_CONTROLLER_REG) &= ~((unsigned int)0x1 << 31) -#define CNS3xxx_I2C_ENABLE_INTR() (I2C_INTERRUPT_ENABLE_REG) |= 0x03 -#define CNS3xxx_I2C_DISABLE_INTR() (I2C_INTERRUPT_ENABLE_REG) &= 0xfc - -#define TWI_TIMEOUT (10*HZ) -#define I2C_100KHZ 100000 -#define I2C_200KHZ 200000 -#define I2C_300KHZ 300000 -#define I2C_400KHZ 400000 - -#define CNS3xxx_I2C_CLK I2C_100KHZ - -#define STATE_DONE 1 -#define STATE_ERROR 2 - -struct cns3xxx_i2c { - struct device *dev; - void __iomem *base; /* virtual */ - wait_queue_head_t wait; - struct i2c_adapter adap; - struct i2c_msg *msg; - u8 state; /* see STATE_ */ - u8 error; /* see TWI_STATUS register */ - int rd_wr_len; - u8 *buf; -}; - -static u32 cns3xxx_i2c_func(struct i2c_adapter *adap) -{ - return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; -} - -static int -cns3xxx_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg) -{ - struct cns3xxx_i2c *i2c = i2c_get_adapdata(adap); - int i, j; - u8 buf[1] = { 0 }; - - if (msg->len == 0) { - /* - * We are probably doing a probe for a device here, - * so set the length to one, and data to 0 - */ - msg->len = 1; - i2c->buf = buf; - } else { - i2c->buf = msg->buf; - } - - if (msg->flags & I2C_M_TEN) { - printk - ("%s:%d: Presently the driver does not handle extended addressing\n", - __FUNCTION__, __LINE__); - return -EINVAL; - } - i2c->msg = msg; - - for (i = 0; i < msg->len; i++) { - if (msg->len - i >= 4) - i2c->rd_wr_len = 3; - else - i2c->rd_wr_len = msg->len - i - 1; - - // Set Data Width and TWI_EN - I2C_CONTROLLER_REG = 0x80000000 | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len); - - // Clear Write Reg - I2C_WRITE_DATA_REG = 0; - - // Set the slave address - I2C_SLAVE_ADDRESS_REG = (msg->addr << 1); - - // Are we Writing - if (!(msg->flags & I2C_M_RD)) { - I2C_CONTROLLER_REG |= (1 << 4); - if (i != 0) { - /* - * We need to set the address in the first byte. - * The base address is going to be in buf[0] and then - * it needs to be incremented by i - 1. - */ - i2c->buf--; - *i2c->buf = buf[0] + i - 1; - - if (i2c->rd_wr_len < 3) { - i += i2c->rd_wr_len; - i2c->rd_wr_len++; - I2C_CONTROLLER_REG = 0x80000000 | (1 << 4) | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len); - } else { - i += i2c->rd_wr_len - 1; - } - } else { - i += i2c->rd_wr_len; - buf[0] = *i2c->buf; - } - for (j = 0; j <= i2c->rd_wr_len; j++) { - I2C_WRITE_DATA_REG |= ((*i2c->buf++) << (8 * j)); - } - } else { - i += i2c->rd_wr_len; - } - - // Start the Transfer - i2c->state = 0; // Clear out the State - i2c->error = 0; - I2C_CONTROLLER_REG |= (1 << 6); - - if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || - (i2c->state == STATE_DONE), TWI_TIMEOUT)) { - if (i2c->state == STATE_ERROR) { - dev_dbg(i2c->dev, "controller error: 0x%2x", i2c->error); - return -EAGAIN; // try again - } - } else { - dev_err(i2c->dev, "controller timed out " - "waiting for start condition to finish\n"); - return -ETIMEDOUT; - } - } - return 0; -} - -static int -cns3xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) -{ - int i; - int ret; - for (i = 0; i < num; i++) - { - ret = cns3xxx_i2c_xfer_msg(adap, &msgs[i]); - if (ret < 0) { - return ret; - } - } - return num; -} - - -static struct i2c_algorithm cns3xxx_i2c_algo = { - .master_xfer = cns3xxx_i2c_xfer, - .functionality = cns3xxx_i2c_func, -}; - -static struct i2c_adapter cns3xxx_i2c_adapter = { - .owner = THIS_MODULE, - .algo = &cns3xxx_i2c_algo, - .algo_data = NULL, - .nr = 0, - .name = "CNS3xxx I2C 0", - .retries = 5, -}; - -static void cns3xxx_i2c_adapter_init(struct cns3xxx_i2c *i2c) -{ - struct clk *clk; - - clk = devm_clk_get(i2c->dev, "cpu"); - if (WARN_ON(!clk)) - return; - - /* Disable the I2C */ - I2C_CONTROLLER_REG = 0; /* Disabled the I2C */ - - /* Check the Reg Dump when testing */ - I2C_TIME_OUT_REG = - (((((clk_get_rate(clk) / (2 * CNS3xxx_I2C_CLK)) - - 1) & 0x3FF) << 8) | (1 << 7) | 0x7F); - I2C_TWI_OUT_DLY_REG |= 0x3; - - /* Enable The Interrupt */ - CNS3xxx_I2C_ENABLE_INTR(); - - /* Clear Interrupt Status (0x2 | 0x1) */ - I2C_INTERRUPT_STATUS_REG |= (I2C_ACTION_DONE_FLAG | I2C_BUS_ERROR_FLAG); - - /* Enable the I2C Controller */ - CNS3xxx_I2C_ENABLE(); -} - -static irqreturn_t cns3xxx_i2c_isr(int irq, void *dev_id) -{ - struct cns3xxx_i2c *i2c = dev_id; - int i; - uint32_t stat = I2C_INTERRUPT_STATUS_REG; - - /* Clear Interrupt */ - I2C_INTERRUPT_STATUS_REG |= 0x1; - - if (stat & I2C_BUS_ERROR_FLAG) { - i2c->state = STATE_ERROR; - i2c->error = (I2C_INTERRUPT_STATUS_REG & 0xff00)>>8; - } else { - if (i2c->msg->flags & I2C_M_RD) { - for (i = 0; i <= i2c->rd_wr_len; i++) - { - *i2c->buf++ = ((I2C_READ_DATA_REG >> (8 * i)) & 0xff); - } - } - i2c->state = STATE_DONE; - } - wake_up(&i2c->wait); - return IRQ_HANDLED; -} - -static int cns3xxx_i2c_probe(struct platform_device *pdev) -{ - struct cns3xxx_i2c *i2c; - struct resource *res, *res2; - int ret; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - printk("%s: IORESOURCE_MEM not defined \n", __FUNCTION__); - return -ENODEV; - } - - res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res2) { - printk("%s: IORESOURCE_IRQ not defined \n", __FUNCTION__); - return -ENODEV; - } - - i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); - if (!i2c) - return -ENOMEM; - - if (!request_mem_region(res->start, res->end - res->start + 1, - pdev->name)) { - dev_err(&pdev->dev, "Memory region busy\n"); - ret = -EBUSY; - goto request_mem_failed; - } - - i2c->dev = &pdev->dev; - i2c->base = ioremap(res->start, res->end - res->start + 1); - if (!i2c->base) { - dev_err(&pdev->dev, "Unable to map registers\n"); - ret = -EIO; - goto map_failed; - } - - cns3xxx_i2c_adapter_init(i2c); - - init_waitqueue_head(&i2c->wait); - ret = request_irq(res2->start, cns3xxx_i2c_isr, 0, pdev->name, i2c); - if (ret) { - dev_err(&pdev->dev, "Cannot claim IRQ\n"); - goto request_irq_failed; - } - - platform_set_drvdata(pdev, i2c); - i2c->adap = cns3xxx_i2c_adapter; - i2c_set_adapdata(&i2c->adap, i2c); - i2c->adap.dev.parent = &pdev->dev; - - /* add i2c adapter to i2c tree */ - ret = i2c_add_numbered_adapter(&i2c->adap); - if (ret) { - dev_err(&pdev->dev, "Failed to add adapter\n"); - goto add_adapter_failed; - } - - return 0; - - add_adapter_failed: - free_irq(res2->start, i2c); - request_irq_failed: - iounmap(i2c->base); - map_failed: - release_mem_region(res->start, res->end - res->start + 1); - request_mem_failed: - kfree(i2c); - - return ret; -} - -static int cns3xxx_i2c_remove(struct platform_device *pdev) -{ - struct cns3xxx_i2c *i2c = platform_get_drvdata(pdev); - struct resource *res; - - /* disable i2c logic */ - CNS3xxx_I2C_DISABLE_INTR(); - CNS3xxx_I2C_DISABLE(); - /* remove adapter & data */ - i2c_del_adapter(&i2c->adap); - platform_set_drvdata(pdev, NULL); - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (res) - free_irq(res->start, i2c); - - iounmap(i2c->base); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res) - release_mem_region(res->start, res->end - res->start + 1); - - kfree(i2c); - - return 0; -} - -static struct platform_driver cns3xxx_i2c_driver = { - .probe = cns3xxx_i2c_probe, - .remove = cns3xxx_i2c_remove, - .driver = { - .owner = THIS_MODULE, - .name = "cns3xxx-i2c", - }, -}; - -static int __init cns3xxx_i2c_init(void) -{ - return platform_driver_register(&cns3xxx_i2c_driver); -} - -static void __exit cns3xxx_i2c_exit(void) -{ - platform_driver_unregister(&cns3xxx_i2c_driver); -} - -module_init(cns3xxx_i2c_init); -module_exit(cns3xxx_i2c_exit); - -MODULE_AUTHOR("Cavium Networks"); -MODULE_DESCRIPTION("Cavium CNS3XXX I2C Controller"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Kconfig b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Kconfig deleted file mode 100644 index 79eebe2863..0000000000 --- a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -config NET_VENDOR_CAVIUM - bool "Cavium devices" - default y - depends on ARCH_CNS3XXX - ---help--- - If you have a network (Ethernet) chipset belonging to this class, - say Y. - - Note that the answer to this question does not directly affect - the kernel: saying N will just case the configurator to skip all - the questions regarding AMD chipsets. If you say Y, you will be asked - for your specific chipset/driver in the following questions. - -if NET_VENDOR_CAVIUM - -config CNS3XXX_ETH - tristate "Cavium CNS3xxx Ethernet support" - depends on ARCH_CNS3XXX - select PHYLIB - help - Say Y here if you want to use built-in Ethernet ports - on CNS3XXX processor. - -endif diff --git a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Makefile b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Makefile deleted file mode 100644 index badd2404a6..0000000000 --- a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the Cavium ethernet device drivers. -# - -obj-$(CONFIG_CNS3XXX_ETH) += cns3xxx_eth.o diff --git a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c deleted file mode 100644 index 4556499429..0000000000 --- a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c +++ /dev/null @@ -1,1325 +0,0 @@ -/* - * Cavium CNS3xxx Gigabit driver for Linux - * - * Copyright 2011 Gateworks Corporation - * Chris Lang - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License - * as published by the Free Software Foundation. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DRV_NAME "cns3xxx_eth" - -#define RX_DESCS 256 -#define TX_DESCS 128 -#define TX_DESC_RESERVE 20 - -#define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS) -#define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS) -#define REGS_SIZE 336 - -#define RX_BUFFER_ALIGN 64 -#define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1)) - -#define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN) -#define RX_SEGMENT_ALLOC_SIZE 2048 -#define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE)) -#define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN) -#define MAX_MTU 9500 - -#define NAPI_WEIGHT 64 - -/* MDIO Defines */ -#define MDIO_CMD_COMPLETE 0x00008000 -#define MDIO_WRITE_COMMAND 0x00002000 -#define MDIO_READ_COMMAND 0x00004000 -#define MDIO_REG_OFFSET 8 -#define MDIO_VALUE_OFFSET 16 - -/* Descritor Defines */ -#define END_OF_RING 0x40000000 -#define FIRST_SEGMENT 0x20000000 -#define LAST_SEGMENT 0x10000000 -#define FORCE_ROUTE 0x04000000 -#define UDP_CHECKSUM 0x00020000 -#define TCP_CHECKSUM 0x00010000 - -/* Port Config Defines */ -#define PORT_BP_ENABLE 0x00020000 -#define PORT_DISABLE 0x00040000 -#define PORT_LEARN_DIS 0x00080000 -#define PORT_BLOCK_STATE 0x00100000 -#define PORT_BLOCK_MODE 0x00200000 - -#define PROMISC_OFFSET 29 - -/* Global Config Defines */ -#define UNKNOWN_VLAN_TO_CPU 0x02000000 -#define ACCEPT_CRC_PACKET 0x00200000 -#define CRC_STRIPPING 0x00100000 - -/* VLAN Config Defines */ -#define NIC_MODE 0x00008000 -#define VLAN_UNAWARE 0x00000001 - -/* DMA AUTO Poll Defines */ -#define TS_POLL_EN 0x00000020 -#define TS_SUSPEND 0x00000010 -#define FS_POLL_EN 0x00000002 -#define FS_SUSPEND 0x00000001 - -/* DMA Ring Control Defines */ -#define QUEUE_THRESHOLD 0x000000f0 -#define CLR_FS_STATE 0x80000000 - -/* Interrupt Status Defines */ -#define MAC0_STATUS_CHANGE 0x00004000 -#define MAC1_STATUS_CHANGE 0x00008000 -#define MAC2_STATUS_CHANGE 0x00010000 -#define MAC0_RX_ERROR 0x00100000 -#define MAC1_RX_ERROR 0x00200000 -#define MAC2_RX_ERROR 0x00400000 - -struct tx_desc -{ - u32 sdp; /* segment data pointer */ - - union { - struct { - u32 sdl:16; /* segment data length */ - u32 tco:1; - u32 uco:1; - u32 ico:1; - u32 rsv_1:3; /* reserve */ - u32 pri:3; - u32 fp:1; /* force priority */ - u32 fr:1; - u32 interrupt:1; - u32 lsd:1; - u32 fsd:1; - u32 eor:1; - u32 cown:1; - }; - u32 config0; - }; - - union { - struct { - u32 ctv:1; - u32 stv:1; - u32 sid:4; - u32 inss:1; - u32 dels:1; - u32 rsv_2:9; - u32 pmap:5; - u32 mark:3; - u32 ewan:1; - u32 fewan:1; - u32 rsv_3:5; - }; - u32 config1; - }; - - union { - struct { - u32 c_vid:12; - u32 c_cfs:1; - u32 c_pri:3; - u32 s_vid:12; - u32 s_dei:1; - u32 s_pri:3; - }; - u32 config2; - }; - - u8 alignment[16]; /* for 32 byte */ -}; - -struct rx_desc -{ - u32 sdp; /* segment data pointer */ - - union { - struct { - u32 sdl:16; /* segment data length */ - u32 l4f:1; - u32 ipf:1; - u32 prot:4; - u32 hr:6; - u32 lsd:1; - u32 fsd:1; - u32 eor:1; - u32 cown:1; - }; - u32 config0; - }; - - union { - struct { - u32 ctv:1; - u32 stv:1; - u32 unv:1; - u32 iwan:1; - u32 exdv:1; - u32 e_wan:1; - u32 rsv_1:2; - u32 sp:3; - u32 crc_err:1; - u32 un_eth:1; - u32 tc:2; - u32 rsv_2:1; - u32 ip_offset:5; - u32 rsv_3:11; - }; - u32 config1; - }; - - union { - struct { - u32 c_vid:12; - u32 c_cfs:1; - u32 c_pri:3; - u32 s_vid:12; - u32 s_dei:1; - u32 s_pri:3; - }; - u32 config2; - }; - - u8 alignment[16]; /* for 32 byte alignment */ -}; - - -struct switch_regs { - u32 phy_control; - u32 phy_auto_addr; - u32 mac_glob_cfg; - u32 mac_cfg[4]; - u32 mac_pri_ctrl[5], __res; - u32 etype[2]; - u32 udp_range[4]; - u32 prio_etype_udp; - u32 prio_ipdscp[8]; - u32 tc_ctrl; - u32 rate_ctrl; - u32 fc_glob_thrs; - u32 fc_port_thrs; - u32 mc_fc_glob_thrs; - u32 dc_glob_thrs; - u32 arl_vlan_cmd; - u32 arl_ctrl[3]; - u32 vlan_cfg; - u32 pvid[2]; - u32 vlan_ctrl[3]; - u32 session_id[8]; - u32 intr_stat; - u32 intr_mask; - u32 sram_test; - u32 mem_queue; - u32 farl_ctrl; - u32 fc_input_thrs, __res1[2]; - u32 clk_skew_ctrl; - u32 mac_glob_cfg_ext, __res2[2]; - u32 dma_ring_ctrl; - u32 dma_auto_poll_cfg; - u32 delay_intr_cfg, __res3; - u32 ts_dma_ctrl0; - u32 ts_desc_ptr0; - u32 ts_desc_base_addr0, __res4; - u32 fs_dma_ctrl0; - u32 fs_desc_ptr0; - u32 fs_desc_base_addr0, __res5; - u32 ts_dma_ctrl1; - u32 ts_desc_ptr1; - u32 ts_desc_base_addr1, __res6; - u32 fs_dma_ctrl1; - u32 fs_desc_ptr1; - u32 fs_desc_base_addr1; - u32 __res7[109]; - u32 mac_counter0[13]; -}; - -struct _tx_ring { - struct tx_desc *desc; - dma_addr_t phys_addr; - struct tx_desc *cur_addr; - struct sk_buff *buff_tab[TX_DESCS]; - unsigned int phys_tab[TX_DESCS]; - u32 free_index; - u32 count_index; - u32 cur_index; - int num_used; - int num_count; - bool stopped; -}; - -struct _rx_ring { - struct rx_desc *desc; - dma_addr_t phys_addr; - struct rx_desc *cur_addr; - void *buff_tab[RX_DESCS]; - unsigned int phys_tab[RX_DESCS]; - u32 cur_index; - u32 alloc_index; - int alloc_count; -}; - -struct sw { - struct switch_regs __iomem *regs; - struct napi_struct napi; - struct cns3xxx_plat_info *plat; - struct _tx_ring tx_ring; - struct _rx_ring rx_ring; - struct sk_buff *frag_first; - struct sk_buff *frag_last; - struct device *dev; - int rx_irq; - int stat_irq; -}; - -struct port { - struct net_device *netdev; - struct phy_device *phydev; - struct sw *sw; - int id; /* logical port ID */ - int speed, duplex; -}; - -static spinlock_t mdio_lock; -static DEFINE_SPINLOCK(tx_lock); -static struct switch_regs __iomem *mdio_regs; /* mdio command and status only */ -struct mii_bus *mdio_bus; -static int ports_open; -static struct port *switch_port_tab[4]; -struct net_device *napi_dev; - -static int cns3xxx_mdio_cmd(struct mii_bus *bus, int phy_id, int location, - int write, u16 cmd) -{ - int cycles = 0; - u32 temp = 0; - - temp = __raw_readl(&mdio_regs->phy_control); - temp |= MDIO_CMD_COMPLETE; - __raw_writel(temp, &mdio_regs->phy_control); - udelay(10); - - if (write) { - temp = (cmd << MDIO_VALUE_OFFSET); - temp |= MDIO_WRITE_COMMAND; - } else { - temp = MDIO_READ_COMMAND; - } - - temp |= ((location & 0x1f) << MDIO_REG_OFFSET); - temp |= (phy_id & 0x1f); - - __raw_writel(temp, &mdio_regs->phy_control); - - while (((__raw_readl(&mdio_regs->phy_control) & MDIO_CMD_COMPLETE) == 0) - && cycles < 5000) { - udelay(1); - cycles++; - } - - if (cycles == 5000) { - printk(KERN_ERR "%s #%i: MII transaction failed\n", bus->name, phy_id); - return -1; - } - - temp = __raw_readl(&mdio_regs->phy_control); - temp |= MDIO_CMD_COMPLETE; - __raw_writel(temp, &mdio_regs->phy_control); - - if (write) - return 0; - - return ((temp >> MDIO_VALUE_OFFSET) & 0xFFFF); -} - -static int cns3xxx_mdio_read(struct mii_bus *bus, int phy_id, int location) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&mdio_lock, flags); - ret = cns3xxx_mdio_cmd(bus, phy_id, location, 0, 0); - spin_unlock_irqrestore(&mdio_lock, flags); - return ret; -} - -static int cns3xxx_mdio_write(struct mii_bus *bus, int phy_id, int location, u16 val) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&mdio_lock, flags); - ret = cns3xxx_mdio_cmd(bus, phy_id, location, 1, val); - spin_unlock_irqrestore(&mdio_lock, flags); - return ret; -} - -static int cns3xxx_mdio_register(void __iomem *base) -{ - int err; - - if (!(mdio_bus = mdiobus_alloc())) - return -ENOMEM; - - mdio_regs = base; - - spin_lock_init(&mdio_lock); - mdio_bus->name = "CNS3xxx MII Bus"; - mdio_bus->read = &cns3xxx_mdio_read; - mdio_bus->write = &cns3xxx_mdio_write; - strcpy(mdio_bus->id, "0"); - - if ((err = mdiobus_register(mdio_bus))) - mdiobus_free(mdio_bus); - - return err; -} - -static void cns3xxx_mdio_remove(void) -{ - mdiobus_unregister(mdio_bus); - mdiobus_free(mdio_bus); -} - -static void enable_tx_dma(struct sw *sw) -{ - __raw_writel(0x1, &sw->regs->ts_dma_ctrl0); -} - -static void enable_rx_dma(struct sw *sw) -{ - __raw_writel(0x1, &sw->regs->fs_dma_ctrl0); -} - -static void cns3xxx_adjust_link(struct net_device *dev) -{ - struct port *port = netdev_priv(dev); - struct phy_device *phydev = port->phydev; - - if (!phydev->link) { - if (port->speed) { - port->speed = 0; - printk(KERN_INFO "%s: link down\n", dev->name); - } - return; - } - - if (port->speed == phydev->speed && port->duplex == phydev->duplex) - return; - - port->speed = phydev->speed; - port->duplex = phydev->duplex; - - printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n", - dev->name, port->speed, port->duplex ? "full" : "half"); -} - -static void eth_schedule_poll(struct sw *sw) -{ - if (unlikely(!napi_schedule_prep(&sw->napi))) - return; - - disable_irq_nosync(sw->rx_irq); - __napi_schedule(&sw->napi); -} - -irqreturn_t eth_rx_irq(int irq, void *pdev) -{ - struct net_device *dev = pdev; - struct sw *sw = netdev_priv(dev); - eth_schedule_poll(sw); - return (IRQ_HANDLED); -} - -irqreturn_t eth_stat_irq(int irq, void *pdev) -{ - struct net_device *dev = pdev; - struct sw *sw = netdev_priv(dev); - u32 cfg; - u32 stat = __raw_readl(&sw->regs->intr_stat); - __raw_writel(0xffffffff, &sw->regs->intr_stat); - - if (stat & MAC2_RX_ERROR) - switch_port_tab[3]->netdev->stats.rx_dropped++; - if (stat & MAC1_RX_ERROR) - switch_port_tab[1]->netdev->stats.rx_dropped++; - if (stat & MAC0_RX_ERROR) - switch_port_tab[0]->netdev->stats.rx_dropped++; - - if (stat & MAC0_STATUS_CHANGE) { - cfg = __raw_readl(&sw->regs->mac_cfg[0]); - switch_port_tab[0]->phydev->link = (cfg & 0x1); - switch_port_tab[0]->phydev->duplex = ((cfg >> 4) & 0x1); - if (((cfg >> 2) & 0x3) == 2) - switch_port_tab[0]->phydev->speed = 1000; - else if (((cfg >> 2) & 0x3) == 1) - switch_port_tab[0]->phydev->speed = 100; - else - switch_port_tab[0]->phydev->speed = 10; - cns3xxx_adjust_link(switch_port_tab[0]->netdev); - } - - if (stat & MAC1_STATUS_CHANGE) { - cfg = __raw_readl(&sw->regs->mac_cfg[1]); - switch_port_tab[1]->phydev->link = (cfg & 0x1); - switch_port_tab[1]->phydev->duplex = ((cfg >> 4) & 0x1); - if (((cfg >> 2) & 0x3) == 2) - switch_port_tab[1]->phydev->speed = 1000; - else if (((cfg >> 2) & 0x3) == 1) - switch_port_tab[1]->phydev->speed = 100; - else - switch_port_tab[1]->phydev->speed = 10; - cns3xxx_adjust_link(switch_port_tab[1]->netdev); - } - - if (stat & MAC2_STATUS_CHANGE) { - cfg = __raw_readl(&sw->regs->mac_cfg[3]); - switch_port_tab[3]->phydev->link = (cfg & 0x1); - switch_port_tab[3]->phydev->duplex = ((cfg >> 4) & 0x1); - if (((cfg >> 2) & 0x3) == 2) - switch_port_tab[3]->phydev->speed = 1000; - else if (((cfg >> 2) & 0x3) == 1) - switch_port_tab[3]->phydev->speed = 100; - else - switch_port_tab[3]->phydev->speed = 10; - cns3xxx_adjust_link(switch_port_tab[3]->netdev); - } - - return (IRQ_HANDLED); -} - - -static void cns3xxx_alloc_rx_buf(struct sw *sw, int received) -{ - struct _rx_ring *rx_ring = &sw->rx_ring; - unsigned int i = rx_ring->alloc_index; - struct rx_desc *desc = &(rx_ring)->desc[i]; - void *buf; - unsigned int phys; - - for (received += rx_ring->alloc_count; received > 0; received--) { - buf = napi_alloc_frag(RX_SEGMENT_ALLOC_SIZE); - if (!buf) - break; - - phys = dma_map_single(sw->dev, buf + SKB_HEAD_ALIGN, - RX_SEGMENT_MRU, DMA_FROM_DEVICE); - if (dma_mapping_error(sw->dev, phys)) { - skb_free_frag(buf); - break; - } - - desc->sdl = RX_SEGMENT_MRU; - desc->sdp = phys; - - wmb(); - - /* put the new buffer on RX-free queue */ - rx_ring->buff_tab[i] = buf; - rx_ring->phys_tab[i] = phys; - - if (i == RX_DESCS - 1) { - desc->config0 = FIRST_SEGMENT | LAST_SEGMENT | RX_SEGMENT_MRU | END_OF_RING; - i = 0; - desc = &(rx_ring)->desc[i]; - } else { - desc->config0 = FIRST_SEGMENT | LAST_SEGMENT | RX_SEGMENT_MRU; - i++; - desc++; - } - } - - rx_ring->alloc_count = received; - rx_ring->alloc_index = i; -} - -static void eth_check_num_used(struct _tx_ring *tx_ring) -{ - bool stop = false; - int i; - - if (tx_ring->num_used >= TX_DESCS - TX_DESC_RESERVE) - stop = true; - - if (tx_ring->stopped == stop) - return; - - tx_ring->stopped = stop; - - for (i = 0; i < 4; i++) { - struct port *port = switch_port_tab[i]; - struct net_device *dev; - - if (!port) - continue; - - dev = port->netdev; - - if (stop) - netif_stop_queue(dev); - else - netif_wake_queue(dev); - } -} - -static void eth_complete_tx(struct sw *sw) -{ - struct _tx_ring *tx_ring = &sw->tx_ring; - struct tx_desc *desc; - int i; - int index; - int num_used = tx_ring->num_used; - struct sk_buff *skb; - - index = tx_ring->free_index; - desc = &(tx_ring)->desc[index]; - - for (i = 0; i < num_used; i++) { - if (!desc->cown) - break; - - skb = tx_ring->buff_tab[index]; - tx_ring->buff_tab[index] = 0; - - if (skb) - dev_kfree_skb_any(skb); - - dma_unmap_single(sw->dev, tx_ring->phys_tab[index], desc->sdl, DMA_TO_DEVICE); - - if (index == TX_DESCS - 1) { - index = 0; - desc = &(tx_ring)->desc[index]; - } else { - index++; - desc++; - } - } - - tx_ring->free_index = index; - tx_ring->num_used -= i; - eth_check_num_used(tx_ring); -} - -static int eth_poll(struct napi_struct *napi, int budget) -{ - struct sw *sw = container_of(napi, struct sw, napi); - struct _rx_ring *rx_ring = &sw->rx_ring; - int received = 0; - unsigned int length; - unsigned int i = rx_ring->cur_index; - struct rx_desc *desc = &(rx_ring)->desc[i]; - unsigned int alloc_count = rx_ring->alloc_count; - - while (desc->cown && alloc_count + received < RX_DESCS - 1) { - struct sk_buff *skb; - int reserve = SKB_HEAD_ALIGN; - - if (received >= budget) - break; - - /* process received frame */ - dma_unmap_single(sw->dev, rx_ring->phys_tab[i], RX_SEGMENT_MRU, DMA_FROM_DEVICE); - - skb = build_skb(rx_ring->buff_tab[i], RX_SEGMENT_ALLOC_SIZE); - if (!skb) - break; - - skb->dev = switch_port_tab[desc->sp]->netdev; - - length = desc->sdl; - if (desc->fsd && !desc->lsd) - length = RX_SEGMENT_MRU; - - if (!desc->fsd) { - reserve -= NET_IP_ALIGN; - if (!desc->lsd) - length += NET_IP_ALIGN; - } - - skb_reserve(skb, reserve); - skb_put(skb, length); - - if (!sw->frag_first) - sw->frag_first = skb; - else { - if (sw->frag_first == sw->frag_last) - skb_shinfo(sw->frag_first)->frag_list = skb; - else - sw->frag_last->next = skb; - sw->frag_first->len += skb->len; - sw->frag_first->data_len += skb->len; - sw->frag_first->truesize += skb->truesize; - } - sw->frag_last = skb; - - if (desc->lsd) { - struct net_device *dev; - - skb = sw->frag_first; - dev = skb->dev; - skb->protocol = eth_type_trans(skb, dev); - - dev->stats.rx_packets++; - dev->stats.rx_bytes += skb->len; - - /* RX Hardware checksum offload */ - skb->ip_summed = CHECKSUM_NONE; - switch (desc->prot) { - case 1: - case 2: - case 5: - case 6: - case 13: - case 14: - if (!desc->l4f) { - skb->ip_summed = CHECKSUM_UNNECESSARY; - napi_gro_receive(napi, skb); - break; - } - /* fall through */ - default: - netif_receive_skb(skb); - break; - } - - sw->frag_first = NULL; - sw->frag_last = NULL; - } - - received++; - if (i == RX_DESCS - 1) { - i = 0; - desc = &(rx_ring)->desc[i]; - } else { - i++; - desc++; - } - } - - rx_ring->cur_index = i; - - cns3xxx_alloc_rx_buf(sw, received); - wmb(); - enable_rx_dma(sw); - - if (received < budget && napi_complete_done(napi, received)) { - enable_irq(sw->rx_irq); - } - - spin_lock_bh(&tx_lock); - eth_complete_tx(sw); - spin_unlock_bh(&tx_lock); - - return received; -} - -static void eth_set_desc(struct sw *sw, struct _tx_ring *tx_ring, int index, - int index_last, void *data, int len, u32 config0, - u32 pmap) -{ - struct tx_desc *tx_desc = &(tx_ring)->desc[index]; - unsigned int phys; - - phys = dma_map_single(sw->dev, data, len, DMA_TO_DEVICE); - tx_desc->sdp = phys; - tx_desc->pmap = pmap; - tx_ring->phys_tab[index] = phys; - - config0 |= len; - - if (index == TX_DESCS - 1) - config0 |= END_OF_RING; - - if (index == index_last) - config0 |= LAST_SEGMENT; - - wmb(); - tx_desc->config0 = config0; -} - -static int eth_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct port *port = netdev_priv(dev); - struct sw *sw = port->sw; - struct _tx_ring *tx_ring = &sw->tx_ring; - struct sk_buff *skb1; - char pmap = (1 << port->id); - int nr_frags = skb_shinfo(skb)->nr_frags; - int nr_desc = nr_frags; - int index0, index, index_last; - int len0; - int i; - u32 config0; - - if (pmap == 8) - pmap = (1 << 4); - - skb_walk_frags(skb, skb1) - nr_desc++; - - eth_schedule_poll(sw); - spin_lock_bh(&tx_lock); - - if ((tx_ring->num_used + nr_desc + 1) >= TX_DESCS) { - spin_unlock_bh(&tx_lock); - return NETDEV_TX_BUSY; - } - - index = index0 = tx_ring->cur_index; - index_last = (index0 + nr_desc) % TX_DESCS; - tx_ring->cur_index = (index_last + 1) % TX_DESCS; - - spin_unlock_bh(&tx_lock); - - config0 = FORCE_ROUTE; - if (skb->ip_summed == CHECKSUM_PARTIAL) - config0 |= UDP_CHECKSUM | TCP_CHECKSUM; - - len0 = skb->len; - - /* fragments */ - for (i = 0; i < nr_frags; i++) { - struct skb_frag_struct *frag; - void *addr; - - index = (index + 1) % TX_DESCS; - - frag = &skb_shinfo(skb)->frags[i]; - addr = page_address(skb_frag_page(frag)) + frag->page_offset; - - eth_set_desc(sw, tx_ring, index, index_last, addr, frag->size, - config0, pmap); - } - - if (nr_frags) - len0 = skb->len - skb->data_len; - - skb_walk_frags(skb, skb1) { - index = (index + 1) % TX_DESCS; - len0 -= skb1->len; - - eth_set_desc(sw, tx_ring, index, index_last, skb1->data, - skb1->len, config0, pmap); - } - - tx_ring->buff_tab[index0] = skb; - eth_set_desc(sw, tx_ring, index0, index_last, skb->data, len0, - config0 | FIRST_SEGMENT, pmap); - - wmb(); - - spin_lock(&tx_lock); - tx_ring->num_used += nr_desc + 1; - spin_unlock(&tx_lock); - - dev->stats.tx_packets++; - dev->stats.tx_bytes += skb->len; - - enable_tx_dma(sw); - - return NETDEV_TX_OK; -} - -static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) -{ - struct port *port = netdev_priv(dev); - - if (!netif_running(dev)) - return -EINVAL; - return phy_mii_ioctl(port->phydev, req, cmd); -} - -/* ethtool support */ - -static void cns3xxx_get_drvinfo(struct net_device *dev, - struct ethtool_drvinfo *info) -{ - strcpy(info->driver, DRV_NAME); - strcpy(info->bus_info, "internal"); -} - -static int cns3xxx_nway_reset(struct net_device *dev) -{ - struct port *port = netdev_priv(dev); - return phy_start_aneg(port->phydev); -} - -static struct ethtool_ops cns3xxx_ethtool_ops = { - .get_drvinfo = cns3xxx_get_drvinfo, - .get_link_ksettings = phy_ethtool_get_link_ksettings, - .set_link_ksettings = phy_ethtool_set_link_ksettings, - .nway_reset = cns3xxx_nway_reset, - .get_link = ethtool_op_get_link, -}; - - -static int init_rings(struct sw *sw) -{ - int i; - struct _rx_ring *rx_ring = &sw->rx_ring; - struct _tx_ring *tx_ring = &sw->tx_ring; - - __raw_writel(0, &sw->regs->fs_dma_ctrl0); - __raw_writel(TS_SUSPEND | FS_SUSPEND, &sw->regs->dma_auto_poll_cfg); - __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl); - __raw_writel(CLR_FS_STATE | QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl); - __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl); - - rx_ring->desc = dmam_alloc_coherent(sw->dev, RX_POOL_ALLOC_SIZE, - &rx_ring->phys_addr, GFP_KERNEL); - if (!rx_ring->desc) - return -ENOMEM; - - /* Setup RX buffers */ - memset(rx_ring->desc, 0, RX_POOL_ALLOC_SIZE); - - for (i = 0; i < RX_DESCS; i++) { - struct rx_desc *desc = &(rx_ring)->desc[i]; - void *buf; - - buf = netdev_alloc_frag(RX_SEGMENT_ALLOC_SIZE); - if (!buf) - return -ENOMEM; - - desc->sdl = RX_SEGMENT_MRU; - - if (i == (RX_DESCS - 1)) - desc->eor = 1; - - desc->fsd = 1; - desc->lsd = 1; - - desc->sdp = dma_map_single(sw->dev, buf + SKB_HEAD_ALIGN, - RX_SEGMENT_MRU, DMA_FROM_DEVICE); - - if (dma_mapping_error(sw->dev, desc->sdp)) - return -EIO; - - rx_ring->buff_tab[i] = buf; - rx_ring->phys_tab[i] = desc->sdp; - desc->cown = 0; - } - __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_ptr0); - __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_base_addr0); - - tx_ring->desc = dmam_alloc_coherent(sw->dev, TX_POOL_ALLOC_SIZE, - &tx_ring->phys_addr, GFP_KERNEL); - if (!tx_ring->desc) - return -ENOMEM; - - /* Setup TX buffers */ - memset(tx_ring->desc, 0, TX_POOL_ALLOC_SIZE); - - for (i = 0; i < TX_DESCS; i++) { - struct tx_desc *desc = &(tx_ring)->desc[i]; - tx_ring->buff_tab[i] = 0; - - if (i == (TX_DESCS - 1)) - desc->eor = 1; - - desc->cown = 1; - } - __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_ptr0); - __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_base_addr0); - - return 0; -} - -static void destroy_rings(struct sw *sw) -{ - int i; - - for (i = 0; i < RX_DESCS; i++) { - struct _rx_ring *rx_ring = &sw->rx_ring; - struct rx_desc *desc = &(rx_ring)->desc[i]; - void *buf = sw->rx_ring.buff_tab[i]; - - if (!buf) - continue; - - dma_unmap_single(sw->dev, desc->sdp, RX_SEGMENT_MRU, DMA_FROM_DEVICE); - skb_free_frag(buf); - } - - for (i = 0; i < TX_DESCS; i++) { - struct _tx_ring *tx_ring = &sw->tx_ring; - struct tx_desc *desc = &(tx_ring)->desc[i]; - struct sk_buff *skb = sw->tx_ring.buff_tab[i]; - - if (!skb) - continue; - - dma_unmap_single(sw->dev, desc->sdp, skb->len, DMA_TO_DEVICE); - dev_kfree_skb(skb); - } -} - -static int eth_open(struct net_device *dev) -{ - struct port *port = netdev_priv(dev); - struct sw *sw = port->sw; - u32 temp; - - port->speed = 0; /* force "link up" message */ - phy_start(port->phydev); - - netif_start_queue(dev); - - if (!ports_open) { - request_irq(sw->rx_irq, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev); - request_irq(sw->stat_irq, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev); - napi_enable(&sw->napi); - netif_start_queue(napi_dev); - - __raw_writel(~(MAC0_STATUS_CHANGE | MAC1_STATUS_CHANGE | MAC2_STATUS_CHANGE | - MAC0_RX_ERROR | MAC1_RX_ERROR | MAC2_RX_ERROR), &sw->regs->intr_mask); - - temp = __raw_readl(&sw->regs->mac_cfg[2]); - temp &= ~(PORT_DISABLE); - __raw_writel(temp, &sw->regs->mac_cfg[2]); - - temp = __raw_readl(&sw->regs->dma_auto_poll_cfg); - temp &= ~(TS_SUSPEND | FS_SUSPEND); - __raw_writel(temp, &sw->regs->dma_auto_poll_cfg); - - enable_rx_dma(sw); - } - temp = __raw_readl(&sw->regs->mac_cfg[port->id]); - temp &= ~(PORT_DISABLE); - __raw_writel(temp, &sw->regs->mac_cfg[port->id]); - - ports_open++; - netif_carrier_on(dev); - - return 0; -} - -static int eth_close(struct net_device *dev) -{ - struct port *port = netdev_priv(dev); - struct sw *sw = port->sw; - u32 temp; - - ports_open--; - - temp = __raw_readl(&sw->regs->mac_cfg[port->id]); - temp |= (PORT_DISABLE); - __raw_writel(temp, &sw->regs->mac_cfg[port->id]); - - netif_stop_queue(dev); - - phy_stop(port->phydev); - - if (!ports_open) { - disable_irq(sw->rx_irq); - free_irq(sw->rx_irq, napi_dev); - disable_irq(sw->stat_irq); - free_irq(sw->stat_irq, napi_dev); - napi_disable(&sw->napi); - netif_stop_queue(napi_dev); - temp = __raw_readl(&sw->regs->mac_cfg[2]); - temp |= (PORT_DISABLE); - __raw_writel(temp, &sw->regs->mac_cfg[2]); - - __raw_writel(TS_SUSPEND | FS_SUSPEND, - &sw->regs->dma_auto_poll_cfg); - } - - netif_carrier_off(dev); - return 0; -} - -static void eth_rx_mode(struct net_device *dev) -{ - struct port *port = netdev_priv(dev); - struct sw *sw = port->sw; - u32 temp; - - temp = __raw_readl(&sw->regs->mac_glob_cfg); - - if (dev->flags & IFF_PROMISC) { - if (port->id == 3) - temp |= ((1 << 2) << PROMISC_OFFSET); - else - temp |= ((1 << port->id) << PROMISC_OFFSET); - } else { - if (port->id == 3) - temp &= ~((1 << 2) << PROMISC_OFFSET); - else - temp &= ~((1 << port->id) << PROMISC_OFFSET); - } - __raw_writel(temp, &sw->regs->mac_glob_cfg); -} - -static int eth_set_mac(struct net_device *netdev, void *p) -{ - struct port *port = netdev_priv(netdev); - struct sw *sw = port->sw; - struct sockaddr *addr = p; - u32 cycles = 0; - - if (!is_valid_ether_addr(addr->sa_data)) - return -EADDRNOTAVAIL; - - /* Invalidate old ARL Entry */ - if (port->id == 3) - __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]); - else - __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]); - __raw_writel( ((netdev->dev_addr[0] << 24) | (netdev->dev_addr[1] << 16) | - (netdev->dev_addr[2] << 8) | (netdev->dev_addr[3])), - &sw->regs->arl_ctrl[1]); - - __raw_writel( ((netdev->dev_addr[4] << 24) | (netdev->dev_addr[5] << 16) | - (1 << 1)), - &sw->regs->arl_ctrl[2]); - __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd); - - while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0) - && cycles < 5000) { - udelay(1); - cycles++; - } - - cycles = 0; - memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); - - if (port->id == 3) - __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]); - else - __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]); - __raw_writel( ((addr->sa_data[0] << 24) | (addr->sa_data[1] << 16) | - (addr->sa_data[2] << 8) | (addr->sa_data[3])), - &sw->regs->arl_ctrl[1]); - - __raw_writel( ((addr->sa_data[4] << 24) | (addr->sa_data[5] << 16) | - (7 << 4) | (1 << 1)), &sw->regs->arl_ctrl[2]); - __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd); - - while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0) - && cycles < 5000) { - udelay(1); - cycles++; - } - return 0; -} - -static const struct net_device_ops cns3xxx_netdev_ops = { - .ndo_open = eth_open, - .ndo_stop = eth_close, - .ndo_start_xmit = eth_xmit, - .ndo_set_rx_mode = eth_rx_mode, - .ndo_do_ioctl = eth_ioctl, - .ndo_set_mac_address = eth_set_mac, - .ndo_validate_addr = eth_validate_addr, -}; - -static int eth_init_one(struct platform_device *pdev) -{ - int i; - struct port *port; - struct sw *sw; - struct net_device *dev; - struct cns3xxx_plat_info *plat = pdev->dev.platform_data; - char phy_id[MII_BUS_ID_SIZE + 3]; - int err; - u32 temp; - struct resource *res; - void __iomem *regs; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(regs)) - return PTR_ERR(regs); - - err = cns3xxx_mdio_register(regs); - if (err) - return err; - - if (!(napi_dev = alloc_etherdev(sizeof(struct sw)))) { - err = -ENOMEM; - goto err_remove_mdio; - } - - strcpy(napi_dev->name, "cns3xxx_eth"); - napi_dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST; - - SET_NETDEV_DEV(napi_dev, &pdev->dev); - sw = netdev_priv(napi_dev); - memset(sw, 0, sizeof(struct sw)); - sw->regs = regs; - sw->dev = &pdev->dev; - - sw->rx_irq = platform_get_irq_byname(pdev, "eth_rx"); - sw->stat_irq = platform_get_irq_byname(pdev, "eth_stat"); - - temp = __raw_readl(&sw->regs->phy_auto_addr); - temp |= (3 << 30); /* maximum frame length: 9600 bytes */ - __raw_writel(temp, &sw->regs->phy_auto_addr); - - for (i = 0; i < 4; i++) { - temp = __raw_readl(&sw->regs->mac_cfg[i]); - temp |= (PORT_DISABLE); - __raw_writel(temp, &sw->regs->mac_cfg[i]); - } - - temp = PORT_DISABLE; - __raw_writel(temp, &sw->regs->mac_cfg[2]); - - temp = __raw_readl(&sw->regs->vlan_cfg); - temp |= NIC_MODE | VLAN_UNAWARE; - __raw_writel(temp, &sw->regs->vlan_cfg); - - __raw_writel(UNKNOWN_VLAN_TO_CPU | - CRC_STRIPPING, &sw->regs->mac_glob_cfg); - - if ((err = init_rings(sw)) != 0) { - err = -ENOMEM; - goto err_free; - } - platform_set_drvdata(pdev, napi_dev); - - netif_napi_add(napi_dev, &sw->napi, eth_poll, NAPI_WEIGHT); - - for (i = 0; i < 3; i++) { - if (!(plat->ports & (1 << i))) { - continue; - } - - if (!(dev = alloc_etherdev(sizeof(struct port)))) { - goto free_ports; - } - - port = netdev_priv(dev); - port->netdev = dev; - if (i == 2) - port->id = 3; - else - port->id = i; - port->sw = sw; - - temp = __raw_readl(&sw->regs->mac_cfg[port->id]); - temp |= (PORT_DISABLE | PORT_BLOCK_STATE | PORT_LEARN_DIS); - __raw_writel(temp, &sw->regs->mac_cfg[port->id]); - - SET_NETDEV_DEV(dev, &pdev->dev); - dev->netdev_ops = &cns3xxx_netdev_ops; - dev->ethtool_ops = &cns3xxx_ethtool_ops; - dev->tx_queue_len = 1000; - dev->max_mtu = MAX_MTU; - dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST; - - switch_port_tab[port->id] = port; - memcpy(dev->dev_addr, &plat->hwaddr[i], ETH_ALEN); - - snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy[i]); - port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link, - PHY_INTERFACE_MODE_RGMII); - if ((err = IS_ERR(port->phydev))) { - switch_port_tab[port->id] = 0; - free_netdev(dev); - goto free_ports; - } - - port->phydev->irq = PHY_IGNORE_INTERRUPT; - - if ((err = register_netdev(dev))) { - phy_disconnect(port->phydev); - switch_port_tab[port->id] = 0; - free_netdev(dev); - goto free_ports; - } - - printk(KERN_INFO "%s: RGMII PHY %i on cns3xxx Switch\n", dev->name, plat->phy[i]); - netif_carrier_off(dev); - dev = 0; - } - - return 0; - -free_ports: - err = -ENOMEM; - for (--i; i >= 0; i--) { - if (switch_port_tab[i]) { - port = switch_port_tab[i]; - dev = port->netdev; - unregister_netdev(dev); - phy_disconnect(port->phydev); - switch_port_tab[i] = 0; - free_netdev(dev); - } - } -err_free: - free_netdev(napi_dev); -err_remove_mdio: - cns3xxx_mdio_remove(); - return err; -} - -static int eth_remove_one(struct platform_device *pdev) -{ - struct net_device *dev = platform_get_drvdata(pdev); - struct sw *sw = netdev_priv(dev); - int i; - - destroy_rings(sw); - for (i = 3; i >= 0; i--) { - if (switch_port_tab[i]) { - struct port *port = switch_port_tab[i]; - struct net_device *dev = port->netdev; - unregister_netdev(dev); - phy_disconnect(port->phydev); - switch_port_tab[i] = 0; - free_netdev(dev); - } - } - - free_netdev(napi_dev); - cns3xxx_mdio_remove(); - - return 0; -} - -static struct platform_driver cns3xxx_eth_driver = { - .driver.name = DRV_NAME, - .probe = eth_init_one, - .remove = eth_remove_one, -}; - -static int __init eth_init_module(void) -{ - return platform_driver_register(&cns3xxx_eth_driver); -} - -static void __exit eth_cleanup_module(void) -{ - platform_driver_unregister(&cns3xxx_eth_driver); -} - -module_init(eth_init_module); -module_exit(eth_cleanup_module); - -MODULE_AUTHOR("Chris Lang"); -MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:cns3xxx_eth"); diff --git a/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c b/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c deleted file mode 100644 index 63019862ee..0000000000 --- a/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c +++ /dev/null @@ -1,448 +0,0 @@ -/******************************************************************************* - * - * CNS3XXX SPI controller driver (master mode only) - * - * Copyright (c) 2008 Cavium Networks - * Copyright 2011 Gateworks Corporation - * Chris Lang - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or - * visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - * - ******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/* - * define access macros - */ -#define SPI_MEM_MAP_VALUE(reg_offset) (*((u32 volatile *)(hw->base + reg_offset))) - -#define SPI_CONFIGURATION_REG SPI_MEM_MAP_VALUE(0x00) -#define SPI_SERVICE_STATUS_REG SPI_MEM_MAP_VALUE(0x04) -#define SPI_BIT_RATE_CONTROL_REG SPI_MEM_MAP_VALUE(0x08) -#define SPI_TRANSMIT_CONTROL_REG SPI_MEM_MAP_VALUE(0x0C) -#define SPI_TRANSMIT_BUFFER_REG SPI_MEM_MAP_VALUE(0x10) -#define SPI_RECEIVE_CONTROL_REG SPI_MEM_MAP_VALUE(0x14) -#define SPI_RECEIVE_BUFFER_REG SPI_MEM_MAP_VALUE(0x18) -#define SPI_FIFO_TRANSMIT_CONFIG_REG SPI_MEM_MAP_VALUE(0x1C) -#define SPI_FIFO_TRANSMIT_CONTROL_REG SPI_MEM_MAP_VALUE(0x20) -#define SPI_FIFO_RECEIVE_CONFIG_REG SPI_MEM_MAP_VALUE(0x24) -#define SPI_INTERRUPT_STATUS_REG SPI_MEM_MAP_VALUE(0x28) -#define SPI_INTERRUPT_ENABLE_REG SPI_MEM_MAP_VALUE(0x2C) - -#define SPI_TRANSMIT_BUFFER_REG_ADDR (CNS3XXX_SSP_BASE +0x10) -#define SPI_RECEIVE_BUFFER_REG_ADDR (CNS3XXX_SSP_BASE +0x18) - -/* Structure for SPI controller of CNS3XXX SOCs */ -struct cns3xxx_spi { - /* bitbang has to be first */ - struct spi_bitbang bitbang; - struct completion done; - wait_queue_head_t wait; - - int len; - int count; - int last_in_message_list; - - /* data buffers */ - const unsigned char *tx; - unsigned char *rx; - - void __iomem *base; - struct spi_master *master; - struct platform_device *pdev; - struct device *dev; -}; - -static inline u8 cns3xxx_spi_bus_idle(struct cns3xxx_spi *hw) -{ - return ((SPI_SERVICE_STATUS_REG & 0x1) ? 0 : 1); -} - -static inline u8 cns3xxx_spi_tx_buffer_empty(struct cns3xxx_spi *hw) -{ - return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 3)) ? 1 : 0); -} - -static inline u8 cns3xxx_spi_rx_buffer_full(struct cns3xxx_spi *hw) -{ - return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 2)) ? 1 : 0); -} - -u8 cns3xxx_spi_tx_rx(struct cns3xxx_spi *hw, u8 tx_channel, u8 tx_eof, - u32 tx_data, u32 * rx_data) -{ - u8 rx_channel; - u8 rx_eof; - - while (!cns3xxx_spi_bus_idle(hw)) ; // do nothing - - while (!cns3xxx_spi_tx_buffer_empty(hw)) ; // do nothing - - SPI_TRANSMIT_CONTROL_REG &= ~(0x7); - SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2); - - SPI_TRANSMIT_BUFFER_REG = tx_data; - - while (!cns3xxx_spi_rx_buffer_full(hw)) ; // do nothing - - rx_channel = SPI_RECEIVE_CONTROL_REG & 0x3; - rx_eof = (SPI_RECEIVE_CONTROL_REG & (0x1 << 2)) ? 1 : 0; - - *rx_data = SPI_RECEIVE_BUFFER_REG; - - if ((tx_channel != rx_channel) || (tx_eof != rx_eof)) { - return 0; - } else { - return 1; - } -} - -u8 cns3xxx_spi_tx(struct cns3xxx_spi *hw, u8 tx_channel, u8 tx_eof, u32 tx_data) -{ - - while (!cns3xxx_spi_bus_idle(hw)) ; // do nothing - - while (!cns3xxx_spi_tx_buffer_empty(hw)) ; // do nothing - - SPI_TRANSMIT_CONTROL_REG &= ~(0x7); - SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2); - - SPI_TRANSMIT_BUFFER_REG = tx_data; - - return 1; -} - -static inline struct cns3xxx_spi *to_hw(struct spi_device *sdev) -{ - return spi_master_get_devdata(sdev->master); -} - -static int cns3xxx_spi_setup_transfer(struct spi_device *spi, - struct spi_transfer *t) -{ - return 0; -} - -static void cns3xxx_spi_chipselect(struct spi_device *spi, int value) -{ - struct cns3xxx_spi *hw = to_hw(spi); - unsigned int spi_config; - - switch (value) { - case BITBANG_CS_INACTIVE: - break; - - case BITBANG_CS_ACTIVE: - spi_config = SPI_CONFIGURATION_REG; - - if (spi->mode & SPI_CPHA) - spi_config |= (0x1 << 13); - else - spi_config &= ~(0x1 << 13); - - if (spi->mode & SPI_CPOL) - spi_config |= (0x1 << 14); - else - spi_config &= ~(0x1 << 14); - - /* write new configration */ - SPI_CONFIGURATION_REG = spi_config; - - SPI_TRANSMIT_CONTROL_REG &= ~(0x7); - SPI_TRANSMIT_CONTROL_REG |= (spi->chip_select & 0x3); - - break; - } -} - -static int cns3xxx_spi_setup(struct spi_device *spi) -{ - if (!spi->bits_per_word) - spi->bits_per_word = 8; - - return 0; -} - -static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t) -{ - struct cns3xxx_spi *hw = to_hw(spi); - - dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", t->tx_buf, t->rx_buf, - t->len); - - hw->tx = t->tx_buf; - hw->rx = t->rx_buf; - hw->len = t->len; - hw->count = 0; - hw->last_in_message_list = t->last_in_message_list; - - init_completion(&hw->done); - - if (hw->tx) { - int i; - u32 rx_data; - for (i = 0; i < (hw->len - 1); i++) { - dev_dbg(&spi->dev, - "[SPI_CNS3XXX_DEBUG] hw->tx[%02d]: 0x%02x\n", i, - hw->tx[i]); - cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, hw->tx[i], - &rx_data); - if (hw->rx) { - hw->rx[i] = rx_data; - dev_dbg(&spi->dev, - "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", - i, hw->rx[i]); - } - } - - if (t->last_in_message_list) { - cns3xxx_spi_tx_rx(hw, spi->chip_select, 1, hw->tx[i], - &rx_data); - if (hw->rx) { - hw->rx[i] = rx_data; - dev_dbg(&spi->dev, - "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", - i, hw->rx[i]); - } - } else { - cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, hw->tx[i], - &rx_data); - } - goto done; - } - - if (hw->rx) { - int i; - u32 rx_data; - for (i = 0; i < (hw->len - 1); i++) { - cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, 0xff, &rx_data); - hw->rx[i] = rx_data; - dev_dbg(&spi->dev, - "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", i, - hw->rx[i]); - } - - if (t->last_in_message_list) { - cns3xxx_spi_tx_rx(hw, spi->chip_select, 1, 0xff, &rx_data); - } else { - cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, 0xff, &rx_data); - } - hw->rx[i] = rx_data; - dev_dbg(&spi->dev, "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", - i, hw->rx[i]); - } -done: - return hw->len; -} - -static void __init cns3xxx_spi_initial(struct cns3xxx_spi *hw) -{ - SPI_CONFIGURATION_REG = (((0x0 & 0x3) << 0) | /* 8bits shift length */ - (0x0 << 9) | /* SPI mode */ - (0x0 << 10) | /* disable FIFO */ - (0x1 << 11) | /* SPI master mode */ - (0x0 << 12) | /* disable SPI loopback mode */ - (0x1 << 13) | /* clock phase */ - (0x1 << 14) | /* clock polarity */ - (0x0 << 24) | /* disable - SPI data swap */ - (0x1 << 29) | /* enable - 2IO Read mode */ - (0x0 << 30) | /* disable - SPI high speed read for system boot up */ - (0x0 << 31)); /* disable - SPI */ - - /* Set SPI bit rate PCLK/2 */ - SPI_BIT_RATE_CONTROL_REG = 0x1; - - /* Set SPI Tx channel 0 */ - SPI_TRANSMIT_CONTROL_REG = 0x0; - - /* Set Tx FIFO Threshold, Tx FIFO has 2 words */ - SPI_FIFO_TRANSMIT_CONFIG_REG &= ~(0x03 << 4); - SPI_FIFO_TRANSMIT_CONFIG_REG |= ((0x0 & 0x03) << 4); - - /* Set Rx FIFO Threshold, Rx FIFO has 2 words */ - SPI_FIFO_RECEIVE_CONFIG_REG &= ~(0x03 << 4); - SPI_FIFO_RECEIVE_CONFIG_REG |= ((0x0 & 0x03) << 4); - - /* Disable all interrupt */ - SPI_INTERRUPT_ENABLE_REG = 0x0; - - /* Clear spurious interrupt sources */ - SPI_INTERRUPT_STATUS_REG = (0x0F << 4); - - /* Enable SPI */ - SPI_CONFIGURATION_REG |= (0x1 << 31); - - return; -} - -static int cns3xxx_spi_probe(struct platform_device *pdev) -{ - struct spi_master *master; - struct cns3xxx_spi *hw; - struct resource *res; - int err = 0; - - printk("%s: setup CNS3XXX SPI Controller\n", __FUNCTION__); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENODEV; - - /* Allocate master with space for cns3xxx_spi */ - master = spi_alloc_master(&pdev->dev, sizeof(struct cns3xxx_spi)); - if (master == NULL) { - dev_err(&pdev->dev, "No memory for spi_master\n"); - err = -ENOMEM; - goto err_nomem; - } - - hw = spi_master_get_devdata(master); - memset(hw, 0, sizeof(struct cns3xxx_spi)); - - hw->master = spi_master_get(master); - hw->dev = &pdev->dev; - - hw->base = devm_ioremap_resource(hw->dev, res); - if (IS_ERR(hw->base)) { - dev_err(hw->dev, "Unable to map registers\n"); - err = PTR_ERR(hw->base); - goto err_register; - } - - platform_set_drvdata(pdev, hw); - init_completion(&hw->done); - - /* setup the master state. */ - - master->num_chipselect = 4; - master->bus_num = 1; - - /* setup the state for the bitbang driver */ - - hw->bitbang.master = hw->master; - hw->bitbang.setup_transfer = cns3xxx_spi_setup_transfer; - hw->bitbang.chipselect = cns3xxx_spi_chipselect; - hw->bitbang.txrx_bufs = cns3xxx_spi_txrx; - hw->bitbang.master->setup = cns3xxx_spi_setup; - - dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); - - /* SPI controller initializations */ - cns3xxx_spi_initial(hw); - - /* register SPI controller */ - - err = spi_bitbang_start(&hw->bitbang); - if (err) { - dev_err(&pdev->dev, "Failed to register SPI master\n"); - goto err_register; - } - - return 0; - -err_register: - spi_master_put(hw->master);; - -err_nomem: - return err; -} - -static int cns3xxx_spi_remove(struct platform_device *dev) -{ - struct cns3xxx_spi *hw = platform_get_drvdata(dev); - - platform_set_drvdata(dev, NULL); - - spi_unregister_master(hw->master); - - spi_master_put(hw->master); - return 0; -} - -#ifdef CONFIG_PM - -static int cns3xxx_spi_suspend(struct platform_device *pdev, pm_message_t msg) -{ - struct cns3xxx_spi *hw = platform_get_drvdata(pdev); - - return 0; -} - -static int cns3xxx_spi_resume(struct platform_device *pdev) -{ - struct cns3xxx_spi *hw = platform_get_drvdata(pdev); - - return 0; -} - -#else -#define cns3xxx_spi_suspend NULL -#define cns3xxx_spi_resume NULL -#endif - -static struct platform_driver cns3xxx_spi_driver = { - .probe = cns3xxx_spi_probe, - .remove = cns3xxx_spi_remove, - .suspend = cns3xxx_spi_suspend, - .resume = cns3xxx_spi_resume, - .driver = { - .name = "cns3xxx_spi", - .owner = THIS_MODULE, - }, -}; - -static int __init cns3xxx_spi_init(void) -{ - return platform_driver_register(&cns3xxx_spi_driver); -} - -static void __exit cns3xxx_spi_exit(void) -{ - platform_driver_unregister(&cns3xxx_spi_driver); -} - -module_init(cns3xxx_spi_init); -module_exit(cns3xxx_spi_exit); - -MODULE_AUTHOR("Cavium Networks"); -MODULE_DESCRIPTION("CNS3XXX SPI Controller Driver"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:cns3xxx_spi"); - -EXPORT_SYMBOL_GPL(cns3xxx_spi_tx_rx); diff --git a/target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h b/target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h deleted file mode 100644 index f286d0dfe9..0000000000 --- a/target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-cns3xxx/include/mach/platform.h - * - * Copyright 2011 Gateworks Corporation - * Chris Lang $(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.bin - $(call Image/Build/$(1),$(1)) - $(call BuildFirmware/Legacy,$(1),laguna_spi,$(LEGACY_SPI_KERNEL_SIZE)) - $(call BuildFirmware/Legacy,$(1),laguna_nor,$(LEGACY_NOR_KERNEL_SIZE)) -endef - -define Image/Build/squashfs - $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.bin) -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/cns3xxx/patches-4.19/000-cns3xxx_arch_include.patch b/target/linux/cns3xxx/patches-4.19/000-cns3xxx_arch_include.patch deleted file mode 100644 index 3ae759021a..0000000000 --- a/target/linux/cns3xxx/patches-4.19/000-cns3xxx_arch_include.patch +++ /dev/null @@ -1,9 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/Makefile -+++ b/arch/arm/mach-cns3xxx/Makefile -@@ -1,4 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0 -+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include -+ - obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o - cns3xxx-y += core.o pm.o - cns3xxx-$(CONFIG_ATAGS) += devices.o diff --git a/target/linux/cns3xxx/patches-4.19/001-arm_openwrt_machtypes.patch b/target/linux/cns3xxx/patches-4.19/001-arm_openwrt_machtypes.patch deleted file mode 100644 index f323deee47..0000000000 --- a/target/linux/cns3xxx/patches-4.19/001-arm_openwrt_machtypes.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/tools/mach-types -+++ b/arch/arm/tools/mach-types -@@ -449,6 +449,7 @@ gplugd MACH_GPLUGD GPLUGD 2625 - qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627 - mx23evk MACH_MX23EVK MX23EVK 2629 - ap4evb MACH_AP4EVB AP4EVB 2630 -+gw2388 MACH_GW2388 GW2388 2635 - mityomapl138 MACH_MITYOMAPL138 MITYOMAPL138 2650 - guruplug MACH_GURUPLUG GURUPLUG 2659 - spear310 MACH_SPEAR310 SPEAR310 2660 diff --git a/target/linux/cns3xxx/patches-4.19/010-arm_introduce-dma-fiq-irq-broadcast.patch b/target/linux/cns3xxx/patches-4.19/010-arm_introduce-dma-fiq-irq-broadcast.patch deleted file mode 100644 index 45f8feead4..0000000000 --- a/target/linux/cns3xxx/patches-4.19/010-arm_introduce-dma-fiq-irq-broadcast.patch +++ /dev/null @@ -1,80 +0,0 @@ ---- a/arch/arm/include/asm/glue-cache.h -+++ b/arch/arm/include/asm/glue-cache.h -@@ -156,9 +156,15 @@ static inline void nop_dma_unmap_area(co - #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) - #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) - #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) --#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) - --#define dmac_flush_range __glue(_CACHE,_dma_flush_range) -+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST -+# define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) -+# define dmac_flush_range __glue(_CACHE,_dma_flush_range) -+#else -+# define __cpuc_flush_dcache_area __glue(fiq,_flush_kern_dcache_area) -+# define dmac_flush_range __glue(fiq,_dma_flush_range) -+#endif -+ - #endif - - #endif ---- a/arch/arm/mm/Kconfig -+++ b/arch/arm/mm/Kconfig -@@ -916,6 +916,17 @@ config DMA_CACHE_RWFO - in hardware, other workarounds are needed (e.g. cache - maintenance broadcasting in software via FIQ). - -+config DMA_CACHE_FIQ_BROADCAST -+ bool "Enable fiq broadcast DMA cache maintenance" -+ depends on CPU_V6K && SMP -+ select FIQ -+ help -+ The Snoop Control Unit on ARM11MPCore does not detect the -+ cache maintenance operations and the dma_{map,unmap}_area() -+ functions may leave stale cache entries on other CPUs. By -+ enabling this option, fiq broadcast in the ARMv6 -+ DMA cache maintenance functions is performed. -+ - config OUTER_CACHE - bool - ---- a/arch/arm/mm/flush.c -+++ b/arch/arm/mm/flush.c -@@ -319,6 +319,7 @@ void __sync_icache_dcache(pte_t pteval) - void flush_dcache_page(struct page *page) - { - struct address_space *mapping; -+ bool skip_broadcast = true; - - /* - * The zero page is never written to, so never has any dirty -@@ -335,7 +336,10 @@ void flush_dcache_page(struct page *page - - mapping = page_mapping_file(page); - -- if (!cache_ops_need_broadcast() && -+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST -+ skip_broadcast = !cache_ops_need_broadcast(); -+#endif -+ if (skip_broadcast && - mapping && !page_mapcount(page)) - clear_bit(PG_dcache_clean, &page->flags); - else { ---- a/arch/arm/mm/dma.h -+++ b/arch/arm/mm/dma.h -@@ -5,8 +5,13 @@ - #include - - #ifndef MULTI_CACHE --#define dmac_map_area __glue(_CACHE,_dma_map_area) --#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) -+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST -+# define dmac_map_area __glue(_CACHE,_dma_map_area) -+# define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) -+#else -+# define dmac_map_area __glue(fiq,_dma_map_area) -+# define dmac_unmap_area __glue(fiq,_dma_unmap_area) -+#endif - - /* - * These are private to the dma-mapping API. Do not use directly. diff --git a/target/linux/cns3xxx/patches-4.19/020-watchdog_support.patch b/target/linux/cns3xxx/patches-4.19/020-watchdog_support.patch deleted file mode 100644 index e626ff29b7..0000000000 --- a/target/linux/cns3xxx/patches-4.19/020-watchdog_support.patch +++ /dev/null @@ -1,184 +0,0 @@ -Add a watchdog driver for ARM MPcore processors. - -Signed-off-by: Felix Fietkau ---- a/drivers/watchdog/Kconfig -+++ b/drivers/watchdog/Kconfig -@@ -375,6 +375,13 @@ config KS8695_WATCHDOG - Watchdog timer embedded into KS8695 processor. This will reboot your - system when the timeout is reached. - -+config MPCORE_WATCHDOG -+ tristate "MPcore watchdog" -+ depends on HAVE_ARM_TWD -+ select WATCHDOG_CORE -+ help -+ Watchdog timer embedded into the MPcore system -+ - config HAVE_S3C2410_WATCHDOG - bool - help ---- a/drivers/watchdog/Makefile -+++ b/drivers/watchdog/Makefile -@@ -49,6 +49,7 @@ obj-$(CONFIG_977_WATCHDOG) += wdt977.o - obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o - obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o - obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o -+obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o - obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o - obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o - obj-$(CONFIG_SAMA5D4_WATCHDOG) += sama5d4_wdt.o ---- /dev/null -+++ b/drivers/watchdog/mpcore_wdt.c -@@ -0,0 +1,118 @@ -+/* -+ * Watchdog driver for ARM MPcore -+ * -+ * Copyright (C) 2017 Felix Fietkau -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static void __iomem *wdt_base; -+static int wdt_timeout = 60; -+ -+static int mpcore_wdt_keepalive(struct watchdog_device *wdd) -+{ -+ static int perturb; -+ u32 count; -+ -+ count = (twd_timer_get_rate() / 256) * wdt_timeout; -+ -+ /* Reload register needs a different value on each refresh */ -+ count += perturb; -+ perturb = !perturb; -+ -+ iowrite32(count, wdt_base + TWD_WDOG_LOAD); -+ -+ return 0; -+} -+ -+static int mpcore_wdt_start(struct watchdog_device *wdd) -+{ -+ mpcore_wdt_keepalive(wdd); -+ -+ /* prescale = 256, mode = 1, enable = 1 */ -+ iowrite32(0x0000FF09, wdt_base + TWD_WDOG_CONTROL); -+ -+ return 0; -+} -+ -+static int mpcore_wdt_stop(struct watchdog_device *wdd) -+{ -+ iowrite32(0x12345678, wdt_base + TWD_WDOG_DISABLE); -+ iowrite32(0x87654321, wdt_base + TWD_WDOG_DISABLE); -+ iowrite32(0x0, wdt_base + TWD_WDOG_CONTROL); -+ -+ return 0; -+} -+ -+static int mpcore_wdt_set_timeout(struct watchdog_device *wdd, -+ unsigned int timeout) -+{ -+ mpcore_wdt_stop(wdd); -+ wdt_timeout = timeout; -+ mpcore_wdt_start(wdd); -+ -+ return 0; -+} -+ -+static const struct watchdog_info mpcore_wdt_info = { -+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, -+ .identity = "MPcore Watchdog", -+}; -+ -+static const struct watchdog_ops mpcore_wdt_ops = { -+ .owner = THIS_MODULE, -+ .start = mpcore_wdt_start, -+ .stop = mpcore_wdt_stop, -+ .ping = mpcore_wdt_keepalive, -+ .set_timeout = mpcore_wdt_set_timeout, -+}; -+ -+static struct watchdog_device mpcore_wdt = { -+ .info = &mpcore_wdt_info, -+ .ops = &mpcore_wdt_ops, -+ .min_timeout = 1, -+ .max_timeout = 65535, -+}; -+ -+static int mpcore_wdt_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ unsigned long rate = twd_timer_get_rate(); -+ -+ pr_info("MPCore WD init. clockrate: %lu prescaler: %u countrate: %lu timeout: %us\n", rate, 256, rate / 256, wdt_timeout); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) -+ return -ENODEV; -+ -+ wdt_base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(wdt_base)) -+ return PTR_ERR(wdt_base); -+ -+ watchdog_register_device(&mpcore_wdt); -+ return 0; -+} -+ -+static int mpcore_wdt_remove(struct platform_device *dev) -+{ -+ watchdog_unregister_device(&mpcore_wdt); -+ return 0; -+} -+ -+static struct platform_driver mpcore_wdt_driver = { -+ .probe = mpcore_wdt_probe, -+ .remove = mpcore_wdt_remove, -+ .driver = { -+ .name = "mpcore_wdt", -+ }, -+}; -+ -+module_platform_driver(mpcore_wdt_driver); -+MODULE_AUTHOR("Felix Fietkau "); -+MODULE_LICENSE("GPL"); ---- a/arch/arm/include/asm/smp_twd.h -+++ b/arch/arm/include/asm/smp_twd.h -@@ -34,5 +34,6 @@ struct twd_local_timer name __initdata = - }; - - int twd_local_timer_register(struct twd_local_timer *); -+unsigned long twd_timer_get_rate(void); - - #endif ---- a/arch/arm/kernel/smp_twd.c -+++ b/arch/arm/kernel/smp_twd.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -380,6 +381,14 @@ int __init twd_local_timer_register(stru - return twd_local_timer_common_register(NULL); - } - -+/* Needed by mpcore_wdt */ -+unsigned long twd_timer_get_rate(void) -+{ -+ return twd_timer_rate; -+} -+EXPORT_SYMBOL_GPL(twd_timer_get_rate); -+ -+ - #ifdef CONFIG_OF - static int __init twd_local_timer_of_register(struct device_node *np) - { diff --git a/target/linux/cns3xxx/patches-4.19/025-smp_support.patch b/target/linux/cns3xxx/patches-4.19/025-smp_support.patch deleted file mode 100644 index dc8e4b03c2..0000000000 --- a/target/linux/cns3xxx/patches-4.19/025-smp_support.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/Makefile -+++ b/arch/arm/mach-cns3xxx/Makefile -@@ -6,3 +6,5 @@ cns3xxx-y += core.o pm.o - cns3xxx-$(CONFIG_ATAGS) += devices.o - cns3xxx-$(CONFIG_PCI) += pcie.o - cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o -+cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o -+cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o ---- a/arch/arm/mach-cns3xxx/Kconfig -+++ b/arch/arm/mach-cns3xxx/Kconfig -@@ -3,6 +3,9 @@ menuconfig ARCH_CNS3XXX - bool "Cavium Networks CNS3XXX family" - depends on ARCH_MULTI_V6 - select ARM_GIC -+ select HAVE_ARM_SCU if SMP -+ select HAVE_ARM_TWD -+ select HAVE_SMP - help - Support for Cavium Networks CNS3XXX platform. - ---- a/arch/arm/mach-cns3xxx/core.h -+++ b/arch/arm/mach-cns3xxx/core.h -@@ -13,6 +13,7 @@ - - #include - -+extern struct smp_operations cns3xxx_smp_ops; - extern void cns3xxx_timer_init(void); - - #ifdef CONFIG_CACHE_L2X0 diff --git a/target/linux/cns3xxx/patches-4.19/030-pcie_clock.patch b/target/linux/cns3xxx/patches-4.19/030-pcie_clock.patch deleted file mode 100644 index 66c3a99ae1..0000000000 --- a/target/linux/cns3xxx/patches-4.19/030-pcie_clock.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/pcie.c -+++ b/arch/arm/mach-cns3xxx/pcie.c -@@ -281,8 +281,6 @@ void __init cns3xxx_pcie_init_late(void) - "imprecise external abort"); - - for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { -- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i)); -- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); - cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); - cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); - private_data = &cns3xxx_pcie[i]; diff --git a/target/linux/cns3xxx/patches-4.19/040-fiq_support.patch b/target/linux/cns3xxx/patches-4.19/040-fiq_support.patch deleted file mode 100644 index bee8c1ef24..0000000000 --- a/target/linux/cns3xxx/patches-4.19/040-fiq_support.patch +++ /dev/null @@ -1,40 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/Kconfig -+++ b/arch/arm/mach-cns3xxx/Kconfig -@@ -6,6 +6,7 @@ menuconfig ARCH_CNS3XXX - select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD - select HAVE_SMP -+ select FIQ - help - Support for Cavium Networks CNS3XXX platform. - ---- a/arch/arm/mach-cns3xxx/Makefile -+++ b/arch/arm/mach-cns3xxx/Makefile -@@ -6,5 +6,5 @@ cns3xxx-y += core.o pm.o - cns3xxx-$(CONFIG_ATAGS) += devices.o - cns3xxx-$(CONFIG_PCI) += pcie.o - cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o --cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o -+cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o - cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o ---- a/arch/arm/mach-cns3xxx/cns3xxx.h -+++ b/arch/arm/mach-cns3xxx/cns3xxx.h -@@ -261,6 +261,7 @@ - #define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) - #define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) - -+#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4) - /* - * Power management and clock control - */ ---- a/arch/arm/mm/Kconfig -+++ b/arch/arm/mm/Kconfig -@@ -899,7 +899,7 @@ config VDSO - - config DMA_CACHE_RWFO - bool "Enable read/write for ownership DMA cache maintenance" -- depends on CPU_V6K && SMP -+ depends on CPU_V6K && SMP && !ARCH_CNS3XXX - default y - help - The Snoop Control Unit on ARM11MPCore does not detect the diff --git a/target/linux/cns3xxx/patches-4.19/045-twd_base.patch b/target/linux/cns3xxx/patches-4.19/045-twd_base.patch deleted file mode 100644 index e722b01bbc..0000000000 --- a/target/linux/cns3xxx/patches-4.19/045-twd_base.patch +++ /dev/null @@ -1,43 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/core.c -+++ b/arch/arm/mach-cns3xxx/core.c -@@ -17,6 +17,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -26,6 +27,8 @@ - #include "core.h" - #include "pm.h" - -+#define IRQ_LOCALTIMER 29 -+ - static struct map_desc cns3xxx_io_desc[] __initdata = { - { - .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT, -@@ -198,6 +201,15 @@ static struct irqaction cns3xxx_timer_ir - .handler = cns3xxx_timer_interrupt, - }; - -+static void __init cns3xxx_init_twd(void) -+{ -+ static DEFINE_TWD_LOCAL_TIMER(cns3xx_twd_local_timer, -+ CNS3XXX_TC11MP_TWD_BASE, -+ IRQ_LOCALTIMER); -+ -+ twd_local_timer_register(&cns3xx_twd_local_timer); -+} -+ - /* - * Set up the clock source and clock events devices - */ -@@ -251,6 +263,7 @@ static void __init __cns3xxx_timer_init( - setup_irq(timer_irq, &cns3xxx_timer_irq); - - cns3xxx_clockevents_init(timer_irq); -+ cns3xxx_init_twd(); - } - - void __init cns3xxx_timer_init(void) diff --git a/target/linux/cns3xxx/patches-4.19/055-pcie_io.patch b/target/linux/cns3xxx/patches-4.19/055-pcie_io.patch deleted file mode 100644 index 4680853e6e..0000000000 --- a/target/linux/cns3xxx/patches-4.19/055-pcie_io.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/core.c -+++ b/arch/arm/mach-cns3xxx/core.c -@@ -81,6 +81,16 @@ static struct map_desc cns3xxx_io_desc[] - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE), - .length = SZ_16M, - .type = MT_DEVICE, -+ }, { -+ .virtual = CNS3XXX_PCIE0_IO_BASE_VIRT, -+ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE), -+ .length = SZ_16M, -+ .type = MT_DEVICE, -+ }, { -+ .virtual = CNS3XXX_PCIE1_IO_BASE_VIRT, -+ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE), -+ .length = SZ_16M, -+ .type = MT_DEVICE, - #endif - }, - }; diff --git a/target/linux/cns3xxx/patches-4.19/060-pcie_abort.patch b/target/linux/cns3xxx/patches-4.19/060-pcie_abort.patch deleted file mode 100644 index 87b1526c3a..0000000000 --- a/target/linux/cns3xxx/patches-4.19/060-pcie_abort.patch +++ /dev/null @@ -1,109 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/pcie.c -+++ b/arch/arm/mach-cns3xxx/pcie.c -@@ -86,6 +86,79 @@ static void __iomem *cns3xxx_pci_map_bus - return base + where + (devfn << 12); - } - -+static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where) -+{ -+ struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); -+ -+ /* check PCI-compatible status register after access */ -+ if (cnspci->linked) { -+ void __iomem *host_base; -+ u32 sreg, ereg; -+ -+ host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual; -+ sreg = __raw_readw(host_base + 0x6) & 0xF900; -+ ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg -+ -+ if (sreg | ereg) { -+ /* SREG: -+ * BIT15 - Detected Parity Error -+ * BIT14 - Signaled System Error -+ * BIT13 - Received Master Abort -+ * BIT12 - Received Target Abort -+ * BIT11 - Signaled Target Abort -+ * BIT08 - Master Data Parity Error -+ * -+ * EREG: -+ * BIT20 - Unsupported Request -+ * BIT19 - ECRC -+ * BIT18 - Malformed TLP -+ * BIT17 - Receiver Overflow -+ * BIT16 - Unexpected Completion -+ * BIT15 - Completer Abort -+ * BIT14 - Completion Timeout -+ * BIT13 - Flow Control Protocol Error -+ * BIT12 - Poisoned TLP -+ * BIT04 - Data Link Protocol Error -+ * -+ * TODO: see Documentation/pci-error-recovery.txt -+ * implement error_detected handler -+ */ -+/* -+ printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg); -+ if (sreg & BIT(15)) printk(" SERR"); -+ if (sreg & BIT(13)) printk(" TABRT"); -+ if (sreg & BIT( 8)) printk(" MPERR"); -+ -+ if (ereg & BIT(20)) printk(" Unsup"); -+ if (ereg & BIT(19)) printk(" ECRC"); -+ if (ereg & BIT(18)) printk(" MTLP"); -+ if (ereg & BIT(17)) printk(" OFLOW"); -+ if (ereg & BIT(16)) printk(" Unex"); -+ if (ereg & BIT(15)) printk(" ABRT"); -+ if (ereg & BIT(14)) printk(" COMPTO"); -+ if (ereg & BIT(13)) printk(" FLOW"); -+ if (ereg & BIT(12)) printk(" PTLP"); -+ if (ereg & BIT( 4)) printk(" DLINK"); -+ printk("\n"); -+*/ -+ pr_debug("%s failed port%d sreg=0x%04x\n", __func__, -+ pci_domain_nr(bus), sreg); -+ -+ /* make sure the status bits are reset */ -+ __raw_writew(sreg, host_base + 6); -+ __raw_writel(ereg, host_base + 0x104); -+ return 1; -+ } -+ } -+ else -+ return 1; -+ -+ return 0; -+} -+ - static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) - { -@@ -95,6 +168,11 @@ static int cns3xxx_pci_read_config(struc - - ret = pci_generic_config_read(bus, devfn, where, size, val); - -+ if (check_master_abort(bus, devfn, where)) { -+ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ } -+ - if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn && - (where & 0xffc) == PCI_CLASS_REVISION) - /* -@@ -257,8 +335,14 @@ static void __init cns3xxx_pcie_hw_init( - static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr, - struct pt_regs *regs) - { -+#if 0 -+/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE -+ * ignore imprecise aborts and use PCI-compatible Status register to -+ * determine errors instead -+ */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; -+#endif - return 0; - } - diff --git a/target/linux/cns3xxx/patches-4.19/065-pcie_skip_inactive.patch b/target/linux/cns3xxx/patches-4.19/065-pcie_skip_inactive.patch deleted file mode 100644 index b8b5f273a1..0000000000 --- a/target/linux/cns3xxx/patches-4.19/065-pcie_skip_inactive.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/pcie.c -+++ b/arch/arm/mach-cns3xxx/pcie.c -@@ -366,6 +366,8 @@ void __init cns3xxx_pcie_init_late(void) - - for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { - cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); -+ if (!cns3xxx_pcie[i].linked) -+ continue; - cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); - private_data = &cns3xxx_pcie[i]; - pci_common_init(&hw_pci); diff --git a/target/linux/cns3xxx/patches-4.19/070-i2c_support.patch b/target/linux/cns3xxx/patches-4.19/070-i2c_support.patch deleted file mode 100644 index 95768f64a8..0000000000 --- a/target/linux/cns3xxx/patches-4.19/070-i2c_support.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -460,6 +460,18 @@ config I2C_CBUS_GPIO - This driver can also be built as a module. If so, the module - will be called i2c-cbus-gpio. - -+config I2C_CNS3XXX -+ tristate "Cavium CNS3xxx I2C driver" -+ depends on ARCH_CNS3XXX -+ help -+ Support for Cavium CNS3xxx I2C controller driver. -+ -+ This driver can also be built as a module. If so, the module -+ will be called i2c-cns3xxx. -+ -+ Please note that this driver might be needed to bring up other -+ devices such as Cavium CNS3xxx Ethernet. -+ - config I2C_CPM - tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)" - depends on CPM1 || CPM2 ---- a/drivers/i2c/busses/Makefile -+++ b/drivers/i2c/busses/Makefile -@@ -131,6 +131,7 @@ obj-$(CONFIG_I2C_VIPERBOARD) += i2c-vipe - obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o - obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o - obj-$(CONFIG_I2C_BRCMSTB) += i2c-brcmstb.o -+obj-$(CONFIG_I2C_CNS3XXX) += i2c-cns3xxx.o - obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-cros-ec-tunnel.o - obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o - obj-$(CONFIG_I2C_MLXCPLD) += i2c-mlxcpld.o diff --git a/target/linux/cns3xxx/patches-4.19/075-spi_support.patch b/target/linux/cns3xxx/patches-4.19/075-spi_support.patch deleted file mode 100644 index afa6d862df..0000000000 --- a/target/linux/cns3xxx/patches-4.19/075-spi_support.patch +++ /dev/null @@ -1,51 +0,0 @@ ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -181,6 +181,13 @@ config SPI_CLPS711X - This enables dedicated general purpose SPI/Microwire1-compatible - master mode interface (SSI1) for CLPS711X-based CPUs. - -+config SPI_CNS3XXX -+ tristate "CNS3XXX SPI controller" -+ depends on ARCH_CNS3XXX && SPI_MASTER -+ select SPI_BITBANG -+ help -+ This enables using the CNS3XXX SPI controller in master mode. -+ - config SPI_COLDFIRE_QSPI - tristate "Freescale Coldfire QSPI controller" - depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x) ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -28,6 +28,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi-bitban - obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o - obj-$(CONFIG_SPI_CADENCE) += spi-cadence.o - obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o -+obj-$(CONFIG_SPI_CNS3XXX) += spi-cns3xxx.o - obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o - obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o - obj-$(CONFIG_SPI_DLN2) += spi-dln2.o ---- a/include/linux/spi/spi.h -+++ b/include/linux/spi/spi.h -@@ -795,6 +795,10 @@ struct spi_transfer { - u32 speed_hz; - - struct list_head transfer_list; -+ -+#ifdef CONFIG_ARCH_CNS3XXX -+ unsigned last_in_message_list; -+#endif - }; - - /** ---- a/drivers/spi/spi.c -+++ b/drivers/spi/spi.c -@@ -1020,6 +1020,9 @@ static int spi_transfer_one_message(stru - list_for_each_entry(xfer, &msg->transfers, transfer_list) { - trace_spi_transfer_start(msg, xfer); - -+ xfer->last_in_message_list = -+ list_is_last(&xfer->transfer_list, &msg->transfers); -+ - spi_statistics_add_transfer_stats(statm, xfer, ctlr); - spi_statistics_add_transfer_stats(stats, xfer, ctlr); - diff --git a/target/linux/cns3xxx/patches-4.19/080-sata_support.patch b/target/linux/cns3xxx/patches-4.19/080-sata_support.patch deleted file mode 100644 index 65a5275bec..0000000000 --- a/target/linux/cns3xxx/patches-4.19/080-sata_support.patch +++ /dev/null @@ -1,40 +0,0 @@ ---- a/drivers/ata/ahci_platform.c -+++ b/drivers/ata/ahci_platform.c -@@ -44,11 +44,18 @@ static struct scsi_host_template ahci_pl - AHCI_SHT(DRV_NAME), - }; - -+static const struct ata_port_info cns3xxx_port_info = { -+ .flags = AHCI_FLAG_COMMON, -+ .pio_mask = ATA_PIO4, -+ .udma_mask = ATA_UDMA6, -+ .port_ops = &ahci_pmp_retry_srst_ops, -+}; -+ - static int ahci_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; - struct ahci_host_priv *hpriv; -- const struct ata_port_info *port; -+ const struct ata_port_info *port = &ahci_port_info; - int rc; - - hpriv = ahci_platform_get_resources(pdev, -@@ -66,9 +73,14 @@ static int ahci_probe(struct platform_de - if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci")) - hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ; - -- port = acpi_device_get_match_data(dev); -- if (!port) -- port = &ahci_port_info; -+ if (IS_ENABLED(CONFIG_ARCH_CNS3XXX)) { -+ port = &cns3xxx_port_info; -+ } -+ else { -+ port = acpi_device_get_match_data(dev); -+ if (!port) -+ port = &ahci_port_info; -+ } - - rc = ahci_platform_init_host(pdev, hpriv, port, - &ahci_platform_sht); diff --git a/target/linux/cns3xxx/patches-4.19/090-timers.patch b/target/linux/cns3xxx/patches-4.19/090-timers.patch deleted file mode 100644 index b3810f8c9b..0000000000 --- a/target/linux/cns3xxx/patches-4.19/090-timers.patch +++ /dev/null @@ -1,105 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/core.c -+++ b/arch/arm/mach-cns3xxx/core.c -@@ -138,6 +138,7 @@ static int cns3xxx_set_oneshot(struct cl - - /* period set, and timer enabled in 'next_event' hook */ - ctrl |= (1 << 2) | (1 << 9); -+ writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); - writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - return 0; - } -@@ -148,7 +149,7 @@ static int cns3xxx_set_periodic(struct c - int pclk = cns3xxx_cpu_clock() / 8; - int reload; - -- reload = pclk * 20 / (3 * HZ) * 0x25000; -+ reload = pclk * 1000000 / HZ; - writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); - ctrl |= (1 << 0) | (1 << 2) | (1 << 9); - writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); -@@ -175,8 +176,8 @@ static struct clock_event_device cns3xxx - .set_state_oneshot = cns3xxx_set_oneshot, - .tick_resume = cns3xxx_shutdown, - .set_next_event = cns3xxx_timer_set_next_event, -- .rating = 350, -- .cpumask = cpu_all_mask, -+ .rating = 300, -+ .cpumask = cpu_possible_mask, - }; - - static void __init cns3xxx_clockevents_init(unsigned int timer_irq) -@@ -220,6 +221,32 @@ static void __init cns3xxx_init_twd(void - twd_local_timer_register(&cns3xx_twd_local_timer); - } - -+static u64 cns3xxx_get_cycles(struct clocksource *cs) -+{ -+ u64 val; -+ -+ val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); -+ val &= 0xffff; -+ -+ return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET)); -+} -+ -+static struct clocksource clocksource_cns3xxx = { -+ .name = "freerun", -+ .rating = 200, -+ .read = cns3xxx_get_cycles, -+ .mask = CLOCKSOURCE_MASK(48), -+ .flags = CLOCK_SOURCE_IS_CONTINUOUS, -+}; -+ -+static void __init cns3xxx_clocksource_init(void) -+{ -+ /* Reset the FreeRunning counter */ -+ writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); -+ -+ clocksource_register_khz(&clocksource_cns3xxx, 100); -+} -+ - /* - * Set up the clock source and clock events devices - */ -@@ -237,13 +264,12 @@ static void __init __cns3xxx_timer_init( - /* stop free running timer3 */ - writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); - -- /* timer1 */ -- writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); -- writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); -- - writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); - writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); - -+ val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ; -+ writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); -+ - /* mask irq, non-mask timer1 overflow */ - irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - irq_mask &= ~(1 << 2); -@@ -255,23 +281,9 @@ static void __init __cns3xxx_timer_init( - val |= (1 << 9); - writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - -- /* timer2 */ -- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); -- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); -- -- /* mask irq */ -- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); -- irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5)); -- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); -- -- /* down counter */ -- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); -- val |= (1 << 10); -- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); -- -- /* Make irqs happen for the system timer */ - setup_irq(timer_irq, &cns3xxx_timer_irq); - -+ cns3xxx_clocksource_init(); - cns3xxx_clockevents_init(timer_irq); - cns3xxx_init_twd(); - } diff --git a/target/linux/cns3xxx/patches-4.19/093-add-virt-pci-io-mapping.patch b/target/linux/cns3xxx/patches-4.19/093-add-virt-pci-io-mapping.patch deleted file mode 100644 index 0fa7ed483f..0000000000 --- a/target/linux/cns3xxx/patches-4.19/093-add-virt-pci-io-mapping.patch +++ /dev/null @@ -1,41 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/cns3xxx.h -+++ b/arch/arm/mach-cns3xxx/cns3xxx.h -@@ -162,11 +162,13 @@ - #define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ - - #define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ -+#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 - - #define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ - #define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000 - - #define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */ -+#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000 - - #define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */ - #define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000 -@@ -175,13 +177,16 @@ - #define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000 - - #define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */ -+#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000 - - #define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */ -+#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000 - - #define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */ - #define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000 - - #define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */ -+#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000 - - #define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */ - #define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000 -@@ -190,6 +195,7 @@ - #define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000 - - #define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */ -+#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000 - - /* - * Testchip peripheral and fpga gic regions diff --git a/target/linux/cns3xxx/patches-4.19/095-gpio_support.patch b/target/linux/cns3xxx/patches-4.19/095-gpio_support.patch deleted file mode 100644 index 8345f2f144..0000000000 --- a/target/linux/cns3xxx/patches-4.19/095-gpio_support.patch +++ /dev/null @@ -1,67 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/cns3420vb.c -+++ b/arch/arm/mach-cns3xxx/cns3420vb.c -@@ -223,6 +223,10 @@ static void __init cns3420_init(void) - - cns3xxx_ahci_init(); - cns3xxx_sdhci_init(); -+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA, -+ NR_IRQS_CNS3XXX); -+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB, -+ NR_IRQS_CNS3XXX + 32); - - pm_power_off = cns3xxx_power_off; - } ---- a/arch/arm/mach-cns3xxx/Kconfig -+++ b/arch/arm/mach-cns3xxx/Kconfig -@@ -3,6 +3,8 @@ menuconfig ARCH_CNS3XXX - bool "Cavium Networks CNS3XXX family" - depends on ARCH_MULTI_V6 - select ARM_GIC -+ select ARCH_REQUIRE_GPIOLIB -+ select GENERIC_IRQ_CHIP - select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD - select HAVE_SMP ---- a/arch/arm/mach-cns3xxx/Makefile -+++ b/arch/arm/mach-cns3xxx/Makefile -@@ -2,7 +2,7 @@ - ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include - - obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o --cns3xxx-y += core.o pm.o -+cns3xxx-y += core.o pm.o gpio.o - cns3xxx-$(CONFIG_ATAGS) += devices.o - cns3xxx-$(CONFIG_PCI) += pcie.o - cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o ---- a/arch/arm/mach-cns3xxx/cns3xxx.h -+++ b/arch/arm/mach-cns3xxx/cns3xxx.h -@@ -68,8 +68,10 @@ - #define SMC_PCELL_ID_3_OFFSET 0xFFC - - #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ -+#define CNS3XXX_GPIOA_BASE_VIRT 0xFB006000 - - #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ -+#define CNS3XXX_GPIOB_BASE_VIRT 0xFB007000 - - #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ - ---- a/arch/arm/mach-cns3xxx/core.c -+++ b/arch/arm/mach-cns3xxx/core.c -@@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[] - .pfn = __phys_to_pfn(CNS3XXX_PM_BASE), - .length = SZ_4K, - .type = MT_DEVICE, -+ }, { -+ .virtual = CNS3XXX_GPIOA_BASE_VIRT, -+ .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE, -+ }, { -+ .virtual = CNS3XXX_GPIOB_BASE_VIRT, -+ .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE, - #ifdef CONFIG_PCI - }, { - .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT, diff --git a/target/linux/cns3xxx/patches-4.19/097-l2x0_cmdline_disable.patch b/target/linux/cns3xxx/patches-4.19/097-l2x0_cmdline_disable.patch deleted file mode 100644 index b4720b11de..0000000000 --- a/target/linux/cns3xxx/patches-4.19/097-l2x0_cmdline_disable.patch +++ /dev/null @@ -1,69 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/core.c -+++ b/arch/arm/mach-cns3xxx/core.c -@@ -307,13 +307,26 @@ void __init cns3xxx_timer_init(void) - - #ifdef CONFIG_CACHE_L2X0 - --void __init cns3xxx_l2x0_init(void) -+static int cns3xxx_l2x0_enable = 1; -+ -+static int __init cns3xxx_l2x0_disable(char *s) -+{ -+ cns3xxx_l2x0_enable = 0; -+ return 1; -+} -+__setup("nol2x0", cns3xxx_l2x0_disable); -+ -+static int __init cns3xxx_l2x0_init(void) - { -- void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); -+ void __iomem *base; - u32 val; - -+ if (!cns3xxx_l2x0_enable) -+ return 0; -+ -+ base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); - if (WARN_ON(!base)) -- return; -+ return 0; - - /* - * Tag RAM Control register -@@ -343,7 +356,10 @@ void __init cns3xxx_l2x0_init(void) - - /* 32 KiB, 8-way, parity disable */ - l2x0_init(base, 0x00500000, 0xfe0f0fff); -+ -+ return 0; - } -+arch_initcall(cns3xxx_l2x0_init); - - #endif /* CONFIG_CACHE_L2X0 */ - ---- a/arch/arm/mach-cns3xxx/cns3420vb.c -+++ b/arch/arm/mach-cns3xxx/cns3420vb.c -@@ -217,8 +217,6 @@ static struct platform_device *cns3420_p - - static void __init cns3420_init(void) - { -- cns3xxx_l2x0_init(); -- - platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); - - cns3xxx_ahci_init(); ---- a/arch/arm/mach-cns3xxx/core.h -+++ b/arch/arm/mach-cns3xxx/core.h -@@ -16,12 +16,6 @@ - extern struct smp_operations cns3xxx_smp_ops; - extern void cns3xxx_timer_init(void); - --#ifdef CONFIG_CACHE_L2X0 --void __init cns3xxx_l2x0_init(void); --#else --static inline void cns3xxx_l2x0_init(void) {} --#endif /* CONFIG_CACHE_L2X0 */ -- - #ifdef CONFIG_PCI - extern void __init cns3xxx_pcie_init_late(void); - #else diff --git a/target/linux/cns3xxx/patches-4.19/100-laguna_support.patch b/target/linux/cns3xxx/patches-4.19/100-laguna_support.patch deleted file mode 100644 index c0160d8f12..0000000000 --- a/target/linux/cns3xxx/patches-4.19/100-laguna_support.patch +++ /dev/null @@ -1,46 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/Kconfig -+++ b/arch/arm/mach-cns3xxx/Kconfig -@@ -23,4 +23,12 @@ config MACH_CNS3420VB - This is a platform with an on-board ARM11 MPCore and has support - for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc. - -+config MACH_GW2388 -+ bool "Support for Gateworks Laguna Platform" -+ help -+ Include support for the Gateworks Laguna Platform -+ -+ This is a platform with an on-board ARM11 MPCore and has support -+ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc. -+ - endif ---- a/arch/arm/mach-cns3xxx/Makefile -+++ b/arch/arm/mach-cns3xxx/Makefile -@@ -8,3 +8,5 @@ cns3xxx-$(CONFIG_PCI) += pcie.o - cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o - cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o - cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o -+cns3xxx-$(CONFIG_MACH_GW2388) += laguna.o -+ ---- a/arch/arm/mach-cns3xxx/devices.c -+++ b/arch/arm/mach-cns3xxx/devices.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include "cns3xxx.h" - #include "pm.h" - #include "core.h" -@@ -101,7 +102,11 @@ void __init cns3xxx_sdhci_init(void) - u32 gpioa_pins = __raw_readl(gpioa); - - /* MMC/SD pins share with GPIOA */ -- gpioa_pins |= 0x1fff0004; -+ if (machine_is_gw2388()) { -+ gpioa_pins |= 0x1fff0000; -+ } else { -+ gpioa_pins |= 0x1fff0004; -+ } - __raw_writel(gpioa_pins, gpioa); - - cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); diff --git a/target/linux/cns3xxx/patches-4.19/101-laguna_sdhci_card_detect.patch b/target/linux/cns3xxx/patches-4.19/101-laguna_sdhci_card_detect.patch deleted file mode 100644 index 72648a5f9f..0000000000 --- a/target/linux/cns3xxx/patches-4.19/101-laguna_sdhci_card_detect.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/drivers/mmc/host/sdhci-cns3xxx.c -+++ b/drivers/mmc/host/sdhci-cns3xxx.c -@@ -88,9 +88,9 @@ static const struct sdhci_pltfm_data sdh - .ops = &sdhci_cns3xxx_ops, - .quirks = SDHCI_QUIRK_BROKEN_DMA | - SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | -- SDHCI_QUIRK_INVERTED_WRITE_PROTECT | - SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | -- SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, -+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | -+ SDHCI_QUIRK_BROKEN_CARD_DETECTION, - }; - - static int sdhci_cns3xxx_probe(struct platform_device *pdev) diff --git a/target/linux/cns3xxx/patches-4.19/110-pci_isolated_interrupts.patch b/target/linux/cns3xxx/patches-4.19/110-pci_isolated_interrupts.patch deleted file mode 100644 index 800be813b8..0000000000 --- a/target/linux/cns3xxx/patches-4.19/110-pci_isolated_interrupts.patch +++ /dev/null @@ -1,95 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/pcie.c -+++ b/arch/arm/mach-cns3xxx/pcie.c -@@ -18,6 +18,7 @@ - #include - #include - #include -+#include - #include - #include - #include "cns3xxx.h" -@@ -27,7 +28,7 @@ struct cns3xxx_pcie { - void __iomem *host_regs; /* PCI config registers for host bridge */ - void __iomem *cfg0_regs; /* PCI Type 0 config registers */ - void __iomem *cfg1_regs; /* PCI Type 1 config registers */ -- unsigned int irqs[2]; -+ unsigned int irqs[5]; - struct resource res_io; - struct resource res_mem; - int port; -@@ -95,7 +96,7 @@ static inline int check_master_abort(str - void __iomem *host_base; - u32 sreg, ereg; - -- host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual; -+ host_base = (void __iomem *) cnspci->host_regs; - sreg = __raw_readw(host_base + 0x6) & 0xF900; - ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg - -@@ -209,7 +210,7 @@ static struct pci_ops cns3xxx_pcie_ops = - static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) - { - struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); -- int irq = cnspci->irqs[!!dev->bus->number]; -+ int irq = cnspci->irqs[!!dev->bus->number + pin - 1]; - - pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", - pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), -@@ -235,7 +236,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[ - .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */ - .flags = IORESOURCE_MEM, - }, -- .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, -+ .irqs = { -+ IRQ_CNS3XXX_PCIE0_RC, -+ IRQ_CNS3XXX_PCIE0_DEVICE, -+ IRQ_CNS3XXX_PCIE0_DEVICE, -+ IRQ_CNS3XXX_PCIE0_DEVICE, -+ IRQ_CNS3XXX_PCIE0_DEVICE, -+ }, - .port = 0, - }, - [1] = { -@@ -254,7 +261,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[ - .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */ - .flags = IORESOURCE_MEM, - }, -- .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, -+ .irqs = { -+ IRQ_CNS3XXX_PCIE1_RC, -+ IRQ_CNS3XXX_PCIE1_DEVICE, -+ IRQ_CNS3XXX_PCIE1_DEVICE, -+ IRQ_CNS3XXX_PCIE1_DEVICE, -+ IRQ_CNS3XXX_PCIE1_DEVICE, -+ }, - .port = 1, - }, - }; -@@ -346,6 +359,14 @@ static int cns3xxx_pcie_abort_handler(un - return 0; - } - -+void __init cns3xxx_pcie_set_irqs(int bus, int *irqs) -+{ -+ int i; -+ -+ for (i = 0; i < 4; i++) -+ cns3xxx_pcie[bus].irqs[i + 1] = irqs[i]; -+} -+ - void __init cns3xxx_pcie_init_late(void) - { - int i; ---- a/arch/arm/mach-cns3xxx/core.h -+++ b/arch/arm/mach-cns3xxx/core.h -@@ -18,8 +18,10 @@ extern void cns3xxx_timer_init(void); - - #ifdef CONFIG_PCI - extern void __init cns3xxx_pcie_init_late(void); -+extern void __init cns3xxx_pcie_set_irqs(int bus, int *irqs); - #else - static inline void __init cns3xxx_pcie_init_late(void) {} -+static inline void cns3xxx_pcie_set_irqs(int bus, int *irqs) {} - #endif - - void __init cns3xxx_map_io(void); diff --git a/target/linux/cns3xxx/patches-4.19/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch b/target/linux/cns3xxx/patches-4.19/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch deleted file mode 100644 index 67aa8df7fe..0000000000 --- a/target/linux/cns3xxx/patches-4.19/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/drivers/pci/probe.c -+++ b/drivers/pci/probe.c -@@ -2655,7 +2655,8 @@ static void pcie_write_mrrs(struct pci_d - * In the "safe" case, do not configure the MRRS. There appear to be - * issues with setting MRRS to 0 on a number of devices. - */ -- if (pcie_bus_config != PCIE_BUS_PERFORMANCE) -+ if (pcie_bus_config != PCIE_BUS_PERFORMANCE && -+ pcie_bus_config != PCIE_BUS_PEER2PEER) - return; - - /* ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -868,7 +868,7 @@ enum pcie_bus_config_types { - PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ - PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ - PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ -- PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ -+ PCIE_BUS_PEER2PEER, /* set MPS and MRSS to 128 for all devices */ - }; - - extern enum pcie_bus_config_types pcie_bus_config; diff --git a/target/linux/cns3xxx/patches-4.19/200-broadcom_phy_reinit.patch b/target/linux/cns3xxx/patches-4.19/200-broadcom_phy_reinit.patch deleted file mode 100644 index b0c3299d85..0000000000 --- a/target/linux/cns3xxx/patches-4.19/200-broadcom_phy_reinit.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/drivers/net/phy/broadcom.c -+++ b/drivers/net/phy/broadcom.c -@@ -429,7 +429,11 @@ static int bcm5481_config_aneg(struct ph - ret = genphy_config_aneg(phydev); - - /* Then we can set up the delay. */ -- bcm5481x_config(phydev); -+ //bcm5481x_config(phydev); -+ -+ phy_write(phydev, 0x18, 0xf1e7); -+ phy_write(phydev, 0x1c, 0x8e00); -+ phy_write(phydev, 0x1c, 0xa41f); - - if (of_property_read_bool(np, "enet-phy-lane-swap")) { - /* Lane Swap - Undocumented register...magic! */ diff --git a/target/linux/cns3xxx/patches-4.19/210-dwc2_defaults.patch b/target/linux/cns3xxx/patches-4.19/210-dwc2_defaults.patch deleted file mode 100644 index 3efcc18854..0000000000 --- a/target/linux/cns3xxx/patches-4.19/210-dwc2_defaults.patch +++ /dev/null @@ -1,63 +0,0 @@ ---- a/drivers/usb/dwc2/params.c -+++ b/drivers/usb/dwc2/params.c -@@ -152,6 +152,36 @@ static void dwc2_set_stm32f7_hsotg_param - p->host_perio_tx_fifo_size = 256; - } - -+static void dwc2_set_cns3xxx_params(struct dwc2_hsotg *hsotg) -+{ -+ struct dwc2_core_params *p = &hsotg->params; -+ -+ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; /* non-HNP/non-SRP capable */ -+ p->host_dma = 1; -+ p->dma_desc_enable = 0; -+ p->speed = DWC2_SPEED_PARAM_HIGH; /* High Speed */ -+ p->enable_dynamic_fifo = 1; -+ p->en_multiple_tx_fifo = 1; -+ p->host_rx_fifo_size = 658; /* 774 DWORDs */ -+ p->host_nperio_tx_fifo_size = 128; /* 256 DWORDs */ -+ p->host_perio_tx_fifo_size = 658; /* 512 DWORDs */ -+ p->max_transfer_size = 65535, -+ p->max_packet_count = 511; -+ p->host_channels = 16; -+ p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; /* UTMI */ -+ p->phy_utmi_width = 16; /* 8 bits */ -+ p->phy_ulpi_ddr = 0; /* Single */ -+ p->phy_ulpi_ext_vbus = 0; -+ p->i2c_enable = 0; -+ p->ulpi_fs_ls = 0; -+ p->host_support_fs_ls_low_power = 0; -+ p->host_ls_low_power_phy_clk = 0; /* 48 MHz */ -+ p->ts_dline = 0; -+ p->reload_ctl = 0; -+ p->ahbcfg = 0x10; -+ p->uframe_sched = false; -+} -+ - const struct of_device_id dwc2_of_match_table[] = { - { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, - { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, -@@ -820,17 +850,23 @@ int dwc2_get_hwparams(struct dwc2_hsotg - - int dwc2_init_params(struct dwc2_hsotg *hsotg) - { -+ /* - const struct of_device_id *match; - void (*set_params)(void *data); -+ */ - - dwc2_set_default_params(hsotg); - dwc2_get_device_properties(hsotg); - -+ /* - match = of_match_device(dwc2_of_match_table, hsotg->dev); - if (match && match->data) { - set_params = match->data; - set_params(hsotg); - } -+ */ -+ -+ dwc2_set_cns3xxx_params(hsotg); - - dwc2_check_params(hsotg); - From 7bb1bd469e98ba4bfd0cf774a82c35039c9b721a Mon Sep 17 00:00:00 2001 From: Birger Koblitz Date: Fri, 11 Sep 2020 17:36:49 +0200 Subject: [PATCH 07/15] kernel: add support for ALLNET devices in mtdsplit Add support for uimage headers from ALLNET and provide support for the SG8208M and SG8310PM devices' magic bytes. Signed-off-by: Birger Koblitz --- .../drivers/mtd/mtdsplit/mtdsplit_uimage.c | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_uimage.c b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_uimage.c index 7a9ec8acde..281175bae7 100644 --- a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_uimage.c +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_uimage.c @@ -319,8 +319,57 @@ static struct mtd_part_parser uimage_netgear_parser = { .of_match_table = mtdsplit_uimage_netgear_of_match_table, .parse_fn = mtdsplit_uimage_parse_netgear, .type = MTD_PARSER_TYPE_FIRMWARE, + }; + +/************************************************** + * ALLNET + **************************************************/ + +#define FW_MAGIC_SG8208M 0x00000006 +#define FW_MAGIC_SG8310PM 0x83000006 + +static ssize_t uimage_verify_allnet(u_char *buf, size_t len, int *extralen) +{ + struct uimage_header *header = (struct uimage_header *)buf; + + switch (be32_to_cpu(header->ih_magic)) { + case FW_MAGIC_SG8208M: + case FW_MAGIC_SG8310PM: + break; + default: + return -EINVAL; + } + + if (header->ih_os != IH_OS_LINUX) + return -EINVAL; + + return 0; +} + +static int +mtdsplit_uimage_parse_allnet(struct mtd_info *master, + const struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + return __mtdsplit_parse_uimage(master, pparts, data, + uimage_verify_allnet); +} + +static const struct of_device_id mtdsplit_uimage_allnet_of_match_table[] = { + { .compatible = "allnet,uimage" }, + {}, +}; + +static struct mtd_part_parser uimage_allnet_parser = { + .owner = THIS_MODULE, + .name = "allnet-fw", + .of_match_table = mtdsplit_uimage_allnet_of_match_table, + .parse_fn = mtdsplit_uimage_parse_allnet, +}; + + /************************************************** * Edimax **************************************************/ @@ -505,6 +554,7 @@ static int __init mtdsplit_uimage_init(void) { register_mtd_parser(&uimage_generic_parser); register_mtd_parser(&uimage_netgear_parser); + register_mtd_parser(&uimage_allnet_parser); register_mtd_parser(&uimage_edimax_parser); register_mtd_parser(&uimage_fonfxc_parser); register_mtd_parser(&uimage_sge_parser); From df8e6be59a1fbce3f8c6878fe7440a129b1245d6 Mon Sep 17 00:00:00 2001 From: Birger Koblitz Date: Sun, 13 Sep 2020 09:06:13 +0200 Subject: [PATCH 08/15] rtl838x: add new architecture This adds support for the RTL838x Architecture. SoCs of this type are used in managed and un-managed Switches and Routers with 8-28 ports. Drivers are provided for SoC initialization, GPIOs, Flash, Ethernet including a DSA switch driver and internal and external PHYs used with these switches. Supported SoCs: RTL8380M RTL8381M RTL8382M The kernel will also boot on the following RTL839x SoCs, however driver support apart from spi-nor is missing: RTL8390 RTL8391 RTL8393 The following PHYs are supported: RTL8214FC (Quad QSGMII multiplexing GMAC and SFP port) RTL8218B internal: internal PHY of the RTL838x chips RTL8318b external (QSGMII 8-port GMAC phy) RTL8382M SerDes for 2 SFP ports Initialization sequences for the PHYs are provided in the form of firmware files. Flash driver supports 3 / 4 byte access DSA switch driver supports VLANs, port isolation, STP and port mirroring. The ALLNET ALL-SG8208M is supported as Proof of Concept: RTL8382M SoC 1 MIPS 4KEc core @ 500MHz 8 Internal PHYs (RTL8218B) 128MB DRAM (Nanya NT5TU128MB) 16MB NOR Flash (MXIC 25L128) 8 GBEthernet ports with one green status LED each (SoC controlled) 1 Power LED (not configurable) 1 SYS LED (configurable) 1 On-Off switch (not configurable) 1 Reset button at the right behind right air-vent (not configurable) 1 Reset button on front panel (configurable) 12V 1A barrel connector 1 serial header with populated standard pin connector and with markings GND TX RX Vcc(3.3V), connection properties: 115200 8N1 To install, upload the sysupgrade image to the OEM webpage. Signed-off-by: Birger Koblitz --- target/linux/rtl838x/Makefile | 22 + .../rtl838x/base-files/etc/board.d/01_leds | 15 + .../rtl838x/base-files/etc/board.d/02_network | 87 + target/linux/rtl838x/base-files/etc/inittab | 3 + .../firmware/rtl838x_phy/rtl838x_8214fc.fw | Bin 0 -> 1676 bytes .../lib/firmware/rtl838x_phy/rtl838x_8218b.fw | Bin 0 -> 1168 bytes .../lib/firmware/rtl838x_phy/rtl838x_8380.fw | Bin 0 -> 1184 bytes .../base-files/lib/upgrade/platform.sh | 19 + target/linux/rtl838x/config-5.4 | 226 ++ .../dts/rtl8382_allnet_all-sg8208m.dts | 221 ++ target/linux/rtl838x/dts/rtl838x.dtsi | 110 + .../mips/include/asm/mach-rtl838x/ioremap.h | 34 + .../arch/mips/include/asm/mach-rtl838x/irq.h | 10 + .../include/asm/mach-rtl838x/mach-rtl838x.h | 428 ++++ .../files-5.4/arch/mips/rtl838x/Makefile | 5 + .../files-5.4/arch/mips/rtl838x/Platform | 6 + .../rtl838x/files-5.4/arch/mips/rtl838x/irq.c | 263 ++ .../files-5.4/arch/mips/rtl838x/prom.c | 174 ++ .../files-5.4/arch/mips/rtl838x/serial.c | 100 + .../files-5.4/arch/mips/rtl838x/setup.c | 187 ++ .../files-5.4/drivers/gpio/gpio-rtl838x.c | 807 +++++++ .../drivers/mtd/spi-nor/rtl838x-nor.c | 607 +++++ .../drivers/mtd/spi-nor/rtl838x-spi.h | 111 + .../files-5.4/drivers/net/dsa/rtl838x.h | 188 ++ .../files-5.4/drivers/net/dsa/rtl838x_phy.c | 1286 ++++++++++ .../files-5.4/drivers/net/dsa/rtl838x_sw.c | 2150 +++++++++++++++++ .../drivers/net/ethernet/rtl838x_eth.c | 1205 +++++++++ .../drivers/net/ethernet/rtl838x_eth.h | 261 ++ target/linux/rtl838x/image/Makefile | 44 + .../300-mips-add-rtl838x-platform.patch | 42 + .../301-gpio-add-rtl838x-driver.patch | 25 + ...400-mtd-add-rtl838x-spi-flash-driver.patch | 23 + ...t-dsa-add-support-for-rtl838x-switch.patch | 26 + ...-add-rtl838x-support-for-tag-trailer.patch | 37 + ...a-increase-dsa-max-ports-for-rtl838x.patch | 13 + ...net-add-support-for-rtl838x-ethernet.patch | 26 + ...nclude-linux-add-phy-ops-for-rtl838x.patch | 13 + ...vers-net-phy-eee-support-for-rtl838x.patch | 41 + target/linux/rtl838x/profiles/00-default.mk | 13 + 39 files changed, 8828 insertions(+) create mode 100644 target/linux/rtl838x/Makefile create mode 100755 target/linux/rtl838x/base-files/etc/board.d/01_leds create mode 100755 target/linux/rtl838x/base-files/etc/board.d/02_network create mode 100644 target/linux/rtl838x/base-files/etc/inittab create mode 100644 target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8214fc.fw create mode 100644 target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8218b.fw create mode 100644 target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8380.fw create mode 100644 target/linux/rtl838x/base-files/lib/upgrade/platform.sh create mode 100644 target/linux/rtl838x/config-5.4 create mode 100644 target/linux/rtl838x/dts/rtl8382_allnet_all-sg8208m.dts create mode 100644 target/linux/rtl838x/dts/rtl838x.dtsi create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Makefile create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Platform create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c create mode 100644 target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c create mode 100644 target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c create mode 100644 target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h create mode 100644 target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h create mode 100644 target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_phy.c create mode 100644 target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c create mode 100644 target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c create mode 100644 target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h create mode 100644 target/linux/rtl838x/image/Makefile create mode 100644 target/linux/rtl838x/patches-5.4/300-mips-add-rtl838x-platform.patch create mode 100644 target/linux/rtl838x/patches-5.4/301-gpio-add-rtl838x-driver.patch create mode 100644 target/linux/rtl838x/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch create mode 100644 target/linux/rtl838x/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch create mode 100644 target/linux/rtl838x/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch create mode 100644 target/linux/rtl838x/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch create mode 100644 target/linux/rtl838x/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch create mode 100644 target/linux/rtl838x/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch create mode 100644 target/linux/rtl838x/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch create mode 100644 target/linux/rtl838x/profiles/00-default.mk diff --git a/target/linux/rtl838x/Makefile b/target/linux/rtl838x/Makefile new file mode 100644 index 0000000000..764b94ae38 --- /dev/null +++ b/target/linux/rtl838x/Makefile @@ -0,0 +1,22 @@ +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mips +CPU_TYPE:=4kec +BOARD:=rtl838x +BOARDNAME:=Realtek MIPS +FEATURES:=ramdisk squashfs + +KERNEL_PATCHVER:=5.4 + +define Target/Description + Build firmware images for Realtek RTL838x based boards. +endef + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += swconfig uboot-envtools ethtool kmod-gpio-button-hotplug + +$(eval $(call BuildTarget)) diff --git a/target/linux/rtl838x/base-files/etc/board.d/01_leds b/target/linux/rtl838x/base-files/etc/board.d/01_leds new file mode 100755 index 0000000000..7991b832f6 --- /dev/null +++ b/target/linux/rtl838x/base-files/etc/board.d/01_leds @@ -0,0 +1,15 @@ +#!/bin/sh + +. /lib/functions/uci-defaults.sh + +board=$(board_name) +boardname="${board##*,}" + +board_config_update + +case $board in +esac + +board_config_flush + +exit 0 diff --git a/target/linux/rtl838x/base-files/etc/board.d/02_network b/target/linux/rtl838x/base-files/etc/board.d/02_network new file mode 100755 index 0000000000..a79869d8c3 --- /dev/null +++ b/target/linux/rtl838x/base-files/etc/board.d/02_network @@ -0,0 +1,87 @@ +#!/bin/sh + +. /lib/functions.sh +. /lib/functions/uci-defaults.sh +. /lib/functions/system.sh + +rtl838x_setup_switch() +{ + local switchid net portid master device lan_role lan_list + + json_select_object switch + # Find slave ports + for net in $(ls -d /sys/class/net/*); do + switchid=$(cat $net/phys_switch_id 2>/dev/null) + [ -z "$switchid" ] && continue + device=$(basename $net) + portid=$(cat $net/phys_port_name) + lan_role="$lan_role ${portid##p}" + lan_list="$lan_list $device" + json_select_object "switch$((switchid))" + json_add_boolean enable 1 + json_add_boolean reset 0 + json_add_boolean dsa 1 + json_select_array ports + json_add_object + json_add_int num "${portid##p}" + json_add_string role "lan" + json_add_string device "$device" + json_close_object + json_select .. + json_select .. + done + # Add switch master device + for net in $(ls -d /sys/class/net/*/dsa); do + master=$(dirname $net) + device=$(basename $master) + portid=$(cat $master/phys_port_name) + lan_role="$lan_role ${portid##p}" + json_select_object "switch$((switchid))" + json_select_array ports + json_add_object + json_add_int num "${portid##p}" + json_add_string device "$device" + json_add_boolean need_tag 0 + json_add_boolean want_untag 0 + json_add_boolean master 1 + json_close_object + json_select .. + json_select_array roles + json_add_object + json_add_string role "lan" + lan_role=$(echo $lan_role | xargs -n1 | sort -n | xargs) + json_add_string ports "$lan_role" + json_close_object + json_select .. + json_select .. + done + json_select .. + lan_list=$(echo $lan_list | xargs -n1 | sort -V | xargs) + ucidef_set_interface_lan "$lan_list" +} + +rtl838x_setup_macs() +{ + local board="$1" + local lan_mac + local wan_mac + local label_mac + + case $board in + allnet,all-sg8208m) + lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr) + label_mac=$lan_mac + esac + + [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac + [ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac +} + +board_config_update +board=$(board_name) +rtl838x_setup_switch +rtl838x_setup_macs $board +board_config_flush + +exit 0 diff --git a/target/linux/rtl838x/base-files/etc/inittab b/target/linux/rtl838x/base-files/etc/inittab new file mode 100644 index 0000000000..9820e7144b --- /dev/null +++ b/target/linux/rtl838x/base-files/etc/inittab @@ -0,0 +1,3 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +::askconsole:/usr/libexec/login.sh diff --git a/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8214fc.fw b/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8214fc.fw new file mode 100644 index 0000000000000000000000000000000000000000..035c02d804048d5aad4435c691901e287ede90f1 GIT binary patch literal 1676 zcmai!y-!p@6veN*3!<2;3yT^guqq8iZL}gtHb@8!6%8a5i@}eCN-H~FprSP~BsLUU zP*`XzZTL6rEiDMqN(;}Kch2luul*-Bo8#XijYfT7yHP9o z-2anM3`sQ=(HIc7k^WK1H^kQ?);22n>3`(!D&LCe3S%Uq(@}sr4?l{z?maOyz1Nle zeKG3XI;iA(;;RuW!eE_k1*kLiNjw^{&=ilMhgtEph|^bMdY_6>bJ1slb?3~eQ@rTc znfWcoTHT9coZHrsm^Gh>QS)q2j5=$TerDH|N1ekj6|eV#vnqZm4-PZy``pmy3HFu- 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zY)3oKva{@+JZsIcFR;JQv-~FGz=)T*fI%0ye+?LlBXKNF#6sjOZ*c+GbsU(A zgGa!AMuy@@9E%gN5CDAkvJA7V$tZQtak$_#N+}f>1*pQ$-KvZI2Own!0b_|apL~bSs!pwSjoa6aowWbhO(zri zUVm{f@wqhXT;MRi*s(xhs-~8UExB0$5r+M~%n)zJS z+n^2X<7g<3#IZOL3(@oG$MZ?gCq19^eA4sDrujYF$$4GgH`4DJ>GzEEdq(;_BmcJ( zz+Rra-BoYYd#-SFfcrW^T6~>6l=flT+fjbs%N!j8o}431ze)O8qj`1~@7a15f0gw7 bthAjm +#include + +/ { + compatible = "allnet,all-sg8208m", "realtek,rtl838x-soc"; + model = "ALLNET ALL-SG8208M"; + + aliases { + led-boot = &led_sys; + led-failsafe = &led_sys; + led-running = &led_sys; + led-upgrade = &led_sys; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + reset { + label = "reset"; + gpios = <&gpio0 67 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_sys: sys { + label = "all-sg8208m:green:sys"; + gpios = <&gpio0 47 GPIO_ACTIVE_HIGH>; + }; + // GPIO 25: power on/off all port leds + }; +}; + +&gpio0 { + indirect-access-bus-id = <0>; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "u-boot-env"; + reg = <0x80000 0x10000>; + read-only; + }; + + partition@90000 { + label = "u-boot-env2"; + reg = <0x90000 0x10000>; + read-only; + }; + + partition@a0000 { + label = "jffs"; + reg = <0xa0000 0x100000>; + }; + + partition@1a0000 { + label = "jffs2"; + reg = <0x1a0000 0x100000>; + }; + + partition@2a0000 { + label = "firmware"; + reg = <0x2a0000 0xd60000>; + compatible = "allnet,uimage"; + }; + }; + }; +}; + +ðernet0 { + mdio: mdio-bus { + compatible = "realtek,rtl838x-mdio"; + regmap = <ðernet0>; + #address-cells = <1>; + #size-cells = <0>; + + /* Internal phy */ + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy9: ethernet-phy@9 { + reg = <9>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy10: ethernet-phy@10 { + reg = <10>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy11: ethernet-phy@11 { + reg = <11>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy12: ethernet-phy@12 { + reg = <12>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy13: ethernet-phy@13 { + reg = <13>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy14: ethernet-phy@14 { + reg = <14>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy15: ethernet-phy@15 { + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&switch0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <8>; + label = "lan1"; + phy-handle = <&phy8>; + phy-mode = "internal"; + }; + + port@1 { + reg = <9>; + label = "lan2"; + phy-handle = <&phy9>; + phy-mode = "internal"; + }; + + port@2 { + reg = <10>; + label = "lan3"; + phy-handle = <&phy10>; + phy-mode = "internal"; + }; + + port@3 { + reg = <11>; + label = "lan4"; + phy-handle = <&phy11>; + phy-mode = "internal"; + }; + + port@4 { + reg = <12>; + label = "lan5"; + phy-handle = <&phy12>; + phy-mode = "internal"; + }; + + port@5 { + reg = <13>; + label = "lan6"; + phy-handle = <&phy13>; + phy-mode = "internal"; + }; + + port@6 { + reg = <14>; + label = "lan7"; + phy-handle = <&phy14>; + phy-mode = "internal"; + }; + + port@7 { + reg = <15>; + label = "lan8"; + phy-handle = <&phy15>; + phy-mode = "internal"; + }; + + port@28 { + ethernet = <ðernet0>; + reg = <28>; + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/target/linux/rtl838x/dts/rtl838x.dtsi b/target/linux/rtl838x/dts/rtl838x.dtsi new file mode 100644 index 0000000000..63dc9bf1ba --- /dev/null +++ b/target/linux/rtl838x/dts/rtl838x.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "realtek,rtl838x-soc"; + reg = <0xbb000000 0xa000>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + frequency = <500000000>; + + cpu@0 { + compatible = "mips,mips4KEc"; + reg = <0>; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,38400"; + }; + + cpuintc: cpuintc { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "rtl838x,icu"; + reg = <0xb8003000 0x20>; + }; + + spi0: spi@b8001200 { + status = "okay"; + + compatible = "realtek,rtl838x-nor"; + reg = <0xb8001200 0x100>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: uart@b8002000 { + status = "disabled"; + + compatible = "ns16550a"; + reg = <0xb8002000 0x100>; + + clock-frequency = <200000000>; + interrupts = <31>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + }; + + uart1: uart@b8002100 { + status = "okay"; + + compatible = "ns16550a"; + reg = <0xb8002100 0x100>; + + clock-frequency = <200000000>; + + interrupt-parent = <&cpuintc>; + interrupts = <30>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + }; + + gpio0: gpio-controller@b8003500 { + compatible = "realtek,rtl838x-gpio"; + reg = <0xb8003500 0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&cpuintc>; + interrupts = <23>; + }; + + ethernet0: ethernet@bb00a300 { + status = "okay"; + + compatible = "realtek,rtl838x-eth"; + reg = <0xbb00a300 0x100>; + interrupt-parent = <&cpuintc>; + interrupts = <24>; + #interrupt-cells = <1>; + phy-mode = "internal"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + switch0: switch@bb000000 { + status = "okay"; + + compatible = "realtek,rtl838x-switch"; + }; +}; diff --git a/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h new file mode 100644 index 0000000000..e7a5bfaffc --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef RTL838X_IOREMAP_H_ +#define RTL838X_IOREMAP_H_ + +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) +{ + return phys_addr; +} + +static inline int is_rtl838x_internal_registers(phys_addr_t offset) +{ + /* IO-Block */ + if (offset >= 0xb8000000 && offset < 0xb9000000) + return 1; + /* Switch block */ + if (offset >= 0xbb000000 && offset < 0xbc000000) + return 1; + return 0; +} + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + if (is_rtl838x_internal_registers(offset)) + return (void __iomem *)offset; + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return is_rtl838x_internal_registers((unsigned long)addr); +} + +#endif diff --git a/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h new file mode 100644 index 0000000000..e821111c5d --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_MACH_RTL838X_IRQ_H +#define __ASM_MACH_RTL838X_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define NR_IRQS 64 + +#include_next + +#endif /* __ASM_MACH_ATH79_IRQ_H */ diff --git a/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h new file mode 100644 index 0000000000..cece36635c --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h @@ -0,0 +1,428 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * Copyright (C) 2020 B. Koblitz + */ +#ifndef _MACH_RTL838X_H_ +#define _MACH_RTL838X_H_ + +/* + * Register access macros + */ + +#define RTL838X_SW_BASE ((volatile void *) 0xBB000000) + +#define rtl838x_r32(reg) __raw_readl(reg) +#define rtl838x_w32(val, reg) __raw_writel(val, reg) +#define rtl838x_w32_mask(clear, set, reg) rtl838x_w32((rtl838x_r32(reg) & ~(clear)) | (set), reg) + +#define sw_r32(reg) __raw_readl(RTL838X_SW_BASE + reg) +#define sw_w32(val, reg) __raw_writel(val, RTL838X_SW_BASE + reg) +#define sw_w32_mask(clear, set, reg) \ + sw_w32((sw_r32(reg) & ~(clear)) | (set), reg) + +#define sw_r64(reg) ((((u64)__raw_readl(RTL838X_SW_BASE + reg)) << 32) | \ + __raw_readl(RTL838X_SW_BASE + reg + 4)) + +#define sw_w64(val, reg) do { \ + __raw_writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \ + __raw_writel((u32)((val) & 0xffffffff), \ + RTL838X_SW_BASE + reg + 4); \ + } while (0) + +/* + * SPRAM + */ +#define RTL838X_ISPRAM_BASE 0x0 +#define RTL838X_DSPRAM_BASE 0x0 + +/* + * IRQ Controller + */ +#define RTL838X_IRQ_CPU_BASE 0 +#define RTL838X_IRQ_CPU_NUM 8 +#define RTL838X_IRQ_ICTL_BASE (RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM) +#define RTL838X_IRQ_ICTL_NUM 32 + +/* + * MIPS32R2 counter + */ +#define RTL838X_COMPARE_IRQ (RTL838X_IRQ_CPU_BASE + 7) + +/* + * ICTL + * Base address 0xb8003000UL + */ +#define RTL838X_ICTL1_IRQ (RTL838X_IRQ_CPU_BASE + 2) +#define RTL838X_ICTL2_IRQ (RTL838X_IRQ_CPU_BASE + 3) +#define RTL838X_ICTL3_IRQ (RTL838X_IRQ_CPU_BASE + 4) +#define RTL838X_ICTL4_IRQ (RTL838X_IRQ_CPU_BASE + 5) +#define RTL838X_ICTL5_IRQ (RTL838X_IRQ_CPU_BASE + 6) + +#define GIMR (0x00) +#define UART0_IE (1 << 31) +#define UART1_IE (1 << 30) +#define TC0_IE (1 << 29) +#define TC1_IE (1 << 28) +#define OCPTO_IE (1 << 27) +#define HLXTO_IE (1 << 26) +#define SLXTO_IE (1 << 25) +#define NIC_IE (1 << 24) +#define GPIO_ABCD_IE (1 << 23) +#define GPIO_EFGH_IE (1 << 22) +#define RTC_IE (1 << 21) +#define WDT_IP1_IE (1 << 19) +#define WDT_IP2_IE (1 << 18) + +#define GISR (0x04) +#define UART0_IP (1 << 31) +#define UART1_IP (1 << 30) +#define TC0_IP (1 << 29) +#define TC1_IP (1 << 28) +#define OCPTO_IP (1 << 27) +#define HLXTO_IP (1 << 26) +#define SLXTO_IP (1 << 25) +#define NIC_IP (1 << 24) +#define GPIO_ABCD_IP (1 << 23) +#define GPIO_EFGH_IP (1 << 22) +#define RTC_IP (1 << 21) +#define WDT_IP1_IP (1 << 19) +#define WDT_IP2_IP (1 << 18) + +#define IRR0 (0x08) +#define IRR0_SETTING ((UART0_RS << 28) | \ + (UART1_RS << 24) | \ + (TC0_RS << 20) | \ + (TC1_RS << 16) | \ + (OCPTO_RS << 12) | \ + (HLXTO_RS << 8) | \ + (SLXTO_RS << 4) | \ + (NIC_RS << 0) \ + ) + +#define IRR1 (0x0c) + +#define IRR1_SETTING ((GPIO_ABCD_RS << 28) | \ + (GPIO_EFGH_RS << 24) | \ + (RTC_RS << 20) | \ + (SWCORE_RS << 16) \ + ) + +#define IRR2 (0x10) +#define IRR2_SETTING 0 + +#define IRR3 (0x14) +#define IRR3_SETTING 0 + +/* Interrupt Routing Selection */ +#define UART0_RS 2 +#define UART1_RS 1 +#define TC0_RS 5 +#define TC1_RS 1 +#define OCPTO_RS 1 +#define HLXTO_RS 1 +#define SLXTO_RS 1 +#define NIC_RS 4 +#define GPIO_ABCD_RS 4 +#define GPIO_EFGH_RS 4 +#define RTC_RS 4 +#define SWCORE_RS 3 +#define WDT_IP1_RS 4 +#define WDT_IP2_RS 5 + +/* Interrupt IRQ Assignments */ +#define UART0_IRQ 31 +#define UART1_IRQ 30 +#define TC0_IRQ 29 +#define TC1_IRQ 28 +#define OCPTO_IRQ 27 +#define HLXTO_IRQ 26 +#define SLXTO_IRQ 25 +#define NIC_IRQ 24 +#define GPIO_ABCD_IRQ 23 +#define GPIO_EFGH_IRQ 22 +#define RTC_IRQ 21 +#define SWCORE_IRQ 20 +#define WDT_IP1_IRQ 19 +#define WDT_IP2_IRQ 18 + +#define SYSTEM_FREQ 200000000 +#define RTL838X_UART0_BASE ((volatile void *)(0xb8002000UL)) +#define RTL838X_UART0_BAUD 38400 /* ex. 19200 or 38400 or 57600 or 115200 */ +#define RTL838X_UART0_FREQ (SYSTEM_FREQ - RTL838X_UART0_BAUD * 24) +#define RTL838X_UART0_MAPBASE 0x18002000UL +#define RTL838X_UART0_MAPSIZE 0x100 +#define RTL838X_UART0_IRQ UART0_IRQ + +#define RTL838X_UART1_BASE ((volatile void *)(0xb8002100UL)) +#define RTL838X_UART1_BAUD 38400 /* ex. 19200 or 38400 or 57600 or 115200 */ +#define RTL838X_UART1_FREQ (SYSTEM_FREQ - RTL838X_UART1_BAUD * 24) +#define RTL838X_UART1_MAPBASE 0x18002100UL +#define RTL838X_UART1_MAPSIZE 0x100 +#define RTL838X_UART1_IRQ UART1_IRQ + +#define UART0_RBR (RTL838X_UART0_BASE + 0x000) +#define UART0_THR (RTL838X_UART0_BASE + 0x000) +#define UART0_DLL (RTL838X_UART0_BASE + 0x000) +#define UART0_IER (RTL838X_UART0_BASE + 0x004) +#define UART0_DLM (RTL838X_UART0_BASE + 0x004) +#define UART0_IIR (RTL838X_UART0_BASE + 0x008) +#define UART0_FCR (RTL838X_UART0_BASE + 0x008) +#define UART0_LCR (RTL838X_UART0_BASE + 0x00C) +#define UART0_MCR (RTL838X_UART0_BASE + 0x010) +#define UART0_LSR (RTL838X_UART0_BASE + 0x014) + +#define UART1_RBR (RTL838X_UART1_BASE + 0x000) +#define UART1_THR (RTL838X_UART1_BASE + 0x000) +#define UART1_DLL (RTL838X_UART1_BASE + 0x000) +#define UART1_IER (RTL838X_UART1_BASE + 0x004) +#define UART1_DLM (RTL838X_UART1_BASE + 0x004) +#define UART1_IIR (RTL838X_UART1_BASE + 0x008) +#define UART1_FCR (RTL838X_UART1_BASE + 0x008) + #define FCR_EN 0x01 + #define FCR_RXRST 0x02 + #define XRST 0x02 + #define FCR_TXRST 0x04 + #define TXRST 0x04 + #define FCR_DMA 0x08 + #define FCR_RTRG 0xC0 + #define CHAR_TRIGGER_01 0x00 + #define CHAR_TRIGGER_04 0x40 + #define CHAR_TRIGGER_08 0x80 + #define CHAR_TRIGGER_14 0xC0 +#define UART1_LCR (RTL838X_UART1_BASE + 0x00C) + #define LCR_WLN 0x03 + #define CHAR_LEN_5 0x00 + #define CHAR_LEN_6 0x01 + #define CHAR_LEN_7 0x02 + #define CHAR_LEN_8 0x03 + #define LCR_STB 0x04 + #define ONE_STOP 0x00 + #define TWO_STOP 0x04 + #define LCR_PEN 0x08 + #define PARITY_ENABLE 0x01 + #define PARITY_DISABLE 0x00 + #define LCR_EPS 0x30 + #define PARITY_ODD 0x00 + #define PARITY_EVEN 0x10 + #define PARITY_MARK 0x20 + #define PARITY_SPACE 0x30 + #define LCR_BRK 0x40 + #define LCR_DLAB 0x80 + #define DLAB 0x80 +#define UART1_MCR (RTL838X_UART1_BASE + 0x010) +#define UART1_LSR (RTL838X_UART1_BASE + 0x014) + #define LSR_DR 0x01 + #define RxCHAR_AVAIL 0x01 + #define LSR_OE 0x02 + #define LSR_PE 0x04 + #define LSR_FE 0x08 + #define LSR_BI 0x10 + #define LSR_THRE 0x20 + #define TxCHAR_AVAIL 0x00 + #define TxCHAR_EMPTY 0x20 + #define LSR_TEMT 0x40 + #define LSR_RFE 0x80 + +/* + * Timer/counter for 8390/80/28 TC & MP chip + */ +#define RTL838X_TIMER0_BASE ((volatile void *)(0xb8003100UL)) +#define RTL838X_TIMER0_IRQ RTL838X_TC0_EXT_IRQ + +#define RTL8390TC_TC1DATA (RTL838X_TIMER0_BASE + 0x04) +#define RTL8390TC_TCD_OFFSET 8 +#define RTL8390TC_TC0CNT (RTL838X_TIMER0_BASE + 0x08) +#define RTL8390TC_TC1CNT (RTL838X_TIMER0_BASE + 0x0C) +#define RTL8390TC_TCCNR (RTL838X_TIMER0_BASE + 0x10) +#define RTL8390TC_TC0EN (1 << 31) +#define RTL8390TC_TC0MODE_TIMER (1 << 30) +#define RTL8390TC_TC1EN (1 << 29) +#define RTL8390TC_TC1MODE_TIMER (1 << 28) +#define RTL8390TC_TCIR (RTL838X_TIMER0_BASE + 0x14) +#define RTL8390TC_TC0IE (1 << 31) +#define RTL8390TC_TC1IE (1 << 30) +#define RTL8390TC_TC0IP (1 << 29) +#define RTL8390TC_TC1IP (1 << 28) +#define RTL8390TC_CDBR (RTL838X_TIMER0_BASE + 0x18) +#define RTL8390TC_DIVF_OFFSET 16 +#define RTL8390TC_WDTCNR (RTL838X_TIMER0_BASE + 0x1C) + +#define RTL8390MP_TC1DATA (RTL838X_TIMER0_BASE + 0x10) +#define RTL8390MP_TC0CNT (RTL838X_TIMER0_BASE + 0x04) +#define RTL8390MP_TC1CNT (RTL838X_TIMER0_BASE + 0x14) +#define RTL8390MP_TC0CTL (RTL838X_TIMER0_BASE + 0x08) +#define RTL8390MP_TC1CTL (RTL838X_TIMER0_BASE + 0x18) +#define RTL8390MP_TCEN (1 << 28) +#define RTL8390MP_TCMODE_TIMER (1 << 24) +#define RTL8390MP_TCDIV_FACTOR (0xFFFF << 0) +#define RTL8390MP_TC0INT (RTL838X_TIMER0_BASE + 0xC) +#define RTL8390MP_TC1INT (RTL838X_TIMER0_BASE + 0x1C) +#define RTL8390MP_TCIE (1 << 20) +#define RTL8390MP_TCIP (1 << 16) +#define RTL8390MP_WDTCNR (RTL838X_TIMER0_BASE + 0x50) + +#define RTL8380MP_TC0DATA (RTL838X_TIMER0_BASE + 0x00) +#define RTL8380MP_TC1DATA (RTL838X_TIMER0_BASE + 0x10) +#define RTL8380MP_TC0CNT (RTL838X_TIMER0_BASE + 0x04) +#define RTL8380MP_TC1CNT (RTL838X_TIMER0_BASE + 0x14) +#define RTL8380MP_TC0CTL (RTL838X_TIMER0_BASE + 0x08) +#define RTL8380MP_TC1CTL (RTL838X_TIMER0_BASE + 0x18) +#define RTL8380MP_TCEN (1 << 28) +#define RTL8380MP_TCMODE_TIMER (1 << 24) +#define RTL8380MP_TCDIV_FACTOR (0xFFFF << 0) +#define RTL8380MP_TC0INT (RTL838X_TIMER0_BASE + 0xC) +#define RTL8380MP_TC1INT (RTL838X_TIMER0_BASE + 0x1C) +#define RTL8380MP_TCIE (1 << 20) +#define RTL8380MP_TCIP (1 << 16) +#define RTL8380MP_WDTCNR (RTL838X_TIMER0_BASE + 0x50) + +#define DIVISOR_RTL8390 55 +#define DIVISOR_RTL8380 2500 +#define DIVISOR_MAX 16834 + +/* + * Memory Controller + */ +#define MC_MCR 0xB8001000 +#define MC_MCR_VAL 0x00000000 + +#define MC_DCR 0xB8001004 +#define MC_DCR0_VAL 0x54480000 + +#define MC_DTCR 0xB8001008 +#define MC_DTCR_VAL 0xFFFF05C0 + +/* + * GPIO + */ +#define GPIO_CTRL_REG_BASE ((volatile void *) 0xb8003500) +#define RTL838X_GPIO_PABC_CNR (GPIO_CTRL_REG_BASE + 0x0) +#define RTL838X_GPIO_PABC_TYPE (GPIO_CTRL_REG_BASE + 0x04) +#define RTL838X_GPIO_PABC_DIR (GPIO_CTRL_REG_BASE + 0x8) +#define RTL838X_GPIO_PABC_DATA (GPIO_CTRL_REG_BASE + 0xc) +#define RTL838X_GPIO_PABC_ISR (GPIO_CTRL_REG_BASE + 0x10) +#define RTL838X_GPIO_PAB_IMR (GPIO_CTRL_REG_BASE + 0x14) +#define RTL838X_GPIO_PC_IMR (GPIO_CTRL_REG_BASE + 0x18) + +#define RTL838X_MODEL_NAME_INFO (0x00D4) +#define RTL839X_MODEL_NAME_INFO (0x0FF0) +#define RTL838X_LED_GLB_CTRL (0xA000) +#define RTL839X_LED_GLB_CTRL (0x00E4) +#define RTL838X_EXT_GPIO_DIR_0 (0xA08C) +#define RTL838X_EXT_GPIO_DIR_1 (0xA090) +#define RTL838X_EXT_GPIO_DATA_0 (0xA094) +#define RTL838X_EXT_GPIO_DATA_1 (0xA098) +#define RTL838X_EXT_GPIO_INDRT_ACCESS (0xA09C) +#define RTL838X_EXTRA_GPIO_CTRL (0xA0E0) +#define RTL838X_EXTRA_GPIO_DIR_0 (0xA0E4) +#define RTL838X_EXTRA_GPIO_DIR_1 (0xA0E8) +#define RTL838X_EXTRA_GPIO_DATA_0 (0xA0EC) +#define RTL838X_EXTRA_GPIO_DATA_1 (0xA0F0) +#define RTL838X_DMY_REG5 (0x0144) +#define RTL838X_EXTRA_GPIO_CTRL (0xA0E0) + +#define RTL838X_GMII_INTF_SEL (0x1000) +#define RTL838X_IO_DRIVING_ABILITY_CTRL (0x1010) + +#define RTL838X_GPIO_A7 31 +#define RTL838X_GPIO_A6 30 +#define RTL838X_GPIO_A5 29 +#define RTL838X_GPIO_A4 28 +#define RTL838X_GPIO_A3 27 +#define RTL838X_GPIO_A2 26 +#define RTL838X_GPIO_A1 25 +#define RTL838X_GPIO_A0 24 +#define RTL838X_GPIO_B7 23 +#define RTL838X_GPIO_B6 22 +#define RTL838X_GPIO_B5 21 +#define RTL838X_GPIO_B4 20 +#define RTL838X_GPIO_B3 19 +#define RTL838X_GPIO_B2 18 +#define RTL838X_GPIO_B1 17 +#define RTL838X_GPIO_B0 16 +#define RTL838X_GPIO_C7 15 +#define RTL838X_GPIO_C6 14 +#define RTL838X_GPIO_C5 13 +#define RTL838X_GPIO_C4 12 +#define RTL838X_GPIO_C3 11 +#define RTL838X_GPIO_C2 10 +#define RTL838X_GPIO_C1 9 +#define RTL838X_GPIO_C0 8 + +#define RTL838X_INT_RW_CTRL (0x0058) +#define RTL838X_EXT_VERSION (0x00D0) +#define RTL838X_PLL_CML_CTRL (0x0FF8) +#define RTL838X_STRAP_DBG (0x100C) + +/* + * Reset + */ +#define RGCR (0x1E70) +#define RTL839X_RST_GLB_CTRL (0x0014) +#define RTL838X_RST_GLB_CTRL_1 (0x0040) + +/* LED control by switch */ +#define RTL838X_LED_MODE_SEL (0x1004) +#define RTL838X_LED_MODE_CTRL (0xA004) +#define RTL838X_LED_P_EN_CTRL (0xA008) + +/* LED control by software */ +#define RTL838X_LED_SW_CTRL (0xA00C) +#define RTL838X_LED0_SW_P_EN_CTRL (0xA010) +#define RTL838X_LED1_SW_P_EN_CTRL (0xA014) +#define RTL838X_LED2_SW_P_EN_CTRL (0xA018) +#define RTL838X_LED_SW_P_CTRL(p) (0xA01C + ((p) << 2)) + +#define RTL839X_MAC_EFUSE_CTRL (0x02ac) + +/* + * MDIO via Realtek's SMI interface + */ +#define RTL838X_SMI_GLB_CTRL (0xa100) +#define RTL838X_SMI_ACCESS_PHY_CTRL_0 (0xa1b8) +#define RTL838X_SMI_ACCESS_PHY_CTRL_1 (0xa1bc) +#define RTL838X_SMI_ACCESS_PHY_CTRL_2 (0xa1c0) +#define RTL838X_SMI_ACCESS_PHY_CTRL_3 (0xa1c4) +#define RTL838X_SMI_PORT0_5_ADDR_CTRL (0xa1c8) +#define RTL838X_SMI_POLL_CTRL (0xa17c) + +#define RTL839X_SMI_GLB_CTRL (0x03f8) +#define RTL839X_SMI_PORT_POLLING_CTRL (0x03fc) +#define RTL839X_PHYREG_ACCESS_CTRL (0x03DC) +#define RTL839X_PHYREG_CTRL (0x03E0) +#define RTL839X_PHYREG_PORT_CTRL(p) (0x03E4 + ((p >> 5) << 2)) +#define RTL839X_PHYREG_DATA_CTRL (0x03F0) + +/* + * Switch interrupts + */ +#define RTL838X_IMR_GLB (0x1100) +#define RTL838X_IMR_PORT_LINK_STS_CHG (0x1104) +#define RTL838X_ISR_GLB_SRC (0x1148) +#define RTL838X_ISR_PORT_LINK_STS_CHG (0x114C) +#define RTL839X_IMR_GLB (0x0064) +#define RTL839X_IMR_PORT_LINK_STS_CHG (0x0068) +#define RTL839X_ISR_GLB_SRC (0x009c) +#define RTL839X_ISR_PORT_LINK_STS_CHG (0x00a0) + +/* Definition of family IDs */ +#define RTL8389_FAMILY_ID (0x8389) +#define RTL8328_FAMILY_ID (0x8328) +#define RTL8390_FAMILY_ID (0x8390) +#define RTL8350_FAMILY_ID (0x8350) +#define RTL8380_FAMILY_ID (0x8380) +#define RTL8330_FAMILY_ID (0x8330) + +struct rtl838x_soc_info { + unsigned char *name; + unsigned int id; + unsigned int family; + unsigned char *compatible; + volatile void *sw_base; + volatile void *icu_base; +}; + +void rtl838x_soc_detect(struct rtl838x_soc_info *i); + +#endif /* _MACH_RTL838X_H_ */ diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Makefile b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Makefile new file mode 100644 index 0000000000..fe5e1d96a9 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the rtl838x specific parts of the kernel +# + +obj-y := serial.o setup.o prom.o irq.o diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Platform b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Platform new file mode 100644 index 0000000000..4d48932d80 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Platform @@ -0,0 +1,6 @@ +# +# Realtek RTL838x SoCs +# +platform-$(CONFIG_RTL838X) += rtl838x/ +cflags-$(CONFIG_RTL838X) += -I$(srctree)/arch/mips/include/asm/mach-rtl838x/ +load-$(CONFIG_RTL838X) += 0xffffffff80000000 diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c new file mode 100644 index 0000000000..34e90982b2 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Realtek RTL838X architecture specific IRQ handling + * + * Copyright (C) 2020 B. Koblitz + * based on the original BSP + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +extern struct rtl838x_soc_info soc_info; + +#define icu_r32(reg) rtl838x_r32(soc_info.icu_base + reg) +#define icu_w32(val, reg) rtl838x_w32(val, soc_info.icu_base + reg) +#define icu_w32_mask(clear, set, reg) rtl838x_w32_mask(clear, set, soc_info.icu_base + reg) + +static DEFINE_RAW_SPINLOCK(irq_lock); + +extern irqreturn_t c0_compare_interrupt(int irq, void *dev_id); +unsigned int rtl838x_ictl_irq_dispatch1(void); +unsigned int rtl838x_ictl_irq_dispatch2(void); +unsigned int rtl838x_ictl_irq_dispatch3(void); +unsigned int rtl838x_ictl_irq_dispatch4(void); +unsigned int rtl838x_ictl_irq_dispatch5(void); + +static struct irqaction irq_cascade1 = { + .handler = no_action, + .name = "RTL838X IRQ cascade1", +}; + +static struct irqaction irq_cascade2 = { + .handler = no_action, + .name = "RTL838X IRQ cascade2", +}; + +static struct irqaction irq_cascade3 = { + .handler = no_action, + .name = "RTL838X IRQ cascade3", +}; + +static struct irqaction irq_cascade4 = { + .handler = no_action, + .name = "RTL838X IRQ cascade4", +}; + +static struct irqaction irq_cascade5 = { + .handler = no_action, + .name = "RTL838X IRQ cascade5", +}; + +static void rtl838x_ictl_enable_irq(struct irq_data *i) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&irq_lock, flags); + icu_w32_mask(0, 1 << i->irq, GIMR); + raw_spin_unlock_irqrestore(&irq_lock, flags); +} + +static unsigned int rtl838x_ictl_startup_irq(struct irq_data *i) +{ + rtl838x_ictl_enable_irq(i); + return 0; +} + +static void rtl838x_ictl_disable_irq(struct irq_data *i) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&irq_lock, flags); + icu_w32_mask(1 << i->irq, 0, GIMR); + raw_spin_unlock_irqrestore(&irq_lock, flags); +} + +static void rtl838x_ictl_eoi_irq(struct irq_data *i) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&irq_lock, flags); + icu_w32_mask(0, 1 << i->irq, GIMR); + raw_spin_unlock_irqrestore(&irq_lock, flags); +} + +static struct irq_chip rtl838x_ictl_irq = { + .name = "RTL838X", + .irq_startup = rtl838x_ictl_startup_irq, + .irq_shutdown = rtl838x_ictl_disable_irq, + .irq_enable = rtl838x_ictl_enable_irq, + .irq_disable = rtl838x_ictl_disable_irq, + .irq_ack = rtl838x_ictl_disable_irq, + .irq_mask = rtl838x_ictl_disable_irq, + .irq_unmask = rtl838x_ictl_enable_irq, + .irq_eoi = rtl838x_ictl_eoi_irq, +}; + +/* + * RTL8390/80/28 Interrupt Scheme + * + * Source IRQ CPU INT + * -------- ------- ------- + * UART0 31 IP3 + * UART1 30 IP2 + * TIMER0 29 IP6 + * TIMER1 28 IP2 + * OCPTO 27 IP2 + * HLXTO 26 IP2 + * SLXTO 25 IP2 + * NIC 24 IP5 + * GPIO_ABCD 23 IP5 + * SWCORE 20 IP4 + */ + +unsigned int rtl838x_ictl_irq_dispatch1(void) +{ + /* Identify shared IRQ */ + unsigned int extint_ip = icu_r32(GIMR) & icu_r32(GISR); + + if (extint_ip & TC1_IP) + do_IRQ(TC1_IRQ); + else if (extint_ip & UART1_IP) + do_IRQ(UART1_IRQ); + else + spurious_interrupt(); + + return IRQ_HANDLED; +} + +unsigned int rtl838x_ictl_irq_dispatch2(void) +{ + do_IRQ(UART0_IRQ); + return IRQ_HANDLED; +} + +unsigned int rtl838x_ictl_irq_dispatch3(void) +{ + do_IRQ(SWCORE_IRQ); + return IRQ_HANDLED; +} + +unsigned int rtl838x_ictl_irq_dispatch4(void) +{ + /* Identify shared IRQ */ + unsigned int extint_ip = icu_r32(GIMR) & icu_r32(GISR); + + if (extint_ip & NIC_IP) + do_IRQ(NIC_IRQ); + else if (extint_ip & GPIO_ABCD_IP) + do_IRQ(GPIO_ABCD_IRQ); + else if ((extint_ip & GPIO_EFGH_IP) && (soc_info.family == RTL8328_FAMILY_ID)) + do_IRQ(GPIO_EFGH_IRQ); + else + spurious_interrupt(); + + return IRQ_HANDLED; +} + +unsigned int rtl838x_ictl_irq_dispatch5(void) +{ + do_IRQ(TC0_IRQ); + return IRQ_HANDLED; +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending; + + pending = read_c0_cause() & read_c0_status() & ST0_IM; + + if (pending & CAUSEF_IP7) + c0_compare_interrupt(7, NULL); + else if (pending & CAUSEF_IP6) + rtl838x_ictl_irq_dispatch5(); + else if (pending & CAUSEF_IP5) + rtl838x_ictl_irq_dispatch4(); + else if (pending & CAUSEF_IP4) + rtl838x_ictl_irq_dispatch3(); + else if (pending & CAUSEF_IP3) + rtl838x_ictl_irq_dispatch2(); + else if (pending & CAUSEF_IP2) + rtl838x_ictl_irq_dispatch1(); + else + spurious_interrupt(); +} + +static void __init rtl838x_ictl_irq_init(unsigned int irq_base) +{ + int i; + + for (i = 0; i < RTL838X_IRQ_ICTL_NUM; i++) + irq_set_chip_and_handler(irq_base + i, &rtl838x_ictl_irq, handle_level_irq); + + setup_irq(RTL838X_ICTL1_IRQ, &irq_cascade1); + setup_irq(RTL838X_ICTL2_IRQ, &irq_cascade2); + setup_irq(RTL838X_ICTL3_IRQ, &irq_cascade3); + setup_irq(RTL838X_ICTL4_IRQ, &irq_cascade4); + setup_irq(RTL838X_ICTL5_IRQ, &irq_cascade5); + + /* Set GIMR, IRR */ + icu_w32(TC0_IE | UART0_IE, GIMR); + icu_w32(IRR0_SETTING, IRR0); + icu_w32(IRR1_SETTING, IRR1); + icu_w32(IRR2_SETTING, IRR2); + icu_w32(IRR3_SETTING, IRR3); +} + +static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) +{ + irq_set_chip_and_handler(hw, &rtl838x_ictl_irq, handle_level_irq); + + return 0; +} + +static const struct irq_domain_ops irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = intc_map, +}; + +int __init icu_of_init(struct device_node *node, struct device_node *parent) +{ + int i; + struct irq_domain *domain; + struct resource res; + + pr_info("Found Interrupt controller: %s (%s)\n", node->name, node->full_name); + if (of_address_to_resource(node, 0, &res)) { + panic("Failed to get icu memory range"); + } + if (!request_mem_region(res.start, resource_size(&res), res.name)) + pr_err("Failed to request icu memory\n"); + soc_info.icu_base = ioremap(res.start, resource_size(&res)); + pr_info("ICU Memory: %08x\n", (u32)soc_info.icu_base); + + mips_cpu_irq_init(); + + domain = irq_domain_add_simple(node, 32, 0, &irq_domain_ops, NULL); + + /* Setup all external HW irqs */ + for (i = 8; i < 32; i++) + irq_domain_associate(domain, i, i); + + rtl838x_ictl_irq_init(RTL838X_IRQ_ICTL_BASE); + return 0; +} + +void __init arch_init_irq(void) +{ + /* do board-specific irq initialization */ + irqchip_init(); +} + +IRQCHIP_DECLARE(mips_cpu_intc, "rtl838x,icu", icu_of_init); diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c new file mode 100644 index 0000000000..604b01806c --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * prom.c + * Early intialization code for the Realtek RTL838X SoC + * + * based on the original BSP by + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * Copyright (C) 2020 B. Koblitz + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern char arcs_cmdline[]; +const void *fdt; +extern const char __appended_dtb; +//extern int __init rtl838x_serial_init(void); + +void prom_console_init(void) +{ + /* UART 16550A is initialized by the bootloader */ +} + +#ifdef CONFIG_EARLY_PRINTK +#define rtl838x_r8(reg) __raw_readb(reg) +#define rtl838x_w8(val, reg) __raw_writeb(val, reg) + +void unregister_prom_console(void) +{ + +} + +void disable_early_printk(void) +{ + +} + +void prom_putchar(char c) +{ + unsigned int retry = 0; + + do { + if (retry++ >= 30000) { + /* Reset Tx FIFO */ + rtl838x_w8(TXRST | CHAR_TRIGGER_14, UART0_FCR); + return; + } + } while ((rtl838x_r8(UART0_LSR) & LSR_THRE) == TxCHAR_AVAIL); + + /* Send Character */ + rtl838x_w8(c, UART0_THR); +} + +char prom_getchar(void) +{ + return '\0'; +} +#endif + +struct rtl838x_soc_info soc_info; + +const char *get_system_type(void) +{ + return soc_info.name; +} + + +void __init prom_free_prom_memory(void) +{ + +} + +void __init device_tree_init(void) +{ + pr_info("%s called\r\n", __func__); + if (!fdt_check_header(&__appended_dtb)) { + fdt = &__appended_dtb; + pr_info("Using appended Device Tree.\n"); + } + initial_boot_params = (void *)fdt; + unflatten_and_copy_device_tree(); +} + +static void __init prom_init_cmdline(void) +{ + int argc = fw_arg0; + char **argv = (char **) KSEG1ADDR(fw_arg1); + int i; + + arcs_cmdline[0] = '\0'; + + for (i = 0; i < argc; i++) { + char *p = (char *) KSEG1ADDR(argv[i]); + + if (CPHYSADDR(p) && *p) { + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + } + } + pr_info("Kernel command line: %s\n", arcs_cmdline); +} + +/* Do basic initialization */ +void __init prom_init(void) +{ + uint32_t model; + + pr_info("%s called\n", __func__); + soc_info.sw_base = RTL838X_SW_BASE; + + model = sw_r32(RTL838X_MODEL_NAME_INFO); + pr_info("RTL838X model is %x\n", model); + model = model >> 16 & 0xFFFF; + + if ((model != 0x8328) && (model != 0x8330) && (model != 0x8332) + && (model != 0x8380) && (model != 0x8382)) { + model = sw_r32(RTL839X_MODEL_NAME_INFO); + pr_info("RTL839X model is %x\n", model); + model = model >> 16 & 0xFFFF; + } + + soc_info.id = model; + + switch (model) { + case 0x8328: + soc_info.name = "RTL8328"; + soc_info.family = RTL8328_FAMILY_ID; + break; + case 0x8332: + soc_info.name = "RTL8332"; + soc_info.family = RTL8380_FAMILY_ID; + break; + case 0x8380: + soc_info.name = "RTL8380"; + soc_info.family = RTL8380_FAMILY_ID; + break; + case 0x8382: + soc_info.name = "RTL8382"; + soc_info.family = RTL8380_FAMILY_ID; + break; + case 0x8390: + soc_info.name = "RTL8390"; + soc_info.family = RTL8390_FAMILY_ID; + break; + case 0x8391: + soc_info.name = "RTL8391"; + soc_info.family = RTL8390_FAMILY_ID; + break; + case 0x8392: + soc_info.name = "RTL8392"; + soc_info.family = RTL8390_FAMILY_ID; + break; + case 0x8393: + soc_info.name = "RTL8393"; + soc_info.family = RTL8390_FAMILY_ID; + break; + default: + soc_info.name = "DEFAULT"; + soc_info.family = 0; + } + pr_info("SoC Type: %s\n", get_system_type()); + prom_init_cmdline(); +} + diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c new file mode 100644 index 0000000000..cebab1df8d --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * 8250 serial console setup for the Realtek RTL838X SoC + * + * based on the original BSP by + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * + * Copyright (C) 2020 B. Koblitz + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern char arcs_cmdline[]; +extern struct rtl838x_soc_info soc_info; + +int __init rtl838x_serial_init(void) +{ +#ifdef CONFIG_SERIAL_8250 + int ret; + struct uart_port p; + unsigned long baud = 0; + int err; + char parity = '\0', bits = '\0', flow = '\0'; + char *s; + struct device_node *dn; + + dn = of_find_compatible_node(NULL, NULL, "ns16550a"); + if (dn) { + pr_info("Found NS16550a: %s (%s)\n", dn->name, dn->full_name); + dn = of_find_compatible_node(dn, NULL, "ns16550a"); + if (dn && of_device_is_available(dn) && soc_info.family == RTL8380_FAMILY_ID) { + /* Enable UART1 on RTL838x */ + pr_info("Enabling uart1\n"); + sw_w32(0x10, RTL838X_GMII_INTF_SEL); + } + } else { + pr_err("No NS16550a UART found!"); + return -ENODEV; + } + + s = strstr(arcs_cmdline, "console=ttyS0,"); + if (s) { + s += 14; + baud = kstrtoul(s, 10, &baud); + if (err) + baud = 0; + while (isdigit(*s)) + s++; + if (*s == ',') + s++; + if (*s) + parity = *s++; + if (*s == ',') + s++; + if (*s) + bits = *s++; + if (*s == ',') + s++; + if (*s == 'h') + flow = 'r'; + } + + if (baud == 0) { + baud = 38400; + pr_warn("Using default baud rate: %lu\n", baud); + } + if (parity != 'n' && parity != 'o' && parity != 'e') + parity = 'n'; + if (bits != '7' && bits != '8') + bits = '8'; + + memset(&p, 0, sizeof(p)); + + p.type = PORT_16550A; + p.membase = (unsigned char *) RTL838X_UART0_BASE; + p.irq = RTL838X_UART0_IRQ; + p.uartclk = SYSTEM_FREQ - (24 * baud); + p.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY | UPF_FIXED_TYPE; + p.iotype = UPIO_MEM; + p.regshift = 2; + p.fifosize = 1; + + /* Call early_serial_setup() here, to set up 8250 console driver */ + if (early_serial_setup(&p) != 0) + ret = 1; +#endif + return 0; +} diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c new file mode 100644 index 0000000000..6a9485c451 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Setup for the Realtek RTL838X SoC: + * Memory, Timer and Serial + * + * Copyright (C) 2020 B. Koblitz + * based on the original BSP by + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * + */ +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include /* for mips_hpt_frequency */ +#include +#include + +#include "mach-rtl838x.h" + +extern int rtl838x_serial_init(void); +extern struct rtl838x_soc_info soc_info; + +struct clk { + struct clk_lookup cl; + unsigned long rate; +}; + +struct clk cpu_clk; + +u32 pll_reset_value; + +static void rtl838x_restart(char *command) +{ + u32 pll = sw_r32(RTL838X_PLL_CML_CTRL); + /* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */ + void (*f)(void) = (void *) 0xbfc00000; + + pr_info("System restart.\n"); + if (soc_info.family == RTL8390_FAMILY_ID) { + f(); + /* If calling reset vector fails, reset entire chip */ + sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL); + /* If this fails, halt the CPU */ + while + (1); + } + + pr_info("PLL control register: %x, applying reset value %x\n", + pll, pll_reset_value); + sw_w32(3, RTL838X_INT_RW_CTRL); + sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL); + sw_w32(0, RTL838X_INT_RW_CTRL); + + pr_info("Resetting RTL838X SoC\n"); + /* Reset Global Control1 Register */ + sw_w32(1, RTL838X_RST_GLB_CTRL_1); +} + +static void rtl838x_halt(void) +{ + pr_info("System halted.\n"); + while + (1); +} + +static void __init rtl838x_setup(void) +{ + unsigned int val; + + pr_info("Registering _machine_restart\n"); + _machine_restart = rtl838x_restart; + _machine_halt = rtl838x_halt; + + val = rtl838x_r32((volatile void *)0xBB0040000); + if (val == 3) + pr_info("PCI device found\n"); + else + pr_info("NO PCI device found\n"); + + /* Setup System LED. Bit 15 (14 for RTL8390) then allows to toggle it */ + if (soc_info.family == RTL8380_FAMILY_ID) + sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL); + else + sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL); +} + +void __init plat_mem_setup(void) +{ + void *dtb; + + pr_info("%s called\n", __func__); + + set_io_port_base(KSEG1); + + if (fw_passed_dtb) /* UHI interface */ + dtb = (void *)fw_passed_dtb; + else if (__dtb_start != __dtb_end) + dtb = (void *)__dtb_start; + else + panic("no dtb found"); + + /* + * Load the devicetree. This causes the chosen node to be + * parsed resulting in our memory appearing + */ + __dt_setup_arch(dtb); + + rtl838x_setup(); +} + + +/* + * Linux clock API + */ +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL_GPL(clk_enable); + +void clk_disable(struct clk *clk) +{ + +} +EXPORT_SYMBOL_GPL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->rate; +} +EXPORT_SYMBOL_GPL(clk_get_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + return -1; +} +EXPORT_SYMBOL_GPL(clk_set_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + return -1; +} +EXPORT_SYMBOL_GPL(clk_round_rate); + +void __init plat_time_init(void) +{ + u32 freq = 500000000; + struct device_node *np; + struct clk *clk = &cpu_clk; + + np = of_find_node_by_name(NULL, "cpus"); + if (!np) { + pr_err("Missing 'cpus' DT node, using default frequency."); + } else { + if (of_property_read_u32(np, "frequency", &freq) < 0) + pr_err("No 'frequency' property in DT, using default."); + else + pr_info("CPU frequency from device tree: %d", freq); + of_node_put(np); + } + + clk->rate = freq; + + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + + pr_info("CPU Clock: %ld MHz\n", clk->rate / 1000000); + mips_hpt_frequency = freq / 2; + + pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL); + pr_info("PLL control register: %x\n", pll_reset_value); + + /* With the info from the command line and cpu-freq we can setup the console */ + rtl838x_serial_init(); +} diff --git a/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c b/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c new file mode 100644 index 0000000000..bba3b3f572 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include + +/* RTL8231 registers for LED control */ +#define RTL8231_LED_FUNC0 0x0000 +#define RTL8231_GPIO_PIN_SEL(gpio) ((0x0002) + ((gpio) >> 4)) +#define RTL8231_GPIO_DIR(gpio) ((0x0005) + ((gpio) >> 4)) +#define RTL8231_GPIO_DATA(gpio) ((0x001C) + ((gpio) >> 4)) +#define RTL8231_GPIO_PIN_SEL0 0x0002 +#define RTL8231_GPIO_PIN_SEL1 0x0003 +#define RTL8231_GPIO_PIN_SEL2 0x0004 +#define RTL8231_GPIO_IO_SEL0 0x0005 +#define RTL8231_GPIO_IO_SEL1 0x0006 +#define RTL8231_GPIO_IO_SEL2 0x0007 + +#define MDC_WAIT { int i; for (i = 0; i < 2; i++); } +#define I2C_WAIT { int i; for (i = 0; i < 5; i++); } + +struct rtl838x_gpios { + struct gpio_chip gc; + u32 id; + struct device *dev; + int irq; + int bus_id; + int num_leds; + int min_led; + int leds_per_port; + u32 led_mode; + u16 rtl8381_phy_id; + int smi_clock; + int smi_data; + int i2c_sda; + int i2c_sdc; +}; + +extern struct mutex smi_lock; + +u32 rtl838x_rtl8231_read(u8 bus_id, u32 reg) +{ + u32 t = 0; + + reg &= 0x1f; + bus_id &= 0x1f; + + /* Calculate read register address */ + t = (bus_id << 2) | (reg << 7); + + mutex_lock(&smi_lock); + /* Set execution bit: cleared when operation completed */ + t |= 1; + sw_w32(t, RTL838X_EXT_GPIO_INDRT_ACCESS); + do { /* TODO: Return 0x80000000 if timeout */ + t = sw_r32(RTL838X_EXT_GPIO_INDRT_ACCESS); + } while (t & 1); + pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, (t & 0xffff0000) >> 16); + + mutex_unlock(&smi_lock); + return (t & 0xffff0000) >> 16; +} + +int rtl838x_rtl8231_write(u8 bus_id, u32 reg, u32 data) +{ + u32 t = 0; + + pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, data); + data &= 0xffff; + reg &= 0x1f; + bus_id &= 0x1f; + + mutex_lock(&smi_lock); + t = (bus_id << 2) | (reg << 7) | (data << 16); + /* Set write bit */ + t |= 2; + + /* Set execution bit: cleared when operation completed */ + t |= 1; + sw_w32(t, RTL838X_EXT_GPIO_INDRT_ACCESS); + do { /* TODO: Return -1 if timeout */ + t = sw_r32(RTL838X_EXT_GPIO_INDRT_ACCESS); + } while (t & 1); + + mutex_unlock(&smi_lock); + return 0; +} + +static int rtl8231_pin_dir(u8 bus_id, u32 gpio, u32 dir) +{ + /* dir 1: input + * dir 0: output + */ + + u32 v; + int pin_sel_addr = RTL8231_GPIO_PIN_SEL(gpio); + int pin_dir_addr = RTL8231_GPIO_DIR(gpio); + int pin = gpio % 16; + int dpin = pin; + + if (gpio > 31) { + dpin = pin << 5; + pin_dir_addr = pin_sel_addr; + } + + /* Select GPIO function for pin */ + v = rtl838x_rtl8231_read(bus_id, pin_sel_addr); + if (v & 0x80000000) { + pr_err("Error reading RTL8231\n"); + return -1; + } + rtl838x_rtl8231_write(bus_id, pin_sel_addr, v | (1 << pin)); + + v = rtl838x_rtl8231_read(bus_id, pin_dir_addr); + if (v & 0x80000000) { + pr_err("Error reading RTL8231\n"); + return -1; + } + rtl838x_rtl8231_write(bus_id, pin_dir_addr, + (v & ~(1 << dpin)) | (dir << dpin)); + return 0; +} + +static int rtl8231_pin_dir_get(u8 bus_id, u32 gpio, u32 *dir) +{ + /* dir 1: input + * dir 0: output + */ + + u32 v; + int pin_dir_addr = RTL8231_GPIO_DIR(gpio); + int pin = gpio % 16; + + if (gpio > 31) { + pin_dir_addr = RTL8231_GPIO_PIN_SEL(gpio); + pin = pin << 5; + } + + v = rtl838x_rtl8231_read(bus_id, pin_dir_addr); + if (v & (1 << pin)) + *dir = 1; + else + *dir = 0; + return 0; +} + +static int rtl8231_pin_set(u8 bus_id, u32 gpio, u32 data) +{ + u32 v = rtl838x_rtl8231_read(bus_id, RTL8231_GPIO_DATA(gpio)); + + if (v & 0x80000000) { + pr_err("Error reading RTL8231\n"); + return -1; + } + rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_DATA(gpio), + (v & ~(1 << (gpio % 16))) | (data << (gpio % 16))); + return 0; +} + +static int rtl8231_pin_get(u8 bus_id, u32 gpio, u16 *state) +{ + u32 v = rtl838x_rtl8231_read(bus_id, RTL8231_GPIO_DATA(gpio)); + + if (v & 0x80000000) { + pr_err("Error reading RTL8231\n"); + return -1; + } + + *state = v & 0xffff; + return 0; +} + +static int rtl838x_direction_input(struct gpio_chip *gc, unsigned int offset) +{ + struct rtl838x_gpios *gpios = gpiochip_get_data(gc); + + pr_debug("%s: %d\n", __func__, offset); + + if (offset < 32) { + rtl838x_w32_mask(1 << offset, 0, RTL838X_GPIO_PABC_DIR); + return 0; + } + + /* Internal LED driver does not support input */ + if (offset >= 32 && offset < 64) + return -ENOTSUPP; + + if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) + return rtl8231_pin_dir(gpios->bus_id, offset - 64, 1); + + return -ENOTSUPP; +} + +static int rtl838x_direction_output(struct gpio_chip *gc, unsigned int offset, int value) +{ + struct rtl838x_gpios *gpios = gpiochip_get_data(gc); + + pr_debug("%s: %d\n", __func__, offset); + if (offset < 32) + rtl838x_w32_mask(0, 1 << offset, RTL838X_GPIO_PABC_DIR); + + /* LED for PWR and SYS driver is direction output by default */ + if (offset >= 32 && offset < 64) + return 0; + + if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) + return rtl8231_pin_dir(gpios->bus_id, offset - 64, 0); + return 0; +} + +static int rtl838x_get_direction(struct gpio_chip *gc, unsigned int offset) +{ + u32 v = 0; + struct rtl838x_gpios *gpios = gpiochip_get_data(gc); + + pr_debug("%s: %d\n", __func__, offset); + if (offset < 32) { + v = rtl838x_r32(RTL838X_GPIO_PABC_DIR); + if (v & (1 << offset)) + return 0; + return 1; + } + + /* LED driver for PWR and SYS is direction output by default */ + if (offset >= 32 && offset < 64) + return 0; + + if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) { + rtl8231_pin_dir_get(gpios->bus_id, offset - 64, &v); + return v; + } + + return 0; +} + +static int rtl838x_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + u32 v; + u16 state = 0; + int bit; + struct rtl838x_gpios *gpios = gpiochip_get_data(gc); + + pr_debug("%s: %d\n", __func__, offset); + + /* Internal GPIO of the RTL8380 */ + if (offset < 32) { + v = rtl838x_r32(RTL838X_GPIO_PABC_DATA); + if (v & (1 << offset)) + return 1; + return 0; + } + + /* LED driver for PWR and SYS */ + if (offset >= 32 && offset < 64) { + v = sw_r32(RTL838X_LED_GLB_CTRL); + if (v & (1 << (offset-32))) + return 1; + return 0; + } + + /* Indirect access GPIO with RTL8231 */ + if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) { + rtl8231_pin_get(gpios->bus_id, offset - 64, &state); + if (state & (1 << (offset % 16))) + return 1; + return 0; + } + + bit = (offset - 100) % 32; + if (offset >= 100 && offset < 132) { + if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & (1 << bit)) + return 1; + return 0; + } + if (offset >= 132 && offset < 164) { + if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & (1 << bit)) + return 1; + return 0; + } + if (offset >= 164 && offset < 196) { + if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & (1 << bit)) + return 1; + return 0; + } + return 0; +} + +void rtl838x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) +{ + int bit; + struct rtl838x_gpios *gpios = gpiochip_get_data(gc); + + pr_debug("rtl838x_set: %d, value: %d\n", offset, value); + /* Internal GPIO of the RTL8380 */ + if (offset < 32) { + if (value) + rtl838x_w32_mask(0, 1 << offset, RTL838X_GPIO_PABC_DATA); + else + rtl838x_w32_mask(1 << offset, 0, RTL838X_GPIO_PABC_DATA); + } + + /* LED driver for PWR and SYS */ + if (offset >= 32 && offset < 64) { + bit = offset - 32; + if (value) + sw_w32_mask(0, 1 << bit, RTL838X_LED_GLB_CTRL); + else + sw_w32_mask(1 << bit, 0, RTL838X_LED_GLB_CTRL); + return; + } + + /* Indirect access GPIO with RTL8231 */ + if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) { + rtl8231_pin_set(gpios->bus_id, offset - 64, value); + return; + } + + bit = (offset - 100) % 32; + /* First Port-LED */ + if (offset >= 100 && offset < 132 + && offset >= (100 + gpios->min_led) + && offset < (100 + gpios->min_led + gpios->num_leds)) { + if (value) + sw_w32_mask(7, 5, RTL838X_LED_SW_P_CTRL(bit)); + else + sw_w32_mask(7, 0, RTL838X_LED_SW_P_CTRL(bit)); + } + if (offset >= 132 && offset < 164 + && offset >= (132 + gpios->min_led) + && offset < (132 + gpios->min_led + gpios->num_leds)) { + if (value) + sw_w32_mask(7 << 3, 5 << 3, RTL838X_LED_SW_P_CTRL(bit)); + else + sw_w32_mask(7 << 3, 0, RTL838X_LED_SW_P_CTRL(bit)); + } + if (offset >= 164 && offset < 196 + && offset >= (164 + gpios->min_led) + && offset < (164 + gpios->min_led + gpios->num_leds)) { + if (value) + sw_w32_mask(7 << 6, 5 << 6, RTL838X_LED_SW_P_CTRL(bit)); + else + sw_w32_mask(7 << 6, 0, RTL838X_LED_SW_P_CTRL(bit)); + } + __asm__ volatile ("sync"); +} + +int rtl8231_init(struct rtl838x_gpios *gpios) +{ + uint32_t v; + u8 bus_id = gpios->bus_id; + + pr_info("%s called\n", __func__); + + /* Enable RTL8231 indirect access mode */ + sw_w32_mask(0, 1, RTL838X_EXTRA_GPIO_CTRL); + sw_w32_mask(3, 1, RTL838X_DMY_REG5); + + /* Enable RTL8231 via GPIO_A1 line */ + rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DIR); + rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DATA); + mdelay(50); /* wait 50ms for reset */ + + /*Select GPIO functionality for pins 0-15, 16-31 and 32-37 */ + rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_PIN_SEL(0), 0xffff); + rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_PIN_SEL(16), 0xffff); + rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_PIN_SEL2, 0x03ff); + + v = rtl838x_rtl8231_read(bus_id, RTL8231_LED_FUNC0); + pr_info("RTL8231 led function now: %x\n", v); + + return 0; +} + +static void smi_write_bit(struct rtl838x_gpios *gpios, u32 bit) +{ + if (bit) + rtl838x_w32_mask(0, 1 << gpios->smi_data, RTL838X_GPIO_PABC_DATA); + else + rtl838x_w32_mask(1 << gpios->smi_data, 0, RTL838X_GPIO_PABC_DATA); + + MDC_WAIT; + rtl838x_w32_mask(1 << gpios->smi_clock, 0, RTL838X_GPIO_PABC_DATA); + MDC_WAIT; + rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DATA); +} + +static int smi_read_bit(struct rtl838x_gpios *gpios) +{ + u32 v; + + MDC_WAIT; + rtl838x_w32_mask(1 << gpios->smi_clock, 0, RTL838X_GPIO_PABC_DATA); + MDC_WAIT; + rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DATA); + + v = rtl838x_r32(RTL838X_GPIO_PABC_DATA); + if (v & (1 << gpios->smi_data)) + return 1; + return 0; +} + +/* Tri-state of MDIO line */ +static void smi_z(struct rtl838x_gpios *gpios) +{ + /* MDIO pin to input */ + rtl838x_w32_mask(1 << gpios->smi_data, 0, RTL838X_GPIO_PABC_DIR); + MDC_WAIT; + rtl838x_w32_mask(1 << gpios->smi_clock, 0, RTL838X_GPIO_PABC_DATA); + MDC_WAIT; + rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DATA); +} + +static void smi_write_bits(struct rtl838x_gpios *gpios, u32 data, int len) +{ + while (len) { + len--; + smi_write_bit(gpios, data & (1 << len)); + } +} + +static void smi_read_bits(struct rtl838x_gpios *gpios, int len, u32 *data) +{ + u32 v = 0; + + while (len) { + len--; + v <<= 1; + v |= smi_read_bit(gpios); + } + *data = v; +} + +/* Bit-banged verson of SMI write access, caller must hold smi_lock */ +int rtl8380_smi_write(struct rtl838x_gpios *gpios, u16 reg, u32 data) +{ + u16 bus_id = gpios->bus_id; + + /* Set clock and data pins on RTL838X to output */ + rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DIR); + rtl838x_w32_mask(0, 1 << gpios->smi_data, RTL838X_GPIO_PABC_DIR); + + /* Write start bits */ + smi_write_bits(gpios, 0xffffffff, 32); + + smi_write_bits(gpios, 0x5, 4); /* ST and write OP */ + + smi_write_bits(gpios, bus_id, 5); /* 5 bits: phy address */ + smi_write_bits(gpios, reg, 5); /* 5 bits: register address */ + + smi_write_bits(gpios, 0x2, 2); /* TURNAROUND */ + + smi_write_bits(gpios, data, 16); /* 16 bits: data*/ + + smi_z(gpios); + + return 0; +} + +/* Bit-banged verson of SMI read access, caller must hold smi_lock */ +int rtl8380_smi_read(struct rtl838x_gpios *gpios, u16 reg, u32 *data) +{ + u16 bus_id = gpios->bus_id; + + /* Set clock and data pins on RTL838X to output */ + rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DIR); + rtl838x_w32_mask(0, 1 << gpios->smi_data, RTL838X_GPIO_PABC_DIR); + + /* Write start bits */ + smi_write_bits(gpios, 0xffffffff, 32); + + smi_write_bits(gpios, 0x6, 4); /* ST and read OP */ + + smi_write_bits(gpios, bus_id, 5); /* 5 bits: phy address */ + smi_write_bits(gpios, reg, 5); /* 5 bits: register address */ + + smi_z(gpios); /* TURNAROUND */ + + smi_read_bits(gpios, 16, data); + return 0; +} + +static void i2c_pin_set(struct rtl838x_gpios *gpios, int pin, u32 data) +{ + u32 v; + + rtl8380_smi_read(gpios, RTL8231_GPIO_DATA(pin), &v); + if (!data) + v &= ~(1 << (pin % 16)); + else + v |= (1 << (pin % 16)); + rtl8380_smi_write(gpios, RTL8231_GPIO_DATA(pin), v); +} + +static void i2c_pin_get(struct rtl838x_gpios *gpios, int pin, u32 *data) +{ + u32 v; + + rtl8380_smi_read(gpios, RTL8231_GPIO_DATA(pin), &v); + if (v & (1 << (pin % 16))) { + *data = 1; + return; + } + *data = 0; +} + +static void i2c_pin_dir(struct rtl838x_gpios *gpios, int pin, u16 direction) +{ + u32 v; + + rtl8380_smi_read(gpios, RTL8231_GPIO_DIR(pin), &v); + if (direction) // Output + v &= ~(1 << (pin % 16)); + else + v |= (1 << (pin % 16)); + rtl8380_smi_write(gpios, RTL8231_GPIO_DIR(pin), v); +} + +static void i2c_start(struct rtl838x_gpios *gpios) +{ + i2c_pin_dir(gpios, gpios->i2c_sda, 0); /* Output */ + i2c_pin_dir(gpios, gpios->i2c_sdc, 0); /* Output */ + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sdc, 1); + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sda, 1); + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sda, 0); + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sdc, 0); + I2C_WAIT; +} + +static void i2c_stop(struct rtl838x_gpios *gpios) +{ + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sdc, 1); + i2c_pin_set(gpios, gpios->i2c_sda, 0); + I2C_WAIT; + + i2c_pin_set(gpios, gpios->i2c_sda, 1); + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sdc, 0); + + i2c_pin_dir(gpios, gpios->i2c_sda, 1); /* Input */ + i2c_pin_dir(gpios, gpios->i2c_sdc, 1); /* Input */ +} + +static void i2c_read_bits(struct rtl838x_gpios *gpios, int len, u32 *data) +{ + u32 v = 0, t; + + while (len) { + len--; + v <<= 1; + i2c_pin_set(gpios, gpios->i2c_sdc, 1); + I2C_WAIT; + i2c_pin_get(gpios, gpios->i2c_sda, &t); + v |= t; + i2c_pin_set(gpios, gpios->i2c_sdc, 0); + I2C_WAIT; + } + *data = v; +} + +static void i2c_write_bits(struct rtl838x_gpios *gpios, u32 data, int len) +{ + while (len) { + len--; + i2c_pin_set(gpios, gpios->i2c_sda, data & (1 << len)); + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sdc, 1); + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sdc, 0); + I2C_WAIT; + } +} + +/* This initializes direct external GPIOs via the RTL8231 */ +int rtl8380_rtl8321_init(struct rtl838x_gpios *gpios) +{ + u32 v; + int mdc = gpios->smi_clock; + int mdio = gpios->smi_data; + + pr_info("Configuring SMI: Clock %d, Data %d\n", mdc, mdio); + sw_w32_mask(0, 0x2, RTL838X_IO_DRIVING_ABILITY_CTRL); + + /* Enter simulated GPIO mode */ + sw_w32_mask(1, 0, RTL838X_EXTRA_GPIO_CTRL); + + /* MDIO clock to 2.6MHz */ + sw_w32_mask(0x3 << 8, 0, RTL838X_EXTRA_GPIO_CTRL); + + /* Configure SMI clock and data GPIO pins */ + rtl838x_w32_mask((1 << mdc) | (1 << mdio), 0, RTL838X_GPIO_PABC_CNR); + rtl838x_w32_mask(0, (1 << mdc) | (1 << mdio), RTL838X_GPIO_PABC_DIR); + + rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL0, 0xffff); + rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL1, 0xffff); + rtl8380_smi_read(gpios, RTL8231_GPIO_PIN_SEL2, &v); + v |= 0x1f; + rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL2, v); + + rtl8380_smi_write(gpios, RTL8231_GPIO_IO_SEL0, 0xffff); + rtl8380_smi_write(gpios, RTL8231_GPIO_IO_SEL1, 0xffff); + rtl8380_smi_read(gpios, RTL8231_GPIO_IO_SEL2, &v); + v |= 0x1f << 5; + rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL2, v); + + return 0; +} + +void rtl8380_led_test(u32 mask) +{ + int i; + u32 mode_sel = sw_r32(RTL838X_LED_MODE_SEL); + u32 led_gbl = sw_r32(RTL838X_LED_GLB_CTRL); + u32 led_p_en = sw_r32(RTL838X_LED_P_EN_CTRL); + + /* 2 Leds for ports 0-23 and 24-27, 3 would be 0x7 */ + sw_w32_mask(0x3f, 0x3 | (0x3 << 3), RTL838X_LED_GLB_CTRL); + /* Enable all leds */ + sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL); + + /* Enable software control of all leds */ + sw_w32(0xFFFFFFF, RTL838X_LED_SW_CTRL); + sw_w32(0xFFFFFFF, RTL838X_LED0_SW_P_EN_CTRL); + sw_w32(0xFFFFFFF, RTL838X_LED1_SW_P_EN_CTRL); + sw_w32(0x0000000, RTL838X_LED2_SW_P_EN_CTRL); + + for (i = 0; i < 28; i++) { + if (mask & (1 << i)) + sw_w32(5 | (5 << 3) | (5 << 6), + RTL838X_LED_SW_P_CTRL(i)); + } + msleep(3000); + + sw_w32(led_p_en, RTL838X_LED_P_EN_CTRL); + /* Disable software control of all leds */ + sw_w32(0x0000000, RTL838X_LED_SW_CTRL); + sw_w32(0x0000000, RTL838X_LED0_SW_P_EN_CTRL); + sw_w32(0x0000000, RTL838X_LED1_SW_P_EN_CTRL); + sw_w32(0x0000000, RTL838X_LED2_SW_P_EN_CTRL); + + sw_w32(led_gbl, RTL838X_LED_GLB_CTRL); + sw_w32(mode_sel, RTL838X_LED_MODE_SEL); +} + +void take_port_leds(struct rtl838x_gpios *gpios) +{ + int leds_per_port = gpios->leds_per_port; + int mode = gpios->led_mode; + + pr_info("%s, %d, %x\n", __func__, leds_per_port, mode); + pr_debug("Bootloader settings: %x %x %x\n", + sw_r32(RTL838X_LED0_SW_P_EN_CTRL), + sw_r32(RTL838X_LED1_SW_P_EN_CTRL), + sw_r32(RTL838X_LED2_SW_P_EN_CTRL) + ); + + pr_debug("led glb: %x, sel %x\n", + sw_r32(RTL838X_LED_GLB_CTRL), sw_r32(RTL838X_LED_MODE_SEL)); + pr_debug("RTL838X_LED_P_EN_CTRL: %x", sw_r32(RTL838X_LED_P_EN_CTRL)); + pr_debug("RTL838X_LED_MODE_CTRL: %x", sw_r32(RTL838X_LED_MODE_CTRL)); + + sw_w32_mask(3, 0, RTL838X_LED_MODE_SEL); + sw_w32(mode, RTL838X_LED_MODE_CTRL); + + /* Enable software control of all leds */ + sw_w32(0xFFFFFFF, RTL838X_LED_SW_CTRL); + sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL); + + sw_w32(0x0000000, RTL838X_LED0_SW_P_EN_CTRL); + sw_w32(0x0000000, RTL838X_LED1_SW_P_EN_CTRL); + sw_w32(0x0000000, RTL838X_LED2_SW_P_EN_CTRL); + + sw_w32_mask(0x3f, 0, RTL838X_LED_GLB_CTRL); + switch (leds_per_port) { + case 3: + sw_w32_mask(0, 0x7 | (0x7 << 3), RTL838X_LED_GLB_CTRL); + sw_w32(0xFFFFFFF, RTL838X_LED2_SW_P_EN_CTRL); + /* FALLTHRU */ + case 2: + sw_w32_mask(0, 0x3 | (0x3 << 3), RTL838X_LED_GLB_CTRL); + sw_w32(0xFFFFFFF, RTL838X_LED1_SW_P_EN_CTRL); + /* FALLTHRU */ + case 1: + sw_w32_mask(0, 0x1 | (0x1 << 3), RTL838X_LED_GLB_CTRL); + sw_w32(0xFFFFFFF, RTL838X_LED0_SW_P_EN_CTRL); + break; + default: + pr_err("No LEDS configured for software control\n"); + } +} + +static const struct of_device_id rtl838x_gpio_of_match[] = { + { .compatible = "realtek,rtl838x-gpio" }, + {}, +}; + +MODULE_DEVICE_TABLE(of, rtl838x_gpio_of_match); + +static int rtl838x_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct rtl838x_gpios *gpios; + int err; + u8 indirect_bus_id; + + pr_info("Probing RTL838X GPIOs\n"); + + if (!np) { + dev_err(&pdev->dev, "No DT found\n"); + return -EINVAL; + } + + gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL); + if (!gpios) + return -ENOMEM; + + gpios->id = sw_r32(RTL838X_MODEL_NAME_INFO) >> 16; + + switch (gpios->id) { + case 0x8332: + pr_debug("Found RTL8332M GPIO\n"); + break; + case 0x8380: + pr_debug("Found RTL8380M GPIO\n"); + break; + case 0x8381: + pr_debug("Found RTL8381M GPIO\n"); + break; + case 0x8382: + pr_debug("Found RTL8382M GPIO\n"); + break; + default: + pr_err("Unknown GPIO chip id (%04x)\n", gpios->id); + return -ENODEV; + } + + gpios->dev = dev; + gpios->gc.base = 0; + /* 0-31: internal + * 32-63, LED control register + * 64-99: external RTL8231 + * 100-131: PORT-LED 0 + * 132-163: PORT-LED 1 + * 164-195: PORT-LED 2 + */ + gpios->gc.ngpio = 196; + gpios->gc.label = "rtl838x"; + gpios->gc.parent = dev; + gpios->gc.owner = THIS_MODULE; + gpios->gc.can_sleep = true; + gpios->bus_id = -1; + gpios->irq = 31; + + gpios->gc.direction_input = rtl838x_direction_input; + gpios->gc.direction_output = rtl838x_direction_output; + gpios->gc.set = rtl838x_gpio_set; + gpios->gc.get = rtl838x_gpio_get; + gpios->gc.get_direction = rtl838x_get_direction; + + if (!of_property_read_u8(np, "indirect-access-bus-id", &indirect_bus_id)) { + gpios->bus_id = indirect_bus_id; + rtl8231_init(gpios); + } + if (!of_property_read_u8(np, "smi-bus-id", &indirect_bus_id)) { + gpios->bus_id = indirect_bus_id; + gpios->smi_clock = RTL838X_GPIO_A2; + gpios->smi_data = RTL838X_GPIO_A3; + gpios->i2c_sda = 1; + gpios->i2c_sdc = 2; + rtl8380_rtl8321_init(gpios); + } + + if (of_property_read_bool(np, "take-port-leds")) { + if (of_property_read_u32(np, "leds-per-port", &gpios->leds_per_port)) + gpios->leds_per_port = 2; + if (of_property_read_u32(np, "led-mode", &gpios->led_mode)) + gpios->led_mode = (0x1ea << 15) | 0x1ea; + if (of_property_read_u32(np, "num-leds", &gpios->num_leds)) + gpios->num_leds = 32; + if (of_property_read_u32(np, "min-led", &gpios->min_led)) + gpios->min_led = 0; + take_port_leds(gpios); + } + + err = devm_gpiochip_add_data(dev, &gpios->gc, gpios); + return err; +} + + +static struct platform_driver rtl838x_gpio_driver = { + .driver = { + .name = "rtl838x-gpio", + .of_match_table = rtl838x_gpio_of_match, + }, + .probe = rtl838x_gpio_probe, +}; + +module_platform_driver(rtl838x_gpio_driver); + +MODULE_DESCRIPTION("Realtek RTL838X GPIO API support"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c b/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c new file mode 100644 index 0000000000..0d8f9dbd3e --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rtl838x-spi.h" +#include + +extern struct rtl838x_soc_info soc_info; + +struct rtl838x_nor { + struct spi_nor nor; + struct device *dev; + volatile void __iomem *base; + bool fourByteMode; + u32 chipSize; + uint32_t flags; + uint32_t io_status; +}; + +static uint32_t spi_prep(struct rtl838x_nor *rtl838x_nor) +{ + /* Needed because of MMU constraints */ + SPI_WAIT_READY; + spi_w32w(SPI_CS_INIT, SFCSR); //deactivate CS0, CS1 + spi_w32w(0, SFCSR); //activate CS0,CS1 + spi_w32w(SPI_CS_INIT, SFCSR); //deactivate CS0, CS1 + + return (CS0 & rtl838x_nor->flags) ? (SPI_eCS0 & SPI_LEN_INIT) + : ((SPI_eCS1 & SPI_LEN_INIT) | SFCSR_CHIP_SEL); +} + +static uint32_t rtl838x_nor_get_SR(struct rtl838x_nor *rtl838x_nor) +{ + uint32_t sfcsr, sfdr; + + sfcsr = spi_prep(rtl838x_nor); + sfdr = (SPINOR_OP_RDSR)<<24; + + pr_debug("%s: rdid,sfcsr_val = %.8x,SFDR = %.8x\n", __func__, sfcsr, sfdr); + pr_debug("rdid,sfcsr = %.8x\n", sfcsr | SPI_LEN4); + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + spi_w32_mask(0, SPI_LEN4, SFCSR); + SPI_WAIT_READY; + + return spi_r32(SFDR); +} + +static void spi_write_disable(struct rtl838x_nor *rtl838x_nor) +{ + uint32_t sfcsr, sfdr; + + sfcsr = spi_prep(rtl838x_nor); + sfdr = (SPINOR_OP_WRDI) << 24; + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr); + + spi_prep(rtl838x_nor); +} + +static void spi_write_enable(struct rtl838x_nor *rtl838x_nor) +{ + uint32_t sfcsr, sfdr; + + sfcsr = spi_prep(rtl838x_nor); + sfdr = (SPINOR_OP_WREN) << 24; + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr); + + spi_prep(rtl838x_nor); +} + +static void spi_4b_set(struct rtl838x_nor *rtl838x_nor, bool enable) +{ + uint32_t sfcsr, sfdr; + + sfcsr = spi_prep(rtl838x_nor); + if (enable) + sfdr = (SPINOR_OP_EN4B) << 24; + else + sfdr = (SPINOR_OP_EX4B) << 24; + + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr); + + spi_prep(rtl838x_nor); +} + +static int rtl838x_get_addr_mode(struct rtl838x_nor *rtl838x_nor) +{ + int res = 3; + u32 reg; + + sw_w32(0x3, RTL838X_INT_RW_CTRL); + if (!sw_r32(RTL838X_EXT_VERSION)) { + if (sw_r32(RTL838X_STRAP_DBG) & (1 << 29)) + res = 4; + } else { + reg = sw_r32(RTL838X_PLL_CML_CTRL); + if ((reg & (1 << 30)) && (reg & (1 << 31))) + res = 4; + if ((!(reg & (1 << 30))) + && sw_r32(RTL838X_STRAP_DBG) & (1 << 29)) + res = 4; + } + sw_w32(0x0, RTL838X_INT_RW_CTRL); + return res; +} + +static int rtl8390_get_addr_mode(struct rtl838x_nor *rtl838x_nor) +{ + if (spi_r32(RTL8390_SOC_SPI_MMIO_CONF) & (1 << 9)) + return 4; + return 3; +} + +ssize_t rtl838x_do_read(struct rtl838x_nor *rtl838x_nor, loff_t from, + size_t length, u_char *buffer, uint8_t command) +{ + uint32_t sfcsr, sfdr; + uint32_t len = length; + + sfcsr = spi_prep(rtl838x_nor); + sfdr = command << 24; + + /* Perform SPINOR_OP_READ: 1 byte command & 3 byte addr*/ + sfcsr |= SPI_LEN4; + sfdr |= from; + + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + + /* Read Data, 4 bytes at a time */ + while (length >= 4) { + SPI_WAIT_READY; + *((uint32_t *) buffer) = spi_r32(SFDR); +/* printk("%.8x ", *((uint32_t*) buffer)); */ + buffer += 4; + length -= 4; + } + + /* The rest needs to be read 1 byte a time */ + sfcsr &= SPI_LEN_INIT|SPI_LEN1; + SPI_WAIT_READY; + spi_w32w(sfcsr, SFCSR); + while (length > 0) { + SPI_WAIT_READY; + *(buffer) = spi_r32(SFDR) >> 24; +/* printk("%.2x ", *(buffer)); */ + buffer++; + length--; + } + return len; +} + +/* + * Do fast read in 3 or 4 Byte addressing mode + */ +static ssize_t rtl838x_do_4bf_read(struct rtl838x_nor *rtl838x_nor, loff_t from, + size_t length, u_char *buffer, uint8_t command) +{ + int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2; + int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8; + uint32_t sfcsr; + uint32_t len = length; + + pr_debug("Fast read from %llx, len %x, shift %d\n", + from, sfcsr_addr_len, sfdr_addr_shift); + sfcsr = spi_prep(rtl838x_nor); + + /* Send read command */ + spi_w32w(sfcsr | SPI_LEN1, SFCSR); + spi_w32w(command << 24, SFDR); + + /* Send address */ + spi_w32w(sfcsr | (sfcsr_addr_len << 28), SFCSR); + spi_w32w(from << sfdr_addr_shift, SFDR); + + /* Dummy cycles */ + spi_w32w(sfcsr | SPI_LEN1, SFCSR); + spi_w32w(0, SFDR); + + /* Start reading */ + spi_w32w(sfcsr | SPI_LEN4, SFCSR); + + /* Read Data, 4 bytes at a time */ + while (length >= 4) { + SPI_WAIT_READY; + *((uint32_t *) buffer) = spi_r32(SFDR); +/* printk("%.8x ", *((uint32_t*) buffer)); */ + buffer += 4; + length -= 4; + } + + /* The rest needs to be read 1 byte a time */ + sfcsr &= SPI_LEN_INIT|SPI_LEN1; + SPI_WAIT_READY; + spi_w32w(sfcsr, SFCSR); + while (length > 0) { + SPI_WAIT_READY; + *(buffer) = spi_r32(SFDR) >> 24; +/* printk("%.2x ", *(buffer)); */ + buffer++; + length--; + } + return len; + +} + +/* + * Do write (Page Programming) in 3 or 4 Byte addressing mode + */ +static ssize_t rtl838x_do_4b_write(struct rtl838x_nor *rtl838x_nor, loff_t to, + size_t length, const u_char *buffer, + uint8_t command) +{ + int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2; + int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8; + uint32_t sfcsr; + uint32_t len = length; + + pr_debug("Write to %llx, len %x, shift %d\n", + to, sfcsr_addr_len, sfdr_addr_shift); + sfcsr = spi_prep(rtl838x_nor); + + /* Send write command, command IO-width is 1 (bit 25/26) */ + spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR); + spi_w32w(command << 24, SFDR); + + /* Send address */ + spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR); + spi_w32w(to << sfdr_addr_shift, SFDR); + + /* Write Data, 1 byte at a time, if we are not 4-byte aligned */ + if (((long)buffer) % 4) { + spi_w32w(sfcsr | SPI_LEN1, SFCSR); + while (length > 0 && (((long)buffer) % 4)) { + SPI_WAIT_READY; + spi_w32(*(buffer) << 24, SFDR); + buffer += 1; + length -= 1; + } + } + + /* Now we can write 4 bytes at a time */ + SPI_WAIT_READY; + spi_w32w(sfcsr | SPI_LEN4, SFCSR); + while (length >= 4) { + SPI_WAIT_READY; + spi_w32(*((uint32_t *)buffer), SFDR); + buffer += 4; + length -= 4; + } + + /* Final bytes might need to be written 1 byte at a time, again */ + SPI_WAIT_READY; + spi_w32w(sfcsr | SPI_LEN1, SFCSR); + while (length > 0) { + SPI_WAIT_READY; + spi_w32(*(buffer) << 24, SFDR); + buffer++; + length--; + } + return len; +} + +static ssize_t rtl838x_nor_write(struct spi_nor *nor, loff_t to, size_t len, + const u_char *buffer) +{ + int ret = 0; + uint32_t offset = 0; + struct rtl838x_nor *rtl838x_nor = nor->priv; + size_t l = len; + uint8_t cmd = SPINOR_OP_PP; + + /* Do write in 4-byte mode on large Macronix chips */ + if (rtl838x_nor->fourByteMode) { + cmd = SPINOR_OP_PP_4B; + spi_4b_set(rtl838x_nor, true); + } + + pr_debug("In %s %8x to: %llx\n", __func__, + (unsigned int) rtl838x_nor, to); + + while (l >= SPI_MAX_TRANSFER_SIZE) { + while + (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP); + do { + spi_write_enable(rtl838x_nor); + } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL)); + ret = rtl838x_do_4b_write(rtl838x_nor, to + offset, + SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd); + l -= SPI_MAX_TRANSFER_SIZE; + offset += SPI_MAX_TRANSFER_SIZE; + } + + if (l > 0) { + while + (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP); + do { + spi_write_enable(rtl838x_nor); + } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL)); + ret = rtl838x_do_4b_write(rtl838x_nor, to+offset, + len, buffer+offset, cmd); + } + + return len; +} + +static ssize_t rtl838x_nor_read(struct spi_nor *nor, loff_t from, + size_t length, u_char *buffer) +{ + uint32_t offset = 0; + uint8_t cmd = SPINOR_OP_READ_FAST; + size_t l = length; + struct rtl838x_nor *rtl838x_nor = nor->priv; + + /* Do fast read in 3, or 4-byte mode on large Macronix chips */ + if (rtl838x_nor->fourByteMode) { + cmd = SPINOR_OP_READ_FAST_4B; + spi_4b_set(rtl838x_nor, true); + } + + /* TODO: do timeout and return error */ + pr_debug("Waiting for pending writes\n"); + while + (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP); + do { + spi_write_enable(rtl838x_nor); + } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL)); + + pr_debug("cmd is %d\n", cmd); + pr_debug("%s: addr %.8llx to addr %.8x, cmd %.8x, size %d\n", __func__, + from, (u32)buffer, (u32)cmd, length); + + while (l >= SPI_MAX_TRANSFER_SIZE) { + rtl838x_do_4bf_read(rtl838x_nor, from + offset, + SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd); + l -= SPI_MAX_TRANSFER_SIZE; + offset += SPI_MAX_TRANSFER_SIZE; + } + + if (l > 0) + rtl838x_do_4bf_read(rtl838x_nor, from + offset, l, buffer+offset, cmd); + + return length; +} + +static int rtl838x_erase(struct spi_nor *nor, loff_t offs) +{ + struct rtl838x_nor *rtl838x_nor = nor->priv; + int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2; + int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8; + uint32_t sfcsr; + uint8_t cmd = SPINOR_OP_SE; + + pr_debug("Erasing sector at %llx\n", offs); + + /* Do erase in 4-byte mode on large Macronix chips */ + if (rtl838x_nor->fourByteMode) { + cmd = SPINOR_OP_SE_4B; + spi_4b_set(rtl838x_nor, true); + } + /* TODO: do timeout and return error */ + while + (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP); + do { + spi_write_enable(rtl838x_nor); + } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL)); + + sfcsr = spi_prep(rtl838x_nor); + + /* Send erase command, command IO-width is 1 (bit 25/26) */ + spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR); + spi_w32w(cmd << 24, SFDR); + + /* Send address */ + spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR); + spi_w32w(offs << sfdr_addr_shift, SFDR); + + return 0; +} + +static int rtl838x_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) +{ + int length = len; + u8 *buffer = buf; + uint32_t sfcsr, sfdr; + struct rtl838x_nor *rtl838x_nor = nor->priv; + + pr_debug("In %s: opcode %x, len %x\n", __func__, opcode, len); + + sfcsr = spi_prep(rtl838x_nor); + sfdr = opcode << 24; + + sfcsr |= SPI_LEN1; + + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + + while (length > 0) { + SPI_WAIT_READY; + *(buffer) = spi_r32(SFDR) >> 24; + buffer++; + length--; + } + + return len; +} + +static int rtl838x_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) +{ + uint32_t sfcsr, sfdr; + struct rtl838x_nor *rtl838x_nor = nor->priv; + + pr_debug("In %s, opcode %x, len %x\n", __func__, opcode, len); + sfcsr = spi_prep(rtl838x_nor); + sfdr = opcode << 24; + + if (len == 1) { /* SPINOR_OP_WRSR */ + sfdr |= buf[0]; + sfcsr |= SPI_LEN2; + } + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + return 0; +} + +static int spi_enter_sio(struct spi_nor *nor) +{ + uint32_t sfcsr, sfcr2, sfdr; + uint32_t ret = 0, reg = 0, size_bits; + struct rtl838x_nor *rtl838x_nor = nor->priv; + + pr_debug("In %s\n", __func__); + rtl838x_nor->io_status = 0; + sfdr = SPI_C_RSTQIO << 24; + sfcsr = spi_prep(rtl838x_nor); + + reg = spi_r32(SFCR2); + pr_debug("SFCR2: %x, size %x, rdopt: %x\n", reg, SFCR2_GETSIZE(reg), + (reg & SFCR2_RDOPT)); + size_bits = rtl838x_nor->fourByteMode ? SFCR2_SIZE(0x6) : SFCR2_SIZE(0x7); + + sfcr2 = SFCR2_HOLD_TILL_SFDR2 | size_bits + | (reg & SFCR2_RDOPT) | SFCR2_CMDIO(0) + | SFCR2_ADDRIO(0) | SFCR2_DUMMYCYCLE(4) + | SFCR2_DATAIO(0) | SFCR2_SFCMD(SPINOR_OP_READ_FAST); + pr_debug("SFCR2: %x, size %x\n", reg, SFCR2_GETSIZE(reg)); + + SPI_WAIT_READY; + spi_w32w(sfcr2, SFCR2); + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + + spi_w32_mask(SFCR2_HOLD_TILL_SFDR2, 0, SFCR2); + rtl838x_nor->io_status &= ~IOSTATUS_CIO_MASK; + rtl838x_nor->io_status |= CIO1; + + spi_prep(rtl838x_nor); + + return ret; +} + +int rtl838x_spi_nor_scan(struct spi_nor *nor, const char *name) +{ + static const struct spi_nor_hwcaps hwcaps = { + .mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_PP + | SNOR_HWCAPS_READ_FAST + }; + + struct rtl838x_nor *rtl838x_nor = nor->priv; + + pr_debug("In %s\n", __func__); + + spi_w32_mask(0, SFCR_EnableWBO, SFCR); + spi_w32_mask(0, SFCR_EnableRBO, SFCR); + + rtl838x_nor->flags = CS0 | R_MODE; + + spi_nor_scan(nor, NULL, &hwcaps); + pr_debug("------------- Got size: %llx\n", nor->mtd.size); + + return 0; +} + +int rtl838x_nor_init(struct rtl838x_nor *rtl838x_nor, + struct device_node *flash_node) +{ + int ret; + struct spi_nor *nor; + + pr_info("%s called\n", __func__); + nor = &rtl838x_nor->nor; + nor->dev = rtl838x_nor->dev; + nor->priv = rtl838x_nor; + spi_nor_set_flash_node(nor, flash_node); + + nor->read_reg = rtl838x_nor_read_reg; + nor->write_reg = rtl838x_nor_write_reg; + nor->read = rtl838x_nor_read; + nor->write = rtl838x_nor_write; + nor->erase = rtl838x_erase; + nor->mtd.name = "rtl838x_nor"; + nor->erase_opcode = rtl838x_nor->fourByteMode ? SPINOR_OP_SE_4B + : SPINOR_OP_SE; + /* initialized with NULL */ + ret = rtl838x_spi_nor_scan(nor, NULL); + if (ret) + return ret; + + spi_enter_sio(nor); + spi_write_disable(rtl838x_nor); + + ret = mtd_device_parse_register(&nor->mtd, NULL, NULL, NULL, 0); + return ret; +} + +static int rtl838x_nor_drv_probe(struct platform_device *pdev) +{ + struct device_node *flash_np; + struct resource *res; + int ret; + struct rtl838x_nor *rtl838x_nor; + int addrMode; + + pr_info("Initializing rtl838x_nor_driver\n"); + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "No DT found\n"); + return -EINVAL; + } + + rtl838x_nor = devm_kzalloc(&pdev->dev, sizeof(*rtl838x_nor), GFP_KERNEL); + if (!rtl838x_nor) + return -ENOMEM; + platform_set_drvdata(pdev, rtl838x_nor); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + rtl838x_nor->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR((void *)rtl838x_nor->base)) + return PTR_ERR((void *)rtl838x_nor->base); + + pr_info("SPI resource base is %08x\n", (u32)rtl838x_nor->base); + rtl838x_nor->dev = &pdev->dev; + + /* only support one attached flash */ + flash_np = of_get_next_available_child(pdev->dev.of_node, NULL); + if (!flash_np) { + dev_err(&pdev->dev, "no SPI flash device to configure\n"); + ret = -ENODEV; + goto nor_free; + } + + /* Get the 3/4 byte address mode as configure by bootloader */ + if (soc_info.family == RTL8390_FAMILY_ID) + addrMode = rtl8390_get_addr_mode(rtl838x_nor); + else + addrMode = rtl838x_get_addr_mode(rtl838x_nor); + pr_info("Address mode is %d bytes\n", addrMode); + if (addrMode == 4) + rtl838x_nor->fourByteMode = true; + + ret = rtl838x_nor_init(rtl838x_nor, flash_np); + +nor_free: + return ret; +} + +static int rtl838x_nor_drv_remove(struct platform_device *pdev) +{ +/* struct rtl8xx_nor *rtl838x_nor = platform_get_drvdata(pdev); */ + return 0; +} + +static const struct of_device_id rtl838x_nor_of_ids[] = { + { .compatible = "realtek,rtl838x-nor"}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtl838x_nor_of_ids); + +static struct platform_driver rtl838x_nor_driver = { + .probe = rtl838x_nor_drv_probe, + .remove = rtl838x_nor_drv_remove, + .driver = { + .name = "rtl838x-nor", + .pm = NULL, + .of_match_table = rtl838x_nor_of_ids, + }, +}; + +module_platform_driver(rtl838x_nor_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("RTL838x SPI NOR Flash Driver"); diff --git a/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h b/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h new file mode 100644 index 0000000000..1209d47b02 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2009 Realtek Semiconductor Corp. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _RTL838X_SPI_H +#define _RTL838X_SPI_H + + +/* + * Register access macros + */ + +#define spi_r32(reg) __raw_readl(rtl838x_nor->base + reg) +#define spi_w32(val, reg) __raw_writel(val, rtl838x_nor->base + reg) +#define spi_w32_mask(clear, set, reg) \ + spi_w32((spi_r32(reg) & ~(clear)) | (set), reg) + +#define SPI_WAIT_READY do { \ + } while (!(spi_r32(SFCSR) & SFCSR_SPI_RDY)) + +#define spi_w32w(val, reg) do { \ + __raw_writel(val, rtl838x_nor->base + reg); \ + SPI_WAIT_READY; \ + } while (0) + +#define SFCR (0x00) /*SPI Flash Configuration Register*/ + #define SFCR_CLK_DIV(val) ((val)<<29) + #define SFCR_EnableRBO (1<<28) + #define SFCR_EnableWBO (1<<27) + #define SFCR_SPI_TCS(val) ((val)<<23) /*4 bit, 1111 */ + +#define SFCR2 (0x04) /*For memory mapped I/O */ + #define SFCR2_SFCMD(val) ((val)<<24) /*8 bit, 1111_1111 */ + #define SFCR2_SIZE(val) ((val)<<21) /*3 bit, 111 */ + #define SFCR2_RDOPT (1<<20) + #define SFCR2_CMDIO(val) ((val)<<18) /*2 bit, 11 */ + #define SFCR2_ADDRIO(val) ((val)<<16) /*2 bit, 11 */ + #define SFCR2_DUMMYCYCLE(val) ((val)<<13) /*3 bit, 111 */ + #define SFCR2_DATAIO(val) ((val)<<11) /*2 bit, 11 */ + #define SFCR2_HOLD_TILL_SFDR2 (1<<10) + #define SFCR2_GETSIZE(x) (((x)&0x00E00000)>>21) + +#define SFCSR (0x08) /*SPI Flash Control&Status Register*/ + #define SFCSR_SPI_CSB0 (1<<31) + #define SFCSR_SPI_CSB1 (1<<30) + #define SFCSR_LEN(val) ((val)<<28) /*2 bits*/ + #define SFCSR_SPI_RDY (1<<27) + #define SFCSR_IO_WIDTH(val) ((val)<<25) /*2 bits*/ + #define SFCSR_CHIP_SEL (1<<24) + #define SFCSR_CMD_BYTE(val) ((val)<<16) /*8 bit, 1111_1111 */ + +#define SFDR (0x0C) /*SPI Flash Data Register*/ +#define SFDR2 (0x10) /*SPI Flash Data Register - for post SPI bootup setting*/ + #define SPI_CS_INIT (SFCSR_SPI_CSB0 | SFCSR_SPI_CSB1 | SPI_LEN1) + #define SPI_CS0 SFCSR_SPI_CSB0 + #define SPI_CS1 SFCSR_SPI_CSB1 + #define SPI_eCS0 ((SFCSR_SPI_CSB1)) /*and SFCSR to active CS0*/ + #define SPI_eCS1 ((SFCSR_SPI_CSB0)) /*and SFCSR to active CS1*/ + + #define SPI_WIP (1) /* Write In Progress */ + #define SPI_WEL (1<<1) /* Write Enable Latch*/ + #define SPI_SST_QIO_WIP (1<<7) /* SST QIO Flash Write In Progress */ + #define SPI_LEN_INIT 0xCFFFFFFF /* and SFCSR to init */ + #define SPI_LEN4 0x30000000 /* or SFCSR to set */ + #define SPI_LEN3 0x20000000 /* or SFCSR to set */ + #define SPI_LEN2 0x10000000 /* or SFCSR to set */ + #define SPI_LEN1 0x00000000 /* or SFCSR to set */ + #define SPI_SETLEN(val) do { \ + SPI_REG(SFCSR) &= 0xCFFFFFFF; \ + SPI_REG(SFCSR) |= (val-1)<<28; \ + } while (0) +/* + * SPI interface control + */ +#define RTL8390_SOC_SPI_MMIO_CONF (0x04) + +#define IOSTATUS_CIO_MASK (0x00000038) + +/* Chip select: bits 4-7*/ +#define CS0 (1<<4) +#define R_MODE 0x04 + +/* io_status */ +#define IO1 (1<<0) +#define IO2 (1<<1) +#define CIO1 (1<<3) +#define CIO2 (1<<4) +#define CMD_IO1 (1<<6) +#define W_ADDR_IO1 ((1)<<12) +#define R_ADDR_IO2 ((2)<<9) +#define R_DATA_IO2 ((2)<<15) +#define W_DATA_IO1 ((1)<<18) + +/* Commands */ +#define SPI_C_RSTQIO 0xFF + +#define SPI_MAX_TRANSFER_SIZE 256 + +#endif /* _RTL838X_SPI_H */ diff --git a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h new file mode 100644 index 0000000000..127a31dca1 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _RTL838X_H +#define _RTL838X_H + +#include + +/* + * Register definition + */ +#define RTL838X_CPU_PORT 28 +#define RTL839X_CPU_PORT 52 + +#define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7))) +#define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7))) +#define RTL838X_RST_GLB_CTRL_0 (0x003c) +#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104) +#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc) + +#define RTL838X_DMY_REG31 (0x3b28) +#define RTL838X_SDS_MODE_SEL (0x0028) +#define RTL838X_SDS_CFG_REG (0x0034) +#define RTL838X_INT_MODE_CTRL (0x005c) +#define RTL838X_CHIP_INFO (0x00d8) +#define RTL839X_CHIP_INFO (0x0ff4) +#define RTL838X_SDS4_REG28 (0xef80) +#define RTL838X_SDS4_DUMMY0 (0xef8c) +#define RTL838X_SDS5_EXT_REG6 (0xf18c) +#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2)) +#define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3)) +#define RTL8380_SDS4_FIB_REG0 (0xF800) +#define RTL838X_STAT_PORT_STD_MIB (0x1200) +#define RTL839X_STAT_PORT_STD_MIB (0xC000) +#define RTL838X_STAT_RST (0x3100) +#define RTL839X_STAT_RST (0xF504) +#define RTL838X_STAT_PORT_RST (0x3104) +#define RTL839X_STAT_PORT_RST (0xF508) +#define RTL838X_STAT_CTRL (0x3108) +#define RTL839X_STAT_CTRL (0x04cc) + +/* Registers of the internal Serdes of the 8380 */ +#define MAPLE_SDS4_REG0r RTL838X_SDS4_REG28 +#define MAPLE_SDS5_REG0r (RTL838X_SDS4_REG28 + 0x100) +#define MAPLE_SDS4_REG3r RTL838X_SDS4_DUMMY0 +#define MAPLE_SDS5_REG3r (RTL838X_SDS4_REG28 + 0x100) +#define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880) +#define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980) + +/* VLAN registers */ +#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2)) +#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84) +#define RTL838X_VLAN_PORT_PB_VLAN(port) (0x3C00 + ((port) << 2)) +#define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C) +#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A7C + 4) + +/* Table 0/1 access registers */ +#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) +#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) +#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8) +#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_CTRL_0 (0x1190) +#define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80) +#define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2)) + +/* MAC handling */ +#define RTL838X_MAC_LINK_STS (0xa188) +#define RTL839X_MAC_LINK_STS (0x0390) +#define RTL838X_MAC_LINK_SPD_STS(port) (0xa190 + (((port >> 4) << 2))) +#define RTL838X_MAC_LINK_DUP_STS (0xa19c) +#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0) +#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4) +#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) +#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) + +/* MAC link state bits */ +#define FORCE_EN (1 << 0) +#define FORCE_LINK_EN (1 << 1) +#define NWAY_EN (1 << 2) +#define DUPLX_MODE (1 << 3) +#define TX_PAUSE_EN (1 << 6) +#define RX_PAUSE_EN (1 << 7) + +/* EEE */ +#define RTL838X_MAC_EEE_ABLTY (0xa1a8) +#define RTL838X_EEE_PORT_TX_EN (0x014c) +#define RTL838X_EEE_PORT_RX_EN (0x0150) +#define RTL838X_EEE_CLK_STOP_CTRL (0x0148) + +/* L2 functionality */ +#define RTL838X_L2_CTRL_0 (0x3200) +#define RTL839X_L2_CTRL_0 (0x3800) +#define RTL838X_L2_CTRL_1 (0x3204) +#define RTL839X_L2_CTRL_1 (0x3804) +#define RTL838X_L2_PORT_AGING_OUT (0x3358) +#define RTL839X_L2_PORT_AGING_OUT (0x3b74) +#define RTL838X_TBL_ACCESS_L2_CTRL (0x6900) +#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180) +#define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2)) +#define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2)) +#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) +#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) + +/* Port Mirroring */ +#define RTL838X_MIR_CTRL(grp) (0x5D00 + (((grp) << 2))) +#define RTL838X_MIR_DPM_CTRL(grp) (0x5D20 + (((grp) << 2))) +#define RTL838X_MIR_SPM_CTRL(grp) (0x5D10 + (((grp) << 2))) + +enum phy_type { + PHY_NONE = 0, + PHY_RTL838X_SDS = 1, + PHY_RTL8218B_INT = 2, + PHY_RTL8218B_EXT = 3, + PHY_RTL8214FC = 4 +}; + +struct rtl838x_port { + bool enable; + u64 pm; + u16 pvid; + bool eee_enabled; + enum phy_type phy; +}; + +struct rtl838x_vlan_info { + u64 untagged_ports; + u64 tagged_ports; + u32 vlan_conf; +}; + +struct rtl838x_switch_priv; + +struct rtl838x_reg { + void (*mask_port_reg)(u64 clear, u64 set, int reg); + void (*set_port_reg)(u64 set, int reg); + u64 (*get_port_reg)(int reg); + int stat_port_rst; + int stat_rst; + int (*stat_port_std_mib)(int p); + void (*mask_port_iso_ctrl)(u64 clear, u64 set, int port); + void (*set_port_iso_ctrl)(u64 set, int port); + int l2_ctrl_0; + int l2_ctrl_1; + int l2_port_aging_out; + int smi_poll_ctrl; + int l2_tbl_flush_ctrl; + void (*exec_tbl0_cmd)(u32 cmd); + void (*exec_tbl1_cmd)(u32 cmd); + int (*tbl_access_data_0)(int i); + int isr_glb_src; + int isr_port_link_sts_chg; + int imr_port_link_sts_chg; + int imr_glb; + void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info); + void (*vlan_set_tagged)(u32 vlan, u64 portmask, u32 conf); + void (*vlan_set_untagged)(u32 vlan, u64 portmask); + int (*mac_force_mode_ctrl)(int port); + int rst_glb_ctrl; +}; + +struct rtl838x_switch_priv { + /* Switch operation */ + struct dsa_switch *ds; + struct device *dev; + u16 id; + u16 family_id; + char version; + struct rtl838x_port ports[54]; /* TODO: correct size! */ + struct mutex reg_mutex; + int link_state_irq; + int mirror_group_ports[4]; + struct mii_bus *mii_bus; + const struct rtl838x_reg *r; + u8 cpu_port; + u8 port_mask; +}; + +extern struct rtl838x_soc_info soc_info; +extern void rtl8380_sds_rst(int mac); + +extern int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val); +extern int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val); +extern int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +extern int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +extern int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val); +extern int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val); + +#endif /* _RTL838X_H */ diff --git a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_phy.c b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_phy.c new file mode 100644 index 0000000000..4440dc99cd --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_phy.c @@ -0,0 +1,1286 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Realtek RTL838X Ethernet MDIO interface driver + * + * Copyright (C) 2020 B. Koblitz + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "rtl838x.h" + +/* External RTL8218B and RTL8214FC IDs are identical */ +#define PHY_ID_RTL8214C 0x001cc942 +#define PHY_ID_RTL8214FC 0x001cc981 +#define PHY_ID_RTL8218B_E 0x001cc981 +#define PHY_ID_RTL8218B_I 0x001cca40 +#define PHY_ID_RTL8390_GENERIC 0x001ccab0 + +struct __attribute__ ((__packed__)) part { + uint16_t start; + uint8_t wordsize; + uint8_t words; +}; + +struct __attribute__ ((__packed__)) fw_header { + uint32_t magic; + uint32_t phy; + uint32_t checksum; + uint32_t version; + struct part parts[10]; +}; + +#define FIRMWARE_838X_8380_1 "rtl838x_phy/rtl838x_8380.fw" +#define FIRMWARE_838X_8214FC_1 "rtl838x_phy/rtl838x_8214fc.fw" +#define FIRMWARE_838X_8218b_1 "rtl838x_phy/rtl838x_8218b.fw" + +static const struct firmware rtl838x_8380_fw; +static const struct firmware rtl838x_8214fc_fw; +static const struct firmware rtl838x_8218b_fw; + +struct rtl838x_phy_priv { + char *name; +}; + +static int read_phy(u32 port, u32 page, u32 reg, u32 *val) +{ + if (soc_info.family == RTL8390_FAMILY_ID) + return rtl839x_read_phy(port, page, reg, val); + else + return rtl838x_read_phy(port, page, reg, val); +} + +static int write_phy(u32 port, u32 page, u32 reg, u32 val) +{ + if (soc_info.family == RTL8390_FAMILY_ID) + return rtl839x_write_phy(port, page, reg, val); + else + return rtl838x_write_phy(port, page, reg, val); +} + +static void rtl8380_int_phy_on_off(int mac, bool on) +{ + u32 val; + + read_phy(mac, 0, 0, &val); + if (on) + write_phy(mac, 0, 0, val & ~(1 << 11)); + else + write_phy(mac, 0, 0, val | (1 << 11)); +} + +static void rtl8380_rtl8214fc_on_off(int mac, bool on) +{ + u32 val; + + /* fiber ports */ + write_phy(mac, 4095, 30, 3); + read_phy(mac, 0, 16, &val); + if (on) + write_phy(mac, 0, 16, val & ~(1 << 11)); + else + write_phy(mac, 0, 16, val | (1 << 11)); + + /* copper ports */ + write_phy(mac, 4095, 30, 1); + read_phy(mac, 0, 16, &val); + if (on) + write_phy(mac, 0xa40, 16, val & ~(1 << 11)); + else + write_phy(mac, 0xa40, 16, val | (1 << 11)); +} + +static void rtl8380_phy_reset(int mac) +{ + u32 val; + + read_phy(mac, 0, 0, &val); + write_phy(mac, 0, 0, val | (0x1 << 15)); +} + +void rtl8380_sds_rst(int mac) +{ + u32 offset = (mac == 24) ? 0 : 0x100; + + sw_w32_mask(1 << 11, 0, RTL8380_SDS4_FIB_REG0 + offset); + sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset); + sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset); + sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset); + sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset); + pr_info("SERDES reset: %d\n", mac); +} + +static struct fw_header * +rtl838x_request_fw(struct phy_device *phydev, const struct firmware *fw, + const char *name) +{ + struct device *dev = &phydev->mdio.dev; + int err; + struct fw_header *h; + uint32_t checksum, my_checksum; + + err = request_firmware(&fw, name, dev); + if (err < 0) + goto out; + + if (fw->size < sizeof(struct fw_header)) { + pr_err("Firmware size too small.\n"); + err = -EINVAL; + goto out; + } + + h = (struct fw_header *) fw->data; + pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic); + + if (h->phy != 0x83800000) { + pr_err("Wrong firmware file: PHY mismatch.\n"); + goto out; + } + + checksum = h->checksum; + h->checksum = 0; + my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size); + if (checksum != my_checksum) { + pr_err("Firmware checksum mismatch.\n"); + err = -EINVAL; + goto out; + } + h->checksum = checksum; + + return h; +out: + dev_err(dev, "Unable to load firmware %s (%d)\n", name, err); + return NULL; +} + +static int rtl8390_configure_generic(struct phy_device *phydev) +{ + u32 val, phy_id; + int mac = phydev->mdio.addr; + + read_phy(mac, 0, 2, &val); + phy_id = val << 16; + read_phy(mac, 0, 3, &val); + phy_id |= val; + pr_debug("Phy on MAC %d: %x\n", mac, phy_id); + + /* Read internal PHY ID */ + write_phy(mac, 31, 27, 0x0002); + read_phy(mac, 31, 28, &val); + + /* Internal RTL8218B, version 2 */ + phydev_info(phydev, "Detected unknown %x\n", val); + return 0; +} + +static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev) +{ + u32 val, phy_id; + int i, p, ipd_flag; + int mac = phydev->mdio.addr; + struct fw_header *h; + u32 *rtl838x_6275B_intPhy_perport; + u32 *rtl8218b_6276B_hwEsd_perport; + + + read_phy(mac, 0, 2, &val); + phy_id = val << 16; + read_phy(mac, 0, 3, &val); + phy_id |= val; + pr_debug("Phy on MAC %d: %x\n", mac, phy_id); + + /* Read internal PHY ID */ + write_phy(mac, 31, 27, 0x0002); + read_phy(mac, 31, 28, &val); + if (val != 0x6275) { + phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val); + return -1; + } + + /* Internal RTL8218B, version 2 */ + phydev_info(phydev, "Detected internal RTL8218B\n"); + + h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1); + if (!h) + return -1; + + if (h->phy != 0x83800000) { + phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n"); + return -1; + } + + rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) + + h->parts[8].start; + + rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) + + h->parts[9].start; + + if (sw_r32(RTL838X_DMY_REG31) == 0x1) + ipd_flag = 1; + + read_phy(mac, 0, 0, &val); + if (val & (1 << 11)) + rtl8380_int_phy_on_off(mac, true); + else + rtl8380_phy_reset(mac); + msleep(100); + + /* Ready PHY for patch */ + for (p = 0; p < 8; p++) { + write_phy(mac + p, 0xfff, 0x1f, 0x0b82); + write_phy(mac + p, 0xfff, 0x10, 0x0010); + } + msleep(500); + for (p = 0; p < 8; p++) { + for (i = 0; i < 100 ; i++) { + read_phy(mac + p, 0x0b80, 0x10, &val); + if (val & 0x40) + break; + } + if (i >= 100) { + phydev_err(phydev, + "ERROR: Port %d not ready for patch.\n", + mac + p); + return -1; + } + } + for (p = 0; p < 8; p++) { + i = 0; + while (rtl838x_6275B_intPhy_perport[i * 2]) { + write_phy(mac + p, 0xfff, + rtl838x_6275B_intPhy_perport[i * 2], + rtl838x_6275B_intPhy_perport[i * 2 + 1]); + i++; + } + i = 0; + while (rtl8218b_6276B_hwEsd_perport[i * 2]) { + write_phy(mac + p, 0xfff, + rtl8218b_6276B_hwEsd_perport[i * 2], + rtl8218b_6276B_hwEsd_perport[i * 2 + 1]); + i++; + } + } + return 0; +} + +static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev) +{ + u32 val, ipd, phy_id; + int i, l; + int mac = phydev->mdio.addr; + struct fw_header *h; + u32 *rtl8380_rtl8218b_perchip; + u32 *rtl8218B_6276B_rtl8380_perport; + u32 *rtl8380_rtl8218b_perport; + + if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) { + phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n"); + return -1; + } + read_phy(mac, 0, 2, &val); + phy_id = val << 16; + read_phy(mac, 0, 3, &val); + phy_id |= val; + pr_info("Phy on MAC %d: %x\n", mac, phy_id); + + /* Read internal PHY ID */ + write_phy(mac, 31, 27, 0x0002); + read_phy(mac, 31, 28, &val); + if (val != 0x6276) { + phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val); + return -1; + } + phydev_info(phydev, "Detected external RTL8218B\n"); + + h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1); + if (!h) + return -1; + + if (h->phy != 0x8218b00) { + phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n"); + return -1; + } + + rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) + + h->parts[0].start; + + rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) + + h->parts[1].start; + + rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) + + h->parts[2].start; + + read_phy(mac, 0, 0, &val); + if (val & (1 << 11)) + rtl8380_int_phy_on_off(mac, true); + else + rtl8380_phy_reset(mac); + msleep(100); + + /* Get Chip revision */ + write_phy(mac, 0xfff, 0x1f, 0x0); + write_phy(mac, 0xfff, 0x1b, 0x4); + read_phy(mac, 0xfff, 0x1c, &val); + + i = 0; + while (rtl8380_rtl8218b_perchip[i * 3] + && rtl8380_rtl8218b_perchip[i * 3 + 1]) { + write_phy(mac + rtl8380_rtl8218b_perchip[i * 3], + 0xfff, rtl8380_rtl8218b_perchip[i * 3 + 1], + rtl8380_rtl8218b_perchip[i * 3 + 2]); + i++; + } + + /* Enable PHY */ + for (i = 0; i < 8; i++) { + write_phy(mac + i, 0xfff, 0x1f, 0x0000); + write_phy(mac + i, 0xfff, 0x00, 0x1140); + } + mdelay(100); + + /* Request patch */ + for (i = 0; i < 8; i++) { + write_phy(mac + i, 0xfff, 0x1f, 0x0b82); + write_phy(mac + i, 0xfff, 0x10, 0x0010); + } + mdelay(300); + + /* Verify patch readiness */ + for (i = 0; i < 8; i++) { + for (l = 0; l < 100; l++) { + read_phy(mac + i, 0xb80, 0x10, &val); + if (val & 0x40) + break; + } + if (l >= 100) { + phydev_err(phydev, "Could not patch PHY\n"); + return -1; + } + } + + /* Use Broadcast ID method for patching */ + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0008); + write_phy(mac, 0xfff, 0x1f, 0x0266); + write_phy(mac, 0xfff, 0x16, 0xff00 + mac); + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0000); + mdelay(1); + + write_phy(mac, 0xfff, 30, 8); + write_phy(mac, 0x26e, 17, 0xb); + write_phy(mac, 0x26e, 16, 0x2); + mdelay(1); + read_phy(mac, 0x26e, 19, &ipd); + write_phy(mac, 0, 30, 0); + ipd = (ipd >> 4) & 0xf; + + i = 0; + while (rtl8218B_6276B_rtl8380_perport[i * 2]) { + write_phy(mac, 0xfff, rtl8218B_6276B_rtl8380_perport[i * 2], + rtl8218B_6276B_rtl8380_perport[i * 2 + 1]); + i++; + } + + /*Disable broadcast ID*/ + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0008); + write_phy(mac, 0xfff, 0x1f, 0x0266); + write_phy(mac, 0xfff, 0x16, 0x00 + mac); + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0000); + mdelay(1); + + return 0; +} + +static int rtl8218b_ext_match_phy_device(struct phy_device *phydev) +{ + int addr = phydev->mdio.addr; + + return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8; +} + + +static int rtl8380_rtl8218b_write_mmd(struct phy_device *phydev, + int devnum, u16 regnum, u16 val) +{ + int addr = phydev->mdio.addr; + + return rtl838x_write_mmd_phy(addr, devnum, regnum, val); +} + +static int rtl8380_rtl8218b_read_mmd(struct phy_device *phydev, + int devnum, u16 regnum) +{ + int ret; + u32 val; + int addr = phydev->mdio.addr; + + ret = rtl838x_read_mmd_phy(addr, devnum, regnum, &val); + if (ret) + return ret; + return val; +} + +static void rtl8380_rtl8214fc_media_set(int mac, bool set_fibre) +{ + int base = mac - (mac % 4); + static int reg[] = {16, 19, 20, 21}; + int val, media, power; + + pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre); + write_phy(base, 0xfff, 29, 8); + read_phy(base, 0x266, reg[mac % 4], &val); + + media = (val >> 10) & 0x3; + pr_info("Current media %x\n", media); + if (media & 0x2) { + pr_info("Powering off COPPER\n"); + write_phy(base, 0xfff, 29, 1); + /* Ensure power is off */ + read_phy(base, 0xa40, 16, &power); + if (!(power & (1 << 11))) + write_phy(base, 0xa40, 16, power | (1 << 11)); + } else { + pr_info("Powering off FIBRE"); + write_phy(base, 0xfff, 29, 3); + /* Ensure power is off */ + read_phy(base, 0xa40, 16, &power); + if (!(power & (1 << 11))) + write_phy(base, 0xa40, 16, power | (1 << 11)); + } + + if (set_fibre) { + val |= 1 << 10; + val &= ~(1 << 11); + } else { + val |= 1 << 10; + val |= 1 << 11; + } + write_phy(base, 0xfff, 29, 8); + write_phy(base, 0x266, reg[mac % 4], val); + write_phy(base, 0xfff, 29, 0); + + if (set_fibre) { + pr_info("Powering on FIBRE"); + write_phy(base, 0xfff, 29, 3); + /* Ensure power is off */ + read_phy(base, 0xa40, 16, &power); + if (power & (1 << 11)) + write_phy(base, 0xa40, 16, power & ~(1 << 11)); + } else { + pr_info("Powering on COPPER\n"); + write_phy(base, 0xfff, 29, 1); + /* Ensure power is off */ + read_phy(base, 0xa40, 16, &power); + if (power & (1 << 11)) + write_phy(base, 0xa40, 16, power & ~(1 << 11)); + } + + write_phy(base, 0xfff, 29, 0); +} + +static bool rtl8380_rtl8214fc_media_is_fibre(int mac) +{ + int base = mac - (mac % 4); + static int reg[] = {16, 19, 20, 21}; + u32 val; + + write_phy(base, 0xfff, 29, 8); + read_phy(base, 0x266, reg[mac % 4], &val); + write_phy(base, 0xfff, 29, 0); + if (val & (1 << 11)) + return false; + return true; +} + +static int rtl8380_rtl8214fc_set_port(struct phy_device *phydev, int port) +{ + bool is_fibre = (port == PORT_FIBRE ? true : false); + int addr = phydev->mdio.addr; + + pr_debug("%s port %d to %d\n", __func__, addr, port); + + rtl8380_rtl8214fc_media_set(addr, is_fibre); + return 0; +} + +static int rtl8380_rtl8214fc_get_port(struct phy_device *phydev) +{ + int addr = phydev->mdio.addr; + + pr_debug("%s: port %d\n", __func__, addr); + if (rtl8380_rtl8214fc_media_is_fibre(addr)) + return PORT_FIBRE; + return PORT_MII; +} + +void rtl8380_rtl8214fc_ldps_set(int mac, struct ethtool_eee *e) +{ + +} + +static void rtl8380_rtl8218b_eee_set_u_boot(int port, bool enable) +{ + u32 val; + bool an_enabled; + + /* Set GPHY page to copper */ + write_phy(port, 0, 30, 0x0001); + read_phy(port, 0, 0, &val); + an_enabled = val & (1 << 12); + + if (enable) { + /* 100/1000M EEE Capability */ + write_phy(port, 0, 13, 0x0007); + write_phy(port, 0, 14, 0x003C); + write_phy(port, 0, 13, 0x4007); + write_phy(port, 0, 14, 0x0006); + + read_phy(port, 0x0A43, 25, &val); + val |= 1 << 4; + write_phy(port, 0x0A43, 25, val); + } else { + /* 100/1000M EEE Capability */ + write_phy(port, 0, 13, 0x0007); + write_phy(port, 0, 14, 0x003C); + write_phy(port, 0, 13, 0x0007); + write_phy(port, 0, 14, 0x0000); + + read_phy(port, 0x0A43, 25, &val); + val &= ~(1 << 4); + write_phy(port, 0x0A43, 25, val); + } + + /* Restart AN if enabled */ + if (an_enabled) { + read_phy(port, 0, 0, &val); + val |= (1 << 12) | (1 << 9); + write_phy(port, 0, 0, val); + } + + /* GPHY page back to auto*/ + write_phy(port, 0xa42, 29, 0); +} + +static int rtl8380_rtl8218b_get_eee_u_boot(struct phy_device *phydev, struct ethtool_eee *e) +{ + u32 val; + int addr = phydev->mdio.addr; + + pr_debug("In %s %d\n", __func__, addr); + + /* Set GPHY page to copper */ + write_phy(addr, 0xa42, 29, 0x0001); + + read_phy(addr, 0xa43, 25, &val); + if (e->eee_enabled && (!!(val & (1 << 4)))) + e->eee_enabled = !!(val & (1 << 4)); + else + e->eee_enabled = 0; + + /* GPHY page to auto */ + write_phy(addr, 0xa42, 29, 0x0000); + + return 0; +} + +void rtl8380_rtl8218b_eee_set(int port, bool enable) +{ + u32 val; + bool an_enabled; + + pr_debug("In %s %d, enable %d\n", __func__, port, enable); + /* Set GPHY page to copper */ + write_phy(port, 0xa42, 29, 0x0001); + + read_phy(port, 0, 0, &val); + an_enabled = val & (1 << 12); + + /* MAC based EEE */ + read_phy(port, 0xa43, 25, &val); + val &= ~(1 << 5); + write_phy(port, 0xa43, 25, val); + + /* 100M / 1000M EEE */ + if (enable) + rtl838x_write_mmd_phy(port, 7, 60, 0x6); + else + rtl838x_write_mmd_phy(port, 7, 60, 0); + + /* 500M EEE ability */ + read_phy(port, 0xa42, 20, &val); + if (enable) + val |= 1 << 7; + else + val &= ~(1 << 7); + write_phy(port, 0xa42, 20, val); + + /* Restart AN if enabled */ + if (an_enabled) { + read_phy(port, 0, 0, &val); + val |= (1 << 12) | (1 << 9); + write_phy(port, 0, 0, val); + } + + /* GPHY page back to auto*/ + write_phy(port, 0xa42, 29, 0); +} + +int rtl8380_rtl8218b_get_eee(struct phy_device *phydev, + struct ethtool_eee *e) +{ + u32 val; + int addr = phydev->mdio.addr; + + pr_debug("In %s, port %d\n", __func__, addr); + + /* Set GPHY page to copper */ + write_phy(addr, 0xa42, 29, 0x0001); + + rtl838x_read_mmd_phy(addr, 7, 60, &val); + if (e->eee_enabled && (!!(val & (1 << 7)))) + e->eee_enabled = !!(val & (1 << 7)); + else + e->eee_enabled = 0; + + /* GPHY page to auto */ + write_phy(addr, 0xa42, 29, 0x0000); + + return 0; +} + +void rtl8380_rtl8218b_green_set(int mac, bool enable) +{ + u32 val; + + /* Set GPHY page to copper */ + write_phy(mac, 0xa42, 29, 0x0001); + + write_phy(mac, 0, 27, 0x8011); + read_phy(mac, 0, 28, &val); + if (enable) { + val |= 1 << 9; + write_phy(mac, 0, 27, 0x8011); + write_phy(mac, 0, 28, val); + } else { + val &= ~(1 << 9); + write_phy(mac, 0, 27, 0x8011); + write_phy(mac, 0, 28, val); + } + + /* GPHY page to auto */ + write_phy(mac, 0xa42, 29, 0x0000); +} + +int rtl8380_rtl8214fc_get_green(struct phy_device *phydev, struct ethtool_eee *e) +{ + u32 val; + int addr = phydev->mdio.addr; + + pr_debug("In %s %d\n", __func__, addr); + /* Set GPHY page to copper */ + write_phy(addr, 0xa42, 29, 0x0001); + + write_phy(addr, 0, 27, 0x8011); + read_phy(addr, 0, 28, &val); + if (e->eee_enabled && (!!(val & (1 << 9)))) + e->eee_enabled = !!(val & (1 << 9)); + else + e->eee_enabled = 0; + + /* GPHY page to auto */ + write_phy(addr, 0xa42, 29, 0x0000); + + return 0; +} + +static int rtl8380_rtl8214fc_set_eee(struct phy_device *phydev, + struct ethtool_eee *e) +{ + u32 pollMask; + int addr = phydev->mdio.addr; + + pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled); + + if (rtl8380_rtl8214fc_media_is_fibre(addr)) { + netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr); + return -ENOTSUPP; + } + + pollMask = sw_r32(RTL838X_SMI_POLL_CTRL); + sw_w32(0, RTL838X_SMI_POLL_CTRL); + rtl8380_rtl8218b_eee_set_u_boot(addr, (bool) e->eee_enabled); + sw_w32(pollMask, RTL838X_SMI_POLL_CTRL); + return 0; +} + +static int rtl8380_rtl8214fc_get_eee(struct phy_device *phydev, + struct ethtool_eee *e) +{ + int addr = phydev->mdio.addr; + + pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled); + if (rtl8380_rtl8214fc_media_is_fibre(addr)) { + netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr); + return -ENOTSUPP; + } + + return rtl8380_rtl8218b_get_eee_u_boot(phydev, e); +} + +static int rtl8380_rtl8218b_set_eee(struct phy_device *phydev, + struct ethtool_eee *e) +{ + u32 pollMask; + int addr = phydev->mdio.addr; + + pr_debug("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled); + + pollMask = sw_r32(RTL838X_SMI_POLL_CTRL); + sw_w32(0, RTL838X_SMI_POLL_CTRL); + rtl8380_rtl8218b_eee_set_u_boot(addr, (bool) e->eee_enabled); + sw_w32(pollMask, RTL838X_SMI_POLL_CTRL); + + return 0; +} + +static int rtl8214c_match_phy_device(struct phy_device *phydev) +{ + return phydev->phy_id == PHY_ID_RTL8214C; +} + +static int rtl8380_configure_rtl8214c(struct phy_device *phydev) +{ + u32 phy_id, val; + int mac = phydev->mdio.addr; + + read_phy(mac, 0, 2, &val); + phy_id = val << 16; + read_phy(mac, 0, 3, &val); + phy_id |= val; + pr_debug("Phy on MAC %d: %x\n", mac, phy_id); + + phydev_info(phydev, "Detected external RTL8214C\n"); + + /* GPHY auto conf */ + write_phy(mac, 0xa42, 29, 0); + return 0; +} + +static int rtl8380_configure_rtl8214fc(struct phy_device *phydev) +{ + u32 phy_id, val, page = 0; + int i, l; + int mac = phydev->mdio.addr; + struct fw_header *h; + u32 *rtl8380_rtl8214fc_perchip; + u32 *rtl8380_rtl8214fc_perport; + + read_phy(mac, 0, 2, &val); + phy_id = val << 16; + read_phy(mac, 0, 3, &val); + phy_id |= val; + pr_debug("Phy on MAC %d: %x\n", mac, phy_id); + + /* Read internal PHY id */ + write_phy(mac, 0, 30, 0x0001); + write_phy(mac, 0, 31, 0x0a42); + write_phy(mac, 31, 27, 0x0002); + read_phy(mac, 31, 28, &val); + if (val != 0x6276) { + phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val); + return -1; + } + phydev_info(phydev, "Detected external RTL8214FC\n"); + + h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1); + if (!h) + return -1; + + if (h->phy != 0x8214fc00) { + phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n"); + return -1; + } + + rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header) + + h->parts[0].start; + + rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header) + + h->parts[1].start; + + /* detect phy version */ + write_phy(mac, 0xfff, 27, 0x0004); + read_phy(mac, 0xfff, 28, &val); + + read_phy(mac, 0, 16, &val); + if (val & (1 << 11)) + rtl8380_rtl8214fc_on_off(mac, true); + else + rtl8380_phy_reset(mac); + + msleep(100); + write_phy(mac, 0, 30, 0x0001); + + i = 0; + while (rtl8380_rtl8214fc_perchip[i * 3] + && rtl8380_rtl8214fc_perchip[i * 3 + 1]) { + if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f) + page = rtl8380_rtl8214fc_perchip[i * 3 + 2]; + if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) { + read_phy(mac + rtl8380_rtl8214fc_perchip[i * 3], 0x260, 13, &val); + val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2] + & 0xe0ff); + write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3], + 0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1], val); + } else { + write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3], + 0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1], + rtl8380_rtl8214fc_perchip[i * 3 + 2]); + } + i++; + } + + /* Force copper medium */ + for (i = 0; i < 4; i++) { + write_phy(mac + i, 0xfff, 0x1f, 0x0000); + write_phy(mac + i, 0xfff, 0x1e, 0x0001); + } + + /* Enable PHY */ + for (i = 0; i < 4; i++) { + write_phy(mac + i, 0xfff, 0x1f, 0x0000); + write_phy(mac + i, 0xfff, 0x00, 0x1140); + } + mdelay(100); + + /* Disable Autosensing */ + for (i = 0; i < 4; i++) { + for (l = 0; l < 100; l++) { + read_phy(mac + i, 0x0a42, 0x10, &val); + if ((val & 0x7) >= 3) + break; + } + if (l >= 100) { + phydev_err(phydev, "Could not disable autosensing\n"); + return -1; + } + } + + /* Request patch */ + for (i = 0; i < 4; i++) { + write_phy(mac + i, 0xfff, 0x1f, 0x0b82); + write_phy(mac + i, 0xfff, 0x10, 0x0010); + } + mdelay(300); + + /* Verify patch readiness */ + for (i = 0; i < 4; i++) { + for (l = 0; l < 100; l++) { + read_phy(mac + i, 0xb80, 0x10, &val); + if (val & 0x40) + break; + } + if (l >= 100) { + phydev_err(phydev, "Could not patch PHY\n"); + return -1; + } + } + + /* Use Broadcast ID method for patching */ + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0008); + write_phy(mac, 0xfff, 0x1f, 0x0266); + write_phy(mac, 0xfff, 0x16, 0xff00 + mac); + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0000); + mdelay(1); + + i = 0; + while (rtl8380_rtl8214fc_perport[i * 2]) { + write_phy(mac, 0xfff, rtl8380_rtl8214fc_perport[i * 2], + rtl8380_rtl8214fc_perport[i * 2 + 1]); + i++; + } + + /*Disable broadcast ID*/ + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0008); + write_phy(mac, 0xfff, 0x1f, 0x0266); + write_phy(mac, 0xfff, 0x16, 0x00 + mac); + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0000); + mdelay(1); + + /* Auto medium selection */ + for (i = 0; i < 4; i++) { + write_phy(mac + i, 0xfff, 0x1f, 0x0000); + write_phy(mac + i, 0xfff, 0x1e, 0x0000); + } + + return 0; +} + +static int rtl8214fc_match_phy_device(struct phy_device *phydev) +{ + int addr = phydev->mdio.addr; + + return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24; +} + +static int rtl8380_configure_serdes(struct phy_device *phydev) +{ + u32 v; + u32 sds_conf_value; + int i; + struct fw_header *h; + u32 *rtl8380_sds_take_reset; + u32 *rtl8380_sds_common; + u32 *rtl8380_sds01_qsgmii_6275b; + u32 *rtl8380_sds23_qsgmii_6275b; + u32 *rtl8380_sds4_fiber_6275b; + u32 *rtl8380_sds5_fiber_6275b; + u32 *rtl8380_sds_reset; + u32 *rtl8380_sds_release_reset; + + phydev_info(phydev, "Detected internal RTL8380 SERDES\n"); + + h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1); + if (!h) + return -1; + + if (h->magic != 0x83808380) { + phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n"); + return -1; + } + + rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) + + h->parts[0].start; + + rtl8380_sds_common = (void *)h + sizeof(struct fw_header) + + h->parts[1].start; + + rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + + h->parts[2].start; + + rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + + h->parts[3].start; + + rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) + + h->parts[4].start; + + rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) + + h->parts[5].start; + + rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) + + h->parts[6].start; + + rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) + + h->parts[7].start; + + /* Back up serdes power off value */ + sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG); + pr_info("SDS power down value: %x\n", sds_conf_value); + + /* take serdes into reset */ + i = 0; + while (rtl8380_sds_take_reset[2 * i]) { + sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]); + i++; + udelay(1000); + } + + /* apply common serdes patch */ + i = 0; + while (rtl8380_sds_common[2 * i]) { + sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]); + i++; + udelay(1000); + } + + /* internal R/W enable */ + sw_w32(3, RTL838X_INT_RW_CTRL); + + /* SerDes ports 4 and 5 are FIBRE ports */ + sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL); + + /* SerDes module settings, SerDes 0-3 are QSGMII */ + v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10; + /* SerDes 4 and 5 are 1000BX FIBRE */ + v |= 0x4 << 5 | 0x4; + sw_w32(v, RTL838X_SDS_MODE_SEL); + + pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL)); + sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL); + i = 0; + while (rtl8380_sds01_qsgmii_6275b[2 * i]) { + sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1], + rtl8380_sds01_qsgmii_6275b[2 * i]); + i++; + } + + i = 0; + while (rtl8380_sds23_qsgmii_6275b[2 * i]) { + sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]); + i++; + } + + i = 0; + while (rtl8380_sds4_fiber_6275b[2 * i]) { + sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]); + i++; + } + + i = 0; + while (rtl8380_sds5_fiber_6275b[2 * i]) { + sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]); + i++; + } + + i = 0; + while (rtl8380_sds_reset[2 * i]) { + sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]); + i++; + } + + i = 0; + while (rtl8380_sds_release_reset[2 * i]) { + sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]); + i++; + } + + pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG)); + sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG); + + pr_info("Configuration of SERDES done\n"); + return 0; +} + +static int rtl8214fc_phy_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct rtl838x_phy_priv *priv; + int addr = phydev->mdio.addr; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->name = "RTL8214FC"; + + /* All base addresses of the PHYs start at multiples of 8 */ + if (!(addr % 8)) { + /* Configuration must be done whil patching still possible */ + return rtl8380_configure_rtl8214fc(phydev); + } + return 0; +} + +static int rtl8214c_phy_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct rtl838x_phy_priv *priv; + int addr = phydev->mdio.addr; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->name = "RTL8214C"; + + /* All base addresses of the PHYs start at multiples of 8 */ + if (!(addr % 8)) { + /* Configuration must be done whil patching still possible */ + return rtl8380_configure_rtl8214c(phydev); + } + return 0; +} + +static int rtl8218b_ext_phy_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct rtl838x_phy_priv *priv; + int addr = phydev->mdio.addr; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->name = "RTL8218B (external)"; + + /* All base addresses of the PHYs start at multiples of 8 */ + if (!(addr % 8)) { + /* Configuration must be done while patching still possible */ + return rtl8380_configure_ext_rtl8218b(phydev); + } + return 0; +} + +static int rtl8218b_int_phy_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct rtl838x_phy_priv *priv; + int addr = phydev->mdio.addr; + + if (soc_info.family != RTL8380_FAMILY_ID) + return -ENODEV; + if (addr >= 24) + return -ENODEV; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->name = "RTL8218B (internal)"; + + /* All base addresses of the PHYs start at multiples of 8 */ + if (!(addr % 8)) { + /* Configuration must be done while patching still possible */ + return rtl8380_configure_int_rtl8218b(phydev); + } + return 0; +} + +static int rtl838x_serdes_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct rtl838x_phy_priv *priv; + int addr = phydev->mdio.addr; + + if (soc_info.family != RTL8380_FAMILY_ID) + return -ENODEV; + if (addr < 24) + return -ENODEV; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->name = "RTL8380 Serdes"; + + /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */ + if (soc_info.id == 0x8380) { + if (addr == 24) + return rtl8380_configure_serdes(phydev); + return 0; + } + return -ENODEV; +} + +static int rtl8390_serdes_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct rtl838x_phy_priv *priv; + int addr = phydev->mdio.addr; + + if (soc_info.family != RTL8390_FAMILY_ID) + return -ENODEV; + + if (addr < 24) + return -ENODEV; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->name = "RTL8390 Serdes"; + return rtl8390_configure_generic(phydev); +} + +static struct phy_driver rtl838x_phy_driver[] = { + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC), + .name = "REATLTEK RTL8214C", + .features = PHY_GBIT_FEATURES, + .match_phy_device = rtl8214c_match_phy_device, + .probe = rtl8214c_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .set_loopback = genphy_loopback, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC), + .name = "REATLTEK RTL8214FC", + .features = PHY_GBIT_FIBRE_FEATURES, + .match_phy_device = rtl8214fc_match_phy_device, + .probe = rtl8214fc_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .set_loopback = genphy_loopback, + .read_mmd = rtl8380_rtl8218b_read_mmd, + .write_mmd = rtl8380_rtl8218b_write_mmd, + .set_port = rtl8380_rtl8214fc_set_port, + .get_port = rtl8380_rtl8214fc_get_port, + .set_eee = rtl8380_rtl8214fc_set_eee, + .get_eee = rtl8380_rtl8214fc_get_eee, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E), + .name = "REATLTEK RTL8218B (external)", + .features = PHY_GBIT_FEATURES, + .match_phy_device = rtl8218b_ext_match_phy_device, + .probe = rtl8218b_ext_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .set_loopback = genphy_loopback, + .read_mmd = rtl8380_rtl8218b_read_mmd, + .write_mmd = rtl8380_rtl8218b_write_mmd, + .set_eee = rtl8380_rtl8218b_set_eee, + .get_eee = rtl8380_rtl8218b_get_eee_u_boot, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I), + .name = "REATLTEK RTL8218B (internal)", + .features = PHY_GBIT_FEATURES, + .probe = rtl8218b_int_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .set_loopback = genphy_loopback, + .read_mmd = rtl8380_rtl8218b_read_mmd, + .write_mmd = rtl8380_rtl8218b_write_mmd, + .set_eee = rtl8380_rtl8218b_set_eee, + .get_eee = rtl8380_rtl8218b_get_eee_u_boot, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I), + .name = "REATLTEK RTL8380 SERDES", + .features = PHY_GBIT_FIBRE_FEATURES, + .probe = rtl838x_serdes_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .set_loopback = genphy_loopback, + .read_mmd = rtl8380_rtl8218b_read_mmd, + .write_mmd = rtl8380_rtl8218b_write_mmd, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC), + .name = "REATLTEK RTL8390 Generic", + .features = PHY_GBIT_FIBRE_FEATURES, + .probe = rtl8390_serdes_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .set_loopback = genphy_loopback, + } +}; + +module_phy_driver(rtl838x_phy_driver); + +static struct mdio_device_id __maybe_unused rtl838x_tbl[] = { + { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) }, + { } +}; + +MODULE_DEVICE_TABLE(mdio, rtl838x_tbl); + +MODULE_AUTHOR("B. Koblitz"); +MODULE_DESCRIPTION("RTL838x PHY driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c new file mode 100644 index 0000000000..7f6c2d6a29 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c @@ -0,0 +1,2150 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "rtl838x.h" + +#define RTL8380_VERSION_A 'A' +#define RTL8390_VERSION_A 'A' +#define RTL8380_VERSION_B 'B' + +DEFINE_MUTEX(smi_lock); + +#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} +struct rtl838x_mib_desc { + unsigned int size; + unsigned int offset; + const char *name; +}; + +inline void rtl838x_mask_port_reg(u64 clear, u64 set, int reg) +{ + sw_w32_mask((u32)clear, (u32)set, reg); +} + +inline void rtl839x_mask_port_reg(u64 clear, u64 set, int reg) +{ + sw_w32_mask((u32) (clear >> 32), (u32) (set >> 32), reg); + sw_w32_mask((u32) (clear & 0xffffffff), (u32) (set & 0xffffffff), reg + 4); +} + +inline void rtl838x_set_port_reg(u64 set, int reg) +{ + sw_w32(set, reg); +} + +inline void rtl839x_set_port_reg(u64 set, int reg) +{ + sw_w32(set >> 32, reg); + sw_w32(set & 0xffffffff, reg + 4); +} + +inline u64 rtl838x_get_port_reg(int reg) +{ + return ((u64) sw_r32(reg)); +} + +inline u64 rtl839x_get_port_reg(int reg) +{ + u64 v = sw_r32(reg); + + v <<= 32; + v |= sw_r32(reg + 4); + return v; +} + +inline int rtl838x_stat_port_std_mib(int p) +{ + return RTL838X_STAT_PORT_STD_MIB + (p << 8); +} + +inline int rtl839x_stat_port_std_mib(int p) +{ + return RTL839X_STAT_PORT_STD_MIB + (p << 8); +} + +inline void rtl838x_mask_port_iso_ctrl(u64 clear, u64 set, int port) +{ + sw_w32_mask(clear, set, RTL838X_PORT_ISO_CTRL(port)); +} + +inline void rtl839x_mask_port_iso_ctrl(u64 clear, u64 set, int port) +{ + sw_w32_mask(clear >> 32, set >> 32, RTL839X_PORT_ISO_CTRL(port)); + sw_w32_mask(clear & 0xffffffff, set & 0xffffffff, + RTL839X_PORT_ISO_CTRL(port) + 4); +} + +inline void rtl838x_set_port_iso_ctrl(u64 set, int port) +{ + sw_w32(set, RTL838X_PORT_ISO_CTRL(port)); +} + +inline void rtl839x_set_port_iso_ctrl(u64 set, int port) +{ + sw_w32(set >> 32, RTL839X_PORT_ISO_CTRL(port)); + sw_w32(set & 0xffffffff, RTL839X_PORT_ISO_CTRL(port) + 4); +} + +inline void rtl838x_exec_tbl0_cmd(u32 cmd) +{ + sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0); + do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & (1 << 15)); +} + +inline void rtl839x_exec_tbl0_cmd(u32 cmd) +{ + sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0); + do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & (1 << 16)); +} + +inline void rtl838x_exec_tbl1_cmd(u32 cmd) +{ + sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1); + do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & (1 << 15)); +} + +inline void rtl839x_exec_tbl1_cmd(u32 cmd) +{ + sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1); + do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & (1 << 16)); +} + +inline int rtl838x_tbl_access_data_0(int i) +{ + return RTL838X_TBL_ACCESS_DATA_0(i); +} + +inline int rtl839x_tbl_access_data_0(int i) +{ + return RTL839X_TBL_ACCESS_DATA_0(i); +} + +static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 cmd; + u64 v; + + cmd = 1 << 16 /* Execute cmd */ + | 0 << 15 /* Read */ + | 0 << 12 /* Table type 0b000 */ + | (vlan & 0xfff); + rtl839x_exec_tbl0_cmd(cmd); + + v = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0)); + v <<= 32; + v |= sw_r32(RTL838X_TBL_ACCESS_DATA_0(1)); + info->tagged_ports = v >> 11; + info->vlan_conf = (v & 0x7ff) << 2; + info->vlan_conf |= sw_r32(RTL838X_TBL_ACCESS_DATA_0(1)) >> 30; + + cmd = 1 << 16 /* Execute cmd */ + | 0 << 15 /* Read */ + | 0 << 12 /* Table type 0b000 */ + | (vlan & 0xfff); + rtl839x_exec_tbl1_cmd(cmd); + v = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0)); + v <<= 32; + v |= sw_r32(RTL838X_TBL_ACCESS_DATA_1(1)); + info->untagged_ports = v >> 11; +} + +static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 cmd; + + cmd = 1 << 15 /* Execute cmd */ + | 1 << 14 /* Read */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + rtl838x_exec_tbl0_cmd(cmd); + info->tagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0)); + info->vlan_conf = sw_r32(RTL838X_TBL_ACCESS_DATA_0(1)); + + cmd = 1 << 15 /* Execute cmd */ + | 1 << 14 /* Read */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + rtl838x_exec_tbl1_cmd(cmd); + info->untagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0)); +} + +static void rtl839x_vlan_set_tagged(u32 vlan, u64 portmask, u32 conf) +{ + u32 cmd = 1 << 16 /* Execute cmd */ + | 1 << 15 /* Write */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + u64 v = portmask << 11; + + v |= (conf >> 2) & 0x7ff; + sw_w64(v, RTL838X_TBL_ACCESS_DATA_0(0)); + sw_w32(conf << 30, RTL838X_TBL_ACCESS_DATA_0(2)); + rtl839x_exec_tbl0_cmd(cmd); +} + +static void rtl838x_vlan_set_tagged(u32 vlan, u64 portmask, u32 conf) +{ + u32 cmd = 1 << 15 /* Execute cmd */ + | 0 << 14 /* Write */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + + sw_w32(portmask, RTL838X_TBL_ACCESS_DATA_0(0)); + sw_w32(conf, RTL838X_TBL_ACCESS_DATA_0(1)); + rtl838x_exec_tbl0_cmd(cmd); +} + +static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask) +{ + u32 cmd = 1 << 16 /* Execute cmd */ + | 1 << 15 /* Write */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + sw_w64(portmask << 11, RTL838X_TBL_ACCESS_DATA_1(0)); + rtl839x_exec_tbl1_cmd(cmd); +} + +static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask) +{ + u32 cmd = 1 << 15 /* Execute cmd */ + | 0 << 14 /* Write */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + sw_w32(portmask & 0x1fffffff, RTL838X_TBL_ACCESS_DATA_1(0)); + rtl838x_exec_tbl1_cmd(cmd); +} + +static inline int rtl838x_mac_force_mode_ctrl(int p) +{ + return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static inline int rtl839x_mac_force_mode_ctrl(int p) +{ + return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static const struct rtl838x_reg rtl838x_reg = { + .mask_port_reg = rtl838x_mask_port_reg, + .set_port_reg = rtl838x_set_port_reg, + .get_port_reg = rtl838x_get_port_reg, + .stat_port_rst = RTL838X_STAT_PORT_RST, + .stat_rst = RTL838X_STAT_RST, + .stat_port_std_mib = rtl838x_stat_port_std_mib, + .mask_port_iso_ctrl = rtl838x_mask_port_iso_ctrl, + .set_port_iso_ctrl = rtl838x_set_port_iso_ctrl, + .l2_ctrl_0 = RTL838X_L2_CTRL_0, + .l2_ctrl_1 = RTL838X_L2_CTRL_1, + .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT, + .smi_poll_ctrl = RTL838X_SMI_POLL_CTRL, + .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL, + .exec_tbl0_cmd = rtl838x_exec_tbl0_cmd, + .exec_tbl1_cmd = rtl838x_exec_tbl1_cmd, + .tbl_access_data_0 = rtl838x_tbl_access_data_0, + .isr_glb_src = RTL838X_ISR_GLB_SRC, + .isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG, + .imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG, + .imr_glb = RTL838X_IMR_GLB, + .vlan_tables_read = rtl838x_vlan_tables_read, + .vlan_set_tagged = rtl838x_vlan_set_tagged, + .vlan_set_untagged = rtl838x_vlan_set_untagged, + .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl, + .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0, +}; + +static const struct rtl838x_reg rtl839x_reg = { + .mask_port_reg = rtl839x_mask_port_reg, + .set_port_reg = rtl839x_set_port_reg, + .get_port_reg = rtl839x_get_port_reg, + .stat_port_rst = RTL839X_STAT_PORT_RST, + .stat_rst = RTL839X_STAT_RST, + .stat_port_std_mib = rtl839x_stat_port_std_mib, + .mask_port_iso_ctrl = rtl839x_mask_port_iso_ctrl, + .set_port_iso_ctrl = rtl839x_set_port_iso_ctrl, + .l2_ctrl_0 = RTL839X_L2_CTRL_0, + .l2_ctrl_1 = RTL839X_L2_CTRL_1, + .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT, + .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL, + .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL, + .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd, + .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd, + .tbl_access_data_0 = rtl839x_tbl_access_data_0, + .isr_glb_src = RTL839X_ISR_GLB_SRC, + .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG, + .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG, + .imr_glb = RTL839X_IMR_GLB, + .vlan_tables_read = rtl839x_vlan_tables_read, + .vlan_set_tagged = rtl839x_vlan_set_tagged, + .vlan_set_untagged = rtl839x_vlan_set_untagged, + .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl, + .rst_glb_ctrl = RTL839X_RST_GLB_CTRL, +}; + +static const struct rtl838x_mib_desc rtl838x_mib[] = { + MIB_DESC(2, 0xf8, "ifInOctets"), + MIB_DESC(2, 0xf0, "ifOutOctets"), + MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"), + MIB_DESC(1, 0xe8, "ifInUcastPkts"), + MIB_DESC(1, 0xe4, "ifInMulticastPkts"), + MIB_DESC(1, 0xe0, "ifInBroadcastPkts"), + MIB_DESC(1, 0xdc, "ifOutUcastPkts"), + MIB_DESC(1, 0xd8, "ifOutMulticastPkts"), + MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"), + MIB_DESC(1, 0xd0, "ifOutDiscards"), + MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"), + MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"), + MIB_DESC(1, 0xc4, ".3DeferredTransmissions"), + MIB_DESC(1, 0xc0, ".3LateCollisions"), + MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"), + MIB_DESC(1, 0xb8, ".3SymbolErrors"), + MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"), + MIB_DESC(1, 0xb0, ".3InPauseFrames"), + MIB_DESC(1, 0xac, ".3OutPauseFrames"), + MIB_DESC(1, 0xa8, "DropEvents"), + MIB_DESC(1, 0xa4, "tx_BroadcastPkts"), + MIB_DESC(1, 0xa0, "tx_MulticastPkts"), + MIB_DESC(1, 0x9c, "CRCAlignErrors"), + MIB_DESC(1, 0x98, "tx_UndersizePkts"), + MIB_DESC(1, 0x94, "rx_UndersizePkts"), + MIB_DESC(1, 0x90, "rx_UndersizedropPkts"), + MIB_DESC(1, 0x8c, "tx_OversizePkts"), + MIB_DESC(1, 0x88, "rx_OversizePkts"), + MIB_DESC(1, 0x84, "Fragments"), + MIB_DESC(1, 0x80, "Jabbers"), + MIB_DESC(1, 0x7c, "Collisions"), + MIB_DESC(1, 0x78, "tx_Pkts64Octets"), + MIB_DESC(1, 0x74, "rx_Pkts64Octets"), + MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"), + MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"), + MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"), + MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"), + MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"), + MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"), + MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"), + MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"), + MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"), + MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"), + MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"), + MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"), + MIB_DESC(1, 0x40, "rxMacDiscards") +}; + +static irqreturn_t rtl838x_switch_irq(int irq, void *dev_id) +{ + struct dsa_switch *ds = dev_id; + u32 status = sw_r32(RTL838X_ISR_GLB_SRC); + u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG); + u32 link; + int i; + + /* Clear status */ + sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG); + pr_info("Link change: status: %x, ports %x\n", status, ports); + + for (i = 0; i < 28; i++) { + if (ports & (1 << i)) { + link = sw_r32(RTL838X_MAC_LINK_STS); + if (link & (1 << i)) + dsa_port_phylink_mac_change(ds, i, true); + else + dsa_port_phylink_mac_change(ds, i, false); + } + } + return IRQ_HANDLED; +} + +static irqreturn_t rtl839x_switch_irq(int irq, void *dev_id) +{ + struct dsa_switch *ds = dev_id; + u32 status = sw_r32(RTL839X_ISR_GLB_SRC); + u64 ports = sw_r64(RTL839X_ISR_PORT_LINK_STS_CHG); + u64 link; + int i; + + /* Clear status */ + sw_w64(ports, RTL839X_ISR_PORT_LINK_STS_CHG); + pr_info("Link change: status: %x, ports %llx\n", status, ports); + + for (i = 0; i < 52; i++) { + if (ports & (1 << i)) { + link = sw_r64(RTL839X_MAC_LINK_STS); + if (link & (1 << i)) + dsa_port_phylink_mac_change(ds, i, true); + else + dsa_port_phylink_mac_change(ds, i, false); + } + } + return IRQ_HANDLED; +} + +int rtl8380_sds_power(int mac, int val) +{ + u32 mode = (val == 1) ? 0x4 : 0x9; + u32 offset = (mac == 24) ? 5 : 0; + + if ((mac != 24) && (mac != 26)) { + pr_err("%s: not a fibre port: %d\n", __func__, mac); + return -1; + } + + sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL); + + rtl8380_sds_rst(mac); + + return 0; +} + +static int rtl838x_smi_wait_op(int timeout) +{ + do { + timeout--; + udelay(10); + } while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & 0x1) && (timeout >= 0)); + if (timeout <= 0) + return -1; + return 0; +} + +/* + * Write to a register in a page of the PHY + */ +int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val) +{ + u32 v; + u32 park_page; + + val &= 0xffff; + if (port > 31 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0); + mdelay(10); + + sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); + + park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2); + v = reg << 20 | page << 3 | 0x4; + sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1); + sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + mutex_unlock(&smi_lock); + return 0; + +timeout: + mutex_unlock(&smi_lock); + return -ETIMEDOUT; +} + +int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val) +{ + u32 v; + int err = 0; + + val &= 0xffff; + if (port > 63 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + /* Clear both port registers */ + sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0)); + sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0) + 4); + sw_w32_mask(0, 1 << port, RTL839X_PHYREG_PORT_CTRL(port)); + + sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL); + + v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23; + sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); + + sw_w32(0x1ff, RTL839X_PHYREG_CTRL); + + v |= 1 << 3 | 1; /* Write operation and execute */ + sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); + + do { + } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1); + + if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2) + err = -EIO; + + mutex_unlock(&smi_lock); + return err; +} + +/* + * Reads a register in a page from the PHY + */ +int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val) +{ + u32 v; + u32 park_page; + + if (port > 31 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); + + park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2); + v = reg << 20 | page << 3; + sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1); + sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff; + + mutex_unlock(&smi_lock); + return 0; + +timeout: + mutex_unlock(&smi_lock); + return -ETIMEDOUT; +} + +int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val) +{ + u32 v; + + if (port > 63 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + + sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL); + v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23; + sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); + + sw_w32(0x1ff, RTL839X_PHYREG_CTRL); + + v |= 1; + sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); + + do { + } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1); + + *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff; + + mutex_unlock(&smi_lock); + return 0; +} + +static int read_phy(u32 port, u32 page, u32 reg, u32 *val) +{ + if (soc_info.family == RTL8390_FAMILY_ID) + return rtl839x_read_phy(port, page, reg, val); + else + return rtl838x_read_phy(port, page, reg, val); +} + +static int write_phy(u32 port, u32 page, u32 reg, u32 val) +{ + if (soc_info.family == RTL8390_FAMILY_ID) + return rtl839x_write_phy(port, page, reg, val); + else + return rtl838x_write_phy(port, page, reg, val); +} + +/* + * Write to an mmd register of the PHY + */ +int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val) +{ + u32 v; + + pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val); + val &= 0xffff; + mutex_lock(&smi_lock); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0); + mdelay(10); + + sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); + + sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3); + sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3); + /* mmd-access | write | cmd-start */ + v = 1 << 1 | 1 << 2 | 1; + sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + mutex_unlock(&smi_lock); + return 0; + +timeout: + mutex_unlock(&smi_lock); + return -ETIMEDOUT; +} + +/* + * Read to an mmd register of the PHY + */ +int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val) +{ + u32 v; + + mutex_lock(&smi_lock); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0); + mdelay(10); + + sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); + + v = addr << 16 | reg; + sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3); + + /* mmd-access | read | cmd-start */ + v = 1 << 1 | 0 << 2 | 1; + sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff; + + mutex_unlock(&smi_lock); + return 0; + +timeout: + mutex_unlock(&smi_lock); + return -ETIMEDOUT; +} + +static void rtl8380_get_version(struct rtl838x_switch_priv *priv) +{ + u32 rw_save, info_save; + u32 info; + + if (priv->id) + pr_debug("SoC ID: %4x: %s\n", priv->id, soc_info.name); + else + pr_err("Unknown chip id (%04x)\n", priv->id); + + rw_save = sw_r32(RTL838X_INT_RW_CTRL); + sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL); + + info_save = sw_r32(RTL838X_CHIP_INFO); + sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO); + + info = sw_r32(RTL838X_CHIP_INFO); + sw_w32(info_save, RTL838X_CHIP_INFO); + sw_w32(rw_save, RTL838X_INT_RW_CTRL); + + if ((info & 0xFFFF) == 0x6275) { + if (((info >> 16) & 0x1F) == 0x1) + priv->version = RTL8380_VERSION_A; + else if (((info >> 16) & 0x1F) == 0x2) + priv->version = RTL8380_VERSION_B; + else + priv->version = RTL8380_VERSION_B; + } else { + priv->version = '-'; + } +} + +static void rtl8390_get_version(struct rtl838x_switch_priv *priv) +{ + u32 info; + + sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO); + info = sw_r32(RTL839X_CHIP_INFO); + pr_info("Chip-Info: %x\n", info); + priv->version = RTL8390_VERSION_A; +} + +int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg) +{ + u32 val; + u32 offset = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + if (phy_addr >= 24 && phy_addr <= 27 + && priv->ports[24].phy == PHY_RTL838X_SDS) { + if (phy_addr == 26) + offset = 0x100; + val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff; + return val; + } + + read_phy(phy_addr, 0, phy_reg, &val); + return val; +} + +int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val) +{ + u32 offset = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + if (phy_addr >= 24 && phy_addr <= 27 + && priv->ports[24].phy == PHY_RTL838X_SDS) { + if (phy_addr == 26) + offset = 0x100; + sw_w32(val, MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)); + return 0; + } + return write_phy(phy_addr, 0, phy_reg, val); +} + +static int rtl838x_mdio_read(struct mii_bus *bus, int addr, int regnum) +{ + int ret; + struct rtl838x_switch_priv *priv = bus->priv; + + ret = dsa_phy_read(priv->ds, addr, regnum); + return ret; +} + +static int rtl838x_mdio_write(struct mii_bus *bus, int addr, int regnum, + u16 val) +{ + struct rtl838x_switch_priv *priv = bus->priv; + + return dsa_phy_write(priv->ds, addr, regnum, val); +} + +static void rtl838x_enable_phy_polling(struct rtl838x_switch_priv *priv) +{ + int i; + u64 v = 0; + + msleep(1000); + /* Enable all ports with a PHY, including the SFP-ports */ + for (i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) + v |= 1 << i; + } + + pr_info("%s: %16llx\n", __func__, v); + priv->r->set_port_reg(v, priv->r->smi_poll_ctrl); + + /* PHY update complete */ + if (priv->family_id == RTL8390_FAMILY_ID) + sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL); + else + sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL); +} + +void rtl839x_print_matrix(void) +{ + volatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0); + int i; + + for (i = 0; i < 52; i += 4) + pr_info("> %16llx %16llx %16llx %16llx\n", + ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]); + pr_info("CPU_PORT> %16llx\n", ptr[52]); +} + +void rtl838x_print_matrix(void) +{ + unsigned volatile int *ptr = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0); + int i; + + if (soc_info.family == RTL8390_FAMILY_ID) + return rtl839x_print_matrix(); + + for (i = 0; i < 28; i += 8) + pr_info("> %8x %8x %8x %8x %8x %8x %8x %8x\n", + ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3], ptr[i + 4], ptr[i + 5], + ptr[i + 6], ptr[i + 7]); + pr_info("CPU_PORT> %8x\n", ptr[28]); +} + +static void rtl838x_init_stats(struct rtl838x_switch_priv *priv) +{ + mutex_lock(&priv->reg_mutex); + + /* Enable statistics module: all counters plus debug. + * On RTL839x all counters are enabled by default + */ + if (priv->family_id == RTL8380_FAMILY_ID) + sw_w32_mask(0, 3, RTL838X_STAT_CTRL); + + /* Reset statistics counters */ + sw_w32_mask(0, 1, priv->r->stat_rst); + + mutex_unlock(&priv->reg_mutex); +} + +static int rtl838x_setup(struct dsa_switch *ds) +{ + int i; + u64 port_bitmap = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s called\n", __func__); + + /* Disable MAC polling the PHY so that we can start configuration */ + priv->r->set_port_reg(0, priv->r->smi_poll_ctrl); + + for (i = 0; i < ds->num_ports; i++) + priv->ports[i].enable = false; + priv->ports[priv->cpu_port].enable = true; + + /* Isolate ports from each other: traffic only CPU <-> port */ + for (i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) { + priv->r->set_port_iso_ctrl(1 << priv->cpu_port, i); + priv->r->mask_port_iso_ctrl(0, 1 << i, i); + port_bitmap |= 1 << i; + } + } + priv->r->set_port_iso_ctrl(port_bitmap, priv->cpu_port); + + rtl838x_print_matrix(); + + rtl838x_init_stats(priv); + + /* Enable MAC Polling PHY again */ + rtl838x_enable_phy_polling(priv); + pr_info("Please wait until PHY is settled\n"); + msleep(1000); + return 0; +} + +static void rtl838x_get_strings(struct dsa_switch *ds, + int port, u32 stringset, u8 *data) +{ + int i; + + if (stringset != ETH_SS_STATS) + return; + + for (i = 0; i < ARRAY_SIZE(rtl838x_mib); i++) + strncpy(data + i * ETH_GSTRING_LEN, rtl838x_mib[i].name, + ETH_GSTRING_LEN); +} + +static void rtl838x_get_ethtool_stats(struct dsa_switch *ds, int port, + uint64_t *data) +{ + struct rtl838x_switch_priv *priv = ds->priv; + const struct rtl838x_mib_desc *mib; + int i; + u64 high; + + for (i = 0; i < ARRAY_SIZE(rtl838x_mib); i++) { + mib = &rtl838x_mib[i]; + + data[i] = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset); + if (mib->size == 2) { + high = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset - 4); + data[i] |= high << 32; + } + } +} + +static int rtl838x_get_sset_count(struct dsa_switch *ds, int port, int sset) +{ + if (sset != ETH_SS_STATS) + return 0; + + return ARRAY_SIZE(rtl838x_mib); +} + +static enum dsa_tag_protocol +rtl838x_get_tag_protocol(struct dsa_switch *ds, int port) +{ + /* The switch does not tag the frames, instead internally the header + * structure for each packet is tagged accordingly. + */ + return DSA_TAG_PROTO_TRAILER; +} + +static int rtl838x_get_l2aging(struct rtl838x_switch_priv *priv) +{ + int t = sw_r32(priv->r->l2_ctrl_1) & 0x7fffff; + + pr_debug("RTL838X_L2_CTRL_1 %x\n", sw_r32(priv->r->l2_ctrl_1)); + + t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */ + pr_info("L2 AGING time: %d sec\n", t); + pr_info("Dynamic aging for ports: %x\n", + sw_r32(priv->r->l2_port_aging_out)); + return t; +} + +/* + * Set Switch L2 Aging time, t is time in milliseconds + * t = 0: aging is disabled + */ +static int rtl838x_set_l2aging(struct dsa_switch *ds, u32 t) +{ + struct rtl838x_switch_priv *priv = ds->priv; + /* Convert time in mseconds to internal value */ + if (t > 0x10000000) /* Set to maximum */ + t = 0x7fffff; + else + t = ((t * 625) / 1000 + 127) / 128; + + sw_w32(t, priv->r->l2_ctrl_1); + + return 0; +} + +static void rtl838x_fast_age(struct dsa_switch *ds, int port) +{ + struct rtl838x_switch_priv *priv = ds->priv; + int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0; + + pr_info("FAST AGE port %d\n", port); + mutex_lock(&priv->reg_mutex); + /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger + * port fields: + * 0-4: Replacing port + * 5-9: Flushed/replaced port + * 10-21: FVID + * 22: Entry types: 1: dynamic, 0: also static + * 23: Match flush port + * 24: Match FVID + * 25: Flush (0) or replace (1) L2 entries + * 26: Status of action (1: Start, 0: Done) + */ + sw_w32(1 << (26 + s) | 1 << (23 + s) | port << 5, priv->r->l2_tbl_flush_ctrl); + + do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << (26 + s))); + + mutex_unlock(&priv->reg_mutex); +} + +/* + * Applies the same hash algorithm as the one used currently by the ASIC + */ +static u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed) +{ + u32 h1, h2, h3, h; + + if (sw_r32(priv->r->l2_ctrl_0) & 1) { + h1 = (seed >> 11) & 0x7ff; + h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f); + + h2 = (seed >> 33) & 0x7ff; + h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f); + + h3 = (seed >> 44) & 0x7ff; + h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf); + + h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff); + h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff); + } else { + h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff) + ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) + ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff); + } + + return h; +} + +static u64 rtl838x_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid) +{ + return rtl838x_hash(priv, mac << 12 | vid); +} + +static u64 read_l2_entry_using_hash(u32 hash, u32 position, u32 *r) +{ + u64 entry; + /* Search in SRAM, with hash and at position in hash bucket (0-3) */ + u32 idx = (0 << 14) | (hash << 2) | position; + + u32 cmd = 1 << 16 /* Execute cmd */ + | 1 << 15 /* Read */ + | 0 << 13 /* Table type 0b00 */ + | (idx & 0x1fff); + + sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16)); + r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0)); + r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1)); + r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2)); + + entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff); + return entry; +} + +static u64 rtl838x_read_cam(int idx, u32 *r) +{ + u64 entry; + u32 cmd = 1 << 16 /* Execute cmd */ + | 1 << 15 /* Read */ + | 1 << 13 /* Table type 0b01 */ + | (idx & 0x3f); + sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16)); + r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0)); + r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1)); + r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2)); + + entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff); + return entry; +} + +static void rtl838x_write_cam(int idx, u32 *r) +{ + u32 cmd = 1 << 16 /* Execute cmd */ + | 1 << 15 /* Read */ + | 1 << 13 /* Table type 0b01 */ + | (idx & 0x3f); + + sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0)); + sw_w32(r[1], RTL838X_TBL_ACCESS_L2_DATA(1)); + sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2)); + + sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16)); +} + +static void rtl838x_write_hash(int idx, u32 *r) +{ + u32 cmd = 1 << 16 /* Execute cmd */ + | 0 << 15 /* Write */ + | 0 << 13 /* Table type 0b00 */ + | (idx & 0x1fff); + + sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0)); + sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1)); + sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2)); + sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16)); +} + +static void dump_fdb(struct rtl838x_switch_priv *priv) +{ + u32 r[3]; + int i; + u8 mac[6]; + u16 vid, rvid; + + mutex_lock(&priv->reg_mutex); + + for (i = 0; i < 8192; i++) { + read_l2_entry_using_hash(i >> 2, i & 0x3, r); + mac[0] = (r[1] >> 20); + mac[1] = (r[1] >> 12); + mac[2] = (r[1] >> 4); + mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28); + mac[4] = (r[2] >> 20); + mac[5] = (r[2] >> 12); + vid = r[0] & 0xfff; + rvid = r[2] & 0xfff; + + if (!(r[0] >> 17)) /* Check for invalid entry */ + continue; + + pr_info("-> port %02d: %pM, vid: %d, rvid: %d\n", + (r[0] >> 12) & priv->port_mask, &mac[0], vid, rvid); + } + + mutex_unlock(&priv->reg_mutex); +} + +static int rtl838x_port_fdb_dump(struct dsa_switch *ds, int port, + dsa_fdb_dump_cb_t *cb, void *data) +{ + u32 r[3]; + u8 mac[6]; + u16 vid, rvid; + struct rtl838x_switch_priv *priv = ds->priv; + int i; + + mutex_lock(&priv->reg_mutex); + + for (i = 0; i < 8192; i++) { + read_l2_entry_using_hash(i >> 2, i & 0x3, r); + mac[0] = (r[1] >> 20); + mac[1] = (r[1] >> 12); + mac[2] = (r[1] >> 4); + mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28); + mac[4] = (r[2] >> 20); + mac[5] = (r[2] >> 12); + vid = r[0] & 0xfff; + rvid = r[2] & 0xfff; + + if (!(r[0] >> 17)) /* Check for invalid entry */ + continue; + + if (port == ((r[0] >> 12) & 0x1f)) { + pr_info("-> mac %pM, vid: %d, rvid: %d\n", &mac[0], vid, rvid); + cb(mac, vid, (r[0] >> 19) & 1, data); + } + } + + for (i = 0; i < 64; i++) { + rtl838x_read_cam(i, r); + mac[0] = (r[1] >> 20); + mac[1] = (r[1] >> 12); + mac[2] = (r[1] >> 4); + mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28); + mac[4] = (r[2] >> 20); + mac[5] = (r[2] >> 12); + vid = r[0] & 0xfff; + + if (!(r[0] >> 17)) + continue; + + pr_info("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]); + if (port == ((r[0] >> 12) & priv->port_mask)) + cb(mac, vid, (r[0] >> 19) & 1, data); + } + + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static int rtl838x_port_fdb_del(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 mac = ether_addr_to_u64(addr); + u32 key = rtl838x_hash_key(priv, mac, vid); + int i; + u32 r[3]; + u64 entry; + int idx = -1; + int err = 0; + + pr_info("In %s, mac %llx, vid: %d, key: %x\n", __func__, mac, vid, key); + mutex_lock(&priv->reg_mutex); + for (i = 0; i < 4; i++) { + entry = read_l2_entry_using_hash(key, i, r); + if (!(r[0] >> 17)) /* Check for invalid entry */ + continue; + if ((entry & 0x0fffffffffffffff) == ((mac << 12) | vid)) { + idx = (key << 2) | i; + break; + } + } + + if (idx >= 0) { + r[0] = r[1] = r[2] = 0; + rtl838x_write_hash(idx, r); + goto out; + } + + /* Check CAM for spillover from hash buckets */ + for (i = 0; i < 64; i++) { + entry = rtl838x_read_cam(i, r); + if ((entry & 0x0fffffffffffffff) == ((mac << 12) | vid)) { + idx = i; + break; + } + } + if (idx >= 0) { + r[0] = r[1] = r[2] = 0; + rtl838x_write_cam(idx, r); + goto out; + } + err = -ENOENT; +out: + mutex_unlock(&priv->reg_mutex); + return err; +} + +static int rtl838x_port_fdb_add(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 mac = ether_addr_to_u64(addr); + u32 key = rtl838x_hash_key(priv, mac, vid); + int i; + u32 r[3]; + int idx = -1; + u64 entry; + int err = 0; + + mutex_lock(&priv->reg_mutex); + for (i = 0; i < 4; i++) { + entry = read_l2_entry_using_hash(key, i, r); + if (!(r[0] >> 17)) { /* Check for invalid entry */ + idx = (key << 2) | i; + break; + } + if ((entry & 0x0fffffffffffffff) == ((mac << 12) | vid)) { + idx = (key << 2) | i; + break; + } + } + if (idx >= 0) { + // Found for del: R1 60000 R2 901b0e9 R3 12b0e000, 901b0e912b0e000 + r[0] = 3 << 17 | port << 12; // Aging and port + r[0] |= vid; + r[1] = mac >> 16; + r[2] = (mac & 0xffff) << 12; /* rvid = 0 */ + rtl838x_write_hash(idx, r); + goto out; + } + + /* Hash bucket full, try CAM */ + for (i = 0; i < 64; i++) { + entry = rtl838x_read_cam(i, r); + if (!(r[0] >> 17)) { /* Check for invalid entry */ + if (idx < 0) /* First empty entry? */ + idx = i; + break; + } else if ((entry & 0x0fffffffffffffff) == ((mac << 12) | vid)) { + pr_debug("Found entry in CAM\n"); + idx = i; + break; + } + } + if (idx >= 0) { + r[0] = 3 << 17 | port << 12; // Aging + r[0] |= vid; + r[1] = mac >> 16; + r[2] = (mac & 0xffff) << 12; /* rvid = 0 */ + rtl838x_write_cam(idx, r); + goto out; + } + err = -ENOTSUPP; +out: + mutex_unlock(&priv->reg_mutex); + return err; +} + +static void rtl838x_port_stp_state_set(struct dsa_switch *ds, int port, + u8 state) +{ + u32 cmd, msti = 0; + u32 port_state[4]; + int index, bit, i; + + struct rtl838x_switch_priv *priv = ds->priv; + int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4; + + pr_info("%s: port %d state %2x\n", __func__, port, state); + if (port >= priv->cpu_port) + return; + + mutex_lock(&priv->reg_mutex); + + index = n - (port >> 4) - 1; + bit = (port << 1) % 32; + + if (priv->family_id == RTL8380_FAMILY_ID) { + cmd = 1 << 15 /* Execute cmd */ + | 1 << 14 /* Read */ + | 2 << 12 /* Table type 0b10 */ + | (msti & 0xfff); + } else { + cmd = 1 << 16 /* Execute cmd */ + | 0 << 15 /* Read */ + | 5 << 12 /* Table type 0b101 */ + | (msti & 0xfff); + } + priv->r->exec_tbl0_cmd(cmd); + + for (i = 0; i < n; i++) + port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); + + pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3); + port_state[index] &= ~(3 << bit); + + switch (state) { + case BR_STATE_DISABLED: /* 0 */ + port_state[index] |= (0 << bit); + break; + case BR_STATE_BLOCKING: /* 4 */ + case BR_STATE_LISTENING: /* 1 */ + port_state[index] |= (1 << bit); + break; + case BR_STATE_LEARNING: /* 2 */ + port_state[index] |= (2 << bit); + break; + case BR_STATE_FORWARDING: /* 3*/ + port_state[index] |= (3 << bit); + default: + break; + } + + if (priv->family_id == RTL8380_FAMILY_ID) { + cmd = 1 << 15 /* Execute cmd */ + | 0 << 14 /* Write */ + | 2 << 12 /* Table type 0b10 */ + | (msti & 0xfff); + } else { + cmd = 1 << 16 /* Execute cmd */ + | 1 << 15 /* Write */ + | 5 << 12 /* Table type 0b101 */ + | (msti & 0xfff); + } + for (i = 0; i < n; i++) + sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); + priv->r->exec_tbl0_cmd(cmd); + + mutex_unlock(&priv->reg_mutex); +} + +static int rtl838x_port_mirror_add(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress) +{ + /* We support 4 mirror groups, one destination port per group */ + int group; + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("In %s\n", __func__); + + for (group = 0; group < 4; group++) { + if (priv->mirror_group_ports[group] == mirror->to_local_port) + break; + } + if (group >= 4) { + for (group = 0; group < 4; group++) { + if (priv->mirror_group_ports[group] < 0) + break; + } + } + + if (group >= 4) + return -ENOSPC; + + pr_debug("Using group %d\n", group); + mutex_lock(&priv->reg_mutex); + /* Enable mirroring to port across VLANs (bit 11) */ + sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, RTL838X_MIR_CTRL(group)); + + if (ingress && (sw_r32(RTL838X_MIR_SPM_CTRL(group)) & (1 << port))) { + mutex_unlock(&priv->reg_mutex); + return -EEXIST; + } + if ((!ingress) && (sw_r32(RTL838X_MIR_DPM_CTRL(group)) & (1 << port))) { + mutex_unlock(&priv->reg_mutex); + return -EEXIST; + } + if (ingress) + sw_w32_mask(0, 1 << port, RTL838X_MIR_SPM_CTRL(group)); + else + sw_w32_mask(0, 1 << port, RTL838X_MIR_DPM_CTRL(group)); + + priv->mirror_group_ports[group] = mirror->to_local_port; + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static void rtl838x_port_mirror_del(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror) +{ + int group = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("In %s\n", __func__); + for (group = 0; group < 4; group++) { + if (priv->mirror_group_ports[group] == mirror->to_local_port) + break; + } + if (group >= 4) + return; + + mutex_lock(&priv->reg_mutex); + if (mirror->ingress) { + /* Ingress, clear source port matrix */ + sw_w32_mask(1 << port, 0, RTL838X_MIR_SPM_CTRL(group)); + } else { + /* Egress, clear destination port matrix */ + sw_w32_mask(1 << port, 0, RTL838X_MIR_DPM_CTRL(group)); + } + + if (!(sw_r32(RTL838X_MIR_DPM_CTRL(group)) || sw_r32(RTL838X_MIR_DPM_CTRL(group)))) { + priv->mirror_group_ports[group] = -1; + sw_w32(0, RTL838X_MIR_CTRL(group)); + } + + mutex_unlock(&priv->reg_mutex); +} + + +void rtl838x_vlan_profile_dump(int index) +{ + u32 profile; + + if (index < 0 || index > 7) + return; + + profile = sw_r32(RTL838X_VLAN_PROFILE(index)); + + pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x", + index, profile & 1, (profile >> 1) & 0x1ff); + pr_info(" IPv4 Unkn MultiCast Field %x, IPv6 Unkn MultiCast Field: %x", + (profile >> 10) & 0x1ff, (profile >> 19) & 0x1ff); +} + +static int rtl838x_vlan_filtering(struct dsa_switch *ds, int port, + bool vlan_filtering) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s: port %d\n", __func__, port); + mutex_lock(&priv->reg_mutex); + + if (vlan_filtering) { + /* Enable ingress and egress filtering */ + if (port != priv->cpu_port) { + if (port < 16) { + sw_w32_mask(0b10 << (port << 1), + 0b01 << (port << 1), + RTL838X_VLAN_PORT_IGR_FLTR_0); + } else { + sw_w32_mask(0b10 << ((port - 16) << 1), + 0b01 << ((port - 16) << 1), + RTL838X_VLAN_PORT_IGR_FLTR_1); + } + } + sw_w32_mask(0, 1 << port, RTL838X_VLAN_PORT_EGR_FLTR); + } else { + /* Disable ingress and egress filtering */ + if (port != priv->cpu_port) { + if (port < 16) { + sw_w32_mask(0b11 << (port << 1), + 0, + RTL838X_VLAN_PORT_IGR_FLTR_0); + } else { + sw_w32_mask(0b11 << ((port - 16) << 1), + 0, + RTL838X_VLAN_PORT_IGR_FLTR_1); + } + } + sw_w32_mask(1 << port, 0, RTL838X_VLAN_PORT_EGR_FLTR); + } + + /* We need to do something to the CPU-Port, too */ + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtl838x_vlan_prepare(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct rtl838x_vlan_info info; + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s: port %d\n", __func__, port); + + mutex_lock(&priv->reg_mutex); + + priv->r->vlan_tables_read(1, &info); + + pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, MSTI %x\n", + info.tagged_ports, info.untagged_ports, info.vlan_conf & 7, + (info.vlan_conf & 8) >> 3, (info.vlan_conf & 16) >> 4, + (info.vlan_conf & 0x3e0) >> 5); + + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static void rtl838x_vlan_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct rtl838x_vlan_info info; + struct rtl838x_switch_priv *priv = ds->priv; + int v; + u64 portmask; + + pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__, + port, vlan->vid_begin, vlan->vid_end, vlan->flags); + + if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) { + dev_err(priv->dev, "VLAN out of range: %d - %d", + vlan->vid_begin, vlan->vid_end); + return; + } + + mutex_lock(&priv->reg_mutex); + + if (vlan->flags & BRIDGE_VLAN_INFO_PVID) { + for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { + /* Set both inner and outer PVID of the port */ + sw_w32((v << 16) | v, RTL838X_VLAN_PORT_PB_VLAN(port)); + } + } + + if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) { + for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { + /* Get untagged port memberships of this vlan */ + priv->r->vlan_tables_read(v, &info); + portmask = info.untagged_ports | (1 << port); + pr_debug("Untagged ports, VLAN %d: %llx\n", v, portmask); + priv->r->vlan_set_untagged(v, portmask); + } + } else { + for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { + /* Get tagged port memberships of this vlan */ + priv->r->vlan_tables_read(v, &info); + portmask = info.tagged_ports | (1 << port); + pr_debug("Tagged ports, VLAN %d: %llx\n", v, portmask); + priv->r->vlan_set_tagged(v, portmask, info.vlan_conf); + } + } + mutex_unlock(&priv->reg_mutex); +} + +static int rtl838x_vlan_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct rtl838x_vlan_info info; + struct rtl838x_switch_priv *priv = ds->priv; + int v; + u64 portmask; + + pr_info("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__, + port, vlan->vid_begin, vlan->vid_end, vlan->flags); + + if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) { + dev_err(priv->dev, "VLAN out of range: %d - %d", + vlan->vid_begin, vlan->vid_end); + return -ENOTSUPP; + } + + mutex_lock(&priv->reg_mutex); + + for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { + /* Reset both inner and out PVID of the port */ + sw_w32(0, RTL838X_VLAN_PORT_PB_VLAN(port)); + + if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) { + /* Get untagged port memberships of this vlan */ + priv->r->vlan_tables_read(v, &info); + portmask = info.untagged_ports & (~(1 << port)); + pr_info("Untagged ports, VLAN %d: %llx\n", v, portmask); + priv->r->vlan_set_untagged(v, portmask); + } + + /* Get tagged port memberships of this vlan */ + priv->r->vlan_tables_read(v, &info); + portmask = info.tagged_ports & (~(1 << port)); + pr_info("Tagged ports, VLAN %d: %llx\n", v, portmask); + priv->r->vlan_set_tagged(v, portmask, info.vlan_conf); + } + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static void rtl838x_port_bridge_leave(struct dsa_switch *ds, int port, + struct net_device *bridge) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 port_bitmap = 1 << priv->cpu_port; + int i; + + pr_info("%s %x: %d", __func__, (u32)priv, port); + mutex_lock(&priv->reg_mutex); + for (i = 0; i < ds->num_ports; i++) { + /* Remove this port from the port matrix of the other ports + * in the same bridge. If the port is disabled, port matrix + * is kept and not being setup until the port becomes enabled. + * And the other port's port matrix cannot be broken when the + * other port is still a VLAN-aware port. + */ + if (dsa_is_user_port(ds, i) && i != port) { + if (dsa_to_port(ds, i)->bridge_dev != bridge) + continue; + if (priv->ports[i].enable) + priv->r->mask_port_iso_ctrl(1 << port, 0, i); + priv->ports[i].pm |= 1 << port; + + port_bitmap &= ~(1 << i); + } + } + + /* Add all other ports to this port matrix. */ + if (priv->ports[port].enable) + priv->r->mask_port_iso_ctrl(0, port_bitmap, port); + priv->ports[port].pm &= ~port_bitmap; + mutex_unlock(&priv->reg_mutex); + + rtl838x_print_matrix(); +} + +static int rtl838x_port_bridge_join(struct dsa_switch *ds, int port, + struct net_device *bridge) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 port_bitmap = 1 << priv->cpu_port; + int i; + + pr_info("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap); + mutex_lock(&priv->reg_mutex); + for (i = 0; i < ds->num_ports; i++) { + /* Add this port to the port matrix of the other ports in the + * same bridge. If the port is disabled, port matrix is kept + * and not being setup until the port becomes enabled. + */ + if (dsa_is_user_port(ds, i) && i != port) { + if (dsa_to_port(ds, i)->bridge_dev != bridge) + continue; + if (priv->ports[i].enable) + priv->r->mask_port_iso_ctrl(0, 1 << port, i); + priv->ports[i].pm |= 1 << port; + + port_bitmap |= 1 << i; + } + } + + /* Add all other ports to this port matrix. */ + if (priv->ports[port].enable) { + priv->r->mask_port_iso_ctrl(0, 1 << port, priv->cpu_port); + priv->r->mask_port_iso_ctrl(0, port_bitmap, port); + } + priv->ports[port].pm |= port_bitmap; + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtl838x_port_enable(struct dsa_switch *ds, int port, + struct phy_device *phydev) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s: %x %d", __func__, (u32) priv, port); + priv->ports[port].enable = true; + + if (dsa_is_cpu_port(ds, port)) + return 0; + + /* add port to switch mask of CPU_PORT */ + priv->r->mask_port_iso_ctrl(0, 1 << port, priv->cpu_port); + + /* add all other ports in the same bridge to switch mask of port */ + priv->r->mask_port_iso_ctrl(0, priv->ports[port].pm, port); + + /* enable PHY polling */ + sw_w32_mask(0, 1 << port, RTL838X_SMI_POLL_CTRL); + + return 0; +} + +static void rtl838x_port_disable(struct dsa_switch *ds, int port) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s %x: %d", __func__, (u32)priv, port); + + /* you can only disable user ports */ + if (!dsa_is_user_port(ds, port)) + return; + + /* remove port from switch mask of CPU_PORT */ + priv->r->mask_port_iso_ctrl(1 << port, 0, priv->cpu_port); + + /* remove all other ports in the same bridge from switch mask of port */ + priv->r->mask_port_iso_ctrl(priv->ports[port].pm, 0, port); + + priv->ports[port].enable = false; + + /* disable PHY polling */ + sw_w32_mask(1 << port, 0, RTL838X_SMI_POLL_CTRL); +} + +static int rtl838x_get_mac_eee(struct dsa_switch *ds, int port, + struct ethtool_eee *e) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s: port %d", __func__, port); + e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full; + if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & (1 << 9)) + e->advertised |= ADVERTISED_100baseT_Full; + + if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & (1 << 10)) + e->advertised |= ADVERTISED_1000baseT_Full; + + e->eee_enabled = priv->ports[port].eee_enabled; + pr_info("enabled: %d, active %x\n", e->eee_enabled, e->advertised); + + if (sw_r32(RTL838X_MAC_EEE_ABLTY) & (1 << port)) { + e->lp_advertised = ADVERTISED_100baseT_Full; + e->lp_advertised |= ADVERTISED_1000baseT_Full; + } + + e->eee_active = !!(e->advertised & e->lp_advertised); + pr_info("active: %d, lp %x\n", e->eee_active, e->lp_advertised); + + return 0; +} + +static int rtl838x_set_mac_eee(struct dsa_switch *ds, int port, + struct ethtool_eee *e) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s: port %d", __func__, port); + if (e->eee_enabled) { + pr_info("Globally enabling EEE\n"); + sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL); + } + if (e->eee_enabled) { + pr_info("Enabling EEE for MAC %d\n", port); + sw_w32_mask(0, 3 << 9, priv->r->mac_force_mode_ctrl(port)); + sw_w32_mask(0, 1 << port, RTL838X_EEE_PORT_TX_EN); + sw_w32_mask(0, 1 << port, RTL838X_EEE_PORT_RX_EN); + priv->ports[port].eee_enabled = true; + e->eee_enabled = true; + } else { + pr_info("Disabling EEE for MAC %d\n", port); + sw_w32_mask(3 << 9, 0, priv->r->mac_force_mode_ctrl(port)); + sw_w32_mask(1 << port, 0, RTL838X_EEE_PORT_TX_EN); + sw_w32_mask(1 << port, 0, RTL838X_EEE_PORT_RX_EN); + priv->ports[port].eee_enabled = false; + e->eee_enabled = false; + } + return 0; +} + +static void rtl838x_phylink_mac_config(struct dsa_switch *ds, int port, + unsigned int mode, + const struct phylink_link_state *state) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u32 reg; + + pr_info("%s port %d, mode %x\n", __func__, port, mode); + + if (port == priv->cpu_port) { + /* Set Speed, duplex, flow control + * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL + * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN + * | MEDIA_SEL + */ + if (priv->family_id == RTL8380_FAMILY_ID) { + sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + /* allow CRC errors on CPU-port */ + sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port)); + } else { + sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + } + return; + } + + reg = sw_r32(priv->r->mac_force_mode_ctrl(port)); + if (mode == MLO_AN_PHY) { + pr_info("PHY autonegotiates\n"); + reg |= 1 << 2; + sw_w32(reg, priv->r->mac_force_mode_ctrl(port)); + return; + } + + if (mode != MLO_AN_FIXED) + pr_info("Not fixed\n"); + + /* Clear id_mode_dis bit, and the existing port mode, let + * RGMII_MODE_EN bet set by mac_link_{up,down} + */ + reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); + + if (state->pause & MLO_PAUSE_TXRX_MASK) { + if (state->pause & MLO_PAUSE_TX) + reg |= TX_PAUSE_EN; + reg |= RX_PAUSE_EN; + } + + reg &= ~(3 << 4); + switch (state->speed) { + case SPEED_1000: + reg |= 2 << 4; + break; + case SPEED_100: + reg |= 1 << 4; + break; + } + + reg &= ~(DUPLEX_FULL | FORCE_LINK_EN); + if (state->link) + reg |= FORCE_LINK_EN; + if (state->duplex == DUPLEX_FULL) + reg |= DUPLX_MODE; + + // Disable AN + reg &= ~(1 << 2); + sw_w32(reg, priv->r->mac_force_mode_ctrl(port)); +} + +static void rtl838x_phylink_mac_link_down(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface) +{ + /* Stop TX/RX to port */ + sw_w32_mask(0x03, 0, RTL838X_MAC_PORT_CTRL(port)); +} + +static void rtl838x_phylink_mac_link_up(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface, + struct phy_device *phydev) +{ + /* Restart TX/RX to port */ + sw_w32_mask(0, 0x03, RTL838X_MAC_PORT_CTRL(port)); +} + +static void rtl838x_phylink_validate(struct dsa_switch *ds, int port, + unsigned long *supported, + struct phylink_link_state *state) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + pr_info("In %s port %d", __func__, port); + + if (!phy_interface_mode_is_rgmii(state->interface) && + state->interface != PHY_INTERFACE_MODE_1000BASEX && + state->interface != PHY_INTERFACE_MODE_MII && + state->interface != PHY_INTERFACE_MODE_REVMII && + state->interface != PHY_INTERFACE_MODE_GMII && + state->interface != PHY_INTERFACE_MODE_QSGMII && + state->interface != PHY_INTERFACE_MODE_INTERNAL && + state->interface != PHY_INTERFACE_MODE_SGMII) { + bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); + dev_err(ds->dev, + "Unsupported interface: %d for port %d\n", + state->interface, port); + return; + } + + /* switch chip-id? if (priv->id == 0x8382) */ + + /* Allow all the expected bits */ + phylink_set(mask, Autoneg); + phylink_set_port_modes(mask); + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + + /* With the exclusion of MII and Reverse MII, we support Gigabit, + * including Half duplex + */ + if (state->interface != PHY_INTERFACE_MODE_MII && + state->interface != PHY_INTERFACE_MODE_REVMII) { + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseT_Half); + } + + /* On both the 8380 and 8382, ports 24-27 are SFP ports */ + if (port >= 24 && port <= 27) + phylink_set(mask, 1000baseX_Full); + + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + + bitmap_and(supported, supported, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); + bitmap_and(state->advertising, state->advertising, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); +} + +static int rtl838x_phylink_mac_link_state(struct dsa_switch *ds, int port, + struct phylink_link_state *state) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u32 speed; + + if (port < 0 || port > priv->cpu_port) + return -EINVAL; + + state->link = 0; + if (sw_r32(RTL838X_MAC_LINK_STS) & (1 << port)) + state->link = 1; + state->duplex = 0; + if (sw_r32(RTL838X_MAC_LINK_DUP_STS) & (1 << port)) + state->duplex = 1; + + speed = sw_r32(RTL838X_MAC_LINK_SPD_STS(port)); + speed >>= (port % 16) << 1; + switch (speed & 0x3) { + case 0: + state->speed = SPEED_10; + break; + case 1: + state->speed = SPEED_100; + break; + case 2: + state->speed = SPEED_1000; + break; + case 3: + if (port == 24 || port == 26) /* Internal serdes */ + state->speed = SPEED_2500; + else + state->speed = SPEED_100; /* Is in fact 500Mbit */ + } + + state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); + if (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port)) + state->pause |= MLO_PAUSE_RX; + if (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port)) + state->pause |= MLO_PAUSE_TX; + return 1; +} + +static int rtl838x_mdio_probe(struct rtl838x_switch_priv *priv) +{ + struct device *dev = priv->dev; + struct device_node *dn, *mii_np = dev->of_node; + struct mii_bus *bus; + int ret; + u32 pn; + + pr_info("In %s\n", __func__); + mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio"); + if (mii_np) { + pr_info("Found compatible MDIO node!\n"); + } else { + dev_err(priv->dev, "no %s child node found", "mdio-bus"); + return -ENODEV; + } + + priv->mii_bus = of_mdio_find_bus(mii_np); + if (!priv->mii_bus) { + pr_info("Deferring probe of mdio bus\n"); + return -EPROBE_DEFER; + } + if (!of_device_is_available(mii_np)) + ret = -ENODEV; + + bus = devm_mdiobus_alloc(priv->ds->dev); + if (!bus) + return -ENOMEM; + + bus->name = "rtl838x slave mii"; + bus->read = &rtl838x_mdio_read; + bus->write = &rtl838x_mdio_write; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id); + bus->parent = dev; + priv->ds->slave_mii_bus = bus; + priv->ds->slave_mii_bus->priv = priv; + + ret = mdiobus_register(priv->ds->slave_mii_bus); + if (ret && mii_np) { + of_node_put(dn); + return ret; + } + + dn = mii_np; + for_each_node_by_name(dn, "ethernet-phy") { + if (of_property_read_u32(dn, "reg", &pn)) + continue; + + // Check for the integrated SerDes of the RTL8380M first + if (of_property_read_bool(dn, "phy-is-integrated") + && priv->id == 0x8380 && pn >= 24) { + pr_info("----> FÓUND A SERDES\n"); + priv->ports[pn].phy = PHY_RTL838X_SDS; + continue; + } + + if (of_property_read_bool(dn, "phy-is-integrated") + && !of_property_read_bool(dn, "sfp")) { + priv->ports[pn].phy = PHY_RTL8218B_INT; + continue; + } + + if (!of_property_read_bool(dn, "phy-is-integrated") + && of_property_read_bool(dn, "sfp")) { + priv->ports[pn].phy = PHY_RTL8214FC; + continue; + } + + if (!of_property_read_bool(dn, "phy-is-integrated") + && !of_property_read_bool(dn, "sfp")) { + priv->ports[pn].phy = PHY_RTL8218B_EXT; + continue; + } + } + + /* Disable MAC polling the PHY so that we can start configuration */ + sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL); + + /* Enable PHY control via SoC */ + sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL); + /* Power on fibre ports and reset them if necessary */ + if (priv->ports[24].phy == PHY_RTL838X_SDS) { + pr_info("Powering on fibre ports & reset\n"); + rtl8380_sds_power(24, 1); + rtl8380_sds_power(26, 1); + } + + pr_info("%s done\n", __func__); + return 0; +} + +static const struct dsa_switch_ops rtl838x_switch_ops = { + .get_tag_protocol = rtl838x_get_tag_protocol, + .setup = rtl838x_setup, + .port_vlan_filtering = rtl838x_vlan_filtering, + .port_vlan_prepare = rtl838x_vlan_prepare, + .port_vlan_add = rtl838x_vlan_add, + .port_vlan_del = rtl838x_vlan_del, + .port_bridge_join = rtl838x_port_bridge_join, + .port_bridge_leave = rtl838x_port_bridge_leave, + .port_stp_state_set = rtl838x_port_stp_state_set, + .set_ageing_time = rtl838x_set_l2aging, + .port_fast_age = rtl838x_fast_age, + .port_fdb_add = rtl838x_port_fdb_add, + .port_fdb_del = rtl838x_port_fdb_del, + .port_fdb_dump = rtl838x_port_fdb_dump, + .port_enable = rtl838x_port_enable, + .port_disable = rtl838x_port_disable, + .port_mirror_add = rtl838x_port_mirror_add, + .port_mirror_del = rtl838x_port_mirror_del, + .phy_read = dsa_phy_read, + .phy_write = dsa_phy_write, + .get_strings = rtl838x_get_strings, + .get_ethtool_stats = rtl838x_get_ethtool_stats, + .get_sset_count = rtl838x_get_sset_count, + .phylink_validate = rtl838x_phylink_validate, + .phylink_mac_link_state = rtl838x_phylink_mac_link_state, + .phylink_mac_config = rtl838x_phylink_mac_config, + .phylink_mac_link_down = rtl838x_phylink_mac_link_down, + .phylink_mac_link_up = rtl838x_phylink_mac_link_up, + .set_mac_eee = rtl838x_set_mac_eee, + .get_mac_eee = rtl838x_get_mac_eee, + +}; + +static int __init rtl838x_sw_probe(struct platform_device *pdev) +{ + int err = 0, i; + struct rtl838x_switch_priv *priv; + struct device *dev = &pdev->dev; + + pr_info("Probing RTL838X switch device\n"); + if (!pdev->dev.of_node) { + dev_err(dev, "No DT found\n"); + return -EINVAL; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS); + + if (!priv->ds) + return -ENOMEM; + priv->ds->dev = dev; + priv->ds->priv = priv; + priv->ds->ops = &rtl838x_switch_ops; + priv->dev = dev; + + priv->family_id = soc_info.family; + priv->id = soc_info.id; + if (soc_info.family == RTL8380_FAMILY_ID) { + priv->cpu_port = RTL838X_CPU_PORT; + priv->port_mask = 0x1f; + priv->r = &rtl838x_reg; + priv->ds->num_ports = 30; + rtl8380_get_version(priv); + } else { + priv->cpu_port = RTL839X_CPU_PORT; + priv->port_mask = 0x3f; + priv->r = &rtl839x_reg; + priv->ds->num_ports = 53; + rtl8390_get_version(priv); + } + pr_info("Chip version %c\n", priv->version); + + err = rtl838x_mdio_probe(priv); + if (err) { + /* Probing fails the 1st time because of missing ethernet driver + * initialization. Use this to disable traffic in case the bootloader left if on + */ + return err; + } + err = dsa_register_switch(priv->ds); + if (err) { + dev_err(dev, "Error registering switch: %d\n", err); + return err; + } + + /* Enable link and media change interrupts. Are the SERDES masks needed? */ + sw_w32_mask(0, 3, priv->r->isr_glb_src); + /* ... for all ports */ + priv->r->set_port_reg(0xffffffffffffffff, priv->r->isr_port_link_sts_chg); + priv->r->set_port_reg(0xffffffffffffffff, priv->r->imr_port_link_sts_chg); + + priv->link_state_irq = 20; + if (priv->family_id == RTL8380_FAMILY_ID) { + err = request_irq(priv->link_state_irq, rtl838x_switch_irq, + IRQF_SHARED, "rtl8838x-link-state", priv->ds); + } else { + err = request_irq(priv->link_state_irq, rtl839x_switch_irq, + IRQF_SHARED, "rtl8838x-link-state", priv->ds); + } + if (err) { + dev_err(dev, "Error setting up switch interrupt.\n"); + /* Need to free allocated switch here */ + } + + /* Enable interrupts for switch */ + sw_w32(0x1, priv->r->imr_glb); + + rtl838x_get_l2aging(priv); + + /* Clear all destination ports for mirror groups */ + for (i = 0; i < 4; i++) + priv->mirror_group_ports[i] = -1; + + return err; +} + +static int rtl838x_sw_remove(struct platform_device *pdev) +{ + pr_info("Removing platform driver for rtl838x-sw\n"); + return 0; +} + +static const struct of_device_id rtl838x_switch_of_ids[] = { + { .compatible = "realtek,rtl838x-switch"}, + { /* sentinel */ } +}; + + +MODULE_DEVICE_TABLE(of, rtl838x_switch_of_ids); + +static struct platform_driver rtl838x_switch_driver = { + .probe = rtl838x_sw_probe, + .remove = rtl838x_sw_remove, + .driver = { + .name = "rtl838x-switch", + .pm = NULL, + .of_match_table = rtl838x_switch_of_ids, + }, +}; + +module_platform_driver(rtl838x_switch_driver); + +MODULE_AUTHOR("B. Koblitz"); +MODULE_DESCRIPTION("RTL838X SoC Switch Driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c b/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c new file mode 100644 index 0000000000..9634b6a24f --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c @@ -0,0 +1,1205 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/drivers/net/ethernet/rtl838x_eth.c + * Copyright (C) 2020 B. Koblitz + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "rtl838x_eth.h" + +extern struct rtl838x_soc_info soc_info; + +/* + * Maximum number of RX rings is 8, assigned by switch based on + * packet/port priortity (not implemented) + * Maximum number of TX rings is 2 (only ring 0 used) + * RX ringlength needs to be at least 200, otherwise CPU and Switch + * may gridlock. + */ +#define RXRINGS 2 +#define RXRINGLEN 300 +#define TXRINGS 2 +#define TXRINGLEN 160 +#define TX_EN 0x8 +#define RX_EN 0x4 +#define TX_DO 0x2 +#define WRAP 0x2 + +#define RING_BUFFER 1600 + +struct p_hdr { + uint8_t *buf; + uint16_t reserved; + uint16_t size; /* buffer size */ + uint16_t offset; + uint16_t len; /* pkt len */ + uint16_t reserved2; + uint16_t cpu_tag[5]; +} __packed __aligned(1); + +struct ring_b { + uint32_t rx_r[RXRINGS][RXRINGLEN]; + uint32_t tx_r[TXRINGS][TXRINGLEN]; + struct p_hdr rx_header[RXRINGS][RXRINGLEN]; + struct p_hdr tx_header[TXRINGS][TXRINGLEN]; + uint32_t c_rx[RXRINGS]; + uint32_t c_tx[TXRINGS]; + uint8_t rx_space[RXRINGS*RXRINGLEN*RING_BUFFER]; + uint8_t tx_space[TXRINGLEN*RING_BUFFER]; +}; + +struct rtl838x_eth_priv { + struct net_device *netdev; + struct platform_device *pdev; + void *membase; + spinlock_t lock; + struct mii_bus *mii_bus; + struct napi_struct napi; + struct phylink *phylink; + struct phylink_config phylink_config; + u16 id; + u16 family_id; + const struct rtl838x_reg *r; + u8 cpu_port; +}; + +static const struct rtl838x_reg rtl838x_reg = { + .mac_port_ctrl = rtl838x_mac_port_ctrl, + .dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS, + .dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK, + .dma_if_ctrl = RTL838X_DMA_IF_CTRL, + .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl, + .dma_rx_base = rtl838x_dma_rx_base, + .dma_tx_base = rtl838x_dma_tx_base, + .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size, + .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr, + .dma_if_rx_cur = rtl838x_dma_if_rx_cur, + .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0, + .get_mac_link_sts = rtl838x_get_mac_link_sts, + .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts, + .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts, + .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts, + .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts, + .mac = RTL838X_MAC, + .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL, +}; + +static const struct rtl838x_reg rtl839x_reg = { + .mac_port_ctrl = rtl839x_mac_port_ctrl, + .dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS, + .dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK, + .dma_if_ctrl = RTL839X_DMA_IF_CTRL, + .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl, + .dma_rx_base = rtl839x_dma_rx_base, + .dma_tx_base = rtl839x_dma_tx_base, + .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size, + .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr, + .dma_if_rx_cur = rtl839x_dma_if_rx_cur, + .rst_glb_ctrl = RTL839X_RST_GLB_CTRL, + .get_mac_link_sts = rtl839x_get_mac_link_sts, + .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts, + .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts, + .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts, + .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts, + .mac = RTL839X_MAC, + .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL, +}; + +/* + * Discard the RX ring-buffers, called as part of the net-ISR + * when the buffer runs over + * Caller needs to hold priv->lock + */ +static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv) +{ + int r; + u32 *last; + struct p_hdr *h; + struct ring_b *ring = priv->membase; + + for (r = 0; r < RXRINGS; r++) { + last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur(r))); + do { + if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) + break; + h = &ring->rx_header[r][ring->c_rx[r]]; + h->buf = (u8 *)CPHYSADDR(ring->rx_space + + r * ring->c_rx[r] * RING_BUFFER); + h->size = RING_BUFFER; + h->len = 0; + /* make sure the header is visible to the ASIC */ + mb(); + + ring->rx_r[r][ring->c_rx[r]] = CPHYSADDR(h) | 0x1 + | (ring->c_rx[r] == (RXRINGLEN-1) ? WRAP : 0x1); + ring->c_rx[r] = (ring->c_rx[r] + 1) % RXRINGLEN; + } while (&ring->rx_r[r][ring->c_rx[r]] != last); + } +} + +static irqreturn_t rtl838x_net_irq(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct rtl838x_eth_priv *priv = netdev_priv(dev); + u32 status = sw_r32(priv->r->dma_if_intr_sts); + + spin_lock(&priv->lock); + /* Ignore TX interrupt */ + if ((status & 0xf0000)) { + /* Clear ISR */ + sw_w32(0x000f0000, priv->r->dma_if_intr_sts); + } + + /* RX interrupt */ + if (status & 0x0ff00) { + /* Disable RX interrupt */ + sw_w32_mask(0xff00, 0, priv->r->dma_if_intr_msk); + sw_w32(0x0000ff00, priv->r->dma_if_intr_sts); + napi_schedule(&priv->napi); + } + + /* RX buffer overrun */ + if (status & 0x000ff) { + sw_w32(0x000000ff, priv->r->dma_if_intr_sts); + rtl838x_rb_cleanup(priv); + } + + spin_unlock(&priv->lock); + return IRQ_HANDLED; +} + +static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv) +{ + u32 int_saved; + + pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port); + /* Stop TX/RX */ + sw_w32(0x0, priv->r->mac_port_ctrl(priv->cpu_port)); + mdelay(500); + + int_saved = sw_r32(priv->r->dma_if_intr_msk); + /* Reset NIC */ + sw_w32(0x08, priv->r->rst_glb_ctrl); + do { + udelay(20); + } while (sw_r32(priv->r->rst_glb_ctrl) & 0x08); + mdelay(100); + + /* Restore notification settings: on RTL838x these bits are null */ + sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk); + + /* Restart TX/RX to CPU port */ + sw_w32(0x03, priv->r->mac_port_ctrl(priv->cpu_port)); + + if (priv->family_id == RTL8380_FAMILY_ID) { + /* Set Speed, duplex, flow control + * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL + * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN + * | MEDIA_SEL + */ + sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + /* allow CRC errors on CPU-port */ + sw_w32_mask(0, 0x8, priv->r->mac_port_ctrl(priv->cpu_port)); + } else { + /* Force CPU port link up */ + sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + } + + /* Disable and clear interrupts */ + sw_w32(0x00000000, priv->r->dma_if_intr_msk); + sw_w32(0xffffffff, priv->r->dma_if_intr_sts); +} + +static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv) +{ + int i; + struct ring_b *ring = priv->membase; + + for (i = 0; i < RXRINGS; i++) + sw_w32(CPHYSADDR(&ring->rx_r[i]), priv->r->dma_rx_base(i)); + + for (i = 0; i < TXRINGS; i++) + sw_w32(CPHYSADDR(&ring->tx_r[i]), priv->r->dma_tx_base(i)); +} + +static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv) +{ + u32 v; + + pr_info("%s\n", __func__); + /* Disable Head of Line features for all RX rings */ + sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0)); + + /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */ + sw_w32(0x06400020, priv->r->dma_if_ctrl); + + /* Enable RX done, RX overflow and TX done interrupts */ + sw_w32(0xfffff, priv->r->dma_if_intr_msk); + + /* Enable traffic, engine expects empty FCS field */ + sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl); + + /* Make sure to flood all traffic to CPU_PORT */ + if (priv->family_id == RTL8390_FAMILY_ID) { + /* CPU port joins Lookup Miss Flooding Portmask */ + /* Table access: CMD: read, table = 2 */ + /* Sets MC_PMSK table port bit for port 52 to 1 */ + sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17)); + v = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0)); + sw_w32(v | 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0)); + sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17)); + } +} + +static void rtl838x_setup_ring_buffer(struct ring_b *ring) +{ + int i, j; + + struct p_hdr *h; + + for (i = 0; i < RXRINGS; i++) { + for (j = 0; j < RXRINGLEN; j++) { + h = &ring->rx_header[i][j]; + h->buf = (u8 *)CPHYSADDR(ring->rx_space + i * j * RING_BUFFER); + h->reserved = 0; + h->size = RING_BUFFER; + h->offset = 0; + h->len = 0; + /* All rings owned by switch, last one wraps */ + ring->rx_r[i][j] = CPHYSADDR(h) | 1 | (j == (RXRINGLEN - 1) ? WRAP : 0); + } + ring->c_rx[i] = 0; + } + + for (i = 0; i < TXRINGS; i++) { + for (j = 0; j < TXRINGLEN; j++) { + h = &ring->tx_header[i][j]; + h->buf = (u8 *)CPHYSADDR(ring->tx_space + i * j * RING_BUFFER); + h->reserved = 0; + h->size = RING_BUFFER; + h->offset = 0; + h->len = 0; + ring->tx_r[i][j] = CPHYSADDR(&ring->tx_header[i][j]); + } + /* Last header is wrapping around */ + ring->tx_r[i][j-1] |= 2; + ring->c_tx[i] = 0; + } +} + +static int rtl838x_eth_open(struct net_device *ndev) +{ + unsigned long flags; + struct rtl838x_eth_priv *priv = netdev_priv(ndev); + struct ring_b *ring = priv->membase; + int err; + + pr_info("%s called %x, ring %x\n", __func__, (uint32_t)priv, (uint32_t)ring); + spin_lock_irqsave(&priv->lock, flags); + rtl838x_hw_reset(priv); + rtl838x_setup_ring_buffer(ring); + rtl838x_hw_ring_setup(priv); + err = request_irq(ndev->irq, rtl838x_net_irq, IRQF_SHARED, + ndev->name, ndev); + if (err) { + netdev_err(ndev, "%s: could not acquire interrupt: %d\n", + __func__, err); + return err; + } + phylink_start(priv->phylink); + + napi_enable(&priv->napi); + netif_start_queue(ndev); + + rtl838x_hw_en_rxtx(priv); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv) +{ + int i; + + /* Block all ports */ + if (priv->family_id == RTL8380_FAMILY_ID) { + sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0)); + sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1)); + sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0); + } + + /* Flush L2 address cache */ + if (priv->family_id == RTL8380_FAMILY_ID) { + for (i = 0; i <= priv->cpu_port; i++) { + sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl); + do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26)); + } + } else { + for (i = 0; i <= priv->cpu_port; i++) { + sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl); + do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28)); + } + } + + /* CPU-Port: Link down BUG: Works only for RTL838x */ + sw_w32(0x6192D, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + mdelay(100); + + /* Disable traffic */ + sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl); + mdelay(200); + + /* Disable all TX/RX interrupts */ + sw_w32(0x00000000, priv->r->dma_if_intr_msk); + sw_w32(0x000fffff, priv->r->dma_if_intr_sts); + sw_w32(0x00000000, priv->r->dma_if_ctrl); + mdelay(200); +} + +static int rtl838x_eth_stop(struct net_device *ndev) +{ + unsigned long flags; + struct rtl838x_eth_priv *priv = netdev_priv(ndev); + + pr_info("in %s\n", __func__); + + spin_lock_irqsave(&priv->lock, flags); + phylink_stop(priv->phylink); + rtl838x_hw_stop(priv); + free_irq(ndev->irq, ndev); + napi_disable(&priv->napi); + netif_stop_queue(ndev); + spin_unlock_irqrestore(&priv->lock, flags); + return 0; +} + +static void rtl838x_eth_set_multicast_list(struct net_device *dev) +{ + +} + +static void rtl838x_eth_tx_timeout(struct net_device *ndev) +{ + unsigned long flags; + struct rtl838x_eth_priv *priv = netdev_priv(ndev); + + pr_info("in %s\n", __func__); + spin_lock_irqsave(&priv->lock, flags); + rtl838x_hw_stop(priv); + rtl838x_hw_ring_setup(priv); + rtl838x_hw_en_rxtx(priv); + netif_trans_update(ndev); + netif_start_queue(ndev); + spin_unlock_irqrestore(&priv->lock, flags); +} + +static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) +{ + int len, i; + struct rtl838x_eth_priv *priv = netdev_priv(dev); + struct ring_b *ring = priv->membase; + uint32_t val; + int ret; + unsigned long flags; + struct p_hdr *h; + int dest_port = -1; + + spin_lock_irqsave(&priv->lock, flags); + len = skb->len; + + /* Check for DSA tagging at the end of the buffer */ + if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 && skb->data[len-3] > 0 + && skb->data[len-3] < 28 && skb->data[len-2] == 0x10 + && skb->data[len-1] == 0x00) { + /* Reuse tag space for CRC */ + dest_port = skb->data[len-3]; + len -= 4; + } + if (len < ETH_ZLEN) + len = ETH_ZLEN; + + /* ASIC expects that packet includes CRC, so we extend by 4 bytes */ + len += 4; + + if (skb_padto(skb, len)) { + ret = NETDEV_TX_OK; + goto txdone; + } + + /* We can send this packet if CPU owns the descriptor */ + if (!(ring->tx_r[0][ring->c_tx[0]] & 0x1)) { + /* Set descriptor for tx */ + h = &ring->tx_header[0][ring->c_tx[0]]; + + h->buf = (u8 *)CPHYSADDR(ring->tx_space); + h->size = len; + h->len = len; + + /* Create cpu_tag */ + if (dest_port > 0) { + h->cpu_tag[0] = 0x0400; + h->cpu_tag[1] = 0x0200; + h->cpu_tag[2] = 0x0000; + h->cpu_tag[3] = (1 << dest_port) >> 16; + h->cpu_tag[4] = (1 << dest_port) & 0xffff; + } else { + h->cpu_tag[0] = 0; + h->cpu_tag[1] = 0; + h->cpu_tag[2] = 0; + h->cpu_tag[3] = 0; + h->cpu_tag[4] = 0; + } + + /* Copy packet data to tx buffer */ + memcpy((void *)KSEG1ADDR(h->buf), skb->data, len); + /* Make sure packet data is visible to ASIC */ + mb(); + + /* Hand over to switch */ + ring->tx_r[0][ring->c_tx[0]] = ring->tx_r[0][ring->c_tx[0]] | 0x1; + + /* BUG: before tx fetch, need to make sure right data is accessed */ + for (i = 0; i < 10; i++) { + val = sw_r32(priv->r->dma_if_ctrl); + if ((val & 0xc) == 0xc) + break; + } + + /* Tell switch to send data */ + sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl); + + dev->stats.tx_packets++; + dev->stats.tx_bytes += len; + dev_kfree_skb(skb); + ring->c_tx[0] = (ring->c_tx[0] + 1) % TXRINGLEN; + ret = NETDEV_TX_OK; + } else { + dev_warn(&priv->pdev->dev, "Data is owned by switch\n"); + ret = NETDEV_TX_BUSY; + } +txdone: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static int rtl838x_hw_receive(struct net_device *dev, int r, int budget) +{ + struct rtl838x_eth_priv *priv = netdev_priv(dev); + struct ring_b *ring = priv->membase; + struct sk_buff *skb; + unsigned long flags; + int i, len, work_done = 0; + u8 *data, *skb_data; + unsigned int val; + u32 *last; + struct p_hdr *h; + bool dsa = netdev_uses_dsa(dev); + + spin_lock_irqsave(&priv->lock, flags); + last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur(r))); + + if (&ring->rx_r[r][ring->c_rx[r]] == last) { + spin_unlock_irqrestore(&priv->lock, flags); + return 0; + } + do { + if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) { + netdev_warn(dev, "WARNING Ring contention: ring %x, last %x, current %x, cPTR %x, ISR %x\n", r, (uint32_t)last, + (u32) &ring->rx_r[r][ring->c_rx[r]], + ring->rx_r[r][ring->c_rx[r]], + sw_r32(priv->r->dma_if_intr_sts)); + break; + } + + h = &ring->rx_header[r][ring->c_rx[r]]; + data = (u8 *)KSEG1ADDR(h->buf); + len = h->len; + + if (!len) + break; + h->buf = (u8 *)CPHYSADDR(ring->rx_space + + r * ring->c_rx[r] * RING_BUFFER); + h->size = RING_BUFFER; + h->len = 0; + work_done++; + + len -= 4; /* strip the CRC */ + /* Add 4 bytes for cpu_tag */ + if (dsa) + len += 4; + + skb = alloc_skb(len + 4, GFP_KERNEL); + skb_reserve(skb, NET_IP_ALIGN); + + if (likely(skb)) { + /* BUG: Prevent ASIC bug */ + sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0)); + for (i = 0; i < RXRINGS; i++) { + /* Update each ring cnt */ + val = sw_r32(priv->r->dma_if_rx_ring_cntr(i)); + sw_w32(val, priv->r->dma_if_rx_ring_cntr(i)); + } + + skb_data = skb_put(skb, len); + /* Make sure data is visible */ + mb(); + memcpy(skb->data, (u8 *)KSEG1ADDR(data), len); + /* Overwrite CRC with cpu_tag */ + if (dsa) { + skb->data[len-4] = 0x80; + skb->data[len-3] = h->cpu_tag[0] & 0x1f; + skb->data[len-2] = 0x10; + skb->data[len-1] = 0x00; + } + + skb->protocol = eth_type_trans(skb, dev); + dev->stats.rx_packets++; + dev->stats.rx_bytes += len; + + netif_receive_skb(skb); + } else { + if (net_ratelimit()) + dev_warn(&dev->dev, "low on memory - packet dropped\n"); + dev->stats.rx_dropped++; + } + ring->rx_r[r][ring->c_rx[r]] + = CPHYSADDR(h) | 0x1 | (ring->c_rx[r] == (RXRINGLEN-1) ? WRAP : 0x1); + ring->c_rx[r] = (ring->c_rx[r] + 1) % RXRINGLEN; + } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget); + + spin_unlock_irqrestore(&priv->lock, flags); + return work_done; +} + +static int rtl838x_poll_rx(struct napi_struct *napi, int budget) +{ + struct rtl838x_eth_priv *priv = container_of(napi, struct rtl838x_eth_priv, napi); + int work_done = 0, r = 0; + + while (work_done < budget && r < RXRINGS) { + work_done += rtl838x_hw_receive(priv->netdev, r, budget - work_done); + r++; + } + + if (work_done < budget) { + napi_complete_done(napi, work_done); + /* Enable RX interrupt */ + sw_w32(0xfffff, priv->r->dma_if_intr_msk); + } + return work_done; +} + + +static void rtl838x_validate(struct phylink_config *config, + unsigned long *supported, + struct phylink_link_state *state) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + pr_info("In %s\n", __func__); + + if (!phy_interface_mode_is_rgmii(state->interface) && + state->interface != PHY_INTERFACE_MODE_1000BASEX && + state->interface != PHY_INTERFACE_MODE_MII && + state->interface != PHY_INTERFACE_MODE_REVMII && + state->interface != PHY_INTERFACE_MODE_GMII && + state->interface != PHY_INTERFACE_MODE_QSGMII && + state->interface != PHY_INTERFACE_MODE_INTERNAL && + state->interface != PHY_INTERFACE_MODE_SGMII) { + bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); + pr_err("Unsupported interface: %d\n", state->interface); + return; + } + + /* Allow all the expected bits */ + phylink_set(mask, Autoneg); + phylink_set_port_modes(mask); + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + + /* With the exclusion of MII and Reverse MII, we support Gigabit, + * including Half duplex + */ + if (state->interface != PHY_INTERFACE_MODE_MII && + state->interface != PHY_INTERFACE_MODE_REVMII) { + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseT_Half); + } + + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + + bitmap_and(supported, supported, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); + bitmap_and(state->advertising, state->advertising, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); +} + + +static void rtl838x_mac_config(struct phylink_config *config, + unsigned int mode, + const struct phylink_link_state *state) +{ + /* This is only being called for the master device, + * i.e. the CPU-Port + */ + + pr_info("In %s, mode %x\n", __func__, mode); +} + +static void rtl838x_mac_an_restart(struct phylink_config *config) +{ + struct net_device *dev = container_of(config->dev, struct net_device, dev); + struct rtl838x_eth_priv *priv = netdev_priv(dev); + + pr_info("In %s\n", __func__); + /* Restart by disabling and re-enabling link */ + sw_w32(0x6192D, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + mdelay(20); + sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port)); +} + +static int rtl838x_mac_pcs_get_state(struct phylink_config *config, + struct phylink_link_state *state) +{ + u32 speed; + struct net_device *dev = container_of(config->dev, struct net_device, dev); + struct rtl838x_eth_priv *priv = netdev_priv(dev); + int port = priv->cpu_port; + + pr_info("In %s\n", __func__); + + state->link = priv->r->get_mac_link_sts(port) ? 1 : 0; + state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0; + + speed = priv->r->get_mac_link_spd_sts(port); + switch (speed) { + case 0: + state->speed = SPEED_10; + break; + case 1: + state->speed = SPEED_100; + break; + state->speed = SPEED_1000; + break; + default: + state->speed = SPEED_UNKNOWN; + break; + } + + state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); + if (priv->r->get_mac_rx_pause_sts(port)) + state->pause |= MLO_PAUSE_RX; + if (priv->r->get_mac_tx_pause_sts(port)) + state->pause |= MLO_PAUSE_TX; + + return 1; +} + +static void dump_mac_conf(struct rtl838x_eth_priv *priv) +{ + int p; + + for (p = 8; p < 16; p++) { + pr_debug("%d: %x, force %x\n", p, sw_r32(priv->r->mac_port_ctrl(p)), + sw_r32(priv->r->mac_force_mode_ctrl(p)) + ); + } + pr_debug("CPU: %x, force %x\n", sw_r32(priv->r->mac_port_ctrl(priv->cpu_port)), + sw_r32(priv->r->mac_force_mode_ctrl(priv->cpu_port)) + ); +} + +static void rtl838x_mac_link_down(struct phylink_config *config, + unsigned int mode, + phy_interface_t interface) +{ + struct net_device *dev = container_of(config->dev, struct net_device, dev); + struct rtl838x_eth_priv *priv = netdev_priv(dev); + + pr_info("In %s\n", __func__); + /* Stop TX/RX to port */ + sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port)); +} + +static void rtl838x_mac_link_up(struct phylink_config *config, unsigned int mode, + phy_interface_t interface, + struct phy_device *phy) +{ + struct net_device *dev = container_of(config->dev, struct net_device, dev); + struct rtl838x_eth_priv *priv = netdev_priv(dev); + + pr_info("In %s\n", __func__); + /* Restart TX/RX to port */ + sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port)); +} + +static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac) +{ + struct rtl838x_eth_priv *priv = netdev_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + pr_info("In %s\n", __func__); + sw_w32((mac[0] << 8) | mac[1], priv->r->mac); + sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4); + + if (priv->family_id == RTL8380_FAMILY_ID) { + /* 2 more registers, ALE/MAC block */ + sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE); + sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], + (RTL838X_MAC_ALE + 4)); + + sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2); + sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], + RTL838X_MAC2 + 4); + } + spin_unlock_irqrestore(&priv->lock, flags); +} + +static int rtl838x_set_mac_address(struct net_device *dev, void *p) +{ + struct rtl838x_eth_priv *priv = netdev_priv(dev); + const struct sockaddr *addr = p; + u8 *mac = (u8 *) (addr->sa_data); + + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); + rtl838x_set_mac_hw(dev, mac); + + pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4)); + return 0; +} + +static int rtl8390_init_mac(struct rtl838x_eth_priv *priv) +{ + pr_info("Configuring RTL8390 MAC\n"); + // from mac_config_init + sw_w32(0x80, RTL839X_MAC_EFUSE_CTRL); + sw_w32(0x4, RTL839X_RST_GLB_CTRL); + sw_w32(0x3c324f40, RTL839X_MAC_GLB_CTRL); + /* Unlimited egress rate */ + sw_w32(0x1297b961, RTL839X_SCHED_LB_TICK_TKN_CTRL); + + return 0; +} + +static int rtl8380_init_mac(struct rtl838x_eth_priv *priv) +{ + int i; + + if (priv->family_id == 0x8390) + return rtl8390_init_mac(priv); + + if (priv->family_id != 0x8380) + return 0; + + pr_info("%s\n", __func__); + /* fix timer for EEE */ + sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL); + sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL); + + /* Init VLAN */ + if (priv->id == 0x8382) { + for (i = 0; i <= 28; i++) + sw_w32(0, 0xd57c + i * 0x80); + } + if (priv->id == 0x8380) { + for (i = 8; i <= 28; i++) + sw_w32(0, 0xd57c + i * 0x80); + } + return 0; +} + +static int rtl838x_get_link_ksettings(struct net_device *ndev, + struct ethtool_link_ksettings *cmd) +{ + struct rtl838x_eth_priv *priv = netdev_priv(ndev); + + pr_info("%s called\n", __func__); + return phylink_ethtool_ksettings_get(priv->phylink, cmd); +} + +static int rtl838x_set_link_ksettings(struct net_device *ndev, + const struct ethtool_link_ksettings *cmd) +{ + struct rtl838x_eth_priv *priv = netdev_priv(ndev); + + pr_info("%s called\n", __func__); + return phylink_ethtool_ksettings_set(priv->phylink, cmd); +} + + +static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum) +{ + u32 val; + u32 offset = 0; + int err; + struct rtl838x_eth_priv *priv = bus->priv; + + if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) { + if (mii_id == 26) + offset = 0x100; + val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (regnum << 2)) & 0xffff; + return val; + } + err = rtl838x_read_phy(mii_id, 0, regnum, &val); + if (err) + return err; + return val; +} + +static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum) +{ + u32 val; + int err; + + err = rtl839x_read_phy(mii_id, 0, regnum, &val); + if (err) + return err; + return val; +} + +static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id, + int regnum, u16 value) +{ + u32 offset = 0; + struct rtl838x_eth_priv *priv = bus->priv; + + if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) { + if (mii_id == 26) + offset = 0x100; + sw_w32(value, MAPLE_SDS4_FIB_REG0r + offset + (regnum << 2)); + return 0; + } + return rtl838x_write_phy(mii_id, 0, regnum, value); +} + +static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id, + int regnum, u16 value) +{ + return rtl839x_write_phy(mii_id, 0, regnum, value); +} + +static int rtl838x_mdio_reset(struct mii_bus *bus) +{ + pr_info("%s called\n", __func__); + /* Disable MAC polling the PHY so that we can start configuration */ + sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL); + + /* Enable PHY control via SoC */ + sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL); + + return 0; +} + +static int rtl839x_mdio_reset(struct mii_bus *bus) +{ + pr_info("%s called\n", __func__); + /* Disable MAC polling the PHY so that we can start configuration */ + sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL); + sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4); + /* Disable PHY polling via SoC */ + sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL); + + return 0; +} + + +static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv) +{ + struct device_node *mii_np; + int ret; + + pr_info("%s called\n", __func__); + mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus"); + + if (!mii_np) { + dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus"); + return -ENODEV; + } + + if (!of_device_is_available(mii_np)) { + ret = -ENODEV; + goto err_put_node; + } + + priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev); + if (!priv->mii_bus) { + ret = -ENOMEM; + goto err_put_node; + } + + if (priv->family_id == RTL8380_FAMILY_ID) { + priv->mii_bus->name = "rtl838x-eth-mdio"; + priv->mii_bus->read = rtl838x_mdio_read; + priv->mii_bus->write = rtl838x_mdio_write; + priv->mii_bus->reset = rtl838x_mdio_reset; + } else { + priv->mii_bus->name = "rtl839x-eth-mdio"; + priv->mii_bus->read = rtl839x_mdio_read; + priv->mii_bus->write = rtl839x_mdio_write; + priv->mii_bus->reset = rtl839x_mdio_reset; + } + priv->mii_bus->priv = priv; + priv->mii_bus->parent = &priv->pdev->dev; + + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); + ret = of_mdiobus_register(priv->mii_bus, mii_np); + +err_put_node: + of_node_put(mii_np); + return ret; +} + +static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv) +{ + pr_info("%s called\n", __func__); + if (!priv->mii_bus) + return 0; + + mdiobus_unregister(priv->mii_bus); + mdiobus_free(priv->mii_bus); + + return 0; +} + +static const struct net_device_ops rtl838x_eth_netdev_ops = { + .ndo_open = rtl838x_eth_open, + .ndo_stop = rtl838x_eth_stop, + .ndo_start_xmit = rtl838x_eth_tx, + .ndo_set_mac_address = rtl838x_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_rx_mode = rtl838x_eth_set_multicast_list, + .ndo_tx_timeout = rtl838x_eth_tx_timeout, +}; + +static const struct phylink_mac_ops rtl838x_phylink_ops = { + .validate = rtl838x_validate, + .mac_link_state = rtl838x_mac_pcs_get_state, + .mac_an_restart = rtl838x_mac_an_restart, + .mac_config = rtl838x_mac_config, + .mac_link_down = rtl838x_mac_link_down, + .mac_link_up = rtl838x_mac_link_up, +}; + +static const struct ethtool_ops rtl838x_ethtool_ops = { + .get_link_ksettings = rtl838x_get_link_ksettings, + .set_link_ksettings = rtl838x_set_link_ksettings, +}; + +static int __init rtl838x_eth_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct device_node *dn = pdev->dev.of_node; + struct rtl838x_eth_priv *priv; + struct resource *res, *mem; + const void *mac; + phy_interface_t phy_mode; + struct phylink *phylink; + int err = 0; + + pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n", + (u32)pdev, (u32)(&(pdev->dev))); + + if (!dn) { + dev_err(&pdev->dev, "No DT found\n"); + return -EINVAL; + } + + dev = alloc_etherdev(sizeof(struct rtl838x_eth_priv)); + if (!dev) { + err = -ENOMEM; + goto err_free; + } + SET_NETDEV_DEV(dev, &pdev->dev); + priv = netdev_priv(dev); + + /* obtain buffer memory space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res) { + mem = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), res->name); + if (!mem) { + dev_err(&pdev->dev, "cannot request memory space\n"); + err = -ENXIO; + goto err_free; + } + + dev->mem_start = mem->start; + dev->mem_end = mem->end; + } else { + dev_err(&pdev->dev, "cannot request IO resource\n"); + err = -ENXIO; + goto err_free; + } + + /* Allocate buffer memory */ + priv->membase = dmam_alloc_coherent(&pdev->dev, + sizeof(struct ring_b), (void *)&dev->mem_start, + GFP_KERNEL); + if (!priv->membase) { + dev_err(&pdev->dev, "cannot allocate DMA buffer\n"); + err = -ENOMEM; + goto err_free; + } + + spin_lock_init(&priv->lock); + + /* obtain device IRQ number */ + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, "cannot obtain IRQ, using default 24\n"); + dev->irq = 24; + } else { + dev->irq = res->start; + } + dev->ethtool_ops = &rtl838x_ethtool_ops; + + priv->id = soc_info.id; + priv->family_id = soc_info.family; + if (priv->id) { + pr_info("Found SoC ID: %4x: %s, family %x\n", + priv->id, soc_info.name, priv->family_id); + } else { + pr_err("Unknown chip id (%04x)\n", priv->id); + return -ENODEV; + } + + if (priv->family_id == 0x8390) { + priv->cpu_port = RTL839X_CPU_PORT; + priv->r = &rtl839x_reg; + } else { + priv->cpu_port = RTL838X_CPU_PORT; + priv->r = &rtl838x_reg; + } + + rtl8380_init_mac(priv); + + /* try to get mac address in the following order: + * 1) from device tree data + * 2) from internal registers set by bootloader + */ + mac = of_get_mac_address(pdev->dev.of_node); + if (!IS_ERR(mac)) { + memcpy(dev->dev_addr, mac, ETH_ALEN); + rtl838x_set_mac_hw(dev, (u8 *)mac); + } else { + dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff; + dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff; + dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff; + dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff; + dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff; + dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff; + } + /* if the address is invalid, use a random value */ + if (!is_valid_ether_addr(dev->dev_addr)) { + struct sockaddr sa = { AF_UNSPEC }; + + netdev_warn(dev, "Invalid MAC address, using random\n"); + eth_hw_addr_random(dev); + memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN); + if (rtl838x_set_mac_address(dev, &sa)) + netdev_warn(dev, "Failed to set MAC address.\n"); + } + pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), + sw_r32(priv->r->mac + 4)); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = &rtl838x_eth_netdev_ops; + priv->pdev = pdev; + priv->netdev = dev; + + err = rtl838x_mdio_init(priv); + if (err) + goto err_free; + + err = register_netdev(dev); + if (err) + goto err_free; + + netif_napi_add(dev, &priv->napi, rtl838x_poll_rx, 64); + platform_set_drvdata(pdev, dev); + + phy_mode = of_get_phy_mode(dn); + if (phy_mode < 0) { + dev_err(&pdev->dev, "incorrect phy-mode\n"); + err = -EINVAL; + goto err_free; + } + priv->phylink_config.dev = &dev->dev; + priv->phylink_config.type = PHYLINK_NETDEV; + + phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode, + phy_mode, &rtl838x_phylink_ops); + if (IS_ERR(phylink)) { + err = PTR_ERR(phylink); + goto err_free; + } + priv->phylink = phylink; + return 0; + +err_free: + pr_err("Error setting up netdev, freeing it again.\n"); + free_netdev(dev); + return err; +} + +static int rtl838x_eth_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct rtl838x_eth_priv *priv = netdev_priv(dev); + + if (dev) { + pr_info("Removing platform driver for rtl838x-eth\n"); + rtl838x_mdio_remove(priv); + rtl838x_hw_stop(priv); + netif_stop_queue(dev); + netif_napi_del(&priv->napi); + unregister_netdev(dev); + free_netdev(dev); + } + return 0; +} + +static const struct of_device_id rtl838x_eth_of_ids[] = { + { .compatible = "realtek,rtl838x-eth"}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids); + +static struct platform_driver rtl838x_eth_driver = { + .probe = rtl838x_eth_probe, + .remove = rtl838x_eth_remove, + .driver = { + .name = "rtl838x-eth", + .pm = NULL, + .of_match_table = rtl838x_eth_of_ids, + }, +}; + +module_platform_driver(rtl838x_eth_driver); + +MODULE_AUTHOR("B. Koblitz"); +MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h b/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h new file mode 100644 index 0000000000..53ab7e5eb2 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h @@ -0,0 +1,261 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _RTL838X_ETH_H +#define _RTL838X_ETH_H + +/* + * Register definition + */ + +#define RTL838X_CPU_PORT 28 +#define RTL839X_CPU_PORT 52 + +#define RTL838X_MAC_PORT_CTRL (0xd560) +#define RTL839X_MAC_PORT_CTRL (0x8004) +#define RTL838X_DMA_IF_INTR_STS (0x9f54) +#define RTL839X_DMA_IF_INTR_STS (0x7868) +#define RTL838X_DMA_IF_INTR_MSK (0x9f50) +#define RTL839X_DMA_IF_INTR_MSK (0x7864) +#define RTL838X_DMA_IF_CTRL (0x9f58) +#define RTL839X_DMA_IF_CTRL (0x786c) +#define RTL838X_RST_GLB_CTRL_0 (0x003c) +#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104) +#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc) + +/* MAC address settings */ +#define RTL838X_MAC (0xa9ec) +#define RTL839X_MAC (0x02b4) +#define RTL838X_MAC_ALE (0x6b04) +#define RTL838X_MAC2 (0xa320) + +#define RTL838X_DMA_RX_BASE (0x9f00) +#define RTL839X_DMA_RX_BASE (0x780c) +#define RTL838X_DMA_TX_BASE (0x9f40) +#define RTL839X_DMA_TX_BASE (0x784c) +#define RTL838X_DMA_IF_RX_RING_SIZE (0xB7E4) +#define RTL839X_DMA_IF_RX_RING_SIZE (0x6038) +#define RTL838X_DMA_IF_RX_RING_CNTR (0xB7E8) +#define RTL839X_DMA_IF_RX_RING_CNTR (0x603c) +#define RTL838X_DMA_IF_RX_CUR (0x9F20) +#define RTL839X_DMA_IF_RX_CUR (0x782c) + +#define RTL838X_DMY_REG31 (0x3b28) +#define RTL838X_SDS_MODE_SEL (0x0028) +#define RTL838X_SDS_CFG_REG (0x0034) +#define RTL838X_INT_MODE_CTRL (0x005c) +#define RTL838X_CHIP_INFO (0x00d8) +#define RTL838X_SDS4_REG28 (0xef80) +#define RTL838X_SDS4_DUMMY0 (0xef8c) +#define RTL838X_SDS5_EXT_REG6 (0xf18c) +#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2)) +#define RTL838X_STAT_PORT_STD_MIB(port) (0x1200 + (((port) << 8))) +#define RTL838X_STAT_RST (0x3100) +#define RTL838X_STAT_CTRL (0x3108) + +/* Registers of the internal Serdes of the 8380 */ +#define MAPLE_SDS4_REG0r RTL838X_SDS4_REG28 +#define MAPLE_SDS5_REG0r (RTL838X_SDS4_REG28 + 0x100) +#define MAPLE_SDS4_REG3r RTL838X_SDS4_DUMMY0 +#define MAPLE_SDS5_REG3r (RTL838X_SDS4_REG28 + 0x100) +#define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880) +#define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980) + +/* VLAN registers */ +#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2)) +#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84) +#define RTL838X_VLAN_PORT_PB_VLAN(port) (0x3C00 + ((port) << 2)) +#define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C) +#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A7C + 4) +#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) +#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) +#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8) +#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180) +#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2)) +/* MAC handling */ +#define RTL838X_MAC_LINK_STS (0xa188) +#define RTL839X_MAC_LINK_STS (0x0390) +#define RTL838X_MAC_LINK_SPD_STS (0xa190) +#define RTL839X_MAC_LINK_SPD_STS (0x03a0) +#define RTL838X_MAC_LINK_DUP_STS (0xa19c) +#define RTL839X_MAC_LINK_DUP_STS (0x03b0) +// TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ??? +#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0) +#define RTL839X_MAC_TX_PAUSE_STS (0x03b8) +#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4) +#define RTL839X_MAC_RX_PAUSE_STS (0x03c0) +#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) +#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) +#define RTL839X_MAC_GLB_CTRL (0x02a8) +#define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60f8) + +#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) +#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) + +/* MAC link state bits */ +#define FORCE_EN (1 << 0) +#define FORCE_LINK_EN (1 << 1) +#define NWAY_EN (1 << 2) +#define DUPLX_MODE (1 << 3) +#define TX_PAUSE_EN (1 << 6) +#define RX_PAUSE_EN (1 << 7) + +inline int rtl838x_mac_port_ctrl(int p) +{ + return RTL838X_MAC_PORT_CTRL + (p << 7); +} + +inline int rtl839x_mac_port_ctrl(int p) +{ + return RTL839X_MAC_PORT_CTRL + (p << 7); +} + +static inline int rtl838x_mac_force_mode_ctrl(int p) +{ + return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static inline int rtl839x_mac_force_mode_ctrl(int p) +{ + return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +inline int rtl838x_dma_rx_base(int i) +{ + return RTL838X_DMA_RX_BASE + (i << 2); +} + +inline int rtl839x_dma_rx_base(int i) +{ + return RTL839X_DMA_RX_BASE + (i << 2); +} + +inline int rtl838x_dma_tx_base(int i) +{ + return RTL838X_DMA_TX_BASE + (i << 2); +} + +inline int rtl839x_dma_tx_base(int i) +{ + return RTL839X_DMA_TX_BASE + (i << 2); +} + +inline int rtl838x_dma_if_rx_ring_size(int i) +{ + return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2); +} + +inline int rtl839x_dma_if_rx_ring_size(int i) +{ + return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2); +} + +inline int rtl838x_dma_if_rx_ring_cntr(int i) +{ + return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2); +} + +inline int rtl839x_dma_if_rx_ring_cntr(int i) +{ + return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2); +} + + +inline int rtl838x_dma_if_rx_cur(int i) +{ + return RTL838X_DMA_IF_RX_CUR + (i << 2); +} + +inline int rtl839x_dma_if_rx_cur(int i) +{ + return RTL839X_DMA_IF_RX_CUR + (i << 2); +} + +inline u32 rtl838x_get_mac_link_sts(int port) +{ + return (sw_r32(RTL838X_MAC_LINK_STS) & (1 << port)); +} + +inline u32 rtl839x_get_mac_link_sts(int p) +{ + return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & (1 << p)); +} + +inline u32 rtl838x_get_mac_link_dup_sts(int port) +{ + return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & (1 << port)); +} + +inline u32 rtl839x_get_mac_link_dup_sts(int p) +{ + return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & (1 << p)); +} + +inline u32 rtl838x_get_mac_link_spd_sts(int port) +{ + int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2); + u32 speed = sw_r32(r); + + speed >>= (port % 16) << 1; + return (speed & 0x3); +} + +inline u32 rtl839x_get_mac_link_spd_sts(int port) +{ + int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2); + u32 speed = sw_r32(r); + + speed >>= (port % 16) << 1; + return (speed & 0x3); +} + +inline u32 rtl838x_get_mac_rx_pause_sts(int port) +{ + return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port)); +} + +inline u32 rtl839x_get_mac_rx_pause_sts(int p) +{ + return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p)); +} + +inline u32 rtl838x_get_mac_tx_pause_sts(int port) +{ + return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port)); +} + +inline u32 rtl839x_get_mac_tx_pause_sts(int p) +{ + return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p)); +} + + +struct rtl838x_reg { + int (*mac_port_ctrl)(int port); + int dma_if_intr_sts; + int dma_if_intr_msk; + int dma_if_ctrl; + int (*mac_force_mode_ctrl)(int port); + int (*dma_rx_base)(int ring); + int (*dma_tx_base)(int ring); + int (*dma_if_rx_ring_size)(int ring); + int (*dma_if_rx_ring_cntr)(int ring); + int (*dma_if_rx_cur)(int ring); + int rst_glb_ctrl; + u32 (*get_mac_link_sts)(int port); + u32 (*get_mac_link_dup_sts)(int port); + u32 (*get_mac_link_spd_sts)(int port); + u32 (*get_mac_rx_pause_sts)(int port); + u32 (*get_mac_tx_pause_sts)(int port); + int mac; + int l2_tbl_flush_ctrl; +}; + +int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val); +int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val); +int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val); + +extern int rtl8380_sds_power(int mac, int val); + +#endif /* _RTL838X_ETH_H */ diff --git a/target/linux/rtl838x/image/Makefile b/target/linux/rtl838x/image/Makefile new file mode 100644 index 0000000000..eef1fe0a33 --- /dev/null +++ b/target/linux/rtl838x/image/Makefile @@ -0,0 +1,44 @@ +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +KERNEL_LOADADDR = 0x80000000 +KERNEL_ENTRY = 0x80000400 + +define Build/custom-uimage + mkimage -A $(LINUX_KARCH) \ + -O linux -T kernel \ + -C gzip -a $(KERNEL_LOADADDR) $(if $(UIMAGE_MAGIC),-M $(UIMAGE_MAGIC),) \ + -e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \ + -n '$(1)' -d $@ $@.new + mv $@.new $@ +endef + + +define Device/Default + PROFILES = Default + KERNEL := kernel-bin | append-dtb | gzip | uImage gzip + KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | uImage gzip + DEVICE_DTS_DIR := ../dts + DEVICE_DTS = $$(SOC)_$(1) + SUPPORTED_DEVICES := $(subst _,$(comma),$(1)) + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-rootfs | pad-rootfs | \ + append-metadata | check-size +endef + +define Device/allnet_all-sg8208m + SOC := rtl8382 + IMAGE_SIZE := 7168k + DEVICE_VENDOR := ALLNET + DEVICE_MODEL := ALL-SG8208M + UIMAGE_MAGIC := 0x00000006 + KERNEL := kernel-bin | append-dtb | gzip | custom-uimage 2.2.2.0 + KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | custom-uimage 2.2.2.0 + DEVICE_PACKAGES := ip-full ip-bridge kmod-gpio-button-hotplug tc +endef +TARGET_DEVICES += allnet_all-sg8208m + +$(eval $(call BuildImage)) diff --git a/target/linux/rtl838x/patches-5.4/300-mips-add-rtl838x-platform.patch b/target/linux/rtl838x/patches-5.4/300-mips-add-rtl838x-platform.patch new file mode 100644 index 0000000000..34fb959a50 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/300-mips-add-rtl838x-platform.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/Kbuild.platforms ++++ b/arch/mips/Kbuild.platforms +@@ -27,6 +27,7 @@ platforms += pistachio + platforms += pmcs-msp71xx + platforms += pnx833x + platforms += ralink ++platforms += rtl838x + platforms += rb532 + platforms += sgi-ip22 + platforms += sgi-ip27 +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -629,6 +629,29 @@ config RALINK + select ARCH_HAS_RESET_CONTROLLER + select RESET_CONTROLLER + ++config RTL838X ++ bool "Realtek based platforms" ++ select DMA_NONCOHERENT ++ select IRQ_MIPS_CPU ++ select CSRC_R4K ++ select CEVT_R4K ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_HAS_CPU_MIPS32_R2 ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_MIPS16 ++ select SYS_SUPPORTS_MULTITHREADING ++ select SYS_SUPPORTS_VPE_LOADER ++ select SYS_HAS_EARLY_PRINTK ++ select SWAP_IO_SPACE ++ select BOOT_RAW ++ select CLKDEV_LOOKUP ++ select PINCTRL ++ select ARCH_HAS_RESET_CONTROLLER ++ select RESET_CONTROLLER ++ select RTL8380_SERIES ++ select USE_OF ++ + config SGI_IP22 + bool "SGI IP22 (Indy/Indigo2)" + select FW_ARC diff --git a/target/linux/rtl838x/patches-5.4/301-gpio-add-rtl838x-driver.patch b/target/linux/rtl838x/patches-5.4/301-gpio-add-rtl838x-driver.patch new file mode 100644 index 0000000000..5eb8521ccb --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/301-gpio-add-rtl838x-driver.patch @@ -0,0 +1,25 @@ +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -441,6 +441,12 @@ + A 32-bit single register GPIO fixed in/out implementation. This + can be used to represent any register as a set of GPIO signals. + ++config GPIO_RTL838X ++ tristate "RTL838X GPIO" ++ depends on RTL838X ++ help ++ Say yes here to support RTL838X GPIO devices. ++ + config GPIO_SAMA5D2_PIOBU + tristate "SAMA5D2 PIOBU GPIO support" + depends on MFD_SYSCON +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -117,6 +117,7 @@ + obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o + obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o + obj-$(CONFIG_GPIO_REG) += gpio-reg.o ++obj-$(CONFIG_GPIO_RTL838X) += gpio-rtl838x.o + obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o + obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o + obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o diff --git a/target/linux/rtl838x/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch b/target/linux/rtl838x/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch new file mode 100644 index 0000000000..16cff75308 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch @@ -0,0 +1,23 @@ +--- a/drivers/mtd/spi-nor/Kconfig ++++ b/drivers/mtd/spi-nor/Kconfig +@@ -118,4 +118,13 @@ config SPI_INTEL_SPI_PLATFORM + To compile this driver as a module, choose M here: the module + will be called intel-spi-platform. + ++config SPI_RTL838X ++ tristate "Realtek RTl838X SPI flash platform driver" ++ depends on RTL838X ++ help ++ This driver provides support for accessing SPI flash ++ in the RTL838X SoC. ++ ++ Say N here unless you know what you are doing. ++ + endif # MTD_SPI_NOR +--- a/drivers/mtd/spi-nor/Makefile ++++ b/drivers/mtd/spi-nor/Makefile +@@ -8,3 +8,4 @@ obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi + obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o + obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o + obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o ++obj-$(CONFIG_SPI_RTL838X) += rtl838x-nor.o diff --git a/target/linux/rtl838x/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch b/target/linux/rtl838x/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch new file mode 100644 index 0000000000..0082176d83 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch @@ -0,0 +1,26 @@ +--- a/drivers/net/dsa/Kconfig ++++ b/drivers/net/dsa/Kconfig +@@ -74,6 +74,13 @@ config NET_DSA_REALTEK_SMI + This enables support for the Realtek SMI-based switch + chips, currently only RTL8366RB. + ++config NET_DSA_RTL838X ++ tristate "Realtek rtl838x switch support" ++ depends on RTL838X ++ select NET_DSA_TAG_TRAILER ++ ---help--- ++ Say Y here if you want to use the Realtek rtl838x switch. ++ + config NET_DSA_SMSC_LAN9303 + tristate + select NET_DSA_TAG_LAN9303 +--- a/drivers/net/dsa/Makefile ++++ b/drivers/net/dsa/Makefile +@@ -11,6 +11,7 @@ obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e + obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o + obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o + realtek-smi-objs := realtek-smi-core.o rtl8366.o rtl8366rb.o ++obj-$(CONFIG_NET_DSA_RTL838X) += rtl838x_sw.o rtl838x_phy.o + obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o + obj-$(CONFIG_NET_DSA_SMSC_LAN9303_I2C) += lan9303_i2c.o + obj-$(CONFIG_NET_DSA_SMSC_LAN9303_MDIO) += lan9303_mdio.o diff --git a/target/linux/rtl838x/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch b/target/linux/rtl838x/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch new file mode 100644 index 0000000000..d45c547803 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch @@ -0,0 +1,37 @@ +--- a/net/dsa/tag_trailer.c ++++ b/net/dsa/tag_trailer.c +@@ -44,7 +44,12 @@ static struct sk_buff *trailer_xmit(stru + + trailer = skb_put(nskb, 4); + trailer[0] = 0x80; ++ ++#ifdef CONFIG_NET_DSA_RTL838X ++ trailer[1] = dp->index; ++#else + trailer[1] = 1 << dp->index; ++#endif /* CONFIG_NET_DSA_RTL838X */ + trailer[2] = 0x10; + trailer[3] = 0x00; + +@@ -61,12 +66,20 @@ static struct sk_buff *trailer_rcv(struc + return NULL; + + trailer = skb_tail_pointer(skb) - 4; ++ ++#ifdef CONFIG_NET_DSA_RTL838X ++ if (trailer[0] != 0x80 || (trailer[1] & 0xe0) != 0x00 || ++ (trailer[2] & 0xef) != 0x00 || trailer[3] != 0x00) ++ return NULL; ++ ++ source_port = trailer[1] & 0x1f; ++#else + if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 || + (trailer[2] & 0xef) != 0x00 || trailer[3] != 0x00) + return NULL; + + source_port = trailer[1] & 7; +- ++#endif + skb->dev = dsa_master_find_slave(dev, 0, source_port); + if (!skb->dev) + return NULL; diff --git a/target/linux/rtl838x/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch b/target/linux/rtl838x/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch new file mode 100644 index 0000000000..5329dcad59 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch @@ -0,0 +1,13 @@ +Index: linux-5.4.24/include/linux/platform_data/dsa.h +=================================================================== +--- linux-5.4.24.orig/include/linux/platform_data/dsa.h ++++ linux-5.4.24/include/linux/platform_data/dsa.h +@@ -6,7 +6,7 @@ struct device; + struct net_device; + + #define DSA_MAX_SWITCHES 4 +-#define DSA_MAX_PORTS 12 ++#define DSA_MAX_PORTS 54 + #define DSA_RTABLE_NONE -1 + + struct dsa_chip_data { diff --git a/target/linux/rtl838x/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch b/target/linux/rtl838x/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch new file mode 100644 index 0000000000..11e62450d5 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch @@ -0,0 +1,26 @@ +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -163,6 +163,13 @@ source "drivers/net/ethernet/rdc/Kconfig + source "drivers/net/ethernet/realtek/Kconfig" + source "drivers/net/ethernet/renesas/Kconfig" + source "drivers/net/ethernet/rocker/Kconfig" ++ ++config NET_RTL838X ++ tristate "Realtek rtl838x Ethernet MAC support" ++ depends on RTL838X ++ ---help--- ++ Say Y here if you want to use the Realtek rtl838x Gbps Ethernet MAC. ++ + source "drivers/net/ethernet/samsung/Kconfig" + source "drivers/net/ethernet/seeq/Kconfig" + source "drivers/net/ethernet/sfc/Kconfig" +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -76,6 +76,7 @@ obj-$(CONFIG_NET_VENDOR_REALTEK) += real + obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/ + obj-$(CONFIG_NET_VENDOR_RDC) += rdc/ + obj-$(CONFIG_NET_VENDOR_ROCKER) += rocker/ ++obj-$(CONFIG_NET_RTL838X) += rtl838x_eth.o + obj-$(CONFIG_NET_VENDOR_SAMSUNG) += samsung/ + obj-$(CONFIG_NET_VENDOR_SEEQ) += seeq/ + obj-$(CONFIG_NET_VENDOR_SILAN) += silan/ diff --git a/target/linux/rtl838x/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch b/target/linux/rtl838x/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch new file mode 100644 index 0000000000..db8b0403f7 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch @@ -0,0 +1,13 @@ +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -628,6 +628,10 @@ + struct ethtool_tunable *tuna, + const void *data); + int (*set_loopback)(struct phy_device *dev, bool enable); ++ int (*get_port)(struct phy_device *dev); ++ int (*set_port)(struct phy_device *dev, int port); ++ int (*get_eee)(struct phy_device *dev, struct ethtool_eee *e); ++ int (*set_eee)(struct phy_device *dev, struct ethtool_eee *e); + }; + #define to_phy_driver(d) container_of(to_mdio_common_driver(d), \ + struct phy_driver, mdiodrv) diff --git a/target/linux/rtl838x/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch b/target/linux/rtl838x/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch new file mode 100644 index 0000000000..5262be53c6 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch @@ -0,0 +1,41 @@ +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -1244,6 +1244,11 @@ + + /* If we have a PHY, configure the phy */ + if (pl->phydev) { ++ if (pl->phydev->drv->get_port && pl->phydev->drv->set_port) { ++ if(pl->phydev->drv->get_port(pl->phydev) != kset->base.port) { ++ pl->phydev->drv->set_port(pl->phydev, kset->base.port); ++ } ++ } + ret = phy_ethtool_ksettings_set(pl->phydev, &our_kset); + if (ret) + return ret; +@@ -1422,8 +1427,11 @@ + + ASSERT_RTNL(); + +- if (pl->phydev) ++ if (pl->phydev) { ++ if (pl->phydev->drv->get_eee) ++ return pl->phydev->drv->get_eee(pl->phydev, eee); + ret = phy_ethtool_get_eee(pl->phydev, eee); ++ } + + return ret; + } +@@ -1440,9 +1448,11 @@ + + ASSERT_RTNL(); + +- if (pl->phydev) ++ if (pl->phydev) { ++ if (pl->phydev->drv->set_eee) ++ return pl->phydev->drv->set_eee(pl->phydev, eee); + ret = phy_ethtool_set_eee(pl->phydev, eee); +- ++ } + return ret; + } + EXPORT_SYMBOL_GPL(phylink_ethtool_set_eee); diff --git a/target/linux/rtl838x/profiles/00-default.mk b/target/linux/rtl838x/profiles/00-default.mk new file mode 100644 index 0000000000..d6890a815a --- /dev/null +++ b/target/linux/rtl838x/profiles/00-default.mk @@ -0,0 +1,13 @@ +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile + PRIORITY:=1 +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,Default)) From 34cc2c9a99f6542f009aa660790061f169aa96b3 Mon Sep 17 00:00:00 2001 From: Paul Spooren Date: Sun, 13 Sep 2020 15:55:52 -1000 Subject: [PATCH 09/15] build: create tmp/userids file Multiple packages contain a USERID variable defining required user and group for the package to run. With the recent addition of "PKG_FILE_MODES" it is possible to define user and group of specific files, replacing (possibly insecure) post-inst scripts. These modes are set during build time and put directly into the packages. To allow user and group names rather than the numeric values, a mapping like `/etc/passwd` is required by the `ipkg-build` script, mapping names defined in "PKG_FILE_MODES" to a numeric value, as the build system does not create any users during build. This commit adds a single line to the `prepare-tmpinfo` target, so that everytime the feeds are updated the *passwd like* content of `./tmp/userids` is updated. Signed-off-by: Paul Spooren --- include/toplevel.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/include/toplevel.mk b/include/toplevel.mk index c7e71ad571..589af94075 100644 --- a/include/toplevel.mk +++ b/include/toplevel.mk @@ -92,6 +92,7 @@ prepare-tmpinfo: FORCE ./scripts/package-metadata.pl mk tmp/.packageinfo > tmp/.packagedeps || { rm -f tmp/.packagedeps; false; } ./scripts/package-metadata.pl pkgaux tmp/.packageinfo > tmp/.packageauxvars || { rm -f tmp/.packageauxvars; false; } touch $(TOPDIR)/tmp/.build + grep "Require-User" tmp/.packageinfo | cut -d ' ' -f 2- | sort -u | grep "=" > tmp/userids .config: ./scripts/config/conf $(if $(CONFIG_HAVE_DOT_CONFIG),,prepare-tmpinfo) @+if [ \! -e .config ] || ! grep CONFIG_HAVE_DOT_CONFIG .config >/dev/null; then \ From 51ec51871fd57b80096baf76d6b21a2ae46e4748 Mon Sep 17 00:00:00 2001 From: Paul Spooren Date: Sun, 13 Sep 2020 16:02:02 -1000 Subject: [PATCH 10/15] build: add user/group ID resolve function With the introduction of `./tmp/userids` the `ipkg-build` script can now resolve values of "PKG_FILE_MODES", allowing users to set names rather than numeric values. Signed-off-by: Paul Spooren --- scripts/ipkg-build | 42 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/scripts/ipkg-build b/scripts/ipkg-build index e3a9a882cf..c9be18ec47 100755 --- a/scripts/ipkg-build +++ b/scripts/ipkg-build @@ -68,6 +68,40 @@ pkg_appears_sane() { return $PKG_ERROR } +resolve_file_mode_id() { + type="$1" + name="$2" + position=1 + if [ "$type" = "group" ]; then + position=2 + fi + + # root is always 0 + if [ "$name" = "root" ]; then + echo 0 + exit 0 + fi + + # return numeric names + if [ "$name" -eq "$name" 2>/dev/null ]; then + echo "$name" + exit 0 + fi + + ids=$(grep "$name" "$TOPDIR/tmp/userids") + for id in $ids; do + resolved_name=$(echo "$id" | cut -d ":" -f "$position" | cut -d "=" -f 1) + resolved_id=$(echo "$id" | cut -d ":" -f "$position" | cut -d "=" -f 2) + if [ "$resolved_name" = "$name" ]; then + echo "$resolved_id" + exit 0 + fi + done + + >&2 echo "No $type ID found for $name" + exit 1 +} + ### # ipkg-build "main" ### @@ -142,10 +176,14 @@ for file_mode in $file_modes; do ;; esac path=$(echo "$file_mode" | cut -d ':' -f 1) - user_group=$(echo "$file_mode" | cut -d ':' -f 2-3) + user=$(echo "$file_mode" | cut -d ':' -f 2) + group=$(echo "$file_mode" | cut -d ':' -f 3) mode=$(echo "$file_mode" | cut -d ':' -f 4) - chown "$user_group" "$pkg_dir/$path" + uid=$(resolve_file_mode_id user "$user") + gid=$(resolve_file_mode_id group "$group") + + chown "$uid:$gid" "$pkg_dir/$path" chmod "$mode" "$pkg_dir/$path" done $TAR -X $tmp_dir/tarX --format=gnu --sort=name -cpf - --mtime="$TIMESTAMP" . | $GZIP -n - > $tmp_dir/data.tar.gz From 7a29e24dbb6643018195f069d9a7249550dc4b47 Mon Sep 17 00:00:00 2001 From: Jo-Philipp Wich Date: Mon, 14 Sep 2020 16:20:35 +0200 Subject: [PATCH 11/15] build: dump effective user/group id mapping to file This file can be subsequently used to resolve symbolic user or group names to their numeric IDs when packing ipk archives. Signed-off-by: Jo-Philipp Wich --- include/toplevel.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/include/toplevel.mk b/include/toplevel.mk index 589af94075..5d872098db 100644 --- a/include/toplevel.mk +++ b/include/toplevel.mk @@ -91,6 +91,7 @@ prepare-tmpinfo: FORCE [ tmp/.config-feeds.in -nt tmp/.packageauxvars ] || ./scripts/feeds feed_config > tmp/.config-feeds.in ./scripts/package-metadata.pl mk tmp/.packageinfo > tmp/.packagedeps || { rm -f tmp/.packagedeps; false; } ./scripts/package-metadata.pl pkgaux tmp/.packageinfo > tmp/.packageauxvars || { rm -f tmp/.packageauxvars; false; } + ./scripts/package-metadata.pl usergroup tmp/.packageinfo > tmp/.packageusergroup || { rm -f tmp/.packageusergroup; false; } touch $(TOPDIR)/tmp/.build grep "Require-User" tmp/.packageinfo | cut -d ' ' -f 2- | sort -u | grep "=" > tmp/userids From 4038c031cbc156d361e80f73dbd88f83b13a4057 Mon Sep 17 00:00:00 2001 From: Jo-Philipp Wich Date: Mon, 14 Sep 2020 16:57:46 +0200 Subject: [PATCH 12/15] scripts: ipkg-build: simplify uid/gid resolving Use the prepared .packageusergroup file to lookup user and group names when processing the passed file mode. Also replace the various subshell/cut invocations with a sequence of standard variable interpolations which fixes paths with embedded colons as a side-effect. Signed-off-by: Jo-Philipp Wich --- scripts/ipkg-build | 63 +++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 35 deletions(-) diff --git a/scripts/ipkg-build b/scripts/ipkg-build index c9be18ec47..343aab6caf 100755 --- a/scripts/ipkg-build +++ b/scripts/ipkg-build @@ -69,37 +69,23 @@ pkg_appears_sane() { } resolve_file_mode_id() { - type="$1" - name="$2" - position=1 - if [ "$type" = "group" ]; then - position=2 - fi + local var=$1 type=$2 name=$3 id - # root is always 0 - if [ "$name" = "root" ]; then - echo 0 - exit 0 - fi + case "$name" in + root) + id=0 + ;; + *[!0-9]*) + id=$(sed -ne "s#^$type $name \\([0-9]\\+\\)\\b.*\$#\\1#p" "$TOPDIR/tmp/.packageusergroup" 2>/dev/null) + ;; + *) + id=$name + ;; + esac - # return numeric names - if [ "$name" -eq "$name" 2>/dev/null ]; then - echo "$name" - exit 0 - fi + export "$var=$id" - ids=$(grep "$name" "$TOPDIR/tmp/userids") - for id in $ids; do - resolved_name=$(echo "$id" | cut -d ":" -f "$position" | cut -d "=" -f 1) - resolved_id=$(echo "$id" | cut -d ":" -f "$position" | cut -d "=" -f 2) - if [ "$resolved_name" = "$name" ]; then - echo "$resolved_id" - exit 0 - fi - done - - >&2 echo "No $type ID found for $name" - exit 1 + [ -n "$id" ] } ### @@ -135,7 +121,7 @@ case $# in ;; *) echo $usage >&2 - exit 1 + exit 1 ;; esac @@ -175,13 +161,20 @@ for file_mode in $file_modes; do exit 1 ;; esac - path=$(echo "$file_mode" | cut -d ':' -f 1) - user=$(echo "$file_mode" | cut -d ':' -f 2) - group=$(echo "$file_mode" | cut -d ':' -f 3) - mode=$(echo "$file_mode" | cut -d ':' -f 4) - uid=$(resolve_file_mode_id user "$user") - gid=$(resolve_file_mode_id group "$group") + mode=${file_mode##*:}; path=${file_mode%:*} + group=${path##*:}; path=${path%:*} + user=${path##*:}; path=${path%:*} + + if ! resolve_file_mode_id uid user "$user"; then + echo "ERROR: unable to resolve uid of $user" >&2 + exit 1 + fi + + if ! resolve_file_mode_id gid group "$group"; then + echo "ERROR: unable to resolve gid of $group" >&2 + exit 1 + fi chown "$uid:$gid" "$pkg_dir/$path" chmod "$mode" "$pkg_dir/$path" From 0b82ebaccbb4aa5033d0ea33b14027edd6dcafc0 Mon Sep 17 00:00:00 2001 From: Jo-Philipp Wich Date: Mon, 14 Sep 2020 16:16:59 +0200 Subject: [PATCH 13/15] Revert "build: create tmp/userids file" This reverts commit 34cc2c9a99f6542f009aa660790061f169aa96b3. The reverted shell code is a very poor reimplementation of the existing package-metadata.pl usergroup subcommand and the resulting file is not used anymore, so drop this code. Signed-off-by: Jo-Philipp Wich --- include/toplevel.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/include/toplevel.mk b/include/toplevel.mk index 5d872098db..c233a4c214 100644 --- a/include/toplevel.mk +++ b/include/toplevel.mk @@ -93,7 +93,6 @@ prepare-tmpinfo: FORCE ./scripts/package-metadata.pl pkgaux tmp/.packageinfo > tmp/.packageauxvars || { rm -f tmp/.packageauxvars; false; } ./scripts/package-metadata.pl usergroup tmp/.packageinfo > tmp/.packageusergroup || { rm -f tmp/.packageusergroup; false; } touch $(TOPDIR)/tmp/.build - grep "Require-User" tmp/.packageinfo | cut -d ' ' -f 2- | sort -u | grep "=" > tmp/userids .config: ./scripts/config/conf $(if $(CONFIG_HAVE_DOT_CONFIG),,prepare-tmpinfo) @+if [ \! -e .config ] || ! grep CONFIG_HAVE_DOT_CONFIG .config >/dev/null; then \ From d5c4750a712797cc039ceec8986e875aa679a864 Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Tue, 15 Sep 2020 12:28:43 +0200 Subject: [PATCH 14/15] rtl838x: remove and add some empty lines Do some minor empty lines cleanup, i.e. remove those at EOF and add some for cosmetic reasons/consistency. Signed-off-by: Adrian Schmutzler --- target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c | 1 - target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c | 1 + target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c | 1 + target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c | 1 + target/linux/rtl838x/profiles/00-default.mk | 1 + 5 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c index 604b01806c..c1678b8785 100644 --- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c @@ -171,4 +171,3 @@ void __init prom_init(void) pr_info("SoC Type: %s\n", get_system_type()); prom_init_cmdline(); } - diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c index cebab1df8d..8a85933baf 100644 --- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c @@ -8,6 +8,7 @@ * Copyright (C) 2020 B. Koblitz * */ + #include #include #include diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c index 6a9485c451..f59481f76d 100644 --- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c @@ -8,6 +8,7 @@ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) * */ + #include #include #include diff --git a/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c b/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c index bba3b3f572..9b1cd3d70c 100644 --- a/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c +++ b/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only + #include #include #include diff --git a/target/linux/rtl838x/profiles/00-default.mk b/target/linux/rtl838x/profiles/00-default.mk index d6890a815a..7f2053da55 100644 --- a/target/linux/rtl838x/profiles/00-default.mk +++ b/target/linux/rtl838x/profiles/00-default.mk @@ -10,4 +10,5 @@ endef define Profile/Default/Description Default package set compatible with most boards. endef + $(eval $(call Profile,Default)) From 4a3230683ba12e4cd688304c551d40398b1e7ad3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 15 Sep 2020 13:41:19 +0200 Subject: [PATCH 15/15] uhttpd: update to the latest master MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1172357 ubus: add new RESTful API fe1888f ubus: fix blob_buf initialization Fixes: 3d167ed805a9 ("uhttpd: update to the latest master") Signed-off-by: Rafał Miłecki --- package/network/services/uhttpd/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/network/services/uhttpd/Makefile b/package/network/services/uhttpd/Makefile index 88478927cc..697ffc10b2 100644 --- a/package/network/services/uhttpd/Makefile +++ b/package/network/services/uhttpd/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/uhttpd.git -PKG_SOURCE_DATE:=2020-08-05 -PKG_SOURCE_VERSION:=212f8364d49c1bc27dd8bdc394fc3615ea9b7ba3 -PKG_MIRROR_HASH:=c717924cd075951846cb8ad271f4754db56af53a271ed0afbdc5a2f482e15f97 +PKG_SOURCE_DATE:=2020-09-15 +PKG_SOURCE_VERSION:=11723570af9cb7bd87842e79c85ee99530be9902 +PKG_MIRROR_HASH:=39aa6d700689419db8e8f9bf59a4b9c9539c3ee636e0befebf38476bc883cc18 PKG_MAINTAINER:=Felix Fietkau PKG_LICENSE:=ISC