diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index adab44327c..520ffb61a6 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -40,6 +40,13 @@ define U-Boot/nanopi-r2c-rk3328 friendlyarm_nanopi-r2c endef +define U-Boot/nanopi-r2c-plus-rk3328 + $(U-Boot/Default/rk3328) + NAME:=NanoPi R2C Plus + BUILD_DEVICES:= \ + friendlyarm_nanopi-r2c-plus +endef + define U-Boot/nanopi-r2s-rk3328 $(U-Boot/Default/rk3328) NAME:=NanoPi R2S @@ -163,6 +170,7 @@ UBOOT_TARGETS := \ rock-pi-4-rk3399 \ rockpro64-rk3399 \ nanopi-r2c-rk3328 \ + nanopi-r2c-plus-rk3328 \ nanopi-r2s-rk3328 \ orangepi-r1-plus-rk3328 \ orangepi-r1-plus-lts-rk3328 \ diff --git a/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch b/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch index 4fda320391..8cb5dc5949 100644 --- a/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch +++ b/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch @@ -1,17 +1,18 @@ --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -123,7 +123,10 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ +@@ -123,7 +123,11 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ + rk3328-nanopi-r2c.dtb \ ++ rk3328-nanopi-r2c-plus.dtb \ rk3328-nanopi-r2s.dtb \ + rk3328-orangepi-r1-plus.dtb \ + rk3328-orangepi-r1-plus-lts.dtb \ rk3328-roc-cc.dtb \ rk3328-rock64.dtb \ rk3328-rock-pi-e.dtb -@@ -151,6 +154,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ +@@ -151,6 +155,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-nanopi-m4b.dtb \ rk3399-nanopi-neo4.dtb \ rk3399-nanopi-r4s.dtb \ @@ -20,7 +21,7 @@ rk3399-orangepi.dtb \ rk3399-pinebook-pro.dtb \ rk3399-pinephone-pro.dtb \ -@@ -166,6 +171,11 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ +@@ -166,6 +172,11 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3568-evb.dtb \ diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi new file mode 100644 index 0000000000..1dc3c022c5 --- /dev/null +++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "rk3328-nanopi-r2c-u-boot.dtsi" diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c-plus.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c-plus.dts new file mode 100644 index 0000000000..edccc5563c --- /dev/null +++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c-plus.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + */ + +/dts-v1/; +#include "rk3328-nanopi-r2c.dts" + +/ { + model = "FriendlyElec NanoPi R2C Plus"; + compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io_33>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; diff --git a/package/boot/uboot-rockchip/src/configs/nanopi-r2c-plus-rk3328_defconfig b/package/boot/uboot-rockchip/src/configs/nanopi-r2c-plus-rk3328_defconfig new file mode 100644 index 0000000000..26cee82bc3 --- /dev/null +++ b/package/boot/uboot-rockchip/src/configs/nanopi-r2c-plus-rk3328_defconfig @@ -0,0 +1,112 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2000000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y