From ef7d8003336544198b83b0b606b9bc0767183f5f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 16 Jun 2023 09:16:39 +0200 Subject: [PATCH 01/17] kernel: backport NVMEM patches queued for the v6.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This includes some driver changes and support for fixed cells layout. Signed-off-by: Rafał Miłecki (cherry picked from commit 07bdc5551558287f7a99f6ae8e6d82d7d09d5781) --- ...set-varaiable-imx_ocotp_layout-stora.patch | 31 +++ ...Reverse-MAC-addresses-on-all-i.MX-de.patch | 71 ++++++ ...ram-add-.read_post_process-for-MACs.patch} | 6 +- ...tp-Add-clks-and-reg_read-to-rockchip.patch | 166 +++++++++++++ ...tp-Generalize-rockchip_otp_wait_stat.patch | 62 +++++ ...tp-Use-devm_reset_control_array_get_.patch | 31 +++ ...hip-otp-Improve-probe-error-handling.patch | 71 ++++++ ...-rockchip-otp-Add-support-for-RK3588.patch | 129 ++++++++++ ...-Switch-xilinx.com-emails-to-amd.com.patch | 26 ++ ...-0010-nvmem-imx-support-i.MX93-OCOTP.patch | 230 ++++++++++++++++++ ...e-add-support-for-fixed-cells-layout.patch | 96 ++++++++ target/linux/imx/config-5.15 | 1 + target/linux/layerscape/armv7/config-5.15 | 1 + 13 files changed, 920 insertions(+), 1 deletion(-) create mode 100644 target/linux/generic/backport-5.15/813-v6.5-0001-nvmem-imx-ocotp-set-varaiable-imx_ocotp_layout-stora.patch create mode 100644 target/linux/generic/backport-5.15/813-v6.5-0002-nvmem-imx-ocotp-Reverse-MAC-addresses-on-all-i.MX-de.patch rename target/linux/generic/backport-5.15/{813-v6.5-nvmem-brcm_nvram-add-.read_post_process-for-MACs.patch => 813-v6.5-0003-nvmem-brcm_nvram-add-.read_post_process-for-MACs.patch} (87%) create mode 100644 target/linux/generic/backport-5.15/813-v6.5-0004-nvmem-rockchip-otp-Add-clks-and-reg_read-to-rockchip.patch create mode 100644 target/linux/generic/backport-5.15/813-v6.5-0005-nvmem-rockchip-otp-Generalize-rockchip_otp_wait_stat.patch create mode 100644 target/linux/generic/backport-5.15/813-v6.5-0006-nvmem-rockchip-otp-Use-devm_reset_control_array_get_.patch create mode 100644 target/linux/generic/backport-5.15/813-v6.5-0007-nvmem-rockchip-otp-Improve-probe-error-handling.patch create mode 100644 target/linux/generic/backport-5.15/813-v6.5-0008-nvmem-rockchip-otp-Add-support-for-RK3588.patch create mode 100644 target/linux/generic/backport-5.15/813-v6.5-0009-nvmem-zynqmp-Switch-xilinx.com-emails-to-amd.com.patch create mode 100644 target/linux/generic/backport-5.15/813-v6.5-0010-nvmem-imx-support-i.MX93-OCOTP.patch create mode 100644 target/linux/generic/backport-5.15/813-v6.5-0011-nvmem-core-add-support-for-fixed-cells-layout.patch diff --git a/target/linux/generic/backport-5.15/813-v6.5-0001-nvmem-imx-ocotp-set-varaiable-imx_ocotp_layout-stora.patch b/target/linux/generic/backport-5.15/813-v6.5-0001-nvmem-imx-ocotp-set-varaiable-imx_ocotp_layout-stora.patch new file mode 100644 index 0000000000..38cfccd5ef --- /dev/null +++ b/target/linux/generic/backport-5.15/813-v6.5-0001-nvmem-imx-ocotp-set-varaiable-imx_ocotp_layout-stora.patch @@ -0,0 +1,31 @@ +From eebc6573ad940b62a87776db3917e912b4f52d78 Mon Sep 17 00:00:00 2001 +From: Tom Rix +Date: Sun, 11 Jun 2023 15:03:05 +0100 +Subject: [PATCH] nvmem: imx-ocotp: set varaiable imx_ocotp_layout + storage-class-specifier to static + +smatch reports +drivers/nvmem/imx-ocotp.c:599:21: warning: symbol + 'imx_ocotp_layout' was not declared. Should it be static? + +This variable is only used in one file so should be static. + +Signed-off-by: Tom Rix +Signed-off-by: Srinivas Kandagatla +Message-ID: <20230611140330.154222-2-srinivas.kandagatla@linaro.org> +Signed-off-by: Greg Kroah-Hartman +--- + drivers/nvmem/imx-ocotp.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/nvmem/imx-ocotp.c ++++ b/drivers/nvmem/imx-ocotp.c +@@ -596,7 +596,7 @@ static void imx_ocotp_fixup_cell_info(st + cell->read_post_process = imx_ocotp_cell_pp; + } + +-struct nvmem_layout imx_ocotp_layout = { ++static struct nvmem_layout imx_ocotp_layout = { + .fixup_cell_info = imx_ocotp_fixup_cell_info, + }; + diff --git a/target/linux/generic/backport-5.15/813-v6.5-0002-nvmem-imx-ocotp-Reverse-MAC-addresses-on-all-i.MX-de.patch b/target/linux/generic/backport-5.15/813-v6.5-0002-nvmem-imx-ocotp-Reverse-MAC-addresses-on-all-i.MX-de.patch new file mode 100644 index 0000000000..7523e5ebf6 --- /dev/null +++ b/target/linux/generic/backport-5.15/813-v6.5-0002-nvmem-imx-ocotp-Reverse-MAC-addresses-on-all-i.MX-de.patch @@ -0,0 +1,71 @@ +From 8a00fc606312c68b98add8fe8e6f7a013ce29e78 Mon Sep 17 00:00:00 2001 +From: Alexander Stein +Date: Sun, 11 Jun 2023 15:03:06 +0100 +Subject: [PATCH] nvmem: imx-ocotp: Reverse MAC addresses on all i.MX derivates + +Not just i.MX8M, but all i.MX6/7 (and subtypes) need to reverse the +MAC address read from fuses. Exceptions are i.MX6SLL and i.MX7ULP which +do not support ethernet at all. + +Fixes: d0221a780cbc ("nvmem: imx-ocotp: add support for post processing") +Signed-off-by: Alexander Stein +Tested-by: Richard Leitner # imx6q +Signed-off-by: Srinivas Kandagatla +Message-ID: <20230611140330.154222-3-srinivas.kandagatla@linaro.org> +Signed-off-by: Greg Kroah-Hartman +--- + drivers/nvmem/imx-ocotp.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +--- a/drivers/nvmem/imx-ocotp.c ++++ b/drivers/nvmem/imx-ocotp.c +@@ -97,7 +97,6 @@ struct ocotp_params { + unsigned int bank_address_words; + void (*set_timing)(struct ocotp_priv *priv); + struct ocotp_ctrl_reg ctrl; +- bool reverse_mac_address; + }; + + static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags) +@@ -545,7 +544,6 @@ static const struct ocotp_params imx8mq_ + .bank_address_words = 0, + .set_timing = imx_ocotp_set_imx6_timing, + .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, +- .reverse_mac_address = true, + }; + + static const struct ocotp_params imx8mm_params = { +@@ -553,7 +551,6 @@ static const struct ocotp_params imx8mm_ + .bank_address_words = 0, + .set_timing = imx_ocotp_set_imx6_timing, + .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, +- .reverse_mac_address = true, + }; + + static const struct ocotp_params imx8mn_params = { +@@ -561,7 +558,6 @@ static const struct ocotp_params imx8mn_ + .bank_address_words = 0, + .set_timing = imx_ocotp_set_imx6_timing, + .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, +- .reverse_mac_address = true, + }; + + static const struct ocotp_params imx8mp_params = { +@@ -569,7 +565,6 @@ static const struct ocotp_params imx8mp_ + .bank_address_words = 0, + .set_timing = imx_ocotp_set_imx6_timing, + .ctrl = IMX_OCOTP_BM_CTRL_8MP, +- .reverse_mac_address = true, + }; + + static const struct of_device_id imx_ocotp_dt_ids[] = { +@@ -624,8 +619,7 @@ static int imx_ocotp_probe(struct platfo + imx_ocotp_nvmem_config.size = 4 * priv->params->nregs; + imx_ocotp_nvmem_config.dev = dev; + imx_ocotp_nvmem_config.priv = priv; +- if (priv->params->reverse_mac_address) +- imx_ocotp_nvmem_config.layout = &imx_ocotp_layout; ++ imx_ocotp_nvmem_config.layout = &imx_ocotp_layout; + + priv->config = &imx_ocotp_nvmem_config; + diff --git a/target/linux/generic/backport-5.15/813-v6.5-nvmem-brcm_nvram-add-.read_post_process-for-MACs.patch b/target/linux/generic/backport-5.15/813-v6.5-0003-nvmem-brcm_nvram-add-.read_post_process-for-MACs.patch similarity index 87% rename from target/linux/generic/backport-5.15/813-v6.5-nvmem-brcm_nvram-add-.read_post_process-for-MACs.patch rename to target/linux/generic/backport-5.15/813-v6.5-0003-nvmem-brcm_nvram-add-.read_post_process-for-MACs.patch index 8749cad7f7..fb4d346a95 100644 --- a/target/linux/generic/backport-5.15/813-v6.5-nvmem-brcm_nvram-add-.read_post_process-for-MACs.patch +++ b/target/linux/generic/backport-5.15/813-v6.5-0003-nvmem-brcm_nvram-add-.read_post_process-for-MACs.patch @@ -1,5 +1,6 @@ +From 73bcd133c910bff3b6d3b3834d0d14be9444e90a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 6 Apr 2023 12:46:16 +0200 +Date: Sun, 11 Jun 2023 15:03:08 +0100 Subject: [PATCH] nvmem: brcm_nvram: add .read_post_process() for MACs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -9,6 +10,9 @@ Content-Transfer-Encoding: 8bit 2. Calculate relative addresses based on index argument Signed-off-by: Rafał Miłecki +Signed-off-by: Srinivas Kandagatla +Message-ID: <20230611140330.154222-5-srinivas.kandagatla@linaro.org> +Signed-off-by: Greg Kroah-Hartman --- drivers/nvmem/Kconfig | 1 + drivers/nvmem/brcm_nvram.c | 28 ++++++++++++++++++++++++++++ diff --git a/target/linux/generic/backport-5.15/813-v6.5-0004-nvmem-rockchip-otp-Add-clks-and-reg_read-to-rockchip.patch b/target/linux/generic/backport-5.15/813-v6.5-0004-nvmem-rockchip-otp-Add-clks-and-reg_read-to-rockchip.patch new file mode 100644 index 0000000000..3b6e6e57f5 --- /dev/null +++ b/target/linux/generic/backport-5.15/813-v6.5-0004-nvmem-rockchip-otp-Add-clks-and-reg_read-to-rockchip.patch @@ -0,0 +1,166 @@ +From 8dc61364164e79e44c07fa2ac0a7b6939f00d5db Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sun, 11 Jun 2023 15:03:13 +0100 +Subject: [PATCH] nvmem: rockchip-otp: Add clks and reg_read to rockchip_data + +In preparation to support new Rockchip OTP memory devices with different +clock configurations and register layout, extend rockchip_data struct +with the related members: clks, num_clks, reg_read. + +Additionally, to avoid managing redundant driver data, drop num_clks +member from rockchip_otp struct and update all references to point to +the equivalent member in rockchip_data. + +Signed-off-by: Cristian Ciocaltea +Tested-by: Vincent Legoll +Reviewed-by: Heiko Stuebner +Signed-off-by: Srinivas Kandagatla +Message-ID: <20230611140330.154222-10-srinivas.kandagatla@linaro.org> +Signed-off-by: Greg Kroah-Hartman +--- + drivers/nvmem/rockchip-otp.c | 79 ++++++++++++++++++++++-------------- + 1 file changed, 49 insertions(+), 30 deletions(-) + +--- a/drivers/nvmem/rockchip-otp.c ++++ b/drivers/nvmem/rockchip-otp.c +@@ -54,21 +54,19 @@ + + #define OTPC_TIMEOUT 10000 + ++struct rockchip_data { ++ int size; ++ const char * const *clks; ++ int num_clks; ++ nvmem_reg_read_t reg_read; ++}; ++ + struct rockchip_otp { + struct device *dev; + void __iomem *base; +- struct clk_bulk_data *clks; +- int num_clks; ++ struct clk_bulk_data *clks; + struct reset_control *rst; +-}; +- +-/* list of required clocks */ +-static const char * const rockchip_otp_clocks[] = { +- "otp", "apb_pclk", "phy", +-}; +- +-struct rockchip_data { +- int size; ++ const struct rockchip_data *data; + }; + + static int rockchip_otp_reset(struct rockchip_otp *otp) +@@ -132,29 +130,23 @@ static int rockchip_otp_ecc_enable(struc + return ret; + } + +-static int rockchip_otp_read(void *context, unsigned int offset, +- void *val, size_t bytes) ++static int px30_otp_read(void *context, unsigned int offset, ++ void *val, size_t bytes) + { + struct rockchip_otp *otp = context; + u8 *buf = val; +- int ret = 0; +- +- ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks); +- if (ret < 0) { +- dev_err(otp->dev, "failed to prepare/enable clks\n"); +- return ret; +- } ++ int ret; + + ret = rockchip_otp_reset(otp); + if (ret) { + dev_err(otp->dev, "failed to reset otp phy\n"); +- goto disable_clks; ++ return ret; + } + + ret = rockchip_otp_ecc_enable(otp, false); + if (ret < 0) { + dev_err(otp->dev, "rockchip_otp_ecc_enable err\n"); +- goto disable_clks; ++ return ret; + } + + writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); +@@ -174,8 +166,28 @@ static int rockchip_otp_read(void *conte + + read_end: + writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); +-disable_clks: +- clk_bulk_disable_unprepare(otp->num_clks, otp->clks); ++ ++ return ret; ++} ++ ++static int rockchip_otp_read(void *context, unsigned int offset, ++ void *val, size_t bytes) ++{ ++ struct rockchip_otp *otp = context; ++ int ret; ++ ++ if (!otp->data || !otp->data->reg_read) ++ return -EINVAL; ++ ++ ret = clk_bulk_prepare_enable(otp->data->num_clks, otp->clks); ++ if (ret < 0) { ++ dev_err(otp->dev, "failed to prepare/enable clks\n"); ++ return ret; ++ } ++ ++ ret = otp->data->reg_read(context, offset, val, bytes); ++ ++ clk_bulk_disable_unprepare(otp->data->num_clks, otp->clks); + + return ret; + } +@@ -189,8 +201,15 @@ static struct nvmem_config otp_config = + .reg_read = rockchip_otp_read, + }; + ++static const char * const px30_otp_clocks[] = { ++ "otp", "apb_pclk", "phy", ++}; ++ + static const struct rockchip_data px30_data = { + .size = 0x40, ++ .clks = px30_otp_clocks, ++ .num_clks = ARRAY_SIZE(px30_otp_clocks), ++ .reg_read = px30_otp_read, + }; + + static const struct of_device_id rockchip_otp_match[] = { +@@ -225,21 +244,21 @@ static int rockchip_otp_probe(struct pla + if (!otp) + return -ENOMEM; + ++ otp->data = data; + otp->dev = dev; + otp->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(otp->base)) + return PTR_ERR(otp->base); + +- otp->num_clks = ARRAY_SIZE(rockchip_otp_clocks); +- otp->clks = devm_kcalloc(dev, otp->num_clks, +- sizeof(*otp->clks), GFP_KERNEL); ++ otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks), ++ GFP_KERNEL); + if (!otp->clks) + return -ENOMEM; + +- for (i = 0; i < otp->num_clks; ++i) +- otp->clks[i].id = rockchip_otp_clocks[i]; ++ for (i = 0; i < data->num_clks; ++i) ++ otp->clks[i].id = data->clks[i]; + +- ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks); ++ ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks); + if (ret) + return ret; + diff --git a/target/linux/generic/backport-5.15/813-v6.5-0005-nvmem-rockchip-otp-Generalize-rockchip_otp_wait_stat.patch b/target/linux/generic/backport-5.15/813-v6.5-0005-nvmem-rockchip-otp-Generalize-rockchip_otp_wait_stat.patch new file mode 100644 index 0000000000..b5b66cfc5a --- /dev/null +++ b/target/linux/generic/backport-5.15/813-v6.5-0005-nvmem-rockchip-otp-Generalize-rockchip_otp_wait_stat.patch @@ -0,0 +1,62 @@ +From 30fd21cfb1e64ef20035559a8246f5fbf682c40e Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sun, 11 Jun 2023 15:03:14 +0100 +Subject: [PATCH] nvmem: rockchip-otp: Generalize rockchip_otp_wait_status() + +In preparation to support additional Rockchip OTP memory devices with +different register layout, generalize rockchip_otp_wait_status() to +accept a new parameter for specifying the offset of the status register. + +Signed-off-by: Cristian Ciocaltea +Tested-by: Vincent Legoll +Reviewed-by: Heiko Stuebner +Signed-off-by: Srinivas Kandagatla +Message-ID: <20230611140330.154222-11-srinivas.kandagatla@linaro.org> +Signed-off-by: Greg Kroah-Hartman +--- + drivers/nvmem/rockchip-otp.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +--- a/drivers/nvmem/rockchip-otp.c ++++ b/drivers/nvmem/rockchip-otp.c +@@ -90,18 +90,19 @@ static int rockchip_otp_reset(struct roc + return 0; + } + +-static int rockchip_otp_wait_status(struct rockchip_otp *otp, u32 flag) ++static int rockchip_otp_wait_status(struct rockchip_otp *otp, ++ unsigned int reg, u32 flag) + { + u32 status = 0; + int ret; + +- ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status, ++ ret = readl_poll_timeout_atomic(otp->base + reg, status, + (status & flag), 1, OTPC_TIMEOUT); + if (ret) + return ret; + + /* clean int status */ +- writel(flag, otp->base + OTPC_INT_STATUS); ++ writel(flag, otp->base + reg); + + return 0; + } +@@ -123,7 +124,7 @@ static int rockchip_otp_ecc_enable(struc + + writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL); + +- ret = rockchip_otp_wait_status(otp, OTPC_SBPI_DONE); ++ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_SBPI_DONE); + if (ret < 0) + dev_err(otp->dev, "timeout during ecc_enable\n"); + +@@ -156,7 +157,7 @@ static int px30_otp_read(void *context, + otp->base + OTPC_USER_ADDR); + writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK, + otp->base + OTPC_USER_ENABLE); +- ret = rockchip_otp_wait_status(otp, OTPC_USER_DONE); ++ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE); + if (ret < 0) { + dev_err(otp->dev, "timeout during read setup\n"); + goto read_end; diff --git a/target/linux/generic/backport-5.15/813-v6.5-0006-nvmem-rockchip-otp-Use-devm_reset_control_array_get_.patch b/target/linux/generic/backport-5.15/813-v6.5-0006-nvmem-rockchip-otp-Use-devm_reset_control_array_get_.patch new file mode 100644 index 0000000000..3a17479d95 --- /dev/null +++ b/target/linux/generic/backport-5.15/813-v6.5-0006-nvmem-rockchip-otp-Use-devm_reset_control_array_get_.patch @@ -0,0 +1,31 @@ +From d325c9dd2b6e94040ca722ddcadcd6af358dd2be Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sun, 11 Jun 2023 15:03:15 +0100 +Subject: [PATCH] nvmem: rockchip-otp: Use + devm_reset_control_array_get_exclusive() + +In preparation to support new Rockchip OTP memory devices having +specific reset configurations, switch devm_reset_control_get() to +devm_reset_control_array_get_exclusive(). + +Signed-off-by: Cristian Ciocaltea +Tested-by: Vincent Legoll +Reviewed-by: Heiko Stuebner +Signed-off-by: Srinivas Kandagatla +Message-ID: <20230611140330.154222-12-srinivas.kandagatla@linaro.org> +Signed-off-by: Greg Kroah-Hartman +--- + drivers/nvmem/rockchip-otp.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/nvmem/rockchip-otp.c ++++ b/drivers/nvmem/rockchip-otp.c +@@ -263,7 +263,7 @@ static int rockchip_otp_probe(struct pla + if (ret) + return ret; + +- otp->rst = devm_reset_control_get(dev, "phy"); ++ otp->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(otp->rst)) + return PTR_ERR(otp->rst); + diff --git a/target/linux/generic/backport-5.15/813-v6.5-0007-nvmem-rockchip-otp-Improve-probe-error-handling.patch b/target/linux/generic/backport-5.15/813-v6.5-0007-nvmem-rockchip-otp-Improve-probe-error-handling.patch new file mode 100644 index 0000000000..37cb927b10 --- /dev/null +++ b/target/linux/generic/backport-5.15/813-v6.5-0007-nvmem-rockchip-otp-Improve-probe-error-handling.patch @@ -0,0 +1,71 @@ +From 912517345b867a69542dc9f5c2cc3e9d8beaccf5 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sun, 11 Jun 2023 15:03:16 +0100 +Subject: [PATCH] nvmem: rockchip-otp: Improve probe error handling + +Enhance error handling in the probe function by making use of +dev_err_probe(), which ensures the error code is always printed, in +addition to the specified error message. + +Signed-off-by: Cristian Ciocaltea +Tested-by: Vincent Legoll +Reviewed-by: Heiko Stuebner +Signed-off-by: Srinivas Kandagatla +Message-ID: <20230611140330.154222-13-srinivas.kandagatla@linaro.org> +Signed-off-by: Greg Kroah-Hartman +--- + drivers/nvmem/rockchip-otp.c | 21 ++++++++++++--------- + 1 file changed, 12 insertions(+), 9 deletions(-) + +--- a/drivers/nvmem/rockchip-otp.c ++++ b/drivers/nvmem/rockchip-otp.c +@@ -235,10 +235,8 @@ static int rockchip_otp_probe(struct pla + int ret, i; + + data = of_device_get_match_data(dev); +- if (!data) { +- dev_err(dev, "failed to get match data\n"); +- return -EINVAL; +- } ++ if (!data) ++ return dev_err_probe(dev, -EINVAL, "failed to get match data\n"); + + otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp), + GFP_KERNEL); +@@ -249,7 +247,8 @@ static int rockchip_otp_probe(struct pla + otp->dev = dev; + otp->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(otp->base)) +- return PTR_ERR(otp->base); ++ return dev_err_probe(dev, PTR_ERR(otp->base), ++ "failed to ioremap resource\n"); + + otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks), + GFP_KERNEL); +@@ -261,18 +260,22 @@ static int rockchip_otp_probe(struct pla + + ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks); + if (ret) +- return ret; ++ return dev_err_probe(dev, ret, "failed to get clocks\n"); + + otp->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(otp->rst)) +- return PTR_ERR(otp->rst); ++ return dev_err_probe(dev, PTR_ERR(otp->rst), ++ "failed to get resets\n"); + + otp_config.size = data->size; + otp_config.priv = otp; + otp_config.dev = dev; +- nvmem = devm_nvmem_register(dev, &otp_config); + +- return PTR_ERR_OR_ZERO(nvmem); ++ nvmem = devm_nvmem_register(dev, &otp_config); ++ if (IS_ERR(nvmem)) ++ return dev_err_probe(dev, PTR_ERR(nvmem), ++ "failed to register nvmem device\n"); ++ return 0; + } + + static struct platform_driver rockchip_otp_driver = { diff --git a/target/linux/generic/backport-5.15/813-v6.5-0008-nvmem-rockchip-otp-Add-support-for-RK3588.patch b/target/linux/generic/backport-5.15/813-v6.5-0008-nvmem-rockchip-otp-Add-support-for-RK3588.patch new file mode 100644 index 0000000000..c1e2231c9e --- /dev/null +++ b/target/linux/generic/backport-5.15/813-v6.5-0008-nvmem-rockchip-otp-Add-support-for-RK3588.patch @@ -0,0 +1,129 @@ +From 8ab099fafbbc8c9607c399d21a774784a6cb8b45 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sun, 11 Jun 2023 15:03:17 +0100 +Subject: [PATCH] nvmem: rockchip-otp: Add support for RK3588 + +Add support for the OTP memory device found on the Rockchip RK3588 SoC. + +While here, remove the unnecessary 'void *' casts in the OF device ID +table. + +Co-developed-by: Finley Xiao +Signed-off-by: Finley Xiao +Signed-off-by: Cristian Ciocaltea +Tested-by: Vincent Legoll +Reviewed-by: Heiko Stuebner +Signed-off-by: Srinivas Kandagatla +Message-ID: <20230611140330.154222-14-srinivas.kandagatla@linaro.org> +Signed-off-by: Greg Kroah-Hartman +--- + drivers/nvmem/rockchip-otp.c | 78 +++++++++++++++++++++++++++++++++++- + 1 file changed, 76 insertions(+), 2 deletions(-) + +--- a/drivers/nvmem/rockchip-otp.c ++++ b/drivers/nvmem/rockchip-otp.c +@@ -54,6 +54,19 @@ + + #define OTPC_TIMEOUT 10000 + ++/* RK3588 Register */ ++#define RK3588_OTPC_AUTO_CTRL 0x04 ++#define RK3588_OTPC_AUTO_EN 0x08 ++#define RK3588_OTPC_INT_ST 0x84 ++#define RK3588_OTPC_DOUT0 0x20 ++#define RK3588_NO_SECURE_OFFSET 0x300 ++#define RK3588_NBYTES 4 ++#define RK3588_BURST_NUM 1 ++#define RK3588_BURST_SHIFT 8 ++#define RK3588_ADDR_SHIFT 16 ++#define RK3588_AUTO_EN BIT(0) ++#define RK3588_RD_DONE BIT(1) ++ + struct rockchip_data { + int size; + const char * const *clks; +@@ -171,6 +184,52 @@ read_end: + return ret; + } + ++static int rk3588_otp_read(void *context, unsigned int offset, ++ void *val, size_t bytes) ++{ ++ struct rockchip_otp *otp = context; ++ unsigned int addr_start, addr_end, addr_len; ++ int ret, i = 0; ++ u32 data; ++ u8 *buf; ++ ++ addr_start = round_down(offset, RK3588_NBYTES) / RK3588_NBYTES; ++ addr_end = round_up(offset + bytes, RK3588_NBYTES) / RK3588_NBYTES; ++ addr_len = addr_end - addr_start; ++ addr_start += RK3588_NO_SECURE_OFFSET; ++ ++ buf = kzalloc(array_size(addr_len, RK3588_NBYTES), GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ while (addr_len--) { ++ writel((addr_start << RK3588_ADDR_SHIFT) | ++ (RK3588_BURST_NUM << RK3588_BURST_SHIFT), ++ otp->base + RK3588_OTPC_AUTO_CTRL); ++ writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN); ++ ++ ret = rockchip_otp_wait_status(otp, RK3588_OTPC_INT_ST, ++ RK3588_RD_DONE); ++ if (ret < 0) { ++ dev_err(otp->dev, "timeout during read setup\n"); ++ goto read_end; ++ } ++ ++ data = readl(otp->base + RK3588_OTPC_DOUT0); ++ memcpy(&buf[i], &data, RK3588_NBYTES); ++ ++ i += RK3588_NBYTES; ++ addr_start++; ++ } ++ ++ memcpy(val, buf + offset % RK3588_NBYTES, bytes); ++ ++read_end: ++ kfree(buf); ++ ++ return ret; ++} ++ + static int rockchip_otp_read(void *context, unsigned int offset, + void *val, size_t bytes) + { +@@ -213,14 +272,29 @@ static const struct rockchip_data px30_d + .reg_read = px30_otp_read, + }; + ++static const char * const rk3588_otp_clocks[] = { ++ "otp", "apb_pclk", "phy", "arb", ++}; ++ ++static const struct rockchip_data rk3588_data = { ++ .size = 0x400, ++ .clks = rk3588_otp_clocks, ++ .num_clks = ARRAY_SIZE(rk3588_otp_clocks), ++ .reg_read = rk3588_otp_read, ++}; ++ + static const struct of_device_id rockchip_otp_match[] = { + { + .compatible = "rockchip,px30-otp", +- .data = (void *)&px30_data, ++ .data = &px30_data, + }, + { + .compatible = "rockchip,rk3308-otp", +- .data = (void *)&px30_data, ++ .data = &px30_data, ++ }, ++ { ++ .compatible = "rockchip,rk3588-otp", ++ .data = &rk3588_data, + }, + { /* sentinel */ }, + }; diff --git a/target/linux/generic/backport-5.15/813-v6.5-0009-nvmem-zynqmp-Switch-xilinx.com-emails-to-amd.com.patch b/target/linux/generic/backport-5.15/813-v6.5-0009-nvmem-zynqmp-Switch-xilinx.com-emails-to-amd.com.patch new file mode 100644 index 0000000000..220e3e9a05 --- /dev/null +++ b/target/linux/generic/backport-5.15/813-v6.5-0009-nvmem-zynqmp-Switch-xilinx.com-emails-to-amd.com.patch @@ -0,0 +1,26 @@ +From 9734408969e978a1c0d5d752be63dd638288e374 Mon Sep 17 00:00:00 2001 +From: Michal Simek +Date: Sun, 11 Jun 2023 15:03:23 +0100 +Subject: [PATCH] nvmem: zynqmp: Switch @xilinx.com emails to @amd.com + +@xilinx.com is still working but better to switch to new amd.com after +AMD/Xilinx acquisition. + +Signed-off-by: Michal Simek +Signed-off-by: Srinivas Kandagatla +Message-ID: <20230611140330.154222-20-srinivas.kandagatla@linaro.org> +Signed-off-by: Greg Kroah-Hartman +--- + drivers/nvmem/zynqmp_nvmem.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/nvmem/zynqmp_nvmem.c ++++ b/drivers/nvmem/zynqmp_nvmem.c +@@ -76,6 +76,6 @@ static struct platform_driver zynqmp_nvm + + module_platform_driver(zynqmp_nvmem_driver); + +-MODULE_AUTHOR("Michal Simek , Nava kishore Manne "); ++MODULE_AUTHOR("Michal Simek , Nava kishore Manne "); + MODULE_DESCRIPTION("ZynqMP NVMEM driver"); + MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/backport-5.15/813-v6.5-0010-nvmem-imx-support-i.MX93-OCOTP.patch b/target/linux/generic/backport-5.15/813-v6.5-0010-nvmem-imx-support-i.MX93-OCOTP.patch new file mode 100644 index 0000000000..f8e6be4241 --- /dev/null +++ b/target/linux/generic/backport-5.15/813-v6.5-0010-nvmem-imx-support-i.MX93-OCOTP.patch @@ -0,0 +1,230 @@ +From 22e9e6fcfb5042cb6d6c7874c459b034800092f1 Mon Sep 17 00:00:00 2001 +From: Peng Fan +Date: Sun, 11 Jun 2023 15:03:25 +0100 +Subject: [PATCH] nvmem: imx: support i.MX93 OCOTP + +Add i.MX93 OCOTP support. i.MX93 OCOTP has two parts: Fuse shadow +block(fsb) and fuse managed by ELE. The FSB part could be directly +accessed with MMIO, the ELE could only be accessed with ELE API. + +Currently the ELE API is not ready, so NULL function callback is used, +but it was tested with downstream ELE API. + +Signed-off-by: Peng Fan +Signed-off-by: Srinivas Kandagatla +Message-ID: <20230611140330.154222-22-srinivas.kandagatla@linaro.org> +Signed-off-by: Greg Kroah-Hartman +--- + drivers/nvmem/Kconfig | 9 ++ + drivers/nvmem/Makefile | 2 + + drivers/nvmem/imx-ocotp-ele.c | 175 ++++++++++++++++++++++++++++++++++ + 3 files changed, 186 insertions(+) + create mode 100644 drivers/nvmem/imx-ocotp-ele.c + +--- a/drivers/nvmem/Kconfig ++++ b/drivers/nvmem/Kconfig +@@ -83,6 +83,15 @@ config NVMEM_IMX_OCOTP + This driver can also be built as a module. If so, the module + will be called nvmem-imx-ocotp. + ++config NVMEM_IMX_OCOTP_ELE ++ tristate "i.MX On-Chip OTP Controller support" ++ depends on ARCH_MXC || COMPILE_TEST ++ depends on HAS_IOMEM ++ depends on OF ++ help ++ This is a driver for the On-Chip OTP Controller (OCOTP) ++ available on i.MX SoCs which has ELE. ++ + config NVMEM_IMX_OCOTP_SCU + tristate "i.MX8 SCU On-Chip OTP Controller support" + depends on IMX_SCU +--- a/drivers/nvmem/Makefile ++++ b/drivers/nvmem/Makefile +@@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_IIM) += nvmem-im + nvmem-imx-iim-y := imx-iim.o + obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o + nvmem-imx-ocotp-y := imx-ocotp.o ++obj-$(CONFIG_NVMEM_IMX_OCOTP_ELE) += nvmem-imx-ocotp-ele.o ++nvmem-imx-ocotp-ele-y := imx-ocotp-ele.o + obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o + nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o + obj-$(CONFIG_NVMEM_JZ4780_EFUSE) += nvmem_jz4780_efuse.o +--- /dev/null ++++ b/drivers/nvmem/imx-ocotp-ele.c +@@ -0,0 +1,175 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * i.MX9 OCOTP fusebox driver ++ * ++ * Copyright 2023 NXP ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++enum fuse_type { ++ FUSE_FSB = 1, ++ FUSE_ELE = 2, ++ FUSE_INVALID = -1 ++}; ++ ++struct ocotp_map_entry { ++ u32 start; /* start word */ ++ u32 num; /* num words */ ++ enum fuse_type type; ++}; ++ ++struct ocotp_devtype_data { ++ u32 reg_off; ++ char *name; ++ u32 size; ++ u32 num_entry; ++ u32 flag; ++ nvmem_reg_read_t reg_read; ++ struct ocotp_map_entry entry[]; ++}; ++ ++struct imx_ocotp_priv { ++ struct device *dev; ++ void __iomem *base; ++ struct nvmem_config config; ++ struct mutex lock; ++ const struct ocotp_devtype_data *data; ++}; ++ ++static enum fuse_type imx_ocotp_fuse_type(void *context, u32 index) ++{ ++ struct imx_ocotp_priv *priv = context; ++ const struct ocotp_devtype_data *data = priv->data; ++ u32 start, end; ++ int i; ++ ++ for (i = 0; i < data->num_entry; i++) { ++ start = data->entry[i].start; ++ end = data->entry[i].start + data->entry[i].num; ++ ++ if (index >= start && index < end) ++ return data->entry[i].type; ++ } ++ ++ return FUSE_INVALID; ++} ++ ++static int imx_ocotp_reg_read(void *context, unsigned int offset, void *val, size_t bytes) ++{ ++ struct imx_ocotp_priv *priv = context; ++ void __iomem *reg = priv->base + priv->data->reg_off; ++ u32 count, index, num_bytes; ++ enum fuse_type type; ++ u32 *buf; ++ void *p; ++ int i; ++ ++ index = offset; ++ num_bytes = round_up(bytes, 4); ++ count = num_bytes >> 2; ++ ++ if (count > ((priv->data->size >> 2) - index)) ++ count = (priv->data->size >> 2) - index; ++ ++ p = kzalloc(num_bytes, GFP_KERNEL); ++ if (!p) ++ return -ENOMEM; ++ ++ mutex_lock(&priv->lock); ++ ++ buf = p; ++ ++ for (i = index; i < (index + count); i++) { ++ type = imx_ocotp_fuse_type(context, i); ++ if (type == FUSE_INVALID || type == FUSE_ELE) { ++ *buf++ = 0; ++ continue; ++ } ++ ++ *buf++ = readl_relaxed(reg + (i << 2)); ++ } ++ ++ memcpy(val, (u8 *)p, bytes); ++ ++ mutex_unlock(&priv->lock); ++ ++ kfree(p); ++ ++ return 0; ++}; ++ ++static int imx_ele_ocotp_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct imx_ocotp_priv *priv; ++ struct nvmem_device *nvmem; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->data = of_device_get_match_data(dev); ++ ++ priv->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ ++ priv->config.dev = dev; ++ priv->config.name = "ELE-OCOTP"; ++ priv->config.id = NVMEM_DEVID_AUTO; ++ priv->config.owner = THIS_MODULE; ++ priv->config.size = priv->data->size; ++ priv->config.reg_read = priv->data->reg_read; ++ priv->config.word_size = 4; ++ priv->config.stride = 1; ++ priv->config.priv = priv; ++ priv->config.read_only = true; ++ mutex_init(&priv->lock); ++ ++ nvmem = devm_nvmem_register(dev, &priv->config); ++ if (IS_ERR(nvmem)) ++ return PTR_ERR(nvmem); ++ ++ return 0; ++} ++ ++static const struct ocotp_devtype_data imx93_ocotp_data = { ++ .reg_off = 0x8000, ++ .reg_read = imx_ocotp_reg_read, ++ .size = 2048, ++ .num_entry = 6, ++ .entry = { ++ { 0, 52, FUSE_FSB }, ++ { 63, 1, FUSE_ELE}, ++ { 128, 16, FUSE_ELE }, ++ { 182, 1, FUSE_ELE }, ++ { 188, 1, FUSE_ELE }, ++ { 312, 200, FUSE_FSB } ++ }, ++}; ++ ++static const struct of_device_id imx_ele_ocotp_dt_ids[] = { ++ { .compatible = "fsl,imx93-ocotp", .data = &imx93_ocotp_data, }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, imx_ele_ocotp_dt_ids); ++ ++static struct platform_driver imx_ele_ocotp_driver = { ++ .driver = { ++ .name = "imx_ele_ocotp", ++ .of_match_table = imx_ele_ocotp_dt_ids, ++ }, ++ .probe = imx_ele_ocotp_probe, ++}; ++module_platform_driver(imx_ele_ocotp_driver); ++ ++MODULE_DESCRIPTION("i.MX OCOTP/ELE driver"); ++MODULE_AUTHOR("Peng Fan "); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/backport-5.15/813-v6.5-0011-nvmem-core-add-support-for-fixed-cells-layout.patch b/target/linux/generic/backport-5.15/813-v6.5-0011-nvmem-core-add-support-for-fixed-cells-layout.patch new file mode 100644 index 0000000000..59b2f9fa2c --- /dev/null +++ b/target/linux/generic/backport-5.15/813-v6.5-0011-nvmem-core-add-support-for-fixed-cells-layout.patch @@ -0,0 +1,96 @@ +From 27f699e578b1a72df89dfa3bc42e093a01dc8d10 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 11 Jun 2023 15:03:29 +0100 +Subject: [PATCH] nvmem: core: add support for fixed cells *layout* +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This adds support for the "fixed-layout" NVMEM layout binding. It allows +defining NVMEM cells in a layout DT node named "nvmem-layout". + +While NVMEM subsystem supports layout drivers it has been discussed that +"fixed-layout" may actually be supperted internally. It's because: +1. It's a very basic layout +2. It allows sharing code with legacy syntax parsing +3. It's safer for soc_device_match() due to -EPROBE_DEFER +4. This will make the syntax transition easier + +Signed-off-by: Rafał Miłecki +Reviewed-by: Michael Walle +Signed-off-by: Srinivas Kandagatla +Message-ID: <20230611140330.154222-26-srinivas.kandagatla@linaro.org> +Signed-off-by: Greg Kroah-Hartman +--- + drivers/nvmem/core.c | 32 +++++++++++++++++++++++++++++--- + 1 file changed, 29 insertions(+), 3 deletions(-) + +--- a/drivers/nvmem/core.c ++++ b/drivers/nvmem/core.c +@@ -696,7 +696,7 @@ static int nvmem_validate_keepouts(struc + return 0; + } + +-static int nvmem_add_cells_from_of(struct nvmem_device *nvmem) ++static int nvmem_add_cells_from_dt(struct nvmem_device *nvmem, struct device_node *np) + { + struct nvmem_layout *layout = nvmem->layout; + struct device *dev = &nvmem->dev; +@@ -704,7 +704,7 @@ static int nvmem_add_cells_from_of(struc + const __be32 *addr; + int len, ret; + +- for_each_child_of_node(dev->of_node, child) { ++ for_each_child_of_node(np, child) { + struct nvmem_cell_info info = {0}; + + addr = of_get_property(child, "reg", &len); +@@ -742,6 +742,28 @@ static int nvmem_add_cells_from_of(struc + return 0; + } + ++static int nvmem_add_cells_from_legacy_of(struct nvmem_device *nvmem) ++{ ++ return nvmem_add_cells_from_dt(nvmem, nvmem->dev.of_node); ++} ++ ++static int nvmem_add_cells_from_fixed_layout(struct nvmem_device *nvmem) ++{ ++ struct device_node *layout_np; ++ int err = 0; ++ ++ layout_np = of_nvmem_layout_get_container(nvmem); ++ if (!layout_np) ++ return 0; ++ ++ if (of_device_is_compatible(layout_np, "fixed-layout")) ++ err = nvmem_add_cells_from_dt(nvmem, layout_np); ++ ++ of_node_put(layout_np); ++ ++ return err; ++} ++ + int __nvmem_layout_register(struct nvmem_layout *layout, struct module *owner) + { + layout->owner = owner; +@@ -972,7 +994,7 @@ struct nvmem_device *nvmem_register(cons + if (rval) + goto err_remove_cells; + +- rval = nvmem_add_cells_from_of(nvmem); ++ rval = nvmem_add_cells_from_legacy_of(nvmem); + if (rval) + goto err_remove_cells; + +@@ -982,6 +1004,10 @@ struct nvmem_device *nvmem_register(cons + if (rval) + goto err_remove_cells; + ++ rval = nvmem_add_cells_from_fixed_layout(nvmem); ++ if (rval) ++ goto err_remove_cells; ++ + rval = nvmem_add_cells_from_layout(nvmem); + if (rval) + goto err_remove_cells; diff --git a/target/linux/imx/config-5.15 b/target/linux/imx/config-5.15 index 73d0b3fe78..7caaacbed7 100644 --- a/target/linux/imx/config-5.15 +++ b/target/linux/imx/config-5.15 @@ -295,6 +295,7 @@ CONFIG_NR_CPUS=4 CONFIG_NVMEM=y # CONFIG_NVMEM_IMX_IIM is not set CONFIG_NVMEM_IMX_OCOTP=y +# CONFIG_NVMEM_IMX_OCOTP_ELE is not set # CONFIG_NVMEM_SNVS_LPGPR is not set CONFIG_NVMEM_SYSFS=y CONFIG_OF=y diff --git a/target/linux/layerscape/armv7/config-5.15 b/target/linux/layerscape/armv7/config-5.15 index d7f151438b..b5df343f4e 100644 --- a/target/linux/layerscape/armv7/config-5.15 +++ b/target/linux/layerscape/armv7/config-5.15 @@ -413,6 +413,7 @@ CONFIG_NR_CPUS=16 CONFIG_NTFS_FS=y CONFIG_NVMEM=y # CONFIG_NVMEM_IMX_IIM is not set +# CONFIG_NVMEM_IMX_OCOTP_ELE is not set # CONFIG_NVMEM_SNVS_LPGPR is not set # CONFIG_NVMEM_SPMI_SDAM is not set CONFIG_NVMEM_SYSFS=y From e341d51e0655e8d1442676181e136364eb090c11 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 10 Jul 2023 11:38:01 +0200 Subject: [PATCH 02/17] bcm47xx: fix bgmac MTU patch filename MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes: 4970dd027bce ("bcm47xx: revert bgmac back to the old limited max frame size") Signed-off-by: Rafał Miłecki (cherry picked from commit 83aeb0bbd47638b42ee6cdda351d0c51e014d790) --- ...01-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename target/linux/bcm47xx/patches-5.15/{701-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch => 701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch} (100%) diff --git a/target/linux/bcm47xx/patches-5.15/701-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch b/target/linux/bcm47xx/patches-5.15/701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch similarity index 100% rename from target/linux/bcm47xx/patches-5.15/701-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch rename to target/linux/bcm47xx/patches-5.15/701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch From a210fced85b9d052580084802c7dfe9243901452 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 10 Jul 2023 11:38:23 +0200 Subject: [PATCH 03/17] kernel: bgmac: fix regressed support for BCM53573 SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Rafał Miłecki (cherry picked from commit d54f3b2cfdbd34aa61ca67fd590eebfdf3db51cf) --- ...ne-turning-IRQs-off-to-avoid-SoC-han.patch | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 target/linux/generic/backport-5.15/735-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch diff --git a/target/linux/generic/backport-5.15/735-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch b/target/linux/generic/backport-5.15/735-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch new file mode 100644 index 0000000000..26e9ae3bcd --- /dev/null +++ b/target/linux/generic/backport-5.15/735-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch @@ -0,0 +1,45 @@ +From e7731194fdf085f46d58b1adccfddbd0dfee4873 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 7 Jul 2023 08:53:25 +0200 +Subject: [PATCH] net: bgmac: postpone turning IRQs off to avoid SoC hangs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Turning IRQs off is done by accessing Ethernet controller registers. +That can't be done until device's clock is enabled. It results in a SoC +hang otherwise. + +This bug remained unnoticed for years as most bootloaders keep all +Ethernet interfaces turned on. It seems to only affect a niche SoC +family BCM47189. It has two Ethernet controllers but CFE bootloader uses +only the first one. + +Fixes: 34322615cbaa ("net: bgmac: Mask interrupts during probe") +Signed-off-by: Rafał Miłecki +Reviewed-by: Michal Kubiak +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/broadcom/bgmac.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1492,8 +1492,6 @@ int bgmac_enet_probe(struct bgmac *bgmac + + bgmac->in_init = true; + +- bgmac_chip_intrs_off(bgmac); +- + net_dev->irq = bgmac->irq; + SET_NETDEV_DEV(net_dev, bgmac->dev); + dev_set_drvdata(bgmac->dev, bgmac); +@@ -1511,6 +1509,8 @@ int bgmac_enet_probe(struct bgmac *bgmac + */ + bgmac_clk_enable(bgmac, 0); + ++ bgmac_chip_intrs_off(bgmac); ++ + /* This seems to be fixing IRQ by assigning OOB #6 to the core */ + if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) { + if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6) From a4792d79e899b28cefdb6d54c43cf0c13a9646e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 11 Jul 2023 10:30:08 +0200 Subject: [PATCH 04/17] bcm53xx: backport DT changes from v6.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Rafał Miłecki (cherry picked from commit 8674b41c0d84f09e14bf8ebe08e1d6dc6ac5fa64) --- .../bcm53xx/base-files/etc/board.d/02_network | 2 +- .../base-files/lib/upgrade/platform.sh | 12 +- ...-Add-devicetree-for-D-Link-DWL-8610A.patch | 2 +- ...-Add-devicetree-for-D-Link-DIR-890L.patch} | 0 ...Correct-description-of-TP-Link-part.patch} | 0 ...m-align-LED-node-names-with-dtschema.patch | 1700 +++++++++++++++++ ...-Relicense-Rafa-s-code-to-the-GPL-2..patch | 487 +++++ ...-Relicense-Florian-s-code-to-the-GPL.patch | 136 ++ ...X-Drop-clock-names-from-the-SPI-node.patch | 32 + ...-Relicense-Hauke-s-code-to-the-GPL-2.patch | 249 +++ ...-Relicense-AXI-interrupts-code-to-th.patch | 203 ++ ...-Specify-MAC-addresses-on-Luxul-devi.patch | 336 ++++ ...-Use-updated-device-compatible-strin.patch | 90 + ...-Use-updated-spi-gpio-binding-proper.patch | 82 + ...-dts-BCM5301X-Drop-invalid-usb-cells.patch | 54 + ...-Drop-invalid-properties-from-Meraki.patch | 31 + ...-Relicense-Christian-s-code-to-the-G.patch | 106 + ...-Describe-switch-ports-in-the-main-D.patch | 838 ++++++++ ...-MR26-MR32-remove-bogus-nand-ecc-alg.patch | 63 + ...-MR32-remove-partition-index-numbers.patch | 54 + ...BCM5301X-fix-duplex-full-full-duplex.patch | 44 + ...-Add-Netgear-R8000-WiFi-regulator-ma.patch | 61 + ...M5301X-Add-cells-sizes-to-PCIe-nodes.patch | 59 + ... 080-v6.2-bcma-support-SPROM-rev-11.patch} | 0 ...-Specify-switch-ports-for-remaining-.patch | 2 +- 25 files changed, 4634 insertions(+), 9 deletions(-) rename target/linux/bcm53xx/patches-5.15/{035-v6.2-0001-ARM-dts-bcm47094-Add-devicetree-for-D-Link-DIR-890L.patch => 035-v6.2-0002-ARM-dts-bcm47094-Add-devicetree-for-D-Link-DIR-890L.patch} (100%) rename target/linux/bcm53xx/patches-5.15/{035-v6.2-0001-ARM-dts-BCM5301X-Correct-description-of-TP-Link-part.patch => 035-v6.2-0003-ARM-dts-BCM5301X-Correct-description-of-TP-Link-part.patch} (100%) create mode 100644 target/linux/bcm53xx/patches-5.15/035-v6.2-0004-ARM-dts-broadcom-align-LED-node-names-with-dtschema.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0001-ARM-dts-BCM5301X-Relicense-Rafa-s-code-to-the-GPL-2..patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0002-ARM-dts-BCM5301X-Relicense-Florian-s-code-to-the-GPL.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0003-ARM-dts-BCM5301X-Drop-clock-names-from-the-SPI-node.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0004-ARM-dts-BCM5301X-Relicense-Hauke-s-code-to-the-GPL-2.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0005-ARM-dts-BCM5301X-Relicense-AXI-interrupts-code-to-th.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0006-ARM-dts-BCM5301X-Specify-MAC-addresses-on-Luxul-devi.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0007-ARM-dts-BCM5301X-Use-updated-device-compatible-strin.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0008-ARM-dts-BCM5301X-Use-updated-spi-gpio-binding-proper.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0009-ARM-dts-BCM5301X-Drop-invalid-usb-cells.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0010-ARM-dts-BCM5301X-Drop-invalid-properties-from-Meraki.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0011-ARM-dts-BCM5301X-Relicense-Christian-s-code-to-the-G.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0012-ARM-dts-BCM5301X-Describe-switch-ports-in-the-main-D.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0013-ARM-dts-BCM5301X-MR26-MR32-remove-bogus-nand-ecc-alg.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0014-ARM-dts-BCM5301X-MR32-remove-partition-index-numbers.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0015-ARM-dts-BCM5301X-fix-duplex-full-full-duplex.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0016-ARM-dts-BCM5301X-Add-Netgear-R8000-WiFi-regulator-ma.patch create mode 100644 target/linux/bcm53xx/patches-5.15/036-v6.5-0017-ARM-dts-BCM5301X-Add-cells-sizes-to-PCIe-nodes.patch rename target/linux/bcm53xx/patches-5.15/{036-v6.2-bcma-support-SPROM-rev-11.patch => 080-v6.2-bcma-support-SPROM-rev-11.patch} (100%) diff --git a/target/linux/bcm53xx/base-files/etc/board.d/02_network b/target/linux/bcm53xx/base-files/etc/board.d/02_network index 6bec600540..13e7311e79 100644 --- a/target/linux/bcm53xx/base-files/etc/board.d/02_network +++ b/target/linux/bcm53xx/base-files/etc/board.d/02_network @@ -57,7 +57,7 @@ bcm53xx_setup_macs() etXmacaddr=$(nvram get et2macaddr) offset=1 ;; - luxul,xwr-3100v1 | \ + luxul,xwr-3100-v1 | \ luxul,xwr-3150-v1) etXmacaddr=$(nvram get et0macaddr) offset=5 diff --git a/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh b/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh index 3ebde77d3f..d9dc497cda 100644 --- a/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh +++ b/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh @@ -39,18 +39,18 @@ platform_expected_image() { "dlink,dir-885l") echo "seamaseal wrgac42_dlink.2015_dir885l"; return;; "luxul,abr-4500-v1") echo "lxl ABR-4500"; return;; "luxul,xap-810-v1") echo "lxl XAP-810"; return;; - "luxul,xap-1410v1") echo "lxl XAP-1410"; return;; + "luxul,xap-1410-v1") echo "lxl XAP-1410"; return;; "luxul,xap-1440-v1") echo "lxl XAP-1440"; return;; - "luxul,xap-1510v1") echo "lxl XAP-1510"; return;; + "luxul,xap-1510-v1") echo "lxl XAP-1510"; return;; "luxul,xap-1610-v1") echo "lxl XAP-1610"; return;; "luxul,xbr-4500-v1") echo "lxl XBR-4500"; return;; "luxul,xwc-1000") echo "lxl XWC-1000"; return;; "luxul,xwc-2000-v1") echo "lxl XWC-2000"; return;; - "luxul,xwr-1200v1") echo "lxl XWR-1200"; return;; - "luxul,xwr-3100v1") echo "lxl XWR-3100"; return;; + "luxul,xwr-1200-v1") echo "lxl XWR-1200"; return;; + "luxul,xwr-3100-v1") echo "lxl XWR-3100"; return;; "luxul,xwr-3150-v1") echo "lxl XWR-3150"; return;; - "netgear,r6250v1") echo "chk U12H245T00_NETGEAR"; return;; - "netgear,r6300v2") echo "chk U12H240T00_NETGEAR"; return;; + "netgear,r6250-v1") echo "chk U12H245T00_NETGEAR"; return;; + "netgear,r6300-v2") echo "chk U12H240T00_NETGEAR"; return;; "netgear,r7000") echo "chk U12H270T00_NETGEAR"; return;; "netgear,r7900") echo "chk U12H315T30_NETGEAR"; return;; "netgear,r8000") echo "chk U12H315T00_NETGEAR"; return;; diff --git a/target/linux/bcm53xx/patches-5.15/035-v6.2-0001-ARM-dts-bcm53016-Add-devicetree-for-D-Link-DWL-8610A.patch b/target/linux/bcm53xx/patches-5.15/035-v6.2-0001-ARM-dts-bcm53016-Add-devicetree-for-D-Link-DWL-8610A.patch index b7528e9f71..206726f5f6 100644 --- a/target/linux/bcm53xx/patches-5.15/035-v6.2-0001-ARM-dts-bcm53016-Add-devicetree-for-D-Link-DWL-8610A.patch +++ b/target/linux/bcm53xx/patches-5.15/035-v6.2-0001-ARM-dts-bcm53016-Add-devicetree-for-D-Link-DWL-8610A.patch @@ -21,7 +21,7 @@ Signed-off-by: Florian Fainelli --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile -@@ -132,6 +132,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ +@@ -131,6 +131,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm47094-netgear-r8500.dtb \ bcm47094-phicomm-k3.dtb \ bcm53015-meraki-mr26.dtb \ diff --git a/target/linux/bcm53xx/patches-5.15/035-v6.2-0001-ARM-dts-bcm47094-Add-devicetree-for-D-Link-DIR-890L.patch b/target/linux/bcm53xx/patches-5.15/035-v6.2-0002-ARM-dts-bcm47094-Add-devicetree-for-D-Link-DIR-890L.patch similarity index 100% rename from target/linux/bcm53xx/patches-5.15/035-v6.2-0001-ARM-dts-bcm47094-Add-devicetree-for-D-Link-DIR-890L.patch rename to target/linux/bcm53xx/patches-5.15/035-v6.2-0002-ARM-dts-bcm47094-Add-devicetree-for-D-Link-DIR-890L.patch diff --git a/target/linux/bcm53xx/patches-5.15/035-v6.2-0001-ARM-dts-BCM5301X-Correct-description-of-TP-Link-part.patch b/target/linux/bcm53xx/patches-5.15/035-v6.2-0003-ARM-dts-BCM5301X-Correct-description-of-TP-Link-part.patch similarity index 100% rename from target/linux/bcm53xx/patches-5.15/035-v6.2-0001-ARM-dts-BCM5301X-Correct-description-of-TP-Link-part.patch rename to target/linux/bcm53xx/patches-5.15/035-v6.2-0003-ARM-dts-BCM5301X-Correct-description-of-TP-Link-part.patch diff --git a/target/linux/bcm53xx/patches-5.15/035-v6.2-0004-ARM-dts-broadcom-align-LED-node-names-with-dtschema.patch b/target/linux/bcm53xx/patches-5.15/035-v6.2-0004-ARM-dts-broadcom-align-LED-node-names-with-dtschema.patch new file mode 100644 index 0000000000..d6bf49d0cd --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/035-v6.2-0004-ARM-dts-broadcom-align-LED-node-names-with-dtschema.patch @@ -0,0 +1,1700 @@ +From af84101e3f2258a303fa2461ebec0878ce23ea10 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Fri, 25 Nov 2022 15:41:27 +0100 +Subject: [PATCH] ARM: dts: broadcom: align LED node names with dtschema + +The node names should be generic and DT schema expects certain pattern: + + bcm4708-asus-rt-ac68u.dtb: leds: 'logo', 'power', 'usb2', 'usb3' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' + +Signed-off-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20221125144128.477059-1-krzysztof.kozlowski@linaro.org +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 15 +++++----- + arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 8 +++--- + .../bcm4708-buffalo-wzr-1166dhp-common.dtsi | 16 +++++------ + .../boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 16 +++++------ + arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 6 ++-- + arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 2 +- + arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 10 +++---- + .../arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 10 +++---- + arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 22 +++++++-------- + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 10 +++---- + .../boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 14 +++++----- + .../boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 16 +++++------ + arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 6 ++-- + arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 20 ++++++------- + .../boot/dts/bcm47081-tplink-archer-c5-v2.dts | 18 ++++++------ + arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 6 ++-- + .../boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 18 ++++++------ + arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 16 +++++------ + arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 22 +++++++-------- + .../boot/dts/bcm4709-tplink-archer-c9-v1.dts | 18 ++++++------ + arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 12 ++++---- + arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 14 +++++----- + arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts | 16 +++++------ + .../boot/dts/bcm47094-linksys-panamera.dts | 28 +++++++++---------- + arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 4 +-- + arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 6 ++-- + arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 4 +-- + arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 2 +- + arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 20 ++++++------- + .../boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 10 +++---- + arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 14 +++++----- + arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts | 4 +-- + arch/arm/boot/dts/bcm47189-luxul-xap-810.dts | 10 +++---- + arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 14 +++++----- + .../boot/dts/bcm53016-dlink-dwl-8610ap.dts | 8 +++--- + arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 6 ++-- + arch/arm/boot/dts/bcm947189acdbmr.dts | 6 ++-- + 37 files changed, 223 insertions(+), 224 deletions(-) + +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +@@ -28,40 +28,39 @@ + leds { + compatible = "gpio-leds"; + +- usb3 { ++ led-usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + +- wan { ++ led-wan { + label = "bcm53xx:blue:wan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + +- lan { ++ led-lan { + label = "bcm53xx:blue:lan"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + +- power { ++ led-power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- all { ++ led-all { + label = "bcm53xx:blue:all"; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + +- +- usb2 { ++ led-usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +@@ -28,24 +28,24 @@ + leds { + compatible = "gpio-leds"; + +- usb2 { ++ led-usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + +- power { ++ led-power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- logo { ++ led-logo { + label = "bcm53xx:white:logo"; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- usb3 { ++ led-usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi +@@ -37,7 +37,7 @@ + leds { + compatible = "gpio-leds"; + +- usb { ++ led-usb { + /* label = "bcm53xx:blue:usb"; */ + function = LED_FUNCTION_USB; + color = ; +@@ -48,14 +48,14 @@ + linux,default-trigger = "usbport"; + }; + +- power0 { ++ led-power0 { + /* label = "bcm53xx:red:power"; */ + function = LED_FUNCTION_FAULT; + color = ; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; + }; + +- power1 { ++ led-power1 { + /* label = "bcm53xx:white:power"; */ + function = LED_FUNCTION_POWER; + color = ; +@@ -63,7 +63,7 @@ + linux,default-trigger = "default-on"; + }; + +- router0 { ++ led-router0 { + /* label = "bcm53xx:blue:router"; */ + function = LED_FUNCTION_STATUS; + color = ; +@@ -71,14 +71,14 @@ + linux,default-trigger = "default-on"; + }; + +- router1 { ++ led-router1 { + /* label = "bcm53xx:amber:router"; */ + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + }; + +- wan { ++ led-wan { + /* label = "bcm53xx:blue:wan"; */ + function = LED_FUNCTION_WAN; + color = ; +@@ -86,14 +86,14 @@ + linux,default-trigger = "default-on"; + }; + +- wireless0 { ++ led-wireless0 { + /* label = "bcm53xx:blue:wireless"; */ + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; + }; + +- wireless1 { ++ led-wireless1 { + /* label = "bcm53xx:amber:wireless"; */ + function = LED_FUNCTION_WLAN; + color = ; +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -49,7 +49,7 @@ + leds { + compatible = "gpio-leds"; + +- usb { ++ led-usb { + label = "bcm53xx:blue:usb"; + gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, +@@ -58,40 +58,40 @@ + linux,default-trigger = "usbport"; + }; + +- power0 { ++ led-power0 { + label = "bcm53xx:red:power"; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; + }; + +- power1 { ++ led-power1 { + label = "bcm53xx:white:power"; + gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- router0 { ++ led-router0 { + label = "bcm53xx:blue:router"; + gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- router1 { ++ led-router1 { + label = "bcm53xx:amber:router"; + gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + }; + +- wan { ++ led-wan { + label = "bcm53xx:blue:wan"; + gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- wireless0 { ++ led-wireless0 { + label = "bcm53xx:blue:wireless"; + gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; + }; + +- wireless1 { ++ led-wireless1 { + label = "bcm53xx:amber:wireless"; + gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; + }; +--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts ++++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +@@ -23,19 +23,19 @@ + leds { + compatible = "gpio-leds"; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + +- status { ++ led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; +--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts ++++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +@@ -42,7 +42,7 @@ + leds { + compatible = "gpio-leds"; + +- status { ++ led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -29,24 +29,24 @@ + leds { + compatible = "gpio-leds"; + +- logo { ++ led-logo { + label = "bcm53xx:white:logo"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- power0 { ++ led-power0 { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- power1 { ++ led-power1 { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + +- usb { ++ led-usb { + label = "bcm53xx:blue:usb"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, +@@ -54,7 +54,7 @@ + linux,default-trigger = "usbport"; + }; + +- wireless { ++ led-wireless { + label = "bcm53xx:blue:wireless"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +@@ -28,29 +28,29 @@ + leds { + compatible = "gpio-leds"; + +- logo { ++ led-logo { + label = "bcm53xx:white:logo"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- power0 { ++ led-power0 { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + +- power1 { ++ led-power1 { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- usb { ++ led-usb { + label = "bcm53xx:blue:usb"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + }; + +- wireless { ++ led-wireless { + label = "bcm53xx:blue:wireless"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts ++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +@@ -28,64 +28,64 @@ + leds { + compatible = "gpio-leds"; + +- power-white { ++ led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- power-amber { ++ led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; + }; + +- usb2 { ++ led-usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + +- usb3-white { ++ led-usb3-white { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + trigger-sources = <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + +- usb3-green { ++ led-usb3-green { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; + }; + +- wps { ++ led-wps { + label = "bcm53xx:white:wps"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + }; + +- status-red { ++ led-status-red { + label = "bcm53xx:red:status"; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + }; + +- status-green { ++ led-status-green { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; + }; + +- status-blue { ++ led-status-blue { + label = "bcm53xx:blue:status"; + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; + }; + +- wan-white { ++ led-wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + +- wan-red { ++ led-wan-red { + label = "bcm53xx:red:wan"; + gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; + }; +--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts ++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +@@ -28,30 +28,30 @@ + leds { + compatible = "gpio-leds"; + +- power { ++ led-power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- usb2 { ++ led-usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + +- wan { ++ led-wan { + label = "bcm53xx:blue:wan"; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- lan { ++ led-lan { + label = "bcm53xx:blue:lan"; + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- usb3 { ++ led-usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +@@ -49,40 +49,40 @@ + leds { + compatible = "gpio-leds"; + +- power0 { ++ led-power0 { + label = "bcm53xx:green:power"; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- power1 { ++ led-power1 { + label = "bcm53xx:red:power"; + gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; + }; + +- router0 { ++ led-router0 { + label = "bcm53xx:green:router"; + gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- router1 { ++ led-router1 { + label = "bcm53xx:amber:router"; + gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + }; + +- wan { ++ led-wan { + label = "bcm53xx:green:wan"; + gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- wireless0 { ++ led-wireless0 { + label = "bcm53xx:green:wireless"; + gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; + }; + +- wireless1 { ++ led-wireless1 { + label = "bcm53xx:amber:wireless"; + gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; + }; +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +@@ -49,45 +49,45 @@ + leds { + compatible = "gpio-leds"; + +- usb { ++ led-usb { + label = "bcm53xx:green:usb"; + gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; + }; + +- power0 { ++ led-power0 { + label = "bcm53xx:green:power"; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- power1 { ++ led-power1 { + label = "bcm53xx:red:power"; + gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; + }; + +- router0 { ++ led-router0 { + label = "bcm53xx:green:router"; + gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- router1 { ++ led-router1 { + label = "bcm53xx:amber:router"; + gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + }; + +- wan { ++ led-wan { + label = "bcm53xx:green:wan"; + gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- wireless0 { ++ led-wireless0 { + label = "bcm53xx:green:wireless"; + gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; + }; + +- wireless1 { ++ led-wireless1 { + label = "bcm53xx:amber:wireless"; + gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; + }; +--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts ++++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +@@ -23,19 +23,19 @@ + leds { + compatible = "gpio-leds"; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + +- status { ++ led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; +--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts ++++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +@@ -29,62 +29,62 @@ + leds { + compatible = "gpio-leds"; + +- power { ++ led-power { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- lan3 { ++ led-lan3 { + label = "bcm53xx:green:lan3"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + +- lan4 { ++ led-lan4 { + label = "bcm53xx:green:lan4"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + +- wan { ++ led-wan { + label = "bcm53xx:green:wan"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + +- lan2 { ++ led-lan2 { + label = "bcm53xx:green:lan2"; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + +- usb { ++ led-usb { + label = "bcm53xx:green:usb"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + +- status { ++ led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:green:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:green:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + +- lan1 { ++ led-lan1 { + label = "bcm53xx:green:lan1"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; +--- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts ++++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +@@ -23,50 +23,50 @@ + leds { + compatible = "gpio-leds"; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:green:2ghz"; + gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; + }; + +- lan { ++ led-lan { + label = "bcm53xx:green:lan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + }; + +- usb2-port1 { ++ led-usb2-port1 { + label = "bcm53xx:green:usb2-port1"; + gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; + }; + +- power { ++ led-power { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- wan-green { ++ led-wan-green { + label = "bcm53xx:green:wan"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + +- wps { ++ led-wps { + label = "bcm53xx:green:wps"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + }; + +- wan-amber { ++ led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + }; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:green:5ghz"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + +- usb2-port2 { ++ led-usb2-port2 { + label = "bcm53xx:green:usb2-port2"; + gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port2>, <&ehci_port2>; +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -28,18 +28,18 @@ + leds { + compatible = "gpio-leds"; + +- wps { ++ led-wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + +- power { ++ led-power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- wan { ++ led-wan { + label = "bcm53xx:red:wan"; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -28,48 +28,48 @@ + leds { + compatible = "gpio-leds"; + +- usb { ++ led-usb { + label = "bcm53xx:green:usb"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + }; + +- power-amber { ++ led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + +- power-white { ++ led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- router-amber { ++ led-router-amber { + label = "bcm53xx:amber:router"; + gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + }; + +- router-white { ++ led-router-white { + label = "bcm53xx:white:router"; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + }; + +- wan-amber { ++ led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; + }; + +- wan-white { ++ led-wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; + }; + +- wireless-amber { ++ led-wireless-amber { + label = "bcm53xx:amber:wireless"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + }; + +- wireless-white { ++ led-wireless-white { + label = "bcm53xx:white:wireless"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; +--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -28,43 +28,43 @@ + leds { + compatible = "gpio-leds"; + +- power-white { ++ led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- power-amber { ++ led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:white:5ghz"; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + +- wps { ++ led-wps { + label = "bcm53xx:white:wps"; + gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; + }; + +- wireless { ++ led-wireless { + label = "bcm53xx:white:wireless"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + }; + +- usb3 { ++ led-usb3 { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + +- usb2 { ++ led-usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -39,59 +39,59 @@ + leds { + compatible = "gpio-leds"; + +- power-white { ++ led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- power-amber { ++ led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + +- wan-white { ++ led-wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- wan-amber { ++ led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; + }; + +- 5ghz-1 { ++ led-5ghz-1 { + label = "bcm53xx:white:5ghz-1"; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + +- wireless { ++ led-wireless { + label = "bcm53xx:white:wireless"; + gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; + }; + +- wps { ++ led-wps { + label = "bcm53xx:white:wps"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + }; + +- 5ghz-2 { ++ led-5ghz-2 { + label = "bcm53xx:white:5ghz-2"; + gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; + }; + +- usb3 { ++ led-usb3 { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + +- usb2 { ++ led-usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts ++++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts +@@ -23,27 +23,27 @@ + leds { + compatible = "gpio-leds"; + +- lan { ++ led-lan { + label = "bcm53xx:blue:lan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + }; + +- wps { ++ led-wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + }; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + +- usb3 { ++ led-usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, +@@ -51,24 +51,24 @@ + linux,default-trigger = "usbport"; + }; + +- usb2 { ++ led-usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + +- wan-blue { ++ led-wan-blue { + label = "bcm53xx:blue:wan"; + gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; + }; + +- wan-amber { ++ led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + }; + +- power { ++ led-power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; +--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts ++++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +@@ -33,37 +33,37 @@ + leds { + compatible = "gpio-leds"; + +- power { ++ led-power { + label = "white:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- wan-red { ++ led-wan-red { + label = "red:wan"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + +- lan { ++ led-lan { + label = "white:lan"; + gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; + }; + +- usb2 { ++ led-usb2 { + label = "white:usb2"; + gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; + trigger-sources = <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + +- usb3 { ++ led-usb3 { + label = "white:usb3"; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + trigger-sources = <&ehci_port1>, <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + +- wps { ++ led-wps { + label = "white:wps"; + gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts ++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +@@ -43,28 +43,28 @@ + leds { + compatible = "gpio-leds"; + +- power-white { ++ led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- wan-white { ++ led-wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + +- power-amber { ++ led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + +- wan-amber { ++ led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + +- usb3-white { ++ led-usb3-white { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, +@@ -72,12 +72,12 @@ + linux,default-trigger = "usbport"; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:white:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts ++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts +@@ -41,47 +41,47 @@ + */ + compatible = "gpio-leds"; + +- power-white { ++ led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- wan-white { ++ led-wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + +- power-amber { ++ led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + +- wan-amber { ++ led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + +- usb3-white { ++ led-usb3-white { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + +- usb2-white { ++ led-usb2-white { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:white:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts ++++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +@@ -52,19 +52,19 @@ + leds { + compatible = "gpio-leds"; + +- wps { ++ led-wps { + label = "bcm53xx:white:wps"; + gpios = <&chipcommon 22 GPIO_ACTIVE_LOW>; + }; + +- usb2 { ++ led-usb2 { + label = "bcm53xx:green:usb2"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + +- usb3 { ++ led-usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, +@@ -72,58 +72,58 @@ + linux,default-trigger = "usbport"; + }; + +- power { ++ led-power { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + +- wifi-disabled { ++ led-wifi-disabled { + label = "bcm53xx:amber:wifi-disabled"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + +- wifi-enabled { ++ led-wifi-enabled { + label = "bcm53xx:white:wifi-enabled"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + +- bluebar1 { ++ led-bluebar1 { + label = "bcm53xx:white:bluebar1"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + }; + +- bluebar2 { ++ led-bluebar2 { + label = "bcm53xx:white:bluebar2"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + +- bluebar3 { ++ led-bluebar3 { + label = "bcm53xx:white:bluebar3"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + +- bluebar4 { ++ led-bluebar4 { + label = "bcm53xx:white:bluebar4"; + gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>; + }; + +- bluebar5 { ++ led-bluebar5 { + label = "bcm53xx:white:bluebar5"; + gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; + }; + +- bluebar6 { ++ led-bluebar6 { + label = "bcm53xx:white:bluebar6"; + gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; + }; + +- bluebar7 { ++ led-bluebar7 { + label = "bcm53xx:white:bluebar7"; + gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>; + }; + +- bluebar8 { ++ led-bluebar8 { + label = "bcm53xx:white:bluebar8"; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + }; +--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +@@ -30,13 +30,13 @@ + leds { + compatible = "gpio-leds"; + +- status { ++ led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + +- usb3 { ++ led-usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, +--- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +@@ -23,18 +23,18 @@ + leds { + compatible = "gpio-leds"; + +- status { ++ led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +@@ -30,13 +30,13 @@ + leds { + compatible = "gpio-leds"; + +- status { ++ led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + +- usb3 { ++ led-usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, +--- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +@@ -25,7 +25,7 @@ + leds { + compatible = "gpio-leds"; + +- status { ++ led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; +--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +@@ -30,38 +30,38 @@ + leds { + compatible = "gpio-leds"; + +- power { ++ led-power { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- lan3 { ++ led-lan3 { + label = "bcm53xx:green:lan3"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + +- lan4 { ++ led-lan4 { + label = "bcm53xx:green:lan4"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + +- wan { ++ led-wan { + label = "bcm53xx:green:wan"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + +- lan1 { ++ led-lan1 { + label = "bcm53xx:green:lan1"; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + +- lan2 { ++ led-lan2 { + label = "bcm53xx:green:lan2"; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + +- usb3 { ++ led-usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, +@@ -69,18 +69,18 @@ + linux,default-trigger = "usbport"; + }; + +- status { ++ led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:green:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:green:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +@@ -33,13 +33,13 @@ + leds { + compatible = "gpio-leds"; + +- power { ++ led-power { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- usb3 { ++ led-usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, +@@ -47,18 +47,18 @@ + linux,default-trigger = "usbport"; + }; + +- status { ++ led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:green:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:green:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts ++++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts +@@ -25,38 +25,38 @@ + leds { + compatible = "gpio-leds"; + +- power0 { ++ led-power0 { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + +- power1 { ++ led-power1 { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + +- 5ghz-1 { ++ led-5ghz-1 { + label = "bcm53xx:white:5ghz-1"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + +- 5ghz-2 { ++ led-5ghz-2 { + label = "bcm53xx:white:5ghz-2"; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + +- usb2 { ++ led-usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + +- usb3 { ++ led-usb3 { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + }; +--- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts ++++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +@@ -23,13 +23,13 @@ + leds { + compatible = "gpio-leds"; + +- wlan { ++ led-wlan { + label = "bcm53xx:blue:wlan"; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + +- system { ++ led-system { + label = "bcm53xx:green:system"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; +--- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts ++++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +@@ -20,26 +20,26 @@ + reg = <0x00000000 0x08000000>; + }; + +- leds { ++ leds-0 { + compatible = "gpio-leds"; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + +- system { ++ led-system { + label = "bcm53xx:green:system"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + }; + +- pcie0_leds { ++ leds-1 { + compatible = "gpio-leds"; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; +--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts ++++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +@@ -20,37 +20,37 @@ + reg = <0x00000000 0x08000000>; + }; + +- leds { ++ leds-0 { + compatible = "gpio-leds"; + +- usb { ++ led-usb { + label = "bcm53xx:blue:usb"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; + }; + +- wps { ++ led-wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; + }; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + }; + +- system { ++ led-system { + label = "bcm53xx:blue:system"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + }; + +- pcie0_leds { ++ leds-1 { + compatible = "gpio-leds"; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; + }; +--- a/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts ++++ b/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts +@@ -20,14 +20,14 @@ + leds { + compatible = "gpio-leds"; + +- power { ++ led-power { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + +- diag { ++ led-diag { + /* Actually "diag" unclear what this means */ + function = LED_FUNCTION_INDICATOR; + color = ; +@@ -36,13 +36,13 @@ + linux,default-trigger = "heartbeat"; + }; + +- wlan-2g { ++ led-wlan-2g { + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + +- wlan-5g { ++ led-wlan-5g { + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; +--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts ++++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +@@ -58,7 +58,7 @@ + pwm-leds { + compatible = "pwm-leds"; + +- red { ++ led-0 { + /* SYS-LED 1 - Tricolor */ + function = LED_FUNCTION_INDICATOR; + color = ; +@@ -66,7 +66,7 @@ + max-brightness = <255>; + }; + +- green { ++ led-1 { + /* SYS-LED 1 - Tricolor */ + function = LED_FUNCTION_POWER; + color = ; +@@ -74,7 +74,7 @@ + max-brightness = <255>; + }; + +- blue { ++ led-2 { + /* SYS-LED 1 - Tricolor */ + function = LED_FUNCTION_INDICATOR; + color = ; +--- a/arch/arm/boot/dts/bcm947189acdbmr.dts ++++ b/arch/arm/boot/dts/bcm947189acdbmr.dts +@@ -25,17 +25,17 @@ + leds { + compatible = "gpio-leds"; + +- wps { ++ led-wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; + }; + +- 5ghz { ++ led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + }; + +- 2ghz { ++ led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0001-ARM-dts-BCM5301X-Relicense-Rafa-s-code-to-the-GPL-2..patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0001-ARM-dts-BCM5301X-Relicense-Rafa-s-code-to-the-GPL-2..patch new file mode 100644 index 0000000000..9c6f0b8e53 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0001-ARM-dts-BCM5301X-Relicense-Rafa-s-code-to-the-GPL-2..patch @@ -0,0 +1,487 @@ +From 915fac07f053418d0ab9075af64da2872ca8a7f8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 3 May 2023 14:16:10 +0200 +Subject: [PATCH] =?UTF-8?q?ARM:=20dts:=20BCM5301X:=20Relicense=20Rafa?= + =?UTF-8?q?=C5=82's=20code=20to=20the=20GPL=202.0+=20/=20MIT?= +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +All BCM5301X device DTS files use dual licensing. Try the same for SoC. +Introduce a new .dtsi file with a proper SPDX tag. + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20230503121611.1629-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + MAINTAINERS | 1 + + arch/arm/boot/dts/bcm-ns.dtsi | 202 ++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/bcm5301x.dtsi | 192 +----------------------------- + 3 files changed, 205 insertions(+), 190 deletions(-) + create mode 100644 arch/arm/boot/dts/bcm-ns.dtsi + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -3579,6 +3579,7 @@ M: Rafał Miłecki + M: bcm-kernel-feedback-list@broadcom.com + L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) + S: Maintained ++F: arch/arm/boot/dts/bcm-ns.dtsi + F: arch/arm/boot/dts/bcm470* + F: arch/arm/boot/dts/bcm5301* + F: arch/arm/boot/dts/bcm953012* +--- /dev/null ++++ b/arch/arm/boot/dts/bcm-ns.dtsi +@@ -0,0 +1,202 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++#include ++#include ++#include ++#include ++#include ++ ++/ { ++ axi@18000000 { ++ compatible = "brcm,bus-axi"; ++ reg = <0x18000000 0x1000>; ++ ranges = <0x00000000 0x18000000 0x00100000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ chipcommon: chipcommon@0 { ++ reg = <0x00000000 0x1000>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ pcie0: pcie@12000 { ++ reg = <0x00012000 0x1000>; ++ }; ++ ++ pcie1: pcie@13000 { ++ reg = <0x00013000 0x1000>; ++ }; ++ ++ usb2: usb2@21000 { ++ reg = <0x00021000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ interrupt-parent = <&gic>; ++ ++ ehci: usb@21000 { ++ #usb-cells = <0>; ++ ++ compatible = "generic-ehci"; ++ reg = <0x00021000 0x1000>; ++ interrupts = ; ++ phys = <&usb2_phy>; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ehci_port1: port@1 { ++ reg = <1>; ++ #trigger-source-cells = <0>; ++ }; ++ ++ ehci_port2: port@2 { ++ reg = <2>; ++ #trigger-source-cells = <0>; ++ }; ++ }; ++ ++ ohci: usb@22000 { ++ #usb-cells = <0>; ++ ++ compatible = "generic-ohci"; ++ reg = <0x00022000 0x1000>; ++ interrupts = ; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ohci_port1: port@1 { ++ reg = <1>; ++ #trigger-source-cells = <0>; ++ }; ++ ++ ohci_port2: port@2 { ++ reg = <2>; ++ #trigger-source-cells = <0>; ++ }; ++ }; ++ }; ++ ++ usb3: usb3@23000 { ++ reg = <0x00023000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ interrupt-parent = <&gic>; ++ ++ xhci: usb@23000 { ++ #usb-cells = <0>; ++ ++ compatible = "generic-xhci"; ++ reg = <0x00023000 0x1000>; ++ interrupts = ; ++ phys = <&usb3_phy>; ++ phy-names = "usb"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ xhci_port1: port@1 { ++ reg = <1>; ++ #trigger-source-cells = <0>; ++ }; ++ }; ++ }; ++ }; ++ ++ mdio: mdio@18003000 { ++ compatible = "brcm,iproc-mdio"; ++ reg = <0x18003000 0x8>; ++ #size-cells = <0>; ++ #address-cells = <1>; ++ }; ++ ++ dmu-bus@1800c000 { ++ compatible = "simple-bus"; ++ ranges = <0 0x1800c000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ cru-bus@100 { ++ compatible = "brcm,ns-cru", "simple-mfd"; ++ reg = <0x100 0x1a4>; ++ ranges; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ usb2_phy: phy@164 { ++ compatible = "brcm,ns-usb2-phy"; ++ reg = <0x164 0x4>; ++ brcm,syscon-clkset = <&cru_clkset>; ++ clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; ++ clock-names = "phy-ref-clk"; ++ #phy-cells = <0>; ++ }; ++ ++ cru_clkset: syscon@180 { ++ compatible = "brcm,cru-clkset", "syscon"; ++ reg = <0x180 0x4>; ++ }; ++ ++ pinctrl: pinctrl@1c0 { ++ compatible = "brcm,bcm4708-pinmux"; ++ reg = <0x1c0 0x24>; ++ reg-names = "cru_gpio_control"; ++ ++ spi-pins { ++ groups = "spi_grp"; ++ function = "spi"; ++ }; ++ ++ pinmux_i2c: i2c-pins { ++ groups = "i2c_grp"; ++ function = "i2c"; ++ }; ++ ++ pinmux_pwm: pwm-pins { ++ groups = "pwm0_grp", "pwm1_grp", ++ "pwm2_grp", "pwm3_grp"; ++ function = "pwm"; ++ }; ++ ++ pinmux_uart1: uart1-pins { ++ groups = "uart1_grp"; ++ function = "uart1"; ++ }; ++ }; ++ ++ thermal: thermal@2c0 { ++ compatible = "brcm,ns-thermal"; ++ reg = <0x2c0 0x10>; ++ #thermal-sensor-cells = <0>; ++ }; ++ }; ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <1000>; ++ coefficients = <(-556) 418000>; ++ thermal-sensors = <&thermal>; ++ ++ trips { ++ cpu-crit { ++ temperature = <125000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ }; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -8,11 +8,7 @@ + * Licensed under the GNU/GPL. See COPYING for details. + */ + +-#include +-#include +-#include +-#include +-#include ++#include "bcm-ns.dtsi" + + / { + #address-cells = <1>; +@@ -149,12 +145,6 @@ + }; + + axi@18000000 { +- compatible = "brcm,bus-axi"; +- reg = <0x18000000 0x1000>; +- ranges = <0x00000000 0x18000000 0x00100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = +@@ -228,108 +218,15 @@ + <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + +- chipcommon: chipcommon@0 { +- reg = <0x00000000 0x1000>; +- +- gpio-controller; +- #gpio-cells = <2>; ++ chipcommon@0 { + interrupt-controller; + #interrupt-cells = <2>; + }; + +- pcie0: pcie@12000 { +- reg = <0x00012000 0x1000>; +- }; +- +- pcie1: pcie@13000 { +- reg = <0x00013000 0x1000>; +- }; +- + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; + }; + +- usb2: usb2@21000 { +- reg = <0x00021000 0x1000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- interrupt-parent = <&gic>; +- +- ehci: usb@21000 { +- #usb-cells = <0>; +- +- compatible = "generic-ehci"; +- reg = <0x00021000 0x1000>; +- interrupts = ; +- phys = <&usb2_phy>; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ehci_port1: port@1 { +- reg = <1>; +- #trigger-source-cells = <0>; +- }; +- +- ehci_port2: port@2 { +- reg = <2>; +- #trigger-source-cells = <0>; +- }; +- }; +- +- ohci: usb@22000 { +- #usb-cells = <0>; +- +- compatible = "generic-ohci"; +- reg = <0x00022000 0x1000>; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- ohci_port1: port@1 { +- reg = <1>; +- #trigger-source-cells = <0>; +- }; +- +- ohci_port2: port@2 { +- reg = <2>; +- #trigger-source-cells = <0>; +- }; +- }; +- }; +- +- usb3: usb3@23000 { +- reg = <0x00023000 0x1000>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- interrupt-parent = <&gic>; +- +- xhci: usb@23000 { +- #usb-cells = <0>; +- +- compatible = "generic-xhci"; +- reg = <0x00023000 0x1000>; +- interrupts = ; +- phys = <&usb3_phy>; +- phy-names = "usb"; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- xhci_port1: port@1 { +- reg = <1>; +- #trigger-source-cells = <0>; +- }; +- }; +- }; +- + gmac0: ethernet@24000 { + reg = <0x24000 0x800>; + }; +@@ -355,13 +252,6 @@ + status = "disabled"; + }; + +- mdio: mdio@18003000 { +- compatible = "brcm,iproc-mdio"; +- reg = <0x18003000 0x8>; +- #size-cells = <0>; +- #address-cells = <1>; +- }; +- + mdio-mux@18003000 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio>; +@@ -409,18 +299,7 @@ + }; + + dmu-bus@1800c000 { +- compatible = "simple-bus"; +- ranges = <0 0x1800c000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- + cru-bus@100 { +- compatible = "brcm,ns-cru", "simple-mfd"; +- reg = <0x100 0x1a4>; +- ranges; +- #address-cells = <1>; +- #size-cells = <1>; +- + lcpll0: clock-controller@100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; +@@ -440,53 +319,6 @@ + "usbclk", "iprocfast", + "sata1", "sata2"; + }; +- +- usb2_phy: phy@164 { +- compatible = "brcm,ns-usb2-phy"; +- reg = <0x164 0x4>; +- brcm,syscon-clkset = <&cru_clkset>; +- clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; +- clock-names = "phy-ref-clk"; +- #phy-cells = <0>; +- }; +- +- cru_clkset: syscon@180 { +- compatible = "brcm,cru-clkset", "syscon"; +- reg = <0x180 0x4>; +- }; +- +- pinctrl: pinctrl@1c0 { +- compatible = "brcm,bcm4708-pinmux"; +- reg = <0x1c0 0x24>; +- reg-names = "cru_gpio_control"; +- +- spi-pins { +- groups = "spi_grp"; +- function = "spi"; +- }; +- +- pinmux_i2c: i2c-pins { +- groups = "i2c_grp"; +- function = "i2c"; +- }; +- +- pinmux_pwm: pwm-pins { +- groups = "pwm0_grp", "pwm1_grp", +- "pwm2_grp", "pwm3_grp"; +- function = "pwm"; +- }; +- +- pinmux_uart1: uart1-pins { +- groups = "uart1_grp"; +- function = "uart1"; +- }; +- }; +- +- thermal: thermal@2c0 { +- compatible = "brcm,ns-thermal"; +- reg = <0x2c0 0x10>; +- #thermal-sensor-cells = <0>; +- }; + }; + }; + +@@ -558,24 +390,4 @@ + }; + }; + }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <1000>; +- coefficients = <(-556) 418000>; +- thermal-sensors = <&thermal>; +- +- trips { +- cpu-crit { +- temperature = <125000>; +- hysteresis = <0>; +- type = "critical"; +- }; +- }; +- +- cooling-maps { +- }; +- }; +- }; + }; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0002-ARM-dts-BCM5301X-Relicense-Florian-s-code-to-the-GPL.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0002-ARM-dts-BCM5301X-Relicense-Florian-s-code-to-the-GPL.patch new file mode 100644 index 0000000000..b98f2daa67 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0002-ARM-dts-BCM5301X-Relicense-Florian-s-code-to-the-GPL.patch @@ -0,0 +1,136 @@ +From 916553449561c4f0b61c71b751b7bb583f5dddd4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 3 May 2023 14:16:11 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Relicense Florian's code to the GPL 2.0+ + / MIT +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +All BCM5301X device DTS files use dual licensing. Try the same for SoC. + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20230503121611.1629-2-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm-ns.dtsi | 36 ++++++++++++++++++++++++++++++ + arch/arm/boot/dts/bcm5301x.dtsi | 39 --------------------------------- + 2 files changed, 36 insertions(+), 39 deletions(-) + +--- a/arch/arm/boot/dts/bcm-ns.dtsi ++++ b/arch/arm/boot/dts/bcm-ns.dtsi +@@ -19,6 +19,8 @@ + + gpio-controller; + #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pcie0: pcie@12000 { +@@ -109,6 +111,22 @@ + }; + }; + }; ++ ++ gmac0: ethernet@24000 { ++ reg = <0x24000 0x800>; ++ }; ++ ++ gmac1: ethernet@25000 { ++ reg = <0x25000 0x800>; ++ }; ++ ++ gmac2: ethernet@26000 { ++ reg = <0x26000 0x800>; ++ }; ++ ++ gmac3: ethernet@27000 { ++ reg = <0x27000 0x800>; ++ }; + }; + + mdio: mdio@18003000 { +@@ -118,6 +136,24 @@ + #address-cells = <1>; + }; + ++ rng: rng@18004000 { ++ compatible = "brcm,bcm5301x-rng"; ++ reg = <0x18004000 0x14>; ++ }; ++ ++ srab: ethernet-switch@18007000 { ++ compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; ++ reg = <0x18007000 0x1000>; ++ ++ status = "disabled"; ++ ++ /* ports are defined in board DTS */ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ + dmu-bus@1800c000 { + compatible = "simple-bus"; + ranges = <0 0x1800c000 0x1000>; +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -218,30 +218,9 @@ + <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + +- chipcommon@0 { +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; + }; +- +- gmac0: ethernet@24000 { +- reg = <0x24000 0x800>; +- }; +- +- gmac1: ethernet@25000 { +- reg = <0x25000 0x800>; +- }; +- +- gmac2: ethernet@26000 { +- reg = <0x26000 0x800>; +- }; +- +- gmac3: ethernet@27000 { +- reg = <0x27000 0x800>; +- }; + }; + + pwm: pwm@18002000 { +@@ -322,24 +301,6 @@ + }; + }; + +- srab: ethernet-switch@18007000 { +- compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; +- reg = <0x18007000 0x1000>; +- +- status = "disabled"; +- +- /* ports are defined in board DTS */ +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- rng: rng@18004000 { +- compatible = "brcm,bcm5301x-rng"; +- reg = <0x18004000 0x14>; +- }; +- + nand_controller: nand-controller@18028000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; + reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0003-ARM-dts-BCM5301X-Drop-clock-names-from-the-SPI-node.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0003-ARM-dts-BCM5301X-Drop-clock-names-from-the-SPI-node.patch new file mode 100644 index 0000000000..4065db8366 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0003-ARM-dts-BCM5301X-Drop-clock-names-from-the-SPI-node.patch @@ -0,0 +1,32 @@ +From d3c8e2c5757153bbfad70019ec1decbca86f3def Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 3 May 2023 14:28:30 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Drop "clock-names" from the SPI node +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There is no such property in the SPI controller binding documentation. +Also Linux driver doesn't look for it. + +This fixes: +arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: spi@18029200: Unevaluated properties are not allowed ('clock-names' was unexpected) + From schema: Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20230503122830.3200-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm5301x.dtsi | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -335,7 +335,6 @@ + "spi_lr_session_done", + "spi_lr_overread"; + clocks = <&iprocmed>; +- clock-names = "iprocmed"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0004-ARM-dts-BCM5301X-Relicense-Hauke-s-code-to-the-GPL-2.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0004-ARM-dts-BCM5301X-Relicense-Hauke-s-code-to-the-GPL-2.patch new file mode 100644 index 0000000000..328748c8e0 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0004-ARM-dts-BCM5301X-Relicense-Hauke-s-code-to-the-GPL-2.patch @@ -0,0 +1,249 @@ +From b3b3cd885ed39cb4b38319a1c4fa4e41db6fee72 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 15 May 2023 17:19:20 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ / + MIT +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Move code added by Hauke to the bcm-ns.dtsi which uses dual licensing. +That syncs more Northstar code to be based on the same licensing schema. + +Signed-off-by: Rafał Miłecki +Cc: Hauke Mehrtens +Acked-by: Hauke Mehrtens +Link: https://lore.kernel.org/r/20230515151921.25021-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm-ns.dtsi | 90 +++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/bcm5301x.dtsi | 85 ------------------------------- + 2 files changed, 90 insertions(+), 85 deletions(-) + +--- a/arch/arm/boot/dts/bcm-ns.dtsi ++++ b/arch/arm/boot/dts/bcm-ns.dtsi +@@ -1,4 +1,7 @@ + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright 2013-2014 Hauke Mehrtens ++ */ + + #include + #include +@@ -7,6 +10,81 @@ + #include + + / { ++ interrupt-parent = <&gic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ chipcommon-a-bus@18000000 { ++ compatible = "simple-bus"; ++ ranges = <0x00000000 0x18000000 0x00001000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ uart0: serial@300 { ++ compatible = "ns16550"; ++ reg = <0x0300 0x100>; ++ interrupts = ; ++ clocks = <&iprocslow>; ++ status = "disabled"; ++ }; ++ ++ uart1: serial@400 { ++ compatible = "ns16550"; ++ reg = <0x0400 0x100>; ++ interrupts = ; ++ clocks = <&iprocslow>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinmux_uart1>; ++ status = "disabled"; ++ }; ++ }; ++ ++ mpcore-bus@19000000 { ++ compatible = "simple-bus"; ++ ranges = <0x00000000 0x19000000 0x00023000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ scu@20000 { ++ compatible = "arm,cortex-a9-scu"; ++ reg = <0x20000 0x100>; ++ }; ++ ++ timer@20200 { ++ compatible = "arm,cortex-a9-global-timer"; ++ reg = <0x20200 0x100>; ++ interrupts = ; ++ clocks = <&periph_clk>; ++ }; ++ ++ timer@20600 { ++ compatible = "arm,cortex-a9-twd-timer"; ++ reg = <0x20600 0x20>; ++ interrupts = ; ++ clocks = <&periph_clk>; ++ }; ++ ++ gic: interrupt-controller@21000 { ++ compatible = "arm,cortex-a9-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <0>; ++ interrupt-controller; ++ reg = <0x21000 0x1000>, ++ <0x20100 0x100>; ++ }; ++ ++ L2: cache-controller@22000 { ++ compatible = "arm,pl310-cache"; ++ reg = <0x22000 0x1000>; ++ cache-unified; ++ arm,shared-override; ++ prefetch-data = <1>; ++ prefetch-instr = <1>; ++ cache-level = <2>; ++ }; ++ }; ++ + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; +@@ -216,6 +294,18 @@ + }; + }; + ++ nand_controller: nand-controller@18028000 { ++ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; ++ reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; ++ reg-names = "nand", "iproc-idm", "iproc-ext"; ++ interrupts = ; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ brcm,nand-has-wp; ++ }; ++ + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -11,41 +11,7 @@ + #include "bcm-ns.dtsi" + + / { +- #address-cells = <1>; +- #size-cells = <1>; +- interrupt-parent = <&gic>; +- +- chipcommon-a-bus@18000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0x18000000 0x00001000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- uart0: serial@300 { +- compatible = "ns16550"; +- reg = <0x0300 0x100>; +- interrupts = ; +- clocks = <&iprocslow>; +- status = "disabled"; +- }; +- +- uart1: serial@400 { +- compatible = "ns16550"; +- reg = <0x0400 0x100>; +- interrupts = ; +- clocks = <&iprocslow>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinmux_uart1>; +- status = "disabled"; +- }; +- }; +- + mpcore-bus@19000000 { +- compatible = "simple-bus"; +- ranges = <0x00000000 0x19000000 0x00023000>; +- #address-cells = <1>; +- #size-cells = <1>; +- + a9pll: arm_clk@0 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; +@@ -53,26 +19,6 @@ + reg = <0x00000 0x1000>; + }; + +- scu@20000 { +- compatible = "arm,cortex-a9-scu"; +- reg = <0x20000 0x100>; +- }; +- +- timer@20200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x20200 0x100>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- +- timer@20600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x20600 0x20>; +- interrupts = ; +- clocks = <&periph_clk>; +- }; +- + watchdog@20620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x20620 0x20>; +@@ -80,25 +26,6 @@ + IRQ_TYPE_EDGE_RISING)>; + clocks = <&periph_clk>; + }; +- +- gic: interrupt-controller@21000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- interrupt-controller; +- reg = <0x21000 0x1000>, +- <0x20100 0x100>; +- }; +- +- L2: cache-controller@22000 { +- compatible = "arm,pl310-cache"; +- reg = <0x22000 0x1000>; +- cache-unified; +- arm,shared-override; +- prefetch-data = <1>; +- prefetch-instr = <1>; +- cache-level = <2>; +- }; + }; + + pmu { +@@ -301,18 +228,6 @@ + }; + }; + +- nand_controller: nand-controller@18028000 { +- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; +- reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; +- reg-names = "nand", "iproc-idm", "iproc-ext"; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- brcm,nand-has-wp; +- }; +- + spi@18029200 { + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; + reg = <0x18029200 0x184>, diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0005-ARM-dts-BCM5301X-Relicense-AXI-interrupts-code-to-th.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0005-ARM-dts-BCM5301X-Relicense-AXI-interrupts-code-to-th.patch new file mode 100644 index 0000000000..ef29266d0b --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0005-ARM-dts-BCM5301X-Relicense-AXI-interrupts-code-to-th.patch @@ -0,0 +1,203 @@ +From 3b3e35b279bee5e51580c648399e20323467f58c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 15 May 2023 17:19:21 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Relicense AXI interrupts code to the GPL + 2.0+ / MIT +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Those entries were added by: +1. Hauke in commits dec378827c4a ("ARM: BCM5301X: Add IRQs to Broadcom's + bus-axi in DTS file") and 1f80de6863ca ("ARM: BCM5301X: add IRQ + numbers for PCIe controller") +2. Florian in the commit 2cd0c0202f13 ("ARM: dts: BCM5301X: Add SRAB + interrupts") + +Move them to the bcm-ns.dtsi which uses dual licensing. That syncs more +Northstar code to be based on the same licensing schema. + +Signed-off-by: Rafał Miłecki +Cc: Hauke Mehrtens +Cc: Florian Fainelli +Acked-by: Hauke Mehrtens +Link: https://lore.kernel.org/r/20230515151921.25021-2-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm-ns.dtsi | 73 ++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/bcm5301x.dtsi | 75 --------------------------------- + 2 files changed, 73 insertions(+), 75 deletions(-) + +--- a/arch/arm/boot/dts/bcm-ns.dtsi ++++ b/arch/arm/boot/dts/bcm-ns.dtsi +@@ -92,6 +92,79 @@ + #address-cells = <1>; + #size-cells = <1>; + ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0x000fffff 0xffff>; ++ interrupt-map = ++ /* ChipCommon */ ++ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* Switch Register Access Block */ ++ <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* PCIe Controller 0 */ ++ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* PCIe Controller 1 */ ++ <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* PCIe Controller 2 */ ++ <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* USB 2.0 Controller */ ++ <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* USB 3.0 Controller */ ++ <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* Ethernet Controller 0 */ ++ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* Ethernet Controller 1 */ ++ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* Ethernet Controller 2 */ ++ <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* Ethernet Controller 3 */ ++ <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* NAND Controller */ ++ <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; ++ + chipcommon: chipcommon@0 { + reg = <0x00000000 0x1000>; + +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -3,8 +3,6 @@ + * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, + * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs + * +- * Copyright 2013-2014 Hauke Mehrtens +- * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +@@ -72,79 +70,6 @@ + }; + + axi@18000000 { +- #interrupt-cells = <1>; +- interrupt-map-mask = <0x000fffff 0xffff>; +- interrupt-map = +- /* ChipCommon */ +- <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Switch Register Access Block */ +- <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, +- +- /* PCIe Controller 0 */ +- <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, +- +- /* PCIe Controller 1 */ +- <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, +- +- /* PCIe Controller 2 */ +- <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, +- +- /* USB 2.0 Controller */ +- <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, +- +- /* USB 3.0 Controller */ +- <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 0 */ +- <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 1 */ +- <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 2 */ +- <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 3 */ +- <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, +- +- /* NAND Controller */ +- <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; +- + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; + }; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0006-ARM-dts-BCM5301X-Specify-MAC-addresses-on-Luxul-devi.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0006-ARM-dts-BCM5301X-Specify-MAC-addresses-on-Luxul-devi.patch new file mode 100644 index 0000000000..7d9b297191 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0006-ARM-dts-BCM5301X-Specify-MAC-addresses-on-Luxul-devi.patch @@ -0,0 +1,336 @@ +From dfa6570eb5ce2f24059caadbe2ed70034b5337bc Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 15 May 2023 10:33:08 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Specify MAC addresses on Luxul devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Use NRAM (NVMEM device) and its "et0macaddr" variable (NVMEM cell) to +point Ethernet devices to their MAC addresses. + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20230515083308.7612-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 13 +++++++++++++ + arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 13 +++++++++++++ + arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 13 +++++++++++++ + arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 11 +++++++++++ + arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 11 +++++++++++ + arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 13 +++++++++++++ + arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 11 +++++++++++ + arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 13 +++++++++++++ + arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 11 +++++++++++ + arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 5 ++++- + 10 files changed, 113 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts ++++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +@@ -20,6 +20,14 @@ + reg = <0x00000000 0x08000000>; + }; + ++ nvram@1eff0000 { ++ compatible = "brcm,nvram"; ++ reg = <0x1eff0000 0x10000>; ++ ++ et0macaddr: et0macaddr { ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -53,6 +61,11 @@ + }; + }; + ++&gmac0 { ++ nvmem-cells = <&et0macaddr>; ++ nvmem-cell-names = "mac-address"; ++}; ++ + &spi_nor { + status = "okay"; + }; +--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts ++++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +@@ -24,6 +24,14 @@ + reg = <0x00000000 0x08000000>; + }; + ++ nvram@1eff0000 { ++ compatible = "brcm,nvram"; ++ reg = <0x1eff0000 0x10000>; ++ ++ et0macaddr: et0macaddr { ++ }; ++ }; ++ + nand_controller: nand-controller@18028000 { + nand@0 { + partitions { +@@ -60,6 +68,11 @@ + }; + }; + ++&gmac0 { ++ nvmem-cells = <&et0macaddr>; ++ nvmem-cell-names = "mac-address"; ++}; ++ + &spi_nor { + status = "okay"; + }; +--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts ++++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +@@ -20,6 +20,14 @@ + reg = <0x00000000 0x08000000>; + }; + ++ nvram@1eff0000 { ++ compatible = "brcm,nvram"; ++ reg = <0x1eff0000 0x10000>; ++ ++ et0macaddr: et0macaddr { ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -53,6 +61,11 @@ + }; + }; + ++&gmac0 { ++ nvmem-cells = <&et0macaddr>; ++ nvmem-cell-names = "mac-address"; ++}; ++ + &spi_nor { + status = "okay"; + }; +--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts ++++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +@@ -24,6 +24,10 @@ + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; ++ ++ et0macaddr: et0macaddr { ++ #nvmem-cell-cells = <1>; ++ }; + }; + + leds { +@@ -106,6 +110,11 @@ + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; + }; + ++&gmac0 { ++ nvmem-cells = <&et0macaddr 0>; ++ nvmem-cell-names = "mac-address"; ++}; ++ + &spi_nor { + status = "okay"; + }; +@@ -137,6 +146,8 @@ + port@4 { + reg = <4>; + label = "wan"; ++ nvmem-cells = <&et0macaddr 5>; ++ nvmem-cell-names = "mac-address"; + }; + + port@5 { +--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +@@ -25,6 +25,10 @@ + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; ++ ++ et0macaddr: et0macaddr { ++ #nvmem-cell-cells = <1>; ++ }; + }; + + leds { +@@ -61,6 +65,11 @@ + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; + }; + ++&gmac0 { ++ nvmem-cells = <&et0macaddr 0>; ++ nvmem-cell-names = "mac-address"; ++}; ++ + &spi_nor { + status = "okay"; + }; +@@ -76,6 +85,8 @@ + port@0 { + reg = <0>; + label = "wan"; ++ nvmem-cells = <&et0macaddr 1>; ++ nvmem-cell-names = "mac-address"; + }; + + port@1 { +--- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +@@ -20,6 +20,14 @@ + reg = <0x00000000 0x08000000>; + }; + ++ nvram@1eff0000 { ++ compatible = "brcm,nvram"; ++ reg = <0x1eff0000 0x10000>; ++ ++ et0macaddr: et0macaddr { ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -51,6 +59,11 @@ + }; + }; + ++&gmac0 { ++ nvmem-cells = <&et0macaddr>; ++ nvmem-cell-names = "mac-address"; ++}; ++ + &spi_nor { + status = "okay"; + }; +--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +@@ -25,6 +25,10 @@ + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; ++ ++ et0macaddr: et0macaddr { ++ #nvmem-cell-cells = <1>; ++ }; + }; + + leds { +@@ -61,6 +65,11 @@ + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; + }; + ++&gmac0 { ++ nvmem-cells = <&et0macaddr 0>; ++ nvmem-cell-names = "mac-address"; ++}; ++ + &spi_nor { + status = "okay"; + }; +@@ -76,6 +85,8 @@ + port@0 { + reg = <0>; + label = "wan"; ++ nvmem-cells = <&et0macaddr 1>; ++ nvmem-cell-names = "mac-address"; + }; + + port@1 { +--- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +@@ -22,6 +22,14 @@ + <0x88000000 0x18000000>; + }; + ++ nvram@1eff0000 { ++ compatible = "brcm,nvram"; ++ reg = <0x1eff0000 0x10000>; ++ ++ et0macaddr: et0macaddr { ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -47,6 +55,11 @@ + status = "okay"; + }; + ++&gmac0 { ++ nvmem-cells = <&et0macaddr>; ++ nvmem-cell-names = "mac-address"; ++}; ++ + &spi_nor { + status = "okay"; + }; +--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +@@ -25,6 +25,10 @@ + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; ++ ++ et0macaddr: et0macaddr { ++ #nvmem-cell-cells = <1>; ++ }; + }; + + leds { +@@ -101,6 +105,11 @@ + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; + }; + ++&gmac0 { ++ nvmem-cells = <&et0macaddr 0>; ++ nvmem-cell-names = "mac-address"; ++}; ++ + &spi_nor { + status = "okay"; + }; +@@ -136,6 +145,8 @@ + port@4 { + reg = <4>; + label = "wan"; ++ nvmem-cells = <&et0macaddr 5>; ++ nvmem-cell-names = "mac-address"; + }; + + port@5 { +--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +@@ -27,6 +27,7 @@ + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { ++ #nvmem-cell-cells = <1>; + }; + }; + +@@ -76,7 +77,7 @@ + }; + + &gmac0 { +- nvmem-cells = <&et0macaddr>; ++ nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; + }; + +@@ -119,6 +120,8 @@ + port@4 { + reg = <4>; + label = "wan"; ++ nvmem-cells = <&et0macaddr 5>; ++ nvmem-cell-names = "mac-address"; + }; + + port@5 { diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0007-ARM-dts-BCM5301X-Use-updated-device-compatible-strin.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0007-ARM-dts-BCM5301X-Use-updated-device-compatible-strin.patch new file mode 100644 index 0000000000..5f5890e291 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0007-ARM-dts-BCM5301X-Use-updated-device-compatible-strin.patch @@ -0,0 +1,90 @@ +From 9d7121f1d2faa0b50bf5b462adcd2dd91970c45e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sat, 20 May 2023 13:26:01 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Use updated device "compatible" strings +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Northstar binding was updated to use minus/hyphen char between model and +version for all devices. + +Signed-off-by: Rafał Miłecki +Reviewed-by: Linus Walleij +Link: https://lore.kernel.org/r/20230520112601.11821-2-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 2 +- + arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 2 +- + arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 2 +- + arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 2 +- + arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 2 +- + arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 2 +- + 6 files changed, 6 insertions(+), 6 deletions(-) + +--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts ++++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +@@ -8,7 +8,7 @@ + #include "bcm4708.dtsi" + + / { +- compatible = "luxul,xap-1510v1", "brcm,bcm4708"; ++ compatible = "luxul,xap-1510-v1", "brcm,bcm4708"; + model = "Luxul XAP-1510 V1"; + + chosen { +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -13,7 +13,7 @@ + #include "bcm5301x-nand-cs0-bch8.dtsi" + + / { +- compatible = "netgear,r6250v1", "brcm,bcm4708"; ++ compatible = "netgear,r6250-v1", "brcm,bcm4708"; + model = "Netgear R6250 V1 (BCM4708)"; + + chosen { +--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +@@ -12,7 +12,7 @@ + #include "bcm5301x-nand-cs0-bch8.dtsi" + + / { +- compatible = "netgear,r6300v2", "brcm,bcm4708"; ++ compatible = "netgear,r6300-v2", "brcm,bcm4708"; + model = "Netgear R6300 V2 (BCM4708)"; + + chosen { +--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts ++++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +@@ -8,7 +8,7 @@ + #include "bcm47081.dtsi" + + / { +- compatible = "luxul,xap-1410v1", "brcm,bcm47081", "brcm,bcm4708"; ++ compatible = "luxul,xap-1410-v1", "brcm,bcm47081", "brcm,bcm4708"; + model = "Luxul XAP-1410 V1"; + + chosen { +--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts ++++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +@@ -9,7 +9,7 @@ + #include "bcm5301x-nand-cs0-bch4.dtsi" + + / { +- compatible = "luxul,xwr-1200v1", "brcm,bcm47081", "brcm,bcm4708"; ++ compatible = "luxul,xwr-1200-v1", "brcm,bcm47081", "brcm,bcm4708"; + model = "Luxul XWR-1200 V1"; + + chosen { +--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +@@ -9,7 +9,7 @@ + #include "bcm5301x-nand-cs0-bch4.dtsi" + + / { +- compatible = "luxul,xwr-3100v1", "brcm,bcm47094", "brcm,bcm4708"; ++ compatible = "luxul,xwr-3100-v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul XWR-3100 V1"; + + chosen { diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0008-ARM-dts-BCM5301X-Use-updated-spi-gpio-binding-proper.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0008-ARM-dts-BCM5301X-Use-updated-spi-gpio-binding-proper.patch new file mode 100644 index 0000000000..c16587f684 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0008-ARM-dts-BCM5301X-Use-updated-spi-gpio-binding-proper.patch @@ -0,0 +1,82 @@ +From 04afb51c1dce90051487d3c7b70a1b1b246ce29a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 2 Jun 2023 17:10:23 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Use updated "spi-gpio" binding properties +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Switch away from deprecated properties. + +This fixes: +arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dtb: spi: gpio-sck: False schema does not allow [[6, 7, 0]] + From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml +arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dtb: spi: gpio-mosi: False schema does not allow [[6, 4, 0]] + From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml +arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dtb: spi: 'sck-gpios' is a required property + From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml +arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dtb: spi: Unevaluated properties are not allowed ('gpio-mosi', 'gpio-sck' were unexpected) + From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20230602151023.8607-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi | 4 ++-- + arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 4 ++-- + arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 4 ++-- + arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 4 ++-- + 4 files changed, 8 insertions(+), 8 deletions(-) + +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi +@@ -16,8 +16,8 @@ + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; +- gpio-sck = <&chipcommon 7 0>; +- gpio-mosi = <&chipcommon 4 0>; ++ sck-gpios = <&chipcommon 7 0>; ++ mosi-gpios = <&chipcommon 4 0>; + cs-gpios = <&chipcommon 6 0>; + #address-cells = <1>; + #size-cells = <0>; +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -28,8 +28,8 @@ + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; +- gpio-sck = <&chipcommon 7 0>; +- gpio-mosi = <&chipcommon 4 0>; ++ sck-gpios = <&chipcommon 7 0>; ++ mosi-gpios = <&chipcommon 4 0>; + cs-gpios = <&chipcommon 6 0>; + #address-cells = <1>; + #size-cells = <0>; +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +@@ -28,8 +28,8 @@ + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; +- gpio-sck = <&chipcommon 7 0>; +- gpio-mosi = <&chipcommon 4 0>; ++ sck-gpios = <&chipcommon 7 0>; ++ mosi-gpios = <&chipcommon 4 0>; + cs-gpios = <&chipcommon 6 0>; + #address-cells = <1>; + #size-cells = <0>; +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +@@ -28,8 +28,8 @@ + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; +- gpio-sck = <&chipcommon 7 0>; +- gpio-mosi = <&chipcommon 4 0>; ++ sck-gpios = <&chipcommon 7 0>; ++ mosi-gpios = <&chipcommon 4 0>; + cs-gpios = <&chipcommon 6 0>; + #address-cells = <1>; + #size-cells = <0>; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0009-ARM-dts-BCM5301X-Drop-invalid-usb-cells.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0009-ARM-dts-BCM5301X-Drop-invalid-usb-cells.patch new file mode 100644 index 0000000000..59fa457aee --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0009-ARM-dts-BCM5301X-Drop-invalid-usb-cells.patch @@ -0,0 +1,54 @@ +From c3acdd4901192bc69dc577012663d5abae21661e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 2 Jun 2023 15:34:54 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Drop invalid #usb-cells +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Such property simply doesn't exist (is not documented or used anywhere). + +This fixes: +arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: usb@21000: Unevaluated properties are not allowed ('#usb-cells' was unexpected) + From schema: Documentation/devicetree/bindings/usb/generic-ehci.yaml +arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: usb@22000: Unevaluated properties are not allowed ('#usb-cells' was unexpected) + From schema: Documentation/devicetree/bindings/usb/generic-ohci.yaml +arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: usb@23000: Unevaluated properties are not allowed ('#usb-cells' was unexpected) + From schema: Documentation/devicetree/bindings/usb/generic-xhci.yaml + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20230602133455.7441-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm-ns.dtsi | 6 ------ + 1 file changed, 6 deletions(-) + +--- a/arch/arm/boot/dts/bcm-ns.dtsi ++++ b/arch/arm/boot/dts/bcm-ns.dtsi +@@ -192,8 +192,6 @@ + interrupt-parent = <&gic>; + + ehci: usb@21000 { +- #usb-cells = <0>; +- + compatible = "generic-ehci"; + reg = <0x00021000 0x1000>; + interrupts = ; +@@ -214,8 +212,6 @@ + }; + + ohci: usb@22000 { +- #usb-cells = <0>; +- + compatible = "generic-ohci"; + reg = <0x00022000 0x1000>; + interrupts = ; +@@ -245,8 +241,6 @@ + interrupt-parent = <&gic>; + + xhci: usb@23000 { +- #usb-cells = <0>; +- + compatible = "generic-xhci"; + reg = <0x00023000 0x1000>; + interrupts = ; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0010-ARM-dts-BCM5301X-Drop-invalid-properties-from-Meraki.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0010-ARM-dts-BCM5301X-Drop-invalid-properties-from-Meraki.patch new file mode 100644 index 0000000000..b8411fc719 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0010-ARM-dts-BCM5301X-Drop-invalid-properties-from-Meraki.patch @@ -0,0 +1,31 @@ +From 676bf7d062c14191c3fc12f1e36e1f3809041483 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 2 Jun 2023 15:34:55 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Drop invalid properties from Meraki MR32 + keys +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This fixes: +arch/arm/boot/dts/bcm53015-meraki-mr26.dtb: keys: '#address-cells', '#size-cells' do not match any of the regexes: '^(button|event|key|switch|(button|event|key|switch)-[a-z0-9-]+|[a-z0-9-]+-(button|event|key|switch))$', 'pinctrl-[0-9]+' + From schema: Documentation/devicetree/bindings/input/gpio-keys.yaml + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20230602133455.7441-2-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 2 -- + 1 file changed, 2 deletions(-) + +--- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts ++++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts +@@ -39,8 +39,6 @@ + + keys { + compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; + + key-restart { + label = "Reset"; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0011-ARM-dts-BCM5301X-Relicense-Christian-s-code-to-the-G.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0011-ARM-dts-BCM5301X-Relicense-Christian-s-code-to-the-G.patch new file mode 100644 index 0000000000..7496321269 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0011-ARM-dts-BCM5301X-Relicense-Christian-s-code-to-the-G.patch @@ -0,0 +1,106 @@ +From 1d5682ccc7d6088179b6cfd50a3e3bb6d2b0527e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 5 Jun 2023 08:10:49 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Relicense Christian's code to the GPL + 2.0+ / MIT +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Move code added by Christian to the bcm-ns.dtsi which uses dual +licensing. That syncs more Northstar code to be based on the same +licensing schema. + +Cc: Christian Lamparter +Signed-off-by: Rafał Miłecki +Acked-by: Christian Lamparter +Link: https://lore.kernel.org/r/20230605061049.16136-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm-ns.dtsi | 21 +++++++++++++++++++++ + arch/arm/boot/dts/bcm5301x.dtsi | 23 ----------------------- + 2 files changed, 21 insertions(+), 23 deletions(-) + +--- a/arch/arm/boot/dts/bcm-ns.dtsi ++++ b/arch/arm/boot/dts/bcm-ns.dtsi +@@ -182,6 +182,10 @@ + reg = <0x00013000 0x1000>; + }; + ++ pcie2: pcie@14000 { ++ reg = <0x00014000 0x1000>; ++ }; ++ + usb2: usb2@21000 { + reg = <0x00021000 0x1000>; + +@@ -274,6 +278,14 @@ + }; + }; + ++ pwm: pwm@18002000 { ++ compatible = "brcm,iproc-pwm"; ++ reg = <0x18002000 0x28>; ++ clocks = <&osc>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + mdio: mdio@18003000 { + compatible = "brcm,iproc-mdio"; + reg = <0x18003000 0x8>; +@@ -299,6 +311,15 @@ + }; + }; + ++ uart2: serial@18008000 { ++ compatible = "ns16550a"; ++ reg = <0x18008000 0x20>; ++ clocks = <&iprocslow>; ++ interrupts = ; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ + dmu-bus@1800c000 { + compatible = "simple-bus"; + ranges = <0 0x1800c000 0x1000>; +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -69,20 +69,6 @@ + }; + }; + +- axi@18000000 { +- pcie2: pcie@14000 { +- reg = <0x00014000 0x1000>; +- }; +- }; +- +- pwm: pwm@18002000 { +- compatible = "brcm,iproc-pwm"; +- reg = <0x18002000 0x28>; +- clocks = <&osc>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- + mdio-mux@18003000 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio>; +@@ -110,15 +96,6 @@ + reg = <0x18105000 0x1000>; + }; + +- uart2: serial@18008000 { +- compatible = "ns16550a"; +- reg = <0x18008000 0x20>; +- clocks = <&iprocslow>; +- interrupts = ; +- reg-shift = <2>; +- status = "disabled"; +- }; +- + i2c0: i2c@18009000 { + compatible = "brcm,iproc-i2c"; + reg = <0x18009000 0x50>; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0012-ARM-dts-BCM5301X-Describe-switch-ports-in-the-main-D.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0012-ARM-dts-BCM5301X-Describe-switch-ports-in-the-main-D.patch new file mode 100644 index 0000000000..fa2f21af53 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0012-ARM-dts-BCM5301X-Describe-switch-ports-in-the-main-D.patch @@ -0,0 +1,838 @@ +From ba4aebce23b2affb810b8a60eae853674d2cded2 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 5 Jun 2023 15:21:09 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Describe switch ports in the main DTS +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +All Northstar SoCs have BCM5301x switches (BCM53011, BCM53012) with 8 +ports (0-8 without 6). By design 3 switch ports (5, 7 and 8) are +hardwired to 3 on-SoC Ethernet interfaces. Switch port 8 requires +forcing link state. + +It seems that global Northstar .dtsi file is the best place to describe +those hw details. Only device specific bits (like labels) should go to +device .dts files. + +This seems to fit well with a tiny exception of Asus RT-AC88U which +somehow was designed to have switch 5 connected to an extra switch. This +case was simply handled with a /delete-property/. + +Signed-off-by: Rafał Miłecki +Reviewed-by: Christian Lamparter (MR32+MR26) +Link: https://lore.kernel.org/r/20230605132109.7933-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm-ns.dtsi | 41 ++++++++++++++++++- + .../bcm4708-buffalo-wzr-1166dhp-common.dtsi | 7 ---- + arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 4 -- + arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 3 -- + arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 7 ---- + arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 7 ---- + .../boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 7 ---- + arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 3 -- + arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 7 ---- + arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 12 ------ + arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 17 +------- + arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 12 ------ + arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts | 12 ------ + .../boot/dts/bcm47094-linksys-panamera.dts | 34 ++++----------- + arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 7 ---- + arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 4 -- + arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 7 ---- + arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 3 -- + arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 7 ---- + .../boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 7 ---- + arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 3 -- + arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 3 -- + 22 files changed, 51 insertions(+), 163 deletions(-) + +--- a/arch/arm/boot/dts/bcm-ns.dtsi ++++ b/arch/arm/boot/dts/bcm-ns.dtsi +@@ -304,10 +304,49 @@ + + status = "disabled"; + +- /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ }; ++ ++ port@5 { ++ reg = <5>; ++ ethernet = <&gmac0>; ++ }; ++ ++ port@7 { ++ reg = <7>; ++ ethernet = <&gmac1>; ++ }; ++ ++ port@8 { ++ reg = <8>; ++ ethernet = <&gmac2>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; + }; + }; + +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi +@@ -159,34 +159,27 @@ + + ports { + port@0 { +- reg = <0>; + label = "lan1"; + }; + + port@1 { +- reg = <1>; + label = "lan2"; + }; + + port@2 { +- reg = <2>; + label = "lan3"; + }; + + port@3 { +- reg = <3>; + label = "lan4"; + }; + + port@4 { +- reg = <4>; + label = "wan"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts ++++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +@@ -75,19 +75,15 @@ + + ports { + port@0 { +- reg = <0>; + label = "poe"; + }; + + port@4 { +- reg = <4>; + label = "lan"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts ++++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +@@ -82,14 +82,11 @@ + + ports { + port@4 { +- reg = <4>; + label = "lan"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -100,34 +100,27 @@ + + ports { + port@0 { +- reg = <0>; + label = "lan4"; + }; + + port@1 { +- reg = <1>; + label = "lan3"; + }; + + port@2 { +- reg = <2>; + label = "lan2"; + }; + + port@3 { +- reg = <3>; + label = "lan1"; + }; + + port@4 { +- reg = <4>; + label = "wan"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts ++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +@@ -123,34 +123,27 @@ + + ports { + port@0 { +- reg = <0>; + label = "lan4"; + }; + + port@1 { +- reg = <1>; + label = "lan3"; + }; + + port@2 { +- reg = <2>; + label = "lan2"; + }; + + port@3 { +- reg = <3>; + label = "lan1"; + }; + + port@4 { +- reg = <4>; + label = "wan"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +@@ -123,34 +123,27 @@ + + ports { + port@0 { +- reg = <0>; + label = "lan1"; + }; + + port@1 { +- reg = <1>; + label = "lan2"; + }; + + port@2 { +- reg = <2>; + label = "lan3"; + }; + + port@3 { +- reg = <3>; + label = "lan4"; + }; + + port@4 { +- reg = <4>; + label = "wan"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts ++++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +@@ -75,14 +75,11 @@ + + ports { + port@4 { +- reg = <4>; + label = "poe"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts ++++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +@@ -124,36 +124,29 @@ + + ports { + port@0 { +- reg = <0>; + label = "lan4"; + }; + + port@1 { +- reg = <1>; + label = "lan3"; + }; + + port@2 { +- reg = <2>; + label = "lan2"; + }; + + port@3 { +- reg = <3>; + label = "lan1"; + }; + + port@4 { +- reg = <4>; + label = "wan"; + nvmem-cells = <&et0macaddr 5>; + nvmem-cell-names = "mac-address"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -191,39 +191,27 @@ + + ports { + port@0 { +- reg = <0>; + label = "lan1"; + }; + + port@1 { +- reg = <1>; + label = "lan2"; + }; + + port@2 { +- reg = <2>; + label = "lan3"; + }; + + port@3 { +- reg = <3>; + label = "lan4"; + }; + + port@4 { +- reg = <4>; + label = "wan"; + }; + + port@8 { +- reg = <8>; + label = "cpu"; +- ethernet = <&gmac2>; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts ++++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +@@ -181,32 +181,28 @@ + + ports { + port@0 { +- reg = <0>; + label = "lan4"; + }; + + port@1 { +- reg = <1>; + label = "lan3"; + }; + + port@2 { +- reg = <2>; + label = "lan2"; + }; + + port@3 { +- reg = <3>; + label = "lan1"; + }; + + port@4 { +- reg = <4>; + label = "wan"; + }; + + sw0_p5: port@5 { +- reg = <5>; ++ /delete-property/ethernet; ++ + label = "extsw"; + phy-mode = "rgmii"; + +@@ -218,8 +214,6 @@ + }; + + port@7 { +- reg = <7>; +- ethernet = <&gmac1>; + label = "cpu"; + + fixed-link { +@@ -229,14 +223,7 @@ + }; + + port@8 { +- reg = <8>; +- ethernet = <&gmac2>; + label = "cpu"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts ++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +@@ -124,39 +124,27 @@ + + ports { + port@0 { +- reg = <0>; + label = "lan4"; + }; + + port@1 { +- reg = <1>; + label = "lan3"; + }; + + port@2 { +- reg = <2>; + label = "lan2"; + }; + + port@3 { +- reg = <3>; + label = "lan1"; + }; + + port@4 { +- reg = <4>; + label = "wan"; + }; + + port@8 { +- reg = <8>; + label = "cpu"; +- ethernet = <&gmac2>; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts ++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts +@@ -172,40 +172,28 @@ + + ports { + port@0 { +- reg = <0>; + label = "lan1"; + }; + + port@1 { +- reg = <1>; + label = "lan2"; + }; + + port@2 { +- reg = <2>; + label = "lan3"; + }; + + port@3 { +- reg = <3>; + label = "lan4"; + }; + + port@4 { +- reg = <4>; + label = "wan"; + }; + + port@8 { +- reg = <8>; + label = "cpu"; +- ethernet = <&gmac2>; + phy-mode = "rgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts ++++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +@@ -207,29 +207,32 @@ + dsa,member = <0 0>; + + ports { ++ sw0_p0: port@0 { ++ label = "extsw"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ + port@1 { +- reg = <1>; + label = "lan7"; + }; + + port@2 { +- reg = <2>; + label = "lan4"; + }; + + port@3 { +- reg = <3>; + label = "lan8"; + }; + + port@4 { +- reg = <4>; + label = "wan"; + }; + + port@5 { +- reg = <5>; +- ethernet = <&gmac0>; + label = "cpu"; + status = "disabled"; + +@@ -240,8 +243,6 @@ + }; + + port@7 { +- reg = <7>; +- ethernet = <&gmac1>; + label = "cpu"; + status = "disabled"; + +@@ -252,24 +253,7 @@ + }; + + port@8 { +- reg = <8>; +- ethernet = <&gmac2>; + label = "cpu"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- sw0_p0: port@0 { +- reg = <0>; +- label = "extsw"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +@@ -83,36 +83,29 @@ + + ports { + port@0 { +- reg = <0>; + label = "wan"; + nvmem-cells = <&et0macaddr 1>; + nvmem-cell-names = "mac-address"; + }; + + port@1 { +- reg = <1>; + label = "lan4"; + }; + + port@2 { +- reg = <2>; + label = "lan3"; + }; + + port@3 { +- reg = <3>; + label = "lan2"; + }; + + port@4 { +- reg = <4>; + label = "lan1"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +@@ -73,19 +73,15 @@ + + ports { + port@0 { +- reg = <0>; + label = "poe"; + }; + + port@1 { +- reg = <1>; + label = "lan"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +@@ -83,36 +83,29 @@ + + ports { + port@0 { +- reg = <0>; + label = "wan"; + nvmem-cells = <&et0macaddr 1>; + nvmem-cell-names = "mac-address"; + }; + + port@1 { +- reg = <1>; + label = "lan4"; + }; + + port@2 { +- reg = <2>; + label = "lan3"; + }; + + port@3 { +- reg = <3>; + label = "lan2"; + }; + + port@4 { +- reg = <4>; + label = "lan1"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +@@ -69,14 +69,11 @@ + + ports { + port@0 { +- reg = <0>; + label = "lan"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +@@ -123,36 +123,29 @@ + + ports { + port@0 { +- reg = <0>; + label = "lan4"; + }; + + port@1 { +- reg = <1>; + label = "lan3"; + }; + + port@2 { +- reg = <2>; + label = "lan2"; + }; + + port@3 { +- reg = <3>; + label = "lan1"; + }; + + port@4 { +- reg = <4>; + label = "wan"; + nvmem-cells = <&et0macaddr 5>; + nvmem-cell-names = "mac-address"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +@@ -98,36 +98,29 @@ + + ports { + port@0 { +- reg = <0>; + label = "lan4"; + }; + + port@1 { +- reg = <1>; + label = "lan3"; + }; + + port@2 { +- reg = <2>; + label = "lan2"; + }; + + port@3 { +- reg = <3>; + label = "lan1"; + }; + + port@4 { +- reg = <4>; + label = "wan"; + nvmem-cells = <&et0macaddr 5>; + nvmem-cell-names = "mac-address"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts ++++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts +@@ -115,14 +115,11 @@ + + ports { + port@0 { +- reg = <0>; + label = "poe"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + + fixed-link { + speed = <1000>; +--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts ++++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +@@ -176,14 +176,11 @@ + + ports { + port@0 { +- reg = <0>; + label = "poe"; + }; + + port@5 { +- reg = <5>; + label = "cpu"; +- ethernet = <&gmac0>; + + fixed-link { + speed = <1000>; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0013-ARM-dts-BCM5301X-MR26-MR32-remove-bogus-nand-ecc-alg.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0013-ARM-dts-BCM5301X-MR26-MR32-remove-bogus-nand-ecc-alg.patch new file mode 100644 index 0000000000..ea571f459a --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0013-ARM-dts-BCM5301X-MR26-MR32-remove-bogus-nand-ecc-alg.patch @@ -0,0 +1,63 @@ +From a6a1a156f5debaebf9f61850d111b966e9be9ee9 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Thu, 8 Jun 2023 17:36:27 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: MR26: MR32: remove bogus nand-ecc-algo + property +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +| bcm53015-meraki-mr26.dtb: nand-controller@18028000: +| nand@0:nand-ecc-algo:0: 'hw' is not one of ['hamming', 'bch', 'rs'] +| From schema: Documentation/[...]/nand-controller.yaml +| bcm53016-meraki-mr32.dtb: nand-controller@18028000: +| nand@0:nand-ecc-algo:0: 'hw' is not one of ['hamming', 'bch', 'rs'] +| From schema: Documentation/[...]/nand-controller.yaml + +original ECC values for these old Merakis are sadly not +provided by the vendor. It looks like Meraki just stuck +with what Broadcom's SDK was doing... which left this +up to the proprietary nand driver. + +Note: The invalid setting was and is handled by brcmnand. It +falls back to "bch" in brcmnand_setup_dev() when ecc.algo is +set to NAND_ECC_ALGO_UNKNOWN (since "hw" is not in the list +above). + +A correct nand-ecc-algo = "bch"; is already specified in the +included "bcm5301x-nand-cs0-bch8.dtsi". So this line can be +dropped. + +Reported-by: Rafał Miłecki (per Mail) +Fixes: 935327a73553 ("ARM: dts: BCM5301X: Add DT for Meraki MR26") +Fixes: ec88a9c344d9 ("ARM: BCM5301X: Add DT for Meraki MR32") +Signed-off-by: Christian Lamparter +Link: https://lore.kernel.org/r/2c4d00dd40124c2ddc0b139cbce7531b108f9052.1686238550.git.chunkeey@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 2 -- + arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 2 -- + 2 files changed, 4 deletions(-) + +--- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts ++++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts +@@ -72,8 +72,6 @@ + }; + + &nandcs { +- nand-ecc-algo = "hw"; +- + partitions { + compatible = "fixed-partitions"; + #address-cells = <0x1>; +--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts ++++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +@@ -125,8 +125,6 @@ + }; + + &nandcs { +- nand-ecc-algo = "hw"; +- + partitions { + /* + * The partition autodetection does not work for this device. diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0014-ARM-dts-BCM5301X-MR32-remove-partition-index-numbers.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0014-ARM-dts-BCM5301X-MR32-remove-partition-index-numbers.patch new file mode 100644 index 0000000000..8eb5442d17 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0014-ARM-dts-BCM5301X-MR32-remove-partition-index-numbers.patch @@ -0,0 +1,54 @@ +From d68b2f7d7d06872450d4f39d84d5926d7e7ae88c Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Thu, 8 Jun 2023 17:36:28 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: MR32: remove partition index numbers + +removes the partition indexes in the node names under. +This brings the device tree source in line with others. + +Signed-off-by: Christian Lamparter +Link: https://lore.kernel.org/r/627f57d568030a56499361790524b4d4f3381619.1686238550.git.chunkeey@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts ++++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +@@ -138,31 +138,31 @@ + #address-cells = <0x1>; + #size-cells = <0x1>; + +- partition0@0 { ++ partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + +- partition1@100000 { ++ partition@100000 { + label = "bootkernel1"; + reg = <0x100000 0x300000>; + read-only; + }; + +- partition2@400000 { ++ partition@400000 { + label = "nvram"; + reg = <0x400000 0x100000>; + read-only; + }; + +- partition3@500000 { ++ partition@500000 { + label = "bootkernel2"; + reg = <0x500000 0x300000>; + read-only; + }; + +- partition4@800000 { ++ partition@800000 { + label = "ubi"; + reg = <0x800000 0x7780000>; + }; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0015-ARM-dts-BCM5301X-fix-duplex-full-full-duplex.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0015-ARM-dts-BCM5301X-fix-duplex-full-full-duplex.patch new file mode 100644 index 0000000000..805dcf54eb --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0015-ARM-dts-BCM5301X-fix-duplex-full-full-duplex.patch @@ -0,0 +1,44 @@ +From fd274b733bfdde3ca72f0fa2a37f032f3a8c402c Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Thu, 8 Jun 2023 17:36:29 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: fix duplex-full => full-duplex + +this typo was found by the dtbs_check +| ports:port@5:fixed-link: 'oneOf' conditional failed, +| {'speed': [[1000]], 'duplex-full': True} is not of type 'array' +| 'duplex-full' does not match any of the regexes: 'pinctrl-[0-]..." + +this should have been full-duplex; + +Fixes: 935327a73553 ("ARM: dts: BCM5301X: Add DT for Meraki MR26") +Fixes: ec88a9c344d9 ("ARM: BCM5301X: Add DT for Meraki MR32") +Signed-off-by: Christian Lamparter +Link: https://lore.kernel.org/r/50522f45566951a9eabd22820647924cc6b4a264.1686238550.git.chunkeey@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 2 +- + arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts ++++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts +@@ -121,7 +121,7 @@ + + fixed-link { + speed = <1000>; +- duplex-full; ++ full-duplex; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts ++++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +@@ -182,7 +182,7 @@ + + fixed-link { + speed = <1000>; +- duplex-full; ++ full-duplex; + }; + }; + }; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0016-ARM-dts-BCM5301X-Add-Netgear-R8000-WiFi-regulator-ma.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0016-ARM-dts-BCM5301X-Add-Netgear-R8000-WiFi-regulator-ma.patch new file mode 100644 index 0000000000..3ffe0b2f17 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0016-ARM-dts-BCM5301X-Add-Netgear-R8000-WiFi-regulator-ma.patch @@ -0,0 +1,61 @@ +From 752a63b8dbe6cc6900efd1035bea427a778a4b55 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 2 Jun 2023 15:59:25 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Add Netgear R8000 WiFi regulator mappings +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This allows setting FullMAC firmware regulatory domain. + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20230602135925.14143-3-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -137,8 +137,10 @@ + #size-cells = <2>; + + wifi@0,1,0 { ++ compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + ieee80211-freq-limit = <5735000 5835000>; ++ brcm,ccode-map = "JP-JP-78", "US-Q2-86"; + }; + }; + }; +@@ -159,6 +161,19 @@ + #address-cells = <3>; + #size-cells = <2>; + ++ bridge@1,0 { ++ reg = <0x800 0 0 0 0>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ wifi@0,0 { ++ compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; ++ reg = <0x0000 0 0 0 0>; ++ brcm,ccode-map = "JP-JP-78", "US-Q2-86"; ++ }; ++ }; ++ + bridge@1,2,2 { + reg = <0x1000 0 0 0 0>; + +@@ -166,8 +181,10 @@ + #size-cells = <2>; + + wifi@1,4,0 { ++ compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + ieee80211-freq-limit = <5170000 5730000>; ++ brcm,ccode-map = "JP-JP-78", "US-Q2-86"; + }; + }; + }; diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.5-0017-ARM-dts-BCM5301X-Add-cells-sizes-to-PCIe-nodes.patch b/target/linux/bcm53xx/patches-5.15/036-v6.5-0017-ARM-dts-BCM5301X-Add-cells-sizes-to-PCIe-nodes.patch new file mode 100644 index 0000000000..454ce4c278 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/036-v6.5-0017-ARM-dts-BCM5301X-Add-cells-sizes-to-PCIe-nodes.patch @@ -0,0 +1,59 @@ +From b67cad33176e472df6d16a24ee7624299bdcd5d5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 16 Jun 2023 12:58:27 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Add cells sizes to PCIe nodes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This fixes: +arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@12000: '#address-cells' is a required property + From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml +arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@12000: '#size-cells' is a required property + From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml +arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@13000: '#address-cells' is a required property + From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml +arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@13000: '#size-cells' is a required property + From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml +arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@14000: '#address-cells' is a required property + From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml +arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@14000: '#size-cells' is a required property + From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml + +Two properties that need to be added later are "device_type" and +"ranges". Adding "device_type" on its own causes a new warning and the +value of "ranges" needs to be determined yet. + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20230616105827.21656-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm-ns.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm/boot/dts/bcm-ns.dtsi ++++ b/arch/arm/boot/dts/bcm-ns.dtsi +@@ -176,14 +176,23 @@ + + pcie0: pcie@12000 { + reg = <0x00012000 0x1000>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; + }; + + pcie1: pcie@13000 { + reg = <0x00013000 0x1000>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; + }; + + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; + }; + + usb2: usb2@21000 { diff --git a/target/linux/bcm53xx/patches-5.15/036-v6.2-bcma-support-SPROM-rev-11.patch b/target/linux/bcm53xx/patches-5.15/080-v6.2-bcma-support-SPROM-rev-11.patch similarity index 100% rename from target/linux/bcm53xx/patches-5.15/036-v6.2-bcma-support-SPROM-rev-11.patch rename to target/linux/bcm53xx/patches-5.15/080-v6.2-bcma-support-SPROM-rev-11.patch diff --git a/target/linux/bcm53xx/patches-5.15/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch b/target/linux/bcm53xx/patches-5.15/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch index 0fb29e99d3..d15506f6d7 100644 --- a/target/linux/bcm53xx/patches-5.15/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch +++ b/target/linux/bcm53xx/patches-5.15/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch @@ -10,7 +10,7 @@ Signed-off-by: Rafał Miłecki --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts -@@ -93,3 +93,40 @@ +@@ -92,3 +92,40 @@ &usb3_phy { status = "okay"; }; From 7bb616d3006e5efc7474e552e861bfece453fa70 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20K=C4=99pie=C5=84?= Date: Thu, 15 Jun 2023 15:59:44 +0200 Subject: [PATCH 05/17] ath79: mikrotik: extract common bits for RB951x-2HnD devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Mikrotik RouterBOARD 951Ui-2HnD and Mikrotik RouterBOARD RB951G-2HnD are very similar devices. Extract the DTS bits that are identical for these two boards to a separate DTSI file. Signed-off-by: Michał Kępień (cherry picked from commit c6ef4170945c6ab5432382110389f31fea92a76c) --- ...ar9344_mikrotik_routerboard-951ui-2hnd.dts | 81 +----------------- ...ar9344_mikrotik_routerboard-951x-2hnd.dtsi | 82 +++++++++++++++++++ 2 files changed, 83 insertions(+), 80 deletions(-) create mode 100644 target/linux/ath79/dts/ar9344_mikrotik_routerboard-951x-2hnd.dtsi diff --git a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951ui-2hnd.dts b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951ui-2hnd.dts index 3d59a30f11..65003cb9a1 100644 --- a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951ui-2hnd.dts +++ b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951ui-2hnd.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "ar9344_mikrotik_routerboard.dtsi" +#include "ar9344_mikrotik_routerboard-951x-2hnd.dtsi" / { compatible = "mikrotik,routerboard-951ui-2hnd", "qca,ar9344"; @@ -59,77 +59,6 @@ }; }; -&gpio { - nand_power { - gpio-hog; - gpios = <14 GPIO_ACTIVE_LOW>; - output-high; - }; -}; - -&nand { - status = "okay"; - - nand-ecc-mode = "soft"; - qca,nand-swap-dma; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "booter"; - reg = <0x0000000 0x0040000>; - read-only; - }; - - partition@40000 { - label = "kernel"; - reg = <0x0040000 0x03c0000>; - }; - - partition@400000 { - label = "ubi"; - reg = <0x0400000 0x7c00000>; - }; - }; -}; - -&spi { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - - partitions { - compatible = "mikrotik,routerboot-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "routerboot"; - reg = <0x0 0x0>; - read-only; - }; - - hard_config: hard_config { - read-only; - }; - - bios { - size = <0x1000>; - read-only; - }; - - soft_config { - }; - }; - }; -}; - ð0 { phy-handle = <&swphy4>; @@ -143,11 +72,3 @@ &wmac { qca,led-pin = /bits/ 8 <11>; }; - -&usb { - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; diff --git a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951x-2hnd.dtsi b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951x-2hnd.dtsi new file mode 100644 index 0000000000..5d135f1ca6 --- /dev/null +++ b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951x-2hnd.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "ar9344_mikrotik_routerboard.dtsi" + +&gpio { + nand_power { + gpio-hog; + gpios = <14 GPIO_ACTIVE_LOW>; + output-high; + }; +}; + +&nand { + status = "okay"; + + nand-ecc-mode = "soft"; + qca,nand-swap-dma; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "booter"; + reg = <0x0000000 0x0040000>; + read-only; + }; + + partition@40000 { + label = "kernel"; + reg = <0x0040000 0x03c0000>; + }; + + partition@400000 { + label = "ubi"; + reg = <0x0400000 0x7c00000>; + }; + }; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "mikrotik,routerboot-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "routerboot"; + reg = <0x0 0x0>; + read-only; + }; + + hard_config: hard_config { + read-only; + }; + + bios { + size = <0x1000>; + read-only; + }; + + soft_config { + }; + }; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; From 98b397d4fb56a7049eeda00ff138f439db32dcef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20K=C4=99pie=C5=84?= Date: Sat, 17 Jun 2023 19:12:21 +0200 Subject: [PATCH 06/17] ath79: add support for MikroTik RB951G-2HnD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MikroTik RB951G-2HnD is a wireless SOHO router that was previously supported by the ar71xx target, see commit 7a709573d7 ("ar71xx: add kernel support for the Mikrotik RB951G board"). Specifications -------------- - SoC: Atheros AR9344 (600 MHz) - RAM: 128 MB (2x 64 MB) - Storage: 128 MB NAND flash (various manufacturers) - Ethernet: Atheros AR8327 switch, 5x 10/100/1000 Mbit/s - 1x PoE in (port 1, 8-30 V input) - Wireless: Atheros AR9340 (802.11b/g/n) - USB: 2.0 (1A) - 8x LED: - 1x power (green, not configurable) - 1x user (green, not configurable) - 5x GE ports (green, not configurable) - 1x wireless (green, not configurable) - 1x button (restart) Unlike on the RB951Ui-2HnD, none of the LEDs on this device seem to be GPIO-controllable, which was also the case for older OpenWRT versions that supported this board via a mach file. The Ethernet port LEDs are controlled by the switch chip. See https://mikrotik.com/product/RB951G-2HnD for more details. Flashing -------- TFTP boot initramfs image and then perform sysupgrade. Follow common MikroTik procedures at https://openwrt.org/toh/mikrotik/common. Signed-off-by: Michał Kępień (cherry picked from commit db02cecd6ad2e5962e6e9d8307da34855a083ad6) --- .../ar9344_mikrotik_routerboard-951g-2hnd.dts | 58 +++++++++++++++++++ target/linux/ath79/image/mikrotik.mk | 9 +++ .../base-files/etc/board.d/02_network | 1 + .../etc/hotplug.d/firmware/10-ath9k-eeprom | 1 + .../base-files/lib/upgrade/platform.sh | 1 + 5 files changed, 70 insertions(+) create mode 100644 target/linux/ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts diff --git a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts new file mode 100644 index 0000000000..16da7a3c95 --- /dev/null +++ b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "ar9344_mikrotik_routerboard-951x-2hnd.dtsi" + +/ { + compatible = "mikrotik,routerboard-951g-2hnd", "qca,ar9344"; + model = "Mikrotik RouterBOARD 951G-2HnD"; + + /delete-node/ aliases; + /delete-node/ leds; + + gpio-export { + compatible = "gpio-export"; + + gpio_usb_power { + gpio-export,name = "rb951g-2hnd:power:usb"; + gpio-export,output = <1>; + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ref { + clock-frequency = <25000000>; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + + qca,ar8327-initvals = < + 0x04 0x07600000 /* PAD0_MODE */ + 0x7c 0x0000007e /* PORT0_STATUS */ + >; + }; +}; + +ð0 { + status = "okay"; + + pll-data = <0x6f000000 0x00000101 0x00001616>; + + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + gmac-config { + device = <&gmac>; + rgmii-gmac0 = <1>; + rxd-delay = <1>; + switch-only-mode = <1>; + }; +}; + +ð1 { + status = "disabled"; +}; diff --git a/target/linux/ath79/image/mikrotik.mk b/target/linux/ath79/image/mikrotik.mk index 3f65b35c8c..683e9a3330 100644 --- a/target/linux/ath79/image/mikrotik.mk +++ b/target/linux/ath79/image/mikrotik.mk @@ -48,6 +48,15 @@ define Device/mikrotik_routerboard-922uags-5hpacd endef TARGET_DEVICES += mikrotik_routerboard-922uags-5hpacd +define Device/mikrotik_routerboard-951g-2hnd + $(Device/mikrotik_nand) + SOC := ar9344 + DEVICE_MODEL := RouterBOARD 951G-2HnD + DEVICE_PACKAGES += kmod-usb-ohci kmod-usb2 + SUPPORTED_DEVICES += rb-951g-2hnd +endef +TARGET_DEVICES += mikrotik_routerboard-951g-2hnd + define Device/mikrotik_routerboard-951ui-2hnd $(Device/mikrotik_nand) SOC := ar9344 diff --git a/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network b/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network index aba811fb2d..68c8cfb96e 100644 --- a/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network +++ b/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network @@ -35,6 +35,7 @@ ath79_setup_interfaces() mikrotik,routerboard-map-2nd) ucidef_set_interface_lan "eth0 eth1" ;; + mikrotik,routerboard-951g-2hnd|\ mikrotik,routerboard-962uigs-5hact2hnt) ucidef_add_switch "switch0" \ "0@eth0" "2:lan" "3:lan" "4:lan" "5:lan" "1:wan" diff --git a/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom index b23bd05bcd..cc05ba080b 100644 --- a/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom +++ b/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom @@ -46,6 +46,7 @@ case "$FIRMWARE" in mikrotik,routerboard-962uigs-5hact2hnt) caldata_mikrotik_ath9k 0x1000 0x440 $(macaddr_add "$mac_base" 7) ;; + mikrotik,routerboard-951g-2hnd|\ mikrotik,routerboard-951ui-2hnd) caldata_mikrotik_ath9k 0x1000 0x440 $(macaddr_add "$mac_base" +11) ;; diff --git a/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh b/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh index cefbc5d334..e3887bfc50 100644 --- a/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh +++ b/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh @@ -33,6 +33,7 @@ platform_do_upgrade() { mikrotik,routerboard-912uag-2hpnd|\ mikrotik,routerboard-921gs-5hpacd-15s|\ mikrotik,routerboard-922uags-5hpacd|\ + mikrotik,routerboard-951g-2hnd|\ mikrotik,routerboard-951ui-2hnd|\ mikrotik,routerboard-sxt-5nd-r2) platform_do_upgrade_mikrotik_nand "$1" From b7fac1bf8c6f975607427734f85318c69aacaeb6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pavel=20Perni=C4=8Dka?= Date: Tue, 27 Jun 2023 18:34:03 +0200 Subject: [PATCH 07/17] ath79: DTS improvement for buzzer on RB951G-2HnD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Mikrotik RB951 router has a buzzer on the board, which makes annoying noises due to the interference caused by PoE input or Wifi transmission when no GPIO pin state is set. I added buzzer node to device's DTS in order to set deault level to 1 and to provide easier access for it. Signed-off-by: Pavel Pernička (cherry picked from commit dac0a133cf8dbf0bd9afabecdc1092456c451ec7) --- .../ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts index 16da7a3c95..6229eefb1f 100644 --- a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts +++ b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts @@ -17,6 +17,12 @@ gpio-export,output = <1>; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; }; + + buzzer { + gpio-export,name = "buzzer"; + gpio-export,output = <1>; + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + }; }; }; From 977ee439d7068e405361322013e9a2114bfefcda Mon Sep 17 00:00:00 2001 From: Wenli Looi Date: Thu, 30 Mar 2023 22:27:11 +0000 Subject: [PATCH 08/17] image: add additional fields to Netgear encrypted image These fields are used for EAX12 and EX6250v2 series, and perhaps other devices. Compatibility is preserved with the WAX202 and WAX206. In addition, adds the related vars to DEVICE_VARS so that the variables work correctly with multiple devices. References in GPL source: https://www.downloads.netgear.com/files/GPL/EAX12_EAX11v2_EAX15v2_GPL_V1.0.3.34_src.tar.gz * tools/imgencoder/src/gj_enc.c Contains code that generates the encrypted image. Signed-off-by: Wenli Looi (cherry picked from commit 0a1ebccc8702cadc50bc096f1e185472f3927786) --- include/image-commands.mk | 2 ++ scripts/netgear-encrypted-factory.py | 15 +++++++++++++-- target/linux/mediatek/image/Makefile | 6 ++++++ target/linux/ramips/image/Makefile | 5 +++++ 4 files changed, 26 insertions(+), 2 deletions(-) diff --git a/include/image-commands.mk b/include/image-commands.mk index 1d69485019..dc6ee6e7c1 100644 --- a/include/image-commands.mk +++ b/include/image-commands.mk @@ -423,6 +423,8 @@ define Build/netgear-encrypted-factory --output-file $@ \ --model $(NETGEAR_ENC_MODEL) \ --region $(NETGEAR_ENC_REGION) \ + $(if $(NETGEAR_ENC_HW_ID_LIST),--hw-id-list "$(NETGEAR_ENC_HW_ID_LIST)") \ + $(if $(NETGEAR_ENC_MODEL_LIST),--model-list "$(NETGEAR_ENC_MODEL_LIST)") \ --version V1.0.0.0.$(shell cat $(VERSION_DIST)| sed -e 's/[[:space:]]/-/g').$(firstword $(subst -, ,$(REVISION))) \ --encryption-block-size 0x20000 \ --openssl-bin "$(STAGING_DIR_HOST)/bin/openssl" \ diff --git a/scripts/netgear-encrypted-factory.py b/scripts/netgear-encrypted-factory.py index b6bb72f3b8..40cfd9df0d 100755 --- a/scripts/netgear-encrypted-factory.py +++ b/scripts/netgear-encrypted-factory.py @@ -14,6 +14,8 @@ def main(): parser.add_argument('--model', type=str, required=True) parser.add_argument('--region', type=str, required=True) parser.add_argument('--version', type=str, required=True) + parser.add_argument('--hw-id-list', type=str) + parser.add_argument('--model-list', type=str) parser.add_argument('--encryption-block-size', type=str, required=True) parser.add_argument('--openssl-bin', type=str, required=True) parser.add_argument('--key', type=str, required=True) @@ -26,6 +28,10 @@ def main(): assert (encryption_block_size > 0 and encryption_block_size % 16 == 0), 'Encryption block size must be a multiple of the AES block size (16)' + hw_id_list = args.hw_id_list.split(';') if args.hw_id_list else [] + model_list = args.model_list.split(';') if args.model_list else [] + hw_info = ';'.join(hw_id_list + model_list) + image = open(args.input_file, 'rb').read() image_enc = [] for i in range(0, len(image), encryption_block_size): @@ -45,13 +51,18 @@ def main(): image_enc = b''.join(image_enc) image_with_header = struct.pack( - '>32s32s64s64s64s256s12sII', + '>32s32s64s64sIBBB13s200s100s12sII', args.model.encode('ascii'), args.region.encode('ascii'), args.version.encode('ascii'), b'Thu Jan 1 00:00:00 1970', # static date for reproducibility + 0, # product hw model + 0, # model index + len(hw_id_list), + len(model_list), + b'', # reserved + hw_info.encode('ascii'), b'', # reserved - b'', # RSA signature - omitted for now b'encrpted_img', len(image_enc), encryption_block_size, diff --git a/target/linux/mediatek/image/Makefile b/target/linux/mediatek/image/Makefile index 97164428e0..d4f79ec974 100644 --- a/target/linux/mediatek/image/Makefile +++ b/target/linux/mediatek/image/Makefile @@ -6,6 +6,8 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/image.mk +DEVICE_VARS += NETGEAR_ENC_MODEL NETGEAR_ENC_REGION NETGEAR_ENC_HW_ID_LIST NETGEAR_ENC_MODEL_LIST + loadaddr-$(CONFIG_TARGET_mediatek_mt7622) := 0x44000000 loadaddr-$(CONFIG_TARGET_mediatek_mt7623) := 0x80008000 loadaddr-$(CONFIG_TARGET_mediatek_mt7629) := 0x40008000 @@ -22,6 +24,10 @@ define Device/Default KERNEL_LOADADDR = $(loadaddr-y) FILESYSTEMS := squashfs DEVICE_DTS_DIR := $(DTS_DIR) + NETGEAR_ENC_MODEL := + NETGEAR_ENC_REGION := + NETGEAR_ENC_HW_ID_LIST := + NETGEAR_ENC_MODEL_LIST := IMAGES := sysupgrade.bin IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | \ pad-rootfs | append-metadata diff --git a/target/linux/ramips/image/Makefile b/target/linux/ramips/image/Makefile index c080456e7a..265e9fb5e0 100644 --- a/target/linux/ramips/image/Makefile +++ b/target/linux/ramips/image/Makefile @@ -7,6 +7,7 @@ include $(INCLUDE_DIR)/image.mk DEVICE_VARS += LOADER_TYPE LOADER_FLASH_OFFS LZMA_TEXT_START DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID +DEVICE_VARS += NETGEAR_ENC_MODEL NETGEAR_ENC_REGION NETGEAR_ENC_HW_ID_LIST NETGEAR_ENC_MODEL_LIST DEVICE_VARS += BUFFALO_TAG_PLATFORM BUFFALO_TAG_VERSION BUFFALO_TAG_MINOR DEVICE_VARS += SEAMA_SIGNATURE SEAMA_MTDBLOCK DEVICE_VARS += SERCOMM_HWNAME SERCOMM_HWID SERCOMM_HWVER SERCOMM_SWVER @@ -179,6 +180,10 @@ define Device/Default SOC := $(DEFAULT_SOC) DEVICE_DTS_DIR := ../dts DEVICE_DTS = $$(SOC)_$(1) + NETGEAR_ENC_MODEL := + NETGEAR_ENC_REGION := + NETGEAR_ENC_HW_ID_LIST := + NETGEAR_ENC_MODEL_LIST := IMAGES := sysupgrade.bin COMPILE := sysupgrade_bin := append-kernel | append-rootfs | pad-rootfs From 23d6474e451216d2e9c7b3b5d29df336b9523b5c Mon Sep 17 00:00:00 2001 From: Wenli Looi Date: Thu, 30 Mar 2023 19:46:19 +0000 Subject: [PATCH 09/17] mediatek: add support for Netgear EX6250v2 series Netgear EX6250v2, EX6400v3, EX6410v2, EX6470 are wall-plug 802.11ac (Wi-Fi 5) extenders. Like other MT7629 devices, Wi-Fi does not work currently as there is no driver. Related: https://github.com/openwrt/openwrt/pull/5084 For future reference, 2.4GHz MAC = LAN+1, 5GHz MAC = LAN+2. Specifications: * MT7629, 256 MiB RAM, 16 MiB SPI NOR * MT7761N (2.4GHz) / MT7762N (5GHz) - no driver * Ethernet: 1 port 10/100/1000 * UART: 115200 baud (labeled on board) Installation: * Flash the factory image through the stock web interface, or TFTP to the bootloader. NMRP can be used to TFTP without opening the case. * After installation, perform a factory reset. Wait for the device to boot, then hold the reset button for 10 seconds. This is needed because sysupgrade in the stock firmware will attempt to preserve its configuration using sysupgrade.tgz. See https://github.com/openwrt/openwrt/pull/4182 Revert to stock firmware: * Flash the stock firmware to the bootloader using TFTP/NMRP. Signed-off-by: Wenli Looi (cherry picked from commit 73de41898fcd06d837b013449c370c493bcdc595) --- .../boot/uboot-envtools/files/mediatek_mt7629 | 3 +- .../mediatek/dts/mt7629-netgear-ex6250-v2.dts | 238 ++++++++++++++++++ target/linux/mediatek/image/mt7629.mk | 26 ++ .../mt7629/base-files/etc/board.d/01_leds | 4 + .../mt7629/base-files/etc/board.d/02_network | 11 + 5 files changed, 281 insertions(+), 1 deletion(-) create mode 100644 target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts diff --git a/package/boot/uboot-envtools/files/mediatek_mt7629 b/package/boot/uboot-envtools/files/mediatek_mt7629 index a5aa2b58a6..313fb6a448 100644 --- a/package/boot/uboot-envtools/files/mediatek_mt7629 +++ b/package/boot/uboot-envtools/files/mediatek_mt7629 @@ -12,7 +12,8 @@ touch /etc/config/ubootenv board=$(board_name) case "$board" in -iptime,a6004mx) +iptime,a6004mx|\ +netgear,ex6250-v2) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x1000" ;; esac diff --git a/target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts b/target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts new file mode 100644 index 0000000000..5645ad799e --- /dev/null +++ b/target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include +#include "mt7629.dtsi" + +/ { + model = "Netgear EX6250 v2"; + compatible = "netgear,ex6250-v2", "mediatek,mt7629"; + + aliases { + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_red; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-override = "console=ttyS0,115200n8"; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 60 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&pio 58 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ap_mode { + label = "ap_mode"; + gpios = <&pio 54 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + extender_mode { + label = "extender_mode"; + gpios = <&pio 53 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_power_green: power_green { + label = "green:power"; + gpios = <&pio 21 GPIO_ACTIVE_LOW>; + }; + + led_power_red: power_red { + label = "red:power"; + gpios = <&pio 61 GPIO_ACTIVE_LOW>; + }; + + client_green { + label = "green:client"; + gpios = <&pio 59 GPIO_ACTIVE_LOW>; + }; + + client_red { + label = "red:client"; + gpios = <&pio 24 GPIO_ACTIVE_LOW>; + }; + + router_green { + label = "green:router"; + gpios = <&pio 55 GPIO_ACTIVE_LOW>; + }; + + router_red { + label = "red:router"; + gpios = <&pio 56 GPIO_ACTIVE_LOW>; + }; + + wps_green { + label = "green:wps"; + gpios = <&pio 57 GPIO_ACTIVE_LOW>; + }; + + eth_green { + label = "green:eth"; + gpios = <&pio 16 GPIO_ACTIVE_LOW>; + }; + + eth_yellow { + label = "yellow:eth"; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + pinctrl-1 = <&ephy_leds_pins>; + status = "okay"; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&phy0>; + }; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&qspi { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Bootloader"; + reg = <0x0 0x60000>; + read-only; + }; + + partition@60000 { + label = "Config"; + reg = <0x60000 0x10000>; + read-only; + }; + + partition@70000 { + label = "Factory"; + reg = <0x70000 0x10000>; + read-only; + }; + + partition@80000 { + label = "firmware"; + reg = <0x80000 0xcd0000>; + compatible = "denx,fit"; + }; + + partition@d50000 { + label = "CFG"; + reg = <0xd50000 0x80000>; + read-only; + }; + + partition@dd0000 { + label = "RAE"; + reg = <0xdd0000 0x200000>; + read-only; + }; + + partition@fd0000 { + label = "POT"; + reg = <0xfd0000 0x10000>; + read-only; + }; + + partition@fe0000 { + label = "LOG"; + reg = <0xfe0000 0x20000>; + read-only; + }; + }; + }; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio"; + }; + }; + + ephy_leds_pins: ephy-leds-pins { + mux { + function = "led"; + groups = "ephy_leds"; + }; + }; + + qspi_pins: qspi-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_txd_rxd" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; diff --git a/target/linux/mediatek/image/mt7629.mk b/target/linux/mediatek/image/mt7629.mk index 3f5b2e2579..33c557190f 100644 --- a/target/linux/mediatek/image/mt7629.mk +++ b/target/linux/mediatek/image/mt7629.mk @@ -22,3 +22,29 @@ define Device/iptime_a6004mx IMAGE/recovery.bin := append-kernel | pad-to 128k | append-ubi | append-metadata endef TARGET_DEVICES += iptime_a6004mx + +define Device/netgear_ex6250-v2 + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := EX6250 + DEVICE_VARIANT := v2 + DEVICE_ALT0_VENDOR := NETGEAR + DEVICE_ALT0_MODEL := EX6400 + DEVICE_ALT0_VARIANT := v3 + DEVICE_ALT1_VENDOR := NETGEAR + DEVICE_ALT1_MODEL := EX6410 + DEVICE_ALT1_VARIANT := v2 + DEVICE_ALT2_VENDOR := NETGEAR + DEVICE_ALT2_MODEL := EX6470 + DEVICE_DTS := mt7629-netgear-ex6250-v2 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := uboot-envtools + NETGEAR_ENC_MODEL := EX6250v2 + NETGEAR_ENC_REGION := US + NETGEAR_ENC_HW_ID_LIST := 1010000003630000_NETGEAR;1010000003540000_NETGEAR + NETGEAR_ENC_MODEL_LIST := EX6250v2;EX6400v3;EX6470;EX6410v2 + IMAGE_SIZE := 13120k + IMAGES += factory.img + IMAGE/factory.img := append-kernel | pad-to 128k | append-rootfs | \ + pad-rootfs | check-size | netgear-encrypted-factory +endef +TARGET_DEVICES += netgear_ex6250-v2 diff --git a/target/linux/mediatek/mt7629/base-files/etc/board.d/01_leds b/target/linux/mediatek/mt7629/base-files/etc/board.d/01_leds index 42b6fcbbb3..c42ab4713b 100644 --- a/target/linux/mediatek/mt7629/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/mt7629/base-files/etc/board.d/01_leds @@ -9,6 +9,10 @@ case $board in iptime,a6004mx) ucidef_set_led_netdev "wan" "WAN" "orange:wan" "eth1" ;; +netgear,ex6250-v2) + ucidef_set_led_netdev "eth_act" "LAN act" "yellow:eth" "eth0" "tx rx" + ucidef_set_led_netdev "eth_link" "LAN link" "green:eth" "eth0" "link" + ;; esac board_config_flush diff --git a/target/linux/mediatek/mt7629/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7629/base-files/etc/board.d/02_network index 4254f39ca0..db931c8334 100644 --- a/target/linux/mediatek/mt7629/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/mt7629/base-files/etc/board.d/02_network @@ -16,6 +16,9 @@ mediatek_setup_interfaces() ucidef_add_switch "switch0" \ "0:lan" "1:lan" "2:lan" "3:lan" "6@eth0" ;; + netgear,ex6250-v2) + ucidef_set_interface_lan "eth0" + ;; esac } @@ -24,7 +27,15 @@ mediatek_setup_macs() local board="$1" case $board in + netgear,ex6250-v2) + lan_mac=$(mtd_get_mac_ascii Config mac) + label_mac=$lan_mac + ;; esac + + [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac + [ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac } board_config_update From f7daeec3bd54fd5f21b31c0aab15e7573d325009 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 20 May 2023 23:03:06 +0800 Subject: [PATCH 10/17] uboot-mediatek: add H3C Magic NX30 Pro support The OEM uboot limit brush into 3rd-party firmware. So add a custom uboot build to support openwrt. Signed-off-by: Chukun Pan (cherry picked from commit 437e79ad6d01100afac9786d287976de6d5cf363) --- .../uboot-envtools/files/mediatek_filogic | 1 + package/boot/uboot-mediatek/Makefile | 13 + .../patches/435-add-h3c_magic-nx30-pro.patch | 440 ++++++++++++++++++ 3 files changed, 454 insertions(+) create mode 100644 package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic index 7918bdacfc..77c9d964db 100644 --- a/package/boot/uboot-envtools/files/mediatek_filogic +++ b/package/boot/uboot-envtools/files/mediatek_filogic @@ -51,6 +51,7 @@ xiaomi,redmi-router-ax6000-stock) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x20000" ubootenv_add_uci_sys_config "/dev/mtd2" "0x0" "0x10000" "0x20000" ;; +h3c,magic-nx30-pro|\ qihoo,360t7|\ tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index 8ea05b9159..33fd7e086e 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -176,6 +176,18 @@ define U-Boot/mt7629_rfb UBOOT_CONFIG:=mt7629_rfb endef +define U-Boot/mt7981_h3c_magic-nx30-pro + NAME:=H3C Magic NX30 Pro + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=h3c_magic-nx30-pro + UBOOT_CONFIG:=mt7981_h3c_magic-nx30-pro + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 +endef + define U-Boot/mt7981_qihoo_360t7 NAME:=Qihoo 360T7 BUILD_SUBTARGET:=filogic @@ -313,6 +325,7 @@ UBOOT_TARGETS := \ mt7628_rfb \ ravpower_rp-wd009 \ mt7629_rfb \ + mt7981_h3c_magic-nx30-pro \ mt7981_qihoo_360t7 \ mt7986_bananapi_bpi-r3-emmc \ mt7986_bananapi_bpi-r3-sdmmc \ diff --git a/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch b/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch new file mode 100644 index 0000000000..e7d1ce764c --- /dev/null +++ b/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch @@ -0,0 +1,440 @@ +--- /dev/null ++++ b/configs/mt7981_h3c_magic-nx30-pro_defconfig +@@ -0,0 +1,175 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7981=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981_h3c_magic-nx30-pro" ++CONFIG_DEFAULT_ENV_FILE="h3c_magic-nx30-pro_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_h3c_magic-nx30-pro.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/arch/arm/dts/mt7981_h3c_magic-nx30-pro.dts +@@ -0,0 +1,200 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include ++#include ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "H3C Magic NX30 Pro"; ++ compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ factory { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "wps"; ++ linux,code = ; ++ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ status_red { ++ label = "red:status"; ++ gpios = <&gpio 4 GPIO_ACTIVE_LOW>; ++ }; ++ ++ status_green { ++ label = "green:status"; ++ gpios = <&gpio 5 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "sgmii"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ }; ++ ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_1"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ pwm_pins: pwm0-pins-func-1 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_1", "pwm1_0"; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0000000 0x0100000>; ++ }; ++ ++ partition@100000 { ++ label = "orig-env"; ++ reg = <0x0100000 0x0080000>; ++ }; ++ ++ partition@180000 { ++ label = "factory"; ++ reg = <0x0180000 0x0200000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x0380000 0x0200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x0580000 0x4000000>; ++ }; ++ ++ partition@4580000 { ++ label = "pdt_data"; ++ reg = <0x4580000 0x0600000>; ++ }; ++ ++ partition@4b80000 { ++ label = "pdt_data_1"; ++ reg = <0x4b80000 0x0600000>; ++ }; ++ ++ partition@5180000 { ++ label = "exp"; ++ reg = <0x5180000 0x0100000>; ++ }; ++ ++ partition@5280000 { ++ label = "plugin"; ++ reg = <0x5280000 0x2580000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/h3c_magic-nx30-pro_env +@@ -0,0 +1,56 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-h3c_magic-nx30-pro-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-h3c_magic-nx30-pro-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-h3c_magic-nx30-pro-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-h3c_magic-nx30-pro-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=red:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" From cf81850ccea9cce9ae64e638d49bf75838e518d9 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 21 May 2023 23:00:16 +0800 Subject: [PATCH 11/17] mediatek: filogic: add H3C Magic NX30 Pro support Hardware specification: SoC: MediaTek MT7981B 2x A53 Flash: W25N01GVZEIG 128MB RAM: NT5CB128M16JR-FL 256MB Ethernet: 4x 10/100/1000 Mbps Switch: MediaTek MT7531AE WiFi: MediaTek MT7976C Button: Reset, WPS Power: DC 12V 1A Flash instructions: 1. PC run command: "telnet 192.168.124.1 99" Username: H3C, password is the web login password of the router. 2. Download preloader.bin and bl31-uboot.fip 3. PC run command: "python3 -m http.server 80" 4. Download files in the telnet window: "wget http://192.168.124.xx/xxx.bin" Replace xx with your PC's IP and the preloader.bin and bl31-uboot.fip. 5. Flushing openwrt's uboot: "mtd write xxx-preloader.bin BL2" "mtd write xxx-bl31-uboot.fip FIP" 6. Connect to the router via the Lan port, set a static ip of your PC. (ip 192.168.1.254, gateway 192.168.1.1) 7. Download initramfs image, reboot router, waiting for tftp recovery to complete. 8. After openwrt boots up, perform sysupgrade. Note: 1. The u-boot-env partition on mtd is empty, OEM stores their env on ubi:u-boot-env. 2. Back up all mtd partitions before flashing. Signed-off-by: Chukun Pan (cherry picked from commit e78d1a06c8a47be9ea5a306bfb43f3d7ceb89646) --- .../dts/mt7981b-h3c-magic-nx30-pro.dts | 239 ++++++++++++++++++ .../filogic/base-files/etc/board.d/02_network | 8 + .../etc/hotplug.d/ieee80211/11_fix_wifi_mac | 5 + .../base-files/lib/upgrade/platform.sh | 1 + target/linux/mediatek/image/filogic.mk | 25 ++ 5 files changed, 278 insertions(+) create mode 100644 target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts diff --git a/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts b/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts new file mode 100644 index 0000000000..358365adba --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include +#include + +#include "mt7981.dtsi" + +/ { + model = "H3C Magic NX30 Pro"; + compatible = "h3c,magic-nx30-pro", "mediatek,mt7981"; + + aliases { + serial0 = &uart0; + led-boot = &led_status_green; + led-failsafe = &led_status_red; + led-running = &led_status_green; + led-upgrade = &led_status_red; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x10000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_green: green { + label = "green:status"; + gpios = <&pio 4 GPIO_ACTIVE_LOW>; + }; + + led_status_red: red { + label = "red:status"; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + }; +}; + +&mdio_bus { + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x0000000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x0180000 0x0200000>; + read-only; + }; + + partition@380000 { + label = "FIP"; + reg = <0x0380000 0x0200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x0580000 0x4000000>; + }; + + /* yaffs partition */ + partition@4580000 { + label = "pdt_data"; + reg = <0x4580000 0x0600000>; + read-only; + }; + + /* yaffs partition */ + partition@4b80000 { + label = "pdt_data_1"; + reg = <0x4b80000 0x0600000>; + read-only; + }; + + partition@5180000 { + label = "exp"; + reg = <0x5180000 0x0100000>; + read-only; + }; + + partition@5280000 { + label = "plugin"; + reg = <0x5280000 0x2580000>; + read-only; + }; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index c05c5d25e4..6abc81a0b0 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -23,6 +23,9 @@ mediatek_setup_interfaces() glinet,gl-mt3000) ucidef_set_interfaces_lan_wan eth1 eth0 ;; + h3c,magic-nx30-pro) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" eth1 + ;; mediatek,mt7986a-rfb) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan6" "eth1 wan" ;; @@ -72,6 +75,11 @@ mediatek_setup_macs() bananapi,bpi-r3) wan_mac=$(macaddr_add $(cat /sys/class/net/eth0/address) 1) ;; + h3c,magic-nx30-pro) + wan_mac=$(mtd_get_mac_ascii pdt_data_1 ethaddr) + lan_mac=$(macaddr_add "$wan_mac" 1) + label_mac=$wan_mac + ;; mercusys,mr90x-v1) label_mac=$(get_mac_binary "/tmp/tp_data/default-mac" 0) lan_mac=$label_mac diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 4b7047eec5..ab23b10044 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -32,6 +32,11 @@ case "$board" in [ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress ;; + h3c,magic-nx30-pro) + addr=$(mtd_get_mac_ascii pdt_data_1 ethaddr) + [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress + ;; mercusys,mr90x-v1) addr=$(get_mac_binary "/tmp/tp_data/default-mac" 0) [ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 11c2c5c664..186abfa5a8 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -74,6 +74,7 @@ platform_do_upgrade() { CI_UBIPART="ubi0" nand_do_upgrade "$1" ;; + h3c,magic-nx30-pro|\ qihoo,360t7|\ tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index fd83b9d441..2ace305140 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -176,6 +176,31 @@ define Device/glinet_gl-mt3000 endef TARGET_DEVICES += glinet_gl-mt3000 +define Device/h3c_magic-nx30-pro + DEVICE_VENDOR := H3C + DEVICE_MODEL := Magic NX30 Pro + DEVICE_DTS := mt7981b-h3c-magic-nx30-pro + DEVICE_DTS_DIR := ../dts + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + IMAGE_SIZE := 65536k + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3 + ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot h3c_magic-nx30-pro +endef +TARGET_DEVICES += h3c_magic-nx30-pro + define Device/netgear_wax220 DEVICE_VENDOR := Netgear DEVICE_MODEL := WAX220 From 0af05cd32a69b2e92f11e9b8307a1537c7406d34 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 8 Jul 2023 16:27:25 +0100 Subject: [PATCH 12/17] mediatek: dts: mt7988a: wire-up mediatek,pio for PHY LEDs The PHY driver needs to read a register containing the values of the bootstrap pins (which happen to be the PHY LEDs) to determine the LED polarities. Allow regmap access to first pinctrl bank by adding the 'syscon' compatible, and reference the pinctrl in the MDIO bus where the PHY driver will look for it. Signed-off-by: Daniel Golle (cherry picked from commit 1f1e0b1144ebaa4ba8b948a12d989a0a6fc9b76f) --- .../arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts | 1 + .../files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts index 98dbf8d691..e204dc4f16 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts @@ -156,6 +156,7 @@ mdio { #address-cells = <1>; #size-cells = <0>; + mediatek,pio = <&pio>; gsw_phy0: ethernet-phy@0 { compatible = "ethernet-phy-id03a2.9481"; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 13ad39500d..17de885629 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -215,7 +215,7 @@ }; pio: pinctrl@1001f000 { - compatible = "mediatek,mt7988-pinctrl"; + compatible = "mediatek,mt7988-pinctrl", "syscon"; reg = <0 0x1001f000 0 0x1000>, <0 0x11c10000 0 0x1000>, <0 0x11d00000 0 0x1000>, From 6092c39c13232dcccf9794c2b9e4b4a820ba1c4a Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 8 Jul 2023 17:21:27 +0100 Subject: [PATCH 13/17] mediatek: use backported Ethernet PHY driver also for 5.15 Backport in-SoC Gigabit Ethernet PHY driver instead of carrying the driver in files-5.15. Signed-off-by: Daniel Golle (cherry picked from commit 9fac59009657068d5a58b3d0255d4ca1507dd457) --- .../drivers/net/phy/mediatek-ge-soc.c | 1263 ----------------- ...er-for-MediaTek-SoC-built-in-GE-PHYs.patch | 82 -- ...er-for-MediaTek-SoC-built-in-GE-PHYs.patch | 1204 ++++++++++++++++ ...-ge-soc-initialize-MT7988-PHY-LEDs-d.patch | 213 +++ 4 files changed, 1417 insertions(+), 1345 deletions(-) delete mode 100644 target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-ge-soc.c delete mode 100644 target/linux/mediatek/patches-5.15/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch create mode 100644 target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch create mode 100644 target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch diff --git a/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-ge-soc.c b/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-ge-soc.c deleted file mode 100644 index e48502ac3f..0000000000 --- a/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-ge-soc.c +++ /dev/null @@ -1,1263 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include -#include -#include -#include -#include -#include -#include - -#define MTK_GPHY_ID_MT7981 0x03a29461 -#define MTK_GPHY_ID_MT7988 0x03a29481 - -#define MTK_EXT_PAGE_ACCESS 0x1f -#define MTK_PHY_PAGE_STANDARD 0x0000 -#define MTK_PHY_PAGE_EXTENDED_3 0x0003 - -#define MTK_PHY_LPI_REG_14 0x14 -#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) - -#define MTK_PHY_LPI_REG_1c 0x1c -#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) - -#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 - -#define ANALOG_INTERNAL_OPERATION_MAX_US 20 -#define TXRESERVE_MIN 0 -#define TXRESERVE_MAX 7 - -#define MTK_PHY_ANARG_RG 0x10 -#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) - -/* Registers on MDIO_MMD_VEND1 */ -#define MTK_PHY_TXVLD_DA_RG 0x12 -#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) -#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 -#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) -#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 -#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 -#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 -#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 -#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 -#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 -#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) - -#define MTK_PHY_RXADC_CTRL_RG7 0xc6 -#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) - -#define MTK_PHY_RXADC_CTRL_RG9 0xc8 -#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) -#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) -#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) -#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) - -#define MTK_PHY_LDO_OUTPUT_V 0xd7 - -#define MTK_PHY_RG_ANA_CAL_RG0 0xdb -#define MTK_PHY_RG_CAL_CKINV BIT(12) -#define MTK_PHY_RG_ANA_CALEN BIT(8) -#define MTK_PHY_RG_ZCALEN_A BIT(0) - -#define MTK_PHY_RG_ANA_CAL_RG1 0xdc -#define MTK_PHY_RG_ZCALEN_B BIT(12) -#define MTK_PHY_RG_ZCALEN_C BIT(8) -#define MTK_PHY_RG_ZCALEN_D BIT(4) -#define MTK_PHY_RG_TXVOS_CALEN BIT(0) - -#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 -#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) - -#define MTK_PHY_RG_TX_FILTER 0xfe - -#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 -#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) -#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) - -#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 -#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) - -#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 -#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) - -#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 -#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) -#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) - -#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 -#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) -#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) - -#define MTK_PHY_RG_AD_CAL_COMP 0x17a -#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) - -#define MTK_PHY_RG_AD_CAL_CLK 0x17b -#define MTK_PHY_DA_CAL_CLK BIT(0) - -#define MTK_PHY_RG_AD_CALIN 0x17c -#define MTK_PHY_DA_CALIN_FLAG BIT(0) - -#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d -#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e -#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f -#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 -#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 -#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 -#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 -#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 -#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DEV1E_REG19b 0x19b -#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) - -#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a -#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b -#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c -#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d -#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e -#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f -#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 -#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 -#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 -#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 - -#define MTK_PHY_RG_DEV1E_REG234 0x234 -#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) -#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) -#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) - -#define MTK_PHY_RG_LPF_CNT_VAL 0x235 - -#define MTK_PHY_RG_DEV1E_REG238 0x238 -#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) -#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) - -#define MTK_PHY_RG_DEV1E_REG239 0x239 -#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) -#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) - -#define MTK_PHY_RG_DEV1E_REG27C 0x27c -#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) -#define MTK_PHY_RG_DEV1E_REG27D 0x27d -#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) - -#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 -#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) -#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) - -#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 -#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) -#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) -#define MTK_PHY_LPI_TR_READY BIT(9) -#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) - -#define MTK_PHY_RG_DEV1E_REG323 0x323 -#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) -#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) - -#define MTK_PHY_RG_DEV1E_REG324 0x324 -#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) -#define MTK_PHY_SMI_DET_MAX_EN BIT(8) - -#define MTK_PHY_RG_DEV1E_REG326 0x326 -#define MTK_PHY_LPI_MODE_SD_ON BIT(0) -#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) -#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) -#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) -#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) - -#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 -#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 - -#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d -#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e -#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f -#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 - -/* Registers on MDIO_MMD_VEND2 */ -#define MTK_PHY_LED0_ON_CTRL 0x24 -#define MTK_PHY_LED0_ON_MASK GENMASK(6, 0) -#define MTK_PHY_LED0_ON_LINK1000 BIT(0) -#define MTK_PHY_LED0_ON_LINK100 BIT(1) -#define MTK_PHY_LED0_ON_LINK10 BIT(2) -#define MTK_PHY_LED0_ON_LINKDOWN BIT(3) -#define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */ -#define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */ -#define MTK_PHY_LED0_FORCE_ON BIT(6) -#define MTK_PHY_LED0_POLARITY BIT(14) -#define MTK_PHY_LED0_ENABLE BIT(15) - -#define MTK_PHY_LED0_BLINK_CTRL 0x25 -#define MTK_PHY_LED0_1000TX BIT(0) -#define MTK_PHY_LED0_1000RX BIT(1) -#define MTK_PHY_LED0_100TX BIT(2) -#define MTK_PHY_LED0_100RX BIT(3) -#define MTK_PHY_LED0_10TX BIT(4) -#define MTK_PHY_LED0_10RX BIT(5) -#define MTK_PHY_LED0_COLLISION BIT(6) -#define MTK_PHY_LED0_RX_CRC_ERR BIT(7) -#define MTK_PHY_LED0_RX_IDLE_ERR BIT(8) -#define MTK_PHY_LED0_FORCE_BLINK BIT(9) - -#define MTK_PHY_LED1_ON_CTRL 0x26 -#define MTK_PHY_LED1_ON_MASK GENMASK(6, 0) -#define MTK_PHY_LED1_ON_LINK1000 BIT(0) -#define MTK_PHY_LED1_ON_LINK100 BIT(1) -#define MTK_PHY_LED1_ON_LINK10 BIT(2) -#define MTK_PHY_LED1_ON_LINKDOWN BIT(3) -#define MTK_PHY_LED1_ON_FDX BIT(4) /* Full duplex */ -#define MTK_PHY_LED1_ON_HDX BIT(5) /* Half duplex */ -#define MTK_PHY_LED1_FORCE_ON BIT(6) -#define MTK_PHY_LED1_POLARITY BIT(14) -#define MTK_PHY_LED1_ENABLE BIT(15) - -#define MTK_PHY_LED1_BLINK_CTRL 0x27 -#define MTK_PHY_LED1_1000TX BIT(0) -#define MTK_PHY_LED1_1000RX BIT(1) -#define MTK_PHY_LED1_100TX BIT(2) -#define MTK_PHY_LED1_100RX BIT(3) -#define MTK_PHY_LED1_10TX BIT(4) -#define MTK_PHY_LED1_10RX BIT(5) -#define MTK_PHY_LED1_COLLISION BIT(6) -#define MTK_PHY_LED1_RX_CRC_ERR BIT(7) -#define MTK_PHY_LED1_RX_IDLE_ERR BIT(8) -#define MTK_PHY_LED1_FORCE_BLINK BIT(9) - -#define MTK_PHY_RG_BG_RASEL 0x115 -#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) - -/* These macro privides efuse parsing for internal phy. */ -#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) -#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) -#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) -#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) -#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) - -#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) -#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) -#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) -#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) -#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) - -#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) -#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) - -#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) -#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) - -enum { - NO_PAIR, - PAIR_A, - PAIR_B, - PAIR_C, - PAIR_D, -}; - -enum { - GPHY_PORT0, - GPHY_PORT1, - GPHY_PORT2, - GPHY_PORT3, -}; - -enum calibration_mode { - EFUSE_K, - SW_K -}; - -enum CAL_ITEM { - REXT, - TX_OFFSET, - TX_AMP, - TX_R50, - TX_VCM -}; - -enum CAL_MODE { - EFUSE_M, - SW_M -}; - -struct mtk_socphy_shared_priv { - u32 boottrap; -}; - -static int mtk_socphy_read_page(struct phy_device *phydev) -{ - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -} - -static int mtk_socphy_write_page(struct phy_device *phydev, int page) -{ - return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); -} - -/* One calibration cycle consists of: - * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high - * until AD_CAL_COMP is ready to output calibration result. - * 2.Wait until DA_CAL_CLK is available. - * 3.Fetch AD_CAL_COMP_OUT. - */ -static int cal_cycle(struct phy_device *phydev, int devad, - u32 regnum, u16 mask, u16 cal_val) -{ - int reg_val; - int ret; - - phy_modify_mmd(phydev, devad, regnum, - mask, cal_val); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, - MTK_PHY_DA_CALIN_FLAG); - - ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_AD_CAL_CLK, reg_val, - reg_val & MTK_PHY_DA_CAL_CLK, 500, - ANALOG_INTERNAL_OPERATION_MAX_US, false); - if (ret) { - phydev_err(phydev, "Calibration cycle timeout\n"); - return ret; - } - - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, - MTK_PHY_DA_CALIN_FLAG); - ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> - MTK_PHY_AD_CAL_COMP_OUT_SHIFT; - phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); - - return ret; -} - -static int rext_fill_result(struct phy_device *phydev, u16 *buf) -{ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, - MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, - MTK_PHY_RG_BG_RASEL_MASK, buf[1]); - - return 0; -} - -static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) -{ - u16 rext_cal_val[2]; - - rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); - rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); - rext_fill_result(phydev, rext_cal_val); - - return 0; -} - -static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) -{ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, - MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, - MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, - MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, - MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); - - return 0; -} - -static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) -{ - u16 tx_offset_cal_val[4]; - - tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); - tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); - tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); - tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); - - tx_offset_fill_result(phydev, tx_offset_cal_val); - - return 0; -} - -static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) -{ - int i; - int bias[16] = {}; - const int vals_9461[16] = { 7, 1, 4, 7, - 7, 1, 4, 7, - 7, 1, 4, 7, - 7, 1, 4, 7 }; - const int vals_9481[16] = { 10, 6, 6, 10, - 10, 6, 6, 10, - 10, 6, 6, 10, - 10, 6, 6, 10 }; - switch (phydev->drv->phy_id) { - case MTK_GPHY_ID_MT7981: - /* We add some calibration to efuse values - * due to board level influence. - * GBE: +7, TBT: +1, HBT: +4, TST: +7 - */ - memcpy(bias, (const void *)vals_9461, sizeof(bias)); - break; - case MTK_GPHY_ID_MT7988: - memcpy(bias, (const void *)vals_9481, sizeof(bias)); - break; - } - - /* Prevent overflow */ - for (i = 0; i < 12; i++) { - if (buf[i >> 2] + bias[i] > 63) { - buf[i >> 2] = 63; - bias[i] = 0; - } - } - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, - MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, - MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, - MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, - MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, - MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, - MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, - MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, - MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, - MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, - MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, - MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, - MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, - MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, - MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, - MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, - MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); - - return 0; -} - -static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) -{ - u16 tx_amp_cal_val[4]; - - tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); - tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); - tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); - tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); - tx_amp_fill_result(phydev, tx_amp_cal_val); - - return 0; -} - -static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, - u8 txg_calen_x) -{ - int bias = 0; - u16 reg, val; - - if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) - bias = -2; - - val = clamp_val(bias + tx_r50_cal_val, 0, 63); - - switch (txg_calen_x) { - case PAIR_A: - reg = MTK_PHY_DA_TX_R50_PAIR_A; - break; - case PAIR_B: - reg = MTK_PHY_DA_TX_R50_PAIR_B; - break; - case PAIR_C: - reg = MTK_PHY_DA_TX_R50_PAIR_C; - break; - case PAIR_D: - reg = MTK_PHY_DA_TX_R50_PAIR_D; - break; - default: - return -EINVAL; - } - - phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); - - return 0; -} - -static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, - u8 txg_calen_x) -{ - u16 tx_r50_cal_val; - - switch (txg_calen_x) { - case PAIR_A: - tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); - break; - case PAIR_B: - tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); - break; - case PAIR_C: - tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); - break; - case PAIR_D: - tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); - break; - default: - return -EINVAL; - } - tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); - - return 0; -} - -static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) -{ - u8 lower_idx, upper_idx, txreserve_val; - u8 lower_ret, upper_ret; - int ret; - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_ANA_CALEN); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_CAL_CKINV); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_TXVOS_CALEN); - - switch (rg_txreserve_x) { - case PAIR_A: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN0_A, - MTK_PHY_DASN_DAC_IN0_A_MASK); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN1_A, - MTK_PHY_DASN_DAC_IN1_A_MASK); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_ZCALEN_A); - break; - case PAIR_B: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN0_B, - MTK_PHY_DASN_DAC_IN0_B_MASK); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN1_B, - MTK_PHY_DASN_DAC_IN1_B_MASK); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_ZCALEN_B); - break; - case PAIR_C: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN0_C, - MTK_PHY_DASN_DAC_IN0_C_MASK); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN1_C, - MTK_PHY_DASN_DAC_IN1_C_MASK); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_ZCALEN_C); - break; - case PAIR_D: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN0_D, - MTK_PHY_DASN_DAC_IN0_D_MASK); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN1_D, - MTK_PHY_DASN_DAC_IN1_D_MASK); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_ZCALEN_D); - break; - default: - ret = -EINVAL; - goto restore; - } - - lower_idx = TXRESERVE_MIN; - upper_idx = TXRESERVE_MAX; - - phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); - while ((upper_idx - lower_idx) > 1) { - txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); - ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - txreserve_val << 12 | txreserve_val << 8 | - txreserve_val << 4 | txreserve_val); - if (ret == 1) { - upper_idx = txreserve_val; - upper_ret = ret; - } else if (ret == 0) { - lower_idx = txreserve_val; - lower_ret = ret; - } else { - goto restore; - } - } - - if (lower_idx == TXRESERVE_MIN) { - lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, - MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - lower_idx << 12 | lower_idx << 8 | - lower_idx << 4 | lower_idx); - ret = lower_ret; - } else if (upper_idx == TXRESERVE_MAX) { - upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, - MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - upper_idx << 12 | upper_idx << 8 | - upper_idx << 4 | upper_idx); - ret = upper_ret; - } - if (ret < 0) - goto restore; - - /* We calibrate TX-VCM in different logic. Check upper index and then - * lower index. If this calibration is valid, apply lower index's result. - */ - ret = upper_ret - lower_ret; - if (ret == 1) { - ret = 0; - /* Make sure we use upper_idx in our calibration system */ - cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - upper_idx << 12 | upper_idx << 8 | - upper_idx << 4 | upper_idx); - phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); - } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && - lower_ret == 1) { - ret = 0; - cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - lower_idx << 12 | lower_idx << 8 | - lower_idx << 4 | lower_idx); - phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", - lower_idx); - } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && - lower_ret == 0) { - ret = 0; - phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", - upper_idx); - } else { - ret = -EINVAL; - } - -restore: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_ANA_CALEN); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_TXVOS_CALEN); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_ZCALEN_A); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | - MTK_PHY_RG_ZCALEN_D); - - return ret; -} - -static void mt798x_phy_common_finetune(struct phy_device *phydev) -{ - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - /* EnabRandUpdTrig = 1 */ - __phy_write(phydev, 0x11, 0x2f00); - __phy_write(phydev, 0x12, 0xe); - __phy_write(phydev, 0x10, 0x8fb0); - - /* NormMseLoThresh = 85 */ - __phy_write(phydev, 0x11, 0x55a0); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x83aa); - - /* TrFreeze = 0 */ - __phy_write(phydev, 0x11, 0x0); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x9686); - - /* SSTrKp1000Slv = 5 */ - __phy_write(phydev, 0x11, 0xbaef); - __phy_write(phydev, 0x12, 0x2e); - __phy_write(phydev, 0x10, 0x968c); - - /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, - * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 - */ - __phy_write(phydev, 0x11, 0xd10a); - __phy_write(phydev, 0x12, 0x34); - __phy_write(phydev, 0x10, 0x8f82); - - /* VcoSlicerThreshBitsHigh */ - __phy_write(phydev, 0x11, 0x5555); - __phy_write(phydev, 0x12, 0x55); - __phy_write(phydev, 0x10, 0x8ec0); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, - MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, - BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); - - /* rg_tr_lpf_cnt_val = 512 */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); - - /* IIR2 related */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); - - /* FFE peaking */ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, - MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, - MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); - - /* Disable LDO pump */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); - /* Adjust LDO output voltage */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); -} - -static void mt7981_phy_finetune(struct phy_device *phydev) -{ - u16 val[8] = { 0x01ce, 0x01c1, - 0x020f, 0x0202, - 0x03d0, 0x03c0, - 0x0013, 0x0005 }; - int i, k; - - /* 100M eye finetune: - * Keep middle level of TX MLT3 shapper as default. - * Only change TX MLT3 overshoot level here. - */ - for (k = 0, i = 1; i < 12; i++) { - if (i % 3 == 0) - continue; - phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); - } - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ - __phy_write(phydev, 0x11, 0xc71); - __phy_write(phydev, 0x12, 0xc); - __phy_write(phydev, 0x10, 0x8fae); - - /* ResetSyncOffset = 6 */ - __phy_write(phydev, 0x11, 0x600); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x8fc0); - - /* VgaDecRate = 1 */ - __phy_write(phydev, 0x11, 0x4c2a); - __phy_write(phydev, 0x12, 0x3e); - __phy_write(phydev, 0x10, 0x8fa4); - - /* FfeUpdGainForce = 4 */ - __phy_write(phydev, 0x11, 0x240); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x9680); - - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -} - -static void mt7988_phy_finetune(struct phy_device *phydev) -{ - u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, - 0x020d, 0x0206, 0x0384, 0x03d0, - 0x03c6, 0x030a, 0x0011, 0x0005 }; - int i; - - /* Set default MLT3 shaper first */ - for (i = 0; i < 12; i++) - phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); - - /* TCT finetune */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); - - /* Disable TX power saving */ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, - MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - - /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ - __phy_write(phydev, 0x11, 0x671); - __phy_write(phydev, 0x12, 0xc); - __phy_write(phydev, 0x10, 0x8fae); - - /* ResetSyncOffset = 5 */ - __phy_write(phydev, 0x11, 0x500); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x8fc0); - - /* VgaDecRate is 1 at default on mt7988 */ - - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); - /* TxClkOffset = 2 */ - __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, - FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -} - -static void mt798x_phy_eee(struct phy_device *phydev) -{ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, - MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | - MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, - FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | - FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, - MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, - FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, - 0xff)); - - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_TESTMUX_ADC_CTRL, - MTK_PHY_RG_TXEN_DIG_MASK); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); - - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, - MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | - MTK_PHY_LPI_SLV_SEND_TX_EN, - FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, - MTK_PHY_LPI_SEND_LOC_TIMER_MASK | - MTK_PHY_LPI_TXPCS_LOC_RCV, - FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, - MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, - FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | - FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, - MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, - FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, - 0x33) | - MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | - MTK_PHY_LPI_VCO_EEE_STG0_EN); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, - MTK_PHY_EEE_WAKE_MAS_INT_DC | - MTK_PHY_EEE_WAKE_SLV_INT_DC); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, - MTK_PHY_SMI_DETCNT_MAX_MASK, - FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | - MTK_PHY_SMI_DET_MAX_EN); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, - MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | - MTK_PHY_TREC_UPDATE_ENAB_CLR | - MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | - MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - /* Regsigdet_sel_1000 = 0 */ - __phy_write(phydev, 0x11, 0xb); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x9690); - - /* REG_EEE_st2TrKf1000 = 3 */ - __phy_write(phydev, 0x11, 0x114f); - __phy_write(phydev, 0x12, 0x2); - __phy_write(phydev, 0x10, 0x969a); - - /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ - __phy_write(phydev, 0x11, 0x3028); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x969e); - - /* RegEEE_slv_wake_int_timer_tar = 8 */ - __phy_write(phydev, 0x11, 0x5010); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96a0); - - /* RegEEE_trfreeze_timer2 = 586 */ - __phy_write(phydev, 0x11, 0x24a); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96a8); - - /* RegEEE100Stg1_tar = 16 */ - __phy_write(phydev, 0x11, 0x3210); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96b8); - - /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ - __phy_write(phydev, 0x11, 0x1463); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96ca); - - /* DfeTailEnableVgaThresh1000 = 27 */ - __phy_write(phydev, 0x11, 0x36); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x8f80); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); - __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, - FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); - - __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, - FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, - MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, - FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); -} - -static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, - u8 start_pair, u8 end_pair) -{ - u8 pair_n; - int ret; - - for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { - /* TX_OFFSET & TX_AMP have no SW calibration. */ - switch (cal_item) { - case TX_VCM: - ret = tx_vcm_cal_sw(phydev, pair_n); - break; - default: - return -EINVAL; - } - if (ret) - return ret; - } - return 0; -} - -static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, - u8 start_pair, u8 end_pair, u32 *buf) -{ - u8 pair_n; - int ret; - - for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { - /* TX_VCM has no efuse calibration. */ - switch (cal_item) { - case REXT: - ret = rext_cal_efuse(phydev, buf); - break; - case TX_OFFSET: - ret = tx_offset_cal_efuse(phydev, buf); - break; - case TX_AMP: - ret = tx_amp_cal_efuse(phydev, buf); - break; - case TX_R50: - ret = tx_r50_cal_efuse(phydev, buf, pair_n); - break; - default: - return -EINVAL; - } - if (ret) - return ret; - } - - return 0; -} - -static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, - enum CAL_MODE cal_mode, u8 start_pair, - u8 end_pair, u32 *buf) -{ - int ret; - - switch (cal_mode) { - case EFUSE_M: - ret = cal_efuse(phydev, cal_item, start_pair, - end_pair, buf); - break; - case SW_M: - ret = cal_sw(phydev, cal_item, start_pair, end_pair); - break; - default: - return -EINVAL; - } - - if (ret) { - phydev_err(phydev, "cal %d failed\n", cal_item); - return -EIO; - } - - return 0; -} - -static int mt798x_phy_calibration(struct phy_device *phydev) -{ - int ret = 0; - u32 *buf; - size_t len; - struct nvmem_cell *cell; - - cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); - if (IS_ERR(cell)) { - if (PTR_ERR(cell) == -EPROBE_DEFER) - return PTR_ERR(cell); - return 0; - } - - buf = (u32 *)nvmem_cell_read(cell, &len); - if (IS_ERR(buf)) - return PTR_ERR(buf); - nvmem_cell_put(cell); - - if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { - phydev_err(phydev, "invalid efuse data\n"); - ret = -EINVAL; - goto out; - } - - ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); - if (ret) - goto out; - ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); - if (ret) - goto out; - ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); - if (ret) - goto out; - ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); - if (ret) - goto out; - ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); - if (ret) - goto out; - -out: - kfree(buf); - return ret; -} - -static int mt798x_phy_config_init(struct phy_device *phydev) -{ - switch (phydev->drv->phy_id) { - case MTK_GPHY_ID_MT7981: - mt7981_phy_finetune(phydev); - break; - case MTK_GPHY_ID_MT7988: - mt7988_phy_finetune(phydev); - break; - } - - mt798x_phy_common_finetune(phydev); - mt798x_phy_eee(phydev); - - return mt798x_phy_calibration(phydev); -} - -static int mt7988_phy_setup_led(struct phy_device *phydev) -{ - struct mtk_socphy_shared_priv *priv = phydev->shared->priv; - int port = phydev->mdio.addr; - u32 reg = priv->boottrap; - struct pinctrl *pinctrl; - - phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY | - MTK_PHY_LED0_ON_LINK10 | - MTK_PHY_LED0_ON_LINK100 | - MTK_PHY_LED0_ON_LINK1000); - phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, - MTK_PHY_LED1_ENABLE | MTK_PHY_LED1_POLARITY | - MTK_PHY_LED1_ON_LINK10 | - MTK_PHY_LED1_ON_LINK100 | - MTK_PHY_LED1_ON_LINK1000); - - if ((port == GPHY_PORT0 && reg & BIT(8)) || - (port == GPHY_PORT1 && reg & BIT(9)) || - (port == GPHY_PORT2 && reg & BIT(10)) || - (port == GPHY_PORT3 && reg & BIT(11))) { - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_POLARITY); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, - MTK_PHY_LED1_POLARITY); - } - - phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, - MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX | - MTK_PHY_LED0_100TX | MTK_PHY_LED0_100RX | - MTK_PHY_LED0_10TX | MTK_PHY_LED0_10RX); - phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL, - MTK_PHY_LED1_1000TX | MTK_PHY_LED1_1000RX | - MTK_PHY_LED1_100TX | MTK_PHY_LED1_100RX | - MTK_PHY_LED1_10TX | MTK_PHY_LED1_10RX); - - pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); - if (IS_ERR(pinctrl)) { - dev_err(&phydev->mdio.bus->dev, "Failed to setup LED pins\n"); - return PTR_ERR(pinctrl); - } - - return 0; -} - -static int mt7988_phy_probe_shared(struct phy_device *phydev) -{ - struct mtk_socphy_shared_priv *priv = phydev->shared->priv; - void __iomem *boottrap; - struct device_node *np; - u32 reg; - - np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap"); - if (!np) - return -ENOENT; - - boottrap = of_iomap(np, 0); - if (!boottrap) - return -ENOMEM; - - reg = readl(boottrap); - iounmap(boottrap); - - priv->boottrap = reg; - - return 0; -} - -static int mt7981_phy_probe(struct phy_device *phydev) -{ - return mt798x_phy_calibration(phydev); -} - -static int mt7988_phy_probe(struct phy_device *phydev) -{ - int err; - - err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, - sizeof(struct mtk_socphy_shared_priv)); - if (err) - return err; - - if (phy_package_probe_once(phydev)) { - err = mt7988_phy_probe_shared(phydev); - if (err) - return err; - } - - mt7988_phy_setup_led(phydev); - - return mt798x_phy_calibration(phydev); -} - -static struct phy_driver mtk_socphy_driver[] = { - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), - .name = "MediaTek MT7981 PHY", - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, - .probe = mt7981_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, - .write_page = mtk_socphy_write_page, - }, - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), - .name = "MediaTek MT7988 PHY", - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, - .probe = mt7988_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, - .write_page = mtk_socphy_write_page, - }, -}; - -module_phy_driver(mtk_socphy_driver); - -static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, - { } -}; - -MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); -MODULE_AUTHOR("Daniel Golle "); -MODULE_AUTHOR("SkyLake Huang "); -MODULE_LICENSE("GPL"); - -MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); diff --git a/target/linux/mediatek/patches-5.15/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-5.15/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch deleted file mode 100644 index 0f06c29867..0000000000 --- a/target/linux/mediatek/patches-5.15/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 60ed9eb9605656c19ca402b7bd3f47552e901601 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 13 Feb 2023 02:33:14 +0000 -Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs - -Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet -PHYs which require calibration data from the SoC's efuse. -Despite the similar design the driver doesn't share any code with the -existing mediatek-ge.c, so add support for these PHYs by introducing a -new driver for only MediaTek's ARM64 SoCs. - -Signed-off-by: Daniel Golle ---- - MAINTAINERS | 9 + - drivers/net/phy/Kconfig | 12 + - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mediatek-ge-soc.c | 1263 +++++++++++++++++++++++++++++ - drivers/net/phy/mediatek-ge.c | 3 +- - 5 files changed, 1287 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/phy/mediatek-ge-soc.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -11790,6 +11790,15 @@ S: Maintained - F: drivers/net/pcs/pcs-mtk-lynxi.c - F: include/linux/pcs/pcs-mtk-lynxi.h - -+MEDIATEK ETHERNET PHY DRIVERS -+M: Daniel Golle -+M: Qingfang Deng -+M: SkyLake Huang -+L: netdev@vger.kernel.org -+S: Maintained -+F: drivers/net/phy/mediatek-ge-soc.c -+F: drivers/net/phy/mediatek-ge.c -+ - MEDIATEK I2C CONTROLLER DRIVER - M: Qii Wang - L: linux-i2c@vger.kernel.org ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -292,6 +292,18 @@ config MEDIATEK_GE_PHY - help - Supports the MediaTek Gigabit Ethernet PHYs. - -+config MEDIATEK_GE_SOC_PHY -+ tristate "MediaTek SoC Ethernet PHYs" -+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST -+ select NVMEM_MTK_EFUSE -+ help -+ Supports MediaTek SoC built-in Gigabit Ethernet PHYs. -+ -+ Include support for built-in Ethernet PHYs which are present in -+ the MT7981 and MT7988 SoCs. These PHYs need calibration data -+ present in the SoCs efuse and will dynamically calibrate VCM -+ (common-mode voltage) during startup. -+ - config MICREL_PHY - tristate "Micrel PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -81,6 +81,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o - obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o - obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o - obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o -+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o - obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o - obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o - obj-$(CONFIG_MICREL_PHY) += micrel.o ---- a/drivers/net/phy/mediatek-ge.c -+++ b/drivers/net/phy/mediatek-ge.c -@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive - module_phy_driver(mtk_gephy_driver); - - static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { -- { PHY_ID_MATCH_VENDOR(0x03a29400) }, -+ { PHY_ID_MATCH_EXACT(0x03a29441) }, -+ { PHY_ID_MATCH_EXACT(0x03a29412) }, - { } - }; - diff --git a/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch new file mode 100644 index 0000000000..26ebcb6733 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch @@ -0,0 +1,1204 @@ +From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 11 Jun 2023 00:48:10 +0100 +Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs + +Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet +PHYs which require calibration data from the SoC's efuse. +Despite the similar design the driver doesn't share any code with the +existing mediatek-ge.c. +Add support for such PHYs by introducing a new driver with basic +support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + MAINTAINERS | 9 + + drivers/net/phy/Kconfig | 12 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++ + drivers/net/phy/mediatek-ge.c | 3 +- + 5 files changed, 1140 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/phy/mediatek-ge-soc.c + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -11790,6 +11790,15 @@ S: Maintained + F: drivers/net/pcs/pcs-mtk-lynxi.c + F: include/linux/pcs/pcs-mtk-lynxi.h + ++MEDIATEK ETHERNET PHY DRIVERS ++M: Daniel Golle ++M: Qingfang Deng ++M: SkyLake Huang ++L: netdev@vger.kernel.org ++S: Maintained ++F: drivers/net/phy/mediatek-ge-soc.c ++F: drivers/net/phy/mediatek-ge.c ++ + MEDIATEK I2C CONTROLLER DRIVER + M: Qii Wang + L: linux-i2c@vger.kernel.org +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -293,6 +293,18 @@ config MEDIATEK_GE_PHY + help + Supports the MediaTek Gigabit Ethernet PHYs. + ++config MEDIATEK_GE_SOC_PHY ++ tristate "MediaTek SoC Ethernet PHYs" ++ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST ++ select NVMEM_MTK_EFUSE ++ help ++ Supports MediaTek SoC built-in Gigabit Ethernet PHYs. ++ ++ Include support for built-in Ethernet PHYs which are present in ++ the MT7981 and MT7988 SoCs. These PHYs need calibration data ++ present in the SoCs efuse and will dynamically calibrate VCM ++ (common-mode voltage) during startup. ++ + config MICREL_PHY + tristate "Micrel PHYs" + help +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -81,6 +81,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o + obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o + obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o + obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o ++obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o + obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o + obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o + obj-$(CONFIG_MICREL_PHY) += micrel.o +--- /dev/null ++++ b/drivers/net/phy/mediatek-ge-soc.c +@@ -0,0 +1,1116 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MTK_GPHY_ID_MT7981 0x03a29461 ++#define MTK_GPHY_ID_MT7988 0x03a29481 ++ ++#define MTK_EXT_PAGE_ACCESS 0x1f ++#define MTK_PHY_PAGE_STANDARD 0x0000 ++#define MTK_PHY_PAGE_EXTENDED_3 0x0003 ++ ++#define MTK_PHY_LPI_REG_14 0x14 ++#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) ++ ++#define MTK_PHY_LPI_REG_1c 0x1c ++#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) ++ ++#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 ++#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 ++ ++#define ANALOG_INTERNAL_OPERATION_MAX_US 20 ++#define TXRESERVE_MIN 0 ++#define TXRESERVE_MAX 7 ++ ++#define MTK_PHY_ANARG_RG 0x10 ++#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) ++ ++/* Registers on MDIO_MMD_VEND1 */ ++#define MTK_PHY_TXVLD_DA_RG 0x12 ++#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) ++#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 ++#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) ++#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 ++#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 ++#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 ++#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 ++#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 ++#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 ++#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_RXADC_CTRL_RG7 0xc6 ++#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) ++ ++#define MTK_PHY_RXADC_CTRL_RG9 0xc8 ++#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) ++#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) ++#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) ++#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) ++ ++#define MTK_PHY_LDO_OUTPUT_V 0xd7 ++ ++#define MTK_PHY_RG_ANA_CAL_RG0 0xdb ++#define MTK_PHY_RG_CAL_CKINV BIT(12) ++#define MTK_PHY_RG_ANA_CALEN BIT(8) ++#define MTK_PHY_RG_ZCALEN_A BIT(0) ++ ++#define MTK_PHY_RG_ANA_CAL_RG1 0xdc ++#define MTK_PHY_RG_ZCALEN_B BIT(12) ++#define MTK_PHY_RG_ZCALEN_C BIT(8) ++#define MTK_PHY_RG_ZCALEN_D BIT(4) ++#define MTK_PHY_RG_TXVOS_CALEN BIT(0) ++ ++#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 ++#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) ++ ++#define MTK_PHY_RG_TX_FILTER 0xfe ++ ++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 ++#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) ++#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) ++ ++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 ++#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) ++ ++#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 ++#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) ++ ++#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 ++#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) ++#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) ++ ++#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 ++#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) ++#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) ++ ++#define MTK_PHY_RG_AD_CAL_COMP 0x17a ++#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) ++ ++#define MTK_PHY_RG_AD_CAL_CLK 0x17b ++#define MTK_PHY_DA_CAL_CLK BIT(0) ++ ++#define MTK_PHY_RG_AD_CALIN 0x17c ++#define MTK_PHY_DA_CALIN_FLAG BIT(0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d ++#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e ++#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f ++#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 ++#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 ++#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 ++#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 ++#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 ++#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DEV1E_REG19b 0x19b ++#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) ++ ++#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a ++#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b ++#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c ++#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d ++#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e ++#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f ++#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 ++#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 ++#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 ++#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 ++ ++#define MTK_PHY_RG_DEV1E_REG234 0x234 ++#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) ++#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) ++#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) ++ ++#define MTK_PHY_RG_LPF_CNT_VAL 0x235 ++ ++#define MTK_PHY_RG_DEV1E_REG238 0x238 ++#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) ++#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) ++ ++#define MTK_PHY_RG_DEV1E_REG239 0x239 ++#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) ++#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) ++ ++#define MTK_PHY_RG_DEV1E_REG27C 0x27c ++#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) ++#define MTK_PHY_RG_DEV1E_REG27D 0x27d ++#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) ++ ++#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 ++#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) ++#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) ++ ++#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 ++#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) ++#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) ++#define MTK_PHY_LPI_TR_READY BIT(9) ++#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) ++ ++#define MTK_PHY_RG_DEV1E_REG323 0x323 ++#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) ++#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) ++ ++#define MTK_PHY_RG_DEV1E_REG324 0x324 ++#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) ++#define MTK_PHY_SMI_DET_MAX_EN BIT(8) ++ ++#define MTK_PHY_RG_DEV1E_REG326 0x326 ++#define MTK_PHY_LPI_MODE_SD_ON BIT(0) ++#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) ++#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) ++#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) ++#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) ++ ++#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 ++#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 ++ ++#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d ++#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e ++#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f ++#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 ++ ++#define MTK_PHY_RG_BG_RASEL 0x115 ++#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) ++ ++/* These macro privides efuse parsing for internal phy. */ ++#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) ++#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) ++#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) ++#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) ++#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) ++ ++#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) ++#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) ++#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) ++#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) ++#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) ++ ++#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) ++#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) ++ ++#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) ++#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) ++ ++enum { ++ NO_PAIR, ++ PAIR_A, ++ PAIR_B, ++ PAIR_C, ++ PAIR_D, ++}; ++ ++enum { ++ GPHY_PORT0, ++ GPHY_PORT1, ++ GPHY_PORT2, ++ GPHY_PORT3, ++}; ++ ++enum calibration_mode { ++ EFUSE_K, ++ SW_K ++}; ++ ++enum CAL_ITEM { ++ REXT, ++ TX_OFFSET, ++ TX_AMP, ++ TX_R50, ++ TX_VCM ++}; ++ ++enum CAL_MODE { ++ EFUSE_M, ++ SW_M ++}; ++ ++static int mtk_socphy_read_page(struct phy_device *phydev) ++{ ++ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); ++} ++ ++static int mtk_socphy_write_page(struct phy_device *phydev, int page) ++{ ++ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); ++} ++ ++/* One calibration cycle consists of: ++ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high ++ * until AD_CAL_COMP is ready to output calibration result. ++ * 2.Wait until DA_CAL_CLK is available. ++ * 3.Fetch AD_CAL_COMP_OUT. ++ */ ++static int cal_cycle(struct phy_device *phydev, int devad, ++ u32 regnum, u16 mask, u16 cal_val) ++{ ++ int reg_val; ++ int ret; ++ ++ phy_modify_mmd(phydev, devad, regnum, ++ mask, cal_val); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, ++ MTK_PHY_DA_CALIN_FLAG); ++ ++ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_AD_CAL_CLK, reg_val, ++ reg_val & MTK_PHY_DA_CAL_CLK, 500, ++ ANALOG_INTERNAL_OPERATION_MAX_US, false); ++ if (ret) { ++ phydev_err(phydev, "Calibration cycle timeout\n"); ++ return ret; ++ } ++ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, ++ MTK_PHY_DA_CALIN_FLAG); ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> ++ MTK_PHY_AD_CAL_COMP_OUT_SHIFT; ++ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); ++ ++ return ret; ++} ++ ++static int rext_fill_result(struct phy_device *phydev, u16 *buf) ++{ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, ++ MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, ++ MTK_PHY_RG_BG_RASEL_MASK, buf[1]); ++ ++ return 0; ++} ++ ++static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) ++{ ++ u16 rext_cal_val[2]; ++ ++ rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); ++ rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); ++ rext_fill_result(phydev, rext_cal_val); ++ ++ return 0; ++} ++ ++static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) ++{ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, ++ MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, ++ MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, ++ MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, ++ MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); ++ ++ return 0; ++} ++ ++static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) ++{ ++ u16 tx_offset_cal_val[4]; ++ ++ tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); ++ tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); ++ tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); ++ tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); ++ ++ tx_offset_fill_result(phydev, tx_offset_cal_val); ++ ++ return 0; ++} ++ ++static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) ++{ ++ int i; ++ int bias[16] = {}; ++ const int vals_9461[16] = { 7, 1, 4, 7, ++ 7, 1, 4, 7, ++ 7, 1, 4, 7, ++ 7, 1, 4, 7 }; ++ const int vals_9481[16] = { 10, 6, 6, 10, ++ 10, 6, 6, 10, ++ 10, 6, 6, 10, ++ 10, 6, 6, 10 }; ++ switch (phydev->drv->phy_id) { ++ case MTK_GPHY_ID_MT7981: ++ /* We add some calibration to efuse values ++ * due to board level influence. ++ * GBE: +7, TBT: +1, HBT: +4, TST: +7 ++ */ ++ memcpy(bias, (const void *)vals_9461, sizeof(bias)); ++ break; ++ case MTK_GPHY_ID_MT7988: ++ memcpy(bias, (const void *)vals_9481, sizeof(bias)); ++ break; ++ } ++ ++ /* Prevent overflow */ ++ for (i = 0; i < 12; i++) { ++ if (buf[i >> 2] + bias[i] > 63) { ++ buf[i >> 2] = 63; ++ bias[i] = 0; ++ } ++ } ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, ++ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, ++ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, ++ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, ++ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, ++ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, ++ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, ++ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, ++ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, ++ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, ++ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, ++ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, ++ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, ++ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, ++ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, ++ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, ++ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); ++ ++ return 0; ++} ++ ++static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) ++{ ++ u16 tx_amp_cal_val[4]; ++ ++ tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); ++ tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); ++ tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); ++ tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); ++ tx_amp_fill_result(phydev, tx_amp_cal_val); ++ ++ return 0; ++} ++ ++static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, ++ u8 txg_calen_x) ++{ ++ int bias = 0; ++ u16 reg, val; ++ ++ if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) ++ bias = -2; ++ ++ val = clamp_val(bias + tx_r50_cal_val, 0, 63); ++ ++ switch (txg_calen_x) { ++ case PAIR_A: ++ reg = MTK_PHY_DA_TX_R50_PAIR_A; ++ break; ++ case PAIR_B: ++ reg = MTK_PHY_DA_TX_R50_PAIR_B; ++ break; ++ case PAIR_C: ++ reg = MTK_PHY_DA_TX_R50_PAIR_C; ++ break; ++ case PAIR_D: ++ reg = MTK_PHY_DA_TX_R50_PAIR_D; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); ++ ++ return 0; ++} ++ ++static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, ++ u8 txg_calen_x) ++{ ++ u16 tx_r50_cal_val; ++ ++ switch (txg_calen_x) { ++ case PAIR_A: ++ tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); ++ break; ++ case PAIR_B: ++ tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); ++ break; ++ case PAIR_C: ++ tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); ++ break; ++ case PAIR_D: ++ tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); ++ break; ++ default: ++ return -EINVAL; ++ } ++ tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); ++ ++ return 0; ++} ++ ++static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) ++{ ++ u8 lower_idx, upper_idx, txreserve_val; ++ u8 lower_ret, upper_ret; ++ int ret; ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ANA_CALEN); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_CAL_CKINV); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_TXVOS_CALEN); ++ ++ switch (rg_txreserve_x) { ++ case PAIR_A: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_A, ++ MTK_PHY_DASN_DAC_IN0_A_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_A, ++ MTK_PHY_DASN_DAC_IN1_A_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ZCALEN_A); ++ break; ++ case PAIR_B: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_B, ++ MTK_PHY_DASN_DAC_IN0_B_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_B, ++ MTK_PHY_DASN_DAC_IN1_B_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_B); ++ break; ++ case PAIR_C: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_C, ++ MTK_PHY_DASN_DAC_IN0_C_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_C, ++ MTK_PHY_DASN_DAC_IN1_C_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_C); ++ break; ++ case PAIR_D: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_D, ++ MTK_PHY_DASN_DAC_IN0_D_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_D, ++ MTK_PHY_DASN_DAC_IN1_D_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_D); ++ break; ++ default: ++ ret = -EINVAL; ++ goto restore; ++ } ++ ++ lower_idx = TXRESERVE_MIN; ++ upper_idx = TXRESERVE_MAX; ++ ++ phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); ++ while ((upper_idx - lower_idx) > 1) { ++ txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); ++ ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ txreserve_val << 12 | txreserve_val << 8 | ++ txreserve_val << 4 | txreserve_val); ++ if (ret == 1) { ++ upper_idx = txreserve_val; ++ upper_ret = ret; ++ } else if (ret == 0) { ++ lower_idx = txreserve_val; ++ lower_ret = ret; ++ } else { ++ goto restore; ++ } ++ } ++ ++ if (lower_idx == TXRESERVE_MIN) { ++ lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ lower_idx << 12 | lower_idx << 8 | ++ lower_idx << 4 | lower_idx); ++ ret = lower_ret; ++ } else if (upper_idx == TXRESERVE_MAX) { ++ upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ upper_idx << 12 | upper_idx << 8 | ++ upper_idx << 4 | upper_idx); ++ ret = upper_ret; ++ } ++ if (ret < 0) ++ goto restore; ++ ++ /* We calibrate TX-VCM in different logic. Check upper index and then ++ * lower index. If this calibration is valid, apply lower index's result. ++ */ ++ ret = upper_ret - lower_ret; ++ if (ret == 1) { ++ ret = 0; ++ /* Make sure we use upper_idx in our calibration system */ ++ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ upper_idx << 12 | upper_idx << 8 | ++ upper_idx << 4 | upper_idx); ++ phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); ++ } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && ++ lower_ret == 1) { ++ ret = 0; ++ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ lower_idx << 12 | lower_idx << 8 | ++ lower_idx << 4 | lower_idx); ++ phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", ++ lower_idx); ++ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && ++ lower_ret == 0) { ++ ret = 0; ++ phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", ++ upper_idx); ++ } else { ++ ret = -EINVAL; ++ } ++ ++restore: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ANA_CALEN); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_TXVOS_CALEN); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ZCALEN_A); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | ++ MTK_PHY_RG_ZCALEN_D); ++ ++ return ret; ++} ++ ++static void mt798x_phy_common_finetune(struct phy_device *phydev) ++{ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* EnabRandUpdTrig = 1 */ ++ __phy_write(phydev, 0x11, 0x2f00); ++ __phy_write(phydev, 0x12, 0xe); ++ __phy_write(phydev, 0x10, 0x8fb0); ++ ++ /* NormMseLoThresh = 85 */ ++ __phy_write(phydev, 0x11, 0x55a0); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x83aa); ++ ++ /* TrFreeze = 0 */ ++ __phy_write(phydev, 0x11, 0x0); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9686); ++ ++ /* SSTrKp1000Slv = 5 */ ++ __phy_write(phydev, 0x11, 0xbaef); ++ __phy_write(phydev, 0x12, 0x2e); ++ __phy_write(phydev, 0x10, 0x968c); ++ ++ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, ++ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 ++ */ ++ __phy_write(phydev, 0x11, 0xd10a); ++ __phy_write(phydev, 0x12, 0x34); ++ __phy_write(phydev, 0x10, 0x8f82); ++ ++ /* VcoSlicerThreshBitsHigh */ ++ __phy_write(phydev, 0x11, 0x5555); ++ __phy_write(phydev, 0x12, 0x55); ++ __phy_write(phydev, 0x10, 0x8ec0); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, ++ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, ++ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); ++ ++ /* rg_tr_lpf_cnt_val = 512 */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); ++ ++ /* IIR2 related */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); ++ ++ /* FFE peaking */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, ++ MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, ++ MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); ++ ++ /* Disable LDO pump */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); ++ /* Adjust LDO output voltage */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); ++} ++ ++static void mt7981_phy_finetune(struct phy_device *phydev) ++{ ++ u16 val[8] = { 0x01ce, 0x01c1, ++ 0x020f, 0x0202, ++ 0x03d0, 0x03c0, ++ 0x0013, 0x0005 }; ++ int i, k; ++ ++ /* 100M eye finetune: ++ * Keep middle level of TX MLT3 shapper as default. ++ * Only change TX MLT3 overshoot level here. ++ */ ++ for (k = 0, i = 1; i < 12; i++) { ++ if (i % 3 == 0) ++ continue; ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); ++ } ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ ++ __phy_write(phydev, 0x11, 0xc71); ++ __phy_write(phydev, 0x12, 0xc); ++ __phy_write(phydev, 0x10, 0x8fae); ++ ++ /* ResetSyncOffset = 6 */ ++ __phy_write(phydev, 0x11, 0x600); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8fc0); ++ ++ /* VgaDecRate = 1 */ ++ __phy_write(phydev, 0x11, 0x4c2a); ++ __phy_write(phydev, 0x12, 0x3e); ++ __phy_write(phydev, 0x10, 0x8fa4); ++ ++ /* FfeUpdGainForce = 4 */ ++ __phy_write(phydev, 0x11, 0x240); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9680); ++ ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++} ++ ++static void mt7988_phy_finetune(struct phy_device *phydev) ++{ ++ u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, ++ 0x020d, 0x0206, 0x0384, 0x03d0, ++ 0x03c6, 0x030a, 0x0011, 0x0005 }; ++ int i; ++ ++ /* Set default MLT3 shaper first */ ++ for (i = 0; i < 12; i++) ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); ++ ++ /* TCT finetune */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); ++ ++ /* Disable TX power saving */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, ++ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ ++ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ ++ __phy_write(phydev, 0x11, 0x671); ++ __phy_write(phydev, 0x12, 0xc); ++ __phy_write(phydev, 0x10, 0x8fae); ++ ++ /* ResetSyncOffset = 5 */ ++ __phy_write(phydev, 0x11, 0x500); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8fc0); ++ ++ /* VgaDecRate is 1 at default on mt7988 */ ++ ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); ++ /* TxClkOffset = 2 */ ++ __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, ++ FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++} ++ ++static void mt798x_phy_eee(struct phy_device *phydev) ++{ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, ++ MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | ++ MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | ++ FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, ++ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ 0xff)); ++ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_TESTMUX_ADC_CTRL, ++ MTK_PHY_RG_TXEN_DIG_MASK); ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); ++ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, ++ MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | ++ MTK_PHY_LPI_SLV_SEND_TX_EN, ++ FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, ++ MTK_PHY_LPI_SEND_LOC_TIMER_MASK | ++ MTK_PHY_LPI_TXPCS_LOC_RCV, ++ FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, ++ MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, ++ FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | ++ FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, ++ MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, ++ FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, ++ 0x33) | ++ MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | ++ MTK_PHY_LPI_VCO_EEE_STG0_EN); ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, ++ MTK_PHY_EEE_WAKE_MAS_INT_DC | ++ MTK_PHY_EEE_WAKE_SLV_INT_DC); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, ++ MTK_PHY_SMI_DETCNT_MAX_MASK, ++ FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | ++ MTK_PHY_SMI_DET_MAX_EN); ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, ++ MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | ++ MTK_PHY_TREC_UPDATE_ENAB_CLR | ++ MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | ++ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* Regsigdet_sel_1000 = 0 */ ++ __phy_write(phydev, 0x11, 0xb); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9690); ++ ++ /* REG_EEE_st2TrKf1000 = 3 */ ++ __phy_write(phydev, 0x11, 0x114f); ++ __phy_write(phydev, 0x12, 0x2); ++ __phy_write(phydev, 0x10, 0x969a); ++ ++ /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ ++ __phy_write(phydev, 0x11, 0x3028); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x969e); ++ ++ /* RegEEE_slv_wake_int_timer_tar = 8 */ ++ __phy_write(phydev, 0x11, 0x5010); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96a0); ++ ++ /* RegEEE_trfreeze_timer2 = 586 */ ++ __phy_write(phydev, 0x11, 0x24a); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96a8); ++ ++ /* RegEEE100Stg1_tar = 16 */ ++ __phy_write(phydev, 0x11, 0x3210); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96b8); ++ ++ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ ++ __phy_write(phydev, 0x11, 0x1463); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96ca); ++ ++ /* DfeTailEnableVgaThresh1000 = 27 */ ++ __phy_write(phydev, 0x11, 0x36); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8f80); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); ++ __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); ++ ++ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, ++ FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, ++ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); ++} ++ ++static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, ++ u8 start_pair, u8 end_pair) ++{ ++ u8 pair_n; ++ int ret; ++ ++ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { ++ /* TX_OFFSET & TX_AMP have no SW calibration. */ ++ switch (cal_item) { ++ case TX_VCM: ++ ret = tx_vcm_cal_sw(phydev, pair_n); ++ break; ++ default: ++ return -EINVAL; ++ } ++ if (ret) ++ return ret; ++ } ++ return 0; ++} ++ ++static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, ++ u8 start_pair, u8 end_pair, u32 *buf) ++{ ++ u8 pair_n; ++ int ret; ++ ++ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { ++ /* TX_VCM has no efuse calibration. */ ++ switch (cal_item) { ++ case REXT: ++ ret = rext_cal_efuse(phydev, buf); ++ break; ++ case TX_OFFSET: ++ ret = tx_offset_cal_efuse(phydev, buf); ++ break; ++ case TX_AMP: ++ ret = tx_amp_cal_efuse(phydev, buf); ++ break; ++ case TX_R50: ++ ret = tx_r50_cal_efuse(phydev, buf, pair_n); ++ break; ++ default: ++ return -EINVAL; ++ } ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, ++ enum CAL_MODE cal_mode, u8 start_pair, ++ u8 end_pair, u32 *buf) ++{ ++ int ret; ++ ++ switch (cal_mode) { ++ case EFUSE_M: ++ ret = cal_efuse(phydev, cal_item, start_pair, ++ end_pair, buf); ++ break; ++ case SW_M: ++ ret = cal_sw(phydev, cal_item, start_pair, end_pair); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (ret) { ++ phydev_err(phydev, "cal %d failed\n", cal_item); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++static int mt798x_phy_calibration(struct phy_device *phydev) ++{ ++ int ret = 0; ++ u32 *buf; ++ size_t len; ++ struct nvmem_cell *cell; ++ ++ cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); ++ if (IS_ERR(cell)) { ++ if (PTR_ERR(cell) == -EPROBE_DEFER) ++ return PTR_ERR(cell); ++ return 0; ++ } ++ ++ buf = (u32 *)nvmem_cell_read(cell, &len); ++ if (IS_ERR(buf)) ++ return PTR_ERR(buf); ++ nvmem_cell_put(cell); ++ ++ if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { ++ phydev_err(phydev, "invalid efuse data\n"); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); ++ if (ret) ++ goto out; ++ ++out: ++ kfree(buf); ++ return ret; ++} ++ ++static int mt798x_phy_config_init(struct phy_device *phydev) ++{ ++ switch (phydev->drv->phy_id) { ++ case MTK_GPHY_ID_MT7981: ++ mt7981_phy_finetune(phydev); ++ break; ++ case MTK_GPHY_ID_MT7988: ++ mt7988_phy_finetune(phydev); ++ break; ++ } ++ ++ mt798x_phy_common_finetune(phydev); ++ mt798x_phy_eee(phydev); ++ ++ return mt798x_phy_calibration(phydev); ++} ++ ++static struct phy_driver mtk_socphy_driver[] = { ++ { ++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), ++ .name = "MediaTek MT7981 PHY", ++ .config_init = mt798x_phy_config_init, ++ .config_intr = genphy_no_config_intr, ++ .handle_interrupt = genphy_handle_interrupt_no_ack, ++ .probe = mt798x_phy_calibration, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_page = mtk_socphy_read_page, ++ .write_page = mtk_socphy_write_page, ++ }, ++ { ++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), ++ .name = "MediaTek MT7988 PHY", ++ .config_init = mt798x_phy_config_init, ++ .config_intr = genphy_no_config_intr, ++ .handle_interrupt = genphy_handle_interrupt_no_ack, ++ .probe = mt798x_phy_calibration, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_page = mtk_socphy_read_page, ++ .write_page = mtk_socphy_write_page, ++ }, ++}; ++ ++module_phy_driver(mtk_socphy_driver); ++ ++static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { ++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, ++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, ++ { } ++}; ++ ++MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); ++MODULE_AUTHOR("Daniel Golle "); ++MODULE_AUTHOR("SkyLake Huang "); ++MODULE_LICENSE("GPL"); ++ ++MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); +--- a/drivers/net/phy/mediatek-ge.c ++++ b/drivers/net/phy/mediatek-ge.c +@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive + module_phy_driver(mtk_gephy_driver); + + static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { +- { PHY_ID_MATCH_VENDOR(0x03a29400) }, ++ { PHY_ID_MATCH_EXACT(0x03a29441) }, ++ { PHY_ID_MATCH_EXACT(0x03a29412) }, + { } + }; + diff --git a/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch b/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch new file mode 100644 index 0000000000..83d0f26bf4 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch @@ -0,0 +1,213 @@ +From 5d2d78860f98eb5c03bc404eb024606878901ac8 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 13 Jun 2023 03:27:14 +0100 +Subject: [PATCH] net: phy: mediatek-ge-soc: initialize MT7988 PHY LEDs default + state + +Initialize LEDs and set sane default values. +Read boottrap register and apply LED polarities accordingly to get +uniform behavior from all LEDs on MT7988. +Requires syscon phandle 'mediatek,pio' present in parenting MDIO bus +which should point to the syscon holding the boottrap register. + +Signed-off-by: Daniel Golle +--- + drivers/net/phy/mediatek-ge-soc.c | 144 ++++++++++++++++++++++++++++-- + 1 file changed, 136 insertions(+), 8 deletions(-) + +--- a/drivers/net/phy/mediatek-ge-soc.c ++++ b/drivers/net/phy/mediatek-ge-soc.c +@@ -1,11 +1,13 @@ + // SPDX-License-Identifier: GPL-2.0+ + #include ++#include + #include + #include + #include + #include + #include + #include ++#include + + #define MTK_GPHY_ID_MT7981 0x03a29461 + #define MTK_GPHY_ID_MT7988 0x03a29481 +@@ -208,9 +210,40 @@ + #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f + #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 + ++/* Registers on MDIO_MMD_VEND2 */ ++#define MTK_PHY_LED0_ON_CTRL 0x24 ++#define MTK_PHY_LED1_ON_CTRL 0x26 ++#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) ++#define MTK_PHY_LED_ON_LINK1000 BIT(0) ++#define MTK_PHY_LED_ON_LINK100 BIT(1) ++#define MTK_PHY_LED_ON_LINK10 BIT(2) ++#define MTK_PHY_LED_ON_LINKDOWN BIT(3) ++#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ ++#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ ++#define MTK_PHY_LED_FORCE_ON BIT(6) ++#define MTK_PHY_LED_POLARITY BIT(14) ++#define MTK_PHY_LED_ENABLE BIT(15) ++ ++#define MTK_PHY_LED0_BLINK_CTRL 0x25 ++#define MTK_PHY_LED1_BLINK_CTRL 0x27 ++#define MTK_PHY_LED_1000TX BIT(0) ++#define MTK_PHY_LED_1000RX BIT(1) ++#define MTK_PHY_LED_100TX BIT(2) ++#define MTK_PHY_LED_100RX BIT(3) ++#define MTK_PHY_LED_10TX BIT(4) ++#define MTK_PHY_LED_10RX BIT(5) ++#define MTK_PHY_LED_COLLISION BIT(6) ++#define MTK_PHY_LED_RX_CRC_ERR BIT(7) ++#define MTK_PHY_LED_RX_IDLE_ERR BIT(8) ++#define MTK_PHY_LED_FORCE_BLINK BIT(9) ++ + #define MTK_PHY_RG_BG_RASEL 0x115 + #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) + ++/* Register in boottrap syscon defining the initial state of the 4 PHY LEDs */ ++#define RG_GPIO_MISC_TPBANK0 0x6f0 ++#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) ++ + /* These macro privides efuse parsing for internal phy. */ + #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) + #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) +@@ -238,13 +271,6 @@ enum { + PAIR_D, + }; + +-enum { +- GPHY_PORT0, +- GPHY_PORT1, +- GPHY_PORT2, +- GPHY_PORT3, +-}; +- + enum calibration_mode { + EFUSE_K, + SW_K +@@ -263,6 +289,10 @@ enum CAL_MODE { + SW_M + }; + ++struct mtk_socphy_shared { ++ u32 boottrap; ++}; ++ + static int mtk_socphy_read_page(struct phy_device *phydev) + { + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +@@ -1073,6 +1103,104 @@ static int mt798x_phy_config_init(struct + return mt798x_phy_calibration(phydev); + } + ++static int mt798x_phy_setup_led(struct phy_device *phydev, bool inverted) ++{ ++ struct pinctrl *pinctrl; ++ const u16 led_on_ctrl_defaults = MTK_PHY_LED_ENABLE | ++ MTK_PHY_LED_ON_LINK1000 | ++ MTK_PHY_LED_ON_LINK100 | ++ MTK_PHY_LED_ON_LINK10; ++ const u16 led_blink_defaults = MTK_PHY_LED_1000TX | ++ MTK_PHY_LED_1000RX | ++ MTK_PHY_LED_100TX | ++ MTK_PHY_LED_100RX | ++ MTK_PHY_LED_10TX | ++ MTK_PHY_LED_10RX; ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, ++ led_on_ctrl_defaults ^ ++ (inverted ? MTK_PHY_LED_POLARITY : 0)); ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, ++ led_on_ctrl_defaults); ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, ++ led_blink_defaults); ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL, ++ led_blink_defaults); ++ ++ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); ++ if (IS_ERR(pinctrl)) ++ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED\n"); ++ ++ return 0; ++} ++ ++static int mt7988_phy_probe_shared(struct phy_device *phydev) ++{ ++ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); ++ struct mtk_socphy_shared *priv = phydev->shared->priv; ++ struct regmap *regmap; ++ u32 reg; ++ int ret; ++ ++ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, ++ * LED_C and LED_D respectively. At the same time those pins are used to ++ * bootstrap configuration of the reference clock source (LED_A), ++ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). ++ * In practise this is done using a LED and a resistor pulling the pin ++ * either to GND or to VIO. ++ * The detected value at boot time is accessible at run-time using the ++ * TPBANK0 register located in the gpio base of the pinctrl, in order ++ * to read it here it needs to be referenced by a phandle called ++ * 'mediatek,pio' in the MDIO bus hosting the PHY. ++ * The 4 bits in TPBANK0 are kept as package shared data and are used to ++ * set LED polarity for each of the LED0. ++ */ ++ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); ++ if (ret) ++ return ret; ++ ++ priv->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); ++ ++ return 0; ++} ++ ++static bool mt7988_phy_get_boottrap_polarity(struct phy_device *phydev) ++{ ++ struct mtk_socphy_shared *priv = phydev->shared->priv; ++ ++ if (priv->boottrap & BIT(phydev->mdio.addr)) ++ return false; ++ ++ return true; ++} ++ ++static int mt7988_phy_probe(struct phy_device *phydev) ++{ ++ int err; ++ ++ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, ++ sizeof(struct mtk_socphy_shared)); ++ if (err) ++ return err; ++ ++ if (phy_package_probe_once(phydev)) { ++ err = mt7988_phy_probe_shared(phydev); ++ if (err) ++ return err; ++ } ++ ++ mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev)); ++ ++ return mt798x_phy_calibration(phydev); ++} ++ + static struct phy_driver mtk_socphy_driver[] = { + { + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), +@@ -1092,7 +1220,7 @@ static struct phy_driver mtk_socphy_driv + .config_init = mt798x_phy_config_init, + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, +- .probe = mt798x_phy_calibration, ++ .probe = mt7988_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_page = mtk_socphy_read_page, From f94cda01873b3d477758ee2e4da69c99e0c1081e Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 8 Jul 2023 16:48:39 +0100 Subject: [PATCH 14/17] mediatek: dts: mt7988a: remove boottrap hack The PHY driver now uses regmap created from pio syscon, we no longer need the boottrap device. Signed-off-by: Daniel Golle (cherry picked from commit f321a49fd523a8d393be8e3cd2de41d67855da91) --- .../files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 17de885629..94aa8251bd 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -303,11 +303,6 @@ }; }; - boottrap: boottrap@1001f6f0 { - compatible = "mediatek,boottrap"; - reg = <0 0x1001f6f0 0 0x4>; - }; - sgmiisys0: syscon@10060000 { compatible = "mediatek,mt7988-sgmiisys", "mediatek,mt7988-sgmiisys_0", From 40a26239ff00ad7bc271e33dbbef0e402eebe325 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 8 Jul 2023 17:31:24 +0100 Subject: [PATCH 15/17] mediatek: replace hack for MaxLinear 2.5G PHY Replace hack with proper patch also for Linux 5.15. Signed-off-by: Daniel Golle (cherry picked from commit 712fa3eff82086da8a13e7e5bc577df17892a581) --- ...et-phy-hack-mxl-gpy-disable-sgmii-an.patch | 166 ------------------ ...-don-t-use-SGMII-AN-if-using-phylink.patch | 63 +++++++ ...hy-add-driver-for-MediaTek-2.5G-PHY.patch} | 0 3 files changed, 63 insertions(+), 166 deletions(-) delete mode 100644 target/linux/mediatek/patches-5.15/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch create mode 100644 target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch rename target/linux/mediatek/patches-5.15/{732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch => 733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch} (100%) diff --git a/target/linux/mediatek/patches-5.15/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch b/target/linux/mediatek/patches-5.15/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch deleted file mode 100644 index 2e39ca3c26..0000000000 --- a/target/linux/mediatek/patches-5.15/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch +++ /dev/null @@ -1,166 +0,0 @@ ---- a/drivers/net/phy/mxl-gpy.c -+++ b/drivers/net/phy/mxl-gpy.c -@@ -126,6 +126,12 @@ static int gpy_config_init(struct phy_de - if (ret < 0) - return ret; - -+ /* Disable SGMII auto-negotiation */ -+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -+ VSPEC1_SGMII_CTRL_ANEN, 0); -+ if (ret < 0) -+ return ret; -+ - return gpy_led_write(phydev); - } - -@@ -151,65 +157,6 @@ static int gpy_probe(struct phy_device * - return 0; - } - --static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) --{ -- int fw_ver, fw_type, fw_minor; -- size_t i; -- -- fw_ver = phy_read(phydev, PHY_FWV); -- if (fw_ver < 0) -- return true; -- -- fw_type = FIELD_GET(PHY_FWV_TYPE_MASK, fw_ver); -- fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_ver); -- -- for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { -- if (fw_type != ver_need_sgmii_reaneg[i].type) -- continue; -- if (fw_minor < ver_need_sgmii_reaneg[i].minor) -- return true; -- break; -- } -- -- return false; --} -- --static bool gpy_2500basex_chk(struct phy_device *phydev) --{ -- int ret; -- -- ret = phy_read(phydev, PHY_MIISTAT); -- if (ret < 0) { -- phydev_err(phydev, "Error: MDIO register access failed: %d\n", -- ret); -- return false; -- } -- -- if (!(ret & PHY_MIISTAT_LS) || -- FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) -- return false; -- -- phydev->speed = SPEED_2500; -- phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANEN, 0); -- return true; --} -- --static bool gpy_sgmii_aneg_en(struct phy_device *phydev) --{ -- int ret; -- -- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); -- if (ret < 0) { -- phydev_err(phydev, "Error: MMD register access failed: %d\n", -- ret); -- return true; -- } -- -- return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; --} -- - static int gpy_config_aneg(struct phy_device *phydev) - { - bool changed = false; -@@ -248,53 +195,11 @@ static int gpy_config_aneg(struct phy_de - phydev->interface == PHY_INTERFACE_MODE_INTERNAL) - return 0; - -- /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is -- * disabled. -- */ -- if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || -- !gpy_sgmii_aneg_en(phydev)) -- return 0; -- -- /* There is a design constraint in GPY2xx device where SGMII AN is -- * only triggered when there is change of speed. If, PHY link -- * partner`s speed is still same even after PHY TPI is down and up -- * again, SGMII AN is not triggered and hence no new in-band message -- * from GPY to MAC side SGMII. -- * This could cause an issue during power up, when PHY is up prior to -- * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII -- * wouldn`t receive new in-band message from GPY with correct link -- * status, speed and duplex info. -- * -- * 1) If PHY is already up and TPI link status is still down (such as -- * hard reboot), TPI link status is polled for 4 seconds before -- * retriggerring SGMII AN. -- * 2) If PHY is already up and TPI link status is also up (such as soft -- * reboot), polling of TPI link status is not needed and SGMII AN is -- * immediately retriggered. -- * 3) Other conditions such as PHY is down, speed change etc, skip -- * retriggering SGMII AN. Note: in case of speed change, GPY FW will -- * initiate SGMII AN. -- */ -- -- if (phydev->state != PHY_UP) -- return 0; -- -- ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, -- 20000, 4000000, false); -- if (ret == -ETIMEDOUT) -- return 0; -- else if (ret < 0) -- return ret; -- -- /* Trigger SGMII AN. */ -- return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); -+ return 0; - } - - static void gpy_update_interface(struct phy_device *phydev) - { -- int ret; -- - /* Interface mode is fixed for USXGMII and integrated PHY */ - if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || - phydev->interface == PHY_INTERFACE_MODE_INTERNAL) -@@ -306,29 +211,11 @@ static void gpy_update_interface(struct - switch (phydev->speed) { - case SPEED_2500: - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANEN, 0); -- if (ret < 0) -- phydev_err(phydev, -- "Error: Disable of SGMII ANEG failed: %d\n", -- ret); - break; - case SPEED_1000: - case SPEED_100: - case SPEED_10: - phydev->interface = PHY_INTERFACE_MODE_SGMII; -- if (gpy_sgmii_aneg_en(phydev)) -- break; -- /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed -- * if ANEG is disabled (in 2500-BaseX mode). -- */ -- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_ANEN_ANRS, -- VSPEC1_SGMII_ANEN_ANRS); -- if (ret < 0) -- phydev_err(phydev, -- "Error: Enable of SGMII ANEG failed: %d\n", -- ret); - break; - } - } diff --git a/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch new file mode 100644 index 0000000000..598d9d0d21 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch @@ -0,0 +1,63 @@ +From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 6 Apr 2023 23:36:50 +0100 +Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink + +MAC drivers using phylink expect SGMII in-band-status to be switched off +when attached to a PHY. Make sure this is the case also for mxl-gpy which +keeps SGMII in-band-status in case of SGMII interface mode is used. + +Signed-off-by: Daniel Golle +--- + drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +--- a/drivers/net/phy/mxl-gpy.c ++++ b/drivers/net/phy/mxl-gpy.c +@@ -191,8 +191,11 @@ static bool gpy_2500basex_chk(struct phy + + phydev->speed = SPEED_2500; + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, +- VSPEC1_SGMII_CTRL_ANEN, 0); ++ ++ if (!phydev->phylink) ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, ++ VSPEC1_SGMII_CTRL_ANEN, 0); ++ + return true; + } + +@@ -216,6 +219,14 @@ static int gpy_config_aneg(struct phy_de + u32 adv; + int ret; + ++ /* Disable SGMII auto-negotiation if using phylink */ ++ if (phydev->phylink) { ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, ++ VSPEC1_SGMII_CTRL_ANEN, 0); ++ if (ret < 0) ++ return ret; ++ } ++ + if (phydev->autoneg == AUTONEG_DISABLE) { + /* Configure half duplex with genphy_setup_forced, + * because genphy_c45_pma_setup_forced does not support. +@@ -306,6 +317,8 @@ static void gpy_update_interface(struct + switch (phydev->speed) { + case SPEED_2500: + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; ++ if (phydev->phylink) ++ break; + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, + VSPEC1_SGMII_CTRL_ANEN, 0); + if (ret < 0) +@@ -317,7 +330,7 @@ static void gpy_update_interface(struct + case SPEED_100: + case SPEED_10: + phydev->interface = PHY_INTERFACE_MODE_SGMII; +- if (gpy_sgmii_aneg_en(phydev)) ++ if (phydev->phylink || gpy_sgmii_aneg_en(phydev)) + break; + /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed + * if ANEG is disabled (in 2500-BaseX mode). diff --git a/target/linux/mediatek/patches-5.15/732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch similarity index 100% rename from target/linux/mediatek/patches-5.15/732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch rename to target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch From 5bd5be03bb5a80338824f7bc9223261a5a14f59d Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 12 Jun 2023 04:06:40 +0100 Subject: [PATCH 16/17] uboot-mediatek: support classic uImage.FIT with internal images in imszb The side-effect and main motivation is to also drop the FIT structure size limit because with multiple device tree overlays it may easily grow beyond the previous 4kB limit in the future. Signed-off-by: Daniel Golle (cherry picked from commit 98e3f82c3fb729c1d9de78fef215322528b50cb4) --- .../patches/200-cmd-add-imsz-and-imszb.patch | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch index 7cf0778e47..fcbb6b28a0 100644 --- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch +++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch @@ -70,7 +70,7 @@ { --- a/boot/image-fit.c +++ b/boot/image-fit.c -@@ -2051,6 +2051,50 @@ static const char *fit_get_image_type_pr +@@ -2051,6 +2051,49 @@ static const char *fit_get_image_type_pr return "unknown"; } @@ -89,9 +89,8 @@ + + hdrsize = fdt_totalsize(fit); + -+ /* simple FIT with internal images */ -+ if (hdrsize > 0x1000) -+ return hdrsize; ++ /* take care of simple FIT with internal images */ ++ max_size = hdrsize; + + images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH); + if (images_noffset < 0) { From 50507f5af3d3b3630a448412581707dcf60b08fa Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 12 Jun 2023 04:07:57 +0100 Subject: [PATCH 17/17] scripts/mkits.sh: DT overlays don't need a loadaddr DT overlays do not need relocation in order to be applied, so drop defining the load address for dtbos. Signed-off-by: Daniel Golle (cherry picked from commit cff3786bd54cec8276f1fd08d5c6697846f393a5) --- scripts/mkits.sh | 7 ------- 1 file changed, 7 deletions(-) diff --git a/scripts/mkits.sh b/scripts/mkits.sh index b1c6f98867..bd6cddabf4 100755 --- a/scripts/mkits.sh +++ b/scripts/mkits.sh @@ -88,11 +88,6 @@ if [ -n "${COMPATIBLE}" ]; then COMPATIBLE_PROP="compatible = \"${COMPATIBLE}\";" fi -[ "$DTOVERLAY" ] && { - dtbsize=$(wc -c "$DTB" | awk '{print $1}') - DTADDR=$(printf "0x%08x" $(($LOAD_ADDR - $dtbsize)) ) -} - [ "$FDTADDR" ] && { DTADDR="$FDTADDR" } @@ -170,7 +165,6 @@ OVCONFIGS="" ovnode="fdt-$ovname" ovsize=$(wc -c "$overlay_blob" | awk '{print $1}') echo "$ovname ($overlay_blob) : $ovsize" >&2 - DTADDR=$(printf "0x%08x" $(($DTADDR - $ovsize))) FDTOVERLAY_NODE="$FDTOVERLAY_NODE $ovnode { @@ -179,7 +173,6 @@ OVCONFIGS="" data = /incbin/(\"${overlay_blob}\"); type = \"flat_dt\"; arch = \"${ARCH}\"; - load = <${DTADDR}>; compression = \"none\"; hash@1 { algo = \"crc32\";