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Merge Official Source

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2021-04-18 21:47:29 +08:00
commit 401b3d3819
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
74 changed files with 949 additions and 734 deletions
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8
include/kernel-version.mk
View File

@ -6,11 +6,11 @@ ifdef CONFIG_TESTING_KERNEL
KERNEL_PATCHVER:=$(KERNEL_TESTING_PATCHVER)
endif
LINUX_VERSION-5.4 = .110
LINUX_VERSION-5.10 = .28
LINUX_VERSION-5.4 = .113
LINUX_VERSION-5.10 = .31
LINUX_KERNEL_HASH-5.4.110 = d0f6978440e8a4b266cb1847405a764bca83667541b9e4cdbbc161fb0dd9b228
LINUX_KERNEL_HASH-5.10.28 = 4dfc3aea719556e63e90b8692e9d4b779ad1cb2a9a4823bf721e30004e7ac354
LINUX_KERNEL_HASH-5.4.113 = 30cde92463c474b75f9eb197654570dd6dbb32ec20695544c5469f292662da47
LINUX_KERNEL_HASH-5.10.31 = 54eef1a4d29a2582281375e028ac73c2c5d90dfa21500fa8c3b00e529a2b510d
remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))

3
package/boot/uboot-envtools/files/mvebu
View File

@ -13,6 +13,9 @@ touch /etc/config/ubootenv
board=$(board_name)
case "$board" in
buffalo,ls421de)
ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x10000"
;;
cznic,turris-omnia)
if grep -q 'U-Boot 2015.10-rc2' /dev/mtd0; then
ubootenv_add_uci_config "/dev/mtd0" "0xc0000" "0x10000" "0x40000"

17
package/firmware/linux-firmware/qca_ath10k.mk
View File

@ -26,6 +26,23 @@ define Package/ath10k-firmware-qca4019/install
endef
$(eval $(call BuildPackage,ath10k-firmware-qca4019))
Package/ath10k-board-qca9377 = $(call Package/firmware-default,ath10k qca9377 board firmware)
define Package/ath10k-board-qca9377/install
$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9377/hw1.0
$(INSTALL_DATA) \
$(PKG_BUILD_DIR)/ath10k/QCA9377/hw1.0/board-2.bin \
$(1)/lib/firmware/ath10k/QCA9377/hw1.0/
endef
$(eval $(call BuildPackage,ath10k-board-qca9377))
Package/ath10k-firmware-qca9377 = $(call Package/firmware-default,ath10k qca9377 firmware,+ath10k-board-qca9377)
define Package/ath10k-firmware-qca9377/install
$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9377/hw1.0
$(INSTALL_DATA) \
$(PKG_BUILD_DIR)/ath10k/QCA9377/hw1.0/firmware-6.bin \
$(1)/lib/firmware/ath10k/QCA9377/hw1.0/firmware-6.bin
endef
$(eval $(call BuildPackage,ath10k-firmware-qca9377))
Package/ath10k-board-qca9887 = $(call Package/firmware-default,ath10k qca9887 board firmware)
define Package/ath10k-board-qca9887/install
$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9887/hw1.0

2
package/kernel/linux/modules/netdevices.mk
View File

@ -1006,7 +1006,7 @@ $(eval $(call KernelPackage,forcedeth))
define KernelPackage/of-mdio
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=OpenFirmware MDIO support
DEPENDS:=+kmod-libphy
DEPENDS:=+kmod-libphy @!TARGET_x86
KCONFIG:=CONFIG_OF_MDIO
FILES:= \
$(LINUX_DIR)/drivers/net/phy/fixed_phy.ko \

4
package/kernel/linux/modules/netsupport.mk
View File

@ -721,7 +721,7 @@ $(eval $(call KernelPackage,mppe))
SCHED_MODULES = $(patsubst $(LINUX_DIR)/net/sched/%.ko,%,$(wildcard $(LINUX_DIR)/net/sched/*.ko))
SCHED_MODULES_CORE = sch_ingress sch_fq_codel sch_hfsc sch_htb sch_tbf cls_basic cls_fw cls_route cls_flow cls_tcindex cls_u32 em_u32 act_mirred act_skbedit cls_matchall
SCHED_MODULES_CORE = sch_ingress sch_fq_codel sch_hfsc sch_htb sch_tbf cls_basic cls_fw cls_route cls_flow cls_tcindex cls_u32 em_u32 act_gact act_mirred act_skbedit cls_matchall
SCHED_MODULES_FILTER = $(SCHED_MODULES_CORE) act_connmark act_ctinfo sch_cake sch_netem sch_mqprio em_ipset cls_bpf cls_flower act_bpf act_vlan
SCHED_MODULES_EXTRA = $(filter-out $(SCHED_MODULES_FILTER),$(SCHED_MODULES))
SCHED_FILES = $(patsubst %,$(LINUX_DIR)/net/sched/%.ko,$(filter $(SCHED_MODULES_CORE),$(SCHED_MODULES)))
@ -745,6 +745,7 @@ define KernelPackage/sched-core
CONFIG_NET_CLS_ROUTE4 \
CONFIG_NET_CLS_TCINDEX \
CONFIG_NET_CLS_U32 \
CONFIG_NET_ACT_GACT \
CONFIG_NET_ACT_MIRRED \
CONFIG_NET_ACT_SKBEDIT \
CONFIG_NET_CLS_MATCHALL \
@ -899,7 +900,6 @@ define KernelPackage/sched
CONFIG_NET_SCH_FQ \
CONFIG_NET_SCH_PIE \
CONFIG_NET_ACT_POLICE \
CONFIG_NET_ACT_GACT \
CONFIG_NET_ACT_IPT \
CONFIG_NET_ACT_PEDIT \
CONFIG_NET_ACT_SIMP \

2
package/kernel/linux/modules/video.mk
View File

@ -243,7 +243,7 @@ define KernelPackage/drm
SUBMENU:=$(VIDEO_MENU)
TITLE:=Direct Rendering Manager (DRM) support
HIDDEN:=1
DEPENDS:=+kmod-dma-buf +kmod-i2c-core
DEPENDS:=+kmod-dma-buf +kmod-i2c-core +PACKAGE_kmod-backlight:kmod-backlight
KCONFIG:=CONFIG_DRM
FILES:= \
$(LINUX_DIR)/drivers/gpu/drm/drm.ko \

72
package/network/config/ltq-vdsl-app/src/src/dsl_cpe_ubus.c
View File

@ -34,6 +34,12 @@
str = text; \
break;
#define STR_CASE_MAP(id, text, number) \
case id: \
str = text; \
map = number; \
break;
#define IOCTL(type, request) \
type out; \
memset(&out, 0, sizeof(type)); \
@ -99,6 +105,34 @@ typedef enum {
PROFILE_35B,
} profile_t;
/* These values are exported via ubus and backwards compability
* needs to be kept!
*/
enum {
LSTATE_MAP_UNKNOWN = -1,
LSTATE_MAP_NOT_INITIALIZED,
LSTATE_MAP_EXCEPTION,
LSTATE_MAP_IDLE,
LSTATE_MAP_SILENT,
LSTATE_MAP_HANDSHAKE,
LSTATE_MAP_FULL_INIT,
LSTATE_MAP_SHOWTIME_NO_SYNC,
LSTATE_MAP_SHOWTIME_TC_SYNC,
LSTATE_MAP_RESYNC,
};
/* These values are exported via ubus and backwards compability
* needs to be kept!
*/
enum {
PSTATE_MAP_UNKNOWN = -2,
PSTATE_MAP_NA,
PSTATE_MAP_L0,
PSTATE_MAP_L1,
PSTATE_MAP_L2,
PSTATE_MAP_L3,
};
static DSL_CPE_ThreadCtrl_t thread;
static struct ubus_context *ctx;
static struct blob_buf b;
@ -306,32 +340,33 @@ static void version_information(int fd) {
static void line_state(int fd) {
IOCTL(DSL_LineState_t, DSL_FIO_LINE_STATE_GET)
int map = LSTATE_MAP_UNKNOWN;
const char *str;
switch (out.data.nLineState) {
STR_CASE(DSL_LINESTATE_NOT_INITIALIZED, "Not initialized")
STR_CASE(DSL_LINESTATE_EXCEPTION, "Exception")
STR_CASE_MAP(DSL_LINESTATE_NOT_INITIALIZED, "Not initialized", LSTATE_MAP_NOT_INITIALIZED)
STR_CASE_MAP(DSL_LINESTATE_EXCEPTION, "Exception", LSTATE_MAP_EXCEPTION)
STR_CASE(DSL_LINESTATE_NOT_UPDATED, "Not updated")
STR_CASE(DSL_LINESTATE_IDLE_REQUEST, "Idle request")
STR_CASE(DSL_LINESTATE_IDLE, "Idle")
STR_CASE_MAP(DSL_LINESTATE_IDLE, "Idle", LSTATE_MAP_IDLE)
STR_CASE(DSL_LINESTATE_SILENT_REQUEST, "Silent request")
STR_CASE(DSL_LINESTATE_SILENT, "Silent")
STR_CASE(DSL_LINESTATE_HANDSHAKE, "Handshake")
STR_CASE_MAP(DSL_LINESTATE_SILENT, "Silent", LSTATE_MAP_SILENT)
STR_CASE_MAP(DSL_LINESTATE_HANDSHAKE, "Handshake", LSTATE_MAP_HANDSHAKE)
STR_CASE(DSL_LINESTATE_BONDING_CLR, "Bonding CLR")
STR_CASE(DSL_LINESTATE_FULL_INIT, "Full init")
STR_CASE_MAP(DSL_LINESTATE_FULL_INIT, "Full init", LSTATE_MAP_FULL_INIT)
STR_CASE(DSL_LINESTATE_SHORT_INIT_ENTRY, "Short init entry")
STR_CASE(DSL_LINESTATE_DISCOVERY, "Discovery")
STR_CASE(DSL_LINESTATE_TRAINING, "Training")
STR_CASE(DSL_LINESTATE_ANALYSIS, "Analysis")
STR_CASE(DSL_LINESTATE_EXCHANGE, "Exchange")
STR_CASE(DSL_LINESTATE_SHOWTIME_NO_SYNC, "Showtime without TC-Layer sync")
STR_CASE(DSL_LINESTATE_SHOWTIME_TC_SYNC, "Showtime with TC-Layer sync")
STR_CASE_MAP(DSL_LINESTATE_SHOWTIME_NO_SYNC, "Showtime without TC-Layer sync", LSTATE_MAP_SHOWTIME_NO_SYNC)
STR_CASE_MAP(DSL_LINESTATE_SHOWTIME_TC_SYNC, "Showtime with TC-Layer sync", LSTATE_MAP_SHOWTIME_TC_SYNC)
STR_CASE(DSL_LINESTATE_FASTRETRAIN, "Fastretrain")
STR_CASE(DSL_LINESTATE_LOWPOWER_L2, "Lowpower L2")
STR_CASE(DSL_LINESTATE_LOOPDIAGNOSTIC_ACTIVE, "Loopdiagnostic active")
STR_CASE(DSL_LINESTATE_LOOPDIAGNOSTIC_DATA_EXCHANGE, "Loopdiagnostic data exchange")
STR_CASE(DSL_LINESTATE_LOOPDIAGNOSTIC_DATA_REQUEST, "Loopdiagnostic data request")
STR_CASE(DSL_LINESTATE_LOOPDIAGNOSTIC_COMPLETE, "Loopdiagnostic complete")
STR_CASE(DSL_LINESTATE_RESYNC, "Resync")
STR_CASE_MAP(DSL_LINESTATE_RESYNC, "Resync", LSTATE_MAP_RESYNC)
STR_CASE(DSL_LINESTATE_TEST, "Test")
STR_CASE(DSL_LINESTATE_TEST_LOOP, "Test loop")
STR_CASE(DSL_LINESTATE_TEST_REVERB, "Test reverb")
@ -351,9 +386,13 @@ static void line_state(int fd) {
str = NULL;
break;
};
if (str)
m_str("state", str);
if (map != LSTATE_MAP_UNKNOWN )
m_u32("state_num", map);
m_bool("up", out.data.nLineState == DSL_LINESTATE_SHOWTIME_TC_SYNC);
}
@ -377,19 +416,24 @@ static void g997_line_inventory(int fd) {
static void g997_power_management_status(int fd) {
IOCTL(DSL_G997_PowerManagementStatus_t, DSL_FIO_G997_POWER_MANAGEMENT_STATUS_GET)
int map = PSTATE_MAP_UNKNOWN;
const char *str;
switch (out.data.nPowerManagementStatus) {
STR_CASE(DSL_G997_PMS_NA, "Power management state is not available")
STR_CASE(DSL_G997_PMS_L0, "L0 - Synchronized")
STR_CASE(DSL_G997_PMS_L1, "L1 - Power Down Data transmission (G.992.2)")
STR_CASE(DSL_G997_PMS_L2, "L2 - Power Down Data transmission (G.992.3 and G.992.4)")
STR_CASE(DSL_G997_PMS_L3, "L3 - No power")
STR_CASE_MAP(DSL_G997_PMS_NA, "Power management state is not available", PSTATE_MAP_NA)
STR_CASE_MAP(DSL_G997_PMS_L0, "L0 - Synchronized", PSTATE_MAP_L0)
STR_CASE_MAP(DSL_G997_PMS_L1, "L1 - Power Down Data transmission (G.992.2)", PSTATE_MAP_L1)
STR_CASE_MAP(DSL_G997_PMS_L2, "L2 - Power Down Data transmission (G.992.3 and G.992.4)", PSTATE_MAP_L2)
STR_CASE_MAP(DSL_G997_PMS_L3, "L3 - No power", PSTATE_MAP_L3)
default:
str = NULL;
break;
};
if (str)
m_str("power_state", str);
if (map != PSTATE_MAP_UNKNOWN)
m_u32("power_state_num", map);
}
static void g997_xtu_system_enabling(int fd, standard_t *standard) {

4
package/network/config/netifd/Makefile
View File

@ -1,7 +1,7 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=netifd
PKG_RELEASE:=2
PKG_RELEASE:=3
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/netifd.git
@ -27,6 +27,7 @@ endef
define Package/netifd/conffiles
/etc/udhcpc.user
/etc/udhcpc.user.d/
endef
TARGET_CFLAGS += \
@ -44,6 +45,7 @@ define Package/netifd/install
$(INSTALL_DIR) $(1)/sbin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/netifd $(1)/sbin/
$(CP) ./files/* $(1)/
$(INSTALL_DIR) $(1)/etc/udhcpc.user.d/
$(CP) $(PKG_BUILD_DIR)/scripts/* $(1)/lib/netifd/
endef

3
package/network/config/netifd/files/lib/netifd/dhcp.script
View File

@ -112,5 +112,8 @@ esac
# user rules
[ -f /etc/udhcpc.user ] && . /etc/udhcpc.user "$@"
for f in /etc/udhcpc.user.d/*; do
[ -f "$f" ] && (. "$f" "$@")
done
exit 0

5
package/network/ipv6/odhcp6c/Makefile
View File

@ -8,7 +8,7 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=odhcp6c
PKG_RELEASE:=17
PKG_RELEASE:=18
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/odhcp6c.git
@ -44,6 +44,7 @@ endef
define Package/odhcp6c/conffiles
/etc/odhcp6c.user
/etc/odhcp6c.user.d/
endef
define Package/odhcp6c/install
@ -52,7 +53,7 @@ define Package/odhcp6c/install
$(INSTALL_DIR) $(1)/lib/netifd/proto
$(INSTALL_BIN) ./files/dhcpv6.sh $(1)/lib/netifd/proto/dhcpv6.sh
$(INSTALL_BIN) ./files/dhcpv6.script $(1)/lib/netifd/
$(INSTALL_DIR) $(1)/etc/
$(INSTALL_DIR) $(1)/etc/odhcp6c.user.d/
$(INSTALL_CONF) ./files/odhcp6c.user $(1)/etc/
endef

3
package/network/ipv6/odhcp6c/files/dhcpv6.script
View File

@ -237,5 +237,8 @@ esac
# user rules
[ -f /etc/odhcp6c.user ] && . /etc/odhcp6c.user "$@"
for f in /etc/odhcp6c.user.d/*; do
[ -f "$f" ] && (. "$f" "$@")
done
exit 0

2
target/linux/arc770/image/Makefile
View File

@ -24,6 +24,8 @@ endef
define Device/nsim
$(call Device/vmlinux)
DEVICE_VENDOR := Synopsys
DEVICE_MODEL := nSIM
DEVICE_PROFILE := nsim
DEVICE_DTS := nsim_700
endef

2
target/linux/archs38/image/Makefile
View File

@ -24,6 +24,8 @@ endef
define Device/nsim_hs
$(call Device/vmlinux)
DEVICE_VENDOR := Synopsys
DEVICE_MODEL := nSIM HS
DEVICE_PROFILE := nsim_hs
DEVICE_DTS := nsim_hs_idu
endef

48
target/linux/ath79/dts/qca9558_mikrotik_routerboard-922uags-5hpacd.dts
View File

@ -23,6 +23,27 @@
gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
};
};
i2c: i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio 18 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio 19 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
i2c-gpio,timeout-ms = <1>;
};
sfp1: sfp {
compatible = "sff,sfp";
i2c-bus = <&i2c>;
maximum-power-milliwatt = <1000>;
los-gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
// Toggling GPIO16 actually enables/disables the transmitter,
// but the SFP driver does not seem to be using it.
};
};
&pcie0 {
@ -55,3 +76,30 @@
&usb_phy1 {
status = "okay";
};
&mdio1 {
status = "okay";
phy_sfp: ethernet-phy@0 {
reg = <0>;
phy-mode = "sgmii";
sfp = <&sfp1>;
};
};
&eth1 {
status = "okay";
phy-handle = <&phy_sfp>;
pll-data = <0x03000000 0x00000101 0x00001616>;
qca955x-sgmii-fixup;
gmac-config {
device = <&gmac>;
};
fixed-link {
speed = <1000>;
full-duplex;
};
};

25
target/linux/ath79/files/drivers/mtd/nand/raw/nand_rb4xx.c
View File

@ -188,10 +188,15 @@ static int rb4xx_nand_probe(struct platform_device *pdev)
if (mtd->writesize == 512)
mtd_set_ooblayout(mtd, &rb4xx_nand_ecclayout_ops);
nand->chip.ecc.mode = NAND_ECC_SOFT;
nand->chip.ecc.algo = NAND_ECC_HAMMING;
nand->chip.options = NAND_NO_SUBPAGE_WRITE;
nand->chip.priv = nand;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
nand->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
nand->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
#else
nand->chip.ecc.mode = NAND_ECC_SOFT;
nand->chip.ecc.algo = NAND_ECC_HAMMING;
#endif
nand->chip.options = NAND_NO_SUBPAGE_WRITE;
nand->chip.priv = nand;
nand->chip.legacy.read_byte = rb4xx_nand_read_byte;
nand->chip.legacy.write_buf = rb4xx_nand_write_buf;
@ -206,7 +211,12 @@ static int rb4xx_nand_probe(struct platform_device *pdev)
ret = mtd_device_register(mtd, NULL, 0);
if (ret) {
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
mtd_device_unregister(nand_to_mtd(&nand->chip));
nand_cleanup(&nand->chip);
#else
nand_release(&nand->chip);
#endif
return ret;
}
@ -217,7 +227,12 @@ static int rb4xx_nand_remove(struct platform_device *pdev)
{
struct rb4xx_nand *nand = platform_get_drvdata(pdev);
nand_release(&nand->chip);
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
mtd_device_unregister(nand_to_mtd(&nand->chip));
nand_cleanup(&nand->chip);
#else
nand_release(&nand->chip);
#endif
return 0;
}

3
target/linux/ath79/image/mikrotik.mk
View File

@ -22,7 +22,8 @@ define Device/mikrotik_routerboard-922uags-5hpacd
$(Device/mikrotik_nand)
SOC := qca9558
DEVICE_MODEL := RouterBOARD 922UAGS-5HPacD
DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct kmod-usb2
DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct kmod-usb2 \
kmod-i2c-gpio kmod-sfp
SUPPORTED_DEVICES += rb-922uags-5hpacd
endef
TARGET_DEVICES += mikrotik_routerboard-922uags-5hpacd

1
target/linux/ath79/mikrotik/base-files/etc/board.d/02_network
View File

@ -15,7 +15,6 @@ ath79_setup_interfaces()
"0@eth1" "1:lan:4" "2:lan:1" "3:lan:2" "4:lan:3"
;;
mikrotik,routerboard-921gs-5hpacd-15s|\
mikrotik,routerboard-922uags-5hpacd|\
mikrotik,routerboard-lhg-2nd|\
mikrotik,routerboard-sxt-5nd-r2|\
mikrotik,routerboard-wap-g-5hact2hnd|\

1
target/linux/ath79/mikrotik/config-default
View File

@ -24,6 +24,7 @@ CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_NET_DSA=y
CONFIG_NET_SWITCHDEV=y
CONFIG_PCI_AR71XX=y
CONFIG_PHY_AR7100_USB=y

21
target/linux/ath79/patches-5.10/0051-spi-ath79-always-call-chipselect-function.patch
View File

@ -1,21 +0,0 @@
From: David Bauer <mail@david-bauer.net>
Date: Wed, 17 Feb 2021 02:44:55 +0100
Subject: [PATCH] spi: ath79: always call chipselect function
api-bitbang has to call the chipselect function on the ath79 SPI driver
in order to communicate with the SPI slave device.
Fixes commit 4a07b8bcd503 ("spi: bitbang: Make chipselect callback optional")
Signed-off-by: David Bauer <mail@david-bauer.net>
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -152,6 +152,7 @@ static int ath79_spi_probe(struct platfo
master->use_gpio_descriptors = true;
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
+ master->flags = SPI_MASTER_GPIO_SS;
sp->bitbang.master = master;
sp->bitbang.chipselect = ath79_spi_chipselect;

26
target/linux/ath79/patches-5.10/0052-mtd-spi-nor-add-block-protection-flags-to-macronix.patch
View File

@ -1,26 +0,0 @@
From 158f9796335b393980afb8e9796eb8d44106652a Mon Sep 17 00:00:00 2001
From: David Bauer <mail@david-bauer.net>
Date: Mon, 26 Oct 2020 15:10:47 +0100
Subject: [PATCH 1/2] mtd: spi-nor: add block protection flags to macronix
Macronix flash chips support block protection by using BP bits in the
read status register. Add the corresponding flag to indicate block
protection support.
Otherwise, locked blocks are not unlocked when requested.
Signed-off-by: David Bauer <mail@david-bauer.net>
---
drivers/mtd/spi-nor/macronix.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -94,6 +94,7 @@ static const struct flash_info macronix_
static void macronix_default_init(struct spi_nor *nor)
{
+ nor->flags |= SNOR_F_HAS_LOCK;
nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
nor->flags |= SNOR_F_HAS_LOCK;

33
target/linux/ath79/patches-5.10/0052-mtd-spi-nor-use-4-bit-locking-for-MX25L12805D.patch Normal file
View File

@ -0,0 +1,33 @@
From a449cd03db4d0e1d292b3734f7676634cfd94f53 Mon Sep 17 00:00:00 2001
From: David Bauer <mail@david-bauer.net>
Date: Sun, 25 Oct 2020 01:14:22 +0200
Subject: [PATCH] mtd: spi-nor: use 4 bit locking for MX25L12805D
Macronix MX25L12805D supports locking with 4 block
protection bits in its status register. Add the corresponding
flag in order to clear these bits when unloking the flash.
Otherwise, the flash might not be writable depending on the state
left by the bootloader.
Tested-on: Ubiquiti UniFi AC Lite (ath79)
Fixes commit 62593cf40b23 ("mtd: spi-nor: refactor block protection functions")
Signed-off-by: David Bauer <mail@david-bauer.net>
---
drivers/mtd/spi-nor/macronix.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -50,7 +50,8 @@ static const struct flash_info macronix_
{ "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
{ "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
- { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K) },
+ { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K |
+ SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
{ "mx25r1635f", INFO(0xc22815, 0, 64 * 1024, 32,
SECT_4K | SPI_NOR_DUAL_READ |

85
target/linux/ath79/patches-5.10/0053-mtd-spi-nor-use-4-bit-BP-for-large-Macronix-flash.patch
View File

@ -1,85 +0,0 @@
From 59f88b8d4447be809d0b5e7a283290d06848d3bc Mon Sep 17 00:00:00 2001
From: David Bauer <mail@david-bauer.net>
Date: Sun, 25 Oct 2020 01:14:22 +0200
Subject: [PATCH 2/2] mtd: spi-nor: use 4 bit BP for large Macronix flash
Macronix SPI-NOR chips with 128 or more 64k blocks have 4 block
protection bits in their status register. Add the corresponding
flag in order to clear these bits when unloking the flash.
Otherwise, the flash might not be writable depending on the state the
bootloader left the flash in.
Fixes commit 62593cf40b23 ("mtd: spi-nor: refactor block protection functions")
Signed-off-by: David Bauer <mail@david-bauer.net>
---
drivers/mtd/spi-nor/macronix.c | 31 ++++++++++++++++++-------------
1 file changed, 18 insertions(+), 13 deletions(-)
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -50,8 +50,8 @@ static const struct flash_info macronix_
{ "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
{ "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
- { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K) },
- { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
+ { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_4BIT_BP) },
+ { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, SPI_NOR_4BIT_BP) },
{ "mx25r1635f", INFO(0xc22815, 0, 64 * 1024, 32,
SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
@@ -60,36 +60,41 @@ static const struct flash_info macronix_
SPI_NOR_QUAD_READ) },
{ "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
+ SPI_NOR_QUAD_READ | SPI_NOR_4BIT_BP) },
{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
- SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_4BIT_BP)
.fixups = &mx25l25635_fixups },
{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512,
- SECT_4K | SPI_NOR_4B_OPCODES) },
+ SECT_4K | SPI_NOR_4B_OPCODES |
+ SPI_NOR_4BIT_BP) },
{ "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
+ SPI_NOR_4BIT_BP) },
{ "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16,
SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
- { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
+ { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, SPI_NOR_4BIT_BP) },
{ "mx25l51245g", INFO(0xc2201a, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_4B_OPCODES) },
+ SPI_NOR_4B_OPCODES | SPI_NOR_4BIT_BP) },
{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_4B_OPCODES) },
+ SPI_NOR_4B_OPCODES | SPI_NOR_4BIT_BP) },
{ "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
+ SPI_NOR_4BIT_BP) },
{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
+ SPI_NOR_QUAD_READ | SPI_NOR_4BIT_BP) },
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048,
- SPI_NOR_QUAD_READ) },
+ SPI_NOR_QUAD_READ | SPI_NOR_4BIT_BP) },
{ "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096,
SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
+ SPI_NOR_4BIT_BP) },
};
static void macronix_default_init(struct spi_nor *nor)

2
target/linux/ath79/patches-5.10/410-spi-ath79-Implement-the-spi_mem-interface.patch
View File

@ -58,7 +58,7 @@ Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
static int ath79_spi_probe(struct platform_device *pdev)
{
struct spi_master *master;
@@ -164,6 +198,7 @@ static int ath79_spi_probe(struct platfo
@@ -163,6 +197,7 @@ static int ath79_spi_probe(struct platfo
ret = PTR_ERR(sp->base);
goto err_put_master;
}

76
target/linux/ath79/patches-5.10/920-mikrotik-rb4xx.patch Normal file
View File

@ -0,0 +1,76 @@
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -2141,6 +2141,14 @@ config RAVE_SP_CORE
Select this to get support for the Supervisory Processor
device found on several devices in RAVE line of hardware.
+config MFD_RB4XX_CPLD
+ tristate "CPLD driver for Mikrotik RB4xx series boards
+ select MFD_CORE
+ depends on ATH79 || COMPILE_TEST
+ help
+ Enables support for the CPLD chip (NAND & GPIO) on Mikrotik
+ Routerboard RB4xx series.
+
config SGI_MFD_IOC3
tristate "SGI IOC3 core driver"
depends on PCI && MIPS && 64BIT
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -264,6 +264,7 @@ obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-b
obj-$(CONFIG_MFD_STMFX) += stmfx.o
obj-$(CONFIG_MFD_KHADAS_MCU) += khadas-mcu.o
+obj-$(CONFIG_MFD_RB4XX_CPLD) += rb4xx-cpld.o
obj-$(CONFIG_SGI_MFD_IOC3) += ioc3.o
obj-$(CONFIG_MFD_SIMPLE_MFD_I2C) += simple-mfd-i2c.o
obj-$(CONFIG_MFD_INTEL_M10_BMC) += intel-m10-bmc.o
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -1518,6 +1518,12 @@ config GPIO_SODAVILLE
help
Say Y here to support Intel Sodaville GPIO.
+config GPIO_RB4XX
+ tristate "GPIO expander for Mikrotik RB4xx series boards"
+ depends on MFD_RB4XX_CPLD
+ help
+ GPIO driver for Mikrotik Routerboard RB4xx series.
+
endmenu
menu "SPI GPIO expanders"
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -120,6 +120,7 @@ obj-$(CONFIG_GPIO_PL061) += gpio-pl061.
obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o
obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o
+obj-$(CONFIG_GPIO_RB4XX) += gpio-rb4xx.o
obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
obj-$(CONFIG_GPIO_RDA) += gpio-rda.o
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -564,4 +564,11 @@ config MTD_NAND_AR934X
Enables support for NAND controller on Qualcomm Atheros SoCs.
This controller is found on AR934x and QCA955x SoCs.
+config MTD_NAND_RB4XX
+ tristate "Support for NAND driver for Mikrotik RB4xx series boards"
+ depends on MFD_RB4XX_CPLD
+ help
+ Enables support for the NAND flash chip on Mikrotik Routerboard
+ RB4xx series.
+
endif # MTD_RAW_NAND
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_MTD_NAND_MESON) += meson_n
obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o
obj-$(CONFIG_MTD_NAND_ARASAN) += arasan-nand-controller.o
obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nand.o
+obj-$(CONFIG_MTD_NAND_RB4XX) += nand_rb4xx.o
nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
nand-objs += nand_onfi.o

4
target/linux/bcm63xx/patches-5.10/143-gpio-fix-device-tree-gpio-hogs-on-dual-role-gpio-pin.patch
View File

@ -116,7 +116,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
}
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1897,7 +1897,8 @@ int gpiochip_add_pingroup_range(struct g
@@ -1893,7 +1893,8 @@ int gpiochip_add_pingroup_range(struct g
list_add_tail(&pin_range->node, &gdev->pin_ranges);
@ -126,7 +126,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
}
EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range);
@@ -1954,7 +1955,7 @@ int gpiochip_add_pin_range(struct gpio_c
@@ -1950,7 +1951,7 @@ int gpiochip_add_pin_range(struct gpio_c
list_add_tail(&pin_range->node, &gdev->pin_ranges);

1
target/linux/gemini/config-5.4
View File

@ -47,7 +47,6 @@ CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BOUNCE=y
# CONFIG_BPF_SYSCALL is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y

2
target/linux/generic/backport-5.10/610-v5.13-02-netfilter-Fix-fall-through-warnings-for-Clang.patch
View File

@ -24,7 +24,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
case CT_DCCP_INVALID:
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
@@ -8364,6 +8364,7 @@ static int nf_tables_check_loops(const s
@@ -8367,6 +8367,7 @@ static int nf_tables_check_loops(const s
data->verdict.chain);
if (err < 0)
return err;

4
target/linux/generic/backport-5.10/610-v5.13-10-netfilter-nftables-update-table-flags-from-the-commi.patch
View File

@ -70,7 +70,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
nft_trans_table_update(trans) = true;
list_add_tail(&trans->list, &ctx->net->nft.commit_list);
return 0;
@@ -7873,11 +7877,10 @@ static int nf_tables_commit(struct net *
@@ -7876,11 +7880,10 @@ static int nf_tables_commit(struct net *
switch (trans->msg_type) {
case NFT_MSG_NEWTABLE:
if (nft_trans_table_update(trans)) {
@ -86,7 +86,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
} else {
nft_clear(net, trans->ctx.table);
}
@@ -8090,11 +8093,9 @@ static int __nf_tables_abort(struct net
@@ -8093,11 +8096,9 @@ static int __nf_tables_abort(struct net
switch (trans->msg_type) {
case NFT_MSG_NEWTABLE:
if (nft_trans_table_update(trans)) {

20
target/linux/generic/config-5.10
View File

@ -979,6 +979,7 @@ CONFIG_CONSTRUCTORS=y
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_NO_EFFICIENT_FFS is not set
CONFIG_CPU_SW_DOMAIN_PAN=y
# CONFIG_CPU_THERMAL is not set
# CONFIG_CRAMFS is not set
CONFIG_CRAMFS_BLOCKDEV=y
# CONFIG_CRAMFS_MTD is not set
@ -1015,6 +1016,12 @@ CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_ARM is not set
# CONFIG_CRYPTO_AES_ARM_BS is not set
# CONFIG_CRYPTO_AES_ARM_CE is not set
# CONFIG_CRYPTO_AES_ARM64 is not set
# CONFIG_CRYPTO_AES_ARM64_BS is not set
# CONFIG_CRYPTO_AES_ARM64_CE is not set
# CONFIG_CRYPTO_AES_ARM64_CE_CCM is not set
# CONFIG_CRYPTO_AES_ARM64_CE_BLK is not set
# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set
# CONFIG_CRYPTO_AES_NI_INTEL is not set
# CONFIG_CRYPTO_AES_TI is not set
CONFIG_CRYPTO_ALGAPI=y
@ -1044,6 +1051,7 @@ CONFIG_CRYPTO_ALGAPI2=y
# CONFIG_CRYPTO_CRC32C_INTEL is not set
# CONFIG_CRYPTO_CRC32_ARM_CE is not set
# CONFIG_CRYPTO_CRCT10DIF is not set
# CONFIG_CRYPTO_CRCT10DIF_ARM64_CE is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
@ -1102,6 +1110,7 @@ CONFIG_CRYPTO_ALGAPI2=y
# CONFIG_CRYPTO_GF128MUL is not set
# CONFIG_CRYPTO_GHASH is not set
# CONFIG_CRYPTO_GHASH_ARM_CE is not set
# CONFIG_CRYPTO_GHASH_ARM64_CE is not set
# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set
# CONFIG_CRYPTO_HASH is not set
# CONFIG_CRYPTO_HMAC is not set
@ -1159,14 +1168,18 @@ CONFIG_CRYPTO_PCRYPT=y
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA1_ARM is not set
# CONFIG_CRYPTO_SHA1_ARM_CE is not set
# CONFIG_CRYPTO_SHA1_ARM64_CE is not set
# CONFIG_CRYPTO_SHA1_ARM_NEON is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA256_ARM is not set
# CONFIG_CRYPTO_SHA256_ARM64 is not set
# CONFIG_CRYPTO_SHA2_ARM_CE is not set
# CONFIG_CRYPTO_SHA2_ARM64_CE is not set
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SHA3_ARM64 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_SHA512_ARM is not set
# CONFIG_CRYPTO_SHA512_ARM64 is not set
# CONFIG_CRYPTO_SHA512_ARM64_CE is not set
# CONFIG_CRYPTO_SIMD is not set
CONFIG_CRYPTO_SKCIPHER=y
@ -1297,7 +1310,6 @@ CONFIG_DEFAULT_CUBIC=y
CONFIG_DEFAULT_DEADLINE=y
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_IOSCHED="deadline"
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
# CONFIG_DEFAULT_NOOP is not set
# CONFIG_DEFAULT_RENO is not set
@ -1355,6 +1367,7 @@ CONFIG_DMA_DECLARE_COHERENT=y
# CONFIG_DMA_JZ4780 is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
# CONFIG_DMA_NOOP_OPS is not set
# CONFIG_DMA_PERNUMA_CMA is not set
# CONFIG_DMA_SHARED_BUFFER is not set
# CONFIG_DMA_VIRT_OPS is not set
# CONFIG_DM_CACHE is not set
@ -2026,6 +2039,7 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_CDEV is not set
# CONFIG_GPIO_CDEV_V1 is not set
# CONFIG_GPIO_CS5535 is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_EM is not set
@ -2600,9 +2614,6 @@ CONFIG_INPUT_MISC=y
# CONFIG_IOMMU_SUPPORT is not set
# CONFIG_IONIC is not set
# CONFIG_IOSCHED_BFQ is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_NOOP=y
CONFIG_IO_STRICT_DEVMEM=y
# CONFIG_IO_URING is not set
CONFIG_IO_WQ=y
@ -3556,6 +3567,7 @@ CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_PHYSMAP_COMPAT is not set
# CONFIG_MTD_PHYSMAP_GEMINI is not set
# CONFIG_MTD_PHYSMAP_IXP4XX is not set
# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_PHYSMAP_OF_GEMINI is not set

1
target/linux/generic/config-5.4
View File

@ -6127,6 +6127,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_RENESAS_USBHS is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_ROLE_SWITCH is not set
# CONFIG_USB_ROLES_INTEL_XHCI is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_RTL8152 is not set
# CONFIG_USB_S2255 is not set

2
target/linux/generic/hack-5.10/204-module_strip.patch
View File

@ -88,7 +88,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -2338,6 +2338,13 @@ config UNUSED_KSYMS_WHITELIST
@@ -2337,6 +2337,13 @@ config UNUSED_KSYMS_WHITELIST
one per line. The path can be absolute, or relative to the kernel
source tree.

2
target/linux/generic/hack-5.10/902-debloat_proc.patch
View File

@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/net/core/sock.c
+++ b/net/core/sock.c
@@ -3680,6 +3680,8 @@ static __net_initdata struct pernet_oper
@@ -3674,6 +3674,8 @@ static __net_initdata struct pernet_oper
static int __init proto_init(void)
{

2
target/linux/generic/hack-5.4/204-module_strip.patch
View File

@ -96,7 +96,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -2196,6 +2196,13 @@ config TRIM_UNUSED_KSYMS
@@ -2195,6 +2195,13 @@ config TRIM_UNUSED_KSYMS
If unsure, or if you need to build out-of-tree modules, say N.

2
target/linux/generic/hack-5.4/902-debloat_proc.patch
View File

@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/net/core/sock.c
+++ b/net/core/sock.c
@@ -3629,6 +3629,8 @@ static __net_initdata struct pernet_oper
@@ -3623,6 +3623,8 @@ static __net_initdata struct pernet_oper
static int __init proto_init(void)
{

2
target/linux/generic/pending-5.10/203-kallsyms_uncompressed.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1385,6 +1385,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW
@@ -1384,6 +1384,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW
the unaligned access emulation.
see arch/parisc/kernel/unaligned.c for reference

14
target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
View File

@ -185,7 +185,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
cfg->fc_flags |= RTF_REJECT;
if (rtm->rtm_type == RTN_LOCAL)
@@ -6062,6 +6093,8 @@ static int ip6_route_dev_notify(struct n
@@ -6064,6 +6095,8 @@ static int ip6_route_dev_notify(struct n
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
net->ipv6.ip6_prohibit_entry->dst.dev = dev;
net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
@ -194,7 +194,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
#endif
@@ -6073,6 +6106,7 @@ static int ip6_route_dev_notify(struct n
@@ -6075,6 +6108,7 @@ static int ip6_route_dev_notify(struct n
in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
@ -202,7 +202,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
#endif
}
@@ -6264,6 +6298,8 @@ static int __net_init ip6_route_net_init
@@ -6266,6 +6300,8 @@ static int __net_init ip6_route_net_init
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
net->ipv6.fib6_has_custom_rules = false;
@ -211,7 +211,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,
sizeof(*net->ipv6.ip6_prohibit_entry),
GFP_KERNEL);
@@ -6274,11 +6310,21 @@ static int __net_init ip6_route_net_init
@@ -6276,11 +6312,21 @@ static int __net_init ip6_route_net_init
ip6_template_metrics, true);
INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);
@ -234,7 +234,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
ip6_template_metrics, true);
@@ -6305,6 +6351,8 @@ out:
@@ -6307,6 +6353,8 @@ out:
return ret;
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
out_ip6_prohibit_entry:
kfree(net->ipv6.ip6_prohibit_entry);
out_ip6_null_entry:
@@ -6324,6 +6372,7 @@ static void __net_exit ip6_route_net_exi
@@ -6326,6 +6374,7 @@ static void __net_exit ip6_route_net_exi
kfree(net->ipv6.ip6_null_entry);
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
kfree(net->ipv6.ip6_prohibit_entry);
@ -251,7 +251,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
kfree(net->ipv6.ip6_blk_hole_entry);
#endif
dst_entries_destroy(&net->ipv6.ip6_dst_ops);
@@ -6401,6 +6450,9 @@ void __init ip6_route_init_special_entri
@@ -6403,6 +6452,9 @@ void __init ip6_route_init_special_entri
init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);

2
target/linux/generic/pending-5.10/920-mangle_bootargs.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1791,6 +1791,15 @@ config EMBEDDED
@@ -1790,6 +1790,15 @@ config EMBEDDED
an embedded system so certain expert options are available
for configuration.

2
target/linux/generic/pending-5.4/203-kallsyms_uncompressed.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1278,6 +1278,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW
@@ -1277,6 +1277,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW
the unaligned access emulation.
see arch/parisc/kernel/unaligned.c for reference

14
target/linux/generic/pending-5.4/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
View File

@ -185,7 +185,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
cfg->fc_flags |= RTF_REJECT;
if (rtm->rtm_type == RTN_LOCAL)
@@ -6019,6 +6050,8 @@ static int ip6_route_dev_notify(struct n
@@ -6021,6 +6052,8 @@ static int ip6_route_dev_notify(struct n
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
net->ipv6.ip6_prohibit_entry->dst.dev = dev;
net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
@ -194,7 +194,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
#endif
@@ -6030,6 +6063,7 @@ static int ip6_route_dev_notify(struct n
@@ -6032,6 +6065,7 @@ static int ip6_route_dev_notify(struct n
in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
@ -202,7 +202,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
#endif
}
@@ -6222,6 +6256,8 @@ static int __net_init ip6_route_net_init
@@ -6224,6 +6258,8 @@ static int __net_init ip6_route_net_init
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
net->ipv6.fib6_has_custom_rules = false;
@ -211,7 +211,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,
sizeof(*net->ipv6.ip6_prohibit_entry),
GFP_KERNEL);
@@ -6232,11 +6268,21 @@ static int __net_init ip6_route_net_init
@@ -6234,11 +6270,21 @@ static int __net_init ip6_route_net_init
ip6_template_metrics, true);
INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);
@ -234,7 +234,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
ip6_template_metrics, true);
@@ -6260,6 +6306,8 @@ out:
@@ -6262,6 +6308,8 @@ out:
return ret;
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
out_ip6_prohibit_entry:
kfree(net->ipv6.ip6_prohibit_entry);
out_ip6_null_entry:
@@ -6279,6 +6327,7 @@ static void __net_exit ip6_route_net_exi
@@ -6281,6 +6329,7 @@ static void __net_exit ip6_route_net_exi
kfree(net->ipv6.ip6_null_entry);
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
kfree(net->ipv6.ip6_prohibit_entry);
@ -251,7 +251,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
kfree(net->ipv6.ip6_blk_hole_entry);
#endif
dst_entries_destroy(&net->ipv6.ip6_dst_ops);
@@ -6356,6 +6405,9 @@ void __init ip6_route_init_special_entri
@@ -6358,6 +6407,9 @@ void __init ip6_route_init_special_entri
init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);

2
target/linux/generic/pending-5.4/920-mangle_bootargs.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1663,6 +1663,15 @@ config EMBEDDED
@@ -1662,6 +1662,15 @@ config EMBEDDED
an embedded system so certain expert options are available
for configuration.

1
target/linux/layerscape/armv7/config-5.4
View File

@ -107,7 +107,6 @@ CONFIG_BLK_SCSI_REQUEST=y
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
CONFIG_BOUNCE=y
# CONFIG_BPF_SYSCALL is not set
CONFIG_BRCMSTB_GISB_ARB=y
CONFIG_BROADCOM_PHY=y
CONFIG_CACHE_L2X0=y

1
target/linux/layerscape/armv8_64b/config-5.4
View File

@ -132,7 +132,6 @@ CONFIG_BLK_PM=y
CONFIG_BLK_SCSI_REQUEST=y
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
# CONFIG_BPF_SYSCALL is not set
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_BTRFS_FS=y

210
target/linux/mediatek/files-5.10/drivers/leds/leds-ubnt-ledbar.c Normal file
View File

@ -0,0 +1,210 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/leds.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/gpio/consumer.h>
/**
* Driver for the Ubiquiti RGB LED controller (LEDBAR).
* This Controller is based on a Holtek HT32F52241 and connected
* via I2C.
*
* - The Controller needs an enable signal set to high when
* performing a transaction. On the U6-LR, this is located
* at Pin 18 (R6902)
*
* - The Pin is also printed when calling the "usetled" function
* contained in the ubntapp bootloader application.
*/
#define UBNT_LEDBAR_MAX_BRIGHTNESS 0xff
#define UBNT_LEDBAR_TRANSACTION_LENGTH 8
#define UBNT_LEDBAR_TRANSACTION_SUCCESS 0xaa
#define UBNT_LEDBAR_TRANSACTION_BLUE_IDX 2
#define UBNT_LEDBAR_TRANSACTION_GREEN_IDX 3
#define UBNT_LEDBAR_TRANSACTION_RED_IDX 4
struct ubnt_ledbar {
struct mutex lock;
struct i2c_client *client;
struct led_classdev led_red;
struct led_classdev led_green;
struct led_classdev led_blue;
struct gpio_desc *enable_gpio;
};
static int ubnt_ledbar_perform_transaction(struct ubnt_ledbar *ledbar,
char *transaction)
{
int ret;
int i;
for (i = 0; i < UBNT_LEDBAR_TRANSACTION_LENGTH; i++)
i2c_smbus_write_byte(ledbar->client, transaction[i]);
return i2c_smbus_read_byte(ledbar->client);
}
static int ubnt_ledbar_apply_state(struct ubnt_ledbar *ledbar)
{
char setup_msg[UBNT_LEDBAR_TRANSACTION_LENGTH] = {0x40, 0x10, 0x00, 0x00,
0x00, 0x00, 0x00, 0x11};
char led_msg[UBNT_LEDBAR_TRANSACTION_LENGTH] = {0x40, 0x00, 0x00, 0x00,
0x00, 0x00, 0x01, 0x00};
char i2c_response;
int ret = 0;
mutex_lock(&ledbar->lock);
led_msg[UBNT_LEDBAR_TRANSACTION_BLUE_IDX] = ledbar->led_blue.brightness;
led_msg[UBNT_LEDBAR_TRANSACTION_GREEN_IDX] = ledbar->led_green.brightness;
led_msg[UBNT_LEDBAR_TRANSACTION_RED_IDX] = ledbar->led_red.brightness;
gpiod_set_raw_value(ledbar->enable_gpio, 1);
msleep(10);
i2c_response = ubnt_ledbar_perform_transaction(ledbar, setup_msg);
if (i2c_response != UBNT_LEDBAR_TRANSACTION_SUCCESS) {
dev_err(&ledbar->client->dev, "Error initializing LED transaction: %02x\n", ret);
ret = -EINVAL;
goto out_gpio;
}
i2c_response = ubnt_ledbar_perform_transaction(ledbar, led_msg);
if (i2c_response != UBNT_LEDBAR_TRANSACTION_SUCCESS) {
dev_err(&ledbar->client->dev, "Failed LED transaction: %02x\n", ret);
ret = -EINVAL;
goto out_gpio;
}
msleep(10);
out_gpio:
gpiod_set_raw_value(ledbar->enable_gpio, 0);
mutex_unlock(&ledbar->lock);
return ret;
}
#define UBNT_LEDBAR_CONTROL_RGBS(name) \
static int ubnt_ledbar_set_##name##_brightness(struct led_classdev *led_cdev,\
enum led_brightness value) \
{ \
struct ubnt_ledbar *ledbar = \
container_of(led_cdev, struct ubnt_ledbar, led_##name); \
int ret; \
led_cdev->brightness = value; \
ret = ubnt_ledbar_apply_state(ledbar); \
return ret; \
}
UBNT_LEDBAR_CONTROL_RGBS(red);
UBNT_LEDBAR_CONTROL_RGBS(green);
UBNT_LEDBAR_CONTROL_RGBS(blue);
static int ubnt_ledbar_init_led(struct device_node *np, struct ubnt_ledbar *ledbar,
struct led_classdev *led_cdev)
{
struct led_init_data init_data = {};
int ret;
if (!np)
return 0;
init_data.fwnode = of_fwnode_handle(np);
led_cdev->max_brightness = UBNT_LEDBAR_MAX_BRIGHTNESS;
ret = devm_led_classdev_register_ext(&ledbar->client->dev, led_cdev,
&init_data);
if (ret)
dev_err(&ledbar->client->dev, "led register err: %d\n", ret);
return ret;
}
static int ubnt_ledbar_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct device_node *np = client->dev.of_node;
struct ubnt_ledbar *ledbar;
int ret;
ledbar = devm_kzalloc(&client->dev, sizeof(*ledbar), GFP_KERNEL);
if (!ledbar)
return -ENOMEM;
ledbar->enable_gpio = devm_gpiod_get(&client->dev, "enable", GPIOD_OUT_LOW);
if (IS_ERR(ledbar->enable_gpio)) {
ret = PTR_ERR(ledbar->enable_gpio);
dev_err(&client->dev, "Failed to get enable gpio: %d\n", ret);
return ret;
}
gpiod_direction_output(ledbar->enable_gpio, 0);
ledbar->client = client;
mutex_init(&ledbar->lock);
i2c_set_clientdata(client, ledbar);
ledbar->led_red.brightness_set_blocking = ubnt_ledbar_set_red_brightness;
ubnt_ledbar_init_led(of_get_child_by_name(np, "red"), ledbar, &ledbar->led_red);
ledbar->led_green.brightness_set_blocking = ubnt_ledbar_set_green_brightness;
ubnt_ledbar_init_led(of_get_child_by_name(np, "green"), ledbar, &ledbar->led_green);
ledbar->led_blue.brightness_set_blocking = ubnt_ledbar_set_blue_brightness;
ubnt_ledbar_init_led(of_get_child_by_name(np, "blue"), ledbar, &ledbar->led_blue);
return ubnt_ledbar_apply_state(ledbar);
}
static int ubnt_ledbar_remove(struct i2c_client *client)
{
struct ubnt_ledbar *ledbar = i2c_get_clientdata(client);
mutex_destroy(&ledbar->lock);
return 0;
}
static const struct i2c_device_id ubnt_ledbar_id[] = {
{ "ubnt-ledbar", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ubnt_ledbar_id);
static const struct of_device_id of_ubnt_ledbar_match[] = {
{ .compatible = "ubnt,ledbar", },
{},
};
MODULE_DEVICE_TABLE(of, of_ubnt_ledbar_match);
static struct i2c_driver ubnt_ledbar_driver = {
.driver = {
.name = "ubnt-ledbar",
.of_match_table = of_ubnt_ledbar_match,
},
.probe = ubnt_ledbar_probe,
.remove = ubnt_ledbar_remove,
.id_table = ubnt_ledbar_id,
};
module_i2c_driver(ubnt_ledbar_driver);
MODULE_DESCRIPTION("Ubiquiti LEDBAR driver");
MODULE_AUTHOR("David Bauer <mail@david-bauer.net>");
MODULE_LICENSE("GPL v2");

5
target/linux/mediatek/mt7622/config-5.10
View File

@ -203,6 +203,10 @@ CONFIG_HAS_IOPORT_MAP=y
CONFIG_HOLES_IN_ZONE=y
CONFIG_HZ=250
CONFIG_HZ_250=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MT65XX=y
CONFIG_ICPLUS_PHY=y
CONFIG_IIO=y
CONFIG_IKCONFIG=y
@ -217,6 +221,7 @@ CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
CONFIG_JUMP_LABEL=y
CONFIG_LEDS_UBNT_LEDBAR=y
CONFIG_LIBFDT=y
CONFIG_LLD_VERSION=0
CONFIG_LOCK_DEBUGGING_SUPPORT=y

4
target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch
View File

@ -1,5 +1,5 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts 2021-03-13 13:46:37.057936814 +0200
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts 2021-03-13 13:49:26.957481217 +0200
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -114,7 +114,7 @@
};

2
target/linux/mediatek/patches-5.10/602-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
View File

@ -253,7 +253,7 @@ Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
#interrupt-cells = <1>;
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -270,18 +270,16 @@
@@ -296,18 +296,16 @@
};
};

2
target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -279,14 +279,14 @@
@@ -305,14 +305,14 @@
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;

2
target/linux/mediatek/patches-5.4/0601-net-dsa-propagate-resolved-link-config-via-mac_link_.patch
View File

@ -51,7 +51,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
struct ethtool_eee *p = &priv->dev->ports[port].eee;
--- a/drivers/net/dsa/lantiq_gswip.c
+++ b/drivers/net/dsa/lantiq_gswip.c
@@ -1508,7 +1508,9 @@ static void gswip_phylink_mac_link_down(
@@ -1657,7 +1657,9 @@ static void gswip_phylink_mac_link_down(
static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
unsigned int mode,
phy_interface_t interface,

8
target/linux/mediatek/patches-5.4/115-dts-bpi64-add-snand-support.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts 2021-03-13 13:46:37.057936814 +0200
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts 2021-03-13 13:49:26.957481217 +0200
@@ -114,7 +114,7 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -108,7 +108,7 @@
};
&bch {
@ -9,7 +9,7 @@
};
&btif {
@@ -259,14 +259,40 @@
@@ -283,14 +283,40 @@
status = "disabled";
};

3
target/linux/mvebu/cortexa53/base-files/lib/upgrade/platform.sh
View File

@ -9,6 +9,7 @@ REQUIRE_IMAGE_METADATA=1
platform_check_image() {
case "$(board_name)" in
glinet,gl-mv1000|\
globalscale,espressobin|\
globalscale,espressobin-emmc|\
globalscale,espressobin-ultra|\
@ -24,6 +25,7 @@ platform_check_image() {
platform_do_upgrade() {
case "$(board_name)" in
glinet,gl-mv1000|\
globalscale,espressobin|\
globalscale,espressobin-emmc|\
globalscale,espressobin-ultra|\
@ -41,6 +43,7 @@ platform_do_upgrade() {
}
platform_copy_config() {
case "$(board_name)" in
glinet,gl-mv1000|\
globalscale,espressobin|\
globalscale,espressobin-emmc|\
globalscale,espressobin-ultra|\

64
target/linux/mvebu/patches-5.10/101-ARM-dts-turris-omnia-configure-LED-2--INTn-pin-as-interrupt-pin.patch
View File

@ -1,64 +0,0 @@
From: "Marek Behún" <kabel@kernel.org>
To: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: "Marek Behún" <kabel@kernel.org>, Rui Salvaterra <rsalvaterra@gmail.com>, "Uwe Kleine-König" <uwe@kleine-koenig.org>, linux-arm-kernel@lists.infradead.org, Andrew Lunn <andrew@lunn.ch>, stable@vger.kernel.org
Subject: [PATCH mvebu-dt] ARM: dts: turris-omnia: configure LED[2]/INTn pin as interrupt pin
Date: Sun, 21 Feb 2021 00:11:44 +0100
Message-Id: <20210220231144.32325-1-kabel@kernel.org>
X-Mailer: git-send-email 2.26.2
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Use the `marvell,reg-init` DT property to configure the LED[2]/INTn pin
of the Marvell 88E1514 ethernet PHY on Turris Omnia into interrupt mode.
Without this the pin is by default in LED[2] mode, and the Marvell PHY
driver configures LED[2] into "On - Link, Blink - Activity" mode.
This fixes the issue where the pca9538 GPIO/interrupt controller (which
can't mask interrupts in HW) received too many interrupts and after a
time started ignoring the interrupt with error message:
IRQ 71: nobody cared
There is a work in progress to have the Marvell PHY driver support
parsing PHY LED nodes from OF and registering the LEDs as Linux LED
class devices. Once this is done the PHY driver can also automatically
set the pin into INTn mode if it does not find LED[2] in OF.
Until then, though, we fix this via `marvell,reg-init` DT property.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reported-by: Rui Salvaterra <rsalvaterra@gmail.com>
Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia")
Cc: Uwe Kleine-König <uwe@kleine-koenig.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: <stable@vger.kernel.org>
---
This patch fixes bug introduced with the commit that added Turris
Omnia's DTS (26ca8b52d6e1), but will not apply cleanly because there is
commit 8ee4a5f4f40d which changed node name and node compatible
property and this commit did not go into stable.
So either commit 8ee4a5f4f40d has also to go into stable before this, or
this patch has to be fixed a little in order to apply to 4.14+.
Please let me know how should I handle this.
---
arch/arm/boot/dts/armada-385-turris-omnia.dts | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -254,6 +254,7 @@
status = "okay";
compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
reg = <1>;
+ marvell,reg-init = <3 18 0 0x4985>;
/* irq is connected to &pcawan pin 7 */
};

29
target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch Normal file
View File

@ -0,0 +1,29 @@
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -234,7 +234,7 @@
clocks = <&gateclk 23>;
clock-names = "cesa0";
marvell,crypto-srams = <&crypto_sram>;
- marvell,crypto-sram-size = <0x7e0>;
+ marvell,crypto-sram-size = <0x800>;
};
};
@@ -255,12 +255,17 @@
* cpuidle workaround.
*/
idle-sram@0 {
+ status = "disabled";
reg = <0x0 0x20>;
};
};
};
};
+&coherencyfab {
+ broken-idle;
+};
+
/*
* Default UART pinctrl setting without RTS/CTS, can be overwritten on
* board level if a different configuration is used.

64
target/linux/mvebu/patches-5.4/319-ARM-dts-turris-omnia-configure-LED-2--INTn-pin-as-interrupt-pin.patch
View File

@ -1,64 +0,0 @@
From: "Marek Behún" <kabel@kernel.org>
To: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: "Marek Behún" <kabel@kernel.org>, Rui Salvaterra <rsalvaterra@gmail.com>, "Uwe Kleine-König" <uwe@kleine-koenig.org>, linux-arm-kernel@lists.infradead.org, Andrew Lunn <andrew@lunn.ch>, stable@vger.kernel.org
Subject: [PATCH mvebu-dt] ARM: dts: turris-omnia: configure LED[2]/INTn pin as interrupt pin
Date: Sun, 21 Feb 2021 00:11:44 +0100
Message-Id: <20210220231144.32325-1-kabel@kernel.org>
X-Mailer: git-send-email 2.26.2
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Use the `marvell,reg-init` DT property to configure the LED[2]/INTn pin
of the Marvell 88E1514 ethernet PHY on Turris Omnia into interrupt mode.
Without this the pin is by default in LED[2] mode, and the Marvell PHY
driver configures LED[2] into "On - Link, Blink - Activity" mode.
This fixes the issue where the pca9538 GPIO/interrupt controller (which
can't mask interrupts in HW) received too many interrupts and after a
time started ignoring the interrupt with error message:
IRQ 71: nobody cared
There is a work in progress to have the Marvell PHY driver support
parsing PHY LED nodes from OF and registering the LEDs as Linux LED
class devices. Once this is done the PHY driver can also automatically
set the pin into INTn mode if it does not find LED[2] in OF.
Until then, though, we fix this via `marvell,reg-init` DT property.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reported-by: Rui Salvaterra <rsalvaterra@gmail.com>
Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia")
Cc: Uwe Kleine-König <uwe@kleine-koenig.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: <stable@vger.kernel.org>
---
This patch fixes bug introduced with the commit that added Turris
Omnia's DTS (26ca8b52d6e1), but will not apply cleanly because there is
commit 8ee4a5f4f40d which changed node name and node compatible
property and this commit did not go into stable.
So either commit 8ee4a5f4f40d has also to go into stable before this, or
this patch has to be fixed a little in order to apply to 4.14+.
Please let me know how should I handle this.
---
arch/arm/boot/dts/armada-385-turris-omnia.dts | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -254,6 +254,7 @@
status = "okay";
compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
reg = <1>;
+ marvell,reg-init = <3 18 0 0x4985>;
/* irq is connected to &pcawan pin 7 */
};

29
target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch Normal file
View File

@ -0,0 +1,29 @@
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -234,7 +234,7 @@
clocks = <&gateclk 23>;
clock-names = "cesa0";
marvell,crypto-srams = <&crypto_sram>;
- marvell,crypto-sram-size = <0x7e0>;
+ marvell,crypto-sram-size = <0x800>;
};
};
@@ -255,12 +255,17 @@
* cpuidle workaround.
*/
idle-sram@0 {
+ status = "disabled";
reg = <0x0 0x20>;
};
};
};
};
+&coherencyfab {
+ broken-idle;
+};
+
/*
* Default UART pinctrl setting without RTS/CTS, can be overwritten on
* board level if a different configuration is used.

3
target/linux/oxnas/config-5.10
View File

@ -65,7 +65,6 @@ CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_BLK_PM=y
CONFIG_BLK_SCSI_REQUEST=y
# CONFIG_BPF_SYSCALL is not set
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_MMIO=y
@ -101,7 +100,6 @@ CONFIG_CPU_PABRT_LEGACY=y
CONFIG_CPU_PM=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V4WBI=y
# CONFIG_CPU_THERMAL is not set
CONFIG_CPU_USE_DOMAINS=y
CONFIG_CRASH_CORE=y
CONFIG_CRC16=y
@ -122,7 +120,6 @@ CONFIG_DECOMPRESS_XZ=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DMA_CMA=y
# CONFIG_DMA_PERNUMA_CMA is not set
CONFIG_DMA_REMAP=y
CONFIG_DNOTIFY=y
CONFIG_DTC=y

1
target/linux/oxnas/config-5.4
View File

@ -65,7 +65,6 @@ CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_BLK_PM=y
CONFIG_BLK_SCSI_REQUEST=y
# CONFIG_BPF_SYSCALL is not set
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_MMIO=y

2
target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi
View File

@ -49,7 +49,7 @@
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-max-frequency = <50000000>;
m25p,fast-read;
partitions {

74
target/linux/ramips/patches-5.10/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch Normal file
View File

@ -0,0 +1,74 @@
From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001
From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Date: Wed, 7 Apr 2021 13:07:38 -0700
Subject: [PATCH] MIPS: add support for buggy MT7621S core detection
Most MT7621 SoCs have 2 cores, which is detected and supported properly
by CPS.
Unfortunately, MT7621 SoC has a less common S variant with only one core.
On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when
starting SMP. CPULAUNCH registers can be used in that case to detect the
absence of the second core and override the GCR_CONFIG PCORES field.
Rework a long-standing OpenWrt patch to override the value of
mips_cps_numcores on single-core MT7621 systems.
Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core
MT7621 device (Netgear R6220).
Original 4.14 OpenWrt patch:
Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7
Current 5.10 OpenWrt patch:
Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904
Suggested-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
--- a/arch/mips/include/asm/mips-cps.h
+++ b/arch/mips/include/asm/mips-cps.h
@@ -10,6 +10,8 @@
#include <linux/io.h>
#include <linux/types.h>
+#include <asm/mips-boards/launch.h>
+
extern unsigned long __cps_access_bad_size(void)
__compiletime_error("Bad size for CPS accessor");
@@ -165,11 +167,30 @@ static inline uint64_t mips_cps_cluster_
*/
static inline unsigned int mips_cps_numcores(unsigned int cluster)
{
+ unsigned int ncores;
+
if (!mips_cm_present())
return 0;
/* Add one before masking to handle 0xff indicating no cores */
- return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
+ ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
+
+ if (IS_ENABLED(CONFIG_SOC_MT7621)) {
+ struct cpulaunch *launch;
+
+ /*
+ * Ralink MT7621S SoC is single core, but the GCR_CONFIG method
+ * always reports 2 cores. Check the second core's LAUNCH_FREADY
+ * flag to detect if the second core is missing. This method
+ * only works before the core has been started.
+ */
+ launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
+ launch += 2; /* MT7621 has 2 VPEs per core */
+ if (!(launch->flags & LAUNCH_FREADY))
+ ncores = 1;
+ }
+
+ return ncores;
}
/**

61
target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch
View File

@ -1,61 +0,0 @@
There is a variant of MT7621 which contains only one CPU core instead of 2.
This is not reflected in the config register, so the kernel detects more
physical cores, which leads to a hang on SMP bringup.
Add a hack to detect missing cores.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -43,6 +43,11 @@ static unsigned core_vpe_count(unsigned
return mips_cps_numvps(cluster, core);
}
+bool __weak plat_cpu_core_present(int core)
+{
+ return true;
+}
+
static void __init cps_smp_setup(void)
{
unsigned int nclusters, ncores, nvpes, core_vpes;
@@ -60,6 +65,8 @@ static void __init cps_smp_setup(void)
ncores = mips_cps_numcores(cl);
for (c = 0; c < ncores; c++) {
+ if (!plat_cpu_core_present(c))
+ continue;
core_vpes = core_vpe_count(cl, c);
if (c > 0)
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -15,6 +15,7 @@
#include <asm/mips-cps.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7621.h>
+#include <asm/mips-boards/launch.h>
#include <pinmux.h>
@@ -146,6 +147,20 @@ static void soc_dev_init(struct ralink_s
}
}
+bool plat_cpu_core_present(int core)
+{
+ struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
+
+ if (!core)
+ return true;
+ launch += core * 2; /* 2 VPEs per core */
+ if (!(launch->flags & LAUNCH_FREADY))
+ return false;
+ if (launch->flags & (LAUNCH_FGO | LAUNCH_FGONE))
+ return false;
+ return true;
+}
+
void prom_soc_init(struct ralink_soc_info *soc_info)
{
void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);

7
target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch
View File

@ -36,7 +36,7 @@
#define MT7621_DDR2_SIZE_MAX 256
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -9,6 +9,10 @@
@@ -9,12 +9,17 @@
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
@ -47,15 +47,14 @@
#include <asm/mipsregs.h>
#include <asm/smp-ops.h>
@@ -16,6 +20,7 @@
#include <asm/mips-cps.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7621.h>
#include <asm/mips-boards/launch.h>
+#include <asm/time.h>
#include <pinmux.h>
@@ -106,11 +111,89 @@ static struct rt2880_pmx_group mt7621_pi
@@ -105,11 +110,89 @@ static struct rt2880_pmx_group mt7621_pi
{ 0 }
};

8
target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch
View File

@ -58,7 +58,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
#include <asm/mipsregs.h>
#include <asm/smp-ops.h>
#include <asm/mips-cps.h>
@@ -55,6 +57,8 @@
@@ -54,6 +56,8 @@
#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
#define MT7621_GPIO_MODE_SDHCI_GPIO 1
@ -67,7 +67,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
static struct rt2880_pmx_func uart3_grp[] = {
@@ -139,6 +143,26 @@ static struct clk *__init mt7621_add_sys
@@ -138,6 +142,26 @@ static struct clk *__init mt7621_add_sys
return clk;
}
@ -94,7 +94,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
void __init ralink_clk_init(void)
{
u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
@@ -292,10 +316,7 @@ void prom_soc_init(struct ralink_soc_inf
@@ -277,10 +301,7 @@ void prom_soc_init(struct ralink_soc_inf
(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
(rev & CHIP_REV_ECO_MASK));
@ -118,7 +118,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -85,6 +85,8 @@ void __init plat_mem_setup(void)
@@ -83,6 +83,8 @@ void __init plat_mem_setup(void)
of_scan_flat_dt(early_init_dt_find_memory, NULL);
if (memory_dtb)
of_scan_flat_dt(early_init_dt_scan_memory, NULL);

14
target/linux/ramips/patches-5.10/710-at803x.patch
View File

@ -139,11 +139,11 @@ Signed-off-by: René van Dorst <opensource@vdorst.com>
ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
if (ret < 0)
return ret;
@@ -1120,6 +1203,7 @@ static struct phy_driver at803x_driver[]
.suspend = at803x_suspend,
.resume = at803x_resume,
/* PHY_GBIT_FEATURES */
@@ -1110,6 +1193,7 @@ static struct phy_driver at803x_driver[]
/* Qualcomm Atheros AR8031/AR8033 */
PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
.name = "Qualcomm Atheros AR8031/AR8033",
+ .config_aneg = at803x_config_aneg,
.read_status = at803x_read_status,
.aneg_done = at803x_aneg_done,
.ack_interrupt = &at803x_ack_interrupt,
.flags = PHY_POLL_CABLE_TEST,
.probe = at803x_probe,
.remove = at803x_remove,

6
target/linux/ramips/patches-5.4/991-at803x.patch
View File

@ -146,11 +146,11 @@ Signed-off-by: René van Dorst <opensource@vdorst.com>
static struct phy_driver at803x_driver[] = {
{
/* ATHEROS 8035 */
@@ -491,6 +581,7 @@ static struct phy_driver at803x_driver[]
@@ -461,6 +551,7 @@ static struct phy_driver at803x_driver[]
.suspend = at803x_suspend,
.resume = at803x_resume,
/* PHY_GBIT_FEATURES */
+ .config_aneg = at803x_config_aneg,
.read_status = at803x_read_status,
.aneg_done = at803x_aneg_done,
.ack_interrupt = &at803x_ack_interrupt,
.ack_interrupt = at803x_ack_interrupt,
.config_intr = at803x_config_intr,

2
target/linux/rockchip/armv8/base-files/etc/board.d/02_network
View File

@ -20,7 +20,7 @@ rockchip_setup_interfaces()
nanopi_r2s_generate_mac()
{
local sd_hash=$(sha256sum /sys/devices/platform/ff500000.dwmmc/mmc_host/mmc0/mmc0:*/cid)
local sd_hash=$(sha256sum /sys/class/block/mmcblk0/device/cid)
local mac_base=$(macaddr_canonicalize "$(echo "${sd_hash}" | dd bs=1 count=12 2>/dev/null)")
echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${mac_base}")")"
}

5
target/linux/rockchip/armv8/config-5.10
View File

@ -193,10 +193,10 @@ CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
# CONFIG_DMA_PERNUMA_CMA is not set
CONFIG_DMA_REMAP=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DNOTIFY=y
# CONFIG_DRM_ROCKCHIP is not set
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
CONFIG_DUMMY_CONSOLE=y
@ -296,6 +296,7 @@ CONFIG_INPUT_KEYBOARD=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_MATRIXKMAP=y
# CONFIG_INPUT_MISC is not set
# CONFIG_INPUT_RK805_PWRKEY is not set
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
@ -521,6 +522,7 @@ CONFIG_ROCKCHIP_MBOX=y
# CONFIG_ROCKCHIP_OTP is not set
CONFIG_ROCKCHIP_PHY=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
# CONFIG_ROCKCHIP_SARADC is not set
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
@ -566,6 +568,7 @@ CONFIG_SG_POOL=y
CONFIG_SIMPLE_PM_BUS=y
CONFIG_SLUB_DEBUG=y
CONFIG_SMP=y
# CONFIG_SND_SOC_ROCKCHIP is not set
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_MANUAL=y

10
target/linux/rockchip/patches-5.10/105-rockchip-rock-pi-4.patch Normal file
View File

@ -0,0 +1,10 @@
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -35,6 +35,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pi
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb

501
target/linux/sunxi/patches-5.4/440-add-h6-pwm.patch
View File

@ -1,8 +1,17 @@
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 581d23287333..487899d4cc3f 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -16,6 +16,7 @@
@@ -3,6 +3,10 @@
* Driver for Allwinner sun4i Pulse Width Modulation Controller
*
* Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
+ *
+ * Limitations:
+ * - When outputing the source clock directly, the PWM logic will be bypassed
+ * and the currently running period is not guaranteed to be completed
*/
#include <linux/bitops.h>
@@ -16,6 +20,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
@ -10,182 +19,70 @@ index 581d23287333..487899d4cc3f 100644
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/time.h>
@@ -78,6 +79,7 @@ struct sun4i_pwm_data {
struct sun4i_pwm_chip {
struct pwm_chip chip;
struct clk *clk;
+ struct reset_control *rst;
void __iomem *base;
spinlock_t ctrl_lock;
const struct sun4i_pwm_data *data;
@@ -364,6 +366,22 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->clk))
return PTR_ERR(pwm->clk);
@@ -72,12 +77,15 @@ static const u32 prescaler_table[] = {
+ pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
+ if (IS_ERR(pwm->rst)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "get reset failed %pe\n",
+ pwm->rst);
+ return PTR_ERR(pwm->rst);
+ }
+
+ /* Deassert reset */
+ ret = reset_control_deassert(pwm->rst);
+ if (ret) {
+ dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
+ ERR_PTR(ret));
+ return ret;
+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;
@@ -376,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
ret = pwmchip_add(&pwm->chip);
if (ret < 0) {
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
- return ret;
+ goto err_pwm_add;
}
platform_set_drvdata(pdev, pwm);
return 0;
+
+err_pwm_add:
+ reset_control_assert(pwm->rst);
+
+ return ret;
}
static int sun4i_pwm_remove(struct platform_device *pdev)
{
struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = pwmchip_remove(&pwm->chip);
+ if (ret)
+ return ret;
+
+ reset_control_assert(pwm->rst);
- return pwmchip_remove(&pwm->chip);
+ return 0;
}
static struct platform_driver sun4i_pwm_driver = {
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 487899d4cc3f..80026167044b 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->base))
return PTR_ERR(pwm->base);
- pwm->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(pwm->clk))
+ /*
+ * All hardware variants need a source clock that is divided and
+ * then feeds the counter that defines the output wave form. In the
+ * device tree this clock is either unnamed or called "mod".
+ * Some variants (e.g. H6) need another clock to access the
+ * hardware registers; this is called "bus".
+ * So we request "mod" first (and ignore the corner case that a
+ * parent provides a "mod" clock while the right one would be the
+ * unnamed one of the PWM device) and if this is not found we fall
+ * back to the first clock of the PWM.
+ */
+ pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
+ if (IS_ERR(pwm->clk)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "get mod clock failed %pe\n",
+ pwm->clk);
return PTR_ERR(pwm->clk);
+ }
+
+ if (!pwm->clk) {
+ pwm->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pwm->clk)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "get unnamed clock failed %pe\n",
+ pwm->clk);
+ return PTR_ERR(pwm->clk);
+ }
+ }
pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
if (IS_ERR(pwm->rst)) {
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 80026167044b..a6727dd89e28 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -78,6 +78,7 @@ struct sun4i_pwm_data {
struct sun4i_pwm_data {
bool has_prescaler_bypass;
+ bool has_direct_mod_clk_output;
unsigned int npwm;
};
struct sun4i_pwm_chip {
struct pwm_chip chip;
+ struct clk *bus_clk;
struct clk *clk;
struct reset_control *rst;
+ struct reset_control *rst;
void __iomem *base;
@@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
}
}
spinlock_t ctrl_lock;
const struct sun4i_pwm_data *data;
@@ -115,6 +123,20 @@ static void sun4i_pwm_get_state(struct p
+ pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
+ if (IS_ERR(pwm->bus_clk)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "get bus clock failed %pe\n",
+ pwm->bus_clk);
+ return PTR_ERR(pwm->bus_clk);
+ }
+
pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
if (IS_ERR(pwm->rst)) {
if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
@@ -407,6 +416,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
return ret;
}
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
+ /*
+ * We're keeping the bus clock on for the sake of simplicity.
+ * Actually it only needs to be on for hardware register accesses.
+ * PWM chapter in H6 manual has a diagram which explains that if bypass
+ * bit is set, no other setting has any meaning. Even more, experiment
+ * proved that also enable bit is ignored in this case.
+ */
+ ret = clk_prepare_enable(pwm->bus_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
+ ERR_PTR(ret));
+ goto err_bus;
+ if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
+ sun4i_pwm->data->has_direct_mod_clk_output) {
+ state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
+ state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
+ state->polarity = PWM_POLARITY_NORMAL;
+ state->enabled = true;
+ return;
+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;
@@ -427,6 +447,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
return 0;
if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
sun4i_pwm->data->has_prescaler_bypass)
prescaler = 1;
@@ -146,13 +168,24 @@ static void sun4i_pwm_get_state(struct p
err_pwm_add:
+ clk_disable_unprepare(pwm->bus_clk);
+err_bus:
reset_control_assert(pwm->rst);
static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
const struct pwm_state *state,
- u32 *dty, u32 *prd, unsigned int *prsclr)
+ u32 *dty, u32 *prd, unsigned int *prsclr,
+ bool *bypass)
{
u64 clk_rate, div = 0;
unsigned int pval, prescaler = 0;
return ret;
@@ -441,6 +463,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev)
if (ret)
return ret;
clk_rate = clk_get_rate(sun4i_pwm->clk);
+ clk_disable_unprepare(pwm->bus_clk);
reset_control_assert(pwm->rst);
return 0;
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index a6727dd89e28..e369b5a398f4 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -202,9 +202,9 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
+ state->enabled &&
+ (state->period * clk_rate >= NSEC_PER_SEC) &&
+ (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
+ (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
+
+ /* Skip calculation of other parameters if we bypass them */
+ if (*bypass)
+ return 0;
+
if (sun4i_pwm->data->has_prescaler_bypass) {
/* First, test without any prescaler when available */
prescaler = PWM_PRESCAL_MASK;
@@ -200,10 +233,11 @@ static int sun4i_pwm_apply(struct pwm_ch
{
struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
struct pwm_state cstate;
@ -195,9 +92,11 @@ index a6727dd89e28..e369b5a398f4 100644
- unsigned int delay_us;
+ unsigned int delay_us, prescaler;
unsigned long now;
+ bool bypass;
pwm_get_state(pwm, &cstate);
@@ -220,43 +220,37 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
@@ -218,43 +252,50 @@ static int sun4i_pwm_apply(struct pwm_ch
spin_lock(&sun4i_pwm->ctrl_lock);
ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
@ -205,22 +104,8 @@ index a6727dd89e28..e369b5a398f4 100644
- (cstate.duty_cycle != state->duty_cycle)) {
- u32 period, duty, val;
- unsigned int prescaler;
-
- ret = sun4i_pwm_calculate(sun4i_pwm, state,
- &duty, &period, &prescaler);
- if (ret) {
- dev_err(chip->dev, "period exceeds the maximum value\n");
- spin_unlock(&sun4i_pwm->ctrl_lock);
- if (!cstate.enabled)
- clk_disable_unprepare(sun4i_pwm->clk);
- return ret;
- }
-
- if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
- /* Prescaler changed, the clock has to be gated */
- ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
- sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
+ ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler);
+ ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
+ &bypass);
+ if (ret) {
+ dev_err(chip->dev, "period exceeds the maximum value\n");
+ spin_unlock(&sun4i_pwm->ctrl_lock);
@ -229,6 +114,30 @@ index a6727dd89e28..e369b5a398f4 100644
+ return ret;
+ }
- ret = sun4i_pwm_calculate(sun4i_pwm, state,
- &duty, &period, &prescaler);
- if (ret) {
- dev_err(chip->dev, "period exceeds the maximum value\n");
+ if (sun4i_pwm->data->has_direct_mod_clk_output) {
+ if (bypass) {
+ ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
+ /* We can skip other parameter */
+ sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
spin_unlock(&sun4i_pwm->ctrl_lock);
- if (!cstate.enabled)
- clk_disable_unprepare(sun4i_pwm->clk);
- return ret;
+ return 0;
+ } else {
+ ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
}
+ }
- if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
- /* Prescaler changed, the clock has to be gated */
- ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
- sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
-
- ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
- ctrl |= BIT_CH(prescaler, pwm->hwpwm);
- }
@ -262,120 +171,7 @@ index a6727dd89e28..e369b5a398f4 100644
if (state->enabled) {
ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
} else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index e369b5a398f4..07bf7be6074b 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -3,6 +3,10 @@
* Driver for Allwinner sun4i Pulse Width Modulation Controller
*
* Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
+ *
+ * Limitations:
+ * - When outputing the source clock directly, the PWM logic will be bypassed
+ * and the currently running period is not guaranteed to be completed
*/
#include <linux/bitops.h>
@@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
struct sun4i_pwm_data {
bool has_prescaler_bypass;
+ bool has_direct_mod_clk_output;
unsigned int npwm;
};
@@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
+ /*
+ * PWM chapter in H6 manual has a diagram which explains that if bypass
+ * bit is set, no other setting has any meaning. Even more, experiment
+ * proved that also enable bit is ignored in this case.
+ */
+ if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
+ sun4i_pwm->data->has_direct_mod_clk_output) {
+ state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
+ state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
+ state->polarity = PWM_POLARITY_NORMAL;
+ state->enabled = true;
+ return;
+ }
+
if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
sun4i_pwm->data->has_prescaler_bypass)
prescaler = 1;
@@ -149,13 +168,24 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
const struct pwm_state *state,
- u32 *dty, u32 *prd, unsigned int *prsclr)
+ u32 *dty, u32 *prd, unsigned int *prsclr,
+ bool *bypass)
{
u64 clk_rate, div = 0;
unsigned int pval, prescaler = 0;
clk_rate = clk_get_rate(sun4i_pwm->clk);
+ *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
+ state->enabled &&
+ (state->period * clk_rate >= NSEC_PER_SEC) &&
+ (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
+ (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
+
+ /* Skip calculation of other parameters if we bypass them */
+ if (*bypass)
+ return 0;
+
if (sun4i_pwm->data->has_prescaler_bypass) {
/* First, test without any prescaler when available */
prescaler = PWM_PRESCAL_MASK;
@@ -206,6 +236,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
int ret;
unsigned int delay_us, prescaler;
unsigned long now;
+ bool bypass;
pwm_get_state(pwm, &cstate);
@@ -220,7 +251,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
spin_lock(&sun4i_pwm->ctrl_lock);
ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
- ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler);
+ ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
+ &bypass);
if (ret) {
dev_err(chip->dev, "period exceeds the maximum value\n");
spin_unlock(&sun4i_pwm->ctrl_lock);
@@ -229,6 +261,18 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
return ret;
}
+ if (sun4i_pwm->data->has_direct_mod_clk_output) {
+ if (bypass) {
+ ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
+ /* We can skip other parameter */
+ sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
+ spin_unlock(&sun4i_pwm->ctrl_lock);
+ return 0;
+ } else {
+ ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
+ }
+ }
+
if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
/* Prescaler changed, the clock has to be gated */
ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 07bf7be6074b..c394878c7e5d 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -360,6 +360,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
@@ -320,6 +361,12 @@ static const struct sun4i_pwm_data sun4i
.npwm = 1,
};
@ -388,13 +184,122 @@ index 07bf7be6074b..c394878c7e5d 100644
static const struct of_device_id sun4i_pwm_dt_ids[] = {
{
.compatible = "allwinner,sun4i-a10-pwm",
@@ -376,6 +382,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = {
}, {
@@ -337,6 +384,9 @@ static const struct of_device_id sun4i_p
.compatible = "allwinner,sun8i-h3-pwm",
.data = &sun4i_pwm_single_bypass,
+ }, {
}, {
+ .compatible = "allwinner,sun50i-h6-pwm",
+ .data = &sun50i_h6_pwm_data,
}, {
+ }, {
/* sentinel */
},
};
@@ -361,9 +411,69 @@ static int sun4i_pwm_probe(struct platfo
if (IS_ERR(pwm->base))
return PTR_ERR(pwm->base);
- pwm->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(pwm->clk))
+ /*
+ * All hardware variants need a source clock that is divided and
+ * then feeds the counter that defines the output wave form. In the
+ * device tree this clock is either unnamed or called "mod".
+ * Some variants (e.g. H6) need another clock to access the
+ * hardware registers; this is called "bus".
+ * So we request "mod" first (and ignore the corner case that a
+ * parent provides a "mod" clock while the right one would be the
+ * unnamed one of the PWM device) and if this is not found we fall
+ * back to the first clock of the PWM.
+ */
+ pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
+ if (IS_ERR(pwm->clk)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "get mod clock failed %pe\n",
+ pwm->clk);
return PTR_ERR(pwm->clk);
+ }
+
+ if (!pwm->clk) {
+ pwm->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pwm->clk)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "get unnamed clock failed %pe\n",
+ pwm->clk);
+ return PTR_ERR(pwm->clk);
+ }
+ }
+
+ pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
+ if (IS_ERR(pwm->bus_clk)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "get bus clock failed %pe\n",
+ pwm->bus_clk);
+ return PTR_ERR(pwm->bus_clk);
+ }
+
+ pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
+ if (IS_ERR(pwm->rst)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "get reset failed %pe\n",
+ pwm->rst);
+ return PTR_ERR(pwm->rst);
+ }
+
+ /* Deassert reset */
+ ret = reset_control_deassert(pwm->rst);
+ if (ret) {
+ dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
+ ERR_PTR(ret));
+ return ret;
+ }
+
+ /*
+ * We're keeping the bus clock on for the sake of simplicity.
+ * Actually it only needs to be on for hardware register accesses.
+ */
+ ret = clk_prepare_enable(pwm->bus_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
+ ERR_PTR(ret));
+ goto err_bus;
+ }
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
@@ -377,19 +487,34 @@ static int sun4i_pwm_probe(struct platfo
ret = pwmchip_add(&pwm->chip);
if (ret < 0) {
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
- return ret;
+ goto err_pwm_add;
}
platform_set_drvdata(pdev, pwm);
return 0;
+
+err_pwm_add:
+ clk_disable_unprepare(pwm->bus_clk);
+err_bus:
+ reset_control_assert(pwm->rst);
+
+ return ret;
}
static int sun4i_pwm_remove(struct platform_device *pdev)
{
struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = pwmchip_remove(&pwm->chip);
+ if (ret)
+ return ret;
- return pwmchip_remove(&pwm->chip);
+ clk_disable_unprepare(pwm->bus_clk);
+ reset_control_assert(pwm->rst);
+
+ return 0;
}
static struct platform_driver sun4i_pwm_driver = {

4
target/linux/sunxi/patches-5.4/441-arm64-dts-add-PWM-node.patch
View File

@ -14,11 +14,9 @@ Signed-off-by: Clément Péron <peron.clem@gmail.com>
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 29824081b43b..6d4bde488f15 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -245,6 +245,16 @@
@@ -231,6 +231,16 @@
status = "disabled";
};

8
target/linux/sunxi/patches-5.4/442-arm64-dts-orangepi-one-plus-enable-PWM.patch
View File

@ -1,10 +1,8 @@
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
index f335f7482a73..cf684bc7374d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
@@ -45,3 +45,7 @@
reg = <1>;
};
@@ -10,3 +10,7 @@
model = "OrangePi One Plus";
compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
};
+
+&pwm {

6
target/linux/sunxi/patches-5.4/443-board-h6-orangepioneplus-fix-missing-ethernet.patch
View File

@ -1,8 +1,6 @@
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
index 12e1756..79139f3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
@@ -9,4 +9,39 @@
@@ -9,6 +9,41 @@
/ {
model = "OrangePi One Plus";
compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
@ -42,3 +40,5 @@ index 12e1756..79139f3 100644
+ reg = <1>;
+ };
};
&pwm {

2
target/linux/x86/image/64.mk
View File

@ -1,7 +1,7 @@
define Device/generic
DEVICE_TITLE := Generic x86/64
DEVICE_PACKAGES += kmod-amazon-ena kmod-bnx2 kmod-e1000e kmod-e1000 \
kmod-forcedeth kmod-igb kmod-ixgbe kmod-r8169
kmod-forcedeth kmod-igb kmod-ixgbe kmod-amd-xgbe kmod-r8169
GRUB2_VARIANT := generic
endef
TARGET_DEVICES += generic

16
target/linux/x86/modules.mk
View File

@ -19,6 +19,22 @@ endef
$(eval $(call KernelPackage,amazon-ena))
define KernelPackage/amd-xgbe
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=AMD Ethernet on SoC support
DEPENDS:=@PCI_SUPPORT @TARGET_x86_64 +kmod-lib-crc32c +kmod-ptp +kmod-libphy +LINUX_5_10:kmod-mdio-devres
KCONFIG:=CONFIG_AMD_XGBE
FILES:=$(LINUX_DIR)/drivers/net/ethernet/amd/xgbe/amd-xgbe.ko
AUTOLOAD:=$(call AutoLoad,35,amd-xgbe)
endef
define KernelPackage/amd-xgbe/description
Kernel modules for AMD 10GbE Ethernet device on an AMD SoC.
endef
$(eval $(call KernelPackage,amd-xgbe))
define KernelPackage/sound-cs5535audio
TITLE:=CS5535/CS5536 Audio Controller
DEPENDS:=@TARGET_x86_geode +kmod-ac97

1
toolchain/gdb/Makefile
View File

@ -22,6 +22,7 @@ HOST_BUILD_PARALLEL:=1
include $(INCLUDE_DIR)/toolchain-build.mk
HOST_CONFIGURE_VARS += \
acx_cv_cc_gcc_supports_ada=false \
gdb_cv_func_sigsetjmp=yes
HOST_CONFIGURE_ARGS = \

4
toolchain/glibc/common.mk
View File

@ -12,8 +12,8 @@ PKG_RELEASE:=2
PKG_SOURCE_PROTO:=git
PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
PKG_SOURCE_VERSION:=e78ea9bd26199497b9f047e421f16284297629cf
PKG_MIRROR_HASH:=1e08d10f04333cc6cd82c6cfc4c83a37db6b7ce1523b3f6e56673178379a9c2c
PKG_SOURCE_VERSION:=12ff80b312c11b0284df7a1c5cb9be6418f85228
PKG_MIRROR_HASH:=84b7715886320794f9787976b20c868f5d6967e0ab08e6c821a8d42103c0721b
PKG_SOURCE_URL:=https://sourceware.org/git/glibc.git
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.xz