From 91ef14a487a51b5f6d20f8f2cc9d1b485535fddc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20M?= Date: Tue, 31 Oct 2023 16:15:06 +0100 Subject: [PATCH 01/15] mediatek: mt7981: improve fan behaviour MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This doubles the number of cooling-levels. In addition the fan is turned on with a low speed at lower temperatures and with a higher speed at higher temperatures. This also attempts to reduce the likelihood of constant start-stop actions. The change only affects the GL.iNet MT3000 and has been tested with it. Signed-off-by: Łukasz M (cherry picked from commit 5a603c7a316c3fb4bae4c7cb5c666232864126f2) --- .../arch/arm64/boot/dts/mediatek/mt7981.dtsi | 52 ++++++++++++------- 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi index 05d4b7d91d..cb161df81e 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi @@ -55,8 +55,8 @@ fan: pwm-fan { compatible = "pwm-fan"; - /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */ - cooling-levels = <0 128 192 255>; + /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */ + cooling-levels = <0 63 95 127 159 191 223 255>; #cooling-cells = <2>; status = "disabled"; }; @@ -67,55 +67,67 @@ polling-delay = <1000>; thermal-sensors = <&thermal 0>; trips { - cpu_trip_crit: crit { - temperature = <125000>; + cpu_trip_active_highest: active-highest { + temperature = <70000>; hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; + type = "active"; }; cpu_trip_active_high: active-high { - temperature = <115000>; + temperature = <60000>; hysteresis = <2000>; type = "active"; }; cpu_trip_active_med: active-med { - temperature = <85000>; + temperature = <50000>; hysteresis = <2000>; type = "active"; }; cpu_trip_active_low: active-low { - temperature = <60000>; + temperature = <45000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_lowest: active-lowest { + temperature = <40000>; hysteresis = <2000>; type = "active"; }; }; cooling-maps { + cpu-active-highest { + /* active: set fan to cooling level 7 */ + cooling-device = <&fan 7 7>; + trip = <&cpu_trip_active_highest>; + }; + cpu-active-high { - /* active: set fan to cooling level 3 */ - cooling-device = <&fan 3 3>; + /* active: set fan to cooling level 5 */ + cooling-device = <&fan 5 5>; trip = <&cpu_trip_active_high>; }; cpu-active-med { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 2 2>; + /* active: set fan to cooling level 3 */ + cooling-device = <&fan 3 3>; trip = <&cpu_trip_active_med>; }; cpu-active-low { - /* passive: set fan to cooling level 1 */ - cooling-device = <&fan 1 1>; + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; trip = <&cpu_trip_active_low>; }; + + cpu-active-lowest { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_lowest>; + }; }; }; }; From 04ec453970eab87b90725df959d7f3caa21de590 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sun, 27 Aug 2023 14:49:41 +0900 Subject: [PATCH 02/15] mediatek: update LED/Key bindings for Buffalo WSR-2533DHP2 Update LED and key nodes with newer DeviceTree bindings for WSR-2533DHP2. - LED - use led-[0-9] for node name of LEDs - add "color" and "function" properties - drop default-state = "on" from green:power LED - this LED will be turned on by led-running alias - key - drop unnecessary poll-interval property - use key-[0-9] for node name of keys Signed-off-by: INAGAKI Hiroshi (cherry picked from commit 6b8e7144c8863686a8ddef6f4fcebb3b8cf85f36) --- .../dts/mt7622-buffalo-wsr-2533dhp2.dts | 37 ++++++++++++------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts b/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts index 6d77be532b..fec559c8af 100644 --- a/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts +++ b/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts @@ -2,6 +2,7 @@ /dts-v1/; #include #include +#include #include "mt7622.dtsi" #include "mt6380.dtsi" @@ -29,43 +30,53 @@ leds { compatible = "gpio-leds"; - wireless_amber { + led-0 { label = "amber:wireless"; gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; }; - power_amber: power_amber { + power_amber: led-1 { label = "amber:power"; gpios = <&pio 3 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_POWER; }; - power_green: power_green { + power_green: led-2 { label = "green:power"; gpios = <&pio 4 GPIO_ACTIVE_LOW>; - default-state = "on"; + color = ; + function = LED_FUNCTION_POWER; }; - wireless_green { + led-3 { label = "green:wireless"; gpios = <&pio 15 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; }; - internet { + led-4 { label = "green:internet"; gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WAN; }; - router { + led-5 { label = "green:router"; gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; }; }; keys { compatible = "gpio-keys"; - poll-interval = <100>; - reset { + key-reset { label = "reset"; gpios = <&pio 0 GPIO_ACTIVE_LOW>; linux,code = ; @@ -74,14 +85,14 @@ /* GPIO 1 and 16 are a tri-state switch button with * ROUTER / AP / WB. */ - router { + key-router { label = "router"; gpios = <&pio 1 GPIO_ACTIVE_LOW>; linux,code = ; linux,input-type = ; }; - bridge { + key-bridge { label = "wb"; gpios = <&pio 16 GPIO_ACTIVE_LOW>; linux,code = ; @@ -89,14 +100,14 @@ }; /* GPIO 18 is a switch button with AUTO / MANUAL. */ - manual { + key-manual { label = "manual"; gpios = <&pio 18 GPIO_ACTIVE_LOW>; linux,code = ; linux,input-type = ; }; - wps { + key-wps { label = "wps"; gpios = <&pio 102 GPIO_ACTIVE_LOW>; linux,code = ; From 7e47913ef66fc01337f8b909c4b5811deee2cf85 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sun, 27 Aug 2023 15:10:53 +0900 Subject: [PATCH 03/15] mediatek: update NVMEM bindings for Buffalo WSR-2533DHP2 Update NVMEM-related nodes and use newer binding for MAC addresses on Buffalo WSR-2533DHP2. Signed-off-by: INAGAKI Hiroshi (cherry picked from commit de62e0165264fb2872e87116ddceb8c7e12c5a5a) --- .../dts/mt7622-buffalo-wsr-2533dhp2.dts | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts b/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts index fec559c8af..9a44152a91 100644 --- a/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts +++ b/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts @@ -229,9 +229,8 @@ phy-connection-type = "2500base-x"; - nvmem-cells = <&macaddr_factory_4>; + nvmem-cells = <&macaddr_factory_4 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; fixed-link { speed = <2500>; @@ -284,9 +283,22 @@ }; factory: partition@1c0000 { + compatible = "nvmem-cells"; label = "factory"; reg = <0x1c0000 0x40000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + }; }; partition@200000 { @@ -349,13 +361,3 @@ &rtc { status = "disabled"; }; - -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_4: macaddr@4 { - reg = <0x4 0x6>; - }; -}; From 9c793c44c98d37f210072d4c60cb3255160e8c95 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sun, 27 Aug 2023 18:04:04 +0900 Subject: [PATCH 04/15] mediatek: add label-mac-device for Buffalo WSR-2533DHP2 Add label-mac-device with "&gmac0" phandle for Buffalo WSR-2533DHP2. Signed-off-by: INAGAKI Hiroshi (cherry picked from commit 94606abf63c22dfda9b9a63c603339505ed5f5b4) --- target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts b/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts index 9a44152a91..f8990b25cf 100644 --- a/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts +++ b/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts @@ -17,6 +17,7 @@ led-failsafe = &power_amber; led-running = &power_green; led-upgrade = &power_green; + label-mac-device = &gmac0; }; chosen { From a26ea172946c407d8cefdccd34b738b9e12691c5 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sun, 27 Aug 2023 23:26:01 +0900 Subject: [PATCH 05/15] mediatek: drop pwm7_pins from Buffalo WSR-2533DHP2 MediaTek MT7622 doesn't support ch7 of PWM and pinctrl groups were dropped from driver source[0]. So pwm7-related groups are unavailable now, then, kernel shows a warning. [ 0.370264] mt7622-pinctrl 10211000.pinctrl: invalid group "pwm_ch7_2" for function "pwm" Drop that pinmux from pinctrl node. [0]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/pinctrl/mediatek/pinctrl-mt7622.c?id=57972641810a97566ffd13e4be3f6a66d61eb3b5 Signed-off-by: INAGAKI Hiroshi (cherry picked from commit 4d9113017b2d401e821fb008518cdd660dafb8a3) --- .../linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts b/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts index f8990b25cf..8b0dc1aa98 100644 --- a/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts +++ b/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts @@ -193,13 +193,6 @@ }; }; - pwm7_pins: pwm1-2-pins { - mux { - function = "pwm"; - groups = "pwm_ch7_2"; - }; - }; - uart0_pins: uart0-pins { mux { function = "uart"; @@ -330,8 +323,6 @@ }; &pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pins>; status = "okay"; }; From 882d20e25b574024442284c433d26f33cbac76f9 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sun, 27 Aug 2023 17:29:12 +0900 Subject: [PATCH 06/15] mediatek: merge trx helpers in image/mt7622.mk Merge similar helpers of trx image generation, "buffalo-kernel-trx" and "trx-nand". Signed-off-by: INAGAKI Hiroshi (cherry picked from commit d0929006f2290307f6b9ba37d221f44a145d8d1b) --- target/linux/mediatek/image/mt7622.mk | 42 ++++++++++++--------------- 1 file changed, 18 insertions(+), 24 deletions(-) diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk index 8f29843f3c..2a5e60989f 100644 --- a/target/linux/mediatek/image/mt7622.mk +++ b/target/linux/mediatek/image/mt7622.mk @@ -6,19 +6,24 @@ define Image/Prepare echo -ne '\xde\xad\xc0\xde' > $(KDIR)/ubi_mark endef -define Build/buffalo-kernel-trx +define Build/buffalo-trx $(eval magic=$(word 1,$(1))) - $(eval dummy=$(word 2,$(1))) + $(eval kern_bin=$(if $(1),$(IMAGE_KERNEL),$@)) + $(eval rtfs_bin=$(word 2,$(1))) + $(eval apnd_bin=$(word 3,$(1))) $(eval kern_size=$(if $(KERNEL_SIZE),$(KERNEL_SIZE),0x400000)) - $(if $(dummy),touch $(dummy)) + $(if $(rtfs_bin),touch $(rtfs_bin)) $(STAGING_DIR_HOST)/bin/otrx create $@.new \ $(if $(magic),-M $(magic),) \ - -f $@ \ - $(if $(dummy),\ + -f $(kern_bin) \ + $(if $(rtfs_bin),\ -a 0x20000 \ -b $$(( $(subst k, * 1024,$(kern_size)) )) \ - -f $(dummy),) + -f $(rtfs_bin),) \ + $(if $(apnd_bin),\ + -A $(apnd_bin) \ + -a 0x20000) mv $@.new $@ endef @@ -51,19 +56,6 @@ define Build/mt7622-gpt rm $@.tmp endef -define Build/trx-nand - # kernel: always use 4 MiB (-28 B or TRX header) to allow upgrades even - # if it grows up between releases - # root: UBI with one extra block containing UBI mark to trigger erasing - # rest of partition - $(STAGING_DIR_HOST)/bin/otrx create $@.new \ - -M 0x32504844 \ - -f $(IMAGE_KERNEL) -a 0x20000 -b 0x400000 \ - -f $@ \ - -A $(KDIR)/ubi_mark -a 0x20000 - mv $@.new $@ -endef - define Device/bananapi_bpi-r64 DEVICE_VENDOR := Bananapi DEVICE_MODEL := BPi-R64 @@ -122,13 +114,15 @@ define Device/buffalo_wsr-2533dhp2 IMAGES += factory.bin factory-uboot.bin KERNEL_INITRAMFS := kernel-bin | lzma | \ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | \ - buffalo-kernel-trx - IMAGE/factory.bin := append-ubi | trx-nand | \ + buffalo-trx + IMAGE/factory.bin := append-ubi | \ + buffalo-trx 0x32504844 $$$$@ $(KDIR)/ubi_mark | \ buffalo-enc WSR-2533DHP2 $$(BUFFALO_TAG_VERSION) -l | \ buffalo-tag-dhp WSR-2533DHP2 JP JP | buffalo-enc-tag -l | buffalo-dhp-image - IMAGE/factory-uboot.bin := append-ubi | trx-nand - IMAGE/sysupgrade.bin := append-kernel | \ - buffalo-kernel-trx 0x32504844 $(KDIR)/tmp/$$(DEVICE_NAME).null | \ + IMAGE/factory-uboot.bin := append-ubi | \ + buffalo-trx 0x32504844 $$$$@ $(KDIR)/ubi_mark + IMAGE/sysupgrade.bin := \ + buffalo-trx 0x32504844 $(KDIR)/tmp/$$(DEVICE_NAME).null | \ sysupgrade-tar kernel=$$$$@ | append-metadata DEVICE_PACKAGES := kmod-mt7615-firmware swconfig endef From 65f9f3131e63908672456aa7f628466eb2367017 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sun, 27 Aug 2023 18:21:28 +0900 Subject: [PATCH 07/15] mediatek: separate dts/dtsi for Buffalo WSR series Separate dts/dtsi from the dts of Buffalo WSR-2533DHP2 to prepare adding suppport for WSR-3200AX4S. Signed-off-by: INAGAKI Hiroshi (cherry picked from commit 9f640cae75ec987f29bf697cee559a0a4ff497e0) --- .../dts/mt7622-buffalo-wsr-2533dhp2.dts | 230 +---------------- .../mediatek/dts/mt7622-buffalo-wsr.dtsi | 236 ++++++++++++++++++ 2 files changed, 240 insertions(+), 226 deletions(-) create mode 100644 target/linux/mediatek/dts/mt7622-buffalo-wsr.dtsi diff --git a/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts b/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts index 8b0dc1aa98..a9f2959191 100644 --- a/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts +++ b/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts @@ -1,120 +1,20 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include -#include -#include -#include "mt7622.dtsi" -#include "mt6380.dtsi" +#include "mt7622-buffalo-wsr.dtsi" / { model = "Buffalo WSR-2533DHP2"; compatible = "buffalo,wsr-2533dhp2", "mediatek,mt7622"; aliases { - serial0 = &uart0; - led-boot = &power_green; - led-failsafe = &power_amber; - led-running = &power_green; - led-upgrade = &power_green; label-mac-device = &gmac0; }; - chosen { - bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512"; - }; - memory { reg = <0 0x40000000 0 0x0F000000>; }; - leds { - compatible = "gpio-leds"; - - led-0 { - label = "amber:wireless"; - gpios = <&pio 2 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_WLAN; - }; - - power_amber: led-1 { - label = "amber:power"; - gpios = <&pio 3 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_POWER; - }; - - power_green: led-2 { - label = "green:power"; - gpios = <&pio 4 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_POWER; - }; - - led-3 { - label = "green:wireless"; - gpios = <&pio 15 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_WLAN; - }; - - led-4 { - label = "green:internet"; - gpios = <&pio 19 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_WAN; - }; - - led-5 { - label = "green:router"; - gpios = <&pio 20 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - }; - }; - - keys { - compatible = "gpio-keys"; - - key-reset { - label = "reset"; - gpios = <&pio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - /* GPIO 1 and 16 are a tri-state switch button with - * ROUTER / AP / WB. - */ - key-router { - label = "router"; - gpios = <&pio 1 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - - key-bridge { - label = "wb"; - gpios = <&pio 16 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - - /* GPIO 18 is a switch button with AUTO / MANUAL. */ - key-manual { - label = "manual"; - gpios = <&pio 18 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - - key-wps { - label = "wps"; - gpios = <&pio 102 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - rtkgsw: rtkgsw@0 { compatible = "mediatek,rtk-gsw"; mediatek,ethsys = <ðsys>; @@ -123,41 +23,7 @@ }; }; -&cpu0 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; -}; - -&cpu1 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - status = "okay"; -}; - -&slot0 { - status = "okay"; - - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - mediatek,mtd-eeprom = <&factory 0x5000>; - ieee80211-freq-limit = <5000000 6000000>; - }; -}; - &pio { - eth_pins: eth-pins { - mux { - function = "eth"; - groups = "mdc_mdio", "rgmii_via_gmac2"; - }; - }; - /* Parallel nand is shared pin with eMMC */ parallel_nand_pins: parallel-nand-pins { mux { @@ -176,67 +42,11 @@ bias-pull-up; }; }; - - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie0_pad_perst", - "pcie0_1_waken", - "pcie0_1_clkreq"; - }; - }; - - pmic_bus_pins: pmic-bus-pins { - mux { - function = "pmic"; - groups = "pmic_bus"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0_0_tx_rx" ; - }; - }; - - watchdog_pins: watchdog-pins { - mux { - function = "watchdog"; - groups = "watchdog"; - }; - }; }; -&bch { - status = "okay"; -}; - -ð { - pinctrl-names = "default"; - pinctrl-0 = <ð_pins>; - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - - phy-connection-type = "2500base-x"; - - nvmem-cells = <&macaddr_factory_4 (-1)>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - }; +&gmac0 { + nvmem-cells = <&macaddr_factory_4 (-1)>; + nvmem-cell-names = "mac-address"; }; &nandc { @@ -321,35 +131,3 @@ }; }; }; - -&pwm { - status = "okay"; -}; - -&pwrap { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_bus_pins>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&watchdog { - pinctrl-names = "default"; - pinctrl-0 = <&watchdog_pins>; - status = "okay"; -}; - -&wmac { - status = "okay"; - - mediatek,mtd-eeprom = <&factory 0x0>; -}; - -&rtc { - status = "disabled"; -}; diff --git a/target/linux/mediatek/dts/mt7622-buffalo-wsr.dtsi b/target/linux/mediatek/dts/mt7622-buffalo-wsr.dtsi new file mode 100644 index 0000000000..e77f83d354 --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-buffalo-wsr.dtsi @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include +#include + +#include "mt7622.dtsi" +#include "mt6380.dtsi" + +/ { + aliases { + serial0 = &uart0; + led-boot = &power_green; + led-failsafe = &power_amber; + led-running = &power_green; + led-upgrade = &power_green; + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "amber:wireless"; + gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; + }; + + power_amber: led-1 { + label = "amber:power"; + gpios = <&pio 3 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_POWER; + }; + + power_green: led-2 { + label = "green:power"; + gpios = <&pio 4 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_POWER; + }; + + led-3 { + label = "green:wireless"; + gpios = <&pio 15 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; + }; + + led-4 { + label = "green:internet"; + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WAN; + }; + + led-5 { + label = "green:router"; + gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + }; + + keys { + compatible = "gpio-keys"; + + key-reset { + label = "reset"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + /* GPIO 1 and 16 are a tri-state switch button with + * ROUTER / AP / WB. + */ + key-router { + label = "router"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + + key-bridge { + label = "wb"; + gpios = <&pio 16 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + + /* GPIO 18 is a switch button with AUTO / MANUAL. */ + key-manual { + label = "manual"; + gpios = <&pio 18 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + + key-wps { + label = "wps"; + gpios = <&pio 102 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&cpu0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; +}; + +&cpu1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&slot0 { + status = "okay"; + + wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x5000>; + ieee80211-freq-limit = <5000000 6000000>; + }; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio", "rgmii_via_gmac2"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pad_perst", + "pcie0_1_waken", + "pcie0_1_clkreq"; + }; + }; + + pmic_bus_pins: pmic-bus-pins { + mux { + function = "pmic"; + groups = "pmic_bus"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_0_tx_rx" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-connection-type = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&bch { + status = "okay"; +}; + +&pwm { + status = "okay"; +}; + +&pwrap { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; + +&wmac { + status = "okay"; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; + +&rtc { + status = "disabled"; +}; From 5b4df9a27e842e4f02c3591300ce92f7b494cec3 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sun, 27 Aug 2023 23:23:20 +0900 Subject: [PATCH 08/15] mediatek: add support for Buffalo WSR-3200AX4S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Buffalo WSR-3200AX4S is a 2.4/5 GHz band 11ax (Wi-Fi 6) router, based on MT7622B. Specification: - SoC : MediaTek MT7622B - RAM : DDR3 512 MiB - Flash : SPI-NAND 128 MiB (Winbond W25N01GVZEIG) - WLAN : 2.4/5 GHz 4T4R - 2.4 GHz : MediaTek MT7622B (SoC) - 5 GHz : MediaTek MT7915 - Ethernet : 5x 10/100/1000 Mbps - Switch : MediaTek MT7531 - LEDs/Keys : 6x/5x (2x: buttons, 3x: slide-switches) - UART : through-hole on PCB (J4) - assignment: 3.3V, GND, TX, RX from tri-angle marking - settings : 115200n8 - Power : 12 VDC, 1.5 A Flash instruction using factory.bin image: 1. Boot WSR-3200AX4S with "Router" mode 2. Access to "http://192.168.11.1/" and open firmware update page ("ファームウェア更新") 3. Select the OpenWrt factory.bin image and click update ("更新実行") button 4. Wait ~120 seconds to complete flashing Note: - This device has 2x OS images on flash. The first one will always be used for booting and the secondary is for backup. - This support generates multiple factory*.bin image: - factory.bin : for flashing from OEM WebUI - factory-uboot.bin: for flashing from U-Boot or clean installation via sysupgrade (don't use for normal sysupgrade) Known issues: - Wi-Fi MAC addresses won't be applied to each adapter. MAC Addresses: LAN : C4:3C:EA:xx:xx:60 (board_data, mac (text)) WAN : C4:3C:EA:xx:xx:60 (board_data, mac (text)) 2.4 GHz: C4:3C:EA:xx:xx:61 5 GHz : C4:3C:EA:xx:xx:68 Signed-off-by: INAGAKI Hiroshi (cherry picked from commit 7383eb266b64f374c7109ad1db5360bf91dc11c3) --- .../dts/mt7622-buffalo-wsr-3200ax4s.dts | 175 ++++++++++++++++++ target/linux/mediatek/image/mt7622.mk | 31 ++++ .../mt7622/base-files/etc/board.d/02_network | 6 + .../etc/hotplug.d/ieee80211/11_fix_wifi_mac | 5 + .../base-files/etc/uci-defaults/09_fix_crc | 4 + .../mt7622/base-files/lib/upgrade/platform.sh | 6 +- 6 files changed, 225 insertions(+), 2 deletions(-) create mode 100644 target/linux/mediatek/dts/mt7622-buffalo-wsr-3200ax4s.dts diff --git a/target/linux/mediatek/dts/mt7622-buffalo-wsr-3200ax4s.dts b/target/linux/mediatek/dts/mt7622-buffalo-wsr-3200ax4s.dts new file mode 100644 index 0000000000..678c31b711 --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-buffalo-wsr-3200ax4s.dts @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "mt7622-buffalo-wsr.dtsi" + +/ { + model = "Buffalo WSR-3200AX4S"; + compatible = "buffalo,wsr-3200ax4s", "mediatek,mt7622"; + + memory { + reg = <0 0x40000000 0 0x1f000000>; + }; +}; + +&pio { + /* Serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + + conf-cmd-dat { + pins = "SPI_WP", "SPI_HOLD", "SPI_MOSI", + "SPI_MISO", "SPI_CS"; + input-enable; + drive-strength = <16>; + bias-pull-up; + }; + + conf-clk { + pins = "SPI_CLK"; + drive-strength = <16>; + bias-pull-down; + }; + }; +}; + +&mdio { + switch@1f { + compatible = "mediatek,mt7531"; + reg = <0x1f>; + reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-connection-type = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; +}; + +&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <104000000>; + nand-ecc-engine = <&snfi>; + mediatek,bmt-v2; + mediatek,bmt-table-size = <0x1000>; + /* + * - Preloader - (kernel (6MiB, in firmware)) + * - Kernel2 - WTB + */ + mediatek,bmt-remap-range = <0x0 0x8c0000>, + <0x1ac0000 0x5200000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Preloader"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "ATF"; + reg = <0x80000 0x40000>; + read-only; + }; + + partition@c0000 { + label = "u-boot"; + reg = <0xc0000 0x80000>; + read-only; + }; + + partition@140000 { + label = "u-boot-env"; + reg = <0x140000 0x80000>; + read-only; + }; + + factory: partition@1c0000 { + label = "factory"; + reg = <0x1c0000 0x100000>; + read-only; + }; + + partition@2c0000 { + compatible = "brcm,trx"; + brcm,trx-magic = <0x33504844>; + label = "firmware"; + reg = <0x2c0000 0x1800000>; + }; + + partition@1ac0000 { + label = "Kernel2"; + reg = <0x1ac0000 0x1800000>; + }; + + partition@32c0000 { + label = "glbcfg"; + reg = <0x32c0000 0x200000>; + read-only; + }; + + partition@34c0000 { + label = "board_data"; + reg = <0x34c0000 0x200000>; + read-only; + }; + + partition@36c0000 { + label = "WTB"; + reg = <0x36c0000 0x3600000>; + read-only; + }; + }; + }; +}; diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk index 2a5e60989f..50166669e2 100644 --- a/target/linux/mediatek/image/mt7622.mk +++ b/target/linux/mediatek/image/mt7622.mk @@ -128,6 +128,37 @@ define Device/buffalo_wsr-2533dhp2 endef TARGET_DEVICES += buffalo_wsr-2533dhp2 +define Device/buffalo_wsr-3200ax4s + DEVICE_VENDOR := Buffalo + DEVICE_MODEL := WSR-3200AX4S + DEVICE_DTS := mt7622-buffalo-wsr-3200ax4s + IMAGE_SIZE := 24576k + BUFFALO_TRX_MAGIC := 0x33504844 + DEVICE_PACKAGES := kmod-mt7915-firmware + DEVICE_DTS_DIR := ../dts + KERNEL_SIZE := 6144k + BLOCKSIZE := 128k + PAGESIZE := 2048 + UBINIZE_OPTS := -E 5 + BUFFALO_TAG_PLATFORM := MTK + BUFFALO_TAG_VERSION := 9.99 + BUFFALO_TAG_MINOR := 9.99 + IMAGES += factory.bin factory-uboot.bin + KERNEL_INITRAMFS = kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | \ + buffalo-trx + IMAGE/factory.bin = append-ubi | \ + buffalo-trx $$$$(BUFFALO_TRX_MAGIC) $$$$@ $(KDIR)/ubi_mark | \ + buffalo-enc $$(DEVICE_MODEL) $$(BUFFALO_TAG_VERSION) -l | \ + buffalo-tag-dhp $$(DEVICE_MODEL) JP JP | buffalo-enc-tag -l | buffalo-dhp-image + IMAGE/factory-uboot.bin := append-ubi | \ + buffalo-trx $$$$(BUFFALO_TRX_MAGIC) $$$$@ $(KDIR)/ubi_mark + IMAGE/sysupgrade.bin := \ + buffalo-trx $$$$(BUFFALO_TRX_MAGIC) $(KDIR)/tmp/$$(DEVICE_NAME).null | \ + sysupgrade-tar kernel=$$$$@ | append-metadata +endef +TARGET_DEVICES += buffalo_wsr-3200ax4s + define Device/elecom_wrc-2533gent DEVICE_VENDOR := Elecom DEVICE_MODEL := WRC-2533GENT diff --git a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network index 38db921f5c..d1341099bc 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network @@ -9,6 +9,7 @@ mediatek_setup_interfaces() case $board in bananapi,bpi-r64|\ + buffalo,wsr-3200ax4s|\ elecom,wrc-x3200gst3|\ linksys,e8450|\ linksys,e8450-ubi|\ @@ -55,6 +56,11 @@ mediatek_setup_macs() local label_mac="" case $board in + buffalo,wsr-3200ax4s) + lan_mac=$(mtd_get_mac_ascii board_data "mac") + wan_mac=$lan_mac + label_mac=$lan_mac + ;; reyee,ax3200-e5|\ ruijie,rg-ew3200gx-pro) lan_mac=$(macaddr_add $(get_mac_label) 1) diff --git a/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index f8639e9f40..7ee9f24071 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -13,6 +13,11 @@ case "$board" in bananapi,bpi-r64) [ "$PHYNBR" = "0" ] && macaddr_add $(cat /sys/class/net/eth0/address) 2 > /sys${DEVPATH}/macaddress ;; + buffalo,wsr-3200ax4s) + basemac=$(mtd_get_mac_ascii board_data "mac") + [ "$PHYNBR" = "0" ] && macaddr_add $basemac 1 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $basemac 8 > /sys${DEVPATH}/macaddress + ;; reyee,ax3200-e5|\ ruijie,rg-ew3200gx-pro) [ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress diff --git a/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/09_fix_crc b/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/09_fix_crc index 81cb6b18b7..59b00a6e69 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/09_fix_crc +++ b/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/09_fix_crc @@ -7,4 +7,8 @@ buffalo,wsr-2533dhp2) mtd -M 0x44485032 ${kernel_size:+-c 0x$kernel_size} fixtrx firmware && exit 0 exit 1 ;; +buffalo,wsr-3200ax4s) + mtd -M 0x44485033 ${kernel_size:+-c 0x$kernel_size} fixtrx firmware && exit 0 + exit 1 + ;; esac diff --git a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh index b37b7b1c6e..ea3176d2d1 100755 --- a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh @@ -21,7 +21,8 @@ platform_do_upgrade() { ;; esac ;; - buffalo,wsr-2533dhp2) + buffalo,wsr-2533dhp2|\ + buffalo,wsr-3200ax4s) local magic="$(get_magic_long "$1")" # use "mtd write" if the magic is "DHP2 (0x44485032)" @@ -67,7 +68,8 @@ platform_check_image() { [ "$#" -gt 1 ] && return 1 case "$board" in - buffalo,wsr-2533dhp2) + buffalo,wsr-2533dhp2|\ + buffalo,wsr-3200ax4s) buffalo_check_image "$board" "$magic" "$1" || return 1 ;; elecom,wrc-x3200gst3|\ From f555fa6fd07bd9715d70a447eb92c75ade59e24b Mon Sep 17 00:00:00 2001 From: Roland Reinl Date: Thu, 20 Jul 2023 16:00:50 +0200 Subject: [PATCH 09/15] mediatek: Add support for D-Link EAGLE PRO AI M32 Specification: - MT7622BV SoC with 2.4GHz wifi - MT7975AN + MT7915AN for 5GHz - MT7531BE Switch - 512MB RAM - 128 MB flash - 3 LEDs (red, orange, white) - 2 buttons (WPS and Reset) MAC addresses: - WAN MAC is stored in partition "Odm" at offset 0x83 - LAN (as printed on the device) is WAN MAC + 1 - WLAN MAC (2.4 GHz) is WAN MAC + 2 - WLAN MAC (5GHz) is WAN MAC + 3 Disassembly: Remove 4 screws in the bottom and 2 screws in the top (after removing the blue cover on the top), then the board can be pulled out. The pins for the serial console are already labeled on the board (VCC, TX, RX, GND). Serial settings: 3.3V, 115200,8n1 Flashing via Recovery Web Interface: - Set your IP address to 192.168.0.10, subnetmask 255.255.255.25 - Press the reset button while powering on the deivce - Keep the reset button pressed until the status LED blinks fast - Open a Chromium based and goto http://192.168.0.1 - Download openwrt-mediatek-mt7622-dlink_eagle-pro-ai-m32-a1-squashfs-recovery.bin Flashing via uBoot: - Open the case, connect to the UART console - Set your IP address to 10.10.10.3, subnet mask 255.255.255.0. Connect to one of the LAN interfaces of the router - Run a tftp server which provides openwrt-mediatek-mt7622-dlink_eagle-pro-ai-m32-initramfs-kernel.bin. You can rename the file to iverson_uImage (no extension), then you don't have to enter the whole file name in uboot later. - Power on the device and select "1. System Load Linux to SDRAM via TFTP." in the boot menu - Enter image file, tftp server IP and device IP (if they differ from the default). - TFTP download to RAM will start. After a few seconds OpenWrt initramfs should start - The initramfs is accessible via 192.168.1.1, change your IP address accordingly (or use multiple IP addresses on your interface) - Create a backup of the Kernel1 partition, this file is required if a revert to stock should be done later - Perform a sysupgrade using openwrt-mediatek-mt7622-dlink_eagle-pro-ai-m32-squashfs-sysupgrade.bin - Reboot the device. OpenWrt should start from flash now Revert back to stock using the Recovery Web Interface: - Set your IP address to 192.168.0.10, subnetmask 255.255.255.25 - Press the reset button while powering on the deivce - Keep the reset button pressed until the status LED blinks fast - Open a Chromium based and goto http://192.168.0.1 - Flash a decrypted firmware image from D-Link. Decrypting an firmware image is described below. Decrypting a D-Link firmware image: - Download https://github.com/RolandoMagico/firmware-utils/blob/M32/src/m32-firmware-util.c - Compile a binary from the downloaded file, e.g. gcc m32-firmware-util.c -lcrypto -o m32-firmware-util - Run ./m32-firmware-util M32 --DecryptFactoryImage - Example for firmware 1.03.01_HOTFIX: ./m32-firmware-util M32 --DecryptFactoryImage M32-REVA_1.03.01_HOTFIX.enc.bin M32-REVA_1.03.01_HOTFIX.decrypted.bin Revert back to stock using uBoot: - Open the case, connect to the UART console - Set your IP address to 10.10.10.3, subnet mask 255.255.255.0. Connect to one of the LAN interfaces of the router - Run a tftp server which provides the previously created backup of the Kernel1 partition. You can rename the file to iverson_uImage (no extension), then you don't have to enter the whole file name in uboot later. - Power on the device and select "2. System Load Linux Kernel then write to Flash via TFTP." in the boot menu - Enter image file, tftp server IP and device IP (if they differ from the default). - TFTP download to FLASH will start. After a few seconds the stock firmware should start again There is also an image openwrt-mediatek-mt7622-dlink_eagle-pro-ai-m32-a1-squashfs-tftp.bin which can directly be flashed via U-Boot and TFTP. It can be used if no backup of the Kernel1 partition is reuqired. Flahsing via OEM web interface is currently not possible, the OEM images are encrypted and require a specific memory layout which is not compatible to the partition layout of OpenWrt. Signed-off-by: Roland Reinl (cherry picked from commit e3a6945b58daf0cda1db1b356bed304404cb77f5) --- .../dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts | 399 ++++++++++++++++++ target/linux/mediatek/image/mt7622.mk | 38 ++ .../mt7622/base-files/etc/board.d/02_network | 7 + .../etc/hotplug.d/ieee80211/11_fix_wifi_mac | 4 + .../mt7622/base-files/lib/upgrade/platform.sh | 2 + 5 files changed, 450 insertions(+) create mode 100644 target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts diff --git a/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts new file mode 100644 index 0000000000..ca680e4c29 --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7622.dtsi" +#include "mt6380.dtsi" +#include +#include + +/ { + model = "D-Link EAGLE PRO AI M32 A1"; + compatible = "dlink,eagle-pro-ai-m32-a1", "mediatek,mt7622"; + + aliases { + led-boot = &status_orange; + led-failsafe = &status_red; + led-running = &status_white; + led-upgrade = &status_red; + serial0 = &uart0; + label-mac-device = &gmac0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512"; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + + cpu@1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = ; + }; + + wps { + gpios = <&pio 102 GPIO_ACTIVE_LOW>; + label = "wps"; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + status_white: status_white { + label = "white:status"; + gpios = <&pio 85 GPIO_ACTIVE_LOW>; + }; + + status_orange: status_orange { + label = "orange:status"; + gpios = <&pio 20 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + status_red: status_red { + label = "red:status"; + gpios = <&pio 17 GPIO_ACTIVE_LOW>; + }; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&bch { + status = "okay"; +}; + +&btif { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + nvmem-cells = <&macaddr_odm_83>; + nvmem-cell-names = "mac-address"; + phy-mode = "2500base-x"; + reg = <0>; + + fixed-link { + full-duplex; + pause; + speed = <2500>; + }; + }; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 54 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + wan: port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&pio { + epa_elna_pins: epa-elna-pins { + mux { + function = "antsel"; + groups = "antsel0", "antsel1", "antsel2", "antsel3", + "antsel4", "antsel5", "antsel6", "antsel7", + "antsel8", "antsel9", "antsel12", "antsel13", + "antsel14", "antsel15", "antsel16", "antsel17"; + }; + }; + + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio", "rgmii_via_gmac2"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pad_perst", + "pcie0_1_waken", + "pcie0_1_clkreq"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie1_pad_perst", + "pcie1_0_waken", + "pcie1_0_clkreq"; + }; + }; + + pmic_bus_pins: pmic-bus-pins { + mux { + function = "pmic"; + groups = "pmic_bus"; + }; + }; + + /* Serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_0_tx_rx"; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&pwrap { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; + status = "okay"; +}; + +&rtc { + status = "disabled"; +}; + +&sata { + status = "disabled"; +}; + +&sata_phy { + status = "disabled"; +}; + +&slot0 { + wmac1: mt7915@0,0 { + reg = <0x0000 0 0 0 0>; + ieee80211-freq-limit = <5000000 6000000>; + mediatek,mtd-eeprom = <&factory 0x05000>; + }; +}; + +&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; + + snand: flash@0 { + compatible = "spi-nand"; + mediatek,bmt-table-size = <0x1000>; + mediatek,bmt-v2; + nand-ecc-engine = <&snfi>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Preloader"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + partition@80000 { + label = "ATF"; + reg = <0x00080000 0x00040000>; + read-only; + }; + + partition@C0000 { + label = "Bootloader"; + reg = <0x000C0000 0x00080000>; + read-only; + }; + + partition@140000 { + label = "BootConfig"; + reg = <0x00140000 0x00040000>; + read-only; + }; + + odm: partition@180000 { + compatible = "nvmem-cells"; + label = "Odm"; + reg = <0x00180000 0x00040000>; + read-only; + + macaddr_odm_83: macaddr@83 { + reg = <0x83 0x6>; + }; + }; + + config1: partition@1C0000 { + compatible = "nvmem-cells"; + label = "Config1"; + reg = <0x001C0000 0x00080000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + }; + + partition@240000 { + label = "Config2"; + reg = <0x00240000 0x00080000>; + read-only; + }; + + partition@2C0000 { + label = "Kernel1"; + reg = <0x002C0000 0x02D00000>; + + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00800000>; + }; + + partition@800000 { + label = "ubi"; + reg = <0x00800000 0x02500000>; + }; + }; + + partition@2FC0000 { + label = "Kernel2"; + reg = <0x02FC0000 0x02D00000>; + read-only; + }; + + factory: partition@5CC0000 { + label = "Factory"; + reg = <0x05CC0000 0x00100000>; + read-only; + }; + + partition@5DC0000 { + label = "Mydlink"; + reg = <0x05DC0000 0x00200000>; + read-only; + }; + + partition@5FC0000 { + label = "Storage"; + reg = <0x05FC0000 0x00300000>; + read-only; + }; + }; + }; +}; + +&ssusb { + status = "disabled"; +}; + +&u3phy { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; + +&wmac { + pinctrl-names = "default"; + pinctrl-0 = <&epa_elna_pins>; + mediatek,mtd-eeprom = <&factory 0x0000>; + status = "okay"; +}; + diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk index 50166669e2..294e23c855 100644 --- a/target/linux/mediatek/image/mt7622.mk +++ b/target/linux/mediatek/image/mt7622.mk @@ -35,6 +35,25 @@ define Build/bl31-uboot cat $(STAGING_DIR_IMAGE)/mt7622_$1-u-boot.fip >> $@ endef +# Append header to a D-Link M32 Kernel 1 partition +define Build/m32-recovery-header-kernel1 + echo -en "DLK6E6010001\x00\x00\xCF\x33" > "$@.header" + echo -en "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\x00\x8D\x57\x30\x0B" >> "$@.header" +# Byte 0-3: Erase Start 0x002C0000 +# Byte 4-7: Erase Length 0x02D00000 +# Byte 8-11: Data offset: 0x002C0000 +# Byte 12-15: Data Length: 0x02D00000 + echo -en "\x00\x00\x2C\x00\x00\x00\xD0\x02\x00\x00\x2C\x00\x00\x00\xD0\x02" >> "$@.header" +# Only zeros + echo -en "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" >> "$@.header" +# Note: The last 2 bytes of the following line are the checksum of the header +# If any data in the header will be changed, the checksum must be re-calculated + echo -en "\x42\x48\x02\x00\x00\x00\x08\x00\x00\x00\x00\x00\x60\x6E\x68\x61" >> "$@.header" + cat "$@.header" "$@" > "$@.new" + mv "$@.new" "$@" + rm "$@.header" +endef + define Build/mt7622-gpt cp $@ $@.tmp 2>/dev/null || true ptgen -g -o $@.tmp -a 1 -l 1024 \ @@ -159,6 +178,25 @@ define Device/buffalo_wsr-3200ax4s endef TARGET_DEVICES += buffalo_wsr-3200ax4s +define Device/dlink_eagle-pro-ai-m32-a1 + IMAGE_SIZE := 46080k + DEVICE_VENDOR := D-Link + DEVICE_MODEL := EAGLE PRO AI M32 + DEVICE_VARIANT := A1 + DEVICE_DTS := mt7622-dlink-eagle-pro-ai-m32-a1 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915-firmware + KERNEL_SIZE := 8192k + BLOCKSIZE := 128k + PAGESIZE := 2048 + UBINIZE_OPTS := -E 5 + IMAGES += tftp.bin recovery.bin + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + IMAGE/tftp.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | check-size + IMAGE/recovery.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | pad-to $$(IMAGE_SIZE) | m32-recovery-header-kernel1 +endef +TARGET_DEVICES += dlink_eagle-pro-ai-m32-a1 + define Device/elecom_wrc-2533gent DEVICE_VENDOR := Elecom DEVICE_MODEL := WRC-2533GENT diff --git a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network index d1341099bc..75c5e37be1 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network @@ -24,6 +24,9 @@ mediatek_setup_interfaces() ucidef_add_switch "switch0" \ "0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6@eth0" ;; + dlink,eagle-pro-ai-m32-a1) + ucidef_set_interfaces_lan_wan "lan1 lan2" wan + ;; ubnt,unifi-6-lr*) ucidef_set_interface_lan "eth0" ;; @@ -61,6 +64,10 @@ mediatek_setup_macs() wan_mac=$lan_mac label_mac=$lan_mac ;; + dlink,eagle-pro-ai-m32-a1) + wan_mac=$(get_mac_label) + lan_mac=$(macaddr_add $(get_mac_label) 1) + ;; reyee,ax3200-e5|\ ruijie,rg-ew3200gx-pro) lan_mac=$(macaddr_add $(get_mac_label) 1) diff --git a/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 7ee9f24071..e9cc592237 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -18,6 +18,10 @@ case "$board" in [ "$PHYNBR" = "0" ] && macaddr_add $basemac 1 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $basemac 8 > /sys${DEVPATH}/macaddress ;; + dlink,eagle-pro-ai-m32-a1) + [ "$PHYNBR" = "0" ] && macaddr_add $(cat /sys/class/net/eth0/address) 2 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $(cat /sys/class/net/eth0/address) 3 > /sys${DEVPATH}/macaddress + ;; reyee,ax3200-e5|\ ruijie,rg-ew3200gx-pro) [ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress diff --git a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh index ea3176d2d1..e256d2b533 100755 --- a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh @@ -34,6 +34,7 @@ platform_do_upgrade() { nand_do_upgrade "$1" fi ;; + dlink,eagle-pro-ai-m32-a1|\ elecom,wrc-x3200gst3|\ mediatek,mt7622-rfb1-ubi|\ netgear,wax206|\ @@ -72,6 +73,7 @@ platform_check_image() { buffalo,wsr-3200ax4s) buffalo_check_image "$board" "$magic" "$1" || return 1 ;; + dlink,eagle-pro-ai-m32-a1|\ elecom,wrc-x3200gst3|\ mediatek,mt7622-rfb1-ubi|\ netgear,wax206|\ From e2954a1e1b6825e9a8f8ad2a39b77a93292eb202 Mon Sep 17 00:00:00 2001 From: Roland Reinl Date: Sun, 1 Oct 2023 11:25:40 +0200 Subject: [PATCH 10/15] mediatek: Add support for TP-Link EAP225v5 Device specification: - MT7629 with 16MB NOR flash W25Q128 and 128 MB DDR3 RAM. - MT7761N and MT7762N wireless chips (currenlty no driver in OpenWrt available) - WiFi is NOT working on this device - Dual core but second CPU doesn't seem to work (Error message during boot: "CPU1: failed to come online") There are two similar merge requests for similar devices with the same issues: - https://github.com/openwrt/openwrt/pull/12286 - https://github.com/openwrt/openwrt/pull/5084 UART interface is next to the reset button, pinout: - 1: TX (the pin with the arrow marker) - 2: RX - 3: GND - 4: VCC UART settings: 115200,8n1, 3.3V U-Boot menu can be entered by pressing Ctrl+B during startup. Booting initramfs: - Set your computers IP adress to 192.168.1.110 - Run a TFTP server providing the initramfs image - Power on the AP, press Ctrl+B to get to the U-Boot menu - Select "1. System Load Linux to SDRAM via TFTP" - Update kernel file name, input server IP and input device IP (if they deviate from the defaults) - After booting, create a backup of all partitions, especially for kernel and root_fs. They are required for reverting back to stock firmware - The sysupgrade image can be flashed now MAC adresses: - LAN and 2.4GHz use the same MAC (the one printed on the device) - 5GHz WiFi MAC is LAN MAC + 1 GPIOs: - GPIO 21 is the reset pin (low active) - GPIO 55 is for the green LED (active high) - GPIO 56 is for the yellow/amber LED (active high) Signed-off-by: Roland Reinl (cherry picked from commit 44cd32d764fe1daed3b6d0595530df0c4d1c3464) --- .../mediatek/dts/mt7629-tplink_eap225-v5.dts | 188 ++++++++++++++++++ target/linux/mediatek/image/mt7629.mk | 9 + .../mt7629/base-files/etc/board.d/02_network | 3 +- 3 files changed, 199 insertions(+), 1 deletion(-) create mode 100644 target/linux/mediatek/dts/mt7629-tplink_eap225-v5.dts diff --git a/target/linux/mediatek/dts/mt7629-tplink_eap225-v5.dts b/target/linux/mediatek/dts/mt7629-tplink_eap225-v5.dts new file mode 100644 index 0000000000..52e22541fa --- /dev/null +++ b/target/linux/mediatek/dts/mt7629-tplink_eap225-v5.dts @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include +#include "mt7629.dtsi" + +/ { + model = "TP-Link EAP225 v5"; + compatible = "tplink,eap225-v5", "mediatek,mt7629"; + + aliases { + led-boot = &led_status_green; + led-failsafe = &led_status_amber; + led-running = &led_status_green; + led-upgrade = &led_status_amber; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-override = "console=ttyS0,115200n8"; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 21 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_green: status_green { + label = "green:status"; + gpios = <&pio 55 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_status_amber: status_amber { + label = "amber:status"; + gpios = <&pio 56 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + pinctrl-1 = <&ephy_leds_pins>; + status = "okay"; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&phy0>; + nvmem-cells = <&macaddr_factory_8>; + nvmem-cell-names = "mac-address"; + }; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&qspi { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Bootloader"; + reg = <0x0 0x00080000>; + read-only; + }; + + partition@80000 { + label = "Partition"; + reg = <0x00080000 0x00010000>; + read-only; + }; + + partition@90000 { + label = "Factory"; + reg = <0x00090000 0x00010000>; + compatible = "nvmem-cells"; + read-only; + + macaddr_factory_8: macaddr@8 { + reg = <0x8 0x6>; + }; + }; + + partition@A0000 { + label = "Radio"; + reg = <0x000A0000 0x00010000>; + read-only; + }; + + partition@B0000 { + label = "Extra"; + reg = <0x000B0000 0x00010000>; + read-only; + }; + + /* Vendor layout: kernel (0x000C0000 0x001A0000) - rootfs (0x00260000 0x00BE0000) */ + /* OpenWrt flash layout: combine kernel and rootfs from OEM layout */ + partition@C0000 { + label = "firmware"; + reg = <0x000C0000 0x00D80000>; + }; + + partition@E40000 { + label = "Config"; + reg = <0x00E40000 0x0001B0000>; + read-only; + }; + }; + }; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio"; + }; + }; + + ephy_leds_pins: ephy-leds-pins { + mux { + function = "led"; + groups = "ephy_leds"; + }; + }; + + qspi_pins: qspi-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_txd_rxd" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; diff --git a/target/linux/mediatek/image/mt7629.mk b/target/linux/mediatek/image/mt7629.mk index 33c557190f..9374228808 100644 --- a/target/linux/mediatek/image/mt7629.mk +++ b/target/linux/mediatek/image/mt7629.mk @@ -48,3 +48,12 @@ define Device/netgear_ex6250-v2 pad-rootfs | check-size | netgear-encrypted-factory endef TARGET_DEVICES += netgear_ex6250-v2 + +define Device/tplink_eap225-v5 + DEVICE_VENDOR := TP-Link + DEVICE_MODEL := EAP225 + DEVICE_VARIANT := v5 + DEVICE_DTS := mt7629-tplink_eap225-v5 + DEVICE_DTS_DIR := ../dts +endef +TARGET_DEVICES += tplink_eap225-v5 diff --git a/target/linux/mediatek/mt7629/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7629/base-files/etc/board.d/02_network index db931c8334..df042f8ad2 100644 --- a/target/linux/mediatek/mt7629/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/mt7629/base-files/etc/board.d/02_network @@ -16,7 +16,8 @@ mediatek_setup_interfaces() ucidef_add_switch "switch0" \ "0:lan" "1:lan" "2:lan" "3:lan" "6@eth0" ;; - netgear,ex6250-v2) + netgear,ex6250-v2|\ + tplink,eap225-v5) ucidef_set_interface_lan "eth0" ;; esac From 6bec68062b83b86ed65a96fe4a7e1ed30e5423b9 Mon Sep 17 00:00:00 2001 From: Valerio 'ftp21' Mancini Date: Wed, 4 Oct 2023 11:43:25 +0200 Subject: [PATCH 11/15] mediatek: add Zyxel EX5601-T0 with uboot custom partition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The flash procedure is similar to the Xiaomi AX6000 router. Load openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-initramfs-recovery.itb from original Zyxel U-Boot: tftpboot openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-initramfs-recovery.itb bootm 0x46000000 Load mtd-rw insmod /lib/modules/$(uname -r)/mtd-rw.ko i_want_a_brick=1 Format ubi and create ubootenv partitions ubidetach -p /dev/mtd5; ubiformat /dev/mtd5 -y; ubiattach -p /dev/mtd5 ubimkvol /dev/ubi0 -n 0 -N ubootenv -s 128KiB ubimkvol /dev/ubi0 -n 1 -N ubootenv2 -s 128KiB Copy openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-initramfs-recovery.itb to /tmp and create recovery partition. If your recovery image is larger than 10MiB, size the recovery partition accordingly to make it fit. ubimkvol /dev/ubi0 -n 2 -N recovery -s 10MiB ubiupdatevol /dev/ubi0_2 openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-initramfs-recovery.itb Copy preloader and uboot to /tmp and write them in the mtd mtd write /tmp/openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-preloader.bin bl2 mtd write /tmp/openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-bl31-uboot.fip fip Now write the firmware: sysupgrade -n /tmp/openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-squashfs-sysupgrade.itb To create a correct BL2, I had to add a profile for 'spim:4k+256' as I could not find a way to value the variable 'NAND_TYPE'. Features and fixes from hitech95 tree has been squashed, I'm attaching his commit message: The Power LED was not working correctly and not reacting to the boot process and statuses. The board has space (footprint) for an unpopulated Zigbee chip, while we dont know the device model having this chip populated we have to assure that the common dts doesnt enable interfaces that share pins with such device. In this instance the PCIe and the uart1 and uart2 are disabled. Some of the control PCIE pins seems to be used for the Zigbee chip, UART1 seems to be used as a flash port while UART2 should be the main comunication interface of Zigbee chip. The Zigbee chip should be a EFR32MG21. But the pins used for UART seems to be not on standard PINS used by other adapters. So it cannot run firmwares shared on the web. But it should be possible to build a custom firmware with the corrtect pinmux. This commit also contains the following squashed commit from hitech95 - mediatek: fix sysupgrade for Zyxel EX7601-T0 ubootmod Changes and fixes added in common board: - added aliases for boot status leds. - added aliases for the mac-label-device. - added pin claims for core features (MDIO and UART 0) - added default LEDs configuration (01_leds) - added default network configuration (02_network) - added missing kmod-usb3 module for USB3 - fixed LED names - fixed reset pin for SLIC chip - removed unused pinmux configurations and devices - fix LAN (switch) port numbering - using nvmem cells for wifi eeprom, dropping deprecated "mediatek,mtd-eeprom" - proper factory partition and mac address handling - cleaned up spi_nand sections and partition Changes and fixxes added in stock layout: - added NMBM, if u-boot has it, the kernel must be informed. Co-authored-by: Nicolò Veronese Co-developed-by: Nicolò Veronese Signed-off-by: Nicolò Veronese Signed-off-by: Valerio 'ftp21' Mancini (cherry picked from commit b5df398a36f153f036c0a5ff9b221abb0f6f240a) --- .../dts/mt7986a-zyxel-ex5601-t0-common.dtsi | 433 +++++++++++++ .../dts/mt7986a-zyxel-ex5601-t0-stock.dts | 598 +++--------------- .../dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts | 106 ++++ .../filogic/base-files/etc/board.d/01_leds | 7 + .../filogic/base-files/etc/board.d/02_network | 4 + .../etc/hotplug.d/ieee80211/11_fix_wifi_mac | 3 +- .../base-files/lib/upgrade/platform.sh | 5 + target/linux/mediatek/image/filogic.mk | 34 +- 8 files changed, 666 insertions(+), 524 deletions(-) create mode 100644 target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-common.dtsi create mode 100644 target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts diff --git a/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-common.dtsi b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-common.dtsi new file mode 100644 index 0000000000..04e86a737d --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-common.dtsi @@ -0,0 +1,433 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +#include "mt7986a.dtsi" +#include +#include + +/ { + aliases { + serial0 = &uart0; + label-mac-device = &gmac0; + led-boot = &led_status_green; + led-failsafe = &led_status_red; + led-running = &led_status_green; + led-upgrade = &led_status_red; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + poll-interval = <20>; + + reset-button { + label = "reset"; + gpios = <&pio 21 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wlan-button { + label = "wlan"; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + wps-button { + label = "wps"; + gpios = <&pio 56 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_green_wifi24g { + label = "green:wifi24g"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_green_wifi5g { + label = "green:wifi5g"; + gpios = <&pio 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_green_inet { + label = "green:inet"; + gpios = <&pio 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_red_inet { + label = "red:inet"; + gpios = <&pio 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_status_green: led_green_pwr { + label = "green:pwr"; + gpios = <&pio 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; /* Default blinking */ + led-pattern = <125 125>; /* Fast blink is 4 HZ */ + }; + + led_status_red: led_red_pwr { + label = "red:pwr"; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_green_fxs { + label = "green:fxs"; + gpios = <&pio 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_amber_fxs { + label = "amber:fxs"; + gpios = <&pio 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_amber_wps24g { + label = "amber:wps24g"; + gpios = <&pio 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_amber_wps5g { + label = "amber:wps5g"; + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_green_lan { + label = "green:lan"; + gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_green_sfp { + label = "green:sfp"; + gpios = <&pio 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + spi_nand: spi_nand@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <10000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + nand_partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + phy = <&phy6>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <1500000>; + reset-post-delay-us = <1000000>; + + phy5: phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <5>; + mxl,led-config = <0x03f0 0x0 0x0 0x0>; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <6>; + mxl,led-config = <0x00f0 0x0 0x0 0x0>; + }; + + switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + label = "lan1"; + phy-mode = "2500base-x"; + phy = <&phy5>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; + +&crypto { + status = "okay"; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "switch_int", "mdc_mdio"; + }; + }; + + spic_pins_g2: spic-pins-29-to-32 { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf_dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + usb-oc-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + input; + line-name = "usb-oc"; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins_g2>; + status = "okay"; + + proslic_spi: proslic_spi@0 { + compatible = "silabs,proslic_spi"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-cpha = <1>; + spi-cpol = <1>; + channel_count = <1>; + debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ + reset_gpio = <&pio 25 GPIO_ACTIVE_HIGH>; + ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ + }; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; + + /* EFR32MG21 Zigbee (BOOT)*/ +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; + + /* EFR32MG21 Zigbee */ +}; + +&usb_phy { + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-stock.dts b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-stock.dts index 331150d85d..987510d486 100644 --- a/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-stock.dts +++ b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-stock.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "mt7986a.dtsi" +#include "mt7986a-zyxel-ex5601-t0-common.dtsi" #include #include @@ -13,540 +14,64 @@ model = "Zyxel EX5601-T0"; compatible = "zyxel,ex5601-t0", "mediatek,mt7986a-rfb-snand"; - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - poll-interval = <20>; - - reset-button { - label = "reset"; - gpios = <&pio 21 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wlan-button { - label = "wlan"; - gpios = <&pio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps-button { - label = "wps"; - gpios = <&pio 56 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - zyleds { - compatible = "gpio-leds"; - - led_green_wifi24g { - label = "zyled-green-wifi24g"; - gpios = <&pio 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_green_wifi5g { - label = "zyled-green-wifi5g"; - gpios = <&pio 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_green_inet { - label = "zyled-green-inet"; - gpios = <&pio 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_red_inet { - label = "zyled-red-inet"; - gpios = <&pio 15 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_green_pwr { - label = "zyled-green-pwr"; - gpios = <&pio 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; /* Default blinking */ - led-pattern = <125 125>; /* Fast blink is 4 HZ */ - }; - - led_red_pwr { - label = "zyled-red-pwr"; - gpios = <&pio 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_green_fxs { - label = "zyled-green-fxs"; - gpios = <&pio 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led_amber_fxs { - label = "zyled-amber-fxs"; - gpios = <&pio 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led_amber_wps24g { - label = "zyled-amber-wps24g"; - gpios = <&pio 18 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led_amber_wps5g { - label = "zyled-amber-wps5g"; - gpios = <&pio 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led_green_lan { - label = "zyled-green-lan"; - gpios = <&pio 20 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led_green_sfp { - label = "zyled-green-sfp"; - gpios = <&pio 24 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - }; - -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - nvmem-cells = <&macaddr_factory_002a>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; - phy = <&phy6>; - - nvmem-cells = <&macaddr_factory_0024>; - nvmem-cell-names = "mac-address"; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; - reset-delay-us = <1500000>; - reset-post-delay-us = <1000000>; - - phy5: phy@5 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <5>; - }; - - phy6: phy@6 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <6>; - }; - - switch@1f { - compatible = "mediatek,mt7531"; - reg = <31>; - reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@5 { - reg = <5>; - label = "lan4"; - phy-mode = "2500base-x"; - phy = <&phy5>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; - }; + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; }; }; -&watchdog { - status = "okay"; +&spi_nand { + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; }; -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; - mediatek,mtd-eeprom = <&factory 0x0>; - nvmem-cells = <&macaddr_factory_0004>; - nvmem-cell-names = "mac-address"; -}; +&nand_partitions { -&crypto { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x14014>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; - no-sd; - no-sdio; - status = "disabled"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pio { - mmc0_pins_default: mmc0-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; }; - mmc0_pins_uhs: mmc0-uhs-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; }; - pcie_pins: pcie-pins { - mux { - function = "pcie"; - groups = "pcie_clk", "pcie_wake", "pcie_pereset"; - }; + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + read-only; }; - spic_pins_g2: spic-pins-29-to-32 { - mux { - function = "spi"; - groups = "spi1_2"; - }; + partition@380000 { + label = "FIP"; + reg = <0x380000 0x01C0000>; + read-only; }; - spi_flash_pins: spi-flash-pins-33-to-38 { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - conf-pu { - pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - conf-pd { - pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; - drive-strength = <8>; - mediatek,pull-down-adv = <0>; /* bias-disable */ - }; + partition@540000 { + label = "zloader"; + reg = <0x540000 0x0040000>; + read-only; }; - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1"; - }; + partition@580000 { + label = "ubi"; + reg = <0x580000 0x4000000>; }; - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2"; - }; + partition@4580000 { + label = "ubi2"; + reg = <0x4580000 0x4000000>; + read-only; }; - wf_2g_5g_pins: wf_2g_5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; + partition@8580000 { + label = "zyubi"; + reg = <0x8580000 0x15A80000>; }; - - wf_dbdc_pins: wf_dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_flash_pins>; - cs-gpios = <0>, <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - spi_nand: spi_nand@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <10000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x0200000>; - read-only; - }; - - partition@380000 { - label = "FIP"; - reg = <0x380000 0x01C0000>; - read-only; - }; - - partition@540000 { - label = "zloader"; - reg = <0x540000 0x0040000>; - read-only; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x4000000>; - }; - - partition@4580000 { - label = "ubi2"; - reg = <0x4580000 0x4000000>; - read-only; - }; - - partition@8580000 { - label = "zyubi"; - reg = <0x8580000 0x15A80000>; - }; - }; - }; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spic_pins_g2>; - status = "okay"; - - proslic_spi: proslic_spi@0 { - compatible = "silabs,proslic_spi"; - reg = <0>; - spi-max-frequency = <10000000>; - spi-cpha = <1>; - spi-cpol = <1>; - channel_count = <1>; - debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ - reset_gpio = <&pio 7 GPIO_ACTIVE_HIGH>; - ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ - }; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&trng { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&usb_phy { - status = "okay"; }; &factory { @@ -554,15 +79,46 @@ #address-cells = <1>; #size-cells = <1>; - macaddr_factory_0004: macaddr@0004 { - reg = <0x0004 0x6>; - }; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; - macaddr_factory_0024: macaddr@0024 { - reg = <0x0024 0x6>; - }; + eeprom_factory: eeprom@0 { + #size-cells = <1>; + reg = <0x0 0x1000>; + }; - macaddr_factory_002a: macaddr@002a { - reg = <0x002a 0x6>; + macaddr_factory_0004: macaddr@0004 { + compatible = "mac-base"; + reg = <0x0004 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_0024: macaddr@0024 { + compatible = "mac-base"; + reg = <0x0024 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_002a: macaddr@002a { + compatible = "mac-base"; + reg = <0x002a 0x6>; + #nvmem-cell-cells = <1>; + }; }; }; + +&gmac0 { + nvmem-cells = <&macaddr_factory_002a 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + nvmem-cells = <&macaddr_factory_0024 0>; + nvmem-cell-names = "mac-address"; +}; + +&wifi { + nvmem-cells = <&eeprom_factory>; + nvmem-cell-names = "eeprom"; +}; diff --git a/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts new file mode 100644 index 0000000000..a300e2052d --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7986a.dtsi" +#include "mt7986a-zyxel-ex5601-t0-common.dtsi" +#include +#include + +/ { + model = "Zyxel EX5601-T0 ubootmod"; + compatible = "zyxel,ex5601-t0-ubootmod", "mediatek,mt7986a"; + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; +}; + +&nand_partitions { + partition@0 { + label = "bl2"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + read-only; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + read-only; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x0200000>; + read-only; + }; + + partition@540000 { + label = "zloader"; + reg = <0x540000 0x0040000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x1da80000>; + }; +}; + +&factory { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + + eeprom_factory: eeprom@0 { + #size-cells = <1>; + reg = <0x0 0x1000>; + }; + + macaddr_factory_0004: macaddr@0004 { + compatible = "mac-base"; + reg = <0x0004 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_0024: macaddr@0024 { + compatible = "mac-base"; + reg = <0x0024 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_002a: macaddr@002a { + compatible = "mac-base"; + reg = <0x002a 0x6>; + #nvmem-cell-cells = <1>; + }; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_002a 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + nvmem-cells = <&macaddr_factory_0024 0>; + nvmem-cell-names = "mac-address"; +}; + +&wifi { + nvmem-cells = <&eeprom_factory>; + nvmem-cell-names = "eeprom"; +}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds index cdeaa6c5c5..75c8fcda9b 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds @@ -42,6 +42,13 @@ xiaomi,redmi-router-ax6000-stock|\ xiaomi,redmi-router-ax6000-ubootmod) ucidef_set_led_netdev "wan" "wan" "rgb:network" "wan" ;; +zyxel_ex5601-t0-stock|\ +zyxel,ex5601-t0-ubootmod) + ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" "link tx rx" + ucidef_set_led_netdev "wan" "WAN" "green:inet" "eth1" "link tx rx" + ucidef_set_led_netdev "wifi-24g" "WIFI-2.4G" "green:wifi24g" "phy0-ap0" "link tx rx" + ucidef_set_led_netdev "wifi-5g" "WIFI-5G" "green:wifi5g" "phy1-ap0" "link tx rx" + ;; esac board_config_flush diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 2e978be680..a48fbbc79c 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -73,6 +73,10 @@ mediatek_setup_interfaces() xiaomi,redmi-router-ax6000-ubootmod) ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" wan ;; + zyxel,ex5601-t0-stock|\ + zyxel,ex5601-t0-ubootmod) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1 + ;; *) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" wan ;; diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index f8ebc1da42..e6378dd498 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -107,7 +107,8 @@ case "$board" in ;; routerich,ax3000|\ zbtlink,zbt-z8102ax|\ - zyxel,ex5601-t0) + zyxel,ex5601-t0|\ + zyxel,ex5601-t0-ubootmod) addr=$(mtd_get_mac_binary "Factory" 0x4) [ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress ;; diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index e3b042c876..9b3ebe92f1 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -142,6 +142,11 @@ platform_do_upgrade() { CI_ROOT_UBIPART=ubi nand_do_upgrade "$1" ;; + zyxel,ex5601-t0-ubootmod) + CI_KERNPART="fit" + CI_ROOTPART="ubi_rootfs" + nand_do_upgrade "$1" + ;; *) nand_do_upgrade "$1" ;; diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 194319a228..7daac6a1fa 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -801,10 +801,11 @@ TARGET_DEVICES += zbtlink_zbt-z8102ax define Device/zyxel_ex5601-t0-stock DEVICE_VENDOR := Zyxel - DEVICE_MODEL := EX5601-T0 (stock layout) + DEVICE_MODEL := EX5601-T0 + DEVICE_VARIANT := (stock layout) DEVICE_DTS := mt7986a-zyxel-ex5601-t0-stock DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware + DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware kmod-usb3 SUPPORTED_DEVICES := mediatek,mt7986a-rfb-snand UBINIZE_OPTS := -E 5 BLOCKSIZE := 256k @@ -821,6 +822,35 @@ define Device/zyxel_ex5601-t0-stock endef TARGET_DEVICES += zyxel_ex5601-t0-stock +define Device/zyxel_ex5601-t0-ubootmod + DEVICE_VENDOR := Zyxel + DEVICE_MODEL := EX5601-T0 + DEVICE_VARIANT := (OpenWrt U-Boot layout) + DEVICE_DTS := mt7986a-zyxel-ex5601-t0-ubootmod + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware kmod-usb3 + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + IMAGES := sysupgrade.itb + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 256k + PAGESIZE := 4096 + KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + KERNEL := kernel-bin | lzma + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd + IMAGE/sysupgrade.itb := append-kernel | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-4k-ddr4 + ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot zyxel_ex5601-t0 +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS += initramfs-factory.ubi + ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-recovery.itb | ubinize-kernel +endif +endef +TARGET_DEVICES += zyxel_ex5601-t0-ubootmod + define Device/zyxel_ex5700-telenor DEVICE_VENDOR := ZyXEL DEVICE_MODEL := EX5700 (Telenor) From 9627654277ca307597028e0b8c2c449ab35bbd5e Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 4 Nov 2023 23:50:20 +0800 Subject: [PATCH 12/15] mediatek: Cetron CT3003: fixes typo for spi properties Same as commit 3674689, correct 'buswidth' to 'bus-width'. Also move the nmbm properties outside the partition definition. Signed-off-by: Chukun Pan (cherry picked from commit 1be6347b7d5cbbe944c9e5bab29aea4ec7de6349) --- target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts b/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts index ae4404466e..aea6f02da2 100644 --- a/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts +++ b/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts @@ -100,18 +100,18 @@ reg = <0>; spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - partition@0 { label = "BL2"; reg = <0x0000000 0x0100000>; From 37c2bc4397c1f7152ab9cb2f4235cb65a6d501bb Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 24 Jan 2024 05:01:43 +0000 Subject: [PATCH 13/15] mediatek: fixes for Ethernet on MT7988 SoC * fix switch ports with modes other than 1000M/Full * set 32-bit dma_coherent_mask to get PPE to work with 4 GiB of RAM * sync driver for built-in 1GE PHY with MediaTek SDK sources Signed-off-by: Daniel Golle (cherry picked from commit 4ae2f43b3a24e8a74963852f9d2fb8fee0872f31) --- ..._eth_soc-set-coherent-mask-to-get-PP.patch | 46 +++ ...-fix-10M-100M-speed-on-MT7988-switch.patch | 45 +++ ...-ge-soc-sync-driver-with-MediaTek-SD.patch | 270 ++++++++++++++++++ ...iatek-split-tx-and-rx-fields-in-mtk_.patch | 18 +- ...iatek-use-QDMA-instead-of-ADMAv2-on-.patch | 4 +- 5 files changed, 372 insertions(+), 11 deletions(-) create mode 100644 target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch create mode 100644 target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch create mode 100644 target/linux/mediatek/patches-5.15/734-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch diff --git a/target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch b/target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch new file mode 100644 index 0000000000..29dca26018 --- /dev/null +++ b/target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch @@ -0,0 +1,46 @@ +From dee3f591103910c8d8b2a6d57879ccd2a4be4b10 Mon Sep 17 00:00:00 2001 +Message-ID: +From: Daniel Golle +Date: Wed, 24 Jan 2024 03:19:49 +0000 +Subject: [PATCH net] net: ethernet: mtk_eth_soc: set coherent mask to get PPE + working +To: Felix Fietkau , + Sean Wang , + Mark Lee , + Lorenzo Bianconi , + David S. Miller , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Matthias Brugger , + AngeloGioacchino Del Regno , + Daniel Golle , + netdev@vger.kernel.org, + linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-mediatek@lists.infradead.org + +Set DMA coherent mask to 32-bit which makes PPE offloading engine start +working on BPi-R4 which got 4 GiB of RAM. + +Fixes: 2d75891ebc09 ("net: ethernet: mtk_eth_soc: support 36-bit DMA addressing on MT7988") +Suggested-by: Elad Yifee +Signed-off-by: Daniel Golle +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -4830,7 +4830,10 @@ static int mtk_probe(struct platform_dev + } + + if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { +- err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36)); ++ err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36)); ++ if (!err) ++ err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ + if (err) { + dev_err(&pdev->dev, "Wrong DMA config\n"); + return -EINVAL; diff --git a/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch b/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch new file mode 100644 index 0000000000..f2e91d3fe5 --- /dev/null +++ b/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch @@ -0,0 +1,45 @@ +From a444877c10a665cd8a869e6d37facdb89fd95f79 Mon Sep 17 00:00:00 2001 +Message-ID: +From: Daniel Golle +Date: Wed, 24 Jan 2024 04:17:11 +0000 +Subject: [PATCH net] net: dsa: mt7530: fix 10M/100M speed on MT7988 switch +To: Arınç ÜNAL , + Daniel Golle , + DENG Qingfang , + Sean Wang , + Andrew Lunn , + Florian Fainelli , + Vladimir Oltean , + David S. Miller , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Matthias Brugger , + AngeloGioacchino Del Regno , + netdev@vger.kernel.org, + linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-mediatek@lists.infradead.org + +Setup PMCR port register for actual speed and duplex on internally +connected PHYs of the MT7988 built-in switch. This fixes links with +speeds other than 1000M. + +Fixes: ("110c18bfed414 net: dsa: mt7530: introduce driver for MT7988 built-in switch") +Signed-off-by: Daniel Golle +--- + drivers/net/dsa/mt7530.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2832,8 +2832,7 @@ static void mt753x_phylink_mac_link_up(s + /* MT753x MAC works in 1G full duplex mode for all up-clocked + * variants. + */ +- if (interface == PHY_INTERFACE_MODE_INTERNAL || +- interface == PHY_INTERFACE_MODE_TRGMII || ++ if (interface == PHY_INTERFACE_MODE_TRGMII || + (phy_interface_mode_is_8023z(interface))) { + speed = SPEED_1000; + duplex = DUPLEX_FULL; diff --git a/target/linux/mediatek/patches-5.15/734-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch b/target/linux/mediatek/patches-5.15/734-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch new file mode 100644 index 0000000000..f983be4e44 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/734-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch @@ -0,0 +1,270 @@ +From f2195279c234c0f618946424b8236026126bc595 Mon Sep 17 00:00:00 2001 +Message-ID: +From: Daniel Golle +Date: Wed, 24 Jan 2024 02:27:04 +0000 +Subject: [PATCH net] net: phy: mediatek-ge-soc: sync driver with MediaTek SDK +To: Daniel Golle , + Qingfang Deng , + SkyLake Huang , + Andrew Lunn , + Heiner Kallweit , + Russell King , + David S. Miller , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Matthias Brugger , + AngeloGioacchino Del Regno , + netdev@vger.kernel.org, + linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-mediatek@lists.infradead.org + +Sync initialization and calibration routines with MediaTek's reference +driver. Improves compliance and resolves link stability issues with +CH340 IoT devices connected to MT798x built-in PHYs. + +Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs") +Signed-off-by: Daniel Golle +--- + drivers/net/phy/mediatek-ge-soc.c | 147 ++++++++++++++++-------------- + 1 file changed, 81 insertions(+), 66 deletions(-) + +--- a/drivers/net/phy/mediatek-ge-soc.c ++++ b/drivers/net/phy/mediatek-ge-soc.c +@@ -479,7 +479,7 @@ static int tx_r50_fill_result(struct phy + u16 reg, val; + + if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) +- bias = -2; ++ bias = -1; + + val = clamp_val(bias + tx_r50_cal_val, 0, 63); + +@@ -695,6 +695,11 @@ restore: + static void mt798x_phy_common_finetune(struct phy_device *phydev) + { + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ ++ __phy_write(phydev, 0x11, 0xc71); ++ __phy_write(phydev, 0x12, 0xc); ++ __phy_write(phydev, 0x10, 0x8fae); ++ + /* EnabRandUpdTrig = 1 */ + __phy_write(phydev, 0x11, 0x2f00); + __phy_write(phydev, 0x12, 0xe); +@@ -705,15 +710,56 @@ static void mt798x_phy_common_finetune(s + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x83aa); + +- /* TrFreeze = 0 */ ++ /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */ ++ __phy_write(phydev, 0x11, 0x240); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9680); ++ ++ /* TrFreeze = 0 (mt7988 default) */ + __phy_write(phydev, 0x11, 0x0); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x9686); + ++ /* SSTrKp100 = 5 */ ++ /* SSTrKf100 = 6 */ ++ /* SSTrKp1000Mas = 5 */ ++ /* SSTrKf1000Mas = 6 */ + /* SSTrKp1000Slv = 5 */ ++ /* SSTrKf1000Slv = 6 */ + __phy_write(phydev, 0x11, 0xbaef); + __phy_write(phydev, 0x12, 0x2e); + __phy_write(phydev, 0x10, 0x968c); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++} ++ ++static void mt7981_phy_finetune(struct phy_device *phydev) ++{ ++ u16 val[8] = { 0x01ce, 0x01c1, ++ 0x020f, 0x0202, ++ 0x03d0, 0x03c0, ++ 0x0013, 0x0005 }; ++ int i, k; ++ ++ /* 100M eye finetune: ++ * Keep middle level of TX MLT3 shapper as default. ++ * Only change TX MLT3 overshoot level here. ++ */ ++ for (k = 0, i = 1; i < 12; i++) { ++ if (i % 3 == 0) ++ continue; ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); ++ } ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* ResetSyncOffset = 6 */ ++ __phy_write(phydev, 0x11, 0x600); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8fc0); ++ ++ /* VgaDecRate = 1 */ ++ __phy_write(phydev, 0x11, 0x4c2a); ++ __phy_write(phydev, 0x12, 0x3e); ++ __phy_write(phydev, 0x10, 0x8fa4); + + /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, + * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 +@@ -728,7 +774,7 @@ static void mt798x_phy_common_finetune(s + __phy_write(phydev, 0x10, 0x8ec0); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + +- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ ++ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, + MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, + BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); +@@ -761,48 +807,6 @@ static void mt798x_phy_common_finetune(s + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); + } + +-static void mt7981_phy_finetune(struct phy_device *phydev) +-{ +- u16 val[8] = { 0x01ce, 0x01c1, +- 0x020f, 0x0202, +- 0x03d0, 0x03c0, +- 0x0013, 0x0005 }; +- int i, k; +- +- /* 100M eye finetune: +- * Keep middle level of TX MLT3 shapper as default. +- * Only change TX MLT3 overshoot level here. +- */ +- for (k = 0, i = 1; i < 12; i++) { +- if (i % 3 == 0) +- continue; +- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); +- } +- +- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ +- __phy_write(phydev, 0x11, 0xc71); +- __phy_write(phydev, 0x12, 0xc); +- __phy_write(phydev, 0x10, 0x8fae); +- +- /* ResetSyncOffset = 6 */ +- __phy_write(phydev, 0x11, 0x600); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x8fc0); +- +- /* VgaDecRate = 1 */ +- __phy_write(phydev, 0x11, 0x4c2a); +- __phy_write(phydev, 0x12, 0x3e); +- __phy_write(phydev, 0x10, 0x8fa4); +- +- /* FfeUpdGainForce = 4 */ +- __phy_write(phydev, 0x11, 0x240); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x9680); +- +- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); +-} +- + static void mt7988_phy_finetune(struct phy_device *phydev) + { + u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, +@@ -817,17 +821,7 @@ static void mt7988_phy_finetune(struct p + /* TCT finetune */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); + +- /* Disable TX power saving */ +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, +- MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); +- + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- +- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ +- __phy_write(phydev, 0x11, 0x671); +- __phy_write(phydev, 0x12, 0xc); +- __phy_write(phydev, 0x10, 0x8fae); +- + /* ResetSyncOffset = 5 */ + __phy_write(phydev, 0x11, 0x500); + __phy_write(phydev, 0x12, 0x0); +@@ -835,13 +829,27 @@ static void mt7988_phy_finetune(struct p + + /* VgaDecRate is 1 at default on mt7988 */ + +- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7, ++ * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7 ++ */ ++ __phy_write(phydev, 0x11, 0xb90a); ++ __phy_write(phydev, 0x12, 0x6f); ++ __phy_write(phydev, 0x10, 0x8f82); ++ ++ /* RemAckCntLimitCtrl = 1 */ ++ __phy_write(phydev, 0x11, 0xfbba); ++ __phy_write(phydev, 0x12, 0xc3); ++ __phy_write(phydev, 0x10, 0x87f8); + +- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); +- /* TxClkOffset = 2 */ +- __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, +- FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, ++ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, ++ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); ++ ++ /* rg_tr_lpf_cnt_val = 1023 */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); + } + + static void mt798x_phy_eee(struct phy_device *phydev) +@@ -874,11 +882,11 @@ static void mt798x_phy_eee(struct phy_de + MTK_PHY_LPI_SLV_SEND_TX_EN, + FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); + +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, +- MTK_PHY_LPI_SEND_LOC_TIMER_MASK | +- MTK_PHY_LPI_TXPCS_LOC_RCV, +- FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); ++ /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, ++ MTK_PHY_LPI_TXPCS_LOC_RCV); + ++ /* This also fixes some IoT issues, such as CH340 */ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, + MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, + FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | +@@ -912,7 +920,7 @@ static void mt798x_phy_eee(struct phy_de + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x9690); + +- /* REG_EEE_st2TrKf1000 = 3 */ ++ /* REG_EEE_st2TrKf1000 = 2 */ + __phy_write(phydev, 0x11, 0x114f); + __phy_write(phydev, 0x12, 0x2); + __phy_write(phydev, 0x10, 0x969a); +@@ -937,7 +945,7 @@ static void mt798x_phy_eee(struct phy_de + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x96b8); + +- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ ++ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ + __phy_write(phydev, 0x11, 0x1463); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x96ca); +@@ -1198,6 +1206,13 @@ static int mt7988_phy_probe(struct phy_d + + mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev)); + ++ /* Disable TX power saving at probing to: ++ * 1. Meet common mode compliance test criteria ++ * 2. Make sure that TX-VCM calibration works fine ++ */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, ++ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); ++ + return mt798x_phy_calibration(phydev); + } + diff --git a/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch b/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch index 7b78033ffb..af95dcf8d2 100644 --- a/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch +++ b/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch @@ -347,7 +347,7 @@ Signed-off-by: Lorenzo Bianconi mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); if (mtk_is_netsys_v3_or_greater(eth)) { -@@ -5163,11 +5163,15 @@ static const struct mtk_soc_data mt2701_ +@@ -5166,11 +5166,15 @@ static const struct mtk_soc_data mt2701_ .required_clks = MT7623_CLKS_BITMAP, .required_pctl = true, .version = 1, @@ -368,7 +368,7 @@ Signed-off-by: Lorenzo Bianconi .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5183,11 +5187,15 @@ static const struct mtk_soc_data mt7621_ +@@ -5186,11 +5190,15 @@ static const struct mtk_soc_data mt7621_ .offload_version = 1, .hash_offset = 2, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, @@ -389,7 +389,7 @@ Signed-off-by: Lorenzo Bianconi .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5205,11 +5213,15 @@ static const struct mtk_soc_data mt7622_ +@@ -5208,11 +5216,15 @@ static const struct mtk_soc_data mt7622_ .hash_offset = 2, .has_accounting = true, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, @@ -410,7 +410,7 @@ Signed-off-by: Lorenzo Bianconi .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5226,11 +5238,15 @@ static const struct mtk_soc_data mt7623_ +@@ -5229,11 +5241,15 @@ static const struct mtk_soc_data mt7623_ .hash_offset = 2, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, .disable_pll_modes = true, @@ -431,7 +431,7 @@ Signed-off-by: Lorenzo Bianconi .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5245,11 +5261,15 @@ static const struct mtk_soc_data mt7629_ +@@ -5248,11 +5264,15 @@ static const struct mtk_soc_data mt7629_ .required_pctl = false, .has_accounting = true, .version = 1, @@ -452,7 +452,7 @@ Signed-off-by: Lorenzo Bianconi .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5267,11 +5287,15 @@ static const struct mtk_soc_data mt7981_ +@@ -5270,11 +5290,15 @@ static const struct mtk_soc_data mt7981_ .hash_offset = 4, .has_accounting = true, .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, @@ -473,7 +473,7 @@ Signed-off-by: Lorenzo Bianconi .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_len_offset = 8, }, -@@ -5289,11 +5313,15 @@ static const struct mtk_soc_data mt7986_ +@@ -5292,11 +5316,15 @@ static const struct mtk_soc_data mt7986_ .hash_offset = 4, .has_accounting = true, .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, @@ -494,7 +494,7 @@ Signed-off-by: Lorenzo Bianconi .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_len_offset = 8, }, -@@ -5311,11 +5339,15 @@ static const struct mtk_soc_data mt7988_ +@@ -5314,11 +5342,15 @@ static const struct mtk_soc_data mt7988_ .hash_offset = 4, .has_accounting = true, .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, @@ -515,7 +515,7 @@ Signed-off-by: Lorenzo Bianconi .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_len_offset = 8, }, -@@ -5328,11 +5360,15 @@ static const struct mtk_soc_data rt5350_ +@@ -5331,11 +5363,15 @@ static const struct mtk_soc_data rt5350_ .required_clks = MT7628_CLKS_BITMAP, .required_pctl = false, .version = 1, diff --git a/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch b/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch index df8e988eb5..ea94bb5e05 100644 --- a/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch +++ b/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch @@ -89,7 +89,7 @@ Signed-off-by: Daniel Golle /* Set FE to PDMAv2 if necessary */ val = mtk_r32(eth, MTK_FE_GLO_MISC); mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); -@@ -5293,11 +5293,11 @@ static const struct mtk_soc_data mt7981_ +@@ -5296,11 +5296,11 @@ static const struct mtk_soc_data mt7981_ .dma_len_offset = 8, }, .rx = { @@ -105,7 +105,7 @@ Signed-off-by: Daniel Golle }, }; -@@ -5319,11 +5319,11 @@ static const struct mtk_soc_data mt7986_ +@@ -5322,11 +5322,11 @@ static const struct mtk_soc_data mt7986_ .dma_len_offset = 8, }, .rx = { From c8898f46f9d35b2b5a82a689a3d87f9afe517c50 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 3 Mar 2024 15:22:54 +0000 Subject: [PATCH 14/15] kernel: lantiq: ltq-vmmc: introduce user group for vmmc asterisk-chan-lantiq is by now the only user of the VMMC interface. And asterisk runs as user 'asterisk' which doesn't give it permission to open the /dev/vmmc* devices. Introduce a new user group 'vmmc' and give permission to access the /dev/vmmc* devices to that group. Another commit for asterisk-chan-lantiq will add the 'asterisk' user to that group. Signed-off-by: Daniel Golle (cherry picked from commit 37bbed6f95856a507d727ffc863b20f8a8b35332) --- package/kernel/lantiq/ltq-vmmc/Makefile | 1 + package/kernel/lantiq/ltq-vmmc/files/vmmc.init | 1 + 2 files changed, 2 insertions(+) diff --git a/package/kernel/lantiq/ltq-vmmc/Makefile b/package/kernel/lantiq/ltq-vmmc/Makefile index c96cee819b..4972f1c374 100644 --- a/package/kernel/lantiq/ltq-vmmc/Makefile +++ b/package/kernel/lantiq/ltq-vmmc/Makefile @@ -29,6 +29,7 @@ define KernelPackage/ltq-vmmc DEPENDS:=@(TARGET_lantiq_xway||TARGET_lantiq_xrx200) +kmod-ltq-tapi FILES:=$(PKG_BUILD_DIR)/src/drv_vmmc.ko AUTOLOAD:=$(call AutoProbe,drv_vmmc) + USERID:=:vmmc=386 endef define KernelPackage/ltq-vmmc/description diff --git a/package/kernel/lantiq/ltq-vmmc/files/vmmc.init b/package/kernel/lantiq/ltq-vmmc/files/vmmc.init index 402376e294..78efe80b98 100644 --- a/package/kernel/lantiq/ltq-vmmc/files/vmmc.init +++ b/package/kernel/lantiq/ltq-vmmc/files/vmmc.init @@ -8,6 +8,7 @@ start() { for i in 10 11 12 13 14 15 16 17 18; do if ! [ -e /dev/vmmc$i ]; then mknod -m 664 /dev/vmmc$i c 122 $i + chown root:vmmc /dev/vmmc$i fi done } From 81f8b93e3600953fc03d227c25e88919a6768b8c Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 2 Feb 2024 00:46:58 +0100 Subject: [PATCH 15/15] build: add $(STAGING_DIR) and $(BIN_DIR) preparation to target and package subdir compile dependencies In a pristine build, these directories are created as dependencies of the tools subdir compile, however this step never runs when the tools compile stamp already exists. Since commit ed6ba2801c0a ("tools: keep stamp file in $(STAGING_DIR_HOST)"), this will happen after `make clean`: $(STAGING_DIR) has been deleted, but the tools stamp still exists, so the next build will fail because $(STAGING_DIR) has not been set up correctly. Fix builds after `make clean` by adding the preparation as dependencies for the target and package directories as well. Fixes: ed6ba2801c0a ("tools: keep stamp file in $(STAGING_DIR_HOST)") Signed-off-by: Matthias Schiffer (cherry picked from commit fbb924abff8af9e69ec90d7bf099046c24145b74) --- package/Makefile | 2 ++ target/Makefile | 2 ++ 2 files changed, 4 insertions(+) diff --git a/package/Makefile b/package/Makefile index 8e72d4ec72..4663b41de4 100644 --- a/package/Makefile +++ b/package/Makefile @@ -117,6 +117,8 @@ endif $(curdir)/flags-install:= -j1 +$(curdir)//compile = $(STAGING_DIR)/.prepared $(BIN_DIR) + $(eval $(call stampfile,$(curdir),package,prereq,.config)) $(eval $(call stampfile,$(curdir),package,cleanup,$(TMP_DIR)/.build)) $(eval $(call stampfile,$(curdir),package,compile,$(TMP_DIR)/.build)) diff --git a/target/Makefile b/target/Makefile index 83f9c4b093..3bbb9f4131 100644 --- a/target/Makefile +++ b/target/Makefile @@ -19,6 +19,8 @@ $(curdir)/builddirs-install:=\ $(curdir)/sdk/install:=$(curdir)/linux/install $(curdir)/imagebuilder/install:=$(curdir)/linux/install +$(curdir)//compile = $(STAGING_DIR)/.prepared $(BIN_DIR) + $(eval $(call stampfile,$(curdir),target,prereq,.config)) $(eval $(call stampfile,$(curdir),target,compile,$(TMP_DIR)/.build)) $(eval $(call stampfile,$(curdir),target,install,$(TMP_DIR)/.build))