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rockchip: refresh rk3588 clk/iio patches

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2023-06-04 17:32:33 +08:00
parent e6f80fc618
commit 459ed9762c
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
10 changed files with 346 additions and 229 deletions
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54
target/linux/rockchip/patches-6.1/117-01-clk-composite-Fix-handling-of-high-clock-rates.patch Normal file
View File

@ -0,0 +1,54 @@
From 3ef7ead7ba37665e0b197f6ae5c2e1f4e043f334 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 18 May 2023 05:28:17 +0200
Subject: [PATCH] clk: composite: Fix handling of high clock rates
ULONG_MAX is used by a few drivers to figure out the highest available
clock rate via clk_round_rate(clk, ULONG_MAX). Since abs() takes a
signed value as input, the current logic effectively calculates with
ULONG_MAX = -1, which results in the worst parent clock being chosen
instead of the best one.
For example on Rockchip RK3588 the eMMC driver tries to figure out
the highest available clock rate. There are three parent clocks
available resulting in the following rate diffs with the existing
logic:
GPLL: abs(18446744073709551615 - 1188000000) = 1188000001
CPLL: abs(18446744073709551615 - 1500000000) = 1500000001
XIN24M: abs(18446744073709551615 - 24000000) = 24000001
As a result the clock framework will promote a maximum supported
clock rate of 24 MHz, even though 1.5GHz are possible. With the
updated logic any casting between signed and unsigned is avoided
and the numbers look like this instead:
GPLL: 18446744073709551615 - 1188000000 = 18446744072521551615
CPLL: 18446744073709551615 - 1500000000 = 18446744072209551615
XIN24M: 18446744073709551615 - 24000000 = 18446744073685551615
As a result the parent with the highest acceptable rate is chosen
instead of the parent clock with the lowest one.
Cc: stable@vger.kernel.org
Fixes: 49502408007b ("mmc: sdhci-of-dwcmshc: properly determine max clock on Rockchip")
Tested-by: Christopher Obbard <chris.obbard@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/clk-composite.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -119,7 +119,10 @@ static int clk_composite_determine_rate(
if (ret)
continue;
- rate_diff = abs(req->rate - tmp_req.rate);
+ if (req->rate >= tmp_req.rate)
+ rate_diff = req->rate - tmp_req.rate;
+ else
+ rate_diff = tmp_req.rate - req->rate;
if (!rate_diff || !req->best_parent_hw
|| best_rate_diff > rate_diff) {

45
target/linux/rockchip/patches-6.1/117-02-clk-composite-Fix-handling-of-high-clock-rates.patch
View File

@ -1,45 +0,0 @@
From 823c6a55a620892fb8a284b880d9d5d40e1c2375 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 18 May 2023 05:28:17 +0200
Subject: [PATCH] clk: composite: Fix handling of high clock rates
If clk_round_rate(clk, ULONG_MAX) is called to acquire the highest
available clock rate and the highest available clock rate is smaller
than ULONG_MAX/2, the result of "req->rate - tmp_req.rate" has the
highest bit set. Since the input to abs() is signed, that means the
number will be miss-interpreted.
This results in the logic being reverted and the worst choice being
selected as the best one. For example this has been observed on RK3588
for the eMMC clock:
GPLL: abs(18446744073709551615 - 1188000000) = 1188000001
CPLL: abs(18446744073709551615 - 1500000000) = 1500000001
XIN24M: abs(18446744073709551615 - 24000000) = 24000001
With the updated logic any casting between signed and unsigned is
avoided and the numbers look like this instead:
GPLL: 18446744073709551615 - 1188000000 = 18446744072521551615
CPLL: 18446744073709551615 - 1500000000 = 18446744072209551615
XIN24M: 18446744073709551615 - 24000000 = 18446744073685551615
As a result the parent with the highest acceptable rate is chosen
instead of the parent clock with the lowest one.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/clk-composite.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -119,7 +119,7 @@ static int clk_composite_determine_rate(
if (ret)
continue;
- rate_diff = abs(req->rate - tmp_req.rate);
+ rate_diff = req->rate > tmp_req.rate ? req->rate - tmp_req.rate : tmp_req.rate - req->rate;
if (!rate_diff || !req->best_parent_hw
|| best_rate_diff > rate_diff) {

25
target/linux/rockchip/patches-6.1/117-01-clk-divider-Fix-handling-of-rates-UINT_MAX.patch → target/linux/rockchip/patches-6.1/117-02-clk-divider-Fix-divisions.patch
View File

@ -1,11 +1,20 @@
From cb57f471ea551d1d19bdd3a6f2a82fbf84287a1b Mon Sep 17 00:00:00 2001
From dd6d843b8fbad84cc585a1379bffd99004c83b79 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 18 May 2023 05:19:48 +0200
Subject: [PATCH] clk: divider: Fix handling of rates > UINT_MAX
Subject: [PATCH] clk: divider: Fix divisions
Fix handling of rates that exceed UINT_MAX (4.29 GHz) to do something
reasonably sensible. Right now asking for UINT_MAX+1 will effectively
return the smallest rate available instead of the biggest one.
The clock framework handles clock rates as "unsigned long", so u32 on
32-bit architectures and u64 on 64-bit architectures.
The current code pointlessly casts the dividend to u64 on 32-bit
architectures and thus pointlessly reducing the performance.
On the other hand on 64-bit architectures the divisor is masked and only
the lower 32-bit are used. Thus requesting a frequency >= 4.3GHz results
in incorrect values. For example requesting 4300000000 (4.3 GHz) will
effectively request ca. 5 MHz. Requesting clk_round_rate(clk, ULONG_MAX)
is a bit of a special case, since that still returns correct values as
long as the parent clock is below 8.5 GHz.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
@ -19,7 +28,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
unsigned long flags)
{
- int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+ int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate > UINT_MAX ? UINT_MAX : rate);
+ int div = DIV_ROUND_UP(parent_rate, rate);
if (flags & CLK_DIVIDER_POWER_OF_TWO)
div = __roundup_pow_of_two(div);
@ -28,7 +37,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
unsigned long up_rate, down_rate;
- up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+ up = DIV_ROUND_UP_ULL((u64)parent_rate, rate > UINT_MAX ? UINT_MAX : rate);
+ up = DIV_ROUND_UP(parent_rate, rate);
down = parent_rate / rate;
if (flags & CLK_DIVIDER_POWER_OF_TWO) {
@ -37,7 +46,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
unsigned int div, value;
- div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+ div = DIV_ROUND_UP_ULL((u64)parent_rate, rate > UINT_MAX ? UINT_MAX : rate);
+ div = DIV_ROUND_UP(parent_rate, rate);
if (!_is_valid_div(table, div, flags))
return -EINVAL;

114
target/linux/rockchip/patches-6.1/118-01-iio-adc-rockchip_saradc-Add-support-for-RK3588.patch → target/linux/rockchip/patches-6.1/118-01-iio-adc-rockchip_saradc-Add-callback-functions.patch
View File

@ -5,44 +5,42 @@ To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
kernel@collabora.com, gustavo.padovan@collabora.com,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>,
Simon Xue <xxm@rock-chips.com>
Subject: [PATCH 1/7] iio: adc: rockchip_saradc: Add support for RK3588
Date: Wed, 17 May 2023 04:30:45 +0530 [thread overview]
Message-ID: <20230516230051.14846-2-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230516230051.14846-1-shreeya.patel@collabora.com>
Subject: [PATCH v3 1/8] iio: adc: rockchip_saradc: Add callback functions
Date: Sun, 4 Jun 2023 00:23:33 +0530 [thread overview]
Message-ID: <20230603185340.13838-2-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
Refactor conversion operation to support rk3588 saradc and
add separate start, read, powerdown in respective hooks.
From: Simon Xue <xxm@rock-chips.com>
Add start, read and power_down callback functions,
which will help in adding new rockchip device support
cleanly.
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
---
drivers/iio/adc/rockchip_saradc.c | 127 +++++++++++++++++++++++++++---
1 file changed, 115 insertions(+), 12 deletions(-)
Changes in v3
- no change
Changes in v2
- Add a from address.
- Create a separate patch for changes done in the code for old
devices.
drivers/iio/adc/rockchip_saradc.c | 64 +++++++++++++++++++++++++------
1 file changed, 52 insertions(+), 12 deletions(-)
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -37,10 +37,29 @@
@@ -37,10 +37,15 @@
#define SARADC_TIMEOUT msecs_to_jiffies(100)
#define SARADC_MAX_CHANNELS 8
+/* v2 registers */
+#define SARADC2_CONV_CON 0x0
+#define SARADC_T_PD_SOC 0x4
+#define SARADC_T_DAS_SOC 0xc
+#define SARADC2_END_INT_EN 0x104
+#define SARADC2_ST_CON 0x108
+#define SARADC2_STATUS 0x10c
+#define SARADC2_END_INT_ST 0x110
+#define SARADC2_DATA_BASE 0x120
+
+#define SARADC2_EN_END_INT BIT(0)
+#define SARADC2_START BIT(4)
+#define SARADC2_SINGLE_MODE BIT(5)
+
+struct rockchip_saradc;
+
struct rockchip_saradc_data {
@ -55,7 +53,7 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
};
struct rockchip_saradc {
@@ -57,27 +76,77 @@ struct rockchip_saradc {
@@ -57,27 +62,50 @@ struct rockchip_saradc {
struct notifier_block nb;
};
@ -71,21 +69,6 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+ SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
+}
+
+static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
+{
+ int val;
+
+ if (info->reset)
+ rockchip_saradc_reset_controller(info->reset);
+
+ writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
+ writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
+ val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT;
+ writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
+ val = SARADC2_START | SARADC2_SINGLE_MODE | chn;
+ writel(val << 16 | val, info->regs + SARADC2_CONV_CON);
+}
+
+static void rockchip_saradc_start(struct rockchip_saradc *info, int chn)
+{
+ info->data->start(info, chn);
@ -96,18 +79,6 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+ return readl_relaxed(info->regs + SARADC_DATA);
+}
+
+static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
+{
+ int offset;
+
+ /* Clear irq */
+ writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
+
+ offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4;
+
+ return readl_relaxed(info->regs + offset);
+}
+
+static int rockchip_saradc_read(struct rockchip_saradc *info)
+{
+ return info->data->read(info);
@ -144,7 +115,7 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
return -ETIMEDOUT;
@@ -120,7 +189,7 @@ static irqreturn_t rockchip_saradc_isr(i
@@ -120,7 +148,7 @@ static irqreturn_t rockchip_saradc_isr(i
struct rockchip_saradc *info = dev_id;
/* Read value */
@ -153,7 +124,7 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
rockchip_saradc_power_down(info);
@@ -160,6 +229,9 @@ static const struct rockchip_saradc_data
@@ -160,6 +188,9 @@ static const struct rockchip_saradc_data
.channels = rockchip_saradc_iio_channels,
.num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
.clk_rate = 1000000,
@ -163,7 +134,7 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
};
static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
@@ -171,6 +243,9 @@ static const struct rockchip_saradc_data
@@ -171,6 +202,9 @@ static const struct rockchip_saradc_data
.channels = rockchip_rk3066_tsadc_iio_channels,
.num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
.clk_rate = 50000,
@ -173,7 +144,7 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
};
static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
@@ -186,6 +261,9 @@ static const struct rockchip_saradc_data
@@ -186,6 +220,9 @@ static const struct rockchip_saradc_data
.channels = rockchip_rk3399_saradc_iio_channels,
.num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
.clk_rate = 1000000,
@ -183,42 +154,13 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
};
static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
@@ -203,6 +281,28 @@ static const struct rockchip_saradc_data
@@ -203,6 +240,9 @@ static const struct rockchip_saradc_data
.channels = rockchip_rk3568_saradc_iio_channels,
.num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
.clk_rate = 1000000,
+ .start = rockchip_saradc_start_v1,
+ .read = rockchip_saradc_read_v1,
+ .power_down = rockchip_saradc_power_down_v1,
+};
+
+static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
+ SARADC_CHANNEL(0, "adc0", 12),
+ SARADC_CHANNEL(1, "adc1", 12),
+ SARADC_CHANNEL(2, "adc2", 12),
+ SARADC_CHANNEL(3, "adc3", 12),
+ SARADC_CHANNEL(4, "adc4", 12),
+ SARADC_CHANNEL(5, "adc5", 12),
+ SARADC_CHANNEL(6, "adc6", 12),
+ SARADC_CHANNEL(7, "adc7", 12),
+};
+
+static const struct rockchip_saradc_data rk3588_saradc_data = {
+ .channels = rockchip_rk3588_saradc_iio_channels,
+ .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
+ .clk_rate = 1000000,
+ .start = rockchip_saradc_start_v2,
+ .read = rockchip_saradc_read_v2,
};
static const struct of_device_id rockchip_saradc_match[] = {
@@ -218,6 +318,9 @@ static const struct of_device_id rockchi
}, {
.compatible = "rockchip,rk3568-saradc",
.data = &rk3568_saradc_data,
+ }, {
+ .compatible = "rockchip,rk3588-saradc",
+ .data = &rk3588_saradc_data,
},
{},
};

156
target/linux/rockchip/patches-6.1/118-02-iio-adc-rockchip_saradc-Add-support-for-RK3588.patch Normal file
View File

@ -0,0 +1,156 @@
From: Shreeya Patel <shreeya.patel@collabora.com>
To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
sebastian.reichel@collabora.com
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>,
Simon Xue <xxm@rock-chips.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: [PATCH v3 2/8] iio: adc: rockchip_saradc: Add support for RK3588
Date: Sun, 4 Jun 2023 00:23:34 +0530 [thread overview]
Message-ID: <20230603185340.13838-3-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
From: Simon Xue <xxm@rock-chips.com>
Add new start and read functions to support rk3588 device.
Also, add a device compatible string for the same.
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Changes in v3
- Add bitfield.h header file.
- Add a Reviewed-by tag.
Changes in v2
- Add a from address.
- Create separate patches for adding new device support and changes to
the old device code.
- Make use of FIELD_PREP.
drivers/iio/adc/rockchip_saradc.c | 70 +++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -4,6 +4,7 @@
* Copyright (C) 2014 ROCKCHIP, Inc.
*/
+#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
@@ -37,6 +38,22 @@
#define SARADC_TIMEOUT msecs_to_jiffies(100)
#define SARADC_MAX_CHANNELS 8
+/* v2 registers */
+#define SARADC2_CONV_CON 0x0
+#define SARADC_T_PD_SOC 0x4
+#define SARADC_T_DAS_SOC 0xc
+#define SARADC2_END_INT_EN 0x104
+#define SARADC2_ST_CON 0x108
+#define SARADC2_STATUS 0x10c
+#define SARADC2_END_INT_ST 0x110
+#define SARADC2_DATA_BASE 0x120
+
+#define SARADC2_EN_END_INT BIT(0)
+#define SARADC2_START BIT(4)
+#define SARADC2_SINGLE_MODE BIT(5)
+
+#define SARADC2_CONV_CHANNELS GENMASK(15, 0)
+
struct rockchip_saradc;
struct rockchip_saradc_data {
@@ -73,6 +90,25 @@ static void rockchip_saradc_start_v1(str
SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
}
+static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
+{
+ int val;
+
+ if (info->reset)
+ rockchip_saradc_reset_controller(info->reset);
+
+ writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
+ writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
+ val = FIELD_PREP(SARADC2_EN_END_INT, 1);
+ val |= val << 16;
+ writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
+ val = FIELD_PREP(SARADC2_START, 1) |
+ FIELD_PREP(SARADC2_SINGLE_MODE, 1) |
+ FIELD_PREP(SARADC2_CONV_CHANNELS, chn);
+ val |= val << 16;
+ writel(val, info->regs + SARADC2_CONV_CON);
+}
+
static void rockchip_saradc_start(struct rockchip_saradc *info, int chn)
{
info->data->start(info, chn);
@@ -83,6 +119,18 @@ static int rockchip_saradc_read_v1(struc
return readl_relaxed(info->regs + SARADC_DATA);
}
+static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
+{
+ int offset;
+
+ /* Clear irq */
+ writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
+
+ offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4;
+
+ return readl_relaxed(info->regs + offset);
+}
+
static int rockchip_saradc_read(struct rockchip_saradc *info)
{
return info->data->read(info);
@@ -245,6 +293,25 @@ static const struct rockchip_saradc_data
.power_down = rockchip_saradc_power_down_v1,
};
+static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
+ SARADC_CHANNEL(0, "adc0", 12),
+ SARADC_CHANNEL(1, "adc1", 12),
+ SARADC_CHANNEL(2, "adc2", 12),
+ SARADC_CHANNEL(3, "adc3", 12),
+ SARADC_CHANNEL(4, "adc4", 12),
+ SARADC_CHANNEL(5, "adc5", 12),
+ SARADC_CHANNEL(6, "adc6", 12),
+ SARADC_CHANNEL(7, "adc7", 12),
+};
+
+static const struct rockchip_saradc_data rk3588_saradc_data = {
+ .channels = rockchip_rk3588_saradc_iio_channels,
+ .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
+ .clk_rate = 1000000,
+ .start = rockchip_saradc_start_v2,
+ .read = rockchip_saradc_read_v2,
+};
+
static const struct of_device_id rockchip_saradc_match[] = {
{
.compatible = "rockchip,saradc",
@@ -258,6 +325,9 @@ static const struct of_device_id rockchi
}, {
.compatible = "rockchip,rk3568-saradc",
.data = &rk3568_saradc_data,
+ }, {
+ .compatible = "rockchip,rk3588-saradc",
+ .data = &rk3588_saradc_data,
},
{},
};

91
target/linux/rockchip/patches-6.1/118-02-iio-adc-rockchip_saradc-Make-use-of-devm_clk_get_enabled.patch → target/linux/rockchip/patches-6.1/118-03-iio-adc-rockchip_saradc-Make-use-of-devm_clk_get_enabled.patch
View File

@ -5,25 +5,34 @@ To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
kernel@collabora.com, gustavo.padovan@collabora.com,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>
Subject: [PATCH 2/7] iio: adc: rockchip_saradc: Make use of devm_clk_get_enabled
Date: Wed, 17 May 2023 04:30:46 +0530 [thread overview]
Message-ID: <20230516230051.14846-3-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230516230051.14846-1-shreeya.patel@collabora.com>
Subject: [PATCH v3 3/8] iio: adc: rockchip_saradc: Make use of devm_clk_get_enabled
Date: Sun, 4 Jun 2023 00:23:35 +0530 [thread overview]
Message-ID: <20230603185340.13838-4-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
Use devm_clk_get_enabled() to avoid manually disabling the
clock.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
---
drivers/iio/adc/rockchip_saradc.c | 77 +++++--------------------------
1 file changed, 11 insertions(+), 66 deletions(-)
Changes in v3
- Do not remove clock enabling and disabling from the suspend and
resume functions respectively.
Changes in v2
- No need to enable the clocks earlier than the original code.
Move the enablement of clocks at it's original position.
drivers/iio/adc/rockchip_saradc.c | 56 +++++--------------------------
1 file changed, 8 insertions(+), 48 deletions(-)
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -336,20 +336,6 @@ static void rockchip_saradc_reset_contro
@@ -343,20 +343,6 @@ static void rockchip_saradc_reset_contro
reset_control_deassert(reset);
}
@ -44,7 +53,7 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
static void rockchip_saradc_regulator_disable(void *data)
{
struct rockchip_saradc *info = data;
@@ -483,16 +469,6 @@ static int rockchip_saradc_probe(struct
@@ -490,16 +476,6 @@ static int rockchip_saradc_probe(struct
return ret;
}
@ -61,24 +70,7 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
info->vref = devm_regulator_get(&pdev->dev, "vref");
if (IS_ERR(info->vref))
return dev_err_probe(&pdev->dev, PTR_ERR(info->vref),
@@ -501,6 +477,16 @@ static int rockchip_saradc_probe(struct
if (info->reset)
rockchip_saradc_reset_controller(info->reset);
+ info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
+ if (IS_ERR(info->pclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
+ "failed to get pclk\n");
+
+ info->clk = devm_clk_get_enabled(&pdev->dev, "saradc");
+ if (IS_ERR(info->clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
+ "failed to get adc clock\n");
+
/*
* Use a default value for the converter clock.
* This may become user-configurable in the future.
@@ -530,32 +516,6 @@ static int rockchip_saradc_probe(struct
@@ -537,31 +513,15 @@ static int rockchip_saradc_probe(struct
info->uv_vref = ret;
@ -94,7 +86,11 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
- ret);
- return ret;
- }
-
+ info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
+ if (IS_ERR(info->pclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
+ "failed to get pclk\n");
- ret = clk_prepare_enable(info->clk);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to enable converter clock\n");
@ -107,39 +103,10 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
- ret);
- return ret;
- }
-
+ info->clk = devm_clk_get_enabled(&pdev->dev, "saradc");
+ if (IS_ERR(info->clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
+ "failed to get adc clock\n");
platform_set_drvdata(pdev, indio_dev);
indio_dev->name = dev_name(&pdev->dev);
@@ -589,8 +549,6 @@ static int rockchip_saradc_suspend(struc
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct rockchip_saradc *info = iio_priv(indio_dev);
- clk_disable_unprepare(info->clk);
- clk_disable_unprepare(info->pclk);
regulator_disable(info->vref);
return 0;
@@ -600,21 +558,8 @@ static int rockchip_saradc_resume(struct
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct rockchip_saradc *info = iio_priv(indio_dev);
- int ret;
-
- ret = regulator_enable(info->vref);
- if (ret)
- return ret;
-
- ret = clk_prepare_enable(info->pclk);
- if (ret)
- return ret;
-
- ret = clk_prepare_enable(info->clk);
- if (ret)
- clk_disable_unprepare(info->pclk);
- return ret;
+ return regulator_enable(info->vref);
}
static DEFINE_SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,

26
target/linux/rockchip/patches-6.1/118-03-iio-adc-rockchip_saradc-Use-of_device_get_match_data.patch → target/linux/rockchip/patches-6.1/118-04-iio-adc-rockchip_saradc-Use-of_device_get_match_data.patch
View File

@ -5,24 +5,34 @@ To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
kernel@collabora.com, gustavo.padovan@collabora.com,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>
Subject: [PATCH 3/7] iio: adc: rockchip_saradc: Use of_device_get_match_data
Date: Wed, 17 May 2023 04:30:47 +0530 [thread overview]
Message-ID: <20230516230051.14846-4-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230516230051.14846-1-shreeya.patel@collabora.com>
Shreeya Patel <shreeya.patel@collabora.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: [PATCH v3 4/8] iio: adc: rockchip_saradc: Use of_device_get_match_data
Date: Sun, 4 Jun 2023 00:23:36 +0530 [thread overview]
Message-ID: <20230603185340.13838-5-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
Use of_device_get_match_data() to simplify the code.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Changes in v3
- No change
Changes in v2
- Add a Reviewed-by tag.
drivers/iio/adc/rockchip_saradc.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -405,10 +405,10 @@ static void rockchip_saradc_regulator_un
@@ -412,10 +412,10 @@ static void rockchip_saradc_regulator_un
static int rockchip_saradc_probe(struct platform_device *pdev)
{
@ -34,7 +44,7 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
int ret;
int irq;
@@ -422,13 +422,13 @@ static int rockchip_saradc_probe(struct
@@ -429,13 +429,13 @@ static int rockchip_saradc_probe(struct
}
info = iio_priv(indio_dev);

26
target/linux/rockchip/patches-6.1/118-04-iio-adc-rockchip_saradc-Match-alignment-with-open-parenth.patch → target/linux/rockchip/patches-6.1/118-05-iio-adc-rockchip_saradc-Match-alignment-with-open-parenth.patch
View File

@ -5,25 +5,35 @@ To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
kernel@collabora.com, gustavo.padovan@collabora.com,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>
Subject: [PATCH 4/7] iio: adc: rockchip_saradc: Match alignment with open parenthesis
Date: Wed, 17 May 2023 04:30:48 +0530 [thread overview]
Message-ID: <20230516230051.14846-5-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230516230051.14846-1-shreeya.patel@collabora.com>
Shreeya Patel <shreeya.patel@collabora.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: [PATCH v3 5/8] iio: adc: rockchip_saradc: Match alignment with open parenthesis
Date: Sun, 4 Jun 2023 00:23:37 +0530 [thread overview]
Message-ID: <20230603185340.13838-6-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
Match alignment with open parenthesis for improving the code
readability.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Changes in v3
- No change
Changes in v2
- Add a Reviewed-by tag.
drivers/iio/adc/rockchip_saradc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -141,7 +141,7 @@ static void rockchip_saradc_power_down(s
@@ -148,7 +148,7 @@ static void rockchip_saradc_power_down(s
}
static int rockchip_saradc_conversion(struct rockchip_saradc *info,
@ -32,7 +42,7 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
{
reinit_completion(&info->completion);
@@ -384,8 +384,7 @@ out:
@@ -391,8 +391,7 @@ out:
}
static int rockchip_saradc_volt_notify(struct notifier_block *nb,

21
target/linux/rockchip/patches-6.1/118-05-iio-adc-rockchip_saradc-Use-dev_err_probe.patch → target/linux/rockchip/patches-6.1/118-06-iio-adc-rockchip_saradc-Use-dev_err_probe.patch
View File

@ -5,13 +5,13 @@ To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
kernel@collabora.com, gustavo.padovan@collabora.com,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>
Subject: [PATCH 5/7] iio: adc: rockchip_saradc: Use dev_err_probe
Date: Wed, 17 May 2023 04:30:49 +0530 [thread overview]
Message-ID: <20230516230051.14846-6-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230516230051.14846-1-shreeya.patel@collabora.com>
Subject: [PATCH v3 6/8] iio: adc: rockchip_saradc: Use dev_err_probe
Date: Sun, 4 Jun 2023 00:23:38 +0530 [thread overview]
Message-ID: <20230603185340.13838-7-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
Use dev_err_probe instead of dev_err in probe function,
which simplifies code a little bit and prints the error
@ -19,12 +19,19 @@ code.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
---
Changes in v3
- No change
Changes in v2
- No change
drivers/iio/adc/rockchip_saradc.c | 45 ++++++++++++++-----------------
1 file changed, 20 insertions(+), 25 deletions(-)
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -415,25 +415,23 @@ static int rockchip_saradc_probe(struct
@@ -422,25 +422,23 @@ static int rockchip_saradc_probe(struct
return -ENODEV;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
@ -60,7 +67,7 @@ Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
info->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(info->regs))
@@ -491,23 +489,20 @@ static int rockchip_saradc_probe(struct
@@ -488,23 +486,20 @@ static int rockchip_saradc_probe(struct
* This may become user-configurable in the future.
*/
ret = clk_set_rate(info->clk, info->data->clk_rate);

17
target/linux/rockchip/patches-6.1/118-06-arm64-dts-rockchip-Add-DT-node-for-ADC-support-in-RK3588.patch → target/linux/rockchip/patches-6.1/118-07-arm64-dts-rockchip-Add-DT-node-for-ADC-support-in-RK3588.patch
View File

@ -5,18 +5,25 @@ To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
kernel@collabora.com, gustavo.padovan@collabora.com,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>
Subject: [PATCH 6/7] arm64: dts: rockchip: Add DT node for ADC support in RK3588
Date: Wed, 17 May 2023 04:30:50 +0530 [thread overview]
Message-ID: <20230516230051.14846-7-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230516230051.14846-1-shreeya.patel@collabora.com>
Subject: [PATCH v3 7/8] arm64: dts: rockchip: Add DT node for ADC support in RK3588
Date: Sun, 4 Jun 2023 00:23:39 +0530 [thread overview]
Message-ID: <20230603185340.13838-8-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
Add DT node for ADC support in RK3588.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
---
Changes in v3
- No change
Changes in v2
- No change
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)