target/ipq40xx: init kernel 5.4 support
This commit is contained in:
CN_SZTL
parent
8853e1aa06
commit
468ae867b8
@ -1,8 +1,105 @@
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diff --git a/src/main.c b/src/main.c
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index 6a9c97a..d902b3d 100644
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--- a/nDPI-patch/src/lib/protocols/netflow.c
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+++ b/nDPI-patch/src/lib/protocols/netflow.c
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@@ -21,6 +21,7 @@
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*/
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+#include <linux/version.h>
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#include "ndpi_api.h"
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#ifdef NDPI_PROTOCOL_NETFLOW
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@@ -29,7 +30,11 @@
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#ifdef WIN32
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extern int gettimeofday(struct timeval * tp, struct timezone * tzp);
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#endif
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+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)
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#define do_gettimeofday(a) gettimeofday(a, NULL)
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+#else
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+#define ktime_get_real_ts64(a) gettimeofday(a, NULL)
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+#endif
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#endif
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struct flow_ver1_rec {
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@@ -105,7 +110,11 @@ static void ndpi_check_netflow(struct ndpi_detection_module_struct *ndpi_struct,
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// const u_int8_t *packet_payload = packet->payload;
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u_int32_t payload_len = packet->payload_packet_len;
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time_t now;
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+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)
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struct timeval now_tv;
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+#else
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+ struct timespec64 now_tv;
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+#endif
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if((packet->udp != NULL) && (payload_len >= 24)) {
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u_int16_t version = (packet->payload[0] << 8) + packet->payload[1], uptime_offset;
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@@ -158,7 +167,11 @@ static void ndpi_check_netflow(struct ndpi_detection_module_struct *ndpi_struct,
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_when = (u_int32_t*)&packet->payload[uptime_offset]; /* Sysuptime */
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when = ntohl(*_when);
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+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)
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do_gettimeofday(&now_tv);
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+#else
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+ ktime_get_real_ts64(&now_tv);
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+#endif
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now = now_tv.tv_sec;
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if(((version == 1) && (when == 0))
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--- a/src/main.c
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+++ b/src/main.c
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@@ -630,7 +630,7 @@ ndpi_mt(const struct sk_buff *skb, struct xt_action_param *par)
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@@ -383,9 +383,16 @@ static void ndpi_gc_flow(void)
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union nf_inet_addr *ipdst;
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u64 t1;
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+
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+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)
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struct timeval tv;
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do_gettimeofday(&tv);
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+#else
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+ struct timespec64 tv;
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+
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+ ktime_get_real_ts64(&tv);
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+#endif
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t1 = (uint64_t) tv.tv_sec;
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if (debug_dpi) pr_info ("xt_ndpi: call garbage collector.\n");
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@@ -418,7 +425,11 @@ ndpi_process_packet(struct nf_conn * ct, const uint64_t time,
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u8 exist_flow=0;
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u64 t1;
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+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)
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struct timeval tv;
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+#else
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+ struct timespec64 tv;
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+#endif
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spin_lock_bh (&flow_lock);
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ipsrc = &ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3;
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@@ -449,7 +460,11 @@ ndpi_process_packet(struct nf_conn * ct, const uint64_t time,
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}
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}
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+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)
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do_gettimeofday(&tv);
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+#else
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+ ktime_get_real_ts64(&tv);
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+#endif
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t1 = (uint64_t) tv.tv_sec;
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if (flow == NULL) {
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@@ -602,7 +617,11 @@ ndpi_mt(const struct sk_buff *skb, struct xt_action_param *par)
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enum ip_conntrack_info ctinfo;
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struct nf_conn * ct;
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+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)
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struct timeval tv;
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+#else
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+ struct timespec64 tv;
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+#endif
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struct sk_buff *linearized_skb = NULL;
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const struct sk_buff *skb_use = NULL;
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@@ -630,7 +649,7 @@ ndpi_mt(const struct sk_buff *skb, struct xt_action_param *par)
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#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
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} else if (nf_ct_is_untracked(skb)){
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#else
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@ -11,3 +108,19 @@ index 6a9c97a..d902b3d 100644
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#endif
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pr_info ("xt_ndpi: ignoring untracked sk_buff.\n");
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return false;
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@@ -641,9 +660,15 @@ ndpi_mt(const struct sk_buff *skb, struct xt_action_param *par)
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ip = ip_hdr(skb_use);
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tcph = (const void *)ip + ip_hdrlen(skb_use);
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+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)
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do_gettimeofday(&tv);
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time = ((uint64_t) tv.tv_sec) * detection_tick_resolution +
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tv.tv_usec / (1000000 / detection_tick_resolution);
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+#else
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+ ktime_get_real_ts64(&tv);
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+ time = ((uint64_t) tv.tv_sec) * detection_tick_resolution +
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+ (tv.tv_nsec / 1000 )/ (1000000 / detection_tick_resolution);
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+#endif
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/* reset for new packets and solve ct collisions */
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if (ctinfo == IP_CT_NEW) {
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555
target/linux/ipq40xx/config-5.4
Normal file
555
target/linux/ipq40xx/config-5.4
Normal file
@ -0,0 +1,555 @@
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CONFIG_ALIGNMENT_TRAP=y
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# CONFIG_APQ_GCC_8084 is not set
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# CONFIG_APQ_MMCC_8084 is not set
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CONFIG_AR40XX_PHY=y
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CONFIG_ARCH_32BIT_OFF_T=y
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CONFIG_ARCH_CLOCKSOURCE_DATA=y
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CONFIG_ARCH_HAS_BINFMT_FLAT=y
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CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
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CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
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CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
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CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
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CONFIG_ARCH_HAS_KCOV=y
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CONFIG_ARCH_HAS_KEEPINITRD=y
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CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
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CONFIG_ARCH_HAS_PHYS_TO_DMA=y
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CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
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CONFIG_ARCH_HAS_SET_MEMORY=y
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CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
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CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
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CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
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CONFIG_ARCH_HAS_TICK_BROADCAST=y
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_IPQ40XX=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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# CONFIG_ARCH_MDM9615 is not set
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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# CONFIG_ARCH_MSM8960 is not set
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# CONFIG_ARCH_MSM8974 is not set
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# CONFIG_ARCH_MSM8X60 is not set
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CONFIG_ARCH_MULTIPLATFORM=y
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CONFIG_ARCH_MULTI_V6_V7=y
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CONFIG_ARCH_MULTI_V7=y
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CONFIG_ARCH_NR_GPIO=0
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CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
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CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
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CONFIG_ARCH_QCOM=y
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CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
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CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
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CONFIG_ARCH_SUPPORTS_UPROBES=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_USE_BUILTIN_BSWAP=y
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CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
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CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
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CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_ARM=y
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CONFIG_ARM_AMBA=y
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CONFIG_ARM_APPENDED_DTB=y
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CONFIG_ARM_ARCH_TIMER=y
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CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
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# CONFIG_ARM_ATAG_DTB_COMPAT is not set
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CONFIG_ARM_CPUIDLE=y
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CONFIG_ARM_CPU_SUSPEND=y
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# CONFIG_ARM_CPU_TOPOLOGY is not set
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CONFIG_ARM_CRYPTO=y
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CONFIG_ARM_GIC=y
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CONFIG_ARM_HAS_SG_CHAIN=y
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CONFIG_ARM_L1_CACHE_SHIFT=6
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CONFIG_ARM_L1_CACHE_SHIFT_6=y
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# CONFIG_ARM_LPAE is not set
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CONFIG_ARM_PATCH_IDIV=y
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CONFIG_ARM_PATCH_PHYS_VIRT=y
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# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
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# CONFIG_ARM_SMMU is not set
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# CONFIG_ARM_SP805_WATCHDOG is not set
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CONFIG_ARM_THUMB=y
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# CONFIG_ARM_THUMBEE is not set
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CONFIG_ARM_UNWIND=y
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CONFIG_ARM_VIRT_EXT=y
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CONFIG_AT803X_PHY=y
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CONFIG_AUTO_ZRELADDR=y
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CONFIG_BCH=y
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CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BOUNCE=y
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# CONFIG_CACHE_L2X0 is not set
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CONFIG_CC_HAS_KASAN_GENERIC=y
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLKSRC_QCOM=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_COMMON_CLK=y
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CONFIG_COMMON_CLK_QCOM=y
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CONFIG_COMPAT_32BIT_TIME=y
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CONFIG_CPUFREQ_DT=y
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CONFIG_CPUFREQ_DT_PLATDEV=y
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CONFIG_CPU_32v6K=y
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CONFIG_CPU_32v7=y
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CONFIG_CPU_ABRT_EV7=y
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# CONFIG_CPU_BIG_ENDIAN is not set
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# CONFIG_CPU_BPREDICT_DISABLE is not set
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CONFIG_CPU_CACHE_V7=y
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CONFIG_CPU_CACHE_VIPT=y
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CONFIG_CPU_COPY_V6=y
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CONFIG_CPU_CP15=y
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CONFIG_CPU_CP15_MMU=y
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CONFIG_CPU_FREQ=y
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CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
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# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
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CONFIG_CPU_FREQ_GOV_ATTR_SET=y
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CONFIG_CPU_FREQ_GOV_COMMON=y
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# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
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CONFIG_CPU_FREQ_GOV_ONDEMAND=y
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CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
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# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
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# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
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CONFIG_CPU_FREQ_STAT=y
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CONFIG_CPU_HAS_ASID=y
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# CONFIG_CPU_ICACHE_DISABLE is not set
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# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set
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CONFIG_CPU_IDLE=y
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CONFIG_CPU_IDLE_GOV_LADDER=y
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CONFIG_CPU_IDLE_GOV_MENU=y
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CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
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CONFIG_CPU_PABRT_V7=y
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CONFIG_CPU_PM=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_SPECTRE=y
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CONFIG_CPU_THERMAL=y
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CONFIG_CPU_THUMB_CAPABLE=y
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CONFIG_CPU_TLB_V7=y
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CONFIG_CPU_V7=y
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CONFIG_CRC16=y
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# CONFIG_CRC32_SARWATE is not set
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CONFIG_CRC32_SLICEBY8=y
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CONFIG_CRYPTO_ACOMP2=y
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CONFIG_CRYPTO_AEAD=y
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CONFIG_CRYPTO_AEAD2=y
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CONFIG_CRYPTO_AES_ARM=y
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CONFIG_CRYPTO_AES_ARM_BS=y
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CONFIG_CRYPTO_CBC=y
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CONFIG_CRYPTO_CRYPTD=y
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CONFIG_CRYPTO_CTR=y
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CONFIG_CRYPTO_DEFLATE=y
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CONFIG_CRYPTO_DES=y
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CONFIG_CRYPTO_DEV_QCE=y
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# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
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# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
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CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
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CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
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CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
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CONFIG_CRYPTO_DEV_QCOM_RNG=y
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CONFIG_CRYPTO_DRBG=y
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CONFIG_CRYPTO_DRBG_HMAC=y
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CONFIG_CRYPTO_DRBG_MENU=y
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CONFIG_CRYPTO_ECB=y
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CONFIG_CRYPTO_HASH=y
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CONFIG_CRYPTO_HASH2=y
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CONFIG_CRYPTO_HASH_INFO=y
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CONFIG_CRYPTO_HMAC=y
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CONFIG_CRYPTO_HW=y
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CONFIG_CRYPTO_JITTERENTROPY=y
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CONFIG_CRYPTO_LIB_DES=y
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CONFIG_CRYPTO_LIB_SHA256=y
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CONFIG_CRYPTO_LZO=y
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CONFIG_CRYPTO_MANAGER=y
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CONFIG_CRYPTO_MANAGER2=y
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CONFIG_CRYPTO_NULL=y
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CONFIG_CRYPTO_NULL2=y
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CONFIG_CRYPTO_RNG=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CRYPTO_RNG_DEFAULT=y
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CONFIG_CRYPTO_SEQIV=y
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CONFIG_CRYPTO_SHA256=y
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CONFIG_CRYPTO_SHA256_ARM=y
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CONFIG_CRYPTO_SIMD=y
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CONFIG_CRYPTO_XTS=y
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CONFIG_CRYPTO_ZSTD=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
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CONFIG_DEBUG_MISC=y
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# CONFIG_DEBUG_USER is not set
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CONFIG_DMADEVICES=y
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CONFIG_DMA_ENGINE=y
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CONFIG_DMA_OF=y
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CONFIG_DMA_REMAP=y
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CONFIG_DMA_SHARED_BUFFER=y
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CONFIG_DMA_VIRTUAL_CHANNELS=y
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CONFIG_DTC=y
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CONFIG_DT_IDLE_STATES=y
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CONFIG_DYNAMIC_DEBUG=y
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CONFIG_EDAC_ATOMIC_SCRUB=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_EEPROM_AT24=y
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CONFIG_ESSEDMA=y
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CONFIG_EXTCON=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_EARLY_IOREMAP=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
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CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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CONFIG_GENERIC_MSI_IRQ=y
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CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_PHY=y
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CONFIG_GENERIC_PINCONF=y
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CONFIG_GENERIC_PINCTRL_GROUPS=y
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CONFIG_GENERIC_PINMUX_FUNCTIONS=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIOLIB_IRQCHIP=y
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CONFIG_GPIO_74X164=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_GPIO_WATCHDOG=y
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# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
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CONFIG_HANDLE_DOMAIN_IRQ=y
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CONFIG_HARDEN_BRANCH_PREDICTOR=y
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HAVE_ARCH_AUDITSYSCALL=y
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CONFIG_HAVE_ARCH_BITREVERSE=y
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_ARCH_PFN_VALID=y
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CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
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CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
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CONFIG_HAVE_ARCH_TRACEHOOK=y
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CONFIG_HAVE_ARM_ARCH_TIMER=y
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CONFIG_HAVE_ARM_SMCCC=y
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CONFIG_HAVE_CLK=y
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CONFIG_HAVE_CLK_PREPARE=y
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CONFIG_HAVE_CONTEXT_TRACKING=y
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CONFIG_HAVE_COPY_THREAD_TLS=y
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CONFIG_HAVE_C_RECORDMCOUNT=y
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CONFIG_HAVE_DEBUG_KMEMLEAK=y
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CONFIG_HAVE_DMA_CONTIGUOUS=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
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CONFIG_HAVE_EBPF_JIT=y
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CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
|
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CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
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CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
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CONFIG_HAVE_NET_DSA=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_OPTPROBES=y
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CONFIG_HAVE_PCI=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HAVE_PERF_REGS=y
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CONFIG_HAVE_PERF_USER_STACK_DUMP=y
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CONFIG_HAVE_PROC_CPU=y
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CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
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CONFIG_HAVE_RSEQ=y
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CONFIG_HAVE_SMP=y
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CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
|
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CONFIG_HAVE_UID16=y
|
||||
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
|
||||
CONFIG_HIGHMEM=y
|
||||
# CONFIG_HIGHPTE is not set
|
||||
CONFIG_HWSPINLOCK=y
|
||||
CONFIG_HWSPINLOCK_QCOM=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_OPTEE=y
|
||||
CONFIG_HZ_FIXED=0
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
# CONFIG_IOMMU_DEBUGFS is not set
|
||||
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
|
||||
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
|
||||
CONFIG_IOMMU_SUPPORT=y
|
||||
CONFIG_IO_URING=y
|
||||
CONFIG_IPQ_GCC_4019=y
|
||||
# CONFIG_IPQ_GCC_806X is not set
|
||||
# CONFIG_IPQ_GCC_8074 is not set
|
||||
# CONFIG_IPQ_LCC_806X is not set
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
# CONFIG_KPSS_XCC is not set
|
||||
# CONFIG_KRAITCC is not set
|
||||
CONFIG_LEDS_LP5523=y
|
||||
CONFIG_LEDS_LP5562=y
|
||||
CONFIG_LEDS_LP55XX_COMMON=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_MDIO_BITBANG=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_GPIO=y
|
||||
CONFIG_MDIO_IPQ40XX=y
|
||||
# CONFIG_MDM_GCC_9615 is not set
|
||||
# CONFIG_MDM_LCC_9615 is not set
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
# CONFIG_MFD_QCOM_RPM is not set
|
||||
# CONFIG_MFD_SPMI_PMIC is not set
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
|
||||
CONFIG_MMC_SDHCI_MSM=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
# CONFIG_MMC_TIFM_SD is not set
|
||||
CONFIG_MODULES_USE_ELF_REL=y
|
||||
# CONFIG_MSM_GCC_8660 is not set
|
||||
# CONFIG_MSM_GCC_8916 is not set
|
||||
# CONFIG_MSM_GCC_8960 is not set
|
||||
# CONFIG_MSM_GCC_8974 is not set
|
||||
# CONFIG_MSM_GCC_8994 is not set
|
||||
# CONFIG_MSM_GCC_8996 is not set
|
||||
# CONFIG_MSM_GCC_8998 is not set
|
||||
# CONFIG_MSM_LCC_8960 is not set
|
||||
# CONFIG_MSM_MMCC_8960 is not set
|
||||
# CONFIG_MSM_MMCC_8974 is not set
|
||||
# CONFIG_MSM_MMCC_8996 is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_NAND_CORE=y
|
||||
CONFIG_MTD_NAND_ECC_SW_BCH=y
|
||||
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
|
||||
CONFIG_MTD_NAND_QCOM=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MTD_SPLIT_FIT_FW=y
|
||||
CONFIG_MTD_SPLIT_WRGG_FW=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
# CONFIG_MTD_UBI_FASTMAP is not set
|
||||
# CONFIG_MTD_UBI_GLUEBI is not set
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_NET_DEVLINK=y
|
||||
CONFIG_NET_DSA=y
|
||||
CONFIG_NET_DSA_QCA8K=y
|
||||
CONFIG_NET_DSA_TAG_QCA=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_PTP_CLASSIFY=y
|
||||
CONFIG_NET_SWITCHDEV=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=4
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OLD_SIGACTION=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_OFFSET=0xC0000000
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
CONFIG_PCIE_QCOM=y
|
||||
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PERF_USE_VMALLOC=y
|
||||
CONFIG_PGTABLE_LEVELS=2
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLINK=y
|
||||
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
|
||||
CONFIG_PHY_QCOM_IPQ4019_USB=y
|
||||
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
|
||||
# CONFIG_PHY_QCOM_PCIE2 is not set
|
||||
# CONFIG_PHY_QCOM_QMP is not set
|
||||
# CONFIG_PHY_QCOM_QUSB2 is not set
|
||||
# CONFIG_PHY_QCOM_UFS is not set
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_APQ8064 is not set
|
||||
# CONFIG_PINCTRL_APQ8084 is not set
|
||||
CONFIG_PINCTRL_IPQ4019=y
|
||||
# CONFIG_PINCTRL_IPQ8064 is not set
|
||||
# CONFIG_PINCTRL_IPQ8074 is not set
|
||||
# CONFIG_PINCTRL_MDM9615 is not set
|
||||
CONFIG_PINCTRL_MSM=y
|
||||
# CONFIG_PINCTRL_MSM8660 is not set
|
||||
# CONFIG_PINCTRL_MSM8916 is not set
|
||||
# CONFIG_PINCTRL_MSM8960 is not set
|
||||
# CONFIG_PINCTRL_MSM8994 is not set
|
||||
# CONFIG_PINCTRL_MSM8996 is not set
|
||||
# CONFIG_PINCTRL_MSM8998 is not set
|
||||
# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
|
||||
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
|
||||
# CONFIG_PINCTRL_QCS404 is not set
|
||||
# CONFIG_PINCTRL_SC7180 is not set
|
||||
# CONFIG_PINCTRL_SDM660 is not set
|
||||
# CONFIG_PINCTRL_SDM845 is not set
|
||||
# CONFIG_PINCTRL_SM8150 is not set
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_MSM=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_PPS=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_PTP_1588_CLOCK=y
|
||||
CONFIG_QCOM_A53PLL=y
|
||||
CONFIG_QCOM_BAM_DMA=y
|
||||
# CONFIG_QCOM_COMMAND_DB is not set
|
||||
# CONFIG_QCOM_EBI2 is not set
|
||||
# CONFIG_QCOM_GENI_SE is not set
|
||||
# CONFIG_QCOM_GSBI is not set
|
||||
# CONFIG_QCOM_HFPLL is not set
|
||||
# CONFIG_QCOM_IOMMU is not set
|
||||
# CONFIG_QCOM_LLCC is not set
|
||||
# CONFIG_QCOM_PDC is not set
|
||||
CONFIG_QCOM_PM=y
|
||||
CONFIG_QCOM_QFPROM=y
|
||||
# CONFIG_QCOM_RMTFS_MEM is not set
|
||||
CONFIG_QCOM_SCM=y
|
||||
CONFIG_QCOM_SCM_32=y
|
||||
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
|
||||
CONFIG_QCOM_SMEM=y
|
||||
# CONFIG_QCOM_SMSM is not set
|
||||
# CONFIG_QCOM_SOCINFO is not set
|
||||
CONFIG_QCOM_TCSR=y
|
||||
# CONFIG_QCOM_TSENS is not set
|
||||
CONFIG_QCOM_WDT=y
|
||||
# CONFIG_QCS_GCC_404 is not set
|
||||
# CONFIG_QCS_TURING_404 is not set
|
||||
# CONFIG_QRTR is not set
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
CONFIG_RCU_CPU_STALL_TIMEOUT=21
|
||||
CONFIG_RCU_NEED_SEGCBLIST=y
|
||||
CONFIG_RCU_STALL_COMMON=y
|
||||
CONFIG_REFCOUNT_FULL=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
# CONFIG_REGULATOR_QCOM_SPMI is not set
|
||||
CONFIG_REGULATOR_VCTRL=y
|
||||
CONFIG_REGULATOR_VQMMC_IPQ4019=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
# CONFIG_RESET_QCOM_AOSS is not set
|
||||
# CONFIG_RESET_QCOM_PDC is not set
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
# CONFIG_SDM_CAMCC_845 is not set
|
||||
# CONFIG_SDM_DISPCC_845 is not set
|
||||
# CONFIG_SDM_GCC_660 is not set
|
||||
# CONFIG_SDM_GCC_845 is not set
|
||||
# CONFIG_SDM_GPUCC_845 is not set
|
||||
# CONFIG_SDM_LPASSCC_845 is not set
|
||||
# CONFIG_SDM_VIDEOCC_845 is not set
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
# CONFIG_SERIAL_AMBA_PL011 is not set
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_ON_UP=y
|
||||
# CONFIG_SM_GCC_8150 is not set
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_GPIO=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_QUP=y
|
||||
CONFIG_SPMI=y
|
||||
CONFIG_SPMI_MSM_PMIC_ARB=y
|
||||
# CONFIG_SPMI_PMIC_CLKDIV is not set
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_SWCONFIG=y
|
||||
CONFIG_SWCONFIG_LEDS=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SWP_EMULATE=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
# CONFIG_THUMB2_KERNEL is not set
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
CONFIG_UBIFS_FS_ZSTD=y
|
||||
CONFIG_UEVENT_HELPER_PATH=""
|
||||
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
||||
CONFIG_UNWINDER_ARM=y
|
||||
# CONFIG_UNWINDER_FRAME_POINTER is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
# CONFIG_USB_EHCI_HCD is not set
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_VDSO=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_VFPv3=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZBOOT_ROM_BSS=0
|
||||
CONFIG_ZBOOT_ROM_TEXT=0
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZSTD_COMPRESS=y
|
||||
CONFIG_ZSTD_DECOMPRESS=y
|
||||
@ -0,0 +1,204 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "OpenMesh A42";
|
||||
compatible = "openmesh,a42", "qcom,ipq4019";
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
/* select hostmode */
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2: usb2@60f8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
red {
|
||||
label = "a42:red:status";
|
||||
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
power: green {
|
||||
label = "a42:green:status";
|
||||
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
blue {
|
||||
label = "a42:blue:status";
|
||||
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "linux,wdt-gpio";
|
||||
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
|
||||
hw_algo = "toggle";
|
||||
/* hw_margin_ms is actually 300s but driver limits it to 60s */
|
||||
hw_margin_ms = <60000>;
|
||||
always-running;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
pin {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pin_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
/* partitions are passed via bootloader */
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
vlan_tag = <1 0x31>;
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "OM-A42";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "OM-A42";
|
||||
};
|
||||
@ -0,0 +1,332 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "ALFA Network AP120C-AC";
|
||||
compatible = "alfa-network,ap120c-ac", "qcom,ipq4019";
|
||||
|
||||
aliases {
|
||||
led-boot = &status;
|
||||
led-failsafe = &status;
|
||||
led-running = &status;
|
||||
led-upgrade = &status;
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status: status {
|
||||
label = "ap120c-ac:blue:status";
|
||||
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
wan {
|
||||
label = "ap120c-ac:amber:wan";
|
||||
gpios = <&qca8075 19 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan2g {
|
||||
label = "ap120c-ac:green:wlan2g";
|
||||
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "phy0tpt";
|
||||
};
|
||||
|
||||
wlan5g {
|
||||
label = "ap120c-ac:red:wlan5g";
|
||||
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "phy1tpt";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
counter@4a1000 {
|
||||
compatible = "qcom,qca-gcnt";
|
||||
reg = <0x4a1000 0x4>;
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2@60f8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@8a00000 {
|
||||
phys = <&usb3_hs_phy>;
|
||||
phy-names = "usb2-phy";
|
||||
};
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
qca8075: ess-switch@c000000 {
|
||||
status = "okay";
|
||||
|
||||
switch_lan_bmp = <0x10>;
|
||||
switch_wan_bmp = <0x20>;
|
||||
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_i2c3 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
tpm@29 {
|
||||
compatible = "atmel,at97sc3204t";
|
||||
reg = <0x29>;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
|
||||
<&tlmm 4 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@60000 {
|
||||
label = "QSEE";
|
||||
reg = <0x00060000 0x00060000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@c0000 {
|
||||
label = "CDT";
|
||||
reg = <0x000c0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@d0000 {
|
||||
label = "DDRPARAMS";
|
||||
reg = <0x000d0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@e0000 {
|
||||
label = "APPSBLENV";
|
||||
reg = <0x000e0000 0x00010000>;
|
||||
};
|
||||
|
||||
partition@f0000 {
|
||||
label = "APPSBL";
|
||||
reg = <0x000f0000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@170000 {
|
||||
label = "ART";
|
||||
reg = <0x00170000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "priv_data1";
|
||||
reg = <0x00180000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@190000 {
|
||||
label = "priv_data2";
|
||||
reg = <0x00190000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nand@1 {
|
||||
compatible = "spinand,mt29f";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "rootfs1";
|
||||
reg = <0x00000000 0x04000000>;
|
||||
};
|
||||
|
||||
partition@4000000 {
|
||||
label = "rootfs2";
|
||||
reg = <0x04000000 0x04000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&serial0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
vlan_tag = <1 0x31>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
i2c0_pins: i2c0_pinmux {
|
||||
mux_i2c {
|
||||
function = "blsp_i2c0";
|
||||
pins = "gpio58", "gpio59";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
mdio_pins: mdio_pinmux {
|
||||
mux_mdio {
|
||||
pins = "gpio53";
|
||||
function = "mdio";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux_mdc {
|
||||
pins = "gpio52";
|
||||
function = "mdc";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
serial0_pins: serial0_pinmux {
|
||||
mux_uart {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi0_pins: spi0_pinmux {
|
||||
mux_spi {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54", "gpio4";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
|
||||
};
|
||||
@ -0,0 +1,287 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "Linksys EA6350v3";
|
||||
compatible = "linksys,ea6350v3", "qcom,ipq4019";
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2@60f8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power: status {
|
||||
label = "EA6350v3:green:status";
|
||||
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "linksys-ea6350v3";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "linksys-ea6350v3";
|
||||
};
|
||||
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
mux {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54", "gpio59";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_spi1 { /* BLSP1 QUP1 */
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
|
||||
<&tlmm 59 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
SBL1@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
MBIB@40000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
QSEE@60000 {
|
||||
label = "QSEE";
|
||||
reg = <0x00060000 0x00060000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
CDT@c0000 {
|
||||
label = "CDT";
|
||||
reg = <0x000c0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBLENV@d0000 {
|
||||
label = "APPSBLENV";
|
||||
reg = <0x000d0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBL@e0000 {
|
||||
label = "APPSBL"; /* uboot */
|
||||
reg = <0x000e0000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
ART@160000 {
|
||||
label = "ART";
|
||||
reg = <0x00160000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
u_env@170000 {
|
||||
label = "u_env";
|
||||
reg = <0x00170000 0x00020000>;
|
||||
};
|
||||
|
||||
s_env@190000 {
|
||||
label = "s_env";
|
||||
reg = <0x00190000 0x00020000>;
|
||||
};
|
||||
|
||||
devinfo@1b0000 {
|
||||
label = "devinfo";
|
||||
reg = <0x001b0000 0x00010000>;
|
||||
};
|
||||
/* 0x001c0000 - 0x00200000 unused */
|
||||
};
|
||||
};
|
||||
|
||||
flash@1 {
|
||||
status = "okay";
|
||||
compatible = "spinand,mt29f", "w25n01gv";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
kernel@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x02800000>;
|
||||
};
|
||||
|
||||
rootfs@300000 {
|
||||
label = "rootfs";
|
||||
reg = <0x00300000 0x02500000>;
|
||||
};
|
||||
|
||||
alt_kernel@2800000 {
|
||||
label = "alt_kernel";
|
||||
reg = <0x02800000 0x02800000>;
|
||||
};
|
||||
|
||||
alt_rootfs@2b00000 {
|
||||
label = "alt_rootfs";
|
||||
reg = <0x02b00000 0x02500000>;
|
||||
};
|
||||
|
||||
sysdiag@5000000 {
|
||||
label = "sysdiag";
|
||||
reg = <0x05000000 0x00100000>;
|
||||
};
|
||||
|
||||
syscfg@5100000 {
|
||||
label = "syscfg";
|
||||
reg = <0x05100000 0x02F00000>;
|
||||
};
|
||||
/* 0x00000000 - 0x08000000: 128 MiB */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
@ -0,0 +1,242 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "EnGenius EAP1300";
|
||||
compatible = "engenius,eap1300", "qcom,ipq4019";
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power: orange {
|
||||
label = "eap1300:orange:power";
|
||||
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan {
|
||||
label = "eap1300:blue:lan";
|
||||
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
mesh {
|
||||
label = "eap1300:blue:mesh";
|
||||
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan2g {
|
||||
label = "eap1300:blue:wlan2g";
|
||||
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan5g {
|
||||
label = "eap1300:yellow:wlan5g";
|
||||
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
pin {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio54", "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pin_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
m25p80@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "0:SBL1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition1@40000 {
|
||||
label = "0:MIBIB";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition2@60000 {
|
||||
label = "0:QSEE";
|
||||
reg = <0x00060000 0x00060000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition3@c0000 {
|
||||
label = "0:CDT";
|
||||
reg = <0x000c0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition4@d0000 {
|
||||
label = "0:DDRPARAMS";
|
||||
reg = <0x000d0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition5@e0000 {
|
||||
label = "0:APPSBLENV";
|
||||
reg = <0x000e0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition6@f0000 {
|
||||
label = "0:APPSBL";
|
||||
reg = <0x000f0000 0x00090000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition7@180000 {
|
||||
label = "0:ART";
|
||||
reg = <0x00180000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition8@190000 {
|
||||
compatible = "denx,fit";
|
||||
label = "firmware";
|
||||
reg = <0x190000 0x1dc0000>;
|
||||
};
|
||||
|
||||
partition9@1f50000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x01f50000 0x00010000>;
|
||||
};
|
||||
|
||||
partition10@1f60000 {
|
||||
label = "userconfig";
|
||||
reg = <0x01f60000 0x000a0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
vlan_tag = <2 0x20>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
vlan_tag = <1 0x10>;
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
|
||||
};
|
||||
@ -0,0 +1,272 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "EnGenius ENS620EXT";
|
||||
compatible = "engenius,ens620ext";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* Disable the broken restart as a workaround for the buggy
|
||||
* 3.0.0/3.0.1 U-boots that ship with the device.
|
||||
* Note: The watchdog is now used to restart this device.
|
||||
*/
|
||||
restart@4ab000 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
buttons {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power: power {
|
||||
label = "ens620ext:amber:power";
|
||||
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan1 {
|
||||
label = "ens620ext:green:lan1";
|
||||
gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan2 {
|
||||
label = "ens620ext:green:lan2";
|
||||
gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wlan2G {
|
||||
label = "ens620ext:green:wlan2G";
|
||||
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan5G {
|
||||
label = "ens620ext:green:wlan5G";
|
||||
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
mux {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_spi1 { /* BLSP1 QUP1 */
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@60000 {
|
||||
label = "QSEE";
|
||||
reg = <0x00060000 0x00060000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@c0000 {
|
||||
label = "CDT";
|
||||
reg = <0x000c0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@d0000 {
|
||||
label = "DDRPARAMS";
|
||||
reg = <0x000d0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@e0000 {
|
||||
label = "APPSBLENV"; /* uboot env*/
|
||||
reg = <0x000e0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@f0000 {
|
||||
label = "APPSBL"; /* uboot */
|
||||
reg = <0x000f0000 0x00090000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "ART";
|
||||
reg = <0x00180000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@190000 {
|
||||
compatible = "denx,fit";
|
||||
label = "firmware";
|
||||
reg = <0x00190000 0x14d0000>;
|
||||
};
|
||||
|
||||
partition@1660000 {
|
||||
label = "failsafe";
|
||||
reg = <0x01660000 0x008f0000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1f50000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x01f50000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1f60000 {
|
||||
label = "userconfig";
|
||||
reg = <0x01f60000 0x000a0000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
|
||||
};
|
||||
@ -0,0 +1,33 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2018, David Bauer <mail@david-bauer.net>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4018-ex61x0v2.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Netgear EX6100v2";
|
||||
compatible = "netgear,ex6100v2", "qcom,ipq4019";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
|
||||
};
|
||||
@ -0,0 +1,33 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2018, David Bauer <mail@david-bauer.net>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4018-ex61x0v2.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Netgear EX6150v2";
|
||||
compatible = "netgear,ex6150v2", "qcom,ipq4019";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
|
||||
};
|
||||
@ -0,0 +1,308 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2018, David Bauer <mail@david-bauer.net>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "Netgear EX61X0v2";
|
||||
compatible = "netgear,ex61x0v2", "qcom,ipq4019";
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
qcom,num_gmac = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &power_amber;
|
||||
led-failsafe = &power_amber;
|
||||
led-running = &power_green;
|
||||
led-upgrade = &power_amber;
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
led_spi {
|
||||
compatible = "spi-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpio-sck = <&tlmm 5 GPIO_ACTIVE_HIGH>;
|
||||
gpio-mosi = <&tlmm 4 GPIO_ACTIVE_HIGH>;
|
||||
num-chipselects = <0>;
|
||||
|
||||
led_gpio: led_gpio@0 {
|
||||
compatible = "fairchild,74hc595";
|
||||
reg = <0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
registers-number = <1>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power_amber: power_amber {
|
||||
label = "ex61x0v2:amber:power";
|
||||
gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
power_green: power_green {
|
||||
label = "ex61x0v2:green:power";
|
||||
gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
right {
|
||||
label = "ex61x0v2:blue:right";
|
||||
gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
left {
|
||||
label = "ex61x0v2:blue:left";
|
||||
gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
client_green {
|
||||
label = "ex61x0v2:green:client";
|
||||
gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
client_red {
|
||||
label = "ex61x0v2:red:client";
|
||||
gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
router_green {
|
||||
label = "ex61x0v2:green:router";
|
||||
gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
router_red {
|
||||
label = "ex61x0v2:red:router";
|
||||
gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "ex61x0v2:green:wps";
|
||||
gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
pin {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pin_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
mx25l12805d@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition0@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition1@40000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition2@60000 {
|
||||
label = "QSEE";
|
||||
reg = <0x00060000 0x00060000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition3@c0000 {
|
||||
label = "CDT";
|
||||
reg = <0x000c0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition4@d0000 {
|
||||
label = "DDRPARAMS";
|
||||
reg = <0x000d0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition5@E0000 {
|
||||
label = "APPSBLENV";
|
||||
reg = <0x000e0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition6@F0000 {
|
||||
label = "APPSBL";
|
||||
reg = <0x000f0000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition7@170000 {
|
||||
label = "ART";
|
||||
reg = <0x00170000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition8@180000 {
|
||||
label = "config";
|
||||
reg = <0x00180000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition9@190000 {
|
||||
label = "pot";
|
||||
reg = <0x00190000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition10@1a0000 {
|
||||
label = "dnidata";
|
||||
reg = <0x001a0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition11@1b0000 {
|
||||
compatible = "denx,fit";
|
||||
label = "firmware";
|
||||
reg = <0x001b0000 0x00e10000>;
|
||||
};
|
||||
|
||||
partition12@fc0000 {
|
||||
label = "language";
|
||||
reg = <0x00fc0000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -0,0 +1,301 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "AVM FRITZ!Box 4040";
|
||||
compatible = "avm,fritzbox-4040", "qcom,ipq4019";
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &flash;
|
||||
led-running = &power;
|
||||
led-upgrade = &flash;
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2@60f8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
qca8075: ess-switch@c000000 {
|
||||
status = "okay";
|
||||
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
|
||||
enable-usb-power {
|
||||
gpio-hog;
|
||||
line-name = "enable USB3 power";
|
||||
gpios = <7 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
wlan {
|
||||
label = "wlan";
|
||||
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
switch-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
wlan {
|
||||
label = "fritz4040:green:wlan";
|
||||
gpios = <&qca8075 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
panic: info_red {
|
||||
label = "fritz4040:red:info";
|
||||
gpios = <&qca8075 3 GPIO_ACTIVE_HIGH>;
|
||||
panic-indicator;
|
||||
};
|
||||
|
||||
wan {
|
||||
label = "fritz4040:green:wan";
|
||||
gpios = <&qca8075 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power: power {
|
||||
label = "fritz4040:green:power";
|
||||
gpios = <&qca8075 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
lan {
|
||||
label = "fritz4040:green:lan";
|
||||
gpios = <&qca8075 13 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
flash: info_amber {
|
||||
label = "fritz4040:amber:info";
|
||||
gpios = <&qca8075 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
mux {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 { /* BLSP1 QUP1 */
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
status = "okay";
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition0@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition1@40000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition2@60000 {
|
||||
label = "QSEE";
|
||||
reg = <0x00060000 0x00060000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition3@c0000 {
|
||||
label = "CDT";
|
||||
reg = <0x000c0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition4@d0000 {
|
||||
label = "DDRPARAMS";
|
||||
reg = <0x000d0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition5@e0000 {
|
||||
label = "APPSBLENV"; /* uboot env - empty */
|
||||
reg = <0x000e0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition6@f0000 {
|
||||
label = "urlader"; /* APPSBL */
|
||||
reg = <0x000f0000 0x0002dc000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition7@11dc00 {
|
||||
/* make a backup of this partition! */
|
||||
label = "urlader_config";
|
||||
reg = <0x0011dc00 0x00002400>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition8@120000 {
|
||||
label = "tffs1";
|
||||
reg = <0x00120000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition9@1a0000 {
|
||||
label = "tffs2";
|
||||
reg = <0x001a0000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition10@220000 {
|
||||
label = "uboot";
|
||||
reg = <0x00220000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition11@2A0000 {
|
||||
compatible = "denx,fit";
|
||||
label = "firmware";
|
||||
reg = <0x002a0000 0x01c60000>;
|
||||
};
|
||||
|
||||
partition12@1f00000 {
|
||||
label = "jffs2";
|
||||
reg = <0x01f00000 0x00100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
|
||||
};
|
||||
@ -0,0 +1,276 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "8devices Jalapeno";
|
||||
compatible = "8dev,jalapeno", "qcom,ipq4019";
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
counter@4a1000 {
|
||||
compatible = "qcom,qca-gcnt";
|
||||
reg = <0x4a1000 0x4>;
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
/* select hostmode */
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2: usb2@60f8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3: usb3@8af8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
switch_lan_bmp = <0x10>; /* lan port bitmap */
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio_pinmux {
|
||||
pinmux_1 {
|
||||
pins = "gpio53";
|
||||
function = "mdio";
|
||||
};
|
||||
|
||||
pinmux_2 {
|
||||
pins = "gpio52";
|
||||
function = "mdc";
|
||||
};
|
||||
|
||||
pinconf {
|
||||
pins = "gpio52", "gpio53";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
pin {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pin_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54", "gpio59";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition0@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition1@40000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition2@60000 {
|
||||
label = "QSEE";
|
||||
reg = <0x00060000 0x00060000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition3@c0000 {
|
||||
label = "CDT";
|
||||
reg = <0x000c0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition4@d0000 {
|
||||
label = "DDRPARAMS";
|
||||
reg = <0x000d0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition5@e0000 {
|
||||
label = "APPSBLENV"; /* uboot env*/
|
||||
reg = <0x000e0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition5@f0000 {
|
||||
label = "APPSBL"; /* uboot */
|
||||
reg = <0x000f0000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition5@170000 {
|
||||
label = "ART";
|
||||
reg = <0x00170000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mt29f@1 {
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "spinand,mt29f", "w25n01gv";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <24000000>;
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition0@0 {
|
||||
label = "ubi";
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
qcom,poll_required = <1>;
|
||||
qcom,poll_required_dynamic = <1>;
|
||||
qcom,phy_mdio_addr = <3>;
|
||||
vlan_tag = <1 0x10>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
qcom,poll_required = <1>;
|
||||
qcom,poll_required_dynamic = <1>;
|
||||
qcom,phy_mdio_addr = <4>;
|
||||
vlan_tag = <2 0x20>;
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "8devices-Jalapeno";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "8devices-Jalapeno";
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
@ -0,0 +1,350 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "ZyXEL NBG6617";
|
||||
compatible = "zyxel,nbg6617", "qcom,ipq4019";
|
||||
|
||||
chosen {
|
||||
/*
|
||||
* the vendor u-boot adds root and mtdparts cmdline parameters
|
||||
* which we don't want... but we have to overwrite them or else
|
||||
* the kernel will take them at face value.
|
||||
*/
|
||||
bootargs-append = " mtdparts= root=31:13";
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2@60f8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@6000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb2_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@8a00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb3_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
|
||||
usb3_port2: port@2 {
|
||||
reg = <2>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
wlan {
|
||||
label = "wlan";
|
||||
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
linux,input-type = <EV_SW>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power: power {
|
||||
label = "nbg6617:green:power";
|
||||
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb {
|
||||
label = "nbg6617:green:usb";
|
||||
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
|
||||
trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
|
||||
linux,default-trigger = "usbport";
|
||||
};
|
||||
|
||||
wlan2G {
|
||||
label = "nbg6617:green:wlan2G";
|
||||
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan5G {
|
||||
label = "nbg6617:green:wlan5G";
|
||||
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "nbg6617:green:wps";
|
||||
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
mux {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pinmux {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1", "gpio3", "gpio5", "gpio58";
|
||||
drive-strength = <0x8>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_spi1 { /* BLSP1 QUP1 */
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
mx25l25635f@0 {
|
||||
compatible = "mx25l25635f", "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
status = "okay";
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition0@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition1@40000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition2@60000 {
|
||||
label = "QSEE";
|
||||
reg = <0x00060000 0x00060000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition3@c0000 {
|
||||
label = "CDT";
|
||||
reg = <0x000c0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition4@d0000 {
|
||||
label = "DDRPARAMS";
|
||||
reg = <0x000d0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition5@e0000 {
|
||||
label = "APPSBL"; /* u-boot */
|
||||
reg = <0x000e0000 0x00080000>;
|
||||
/* U-Boot Standalone App "zloader" is located at 0x64000 */
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition6@160000 {
|
||||
label = "APPSBLENV"; /* u-boot env */
|
||||
reg = <0x00160000 0x00010000>;
|
||||
};
|
||||
|
||||
partition7@170000 {
|
||||
/* make a backup of this partition! */
|
||||
label = "ART";
|
||||
reg = <0x00170000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition8@180000 {
|
||||
label = "kernel";
|
||||
reg = <0x00180000 0x00400000>;
|
||||
};
|
||||
|
||||
partition9@580000 {
|
||||
label = "dualflag";
|
||||
reg = <0x00580000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition10@590000 {
|
||||
label = "header";
|
||||
reg = <0x00590000 0x00010000>;
|
||||
};
|
||||
|
||||
partition11@5a0000 {
|
||||
label = "romd";
|
||||
reg = <0x005a0000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition12@6a0000 {
|
||||
label = "not_root_data";
|
||||
/*
|
||||
* for some strange reason, someone at ZyXEL
|
||||
* had the "great" idea to put the rootfs_data
|
||||
* in front of rootfs... Don't do that!
|
||||
* As a result this one, full MebiByte remains
|
||||
* unused.
|
||||
*/
|
||||
reg = <0x006a0000 0x00100000>;
|
||||
};
|
||||
|
||||
partition13@7a0000 {
|
||||
label = "rootfs";
|
||||
reg = <0x007a0000 0x01860000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
@ -0,0 +1,304 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "ASUS RT-AC58U / RT-AC1300UHP";
|
||||
compatible = "asus,rt-ac58u", "qcom,ipq4019";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &led_power;
|
||||
led-failsafe = &led_power;
|
||||
led-running = &led_power;
|
||||
led-upgrade = &led_power;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs-append = " ubi.mtd=UBI_DEV";
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@8a00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb3_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
|
||||
usb3_port2: port@2 {
|
||||
reg = <2>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wifi@a000000 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "RT-AC58U";
|
||||
};
|
||||
|
||||
wifi@a800000 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "RT-AC58U";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_power: status {
|
||||
label = "rt-ac58u:blue:status";
|
||||
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan {
|
||||
label = "rt-ac58u:blue:wan";
|
||||
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan2G {
|
||||
label = "rt-ac58u:blue:wlan2G";
|
||||
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "phy0tpt";
|
||||
};
|
||||
|
||||
wlan5G {
|
||||
label = "rt-ac58u:blue:wlan5G";
|
||||
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "phy1tpt";
|
||||
};
|
||||
|
||||
usb {
|
||||
label = "rt-ac58u:blue:usb";
|
||||
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
|
||||
trigger-sources = <&usb3_port1>, <&usb3_port2>;
|
||||
linux,default-trigger = "usbport";
|
||||
};
|
||||
|
||||
lan {
|
||||
label = "rt-ac58u:blue:lan";
|
||||
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
mux {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54", "gpio59";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_spi1 { /* BLSP1 QUP1 */
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
|
||||
<&tlmm 59 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
/*
|
||||
* U-boot looks for "n25q128a11" node,
|
||||
* if we don't have it, it will spit out the following warning:
|
||||
* "ipq: fdt fixup unable to find compatible node".
|
||||
*/
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
linux,modalias = "m25p80", "mx25l1606e", "n25q128a11";
|
||||
spi-max-frequency = <30000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition0@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition1@40000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
read-only;
|
||||
};
|
||||
partition2@60000 {
|
||||
label = "QSEE";
|
||||
reg = <0x00060000 0x00060000>;
|
||||
read-only;
|
||||
};
|
||||
partition3@c0000 {
|
||||
label = "CDT";
|
||||
reg = <0x000c0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
partition4@d0000 {
|
||||
label = "DDRPARAMS";
|
||||
reg = <0x000d0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
partition5@e0000 {
|
||||
label = "APPSBLENV"; /* uboot env*/
|
||||
reg = <0x000e0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
partition5@f0000 {
|
||||
label = "APPSBL"; /* uboot */
|
||||
reg = <0x000f0000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
partition5@170000 {
|
||||
label = "ART";
|
||||
reg = <0x00170000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
/* 0x00180000 - 0x00200000 unused */
|
||||
};
|
||||
};
|
||||
|
||||
flash@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "spinand,mt29f";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <30000000>;
|
||||
|
||||
/*
|
||||
* U-boot looks for "spinand,mt29f" node,
|
||||
* if we don't have it, it will spit out the following warning:
|
||||
* "ipq: fdt fixup unable to find compatible node".
|
||||
*/
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "ubi";
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
@ -0,0 +1,262 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2018, David Bauer <mail@david-bauer.net>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "ZyXEL WRE6606";
|
||||
compatible = "zyxel,wre6606", "qcom,ipq4019";
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs-append = " mtdparts=";
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
qcom,num_gmac = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
wps {
|
||||
label = "wre6606:green:wps";
|
||||
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan5g_green {
|
||||
label = "wre6606:green:wlan5g";
|
||||
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power: power {
|
||||
label = "wre6606:green:power";
|
||||
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan5g_red {
|
||||
label = "wre6606:red:wlan5g";
|
||||
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan2g_red {
|
||||
label = "wre6606:red:wlan2g";
|
||||
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan2g_green {
|
||||
label = "wre6606:green:wlan2g";
|
||||
gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
pin {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pin_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
mx25l12805d@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition0@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition1@40000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition2@60000 {
|
||||
label = "QSEE";
|
||||
reg = <0x00060000 0x00060000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition3@c0000 {
|
||||
label = "CDT";
|
||||
reg = <0x000c0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition4@d0000 {
|
||||
label = "DDRPARAMS";
|
||||
reg = <0x000d0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition5@E0000 {
|
||||
label = "APPSBLENV";
|
||||
reg = <0x000e0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition6@F0000 {
|
||||
label = "APPSBL";
|
||||
reg = <0x000f0000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition7@170000 {
|
||||
label = "ART";
|
||||
reg = <0x00170000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition8@180000 {
|
||||
compatible = "denx,fit";
|
||||
label = "firmware";
|
||||
reg = <0x00180000 0x00ce0000>;
|
||||
};
|
||||
|
||||
partition9@e60000 {
|
||||
label = "manufacture";
|
||||
reg = <0x00e60000 0x00050000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition10@eb0000 {
|
||||
label = "storage";
|
||||
reg = <0x00eb0000 0x00150000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
|
||||
};
|
||||
@ -0,0 +1,236 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "OpenMesh A62";
|
||||
compatible = "openmesh,a62", "qcom,ipq4019";
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
/* select hostmode */
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2: usb2@60f8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
switch_lan_bmp = <0x10>;
|
||||
switch_wan_bmp = <0x20>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
red {
|
||||
label = "a62:red:status";
|
||||
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
power: green {
|
||||
label = "a62:green:status";
|
||||
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
blue {
|
||||
label = "a62:blue:status";
|
||||
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "linux,wdt-gpio";
|
||||
gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
|
||||
hw_algo = "toggle";
|
||||
/* hw_margin_ms is actually 300s but driver limits it to 60s */
|
||||
hw_margin_ms = <60000>;
|
||||
always-running;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
pin {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio13", "gpio14", "gpio15";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pin_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio12";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
enable-usb-power {
|
||||
gpio-hog;
|
||||
gpios = <58 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "enable USB2 power";
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
/* partitions are passed via bootloader */
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
vlan_tag = <1 0x31>;
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
|
||||
|
||||
bridge@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
wifi2: wifi@1,0 {
|
||||
compatible = "qcom,ath10k";
|
||||
status = "okay";
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
qcom,ath10k-calibration-variant = "OM-A62";
|
||||
ieee80211-freq-limit = <5170000 5350000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "OM-A62";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "OM-A62";
|
||||
ieee80211-freq-limit = <5470000 5875000>;
|
||||
};
|
||||
@ -0,0 +1,21 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019-ap.dk04.1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK04.1-C1";
|
||||
};
|
||||
@ -0,0 +1,180 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
|
||||
compatible = "qcom,ipq4019";
|
||||
|
||||
soc {
|
||||
pinctrl@1000000 {
|
||||
serial_0_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
serial_1_pins: serial1_pinmux {
|
||||
mux {
|
||||
pins = "gpio8", "gpio9";
|
||||
function = "blsp_uart1";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
pinmux {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio13", "gpio14", "gpio15";
|
||||
};
|
||||
|
||||
pinmux_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio12";
|
||||
};
|
||||
|
||||
pinconf {
|
||||
pins = "gpio13", "gpio14", "gpio15";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinconf_cs {
|
||||
pins = "gpio12";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
i2c_0_pins: i2c_0_pinmux {
|
||||
pinmux {
|
||||
function = "blsp_i2c0";
|
||||
pins = "gpio10", "gpio11";
|
||||
};
|
||||
|
||||
pinconf {
|
||||
pins = "gpio10", "gpio11";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
pullups {
|
||||
pins = "gpio52", "gpio53", "gpio58",
|
||||
"gpio59";
|
||||
function = "qpic";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pulldowns {
|
||||
pins = "gpio54", "gpio55", "gpio56",
|
||||
"gpio57", "gpio60", "gpio61",
|
||||
"gpio62", "gpio63", "gpio64",
|
||||
"gpio65", "gpio66", "gpio67",
|
||||
"gpio68", "gpio69";
|
||||
function = "qpic";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
blsp_dma: dma@7884000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@78b5000 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
mx25l25635e@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
compatible = "mx25l25635e";
|
||||
spi-max-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@78b7000 { /* BLSP1 QUP2 */
|
||||
pinctrl-0 = <&i2c_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@78af000 {
|
||||
pinctrl-0 = <&serial_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@78b0000 {
|
||||
pinctrl-0 = <&serial_1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3_ss_phy: ssphy@9a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3_hs_phy: hsphy@a6000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3: usb3@8af8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2_hs_phy: hsphy@a8000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2: usb2@60f8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
cryptobam: dma@8e04000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
qpic_bam: dma@7984000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
nand: qpic-nand@79b0000 {
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,300 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "MobiPromo CM520-79F";
|
||||
compatible = "mobipromo,cm520-79f";
|
||||
|
||||
aliases {
|
||||
led-boot = &led_sys;
|
||||
led-failsafe = &led_sys;
|
||||
led-running = &led_sys;
|
||||
led-upgrade = &led_sys;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs-append = " ubi.block=0,1 root=/dev/ubiblock0_1";
|
||||
};
|
||||
|
||||
soc {
|
||||
rng@22000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
|
||||
reset-delay-us = <1000>;
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2@60f8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@6000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb2_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@8a00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb3_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
|
||||
usb3_port2: port@2 {
|
||||
reg = <2>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
led_spi {
|
||||
compatible = "spi-gpio";
|
||||
#address-cells = <1>;
|
||||
ranges;
|
||||
|
||||
sck-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
|
||||
mosi-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
|
||||
num-chipselects = <0>;
|
||||
|
||||
led_gpio: led_gpio@0 {
|
||||
compatible = "fairchild,74hc595";
|
||||
reg = <0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
registers-number = <1>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_usb: usb {
|
||||
label = "cm520-79f:blue:usb";
|
||||
gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "usbport";
|
||||
trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
|
||||
};
|
||||
|
||||
led_sys: can {
|
||||
label = "cm520-79f:blue:can";
|
||||
gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan {
|
||||
label = "cm520-79f:blue:wan";
|
||||
gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan1 {
|
||||
label = "cm520-79f:blue:lan1";
|
||||
gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan2 {
|
||||
label = "cm520-79f:blue:lan2";
|
||||
gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wlan2g {
|
||||
label = "cm520-79f:blue:wlan2g";
|
||||
gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "phy0tpt";
|
||||
};
|
||||
|
||||
wlan5g {
|
||||
label = "cm520-79f:blue:wlan5g";
|
||||
gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "phy1tpt";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
mtd-mac-address = <&art 0x1006>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
mtd-mac-address = <&art 0x5006>;
|
||||
};
|
||||
|
||||
&nand {
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "Bootloader";
|
||||
reg = <0x0 0xb00000>;
|
||||
};
|
||||
|
||||
art: partition@b00000 {
|
||||
label = "ART";
|
||||
reg = <0xb00000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@b80000 {
|
||||
label = "rootfs";
|
||||
reg = <0xb80000 0x7480000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio_pinmux {
|
||||
mux_1 {
|
||||
pins = "gpio6";
|
||||
function = "mdio";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux_2 {
|
||||
pins = "gpio7";
|
||||
function = "mdc";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
pullups {
|
||||
pins = "gpio52", "gpio53", "gpio58",
|
||||
"gpio59";
|
||||
function = "qpic";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pulldowns {
|
||||
pins = "gpio54", "gpio55", "gpio56",
|
||||
"gpio57", "gpio60", "gpio61",
|
||||
"gpio62", "gpio63", "gpio64",
|
||||
"gpio65", "gpio66", "gpio67",
|
||||
"gpio68", "gpio69";
|
||||
function = "qpic";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "CM520-79F";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "CM520-79F";
|
||||
};
|
||||
@ -0,0 +1,87 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
*
|
||||
* Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019-e2600ac.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Qxwlan E2600AC c1";
|
||||
compatible = "qxwlan,e2600ac-c1", "qcom,ipq4019";
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
|
||||
|
||||
flash@0 {
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "0:SBL1";
|
||||
reg = <0x0 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "0:MIBIB";
|
||||
reg = <0x40000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@60000 {
|
||||
label = "0:QSEE";
|
||||
reg = <0x60000 0x60000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@c0000 {
|
||||
label = "0:CDT";
|
||||
reg = <0xc0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@d0000 {
|
||||
label = "0:DDRPARAMS";
|
||||
reg = <0xd0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@e0000 {
|
||||
label = "0:APPSBLENV";
|
||||
reg = <0xe0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@f0000 {
|
||||
label = "0:APPSBL";
|
||||
reg = <0xf0000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@170000 {
|
||||
label = "0:ART";
|
||||
reg = <0x170000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
compatible = "denx,fit";
|
||||
label = "firmware";
|
||||
reg = <0x180000 0x1e80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,120 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
*
|
||||
* Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019-e2600ac.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Qxwlan E2600AC c2";
|
||||
compatible = "qxwlan,e2600ac-c2", "qcom,ipq4019";
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
|
||||
|
||||
flash@0 {
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "0:SBL1";
|
||||
reg = <0x0 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "0:MIBIB";
|
||||
reg = <0x40000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@60000 {
|
||||
label = "0:QSEE";
|
||||
reg = <0x60000 0x60000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@c0000 {
|
||||
label = "0:CDT";
|
||||
reg = <0xc0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@d0000 {
|
||||
label = "0:DDRPARAMS";
|
||||
reg = <0xd0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@e0000 {
|
||||
label = "0:APPSBLENV";
|
||||
reg = <0xe0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@f0000 {
|
||||
label = "0:APPSBL";
|
||||
reg = <0xf0000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@170000 {
|
||||
label = "0:ART";
|
||||
reg = <0x170000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nand {
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "ubi";
|
||||
reg = <0x00000000 0x04000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
nand_pins: nand-pins {
|
||||
pullups {
|
||||
pins = "gpio53", "gpio58", "gpio59";
|
||||
function = "qpic";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pulldowns {
|
||||
pins = "gpio54", "gpio55", "gpio56",
|
||||
"gpio57", "gpio60", "gpio61",
|
||||
"gpio62", "gpio63", "gpio64",
|
||||
"gpio65", "gpio66", "gpio67",
|
||||
"gpio68", "gpio69";
|
||||
function = "qpic";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,264 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
*
|
||||
* Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
|
||||
model = "Qxwlan E2600AC";
|
||||
compatible = "qcom,ipq4019";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256MB */
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
/* select hostmode */
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2: usb2@60f8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@6000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb2_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@78af000 {
|
||||
pinctrl-0 = <&serial_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@78b0000 {
|
||||
pinctrl-0 = <&serial_1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@78b7000 { /* BLSP1 QUP2 */
|
||||
pinctrl-0 = <&i2c_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3: usb3@8af8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@8a00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb3_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
|
||||
usb3_port2: port@2 {
|
||||
reg = <2>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led1 {
|
||||
label = "e2600ac:green:wlan0";
|
||||
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led2 {
|
||||
label = "e2600ac:green:wlan1";
|
||||
gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led3 {
|
||||
label = "e2600ac:green:usb";
|
||||
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
|
||||
trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
|
||||
linux,default-trigger = "usbport";
|
||||
};
|
||||
|
||||
led4 {
|
||||
label = "e2600ac:green:ctrl1";
|
||||
gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led5 {
|
||||
label = "e2600ac:green:ctrl2";
|
||||
gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led6 {
|
||||
label = "e2600ac:green:ctrl3";
|
||||
gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
i2c_0_pins: i2c-0-pinmux {
|
||||
mux {
|
||||
pins = "gpio20", "gpio21";
|
||||
function = "blsp_i2c0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
mdio_pins: mdio_pinmux {
|
||||
mux_1 {
|
||||
pins = "gpio6";
|
||||
function = "mdio";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux_2 {
|
||||
pins = "gpio7";
|
||||
function = "mdc";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
serial_0_pins: serial0-pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
serial_1_pins: serial1_pinmux {
|
||||
mux {
|
||||
pins = "gpio8", "gpio9";
|
||||
function = "blsp_uart1";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
pinmux {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio13", "gpio14", "gpio15";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinmux_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio12";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "Qxwlan-E2600AC";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "Qxwlan-E2600AC";
|
||||
};
|
||||
@ -0,0 +1,391 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
/*
|
||||
* Device Tree Source for Linksys EA8300 (Dallas)
|
||||
*
|
||||
* Copyright (C) 2019 Jeff Kletsky
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "Linksys EA8300 (Dallas)";
|
||||
compatible = "linksys,ea8300", "qcom,ipq4019";
|
||||
|
||||
aliases {
|
||||
led-boot = &led_wps_amber;
|
||||
led-failsafe = &led_wps;
|
||||
led-running = &led_linksys;
|
||||
led-upgrade = &led_world;
|
||||
serial0 = &blsp1_uart1;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
// Retain node names from running OEM on EA8300
|
||||
|
||||
// Front panel LEDs, top to bottom
|
||||
|
||||
led_plug: diag {
|
||||
label = "ea8300:amber:plug";
|
||||
gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_world: internet {
|
||||
label = "ea8300:amber:world";
|
||||
gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_wps: wps {
|
||||
label = "ea8300:white:wps";
|
||||
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_wps_amber: wps_amber {
|
||||
label = "ea8300:amber:wps";
|
||||
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
|
||||
panic-indicator;
|
||||
};
|
||||
|
||||
led_linksys: pwr {
|
||||
label = "ea8300:white:linksys";
|
||||
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
// On back panel, above USB socket
|
||||
|
||||
led_usb: usb {
|
||||
label = "ea8300:green:usb";
|
||||
gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
|
||||
trigger-sources = <&usb3_port1>, <&usb3_port2>,
|
||||
<&usb2_port1>;
|
||||
linux,default-trigger = "usbport";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
button@0 {
|
||||
label = "reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
button@1 {
|
||||
label = "wps";
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
//
|
||||
// OEM U-Boot provides either
|
||||
// init=/sbin/init rootfstype=ubifs ubi.mtd=11,2048 \
|
||||
// root=ubi0:ubifs rootwait rw
|
||||
// or the same with ubi.mtd=13,2048
|
||||
//
|
||||
|
||||
chosen {
|
||||
bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
rng@22000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2@60f8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@6000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb2_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@8a00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb3_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
|
||||
usb3_port2: port@2 {
|
||||
reg = <2>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&serial_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "sbl1";
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "mibib";
|
||||
reg = <0x100000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
label = "qsee";
|
||||
reg = <0x200000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@300000 {
|
||||
label = "cdt";
|
||||
reg = <0x300000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@380000 {
|
||||
label = "appsblenv";
|
||||
reg = <0x380000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "ART";
|
||||
reg = <0x400000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@480000 {
|
||||
label = "appsbl";
|
||||
reg = <0x480000 0x200000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@680000 {
|
||||
label = "u_env";
|
||||
reg = <0x680000 0x80000>;
|
||||
// writable -- U-Boot environment
|
||||
};
|
||||
|
||||
partition@700000 {
|
||||
label = "s_env";
|
||||
reg = <0x700000 0x40000>;
|
||||
// writable -- Boot counter records
|
||||
};
|
||||
|
||||
partition@740000 {
|
||||
label = "devinfo";
|
||||
reg = <0x740000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@780000 {
|
||||
label = "kernel";
|
||||
reg = <0x780000 0x5800000>;
|
||||
};
|
||||
|
||||
partition@a80000 {
|
||||
label = "rootfs";
|
||||
reg = <0xa80000 0x5500000>;
|
||||
};
|
||||
|
||||
partition@5f80000 {
|
||||
label = "alt_kernel";
|
||||
reg = <0x5f80000 0x5800000>;
|
||||
};
|
||||
|
||||
partition@6280000 {
|
||||
label = "alt_rootfs";
|
||||
reg = <0x6280000 0x5500000>;
|
||||
};
|
||||
|
||||
partition@b780000 {
|
||||
label = "sysdiag";
|
||||
reg = <0xb780000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@b880000 {
|
||||
label = "syscfg";
|
||||
reg = <0xb880000 0x4680000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
|
||||
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
|
||||
|
||||
bridge@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
wifi2: wifi@1,0 {
|
||||
compatible = "qcom,ath10k";
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_0_pins: serial0-pinmux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
pullups {
|
||||
pins = "gpio53", "gpio58", "gpio59";
|
||||
function = "qpic";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
// gpio61 controls led_usb
|
||||
|
||||
pulldowns {
|
||||
pins = "gpio55", "gpio56", "gpio57",
|
||||
"gpio60", "gpio62", "gpio63",
|
||||
"gpio64", "gpio65", "gpio66",
|
||||
"gpio67", "gpio68", "gpio69";
|
||||
function = "qpic";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
ieee80211-freq-limit = <5170000 5330000>;
|
||||
qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
|
||||
};
|
||||
|
||||
&wifi2 {
|
||||
status = "okay";
|
||||
ieee80211-freq-limit = <5490000 5835000>;
|
||||
qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
|
||||
};
|
||||
@ -0,0 +1,299 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "AVM FRITZ!Box 7530";
|
||||
compatible = "avm,fritzbox-7530";
|
||||
|
||||
aliases {
|
||||
led-boot = &power_green;
|
||||
led-failsafe = &info_red;
|
||||
led-running = &power_green;
|
||||
led-upgrade = &info_green;
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
qcom,num_gmac = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
wlan {
|
||||
label = "wlan";
|
||||
gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
|
||||
dect {
|
||||
label = "dect";
|
||||
gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_PHONE>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
info_red: info_red {
|
||||
label = "fritzbox-7530:red:info";
|
||||
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
info_green: info {
|
||||
label = "fritzbox-7530:green:info";
|
||||
gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wlan {
|
||||
label = "fritzbox-7530:green:wlan";
|
||||
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
fon {
|
||||
label = "fritzbox-7530:green:fon";
|
||||
gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
power_green: power {
|
||||
label = "fritzbox-7530:green:power";
|
||||
gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "fritzbox-7530:green:wps";
|
||||
gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_0_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
pullups {
|
||||
pins = "gpio53", "gpio58", "gpio59";
|
||||
function = "qpic";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pulldowns {
|
||||
pins = "gpio54", "gpio55", "gpio56",
|
||||
"gpio57", "gpio60", "gpio61",
|
||||
"gpio62", "gpio63", "gpio64",
|
||||
"gpio65", "gpio66", "gpio67",
|
||||
"gpio68", "gpio69";
|
||||
function = "qpic";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
usb-power {
|
||||
line-name = "enable USB3 power";
|
||||
gpios = <49 GPIO_ACTIVE_HIGH>;
|
||||
gpio-hog;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&nand {
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x000000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x080000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "QSEE";
|
||||
reg = <0x100000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "CDT";
|
||||
reg = <0x180000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1c0000 {
|
||||
label = "QSEE_B";
|
||||
reg = <0x1c0000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@240000 {
|
||||
label = "urlader0";
|
||||
reg = <0x240000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "urlader1";
|
||||
reg = <0x280000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@2c0000 {
|
||||
label = "nand-tffs";
|
||||
reg = <0x2c0000 0x840000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@b00000 {
|
||||
/* 'kernel1' in AVM firmware */
|
||||
label = "uboot0";
|
||||
reg = <0xb00000 0x400000>;
|
||||
};
|
||||
|
||||
partition@f00000 {
|
||||
/* 'kernel2' in AVM firmware */
|
||||
label = "uboot1";
|
||||
reg = <0xf00000 0x400000>;
|
||||
};
|
||||
|
||||
partition@1300000 {
|
||||
label = "ubi";
|
||||
reg = <0x1300000 0x6d00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
|
||||
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
|
||||
|
||||
bridge@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
dsl@1,0 {
|
||||
compatible = "intel,vrx518";
|
||||
status = "okay";
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,263 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "AVM FRITZ!Repeater 1200";
|
||||
compatible = "avm,fritzrepeater-1200";
|
||||
|
||||
aliases {
|
||||
led-boot = &power_green;
|
||||
led-failsafe = &power_red;
|
||||
led-running = &power_green;
|
||||
led-upgrade = &power_red;
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
|
||||
switch_lan_bmp = <0x0>; /* lan port bitmap */
|
||||
switch_wan_bmp = <0x10>; /* wan port bitmap */
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-rxid";
|
||||
qcom,num_gmac = <1>;
|
||||
qcom,single-phy;
|
||||
};
|
||||
};
|
||||
|
||||
key {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
wps {
|
||||
label = "WPS button";
|
||||
gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power_red: power_red {
|
||||
label = "fritzwlan-1200:red:power";
|
||||
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
power_green: power_green {
|
||||
label = "fritzwlan-1200:green:power";
|
||||
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power_yellow {
|
||||
label = "fritzwlan-1200:yellow:power";
|
||||
gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_0_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
pullups {
|
||||
pins = "gpio53", "gpio58", "gpio59";
|
||||
function = "qpic";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pulldowns {
|
||||
pins = "gpio54", "gpio55", "gpio56",
|
||||
"gpio57", "gpio60", "gpio61",
|
||||
"gpio62", "gpio63", "gpio64",
|
||||
"gpio65", "gpio66", "gpio67",
|
||||
"gpio68", "gpio69";
|
||||
function = "qpic";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
mdio_pins: mdio_pinmux {
|
||||
mux_1 {
|
||||
pins = "gpio6";
|
||||
function = "mdio";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux_2 {
|
||||
pins = "gpio7";
|
||||
function = "mdc";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
phy-reset {
|
||||
line-name = "PHY-reset";
|
||||
gpios = <19 GPIO_ACTIVE_HIGH>;
|
||||
gpio-hog;
|
||||
output-high;
|
||||
};
|
||||
|
||||
phy-reset-2 {
|
||||
line-name = "PHY-reset-2";
|
||||
gpios = <47 GPIO_ACTIVE_HIGH>;
|
||||
gpio-hog;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&nand {
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x0 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x80000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "QSEE";
|
||||
reg = <0x100000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "CDT";
|
||||
reg = <0x180000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1c0000 {
|
||||
label = "QSEE_B";
|
||||
reg = <0x1c0000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@240000 {
|
||||
label = "urlader0";
|
||||
reg = <0x240000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "urlader1";
|
||||
reg = <0x280000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@2c0000 {
|
||||
label = "nand-tffs";
|
||||
reg = <0x2c0000 0x840000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@b00000 {
|
||||
/* 'kernel1' in AVM firmware */
|
||||
label = "uboot0";
|
||||
reg = <0xb00000 0x400000>;
|
||||
};
|
||||
|
||||
partition@f00000 {
|
||||
/* 'kernel2' in AVM firmware */
|
||||
label = "uboot1";
|
||||
reg = <0xf00000 0x400000>;
|
||||
};
|
||||
|
||||
partition@1300000 {
|
||||
label = "ubi";
|
||||
reg = <0x1300000 0x6d00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
qcom,phy_mdio_addr = <0>;
|
||||
qcom,poll_required = <1>;
|
||||
vlan_tag = <0 0x20>;
|
||||
};
|
||||
@ -0,0 +1,260 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "AVM FRITZ!Repeater 3000";
|
||||
compatible = "avm,fritzrepeater-3000";
|
||||
|
||||
aliases {
|
||||
led-boot = &power_led;
|
||||
led-failsafe = &power_led;
|
||||
led-running = &power_led;
|
||||
led-upgrade = &power_led;
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
|
||||
switch_lan_bmp = <0x10>;
|
||||
switch_wan_bmp = <0x20>;
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
key {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
connect {
|
||||
label = "Connect";
|
||||
gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
connect_red {
|
||||
label = "fritzwlan-3000:red:connect";
|
||||
gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
connect_green {
|
||||
label = "fritzwlan-3000:green:connect";
|
||||
gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
connect_blue {
|
||||
label = "fritzwlan-3000:blue:connect";
|
||||
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
power_led: power {
|
||||
label = "fritzwlan-3000:green:power";
|
||||
gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_0_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
pullups {
|
||||
pins = "gpio53", "gpio58", "gpio59";
|
||||
function = "qpic";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pulldowns {
|
||||
pins = "gpio54", "gpio55", "gpio56",
|
||||
"gpio57", "gpio60", "gpio61",
|
||||
"gpio62", "gpio63", "gpio64",
|
||||
"gpio65", "gpio66", "gpio67",
|
||||
"gpio68", "gpio69";
|
||||
function = "qpic";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nand {
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x000000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x080000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "QSEE";
|
||||
reg = <0x100000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "CDT";
|
||||
reg = <0x180000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1c0000 {
|
||||
label = "QSEE_B";
|
||||
reg = <0x1c0000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@240000 {
|
||||
label = "urlader0";
|
||||
reg = <0x240000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "urlader1";
|
||||
reg = <0x280000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@2c0000 {
|
||||
label = "nand-tffs";
|
||||
reg = <0x2c0000 0x840000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@b00000 {
|
||||
/* 'kernel1' in AVM firmware */
|
||||
label = "uboot0";
|
||||
reg = <0xb00000 0x400000>;
|
||||
};
|
||||
|
||||
partition@f00000 {
|
||||
/* 'kernel2' in AVM firmware */
|
||||
label = "uboot1";
|
||||
reg = <0xf00000 0x400000>;
|
||||
};
|
||||
|
||||
partition@1300000 {
|
||||
label = "ubi";
|
||||
reg = <0x1300000 0x6d00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
/* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
|
||||
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
ieee80211-freq-limit = <5170000 5350000>;
|
||||
/* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
|
||||
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
|
||||
perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
|
||||
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
|
||||
|
||||
bridge@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
wifi@1,0 {
|
||||
/* QCA9984 */
|
||||
compatible = "qcom,ath10k";
|
||||
status = "okay";
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
ieee80211-freq-limit = <5470000 5875000>;
|
||||
/* Uses the reference BDF */
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,324 @@
|
||||
/*
|
||||
* Copyright (c) 2019 Hugo Yuan <hugolxq@gmail.com>
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "Hugo AC1200";
|
||||
compatible = "hugo,ac1200", "qcom,ipq4019";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256MB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
/* select hostmode */
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2@60f8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@6000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb2_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@78af000 {
|
||||
pinctrl-0 = <&serial_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@78b0000 {
|
||||
pinctrl-0 = <&serial_1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@78b7000 { /* BLSP1 QUP2 */
|
||||
pinctrl-0 = <&i2c_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3: usb3@8af8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@8a00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb3_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
|
||||
usb3_port2: port@2 {
|
||||
reg = <2>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led1 {
|
||||
label = "ac1200:green:ctrl1";
|
||||
gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led2 {
|
||||
label = "ac1200:red:ctrl2";
|
||||
gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
power: led3 {
|
||||
label = "ac1200:blue:ctrl3";
|
||||
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
|
||||
|
||||
flash@0 {
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "0:SBL1";
|
||||
reg = <0x0 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "0:MIBIB";
|
||||
reg = <0x40000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@60000 {
|
||||
label = "0:QSEE";
|
||||
reg = <0x60000 0x60000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@c0000 {
|
||||
label = "0:CDT";
|
||||
reg = <0xc0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@d0000 {
|
||||
label = "0:DDRPARAMS";
|
||||
reg = <0xd0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@e0000 {
|
||||
label = "0:APPSBLENV";
|
||||
reg = <0xe0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@f0000 {
|
||||
label = "0:APPSBL";
|
||||
reg = <0xf0000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@170000 {
|
||||
label = "0:ART";
|
||||
reg = <0x170000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
compatible = "denx,fit";
|
||||
label = "firmware";
|
||||
reg = <0x180000 0x1e80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
i2c_0_pins: i2c-0-pinmux {
|
||||
mux {
|
||||
pins = "gpio20", "gpio21";
|
||||
function = "blsp_i2c0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
mdio_pins: mdio_pinmux {
|
||||
mux_1 {
|
||||
pins = "gpio6";
|
||||
function = "mdio";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux_2 {
|
||||
pins = "gpio7";
|
||||
function = "mdc";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
serial_0_pins: serial0-pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
serial_1_pins: serial1_pinmux {
|
||||
mux {
|
||||
pins = "gpio8", "gpio9";
|
||||
function = "blsp_uart1";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
pinmux {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio13", "gpio14", "gpio15";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinmux_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio12";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "hugo_ac1200";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "hugo_ac1200";
|
||||
};
|
||||
@ -0,0 +1,306 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/dts-v1/;
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "ASUS Lyra MAP-AC2200";
|
||||
compatible = "asus,map-ac2200";
|
||||
|
||||
aliases {
|
||||
led-boot = &led_blue0;
|
||||
led-failsafe = &led_red0;
|
||||
led-running = &led_blue0;
|
||||
led-upgrade = &led_red0;
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2@60f8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nand {
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x0 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x80000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "QSEE";
|
||||
reg = <0x100000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
label = "CDT";
|
||||
reg = <0x200000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "APPSBL";
|
||||
reg = <0x280000 0x140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3c0000 {
|
||||
label = "APPSBLENV";
|
||||
reg = <0x3c0000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "ubi";
|
||||
reg = <0x400000 0x7c00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
i2c_0_pins: i2c_0_pinmux {
|
||||
pinmux {
|
||||
function = "blsp_i2c0";
|
||||
pins = "gpio20", "gpio21";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
pullups {
|
||||
pins = "gpio52", "gpio53", "gpio58",
|
||||
"gpio59";
|
||||
function = "qpic";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pulldowns {
|
||||
pins = "gpio54", "gpio55", "gpio56",
|
||||
"gpio57", "gpio60", "gpio61",
|
||||
"gpio62", "gpio63", "gpio64",
|
||||
"gpio65", "gpio66", "gpio67",
|
||||
"gpio68", "gpio69";
|
||||
function = "qpic";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
|
||||
ieee80211-freq-limit = <5470000 5875000>;
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
|
||||
|
||||
bridge@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
wifi2: wifi@1,0 {
|
||||
compatible = "qcom,ath10k";
|
||||
status = "okay";
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
|
||||
ieee80211-freq-limit = <5170000 5350000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
/* Bluetooth module attached via USB */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_i2c3 {
|
||||
pinctrl-0 = <&i2c_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
led-controller@32 {
|
||||
/* 9-channel RGB LED controller */
|
||||
compatible = "national,lp5523";
|
||||
reg = <0x32>;
|
||||
clock-mode = [01];
|
||||
|
||||
led_blue0: blue0 {
|
||||
chan-name = "blue0";
|
||||
label = "map-ac2200:blue:chan0";
|
||||
led-cur = [fa];
|
||||
max-cur = [ff];
|
||||
};
|
||||
|
||||
blue1 {
|
||||
chan-name = "blue1";
|
||||
label = "map-ac2200:blue:chan1";
|
||||
led-cur = [fa];
|
||||
max-cur = [ff];
|
||||
};
|
||||
|
||||
blue2 {
|
||||
chan-name = "blue2";
|
||||
label = "map-ac2200:blue:chan2";
|
||||
led-cur = [fa];
|
||||
max-cur = [ff];
|
||||
};
|
||||
|
||||
led_green0: green0 {
|
||||
chan-name = "green0";
|
||||
label = "map-ac2200:green:chan0";
|
||||
led-cur = [fa];
|
||||
max-cur = [ff];
|
||||
};
|
||||
|
||||
green1 {
|
||||
chan-name = "green1";
|
||||
label = "map-ac2200:green:chan1";
|
||||
led-cur = [fa];
|
||||
max-cur = [ff];
|
||||
};
|
||||
|
||||
green2 {
|
||||
chan-name = "green2";
|
||||
label = "map-ac2200:green:chan2";
|
||||
led-cur = [fa];
|
||||
max-cur = [ff];
|
||||
};
|
||||
|
||||
led_red0: red0 {
|
||||
chan-name = "red0";
|
||||
label = "map-ac2200:red:chan0";
|
||||
led-cur = [fa];
|
||||
max-cur = [ff];
|
||||
};
|
||||
|
||||
red1 {
|
||||
chan-name = "red1";
|
||||
label = "map-ac2200:red:chan1";
|
||||
led-cur = [fa];
|
||||
max-cur = [ff];
|
||||
};
|
||||
|
||||
red2 {
|
||||
chan-name = "red2";
|
||||
label = "map-ac2200:red:chan2";
|
||||
led-cur = [fa];
|
||||
max-cur = [ff];
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
@ -0,0 +1,26 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019-r619ac.dtsi"
|
||||
|
||||
/ {
|
||||
model = "P&W R619AC PCIE";
|
||||
compatible = "p2w,r619ac-pcie";
|
||||
|
||||
chosen {
|
||||
bootargs-append = " root=/dev/ubiblock0_1 rootfstype=squashfs";
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
perst-gpio = <&tlmm 4 GPIO_ACTIVE_LOW>;
|
||||
wake-gpio = <&tlmm 40 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/* Free slot for use */
|
||||
bridge@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,12 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019-r619ac.dtsi"
|
||||
|
||||
/ {
|
||||
model = "P&W R619AC";
|
||||
compatible = "p2w,r619ac";
|
||||
|
||||
chosen {
|
||||
bootargs-append = " root=/dev/ubiblock0_1 rootfstype=squashfs";
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,273 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
led-boot = &led_sys;
|
||||
led-failsafe = &led_sys;
|
||||
led-running = &led_sys;
|
||||
led-upgrade = &led_sys;
|
||||
label-mac-device = &gmac0;
|
||||
};
|
||||
|
||||
soc {
|
||||
rng@22000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2@60f8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
led_sys: sys {
|
||||
label = "r619ac:blue:sys";
|
||||
gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan2g {
|
||||
label = "r619ac:blue:wlan2g";
|
||||
gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "phy0tpt";
|
||||
};
|
||||
|
||||
wlan5g {
|
||||
label = "r619ac:blue:wlan5g";
|
||||
gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "phy1tpt";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "Bootloader";
|
||||
reg = <0 0x170000>;
|
||||
};
|
||||
|
||||
partition@170000 {
|
||||
label = "ART";
|
||||
reg = <0x170000 0x10000>;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "unused";
|
||||
reg = <0x180000 0xe80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "rootfs";
|
||||
reg = <0x0 0x8000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
pinctrl-0 = <&sd_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
vqmmc-supply = <&vqmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio_pinmux {
|
||||
mux_1 {
|
||||
pins = "gpio6";
|
||||
function = "mdio";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux_2 {
|
||||
pins = "gpio7";
|
||||
function = "mdc";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sd_0_pins: sd_0_pinmux {
|
||||
mux_1 {
|
||||
pins = "gpio23", "gpio24", "gpio25", "gpio26", "gpio28";
|
||||
function = "sdio";
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
mux_2 {
|
||||
pins = "gpio27";
|
||||
function = "sdio";
|
||||
drive-strength = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
serial_0_pins: serial0-pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pinmux {
|
||||
mux {
|
||||
pins = "gpio32", "gpio39", "gpio50";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
output-low;
|
||||
};
|
||||
|
||||
mux_1 {
|
||||
pins = "gpio52";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
output-high;
|
||||
};
|
||||
|
||||
mux_2 {
|
||||
pins = "gpio61";
|
||||
function = "gpio";
|
||||
bias-pull-down;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vqmmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "R619AC";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "R619AC";
|
||||
};
|
||||
@ -0,0 +1,273 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "ASUS RT-ACRH17";
|
||||
compatible = "asus,rt-acrh17", "qcom,ipq4019";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs-append = " ubi.mtd=UBI_DEV";
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2@60f8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power: status {
|
||||
label = "rt-acrh17:blue:status";
|
||||
gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan1 {
|
||||
label = "rt-acrh17:blue:lan1";
|
||||
gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan2 {
|
||||
label = "rt-acrh17:blue:lan2";
|
||||
gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan3 {
|
||||
label = "rt-acrh17:blue:lan3";
|
||||
gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan4 {
|
||||
label = "rt-acrh17:blue:lan4";
|
||||
gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wan_blue {
|
||||
label = "rt-acrh17:blue:wan";
|
||||
gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan_red {
|
||||
label = "rt-acrh17:red:wan";
|
||||
gpios = <&tlmm 68 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan2g {
|
||||
label = "rt-acrh17:blue:wlan2g";
|
||||
gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wlan5g {
|
||||
label = "rt-acrh17:blue:wlan5g";
|
||||
gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nand {
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "Bootloader";
|
||||
reg = <0x000000000000 0x000000400000>;
|
||||
read-only;
|
||||
};
|
||||
partition@1 {
|
||||
label = "UBI_DEV";
|
||||
reg = <0x000000400000 0x000007C00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
pullups {
|
||||
pins = "gpio53", "gpio58",
|
||||
"gpio59";
|
||||
function = "qpic";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pulldowns {
|
||||
pins = "gpio55", "gpio56",
|
||||
"gpio57", "gpio60",
|
||||
"gpio62", "gpio63", "gpio64",
|
||||
"gpio65", "gpio66", "gpio67",
|
||||
"gpio69";
|
||||
function = "qpic";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
|
||||
/* overwrite interrupts */
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
|
||||
|
||||
bridge@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
wifi2: wifi@1,0 {
|
||||
compatible = "qcom,ath10k";
|
||||
status = "okay";
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "RT-ACRH17";
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
@ -0,0 +1,265 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2017, Christian Mehlis <christian@m3hlis.de>
|
||||
* Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "Compex WPJ428";
|
||||
compatible = "compex,wpj428", "qcom,ipq4019";
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
/* select hostmode */
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2: usb2@60f8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3: usb3@8af8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
switch_lan_bmp = <0x10>;
|
||||
switch_wan_bmp = <0x20>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &status;
|
||||
led-failsafe = &status;
|
||||
led-upgrade = &status;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status: rss4 {
|
||||
label = "wpj428:green:rss4";
|
||||
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
rss3 {
|
||||
label = "wpj428:green:rss3";
|
||||
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
beeper: beeper {
|
||||
compatible = "gpio-beeper";
|
||||
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
pin {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pin_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition0@0 {
|
||||
label = "0:SBL1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition1@40000 {
|
||||
label = "0:MIBIB";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition2@60000 {
|
||||
label = "0:QSEE";
|
||||
reg = <0x00060000 0x00060000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition3@c0000 {
|
||||
label = "0:CDT";
|
||||
reg = <0x000c0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition4@d0000 {
|
||||
label = "0:DDRPARAMS";
|
||||
reg = <0x000d0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition5@e0000 {
|
||||
label = "0:APPSBLENV"; /* uboot env*/
|
||||
reg = <0x000e0000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition5@f0000 {
|
||||
label = "0:APPSBL"; /* uboot */
|
||||
reg = <0x000f0000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition5@170000 {
|
||||
label = "0:ART";
|
||||
reg = <0x00170000 0x00010000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition6@180000 {
|
||||
compatible = "denx,fit";
|
||||
label = "firmware";
|
||||
reg = <0x00180000 0x01e80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
vlan_tag = <1 0x31>;
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -0,0 +1,285 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "GL.iNet GL-B1300";
|
||||
compatible = "glinet,gl-b1300", "qcom,ipq4019";
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
/* select hostmode */
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2@60f8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
switch_lan_bmp = <0x18>;
|
||||
switch_wan_bmp = <0x20>;
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power: power {
|
||||
label = "gl-b1300:green:power";
|
||||
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
mesh {
|
||||
label = "gl-b1300:green:mesh";
|
||||
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan {
|
||||
label = "gl-b1300:green:wlan";
|
||||
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
mx25l25635f@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
SBL1@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x0 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
MIBIB@40000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x40000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
QSEE@60000 {
|
||||
label = "QSEE";
|
||||
reg = <0x60000 0x60000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
CDT@c0000 {
|
||||
label = "CDT";
|
||||
reg = <0xc0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
DDRPARAMS@d0000 {
|
||||
label = "DDRPARAMS";
|
||||
reg = <0xd0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBLENV@e0000 {
|
||||
label = "APPSBLENV";
|
||||
reg = <0xe0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBL@f0000 {
|
||||
label = "APPSBL";
|
||||
reg = <0xf0000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
ART@170000 {
|
||||
label = "ART";
|
||||
reg = <0x170000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
firmware@180000 {
|
||||
compatible = "denx,fit";
|
||||
label = "firmware";
|
||||
reg = <0x180000 0x1e80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
pinmux {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
};
|
||||
|
||||
pinmux_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54";
|
||||
};
|
||||
|
||||
pinconf {
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinconf_cs {
|
||||
pins = "gpio54";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
vlan_tag = <1 0x39>;
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "GL-B1300";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "GL-B1300";
|
||||
};
|
||||
@ -0,0 +1,408 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for Meraki MR33 (Stinkbug)
|
||||
*
|
||||
* Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
|
||||
* Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
|
||||
*
|
||||
* Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "Meraki MR33 Access Point";
|
||||
compatible = "meraki,mr33", "qcom,ipq4019";
|
||||
|
||||
aliases {
|
||||
led-boot = &status_green;
|
||||
led-failsafe = &status_red;
|
||||
led-running = &status_green;
|
||||
led-upgrade = &power_orange;
|
||||
};
|
||||
|
||||
/* Do we really need this defined? */
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
/delete-node/ ethernet-phy@0;
|
||||
/delete-node/ ethernet-phy@2;
|
||||
/delete-node/ ethernet-phy@3;
|
||||
/delete-node/ ethernet-phy@4;
|
||||
};
|
||||
|
||||
/* It is a 56-bit counter that supplies the count to the ARM arch
|
||||
timers and without upstream driver */
|
||||
counter@4a1000 {
|
||||
compatible = "qcom,qca-gcnt";
|
||||
reg = <0x4a1000 0x4>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
serial@78b0000 {
|
||||
pinctrl-0 = <&serial_1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "ti,cc2650";
|
||||
enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
|
||||
switch_lan_bmp = <0x0>; /* lan port bitmap */
|
||||
switch_wan_bmp = <0x10>; /* wan port bitmap */
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
qcom,single-phy;
|
||||
qcom,num_gmac = <1>;
|
||||
phy-mode = "rgmii-rxid";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power_orange: power {
|
||||
label = "mr33:orange:power";
|
||||
gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
|
||||
panic-indicator;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
pinctrl-0 = <&serial_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
qcom,phy_mdio_addr = <1>;
|
||||
qcom,poll_required = <1>;
|
||||
vlan_tag = <0 0x20>;
|
||||
};
|
||||
|
||||
&blsp1_i2c3{
|
||||
pinctrl-0 = <&i2c_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
at24@50 {
|
||||
compatible = "atmel,24c64";
|
||||
pagesize = <32>;
|
||||
reg = <0x50>;
|
||||
read-only; /* This holds our MAC & Meraki board-data */
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_i2c4{
|
||||
pinctrl-0 = <&i2c_1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
led-controller@30 {
|
||||
compatible = "ti,lp5562";
|
||||
reg = <0x30>;
|
||||
clock-mode = /bits/8 <2>;
|
||||
enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/* RGB led */
|
||||
status_red: chan0 {
|
||||
chan-name = "mr33:red:status";
|
||||
led-cur = /bits/ 8 <0x20>;
|
||||
max-cur = /bits/ 8 <0x60>;
|
||||
};
|
||||
|
||||
status_green: chan1 {
|
||||
chan-name = "mr33:green:status";
|
||||
led-cur = /bits/ 8 <0x20>;
|
||||
max-cur = /bits/ 8 <0x60>;
|
||||
};
|
||||
|
||||
chan2 {
|
||||
chan-name = "mr33:blue:status";
|
||||
led-cur = /bits/ 8 <0x20>;
|
||||
max-cur = /bits/ 8 <0x60>;
|
||||
};
|
||||
|
||||
chan3 {
|
||||
chan-name = "mr33:white:status";
|
||||
led-cur = /bits/ 8 <0x20>;
|
||||
max-cur = /bits/ 8 <0x60>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nand {
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "sbl1";
|
||||
reg = <0x000000000000 0x000000100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "mibib";
|
||||
reg = <0x000000100000 0x000000100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@2 {
|
||||
label = "bootconfig";
|
||||
reg = <0x000000200000 0x000000100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3 {
|
||||
label = "qsee";
|
||||
reg = <0x000000300000 0x000000100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@4 {
|
||||
label = "qsee_alt";
|
||||
reg = <0x000000400000 0x000000100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@5 {
|
||||
label = "cdt";
|
||||
reg = <0x000000500000 0x000000080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@6 {
|
||||
label = "cdt_alt";
|
||||
reg = <0x000000580000 0x000000080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@7 {
|
||||
label = "ddrparams";
|
||||
reg = <0x000000600000 0x000000080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@8 {
|
||||
label = "u-boot";
|
||||
reg = <0x000000700000 0x000000200000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@9 {
|
||||
label = "u-boot-backup";
|
||||
reg = <0x000000900000 0x000000200000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@10 {
|
||||
label = "ART";
|
||||
reg = <0x000000b00000 0x000000080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@11 {
|
||||
label = "ubi";
|
||||
reg = <0x000000c00000 0x000007000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
|
||||
|
||||
bridge@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
wifi2: wifi@1,0 {
|
||||
compatible = "qcom,ath10k";
|
||||
status = "okay";
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
/*
|
||||
* GPIO43 should be 0/1 whenever the unit is
|
||||
* powered through PoE or AC-Adapter.
|
||||
* That said, playing with this seems to
|
||||
* reset the AP.
|
||||
*/
|
||||
|
||||
mdio_pins: mdio_pinmux {
|
||||
mux_1 {
|
||||
pins = "gpio6";
|
||||
function = "mdio";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux_2 {
|
||||
pins = "gpio7";
|
||||
function = "mdc";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
serial_0_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
serial_1_pins: serial1_pinmux {
|
||||
mux {
|
||||
/* We use the i2c-0 pins for serial_1 */
|
||||
pins = "gpio8", "gpio9";
|
||||
function = "blsp_uart1";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c_0_pins: i2c_0_pinmux {
|
||||
pinmux {
|
||||
function = "blsp_i2c0";
|
||||
pins = "gpio20", "gpio21";
|
||||
};
|
||||
|
||||
pinconf {
|
||||
pins = "gpio20", "gpio21";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c_1_pins: i2c_1_pinmux {
|
||||
pinmux {
|
||||
function = "blsp_i2c1";
|
||||
pins = "gpio34", "gpio35";
|
||||
};
|
||||
|
||||
pinconf {
|
||||
pins = "gpio34", "gpio35";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
/*
|
||||
* There are 18 pins. 15 pins are common between LCD and NAND.
|
||||
* The QPIC controller arbitrates between LCD and NAND. Of the
|
||||
* remaining 4, 2 are for NAND and 2 are for LCD exclusively.
|
||||
*
|
||||
* The meraki source hints that the bluetooth module claims
|
||||
* pin 52 as well. But sadly, there's no data whenever this
|
||||
* is a NAND or LCD exclusive pin or not.
|
||||
*/
|
||||
|
||||
pullups {
|
||||
pins = "gpio52", "gpio53", "gpio58",
|
||||
"gpio59";
|
||||
function = "qpic";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pulldowns {
|
||||
pins = "gpio54", "gpio55", "gpio56",
|
||||
"gpio57", "gpio60", "gpio61",
|
||||
"gpio62", "gpio63", "gpio64",
|
||||
"gpio65", "gpio66", "gpio67",
|
||||
"gpio68", "gpio69";
|
||||
function = "qpic";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "Meraki-MR33";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "Meraki-MR33";
|
||||
};
|
||||
@ -0,0 +1,9 @@
|
||||
#
|
||||
## Makefile for the Qualcomm Atheros ethernet edma driver
|
||||
#
|
||||
|
||||
|
||||
obj-$(CONFIG_ESSEDMA) += essedma.o
|
||||
|
||||
essedma-objs := edma_axi.o edma.o edma_ethtool.o
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,455 @@
|
||||
/*
|
||||
* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all copies.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
|
||||
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _EDMA_H_
|
||||
#define _EDMA_H_
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/pagemap.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/sysctl.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/of_net.h>
|
||||
#include <net/checksum.h>
|
||||
#include <net/ip6_checksum.h>
|
||||
#include <asm-generic/bug.h>
|
||||
#include "ess_edma.h"
|
||||
|
||||
#define EDMA_CPU_CORES_SUPPORTED 4
|
||||
#define EDMA_MAX_PORTID_SUPPORTED 5
|
||||
#define EDMA_MAX_VLAN_SUPPORTED EDMA_MAX_PORTID_SUPPORTED
|
||||
#define EDMA_MAX_PORTID_BITMAP_INDEX (EDMA_MAX_PORTID_SUPPORTED + 1)
|
||||
#define EDMA_MAX_PORTID_BITMAP_SUPPORTED 0x1f /* 0001_1111 = 0x1f */
|
||||
#define EDMA_MAX_NETDEV_PER_QUEUE 4 /* 3 Netdev per queue, 1 space for indexing */
|
||||
|
||||
#define EDMA_MAX_RECEIVE_QUEUE 8
|
||||
#define EDMA_MAX_TRANSMIT_QUEUE 16
|
||||
|
||||
/* WAN/LAN adapter number */
|
||||
#define EDMA_WAN 0
|
||||
#define EDMA_LAN 1
|
||||
|
||||
/* VLAN tag */
|
||||
#define EDMA_LAN_DEFAULT_VLAN 1
|
||||
#define EDMA_WAN_DEFAULT_VLAN 2
|
||||
|
||||
#define EDMA_DEFAULT_GROUP1_VLAN 1
|
||||
#define EDMA_DEFAULT_GROUP2_VLAN 2
|
||||
#define EDMA_DEFAULT_GROUP3_VLAN 3
|
||||
#define EDMA_DEFAULT_GROUP4_VLAN 4
|
||||
#define EDMA_DEFAULT_GROUP5_VLAN 5
|
||||
|
||||
/* Queues exposed to linux kernel */
|
||||
#define EDMA_NETDEV_TX_QUEUE 4
|
||||
#define EDMA_NETDEV_RX_QUEUE 4
|
||||
|
||||
/* Number of queues per core */
|
||||
#define EDMA_NUM_TXQ_PER_CORE 4
|
||||
#define EDMA_NUM_RXQ_PER_CORE 2
|
||||
|
||||
#define EDMA_TPD_EOP_SHIFT 31
|
||||
|
||||
#define EDMA_PORT_ID_SHIFT 12
|
||||
#define EDMA_PORT_ID_MASK 0x7
|
||||
|
||||
/* tpd word 3 bit 18-28 */
|
||||
#define EDMA_TPD_PORT_BITMAP_SHIFT 18
|
||||
|
||||
#define EDMA_TPD_FROM_CPU_SHIFT 25
|
||||
|
||||
#define EDMA_FROM_CPU_MASK 0x80
|
||||
#define EDMA_SKB_PRIORITY_MASK 0x38
|
||||
|
||||
/* TX/RX descriptor ring count */
|
||||
/* should be a power of 2 */
|
||||
#define EDMA_RX_RING_SIZE 128
|
||||
#define EDMA_TX_RING_SIZE 128
|
||||
|
||||
/* Flags used in paged/non paged mode */
|
||||
#define EDMA_RX_HEAD_BUFF_SIZE_JUMBO 256
|
||||
#define EDMA_RX_HEAD_BUFF_SIZE 1540
|
||||
|
||||
/* MAX frame size supported by switch */
|
||||
#define EDMA_MAX_JUMBO_FRAME_SIZE 9216
|
||||
|
||||
/* Configurations */
|
||||
#define EDMA_INTR_CLEAR_TYPE 0
|
||||
#define EDMA_INTR_SW_IDX_W_TYPE 0
|
||||
#define EDMA_FIFO_THRESH_TYPE 0
|
||||
#define EDMA_RSS_TYPE 0
|
||||
#define EDMA_RX_IMT 0x0020
|
||||
#define EDMA_TX_IMT 0x0050
|
||||
#define EDMA_TPD_BURST 5
|
||||
#define EDMA_TXF_BURST 0x100
|
||||
#define EDMA_RFD_BURST 8
|
||||
#define EDMA_RFD_THR 16
|
||||
#define EDMA_RFD_LTHR 0
|
||||
|
||||
/* RX/TX per CPU based mask/shift */
|
||||
#define EDMA_TX_PER_CPU_MASK 0xF
|
||||
#define EDMA_RX_PER_CPU_MASK 0x3
|
||||
#define EDMA_TX_PER_CPU_MASK_SHIFT 0x2
|
||||
#define EDMA_RX_PER_CPU_MASK_SHIFT 0x1
|
||||
#define EDMA_TX_CPU_START_SHIFT 0x2
|
||||
#define EDMA_RX_CPU_START_SHIFT 0x1
|
||||
|
||||
/* FLags used in transmit direction */
|
||||
#define EDMA_HW_CHECKSUM 0x00000001
|
||||
#define EDMA_VLAN_TX_TAG_INSERT_FLAG 0x00000002
|
||||
#define EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG 0x00000004
|
||||
|
||||
#define EDMA_SW_DESC_FLAG_LAST 0x1
|
||||
#define EDMA_SW_DESC_FLAG_SKB_HEAD 0x2
|
||||
#define EDMA_SW_DESC_FLAG_SKB_FRAG 0x4
|
||||
#define EDMA_SW_DESC_FLAG_SKB_FRAGLIST 0x8
|
||||
#define EDMA_SW_DESC_FLAG_SKB_NONE 0x10
|
||||
#define EDMA_SW_DESC_FLAG_SKB_REUSE 0x20
|
||||
|
||||
|
||||
#define EDMA_MAX_SKB_FRAGS (MAX_SKB_FRAGS + 1)
|
||||
|
||||
/* Ethtool specific list of EDMA supported features */
|
||||
#define EDMA_SUPPORTED_FEATURES (SUPPORTED_10baseT_Half \
|
||||
| SUPPORTED_10baseT_Full \
|
||||
| SUPPORTED_100baseT_Half \
|
||||
| SUPPORTED_100baseT_Full \
|
||||
| SUPPORTED_1000baseT_Full)
|
||||
|
||||
/* Recevie side atheros Header */
|
||||
#define EDMA_RX_ATH_HDR_VERSION 0x2
|
||||
#define EDMA_RX_ATH_HDR_VERSION_SHIFT 14
|
||||
#define EDMA_RX_ATH_HDR_PRIORITY_SHIFT 11
|
||||
#define EDMA_RX_ATH_PORT_TYPE_SHIFT 6
|
||||
#define EDMA_RX_ATH_HDR_RSTP_PORT_TYPE 0x4
|
||||
|
||||
/* Transmit side atheros Header */
|
||||
#define EDMA_TX_ATH_HDR_PORT_BITMAP_MASK 0x7F
|
||||
#define EDMA_TX_ATH_HDR_FROM_CPU_MASK 0x80
|
||||
#define EDMA_TX_ATH_HDR_FROM_CPU_SHIFT 7
|
||||
|
||||
#define EDMA_TXQ_START_CORE0 8
|
||||
#define EDMA_TXQ_START_CORE1 12
|
||||
#define EDMA_TXQ_START_CORE2 0
|
||||
#define EDMA_TXQ_START_CORE3 4
|
||||
|
||||
#define EDMA_TXQ_IRQ_MASK_CORE0 0x0F00
|
||||
#define EDMA_TXQ_IRQ_MASK_CORE1 0xF000
|
||||
#define EDMA_TXQ_IRQ_MASK_CORE2 0x000F
|
||||
#define EDMA_TXQ_IRQ_MASK_CORE3 0x00F0
|
||||
|
||||
#define EDMA_ETH_HDR_LEN 12
|
||||
#define EDMA_ETH_TYPE_MASK 0xFFFF
|
||||
|
||||
#define EDMA_RX_BUFFER_WRITE 16
|
||||
#define EDMA_RFD_AVAIL_THR 80
|
||||
|
||||
#define EDMA_GMAC_NO_MDIO_PHY PHY_MAX_ADDR
|
||||
|
||||
extern int ssdk_rfs_ipct_rule_set(__be32 ip_src, __be32 ip_dst,
|
||||
__be16 sport, __be16 dport,
|
||||
uint8_t proto, u16 loadbalance, bool action);
|
||||
struct edma_ethtool_statistics {
|
||||
u32 tx_q0_pkt;
|
||||
u32 tx_q1_pkt;
|
||||
u32 tx_q2_pkt;
|
||||
u32 tx_q3_pkt;
|
||||
u32 tx_q4_pkt;
|
||||
u32 tx_q5_pkt;
|
||||
u32 tx_q6_pkt;
|
||||
u32 tx_q7_pkt;
|
||||
u32 tx_q8_pkt;
|
||||
u32 tx_q9_pkt;
|
||||
u32 tx_q10_pkt;
|
||||
u32 tx_q11_pkt;
|
||||
u32 tx_q12_pkt;
|
||||
u32 tx_q13_pkt;
|
||||
u32 tx_q14_pkt;
|
||||
u32 tx_q15_pkt;
|
||||
u32 tx_q0_byte;
|
||||
u32 tx_q1_byte;
|
||||
u32 tx_q2_byte;
|
||||
u32 tx_q3_byte;
|
||||
u32 tx_q4_byte;
|
||||
u32 tx_q5_byte;
|
||||
u32 tx_q6_byte;
|
||||
u32 tx_q7_byte;
|
||||
u32 tx_q8_byte;
|
||||
u32 tx_q9_byte;
|
||||
u32 tx_q10_byte;
|
||||
u32 tx_q11_byte;
|
||||
u32 tx_q12_byte;
|
||||
u32 tx_q13_byte;
|
||||
u32 tx_q14_byte;
|
||||
u32 tx_q15_byte;
|
||||
u32 rx_q0_pkt;
|
||||
u32 rx_q1_pkt;
|
||||
u32 rx_q2_pkt;
|
||||
u32 rx_q3_pkt;
|
||||
u32 rx_q4_pkt;
|
||||
u32 rx_q5_pkt;
|
||||
u32 rx_q6_pkt;
|
||||
u32 rx_q7_pkt;
|
||||
u32 rx_q0_byte;
|
||||
u32 rx_q1_byte;
|
||||
u32 rx_q2_byte;
|
||||
u32 rx_q3_byte;
|
||||
u32 rx_q4_byte;
|
||||
u32 rx_q5_byte;
|
||||
u32 rx_q6_byte;
|
||||
u32 rx_q7_byte;
|
||||
u32 tx_desc_error;
|
||||
u32 rx_alloc_fail_ctr;
|
||||
};
|
||||
|
||||
struct edma_mdio_data {
|
||||
struct mii_bus *mii_bus;
|
||||
void __iomem *membase;
|
||||
int phy_irq[PHY_MAX_ADDR];
|
||||
};
|
||||
|
||||
/* EDMA LINK state */
|
||||
enum edma_link_state {
|
||||
__EDMA_LINKUP, /* Indicate link is UP */
|
||||
__EDMA_LINKDOWN /* Indicate link is down */
|
||||
};
|
||||
|
||||
/* EDMA GMAC state */
|
||||
enum edma_gmac_state {
|
||||
__EDMA_UP /* use to indicate GMAC is up */
|
||||
};
|
||||
|
||||
/* edma transmit descriptor */
|
||||
struct edma_tx_desc {
|
||||
__le16 len; /* full packet including CRC */
|
||||
__le16 svlan_tag; /* vlan tag */
|
||||
__le32 word1; /* byte 4-7 */
|
||||
__le32 addr; /* address of buffer */
|
||||
__le32 word3; /* byte 12 */
|
||||
};
|
||||
|
||||
/* edma receive return descriptor */
|
||||
struct edma_rx_return_desc {
|
||||
u16 rrd0;
|
||||
u16 rrd1;
|
||||
u16 rrd2;
|
||||
u16 rrd3;
|
||||
u16 rrd4;
|
||||
u16 rrd5;
|
||||
u16 rrd6;
|
||||
u16 rrd7;
|
||||
};
|
||||
|
||||
/* RFD descriptor */
|
||||
struct edma_rx_free_desc {
|
||||
__le32 buffer_addr; /* buffer address */
|
||||
};
|
||||
|
||||
/* edma hw specific data */
|
||||
struct edma_hw {
|
||||
u32 __iomem *hw_addr; /* inner register address */
|
||||
struct edma_adapter *adapter; /* netdevice adapter */
|
||||
u32 rx_intr_mask; /*rx interrupt mask */
|
||||
u32 tx_intr_mask; /* tx interrupt nask */
|
||||
u32 misc_intr_mask; /* misc interrupt mask */
|
||||
u32 wol_intr_mask; /* wake on lan interrupt mask */
|
||||
bool intr_clear_type; /* interrupt clear */
|
||||
bool intr_sw_idx_w; /* interrupt software index */
|
||||
u32 rx_head_buff_size; /* Rx buffer size */
|
||||
u8 rss_type; /* rss protocol type */
|
||||
};
|
||||
|
||||
/* edma_sw_desc stores software descriptor
|
||||
* SW descriptor has 1:1 map with HW descriptor
|
||||
*/
|
||||
struct edma_sw_desc {
|
||||
struct sk_buff *skb;
|
||||
dma_addr_t dma; /* dma address */
|
||||
u16 length; /* Tx/Rx buffer length */
|
||||
u32 flags;
|
||||
};
|
||||
|
||||
/* per core related information */
|
||||
struct edma_per_cpu_queues_info {
|
||||
struct napi_struct napi; /* napi associated with the core */
|
||||
u32 tx_mask; /* tx interrupt mask */
|
||||
u32 rx_mask; /* rx interrupt mask */
|
||||
u32 tx_status; /* tx interrupt status */
|
||||
u32 rx_status; /* rx interrupt status */
|
||||
u32 tx_start; /* tx queue start */
|
||||
u32 rx_start; /* rx queue start */
|
||||
struct edma_common_info *edma_cinfo; /* edma common info */
|
||||
};
|
||||
|
||||
/* edma specific common info */
|
||||
struct edma_common_info {
|
||||
struct edma_tx_desc_ring *tpd_ring[16]; /* 16 Tx queues */
|
||||
struct edma_rfd_desc_ring *rfd_ring[8]; /* 8 Rx queues */
|
||||
struct platform_device *pdev; /* device structure */
|
||||
struct net_device *netdev[EDMA_MAX_PORTID_SUPPORTED];
|
||||
struct net_device *portid_netdev_lookup_tbl[EDMA_MAX_PORTID_BITMAP_INDEX];
|
||||
struct ctl_table_header *edma_ctl_table_hdr;
|
||||
int num_gmac;
|
||||
struct edma_ethtool_statistics edma_ethstats; /* ethtool stats */
|
||||
int num_rx_queues; /* number of rx queue */
|
||||
u32 num_tx_queues; /* number of tx queue */
|
||||
u32 tx_irq[16]; /* number of tx irq */
|
||||
u32 rx_irq[8]; /* number of rx irq */
|
||||
u32 from_cpu; /* from CPU TPD field */
|
||||
u32 num_rxq_per_core; /* Rx queues per core */
|
||||
u32 num_txq_per_core; /* Tx queues per core */
|
||||
u16 tx_ring_count; /* Tx ring count */
|
||||
u16 rx_ring_count; /* Rx ring*/
|
||||
u16 rx_head_buffer_len; /* rx buffer length */
|
||||
u16 rx_page_buffer_len; /* rx buffer length */
|
||||
u32 page_mode; /* Jumbo frame supported flag */
|
||||
u32 fraglist_mode; /* fraglist supported flag */
|
||||
struct edma_hw hw; /* edma hw specific structure */
|
||||
struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */
|
||||
spinlock_t stats_lock; /* protect edma stats area for updation */
|
||||
struct timer_list edma_stats_timer;
|
||||
bool is_single_phy;
|
||||
void __iomem *ess_hw_addr;
|
||||
struct clk *ess_clk;
|
||||
};
|
||||
|
||||
/* transimit packet descriptor (tpd) ring */
|
||||
struct edma_tx_desc_ring {
|
||||
struct netdev_queue *nq[EDMA_MAX_NETDEV_PER_QUEUE]; /* Linux queue index */
|
||||
struct net_device *netdev[EDMA_MAX_NETDEV_PER_QUEUE];
|
||||
/* Array of netdevs associated with the tpd ring */
|
||||
void *hw_desc; /* descriptor ring virtual address */
|
||||
struct edma_sw_desc *sw_desc; /* buffer associated with ring */
|
||||
int netdev_bmp; /* Bitmap for per-ring netdevs */
|
||||
u32 size; /* descriptor ring length in bytes */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
u16 sw_next_to_fill; /* next Tx descriptor to fill */
|
||||
u16 sw_next_to_clean; /* next Tx descriptor to clean */
|
||||
};
|
||||
|
||||
/* receive free descriptor (rfd) ring */
|
||||
struct edma_rfd_desc_ring {
|
||||
void *hw_desc; /* descriptor ring virtual address */
|
||||
struct edma_sw_desc *sw_desc; /* buffer associated with ring */
|
||||
u16 size; /* bytes allocated to sw_desc */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
u16 sw_next_to_fill; /* next descriptor to fill */
|
||||
u16 sw_next_to_clean; /* next descriptor to clean */
|
||||
u16 pending_fill; /* fill pending from previous iteration */
|
||||
};
|
||||
|
||||
/* edma_rfs_flter_node - rfs filter node in hash table */
|
||||
struct edma_rfs_filter_node {
|
||||
struct flow_keys keys;
|
||||
u32 flow_id; /* flow_id of filter provided by kernel */
|
||||
u16 filter_id; /* filter id of filter returned by adaptor */
|
||||
u16 rq_id; /* desired rq index */
|
||||
struct hlist_node node; /* edma rfs list node */
|
||||
};
|
||||
|
||||
/* edma_rfs_flow_tbl - rfs flow table */
|
||||
struct edma_rfs_flow_table {
|
||||
u16 max_num_filter; /* Maximum number of filters edma supports */
|
||||
u16 hashtoclean; /* hash table index to clean next */
|
||||
int filter_available; /* Number of free filters available */
|
||||
struct hlist_head hlist_head[EDMA_RFS_FLOW_ENTRIES];
|
||||
spinlock_t rfs_ftab_lock;
|
||||
struct timer_list expire_rfs; /* timer function for edma_rps_may_expire_flow */
|
||||
};
|
||||
|
||||
/* EDMA net device structure */
|
||||
struct edma_adapter {
|
||||
struct net_device *netdev; /* netdevice */
|
||||
struct platform_device *pdev; /* platform device */
|
||||
struct edma_common_info *edma_cinfo; /* edma common info */
|
||||
struct phy_device *phydev; /* Phy device */
|
||||
struct edma_rfs_flow_table rfs; /* edma rfs flow table */
|
||||
struct net_device_stats stats; /* netdev statistics */
|
||||
set_rfs_filter_callback_t set_rfs_rule;
|
||||
u32 flags;/* status flags */
|
||||
unsigned long state_flags; /* GMAC up/down flags */
|
||||
u32 forced_speed; /* link force speed */
|
||||
u32 forced_duplex; /* link force duplex */
|
||||
u32 link_state; /* phy link state */
|
||||
u32 phy_mdio_addr; /* PHY device address on MII interface */
|
||||
u32 poll_required; /* check if link polling is required */
|
||||
u32 tx_start_offset[CONFIG_NR_CPUS]; /* tx queue start */
|
||||
u32 default_vlan_tag; /* vlan tag */
|
||||
u32 dp_bitmap;
|
||||
uint8_t phy_id[MII_BUS_ID_SIZE + 3];
|
||||
};
|
||||
|
||||
int edma_alloc_queues_tx(struct edma_common_info *edma_cinfo);
|
||||
int edma_alloc_queues_rx(struct edma_common_info *edma_cinfo);
|
||||
int edma_open(struct net_device *netdev);
|
||||
int edma_close(struct net_device *netdev);
|
||||
void edma_free_tx_resources(struct edma_common_info *edma_c_info);
|
||||
void edma_free_rx_resources(struct edma_common_info *edma_c_info);
|
||||
int edma_alloc_tx_rings(struct edma_common_info *edma_cinfo);
|
||||
int edma_alloc_rx_rings(struct edma_common_info *edma_cinfo);
|
||||
void edma_free_tx_rings(struct edma_common_info *edma_cinfo);
|
||||
void edma_free_rx_rings(struct edma_common_info *edma_cinfo);
|
||||
void edma_free_queues(struct edma_common_info *edma_cinfo);
|
||||
void edma_irq_disable(struct edma_common_info *edma_cinfo);
|
||||
int edma_reset(struct edma_common_info *edma_cinfo);
|
||||
int edma_poll(struct napi_struct *napi, int budget);
|
||||
netdev_tx_t edma_xmit(struct sk_buff *skb,
|
||||
struct net_device *netdev);
|
||||
int edma_configure(struct edma_common_info *edma_cinfo);
|
||||
void edma_irq_enable(struct edma_common_info *edma_cinfo);
|
||||
void edma_enable_tx_ctrl(struct edma_hw *hw);
|
||||
void edma_enable_rx_ctrl(struct edma_hw *hw);
|
||||
void edma_stop_rx_tx(struct edma_hw *hw);
|
||||
void edma_free_irqs(struct edma_adapter *adapter);
|
||||
irqreturn_t edma_interrupt(int irq, void *dev);
|
||||
void edma_write_reg(u16 reg_addr, u32 reg_value);
|
||||
void edma_read_reg(u16 reg_addr, volatile u32 *reg_value);
|
||||
struct net_device_stats *edma_get_stats(struct net_device *netdev);
|
||||
int edma_set_mac_addr(struct net_device *netdev, void *p);
|
||||
int edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
|
||||
u16 rxq, u32 flow_id);
|
||||
int edma_register_rfs_filter(struct net_device *netdev,
|
||||
set_rfs_filter_callback_t set_filter);
|
||||
void edma_flow_may_expire(struct timer_list *t);
|
||||
void edma_set_ethtool_ops(struct net_device *netdev);
|
||||
void edma_set_stp_rstp(bool tag);
|
||||
void edma_assign_ath_hdr_type(int tag);
|
||||
int edma_get_default_vlan_tag(struct net_device *netdev);
|
||||
void edma_adjust_link(struct net_device *netdev);
|
||||
int edma_fill_netdev(struct edma_common_info *edma_cinfo, int qid, int num, int txq_id);
|
||||
void edma_read_append_stats(struct edma_common_info *edma_cinfo);
|
||||
void edma_change_tx_coalesce(int usecs);
|
||||
void edma_change_rx_coalesce(int usecs);
|
||||
void edma_get_tx_rx_coalesce(u32 *reg_val);
|
||||
void edma_clear_irq_status(void);
|
||||
void ess_set_port_status_speed(struct edma_common_info *edma_cinfo,
|
||||
struct phy_device *phydev, uint8_t port_id);
|
||||
#endif /* _EDMA_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,384 @@
|
||||
/*
|
||||
* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all copies.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
|
||||
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/string.h>
|
||||
#include "edma.h"
|
||||
|
||||
struct edma_ethtool_stats {
|
||||
uint8_t stat_string[ETH_GSTRING_LEN];
|
||||
uint32_t stat_offset;
|
||||
};
|
||||
|
||||
#define EDMA_STAT(m) offsetof(struct edma_ethtool_statistics, m)
|
||||
#define DRVINFO_LEN 32
|
||||
|
||||
/* Array of strings describing statistics
|
||||
*/
|
||||
static const struct edma_ethtool_stats edma_gstrings_stats[] = {
|
||||
{"tx_q0_pkt", EDMA_STAT(tx_q0_pkt)},
|
||||
{"tx_q1_pkt", EDMA_STAT(tx_q1_pkt)},
|
||||
{"tx_q2_pkt", EDMA_STAT(tx_q2_pkt)},
|
||||
{"tx_q3_pkt", EDMA_STAT(tx_q3_pkt)},
|
||||
{"tx_q4_pkt", EDMA_STAT(tx_q4_pkt)},
|
||||
{"tx_q5_pkt", EDMA_STAT(tx_q5_pkt)},
|
||||
{"tx_q6_pkt", EDMA_STAT(tx_q6_pkt)},
|
||||
{"tx_q7_pkt", EDMA_STAT(tx_q7_pkt)},
|
||||
{"tx_q8_pkt", EDMA_STAT(tx_q8_pkt)},
|
||||
{"tx_q9_pkt", EDMA_STAT(tx_q9_pkt)},
|
||||
{"tx_q10_pkt", EDMA_STAT(tx_q10_pkt)},
|
||||
{"tx_q11_pkt", EDMA_STAT(tx_q11_pkt)},
|
||||
{"tx_q12_pkt", EDMA_STAT(tx_q12_pkt)},
|
||||
{"tx_q13_pkt", EDMA_STAT(tx_q13_pkt)},
|
||||
{"tx_q14_pkt", EDMA_STAT(tx_q14_pkt)},
|
||||
{"tx_q15_pkt", EDMA_STAT(tx_q15_pkt)},
|
||||
{"tx_q0_byte", EDMA_STAT(tx_q0_byte)},
|
||||
{"tx_q1_byte", EDMA_STAT(tx_q1_byte)},
|
||||
{"tx_q2_byte", EDMA_STAT(tx_q2_byte)},
|
||||
{"tx_q3_byte", EDMA_STAT(tx_q3_byte)},
|
||||
{"tx_q4_byte", EDMA_STAT(tx_q4_byte)},
|
||||
{"tx_q5_byte", EDMA_STAT(tx_q5_byte)},
|
||||
{"tx_q6_byte", EDMA_STAT(tx_q6_byte)},
|
||||
{"tx_q7_byte", EDMA_STAT(tx_q7_byte)},
|
||||
{"tx_q8_byte", EDMA_STAT(tx_q8_byte)},
|
||||
{"tx_q9_byte", EDMA_STAT(tx_q9_byte)},
|
||||
{"tx_q10_byte", EDMA_STAT(tx_q10_byte)},
|
||||
{"tx_q11_byte", EDMA_STAT(tx_q11_byte)},
|
||||
{"tx_q12_byte", EDMA_STAT(tx_q12_byte)},
|
||||
{"tx_q13_byte", EDMA_STAT(tx_q13_byte)},
|
||||
{"tx_q14_byte", EDMA_STAT(tx_q14_byte)},
|
||||
{"tx_q15_byte", EDMA_STAT(tx_q15_byte)},
|
||||
{"rx_q0_pkt", EDMA_STAT(rx_q0_pkt)},
|
||||
{"rx_q1_pkt", EDMA_STAT(rx_q1_pkt)},
|
||||
{"rx_q2_pkt", EDMA_STAT(rx_q2_pkt)},
|
||||
{"rx_q3_pkt", EDMA_STAT(rx_q3_pkt)},
|
||||
{"rx_q4_pkt", EDMA_STAT(rx_q4_pkt)},
|
||||
{"rx_q5_pkt", EDMA_STAT(rx_q5_pkt)},
|
||||
{"rx_q6_pkt", EDMA_STAT(rx_q6_pkt)},
|
||||
{"rx_q7_pkt", EDMA_STAT(rx_q7_pkt)},
|
||||
{"rx_q0_byte", EDMA_STAT(rx_q0_byte)},
|
||||
{"rx_q1_byte", EDMA_STAT(rx_q1_byte)},
|
||||
{"rx_q2_byte", EDMA_STAT(rx_q2_byte)},
|
||||
{"rx_q3_byte", EDMA_STAT(rx_q3_byte)},
|
||||
{"rx_q4_byte", EDMA_STAT(rx_q4_byte)},
|
||||
{"rx_q5_byte", EDMA_STAT(rx_q5_byte)},
|
||||
{"rx_q6_byte", EDMA_STAT(rx_q6_byte)},
|
||||
{"rx_q7_byte", EDMA_STAT(rx_q7_byte)},
|
||||
{"tx_desc_error", EDMA_STAT(tx_desc_error)},
|
||||
{"rx_alloc_fail_ctr", EDMA_STAT(rx_alloc_fail_ctr)},
|
||||
};
|
||||
|
||||
#define EDMA_STATS_LEN ARRAY_SIZE(edma_gstrings_stats)
|
||||
|
||||
/* edma_get_strset_count()
|
||||
* Get strset count
|
||||
*/
|
||||
static int edma_get_strset_count(struct net_device *netdev,
|
||||
int sset)
|
||||
{
|
||||
switch (sset) {
|
||||
case ETH_SS_STATS:
|
||||
return EDMA_STATS_LEN;
|
||||
default:
|
||||
netdev_dbg(netdev, "%s: Invalid string set", __func__);
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* edma_get_strings()
|
||||
* get stats string
|
||||
*/
|
||||
static void edma_get_strings(struct net_device *netdev, uint32_t stringset,
|
||||
uint8_t *data)
|
||||
{
|
||||
uint8_t *p = data;
|
||||
uint32_t i;
|
||||
|
||||
switch (stringset) {
|
||||
case ETH_SS_STATS:
|
||||
for (i = 0; i < EDMA_STATS_LEN; i++) {
|
||||
memcpy(p, edma_gstrings_stats[i].stat_string,
|
||||
min((size_t)ETH_GSTRING_LEN,
|
||||
strlen(edma_gstrings_stats[i].stat_string)
|
||||
+ 1));
|
||||
p += ETH_GSTRING_LEN;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* edma_get_ethtool_stats()
|
||||
* Get ethtool statistics
|
||||
*/
|
||||
static void edma_get_ethtool_stats(struct net_device *netdev,
|
||||
struct ethtool_stats *stats, uint64_t *data)
|
||||
{
|
||||
struct edma_adapter *adapter = netdev_priv(netdev);
|
||||
struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
|
||||
int i;
|
||||
uint8_t *p = NULL;
|
||||
|
||||
edma_read_append_stats(edma_cinfo);
|
||||
|
||||
for(i = 0; i < EDMA_STATS_LEN; i++) {
|
||||
p = (uint8_t *)&(edma_cinfo->edma_ethstats) +
|
||||
edma_gstrings_stats[i].stat_offset;
|
||||
data[i] = *(uint32_t *)p;
|
||||
}
|
||||
}
|
||||
|
||||
/* edma_get_drvinfo()
|
||||
* get edma driver info
|
||||
*/
|
||||
static void edma_get_drvinfo(struct net_device *dev,
|
||||
struct ethtool_drvinfo *info)
|
||||
{
|
||||
strlcpy(info->driver, "ess_edma", DRVINFO_LEN);
|
||||
strlcpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
|
||||
}
|
||||
|
||||
/* edma_nway_reset()
|
||||
* Reset the phy, if available.
|
||||
*/
|
||||
static int edma_nway_reset(struct net_device *netdev)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* edma_get_wol()
|
||||
* get wake on lan info
|
||||
*/
|
||||
static void edma_get_wol(struct net_device *netdev,
|
||||
struct ethtool_wolinfo *wol)
|
||||
{
|
||||
wol->supported = 0;
|
||||
wol->wolopts = 0;
|
||||
}
|
||||
|
||||
/* edma_get_msglevel()
|
||||
* get message level.
|
||||
*/
|
||||
static uint32_t edma_get_msglevel(struct net_device *netdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_get_settings()
|
||||
* Get edma settings
|
||||
*/
|
||||
static int edma_get_settings(struct net_device *netdev,
|
||||
struct ethtool_link_ksettings *cmd)
|
||||
{
|
||||
struct edma_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
if (adapter->poll_required) {
|
||||
struct phy_device *phydev = NULL;
|
||||
uint16_t phyreg;
|
||||
|
||||
if ((adapter->forced_speed != SPEED_UNKNOWN)
|
||||
&& !(adapter->poll_required))
|
||||
return -EPERM;
|
||||
|
||||
phydev = adapter->phydev;
|
||||
|
||||
linkmode_copy(cmd->link_modes.advertising, phydev->advertising);
|
||||
linkmode_copy(cmd->link_modes.supported, phydev->supported);
|
||||
|
||||
cmd->base.autoneg = phydev->autoneg;
|
||||
|
||||
if (adapter->link_state == __EDMA_LINKDOWN) {
|
||||
cmd->base.speed = SPEED_UNKNOWN;
|
||||
cmd->base.duplex = DUPLEX_UNKNOWN;
|
||||
} else {
|
||||
cmd->base.speed = phydev->speed;
|
||||
cmd->base.duplex = phydev->duplex;
|
||||
}
|
||||
|
||||
cmd->base.phy_address = adapter->phy_mdio_addr;
|
||||
|
||||
phyreg = (uint16_t)phy_read(adapter->phydev, MII_LPA);
|
||||
if (phyreg & LPA_10HALF)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
if (phyreg & LPA_10FULL)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
if (phyreg & LPA_100HALF)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
if (phyreg & LPA_100FULL)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
phyreg = (uint16_t)phy_read(adapter->phydev, MII_STAT1000);
|
||||
if (phyreg & LPA_1000HALF)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
if (phyreg & LPA_1000FULL)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
} else {
|
||||
/* If the speed/duplex for this GMAC is forced and we
|
||||
* are not polling for link state changes, return the
|
||||
* values as specified by platform. This will be true
|
||||
* for GMACs connected to switch, and interfaces that
|
||||
* do not use a PHY.
|
||||
*/
|
||||
if (!(adapter->poll_required)) {
|
||||
if (adapter->forced_speed != SPEED_UNKNOWN) {
|
||||
/* set speed and duplex */
|
||||
cmd->base.speed = SPEED_1000;
|
||||
cmd->base.duplex = DUPLEX_FULL;
|
||||
|
||||
/* Populate capabilities advertised by self */
|
||||
linkmode_zero(cmd->link_modes.advertising);
|
||||
cmd->base.autoneg = 0;
|
||||
cmd->base.port = PORT_TP;
|
||||
cmd->base.transceiver = XCVR_EXTERNAL;
|
||||
} else {
|
||||
/* non link polled and non
|
||||
* forced speed/duplex interface
|
||||
*/
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_set_settings()
|
||||
* Set EDMA settings
|
||||
*/
|
||||
static int edma_set_settings(struct net_device *netdev,
|
||||
const struct ethtool_link_ksettings *cmd)
|
||||
{
|
||||
struct edma_adapter *adapter = netdev_priv(netdev);
|
||||
struct phy_device *phydev = NULL;
|
||||
|
||||
if ((adapter->forced_speed != SPEED_UNKNOWN) &&
|
||||
!adapter->poll_required)
|
||||
return -EPERM;
|
||||
|
||||
phydev = adapter->phydev;
|
||||
linkmode_copy(phydev->advertising, cmd->link_modes.advertising);
|
||||
linkmode_copy(phydev->supported, cmd->link_modes.supported);
|
||||
phydev->autoneg = cmd->base.autoneg;
|
||||
phydev->speed = cmd->base.speed;
|
||||
phydev->duplex = cmd->base.duplex;
|
||||
|
||||
genphy_config_aneg(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_get_coalesce
|
||||
* get interrupt mitigation
|
||||
*/
|
||||
static int edma_get_coalesce(struct net_device *netdev,
|
||||
struct ethtool_coalesce *ec)
|
||||
{
|
||||
u32 reg_val;
|
||||
|
||||
edma_get_tx_rx_coalesce(®_val);
|
||||
|
||||
/* We read the Interrupt Moderation Timer(IMT) register value,
|
||||
* use lower 16 bit for rx and higher 16 bit for Tx. We do a
|
||||
* left shift by 1, because IMT resolution timer is 2usecs.
|
||||
* Hence the value given by the register is multiplied by 2 to
|
||||
* get the actual time in usecs.
|
||||
*/
|
||||
ec->tx_coalesce_usecs = (((reg_val >> 16) & 0xffff) << 1);
|
||||
ec->rx_coalesce_usecs = ((reg_val & 0xffff) << 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_set_coalesce
|
||||
* set interrupt mitigation
|
||||
*/
|
||||
static int edma_set_coalesce(struct net_device *netdev,
|
||||
struct ethtool_coalesce *ec)
|
||||
{
|
||||
if (ec->tx_coalesce_usecs)
|
||||
edma_change_tx_coalesce(ec->tx_coalesce_usecs);
|
||||
if (ec->rx_coalesce_usecs)
|
||||
edma_change_rx_coalesce(ec->rx_coalesce_usecs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_set_priv_flags()
|
||||
* Set EDMA private flags
|
||||
*/
|
||||
static int edma_set_priv_flags(struct net_device *netdev, u32 flags)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_get_priv_flags()
|
||||
* get edma driver flags
|
||||
*/
|
||||
static u32 edma_get_priv_flags(struct net_device *netdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_get_ringparam()
|
||||
* get ring size
|
||||
*/
|
||||
static void edma_get_ringparam(struct net_device *netdev,
|
||||
struct ethtool_ringparam *ring)
|
||||
{
|
||||
struct edma_adapter *adapter = netdev_priv(netdev);
|
||||
struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
|
||||
|
||||
ring->tx_max_pending = edma_cinfo->tx_ring_count;
|
||||
ring->rx_max_pending = edma_cinfo->rx_ring_count;
|
||||
}
|
||||
|
||||
/* Ethtool operations
|
||||
*/
|
||||
static const struct ethtool_ops edma_ethtool_ops = {
|
||||
.get_drvinfo = &edma_get_drvinfo,
|
||||
.get_link = ðtool_op_get_link,
|
||||
.get_msglevel = &edma_get_msglevel,
|
||||
.nway_reset = &edma_nway_reset,
|
||||
.get_wol = &edma_get_wol,
|
||||
.get_link_ksettings = &edma_get_settings,
|
||||
.set_link_ksettings = &edma_set_settings,
|
||||
.get_strings = &edma_get_strings,
|
||||
.get_sset_count = &edma_get_strset_count,
|
||||
.get_ethtool_stats = &edma_get_ethtool_stats,
|
||||
.get_coalesce = &edma_get_coalesce,
|
||||
.set_coalesce = &edma_set_coalesce,
|
||||
.get_priv_flags = edma_get_priv_flags,
|
||||
.set_priv_flags = edma_set_priv_flags,
|
||||
.get_ringparam = edma_get_ringparam,
|
||||
};
|
||||
|
||||
/* edma_set_ethtool_ops
|
||||
* Set ethtool operations
|
||||
*/
|
||||
void edma_set_ethtool_ops(struct net_device *netdev)
|
||||
{
|
||||
netdev->ethtool_ops = &edma_ethtool_ops;
|
||||
}
|
||||
@ -0,0 +1,389 @@
|
||||
/*
|
||||
* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all copies.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
|
||||
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _ESS_EDMA_H_
|
||||
#define _ESS_EDMA_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct edma_adapter;
|
||||
struct edma_hw;
|
||||
|
||||
/* register definition */
|
||||
#define EDMA_REG_MAS_CTRL 0x0
|
||||
#define EDMA_REG_TIMEOUT_CTRL 0x004
|
||||
#define EDMA_REG_DBG0 0x008
|
||||
#define EDMA_REG_DBG1 0x00C
|
||||
#define EDMA_REG_SW_CTRL0 0x100
|
||||
#define EDMA_REG_SW_CTRL1 0x104
|
||||
|
||||
/* Interrupt Status Register */
|
||||
#define EDMA_REG_RX_ISR 0x200
|
||||
#define EDMA_REG_TX_ISR 0x208
|
||||
#define EDMA_REG_MISC_ISR 0x210
|
||||
#define EDMA_REG_WOL_ISR 0x218
|
||||
|
||||
#define EDMA_MISC_ISR_RX_URG_Q(x) (1 << x)
|
||||
|
||||
#define EDMA_MISC_ISR_AXIR_TIMEOUT 0x00000100
|
||||
#define EDMA_MISC_ISR_AXIR_ERR 0x00000200
|
||||
#define EDMA_MISC_ISR_TXF_DEAD 0x00000400
|
||||
#define EDMA_MISC_ISR_AXIW_ERR 0x00000800
|
||||
#define EDMA_MISC_ISR_AXIW_TIMEOUT 0x00001000
|
||||
|
||||
#define EDMA_WOL_ISR 0x00000001
|
||||
|
||||
/* Interrupt Mask Register */
|
||||
#define EDMA_REG_MISC_IMR 0x214
|
||||
#define EDMA_REG_WOL_IMR 0x218
|
||||
|
||||
#define EDMA_RX_IMR_NORMAL_MASK 0x1
|
||||
#define EDMA_TX_IMR_NORMAL_MASK 0x1
|
||||
#define EDMA_MISC_IMR_NORMAL_MASK 0x80001FFF
|
||||
#define EDMA_WOL_IMR_NORMAL_MASK 0x1
|
||||
|
||||
/* Edma receive consumer index */
|
||||
#define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
|
||||
/* Edma transmit consumer index */
|
||||
#define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
|
||||
|
||||
/* IRQ Moderator Initial Timer Register */
|
||||
#define EDMA_REG_IRQ_MODRT_TIMER_INIT 0x280
|
||||
#define EDMA_IRQ_MODRT_TIMER_MASK 0xFFFF
|
||||
#define EDMA_IRQ_MODRT_RX_TIMER_SHIFT 0
|
||||
#define EDMA_IRQ_MODRT_TX_TIMER_SHIFT 16
|
||||
|
||||
/* Interrupt Control Register */
|
||||
#define EDMA_REG_INTR_CTRL 0x284
|
||||
#define EDMA_INTR_CLR_TYP_SHIFT 0
|
||||
#define EDMA_INTR_SW_IDX_W_TYP_SHIFT 1
|
||||
#define EDMA_INTR_CLEAR_TYPE_W1 0
|
||||
#define EDMA_INTR_CLEAR_TYPE_R 1
|
||||
|
||||
/* RX Interrupt Mask Register */
|
||||
#define EDMA_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* TX Interrupt mask register */
|
||||
#define EDMA_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* Load Ptr Register
|
||||
* Software sets this bit after the initialization of the head and tail
|
||||
*/
|
||||
#define EDMA_REG_TX_SRAM_PART 0x400
|
||||
#define EDMA_LOAD_PTR_SHIFT 16
|
||||
|
||||
/* TXQ Control Register */
|
||||
#define EDMA_REG_TXQ_CTRL 0x404
|
||||
#define EDMA_TXQ_CTRL_IP_OPTION_EN 0x10
|
||||
#define EDMA_TXQ_CTRL_TXQ_EN 0x20
|
||||
#define EDMA_TXQ_CTRL_ENH_MODE 0x40
|
||||
#define EDMA_TXQ_CTRL_LS_8023_EN 0x80
|
||||
#define EDMA_TXQ_CTRL_TPD_BURST_EN 0x100
|
||||
#define EDMA_TXQ_CTRL_LSO_BREAK_EN 0x200
|
||||
#define EDMA_TXQ_NUM_TPD_BURST_MASK 0xF
|
||||
#define EDMA_TXQ_TXF_BURST_NUM_MASK 0xFFFF
|
||||
#define EDMA_TXQ_NUM_TPD_BURST_SHIFT 0
|
||||
#define EDMA_TXQ_TXF_BURST_NUM_SHIFT 16
|
||||
|
||||
#define EDMA_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
|
||||
#define EDMA_TXF_WATER_MARK_MASK 0x0FFF
|
||||
#define EDMA_TXF_LOW_WATER_MARK_SHIFT 0
|
||||
#define EDMA_TXF_HIGH_WATER_MARK_SHIFT 16
|
||||
#define EDMA_TXQ_CTRL_BURST_MODE_EN 0x80000000
|
||||
|
||||
/* WRR Control Register */
|
||||
#define EDMA_REG_WRR_CTRL_Q0_Q3 0x40c
|
||||
#define EDMA_REG_WRR_CTRL_Q4_Q7 0x410
|
||||
#define EDMA_REG_WRR_CTRL_Q8_Q11 0x414
|
||||
#define EDMA_REG_WRR_CTRL_Q12_Q15 0x418
|
||||
|
||||
/* Weight round robin(WRR), it takes queue as input, and computes
|
||||
* starting bits where we need to write the weight for a particular
|
||||
* queue
|
||||
*/
|
||||
#define EDMA_WRR_SHIFT(x) (((x) * 5) % 20)
|
||||
|
||||
/* Tx Descriptor Control Register */
|
||||
#define EDMA_REG_TPD_RING_SIZE 0x41C
|
||||
#define EDMA_TPD_RING_SIZE_SHIFT 0
|
||||
#define EDMA_TPD_RING_SIZE_MASK 0xFFFF
|
||||
|
||||
/* Transmit descriptor base address */
|
||||
#define EDMA_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* TPD Index Register */
|
||||
#define EDMA_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
#define EDMA_TPD_PROD_IDX_BITS 0x0000FFFF
|
||||
#define EDMA_TPD_CONS_IDX_BITS 0xFFFF0000
|
||||
#define EDMA_TPD_PROD_IDX_MASK 0xFFFF
|
||||
#define EDMA_TPD_CONS_IDX_MASK 0xFFFF
|
||||
#define EDMA_TPD_PROD_IDX_SHIFT 0
|
||||
#define EDMA_TPD_CONS_IDX_SHIFT 16
|
||||
|
||||
/* TX Virtual Queue Mapping Control Register */
|
||||
#define EDMA_REG_VQ_CTRL0 0x4A0
|
||||
#define EDMA_REG_VQ_CTRL1 0x4A4
|
||||
|
||||
/* Virtual QID shift, it takes queue as input, and computes
|
||||
* Virtual QID position in virtual qid control register
|
||||
*/
|
||||
#define EDMA_VQ_ID_SHIFT(i) (((i) * 3) % 24)
|
||||
|
||||
/* Virtual Queue Default Value */
|
||||
#define EDMA_VQ_REG_VALUE 0x240240
|
||||
|
||||
/* Tx side Port Interface Control Register */
|
||||
#define EDMA_REG_PORT_CTRL 0x4A8
|
||||
#define EDMA_PAD_EN_SHIFT 15
|
||||
|
||||
/* Tx side VLAN Configuration Register */
|
||||
#define EDMA_REG_VLAN_CFG 0x4AC
|
||||
|
||||
#define EDMA_TX_CVLAN 16
|
||||
#define EDMA_TX_INS_CVLAN 17
|
||||
#define EDMA_TX_CVLAN_TAG_SHIFT 0
|
||||
|
||||
#define EDMA_TX_SVLAN 14
|
||||
#define EDMA_TX_INS_SVLAN 15
|
||||
#define EDMA_TX_SVLAN_TAG_SHIFT 16
|
||||
|
||||
/* Tx Queue Packet Statistic Register */
|
||||
#define EDMA_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
|
||||
|
||||
#define EDMA_TX_STAT_PKT_MASK 0xFFFFFF
|
||||
|
||||
/* Tx Queue Byte Statistic Register */
|
||||
#define EDMA_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
|
||||
|
||||
/* Load Balance Based Ring Offset Register */
|
||||
#define EDMA_REG_LB_RING 0x800
|
||||
#define EDMA_LB_RING_ENTRY_MASK 0xff
|
||||
#define EDMA_LB_RING_ID_MASK 0x7
|
||||
#define EDMA_LB_RING_PROFILE_ID_MASK 0x3
|
||||
#define EDMA_LB_RING_ENTRY_BIT_OFFSET 8
|
||||
#define EDMA_LB_RING_ID_OFFSET 0
|
||||
#define EDMA_LB_RING_PROFILE_ID_OFFSET 3
|
||||
#define EDMA_LB_REG_VALUE 0x6040200
|
||||
|
||||
/* Load Balance Priority Mapping Register */
|
||||
#define EDMA_REG_LB_PRI_START 0x804
|
||||
#define EDMA_REG_LB_PRI_END 0x810
|
||||
#define EDMA_LB_PRI_REG_INC 4
|
||||
#define EDMA_LB_PRI_ENTRY_BIT_OFFSET 4
|
||||
#define EDMA_LB_PRI_ENTRY_MASK 0xf
|
||||
|
||||
/* RSS Priority Mapping Register */
|
||||
#define EDMA_REG_RSS_PRI 0x820
|
||||
#define EDMA_RSS_PRI_ENTRY_MASK 0xf
|
||||
#define EDMA_RSS_RING_ID_MASK 0x7
|
||||
#define EDMA_RSS_PRI_ENTRY_BIT_OFFSET 4
|
||||
|
||||
/* RSS Indirection Register */
|
||||
#define EDMA_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
|
||||
#define EDMA_NUM_IDT 16
|
||||
#define EDMA_RSS_IDT_VALUE 0x64206420
|
||||
|
||||
/* Default RSS Ring Register */
|
||||
#define EDMA_REG_DEF_RSS 0x890
|
||||
#define EDMA_DEF_RSS_MASK 0x7
|
||||
|
||||
/* RSS Hash Function Type Register */
|
||||
#define EDMA_REG_RSS_TYPE 0x894
|
||||
#define EDMA_RSS_TYPE_NONE 0x01
|
||||
#define EDMA_RSS_TYPE_IPV4TCP 0x02
|
||||
#define EDMA_RSS_TYPE_IPV6_TCP 0x04
|
||||
#define EDMA_RSS_TYPE_IPV4_UDP 0x08
|
||||
#define EDMA_RSS_TYPE_IPV6UDP 0x10
|
||||
#define EDMA_RSS_TYPE_IPV4 0x20
|
||||
#define EDMA_RSS_TYPE_IPV6 0x40
|
||||
#define EDMA_RSS_HASH_MODE_MASK 0x7f
|
||||
|
||||
#define EDMA_REG_RSS_HASH_VALUE 0x8C0
|
||||
|
||||
#define EDMA_REG_RSS_TYPE_RESULT 0x8C4
|
||||
|
||||
#define EDMA_HASH_TYPE_START 0
|
||||
#define EDMA_HASH_TYPE_END 5
|
||||
#define EDMA_HASH_TYPE_SHIFT 12
|
||||
|
||||
#define EDMA_RFS_FLOW_ENTRIES 1024
|
||||
#define EDMA_RFS_FLOW_ENTRIES_MASK (EDMA_RFS_FLOW_ENTRIES - 1)
|
||||
#define EDMA_RFS_EXPIRE_COUNT_PER_CALL 128
|
||||
|
||||
/* RFD Base Address Register */
|
||||
#define EDMA_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* RFD Index Register */
|
||||
#define EDMA_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2))
|
||||
|
||||
#define EDMA_RFD_PROD_IDX_BITS 0x00000FFF
|
||||
#define EDMA_RFD_CONS_IDX_BITS 0x0FFF0000
|
||||
#define EDMA_RFD_PROD_IDX_MASK 0xFFF
|
||||
#define EDMA_RFD_CONS_IDX_MASK 0xFFF
|
||||
#define EDMA_RFD_PROD_IDX_SHIFT 0
|
||||
#define EDMA_RFD_CONS_IDX_SHIFT 16
|
||||
|
||||
/* Rx Descriptor Control Register */
|
||||
#define EDMA_REG_RX_DESC0 0xA10
|
||||
#define EDMA_RFD_RING_SIZE_MASK 0xFFF
|
||||
#define EDMA_RX_BUF_SIZE_MASK 0xFFFF
|
||||
#define EDMA_RFD_RING_SIZE_SHIFT 0
|
||||
#define EDMA_RX_BUF_SIZE_SHIFT 16
|
||||
|
||||
#define EDMA_REG_RX_DESC1 0xA14
|
||||
#define EDMA_RXQ_RFD_BURST_NUM_MASK 0x3F
|
||||
#define EDMA_RXQ_RFD_PF_THRESH_MASK 0x1F
|
||||
#define EDMA_RXQ_RFD_LOW_THRESH_MASK 0xFFF
|
||||
#define EDMA_RXQ_RFD_BURST_NUM_SHIFT 0
|
||||
#define EDMA_RXQ_RFD_PF_THRESH_SHIFT 8
|
||||
#define EDMA_RXQ_RFD_LOW_THRESH_SHIFT 16
|
||||
|
||||
/* RXQ Control Register */
|
||||
#define EDMA_REG_RXQ_CTRL 0xA18
|
||||
#define EDMA_FIFO_THRESH_TYPE_SHIF 0
|
||||
#define EDMA_FIFO_THRESH_128_BYTE 0x0
|
||||
#define EDMA_FIFO_THRESH_64_BYTE 0x1
|
||||
#define EDMA_RXQ_CTRL_RMV_VLAN 0x00000002
|
||||
#define EDMA_RXQ_CTRL_EN 0x0000FF00
|
||||
|
||||
/* AXI Burst Size Config */
|
||||
#define EDMA_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
|
||||
#define EDMA_AXIW_MAXWRSIZE_VALUE 0x0
|
||||
|
||||
/* Rx Statistics Register */
|
||||
#define EDMA_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
|
||||
#define EDMA_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* WoL Pattern Length Register */
|
||||
#define EDMA_REG_WOL_PATTERN_LEN0 0xC00
|
||||
#define EDMA_WOL_PT_LEN_MASK 0xFF
|
||||
#define EDMA_WOL_PT0_LEN_SHIFT 0
|
||||
#define EDMA_WOL_PT1_LEN_SHIFT 8
|
||||
#define EDMA_WOL_PT2_LEN_SHIFT 16
|
||||
#define EDMA_WOL_PT3_LEN_SHIFT 24
|
||||
|
||||
#define EDMA_REG_WOL_PATTERN_LEN1 0xC04
|
||||
#define EDMA_WOL_PT4_LEN_SHIFT 0
|
||||
#define EDMA_WOL_PT5_LEN_SHIFT 8
|
||||
#define EDMA_WOL_PT6_LEN_SHIFT 16
|
||||
|
||||
/* WoL Control Register */
|
||||
#define EDMA_REG_WOL_CTRL 0xC08
|
||||
#define EDMA_WOL_WK_EN 0x00000001
|
||||
#define EDMA_WOL_MG_EN 0x00000002
|
||||
#define EDMA_WOL_PT0_EN 0x00000004
|
||||
#define EDMA_WOL_PT1_EN 0x00000008
|
||||
#define EDMA_WOL_PT2_EN 0x00000010
|
||||
#define EDMA_WOL_PT3_EN 0x00000020
|
||||
#define EDMA_WOL_PT4_EN 0x00000040
|
||||
#define EDMA_WOL_PT5_EN 0x00000080
|
||||
#define EDMA_WOL_PT6_EN 0x00000100
|
||||
|
||||
/* MAC Control Register */
|
||||
#define EDMA_REG_MAC_CTRL0 0xC20
|
||||
#define EDMA_REG_MAC_CTRL1 0xC24
|
||||
|
||||
/* WoL Pattern Register */
|
||||
#define EDMA_REG_WOL_PATTERN_START 0x5000
|
||||
#define EDMA_PATTERN_PART_REG_OFFSET 0x40
|
||||
|
||||
|
||||
/* TX descriptor fields */
|
||||
#define EDMA_TPD_HDR_SHIFT 0
|
||||
#define EDMA_TPD_PPPOE_EN 0x00000100
|
||||
#define EDMA_TPD_IP_CSUM_EN 0x00000200
|
||||
#define EDMA_TPD_TCP_CSUM_EN 0x0000400
|
||||
#define EDMA_TPD_UDP_CSUM_EN 0x00000800
|
||||
#define EDMA_TPD_CUSTOM_CSUM_EN 0x00000C00
|
||||
#define EDMA_TPD_LSO_EN 0x00001000
|
||||
#define EDMA_TPD_LSO_V2_EN 0x00002000
|
||||
#define EDMA_TPD_IPV4_EN 0x00010000
|
||||
#define EDMA_TPD_MSS_MASK 0x1FFF
|
||||
#define EDMA_TPD_MSS_SHIFT 18
|
||||
#define EDMA_TPD_CUSTOM_CSUM_SHIFT 18
|
||||
|
||||
/* RRD descriptor fields */
|
||||
#define EDMA_RRD_NUM_RFD_MASK 0x000F
|
||||
#define EDMA_RRD_SVLAN 0x8000
|
||||
#define EDMA_RRD_FLOW_COOKIE_MASK 0x07FF;
|
||||
|
||||
#define EDMA_RRD_PKT_SIZE_MASK 0x3FFF
|
||||
#define EDMA_RRD_CSUM_FAIL_MASK 0xC000
|
||||
#define EDMA_RRD_CVLAN 0x0001
|
||||
#define EDMA_RRD_DESC_VALID 0x8000
|
||||
|
||||
#define EDMA_RRD_PRIORITY_SHIFT 4
|
||||
#define EDMA_RRD_PRIORITY_MASK 0x7
|
||||
#define EDMA_RRD_PORT_TYPE_SHIFT 7
|
||||
#define EDMA_RRD_PORT_TYPE_MASK 0x1F
|
||||
|
||||
#define ESS_RGMII_CTRL 0x0004
|
||||
|
||||
/* Port status registers */
|
||||
#define ESS_PORT0_STATUS 0x007C
|
||||
#define ESS_PORT1_STATUS 0x0080
|
||||
#define ESS_PORT2_STATUS 0x0084
|
||||
#define ESS_PORT3_STATUS 0x0088
|
||||
#define ESS_PORT4_STATUS 0x008C
|
||||
#define ESS_PORT5_STATUS 0x0090
|
||||
|
||||
#define ESS_PORT_STATUS_HDX_FLOW_CTL 0x80
|
||||
#define ESS_PORT_STATUS_DUPLEX_MODE 0x40
|
||||
#define ESS_PORT_STATUS_RX_FLOW_EN 0x20
|
||||
#define ESS_PORT_STATUS_TX_FLOW_EN 0x10
|
||||
#define ESS_PORT_STATUS_RX_MAC_EN 0x08
|
||||
#define ESS_PORT_STATUS_TX_MAC_EN 0x04
|
||||
#define ESS_PORT_STATUS_SPEED_INV 0x03
|
||||
#define ESS_PORT_STATUS_SPEED_1000 0x02
|
||||
#define ESS_PORT_STATUS_SPEED_100 0x01
|
||||
#define ESS_PORT_STATUS_SPEED_10 0x00
|
||||
|
||||
#define ESS_PORT_1G_FDX (ESS_PORT_STATUS_DUPLEX_MODE | ESS_PORT_STATUS_RX_FLOW_EN | \
|
||||
ESS_PORT_STATUS_TX_FLOW_EN | ESS_PORT_STATUS_RX_MAC_EN | \
|
||||
ESS_PORT_STATUS_TX_MAC_EN | ESS_PORT_STATUS_SPEED_1000)
|
||||
|
||||
#define PHY_STATUS_REG 0x11
|
||||
#define PHY_STATUS_SPEED 0xC000
|
||||
#define PHY_STATUS_SPEED_SHIFT 14
|
||||
#define PHY_STATUS_DUPLEX 0x2000
|
||||
#define PHY_STATUS_DUPLEX_SHIFT 13
|
||||
#define PHY_STATUS_SPEED_DUPLEX_RESOLVED 0x0800
|
||||
#define PHY_STATUS_CARRIER 0x0400
|
||||
#define PHY_STATUS_CARRIER_SHIFT 10
|
||||
|
||||
/* Port lookup control registers */
|
||||
#define ESS_PORT0_LOOKUP_CTRL 0x0660
|
||||
#define ESS_PORT1_LOOKUP_CTRL 0x066C
|
||||
#define ESS_PORT2_LOOKUP_CTRL 0x0678
|
||||
#define ESS_PORT3_LOOKUP_CTRL 0x0684
|
||||
#define ESS_PORT4_LOOKUP_CTRL 0x0690
|
||||
#define ESS_PORT5_LOOKUP_CTRL 0x069C
|
||||
|
||||
#define ESS_PORT0_HEADER_CTRL 0x009C
|
||||
|
||||
#define ESS_PORTS_ALL 0x3f
|
||||
|
||||
#define ESS_FWD_CTRL1 0x0624
|
||||
#define ESS_FWD_CTRL1_UC_FLOOD BITS(0, 7)
|
||||
#define ESS_FWD_CTRL1_UC_FLOOD_S 0
|
||||
#define ESS_FWD_CTRL1_MC_FLOOD BITS(8, 7)
|
||||
#define ESS_FWD_CTRL1_MC_FLOOD_S 8
|
||||
#define ESS_FWD_CTRL1_BC_FLOOD BITS(16, 7)
|
||||
#define ESS_FWD_CTRL1_BC_FLOOD_S 16
|
||||
#define ESS_FWD_CTRL1_IGMP BITS(24, 7)
|
||||
#define ESS_FWD_CTRL1_IGMP_S 24
|
||||
|
||||
#endif /* _ESS_EDMA_H_ */
|
||||
@ -0,0 +1,111 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// Copyright (c) 2019 Mantas Pucka <mantas@8devices.com>
|
||||
// Copyright (c) 2019 Robert Marko <robimarko@gmail.com>
|
||||
//
|
||||
// Driver for IPQ4019 SD/MMC controller's I/O LDO voltage regulator
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/regulator/driver.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/regulator/of_regulator.h>
|
||||
|
||||
static const unsigned int ipq4019_vmmc_voltages[] = {
|
||||
1500000, 1800000, 2500000, 3000000,
|
||||
};
|
||||
|
||||
static struct regulator_ops ipq4019_regulator_voltage_ops = {
|
||||
.list_voltage = regulator_list_voltage_table,
|
||||
.get_voltage_sel = regulator_get_voltage_sel_regmap,
|
||||
.set_voltage_sel = regulator_set_voltage_sel_regmap,
|
||||
};
|
||||
|
||||
static struct regulator_desc vmmc_regulator = {
|
||||
.name = "vmmcq",
|
||||
.ops = &ipq4019_regulator_voltage_ops,
|
||||
.type = REGULATOR_VOLTAGE,
|
||||
.owner = THIS_MODULE,
|
||||
.volt_table = ipq4019_vmmc_voltages,
|
||||
.n_voltages = ARRAY_SIZE(ipq4019_vmmc_voltages),
|
||||
.vsel_reg = 0,
|
||||
.vsel_mask = 0x3,
|
||||
};
|
||||
|
||||
const struct regmap_config ipq4019_vmmcq_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
};
|
||||
|
||||
static int ipq4019_regulator_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct regulator_init_data *init_data;
|
||||
struct regulator_config cfg = {};
|
||||
struct regulator_dev *rdev;
|
||||
struct resource *res;
|
||||
struct regmap *rmap;
|
||||
void __iomem *base;
|
||||
|
||||
init_data = of_get_regulator_init_data(dev, dev->of_node,
|
||||
&vmmc_regulator);
|
||||
if (!init_data)
|
||||
return -EINVAL;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
rmap = devm_regmap_init_mmio(dev, base, &ipq4019_vmmcq_regmap_config);
|
||||
if (IS_ERR(rmap))
|
||||
return PTR_ERR(rmap);
|
||||
|
||||
cfg.dev = dev;
|
||||
cfg.init_data = init_data;
|
||||
cfg.of_node = dev->of_node;
|
||||
cfg.regmap = rmap;
|
||||
|
||||
rdev = devm_regulator_register(dev, &vmmc_regulator, &cfg);
|
||||
if (IS_ERR(rdev)) {
|
||||
dev_err(dev, "Failed to register regulator: %ld\n",
|
||||
PTR_ERR(rdev));
|
||||
return PTR_ERR(rdev);
|
||||
}
|
||||
platform_set_drvdata(pdev, rdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ipq4019_regulator_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct regulator_dev *rdev = platform_get_drvdata(pdev);
|
||||
|
||||
regulator_unregister(rdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id regulator_ipq4019_of_match[] = {
|
||||
{ .compatible = "qcom,ipq4019-vqmmc-regulator", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver ipq4019_regulator_driver = {
|
||||
.probe = ipq4019_regulator_probe,
|
||||
.remove = ipq4019_regulator_remove,
|
||||
.driver = {
|
||||
.name = "regulator-vqmmc-ipq4019",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(regulator_ipq4019_of_match),
|
||||
},
|
||||
};
|
||||
module_platform_driver(ipq4019_regulator_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Mantas Pucka <mantas@8devices.com>");
|
||||
MODULE_DESCRIPTION("IPQ4019 VQMMC voltage regulator");
|
||||
@ -0,0 +1,31 @@
|
||||
From: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Subject: [PATCH] crypto: qce - add CRYPTO_ALG_KERN_DRIVER_ONLY flag
|
||||
|
||||
Set the CRYPTO_ALG_KERN_DRIVER_ONLY flag to all algorithms exposed by
|
||||
the qce driver, since they are all hardware accelerated, accessible
|
||||
through a kernel driver only, and not available directly to userspace.
|
||||
|
||||
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
|
||||
--- a/drivers/crypto/qce/ablkcipher.c
|
||||
+++ b/drivers/crypto/qce/ablkcipher.c
|
||||
@@ -380,7 +380,7 @@ static int qce_ablkcipher_register_one(c
|
||||
|
||||
alg->cra_priority = 300;
|
||||
alg->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC |
|
||||
- CRYPTO_ALG_NEED_FALLBACK;
|
||||
+ CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY;
|
||||
alg->cra_ctxsize = sizeof(struct qce_cipher_ctx);
|
||||
alg->cra_alignmask = 0;
|
||||
alg->cra_type = &crypto_ablkcipher_type;
|
||||
--- a/drivers/crypto/qce/sha.c
|
||||
+++ b/drivers/crypto/qce/sha.c
|
||||
@@ -495,7 +495,7 @@ static int qce_ahash_register_one(const
|
||||
base = &alg->halg.base;
|
||||
base->cra_blocksize = def->blocksize;
|
||||
base->cra_priority = 300;
|
||||
- base->cra_flags = CRYPTO_ALG_ASYNC;
|
||||
+ base->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
|
||||
base->cra_ctxsize = sizeof(struct qce_sha_ctx);
|
||||
base->cra_alignmask = 0;
|
||||
base->cra_module = THIS_MODULE;
|
||||
@ -0,0 +1,993 @@
|
||||
From f441873642eebf20566c18d2966a8cd4b433ec1c Mon Sep 17 00:00:00 2001
|
||||
From: Ard Biesheuvel <ardb@kernel.org>
|
||||
Date: Tue, 5 Nov 2019 14:28:17 +0100
|
||||
Subject: [PATCH] crypto: qce - switch to skcipher API
|
||||
|
||||
Commit 7a7ffe65c8c5 ("crypto: skcipher - Add top-level skcipher interface")
|
||||
dated 20 august 2015 introduced the new skcipher API which is supposed to
|
||||
replace both blkcipher and ablkcipher. While all consumers of the API have
|
||||
been converted long ago, some producers of the ablkcipher remain, forcing
|
||||
us to keep the ablkcipher support routines alive, along with the matching
|
||||
code to expose [a]blkciphers via the skcipher API.
|
||||
|
||||
So switch this driver to the skcipher API, allowing us to finally drop the
|
||||
blkcipher code in the near future.
|
||||
|
||||
Reviewed-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
|
||||
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
|
||||
Backported-to-4.19-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
|
||||
--- a/drivers/crypto/qce/Makefile
|
||||
+++ b/drivers/crypto/qce/Makefile
|
||||
@@ -4,4 +4,4 @@ qcrypto-objs := core.o \
|
||||
common.o \
|
||||
dma.o \
|
||||
sha.o \
|
||||
- ablkcipher.o
|
||||
+ skcipher.o
|
||||
--- a/drivers/crypto/qce/cipher.h
|
||||
+++ b/drivers/crypto/qce/cipher.h
|
||||
@@ -45,12 +45,12 @@ struct qce_cipher_reqctx {
|
||||
unsigned int cryptlen;
|
||||
};
|
||||
|
||||
-static inline struct qce_alg_template *to_cipher_tmpl(struct crypto_tfm *tfm)
|
||||
+static inline struct qce_alg_template *to_cipher_tmpl(struct crypto_skcipher *tfm)
|
||||
{
|
||||
- struct crypto_alg *alg = tfm->__crt_alg;
|
||||
- return container_of(alg, struct qce_alg_template, alg.crypto);
|
||||
+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
|
||||
+ return container_of(alg, struct qce_alg_template, alg.skcipher);
|
||||
}
|
||||
|
||||
-extern const struct qce_algo_ops ablkcipher_ops;
|
||||
+extern const struct qce_algo_ops skcipher_ops;
|
||||
|
||||
#endif /* _CIPHER_H_ */
|
||||
--- a/drivers/crypto/qce/common.c
|
||||
+++ b/drivers/crypto/qce/common.c
|
||||
@@ -304,13 +304,13 @@ go_proc:
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int qce_setup_regs_ablkcipher(struct crypto_async_request *async_req,
|
||||
+static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
|
||||
u32 totallen, u32 offset)
|
||||
{
|
||||
- struct ablkcipher_request *req = ablkcipher_request_cast(async_req);
|
||||
- struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req);
|
||||
+ struct skcipher_request *req = skcipher_request_cast(async_req);
|
||||
+ struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
|
||||
struct qce_cipher_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
|
||||
- struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm);
|
||||
+ struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req));
|
||||
struct qce_device *qce = tmpl->qce;
|
||||
__be32 enckey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(__be32)] = {0};
|
||||
__be32 enciv[QCE_MAX_IV_SIZE / sizeof(__be32)] = {0};
|
||||
@@ -389,8 +389,8 @@ int qce_start(struct crypto_async_reques
|
||||
u32 offset)
|
||||
{
|
||||
switch (type) {
|
||||
- case CRYPTO_ALG_TYPE_ABLKCIPHER:
|
||||
- return qce_setup_regs_ablkcipher(async_req, totallen, offset);
|
||||
+ case CRYPTO_ALG_TYPE_SKCIPHER:
|
||||
+ return qce_setup_regs_skcipher(async_req, totallen, offset);
|
||||
case CRYPTO_ALG_TYPE_AHASH:
|
||||
return qce_setup_regs_ahash(async_req, totallen, offset);
|
||||
default:
|
||||
--- a/drivers/crypto/qce/common.h
|
||||
+++ b/drivers/crypto/qce/common.h
|
||||
@@ -10,6 +10,7 @@
|
||||
#include <linux/types.h>
|
||||
#include <crypto/aes.h>
|
||||
#include <crypto/hash.h>
|
||||
+#include <crypto/internal/skcipher.h>
|
||||
|
||||
/* key size in bytes */
|
||||
#define QCE_SHA_HMAC_KEY_SIZE 64
|
||||
@@ -79,7 +80,7 @@ struct qce_alg_template {
|
||||
unsigned long alg_flags;
|
||||
const u32 *std_iv;
|
||||
union {
|
||||
- struct crypto_alg crypto;
|
||||
+ struct skcipher_alg skcipher;
|
||||
struct ahash_alg ahash;
|
||||
} alg;
|
||||
struct qce_device *qce;
|
||||
--- a/drivers/crypto/qce/core.c
|
||||
+++ b/drivers/crypto/qce/core.c
|
||||
@@ -22,7 +22,7 @@
|
||||
#define QCE_QUEUE_LENGTH 1
|
||||
|
||||
static const struct qce_algo_ops *qce_ops[] = {
|
||||
- &ablkcipher_ops,
|
||||
+ &skcipher_ops,
|
||||
&ahash_ops,
|
||||
};
|
||||
|
||||
--- a/drivers/crypto/qce/ablkcipher.c
|
||||
+++ /dev/null
|
||||
@@ -1,440 +0,0 @@
|
||||
-// SPDX-License-Identifier: GPL-2.0-only
|
||||
-/*
|
||||
- * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
|
||||
- */
|
||||
-
|
||||
-#include <linux/device.h>
|
||||
-#include <linux/interrupt.h>
|
||||
-#include <linux/types.h>
|
||||
-#include <crypto/aes.h>
|
||||
-#include <crypto/internal/des.h>
|
||||
-#include <crypto/internal/skcipher.h>
|
||||
-
|
||||
-#include "cipher.h"
|
||||
-
|
||||
-static LIST_HEAD(ablkcipher_algs);
|
||||
-
|
||||
-static void qce_ablkcipher_done(void *data)
|
||||
-{
|
||||
- struct crypto_async_request *async_req = data;
|
||||
- struct ablkcipher_request *req = ablkcipher_request_cast(async_req);
|
||||
- struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req);
|
||||
- struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm);
|
||||
- struct qce_device *qce = tmpl->qce;
|
||||
- enum dma_data_direction dir_src, dir_dst;
|
||||
- u32 status;
|
||||
- int error;
|
||||
- bool diff_dst;
|
||||
-
|
||||
- diff_dst = (req->src != req->dst) ? true : false;
|
||||
- dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;
|
||||
- dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;
|
||||
-
|
||||
- error = qce_dma_terminate_all(&qce->dma);
|
||||
- if (error)
|
||||
- dev_dbg(qce->dev, "ablkcipher dma termination error (%d)\n",
|
||||
- error);
|
||||
-
|
||||
- if (diff_dst)
|
||||
- dma_unmap_sg(qce->dev, rctx->src_sg, rctx->src_nents, dir_src);
|
||||
- dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
|
||||
-
|
||||
- sg_free_table(&rctx->dst_tbl);
|
||||
-
|
||||
- error = qce_check_status(qce, &status);
|
||||
- if (error < 0)
|
||||
- dev_dbg(qce->dev, "ablkcipher operation error (%x)\n", status);
|
||||
-
|
||||
- qce->async_req_done(tmpl->qce, error);
|
||||
-}
|
||||
-
|
||||
-static int
|
||||
-qce_ablkcipher_async_req_handle(struct crypto_async_request *async_req)
|
||||
-{
|
||||
- struct ablkcipher_request *req = ablkcipher_request_cast(async_req);
|
||||
- struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req);
|
||||
- struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
|
||||
- struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm);
|
||||
- struct qce_device *qce = tmpl->qce;
|
||||
- enum dma_data_direction dir_src, dir_dst;
|
||||
- struct scatterlist *sg;
|
||||
- bool diff_dst;
|
||||
- gfp_t gfp;
|
||||
- int ret;
|
||||
-
|
||||
- rctx->iv = req->info;
|
||||
- rctx->ivsize = crypto_ablkcipher_ivsize(ablkcipher);
|
||||
- rctx->cryptlen = req->nbytes;
|
||||
-
|
||||
- diff_dst = (req->src != req->dst) ? true : false;
|
||||
- dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;
|
||||
- dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;
|
||||
-
|
||||
- rctx->src_nents = sg_nents_for_len(req->src, req->nbytes);
|
||||
- if (diff_dst)
|
||||
- rctx->dst_nents = sg_nents_for_len(req->dst, req->nbytes);
|
||||
- else
|
||||
- rctx->dst_nents = rctx->src_nents;
|
||||
- if (rctx->src_nents < 0) {
|
||||
- dev_err(qce->dev, "Invalid numbers of src SG.\n");
|
||||
- return rctx->src_nents;
|
||||
- }
|
||||
- if (rctx->dst_nents < 0) {
|
||||
- dev_err(qce->dev, "Invalid numbers of dst SG.\n");
|
||||
- return -rctx->dst_nents;
|
||||
- }
|
||||
-
|
||||
- rctx->dst_nents += 1;
|
||||
-
|
||||
- gfp = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
|
||||
- GFP_KERNEL : GFP_ATOMIC;
|
||||
-
|
||||
- ret = sg_alloc_table(&rctx->dst_tbl, rctx->dst_nents, gfp);
|
||||
- if (ret)
|
||||
- return ret;
|
||||
-
|
||||
- sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
|
||||
-
|
||||
- sg = qce_sgtable_add(&rctx->dst_tbl, req->dst);
|
||||
- if (IS_ERR(sg)) {
|
||||
- ret = PTR_ERR(sg);
|
||||
- goto error_free;
|
||||
- }
|
||||
-
|
||||
- sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg);
|
||||
- if (IS_ERR(sg)) {
|
||||
- ret = PTR_ERR(sg);
|
||||
- goto error_free;
|
||||
- }
|
||||
-
|
||||
- sg_mark_end(sg);
|
||||
- rctx->dst_sg = rctx->dst_tbl.sgl;
|
||||
-
|
||||
- ret = dma_map_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
|
||||
- if (ret < 0)
|
||||
- goto error_free;
|
||||
-
|
||||
- if (diff_dst) {
|
||||
- ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, dir_src);
|
||||
- if (ret < 0)
|
||||
- goto error_unmap_dst;
|
||||
- rctx->src_sg = req->src;
|
||||
- } else {
|
||||
- rctx->src_sg = rctx->dst_sg;
|
||||
- }
|
||||
-
|
||||
- ret = qce_dma_prep_sgs(&qce->dma, rctx->src_sg, rctx->src_nents,
|
||||
- rctx->dst_sg, rctx->dst_nents,
|
||||
- qce_ablkcipher_done, async_req);
|
||||
- if (ret)
|
||||
- goto error_unmap_src;
|
||||
-
|
||||
- qce_dma_issue_pending(&qce->dma);
|
||||
-
|
||||
- ret = qce_start(async_req, tmpl->crypto_alg_type, req->nbytes, 0);
|
||||
- if (ret)
|
||||
- goto error_terminate;
|
||||
-
|
||||
- return 0;
|
||||
-
|
||||
-error_terminate:
|
||||
- qce_dma_terminate_all(&qce->dma);
|
||||
-error_unmap_src:
|
||||
- if (diff_dst)
|
||||
- dma_unmap_sg(qce->dev, req->src, rctx->src_nents, dir_src);
|
||||
-error_unmap_dst:
|
||||
- dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
|
||||
-error_free:
|
||||
- sg_free_table(&rctx->dst_tbl);
|
||||
- return ret;
|
||||
-}
|
||||
-
|
||||
-static int qce_ablkcipher_setkey(struct crypto_ablkcipher *ablk, const u8 *key,
|
||||
- unsigned int keylen)
|
||||
-{
|
||||
- struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablk);
|
||||
- struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
|
||||
- int ret;
|
||||
-
|
||||
- if (!key || !keylen)
|
||||
- return -EINVAL;
|
||||
-
|
||||
- switch (keylen) {
|
||||
- case AES_KEYSIZE_128:
|
||||
- case AES_KEYSIZE_256:
|
||||
- break;
|
||||
- default:
|
||||
- goto fallback;
|
||||
- }
|
||||
-
|
||||
- ctx->enc_keylen = keylen;
|
||||
- memcpy(ctx->enc_key, key, keylen);
|
||||
- return 0;
|
||||
-fallback:
|
||||
- ret = crypto_sync_skcipher_setkey(ctx->fallback, key, keylen);
|
||||
- if (!ret)
|
||||
- ctx->enc_keylen = keylen;
|
||||
- return ret;
|
||||
-}
|
||||
-
|
||||
-static int qce_des_setkey(struct crypto_ablkcipher *ablk, const u8 *key,
|
||||
- unsigned int keylen)
|
||||
-{
|
||||
- struct qce_cipher_ctx *ctx = crypto_ablkcipher_ctx(ablk);
|
||||
- int err;
|
||||
-
|
||||
- err = verify_ablkcipher_des_key(ablk, key);
|
||||
- if (err)
|
||||
- return err;
|
||||
-
|
||||
- ctx->enc_keylen = keylen;
|
||||
- memcpy(ctx->enc_key, key, keylen);
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
-static int qce_des3_setkey(struct crypto_ablkcipher *ablk, const u8 *key,
|
||||
- unsigned int keylen)
|
||||
-{
|
||||
- struct qce_cipher_ctx *ctx = crypto_ablkcipher_ctx(ablk);
|
||||
- int err;
|
||||
-
|
||||
- err = verify_ablkcipher_des3_key(ablk, key);
|
||||
- if (err)
|
||||
- return err;
|
||||
-
|
||||
- ctx->enc_keylen = keylen;
|
||||
- memcpy(ctx->enc_key, key, keylen);
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
-static int qce_ablkcipher_crypt(struct ablkcipher_request *req, int encrypt)
|
||||
-{
|
||||
- struct crypto_tfm *tfm =
|
||||
- crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req));
|
||||
- struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
|
||||
- struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req);
|
||||
- struct qce_alg_template *tmpl = to_cipher_tmpl(tfm);
|
||||
- int ret;
|
||||
-
|
||||
- rctx->flags = tmpl->alg_flags;
|
||||
- rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
|
||||
-
|
||||
- if (IS_AES(rctx->flags) && ctx->enc_keylen != AES_KEYSIZE_128 &&
|
||||
- ctx->enc_keylen != AES_KEYSIZE_256) {
|
||||
- SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
|
||||
-
|
||||
- skcipher_request_set_sync_tfm(subreq, ctx->fallback);
|
||||
- skcipher_request_set_callback(subreq, req->base.flags,
|
||||
- NULL, NULL);
|
||||
- skcipher_request_set_crypt(subreq, req->src, req->dst,
|
||||
- req->nbytes, req->info);
|
||||
- ret = encrypt ? crypto_skcipher_encrypt(subreq) :
|
||||
- crypto_skcipher_decrypt(subreq);
|
||||
- skcipher_request_zero(subreq);
|
||||
- return ret;
|
||||
- }
|
||||
-
|
||||
- return tmpl->qce->async_req_enqueue(tmpl->qce, &req->base);
|
||||
-}
|
||||
-
|
||||
-static int qce_ablkcipher_encrypt(struct ablkcipher_request *req)
|
||||
-{
|
||||
- return qce_ablkcipher_crypt(req, 1);
|
||||
-}
|
||||
-
|
||||
-static int qce_ablkcipher_decrypt(struct ablkcipher_request *req)
|
||||
-{
|
||||
- return qce_ablkcipher_crypt(req, 0);
|
||||
-}
|
||||
-
|
||||
-static int qce_ablkcipher_init(struct crypto_tfm *tfm)
|
||||
-{
|
||||
- struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
|
||||
-
|
||||
- memset(ctx, 0, sizeof(*ctx));
|
||||
- tfm->crt_ablkcipher.reqsize = sizeof(struct qce_cipher_reqctx);
|
||||
-
|
||||
- ctx->fallback = crypto_alloc_sync_skcipher(crypto_tfm_alg_name(tfm),
|
||||
- 0, CRYPTO_ALG_NEED_FALLBACK);
|
||||
- return PTR_ERR_OR_ZERO(ctx->fallback);
|
||||
-}
|
||||
-
|
||||
-static void qce_ablkcipher_exit(struct crypto_tfm *tfm)
|
||||
-{
|
||||
- struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
|
||||
-
|
||||
- crypto_free_sync_skcipher(ctx->fallback);
|
||||
-}
|
||||
-
|
||||
-struct qce_ablkcipher_def {
|
||||
- unsigned long flags;
|
||||
- const char *name;
|
||||
- const char *drv_name;
|
||||
- unsigned int blocksize;
|
||||
- unsigned int ivsize;
|
||||
- unsigned int min_keysize;
|
||||
- unsigned int max_keysize;
|
||||
-};
|
||||
-
|
||||
-static const struct qce_ablkcipher_def ablkcipher_def[] = {
|
||||
- {
|
||||
- .flags = QCE_ALG_AES | QCE_MODE_ECB,
|
||||
- .name = "ecb(aes)",
|
||||
- .drv_name = "ecb-aes-qce",
|
||||
- .blocksize = AES_BLOCK_SIZE,
|
||||
- .ivsize = AES_BLOCK_SIZE,
|
||||
- .min_keysize = AES_MIN_KEY_SIZE,
|
||||
- .max_keysize = AES_MAX_KEY_SIZE,
|
||||
- },
|
||||
- {
|
||||
- .flags = QCE_ALG_AES | QCE_MODE_CBC,
|
||||
- .name = "cbc(aes)",
|
||||
- .drv_name = "cbc-aes-qce",
|
||||
- .blocksize = AES_BLOCK_SIZE,
|
||||
- .ivsize = AES_BLOCK_SIZE,
|
||||
- .min_keysize = AES_MIN_KEY_SIZE,
|
||||
- .max_keysize = AES_MAX_KEY_SIZE,
|
||||
- },
|
||||
- {
|
||||
- .flags = QCE_ALG_AES | QCE_MODE_CTR,
|
||||
- .name = "ctr(aes)",
|
||||
- .drv_name = "ctr-aes-qce",
|
||||
- .blocksize = AES_BLOCK_SIZE,
|
||||
- .ivsize = AES_BLOCK_SIZE,
|
||||
- .min_keysize = AES_MIN_KEY_SIZE,
|
||||
- .max_keysize = AES_MAX_KEY_SIZE,
|
||||
- },
|
||||
- {
|
||||
- .flags = QCE_ALG_AES | QCE_MODE_XTS,
|
||||
- .name = "xts(aes)",
|
||||
- .drv_name = "xts-aes-qce",
|
||||
- .blocksize = AES_BLOCK_SIZE,
|
||||
- .ivsize = AES_BLOCK_SIZE,
|
||||
- .min_keysize = AES_MIN_KEY_SIZE,
|
||||
- .max_keysize = AES_MAX_KEY_SIZE,
|
||||
- },
|
||||
- {
|
||||
- .flags = QCE_ALG_DES | QCE_MODE_ECB,
|
||||
- .name = "ecb(des)",
|
||||
- .drv_name = "ecb-des-qce",
|
||||
- .blocksize = DES_BLOCK_SIZE,
|
||||
- .ivsize = 0,
|
||||
- .min_keysize = DES_KEY_SIZE,
|
||||
- .max_keysize = DES_KEY_SIZE,
|
||||
- },
|
||||
- {
|
||||
- .flags = QCE_ALG_DES | QCE_MODE_CBC,
|
||||
- .name = "cbc(des)",
|
||||
- .drv_name = "cbc-des-qce",
|
||||
- .blocksize = DES_BLOCK_SIZE,
|
||||
- .ivsize = DES_BLOCK_SIZE,
|
||||
- .min_keysize = DES_KEY_SIZE,
|
||||
- .max_keysize = DES_KEY_SIZE,
|
||||
- },
|
||||
- {
|
||||
- .flags = QCE_ALG_3DES | QCE_MODE_ECB,
|
||||
- .name = "ecb(des3_ede)",
|
||||
- .drv_name = "ecb-3des-qce",
|
||||
- .blocksize = DES3_EDE_BLOCK_SIZE,
|
||||
- .ivsize = 0,
|
||||
- .min_keysize = DES3_EDE_KEY_SIZE,
|
||||
- .max_keysize = DES3_EDE_KEY_SIZE,
|
||||
- },
|
||||
- {
|
||||
- .flags = QCE_ALG_3DES | QCE_MODE_CBC,
|
||||
- .name = "cbc(des3_ede)",
|
||||
- .drv_name = "cbc-3des-qce",
|
||||
- .blocksize = DES3_EDE_BLOCK_SIZE,
|
||||
- .ivsize = DES3_EDE_BLOCK_SIZE,
|
||||
- .min_keysize = DES3_EDE_KEY_SIZE,
|
||||
- .max_keysize = DES3_EDE_KEY_SIZE,
|
||||
- },
|
||||
-};
|
||||
-
|
||||
-static int qce_ablkcipher_register_one(const struct qce_ablkcipher_def *def,
|
||||
- struct qce_device *qce)
|
||||
-{
|
||||
- struct qce_alg_template *tmpl;
|
||||
- struct crypto_alg *alg;
|
||||
- int ret;
|
||||
-
|
||||
- tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL);
|
||||
- if (!tmpl)
|
||||
- return -ENOMEM;
|
||||
-
|
||||
- alg = &tmpl->alg.crypto;
|
||||
-
|
||||
- snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name);
|
||||
- snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
|
||||
- def->drv_name);
|
||||
-
|
||||
- alg->cra_blocksize = def->blocksize;
|
||||
- alg->cra_ablkcipher.ivsize = def->ivsize;
|
||||
- alg->cra_ablkcipher.min_keysize = def->min_keysize;
|
||||
- alg->cra_ablkcipher.max_keysize = def->max_keysize;
|
||||
- alg->cra_ablkcipher.setkey = IS_3DES(def->flags) ? qce_des3_setkey :
|
||||
- IS_DES(def->flags) ? qce_des_setkey :
|
||||
- qce_ablkcipher_setkey;
|
||||
- alg->cra_ablkcipher.encrypt = qce_ablkcipher_encrypt;
|
||||
- alg->cra_ablkcipher.decrypt = qce_ablkcipher_decrypt;
|
||||
-
|
||||
- alg->cra_priority = 300;
|
||||
- alg->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC |
|
||||
- CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY;
|
||||
- alg->cra_ctxsize = sizeof(struct qce_cipher_ctx);
|
||||
- alg->cra_alignmask = 0;
|
||||
- alg->cra_type = &crypto_ablkcipher_type;
|
||||
- alg->cra_module = THIS_MODULE;
|
||||
- alg->cra_init = qce_ablkcipher_init;
|
||||
- alg->cra_exit = qce_ablkcipher_exit;
|
||||
-
|
||||
- INIT_LIST_HEAD(&tmpl->entry);
|
||||
- tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_ABLKCIPHER;
|
||||
- tmpl->alg_flags = def->flags;
|
||||
- tmpl->qce = qce;
|
||||
-
|
||||
- ret = crypto_register_alg(alg);
|
||||
- if (ret) {
|
||||
- kfree(tmpl);
|
||||
- dev_err(qce->dev, "%s registration failed\n", alg->cra_name);
|
||||
- return ret;
|
||||
- }
|
||||
-
|
||||
- list_add_tail(&tmpl->entry, &ablkcipher_algs);
|
||||
- dev_dbg(qce->dev, "%s is registered\n", alg->cra_name);
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
-static void qce_ablkcipher_unregister(struct qce_device *qce)
|
||||
-{
|
||||
- struct qce_alg_template *tmpl, *n;
|
||||
-
|
||||
- list_for_each_entry_safe(tmpl, n, &ablkcipher_algs, entry) {
|
||||
- crypto_unregister_alg(&tmpl->alg.crypto);
|
||||
- list_del(&tmpl->entry);
|
||||
- kfree(tmpl);
|
||||
- }
|
||||
-}
|
||||
-
|
||||
-static int qce_ablkcipher_register(struct qce_device *qce)
|
||||
-{
|
||||
- int ret, i;
|
||||
-
|
||||
- for (i = 0; i < ARRAY_SIZE(ablkcipher_def); i++) {
|
||||
- ret = qce_ablkcipher_register_one(&ablkcipher_def[i], qce);
|
||||
- if (ret)
|
||||
- goto err;
|
||||
- }
|
||||
-
|
||||
- return 0;
|
||||
-err:
|
||||
- qce_ablkcipher_unregister(qce);
|
||||
- return ret;
|
||||
-}
|
||||
-
|
||||
-const struct qce_algo_ops ablkcipher_ops = {
|
||||
- .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
||||
- .register_algs = qce_ablkcipher_register,
|
||||
- .unregister_algs = qce_ablkcipher_unregister,
|
||||
- .async_req_handle = qce_ablkcipher_async_req_handle,
|
||||
-};
|
||||
--- /dev/null
|
||||
+++ b/drivers/crypto/qce/skcipher.c
|
||||
@@ -0,0 +1,440 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-only
|
||||
+/*
|
||||
+ * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/device.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/types.h>
|
||||
+#include <crypto/aes.h>
|
||||
+#include <crypto/internal/des.h>
|
||||
+#include <crypto/internal/skcipher.h>
|
||||
+
|
||||
+#include "cipher.h"
|
||||
+
|
||||
+static LIST_HEAD(skcipher_algs);
|
||||
+
|
||||
+static void qce_skcipher_done(void *data)
|
||||
+{
|
||||
+ struct crypto_async_request *async_req = data;
|
||||
+ struct skcipher_request *req = skcipher_request_cast(async_req);
|
||||
+ struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
|
||||
+ struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req));
|
||||
+ struct qce_device *qce = tmpl->qce;
|
||||
+ enum dma_data_direction dir_src, dir_dst;
|
||||
+ u32 status;
|
||||
+ int error;
|
||||
+ bool diff_dst;
|
||||
+
|
||||
+ diff_dst = (req->src != req->dst) ? true : false;
|
||||
+ dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;
|
||||
+ dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;
|
||||
+
|
||||
+ error = qce_dma_terminate_all(&qce->dma);
|
||||
+ if (error)
|
||||
+ dev_dbg(qce->dev, "skcipher dma termination error (%d)\n",
|
||||
+ error);
|
||||
+
|
||||
+ if (diff_dst)
|
||||
+ dma_unmap_sg(qce->dev, rctx->src_sg, rctx->src_nents, dir_src);
|
||||
+ dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
|
||||
+
|
||||
+ sg_free_table(&rctx->dst_tbl);
|
||||
+
|
||||
+ error = qce_check_status(qce, &status);
|
||||
+ if (error < 0)
|
||||
+ dev_dbg(qce->dev, "skcipher operation error (%x)\n", status);
|
||||
+
|
||||
+ qce->async_req_done(tmpl->qce, error);
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+qce_skcipher_async_req_handle(struct crypto_async_request *async_req)
|
||||
+{
|
||||
+ struct skcipher_request *req = skcipher_request_cast(async_req);
|
||||
+ struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
|
||||
+ struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
|
||||
+ struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req));
|
||||
+ struct qce_device *qce = tmpl->qce;
|
||||
+ enum dma_data_direction dir_src, dir_dst;
|
||||
+ struct scatterlist *sg;
|
||||
+ bool diff_dst;
|
||||
+ gfp_t gfp;
|
||||
+ int ret;
|
||||
+
|
||||
+ rctx->iv = req->iv;
|
||||
+ rctx->ivsize = crypto_skcipher_ivsize(skcipher);
|
||||
+ rctx->cryptlen = req->cryptlen;
|
||||
+
|
||||
+ diff_dst = (req->src != req->dst) ? true : false;
|
||||
+ dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;
|
||||
+ dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;
|
||||
+
|
||||
+ rctx->src_nents = sg_nents_for_len(req->src, req->cryptlen);
|
||||
+ if (diff_dst)
|
||||
+ rctx->dst_nents = sg_nents_for_len(req->dst, req->cryptlen);
|
||||
+ else
|
||||
+ rctx->dst_nents = rctx->src_nents;
|
||||
+ if (rctx->src_nents < 0) {
|
||||
+ dev_err(qce->dev, "Invalid numbers of src SG.\n");
|
||||
+ return rctx->src_nents;
|
||||
+ }
|
||||
+ if (rctx->dst_nents < 0) {
|
||||
+ dev_err(qce->dev, "Invalid numbers of dst SG.\n");
|
||||
+ return -rctx->dst_nents;
|
||||
+ }
|
||||
+
|
||||
+ rctx->dst_nents += 1;
|
||||
+
|
||||
+ gfp = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
|
||||
+ GFP_KERNEL : GFP_ATOMIC;
|
||||
+
|
||||
+ ret = sg_alloc_table(&rctx->dst_tbl, rctx->dst_nents, gfp);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
|
||||
+
|
||||
+ sg = qce_sgtable_add(&rctx->dst_tbl, req->dst);
|
||||
+ if (IS_ERR(sg)) {
|
||||
+ ret = PTR_ERR(sg);
|
||||
+ goto error_free;
|
||||
+ }
|
||||
+
|
||||
+ sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg);
|
||||
+ if (IS_ERR(sg)) {
|
||||
+ ret = PTR_ERR(sg);
|
||||
+ goto error_free;
|
||||
+ }
|
||||
+
|
||||
+ sg_mark_end(sg);
|
||||
+ rctx->dst_sg = rctx->dst_tbl.sgl;
|
||||
+
|
||||
+ ret = dma_map_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
|
||||
+ if (ret < 0)
|
||||
+ goto error_free;
|
||||
+
|
||||
+ if (diff_dst) {
|
||||
+ ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, dir_src);
|
||||
+ if (ret < 0)
|
||||
+ goto error_unmap_dst;
|
||||
+ rctx->src_sg = req->src;
|
||||
+ } else {
|
||||
+ rctx->src_sg = rctx->dst_sg;
|
||||
+ }
|
||||
+
|
||||
+ ret = qce_dma_prep_sgs(&qce->dma, rctx->src_sg, rctx->src_nents,
|
||||
+ rctx->dst_sg, rctx->dst_nents,
|
||||
+ qce_skcipher_done, async_req);
|
||||
+ if (ret)
|
||||
+ goto error_unmap_src;
|
||||
+
|
||||
+ qce_dma_issue_pending(&qce->dma);
|
||||
+
|
||||
+ ret = qce_start(async_req, tmpl->crypto_alg_type, req->cryptlen, 0);
|
||||
+ if (ret)
|
||||
+ goto error_terminate;
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+error_terminate:
|
||||
+ qce_dma_terminate_all(&qce->dma);
|
||||
+error_unmap_src:
|
||||
+ if (diff_dst)
|
||||
+ dma_unmap_sg(qce->dev, req->src, rctx->src_nents, dir_src);
|
||||
+error_unmap_dst:
|
||||
+ dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
|
||||
+error_free:
|
||||
+ sg_free_table(&rctx->dst_tbl);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int qce_skcipher_setkey(struct crypto_skcipher *ablk, const u8 *key,
|
||||
+ unsigned int keylen)
|
||||
+{
|
||||
+ struct crypto_tfm *tfm = crypto_skcipher_tfm(ablk);
|
||||
+ struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
|
||||
+ int ret;
|
||||
+
|
||||
+ if (!key || !keylen)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ switch (keylen) {
|
||||
+ case AES_KEYSIZE_128:
|
||||
+ case AES_KEYSIZE_256:
|
||||
+ break;
|
||||
+ default:
|
||||
+ goto fallback;
|
||||
+ }
|
||||
+
|
||||
+ ctx->enc_keylen = keylen;
|
||||
+ memcpy(ctx->enc_key, key, keylen);
|
||||
+ return 0;
|
||||
+fallback:
|
||||
+ ret = crypto_sync_skcipher_setkey(ctx->fallback, key, keylen);
|
||||
+ if (!ret)
|
||||
+ ctx->enc_keylen = keylen;
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int qce_des_setkey(struct crypto_skcipher *ablk, const u8 *key,
|
||||
+ unsigned int keylen)
|
||||
+{
|
||||
+ struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(ablk);
|
||||
+ int err;
|
||||
+
|
||||
+ err = verify_skcipher_des_key(ablk, key);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+
|
||||
+ ctx->enc_keylen = keylen;
|
||||
+ memcpy(ctx->enc_key, key, keylen);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qce_des3_setkey(struct crypto_skcipher *ablk, const u8 *key,
|
||||
+ unsigned int keylen)
|
||||
+{
|
||||
+ struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(ablk);
|
||||
+ int err;
|
||||
+
|
||||
+ err = verify_skcipher_des3_key(ablk, key);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+
|
||||
+ ctx->enc_keylen = keylen;
|
||||
+ memcpy(ctx->enc_key, key, keylen);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qce_skcipher_crypt(struct skcipher_request *req, int encrypt)
|
||||
+{
|
||||
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
|
||||
+ struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
|
||||
+ struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
|
||||
+ struct qce_alg_template *tmpl = to_cipher_tmpl(tfm);
|
||||
+ int ret;
|
||||
+
|
||||
+ rctx->flags = tmpl->alg_flags;
|
||||
+ rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
|
||||
+
|
||||
+ if (IS_AES(rctx->flags) && ctx->enc_keylen != AES_KEYSIZE_128 &&
|
||||
+ ctx->enc_keylen != AES_KEYSIZE_256) {
|
||||
+ SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
|
||||
+
|
||||
+ skcipher_request_set_sync_tfm(subreq, ctx->fallback);
|
||||
+ skcipher_request_set_callback(subreq, req->base.flags,
|
||||
+ NULL, NULL);
|
||||
+ skcipher_request_set_crypt(subreq, req->src, req->dst,
|
||||
+ req->cryptlen, req->iv);
|
||||
+ ret = encrypt ? crypto_skcipher_encrypt(subreq) :
|
||||
+ crypto_skcipher_decrypt(subreq);
|
||||
+ skcipher_request_zero(subreq);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ return tmpl->qce->async_req_enqueue(tmpl->qce, &req->base);
|
||||
+}
|
||||
+
|
||||
+static int qce_skcipher_encrypt(struct skcipher_request *req)
|
||||
+{
|
||||
+ return qce_skcipher_crypt(req, 1);
|
||||
+}
|
||||
+
|
||||
+static int qce_skcipher_decrypt(struct skcipher_request *req)
|
||||
+{
|
||||
+ return qce_skcipher_crypt(req, 0);
|
||||
+}
|
||||
+
|
||||
+static int qce_skcipher_init(struct crypto_skcipher *tfm)
|
||||
+{
|
||||
+ struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
|
||||
+
|
||||
+ memset(ctx, 0, sizeof(*ctx));
|
||||
+ crypto_skcipher_set_reqsize(tfm, sizeof(struct qce_cipher_reqctx));
|
||||
+
|
||||
+ ctx->fallback = crypto_alloc_sync_skcipher(crypto_tfm_alg_name(&tfm->base),
|
||||
+ 0, CRYPTO_ALG_NEED_FALLBACK);
|
||||
+ return PTR_ERR_OR_ZERO(ctx->fallback);
|
||||
+}
|
||||
+
|
||||
+static void qce_skcipher_exit(struct crypto_skcipher *tfm)
|
||||
+{
|
||||
+ struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
|
||||
+
|
||||
+ crypto_free_sync_skcipher(ctx->fallback);
|
||||
+}
|
||||
+
|
||||
+struct qce_skcipher_def {
|
||||
+ unsigned long flags;
|
||||
+ const char *name;
|
||||
+ const char *drv_name;
|
||||
+ unsigned int blocksize;
|
||||
+ unsigned int ivsize;
|
||||
+ unsigned int min_keysize;
|
||||
+ unsigned int max_keysize;
|
||||
+};
|
||||
+
|
||||
+static const struct qce_skcipher_def skcipher_def[] = {
|
||||
+ {
|
||||
+ .flags = QCE_ALG_AES | QCE_MODE_ECB,
|
||||
+ .name = "ecb(aes)",
|
||||
+ .drv_name = "ecb-aes-qce",
|
||||
+ .blocksize = AES_BLOCK_SIZE,
|
||||
+ .ivsize = AES_BLOCK_SIZE,
|
||||
+ .min_keysize = AES_MIN_KEY_SIZE,
|
||||
+ .max_keysize = AES_MAX_KEY_SIZE,
|
||||
+ },
|
||||
+ {
|
||||
+ .flags = QCE_ALG_AES | QCE_MODE_CBC,
|
||||
+ .name = "cbc(aes)",
|
||||
+ .drv_name = "cbc-aes-qce",
|
||||
+ .blocksize = AES_BLOCK_SIZE,
|
||||
+ .ivsize = AES_BLOCK_SIZE,
|
||||
+ .min_keysize = AES_MIN_KEY_SIZE,
|
||||
+ .max_keysize = AES_MAX_KEY_SIZE,
|
||||
+ },
|
||||
+ {
|
||||
+ .flags = QCE_ALG_AES | QCE_MODE_CTR,
|
||||
+ .name = "ctr(aes)",
|
||||
+ .drv_name = "ctr-aes-qce",
|
||||
+ .blocksize = AES_BLOCK_SIZE,
|
||||
+ .ivsize = AES_BLOCK_SIZE,
|
||||
+ .min_keysize = AES_MIN_KEY_SIZE,
|
||||
+ .max_keysize = AES_MAX_KEY_SIZE,
|
||||
+ },
|
||||
+ {
|
||||
+ .flags = QCE_ALG_AES | QCE_MODE_XTS,
|
||||
+ .name = "xts(aes)",
|
||||
+ .drv_name = "xts-aes-qce",
|
||||
+ .blocksize = AES_BLOCK_SIZE,
|
||||
+ .ivsize = AES_BLOCK_SIZE,
|
||||
+ .min_keysize = AES_MIN_KEY_SIZE,
|
||||
+ .max_keysize = AES_MAX_KEY_SIZE,
|
||||
+ },
|
||||
+ {
|
||||
+ .flags = QCE_ALG_DES | QCE_MODE_ECB,
|
||||
+ .name = "ecb(des)",
|
||||
+ .drv_name = "ecb-des-qce",
|
||||
+ .blocksize = DES_BLOCK_SIZE,
|
||||
+ .ivsize = 0,
|
||||
+ .min_keysize = DES_KEY_SIZE,
|
||||
+ .max_keysize = DES_KEY_SIZE,
|
||||
+ },
|
||||
+ {
|
||||
+ .flags = QCE_ALG_DES | QCE_MODE_CBC,
|
||||
+ .name = "cbc(des)",
|
||||
+ .drv_name = "cbc-des-qce",
|
||||
+ .blocksize = DES_BLOCK_SIZE,
|
||||
+ .ivsize = DES_BLOCK_SIZE,
|
||||
+ .min_keysize = DES_KEY_SIZE,
|
||||
+ .max_keysize = DES_KEY_SIZE,
|
||||
+ },
|
||||
+ {
|
||||
+ .flags = QCE_ALG_3DES | QCE_MODE_ECB,
|
||||
+ .name = "ecb(des3_ede)",
|
||||
+ .drv_name = "ecb-3des-qce",
|
||||
+ .blocksize = DES3_EDE_BLOCK_SIZE,
|
||||
+ .ivsize = 0,
|
||||
+ .min_keysize = DES3_EDE_KEY_SIZE,
|
||||
+ .max_keysize = DES3_EDE_KEY_SIZE,
|
||||
+ },
|
||||
+ {
|
||||
+ .flags = QCE_ALG_3DES | QCE_MODE_CBC,
|
||||
+ .name = "cbc(des3_ede)",
|
||||
+ .drv_name = "cbc-3des-qce",
|
||||
+ .blocksize = DES3_EDE_BLOCK_SIZE,
|
||||
+ .ivsize = DES3_EDE_BLOCK_SIZE,
|
||||
+ .min_keysize = DES3_EDE_KEY_SIZE,
|
||||
+ .max_keysize = DES3_EDE_KEY_SIZE,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int qce_skcipher_register_one(const struct qce_skcipher_def *def,
|
||||
+ struct qce_device *qce)
|
||||
+{
|
||||
+ struct qce_alg_template *tmpl;
|
||||
+ struct skcipher_alg *alg;
|
||||
+ int ret;
|
||||
+
|
||||
+ tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL);
|
||||
+ if (!tmpl)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ alg = &tmpl->alg.skcipher;
|
||||
+
|
||||
+ snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name);
|
||||
+ snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
|
||||
+ def->drv_name);
|
||||
+
|
||||
+ alg->base.cra_blocksize = def->blocksize;
|
||||
+ alg->ivsize = def->ivsize;
|
||||
+ alg->min_keysize = def->min_keysize;
|
||||
+ alg->max_keysize = def->max_keysize;
|
||||
+ alg->setkey = IS_3DES(def->flags) ? qce_des3_setkey :
|
||||
+ IS_DES(def->flags) ? qce_des_setkey :
|
||||
+ qce_skcipher_setkey;
|
||||
+ alg->encrypt = qce_skcipher_encrypt;
|
||||
+ alg->decrypt = qce_skcipher_decrypt;
|
||||
+
|
||||
+ alg->base.cra_priority = 300;
|
||||
+ alg->base.cra_flags = CRYPTO_ALG_ASYNC |
|
||||
+ CRYPTO_ALG_NEED_FALLBACK |
|
||||
+ CRYPTO_ALG_KERN_DRIVER_ONLY;
|
||||
+ alg->base.cra_ctxsize = sizeof(struct qce_cipher_ctx);
|
||||
+ alg->base.cra_alignmask = 0;
|
||||
+ alg->base.cra_module = THIS_MODULE;
|
||||
+
|
||||
+ alg->init = qce_skcipher_init;
|
||||
+ alg->exit = qce_skcipher_exit;
|
||||
+
|
||||
+ INIT_LIST_HEAD(&tmpl->entry);
|
||||
+ tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_SKCIPHER;
|
||||
+ tmpl->alg_flags = def->flags;
|
||||
+ tmpl->qce = qce;
|
||||
+
|
||||
+ ret = crypto_register_skcipher(alg);
|
||||
+ if (ret) {
|
||||
+ kfree(tmpl);
|
||||
+ dev_err(qce->dev, "%s registration failed\n", alg->base.cra_name);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ list_add_tail(&tmpl->entry, &skcipher_algs);
|
||||
+ dev_dbg(qce->dev, "%s is registered\n", alg->base.cra_name);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void qce_skcipher_unregister(struct qce_device *qce)
|
||||
+{
|
||||
+ struct qce_alg_template *tmpl, *n;
|
||||
+
|
||||
+ list_for_each_entry_safe(tmpl, n, &skcipher_algs, entry) {
|
||||
+ crypto_unregister_skcipher(&tmpl->alg.skcipher);
|
||||
+ list_del(&tmpl->entry);
|
||||
+ kfree(tmpl);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int qce_skcipher_register(struct qce_device *qce)
|
||||
+{
|
||||
+ int ret, i;
|
||||
+
|
||||
+ for (i = 0; i < ARRAY_SIZE(skcipher_def); i++) {
|
||||
+ ret = qce_skcipher_register_one(&skcipher_def[i], qce);
|
||||
+ if (ret)
|
||||
+ goto err;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+err:
|
||||
+ qce_skcipher_unregister(qce);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+const struct qce_algo_ops skcipher_ops = {
|
||||
+ .type = CRYPTO_ALG_TYPE_SKCIPHER,
|
||||
+ .register_algs = qce_skcipher_register,
|
||||
+ .unregister_algs = qce_skcipher_unregister,
|
||||
+ .async_req_handle = qce_skcipher_async_req_handle,
|
||||
+};
|
||||
@ -0,0 +1,43 @@
|
||||
From bb5c863b3d3cbd10e80b2ebf409934a091058f54 Mon Sep 17 00:00:00 2001
|
||||
From: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Date: Fri, 20 Dec 2019 16:02:13 -0300
|
||||
Subject: [PATCH 02/11] crypto: qce - fix ctr-aes-qce block, chunk sizes
|
||||
|
||||
Set blocksize of ctr-aes-qce to 1, so it can operate as a stream cipher,
|
||||
adding the definition for chucksize instead, where the underlying block
|
||||
size belongs.
|
||||
|
||||
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
||||
---
|
||||
drivers/crypto/qce/skcipher.c | 5 ++++-
|
||||
1 file changed, 4 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/crypto/qce/skcipher.c
|
||||
+++ b/drivers/crypto/qce/skcipher.c
|
||||
@@ -270,6 +270,7 @@ struct qce_skcipher_def {
|
||||
const char *name;
|
||||
const char *drv_name;
|
||||
unsigned int blocksize;
|
||||
+ unsigned int chunksize;
|
||||
unsigned int ivsize;
|
||||
unsigned int min_keysize;
|
||||
unsigned int max_keysize;
|
||||
@@ -298,7 +299,8 @@ static const struct qce_skcipher_def skc
|
||||
.flags = QCE_ALG_AES | QCE_MODE_CTR,
|
||||
.name = "ctr(aes)",
|
||||
.drv_name = "ctr-aes-qce",
|
||||
- .blocksize = AES_BLOCK_SIZE,
|
||||
+ .blocksize = 1,
|
||||
+ .chunksize = AES_BLOCK_SIZE,
|
||||
.ivsize = AES_BLOCK_SIZE,
|
||||
.min_keysize = AES_MIN_KEY_SIZE,
|
||||
.max_keysize = AES_MAX_KEY_SIZE,
|
||||
@@ -368,6 +370,7 @@ static int qce_skcipher_register_one(con
|
||||
def->drv_name);
|
||||
|
||||
alg->base.cra_blocksize = def->blocksize;
|
||||
+ alg->chunksize = def->chunksize;
|
||||
alg->ivsize = def->ivsize;
|
||||
alg->min_keysize = def->min_keysize;
|
||||
alg->max_keysize = def->max_keysize;
|
||||
@ -0,0 +1,60 @@
|
||||
From 7de4c2bd196f111e39cc60f6197654aff23ba2b4 Mon Sep 17 00:00:00 2001
|
||||
From: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Date: Fri, 20 Dec 2019 16:02:14 -0300
|
||||
Subject: [PATCH 03/11] crypto: qce - fix xts-aes-qce key sizes
|
||||
|
||||
XTS-mode uses two keys, so the keysizes should be doubled in
|
||||
skcipher_def, and halved when checking if it is AES-128/192/256.
|
||||
|
||||
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
||||
---
|
||||
drivers/crypto/qce/skcipher.c | 13 ++++++++-----
|
||||
1 file changed, 8 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/crypto/qce/skcipher.c
|
||||
+++ b/drivers/crypto/qce/skcipher.c
|
||||
@@ -154,12 +154,13 @@ static int qce_skcipher_setkey(struct cr
|
||||
{
|
||||
struct crypto_tfm *tfm = crypto_skcipher_tfm(ablk);
|
||||
struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
|
||||
+ unsigned long flags = to_cipher_tmpl(ablk)->alg_flags;
|
||||
int ret;
|
||||
|
||||
if (!key || !keylen)
|
||||
return -EINVAL;
|
||||
|
||||
- switch (keylen) {
|
||||
+ switch (IS_XTS(flags) ? keylen >> 1 : keylen) {
|
||||
case AES_KEYSIZE_128:
|
||||
case AES_KEYSIZE_256:
|
||||
break;
|
||||
@@ -213,13 +214,15 @@ static int qce_skcipher_crypt(struct skc
|
||||
struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
|
||||
struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
|
||||
struct qce_alg_template *tmpl = to_cipher_tmpl(tfm);
|
||||
+ int keylen;
|
||||
int ret;
|
||||
|
||||
rctx->flags = tmpl->alg_flags;
|
||||
rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
|
||||
+ keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen;
|
||||
|
||||
- if (IS_AES(rctx->flags) && ctx->enc_keylen != AES_KEYSIZE_128 &&
|
||||
- ctx->enc_keylen != AES_KEYSIZE_256) {
|
||||
+ if (IS_AES(rctx->flags) && keylen != AES_KEYSIZE_128 &&
|
||||
+ keylen != AES_KEYSIZE_256) {
|
||||
SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
|
||||
|
||||
skcipher_request_set_sync_tfm(subreq, ctx->fallback);
|
||||
@@ -311,8 +314,8 @@ static const struct qce_skcipher_def skc
|
||||
.drv_name = "xts-aes-qce",
|
||||
.blocksize = AES_BLOCK_SIZE,
|
||||
.ivsize = AES_BLOCK_SIZE,
|
||||
- .min_keysize = AES_MIN_KEY_SIZE,
|
||||
- .max_keysize = AES_MAX_KEY_SIZE,
|
||||
+ .min_keysize = AES_MIN_KEY_SIZE * 2,
|
||||
+ .max_keysize = AES_MAX_KEY_SIZE * 2,
|
||||
},
|
||||
{
|
||||
.flags = QCE_ALG_DES | QCE_MODE_ECB,
|
||||
@ -0,0 +1,85 @@
|
||||
From 3ee50c896d712dc2fc8f34c2cd1918d035e74045 Mon Sep 17 00:00:00 2001
|
||||
From: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Date: Fri, 20 Dec 2019 16:02:15 -0300
|
||||
Subject: [PATCH 04/11] crypto: qce - save a sg table slot for result buf
|
||||
|
||||
When ctr-aes-qce is used for gcm-mode, an extra sg entry for the
|
||||
authentication tag is present, causing trouble when the qce driver
|
||||
prepares the dst-results sg table for dma.
|
||||
|
||||
It computes the number of entries needed with sg_nents_for_len, leaving
|
||||
out the tag entry. Then it creates a sg table with that number plus
|
||||
one, used to store a result buffer.
|
||||
|
||||
When copying the sg table, there's no limit to the number of entries
|
||||
copied, so the extra slot is filled with the authentication tag sg.
|
||||
When the driver tries to add the result sg, the list is full, and it
|
||||
returns EINVAL.
|
||||
|
||||
By limiting the number of sg entries copied to the dest table, the slot
|
||||
for the result buffer is guaranteed to be unused.
|
||||
|
||||
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
||||
---
|
||||
drivers/crypto/qce/dma.c | 6 ++++--
|
||||
drivers/crypto/qce/dma.h | 3 ++-
|
||||
drivers/crypto/qce/skcipher.c | 4 ++--
|
||||
3 files changed, 8 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/crypto/qce/dma.c
|
||||
+++ b/drivers/crypto/qce/dma.c
|
||||
@@ -47,7 +47,8 @@ void qce_dma_release(struct qce_dma_data
|
||||
}
|
||||
|
||||
struct scatterlist *
|
||||
-qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl)
|
||||
+qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl,
|
||||
+ int max_ents)
|
||||
{
|
||||
struct scatterlist *sg = sgt->sgl, *sg_last = NULL;
|
||||
|
||||
@@ -60,12 +61,13 @@ qce_sgtable_add(struct sg_table *sgt, st
|
||||
if (!sg)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
- while (new_sgl && sg) {
|
||||
+ while (new_sgl && sg && max_ents) {
|
||||
sg_set_page(sg, sg_page(new_sgl), new_sgl->length,
|
||||
new_sgl->offset);
|
||||
sg_last = sg;
|
||||
sg = sg_next(sg);
|
||||
new_sgl = sg_next(new_sgl);
|
||||
+ max_ents--;
|
||||
}
|
||||
|
||||
return sg_last;
|
||||
--- a/drivers/crypto/qce/dma.h
|
||||
+++ b/drivers/crypto/qce/dma.h
|
||||
@@ -42,6 +42,7 @@ int qce_dma_prep_sgs(struct qce_dma_data
|
||||
void qce_dma_issue_pending(struct qce_dma_data *dma);
|
||||
int qce_dma_terminate_all(struct qce_dma_data *dma);
|
||||
struct scatterlist *
|
||||
-qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add);
|
||||
+qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add,
|
||||
+ int max_ents);
|
||||
|
||||
#endif /* _DMA_H_ */
|
||||
--- a/drivers/crypto/qce/skcipher.c
|
||||
+++ b/drivers/crypto/qce/skcipher.c
|
||||
@@ -95,13 +95,13 @@ qce_skcipher_async_req_handle(struct cry
|
||||
|
||||
sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
|
||||
|
||||
- sg = qce_sgtable_add(&rctx->dst_tbl, req->dst);
|
||||
+ sg = qce_sgtable_add(&rctx->dst_tbl, req->dst, rctx->dst_nents - 1);
|
||||
if (IS_ERR(sg)) {
|
||||
ret = PTR_ERR(sg);
|
||||
goto error_free;
|
||||
}
|
||||
|
||||
- sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg);
|
||||
+ sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg, 1);
|
||||
if (IS_ERR(sg)) {
|
||||
ret = PTR_ERR(sg);
|
||||
goto error_free;
|
||||
@ -0,0 +1,31 @@
|
||||
From 3e806a12d10af2581aa26c37b58439286eab9782 Mon Sep 17 00:00:00 2001
|
||||
From: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Date: Fri, 20 Dec 2019 16:02:16 -0300
|
||||
Subject: [PATCH 05/11] crypto: qce - update the skcipher IV
|
||||
|
||||
Update the IV after the completion of each cipher operation.
|
||||
|
||||
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
||||
---
|
||||
drivers/crypto/qce/skcipher.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/drivers/crypto/qce/skcipher.c
|
||||
+++ b/drivers/crypto/qce/skcipher.c
|
||||
@@ -21,6 +21,7 @@ static void qce_skcipher_done(void *data
|
||||
struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
|
||||
struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req));
|
||||
struct qce_device *qce = tmpl->qce;
|
||||
+ struct qce_result_dump *result_buf = qce->dma.result_buf;
|
||||
enum dma_data_direction dir_src, dir_dst;
|
||||
u32 status;
|
||||
int error;
|
||||
@@ -45,6 +46,7 @@ static void qce_skcipher_done(void *data
|
||||
if (error < 0)
|
||||
dev_dbg(qce->dev, "skcipher operation error (%x)\n", status);
|
||||
|
||||
+ memcpy(rctx->iv, result_buf->encr_cntr_iv, rctx->ivsize);
|
||||
qce->async_req_done(tmpl->qce, error);
|
||||
}
|
||||
|
||||
@ -0,0 +1,54 @@
|
||||
From 8ceda883205db6dfedb82e39f67feae3b50c95a1 Mon Sep 17 00:00:00 2001
|
||||
From: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Date: Fri, 20 Dec 2019 16:02:17 -0300
|
||||
Subject: [PATCH 06/11] crypto: qce - initialize fallback only for AES
|
||||
|
||||
Adjust cra_flags to add CRYPTO_NEED_FALLBACK only for AES ciphers, where
|
||||
AES-192 is not handled by the qce hardware, and don't allocate & free
|
||||
the fallback skcipher for other algorithms.
|
||||
|
||||
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
||||
---
|
||||
drivers/crypto/qce/skcipher.c | 17 ++++++++++++++---
|
||||
1 file changed, 14 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/crypto/qce/skcipher.c
|
||||
+++ b/drivers/crypto/qce/skcipher.c
|
||||
@@ -257,7 +257,14 @@ static int qce_skcipher_init(struct cryp
|
||||
|
||||
memset(ctx, 0, sizeof(*ctx));
|
||||
crypto_skcipher_set_reqsize(tfm, sizeof(struct qce_cipher_reqctx));
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qce_skcipher_init_fallback(struct crypto_skcipher *tfm)
|
||||
+{
|
||||
+ struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
|
||||
|
||||
+ qce_skcipher_init(tfm);
|
||||
ctx->fallback = crypto_alloc_sync_skcipher(crypto_tfm_alg_name(&tfm->base),
|
||||
0, CRYPTO_ALG_NEED_FALLBACK);
|
||||
return PTR_ERR_OR_ZERO(ctx->fallback);
|
||||
@@ -387,14 +394,18 @@ static int qce_skcipher_register_one(con
|
||||
|
||||
alg->base.cra_priority = 300;
|
||||
alg->base.cra_flags = CRYPTO_ALG_ASYNC |
|
||||
- CRYPTO_ALG_NEED_FALLBACK |
|
||||
CRYPTO_ALG_KERN_DRIVER_ONLY;
|
||||
alg->base.cra_ctxsize = sizeof(struct qce_cipher_ctx);
|
||||
alg->base.cra_alignmask = 0;
|
||||
alg->base.cra_module = THIS_MODULE;
|
||||
|
||||
- alg->init = qce_skcipher_init;
|
||||
- alg->exit = qce_skcipher_exit;
|
||||
+ if (IS_AES(def->flags)) {
|
||||
+ alg->base.cra_flags |= CRYPTO_ALG_NEED_FALLBACK;
|
||||
+ alg->init = qce_skcipher_init_fallback;
|
||||
+ alg->exit = qce_skcipher_exit;
|
||||
+ } else {
|
||||
+ alg->init = qce_skcipher_init;
|
||||
+ }
|
||||
|
||||
INIT_LIST_HEAD(&tmpl->entry);
|
||||
tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_SKCIPHER;
|
||||
@ -0,0 +1,89 @@
|
||||
From d6364b8128439a8c0e381f80c38667de9f15eef8 Mon Sep 17 00:00:00 2001
|
||||
From: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Date: Fri, 7 Feb 2020 12:02:25 -0300
|
||||
Subject: [PATCH 09/11] crypto: qce - use cryptlen when adding extra sgl
|
||||
|
||||
The qce crypto driver appends an extra entry to the dst sgl, to maintain
|
||||
private state information.
|
||||
|
||||
When the gcm driver sends requests to the ctr skcipher, it passes the
|
||||
authentication tag after the actual crypto payload, but it must not be
|
||||
touched.
|
||||
|
||||
Commit 1336c2221bee ("crypto: qce - save a sg table slot for result
|
||||
buf") limited the destination sgl to avoid overwriting the
|
||||
authentication tag but it assumed the tag would be in a separate sgl
|
||||
entry.
|
||||
|
||||
This is not always the case, so it is better to limit the length of the
|
||||
destination buffer to req->cryptlen before appending the result buf.
|
||||
|
||||
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
||||
---
|
||||
drivers/crypto/qce/dma.c | 11 ++++++-----
|
||||
drivers/crypto/qce/dma.h | 2 +-
|
||||
drivers/crypto/qce/skcipher.c | 5 +++--
|
||||
3 files changed, 10 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/drivers/crypto/qce/dma.c
|
||||
+++ b/drivers/crypto/qce/dma.c
|
||||
@@ -48,9 +48,10 @@ void qce_dma_release(struct qce_dma_data
|
||||
|
||||
struct scatterlist *
|
||||
qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl,
|
||||
- int max_ents)
|
||||
+ unsigned int max_len)
|
||||
{
|
||||
struct scatterlist *sg = sgt->sgl, *sg_last = NULL;
|
||||
+ unsigned int new_len;
|
||||
|
||||
while (sg) {
|
||||
if (!sg_page(sg))
|
||||
@@ -61,13 +62,13 @@ qce_sgtable_add(struct sg_table *sgt, st
|
||||
if (!sg)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
- while (new_sgl && sg && max_ents) {
|
||||
- sg_set_page(sg, sg_page(new_sgl), new_sgl->length,
|
||||
- new_sgl->offset);
|
||||
+ while (new_sgl && sg && max_len) {
|
||||
+ new_len = new_sgl->length > max_len ? max_len : new_sgl->length;
|
||||
+ sg_set_page(sg, sg_page(new_sgl), new_len, new_sgl->offset);
|
||||
sg_last = sg;
|
||||
sg = sg_next(sg);
|
||||
new_sgl = sg_next(new_sgl);
|
||||
- max_ents--;
|
||||
+ max_len -= new_len;
|
||||
}
|
||||
|
||||
return sg_last;
|
||||
--- a/drivers/crypto/qce/dma.h
|
||||
+++ b/drivers/crypto/qce/dma.h
|
||||
@@ -43,6 +43,6 @@ void qce_dma_issue_pending(struct qce_dm
|
||||
int qce_dma_terminate_all(struct qce_dma_data *dma);
|
||||
struct scatterlist *
|
||||
qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add,
|
||||
- int max_ents);
|
||||
+ unsigned int max_len);
|
||||
|
||||
#endif /* _DMA_H_ */
|
||||
--- a/drivers/crypto/qce/skcipher.c
|
||||
+++ b/drivers/crypto/qce/skcipher.c
|
||||
@@ -97,13 +97,14 @@ qce_skcipher_async_req_handle(struct cry
|
||||
|
||||
sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
|
||||
|
||||
- sg = qce_sgtable_add(&rctx->dst_tbl, req->dst, rctx->dst_nents - 1);
|
||||
+ sg = qce_sgtable_add(&rctx->dst_tbl, req->dst, req->cryptlen);
|
||||
if (IS_ERR(sg)) {
|
||||
ret = PTR_ERR(sg);
|
||||
goto error_free;
|
||||
}
|
||||
|
||||
- sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg, 1);
|
||||
+ sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg,
|
||||
+ QCE_RESULT_BUF_SZ);
|
||||
if (IS_ERR(sg)) {
|
||||
ret = PTR_ERR(sg);
|
||||
goto error_free;
|
||||
@ -0,0 +1,113 @@
|
||||
From ce163ba0bf298f1707321ac025ef639f88e62801 Mon Sep 17 00:00:00 2001
|
||||
From: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Date: Fri, 7 Feb 2020 12:02:26 -0300
|
||||
Subject: [PATCH 10/11] crypto: qce - use AES fallback for small requests
|
||||
|
||||
Process small blocks using the fallback cipher, as a workaround for an
|
||||
observed failure (DMA-related, apparently) when computing the GCM ghash
|
||||
key. This brings a speed gain as well, since it avoids the latency of
|
||||
using the hardware engine to process small blocks.
|
||||
|
||||
Using software for all 16-byte requests would be enough to make GCM
|
||||
work, but to increase performance, a larger threshold would be better.
|
||||
Measuring the performance of supported ciphers with openssl speed,
|
||||
software matches hardware at around 768-1024 bytes.
|
||||
|
||||
Considering the 256-bit ciphers, software is 2-3 times faster than qce
|
||||
at 256-bytes, 30% faster at 512, and about even at 768-bytes. With
|
||||
128-bit keys, the break-even point would be around 1024-bytes.
|
||||
|
||||
This adds the 'aes_sw_max_len' parameter, to set the largest request
|
||||
length processed by the software fallback. Its default is being set to
|
||||
512 bytes, a little lower than the break-even point, to balance the cost
|
||||
in CPU usage.
|
||||
|
||||
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
||||
---
|
||||
|
||||
--- a/drivers/crypto/Kconfig
|
||||
+++ b/drivers/crypto/Kconfig
|
||||
@@ -628,6 +628,29 @@ config CRYPTO_DEV_QCE
|
||||
hardware. To compile this driver as a module, choose M here. The
|
||||
module will be called qcrypto.
|
||||
|
||||
+config CRYPTO_DEV_QCE_SW_MAX_LEN
|
||||
+ int "Default maximum request size to use software for AES"
|
||||
+ depends on CRYPTO_DEV_QCE && CRYPTO_DEV_QCE_SKCIPHER
|
||||
+ default 512
|
||||
+ help
|
||||
+ This sets the default maximum request size to perform AES requests
|
||||
+ using software instead of the crypto engine. It can be changed by
|
||||
+ setting the aes_sw_max_len parameter.
|
||||
+
|
||||
+ Small blocks are processed faster in software than hardware.
|
||||
+ Considering the 256-bit ciphers, software is 2-3 times faster than
|
||||
+ qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
|
||||
+ With 128-bit keys, the break-even point would be around 1024-bytes.
|
||||
+
|
||||
+ The default is set a little lower, to 512 bytes, to balance the
|
||||
+ cost in CPU usage. The minimum recommended setting is 16-bytes
|
||||
+ (1 AES block), since AES-GCM will fail if you set it lower.
|
||||
+ Setting this to zero will send all requests to the hardware.
|
||||
+
|
||||
+ Note that 192-bit keys are not supported by the hardware and are
|
||||
+ always processed by the software fallback, and all DES requests
|
||||
+ are done by the hardware.
|
||||
+
|
||||
config CRYPTO_DEV_QCOM_RNG
|
||||
tristate "Qualcomm Random Number Generator Driver"
|
||||
depends on ARCH_QCOM || COMPILE_TEST
|
||||
--- a/drivers/crypto/qce/skcipher.c
|
||||
+++ b/drivers/crypto/qce/skcipher.c
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/interrupt.h>
|
||||
+#include <linux/moduleparam.h>
|
||||
#include <linux/types.h>
|
||||
#include <crypto/aes.h>
|
||||
#include <crypto/internal/des.h>
|
||||
@@ -12,6 +13,13 @@
|
||||
|
||||
#include "cipher.h"
|
||||
|
||||
+static unsigned int aes_sw_max_len = CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN;
|
||||
+module_param(aes_sw_max_len, uint, 0644);
|
||||
+MODULE_PARM_DESC(aes_sw_max_len,
|
||||
+ "Only use hardware for AES requests larger than this "
|
||||
+ "[0=always use hardware; anything <16 breaks AES-GCM; default="
|
||||
+ __stringify(CONFIG_CRYPTO_DEV_QCE_SOFT_THRESHOLD)"]");
|
||||
+
|
||||
static LIST_HEAD(skcipher_algs);
|
||||
|
||||
static void qce_skcipher_done(void *data)
|
||||
@@ -166,15 +174,10 @@ static int qce_skcipher_setkey(struct cr
|
||||
switch (IS_XTS(flags) ? keylen >> 1 : keylen) {
|
||||
case AES_KEYSIZE_128:
|
||||
case AES_KEYSIZE_256:
|
||||
+ memcpy(ctx->enc_key, key, keylen);
|
||||
break;
|
||||
- default:
|
||||
- goto fallback;
|
||||
}
|
||||
|
||||
- ctx->enc_keylen = keylen;
|
||||
- memcpy(ctx->enc_key, key, keylen);
|
||||
- return 0;
|
||||
-fallback:
|
||||
ret = crypto_sync_skcipher_setkey(ctx->fallback, key, keylen);
|
||||
if (!ret)
|
||||
ctx->enc_keylen = keylen;
|
||||
@@ -224,8 +227,9 @@ static int qce_skcipher_crypt(struct skc
|
||||
rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
|
||||
keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen;
|
||||
|
||||
- if (IS_AES(rctx->flags) && keylen != AES_KEYSIZE_128 &&
|
||||
- keylen != AES_KEYSIZE_256) {
|
||||
+ if (IS_AES(rctx->flags) &&
|
||||
+ ((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) ||
|
||||
+ req->cryptlen <= aes_sw_max_len)) {
|
||||
SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
|
||||
|
||||
skcipher_request_set_sync_tfm(subreq, ctx->fallback);
|
||||
@ -0,0 +1,59 @@
|
||||
From 7f19380b2cfd412dcef2facefb3f6c62788864d7 Mon Sep 17 00:00:00 2001
|
||||
From: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Date: Fri, 7 Feb 2020 12:02:27 -0300
|
||||
Subject: [PATCH 11/11] crypto: qce - handle AES-XTS cases that qce fails
|
||||
|
||||
QCE hangs when presented with an AES-XTS request whose length is larger
|
||||
than QCE_SECTOR_SIZE (512-bytes), and is not a multiple of it. Let the
|
||||
fallback cipher handle them.
|
||||
|
||||
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
||||
---
|
||||
drivers/crypto/qce/common.c | 2 --
|
||||
drivers/crypto/qce/common.h | 3 +++
|
||||
drivers/crypto/qce/skcipher.c | 9 +++++++--
|
||||
3 files changed, 10 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/crypto/qce/common.c
|
||||
+++ b/drivers/crypto/qce/common.c
|
||||
@@ -15,8 +15,6 @@
|
||||
#include "regs-v5.h"
|
||||
#include "sha.h"
|
||||
|
||||
-#define QCE_SECTOR_SIZE 512
|
||||
-
|
||||
static inline u32 qce_read(struct qce_device *qce, u32 offset)
|
||||
{
|
||||
return readl(qce->base + offset);
|
||||
--- a/drivers/crypto/qce/common.h
|
||||
+++ b/drivers/crypto/qce/common.h
|
||||
@@ -12,6 +12,9 @@
|
||||
#include <crypto/hash.h>
|
||||
#include <crypto/internal/skcipher.h>
|
||||
|
||||
+/* xts du size */
|
||||
+#define QCE_SECTOR_SIZE 512
|
||||
+
|
||||
/* key size in bytes */
|
||||
#define QCE_SHA_HMAC_KEY_SIZE 64
|
||||
#define QCE_MAX_CIPHER_KEY_SIZE AES_KEYSIZE_256
|
||||
--- a/drivers/crypto/qce/skcipher.c
|
||||
+++ b/drivers/crypto/qce/skcipher.c
|
||||
@@ -227,9 +227,14 @@ static int qce_skcipher_crypt(struct skc
|
||||
rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
|
||||
keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen;
|
||||
|
||||
+ /* qce is hanging when AES-XTS request len > QCE_SECTOR_SIZE and
|
||||
+ * is not a multiple of it; pass such requests to the fallback
|
||||
+ */
|
||||
if (IS_AES(rctx->flags) &&
|
||||
- ((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) ||
|
||||
- req->cryptlen <= aes_sw_max_len)) {
|
||||
+ (((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) ||
|
||||
+ req->cryptlen <= aes_sw_max_len) ||
|
||||
+ (IS_XTS(rctx->flags) && req->cryptlen > QCE_SECTOR_SIZE &&
|
||||
+ req->cryptlen % QCE_SECTOR_SIZE))) {
|
||||
SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
|
||||
|
||||
skcipher_request_set_sync_tfm(subreq, ctx->fallback);
|
||||
@ -0,0 +1,419 @@
|
||||
From 59e056cda4beb5412e3653e6360c2eb0fa770baa Mon Sep 17 00:00:00 2001
|
||||
From: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Date: Fri, 20 Dec 2019 16:02:18 -0300
|
||||
Subject: [PATCH 07/11] crypto: qce - allow building only hashes/ciphers
|
||||
|
||||
Allow the user to choose whether to build support for all algorithms
|
||||
(default), hashes-only, or skciphers-only.
|
||||
|
||||
The QCE engine does not appear to scale as well as the CPU to handle
|
||||
multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
|
||||
QCE handles only 2 requests in parallel.
|
||||
|
||||
Ipsec throughput seems to improve when disabling either family of
|
||||
algorithms, sharing the load with the CPU. Enabling skciphers-only
|
||||
appears to work best.
|
||||
|
||||
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
|
||||
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
||||
---
|
||||
|
||||
--- a/drivers/crypto/Kconfig
|
||||
+++ b/drivers/crypto/Kconfig
|
||||
@@ -616,6 +616,14 @@ config CRYPTO_DEV_QCE
|
||||
tristate "Qualcomm crypto engine accelerator"
|
||||
depends on ARCH_QCOM || COMPILE_TEST
|
||||
depends on HAS_IOMEM
|
||||
+ help
|
||||
+ This driver supports Qualcomm crypto engine accelerator
|
||||
+ hardware. To compile this driver as a module, choose M here. The
|
||||
+ module will be called qcrypto.
|
||||
+
|
||||
+config CRYPTO_DEV_QCE_SKCIPHER
|
||||
+ bool
|
||||
+ depends on CRYPTO_DEV_QCE
|
||||
select CRYPTO_AES
|
||||
select CRYPTO_LIB_DES
|
||||
select CRYPTO_ECB
|
||||
@@ -623,10 +631,57 @@ config CRYPTO_DEV_QCE
|
||||
select CRYPTO_XTS
|
||||
select CRYPTO_CTR
|
||||
select CRYPTO_BLKCIPHER
|
||||
+
|
||||
+config CRYPTO_DEV_QCE_SHA
|
||||
+ bool
|
||||
+ depends on CRYPTO_DEV_QCE
|
||||
+
|
||||
+choice
|
||||
+ prompt "Algorithms enabled for QCE acceleration"
|
||||
+ default CRYPTO_DEV_QCE_ENABLE_ALL
|
||||
+ depends on CRYPTO_DEV_QCE
|
||||
help
|
||||
- This driver supports Qualcomm crypto engine accelerator
|
||||
- hardware. To compile this driver as a module, choose M here. The
|
||||
- module will be called qcrypto.
|
||||
+ This option allows to choose whether to build support for all algorihtms
|
||||
+ (default), hashes-only, or skciphers-only.
|
||||
+
|
||||
+ The QCE engine does not appear to scale as well as the CPU to handle
|
||||
+ multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
|
||||
+ QCE handles only 2 requests in parallel.
|
||||
+
|
||||
+ Ipsec throughput seems to improve when disabling either family of
|
||||
+ algorithms, sharing the load with the CPU. Enabling skciphers-only
|
||||
+ appears to work best.
|
||||
+
|
||||
+ config CRYPTO_DEV_QCE_ENABLE_ALL
|
||||
+ bool "All supported algorithms"
|
||||
+ select CRYPTO_DEV_QCE_SKCIPHER
|
||||
+ select CRYPTO_DEV_QCE_SHA
|
||||
+ help
|
||||
+ Enable all supported algorithms:
|
||||
+ - AES (CBC, CTR, ECB, XTS)
|
||||
+ - 3DES (CBC, ECB)
|
||||
+ - DES (CBC, ECB)
|
||||
+ - SHA1, HMAC-SHA1
|
||||
+ - SHA256, HMAC-SHA256
|
||||
+
|
||||
+ config CRYPTO_DEV_QCE_ENABLE_SKCIPHER
|
||||
+ bool "Symmetric-key ciphers only"
|
||||
+ select CRYPTO_DEV_QCE_SKCIPHER
|
||||
+ help
|
||||
+ Enable symmetric-key ciphers only:
|
||||
+ - AES (CBC, CTR, ECB, XTS)
|
||||
+ - 3DES (ECB, CBC)
|
||||
+ - DES (ECB, CBC)
|
||||
+
|
||||
+ config CRYPTO_DEV_QCE_ENABLE_SHA
|
||||
+ bool "Hash/HMAC only"
|
||||
+ select CRYPTO_DEV_QCE_SHA
|
||||
+ help
|
||||
+ Enable hashes/HMAC algorithms only:
|
||||
+ - SHA1, HMAC-SHA1
|
||||
+ - SHA256, HMAC-SHA256
|
||||
+
|
||||
+endchoice
|
||||
|
||||
config CRYPTO_DEV_QCE_SW_MAX_LEN
|
||||
int "Default maximum request size to use software for AES"
|
||||
--- a/drivers/crypto/qce/Makefile
|
||||
+++ b/drivers/crypto/qce/Makefile
|
||||
@@ -2,6 +2,7 @@
|
||||
obj-$(CONFIG_CRYPTO_DEV_QCE) += qcrypto.o
|
||||
qcrypto-objs := core.o \
|
||||
common.o \
|
||||
- dma.o \
|
||||
- sha.o \
|
||||
- skcipher.o
|
||||
+ dma.o
|
||||
+
|
||||
+qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SHA) += sha.o
|
||||
+qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SKCIPHER) += skcipher.o
|
||||
--- a/drivers/crypto/qce/common.c
|
||||
+++ b/drivers/crypto/qce/common.c
|
||||
@@ -43,52 +43,56 @@ qce_clear_array(struct qce_device *qce,
|
||||
qce_write(qce, offset + i * sizeof(u32), 0);
|
||||
}
|
||||
|
||||
-static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
|
||||
+static u32 qce_config_reg(struct qce_device *qce, int little)
|
||||
{
|
||||
- u32 cfg = 0;
|
||||
+ u32 beats = (qce->burst_size >> 3) - 1;
|
||||
+ u32 pipe_pair = qce->pipe_pair_id;
|
||||
+ u32 config;
|
||||
|
||||
- if (IS_AES(flags)) {
|
||||
- if (aes_key_size == AES_KEYSIZE_128)
|
||||
- cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
|
||||
- else if (aes_key_size == AES_KEYSIZE_256)
|
||||
- cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
|
||||
- }
|
||||
+ config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
|
||||
+ config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
|
||||
+ BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
|
||||
+ config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
|
||||
+ config &= ~HIGH_SPD_EN_N_SHIFT;
|
||||
|
||||
- if (IS_AES(flags))
|
||||
- cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
|
||||
- else if (IS_DES(flags) || IS_3DES(flags))
|
||||
- cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
|
||||
+ if (little)
|
||||
+ config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
|
||||
|
||||
- if (IS_DES(flags))
|
||||
- cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
|
||||
+ return config;
|
||||
+}
|
||||
|
||||
- if (IS_3DES(flags))
|
||||
- cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
|
||||
+void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
|
||||
+{
|
||||
+ __be32 *d = dst;
|
||||
+ const u8 *s = src;
|
||||
+ unsigned int n;
|
||||
|
||||
- switch (flags & QCE_MODE_MASK) {
|
||||
- case QCE_MODE_ECB:
|
||||
- cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
|
||||
- break;
|
||||
- case QCE_MODE_CBC:
|
||||
- cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
|
||||
- break;
|
||||
- case QCE_MODE_CTR:
|
||||
- cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
|
||||
- break;
|
||||
- case QCE_MODE_XTS:
|
||||
- cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
|
||||
- break;
|
||||
- case QCE_MODE_CCM:
|
||||
- cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
|
||||
- cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
|
||||
- break;
|
||||
- default:
|
||||
- return ~0;
|
||||
+ n = len / sizeof(u32);
|
||||
+ for (; n > 0; n--) {
|
||||
+ *d = cpu_to_be32p((const __u32 *) s);
|
||||
+ s += sizeof(__u32);
|
||||
+ d++;
|
||||
}
|
||||
+}
|
||||
|
||||
- return cfg;
|
||||
+static void qce_setup_config(struct qce_device *qce)
|
||||
+{
|
||||
+ u32 config;
|
||||
+
|
||||
+ /* get big endianness */
|
||||
+ config = qce_config_reg(qce, 0);
|
||||
+
|
||||
+ /* clear status */
|
||||
+ qce_write(qce, REG_STATUS, 0);
|
||||
+ qce_write(qce, REG_CONFIG, config);
|
||||
+}
|
||||
+
|
||||
+static inline void qce_crypto_go(struct qce_device *qce)
|
||||
+{
|
||||
+ qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
|
||||
}
|
||||
|
||||
+#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
|
||||
static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
|
||||
{
|
||||
u32 cfg = 0;
|
||||
@@ -135,88 +139,6 @@ static u32 qce_auth_cfg(unsigned long fl
|
||||
return cfg;
|
||||
}
|
||||
|
||||
-static u32 qce_config_reg(struct qce_device *qce, int little)
|
||||
-{
|
||||
- u32 beats = (qce->burst_size >> 3) - 1;
|
||||
- u32 pipe_pair = qce->pipe_pair_id;
|
||||
- u32 config;
|
||||
-
|
||||
- config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
|
||||
- config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
|
||||
- BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
|
||||
- config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
|
||||
- config &= ~HIGH_SPD_EN_N_SHIFT;
|
||||
-
|
||||
- if (little)
|
||||
- config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
|
||||
-
|
||||
- return config;
|
||||
-}
|
||||
-
|
||||
-void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
|
||||
-{
|
||||
- __be32 *d = dst;
|
||||
- const u8 *s = src;
|
||||
- unsigned int n;
|
||||
-
|
||||
- n = len / sizeof(u32);
|
||||
- for (; n > 0; n--) {
|
||||
- *d = cpu_to_be32p((const __u32 *) s);
|
||||
- s += sizeof(__u32);
|
||||
- d++;
|
||||
- }
|
||||
-}
|
||||
-
|
||||
-static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
|
||||
-{
|
||||
- u8 swap[QCE_AES_IV_LENGTH];
|
||||
- u32 i, j;
|
||||
-
|
||||
- if (ivsize > QCE_AES_IV_LENGTH)
|
||||
- return;
|
||||
-
|
||||
- memset(swap, 0, QCE_AES_IV_LENGTH);
|
||||
-
|
||||
- for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
|
||||
- i < QCE_AES_IV_LENGTH; i++, j--)
|
||||
- swap[i] = src[j];
|
||||
-
|
||||
- qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
|
||||
-}
|
||||
-
|
||||
-static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
|
||||
- unsigned int enckeylen, unsigned int cryptlen)
|
||||
-{
|
||||
- u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
|
||||
- unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
|
||||
- unsigned int xtsdusize;
|
||||
-
|
||||
- qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
|
||||
- enckeylen / 2);
|
||||
- qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
|
||||
-
|
||||
- /* xts du size 512B */
|
||||
- xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
|
||||
- qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
|
||||
-}
|
||||
-
|
||||
-static void qce_setup_config(struct qce_device *qce)
|
||||
-{
|
||||
- u32 config;
|
||||
-
|
||||
- /* get big endianness */
|
||||
- config = qce_config_reg(qce, 0);
|
||||
-
|
||||
- /* clear status */
|
||||
- qce_write(qce, REG_STATUS, 0);
|
||||
- qce_write(qce, REG_CONFIG, config);
|
||||
-}
|
||||
-
|
||||
-static inline void qce_crypto_go(struct qce_device *qce)
|
||||
-{
|
||||
- qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
|
||||
-}
|
||||
-
|
||||
static int qce_setup_regs_ahash(struct crypto_async_request *async_req,
|
||||
u32 totallen, u32 offset)
|
||||
{
|
||||
@@ -301,6 +223,87 @@ go_proc:
|
||||
|
||||
return 0;
|
||||
}
|
||||
+#endif
|
||||
+
|
||||
+#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
|
||||
+static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
|
||||
+{
|
||||
+ u32 cfg = 0;
|
||||
+
|
||||
+ if (IS_AES(flags)) {
|
||||
+ if (aes_key_size == AES_KEYSIZE_128)
|
||||
+ cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
|
||||
+ else if (aes_key_size == AES_KEYSIZE_256)
|
||||
+ cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
|
||||
+ }
|
||||
+
|
||||
+ if (IS_AES(flags))
|
||||
+ cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
|
||||
+ else if (IS_DES(flags) || IS_3DES(flags))
|
||||
+ cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
|
||||
+
|
||||
+ if (IS_DES(flags))
|
||||
+ cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
|
||||
+
|
||||
+ if (IS_3DES(flags))
|
||||
+ cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
|
||||
+
|
||||
+ switch (flags & QCE_MODE_MASK) {
|
||||
+ case QCE_MODE_ECB:
|
||||
+ cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
|
||||
+ break;
|
||||
+ case QCE_MODE_CBC:
|
||||
+ cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
|
||||
+ break;
|
||||
+ case QCE_MODE_CTR:
|
||||
+ cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
|
||||
+ break;
|
||||
+ case QCE_MODE_XTS:
|
||||
+ cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
|
||||
+ break;
|
||||
+ case QCE_MODE_CCM:
|
||||
+ cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
|
||||
+ cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
|
||||
+ break;
|
||||
+ default:
|
||||
+ return ~0;
|
||||
+ }
|
||||
+
|
||||
+ return cfg;
|
||||
+}
|
||||
+
|
||||
+static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
|
||||
+{
|
||||
+ u8 swap[QCE_AES_IV_LENGTH];
|
||||
+ u32 i, j;
|
||||
+
|
||||
+ if (ivsize > QCE_AES_IV_LENGTH)
|
||||
+ return;
|
||||
+
|
||||
+ memset(swap, 0, QCE_AES_IV_LENGTH);
|
||||
+
|
||||
+ for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
|
||||
+ i < QCE_AES_IV_LENGTH; i++, j--)
|
||||
+ swap[i] = src[j];
|
||||
+
|
||||
+ qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
|
||||
+}
|
||||
+
|
||||
+static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
|
||||
+ unsigned int enckeylen, unsigned int cryptlen)
|
||||
+{
|
||||
+ u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
|
||||
+ unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
|
||||
+ unsigned int xtsdusize;
|
||||
+
|
||||
+ qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
|
||||
+ enckeylen / 2);
|
||||
+ qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
|
||||
+
|
||||
+ /* xts du size 512B */
|
||||
+ xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
|
||||
+ qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
|
||||
+}
|
||||
|
||||
static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
|
||||
u32 totallen, u32 offset)
|
||||
@@ -382,15 +385,20 @@ static int qce_setup_regs_skcipher(struc
|
||||
|
||||
return 0;
|
||||
}
|
||||
+#endif
|
||||
|
||||
int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
|
||||
u32 offset)
|
||||
{
|
||||
switch (type) {
|
||||
+#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
|
||||
case CRYPTO_ALG_TYPE_SKCIPHER:
|
||||
return qce_setup_regs_skcipher(async_req, totallen, offset);
|
||||
+#endif
|
||||
+#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
|
||||
case CRYPTO_ALG_TYPE_AHASH:
|
||||
return qce_setup_regs_ahash(async_req, totallen, offset);
|
||||
+#endif
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
--- a/drivers/crypto/qce/core.c
|
||||
+++ b/drivers/crypto/qce/core.c
|
||||
@@ -22,8 +22,12 @@
|
||||
#define QCE_QUEUE_LENGTH 1
|
||||
|
||||
static const struct qce_algo_ops *qce_ops[] = {
|
||||
+#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
|
||||
&skcipher_ops,
|
||||
+#endif
|
||||
+#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
|
||||
&ahash_ops,
|
||||
+#endif
|
||||
};
|
||||
|
||||
static void qce_unregister_algs(struct qce_device *qce)
|
||||
@ -0,0 +1,38 @@
|
||||
From 8a4540321e8bcf7a5b485c332a2e78f3501c78ed Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Thu, 29 Nov 2018 22:29:36 +0100
|
||||
Subject: [PATCH] ipq40xx: Fix booting secondary cores
|
||||
|
||||
Add the second part of old 071-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch
|
||||
We dont modify the patch itself as its upstream and this change is not.
|
||||
|
||||
Originally added by Mantas Pucka Mantas Pucka <mantas@8devices.com>
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -102,6 +102,7 @@
|
||||
L2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
+ qcom,saw = <&saw_l2>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -341,6 +342,12 @@
|
||||
regulator;
|
||||
};
|
||||
|
||||
+ saw_l2: regulator@b012000 {
|
||||
+ compatible = "qcom,saw2";
|
||||
+ reg = <0xb012000 0x1000>;
|
||||
+ regulator;
|
||||
+ };
|
||||
+
|
||||
blsp1_uart1: serial@78af000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78af000 0x200>;
|
||||
@ -0,0 +1,36 @@
|
||||
From 89b43d59ec8c9cda588555eb1f2754dd19ef5144 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sun, 22 Jul 2018 12:07:57 +0200
|
||||
Subject: [PATCH 8/8] ARM: qcom: Add IPQ4019 SoC support
|
||||
|
||||
Add support for the Qualcomm Atheros IPQ4019 SoC.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
arch/arm/Makefile | 1 +
|
||||
arch/arm/mach-qcom/Kconfig | 5 +++++
|
||||
2 files changed, 6 insertions(+)
|
||||
|
||||
--- a/arch/arm/Makefile
|
||||
+++ b/arch/arm/Makefile
|
||||
@@ -156,6 +156,7 @@ textofs-$(CONFIG_ARCH_MSM8X60) := 0x0020
|
||||
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
|
||||
textofs-$(CONFIG_ARCH_MESON) := 0x00208000
|
||||
textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
|
||||
+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
|
||||
|
||||
# Machine directory name. This list is sorted alphanumerically
|
||||
# by CONFIG_* macro name.
|
||||
--- a/arch/arm/mach-qcom/Kconfig
|
||||
+++ b/arch/arm/mach-qcom/Kconfig
|
||||
@@ -28,4 +28,9 @@ config ARCH_MDM9615
|
||||
bool "Enable support for MDM9615"
|
||||
select CLKSRC_QCOM
|
||||
|
||||
+config ARCH_IPQ40XX
|
||||
+ bool "Enable support for IPQ40XX"
|
||||
+ select CLKSRC_QCOM
|
||||
+ select HAVE_ARM_ARCH_TIMER
|
||||
+
|
||||
endif
|
||||
@ -0,0 +1,38 @@
|
||||
From 5f01733dc755dfadfa51b7b3c6c160e632fc6002 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Tue, 24 Jul 2018 15:09:36 +0200
|
||||
Subject: [PATCH 1/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document
|
||||
|
||||
This patch adds the binding documentation for the HS/SS USB PHY found
|
||||
inside Qualcom Dakota SoCs.
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
.../bindings/phy/phy-qcom-ipq4019-usb.txt | 21 +++++++++++++++++++++
|
||||
1 file changed, 21 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
|
||||
@@ -0,0 +1,21 @@
|
||||
+Qualcom Dakota HS/SS USB PHY
|
||||
+
|
||||
+Required properties:
|
||||
+ - compatible: "qcom,usb-ss-ipq4019-phy",
|
||||
+ "qcom,usb-hs-ipq4019-phy"
|
||||
+ - reg: offset and length of the registers
|
||||
+ - #phy-cells: should be 0
|
||||
+ - resets: the reset controllers as listed below
|
||||
+ - reset-names: the names of the reset controllers
|
||||
+ "por_rst" - the POR reset line for SS and HS phys
|
||||
+ "srif_rst" - the SRIF reset line for HS phys
|
||||
+Example:
|
||||
+
|
||||
+hsphy@a8000 {
|
||||
+ compatible = "qcom,usb-hs-ipq4019-phy";
|
||||
+ phy-cells = <0>;
|
||||
+ reg = <0xa8000 0x40>;
|
||||
+ resets = <&gcc USB2_HSPHY_POR_ARES>,
|
||||
+ <&gcc USB2_HSPHY_S_ARES>;
|
||||
+ reset-names = "por_rst", "srif_rst";
|
||||
+};
|
||||
@ -0,0 +1,234 @@
|
||||
From 633f0e08498aebfdb932bd71319b4cb136709499 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Tue, 24 Jul 2018 14:45:49 +0200
|
||||
Subject: [PATCH 2/3] phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019
|
||||
|
||||
Add a driver to setup the USB phy on Qualcom Dakota SoCs.
|
||||
The driver sets up HS and SS phys. In case of HS some magic values need to
|
||||
be written to magic offsets. These were taken from the SDK driver.
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
drivers/phy/qualcomm/Kconfig | 7 ++
|
||||
drivers/phy/qualcomm/Makefile | 1 +
|
||||
drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 188 ++++++++++++++++++++++++++++
|
||||
3 files changed, 196 insertions(+)
|
||||
create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
|
||||
|
||||
--- a/drivers/phy/qualcomm/Kconfig
|
||||
+++ b/drivers/phy/qualcomm/Kconfig
|
||||
@@ -18,6 +18,13 @@ config PHY_QCOM_APQ8064_SATA
|
||||
depends on OF
|
||||
select GENERIC_PHY
|
||||
|
||||
+config PHY_QCOM_IPQ4019_USB
|
||||
+ tristate "Qualcomm IPQ4019 USB PHY module"
|
||||
+ depends on OF && ARCH_QCOM
|
||||
+ select GENERIC_PHY
|
||||
+ help
|
||||
+ Support for the USB PHY on QCOM IPQ4019/Dakota chipsets.
|
||||
+
|
||||
config PHY_QCOM_IPQ806X_SATA
|
||||
tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
|
||||
depends on ARCH_QCOM
|
||||
--- /dev/null
|
||||
+++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
|
||||
@@ -0,0 +1,188 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2018 John Crispin <john@phrozen.org>
|
||||
+ *
|
||||
+ * Based on code from
|
||||
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License as published by
|
||||
+ * the Free Software Foundation; either version 2 of the License, or
|
||||
+ * (at your option) any later version.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/mutex.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/reset.h>
|
||||
+
|
||||
+/*
|
||||
+ * Magic registers copied from the SDK driver code
|
||||
+ */
|
||||
+#define PHY_CTRL0_ADDR 0x000
|
||||
+#define PHY_CTRL1_ADDR 0x004
|
||||
+#define PHY_CTRL2_ADDR 0x008
|
||||
+#define PHY_CTRL3_ADDR 0x00C
|
||||
+#define PHY_CTRL4_ADDR 0x010
|
||||
+#define PHY_MISC_ADDR 0x024
|
||||
+#define PHY_IPG_ADDR 0x030
|
||||
+
|
||||
+#define PHY_CTRL0_VAL 0xA4600015
|
||||
+#define PHY_CTRL1_VAL 0x09500000
|
||||
+#define PHY_CTRL2_VAL 0x00058180
|
||||
+#define PHY_CTRL3_VAL 0x6DB6DCD6
|
||||
+#define PHY_CTRL4_VAL 0x836DB6DB
|
||||
+#define PHY_MISC_VAL 0x3803FB0C
|
||||
+#define PHY_IPG_VAL 0x47323232
|
||||
+
|
||||
+struct ipq4019_usb_phy {
|
||||
+ struct device *dev;
|
||||
+ struct phy *phy;
|
||||
+ void __iomem *base;
|
||||
+ struct reset_control *por_rst;
|
||||
+ struct reset_control *srif_rst;
|
||||
+};
|
||||
+
|
||||
+static int ipq4019_ss_phy_power_off(struct phy *_phy)
|
||||
+{
|
||||
+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
|
||||
+
|
||||
+ reset_control_assert(phy->por_rst);
|
||||
+ msleep(10);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ipq4019_ss_phy_power_on(struct phy *_phy)
|
||||
+{
|
||||
+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
|
||||
+
|
||||
+ ipq4019_ss_phy_power_off(_phy);
|
||||
+
|
||||
+ reset_control_deassert(phy->por_rst);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct phy_ops ipq4019_usb_ss_phy_ops = {
|
||||
+ .power_on = ipq4019_ss_phy_power_on,
|
||||
+ .power_off = ipq4019_ss_phy_power_off,
|
||||
+};
|
||||
+
|
||||
+static int ipq4019_hs_phy_power_off(struct phy *_phy)
|
||||
+{
|
||||
+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
|
||||
+
|
||||
+ reset_control_assert(phy->por_rst);
|
||||
+ msleep(10);
|
||||
+
|
||||
+ reset_control_assert(phy->srif_rst);
|
||||
+ msleep(10);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ipq4019_hs_phy_power_on(struct phy *_phy)
|
||||
+{
|
||||
+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
|
||||
+
|
||||
+ ipq4019_hs_phy_power_off(_phy);
|
||||
+
|
||||
+ reset_control_deassert(phy->srif_rst);
|
||||
+ msleep(10);
|
||||
+
|
||||
+ writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
|
||||
+ writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
|
||||
+ writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
|
||||
+ writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
|
||||
+ writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
|
||||
+ writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
|
||||
+ writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
|
||||
+ msleep(10);
|
||||
+
|
||||
+ reset_control_deassert(phy->por_rst);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct phy_ops ipq4019_usb_hs_phy_ops = {
|
||||
+ .power_on = ipq4019_hs_phy_power_on,
|
||||
+ .power_off = ipq4019_hs_phy_power_off,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id ipq4019_usb_phy_of_match[] = {
|
||||
+ { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hs_phy_ops},
|
||||
+ { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ss_phy_ops},
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, ipq4019_usb_phy_of_match);
|
||||
+
|
||||
+static int ipq4019_usb_phy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct resource *res;
|
||||
+ struct phy_provider *phy_provider;
|
||||
+ struct ipq4019_usb_phy *phy;
|
||||
+ const struct of_device_id *match;
|
||||
+
|
||||
+ match = of_match_device(ipq4019_usb_phy_of_match, &pdev->dev);
|
||||
+ if (!match)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
|
||||
+ if (!phy)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ phy->dev = &pdev->dev;
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ phy->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(phy->base)) {
|
||||
+ dev_err(dev, "failed to remap register memory\n");
|
||||
+ return PTR_ERR(phy->base);
|
||||
+ }
|
||||
+
|
||||
+ phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
|
||||
+ if (IS_ERR(phy->por_rst)) {
|
||||
+ if (PTR_ERR(phy->por_rst) != -EPROBE_DEFER)
|
||||
+ dev_err(dev, "POR reset is missing\n");
|
||||
+ return PTR_ERR(phy->por_rst);
|
||||
+ }
|
||||
+
|
||||
+ phy->srif_rst = devm_reset_control_get_optional(phy->dev, "srif_rst");
|
||||
+ if (IS_ERR(phy->srif_rst))
|
||||
+ return PTR_ERR(phy->srif_rst);
|
||||
+
|
||||
+ phy->phy = devm_phy_create(dev, NULL, match->data);
|
||||
+ if (IS_ERR(phy->phy)) {
|
||||
+ dev_err(dev, "failed to create PHY\n");
|
||||
+ return PTR_ERR(phy->phy);
|
||||
+ }
|
||||
+ phy_set_drvdata(phy->phy, phy);
|
||||
+
|
||||
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
+
|
||||
+ return PTR_ERR_OR_ZERO(phy_provider);
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver ipq4019_usb_phy_driver = {
|
||||
+ .probe = ipq4019_usb_phy_probe,
|
||||
+ .driver = {
|
||||
+ .of_match_table = ipq4019_usb_phy_of_match,
|
||||
+ .name = "ipq4019-usb-phy",
|
||||
+ }
|
||||
+};
|
||||
+module_platform_driver(ipq4019_usb_phy_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver");
|
||||
+MODULE_AUTHOR("John Crispin <john@phrozen.org>");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
--- a/drivers/phy/qualcomm/Makefile
|
||||
+++ b/drivers/phy/qualcomm/Makefile
|
||||
@@ -1,6 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
|
||||
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
|
||||
+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
|
||||
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
|
||||
obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
|
||||
obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
|
||||
@ -0,0 +1,123 @@
|
||||
From 1fc7d5523e21ed140fed43c4dde011a3b6d9ba08 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Tue, 24 Jul 2018 14:47:55 +0200
|
||||
Subject: [PATCH 3/3] qcom: ipq4019: add USB devicetree nodes
|
||||
|
||||
This patch makes USB work on the Dakota EVB.
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++
|
||||
2 files changed, 94 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -109,5 +109,25 @@
|
||||
wifi@a800000 {
|
||||
status = "ok";
|
||||
};
|
||||
+
|
||||
+ usb3_ss_phy: ssphy@9a000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb3_hs_phy: hsphy@a6000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb3: usb3@8af8800 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb2_hs_phy: hsphy@a8000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb2: usb2@60f8800 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -563,5 +563,79 @@
|
||||
"legacy";
|
||||
status = "disabled";
|
||||
};
|
||||
+
|
||||
+ usb3_ss_phy: ssphy@9a000 {
|
||||
+ compatible = "qcom,usb-ss-ipq4019-phy";
|
||||
+ #phy-cells = <0>;
|
||||
+ reg = <0x9a000 0x800>;
|
||||
+ reg-names = "phy_base";
|
||||
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
|
||||
+ reset-names = "por_rst";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb3_hs_phy: hsphy@a6000 {
|
||||
+ compatible = "qcom,usb-hs-ipq4019-phy";
|
||||
+ #phy-cells = <0>;
|
||||
+ reg = <0xa6000 0x40>;
|
||||
+ reg-names = "phy_base";
|
||||
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
|
||||
+ reset-names = "por_rst", "srif_rst";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb3@8af8800 {
|
||||
+ compatible = "qcom,dwc3";
|
||||
+ reg = <0x8af8800 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
|
||||
+ <&gcc GCC_USB3_SLEEP_CLK>,
|
||||
+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
|
||||
+ clock-names = "master", "sleep", "mock_utmi";
|
||||
+ ranges;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ dwc3@8a00000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x8a00000 0xf8000>;
|
||||
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
|
||||
+ phy-names = "usb2-phy", "usb3-phy";
|
||||
+ dr_mode = "host";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb2_hs_phy: hsphy@a8000 {
|
||||
+ compatible = "qcom,usb-hs-ipq4019-phy";
|
||||
+ #phy-cells = <0>;
|
||||
+ reg = <0xa8000 0x40>;
|
||||
+ reg-names = "phy_base";
|
||||
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
|
||||
+ reset-names = "por_rst", "srif_rst";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb2@60f8800 {
|
||||
+ compatible = "qcom,dwc3";
|
||||
+ reg = <0x60f8800 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
|
||||
+ <&gcc GCC_USB2_SLEEP_CLK>,
|
||||
+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
|
||||
+ clock-names = "master", "sleep", "mock_utmi";
|
||||
+ ranges;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ dwc3@6000000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x6000000 0xf8000>;
|
||||
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ phys = <&usb2_hs_phy>;
|
||||
+ phy-names = "usb2-phy";
|
||||
+ dr_mode = "host";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,70 @@
|
||||
From patchwork Mon May 21 20:57:38 2018
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v5,3/4] ARM: dts: qcom: add gpio-ranges property
|
||||
X-Patchwork-Submitter: Christian Lamparter <chunkeey@gmail.com>
|
||||
X-Patchwork-Id: 917856
|
||||
Message-Id: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com>
|
||||
To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
|
||||
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org
|
||||
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
|
||||
Linus Walleij <linus.walleij@linaro.org>,
|
||||
Stephen Boyd <sboyd@kernel.org>, David Brown <david.brown@linaro.org>,
|
||||
Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
|
||||
Andy Gross <andy.gross@linaro.org>,
|
||||
Sven Eckelmann <sven.eckelmann@openmesh.com>
|
||||
Date: Mon, 21 May 2018 22:57:38 +0200
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
List-Id: <linux-gpio.vger.kernel.org>
|
||||
|
||||
This patch adds the gpio-ranges property to almost all of
|
||||
the Qualcomm ARM platforms that utilize the pinctrl-msm
|
||||
framework.
|
||||
|
||||
The gpio-ranges property is part of the gpiolib subsystem.
|
||||
As a result, the binding text is available in section
|
||||
"2.1 gpio- and pin-controller interaction" of
|
||||
Documentation/devicetree/bindings/gpio/gpio.txt
|
||||
|
||||
For more information please see the patch titled:
|
||||
"pinctrl: msm: fix gpio-hog related boot issues" from
|
||||
this series.
|
||||
|
||||
Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
|
||||
Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019]
|
||||
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
---
|
||||
To help with git bisect, the DT update patch has been intentionally
|
||||
placed after the "pinctrl: msm: fix gpio-hog related boot issues".
|
||||
Otherwise - if the order was reveresed - and bisect decides to split
|
||||
between these two patches, the gpiochip_add_pin_ranges() function
|
||||
will be executed twice with the same parameters for the same pinctrl.
|
||||
---
|
||||
arch/arm/boot/dts/qcom-apq8064.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-apq8084.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-msm8660.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-msm8960.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-msm8974.dtsi | 1 +
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
|
||||
arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
|
||||
arch/arm64/boot/dts/qcom/msm8992.dtsi | 1 +
|
||||
arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 +
|
||||
arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 +
|
||||
13 files changed, 14 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -201,6 +201,7 @@
|
||||
compatible = "qcom,ipq4019-pinctrl";
|
||||
reg = <0x01000000 0x300000>;
|
||||
gpio-controller;
|
||||
+ gpio-ranges = <&tlmm 0 0 100>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
@ -0,0 +1,115 @@
|
||||
From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@googlemail.com>
|
||||
Date: Sun, 11 Mar 2018 14:41:31 +0100
|
||||
Subject: [PATCH 2/2] clk: fix apss cpu overclocking
|
||||
|
||||
There's an interaction issue between the clk changes:"
|
||||
clk: qcom: ipq4019: Add the apss cpu pll divider clock node
|
||||
clk: qcom: ipq4019: remove fixed clocks and add pll clocks
|
||||
" and the cpufreq-dt.
|
||||
|
||||
cpufreq-dt is now spamming the kernel-log with the following:
|
||||
|
||||
[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
|
||||
for freq 761142857 (-34)
|
||||
|
||||
This only happens on certain devices like the Compex WPJ428
|
||||
and AVM FritzBox!4040. However, other devices like the Asus
|
||||
RT-AC58U and Meraki MR33 work just fine.
|
||||
|
||||
The issue stem from the fact that all higher CPU-Clocks
|
||||
are achieved by switching the clock-parent to the P_DDRPLLAPSS
|
||||
(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
|
||||
as part of the DDR calibration.
|
||||
|
||||
For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
|
||||
at round 533 MHz (ddrpllsdcc = 190285714 Hz).
|
||||
|
||||
whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
|
||||
clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
|
||||
|
||||
This patch attempts to fix the issue by modifying
|
||||
clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
|
||||
to use a new qcom_find_freq_close() function, which returns the closest
|
||||
matching frequency, instead of the next higher. This way, the SoC in
|
||||
the FB4040 (with its max clock speed of 710.4 MHz) will no longer
|
||||
try to overclock to 761 MHz.
|
||||
|
||||
Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
|
||||
1 file changed, 31 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/clk/qcom/gcc-ipq4019.c
|
||||
+++ b/drivers/clk/qcom/gcc-ipq4019.c
|
||||
@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
|
||||
.reg = 0x2f020,
|
||||
};
|
||||
|
||||
+
|
||||
+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
|
||||
+ unsigned long rate)
|
||||
+{
|
||||
+ const struct freq_tbl *last = NULL;
|
||||
+
|
||||
+ for ( ; f->freq; f++) {
|
||||
+ if (rate == f->freq)
|
||||
+ return f;
|
||||
+
|
||||
+ if (f->freq > rate) {
|
||||
+ if (!last ||
|
||||
+ (f->freq - rate) < (rate - last->freq))
|
||||
+ return f;
|
||||
+ else
|
||||
+ return last;
|
||||
+ }
|
||||
+ last = f;
|
||||
+ }
|
||||
+
|
||||
+ return last;
|
||||
+}
|
||||
+
|
||||
/*
|
||||
* Round rate function for APSS CPU PLL Clock divider.
|
||||
* It looks up the frequency table and returns the next higher frequency
|
||||
@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
|
||||
struct clk_hw *p_hw;
|
||||
const struct freq_tbl *f;
|
||||
|
||||
- f = qcom_find_freq(pll->freq_tbl, rate);
|
||||
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c
|
||||
u32 mask;
|
||||
int ret;
|
||||
|
||||
- f = qcom_find_freq(pll->freq_tbl, rate);
|
||||
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
@@ -1305,6 +1328,7 @@ static unsigned long
|
||||
clk_cpu_div_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
+ const struct freq_tbl *f;
|
||||
struct clk_fepll *pll = to_clk_fepll(hw);
|
||||
u32 cdiv, pre_div;
|
||||
u64 rate;
|
||||
@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
|
||||
rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
|
||||
do_div(rate, pre_div);
|
||||
|
||||
- return rate;
|
||||
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
|
||||
+ if (!f)
|
||||
+ return rate;
|
||||
+
|
||||
+ return f->freq;
|
||||
};
|
||||
|
||||
static const struct clk_ops clk_regmap_cpu_div_ops = {
|
||||
@ -0,0 +1,29 @@
|
||||
From 09f145f417a5d64d6b8d4476699dfb0eccc6c784 Mon Sep 17 00:00:00 2001
|
||||
From: Abhishek Sahu <absahu@codeaurora.org>
|
||||
Date: Tue, 7 May 2019 10:14:05 +0300
|
||||
Subject: [PATCH] ipq40xx: fix high resolution timer
|
||||
|
||||
Cherry-picked from CAF QSDK repo.
|
||||
Original commit message:
|
||||
The kernel is failing in switching the timer for high resolution
|
||||
mode and clock source operates in 10ms resolution. The always-on
|
||||
property needs to be given for timer device tree node to make
|
||||
clock source working in 1ns resolution.
|
||||
|
||||
Change-Id: I7c00b3c74d97c2a30ac9f05e18b511a0550fd459
|
||||
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
|
||||
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -166,6 +166,7 @@
|
||||
<1 4 0xf08>,
|
||||
<1 1 0xf08>;
|
||||
clock-frequency = <48000000>;
|
||||
+ always-on;
|
||||
};
|
||||
|
||||
soc {
|
||||
@ -0,0 +1,153 @@
|
||||
From 97043d292365ae39d62b54a6d79dff98d048b501 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robert.marko@sartura.hr>
|
||||
Date: Wed, 22 Jan 2020 12:44:14 +0100
|
||||
Subject: [PATCH] From ebf652b408200504194be32ad0a3f5bb49d6000a Mon Sep 17
|
||||
00:00:00 2001 From: Robert Marko <robert.marko@sartura.hr> Date: Sun, 12 Jan
|
||||
2020 12:30:01 +0100 Subject: [PATCH] regulator: add IPQ4019 SDHCI VQMMC LDO
|
||||
driver
|
||||
|
||||
This introduces the IPQ4019 VQMMC LDO driver needed for
|
||||
the SD/EMMC driver I/O level operation.
|
||||
This will enable introducing SD/EMMC support for the built-in controller.
|
||||
|
||||
Signed-off-by: Mantas Pucka <mantas@8devices.com>
|
||||
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
|
||||
Link: https://lore.kernel.org/r/20200112113003.11110-1-robert.marko@sartura.hr
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/regulator/Kconfig | 7 ++
|
||||
drivers/regulator/Makefile | 1 +
|
||||
drivers/regulator/vqmmc-ipq4019-regulator.c | 101 ++++++++++++++++++++
|
||||
3 files changed, 109 insertions(+)
|
||||
create mode 100644 drivers/regulator/vqmmc-ipq4019-regulator.c
|
||||
|
||||
--- a/drivers/regulator/Kconfig
|
||||
+++ b/drivers/regulator/Kconfig
|
||||
@@ -1077,6 +1077,13 @@ config REGULATOR_VEXPRESS
|
||||
This driver provides support for voltage regulators available
|
||||
on the ARM Ltd's Versatile Express platform.
|
||||
|
||||
+config REGULATOR_VQMMC_IPQ4019
|
||||
+ tristate "IPQ4019 VQMMC SD LDO regulator support"
|
||||
+ depends on ARCH_QCOM
|
||||
+ help
|
||||
+ This driver provides support for the VQMMC LDO I/0
|
||||
+ voltage regulator of the IPQ4019 SD/EMMC controller.
|
||||
+
|
||||
config REGULATOR_WM831X
|
||||
tristate "Wolfson Microelectronics WM831x PMIC regulators"
|
||||
depends on MFD_WM831X
|
||||
--- a/drivers/regulator/Makefile
|
||||
+++ b/drivers/regulator/Makefile
|
||||
@@ -132,6 +132,7 @@ obj-$(CONFIG_REGULATOR_TWL4030) += twl-r
|
||||
obj-$(CONFIG_REGULATOR_UNIPHIER) += uniphier-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_VCTRL) += vctrl-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_VEXPRESS) += vexpress-regulator.o
|
||||
+obj-$(CONFIG_REGULATOR_VQMMC_IPQ4019) += vqmmc-ipq4019-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_WM831X) += wm831x-dcdc.o
|
||||
obj-$(CONFIG_REGULATOR_WM831X) += wm831x-isink.o
|
||||
obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/regulator/vqmmc-ipq4019-regulator.c
|
||||
@@ -0,0 +1,101 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+//
|
||||
+// Copyright (c) 2019 Mantas Pucka <mantas@8devices.com>
|
||||
+// Copyright (c) 2019 Robert Marko <robert.marko@sartura.hr>
|
||||
+//
|
||||
+// Driver for IPQ4019 SD/MMC controller's I/O LDO voltage regulator
|
||||
+
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/regulator/driver.h>
|
||||
+#include <linux/regulator/machine.h>
|
||||
+#include <linux/regulator/of_regulator.h>
|
||||
+
|
||||
+static const unsigned int ipq4019_vmmc_voltages[] = {
|
||||
+ 1500000, 1800000, 2500000, 3000000,
|
||||
+};
|
||||
+
|
||||
+static const struct regulator_ops ipq4019_regulator_voltage_ops = {
|
||||
+ .list_voltage = regulator_list_voltage_table,
|
||||
+ .map_voltage = regulator_map_voltage_ascend,
|
||||
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
|
||||
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
|
||||
+};
|
||||
+
|
||||
+static const struct regulator_desc vmmc_regulator = {
|
||||
+ .name = "vmmcq",
|
||||
+ .ops = &ipq4019_regulator_voltage_ops,
|
||||
+ .type = REGULATOR_VOLTAGE,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .volt_table = ipq4019_vmmc_voltages,
|
||||
+ .n_voltages = ARRAY_SIZE(ipq4019_vmmc_voltages),
|
||||
+ .vsel_reg = 0,
|
||||
+ .vsel_mask = 0x3,
|
||||
+};
|
||||
+
|
||||
+static const struct regmap_config ipq4019_vmmcq_regmap_config = {
|
||||
+ .reg_bits = 32,
|
||||
+ .reg_stride = 4,
|
||||
+ .val_bits = 32,
|
||||
+};
|
||||
+
|
||||
+static int ipq4019_regulator_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct regulator_init_data *init_data;
|
||||
+ struct regulator_config cfg = {};
|
||||
+ struct regulator_dev *rdev;
|
||||
+ struct resource *res;
|
||||
+ struct regmap *rmap;
|
||||
+ void __iomem *base;
|
||||
+
|
||||
+ init_data = of_get_regulator_init_data(dev, dev->of_node,
|
||||
+ &vmmc_regulator);
|
||||
+ if (!init_data)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ base = devm_ioremap_resource(dev, res);
|
||||
+ if (IS_ERR(base))
|
||||
+ return PTR_ERR(base);
|
||||
+
|
||||
+ rmap = devm_regmap_init_mmio(dev, base, &ipq4019_vmmcq_regmap_config);
|
||||
+ if (IS_ERR(rmap))
|
||||
+ return PTR_ERR(rmap);
|
||||
+
|
||||
+ cfg.dev = dev;
|
||||
+ cfg.init_data = init_data;
|
||||
+ cfg.of_node = dev->of_node;
|
||||
+ cfg.regmap = rmap;
|
||||
+
|
||||
+ rdev = devm_regulator_register(dev, &vmmc_regulator, &cfg);
|
||||
+ if (IS_ERR(rdev)) {
|
||||
+ dev_err(dev, "Failed to register regulator: %ld\n",
|
||||
+ PTR_ERR(rdev));
|
||||
+ return PTR_ERR(rdev);
|
||||
+ }
|
||||
+ platform_set_drvdata(pdev, rdev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id regulator_ipq4019_of_match[] = {
|
||||
+ { .compatible = "qcom,vqmmc-ipq4019-regulator", },
|
||||
+ {},
|
||||
+};
|
||||
+
|
||||
+static struct platform_driver ipq4019_regulator_driver = {
|
||||
+ .probe = ipq4019_regulator_probe,
|
||||
+ .driver = {
|
||||
+ .name = "vqmmc-ipq4019-regulator",
|
||||
+ .of_match_table = of_match_ptr(regulator_ipq4019_of_match),
|
||||
+ },
|
||||
+};
|
||||
+module_platform_driver(ipq4019_regulator_driver);
|
||||
+
|
||||
+MODULE_LICENSE("GPL");
|
||||
+MODULE_AUTHOR("Mantas Pucka <mantas@8devices.com>");
|
||||
+MODULE_DESCRIPTION("IPQ4019 VQMMC voltage regulator");
|
||||
@ -0,0 +1,36 @@
|
||||
From 04b3b72b5b8fdb883bfdc619cb29b03641b1cc6a Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Thu, 15 Aug 2019 19:28:23 +0200
|
||||
Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI controller node
|
||||
|
||||
IPQ4019 has a built in SD/eMMC controller which is supported by the
|
||||
SDHCI MSM driver, by the "qcom,sdhci-msm-v4" binding.
|
||||
So lets add the appropriate node for it.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -209,6 +209,18 @@
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
+ sdhci: sdhci@7824900 {
|
||||
+ compatible = "qcom,sdhci-msm-v4";
|
||||
+ reg = <0x7824900 0x11c>, <0x7824000 0x800>;
|
||||
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "hc_irq", "pwr_irq";
|
||||
+ bus-width = <8>;
|
||||
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
|
||||
+ <&gcc GCC_DCD_XO_CLK>;
|
||||
+ clock-names = "core", "iface", "xo";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
blsp_dma: dma@7884000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07884000 0x23000>;
|
||||
@ -0,0 +1,32 @@
|
||||
From 77d9b11ae7269dcf376c3b9493209f712524e986 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robert.marko@sartura.hr>
|
||||
Date: Wed, 22 Jan 2020 12:56:35 +0100
|
||||
Subject: [PATCH] arm: dts: IPQ4019: add SDHCI VQMMC LDO node
|
||||
|
||||
Since we now have driver for the SDHCI VQMMC LDO needed
|
||||
for I/0 voltage levels lets introduce the necessary node for it.
|
||||
|
||||
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -209,6 +209,16 @@
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
+ vqmmc: regulator@1948000 {
|
||||
+ compatible = "qcom,vqmmc-ipq4019-regulator";
|
||||
+ reg = <0x01948000 0x4>;
|
||||
+ regulator-name = "vqmmc";
|
||||
+ regulator-min-microvolt = <1500000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-always-on;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
sdhci: sdhci@7824900 {
|
||||
compatible = "qcom,sdhci-msm-v4";
|
||||
reg = <0x7824900 0x11c>, <0x7824000 0x800>;
|
||||
@ -0,0 +1,52 @@
|
||||
From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001
|
||||
From: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
Date: Tue, 28 Mar 2017 22:35:33 +0530
|
||||
Subject: [PATCH] clk: qcom: ipq4019: add ess reset
|
||||
|
||||
Added the ESS reset in IPQ4019 GCC.
|
||||
|
||||
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
---
|
||||
drivers/clk/qcom/gcc-ipq4019.c | 11 +++++++++++
|
||||
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++
|
||||
2 files changed, 22 insertions(+)
|
||||
|
||||
--- a/drivers/clk/qcom/gcc-ipq4019.c
|
||||
+++ b/drivers/clk/qcom/gcc-ipq4019.c
|
||||
@@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i
|
||||
[GCC_TCSR_BCR] = {0x22000, 0},
|
||||
[GCC_MPM_BCR] = {0x24000, 0},
|
||||
[GCC_SPDM_BCR] = {0x25000, 0},
|
||||
+ [ESS_MAC1_ARES] = {0x1200C, 0},
|
||||
+ [ESS_MAC2_ARES] = {0x1200C, 1},
|
||||
+ [ESS_MAC3_ARES] = {0x1200C, 2},
|
||||
+ [ESS_MAC4_ARES] = {0x1200C, 3},
|
||||
+ [ESS_MAC5_ARES] = {0x1200C, 4},
|
||||
+ [ESS_PSGMII_ARES] = {0x1200C, 5},
|
||||
+ [ESS_MAC1_CLK_DIS] = {0x1200C, 8},
|
||||
+ [ESS_MAC2_CLK_DIS] = {0x1200C, 9},
|
||||
+ [ESS_MAC3_CLK_DIS] = {0x1200C, 10},
|
||||
+ [ESS_MAC4_CLK_DIS] = {0x1200C, 11},
|
||||
+ [ESS_MAC5_CLK_DIS] = {0x1200C, 12},
|
||||
};
|
||||
|
||||
static const struct regmap_config gcc_ipq4019_regmap_config = {
|
||||
--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
@@ -165,5 +165,16 @@
|
||||
#define GCC_QDSS_BCR 69
|
||||
#define GCC_MPM_BCR 70
|
||||
#define GCC_SPDM_BCR 71
|
||||
+#define ESS_MAC1_ARES 72
|
||||
+#define ESS_MAC2_ARES 73
|
||||
+#define ESS_MAC3_ARES 74
|
||||
+#define ESS_MAC4_ARES 75
|
||||
+#define ESS_MAC5_ARES 76
|
||||
+#define ESS_PSGMII_ARES 77
|
||||
+#define ESS_MAC1_CLK_DIS 78
|
||||
+#define ESS_MAC2_CLK_DIS 79
|
||||
+#define ESS_MAC3_CLK_DIS 80
|
||||
+#define ESS_MAC4_CLK_DIS 81
|
||||
+#define ESS_MAC5_CLK_DIS 82
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,26 @@
|
||||
From 158acdbf0336f601971637f988b57a6a67a0869b Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Sun, 15 Dec 2019 13:10:50 +0100
|
||||
Subject: [PATCH] mtd: spi-nor: Add support for mx25r3235f
|
||||
|
||||
Add MTD support for the Macronix MX25R3235F SPI NOR chip from Macronix.
|
||||
The chip has 4MB of total capacity, divided into a total of 64 sectors,
|
||||
each 64KB sized. The chip also supports 4KB large sectors.
|
||||
Additionally, it supports dual and quad read modes.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
drivers/mtd/spi-nor/spi-nor.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/drivers/mtd/spi-nor/spi-nor.c
|
||||
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
||||
@@ -2286,6 +2286,8 @@ static const struct flash_info spi_nor_i
|
||||
{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
|
||||
{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
|
||||
{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
|
||||
+ { "mx25r3235f", INFO(0xc22816, 0, 64 * 1024, 64,
|
||||
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
|
||||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
|
||||
@ -0,0 +1,25 @@
|
||||
From 0e28623a11f3916c1fe5b7e789c7ab8ca932a929 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Wed, 22 Jan 2020 13:02:13 +0100
|
||||
Subject: [PATCH] mmc: sdhci: sdhci-msm: use sdhci_set_clock instead of
|
||||
sdhci_msm_set_clock
|
||||
|
||||
When using sdhci_msm_set_clock clock setting will fail, so lets
|
||||
use the generic sdhci_set_clock.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
drivers/mmc/host/sdhci-msm.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/mmc/host/sdhci-msm.c
|
||||
+++ b/drivers/mmc/host/sdhci-msm.c
|
||||
@@ -1724,7 +1724,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
|
||||
|
||||
static const struct sdhci_ops sdhci_msm_ops = {
|
||||
.reset = sdhci_reset,
|
||||
- .set_clock = sdhci_msm_set_clock,
|
||||
+ .set_clock = sdhci_set_clock,
|
||||
.get_min_clock = sdhci_msm_get_min_clock,
|
||||
.get_max_clock = sdhci_msm_get_max_clock,
|
||||
.set_bus_width = sdhci_set_bus_width,
|
||||
225
target/linux/ipq40xx/patches-5.4/700-net-add-qualcomm-mdio.patch
Normal file
225
target/linux/ipq40xx/patches-5.4/700-net-add-qualcomm-mdio.patch
Normal file
@ -0,0 +1,225 @@
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
+++ b/drivers/net/phy/Kconfig
|
||||
@@ -580,6 +580,13 @@ config XILINX_GMII2RGMII
|
||||
the Reduced Gigabit Media Independent Interface(RGMII) between
|
||||
Ethernet physical media devices and the Gigabit Ethernet controller.
|
||||
|
||||
+config MDIO_IPQ40XX
|
||||
+ tristate "Qualcomm Atheros ipq40xx MDIO interface"
|
||||
+ depends on HAS_IOMEM && OF
|
||||
+ ---help---
|
||||
+ This driver supports the MDIO interface found in Qualcomm
|
||||
+ Atheros ipq40xx Soc chip.
|
||||
+
|
||||
endif # PHYLIB
|
||||
|
||||
config MICREL_KS8995MA
|
||||
--- a/drivers/net/phy/Makefile
|
||||
+++ b/drivers/net/phy/Makefile
|
||||
@@ -51,6 +51,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium
|
||||
obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
|
||||
obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
|
||||
obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o
|
||||
+obj-$(CONFIG_MDIO_IPQ40XX) += mdio-ipq40xx.o
|
||||
obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
|
||||
obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o
|
||||
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/net/phy/mdio-ipq40xx.c
|
||||
@@ -0,0 +1,196 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * Permission to use, copy, modify, and/or distribute this software for
|
||||
+ * any purpose with or without fee is hereby granted, provided that the
|
||||
+ * above copyright notice and this permission notice appear in all copies.
|
||||
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
|
||||
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/mutex.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/of_address.h>
|
||||
+#include <linux/of_mdio.h>
|
||||
+#include <linux/phy.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+
|
||||
+#define MDIO_CTRL_0_REG 0x40
|
||||
+#define MDIO_CTRL_1_REG 0x44
|
||||
+#define MDIO_CTRL_2_REG 0x48
|
||||
+#define MDIO_CTRL_3_REG 0x4c
|
||||
+#define MDIO_CTRL_4_REG 0x50
|
||||
+#define MDIO_CTRL_4_ACCESS_BUSY BIT(16)
|
||||
+#define MDIO_CTRL_4_ACCESS_START BIT(8)
|
||||
+#define MDIO_CTRL_4_ACCESS_CODE_READ 0
|
||||
+#define MDIO_CTRL_4_ACCESS_CODE_WRITE 1
|
||||
+#define CTRL_0_REG_DEFAULT_VALUE 0x150FF
|
||||
+
|
||||
+#define IPQ40XX_MDIO_RETRY 1000
|
||||
+#define IPQ40XX_MDIO_DELAY 10
|
||||
+
|
||||
+struct ipq40xx_mdio_data {
|
||||
+ struct mii_bus *mii_bus;
|
||||
+ void __iomem *membase;
|
||||
+ struct device *dev;
|
||||
+};
|
||||
+
|
||||
+static int ipq40xx_mdio_wait_busy(struct ipq40xx_mdio_data *am)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < IPQ40XX_MDIO_RETRY; i++) {
|
||||
+ unsigned int busy;
|
||||
+
|
||||
+ busy = readl(am->membase + MDIO_CTRL_4_REG) &
|
||||
+ MDIO_CTRL_4_ACCESS_BUSY;
|
||||
+ if (!busy)
|
||||
+ return 0;
|
||||
+
|
||||
+ /* BUSY might take to be cleard by 15~20 times of loop */
|
||||
+ udelay(IPQ40XX_MDIO_DELAY);
|
||||
+ }
|
||||
+
|
||||
+ dev_err(am->dev, "%s: MDIO operation timed out\n", am->mii_bus->name);
|
||||
+
|
||||
+ return -ETIMEDOUT;
|
||||
+}
|
||||
+
|
||||
+static int ipq40xx_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
|
||||
+{
|
||||
+ struct ipq40xx_mdio_data *am = bus->priv;
|
||||
+ int value = 0;
|
||||
+ unsigned int cmd = 0;
|
||||
+
|
||||
+ lockdep_assert_held(&bus->mdio_lock);
|
||||
+
|
||||
+ if (ipq40xx_mdio_wait_busy(am))
|
||||
+ return -ETIMEDOUT;
|
||||
+
|
||||
+ /* issue the phy address and reg */
|
||||
+ writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
|
||||
+
|
||||
+ cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_READ;
|
||||
+
|
||||
+ /* issue read command */
|
||||
+ writel(cmd, am->membase + MDIO_CTRL_4_REG);
|
||||
+
|
||||
+ /* Wait read complete */
|
||||
+ if (ipq40xx_mdio_wait_busy(am))
|
||||
+ return -ETIMEDOUT;
|
||||
+
|
||||
+ /* Read data */
|
||||
+ value = readl(am->membase + MDIO_CTRL_3_REG);
|
||||
+
|
||||
+ return value;
|
||||
+}
|
||||
+
|
||||
+static int ipq40xx_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
|
||||
+ u16 value)
|
||||
+{
|
||||
+ struct ipq40xx_mdio_data *am = bus->priv;
|
||||
+ unsigned int cmd = 0;
|
||||
+
|
||||
+ lockdep_assert_held(&bus->mdio_lock);
|
||||
+
|
||||
+ if (ipq40xx_mdio_wait_busy(am))
|
||||
+ return -ETIMEDOUT;
|
||||
+
|
||||
+ /* issue the phy address and reg */
|
||||
+ writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
|
||||
+
|
||||
+ /* issue write data */
|
||||
+ writel(value, am->membase + MDIO_CTRL_2_REG);
|
||||
+
|
||||
+ cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_WRITE;
|
||||
+ /* issue write command */
|
||||
+ writel(cmd, am->membase + MDIO_CTRL_4_REG);
|
||||
+
|
||||
+ /* Wait write complete */
|
||||
+ if (ipq40xx_mdio_wait_busy(am))
|
||||
+ return -ETIMEDOUT;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ipq40xx_mdio_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct ipq40xx_mdio_data *am;
|
||||
+ struct resource *res;
|
||||
+ int i;
|
||||
+
|
||||
+ am = devm_kzalloc(&pdev->dev, sizeof(*am), GFP_KERNEL);
|
||||
+ if (!am)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ if (!res) {
|
||||
+ dev_err(&pdev->dev, "no iomem resource found\n");
|
||||
+ return -ENXIO;
|
||||
+ }
|
||||
+
|
||||
+ am->membase = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(am->membase)) {
|
||||
+ dev_err(&pdev->dev, "unable to ioremap registers\n");
|
||||
+ return PTR_ERR(am->membase);
|
||||
+ }
|
||||
+
|
||||
+ am->mii_bus = devm_mdiobus_alloc(&pdev->dev);
|
||||
+ if (!am->mii_bus)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ writel(CTRL_0_REG_DEFAULT_VALUE, am->membase + MDIO_CTRL_0_REG);
|
||||
+
|
||||
+ am->mii_bus->name = "ipq40xx_mdio";
|
||||
+ am->mii_bus->read = ipq40xx_mdio_read;
|
||||
+ am->mii_bus->write = ipq40xx_mdio_write;
|
||||
+ am->mii_bus->priv = am;
|
||||
+ am->mii_bus->parent = &pdev->dev;
|
||||
+ snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev));
|
||||
+
|
||||
+ am->dev = &pdev->dev;
|
||||
+ platform_set_drvdata(pdev, am);
|
||||
+
|
||||
+ return of_mdiobus_register(am->mii_bus, pdev->dev.of_node);
|
||||
+}
|
||||
+
|
||||
+static int ipq40xx_mdio_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct ipq40xx_mdio_data *am = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ mdiobus_unregister(am->mii_bus);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id ipq40xx_mdio_dt_ids[] = {
|
||||
+ { .compatible = "qcom,ipq4019-mdio" },
|
||||
+ { }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, ipq40xx_mdio_dt_ids);
|
||||
+
|
||||
+static struct platform_driver ipq40xx_mdio_driver = {
|
||||
+ .probe = ipq40xx_mdio_probe,
|
||||
+ .remove = ipq40xx_mdio_remove,
|
||||
+ .driver = {
|
||||
+ .name = "ipq40xx-mdio",
|
||||
+ .of_match_table = ipq40xx_mdio_dt_ids,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(ipq40xx_mdio_driver);
|
||||
+
|
||||
+#define DRV_VERSION "1.0"
|
||||
+
|
||||
+MODULE_DESCRIPTION("IPQ40XX MDIO interface driver");
|
||||
+MODULE_AUTHOR("Qualcomm Atheros");
|
||||
+MODULE_VERSION(DRV_VERSION);
|
||||
+MODULE_LICENSE("Dual BSD/GPL");
|
||||
@ -0,0 +1,52 @@
|
||||
From 09ed737593f71bcca08a537a6c15264a1a6add08 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sun, 20 Nov 2016 01:10:33 +0100
|
||||
Subject: [PATCH] dts: ipq4019: add mdio node for ethernet
|
||||
|
||||
This patch adds the mdio device-tree node.
|
||||
This is where the switch is connected to, so it's needed
|
||||
for the ethernet interfaces.
|
||||
|
||||
Note: The driver isn't anywhere close to be upstream,
|
||||
so the info might change.
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 28 ++++++++++++++++++++++++++++
|
||||
1 file changed, 28 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -588,6 +588,34 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ mdio: mdio@90000 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ compatible = "qcom,ipq4019-mdio";
|
||||
+ reg = <0x90000 0x64>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ ethphy0: ethernet-phy@0 {
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+
|
||||
+ ethphy1: ethernet-phy@1 {
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+
|
||||
+ ethphy2: ethernet-phy@2 {
|
||||
+ reg = <2>;
|
||||
+ };
|
||||
+
|
||||
+ ethphy3: ethernet-phy@3 {
|
||||
+ reg = <3>;
|
||||
+ };
|
||||
+
|
||||
+ ethphy4: ethernet-phy@4 {
|
||||
+ reg = <4>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb3_ss_phy: ssphy@9a000 {
|
||||
compatible = "qcom,usb-ss-ipq4019-phy";
|
||||
#phy-cells = <0>;
|
||||
@ -0,0 +1,46 @@
|
||||
From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sun, 20 Nov 2016 02:20:54 +0100
|
||||
Subject: [PATCH] dts: ipq4019: add PHY/switch nodes
|
||||
|
||||
This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii"
|
||||
nodes which are needed for the ar40xx.c driver to initialize the
|
||||
switch.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++
|
||||
1 file changed, 23 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -616,6 +616,29 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ ess-switch@c000000 {
|
||||
+ compatible = "qcom,ess-switch";
|
||||
+ reg = <0xc000000 0x80000>;
|
||||
+ switch_access_mode = "local bus";
|
||||
+ resets = <&gcc ESS_RESET>;
|
||||
+ reset-names = "ess_rst";
|
||||
+ clocks = <&gcc GCC_ESS_CLK>;
|
||||
+ clock-names = "ess_clk";
|
||||
+ switch_cpu_bmp = <0x1>;
|
||||
+ switch_lan_bmp = <0x1e>;
|
||||
+ switch_wan_bmp = <0x20>;
|
||||
+ switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
|
||||
+ switch_initvlas = <0x7c 0x54>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ ess-psgmii@98000 {
|
||||
+ compatible = "qcom,ess-psgmii";
|
||||
+ reg = <0x98000 0x800>;
|
||||
+ psgmii_access_mode = "local bus";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
usb3_ss_phy: ssphy@9a000 {
|
||||
compatible = "qcom,usb-ss-ipq4019-phy";
|
||||
#phy-cells = <0>;
|
||||
@ -0,0 +1,53 @@
|
||||
From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001
|
||||
From: Rakesh Nair <ranair@codeaurora.org>
|
||||
Date: Wed, 20 Jul 2016 15:02:01 +0530
|
||||
Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in
|
||||
netdev_ops
|
||||
|
||||
Add callback support to get default vlan tag and register
|
||||
receive flow steering filter.
|
||||
|
||||
Used by IPQ4019 ess-edma driver.
|
||||
|
||||
BUG=chrome-os-partner:33096
|
||||
TEST=none
|
||||
|
||||
Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75
|
||||
Signed-off-by: Rakesh Nair <ranair@codeaurora.org>
|
||||
Reviewed-on: https://chromium-review.googlesource.com/362203
|
||||
Commit-Ready: Grant Grundler <grundler@chromium.org>
|
||||
Tested-by: Grant Grundler <grundler@chromium.org>
|
||||
Reviewed-by: Grant Grundler <grundler@chromium.org>
|
||||
---
|
||||
include/linux/netdevice.h | 13 +++++++++++++
|
||||
1 file changed, 13 insertions(+)
|
||||
|
||||
--- a/include/linux/netdevice.h
|
||||
+++ b/include/linux/netdevice.h
|
||||
@@ -773,6 +773,16 @@ struct xps_map {
|
||||
#define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
|
||||
- sizeof(struct xps_map)) / sizeof(u16))
|
||||
|
||||
+#ifdef CONFIG_RFS_ACCEL
|
||||
+typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,
|
||||
+ __be32 src,
|
||||
+ __be32 dst,
|
||||
+ __be16 sport,
|
||||
+ __be16 dport,
|
||||
+ u8 proto,
|
||||
+ u16 rxq_index,
|
||||
+ u32 action);
|
||||
+#endif
|
||||
/*
|
||||
* This structure holds all XPS maps for device. Maps are indexed by CPU.
|
||||
*/
|
||||
@@ -1376,6 +1386,9 @@ struct net_device_ops {
|
||||
const struct sk_buff *skb,
|
||||
u16 rxq_index,
|
||||
u32 flow_id);
|
||||
+ int (*ndo_register_rfs_filter)(struct net_device *dev,
|
||||
+ set_rfs_filter_callback_t set_filter);
|
||||
+ int (*ndo_get_default_vlan_tag)(struct net_device *net);
|
||||
#endif
|
||||
int (*ndo_add_slave)(struct net_device *dev,
|
||||
struct net_device *slave_dev,
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,23 @@
|
||||
--- a/drivers/net/phy/ar40xx.c
|
||||
+++ b/drivers/net/phy/ar40xx.c
|
||||
@@ -2021,6 +2021,12 @@ static int ar40xx_probe(struct platform_
|
||||
/* register switch */
|
||||
swdev = &priv->dev;
|
||||
|
||||
+ if (priv->mii_bus == NULL) {
|
||||
+ dev_err(&pdev->dev, "Probe failed - Missing PHYs!\n");
|
||||
+ ret = -ENODEV;
|
||||
+ goto err_missing_phy;
|
||||
+ }
|
||||
+
|
||||
swdev->alias = dev_name(&priv->mii_bus->dev);
|
||||
|
||||
swdev->cpu_port = AR40XX_PORT_CPU;
|
||||
@@ -2052,6 +2058,7 @@ err_unregister_switch:
|
||||
unregister_switch(&priv->dev);
|
||||
err_unregister_phy:
|
||||
phy_driver_unregister(&ar40xx_phy_driver);
|
||||
+err_missing_phy:
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
return ret;
|
||||
}
|
||||
@ -0,0 +1,36 @@
|
||||
From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@googlemail.com>
|
||||
Date: Thu, 19 Jan 2017 02:01:31 +0100
|
||||
Subject: [PATCH 33/38] NET: add qualcomm essedma ethernet driver
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
drivers/net/ethernet/qualcomm/Kconfig | 9 +++++++++
|
||||
drivers/net/ethernet/qualcomm/Makefile | 1 +
|
||||
2 files changed, 10 insertions(+)
|
||||
|
||||
--- a/drivers/net/ethernet/qualcomm/Kconfig
|
||||
+++ b/drivers/net/ethernet/qualcomm/Kconfig
|
||||
@@ -62,4 +62,13 @@ config QCOM_EMAC
|
||||
|
||||
source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
|
||||
|
||||
+config ESSEDMA
|
||||
+ tristate "Qualcomm Atheros ESS Edma support"
|
||||
+ ---help---
|
||||
+ This driver supports ethernet edma adapter.
|
||||
+ Say Y to build this driver.
|
||||
+
|
||||
+ To compile this driver as a module, choose M here. The module
|
||||
+ will be called essedma.ko.
|
||||
+
|
||||
endif # NET_VENDOR_QUALCOMM
|
||||
--- a/drivers/net/ethernet/qualcomm/Makefile
|
||||
+++ b/drivers/net/ethernet/qualcomm/Makefile
|
||||
@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
|
||||
qcauart-objs := qca_uart.o
|
||||
|
||||
obj-y += emac/
|
||||
+obj-$(CONFIG_ESSEDMA) += essedma/
|
||||
|
||||
obj-$(CONFIG_RMNET) += rmnet/
|
||||
@ -0,0 +1,92 @@
|
||||
From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sun, 20 Nov 2016 01:01:10 +0100
|
||||
Subject: [PATCH] dts: ipq4019: add ethernet essedma node
|
||||
|
||||
This patch adds the device-tree node for the ethernet
|
||||
interfaces.
|
||||
|
||||
Note: The driver isn't anywhere close to be upstream,
|
||||
so the info might change.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 60 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -38,6 +38,8 @@
|
||||
spi1 = &blsp1_spi2;
|
||||
i2c0 = &blsp1_i2c3;
|
||||
i2c1 = &blsp1_i2c4;
|
||||
+ ethernet0 = &gmac0;
|
||||
+ ethernet1 = &gmac1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
@@ -639,6 +641,64 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ edma@c080000 {
|
||||
+ compatible = "qcom,ess-edma";
|
||||
+ reg = <0xc080000 0x8000>;
|
||||
+ qcom,page-mode = <0>;
|
||||
+ qcom,rx_head_buf_size = <1540>;
|
||||
+ qcom,mdio_supported;
|
||||
+ qcom,poll_required = <1>;
|
||||
+ qcom,num_gmac = <2>;
|
||||
+ interrupts = <0 65 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 66 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 67 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 68 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 69 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 70 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 71 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 72 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 73 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 74 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 75 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 76 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 77 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 78 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 79 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 80 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 240 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 241 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 242 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 243 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 244 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 245 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 246 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 247 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 248 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 249 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 250 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 251 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 252 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 253 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 254 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 255 IRQ_TYPE_EDGE_RISING>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ gmac0: gmac0 {
|
||||
+ local-mac-address = [00 00 00 00 00 00];
|
||||
+ vlan_tag = <1 0x1f>;
|
||||
+ };
|
||||
+
|
||||
+ gmac1: gmac1 {
|
||||
+ local-mac-address = [00 00 00 00 00 00];
|
||||
+ qcom,phy_mdio_addr = <4>;
|
||||
+ qcom,poll_required = <1>;
|
||||
+ qcom,forced_speed = <1000>;
|
||||
+ qcom,forced_duplex = <1>;
|
||||
+ vlan_tag = <2 0x20>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb3_ss_phy: ssphy@9a000 {
|
||||
compatible = "qcom,usb-ss-ipq4019-phy";
|
||||
#phy-cells = <0>;
|
||||
@ -0,0 +1,69 @@
|
||||
From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sun, 20 Nov 2016 01:01:10 +0100
|
||||
Subject: [PATCH] dts: ipq4019: add ethernet ipqess node
|
||||
|
||||
This patch adds the device-tree node for the ipqess ethernet
|
||||
interfaces.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 60 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -699,6 +699,53 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ gmac: ethernet@c080000 {
|
||||
+ compatible = "qcom,ipq4019-ess-edma";
|
||||
+ reg = <0xc080000 0x8000>;
|
||||
+ interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ phy-mode = "internal";
|
||||
+ fixed-link {
|
||||
+ speed = <1000>;
|
||||
+ full-duplex;
|
||||
+ pause;
|
||||
+ asym-pause;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb3_ss_phy: ssphy@9a000 {
|
||||
compatible = "qcom,usb-ss-ipq4019-phy";
|
||||
#phy-cells = <0>;
|
||||
@ -0,0 +1,180 @@
|
||||
From: Christian Lamparter <chunkeey@googlemail.com>
|
||||
Subject: SoC: add qualcomm syscon
|
||||
--- a/drivers/soc/qcom/Makefile
|
||||
+++ b/drivers/soc/qcom/Makefile
|
||||
@@ -20,6 +20,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
|
||||
obj-$(CONFIG_QCOM_SMSM) += smsm.o
|
||||
obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
|
||||
obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
|
||||
+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
|
||||
obj-$(CONFIG_QCOM_APR) += apr.o
|
||||
obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o
|
||||
obj-$(CONFIG_QCOM_SDM845_LLCC) += llcc-sdm845.o
|
||||
--- a/drivers/soc/qcom/Kconfig
|
||||
+++ b/drivers/soc/qcom/Kconfig
|
||||
@@ -183,6 +183,13 @@ config QCOM_SOCINFO
|
||||
Say yes here to support the Qualcomm socinfo driver, providing
|
||||
information about the SoC to user space.
|
||||
|
||||
+config QCOM_TCSR
|
||||
+ tristate "QCOM Top Control and Status Registers"
|
||||
+ depends on ARCH_QCOM
|
||||
+ help
|
||||
+ Say y here to enable TCSR support. The TCSR provides control
|
||||
+ functions for various peripherals.
|
||||
+
|
||||
config QCOM_WCNSS_CTRL
|
||||
tristate "Qualcomm WCNSS control driver"
|
||||
depends on ARCH_QCOM || COMPILE_TEST
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/qcom/qcom_tcsr.c
|
||||
@@ -0,0 +1,98 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License rev 2 and
|
||||
+ * only rev 2 as published by the free Software foundation.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+
|
||||
+#define TCSR_USB_PORT_SEL 0xb0
|
||||
+#define TCSR_USB_HSPHY_CONFIG 0xC
|
||||
+
|
||||
+#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0
|
||||
+#define TCSR_ESS_INTERFACE_SEL_MASK 0xf
|
||||
+
|
||||
+#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0
|
||||
+#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4
|
||||
+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4
|
||||
+
|
||||
+static int tcsr_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct resource *res;
|
||||
+ const struct device_node *node = pdev->dev.of_node;
|
||||
+ void __iomem *base;
|
||||
+ u32 val;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ base = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(base))
|
||||
+ return PTR_ERR(base);
|
||||
+
|
||||
+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
|
||||
+ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
|
||||
+ writel(val, base + TCSR_USB_PORT_SEL);
|
||||
+ }
|
||||
+
|
||||
+ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
|
||||
+ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
|
||||
+ writel(val, base + TCSR_USB_HSPHY_CONFIG);
|
||||
+ }
|
||||
+
|
||||
+ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
|
||||
+ u32 tmp = 0;
|
||||
+ dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
|
||||
+ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
|
||||
+ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
|
||||
+ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
|
||||
+ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
|
||||
+ }
|
||||
+
|
||||
+ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
|
||||
+ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
|
||||
+ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
|
||||
+ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
|
||||
+ }
|
||||
+
|
||||
+ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
|
||||
+ dev_info(&pdev->dev,
|
||||
+ "setting wifi_noc_memtype_m0_m2 = %x\n", val);
|
||||
+ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id tcsr_dt_match[] = {
|
||||
+ { .compatible = "qcom,tcsr", },
|
||||
+ { },
|
||||
+};
|
||||
+
|
||||
+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
|
||||
+
|
||||
+static struct platform_driver tcsr_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "tcsr",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = tcsr_dt_match,
|
||||
+ },
|
||||
+ .probe = tcsr_probe,
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(tcsr_driver);
|
||||
+
|
||||
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
|
||||
+MODULE_DESCRIPTION("QCOM TCSR driver");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/soc/qcom,tcsr.h
|
||||
@@ -0,0 +1,48 @@
|
||||
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 and
|
||||
+ * only version 2 as published by the Free Software Foundation.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ */
|
||||
+#ifndef __DT_BINDINGS_QCOM_TCSR_H
|
||||
+#define __DT_BINDINGS_QCOM_TCSR_H
|
||||
+
|
||||
+#define TCSR_USB_SELECT_USB3_P0 0x1
|
||||
+#define TCSR_USB_SELECT_USB3_P1 0x2
|
||||
+#define TCSR_USB_SELECT_USB3_DUAL 0x3
|
||||
+
|
||||
+/* IPQ40xx HS PHY Mode Select */
|
||||
+#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7
|
||||
+#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7
|
||||
+
|
||||
+/* IPQ40xx ess interface mode select */
|
||||
+#define TCSR_ESS_PSGMII 0
|
||||
+#define TCSR_ESS_PSGMII_RGMII5 1
|
||||
+#define TCSR_ESS_PSGMII_RMII0 2
|
||||
+#define TCSR_ESS_PSGMII_RMII1 4
|
||||
+#define TCSR_ESS_PSGMII_RMII0_RMII1 6
|
||||
+#define TCSR_ESS_PSGMII_RGMII4 9
|
||||
+
|
||||
+/*
|
||||
+ * IPQ40xx WiFi Global Config
|
||||
+ * Bit 30:AXID_EN
|
||||
+ * Enable AXI master bus Axid translating to confirm all txn submitted by order
|
||||
+ * Bit 24: Use locally generated socslv_wxi_bvalid
|
||||
+ * 1: use locally generate socslv_wxi_bvalid for performance.
|
||||
+ * 0: use SNOC socslv_wxi_bvalid.
|
||||
+ */
|
||||
+#define TCSR_WIFI_GLB_CFG 0x41000000
|
||||
+
|
||||
+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
|
||||
+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222
|
||||
+
|
||||
+/* TCSR A/B REG */
|
||||
+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
|
||||
+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
|
||||
+
|
||||
+#endif
|
||||
@ -0,0 +1,26 @@
|
||||
--- a/drivers/regulator/Kconfig
|
||||
+++ b/drivers/regulator/Kconfig
|
||||
@@ -334,6 +334,13 @@ config REGULATOR_HI655X
|
||||
This driver provides support for the voltage regulators of the
|
||||
Hisilicon Hi655x PMIC device.
|
||||
|
||||
+config REGULATOR_VQMMC_IPQ4019
|
||||
+ tristate "IPQ4019 VQMMC SD LDO regulator support"
|
||||
+ depends on ARCH_QCOM
|
||||
+ help
|
||||
+ This driver provides support for the VQMMC LDO I/0
|
||||
+ voltage regulator of the IPQ4019 SD/EMMC controller.
|
||||
+
|
||||
config REGULATOR_ISL9305
|
||||
tristate "Intersil ISL9305 regulator"
|
||||
depends on I2C
|
||||
--- a/drivers/regulator/Makefile
|
||||
+++ b/drivers/regulator/Makefile
|
||||
@@ -43,6 +43,7 @@ obj-$(CONFIG_REGULATOR_GPIO) += gpio-reg
|
||||
obj-$(CONFIG_REGULATOR_HI6421) += hi6421-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_HI6421V530) += hi6421v530-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_HI655X) += hi655x-regulator.o
|
||||
+obj-$(CONFIG_REGULATOR_VQMMC_IPQ4019) += ipq4019-vqmmc-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_ISL9305) += isl9305.o
|
||||
obj-$(CONFIG_REGULATOR_LM363X) += lm363x-regulator.o
|
||||
@ -0,0 +1,33 @@
|
||||
From beae4078c07d3cdc90473a2b35eb0d2b4f3c922c Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Sat, 14 Sep 2019 23:13:17 +0200
|
||||
Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI VQMMC LDO regulator node
|
||||
|
||||
IPQ4019 has a built in SD/eMMC controller which depends on
|
||||
VQMMC LDO regulator working.
|
||||
Since we have a driver for it lets add the appropriate node for it.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -216,6 +216,16 @@
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
+ vqmmc: regulator@1948000 {
|
||||
+ compatible = "qcom,ipq4019-vqmmc-regulator";
|
||||
+ reg = <0x01948000 0x4>;
|
||||
+ regulator-name = "vqmmc";
|
||||
+ regulator-min-microvolt = <1500000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-always-on;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
blsp_dma: dma@7884000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07884000 0x23000>;
|
||||
@ -0,0 +1,41 @@
|
||||
Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI controller node
|
||||
Date: Thu, 15 Aug 2019 19:28:23 +0200
|
||||
Message-Id: <20190815172823.12028-1-robimarko@gmail.com>
|
||||
X-Mailer: git-send-email 2.21.0
|
||||
MIME-Version: 1.0
|
||||
Sender: linux-arm-msm-owner@vger.kernel.org
|
||||
Precedence: bulk
|
||||
List-ID: <linux-arm-msm.vger.kernel.org>
|
||||
X-Mailing-List: linux-arm-msm@vger.kernel.org
|
||||
X-Virus-Scanned: ClamAV using ClamSMTP
|
||||
|
||||
IPQ4019 has a built in SD/eMMC controller which is supported by the
|
||||
SDHCI MSM driver, by the "qcom,sdhci-msm-v4" binding.
|
||||
So lets add the appropriate node for it.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -226,6 +226,18 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ sdhci: sdhci@7824900 {
|
||||
+ compatible = "qcom,sdhci-msm-v4";
|
||||
+ reg = <0x7824900 0x11c>, <0x7824000 0x800>;
|
||||
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "hc_irq", "pwr_irq";
|
||||
+ bus-width = <8>;
|
||||
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
|
||||
+ <&gcc GCC_DCD_XO_CLK>;
|
||||
+ clock-names = "core", "iface", "xo";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
blsp_dma: dma@7884000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07884000 0x23000>;
|
||||
157
target/linux/ipq40xx/patches-5.4/900-dts-ipq4019-ap-dk01.1.patch
Normal file
157
target/linux/ipq40xx/patches-5.4/900-dts-ipq4019-ap-dk01.1.patch
Normal file
@ -0,0 +1,157 @@
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -15,6 +15,7 @@
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
+#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
|
||||
@@ -29,6 +30,32 @@
|
||||
};
|
||||
|
||||
soc {
|
||||
+ tcsr@194b000 {
|
||||
+ /* select hostmode */
|
||||
+ compatible = "qcom,tcsr";
|
||||
+ reg = <0x194b000 0x100>;
|
||||
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ ess_tcsr@1953000 {
|
||||
+ compatible = "qcom,tcsr";
|
||||
+ reg = <0x1953000 0x1000>;
|
||||
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
+ };
|
||||
+
|
||||
+ tcsr@1949000 {
|
||||
+ compatible = "qcom,tcsr";
|
||||
+ reg = <0x1949000 0x100>;
|
||||
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
+ };
|
||||
+
|
||||
+ tcsr@1957000 {
|
||||
+ compatible = "qcom,tcsr";
|
||||
+ reg = <0x1957000 0x100>;
|
||||
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
+ };
|
||||
+
|
||||
rng@22000 {
|
||||
status = "ok";
|
||||
};
|
||||
@@ -74,14 +101,6 @@
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
cs-gpios = <&tlmm 54 0>;
|
||||
-
|
||||
- mx25l25635e@0 {
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
- reg = <0>;
|
||||
- compatible = "mx25l25635e";
|
||||
- spi-max-frequency = <24000000>;
|
||||
- };
|
||||
};
|
||||
|
||||
serial@78af000 {
|
||||
@@ -110,6 +129,22 @@
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
+ mdio@90000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ ess-switch@c000000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ ess-psgmii@98000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ edma@c080000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
usb3_ss_phy: ssphy@9a000 {
|
||||
status = "ok";
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
@@ -18,5 +18,73 @@
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
|
||||
+ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1";
|
||||
|
||||
+ memory {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x80000000 0x10000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&blsp1_spi1 {
|
||||
+ mx25l25635f@0 {
|
||||
+ compatible = "mx25l25635f", "jedec,spi-nor";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <24000000>;
|
||||
+
|
||||
+ SBL1@0 {
|
||||
+ label = "SBL1";
|
||||
+ reg = <0x0 0x40000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ MIBIB@40000 {
|
||||
+ label = "MIBIB";
|
||||
+ reg = <0x40000 0x20000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ QSEE@60000 {
|
||||
+ label = "QSEE";
|
||||
+ reg = <0x60000 0x60000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ CDT@c0000 {
|
||||
+ label = "CDT";
|
||||
+ reg = <0xc0000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ DDRPARAMS@d0000 {
|
||||
+ label = "DDRPARAMS";
|
||||
+ reg = <0xd0000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ APPSBLENV@e0000 {
|
||||
+ label = "APPSBLENV";
|
||||
+ reg = <0xe0000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ APPSBL@f0000 {
|
||||
+ label = "APPSBL";
|
||||
+ reg = <0xf0000 0x80000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ ART@170000 {
|
||||
+ label = "ART";
|
||||
+ reg = <0x170000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ kernel@180000 {
|
||||
+ label = "kernel";
|
||||
+ reg = <0x180000 0x400000>;
|
||||
+ };
|
||||
+ rootfs@580000 {
|
||||
+ label = "rootfs";
|
||||
+ reg = <0x580000 0x1600000>;
|
||||
+ };
|
||||
+ firmware@180000 {
|
||||
+ label = "firmware";
|
||||
+ reg = <0x180000 0x1a00000>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
@ -0,0 +1,61 @@
|
||||
From a10fab12a927e60b7141a602e740d70cb4d09e4a Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Thu, 9 Mar 2017 11:03:18 +0100
|
||||
Subject: [PATCH] arm: boot: add dts files
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
arch/arm/boot/dts/Makefile | 23 +++++++++++++++++++++++
|
||||
1 file changed, 23 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -837,11 +837,48 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
qcom-apq8074-dragonboard.dtb \
|
||||
qcom-apq8084-ifc6540.dtb \
|
||||
qcom-apq8084-mtp.dtb \
|
||||
+ qcom-ipq4018-a42.dtb \
|
||||
+ qcom-ipq4018-ap120c-ac.dtb \
|
||||
+ qcom-ipq4018-dap-2610.dtb \
|
||||
+ qcom-ipq4018-cs-w3-wd1200g-eup.dtb \
|
||||
+ qcom-ipq4018-ea6350v3.dtb \
|
||||
+ qcom-ipq4018-eap1300.dtb \
|
||||
+ qcom-ipq4018-emd1.dtb \
|
||||
+ qcom-ipq4018-ens620ext.dtb \
|
||||
+ qcom-ipq4018-ex6100v2.dtb \
|
||||
+ qcom-ipq4018-ex6150v2.dtb \
|
||||
+ qcom-ipq4018-ex6200v2.dtb \
|
||||
+ qcom-ipq4018-fritzbox-4040.dtb \
|
||||
+ qcom-ipq4018-jalapeno.dtb \
|
||||
+ qcom-ipq4018-meshpoint-one.dtb \
|
||||
+ qcom-ipq4018-nbg6617.dtb \
|
||||
+ qcom-ipq4018-rt-ac58u.dtb \
|
||||
+ qcom-ipq4018-wre6606.dtb \
|
||||
qcom-ipq4019-ap.dk01.1-c1.dtb \
|
||||
qcom-ipq4019-ap.dk04.1-c1.dtb \
|
||||
qcom-ipq4019-ap.dk04.1-c3.dtb \
|
||||
qcom-ipq4019-ap.dk07.1-c1.dtb \
|
||||
qcom-ipq4019-ap.dk07.1-c2.dtb \
|
||||
+ qcom-ipq4019-a62.dtb \
|
||||
+ qcom-ipq4019-cm520-79f.dtb \
|
||||
+ qcom-ipq4019-hugo-ac1200.dtb \
|
||||
+ qcom-ipq4019-fritzbox-7530.dtb \
|
||||
+ qcom-ipq4019-fritzrepeater-1200.dtb \
|
||||
+ qcom-ipq4019-fritzrepeater-3000.dtb \
|
||||
+ qcom-ipq4019-ea8300.dtb \
|
||||
+ qcom-ipq4019-map-ac2200.dtb \
|
||||
+ qcom-ipq4019-r619ac.dtb \
|
||||
+ qcom-ipq4019-r619ac-pcie.dtb \
|
||||
+ qcom-ipq4019-e2600ac-c1.dtb \
|
||||
+ qcom-ipq4019-e2600ac-c2.dtb \
|
||||
+ qcom-ipq4019-u4019-32m.dtb \
|
||||
+ qcom-ipq4019-rt-acrh17.dtb \
|
||||
+ qcom-ipq4019-wpj419.dtb \
|
||||
+ qcom-ipq4028-wpj428.dtb \
|
||||
+ qcom-ipq4029-ap-303.dtb \
|
||||
+ qcom-ipq4029-ap-303h.dtb \
|
||||
+ qcom-ipq4029-gl-b1300.dtb \
|
||||
+ qcom-ipq4029-mr33.dtb \
|
||||
qcom-ipq8064-ap148.dtb \
|
||||
qcom-msm8660-surf.dtb \
|
||||
qcom-msm8960-cdp.dtb \
|
||||
@ -0,0 +1,46 @@
|
||||
--- a/drivers/net/usb/qmi_wwan.c
|
||||
+++ b/drivers/net/usb/qmi_wwan.c
|
||||
@@ -1297,6 +1297,7 @@ static const struct usb_device_id products[] = {
|
||||
{QMI_FIXED_INTF(0x03f0, 0x9d1d, 1)}, /* HP lt4120 Snapdragon X5 LTE */
|
||||
{QMI_FIXED_INTF(0x22de, 0x9061, 3)}, /* WeTelecom WPD-600N */
|
||||
{QMI_QUIRK_SET_DTR(0x1e0e, 0x9001, 5)}, /* SIMCom 7100E, 7230E, 7600E ++ */
|
||||
+ {QMI_FIXED_INTF(0x1c9e, 0x9b3c, 4)}, /* LONGSUNG_U9300 */
|
||||
{QMI_QUIRK_SET_DTR(0x2c7c, 0x0121, 4)}, /* Quectel EC21 Mini PCIe */
|
||||
{QMI_QUIRK_SET_DTR(0x2c7c, 0x0191, 4)}, /* Quectel EG91 */
|
||||
{QMI_FIXED_INTF(0x2c7c, 0x0296, 4)}, /* Quectel BG96 */
|
||||
--- a/drivers/usb/serial/option.c
|
||||
+++ b/drivers/usb/serial/option.c
|
||||
@@ -381,6 +381,7 @@ static void option_instat_callback(struct urb *urb);
|
||||
* Mobidata, etc sell under their own brand names.
|
||||
*/
|
||||
#define LONGCHEER_VENDOR_ID 0x1c9e
|
||||
+#define LONGSUNG_U9300_PRODUCT_ID 0x9b3c
|
||||
|
||||
/* 4G Systems products */
|
||||
/* This is the 4G XS Stick W14 a.k.a. Mobilcom Debitel Surf-Stick *
|
||||
@@ -571,6 +572,16 @@ static void option_instat_callback(struct urb *urb);
|
||||
/* Device needs ZLP */
|
||||
#define ZLP BIT(17)
|
||||
|
||||
+struct option_blacklist_info {
|
||||
+ /* bitfield of interface numbers for OPTION_BLACKLIST_SENDSETUP */
|
||||
+ const unsigned long sendsetup;
|
||||
+ /* bitfield of interface numbers for OPTION_BLACKLIST_RESERVED_IF */
|
||||
+ const unsigned long reserved;
|
||||
+};
|
||||
+
|
||||
+static const struct option_blacklist_info longsung_u9300_blacklist = {
|
||||
+ .reserved = BIT(4),
|
||||
+};
|
||||
|
||||
static const struct usb_device_id option_ids[] = {
|
||||
{ USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_COLT) },
|
||||
@@ -605,6 +616,8 @@ static const struct usb_device_id option_ids[] = {
|
||||
{ USB_DEVICE(QUANTA_VENDOR_ID, QUANTA_PRODUCT_GLE) },
|
||||
{ USB_DEVICE(QUANTA_VENDOR_ID, 0xea42),
|
||||
.driver_info = RSVD(4) },
|
||||
+ { USB_DEVICE(LONGCHEER_VENDOR_ID,LONGSUNG_U9300_PRODUCT_ID),
|
||||
+ .driver_info = (kernel_ulong_t)&longsung_u9300_blacklist},
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, 0x1c05, USB_CLASS_COMM, 0x02, 0xff) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, 0x1c1f, USB_CLASS_COMM, 0x02, 0xff) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, 0x1c23, USB_CLASS_COMM, 0x02, 0xff) },
|
||||
@ -0,0 +1,12 @@
|
||||
--- a/drivers/of/fdt.c
|
||||
+++ b/drivers/of/fdt.c
|
||||
@@ -1059,6 +1059,9 @@ int __init early_init_dt_scan_chosen(uns
|
||||
p = of_get_flat_dt_prop(node, "bootargs", &l);
|
||||
if (p != NULL && l > 0)
|
||||
strlcpy(data, p, min(l, COMMAND_LINE_SIZE));
|
||||
+ p = of_get_flat_dt_prop(node, "bootargs-append", &l);
|
||||
+ if (p != NULL && l > 0)
|
||||
+ strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
|
||||
|
||||
/*
|
||||
* CONFIG_CMDLINE is meant to be a default in case nothing else
|
||||
Loading…
Reference in New Issue
Block a user