From 08a42ef057b0c1c31d66358f29376b939487c732 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Fri, 16 Oct 2020 21:42:11 +0200 Subject: [PATCH 01/15] mac80211: fix memory leak on filtered powersave frames After the status rework, ieee80211_tx_status_ext is leaking un-acknowledged packets for stations in powersave mode. To fix this, move the code handling those packets from __ieee80211_tx_status into ieee80211_tx_status_ext Reported-by: Tobias Waldvogel Signed-off-by: Felix Fietkau --- ...ory-leak-on-filtered-powersave-frame.patch | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 package/kernel/mac80211/patches/subsys/333-mac80211-fix-memory-leak-on-filtered-powersave-frame.patch diff --git a/package/kernel/mac80211/patches/subsys/333-mac80211-fix-memory-leak-on-filtered-powersave-frame.patch b/package/kernel/mac80211/patches/subsys/333-mac80211-fix-memory-leak-on-filtered-powersave-frame.patch new file mode 100644 index 0000000000..cdbbcf5d06 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/333-mac80211-fix-memory-leak-on-filtered-powersave-frame.patch @@ -0,0 +1,55 @@ +From: Felix Fietkau +Date: Fri, 16 Oct 2020 19:54:49 +0200 +Subject: [PATCH] mac80211: fix memory leak on filtered powersave frames + +After the status rework, ieee80211_tx_status_ext is leaking un-acknowledged +packets for stations in powersave mode. +To fix this, move the code handling those packets from __ieee80211_tx_status +into ieee80211_tx_status_ext + +Reported-by: Tobias Waldvogel +Fixes: 3318111cf63d ("mac80211: reduce duplication in tx status functions") +Signed-off-by: Felix Fietkau +--- + +--- a/net/mac80211/status.c ++++ b/net/mac80211/status.c +@@ -49,7 +49,8 @@ static void ieee80211_handle_filtered_fr + int ac; + + if (info->flags & (IEEE80211_TX_CTL_NO_PS_BUFFER | +- IEEE80211_TX_CTL_AMPDU)) { ++ IEEE80211_TX_CTL_AMPDU | ++ IEEE80211_TX_CTL_HW_80211_ENCAP)) { + ieee80211_free_txskb(&local->hw, skb); + return; + } +@@ -924,15 +925,6 @@ static void __ieee80211_tx_status(struct + ieee80211_mpsp_trigger_process( + ieee80211_get_qos_ctl(hdr), sta, true, acked); + +- if (!acked && test_sta_flag(sta, WLAN_STA_PS_STA)) { +- /* +- * The STA is in power save mode, so assume +- * that this TX packet failed because of that. +- */ +- ieee80211_handle_filtered_frame(local, sta, skb); +- return; +- } +- + if (ieee80211_hw_check(&local->hw, HAS_RATE_CONTROL) && + (ieee80211_is_data(hdr->frame_control)) && + (rates_idx != -1)) +@@ -1159,6 +1151,12 @@ void ieee80211_tx_status_ext(struct ieee + -info->status.ack_signal); + } + } else if (test_sta_flag(sta, WLAN_STA_PS_STA)) { ++ /* ++ * The STA is in power save mode, so assume ++ * that this TX packet failed because of that. ++ */ ++ if (skb) ++ ieee80211_handle_filtered_frame(local, sta, skb); + return; + } else if (noack_success) { + /* nothing to do here, do not account as lost */ From 93f98b283553af9f354b396bc8bb91ca791cc566 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sat, 17 Oct 2020 11:14:11 +0200 Subject: [PATCH 02/15] kernel: remove obsolete non-upstream block2mtd patches Since block2mtd is not used for firmware images anymore, these patches are no longer needed Signed-off-by: Felix Fietkau --- .../pending-4.19/440-block2mtd_init.patch | 116 ------------------ .../pending-4.19/441-block2mtd_probe.patch | 47 ------- .../pending-5.4/440-block2mtd_init.patch | 116 ------------------ .../pending-5.4/441-block2mtd_probe.patch | 47 ------- 4 files changed, 326 deletions(-) delete mode 100644 target/linux/generic/pending-4.19/440-block2mtd_init.patch delete mode 100644 target/linux/generic/pending-4.19/441-block2mtd_probe.patch delete mode 100644 target/linux/generic/pending-5.4/440-block2mtd_init.patch delete mode 100644 target/linux/generic/pending-5.4/441-block2mtd_probe.patch diff --git a/target/linux/generic/pending-4.19/440-block2mtd_init.patch b/target/linux/generic/pending-4.19/440-block2mtd_init.patch deleted file mode 100644 index b8ec11f3dd..0000000000 --- a/target/linux/generic/pending-4.19/440-block2mtd_init.patch +++ /dev/null @@ -1,116 +0,0 @@ -From: Felix Fietkau -Subject: block2mtd - -Signed-off-by: Felix Fietkau ---- - drivers/mtd/devices/block2mtd.c | 30 ++++++++++++++++++++---------- - 1 file changed, 20 insertions(+), 10 deletions(-) - ---- a/drivers/mtd/devices/block2mtd.c -+++ b/drivers/mtd/devices/block2mtd.c -@@ -26,6 +26,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -214,7 +215,7 @@ static void block2mtd_free_device(struct - - - static struct block2mtd_dev *add_device(char *devname, int erase_size, -- int timeout) -+ const char *mtdname, int timeout) - { - #ifndef MODULE - int i; -@@ -222,6 +223,7 @@ static struct block2mtd_dev *add_device( - const fmode_t mode = FMODE_READ | FMODE_WRITE | FMODE_EXCL; - struct block_device *bdev; - struct block2mtd_dev *dev; -+ struct mtd_partition *part; - char *name; - - if (!devname) -@@ -278,13 +280,16 @@ static struct block2mtd_dev *add_device( - - /* Setup the MTD structure */ - /* make the name contain the block device in */ -- name = kasprintf(GFP_KERNEL, "block2mtd: %s", devname); -+ if (!mtdname) -+ mtdname = devname; -+ name = kmalloc(strlen(mtdname) + 1, GFP_KERNEL); - if (!name) - goto err_destroy_mutex; - -+ strcpy(name, mtdname); - dev->mtd.name = name; - -- dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK; -+ dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK & ~(erase_size - 1); - dev->mtd.erasesize = erase_size; - dev->mtd.writesize = 1; - dev->mtd.writebufsize = PAGE_SIZE; -@@ -297,7 +302,11 @@ static struct block2mtd_dev *add_device( - dev->mtd.priv = dev; - dev->mtd.owner = THIS_MODULE; - -- if (mtd_device_register(&dev->mtd, NULL, 0)) { -+ part = kzalloc(sizeof(struct mtd_partition), GFP_KERNEL); -+ part->name = name; -+ part->offset = 0; -+ part->size = dev->mtd.size; -+ if (mtd_device_register(&dev->mtd, part, 1)) { - /* Device didn't get added, so free the entry */ - goto err_destroy_mutex; - } -@@ -305,8 +314,7 @@ static struct block2mtd_dev *add_device( - list_add(&dev->list, &blkmtd_device_list); - pr_info("mtd%d: [%s] erase_size = %dKiB [%d]\n", - dev->mtd.index, -- dev->mtd.name + strlen("block2mtd: "), -- dev->mtd.erasesize >> 10, dev->mtd.erasesize); -+ mtdname, dev->mtd.erasesize >> 10, dev->mtd.erasesize); - return dev; - - err_destroy_mutex: -@@ -379,7 +387,7 @@ static int block2mtd_setup2(const char * - /* 80 for device, 12 for erase size, 80 for name, 8 for timeout */ - char buf[80 + 12 + 80 + 8]; - char *str = buf; -- char *token[2]; -+ char *token[3]; - char *name; - size_t erase_size = PAGE_SIZE; - unsigned long timeout = MTD_DEFAULT_TIMEOUT; -@@ -393,7 +401,7 @@ static int block2mtd_setup2(const char * - strcpy(str, val); - kill_final_newline(str); - -- for (i = 0; i < 2; i++) -+ for (i = 0; i < 3; i++) - token[i] = strsep(&str, ","); - - if (str) { -@@ -419,8 +427,10 @@ static int block2mtd_setup2(const char * - return 0; - } - } -+ if (token[2] && (strlen(token[2]) + 1 > 80)) -+ pr_err("mtd device name too long\n"); - -- add_device(name, erase_size, timeout); -+ add_device(name, erase_size, token[2], timeout); - - return 0; - } -@@ -454,7 +464,7 @@ static int block2mtd_setup(const char *v - - - module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); --MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,]\""); -+MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,]]\""); - - static int __init block2mtd_init(void) - { diff --git a/target/linux/generic/pending-4.19/441-block2mtd_probe.patch b/target/linux/generic/pending-4.19/441-block2mtd_probe.patch deleted file mode 100644 index 7e974e01ed..0000000000 --- a/target/linux/generic/pending-4.19/441-block2mtd_probe.patch +++ /dev/null @@ -1,47 +0,0 @@ -From: Felix Fietkau -Subject: block2mtd - -Signed-off-by: Felix Fietkau ---- - drivers/mtd/devices/block2mtd.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - ---- a/drivers/mtd/devices/block2mtd.c -+++ b/drivers/mtd/devices/block2mtd.c -@@ -387,7 +387,7 @@ static int block2mtd_setup2(const char * - /* 80 for device, 12 for erase size, 80 for name, 8 for timeout */ - char buf[80 + 12 + 80 + 8]; - char *str = buf; -- char *token[3]; -+ char *token[4]; - char *name; - size_t erase_size = PAGE_SIZE; - unsigned long timeout = MTD_DEFAULT_TIMEOUT; -@@ -401,7 +401,7 @@ static int block2mtd_setup2(const char * - strcpy(str, val); - kill_final_newline(str); - -- for (i = 0; i < 3; i++) -+ for (i = 0; i < 4; i++) - token[i] = strsep(&str, ","); - - if (str) { -@@ -430,6 +430,9 @@ static int block2mtd_setup2(const char * - if (token[2] && (strlen(token[2]) + 1 > 80)) - pr_err("mtd device name too long\n"); - -+ if (token[3] && kstrtoul(token[3], 0, &timeout)) -+ pr_err("invalid timeout\n"); -+ - add_device(name, erase_size, token[2], timeout); - - return 0; -@@ -464,7 +467,7 @@ static int block2mtd_setup(const char *v - - - module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); --MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,]]\""); -+MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,[,]]]\""); - - static int __init block2mtd_init(void) - { diff --git a/target/linux/generic/pending-5.4/440-block2mtd_init.patch b/target/linux/generic/pending-5.4/440-block2mtd_init.patch deleted file mode 100644 index d88c226233..0000000000 --- a/target/linux/generic/pending-5.4/440-block2mtd_init.patch +++ /dev/null @@ -1,116 +0,0 @@ -From: Felix Fietkau -Subject: block2mtd - -Signed-off-by: Felix Fietkau ---- - drivers/mtd/devices/block2mtd.c | 30 ++++++++++++++++++++---------- - 1 file changed, 20 insertions(+), 10 deletions(-) - ---- a/drivers/mtd/devices/block2mtd.c -+++ b/drivers/mtd/devices/block2mtd.c -@@ -26,6 +26,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -214,7 +215,7 @@ static void block2mtd_free_device(struct - - - static struct block2mtd_dev *add_device(char *devname, int erase_size, -- int timeout) -+ const char *mtdname, int timeout) - { - #ifndef MODULE - int i; -@@ -222,6 +223,7 @@ static struct block2mtd_dev *add_device( - const fmode_t mode = FMODE_READ | FMODE_WRITE | FMODE_EXCL; - struct block_device *bdev; - struct block2mtd_dev *dev; -+ struct mtd_partition *part; - char *name; - - if (!devname) -@@ -278,13 +280,16 @@ static struct block2mtd_dev *add_device( - - /* Setup the MTD structure */ - /* make the name contain the block device in */ -- name = kasprintf(GFP_KERNEL, "block2mtd: %s", devname); -+ if (!mtdname) -+ mtdname = devname; -+ name = kmalloc(strlen(mtdname) + 1, GFP_KERNEL); - if (!name) - goto err_destroy_mutex; - -+ strcpy(name, mtdname); - dev->mtd.name = name; - -- dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK; -+ dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK & ~(erase_size - 1); - dev->mtd.erasesize = erase_size; - dev->mtd.writesize = 1; - dev->mtd.writebufsize = PAGE_SIZE; -@@ -297,7 +302,11 @@ static struct block2mtd_dev *add_device( - dev->mtd.priv = dev; - dev->mtd.owner = THIS_MODULE; - -- if (mtd_device_register(&dev->mtd, NULL, 0)) { -+ part = kzalloc(sizeof(struct mtd_partition), GFP_KERNEL); -+ part->name = name; -+ part->offset = 0; -+ part->size = dev->mtd.size; -+ if (mtd_device_register(&dev->mtd, part, 1)) { - /* Device didn't get added, so free the entry */ - goto err_destroy_mutex; - } -@@ -305,8 +314,7 @@ static struct block2mtd_dev *add_device( - list_add(&dev->list, &blkmtd_device_list); - pr_info("mtd%d: [%s] erase_size = %dKiB [%d]\n", - dev->mtd.index, -- dev->mtd.name + strlen("block2mtd: "), -- dev->mtd.erasesize >> 10, dev->mtd.erasesize); -+ mtdname, dev->mtd.erasesize >> 10, dev->mtd.erasesize); - return dev; - - err_destroy_mutex: -@@ -381,7 +389,7 @@ static int block2mtd_setup2(const char * - /* 80 for device, 12 for erase size, 80 for name, 8 for timeout */ - char buf[80 + 12 + 80 + 8]; - char *str = buf; -- char *token[2]; -+ char *token[3]; - char *name; - size_t erase_size = PAGE_SIZE; - unsigned long timeout = MTD_DEFAULT_TIMEOUT; -@@ -395,7 +403,7 @@ static int block2mtd_setup2(const char * - strcpy(str, val); - kill_final_newline(str); - -- for (i = 0; i < 2; i++) -+ for (i = 0; i < 3; i++) - token[i] = strsep(&str, ","); - - if (str) { -@@ -421,8 +429,10 @@ static int block2mtd_setup2(const char * - return 0; - } - } -+ if (token[2] && (strlen(token[2]) + 1 > 80)) -+ pr_err("mtd device name too long\n"); - -- add_device(name, erase_size, timeout); -+ add_device(name, erase_size, token[2], timeout); - - return 0; - } -@@ -456,7 +466,7 @@ static int block2mtd_setup(const char *v - - - module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); --MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,]\""); -+MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,]]\""); - - static int __init block2mtd_init(void) - { diff --git a/target/linux/generic/pending-5.4/441-block2mtd_probe.patch b/target/linux/generic/pending-5.4/441-block2mtd_probe.patch deleted file mode 100644 index cba17a57f3..0000000000 --- a/target/linux/generic/pending-5.4/441-block2mtd_probe.patch +++ /dev/null @@ -1,47 +0,0 @@ -From: Felix Fietkau -Subject: block2mtd - -Signed-off-by: Felix Fietkau ---- - drivers/mtd/devices/block2mtd.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - ---- a/drivers/mtd/devices/block2mtd.c -+++ b/drivers/mtd/devices/block2mtd.c -@@ -389,7 +389,7 @@ static int block2mtd_setup2(const char * - /* 80 for device, 12 for erase size, 80 for name, 8 for timeout */ - char buf[80 + 12 + 80 + 8]; - char *str = buf; -- char *token[3]; -+ char *token[4]; - char *name; - size_t erase_size = PAGE_SIZE; - unsigned long timeout = MTD_DEFAULT_TIMEOUT; -@@ -403,7 +403,7 @@ static int block2mtd_setup2(const char * - strcpy(str, val); - kill_final_newline(str); - -- for (i = 0; i < 3; i++) -+ for (i = 0; i < 4; i++) - token[i] = strsep(&str, ","); - - if (str) { -@@ -432,6 +432,9 @@ static int block2mtd_setup2(const char * - if (token[2] && (strlen(token[2]) + 1 > 80)) - pr_err("mtd device name too long\n"); - -+ if (token[3] && kstrtoul(token[3], 0, &timeout)) -+ pr_err("invalid timeout\n"); -+ - add_device(name, erase_size, token[2], timeout); - - return 0; -@@ -466,7 +469,7 @@ static int block2mtd_setup(const char *v - - - module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); --MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,]]\""); -+MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,[,]]]\""); - - static int __init block2mtd_init(void) - { From 4a0688ed71532a3dd68907f5603177d970e4ec03 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sat, 17 Oct 2020 11:15:32 +0200 Subject: [PATCH 03/15] base-files: remove block2mtd checks from sysupgrade This hasn't been used in a long time Signed-off-by: Felix Fietkau --- package/base-files/files/lib/upgrade/common.sh | 4 ---- target/linux/octeon/base-files/lib/upgrade/platform.sh | 4 ---- 2 files changed, 8 deletions(-) diff --git a/package/base-files/files/lib/upgrade/common.sh b/package/base-files/files/lib/upgrade/common.sh index c375b70742..2eb26ba44b 100644 --- a/package/base-files/files/lib/upgrade/common.sh +++ b/package/base-files/files/lib/upgrade/common.sh @@ -126,10 +126,6 @@ export_bootdevice() { if read cmdline < /proc/cmdline; then case "$cmdline" in - *block2mtd=*) - bootdisk="${cmdline##*block2mtd=}" - bootdisk="${bootdisk%%,*}" - ;; *root=*) rootpart="${cmdline##*root=}" rootpart="${rootpart%% *}" diff --git a/target/linux/octeon/base-files/lib/upgrade/platform.sh b/target/linux/octeon/base-files/lib/upgrade/platform.sh index d938950906..33a9931263 100755 --- a/target/linux/octeon/base-files/lib/upgrade/platform.sh +++ b/target/linux/octeon/base-files/lib/upgrade/platform.sh @@ -7,10 +7,6 @@ platform_get_rootfs() { if read cmdline < /proc/cmdline; then case "$cmdline" in - *block2mtd=*) - rootfsdev="${cmdline##*block2mtd=}" - rootfsdev="${rootfsdev%%,*}" - ;; *root=*) rootfsdev="${cmdline##*root=}" rootfsdev="${rootfsdev%% *}" From 27a7d071c0e0576eddeb641d1f68abe1b6205aee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=BC=A0=E9=B9=8F?= Date: Wed, 14 Oct 2020 15:47:35 +0800 Subject: [PATCH 04/15] ath79: add support for Qxwlan E750G v8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Qxwlan E750G v8 is based on Qualcomm QCA9344 + QCA9334. Specification: - 560/450/225 MHz (CPU/DDR/AHB) - 128 MB of RAM (DDR2) - 8/16 MB of FLASH (SPI NOR) - 2T2R 2.4G GHz (AR9344) - 2x 10/100/1000 Mbps Ethernet (one port with PoE support) - 7x LED (6 driven by GPIO) - 1x button (reset) - 1x DC jack for main power input (9-48 V) - UART (J23) and LEDs (J2) headers on PCB Flash instruction: 1.Using tftp mode with UART connection and original LEDE image - Configure PC with static IP 192.168.1.10 and tftp server. - Rename "openwrt-ar71xx-generic-xxx-squashfs-sysupgrade.bin" to "firmware.bin" and place it in tftp server directory. - Connect PC with one of LAN ports, power up the router and press key "Enter" to access U-Boot CLI. - Use the following commands to update the device to LEDE: run lfw - After that the device will reboot and boot to LEDE. - Wait until all LEDs stops flashing and use the router. 2.Using httpd mode with Web UI connection and original LEDE image - Configure PC with static IP 192.168.1.xxx(2-255) and tftp server. - Connect PC with one of LAN ports,press the reset button, power up the router and keep button pressed for around 6-7 seconds, until leds flashing. - Open your browser and enter 192.168.1.1,You will see the upgrade interface, select "openwrt-ar71xx-generic-xxx-squashfs- sysupgrade.bin" and click the upgrade button. - After that the device will reboot and boot to LEDE. - Wait until all LEDs stops flashing and use the router. Signed-off-by: 张鹏 [cut out of bigger patch, keep swconfig] Signed-off-by: Adrian Schmutzler --- .../ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts | 48 +++++++++++++++++++ .../ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts | 48 +++++++++++++++++++ .../generic/base-files/etc/board.d/02_network | 2 + target/linux/ath79/image/generic.mk | 21 ++++++++ 4 files changed, 119 insertions(+) create mode 100644 target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts create mode 100644 target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts b/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts new file mode 100644 index 0000000000..fb200fae35 --- /dev/null +++ b/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "ar9344_qxwlan_e750x.dtsi" + +/ { + model = "Qxwlan E750G v8 16M"; + compatible = "qxwlan,e750g-v8-16m", "qca,ar9344"; +}; + +&mdio0 { + status = "okay"; + + phy-mask = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "rgmii"; + + qca,ar8327-initvals = < + 0x04 0x07600000 /* PORT0 PAD MODE CTRL */ + 0x10 0x81000080 /* POWER_ON_STRAP */ + 0x50 0xcc35cc35 /* LED_CTRL0 */ + 0x54 0xca35ca35 /* LED_CTRL1 */ + 0x58 0xc935c935 /* LED_CTRL2 */ + 0x5c 0x03ffff00 /* LED_CTRL3 */ + 0x7c 0x0000007e /* PORT0_STATUS */ + >; + }; +}; + +ð0 { + status = "okay"; + + pll-data = <0x06000000 0x00000101 0x00001616>; + + mtd-mac-address = <&pridata 0x400>; + + phy-mode = "rgmii"; + phy-handle = <&phy0>; +}; + +&partitions { + partition@70000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x070000 0xf90000>; + }; +}; diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts b/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts new file mode 100644 index 0000000000..75ef13ec13 --- /dev/null +++ b/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "ar9344_qxwlan_e750x.dtsi" + +/ { + model = "Qxwlan E750G v8 8M"; + compatible = "qxwlan,e750g-v8-8m", "qca,ar9344"; +}; + +&mdio0 { + status = "okay"; + + phy-mask = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "rgmii"; + + qca,ar8327-initvals = < + 0x04 0x07600000 /* PORT0 PAD MODE CTRL */ + 0x10 0x81000080 /* POWER_ON_STRAP */ + 0x50 0xcc35cc35 /* LED_CTRL0 */ + 0x54 0xca35ca35 /* LED_CTRL1 */ + 0x58 0xc935c935 /* LED_CTRL2 */ + 0x5c 0x03ffff00 /* LED_CTRL3 */ + 0x7c 0x0000007e /* PORT0_STATUS */ + >; + }; +}; + +ð0 { + status = "okay"; + + pll-data = <0x06000000 0x00000101 0x00001616>; + + mtd-mac-address = <&pridata 0x400>; + + phy-mode = "rgmii"; + phy-handle = <&phy0>; +}; + +&partitions { + partition@70000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x070000 0x790000>; + }; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index 060c0c9e42..78ec5c6afe 100755 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -244,6 +244,8 @@ ath79_setup_interfaces() "0@eth0" "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "1:wan" ;; nec,wg1200cr|\ + qxwlan,e750g-v8-8m|\ + qxwlan,e750g-v8-16m|\ ubnt,nanostation-ac|\ yuncore,a782|\ yuncore,xd4200) diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk index f15d7a3b89..71dc261b2c 100644 --- a/target/linux/ath79/image/generic.mk +++ b/target/linux/ath79/image/generic.mk @@ -1496,6 +1496,27 @@ define Device/qxwlan_e750a-v4-8m endef TARGET_DEVICES += qxwlan_e750a-v4-8m +define Device/qxwlan_e750g-v8 + SOC := ar9344 + DEVICE_VENDOR := Qxwlan + DEVICE_MODEL := E750G + DEVICE_PACKAGES := kmod-usb2 +endef + +define Device/qxwlan_e750g-v8-16m + $(Device/qxwlan_e750g-v8) + DEVICE_VARIANT := v8 (16M) + IMAGE_SIZE := 15936k +endef +TARGET_DEVICES += qxwlan_e750g-v8-16m + +define Device/qxwlan_e750g-v8-8m + $(Device/qxwlan_e750g-v8) + DEVICE_VARIANT := v8 (8M) + IMAGE_SIZE := 7744k +endef +TARGET_DEVICES += qxwlan_e750g-v8-8m + define Device/rosinson_wr818 SOC := qca9563 DEVICE_VENDOR := Rosinson From 987d9028e12f37fcb3ca095efd6ffde6d7007469 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=BC=A0=E9=B9=8F?= Date: Fri, 16 Oct 2020 12:42:15 +0200 Subject: [PATCH 05/15] ath79: add support for Qxwlan E558 v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Qxwlan E558 v2 is based on Qualcomm QCA9558 + AR8327. Specification: - 720/600/200 MHz (CPU/DDR/AHB) - 128 MB of RAM (DDR2) - 8/16 MB of FLASH (SPI NOR) - 2T2R 2.4 GHz (QCA9558) - 3x 10/100/1000 Mbps Ethernet (one port with PoE support) - 4x miniPCIe slot (USB 2.0 bus only) - 1x microSIM slot - 5x LED (4 driven by GPIO) - 1x button (reset) - 1x 3-pos switch - 1x DC jack for main power input (9-48 V) - UART (JP5) and LEDs (J8) headers on PCB Flash instruction: 1.Using tftp mode with UART connection and original LEDE image - Configure PC with static IP 192.168.1.10 and tftp server. - Rename "openwrt-ar71xx-generic-xxx-squashfs-sysupgrade.bin" to "firmware.bin" and place it in tftp server directory. - Connect PC with one of LAN ports, power up the router and press key "Enter" to access U-Boot CLI. - Use the following commands to update the device to LEDE: run lfw - After that the device will reboot and boot to LEDE. - Wait until all LEDs stops flashing and use the router. 2.Using httpd mode with Web UI connection and original LEDE image - Configure PC with static IP 192.168.1.xxx(2-255) and tftp server. - Connect PC with one of LAN ports,press the reset button, power up the router and keep button pressed for around 6-7 seconds, until leds flashing. - Open your browser and enter 192.168.1.1,You will see the upgrade interface, select "openwrt-ar71xx-generic-xxx-squashfs- sysupgrade.bin" and click the upgrade button. - After that the device will reboot and boot to LEDE. - Wait until all LEDs stops flashing and use the router. Signed-off-by: 张鹏 [cut out of bigger patch, keep swconfig, whitespace adjustments] Signed-off-by: Adrian Schmutzler --- .../ath79/dts/qca9558_qxwlan_e558-v2-16m.dts | 16 ++ .../ath79/dts/qca9558_qxwlan_e558-v2-8m.dts | 16 ++ .../linux/ath79/dts/qca9558_qxwlan_e558.dtsi | 172 ++++++++++++++++++ .../generic/base-files/etc/board.d/02_network | 5 + target/linux/ath79/image/generic.mk | 21 +++ 5 files changed, 230 insertions(+) create mode 100644 target/linux/ath79/dts/qca9558_qxwlan_e558-v2-16m.dts create mode 100644 target/linux/ath79/dts/qca9558_qxwlan_e558-v2-8m.dts create mode 100644 target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi diff --git a/target/linux/ath79/dts/qca9558_qxwlan_e558-v2-16m.dts b/target/linux/ath79/dts/qca9558_qxwlan_e558-v2-16m.dts new file mode 100644 index 0000000000..1df4c5e6b5 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_qxwlan_e558-v2-16m.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca9558_qxwlan_e558.dtsi" + +/ { + model = "Qxwlan E558 v2 16M"; + compatible = "qxwlan,e558-v2-16m", "qca,qca9558"; +}; + +&partitions { + partition@70000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x070000 0xf90000>; + }; +}; diff --git a/target/linux/ath79/dts/qca9558_qxwlan_e558-v2-8m.dts b/target/linux/ath79/dts/qca9558_qxwlan_e558-v2-8m.dts new file mode 100644 index 0000000000..30d17d5b05 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_qxwlan_e558-v2-8m.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca9558_qxwlan_e558.dtsi" + +/ { + model = "Qxwlan E558 v2 8M"; + compatible = "qxwlan,e558-v2-8m", "qca,qca9558"; +}; + +&partitions { + partition@70000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x070000 0x790000>; + }; +}; diff --git a/target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi b/target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi new file mode 100644 index 0000000000..99f37ac025 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca955x.dtsi" + +#include +#include + +/ { + aliases { + led-boot = &led_system; + led-failsafe = &led_system; + led-running = &led_system; + led-upgrade = &led_system; + label-mac-device = ð0; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "Reset button"; + linux,code = ; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + wlan { + label = "green:wlan"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + led_system: system { + label = "green:system"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + sig1 { + label = "green:sig1"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + + sig2 { + label = "green:sig2"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&spi { + status = "okay"; + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x040000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x040000 0x010000>; + read-only; + }; + + pridata: partition@50000 { + label = "pri-data"; + reg = <0x050000 0x010000>; + read-only; + }; + + art: partition@60000 { + label = "art"; + reg = <0x060000 0x010000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + + qca,ar8327-initvals = < + 0x04 0x00080080 /* PORT0 PAD MODE CTRL */ + 0x0c 0x07600000 /* PORT6 PAD MODE CTRL */ + 0x10 0x81000080 /* POWER_ON_STRAP */ + 0x50 0xcc35cc35 /* LED_CTRL0 */ + 0x54 0xca35ca35 /* LED_CTRL1 */ + 0x58 0xc935c935 /* LED_CTRL2 */ + 0x5c 0x03ffff00 /* LED_CTRL3 */ + 0x7c 0x0000007e /* PORT0_STATUS */ + 0x94 0x0000007e /* PORT6 STATUS */ + >; + }; +}; + +ð0 { + status = "okay"; + + pll-data = <0x56000000 0x00000101 0x00001616>; + + phy-handle = <&phy0>; + + mtd-mac-address = <&pridata 0x400>; + mtd-mac-address-increment = <1>; +}; + +ð1 { + status = "okay"; + + pll-data = <0x03000101 0x00000101 0x00001616>; + + mtd-mac-address = <&pridata 0x400>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&uart { + status = "okay"; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&wmac { + status = "okay"; + + mtd-cal-data = <&art 0x1000>; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index 78ec5c6afe..8f528c33cd 100755 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -285,6 +285,11 @@ ath79_setup_interfaces() ucidef_add_switch "switch0" \ "0@eth0" "2:lan" "3:lan" ;; + qxwlan,e558-v2-8m|\ + qxwlan,e558-v2-16m) + ucidef_add_switch "switch0" \ + "0@eth1" "4:lan" "5:lan" "6@eth0" "3:wan" + ;; rosinson,wr818) ucidef_add_switch "switch0" \ "0@eth0" "1:lan" "2:lan" "3:wan" diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk index 71dc261b2c..528a63f629 100644 --- a/target/linux/ath79/image/generic.mk +++ b/target/linux/ath79/image/generic.mk @@ -1475,6 +1475,27 @@ define Device/qihoo_c301 endef TARGET_DEVICES += qihoo_c301 +define Device/qxwlan_e558-v2 + SOC := qca9558 + DEVICE_VENDOR := Qxwlan + DEVICE_MODEL := E558 + DEVICE_PACKAGES := kmod-usb2 +endef + +define Device/qxwlan_e558-v2-16m + $(Device/qxwlan_e558-v2) + DEVICE_VARIANT := v2 (16M) + IMAGE_SIZE := 15936k +endef +TARGET_DEVICES += qxwlan_e558-v2-16m + +define Device/qxwlan_e558-v2-8m + $(Device/qxwlan_e558-v2) + DEVICE_VARIANT := v2 (8M) + IMAGE_SIZE := 7744k +endef +TARGET_DEVICES += qxwlan_e558-v2-8m + define Device/qxwlan_e750a-v4 SOC := ar9344 DEVICE_VENDOR := Qxwlan From 4ff7bdfeebd4c974b74df74f779fc10891898f5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=BC=A0=E9=B9=8F?= Date: Fri, 16 Oct 2020 12:53:51 +0200 Subject: [PATCH 06/15] ath79: add support for Qxwlan E1700AC v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit E1700AC v2 based on Qualcomm/Atheros QCA9563 + QCA9880. Specification: - 750/400/250 MHz (CPU/DDR/AHB) - 128 MB of RAM (DDR2) - 8/16 MB of FLASH (SPI NOR) - 3T3R 2.4 GHz - 3T3R 5 GHz - 2 x 10/1000M Mbps Ethernet (RJ45) - 1 x MiniPCI-e - 1 x SIM (3G/4G) - 1 x USB 2.0 Port - 5 x LED , 2 x Button(S8-Reset Buttun), 1 x power input - UART (J5) header on PCB (115200 8N1) Flash instruction: 1.Using tftp mode with UART connection and original LEDE image - Configure PC with static IP 192.168.1.10 and tftp server. - Rename "openwrt-ar71xx-generic-xxx-squashfs-sysupgrade.bin" to "firmware.bin" and place it in tftp server directory. - Connect PC with one of LAN ports, power up the router and press key "Enter" to access U-Boot CLI. - Use the following commands to update the device to LEDE: run lfw - After that the device will reboot and boot to LEDE. - Wait until all LEDs stops flashing and use the router. 2.Using httpd mode with Web UI connection and original LEDE image - Configure PC with static IP 192.168.1.xxx(2-255) and tftp server. - Connect PC with one of LAN ports,press the reset button, power up the router and keep button pressed for around 6-7 seconds, until leds flashing. - Open your browser and enter 192.168.1.1,You will see the upgrade interface, select "openwrt-ar71xx-generic-xxx-squashfs- sysupgrade.bin" and click the upgrade button. - After that the device will reboot and boot to LEDE. - Wait until all LEDs stops flashing and use the router. Signed-off-by: 张鹏 [cut out of bigger patch, keep swconfig, whitespace fixes] Signed-off-by: Adrian Schmutzler --- .../dts/qca9563_qxwlan_e1700ac-v2-16m.dts | 16 ++ .../dts/qca9563_qxwlan_e1700ac-v2-8m.dts | 16 ++ .../ath79/dts/qca9563_qxwlan_e1700ac.dtsi | 157 ++++++++++++++++++ .../generic/base-files/etc/board.d/02_network | 2 + .../etc/hotplug.d/firmware/11-ath10k-caldata | 2 + target/linux/ath79/image/generic.mk | 21 +++ 6 files changed, 214 insertions(+) create mode 100644 target/linux/ath79/dts/qca9563_qxwlan_e1700ac-v2-16m.dts create mode 100644 target/linux/ath79/dts/qca9563_qxwlan_e1700ac-v2-8m.dts create mode 100644 target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi diff --git a/target/linux/ath79/dts/qca9563_qxwlan_e1700ac-v2-16m.dts b/target/linux/ath79/dts/qca9563_qxwlan_e1700ac-v2-16m.dts new file mode 100644 index 0000000000..b851380a47 --- /dev/null +++ b/target/linux/ath79/dts/qca9563_qxwlan_e1700ac-v2-16m.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca9563_qxwlan_e1700ac.dtsi" + +/ { + model = "Qxwlan E1700AC v2 16M"; + compatible = "qxwlan,e1700ac-v2-16m", "qca,qca9563"; +}; + +&partitions { + partition@70000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x070000 0xf90000>; + }; +}; diff --git a/target/linux/ath79/dts/qca9563_qxwlan_e1700ac-v2-8m.dts b/target/linux/ath79/dts/qca9563_qxwlan_e1700ac-v2-8m.dts new file mode 100644 index 0000000000..7aaac487c2 --- /dev/null +++ b/target/linux/ath79/dts/qca9563_qxwlan_e1700ac-v2-8m.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca9563_qxwlan_e1700ac.dtsi" + +/ { + model = "Qxwlan E1700AC v2 8M"; + compatible = "qxwlan,e1700ac-v2-8m", "qca,qca9563"; +}; + +&partitions { + partition@70000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x070000 0x790000>; + }; +}; diff --git a/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi b/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi new file mode 100644 index 0000000000..0c397e7dd9 --- /dev/null +++ b/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca956x.dtsi" + +#include +#include + +/ { + aliases { + label-mac-device = ð0; + led-boot = &led_system; + led-failsafe = &led_system; + led-running = &led_system; + led-upgrade = &led_system; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_system: system { + label = "green:system"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + usb { + label = "green:usb"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + trigger-sources = <&hub_port0>; + linux,default-trigger = "usbport"; + }; + + wlan2g { + label = "green:wlan2g"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&spi { + status = "okay"; + + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x040000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x040000 0x010000>; + read-only; + }; + + pridata: partition@50000 { + label = "pri-data"; + reg = <0x050000 0x010000>; + read-only; + }; + + art: partition@60000 { + label = "art"; + reg = <0x060000 0x010000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy-mask = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "sgmii"; + qca,mib-poll-interval = <500>; + + qca,ar8327-initvals = < + 0x04 0x00080080 /* PORT0 PAD MODE CTRL */ + 0x7c 0x0000007e /* PORT0_STATUS */ + >; + }; +}; + +ð0 { + status = "okay"; + + pll-data = <0x03000101 0x00000101 0x00001919>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + + mtd-mac-address = <&pridata 0x400>; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_port0: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&uart { + status = "okay"; +}; + +&wmac { + status = "okay"; + + mtd-cal-data = <&art 0x1000>; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index 8f528c33cd..a587cfac96 100755 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -244,6 +244,8 @@ ath79_setup_interfaces() "0@eth0" "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "1:wan" ;; nec,wg1200cr|\ + qxwlan,e1700ac-v2-8m|\ + qxwlan,e1700ac-v2-16m|\ qxwlan,e750g-v8-8m|\ qxwlan,e750g-v8-16m|\ ubnt,nanostation-ac|\ diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index 857f566db8..25e864ba72 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -22,6 +22,8 @@ case "$FIRMWARE" in comfast,cf-wr650ac-v1|\ comfast,cf-wr650ac-v2|\ devolo,magic-2-wifi|\ + qxwlan,e1700ac-v2-8m|\ + qxwlan,e1700ac-v2-16m|\ ubnt,unifiac-lite|\ ubnt,unifiac-lr|\ ubnt,unifiac-mesh|\ diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk index 528a63f629..8b0c247876 100644 --- a/target/linux/ath79/image/generic.mk +++ b/target/linux/ath79/image/generic.mk @@ -1475,6 +1475,27 @@ define Device/qihoo_c301 endef TARGET_DEVICES += qihoo_c301 +define Device/qxwlan_e1700ac-v2 + SOC := qca9563 + DEVICE_VENDOR := Qxwlan + DEVICE_MODEL := E1700AC + DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca988x-ct +endef + +define Device/qxwlan_e1700ac-v2-16m + $(Device/qxwlan_e1700ac-v2) + DEVICE_VARIANT := v2 (16M) + IMAGE_SIZE := 15936k +endef +TARGET_DEVICES += qxwlan_e1700ac-v2-16m + +define Device/qxwlan_e1700ac-v2-8m + $(Device/qxwlan_e1700ac-v2) + DEVICE_VARIANT := v2 (8M) + IMAGE_SIZE := 7744k +endef +TARGET_DEVICES += qxwlan_e1700ac-v2-8m + define Device/qxwlan_e558-v2 SOC := qca9558 DEVICE_VENDOR := Qxwlan From e6d9f6fdffc6730cfa2019788afa411828eac816 Mon Sep 17 00:00:00 2001 From: Jayantajit Gogoi Date: Mon, 12 Oct 2020 18:51:34 +0000 Subject: [PATCH 07/15] sunxi: add support for FriendlyARM NanoPi R1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Specification: - CPU: Allwinner H3, Quad-core Cortex-A7 Up to 1.2GHz - DDR3 RAM: 512MB/1GB - Network: 10/100/1000M Ethernet x 1， 10/100M Ethernet x 1 - WiFi: 802.11b/g/n, with SMA antenna interface - USB Host: Type-A x2 - MicroSD Slot x 1 - MicroUSB: for OTG and power input - Debug Serial Port: 3Pin 2.54mm pitch pin-header - LED: nanopi:red:status nanopi:green:wan nanopi:green:lan - KEY: reset - Power Supply: DC 5V/2A Installation: - Write the image to SD Card with dd - Boot NanoPi from the SD Card Signed-off-by: Jayantajit Gogoi --- package/boot/uboot-sunxi/Makefile | 7 + ...2-sunxi-h3-add-support-for-nanopi-r1.patch | 198 ++++++++++++++++++ .../sunxi/base-files/etc/board.d/01_leds | 20 ++ .../sunxi/base-files/etc/board.d/02_network | 3 + target/linux/sunxi/image/cortexa7.mk | 10 + ...0-sunxi-h3-add-support-for-nanopi-r1.patch | 186 ++++++++++++++++ 6 files changed, 424 insertions(+) create mode 100644 package/boot/uboot-sunxi/patches/252-sunxi-h3-add-support-for-nanopi-r1.patch create mode 100644 target/linux/sunxi/base-files/etc/board.d/01_leds create mode 100644 target/linux/sunxi/patches-5.4/100-sunxi-h3-add-support-for-nanopi-r1.patch diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile index 4363445114..abdb263774 100644 --- a/package/boot/uboot-sunxi/Makefile +++ b/package/boot/uboot-sunxi/Makefile @@ -172,6 +172,12 @@ define U-Boot/nanopi_neo BUILD_DEVICES:=friendlyarm_nanopi-neo endef +define U-Boot/nanopi_r1 + BUILD_SUBTARGET:=cortexa7 + NAME:=U-Boot for NanoPi R1 (H3) + BUILD_DEVICES:=friendlyarm_nanopi-r1 +endef + define U-Boot/orangepi_r1 BUILD_SUBTARGET:=cortexa7 NAME:=Orange Pi R1 (H2+) @@ -310,6 +316,7 @@ UBOOT_TARGETS := \ nanopi_neo_air \ nanopi_neo_plus2 \ nanopi_neo2 \ + nanopi_r1 \ orangepi_zero \ orangepi_r1 \ orangepi_one \ diff --git a/package/boot/uboot-sunxi/patches/252-sunxi-h3-add-support-for-nanopi-r1.patch b/package/boot/uboot-sunxi/patches/252-sunxi-h3-add-support-for-nanopi-r1.patch new file mode 100644 index 0000000000..0db7be5421 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/252-sunxi-h3-add-support-for-nanopi-r1.patch @@ -0,0 +1,198 @@ +From 0e8043aff1aae95d1f7b7422b91b57d9569860d3 Mon Sep 17 00:00:00 2001 +From: Jayantajit Gogoi +Date: Mon, 12 Oct 2020 18:39:53 +0000 +Subject: [PATCH] sunxi: add support for FriendlyARM NanoPi R1 + +Signed-off-by: Jayantajit Gogoi +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/sun8i-h3-nanopi-r1.dts | 146 ++++++++++++++++++++++++++++ + configs/nanopi_r1_defconfig | 22 +++++ + 3 files changed, 169 insertions(+) + create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts + create mode 100644 configs/nanopi_r1_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -531,6 +531,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ + sun8i-h3-nanopi-neo-air.dtb \ ++ sun8i-h3-nanopi-r1.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ +--- /dev/null ++++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts +@@ -0,0 +1,146 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2019 Igor Pecovnik ++ * Copyright (C) 2020 Jayantajit Gogoi ++ */ ++ ++/* NanoPi R1 is based on the NanoPi-H3 design from FriendlyARM */ ++#include "sun8i-h3-nanopi.dtsi" ++ ++/ { ++ model = "FriendlyARM NanoPi R1"; ++ compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3"; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vdd_cpux: gpio-regulator { ++ compatible = "regulator-gpio"; ++ pinctrl-names = "default"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-ramp-delay = <50>; ++ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; ++ gpios-states = <0x1>; ++ states = <1100000 0x0 ++ 1300000 0x1>; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ leds { ++ /delete-node/ pwr; ++ status { ++ label = "nanopi:red:status"; ++ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ wan { ++ label = "nanopi:green:wan"; ++ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ lan { ++ label = "nanopi:green:lan"; ++ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ r_gpio_keys { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sw_r_npi>; ++ ++ /delete-node/ k1; ++ reset { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpux>; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii"; ++ status = "okay"; ++}; ++ ++&external_mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <7>; ++ }; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ sdio_wifi: sdio_wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&pio>; ++ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&r_pio { ++ sw_r_npi: key_pins { ++ pins = "PL3"; ++ function = "gpio_in"; ++ }; ++}; +--- /dev/null ++++ b/configs/nanopi_r1_defconfig +@@ -0,0 +1,22 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MACPWR="PD6" ++# CONFIG_VIDEO_DE2 is not set ++CONFIG_NR_DRAM_BANKS=1 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_CONSOLE_MUX=y ++CONFIG_SYS_CLK_FREQ=480000000 ++# CONFIG_CMD_FLASH is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-r1" ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/target/linux/sunxi/base-files/etc/board.d/01_leds b/target/linux/sunxi/base-files/etc/board.d/01_leds new file mode 100644 index 0000000000..514b8d1796 --- /dev/null +++ b/target/linux/sunxi/base-files/etc/board.d/01_leds @@ -0,0 +1,20 @@ +#!/bin/sh + +. /lib/functions/leds.sh +. /lib/functions/uci-defaults.sh + +board=$(board_name) +boardname="${board##*,}" + +board_config_update + +case $board in +friendlyarm,nanopi-r1) + ucidef_set_led_netdev "wan" "WAN" "nanopi:green:wan" "eth0" + ucidef_set_led_netdev "lan" "LAN" "nanopi:green:lan" "eth1" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/sunxi/base-files/etc/board.d/02_network b/target/linux/sunxi/base-files/etc/board.d/02_network index 5cf000cccf..08d31caadc 100755 --- a/target/linux/sunxi/base-files/etc/board.d/02_network +++ b/target/linux/sunxi/base-files/etc/board.d/02_network @@ -8,6 +8,9 @@ board_config_update case $(board_name) in +friendlyarm,nanopi-r1) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; lamobo,lamobo-r1) ucidef_add_switch "switch0" \ "4:lan:1" "0:lan:2" "1:lan:3" "2:lan:4" "3:wan" "8@eth0" diff --git a/target/linux/sunxi/image/cortexa7.mk b/target/linux/sunxi/image/cortexa7.mk index f11b13625c..a87817037d 100644 --- a/target/linux/sunxi/image/cortexa7.mk +++ b/target/linux/sunxi/image/cortexa7.mk @@ -47,6 +47,16 @@ define Device/friendlyarm_nanopi-neo-air endef TARGET_DEVICES += friendlyarm_nanopi-neo-air +define Device/friendlyarm_nanopi-r1 + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := NanoPi R1 + DEVICE_PACKAGES := kmod-rtc-sunxi kmod-usb-net-rtl8152 \ + kmod-brcmfmac kmod-leds-gpio kmod-ledtrig-heartbeat wpad-basic-wolfssl \ + brcmfmac-firmware-43430-sdio + SOC := sun8i-h3 +endef +TARGET_DEVICES += friendlyarm_nanopi-r1 + define Device/friendlyarm_zeropi DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := ZeroPi diff --git a/target/linux/sunxi/patches-5.4/100-sunxi-h3-add-support-for-nanopi-r1.patch b/target/linux/sunxi/patches-5.4/100-sunxi-h3-add-support-for-nanopi-r1.patch new file mode 100644 index 0000000000..834ea153c8 --- /dev/null +++ b/target/linux/sunxi/patches-5.4/100-sunxi-h3-add-support-for-nanopi-r1.patch @@ -0,0 +1,186 @@ +From 5aee0b1272cd5b42933ef629d66b677669e2e8d2 Mon Sep 17 00:00:00 2001 +From: Jayantajit Gogoi +Date: Mon, 12 Oct 2020 05:24:51 +0000 +Subject: [PATCH] sunxi: add support for friendlyarm nanopi r1 + +Signed-off-by: Jayantajit Gogoi +--- + .../devicetree/bindings/arm/sunxi.yaml | 5 + + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts | 146 ++++++++++++++++++ + 3 files changed, 152 insertions(+) + create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts + +--- a/Documentation/devicetree/bindings/arm/sunxi.yaml ++++ b/Documentation/devicetree/bindings/arm/sunxi.yaml +@@ -241,6 +241,11 @@ properties: + - const: friendlyarm,nanopi-neo-plus2 + - const: allwinner,sun50i-h5 + ++ - description: FriendlyARM NanoPi R1 ++ items: ++ - const: friendlyarm,nanopi-r1 ++ - const: allwinner,sun8i-h3 ++ + - description: Gemei G9 Tablet + items: + - const: gemei,g9 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -1109,6 +1109,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ + sun8i-h3-nanopi-neo-air.dtb \ ++ sun8i-h3-nanopi-r1.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts +@@ -0,0 +1,146 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2019 Igor Pecovnik ++ * Copyright (C) 2020 Jayantajit Gogoi ++ */ ++ ++/* NanoPi R1 is based on the NanoPi-H3 design from FriendlyARM */ ++#include "sun8i-h3-nanopi.dtsi" ++ ++/ { ++ model = "FriendlyARM NanoPi R1"; ++ compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3"; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vdd_cpux: gpio-regulator { ++ compatible = "regulator-gpio"; ++ pinctrl-names = "default"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-ramp-delay = <50>; ++ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; ++ gpios-states = <0x1>; ++ states = <1100000 0x0 ++ 1300000 0x1>; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ leds { ++ /delete-node/ pwr; ++ status { ++ label = "nanopi:red:status"; ++ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ wan { ++ label = "nanopi:green:wan"; ++ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ lan { ++ label = "nanopi:green:lan"; ++ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ r_gpio_keys { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sw_r_npi>; ++ ++ /delete-node/ k1; ++ reset { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpux>; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii"; ++ status = "okay"; ++}; ++ ++&external_mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <7>; ++ }; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ sdio_wifi: sdio_wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&pio>; ++ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&r_pio { ++ sw_r_npi: key_pins { ++ pins = "PL3"; ++ function = "gpio_in"; ++ }; ++}; From 7f5f738466aca2cd8f5daf73f68f4d32b70d43b5 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 18 Oct 2020 14:26:55 +0200 Subject: [PATCH 08/15] sunxi: Adapt U-Boot config to board rename The board was renamed without changing the BUILD_DEVICES in the U-Boot Makefile, this broken the build. Fixes: 0830ae3a2fdf ("sunxi: Correct manufacturer name to Sinovoip") Signed-off-by: Hauke Mehrtens --- package/boot/uboot-sunxi/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile index abdb263774..58a5923eab 100644 --- a/package/boot/uboot-sunxi/Makefile +++ b/package/boot/uboot-sunxi/Makefile @@ -284,7 +284,7 @@ endef define U-Boot/Bananapi_M2_Ultra BUILD_SUBTARGET:=cortexa7 NAME:=Bananapi M2 Ultra - BUILD_DEVICES:=lemaker_bananapi-m2-ultra + BUILD_DEVICES:=sinovoip_bananapi-m2-ultra endef UBOOT_TARGETS := \ From c78e123d5a5e7c3baa74f326613a14f7e99a29a3 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 19 Oct 2020 14:47:45 +0200 Subject: [PATCH 09/15] rtl838x: various fixes * add d-link_dgs-1210-10p support * make sure mips16 is disabled * add a generic sub target * add proper cflags Signed-off-by: John Crispin --- include/target.mk | 1 + target/linux/rtl838x/Makefile | 3 + .../dts/rtl8382_d-link_dgs-1210-10p.dts | 231 ++++++++++++++++++ target/linux/rtl838x/generic/target.mk | 1 + target/linux/rtl838x/image/Makefile | 9 + 5 files changed, 245 insertions(+) create mode 100644 target/linux/rtl838x/dts/rtl8382_d-link_dgs-1210-10p.dts create mode 100644 target/linux/rtl838x/generic/target.mk diff --git a/include/target.mk b/include/target.mk index d593a5f0df..31ce592c8b 100644 --- a/include/target.mk +++ b/include/target.mk @@ -199,6 +199,7 @@ ifeq ($(DUMP),1) CPU_CFLAGS_mips32 = -mips32 -mtune=mips32 CPU_CFLAGS_mips64 = -mips64 -mtune=mips64 -mabi=64 CPU_CFLAGS_mips64r2 = -mips64r2 -mtune=mips64r2 -mabi=64 + CPU_CFLAGS_4kec = -mips32r2 -mtune=4kec CPU_CFLAGS_24kc = -mips32r2 -mtune=24kc CPU_CFLAGS_74kc = -mips32r2 -mtune=74kc CPU_CFLAGS_octeonplus = -march=octeon+ -mabi=64 diff --git a/target/linux/rtl838x/Makefile b/target/linux/rtl838x/Makefile index c4138c7a9a..83cb074b89 100644 --- a/target/linux/rtl838x/Makefile +++ b/target/linux/rtl838x/Makefile @@ -9,6 +9,7 @@ BOARD:=rtl838x BOARDNAME:=Realtek MIPS DEVICE_TYPE:=basic FEATURES:=ramdisk squashfs +SUBTARGETS:=generic KERNEL_PATCHVER:=5.4 @@ -18,6 +19,8 @@ endef include $(INCLUDE_DIR)/target.mk +FEATURES := $(filter-out mips16,$(FEATURES)) + DEFAULT_PACKAGES += swconfig uboot-envtools ethtool kmod-gpio-button-hotplug $(eval $(call BuildTarget)) diff --git a/target/linux/rtl838x/dts/rtl8382_d-link_dgs-1210-10p.dts b/target/linux/rtl838x/dts/rtl8382_d-link_dgs-1210-10p.dts new file mode 100644 index 0000000000..d7c6cbfc7c --- /dev/null +++ b/target/linux/rtl838x/dts/rtl8382_d-link_dgs-1210-10p.dts @@ -0,0 +1,231 @@ +#include "rtl838x.dtsi" + +#include +#include + +/ { + compatible = "d-link,dgs-1210-10p", "realtek,rtl838x-soc"; + model = "D-Link DGS-1210-10P"; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + leds { + compatible = "gpio-leds"; + + led_power: power { + // GPIO 24 seems to provide power to the leds + label = "green:power"; + gpios = <&gpio0 47 GPIO_ACTIVE_LOW>; + }; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + mode { + label = "reset"; + gpios = <&gpio0 94 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + + +&gpio0 { + indirect-access-bus-id = <0>; +}; + +&spi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x80000>; + read-only; + }; + partition@80000 { + label = "u-boot-env"; + reg = <0x00080000 0x40000>; + read-only; + }; + partition@c0000 { + label = "u-boot-env2"; + reg = <0x000c0000 0x40000>; + read-only; + }; + partition@280000 { + label = "firmware"; + compatible = "denx,uimage"; + reg = <0x00100000 0xd80000>; + }; + partition@be80000 { + label = "kernel2"; + reg = <0x00e80000 0x180000>; + }; + partition@1000000 { + label = "sysinfo"; + reg = <0x01000000 0x40000>; + }; + partition@1040000 { + label = "rootfs2"; + reg = <0x01040000 0xc00000>; + }; + partition@1c40000 { + label = "jffs2"; + reg = <0x01c40000 0x3c0000>; + }; + }; + }; +}; + + + +ðernet0 { + mdio: mdio-bus { + compatible = "realtek,rtl838x-mdio"; + regmap = <ðernet0>; + #address-cells = <1>; + #size-cells = <0>; + + /* Internal phy */ + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + phy9: ethernet-phy@9 { + reg = <9>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + phy10: ethernet-phy@10 { + reg = <10>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <11>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + phy12: ethernet-phy@12 { + reg = <12>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <13>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + phy14: ethernet-phy@14 { + reg = <14>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + phy15: ethernet-phy@15 { + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + phy24: ethernet-phy@24 { + compatible = "ethernet-phy-ieee802.3-c22"; + phy-is-integrated; + reg = <24>; + }; + phy26: ethernet-phy@26 { + compatible = "ethernet-phy-ieee802.3-c22"; + phy-is-integrated; + reg = <26>; + }; + }; +}; + +&switch0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <8>; + label = "lan1"; + phy-handle = <&phy8>; + phy-mode = "internal"; + }; + port@1 { + reg = <9>; + label = "lan2"; + phy-handle = <&phy9>; + phy-mode = "internal"; + }; + port@2 { + reg = <10>; + label = "lan3"; + phy-handle = <&phy10>; + phy-mode = "internal"; + }; + port@3 { + reg = <11>; + label = "lan4"; + phy-handle = <&phy11>; + phy-mode = "internal"; + }; + port@4 { + reg = <12>; + label = "lan5"; + phy-handle = <&phy12>; + phy-mode = "internal"; + }; + port@5 { + reg = <13>; + label = "lan6"; + phy-handle = <&phy13>; + phy-mode = "internal"; + }; + port@6 { + reg = <14>; + label = "lan7"; + phy-handle = <&phy14>; + phy-mode = "internal"; + }; + port@7 { + reg = <15>; + label = "lan8"; + phy-handle = <&phy15>; + phy-mode = "internal"; + }; + + port@24 { + reg = <24>; + label = "lan9"; + phy-mode = "internal"; + phy-handle = <&phy24>; + }; + port@26 { + reg = <26>; + label = "lan10"; + phy-mode = "internal"; + phy-handle = <&phy26>; + }; + port@28 { + ethernet = <ðernet0>; + reg = <28>; + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/target/linux/rtl838x/generic/target.mk b/target/linux/rtl838x/generic/target.mk new file mode 100644 index 0000000000..f5cb1fb19b --- /dev/null +++ b/target/linux/rtl838x/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic diff --git a/target/linux/rtl838x/image/Makefile b/target/linux/rtl838x/image/Makefile index 291888ab2d..f490fa7ffe 100644 --- a/target/linux/rtl838x/image/Makefile +++ b/target/linux/rtl838x/image/Makefile @@ -50,4 +50,13 @@ define Device/d-link_dgs-1210-16 endef TARGET_DEVICES += d-link_dgs-1210-16 +define Device/d-link_dgs-1210-10p + SOC := rtl8382 + IMAGE_SIZE := 13824k + DEVICE_VENDOR := D-Link + DEVICE_MODEL := DGS-1210-10P + DEVICE_PACKAGES := ip-full ip-bridge ethtool tc lua-rs232 +endef +TARGET_DEVICES += d-link_dgs-1210-10p + $(eval $(call BuildImage)) From a7afeb31421bd6810c903468b23734baa6999438 Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Mon, 19 Oct 2020 15:30:44 +0200 Subject: [PATCH 10/15] ipq40xx: remove support for kernel 4.19 The target uses 5.4 as default kernel since 03/2020. Kernel 4.19 support is not really maintained anymore, it does not seem to be needed, and removing it will make upcoming driver updates easier. Thus, remove it. Signed-off-by: Adrian Schmutzler --- target/linux/ipq40xx/config-4.19 | 509 -- .../net/ethernet/qualcomm/essedma/Makefile | 0 .../net/ethernet/qualcomm/essedma/edma.c | 0 .../net/ethernet/qualcomm/essedma/edma.h | 0 .../net/ethernet/qualcomm/essedma/edma_axi.c | 0 .../ethernet/qualcomm/essedma/edma_ethtool.c | 0 .../net/ethernet/qualcomm/essedma/ess_edma.h | 0 .../drivers/net/phy/ar40xx.c | 0 .../drivers/net/phy/ar40xx.h | 0 ...add-CRYPTO_ALG_KERN_DRIVER_ONLY-flag.patch | 31 - ...40-crypto-qce-switch-to-skcipher-API.patch | 973 ---- ...ce-fix-ctr-aes-qce-block-chunk-sizes.patch | 39 - ...crypto-qce-fix-xts-aes-qce-key-sizes.patch | 50 - ...-save-a-sg-table-slot-for-result-buf.patch | 79 - ...44-crypto-qce-update-the-skcipher-IV.patch | 27 - ...qce-initialize-fallback-only-for-AES.patch | 54 - ...e-use-cryptlen-when-adding-extra-sgl.patch | 83 - ...-use-AES-fallback-for-small-requests.patch | 122 - ...-handle-AES-XTS-cases-that-qce-fails.patch | 53 - ...e-allow-building-only-hashes-ciphers.patch | 406 -- ...oc-qcom-spm-add-SCM-probe-dependency.patch | 27 - ...4019-use-v2-of-the-kpss-bringup-mech.patch | 97 - ...-ipq40xx-Fix-booting-secondary-cores.patch | 38 - ...4019-add-cpu-operating-points-for-cp.patch | 114 - ...074-ARM-qcom-Add-IPQ4019-SoC-support.patch | 36 - ...qcom-ipq4019-usb-add-binding-documen.patch | 38 - ...4019-usb-add-driver-for-QCOM-IPQ4019.patch | 234 - ...com-ipq4019-add-USB-devicetree-nodes.patch | 123 - ...RM-dts-qcom-add-gpio-ranges-property.patch | 70 - .../081-clk-fix-apss-cpu-overclocking.patch | 115 - ...86-ipq40xx-fix-high-resolution-timer.patch | 29 - ...r-add-IPQ4019-SDHCI-VQMMC-LDO-driver.patch | 153 - ...om-ipq4019-Add-SDHCI-controller-node.patch | 36 - ...dts-IPQ4019-add-SDHCI-VQMMC-LDO-node.patch | 32 - ...or-enable-4B-opcodes-for-mx25l25635f.patch | 62 - ...d-spi-nor-Add-support-for-mx25r3235f.patch | 26 - ...msm-use-sdhci_set_clock-instead-of-s.patch | 25 - .../700-net-add-qualcomm-mdio.patch | 225 - .../701-dts-ipq4019-add-mdio-node.patch | 52 - ...702-dts-ipq4019-add-PHY-switch-nodes.patch | 46 - ...4019-needs-rfs-vlan_tag-callbacks-in.patch | 53 - .../705-net-add-qualcomm-ar40xx-phy.patch | 2459 --------- ...706-ar40xx-abort-probe-on-missig-phy.patch | 23 - ...add-qualcomm-essedma-ethernet-driver.patch | 4575 ----------------- ...ts-ipq4019-add-ethernet-essedma-node.patch | 92 - .../patches-4.19/712-mr33-essedma.patch | 334 -- .../713-essedma-alloc-skb-ip-align.patch | 21 - ...ssedma-add-fix-for-memory-allocation.patch | 197 - .../850-soc-add-qualcomm-syscon.patch | 180 - .../900-dts-ipq4019-ap-dk01.1.patch | 157 - .../901-arm-boot-add-dts-files.patch | 62 - .../997-device_tree_cmdline.patch | 12 - 52 files changed, 12169 deletions(-) delete mode 100644 target/linux/ipq40xx/config-4.19 rename target/linux/ipq40xx/{files-5.4 => files}/drivers/net/ethernet/qualcomm/essedma/Makefile (100%) rename target/linux/ipq40xx/{files-5.4 => files}/drivers/net/ethernet/qualcomm/essedma/edma.c (100%) rename target/linux/ipq40xx/{files-5.4 => files}/drivers/net/ethernet/qualcomm/essedma/edma.h (100%) rename target/linux/ipq40xx/{files-5.4 => files}/drivers/net/ethernet/qualcomm/essedma/edma_axi.c (100%) rename target/linux/ipq40xx/{files-5.4 => files}/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c (100%) rename target/linux/ipq40xx/{files-5.4 => files}/drivers/net/ethernet/qualcomm/essedma/ess_edma.h (100%) rename target/linux/ipq40xx/{files-5.4 => files}/drivers/net/phy/ar40xx.c (100%) rename target/linux/ipq40xx/{files-5.4 => files}/drivers/net/phy/ar40xx.h (100%) delete mode 100644 target/linux/ipq40xx/patches-4.19/039-crypto-qce-add-CRYPTO_ALG_KERN_DRIVER_ONLY-flag.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/040-crypto-qce-switch-to-skcipher-API.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/041-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/042-crypto-qce-fix-xts-aes-qce-key-sizes.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/043-crypto-qce-save-a-sg-table-slot-for-result-buf.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/044-crypto-qce-update-the-skcipher-IV.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/046-crypto-qce-initialize-fallback-only-for-AES.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/047-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/048-crypto-qce-use-AES-fallback-for-small-requests.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/049-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/051-crypto-qce-allow-building-only-hashes-ciphers.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/070-v4.20-soc-qcom-spm-add-SCM-probe-dependency.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/071-01-v4.20-ARM-dts-qcom-ipq4019-use-v2-of-the-kpss-bringup-mech.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/071-02-ipq40xx-Fix-booting-secondary-cores.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/072-v4.20-ARM-dts-qcom-ipq4019-add-cpu-operating-points-for-cp.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/074-ARM-qcom-Add-IPQ4019-SoC-support.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/075-dt-bindings-phy-qcom-ipq4019-usb-add-binding-documen.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/076-phy-qcom-ipq4019-usb-add-driver-for-QCOM-IPQ4019.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/077-qcom-ipq4019-add-USB-devicetree-nodes.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/080-ARM-dts-qcom-add-gpio-ranges-property.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/081-clk-fix-apss-cpu-overclocking.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/086-ipq40xx-fix-high-resolution-timer.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/088-v5.6-regulator-add-IPQ4019-SDHCI-VQMMC-LDO-driver.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/089-v5.5-ARM-dts-qcom-ipq4019-Add-SDHCI-controller-node.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/100-arm-dts-IPQ4019-add-SDHCI-VQMMC-LDO-node.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/303-spi-nor-enable-4B-opcodes-for-mx25l25635f.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/304-mtd-spi-nor-Add-support-for-mx25r3235f.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/700-net-add-qualcomm-mdio.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/701-dts-ipq4019-add-mdio-node.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/702-dts-ipq4019-add-PHY-switch-nodes.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/705-net-add-qualcomm-ar40xx-phy.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/706-ar40xx-abort-probe-on-missig-phy.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/710-net-add-qualcomm-essedma-ethernet-driver.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/711-dts-ipq4019-add-ethernet-essedma-node.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/712-mr33-essedma.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/713-essedma-alloc-skb-ip-align.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/714-essedma-add-fix-for-memory-allocation.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/850-soc-add-qualcomm-syscon.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/900-dts-ipq4019-ap-dk01.1.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/901-arm-boot-add-dts-files.patch delete mode 100644 target/linux/ipq40xx/patches-4.19/997-device_tree_cmdline.patch diff --git a/target/linux/ipq40xx/config-4.19 b/target/linux/ipq40xx/config-4.19 deleted file mode 100644 index 0adcc25340..0000000000 --- a/target/linux/ipq40xx/config-4.19 +++ /dev/null @@ -1,509 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_APQ_GCC_8084 is not set -# CONFIG_APQ_MMCC_8084 is not set -CONFIG_AR40XX_PHY=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_KCOV=y -CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_ARCH_HAS_PHYS_TO_DMA=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_IPQ40XX=y -# CONFIG_ARCH_MDM9615 is not set -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -# CONFIG_ARCH_MSM8960 is not set -# CONFIG_ARCH_MSM8974 is not set -# CONFIG_ARCH_MSM8X60 is not set -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARM=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_ATAG_DTB_COMPAT is not set -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_CPU_SUSPEND=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -# CONFIG_ARM_LPAE is not set -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_SMMU is not set -# CONFIG_ARM_SP805_WATCHDOG is not set -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_AT803X_PHY=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_QCOM=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -# CONFIG_CPU_BIG_ENDIAN is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_AES_ARM=y -CONFIG_CRYPTO_AES_ARM_BS=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_QCE=y -# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set -# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set -CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y -CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512 -CONFIG_CRYPTO_DEV_QCOM_RNG=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_GF128MUL=y -# CONFIG_CRYPTO_GHASH_ARM_CE is not set -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -# CONFIG_CRYPTO_SHA1_ARM_CE is not set -# CONFIG_CRYPTO_SHA1_ARM_NEON is not set -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CRYPTO_XTS=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEBUG_USER is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -CONFIG_ESSEDMA=y -CONFIG_EXTCON=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_74X164=y -CONFIG_GPIO_WATCHDOG=y -CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_SMP=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HIGHMEM=y -# CONFIG_HIGHPTE is not set -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_QUP=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IPQ_GCC_4019=y -# CONFIG_IPQ_GCC_806X is not set -# CONFIG_IPQ_GCC_8074 is not set -# CONFIG_IPQ_LCC_806X is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_LEDS_LP5523=y -CONFIG_LEDS_LP5562=y -CONFIG_LEDS_LP55XX_COMMON=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_GPIO=y -CONFIG_MDIO_IPQ40XX=y -# CONFIG_MDM_GCC_9615 is not set -# CONFIG_MDM_LCC_9615 is not set -CONFIG_MEMFD_CREATE=y -# CONFIG_MFD_QCOM_RPM is not set -# CONFIG_MFD_SPMI_PMIC is not set -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGHT_HAVE_PCI=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_MSM=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -# CONFIG_MMC_TIFM_SD is not set -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MSM_GCC_8660 is not set -# CONFIG_MSM_GCC_8916 is not set -# CONFIG_MSM_GCC_8960 is not set -# CONFIG_MSM_GCC_8974 is not set -# CONFIG_MSM_GCC_8994 is not set -# CONFIG_MSM_GCC_8996 is not set -# CONFIG_MSM_GCC_8998 is not set -# CONFIG_MSM_LCC_8960 is not set -# CONFIG_MSM_MMCC_8960 is not set -# CONFIG_MSM_MMCC_8974 is not set -# CONFIG_MSM_MMCC_8996 is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_QCOM=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_SPLIT_WRGG_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -# CONFIG_MTD_UBI_FASTMAP is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NLS=y -CONFIG_NO_BOOTMEM=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OPTEE=y -CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1 -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_QCOM=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -# CONFIG_PHY_QCOM_APQ8064_SATA is not set -CONFIG_PHY_QCOM_IPQ4019_USB=y -# CONFIG_PHY_QCOM_IPQ806X_SATA is not set -# CONFIG_PHY_QCOM_QMP is not set -# CONFIG_PHY_QCOM_QUSB2 is not set -# CONFIG_PHY_QCOM_UFS is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_APQ8064 is not set -# CONFIG_PINCTRL_APQ8084 is not set -CONFIG_PINCTRL_IPQ4019=y -# CONFIG_PINCTRL_IPQ8064 is not set -# CONFIG_PINCTRL_IPQ8074 is not set -# CONFIG_PINCTRL_MDM9615 is not set -CONFIG_PINCTRL_MSM=y -# CONFIG_PINCTRL_MSM8660 is not set -# CONFIG_PINCTRL_MSM8916 is not set -# CONFIG_PINCTRL_MSM8960 is not set -# CONFIG_PINCTRL_MSM8994 is not set -# CONFIG_PINCTRL_MSM8996 is not set -# CONFIG_PINCTRL_MSM8998 is not set -# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set -# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set -# CONFIG_PINCTRL_SDM845 is not set -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_MSM=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_QCOM_A53PLL=y -CONFIG_QCOM_BAM_DMA=y -# CONFIG_QCOM_COMMAND_DB is not set -# CONFIG_QCOM_EBI2 is not set -# CONFIG_QCOM_GENI_SE is not set -# CONFIG_QCOM_GSBI is not set -# CONFIG_QCOM_IOMMU is not set -# CONFIG_QCOM_LLCC is not set -# CONFIG_QCOM_PDC is not set -CONFIG_QCOM_PM=y -CONFIG_QCOM_QFPROM=y -# CONFIG_QCOM_RMTFS_MEM is not set -CONFIG_QCOM_SCM=y -CONFIG_QCOM_SCM_32=y -# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set -CONFIG_QCOM_SMEM=y -# CONFIG_QCOM_SMSM is not set -CONFIG_QCOM_TCSR=y -# CONFIG_QCOM_TSENS is not set -CONFIG_QCOM_WDT=y -# CONFIG_QRTR is not set -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_REFCOUNT_FULL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -# CONFIG_REGULATOR_QCOM_SPMI is not set -CONFIG_REGULATOR_VCTRL=y -CONFIG_REGULATOR_VQMMC_IPQ4019=y -CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_QCOM_AOSS is not set -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_CMOS is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -# CONFIG_SDM_DISPCC_845 is not set -# CONFIG_SDM_GCC_845 is not set -# CONFIG_SDM_VIDEOCC_845 is not set -CONFIG_SERIAL_8250_FSL=y -# CONFIG_SERIAL_AMBA_PL011 is not set -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_QUP=y -CONFIG_SPMI=y -CONFIG_SPMI_MSM_PMIC_ARB=y -# CONFIG_SPMI_PMIC_CLKDIV is not set -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TEE=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -# CONFIG_THUMB2_KERNEL is not set -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/Makefile b/target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/Makefile similarity index 100% rename from target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/Makefile rename to target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/Makefile diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma.c b/target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma.c similarity index 100% rename from target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma.c rename to target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma.c diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma.h b/target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma.h similarity index 100% rename from target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma.h rename to target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma.h diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_axi.c b/target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma_axi.c similarity index 100% rename from target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_axi.c rename to target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma_axi.c diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c b/target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c similarity index 100% rename from target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c rename to target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/ess_edma.h b/target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/ess_edma.h similarity index 100% rename from target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/ess_edma.h rename to target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/ess_edma.h diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/phy/ar40xx.c b/target/linux/ipq40xx/files/drivers/net/phy/ar40xx.c similarity index 100% rename from target/linux/ipq40xx/files-5.4/drivers/net/phy/ar40xx.c rename to target/linux/ipq40xx/files/drivers/net/phy/ar40xx.c diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/phy/ar40xx.h b/target/linux/ipq40xx/files/drivers/net/phy/ar40xx.h similarity index 100% rename from target/linux/ipq40xx/files-5.4/drivers/net/phy/ar40xx.h rename to target/linux/ipq40xx/files/drivers/net/phy/ar40xx.h diff --git a/target/linux/ipq40xx/patches-4.19/039-crypto-qce-add-CRYPTO_ALG_KERN_DRIVER_ONLY-flag.patch b/target/linux/ipq40xx/patches-4.19/039-crypto-qce-add-CRYPTO_ALG_KERN_DRIVER_ONLY-flag.patch deleted file mode 100644 index c8aa9f4c95..0000000000 --- a/target/linux/ipq40xx/patches-4.19/039-crypto-qce-add-CRYPTO_ALG_KERN_DRIVER_ONLY-flag.patch +++ /dev/null @@ -1,31 +0,0 @@ -From: Eneas U de Queiroz -Subject: [PATCH] crypto: qce - add CRYPTO_ALG_KERN_DRIVER_ONLY flag - -Set the CRYPTO_ALG_KERN_DRIVER_ONLY flag to all algorithms exposed by -the qce driver, since they are all hardware accelerated, accessible -through a kernel driver only, and not available directly to userspace. - -Signed-off-by: Eneas U de Queiroz - ---- a/drivers/crypto/qce/ablkcipher.c -+++ b/drivers/crypto/qce/ablkcipher.c -@@ -370,7 +370,7 @@ static int qce_ablkcipher_register_one(c - - alg->cra_priority = 300; - alg->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC | -- CRYPTO_ALG_NEED_FALLBACK; -+ CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY; - alg->cra_ctxsize = sizeof(struct qce_cipher_ctx); - alg->cra_alignmask = 0; - alg->cra_type = &crypto_ablkcipher_type; ---- a/drivers/crypto/qce/sha.c -+++ b/drivers/crypto/qce/sha.c -@@ -503,7 +503,7 @@ static int qce_ahash_register_one(const - base = &alg->halg.base; - base->cra_blocksize = def->blocksize; - base->cra_priority = 300; -- base->cra_flags = CRYPTO_ALG_ASYNC; -+ base->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; - base->cra_ctxsize = sizeof(struct qce_sha_ctx); - base->cra_alignmask = 0; - base->cra_module = THIS_MODULE; diff --git a/target/linux/ipq40xx/patches-4.19/040-crypto-qce-switch-to-skcipher-API.patch b/target/linux/ipq40xx/patches-4.19/040-crypto-qce-switch-to-skcipher-API.patch deleted file mode 100644 index f13f614fd4..0000000000 --- a/target/linux/ipq40xx/patches-4.19/040-crypto-qce-switch-to-skcipher-API.patch +++ /dev/null @@ -1,973 +0,0 @@ -From f441873642eebf20566c18d2966a8cd4b433ec1c Mon Sep 17 00:00:00 2001 -From: Ard Biesheuvel -Date: Tue, 5 Nov 2019 14:28:17 +0100 -Subject: [PATCH] crypto: qce - switch to skcipher API - -Commit 7a7ffe65c8c5 ("crypto: skcipher - Add top-level skcipher interface") -dated 20 august 2015 introduced the new skcipher API which is supposed to -replace both blkcipher and ablkcipher. While all consumers of the API have -been converted long ago, some producers of the ablkcipher remain, forcing -us to keep the ablkcipher support routines alive, along with the matching -code to expose [a]blkciphers via the skcipher API. - -So switch this driver to the skcipher API, allowing us to finally drop the -blkcipher code in the near future. - -Reviewed-by: Stanimir Varbanov -Signed-off-by: Ard Biesheuvel -Backported-to-4.19-by: Eneas U de Queiroz - ---- a/drivers/crypto/qce/Makefile -+++ b/drivers/crypto/qce/Makefile -@@ -4,4 +4,4 @@ qcrypto-objs := core.o \ - common.o \ - dma.o \ - sha.o \ -- ablkcipher.o -+ skcipher.o ---- a/drivers/crypto/qce/cipher.h -+++ b/drivers/crypto/qce/cipher.h -@@ -53,12 +53,12 @@ struct qce_cipher_reqctx { - unsigned int cryptlen; - }; - --static inline struct qce_alg_template *to_cipher_tmpl(struct crypto_tfm *tfm) -+static inline struct qce_alg_template *to_cipher_tmpl(struct crypto_skcipher *tfm) - { -- struct crypto_alg *alg = tfm->__crt_alg; -- return container_of(alg, struct qce_alg_template, alg.crypto); -+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); -+ return container_of(alg, struct qce_alg_template, alg.skcipher); - } - --extern const struct qce_algo_ops ablkcipher_ops; -+extern const struct qce_algo_ops skcipher_ops; - - #endif /* _CIPHER_H_ */ ---- a/drivers/crypto/qce/common.c -+++ b/drivers/crypto/qce/common.c -@@ -312,13 +312,13 @@ go_proc: - return 0; - } - --static int qce_setup_regs_ablkcipher(struct crypto_async_request *async_req, -+static int qce_setup_regs_skcipher(struct crypto_async_request *async_req, - u32 totallen, u32 offset) - { -- struct ablkcipher_request *req = ablkcipher_request_cast(async_req); -- struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req); -+ struct skcipher_request *req = skcipher_request_cast(async_req); -+ struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req); - struct qce_cipher_ctx *ctx = crypto_tfm_ctx(async_req->tfm); -- struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm); -+ struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req)); - struct qce_device *qce = tmpl->qce; - __be32 enckey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(__be32)] = {0}; - __be32 enciv[QCE_MAX_IV_SIZE / sizeof(__be32)] = {0}; -@@ -397,8 +397,8 @@ int qce_start(struct crypto_async_reques - u32 offset) - { - switch (type) { -- case CRYPTO_ALG_TYPE_ABLKCIPHER: -- return qce_setup_regs_ablkcipher(async_req, totallen, offset); -+ case CRYPTO_ALG_TYPE_SKCIPHER: -+ return qce_setup_regs_skcipher(async_req, totallen, offset); - case CRYPTO_ALG_TYPE_AHASH: - return qce_setup_regs_ahash(async_req, totallen, offset); - default: ---- a/drivers/crypto/qce/common.h -+++ b/drivers/crypto/qce/common.h -@@ -18,6 +18,7 @@ - #include - #include - #include -+#include - - /* key size in bytes */ - #define QCE_SHA_HMAC_KEY_SIZE 64 -@@ -87,7 +88,7 @@ struct qce_alg_template { - unsigned long alg_flags; - const u32 *std_iv; - union { -- struct crypto_alg crypto; -+ struct skcipher_alg skcipher; - struct ahash_alg ahash; - } alg; - struct qce_device *qce; ---- a/drivers/crypto/qce/core.c -+++ b/drivers/crypto/qce/core.c -@@ -30,7 +30,7 @@ - #define QCE_QUEUE_LENGTH 1 - - static const struct qce_algo_ops *qce_ops[] = { -- &ablkcipher_ops, -+ &skcipher_ops, - &ahash_ops, - }; - ---- a/drivers/crypto/qce/ablkcipher.c -+++ /dev/null -@@ -1,431 +0,0 @@ --/* -- * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License version 2 and -- * only version 2 as published by the Free Software Foundation. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- */ -- --#include --#include --#include --#include --#include --#include -- --#include "cipher.h" -- --static LIST_HEAD(ablkcipher_algs); -- --static void qce_ablkcipher_done(void *data) --{ -- struct crypto_async_request *async_req = data; -- struct ablkcipher_request *req = ablkcipher_request_cast(async_req); -- struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req); -- struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm); -- struct qce_device *qce = tmpl->qce; -- enum dma_data_direction dir_src, dir_dst; -- u32 status; -- int error; -- bool diff_dst; -- -- diff_dst = (req->src != req->dst) ? true : false; -- dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; -- dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL; -- -- error = qce_dma_terminate_all(&qce->dma); -- if (error) -- dev_dbg(qce->dev, "ablkcipher dma termination error (%d)\n", -- error); -- -- if (diff_dst) -- dma_unmap_sg(qce->dev, rctx->src_sg, rctx->src_nents, dir_src); -- dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst); -- -- sg_free_table(&rctx->dst_tbl); -- -- error = qce_check_status(qce, &status); -- if (error < 0) -- dev_dbg(qce->dev, "ablkcipher operation error (%x)\n", status); -- -- qce->async_req_done(tmpl->qce, error); --} -- --static int --qce_ablkcipher_async_req_handle(struct crypto_async_request *async_req) --{ -- struct ablkcipher_request *req = ablkcipher_request_cast(async_req); -- struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req); -- struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); -- struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm); -- struct qce_device *qce = tmpl->qce; -- enum dma_data_direction dir_src, dir_dst; -- struct scatterlist *sg; -- bool diff_dst; -- gfp_t gfp; -- int ret; -- -- rctx->iv = req->info; -- rctx->ivsize = crypto_ablkcipher_ivsize(ablkcipher); -- rctx->cryptlen = req->nbytes; -- -- diff_dst = (req->src != req->dst) ? true : false; -- dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; -- dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL; -- -- rctx->src_nents = sg_nents_for_len(req->src, req->nbytes); -- if (diff_dst) -- rctx->dst_nents = sg_nents_for_len(req->dst, req->nbytes); -- else -- rctx->dst_nents = rctx->src_nents; -- if (rctx->src_nents < 0) { -- dev_err(qce->dev, "Invalid numbers of src SG.\n"); -- return rctx->src_nents; -- } -- if (rctx->dst_nents < 0) { -- dev_err(qce->dev, "Invalid numbers of dst SG.\n"); -- return -rctx->dst_nents; -- } -- -- rctx->dst_nents += 1; -- -- gfp = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? -- GFP_KERNEL : GFP_ATOMIC; -- -- ret = sg_alloc_table(&rctx->dst_tbl, rctx->dst_nents, gfp); -- if (ret) -- return ret; -- -- sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ); -- -- sg = qce_sgtable_add(&rctx->dst_tbl, req->dst); -- if (IS_ERR(sg)) { -- ret = PTR_ERR(sg); -- goto error_free; -- } -- -- sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg); -- if (IS_ERR(sg)) { -- ret = PTR_ERR(sg); -- goto error_free; -- } -- -- sg_mark_end(sg); -- rctx->dst_sg = rctx->dst_tbl.sgl; -- -- ret = dma_map_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst); -- if (ret < 0) -- goto error_free; -- -- if (diff_dst) { -- ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, dir_src); -- if (ret < 0) -- goto error_unmap_dst; -- rctx->src_sg = req->src; -- } else { -- rctx->src_sg = rctx->dst_sg; -- } -- -- ret = qce_dma_prep_sgs(&qce->dma, rctx->src_sg, rctx->src_nents, -- rctx->dst_sg, rctx->dst_nents, -- qce_ablkcipher_done, async_req); -- if (ret) -- goto error_unmap_src; -- -- qce_dma_issue_pending(&qce->dma); -- -- ret = qce_start(async_req, tmpl->crypto_alg_type, req->nbytes, 0); -- if (ret) -- goto error_terminate; -- -- return 0; -- --error_terminate: -- qce_dma_terminate_all(&qce->dma); --error_unmap_src: -- if (diff_dst) -- dma_unmap_sg(qce->dev, req->src, rctx->src_nents, dir_src); --error_unmap_dst: -- dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst); --error_free: -- sg_free_table(&rctx->dst_tbl); -- return ret; --} -- --static int qce_ablkcipher_setkey(struct crypto_ablkcipher *ablk, const u8 *key, -- unsigned int keylen) --{ -- struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablk); -- struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm); -- unsigned long flags = to_cipher_tmpl(tfm)->alg_flags; -- int ret; -- -- if (!key || !keylen) -- return -EINVAL; -- -- if (IS_AES(flags)) { -- switch (keylen) { -- case AES_KEYSIZE_128: -- case AES_KEYSIZE_256: -- break; -- default: -- goto fallback; -- } -- } else if (IS_DES(flags)) { -- u32 tmp[DES_EXPKEY_WORDS]; -- -- ret = des_ekey(tmp, key); -- if (!ret && crypto_ablkcipher_get_flags(ablk) & -- CRYPTO_TFM_REQ_WEAK_KEY) -- goto weakkey; -- } -- -- ctx->enc_keylen = keylen; -- memcpy(ctx->enc_key, key, keylen); -- return 0; --fallback: -- ret = crypto_skcipher_setkey(ctx->fallback, key, keylen); -- if (!ret) -- ctx->enc_keylen = keylen; -- return ret; --weakkey: -- crypto_ablkcipher_set_flags(ablk, CRYPTO_TFM_RES_WEAK_KEY); -- return -EINVAL; --} -- --static int qce_ablkcipher_crypt(struct ablkcipher_request *req, int encrypt) --{ -- struct crypto_tfm *tfm = -- crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req)); -- struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm); -- struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req); -- struct qce_alg_template *tmpl = to_cipher_tmpl(tfm); -- int ret; -- -- rctx->flags = tmpl->alg_flags; -- rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT; -- -- if (IS_AES(rctx->flags) && ctx->enc_keylen != AES_KEYSIZE_128 && -- ctx->enc_keylen != AES_KEYSIZE_256) { -- SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); -- -- skcipher_request_set_tfm(subreq, ctx->fallback); -- skcipher_request_set_callback(subreq, req->base.flags, -- NULL, NULL); -- skcipher_request_set_crypt(subreq, req->src, req->dst, -- req->nbytes, req->info); -- ret = encrypt ? crypto_skcipher_encrypt(subreq) : -- crypto_skcipher_decrypt(subreq); -- skcipher_request_zero(subreq); -- return ret; -- } -- -- return tmpl->qce->async_req_enqueue(tmpl->qce, &req->base); --} -- --static int qce_ablkcipher_encrypt(struct ablkcipher_request *req) --{ -- return qce_ablkcipher_crypt(req, 1); --} -- --static int qce_ablkcipher_decrypt(struct ablkcipher_request *req) --{ -- return qce_ablkcipher_crypt(req, 0); --} -- --static int qce_ablkcipher_init(struct crypto_tfm *tfm) --{ -- struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm); -- -- memset(ctx, 0, sizeof(*ctx)); -- tfm->crt_ablkcipher.reqsize = sizeof(struct qce_cipher_reqctx); -- -- ctx->fallback = crypto_alloc_skcipher(crypto_tfm_alg_name(tfm), 0, -- CRYPTO_ALG_ASYNC | -- CRYPTO_ALG_NEED_FALLBACK); -- return PTR_ERR_OR_ZERO(ctx->fallback); --} -- --static void qce_ablkcipher_exit(struct crypto_tfm *tfm) --{ -- struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm); -- -- crypto_free_skcipher(ctx->fallback); --} -- --struct qce_ablkcipher_def { -- unsigned long flags; -- const char *name; -- const char *drv_name; -- unsigned int blocksize; -- unsigned int ivsize; -- unsigned int min_keysize; -- unsigned int max_keysize; --}; -- --static const struct qce_ablkcipher_def ablkcipher_def[] = { -- { -- .flags = QCE_ALG_AES | QCE_MODE_ECB, -- .name = "ecb(aes)", -- .drv_name = "ecb-aes-qce", -- .blocksize = AES_BLOCK_SIZE, -- .ivsize = AES_BLOCK_SIZE, -- .min_keysize = AES_MIN_KEY_SIZE, -- .max_keysize = AES_MAX_KEY_SIZE, -- }, -- { -- .flags = QCE_ALG_AES | QCE_MODE_CBC, -- .name = "cbc(aes)", -- .drv_name = "cbc-aes-qce", -- .blocksize = AES_BLOCK_SIZE, -- .ivsize = AES_BLOCK_SIZE, -- .min_keysize = AES_MIN_KEY_SIZE, -- .max_keysize = AES_MAX_KEY_SIZE, -- }, -- { -- .flags = QCE_ALG_AES | QCE_MODE_CTR, -- .name = "ctr(aes)", -- .drv_name = "ctr-aes-qce", -- .blocksize = AES_BLOCK_SIZE, -- .ivsize = AES_BLOCK_SIZE, -- .min_keysize = AES_MIN_KEY_SIZE, -- .max_keysize = AES_MAX_KEY_SIZE, -- }, -- { -- .flags = QCE_ALG_AES | QCE_MODE_XTS, -- .name = "xts(aes)", -- .drv_name = "xts-aes-qce", -- .blocksize = AES_BLOCK_SIZE, -- .ivsize = AES_BLOCK_SIZE, -- .min_keysize = AES_MIN_KEY_SIZE, -- .max_keysize = AES_MAX_KEY_SIZE, -- }, -- { -- .flags = QCE_ALG_DES | QCE_MODE_ECB, -- .name = "ecb(des)", -- .drv_name = "ecb-des-qce", -- .blocksize = DES_BLOCK_SIZE, -- .ivsize = 0, -- .min_keysize = DES_KEY_SIZE, -- .max_keysize = DES_KEY_SIZE, -- }, -- { -- .flags = QCE_ALG_DES | QCE_MODE_CBC, -- .name = "cbc(des)", -- .drv_name = "cbc-des-qce", -- .blocksize = DES_BLOCK_SIZE, -- .ivsize = DES_BLOCK_SIZE, -- .min_keysize = DES_KEY_SIZE, -- .max_keysize = DES_KEY_SIZE, -- }, -- { -- .flags = QCE_ALG_3DES | QCE_MODE_ECB, -- .name = "ecb(des3_ede)", -- .drv_name = "ecb-3des-qce", -- .blocksize = DES3_EDE_BLOCK_SIZE, -- .ivsize = 0, -- .min_keysize = DES3_EDE_KEY_SIZE, -- .max_keysize = DES3_EDE_KEY_SIZE, -- }, -- { -- .flags = QCE_ALG_3DES | QCE_MODE_CBC, -- .name = "cbc(des3_ede)", -- .drv_name = "cbc-3des-qce", -- .blocksize = DES3_EDE_BLOCK_SIZE, -- .ivsize = DES3_EDE_BLOCK_SIZE, -- .min_keysize = DES3_EDE_KEY_SIZE, -- .max_keysize = DES3_EDE_KEY_SIZE, -- }, --}; -- --static int qce_ablkcipher_register_one(const struct qce_ablkcipher_def *def, -- struct qce_device *qce) --{ -- struct qce_alg_template *tmpl; -- struct crypto_alg *alg; -- int ret; -- -- tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL); -- if (!tmpl) -- return -ENOMEM; -- -- alg = &tmpl->alg.crypto; -- -- snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name); -- snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", -- def->drv_name); -- -- alg->cra_blocksize = def->blocksize; -- alg->cra_ablkcipher.ivsize = def->ivsize; -- alg->cra_ablkcipher.min_keysize = def->min_keysize; -- alg->cra_ablkcipher.max_keysize = def->max_keysize; -- alg->cra_ablkcipher.setkey = qce_ablkcipher_setkey; -- alg->cra_ablkcipher.encrypt = qce_ablkcipher_encrypt; -- alg->cra_ablkcipher.decrypt = qce_ablkcipher_decrypt; -- -- alg->cra_priority = 300; -- alg->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC | -- CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY; -- alg->cra_ctxsize = sizeof(struct qce_cipher_ctx); -- alg->cra_alignmask = 0; -- alg->cra_type = &crypto_ablkcipher_type; -- alg->cra_module = THIS_MODULE; -- alg->cra_init = qce_ablkcipher_init; -- alg->cra_exit = qce_ablkcipher_exit; -- INIT_LIST_HEAD(&alg->cra_list); -- -- INIT_LIST_HEAD(&tmpl->entry); -- tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_ABLKCIPHER; -- tmpl->alg_flags = def->flags; -- tmpl->qce = qce; -- -- ret = crypto_register_alg(alg); -- if (ret) { -- kfree(tmpl); -- dev_err(qce->dev, "%s registration failed\n", alg->cra_name); -- return ret; -- } -- -- list_add_tail(&tmpl->entry, &ablkcipher_algs); -- dev_dbg(qce->dev, "%s is registered\n", alg->cra_name); -- return 0; --} -- --static void qce_ablkcipher_unregister(struct qce_device *qce) --{ -- struct qce_alg_template *tmpl, *n; -- -- list_for_each_entry_safe(tmpl, n, &ablkcipher_algs, entry) { -- crypto_unregister_alg(&tmpl->alg.crypto); -- list_del(&tmpl->entry); -- kfree(tmpl); -- } --} -- --static int qce_ablkcipher_register(struct qce_device *qce) --{ -- int ret, i; -- -- for (i = 0; i < ARRAY_SIZE(ablkcipher_def); i++) { -- ret = qce_ablkcipher_register_one(&ablkcipher_def[i], qce); -- if (ret) -- goto err; -- } -- -- return 0; --err: -- qce_ablkcipher_unregister(qce); -- return ret; --} -- --const struct qce_algo_ops ablkcipher_ops = { -- .type = CRYPTO_ALG_TYPE_ABLKCIPHER, -- .register_algs = qce_ablkcipher_register, -- .unregister_algs = qce_ablkcipher_unregister, -- .async_req_handle = qce_ablkcipher_async_req_handle, --}; ---- /dev/null -+++ b/drivers/crypto/qce/skcipher.c -@@ -0,0 +1,429 @@ -+/* -+ * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "cipher.h" -+ -+static LIST_HEAD(skcipher_algs); -+ -+static void qce_skcipher_done(void *data) -+{ -+ struct crypto_async_request *async_req = data; -+ struct skcipher_request *req = skcipher_request_cast(async_req); -+ struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req); -+ struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req)); -+ struct qce_device *qce = tmpl->qce; -+ enum dma_data_direction dir_src, dir_dst; -+ u32 status; -+ int error; -+ bool diff_dst; -+ -+ diff_dst = (req->src != req->dst) ? true : false; -+ dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; -+ dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL; -+ -+ error = qce_dma_terminate_all(&qce->dma); -+ if (error) -+ dev_dbg(qce->dev, "skcipher dma termination error (%d)\n", -+ error); -+ -+ if (diff_dst) -+ dma_unmap_sg(qce->dev, rctx->src_sg, rctx->src_nents, dir_src); -+ dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst); -+ -+ sg_free_table(&rctx->dst_tbl); -+ -+ error = qce_check_status(qce, &status); -+ if (error < 0) -+ dev_dbg(qce->dev, "skcipher operation error (%x)\n", status); -+ -+ qce->async_req_done(tmpl->qce, error); -+} -+ -+static int -+qce_skcipher_async_req_handle(struct crypto_async_request *async_req) -+{ -+ struct skcipher_request *req = skcipher_request_cast(async_req); -+ struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req); -+ struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); -+ struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req)); -+ struct qce_device *qce = tmpl->qce; -+ enum dma_data_direction dir_src, dir_dst; -+ struct scatterlist *sg; -+ bool diff_dst; -+ gfp_t gfp; -+ int ret; -+ -+ rctx->iv = req->iv; -+ rctx->ivsize = crypto_skcipher_ivsize(skcipher); -+ rctx->cryptlen = req->cryptlen; -+ -+ diff_dst = (req->src != req->dst) ? true : false; -+ dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; -+ dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL; -+ -+ rctx->src_nents = sg_nents_for_len(req->src, req->cryptlen); -+ if (diff_dst) -+ rctx->dst_nents = sg_nents_for_len(req->dst, req->cryptlen); -+ else -+ rctx->dst_nents = rctx->src_nents; -+ if (rctx->src_nents < 0) { -+ dev_err(qce->dev, "Invalid numbers of src SG.\n"); -+ return rctx->src_nents; -+ } -+ if (rctx->dst_nents < 0) { -+ dev_err(qce->dev, "Invalid numbers of dst SG.\n"); -+ return -rctx->dst_nents; -+ } -+ -+ rctx->dst_nents += 1; -+ -+ gfp = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? -+ GFP_KERNEL : GFP_ATOMIC; -+ -+ ret = sg_alloc_table(&rctx->dst_tbl, rctx->dst_nents, gfp); -+ if (ret) -+ return ret; -+ -+ sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ); -+ -+ sg = qce_sgtable_add(&rctx->dst_tbl, req->dst); -+ if (IS_ERR(sg)) { -+ ret = PTR_ERR(sg); -+ goto error_free; -+ } -+ -+ sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg); -+ if (IS_ERR(sg)) { -+ ret = PTR_ERR(sg); -+ goto error_free; -+ } -+ -+ sg_mark_end(sg); -+ rctx->dst_sg = rctx->dst_tbl.sgl; -+ -+ ret = dma_map_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst); -+ if (ret < 0) -+ goto error_free; -+ -+ if (diff_dst) { -+ ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, dir_src); -+ if (ret < 0) -+ goto error_unmap_dst; -+ rctx->src_sg = req->src; -+ } else { -+ rctx->src_sg = rctx->dst_sg; -+ } -+ -+ ret = qce_dma_prep_sgs(&qce->dma, rctx->src_sg, rctx->src_nents, -+ rctx->dst_sg, rctx->dst_nents, -+ qce_skcipher_done, async_req); -+ if (ret) -+ goto error_unmap_src; -+ -+ qce_dma_issue_pending(&qce->dma); -+ -+ ret = qce_start(async_req, tmpl->crypto_alg_type, req->cryptlen, 0); -+ if (ret) -+ goto error_terminate; -+ -+ return 0; -+ -+error_terminate: -+ qce_dma_terminate_all(&qce->dma); -+error_unmap_src: -+ if (diff_dst) -+ dma_unmap_sg(qce->dev, req->src, rctx->src_nents, dir_src); -+error_unmap_dst: -+ dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst); -+error_free: -+ sg_free_table(&rctx->dst_tbl); -+ return ret; -+} -+ -+static int qce_skcipher_setkey(struct crypto_skcipher *ablk, const u8 *key, -+ unsigned int keylen) -+{ -+ struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(ablk); -+ unsigned long flags = to_cipher_tmpl(ablk)->alg_flags; -+ int ret; -+ -+ if (!key || !keylen) -+ return -EINVAL; -+ -+ if (IS_AES(flags)) { -+ switch (keylen) { -+ case AES_KEYSIZE_128: -+ case AES_KEYSIZE_256: -+ break; -+ default: -+ goto fallback; -+ } -+ } else if (IS_DES(flags)) { -+ u32 tmp[DES_EXPKEY_WORDS]; -+ -+ ret = des_ekey(tmp, key); -+ if (!ret && crypto_skcipher_get_flags(ablk) & -+ CRYPTO_TFM_REQ_WEAK_KEY) -+ goto weakkey; -+ } -+ -+ ctx->enc_keylen = keylen; -+ memcpy(ctx->enc_key, key, keylen); -+ return 0; -+fallback: -+ ret = crypto_skcipher_setkey(ctx->fallback, key, keylen); -+ if (!ret) -+ ctx->enc_keylen = keylen; -+ return ret; -+weakkey: -+ crypto_skcipher_set_flags(ablk, CRYPTO_TFM_RES_WEAK_KEY); -+ return -EINVAL; -+} -+ -+static int qce_skcipher_crypt(struct skcipher_request *req, int encrypt) -+{ -+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); -+ struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); -+ struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req); -+ struct qce_alg_template *tmpl = to_cipher_tmpl(tfm); -+ int ret; -+ -+ rctx->flags = tmpl->alg_flags; -+ rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT; -+ -+ if (IS_AES(rctx->flags) && ctx->enc_keylen != AES_KEYSIZE_128 && -+ ctx->enc_keylen != AES_KEYSIZE_256) { -+ SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); -+ -+ skcipher_request_set_tfm(subreq, ctx->fallback); -+ skcipher_request_set_callback(subreq, req->base.flags, -+ NULL, NULL); -+ skcipher_request_set_crypt(subreq, req->src, req->dst, -+ req->cryptlen, req->iv); -+ ret = encrypt ? crypto_skcipher_encrypt(subreq) : -+ crypto_skcipher_decrypt(subreq); -+ skcipher_request_zero(subreq); -+ return ret; -+ } -+ -+ return tmpl->qce->async_req_enqueue(tmpl->qce, &req->base); -+} -+ -+static int qce_skcipher_encrypt(struct skcipher_request *req) -+{ -+ return qce_skcipher_crypt(req, 1); -+} -+ -+static int qce_skcipher_decrypt(struct skcipher_request *req) -+{ -+ return qce_skcipher_crypt(req, 0); -+} -+ -+static int qce_skcipher_init(struct crypto_skcipher *tfm) -+{ -+ struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); -+ -+ memset(ctx, 0, sizeof(*ctx)); -+ crypto_skcipher_set_reqsize(tfm, sizeof(struct qce_cipher_reqctx)); -+ -+ ctx->fallback = crypto_alloc_skcipher(crypto_tfm_alg_name(&tfm->base), -+ 0, CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK); -+ return PTR_ERR_OR_ZERO(ctx->fallback); -+} -+ -+static void qce_skcipher_exit(struct crypto_skcipher *tfm) -+{ -+ struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); -+ -+ crypto_free_skcipher(ctx->fallback); -+} -+ -+struct qce_skcipher_def { -+ unsigned long flags; -+ const char *name; -+ const char *drv_name; -+ unsigned int blocksize; -+ unsigned int ivsize; -+ unsigned int min_keysize; -+ unsigned int max_keysize; -+}; -+ -+static const struct qce_skcipher_def skcipher_def[] = { -+ { -+ .flags = QCE_ALG_AES | QCE_MODE_ECB, -+ .name = "ecb(aes)", -+ .drv_name = "ecb-aes-qce", -+ .blocksize = AES_BLOCK_SIZE, -+ .ivsize = AES_BLOCK_SIZE, -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ }, -+ { -+ .flags = QCE_ALG_AES | QCE_MODE_CBC, -+ .name = "cbc(aes)", -+ .drv_name = "cbc-aes-qce", -+ .blocksize = AES_BLOCK_SIZE, -+ .ivsize = AES_BLOCK_SIZE, -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ }, -+ { -+ .flags = QCE_ALG_AES | QCE_MODE_CTR, -+ .name = "ctr(aes)", -+ .drv_name = "ctr-aes-qce", -+ .blocksize = AES_BLOCK_SIZE, -+ .ivsize = AES_BLOCK_SIZE, -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ }, -+ { -+ .flags = QCE_ALG_AES | QCE_MODE_XTS, -+ .name = "xts(aes)", -+ .drv_name = "xts-aes-qce", -+ .blocksize = AES_BLOCK_SIZE, -+ .ivsize = AES_BLOCK_SIZE, -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ }, -+ { -+ .flags = QCE_ALG_DES | QCE_MODE_ECB, -+ .name = "ecb(des)", -+ .drv_name = "ecb-des-qce", -+ .blocksize = DES_BLOCK_SIZE, -+ .ivsize = 0, -+ .min_keysize = DES_KEY_SIZE, -+ .max_keysize = DES_KEY_SIZE, -+ }, -+ { -+ .flags = QCE_ALG_DES | QCE_MODE_CBC, -+ .name = "cbc(des)", -+ .drv_name = "cbc-des-qce", -+ .blocksize = DES_BLOCK_SIZE, -+ .ivsize = DES_BLOCK_SIZE, -+ .min_keysize = DES_KEY_SIZE, -+ .max_keysize = DES_KEY_SIZE, -+ }, -+ { -+ .flags = QCE_ALG_3DES | QCE_MODE_ECB, -+ .name = "ecb(des3_ede)", -+ .drv_name = "ecb-3des-qce", -+ .blocksize = DES3_EDE_BLOCK_SIZE, -+ .ivsize = 0, -+ .min_keysize = DES3_EDE_KEY_SIZE, -+ .max_keysize = DES3_EDE_KEY_SIZE, -+ }, -+ { -+ .flags = QCE_ALG_3DES | QCE_MODE_CBC, -+ .name = "cbc(des3_ede)", -+ .drv_name = "cbc-3des-qce", -+ .blocksize = DES3_EDE_BLOCK_SIZE, -+ .ivsize = DES3_EDE_BLOCK_SIZE, -+ .min_keysize = DES3_EDE_KEY_SIZE, -+ .max_keysize = DES3_EDE_KEY_SIZE, -+ }, -+}; -+ -+static int qce_skcipher_register_one(const struct qce_skcipher_def *def, -+ struct qce_device *qce) -+{ -+ struct qce_alg_template *tmpl; -+ struct skcipher_alg *alg; -+ int ret; -+ -+ tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL); -+ if (!tmpl) -+ return -ENOMEM; -+ -+ alg = &tmpl->alg.skcipher; -+ -+ snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name); -+ snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", -+ def->drv_name); -+ -+ alg->base.cra_blocksize = def->blocksize; -+ alg->ivsize = def->ivsize; -+ alg->min_keysize = def->min_keysize; -+ alg->max_keysize = def->max_keysize; -+ alg->setkey = qce_skcipher_setkey; -+ alg->encrypt = qce_skcipher_encrypt; -+ alg->decrypt = qce_skcipher_decrypt; -+ -+ alg->base.cra_priority = 300; -+ alg->base.cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK | -+ CRYPTO_ALG_KERN_DRIVER_ONLY; -+ alg->base.cra_ctxsize = sizeof(struct qce_cipher_ctx); -+ alg->base.cra_alignmask = 0; -+ alg->base.cra_module = THIS_MODULE; -+ -+ alg->init = qce_skcipher_init; -+ alg->exit = qce_skcipher_exit; -+ -+ INIT_LIST_HEAD(&tmpl->entry); -+ tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_SKCIPHER; -+ tmpl->alg_flags = def->flags; -+ tmpl->qce = qce; -+ -+ ret = crypto_register_skcipher(alg); -+ if (ret) { -+ kfree(tmpl); -+ dev_err(qce->dev, "%s registration failed\n", alg->base.cra_name); -+ return ret; -+ } -+ -+ list_add_tail(&tmpl->entry, &skcipher_algs); -+ dev_dbg(qce->dev, "%s is registered\n", alg->base.cra_name); -+ return 0; -+} -+ -+static void qce_skcipher_unregister(struct qce_device *qce) -+{ -+ struct qce_alg_template *tmpl, *n; -+ -+ list_for_each_entry_safe(tmpl, n, &skcipher_algs, entry) { -+ crypto_unregister_skcipher(&tmpl->alg.skcipher); -+ list_del(&tmpl->entry); -+ kfree(tmpl); -+ } -+} -+ -+static int qce_skcipher_register(struct qce_device *qce) -+{ -+ int ret, i; -+ -+ for (i = 0; i < ARRAY_SIZE(skcipher_def); i++) { -+ ret = qce_skcipher_register_one(&skcipher_def[i], qce); -+ if (ret) -+ goto err; -+ } -+ -+ return 0; -+err: -+ qce_skcipher_unregister(qce); -+ return ret; -+} -+ -+const struct qce_algo_ops skcipher_ops = { -+ .type = CRYPTO_ALG_TYPE_SKCIPHER, -+ .register_algs = qce_skcipher_register, -+ .unregister_algs = qce_skcipher_unregister, -+ .async_req_handle = qce_skcipher_async_req_handle, -+}; diff --git a/target/linux/ipq40xx/patches-4.19/041-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch b/target/linux/ipq40xx/patches-4.19/041-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch deleted file mode 100644 index 59f7445a15..0000000000 --- a/target/linux/ipq40xx/patches-4.19/041-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 3f5598286445f695bb63a22239dd3603c69a6eaf Mon Sep 17 00:00:00 2001 -From: Eneas U de Queiroz -Date: Mon, 28 Oct 2019 09:03:07 -0300 -Subject: [PATCH] crypto: qce - fix ctr-aes-qce block, chunk sizes - -Set blocksize of ctr-aes-qce to 1, so it can operate as a stream cipher, -adding the definition for chucksize instead, where the underlying block -size belongs. - -Signed-off-by: Eneas U de Queiroz - ---- a/drivers/crypto/qce/skcipher.c -+++ b/drivers/crypto/qce/skcipher.c -@@ -261,6 +261,7 @@ struct qce_skcipher_def { - const char *name; - const char *drv_name; - unsigned int blocksize; -+ unsigned int chunksize; - unsigned int ivsize; - unsigned int min_keysize; - unsigned int max_keysize; -@@ -289,7 +290,8 @@ static const struct qce_skcipher_def skc - .flags = QCE_ALG_AES | QCE_MODE_CTR, - .name = "ctr(aes)", - .drv_name = "ctr-aes-qce", -- .blocksize = AES_BLOCK_SIZE, -+ .blocksize = 1, -+ .chunksize = AES_BLOCK_SIZE, - .ivsize = AES_BLOCK_SIZE, - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, -@@ -359,6 +361,7 @@ static int qce_skcipher_register_one(con - def->drv_name); - - alg->base.cra_blocksize = def->blocksize; -+ alg->chunksize = def->chunksize; - alg->ivsize = def->ivsize; - alg->min_keysize = def->min_keysize; - alg->max_keysize = def->max_keysize; diff --git a/target/linux/ipq40xx/patches-4.19/042-crypto-qce-fix-xts-aes-qce-key-sizes.patch b/target/linux/ipq40xx/patches-4.19/042-crypto-qce-fix-xts-aes-qce-key-sizes.patch deleted file mode 100644 index 50b888351c..0000000000 --- a/target/linux/ipq40xx/patches-4.19/042-crypto-qce-fix-xts-aes-qce-key-sizes.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 0138c3c13809250338d7cfba6f4ca3b2da02b2c8 Mon Sep 17 00:00:00 2001 -From: Eneas U de Queiroz -Date: Thu, 21 Nov 2019 14:28:23 -0300 -Subject: [PATCH] crypto: qce - fix xts-aes-qce key sizes - -XTS-mode uses two keys, so the keysizes should be doubled in -skcipher_def, and halved when checking if it is AES-128/192/256. - -Signed-off-by: Eneas U de Queiroz - ---- a/drivers/crypto/qce/skcipher.c -+++ b/drivers/crypto/qce/skcipher.c -@@ -168,7 +168,7 @@ static int qce_skcipher_setkey(struct cr - return -EINVAL; - - if (IS_AES(flags)) { -- switch (keylen) { -+ switch (IS_XTS(flags) ? keylen >> 1 : keylen) { - case AES_KEYSIZE_128: - case AES_KEYSIZE_256: - break; -@@ -203,13 +203,15 @@ static int qce_skcipher_crypt(struct skc - struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); - struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req); - struct qce_alg_template *tmpl = to_cipher_tmpl(tfm); -+ int keylen; - int ret; - - rctx->flags = tmpl->alg_flags; - rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT; -+ keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen; - -- if (IS_AES(rctx->flags) && ctx->enc_keylen != AES_KEYSIZE_128 && -- ctx->enc_keylen != AES_KEYSIZE_256) { -+ if (IS_AES(rctx->flags) && keylen != AES_KEYSIZE_128 && -+ keylen != AES_KEYSIZE_256) { - SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); - - skcipher_request_set_tfm(subreq, ctx->fallback); -@@ -302,8 +304,8 @@ static const struct qce_skcipher_def skc - .drv_name = "xts-aes-qce", - .blocksize = AES_BLOCK_SIZE, - .ivsize = AES_BLOCK_SIZE, -- .min_keysize = AES_MIN_KEY_SIZE, -- .max_keysize = AES_MAX_KEY_SIZE, -+ .min_keysize = AES_MIN_KEY_SIZE * 2, -+ .max_keysize = AES_MAX_KEY_SIZE * 2, - }, - { - .flags = QCE_ALG_DES | QCE_MODE_ECB, diff --git a/target/linux/ipq40xx/patches-4.19/043-crypto-qce-save-a-sg-table-slot-for-result-buf.patch b/target/linux/ipq40xx/patches-4.19/043-crypto-qce-save-a-sg-table-slot-for-result-buf.patch deleted file mode 100644 index 95650690fb..0000000000 --- a/target/linux/ipq40xx/patches-4.19/043-crypto-qce-save-a-sg-table-slot-for-result-buf.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 31f796293b6c38126a466414c565827b9cfdbe39 Mon Sep 17 00:00:00 2001 -From: Eneas U de Queiroz -Date: Wed, 20 Nov 2019 21:39:11 -0300 -Subject: [PATCH] crypto: qce - save a sg table slot for result buf - -When ctr-aes-qce is used for gcm-mode, an extra sg entry for the -authentication tag is present, causing trouble when the qce driver -prepares the dst-results eg table for dma. - -It computes the number of entries needed with sg_nents_for_len, leaving -out the tag entry. Then it creates a sg table with that number plus -one, used to store a "result" sg. - -When copying the sg table, it does not limit the number of entries -copied, so tha extra slot is filled with the authentication tag sg. -When the driver tries to add the result sg, the list is full, and it -returns EINVAL. - -By limiting the number of sg entries copied to the dest table, the slot -for the result buffer is guaranteed to be unused. - -Signed-off-by: Eneas U de Queiroz - ---- a/drivers/crypto/qce/dma.c -+++ b/drivers/crypto/qce/dma.c -@@ -55,7 +55,8 @@ void qce_dma_release(struct qce_dma_data - } - - struct scatterlist * --qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl) -+qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl, -+ int max_ents) - { - struct scatterlist *sg = sgt->sgl, *sg_last = NULL; - -@@ -68,12 +69,13 @@ qce_sgtable_add(struct sg_table *sgt, st - if (!sg) - return ERR_PTR(-EINVAL); - -- while (new_sgl && sg) { -+ while (new_sgl && sg && max_ents) { - sg_set_page(sg, sg_page(new_sgl), new_sgl->length, - new_sgl->offset); - sg_last = sg; - sg = sg_next(sg); - new_sgl = sg_next(new_sgl); -+ max_ents--; - } - - return sg_last; ---- a/drivers/crypto/qce/dma.h -+++ b/drivers/crypto/qce/dma.h -@@ -50,6 +50,7 @@ int qce_dma_prep_sgs(struct qce_dma_data - void qce_dma_issue_pending(struct qce_dma_data *dma); - int qce_dma_terminate_all(struct qce_dma_data *dma); - struct scatterlist * --qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add); -+qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add, -+ int max_ents); - - #endif /* _DMA_H_ */ ---- a/drivers/crypto/qce/skcipher.c -+++ b/drivers/crypto/qce/skcipher.c -@@ -103,13 +103,13 @@ qce_skcipher_async_req_handle(struct cry - - sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ); - -- sg = qce_sgtable_add(&rctx->dst_tbl, req->dst); -+ sg = qce_sgtable_add(&rctx->dst_tbl, req->dst, rctx->dst_nents - 1); - if (IS_ERR(sg)) { - ret = PTR_ERR(sg); - goto error_free; - } - -- sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg); -+ sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg, 1); - if (IS_ERR(sg)) { - ret = PTR_ERR(sg); - goto error_free; diff --git a/target/linux/ipq40xx/patches-4.19/044-crypto-qce-update-the-skcipher-IV.patch b/target/linux/ipq40xx/patches-4.19/044-crypto-qce-update-the-skcipher-IV.patch deleted file mode 100644 index 33be510a82..0000000000 --- a/target/linux/ipq40xx/patches-4.19/044-crypto-qce-update-the-skcipher-IV.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 502ca0b7c1d856a46dbd78e67690c12c47775b97 Mon Sep 17 00:00:00 2001 -From: Eneas U de Queiroz -Date: Fri, 22 Nov 2019 09:00:02 -0300 -Subject: [PATCH] crypto: qce - update the skcipher IV - -Update the IV after the completion of each cipher operation. - -Signed-off-by: Eneas U de Queiroz - ---- a/drivers/crypto/qce/skcipher.c -+++ b/drivers/crypto/qce/skcipher.c -@@ -29,6 +29,7 @@ static void qce_skcipher_done(void *data - struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req); - struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req)); - struct qce_device *qce = tmpl->qce; -+ struct qce_result_dump *result_buf = qce->dma.result_buf; - enum dma_data_direction dir_src, dir_dst; - u32 status; - int error; -@@ -53,6 +54,7 @@ static void qce_skcipher_done(void *data - if (error < 0) - dev_dbg(qce->dev, "skcipher operation error (%x)\n", status); - -+ memcpy(rctx->iv, result_buf->encr_cntr_iv, rctx->ivsize); - qce->async_req_done(tmpl->qce, error); - } - diff --git a/target/linux/ipq40xx/patches-4.19/046-crypto-qce-initialize-fallback-only-for-AES.patch b/target/linux/ipq40xx/patches-4.19/046-crypto-qce-initialize-fallback-only-for-AES.patch deleted file mode 100644 index e3adaf864e..0000000000 --- a/target/linux/ipq40xx/patches-4.19/046-crypto-qce-initialize-fallback-only-for-AES.patch +++ /dev/null @@ -1,54 +0,0 @@ -From f2a33ce18232919d3831d1c61a06b6067209282d Mon Sep 17 00:00:00 2001 -From: Eneas U de Queiroz -Date: Fri, 22 Nov 2019 09:34:29 -0300 -Subject: [PATCH] crypto: qce - initialize fallback only for AES - -Adjust cra_flags to add CRYPTO_NEED_FALLBACK only for AES ciphers, where -AES-192 is not handled by the qce hardware, and don't allocate & free -the fallback skcipher for anything other than AES. - -The rest of the code is unchanged, as the use of the fallback is already -restricted to AES. - -Signed-off-by: Eneas U de Queiroz - ---- a/drivers/crypto/qce/skcipher.c -+++ b/drivers/crypto/qce/skcipher.c -@@ -246,7 +246,15 @@ static int qce_skcipher_init(struct cryp - - memset(ctx, 0, sizeof(*ctx)); - crypto_skcipher_set_reqsize(tfm, sizeof(struct qce_cipher_reqctx)); -+ return 0; -+} -+ -+static int qce_skcipher_init_fallback(struct crypto_skcipher *tfm) -+{ -+ struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); -+ int ret; - -+ qce_skcipher_init(tfm); - ctx->fallback = crypto_alloc_skcipher(crypto_tfm_alg_name(&tfm->base), - 0, CRYPTO_ALG_ASYNC | - CRYPTO_ALG_NEED_FALLBACK); -@@ -375,14 +383,18 @@ static int qce_skcipher_register_one(con - - alg->base.cra_priority = 300; - alg->base.cra_flags = CRYPTO_ALG_ASYNC | -- CRYPTO_ALG_NEED_FALLBACK | - CRYPTO_ALG_KERN_DRIVER_ONLY; - alg->base.cra_ctxsize = sizeof(struct qce_cipher_ctx); - alg->base.cra_alignmask = 0; - alg->base.cra_module = THIS_MODULE; - -- alg->init = qce_skcipher_init; -- alg->exit = qce_skcipher_exit; -+ if (IS_AES(def->flags)) { -+ alg->base.cra_flags |= CRYPTO_ALG_NEED_FALLBACK; -+ alg->init = qce_skcipher_init_fallback; -+ alg->exit = qce_skcipher_exit; -+ } else { -+ alg->init = qce_skcipher_init; -+ } - - INIT_LIST_HEAD(&tmpl->entry); - tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_SKCIPHER; diff --git a/target/linux/ipq40xx/patches-4.19/047-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch b/target/linux/ipq40xx/patches-4.19/047-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch deleted file mode 100644 index aabc8fd622..0000000000 --- a/target/linux/ipq40xx/patches-4.19/047-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 686aa4db696270dadc5e8b2971769e1676251ff1 Mon Sep 17 00:00:00 2001 -From: Eneas U de Queiroz -Date: Fri, 31 Jan 2020 17:43:16 -0300 -Subject: [PATCH] crypto: qce - use cryptlen when adding extra sgl - -The qce crypto driver appends an extra entry to the dst sgl, to maintain -private state information. - -When the gcm driver sends requests to the ctr skcipher, it passes the -authentication tag after the actual crypto payload, but it must not be -touched. - -Commit 1336c2221bee ("crypto: qce - save a sg table slot for result -buf") limited the destination sgl to avoid overwriting the -authentication tag but it assumed the tag would be in a separate sgl -entry. - -This is not always the case, so it is better to limit the length of the -destination buffer to req->cryptlen before appending the result buf. - -Signed-off-by: Eneas U de Queiroz - ---- a/drivers/crypto/qce/dma.c -+++ b/drivers/crypto/qce/dma.c -@@ -56,9 +56,10 @@ void qce_dma_release(struct qce_dma_data - - struct scatterlist * - qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl, -- int max_ents) -+ unsigned int max_len) - { - struct scatterlist *sg = sgt->sgl, *sg_last = NULL; -+ unsigned int new_len; - - while (sg) { - if (!sg_page(sg)) -@@ -69,13 +70,13 @@ qce_sgtable_add(struct sg_table *sgt, st - if (!sg) - return ERR_PTR(-EINVAL); - -- while (new_sgl && sg && max_ents) { -- sg_set_page(sg, sg_page(new_sgl), new_sgl->length, -- new_sgl->offset); -+ while (new_sgl && sg && max_len) { -+ new_len = new_sgl->length > max_len ? max_len : new_sgl->length; -+ sg_set_page(sg, sg_page(new_sgl), new_len, new_sgl->offset); - sg_last = sg; - sg = sg_next(sg); - new_sgl = sg_next(new_sgl); -- max_ents--; -+ max_len -= new_len; - } - - return sg_last; ---- a/drivers/crypto/qce/dma.h -+++ b/drivers/crypto/qce/dma.h -@@ -51,6 +51,6 @@ void qce_dma_issue_pending(struct qce_dm - int qce_dma_terminate_all(struct qce_dma_data *dma); - struct scatterlist * - qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add, -- int max_ents); -+ unsigned int max_len); - - #endif /* _DMA_H_ */ ---- a/drivers/crypto/qce/skcipher.c -+++ b/drivers/crypto/qce/skcipher.c -@@ -105,13 +105,14 @@ qce_skcipher_async_req_handle(struct cry - - sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ); - -- sg = qce_sgtable_add(&rctx->dst_tbl, req->dst, rctx->dst_nents - 1); -+ sg = qce_sgtable_add(&rctx->dst_tbl, req->dst, req->cryptlen); - if (IS_ERR(sg)) { - ret = PTR_ERR(sg); - goto error_free; - } - -- sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg, 1); -+ sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg, -+ QCE_RESULT_BUF_SZ); - if (IS_ERR(sg)) { - ret = PTR_ERR(sg); - goto error_free; diff --git a/target/linux/ipq40xx/patches-4.19/048-crypto-qce-use-AES-fallback-for-small-requests.patch b/target/linux/ipq40xx/patches-4.19/048-crypto-qce-use-AES-fallback-for-small-requests.patch deleted file mode 100644 index 514fde7b63..0000000000 --- a/target/linux/ipq40xx/patches-4.19/048-crypto-qce-use-AES-fallback-for-small-requests.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 2d3b6fae7d1a2ad821769440daa91d7eec5c8250 Mon Sep 17 00:00:00 2001 -From: Eneas U de Queiroz -Date: Fri, 20 Dec 2019 09:41:44 -0300 -Subject: [PATCH] crypto: qce - use AES fallback for small requests - -Process small blocks using the fallback cipher, as a workaround for an -observed failure (DMA-related, apparently) when computing the GCM ghash -key. This brings a speed gain as well, since it avoids the latency of -using the hardware engine to process small blocks. - -Using software for all 16-byte requests would be enough to make GCM -work, but to increase performance, a larger threshold would be better. -Measuring the performance of supported ciphers with openssl speed, -software matches hardware at around 768-1024 bytes. - -Considering the 256-bit ciphers, software is 2-3 times faster than qce -at 256-bytes, 30% faster at 512, and about even at 768-bytes. With -128-bit keys, the break-even point would be around 1024-bytes. - -This adds the 'aes_sw_max_len' parameter, to set the largest request -length processed by the software fallback. Its default is being set to -512 bytes, a little lower than the break-even point, to balance the cost -in CPU usage. - -Signed-off-by: Eneas U de Queiroz - ---- a/drivers/crypto/Kconfig -+++ b/drivers/crypto/Kconfig -@@ -585,6 +585,29 @@ config CRYPTO_DEV_QCE - hardware. To compile this driver as a module, choose M here. The - module will be called qcrypto. - -+config CRYPTO_DEV_QCE_SW_MAX_LEN -+ int "Default maximum request size to use software for AES" -+ depends on CRYPTO_DEV_QCE && CRYPTO_DEV_QCE_SKCIPHER -+ default 512 -+ help -+ This sets the default maximum request size to perform AES requests -+ using software instead of the crypto engine. It can be changed by -+ setting the aes_sw_max_len parameter. -+ -+ Small blocks are processed faster in software than hardware. -+ Considering the 256-bit ciphers, software is 2-3 times faster than -+ qce at 256-bytes, 30% faster at 512, and about even at 768-bytes. -+ With 128-bit keys, the break-even point would be around 1024-bytes. -+ -+ The default is set a little lower, to 512 bytes, to balance the -+ cost in CPU usage. The minimum recommended setting is 16-bytes -+ (1 AES block), since AES-GCM will fail if you set it lower. -+ Setting this to zero will send all requests to the hardware. -+ -+ Note that 192-bit keys are not supported by the hardware and are -+ always processed by the software fallback, and all DES requests -+ are done by the hardware. -+ - config CRYPTO_DEV_QCOM_RNG - tristate "Qualcomm Random Number Generator Driver" - depends on ARCH_QCOM || COMPILE_TEST ---- a/drivers/crypto/qce/skcipher.c -+++ b/drivers/crypto/qce/skcipher.c -@@ -13,6 +13,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -20,6 +21,13 @@ - - #include "cipher.h" - -+static unsigned int aes_sw_max_len = CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN; -+module_param(aes_sw_max_len, uint, 0644); -+MODULE_PARM_DESC(aes_sw_max_len, -+ "Only use hardware for AES requests larger than this " -+ "[0=always use hardware; anything <16 breaks AES-GCM; default=" -+ __stringify(CONFIG_CRYPTO_DEV_QCE_SOFT_THRESHOLD)"]"); -+ - static LIST_HEAD(skcipher_algs); - - static void qce_skcipher_done(void *data) -@@ -170,15 +178,7 @@ static int qce_skcipher_setkey(struct cr - if (!key || !keylen) - return -EINVAL; - -- if (IS_AES(flags)) { -- switch (IS_XTS(flags) ? keylen >> 1 : keylen) { -- case AES_KEYSIZE_128: -- case AES_KEYSIZE_256: -- break; -- default: -- goto fallback; -- } -- } else if (IS_DES(flags)) { -+ if (IS_DES(flags)) { - u32 tmp[DES_EXPKEY_WORDS]; - - ret = des_ekey(tmp, key); -@@ -189,8 +189,8 @@ static int qce_skcipher_setkey(struct cr - - ctx->enc_keylen = keylen; - memcpy(ctx->enc_key, key, keylen); -- return 0; --fallback: -+ if (!IS_AES(flags)) -+ return 0; - ret = crypto_skcipher_setkey(ctx->fallback, key, keylen); - if (!ret) - ctx->enc_keylen = keylen; -@@ -213,8 +213,9 @@ static int qce_skcipher_crypt(struct skc - rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT; - keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen; - -- if (IS_AES(rctx->flags) && keylen != AES_KEYSIZE_128 && -- keylen != AES_KEYSIZE_256) { -+ if (IS_AES(rctx->flags) && -+ ((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) || -+ req->cryptlen <= aes_sw_max_len)) { - SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); - - skcipher_request_set_tfm(subreq, ctx->fallback); diff --git a/target/linux/ipq40xx/patches-4.19/049-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch b/target/linux/ipq40xx/patches-4.19/049-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch deleted file mode 100644 index 00dc3791ab..0000000000 --- a/target/linux/ipq40xx/patches-4.19/049-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch +++ /dev/null @@ -1,53 +0,0 @@ -From bbf2b1cf22dc98f3df33b6666df046dfb9564d91 Mon Sep 17 00:00:00 2001 -From: Eneas U de Queiroz -Date: Wed, 5 Feb 2020 13:42:25 -0300 -Subject: [PATCH] crypto: qce - handle AES-XTS cases that qce fails - -QCE hangs when presented with an AES-XTS request whose length is larger -than QCE_SECTOR_SIZE (512-bytes), and is not a multiple of it. Let the -fallback cipher handle them. - -Signed-off-by: Eneas U de Queiroz - ---- a/drivers/crypto/qce/common.c -+++ b/drivers/crypto/qce/common.c -@@ -23,8 +23,6 @@ - #include "regs-v5.h" - #include "sha.h" - --#define QCE_SECTOR_SIZE 512 -- - static inline u32 qce_read(struct qce_device *qce, u32 offset) - { - return readl(qce->base + offset); ---- a/drivers/crypto/qce/common.h -+++ b/drivers/crypto/qce/common.h -@@ -20,6 +20,9 @@ - #include - #include - -+/* xts du size */ -+#define QCE_SECTOR_SIZE 512 -+ - /* key size in bytes */ - #define QCE_SHA_HMAC_KEY_SIZE 64 - #define QCE_MAX_CIPHER_KEY_SIZE AES_KEYSIZE_256 ---- a/drivers/crypto/qce/skcipher.c -+++ b/drivers/crypto/qce/skcipher.c -@@ -213,9 +213,14 @@ static int qce_skcipher_crypt(struct skc - rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT; - keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen; - -+ /* qce is hanging when AES-XTS request len > QCE_SECTOR_SIZE and -+ * is not a multiple of it; pass such requests to the fallback -+ */ - if (IS_AES(rctx->flags) && -- ((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) || -- req->cryptlen <= aes_sw_max_len)) { -+ (((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) || -+ req->cryptlen <= aes_sw_max_len) || -+ (IS_XTS(rctx->flags) && req->cryptlen > QCE_SECTOR_SIZE && -+ req->cryptlen % QCE_SECTOR_SIZE))) { - SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); - - skcipher_request_set_tfm(subreq, ctx->fallback); diff --git a/target/linux/ipq40xx/patches-4.19/051-crypto-qce-allow-building-only-hashes-ciphers.patch b/target/linux/ipq40xx/patches-4.19/051-crypto-qce-allow-building-only-hashes-ciphers.patch deleted file mode 100644 index 11f711940d..0000000000 --- a/target/linux/ipq40xx/patches-4.19/051-crypto-qce-allow-building-only-hashes-ciphers.patch +++ /dev/null @@ -1,406 +0,0 @@ -From 62134842498927a0fcc19798a615340a7a6a9e62 Mon Sep 17 00:00:00 2001 -From: Eneas U de Queiroz -Date: Mon, 28 Oct 2019 15:17:19 -0300 -Subject: [PATCH] crypto: qce - allow building only hashes/ciphers - -Signed-off-by: Eneas U de Queiroz - ---- a/drivers/crypto/Kconfig -+++ b/drivers/crypto/Kconfig -@@ -573,6 +573,14 @@ config CRYPTO_DEV_QCE - tristate "Qualcomm crypto engine accelerator" - depends on ARCH_QCOM || COMPILE_TEST - depends on HAS_IOMEM -+ help -+ This driver supports Qualcomm crypto engine accelerator -+ hardware. To compile this driver as a module, choose M here. The -+ module will be called qcrypto. -+ -+config CRYPTO_DEV_QCE_SKCIPHER -+ bool -+ depends on CRYPTO_DEV_QCE - select CRYPTO_AES - select CRYPTO_DES - select CRYPTO_ECB -@@ -580,10 +588,57 @@ config CRYPTO_DEV_QCE - select CRYPTO_XTS - select CRYPTO_CTR - select CRYPTO_BLKCIPHER -+ -+config CRYPTO_DEV_QCE_SHA -+ bool -+ depends on CRYPTO_DEV_QCE -+ -+choice -+ prompt "Algorithms enabled for QCE acceleration" -+ default CRYPTO_DEV_QCE_ENABLE_ALL -+ depends on CRYPTO_DEV_QCE - help -- This driver supports Qualcomm crypto engine accelerator -- hardware. To compile this driver as a module, choose M here. The -- module will be called qcrypto. -+ This option allows to choose whether to build support for all algorihtms -+ (default), hashes-only, or skciphers-only. -+ -+ The QCE engine does not appear to scale as well as the CPU to handle -+ multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the -+ QCE handles only 2 requests in parallel. -+ -+ Ipsec throughput seems to improve when disabling either family of -+ algorithms, sharing the load with the CPU. Enabling skciphers-only -+ appears to work best. -+ -+ config CRYPTO_DEV_QCE_ENABLE_ALL -+ bool "All supported algorithms" -+ select CRYPTO_DEV_QCE_SKCIPHER -+ select CRYPTO_DEV_QCE_SHA -+ help -+ Enable all supported algorithms: -+ - AES (CBC, CTR, ECB, XTS) -+ - 3DES (CBC, ECB) -+ - DES (CBC, ECB) -+ - SHA1, HMAC-SHA1 -+ - SHA256, HMAC-SHA256 -+ -+ config CRYPTO_DEV_QCE_ENABLE_SKCIPHER -+ bool "Symmetric-key ciphers only" -+ select CRYPTO_DEV_QCE_SKCIPHER -+ help -+ Enable symmetric-key ciphers only: -+ - AES (CBC, CTR, ECB, XTS) -+ - 3DES (ECB, CBC) -+ - DES (ECB, CBC) -+ -+ config CRYPTO_DEV_QCE_ENABLE_SHA -+ bool "Hash/HMAC only" -+ select CRYPTO_DEV_QCE_SHA -+ help -+ Enable hashes/HMAC algorithms only: -+ - SHA1, HMAC-SHA1 -+ - SHA256, HMAC-SHA256 -+ -+endchoice - - config CRYPTO_DEV_QCE_SW_MAX_LEN - int "Default maximum request size to use software for AES" ---- a/drivers/crypto/qce/Makefile -+++ b/drivers/crypto/qce/Makefile -@@ -2,6 +2,7 @@ - obj-$(CONFIG_CRYPTO_DEV_QCE) += qcrypto.o - qcrypto-objs := core.o \ - common.o \ -- dma.o \ -- sha.o \ -- skcipher.o -+ dma.o -+ -+qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SHA) += sha.o -+qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SKCIPHER) += skcipher.o ---- a/drivers/crypto/qce/common.c -+++ b/drivers/crypto/qce/common.c -@@ -51,52 +51,56 @@ qce_clear_array(struct qce_device *qce, - qce_write(qce, offset + i * sizeof(u32), 0); - } - --static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size) -+static u32 qce_config_reg(struct qce_device *qce, int little) - { -- u32 cfg = 0; -+ u32 beats = (qce->burst_size >> 3) - 1; -+ u32 pipe_pair = qce->pipe_pair_id; -+ u32 config; - -- if (IS_AES(flags)) { -- if (aes_key_size == AES_KEYSIZE_128) -- cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT; -- else if (aes_key_size == AES_KEYSIZE_256) -- cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT; -- } -+ config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK; -+ config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) | -+ BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT); -+ config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK; -+ config &= ~HIGH_SPD_EN_N_SHIFT; - -- if (IS_AES(flags)) -- cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT; -- else if (IS_DES(flags) || IS_3DES(flags)) -- cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT; -+ if (little) -+ config |= BIT(LITTLE_ENDIAN_MODE_SHIFT); - -- if (IS_DES(flags)) -- cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT; -+ return config; -+} - -- if (IS_3DES(flags)) -- cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT; -+void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len) -+{ -+ __be32 *d = dst; -+ const u8 *s = src; -+ unsigned int n; - -- switch (flags & QCE_MODE_MASK) { -- case QCE_MODE_ECB: -- cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT; -- break; -- case QCE_MODE_CBC: -- cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT; -- break; -- case QCE_MODE_CTR: -- cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT; -- break; -- case QCE_MODE_XTS: -- cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT; -- break; -- case QCE_MODE_CCM: -- cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT; -- cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT; -- break; -- default: -- return ~0; -+ n = len / sizeof(u32); -+ for (; n > 0; n--) { -+ *d = cpu_to_be32p((const __u32 *) s); -+ s += sizeof(__u32); -+ d++; - } -+} - -- return cfg; -+static void qce_setup_config(struct qce_device *qce) -+{ -+ u32 config; -+ -+ /* get big endianness */ -+ config = qce_config_reg(qce, 0); -+ -+ /* clear status */ -+ qce_write(qce, REG_STATUS, 0); -+ qce_write(qce, REG_CONFIG, config); -+} -+ -+static inline void qce_crypto_go(struct qce_device *qce) -+{ -+ qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); - } - -+#ifdef CONFIG_CRYPTO_DEV_QCE_SHA - static u32 qce_auth_cfg(unsigned long flags, u32 key_size) - { - u32 cfg = 0; -@@ -143,88 +147,6 @@ static u32 qce_auth_cfg(unsigned long fl - return cfg; - } - --static u32 qce_config_reg(struct qce_device *qce, int little) --{ -- u32 beats = (qce->burst_size >> 3) - 1; -- u32 pipe_pair = qce->pipe_pair_id; -- u32 config; -- -- config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK; -- config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) | -- BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT); -- config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK; -- config &= ~HIGH_SPD_EN_N_SHIFT; -- -- if (little) -- config |= BIT(LITTLE_ENDIAN_MODE_SHIFT); -- -- return config; --} -- --void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len) --{ -- __be32 *d = dst; -- const u8 *s = src; -- unsigned int n; -- -- n = len / sizeof(u32); -- for (; n > 0; n--) { -- *d = cpu_to_be32p((const __u32 *) s); -- s += sizeof(__u32); -- d++; -- } --} -- --static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize) --{ -- u8 swap[QCE_AES_IV_LENGTH]; -- u32 i, j; -- -- if (ivsize > QCE_AES_IV_LENGTH) -- return; -- -- memset(swap, 0, QCE_AES_IV_LENGTH); -- -- for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1; -- i < QCE_AES_IV_LENGTH; i++, j--) -- swap[i] = src[j]; -- -- qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH); --} -- --static void qce_xtskey(struct qce_device *qce, const u8 *enckey, -- unsigned int enckeylen, unsigned int cryptlen) --{ -- u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0}; -- unsigned int xtsklen = enckeylen / (2 * sizeof(u32)); -- unsigned int xtsdusize; -- -- qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2, -- enckeylen / 2); -- qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen); -- -- /* xts du size 512B */ -- xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen); -- qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize); --} -- --static void qce_setup_config(struct qce_device *qce) --{ -- u32 config; -- -- /* get big endianness */ -- config = qce_config_reg(qce, 0); -- -- /* clear status */ -- qce_write(qce, REG_STATUS, 0); -- qce_write(qce, REG_CONFIG, config); --} -- --static inline void qce_crypto_go(struct qce_device *qce) --{ -- qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); --} -- - static int qce_setup_regs_ahash(struct crypto_async_request *async_req, - u32 totallen, u32 offset) - { -@@ -309,6 +231,87 @@ go_proc: - - return 0; - } -+#endif -+ -+#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER -+static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size) -+{ -+ u32 cfg = 0; -+ -+ if (IS_AES(flags)) { -+ if (aes_key_size == AES_KEYSIZE_128) -+ cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT; -+ else if (aes_key_size == AES_KEYSIZE_256) -+ cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT; -+ } -+ -+ if (IS_AES(flags)) -+ cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT; -+ else if (IS_DES(flags) || IS_3DES(flags)) -+ cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT; -+ -+ if (IS_DES(flags)) -+ cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT; -+ -+ if (IS_3DES(flags)) -+ cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT; -+ -+ switch (flags & QCE_MODE_MASK) { -+ case QCE_MODE_ECB: -+ cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT; -+ break; -+ case QCE_MODE_CBC: -+ cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT; -+ break; -+ case QCE_MODE_CTR: -+ cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT; -+ break; -+ case QCE_MODE_XTS: -+ cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT; -+ break; -+ case QCE_MODE_CCM: -+ cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT; -+ cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT; -+ break; -+ default: -+ return ~0; -+ } -+ -+ return cfg; -+} -+ -+static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize) -+{ -+ u8 swap[QCE_AES_IV_LENGTH]; -+ u32 i, j; -+ -+ if (ivsize > QCE_AES_IV_LENGTH) -+ return; -+ -+ memset(swap, 0, QCE_AES_IV_LENGTH); -+ -+ for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1; -+ i < QCE_AES_IV_LENGTH; i++, j--) -+ swap[i] = src[j]; -+ -+ qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH); -+} -+ -+static void qce_xtskey(struct qce_device *qce, const u8 *enckey, -+ unsigned int enckeylen, unsigned int cryptlen) -+{ -+ u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0}; -+ unsigned int xtsklen = enckeylen / (2 * sizeof(u32)); -+ unsigned int xtsdusize; -+ -+ qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2, -+ enckeylen / 2); -+ qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen); -+ -+ /* xts du size 512B */ -+ xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen); -+ qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize); -+} - - static int qce_setup_regs_skcipher(struct crypto_async_request *async_req, - u32 totallen, u32 offset) -@@ -390,15 +393,20 @@ static int qce_setup_regs_skcipher(struc - - return 0; - } -+#endif - - int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen, - u32 offset) - { - switch (type) { -+#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER - case CRYPTO_ALG_TYPE_SKCIPHER: - return qce_setup_regs_skcipher(async_req, totallen, offset); -+#endif -+#ifdef CONFIG_CRYPTO_DEV_QCE_SHA - case CRYPTO_ALG_TYPE_AHASH: - return qce_setup_regs_ahash(async_req, totallen, offset); -+#endif - default: - return -EINVAL; - } ---- a/drivers/crypto/qce/core.c -+++ b/drivers/crypto/qce/core.c -@@ -30,8 +30,12 @@ - #define QCE_QUEUE_LENGTH 1 - - static const struct qce_algo_ops *qce_ops[] = { -+#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER - &skcipher_ops, -+#endif -+#ifdef CONFIG_CRYPTO_DEV_QCE_SHA - &ahash_ops, -+#endif - }; - - static void qce_unregister_algs(struct qce_device *qce) diff --git a/target/linux/ipq40xx/patches-4.19/070-v4.20-soc-qcom-spm-add-SCM-probe-dependency.patch b/target/linux/ipq40xx/patches-4.19/070-v4.20-soc-qcom-spm-add-SCM-probe-dependency.patch deleted file mode 100644 index d0b520f389..0000000000 --- a/target/linux/ipq40xx/patches-4.19/070-v4.20-soc-qcom-spm-add-SCM-probe-dependency.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 61a3bd10082b0e861b4e1bc451a92e20181a52f5 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Mon, 23 Jul 2018 16:17:35 +0200 -Subject: [PATCH] soc: qcom: spm: add SCM probe dependency - -Check for SCM availability before attempting to use SPM. SPM probe will -fail otherwise. - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin -Signed-off-by: Andy Gross ---- - drivers/soc/qcom/spm.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/soc/qcom/spm.c -+++ b/drivers/soc/qcom/spm.c -@@ -219,6 +219,9 @@ static int __init qcom_cpuidle_init(stru - cpumask_t mask; - bool use_scm_power_down = false; - -+ if (!qcom_scm_is_available()) -+ return -EPROBE_DEFER; -+ - for (i = 0; ; i++) { - state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i); - if (!state_node) diff --git a/target/linux/ipq40xx/patches-4.19/071-01-v4.20-ARM-dts-qcom-ipq4019-use-v2-of-the-kpss-bringup-mech.patch b/target/linux/ipq40xx/patches-4.19/071-01-v4.20-ARM-dts-qcom-ipq4019-use-v2-of-the-kpss-bringup-mech.patch deleted file mode 100644 index b1d69ca0ee..0000000000 --- a/target/linux/ipq40xx/patches-4.19/071-01-v4.20-ARM-dts-qcom-ipq4019-use-v2-of-the-kpss-bringup-mech.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 233c77d4f1d12e4337fba1146d5197f4c0f9107d Mon Sep 17 00:00:00 2001 -From: Matthew McClintock -Date: Wed, 25 Jul 2018 10:37:45 +0200 -Subject: [PATCH] ARM: dts: qcom: ipq4019: use v2 of the kpss bringup mechanism - -v1 was the incorrect choice here and sometimes the board -would not come up properly. - -Signed-off-by: Matthew McClintock -Signed-off-by: Christian Lamparter -Signed-off-by: John Crispin -Signed-off-by: Andy Gross ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +++++++++++++++++-------- - 1 file changed, 17 insertions(+), 8 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -52,7 +52,8 @@ - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; -- enable-method = "qcom,kpss-acc-v1"; -+ enable-method = "qcom,kpss-acc-v2"; -+ next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - reg = <0x0>; -@@ -71,7 +72,8 @@ - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; -- enable-method = "qcom,kpss-acc-v1"; -+ enable-method = "qcom,kpss-acc-v2"; -+ next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - reg = <0x1>; -@@ -90,7 +92,8 @@ - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; -- enable-method = "qcom,kpss-acc-v1"; -+ enable-method = "qcom,kpss-acc-v2"; -+ next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - reg = <0x2>; -@@ -109,7 +112,8 @@ - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; -- enable-method = "qcom,kpss-acc-v1"; -+ enable-method = "qcom,kpss-acc-v2"; -+ next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - reg = <0x3>; -@@ -124,6 +128,11 @@ - >; - clock-latency = <256000>; - }; -+ -+ L2: l2-cache { -+ compatible = "cache"; -+ cache-level = <2>; -+ }; - }; - - pmu { -@@ -292,22 +301,22 @@ - }; - - acc0: clock-controller@b088000 { -- compatible = "qcom,kpss-acc-v1"; -+ compatible = "qcom,kpss-acc-v2"; - reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; - }; - - acc1: clock-controller@b098000 { -- compatible = "qcom,kpss-acc-v1"; -+ compatible = "qcom,kpss-acc-v2"; - reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; - }; - - acc2: clock-controller@b0a8000 { -- compatible = "qcom,kpss-acc-v1"; -+ compatible = "qcom,kpss-acc-v2"; - reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; - }; - - acc3: clock-controller@b0b8000 { -- compatible = "qcom,kpss-acc-v1"; -+ compatible = "qcom,kpss-acc-v2"; - reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; - }; - diff --git a/target/linux/ipq40xx/patches-4.19/071-02-ipq40xx-Fix-booting-secondary-cores.patch b/target/linux/ipq40xx/patches-4.19/071-02-ipq40xx-Fix-booting-secondary-cores.patch deleted file mode 100644 index d37a8cb6ba..0000000000 --- a/target/linux/ipq40xx/patches-4.19/071-02-ipq40xx-Fix-booting-secondary-cores.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 8a4540321e8bcf7a5b485c332a2e78f3501c78ed Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 29 Nov 2018 22:29:36 +0100 -Subject: [PATCH] ipq40xx: Fix booting secondary cores - -Add the second part of old 071-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch -We dont modify the patch itself as its upstream and this change is not. - -Originally added by Mantas Pucka Mantas Pucka - -Signed-off-by: Robert Marko ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -132,6 +132,7 @@ - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; -+ qcom,saw = <&saw_l2>; - }; - }; - -@@ -344,6 +345,12 @@ - regulator; - }; - -+ saw_l2: regulator@b012000 { -+ compatible = "qcom,saw2"; -+ reg = <0xb012000 0x1000>; -+ regulator; -+ }; -+ - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; diff --git a/target/linux/ipq40xx/patches-4.19/072-v4.20-ARM-dts-qcom-ipq4019-add-cpu-operating-points-for-cp.patch b/target/linux/ipq40xx/patches-4.19/072-v4.20-ARM-dts-qcom-ipq4019-add-cpu-operating-points-for-cp.patch deleted file mode 100644 index 991b366eda..0000000000 --- a/target/linux/ipq40xx/patches-4.19/072-v4.20-ARM-dts-qcom-ipq4019-add-cpu-operating-points-for-cp.patch +++ /dev/null @@ -1,114 +0,0 @@ -From bcb9ab4c2917e92114d2f4c2b1da97cdf15b471b Mon Sep 17 00:00:00 2001 -From: Matthew McClintock -Date: Wed, 25 Jul 2018 10:37:46 +0200 -Subject: [PATCH] ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq - support - -This adds some operating points for cpu frequeny scaling - -Signed-off-by: Matthew McClintock -Signed-off-by: John Crispin -Signed-off-by: Andy Gross ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 58 ++++++++++++++--------------- - 1 file changed, 30 insertions(+), 28 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -59,14 +59,8 @@ - reg = <0x0>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; -- operating-points = < -- /* kHz uV (fixed) */ -- 48000 1100000 -- 200000 1100000 -- 500000 1100000 -- 716000 1100000 -- >; - clock-latency = <256000>; -+ operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { -@@ -79,14 +73,8 @@ - reg = <0x1>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; -- operating-points = < -- /* kHz uV (fixed) */ -- 48000 1100000 -- 200000 1100000 -- 500000 1100000 -- 666000 1100000 -- >; - clock-latency = <256000>; -+ operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@2 { -@@ -99,14 +87,8 @@ - reg = <0x2>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; -- operating-points = < -- /* kHz uV (fixed) */ -- 48000 1100000 -- 200000 1100000 -- 500000 1100000 -- 666000 1100000 -- >; - clock-latency = <256000>; -+ operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@3 { -@@ -119,14 +101,8 @@ - reg = <0x3>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; -- operating-points = < -- /* kHz uV (fixed) */ -- 48000 1100000 -- 200000 1100000 -- 500000 1100000 -- 666000 1100000 -- >; - clock-latency = <256000>; -+ operating-points-v2 = <&cpu0_opp_table>; - }; - - L2: l2-cache { -@@ -136,6 +112,32 @@ - }; - }; - -+ cpu0_opp_table: opp_table0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-48000000 { -+ opp-hz = /bits/ 64 <48000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <256000>; -+ }; -+ opp-200000000 { -+ opp-hz = /bits/ 64 <200000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <256000>; -+ }; -+ opp-500000000 { -+ opp-hz = /bits/ 64 <500000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <256000>; -+ }; -+ opp-716000000 { -+ opp-hz = /bits/ 64 <716000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <256000>; -+ }; -+ }; -+ - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = -Date: Sun, 22 Jul 2018 12:07:57 +0200 -Subject: [PATCH 8/8] ARM: qcom: Add IPQ4019 SoC support - -Add support for the Qualcomm Atheros IPQ4019 SoC. - -Signed-off-by: Christian Lamparter -Signed-off-by: John Crispin ---- - arch/arm/Makefile | 1 + - arch/arm/mach-qcom/Kconfig | 5 +++++ - 2 files changed, 6 insertions(+) - ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -150,6 +150,7 @@ textofs-$(CONFIG_ARCH_MSM8X60) := 0x0020 - textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 - textofs-$(CONFIG_ARCH_MESON) := 0x00208000 - textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 -+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000 - - # Machine directory name. This list is sorted alphanumerically - # by CONFIG_* macro name. ---- a/arch/arm/mach-qcom/Kconfig -+++ b/arch/arm/mach-qcom/Kconfig -@@ -27,4 +27,9 @@ config ARCH_MDM9615 - bool "Enable support for MDM9615" - select CLKSRC_QCOM - -+config ARCH_IPQ40XX -+ bool "Enable support for IPQ40XX" -+ select CLKSRC_QCOM -+ select HAVE_ARM_ARCH_TIMER -+ - endif diff --git a/target/linux/ipq40xx/patches-4.19/075-dt-bindings-phy-qcom-ipq4019-usb-add-binding-documen.patch b/target/linux/ipq40xx/patches-4.19/075-dt-bindings-phy-qcom-ipq4019-usb-add-binding-documen.patch deleted file mode 100644 index e7407bcbab..0000000000 --- a/target/linux/ipq40xx/patches-4.19/075-dt-bindings-phy-qcom-ipq4019-usb-add-binding-documen.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 5f01733dc755dfadfa51b7b3c6c160e632fc6002 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 24 Jul 2018 15:09:36 +0200 -Subject: [PATCH 1/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document - -This patch adds the binding documentation for the HS/SS USB PHY found -inside Qualcom Dakota SoCs. - -Signed-off-by: John Crispin ---- - .../bindings/phy/phy-qcom-ipq4019-usb.txt | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt -@@ -0,0 +1,21 @@ -+Qualcom Dakota HS/SS USB PHY -+ -+Required properties: -+ - compatible: "qcom,usb-ss-ipq4019-phy", -+ "qcom,usb-hs-ipq4019-phy" -+ - reg: offset and length of the registers -+ - #phy-cells: should be 0 -+ - resets: the reset controllers as listed below -+ - reset-names: the names of the reset controllers -+ "por_rst" - the POR reset line for SS and HS phys -+ "srif_rst" - the SRIF reset line for HS phys -+Example: -+ -+hsphy@a8000 { -+ compatible = "qcom,usb-hs-ipq4019-phy"; -+ phy-cells = <0>; -+ reg = <0xa8000 0x40>; -+ resets = <&gcc USB2_HSPHY_POR_ARES>, -+ <&gcc USB2_HSPHY_S_ARES>; -+ reset-names = "por_rst", "srif_rst"; -+}; diff --git a/target/linux/ipq40xx/patches-4.19/076-phy-qcom-ipq4019-usb-add-driver-for-QCOM-IPQ4019.patch b/target/linux/ipq40xx/patches-4.19/076-phy-qcom-ipq4019-usb-add-driver-for-QCOM-IPQ4019.patch deleted file mode 100644 index e7e7a1f89a..0000000000 --- a/target/linux/ipq40xx/patches-4.19/076-phy-qcom-ipq4019-usb-add-driver-for-QCOM-IPQ4019.patch +++ /dev/null @@ -1,234 +0,0 @@ -From 633f0e08498aebfdb932bd71319b4cb136709499 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 24 Jul 2018 14:45:49 +0200 -Subject: [PATCH 2/3] phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019 - -Add a driver to setup the USB phy on Qualcom Dakota SoCs. -The driver sets up HS and SS phys. In case of HS some magic values need to -be written to magic offsets. These were taken from the SDK driver. - -Signed-off-by: John Crispin ---- - drivers/phy/qualcomm/Kconfig | 7 ++ - drivers/phy/qualcomm/Makefile | 1 + - drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 188 ++++++++++++++++++++++++++++ - 3 files changed, 196 insertions(+) - create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c - ---- a/drivers/phy/qualcomm/Kconfig -+++ b/drivers/phy/qualcomm/Kconfig -@@ -17,6 +17,13 @@ config PHY_QCOM_APQ8064_SATA - depends on OF - select GENERIC_PHY - -+config PHY_QCOM_IPQ4019_USB -+ tristate "Qualcomm IPQ4019 USB PHY module" -+ depends on OF && ARCH_QCOM -+ select GENERIC_PHY -+ help -+ Support for the USB PHY on QCOM IPQ4019/Dakota chipsets. -+ - config PHY_QCOM_IPQ806X_SATA - tristate "Qualcomm IPQ806x SATA SerDes/PHY driver" - depends on ARCH_QCOM ---- /dev/null -+++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c -@@ -0,0 +1,188 @@ -+/* -+ * Copyright (C) 2018 John Crispin -+ * -+ * Based on code from -+ * Allwinner Technology Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * Magic registers copied from the SDK driver code -+ */ -+#define PHY_CTRL0_ADDR 0x000 -+#define PHY_CTRL1_ADDR 0x004 -+#define PHY_CTRL2_ADDR 0x008 -+#define PHY_CTRL3_ADDR 0x00C -+#define PHY_CTRL4_ADDR 0x010 -+#define PHY_MISC_ADDR 0x024 -+#define PHY_IPG_ADDR 0x030 -+ -+#define PHY_CTRL0_VAL 0xA4600015 -+#define PHY_CTRL1_VAL 0x09500000 -+#define PHY_CTRL2_VAL 0x00058180 -+#define PHY_CTRL3_VAL 0x6DB6DCD6 -+#define PHY_CTRL4_VAL 0x836DB6DB -+#define PHY_MISC_VAL 0x3803FB0C -+#define PHY_IPG_VAL 0x47323232 -+ -+struct ipq4019_usb_phy { -+ struct device *dev; -+ struct phy *phy; -+ void __iomem *base; -+ struct reset_control *por_rst; -+ struct reset_control *srif_rst; -+}; -+ -+static int ipq4019_ss_phy_power_off(struct phy *_phy) -+{ -+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); -+ -+ reset_control_assert(phy->por_rst); -+ msleep(10); -+ -+ return 0; -+} -+ -+static int ipq4019_ss_phy_power_on(struct phy *_phy) -+{ -+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); -+ -+ ipq4019_ss_phy_power_off(_phy); -+ -+ reset_control_deassert(phy->por_rst); -+ -+ return 0; -+} -+ -+static struct phy_ops ipq4019_usb_ss_phy_ops = { -+ .power_on = ipq4019_ss_phy_power_on, -+ .power_off = ipq4019_ss_phy_power_off, -+}; -+ -+static int ipq4019_hs_phy_power_off(struct phy *_phy) -+{ -+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); -+ -+ reset_control_assert(phy->por_rst); -+ msleep(10); -+ -+ reset_control_assert(phy->srif_rst); -+ msleep(10); -+ -+ return 0; -+} -+ -+static int ipq4019_hs_phy_power_on(struct phy *_phy) -+{ -+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); -+ -+ ipq4019_hs_phy_power_off(_phy); -+ -+ reset_control_deassert(phy->srif_rst); -+ msleep(10); -+ -+ writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR); -+ writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR); -+ writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR); -+ writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR); -+ writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR); -+ writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR); -+ writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR); -+ msleep(10); -+ -+ reset_control_deassert(phy->por_rst); -+ -+ return 0; -+} -+ -+static struct phy_ops ipq4019_usb_hs_phy_ops = { -+ .power_on = ipq4019_hs_phy_power_on, -+ .power_off = ipq4019_hs_phy_power_off, -+}; -+ -+static const struct of_device_id ipq4019_usb_phy_of_match[] = { -+ { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hs_phy_ops}, -+ { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ss_phy_ops}, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, ipq4019_usb_phy_of_match); -+ -+static int ipq4019_usb_phy_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct resource *res; -+ struct phy_provider *phy_provider; -+ struct ipq4019_usb_phy *phy; -+ const struct of_device_id *match; -+ -+ match = of_match_device(ipq4019_usb_phy_of_match, &pdev->dev); -+ if (!match) -+ return -ENODEV; -+ -+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); -+ if (!phy) -+ return -ENOMEM; -+ -+ phy->dev = &pdev->dev; -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ phy->base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(phy->base)) { -+ dev_err(dev, "failed to remap register memory\n"); -+ return PTR_ERR(phy->base); -+ } -+ -+ phy->por_rst = devm_reset_control_get(phy->dev, "por_rst"); -+ if (IS_ERR(phy->por_rst)) { -+ if (PTR_ERR(phy->por_rst) != -EPROBE_DEFER) -+ dev_err(dev, "POR reset is missing\n"); -+ return PTR_ERR(phy->por_rst); -+ } -+ -+ phy->srif_rst = devm_reset_control_get_optional(phy->dev, "srif_rst"); -+ if (IS_ERR(phy->srif_rst)) -+ return PTR_ERR(phy->srif_rst); -+ -+ phy->phy = devm_phy_create(dev, NULL, match->data); -+ if (IS_ERR(phy->phy)) { -+ dev_err(dev, "failed to create PHY\n"); -+ return PTR_ERR(phy->phy); -+ } -+ phy_set_drvdata(phy->phy, phy); -+ -+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static struct platform_driver ipq4019_usb_phy_driver = { -+ .probe = ipq4019_usb_phy_probe, -+ .driver = { -+ .of_match_table = ipq4019_usb_phy_of_match, -+ .name = "ipq4019-usb-phy", -+ } -+}; -+module_platform_driver(ipq4019_usb_phy_driver); -+ -+MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver"); -+MODULE_AUTHOR("John Crispin "); -+MODULE_LICENSE("GPL v2"); ---- a/drivers/phy/qualcomm/Makefile -+++ b/drivers/phy/qualcomm/Makefile -@@ -1,6 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0 - obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o - obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o -+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o - obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o - obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o - obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o diff --git a/target/linux/ipq40xx/patches-4.19/077-qcom-ipq4019-add-USB-devicetree-nodes.patch b/target/linux/ipq40xx/patches-4.19/077-qcom-ipq4019-add-USB-devicetree-nodes.patch deleted file mode 100644 index 30a0678fd8..0000000000 --- a/target/linux/ipq40xx/patches-4.19/077-qcom-ipq4019-add-USB-devicetree-nodes.patch +++ /dev/null @@ -1,123 +0,0 @@ -From 1fc7d5523e21ed140fed43c4dde011a3b6d9ba08 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 24 Jul 2018 14:47:55 +0200 -Subject: [PATCH 3/3] qcom: ipq4019: add USB devicetree nodes - -This patch makes USB work on the Dakota EVB. - -Signed-off-by: John Crispin ---- - arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++ - arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++ - 2 files changed, 94 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -@@ -109,5 +109,25 @@ - wifi@a800000 { - status = "ok"; - }; -+ -+ usb3_ss_phy: ssphy@9a000 { -+ status = "okay"; -+ }; -+ -+ usb3_hs_phy: hsphy@a6000 { -+ status = "okay"; -+ }; -+ -+ usb3: usb3@8af8800 { -+ status = "okay"; -+ }; -+ -+ usb2_hs_phy: hsphy@a8000 { -+ status = "okay"; -+ }; -+ -+ usb2: usb2@60f8800 { -+ status = "okay"; -+ }; - }; - }; ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -568,5 +568,79 @@ - "legacy"; - status = "disabled"; - }; -+ -+ usb3_ss_phy: ssphy@9a000 { -+ compatible = "qcom,usb-ss-ipq4019-phy"; -+ #phy-cells = <0>; -+ reg = <0x9a000 0x800>; -+ reg-names = "phy_base"; -+ resets = <&gcc USB3_UNIPHY_PHY_ARES>; -+ reset-names = "por_rst"; -+ status = "disabled"; -+ }; -+ -+ usb3_hs_phy: hsphy@a6000 { -+ compatible = "qcom,usb-hs-ipq4019-phy"; -+ #phy-cells = <0>; -+ reg = <0xa6000 0x40>; -+ reg-names = "phy_base"; -+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; -+ reset-names = "por_rst", "srif_rst"; -+ status = "disabled"; -+ }; -+ -+ usb3@8af8800 { -+ compatible = "qcom,dwc3"; -+ reg = <0x8af8800 0x100>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&gcc GCC_USB3_MASTER_CLK>, -+ <&gcc GCC_USB3_SLEEP_CLK>, -+ <&gcc GCC_USB3_MOCK_UTMI_CLK>; -+ clock-names = "master", "sleep", "mock_utmi"; -+ ranges; -+ status = "disabled"; -+ -+ dwc3@8a00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x8a00000 0xf8000>; -+ interrupts = ; -+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ dr_mode = "host"; -+ }; -+ }; -+ -+ usb2_hs_phy: hsphy@a8000 { -+ compatible = "qcom,usb-hs-ipq4019-phy"; -+ #phy-cells = <0>; -+ reg = <0xa8000 0x40>; -+ reg-names = "phy_base"; -+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; -+ reset-names = "por_rst", "srif_rst"; -+ status = "disabled"; -+ }; -+ -+ usb2@60f8800 { -+ compatible = "qcom,dwc3"; -+ reg = <0x60f8800 0x100>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&gcc GCC_USB2_MASTER_CLK>, -+ <&gcc GCC_USB2_SLEEP_CLK>, -+ <&gcc GCC_USB2_MOCK_UTMI_CLK>; -+ clock-names = "master", "sleep", "mock_utmi"; -+ ranges; -+ status = "disabled"; -+ -+ dwc3@6000000 { -+ compatible = "snps,dwc3"; -+ reg = <0x6000000 0xf8000>; -+ interrupts = ; -+ phys = <&usb2_hs_phy>; -+ phy-names = "usb2-phy"; -+ dr_mode = "host"; -+ }; -+ }; - }; - }; diff --git a/target/linux/ipq40xx/patches-4.19/080-ARM-dts-qcom-add-gpio-ranges-property.patch b/target/linux/ipq40xx/patches-4.19/080-ARM-dts-qcom-add-gpio-ranges-property.patch deleted file mode 100644 index 3a18ffc08f..0000000000 --- a/target/linux/ipq40xx/patches-4.19/080-ARM-dts-qcom-add-gpio-ranges-property.patch +++ /dev/null @@ -1,70 +0,0 @@ -From patchwork Mon May 21 20:57:38 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v5,3/4] ARM: dts: qcom: add gpio-ranges property -X-Patchwork-Submitter: Christian Lamparter -X-Patchwork-Id: 917856 -Message-Id: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com> -To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, - linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org -Cc: Bjorn Andersson , - Linus Walleij , - Stephen Boyd , David Brown , - Rob Herring , Mark Rutland , - Andy Gross , - Sven Eckelmann -Date: Mon, 21 May 2018 22:57:38 +0200 -From: Christian Lamparter -List-Id: - -This patch adds the gpio-ranges property to almost all of -the Qualcomm ARM platforms that utilize the pinctrl-msm -framework. - -The gpio-ranges property is part of the gpiolib subsystem. -As a result, the binding text is available in section -"2.1 gpio- and pin-controller interaction" of -Documentation/devicetree/bindings/gpio/gpio.txt - -For more information please see the patch titled: -"pinctrl: msm: fix gpio-hog related boot issues" from -this series. - -Reported-by: Sven Eckelmann -Tested-by: Sven Eckelmann [ipq4019] -Reviewed-by: Bjorn Andersson -Signed-off-by: Christian Lamparter -Reviewed-by: Linus Walleij ---- -To help with git bisect, the DT update patch has been intentionally -placed after the "pinctrl: msm: fix gpio-hog related boot issues". -Otherwise - if the order was reveresed - and bisect decides to split -between these two patches, the gpiochip_add_pin_ranges() function -will be executed twice with the same parameters for the same pinctrl. ---- - arch/arm/boot/dts/qcom-apq8064.dtsi | 1 + - arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + - arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + - arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 + - arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 + - arch/arm/boot/dts/qcom-msm8660.dtsi | 1 + - arch/arm/boot/dts/qcom-msm8960.dtsi | 1 + - arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++- - arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + - arch/arm64/boot/dts/qcom/msm8992.dtsi | 1 + - arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 + - arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 + - 13 files changed, 14 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -206,6 +206,7 @@ - compatible = "qcom,ipq4019-pinctrl"; - reg = <0x01000000 0x300000>; - gpio-controller; -+ gpio-ranges = <&tlmm 0 0 100>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; diff --git a/target/linux/ipq40xx/patches-4.19/081-clk-fix-apss-cpu-overclocking.patch b/target/linux/ipq40xx/patches-4.19/081-clk-fix-apss-cpu-overclocking.patch deleted file mode 100644 index de99792541..0000000000 --- a/target/linux/ipq40xx/patches-4.19/081-clk-fix-apss-cpu-overclocking.patch +++ /dev/null @@ -1,115 +0,0 @@ -From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sun, 11 Mar 2018 14:41:31 +0100 -Subject: [PATCH 2/2] clk: fix apss cpu overclocking - -There's an interaction issue between the clk changes:" -clk: qcom: ipq4019: Add the apss cpu pll divider clock node -clk: qcom: ipq4019: remove fixed clocks and add pll clocks -" and the cpufreq-dt. - -cpufreq-dt is now spamming the kernel-log with the following: - -[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP -for freq 761142857 (-34) - -This only happens on certain devices like the Compex WPJ428 -and AVM FritzBox!4040. However, other devices like the Asus -RT-AC58U and Meraki MR33 work just fine. - -The issue stem from the fact that all higher CPU-Clocks -are achieved by switching the clock-parent to the P_DDRPLLAPSS -(ddrpllapss). Which is set by Qualcomm's proprietary bootcode -as part of the DDR calibration. - -For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked -at round 533 MHz (ddrpllsdcc = 190285714 Hz). - -whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is -clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz). - -This patch attempts to fix the issue by modifying -clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate() -to use a new qcom_find_freq_close() function, which returns the closest -matching frequency, instead of the next higher. This way, the SoC in -the FB4040 (with its max clock speed of 710.4 MHz) will no longer -try to overclock to 761 MHz. - -Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node") -Signed-off-by: Christian Lamparter -Signed-off-by: John Crispin ---- - drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++--- - 1 file changed, 31 insertions(+), 3 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq4019.c -+++ b/drivers/clk/qcom/gcc-ipq4019.c -@@ -1251,6 +1251,29 @@ static const struct clk_fepll_vco gcc_fe - .reg = 0x2f020, - }; - -+ -+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f, -+ unsigned long rate) -+{ -+ const struct freq_tbl *last = NULL; -+ -+ for ( ; f->freq; f++) { -+ if (rate == f->freq) -+ return f; -+ -+ if (f->freq > rate) { -+ if (!last || -+ (f->freq - rate) < (rate - last->freq)) -+ return f; -+ else -+ return last; -+ } -+ last = f; -+ } -+ -+ return last; -+} -+ - /* - * Round rate function for APSS CPU PLL Clock divider. - * It looks up the frequency table and returns the next higher frequency -@@ -1263,7 +1286,7 @@ static long clk_cpu_div_round_rate(struc - struct clk_hw *p_hw; - const struct freq_tbl *f; - -- f = qcom_find_freq(pll->freq_tbl, rate); -+ f = qcom_find_freq_close(pll->freq_tbl, rate); - if (!f) - return -EINVAL; - -@@ -1286,7 +1309,7 @@ static int clk_cpu_div_set_rate(struct c - u32 mask; - int ret; - -- f = qcom_find_freq(pll->freq_tbl, rate); -+ f = qcom_find_freq_close(pll->freq_tbl, rate); - if (!f) - return -EINVAL; - -@@ -1313,6 +1336,7 @@ static unsigned long - clk_cpu_div_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) - { -+ const struct freq_tbl *f; - struct clk_fepll *pll = to_clk_fepll(hw); - u32 cdiv, pre_div; - u64 rate; -@@ -1333,7 +1357,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h - rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2; - do_div(rate, pre_div); - -- return rate; -+ f = qcom_find_freq_close(pll->freq_tbl, rate); -+ if (!f) -+ return rate; -+ -+ return f->freq; - }; - - static const struct clk_ops clk_regmap_cpu_div_ops = { diff --git a/target/linux/ipq40xx/patches-4.19/086-ipq40xx-fix-high-resolution-timer.patch b/target/linux/ipq40xx/patches-4.19/086-ipq40xx-fix-high-resolution-timer.patch deleted file mode 100644 index b45182271a..0000000000 --- a/target/linux/ipq40xx/patches-4.19/086-ipq40xx-fix-high-resolution-timer.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 09f145f417a5d64d6b8d4476699dfb0eccc6c784 Mon Sep 17 00:00:00 2001 -From: Abhishek Sahu -Date: Tue, 7 May 2019 10:14:05 +0300 -Subject: [PATCH] ipq40xx: fix high resolution timer - -Cherry-picked from CAF QSDK repo. -Original commit message: -The kernel is failing in switching the timer for high resolution -mode and clock source operates in 10ms resolution. The always-on -property needs to be given for timer device tree node to make -clock source working in 1ns resolution. - -Change-Id: I7c00b3c74d97c2a30ac9f05e18b511a0550fd459 -Signed-off-by: Abhishek Sahu -Signed-off-by: Pavel Kubelun ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -171,6 +171,7 @@ - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <48000000>; -+ always-on; - }; - - soc { diff --git a/target/linux/ipq40xx/patches-4.19/088-v5.6-regulator-add-IPQ4019-SDHCI-VQMMC-LDO-driver.patch b/target/linux/ipq40xx/patches-4.19/088-v5.6-regulator-add-IPQ4019-SDHCI-VQMMC-LDO-driver.patch deleted file mode 100644 index 6b46cda941..0000000000 --- a/target/linux/ipq40xx/patches-4.19/088-v5.6-regulator-add-IPQ4019-SDHCI-VQMMC-LDO-driver.patch +++ /dev/null @@ -1,153 +0,0 @@ -From 97043d292365ae39d62b54a6d79dff98d048b501 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 22 Jan 2020 12:44:14 +0100 -Subject: [PATCH] From ebf652b408200504194be32ad0a3f5bb49d6000a Mon Sep 17 - 00:00:00 2001 From: Robert Marko Date: Sun, 12 Jan - 2020 12:30:01 +0100 Subject: [PATCH] regulator: add IPQ4019 SDHCI VQMMC LDO - driver - -This introduces the IPQ4019 VQMMC LDO driver needed for -the SD/EMMC driver I/O level operation. -This will enable introducing SD/EMMC support for the built-in controller. - -Signed-off-by: Mantas Pucka -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20200112113003.11110-1-robert.marko@sartura.hr -Signed-off-by: Mark Brown ---- - drivers/regulator/Kconfig | 7 ++ - drivers/regulator/Makefile | 1 + - drivers/regulator/vqmmc-ipq4019-regulator.c | 101 ++++++++++++++++++++ - 3 files changed, 109 insertions(+) - create mode 100644 drivers/regulator/vqmmc-ipq4019-regulator.c - ---- a/drivers/regulator/Kconfig -+++ b/drivers/regulator/Kconfig -@@ -981,6 +981,13 @@ config REGULATOR_VEXPRESS - This driver provides support for voltage regulators available - on the ARM Ltd's Versatile Express platform. - -+config REGULATOR_VQMMC_IPQ4019 -+ tristate "IPQ4019 VQMMC SD LDO regulator support" -+ depends on ARCH_QCOM -+ help -+ This driver provides support for the VQMMC LDO I/0 -+ voltage regulator of the IPQ4019 SD/EMMC controller. -+ - config REGULATOR_WM831X - tristate "Wolfson Microelectronics WM831x PMIC regulators" - depends on MFD_WM831X ---- a/drivers/regulator/Makefile -+++ b/drivers/regulator/Makefile -@@ -122,6 +122,7 @@ obj-$(CONFIG_REGULATOR_TWL4030) += twl-r - obj-$(CONFIG_REGULATOR_UNIPHIER) += uniphier-regulator.o - obj-$(CONFIG_REGULATOR_VCTRL) += vctrl-regulator.o - obj-$(CONFIG_REGULATOR_VEXPRESS) += vexpress-regulator.o -+obj-$(CONFIG_REGULATOR_VQMMC_IPQ4019) += vqmmc-ipq4019-regulator.o - obj-$(CONFIG_REGULATOR_WM831X) += wm831x-dcdc.o - obj-$(CONFIG_REGULATOR_WM831X) += wm831x-isink.o - obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o ---- /dev/null -+++ b/drivers/regulator/vqmmc-ipq4019-regulator.c -@@ -0,0 +1,101 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// -+// Copyright (c) 2019 Mantas Pucka -+// Copyright (c) 2019 Robert Marko -+// -+// Driver for IPQ4019 SD/MMC controller's I/O LDO voltage regulator -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static const unsigned int ipq4019_vmmc_voltages[] = { -+ 1500000, 1800000, 2500000, 3000000, -+}; -+ -+static const struct regulator_ops ipq4019_regulator_voltage_ops = { -+ .list_voltage = regulator_list_voltage_table, -+ .map_voltage = regulator_map_voltage_ascend, -+ .get_voltage_sel = regulator_get_voltage_sel_regmap, -+ .set_voltage_sel = regulator_set_voltage_sel_regmap, -+}; -+ -+static const struct regulator_desc vmmc_regulator = { -+ .name = "vmmcq", -+ .ops = &ipq4019_regulator_voltage_ops, -+ .type = REGULATOR_VOLTAGE, -+ .owner = THIS_MODULE, -+ .volt_table = ipq4019_vmmc_voltages, -+ .n_voltages = ARRAY_SIZE(ipq4019_vmmc_voltages), -+ .vsel_reg = 0, -+ .vsel_mask = 0x3, -+}; -+ -+static const struct regmap_config ipq4019_vmmcq_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+}; -+ -+static int ipq4019_regulator_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct regulator_init_data *init_data; -+ struct regulator_config cfg = {}; -+ struct regulator_dev *rdev; -+ struct resource *res; -+ struct regmap *rmap; -+ void __iomem *base; -+ -+ init_data = of_get_regulator_init_data(dev, dev->of_node, -+ &vmmc_regulator); -+ if (!init_data) -+ return -EINVAL; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(dev, res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ rmap = devm_regmap_init_mmio(dev, base, &ipq4019_vmmcq_regmap_config); -+ if (IS_ERR(rmap)) -+ return PTR_ERR(rmap); -+ -+ cfg.dev = dev; -+ cfg.init_data = init_data; -+ cfg.of_node = dev->of_node; -+ cfg.regmap = rmap; -+ -+ rdev = devm_regulator_register(dev, &vmmc_regulator, &cfg); -+ if (IS_ERR(rdev)) { -+ dev_err(dev, "Failed to register regulator: %ld\n", -+ PTR_ERR(rdev)); -+ return PTR_ERR(rdev); -+ } -+ platform_set_drvdata(pdev, rdev); -+ -+ return 0; -+} -+ -+static const struct of_device_id regulator_ipq4019_of_match[] = { -+ { .compatible = "qcom,vqmmc-ipq4019-regulator", }, -+ {}, -+}; -+ -+static struct platform_driver ipq4019_regulator_driver = { -+ .probe = ipq4019_regulator_probe, -+ .driver = { -+ .name = "vqmmc-ipq4019-regulator", -+ .of_match_table = of_match_ptr(regulator_ipq4019_of_match), -+ }, -+}; -+module_platform_driver(ipq4019_regulator_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Mantas Pucka "); -+MODULE_DESCRIPTION("IPQ4019 VQMMC voltage regulator"); diff --git a/target/linux/ipq40xx/patches-4.19/089-v5.5-ARM-dts-qcom-ipq4019-Add-SDHCI-controller-node.patch b/target/linux/ipq40xx/patches-4.19/089-v5.5-ARM-dts-qcom-ipq4019-Add-SDHCI-controller-node.patch deleted file mode 100644 index 90e6b25538..0000000000 --- a/target/linux/ipq40xx/patches-4.19/089-v5.5-ARM-dts-qcom-ipq4019-Add-SDHCI-controller-node.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 04b3b72b5b8fdb883bfdc619cb29b03641b1cc6a Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 15 Aug 2019 19:28:23 +0200 -Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI controller node - -IPQ4019 has a built in SD/eMMC controller which is supported by the -SDHCI MSM driver, by the "qcom,sdhci-msm-v4" binding. -So lets add the appropriate node for it. - -Signed-off-by: Robert Marko -Signed-off-by: Bjorn Andersson ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -214,6 +214,18 @@ - interrupts = ; - }; - -+ sdhci: sdhci@7824900 { -+ compatible = "qcom,sdhci-msm-v4"; -+ reg = <0x7824900 0x11c>, <0x7824000 0x800>; -+ interrupts = , ; -+ interrupt-names = "hc_irq", "pwr_irq"; -+ bus-width = <8>; -+ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, -+ <&gcc GCC_DCD_XO_CLK>; -+ clock-names = "core", "iface", "xo"; -+ status = "disabled"; -+ }; -+ - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x23000>; diff --git a/target/linux/ipq40xx/patches-4.19/100-arm-dts-IPQ4019-add-SDHCI-VQMMC-LDO-node.patch b/target/linux/ipq40xx/patches-4.19/100-arm-dts-IPQ4019-add-SDHCI-VQMMC-LDO-node.patch deleted file mode 100644 index 1f346371de..0000000000 --- a/target/linux/ipq40xx/patches-4.19/100-arm-dts-IPQ4019-add-SDHCI-VQMMC-LDO-node.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 77d9b11ae7269dcf376c3b9493209f712524e986 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 22 Jan 2020 12:56:35 +0100 -Subject: [PATCH] arm: dts: IPQ4019: add SDHCI VQMMC LDO node - -Since we now have driver for the SDHCI VQMMC LDO needed -for I/0 voltage levels lets introduce the necessary node for it. - -Signed-off-by: Robert Marko ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -214,6 +214,16 @@ - interrupts = ; - }; - -+ vqmmc: regulator@1948000 { -+ compatible = "qcom,vqmmc-ipq4019-regulator"; -+ reg = <0x01948000 0x4>; -+ regulator-name = "vqmmc"; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-always-on; -+ status = "disabled"; -+ }; -+ - sdhci: sdhci@7824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x11c>, <0x7824000 0x800>; diff --git a/target/linux/ipq40xx/patches-4.19/303-spi-nor-enable-4B-opcodes-for-mx25l25635f.patch b/target/linux/ipq40xx/patches-4.19/303-spi-nor-enable-4B-opcodes-for-mx25l25635f.patch deleted file mode 100644 index 4cabfc8f59..0000000000 --- a/target/linux/ipq40xx/patches-4.19/303-spi-nor-enable-4B-opcodes-for-mx25l25635f.patch +++ /dev/null @@ -1,62 +0,0 @@ ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -1099,6 +1099,7 @@ static const struct flash_info spi_nor_i - { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { "mx25l25635f", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, - { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, - { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, -@@ -1286,11 +1287,12 @@ static const struct flash_info spi_nor_i - { }, - }; - --static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) -+static const struct flash_info *spi_nor_read_id(struct spi_nor *nor, -+ const char *name) - { - int tmp; - u8 id[SPI_NOR_MAX_ID_LEN]; -- const struct flash_info *info; -+ const struct flash_info *info, *first_match = NULL; - - tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); - if (tmp < 0) { -@@ -1301,10 +1303,16 @@ static const struct flash_info *spi_nor_ - for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { - info = &spi_nor_ids[tmp]; - if (info->id_len) { -- if (!memcmp(info->id, id, info->id_len)) -- return &spi_nor_ids[tmp]; -+ if (!memcmp(info->id, id, info->id_len)) { -+ if (!name || !strcmp(name, info->name)) -+ return info; -+ if (!first_match) -+ first_match = info; -+ } - } - } -+ if (first_match) -+ return first_match; - dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", - id[0], id[1], id[2]); - return ERR_PTR(-ENODEV); -@@ -2838,7 +2846,7 @@ int spi_nor_scan(struct spi_nor *nor, co - info = spi_nor_match_id(name); - /* Try to auto-detect if chip name wasn't specified or not found */ - if (!info) -- info = spi_nor_read_id(nor); -+ info = spi_nor_read_id(nor, NULL); - if (IS_ERR_OR_NULL(info)) - return -ENOENT; - -@@ -2849,7 +2857,7 @@ int spi_nor_scan(struct spi_nor *nor, co - if (name && info->id_len) { - const struct flash_info *jinfo; - -- jinfo = spi_nor_read_id(nor); -+ jinfo = spi_nor_read_id(nor, name); - if (IS_ERR(jinfo)) { - return PTR_ERR(jinfo); - } else if (jinfo != info) { diff --git a/target/linux/ipq40xx/patches-4.19/304-mtd-spi-nor-Add-support-for-mx25r3235f.patch b/target/linux/ipq40xx/patches-4.19/304-mtd-spi-nor-Add-support-for-mx25r3235f.patch deleted file mode 100644 index ad66f409b1..0000000000 --- a/target/linux/ipq40xx/patches-4.19/304-mtd-spi-nor-Add-support-for-mx25r3235f.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 158acdbf0336f601971637f988b57a6a67a0869b Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Sun, 15 Dec 2019 13:10:50 +0100 -Subject: [PATCH] mtd: spi-nor: Add support for mx25r3235f - -Add MTD support for the Macronix MX25R3235F SPI NOR chip from Macronix. -The chip has 4MB of total capacity, divided into a total of 64 sectors, -each 64KB sized. The chip also supports 4KB large sectors. -Additionally, it supports dual and quad read modes. - -Signed-off-by: David Bauer ---- - drivers/mtd/spi-nor/spi-nor.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -1096,6 +1096,8 @@ static const struct flash_info spi_nor_i - { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, - { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, - { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, -+ { "mx25r3235f", INFO(0xc22816, 0, 64 * 1024, 64, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, diff --git a/target/linux/ipq40xx/patches-4.19/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch b/target/linux/ipq40xx/patches-4.19/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch deleted file mode 100644 index 3ec6f4a0e8..0000000000 --- a/target/linux/ipq40xx/patches-4.19/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 0e28623a11f3916c1fe5b7e789c7ab8ca932a929 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 22 Jan 2020 13:02:13 +0100 -Subject: [PATCH] mmc: sdhci: sdhci-msm: use sdhci_set_clock instead of - sdhci_msm_set_clock - -When using sdhci_msm_set_clock clock setting will fail, so lets -use the generic sdhci_set_clock. - -Signed-off-by: Robert Marko ---- - drivers/mmc/host/sdhci-msm.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mmc/host/sdhci-msm.c -+++ b/drivers/mmc/host/sdhci-msm.c -@@ -1694,7 +1694,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat - - static const struct sdhci_ops sdhci_msm_ops = { - .reset = sdhci_reset, -- .set_clock = sdhci_msm_set_clock, -+ .set_clock = sdhci_set_clock, - .get_min_clock = sdhci_msm_get_min_clock, - .get_max_clock = sdhci_msm_get_max_clock, - .set_bus_width = sdhci_set_bus_width, diff --git a/target/linux/ipq40xx/patches-4.19/700-net-add-qualcomm-mdio.patch b/target/linux/ipq40xx/patches-4.19/700-net-add-qualcomm-mdio.patch deleted file mode 100644 index 847e2e8701..0000000000 --- a/target/linux/ipq40xx/patches-4.19/700-net-add-qualcomm-mdio.patch +++ /dev/null @@ -1,225 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -524,6 +524,13 @@ config XILINX_GMII2RGMII - the Reduced Gigabit Media Independent Interface(RGMII) between - Ethernet physical media devices and the Gigabit Ethernet controller. - -+config MDIO_IPQ40XX -+ tristate "Qualcomm Atheros ipq40xx MDIO interface" -+ depends on HAS_IOMEM && OF -+ ---help--- -+ This driver supports the MDIO interface found in Qualcomm -+ Atheros ipq40xx Soc chip. -+ - endif # PHYLIB - - config MICREL_KS8995MA ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -48,6 +48,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium - obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o - obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o - obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o -+obj-$(CONFIG_MDIO_IPQ40XX) += mdio-ipq40xx.o - obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o - obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o - obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o ---- /dev/null -+++ b/drivers/net/phy/mdio-ipq40xx.c -@@ -0,0 +1,196 @@ -+/* -+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for -+ * any purpose with or without fee is hereby granted, provided that the -+ * above copyright notice and this permission notice appear in all copies. -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MDIO_CTRL_0_REG 0x40 -+#define MDIO_CTRL_1_REG 0x44 -+#define MDIO_CTRL_2_REG 0x48 -+#define MDIO_CTRL_3_REG 0x4c -+#define MDIO_CTRL_4_REG 0x50 -+#define MDIO_CTRL_4_ACCESS_BUSY BIT(16) -+#define MDIO_CTRL_4_ACCESS_START BIT(8) -+#define MDIO_CTRL_4_ACCESS_CODE_READ 0 -+#define MDIO_CTRL_4_ACCESS_CODE_WRITE 1 -+#define CTRL_0_REG_DEFAULT_VALUE 0x150FF -+ -+#define IPQ40XX_MDIO_RETRY 1000 -+#define IPQ40XX_MDIO_DELAY 10 -+ -+struct ipq40xx_mdio_data { -+ struct mii_bus *mii_bus; -+ void __iomem *membase; -+ struct device *dev; -+}; -+ -+static int ipq40xx_mdio_wait_busy(struct ipq40xx_mdio_data *am) -+{ -+ int i; -+ -+ for (i = 0; i < IPQ40XX_MDIO_RETRY; i++) { -+ unsigned int busy; -+ -+ busy = readl(am->membase + MDIO_CTRL_4_REG) & -+ MDIO_CTRL_4_ACCESS_BUSY; -+ if (!busy) -+ return 0; -+ -+ /* BUSY might take to be cleard by 15~20 times of loop */ -+ udelay(IPQ40XX_MDIO_DELAY); -+ } -+ -+ dev_err(am->dev, "%s: MDIO operation timed out\n", am->mii_bus->name); -+ -+ return -ETIMEDOUT; -+} -+ -+static int ipq40xx_mdio_read(struct mii_bus *bus, int mii_id, int regnum) -+{ -+ struct ipq40xx_mdio_data *am = bus->priv; -+ int value = 0; -+ unsigned int cmd = 0; -+ -+ lockdep_assert_held(&bus->mdio_lock); -+ -+ if (ipq40xx_mdio_wait_busy(am)) -+ return -ETIMEDOUT; -+ -+ /* issue the phy address and reg */ -+ writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG); -+ -+ cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_READ; -+ -+ /* issue read command */ -+ writel(cmd, am->membase + MDIO_CTRL_4_REG); -+ -+ /* Wait read complete */ -+ if (ipq40xx_mdio_wait_busy(am)) -+ return -ETIMEDOUT; -+ -+ /* Read data */ -+ value = readl(am->membase + MDIO_CTRL_3_REG); -+ -+ return value; -+} -+ -+static int ipq40xx_mdio_write(struct mii_bus *bus, int mii_id, int regnum, -+ u16 value) -+{ -+ struct ipq40xx_mdio_data *am = bus->priv; -+ unsigned int cmd = 0; -+ -+ lockdep_assert_held(&bus->mdio_lock); -+ -+ if (ipq40xx_mdio_wait_busy(am)) -+ return -ETIMEDOUT; -+ -+ /* issue the phy address and reg */ -+ writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG); -+ -+ /* issue write data */ -+ writel(value, am->membase + MDIO_CTRL_2_REG); -+ -+ cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_WRITE; -+ /* issue write command */ -+ writel(cmd, am->membase + MDIO_CTRL_4_REG); -+ -+ /* Wait write complete */ -+ if (ipq40xx_mdio_wait_busy(am)) -+ return -ETIMEDOUT; -+ -+ return 0; -+} -+ -+static int ipq40xx_mdio_probe(struct platform_device *pdev) -+{ -+ struct ipq40xx_mdio_data *am; -+ struct resource *res; -+ int i; -+ -+ am = devm_kzalloc(&pdev->dev, sizeof(*am), GFP_KERNEL); -+ if (!am) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "no iomem resource found\n"); -+ return -ENXIO; -+ } -+ -+ am->membase = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(am->membase)) { -+ dev_err(&pdev->dev, "unable to ioremap registers\n"); -+ return PTR_ERR(am->membase); -+ } -+ -+ am->mii_bus = devm_mdiobus_alloc(&pdev->dev); -+ if (!am->mii_bus) -+ return -ENOMEM; -+ -+ writel(CTRL_0_REG_DEFAULT_VALUE, am->membase + MDIO_CTRL_0_REG); -+ -+ am->mii_bus->name = "ipq40xx_mdio"; -+ am->mii_bus->read = ipq40xx_mdio_read; -+ am->mii_bus->write = ipq40xx_mdio_write; -+ am->mii_bus->priv = am; -+ am->mii_bus->parent = &pdev->dev; -+ snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev)); -+ -+ am->dev = &pdev->dev; -+ platform_set_drvdata(pdev, am); -+ -+ return of_mdiobus_register(am->mii_bus, pdev->dev.of_node); -+} -+ -+static int ipq40xx_mdio_remove(struct platform_device *pdev) -+{ -+ struct ipq40xx_mdio_data *am = platform_get_drvdata(pdev); -+ -+ mdiobus_unregister(am->mii_bus); -+ -+ return 0; -+} -+ -+static const struct of_device_id ipq40xx_mdio_dt_ids[] = { -+ { .compatible = "qcom,ipq4019-mdio" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, ipq40xx_mdio_dt_ids); -+ -+static struct platform_driver ipq40xx_mdio_driver = { -+ .probe = ipq40xx_mdio_probe, -+ .remove = ipq40xx_mdio_remove, -+ .driver = { -+ .name = "ipq40xx-mdio", -+ .of_match_table = ipq40xx_mdio_dt_ids, -+ }, -+}; -+ -+module_platform_driver(ipq40xx_mdio_driver); -+ -+#define DRV_VERSION "1.0" -+ -+MODULE_DESCRIPTION("IPQ40XX MDIO interface driver"); -+MODULE_AUTHOR("Qualcomm Atheros"); -+MODULE_VERSION(DRV_VERSION); -+MODULE_LICENSE("Dual BSD/GPL"); diff --git a/target/linux/ipq40xx/patches-4.19/701-dts-ipq4019-add-mdio-node.patch b/target/linux/ipq40xx/patches-4.19/701-dts-ipq4019-add-mdio-node.patch deleted file mode 100644 index 7117a4bdfe..0000000000 --- a/target/linux/ipq40xx/patches-4.19/701-dts-ipq4019-add-mdio-node.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 09ed737593f71bcca08a537a6c15264a1a6add08 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sun, 20 Nov 2016 01:10:33 +0100 -Subject: [PATCH] dts: ipq4019: add mdio node for ethernet - -This patch adds the mdio device-tree node. -This is where the switch is connected to, so it's needed -for the ethernet interfaces. - -Note: The driver isn't anywhere close to be upstream, -so the info might change. ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 28 ++++++++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -593,6 +593,34 @@ - status = "disabled"; - }; - -+ mdio: mdio@90000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "qcom,ipq4019-mdio"; -+ reg = <0x90000 0x64>; -+ status = "disabled"; -+ -+ ethphy0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ -+ ethphy2: ethernet-phy@2 { -+ reg = <2>; -+ }; -+ -+ ethphy3: ethernet-phy@3 { -+ reg = <3>; -+ }; -+ -+ ethphy4: ethernet-phy@4 { -+ reg = <4>; -+ }; -+ }; -+ - usb3_ss_phy: ssphy@9a000 { - compatible = "qcom,usb-ss-ipq4019-phy"; - #phy-cells = <0>; diff --git a/target/linux/ipq40xx/patches-4.19/702-dts-ipq4019-add-PHY-switch-nodes.patch b/target/linux/ipq40xx/patches-4.19/702-dts-ipq4019-add-PHY-switch-nodes.patch deleted file mode 100644 index 4ef8044893..0000000000 --- a/target/linux/ipq40xx/patches-4.19/702-dts-ipq4019-add-PHY-switch-nodes.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sun, 20 Nov 2016 02:20:54 +0100 -Subject: [PATCH] dts: ipq4019: add PHY/switch nodes - -This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii" -nodes which are needed for the ar40xx.c driver to initialize the -switch. - -Signed-off-by: Christian Lamparter ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -621,6 +621,29 @@ - }; - }; - -+ ess-switch@c000000 { -+ compatible = "qcom,ess-switch"; -+ reg = <0xc000000 0x80000>; -+ switch_access_mode = "local bus"; -+ resets = <&gcc ESS_RESET>; -+ reset-names = "ess_rst"; -+ clocks = <&gcc GCC_ESS_CLK>; -+ clock-names = "ess_clk"; -+ switch_cpu_bmp = <0x1>; -+ switch_lan_bmp = <0x1e>; -+ switch_wan_bmp = <0x20>; -+ switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */ -+ switch_initvlas = <0x7c 0x54>; -+ status = "disabled"; -+ }; -+ -+ ess-psgmii@98000 { -+ compatible = "qcom,ess-psgmii"; -+ reg = <0x98000 0x800>; -+ psgmii_access_mode = "local bus"; -+ status = "disabled"; -+ }; -+ - usb3_ss_phy: ssphy@9a000 { - compatible = "qcom,usb-ss-ipq4019-phy"; - #phy-cells = <0>; diff --git a/target/linux/ipq40xx/patches-4.19/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch b/target/linux/ipq40xx/patches-4.19/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch deleted file mode 100644 index cc7e49736d..0000000000 --- a/target/linux/ipq40xx/patches-4.19/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001 -From: Rakesh Nair -Date: Wed, 20 Jul 2016 15:02:01 +0530 -Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in - netdev_ops - -Add callback support to get default vlan tag and register -receive flow steering filter. - -Used by IPQ4019 ess-edma driver. - -BUG=chrome-os-partner:33096 -TEST=none - -Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75 -Signed-off-by: Rakesh Nair -Reviewed-on: https://chromium-review.googlesource.com/362203 -Commit-Ready: Grant Grundler -Tested-by: Grant Grundler -Reviewed-by: Grant Grundler ---- - include/linux/netdevice.h | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -739,6 +739,16 @@ struct xps_map { - #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \ - - sizeof(struct xps_map)) / sizeof(u16)) - -+#ifdef CONFIG_RFS_ACCEL -+typedef int (*set_rfs_filter_callback_t)(struct net_device *dev, -+ __be32 src, -+ __be32 dst, -+ __be16 sport, -+ __be16 dport, -+ u8 proto, -+ u16 rxq_index, -+ u32 action); -+#endif - /* - * This structure holds all XPS maps for device. Maps are indexed by CPU. - */ -@@ -1353,6 +1363,9 @@ struct net_device_ops { - const struct sk_buff *skb, - u16 rxq_index, - u32 flow_id); -+ int (*ndo_register_rfs_filter)(struct net_device *dev, -+ set_rfs_filter_callback_t set_filter); -+ int (*ndo_get_default_vlan_tag)(struct net_device *net); - #endif - int (*ndo_add_slave)(struct net_device *dev, - struct net_device *slave_dev, diff --git a/target/linux/ipq40xx/patches-4.19/705-net-add-qualcomm-ar40xx-phy.patch b/target/linux/ipq40xx/patches-4.19/705-net-add-qualcomm-ar40xx-phy.patch deleted file mode 100644 index 4247ef10c6..0000000000 --- a/target/linux/ipq40xx/patches-4.19/705-net-add-qualcomm-ar40xx-phy.patch +++ /dev/null @@ -1,2459 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -531,6 +531,13 @@ config MDIO_IPQ40XX - This driver supports the MDIO interface found in Qualcomm - Atheros ipq40xx Soc chip. - -+config AR40XX_PHY -+ tristate "Driver for Qualcomm Atheros IPQ40XX switches" -+ depends on HAS_IOMEM && OF -+ select SWCONFIG -+ ---help--- -+ This is the driver for Qualcomm Atheros IPQ40XX ESS switches. -+ - endif # PHYLIB - - config MICREL_KS8995MA ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -62,6 +62,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) - - obj-$(CONFIG_AMD_PHY) += amd.o - obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o -+obj-$(CONFIG_AR40XX_PHY) += ar40xx.o - obj-$(CONFIG_AX88796B_PHY) += ax88796b.o - obj-$(CONFIG_AT803X_PHY) += at803x.o - obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o ---- /dev/null -+++ b/drivers/net/phy/ar40xx.c -@@ -0,0 +1,2090 @@ -+/* -+ * Copyright (c) 2016, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for -+ * any purpose with or without fee is hereby granted, provided that the -+ * above copyright notice and this permission notice appear in all copies. -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "ar40xx.h" -+ -+static struct ar40xx_priv *ar40xx_priv; -+ -+#define MIB_DESC(_s , _o, _n) \ -+ { \ -+ .size = (_s), \ -+ .offset = (_o), \ -+ .name = (_n), \ -+ } -+ -+static const struct ar40xx_mib_desc ar40xx_mibs[] = { -+ MIB_DESC(1, AR40XX_STATS_RXBROAD, "RxBroad"), -+ MIB_DESC(1, AR40XX_STATS_RXPAUSE, "RxPause"), -+ MIB_DESC(1, AR40XX_STATS_RXMULTI, "RxMulti"), -+ MIB_DESC(1, AR40XX_STATS_RXFCSERR, "RxFcsErr"), -+ MIB_DESC(1, AR40XX_STATS_RXALIGNERR, "RxAlignErr"), -+ MIB_DESC(1, AR40XX_STATS_RXRUNT, "RxRunt"), -+ MIB_DESC(1, AR40XX_STATS_RXFRAGMENT, "RxFragment"), -+ MIB_DESC(1, AR40XX_STATS_RX64BYTE, "Rx64Byte"), -+ MIB_DESC(1, AR40XX_STATS_RX128BYTE, "Rx128Byte"), -+ MIB_DESC(1, AR40XX_STATS_RX256BYTE, "Rx256Byte"), -+ MIB_DESC(1, AR40XX_STATS_RX512BYTE, "Rx512Byte"), -+ MIB_DESC(1, AR40XX_STATS_RX1024BYTE, "Rx1024Byte"), -+ MIB_DESC(1, AR40XX_STATS_RX1518BYTE, "Rx1518Byte"), -+ MIB_DESC(1, AR40XX_STATS_RXMAXBYTE, "RxMaxByte"), -+ MIB_DESC(1, AR40XX_STATS_RXTOOLONG, "RxTooLong"), -+ MIB_DESC(2, AR40XX_STATS_RXGOODBYTE, "RxGoodByte"), -+ MIB_DESC(2, AR40XX_STATS_RXBADBYTE, "RxBadByte"), -+ MIB_DESC(1, AR40XX_STATS_RXOVERFLOW, "RxOverFlow"), -+ MIB_DESC(1, AR40XX_STATS_FILTERED, "Filtered"), -+ MIB_DESC(1, AR40XX_STATS_TXBROAD, "TxBroad"), -+ MIB_DESC(1, AR40XX_STATS_TXPAUSE, "TxPause"), -+ MIB_DESC(1, AR40XX_STATS_TXMULTI, "TxMulti"), -+ MIB_DESC(1, AR40XX_STATS_TXUNDERRUN, "TxUnderRun"), -+ MIB_DESC(1, AR40XX_STATS_TX64BYTE, "Tx64Byte"), -+ MIB_DESC(1, AR40XX_STATS_TX128BYTE, "Tx128Byte"), -+ MIB_DESC(1, AR40XX_STATS_TX256BYTE, "Tx256Byte"), -+ MIB_DESC(1, AR40XX_STATS_TX512BYTE, "Tx512Byte"), -+ MIB_DESC(1, AR40XX_STATS_TX1024BYTE, "Tx1024Byte"), -+ MIB_DESC(1, AR40XX_STATS_TX1518BYTE, "Tx1518Byte"), -+ MIB_DESC(1, AR40XX_STATS_TXMAXBYTE, "TxMaxByte"), -+ MIB_DESC(1, AR40XX_STATS_TXOVERSIZE, "TxOverSize"), -+ MIB_DESC(2, AR40XX_STATS_TXBYTE, "TxByte"), -+ MIB_DESC(1, AR40XX_STATS_TXCOLLISION, "TxCollision"), -+ MIB_DESC(1, AR40XX_STATS_TXABORTCOL, "TxAbortCol"), -+ MIB_DESC(1, AR40XX_STATS_TXMULTICOL, "TxMultiCol"), -+ MIB_DESC(1, AR40XX_STATS_TXSINGLECOL, "TxSingleCol"), -+ MIB_DESC(1, AR40XX_STATS_TXEXCDEFER, "TxExcDefer"), -+ MIB_DESC(1, AR40XX_STATS_TXDEFER, "TxDefer"), -+ MIB_DESC(1, AR40XX_STATS_TXLATECOL, "TxLateCol"), -+}; -+ -+static u32 -+ar40xx_read(struct ar40xx_priv *priv, int reg) -+{ -+ return readl(priv->hw_addr + reg); -+} -+ -+static u32 -+ar40xx_psgmii_read(struct ar40xx_priv *priv, int reg) -+{ -+ return readl(priv->psgmii_hw_addr + reg); -+} -+ -+static void -+ar40xx_write(struct ar40xx_priv *priv, int reg, u32 val) -+{ -+ writel(val, priv->hw_addr + reg); -+} -+ -+static u32 -+ar40xx_rmw(struct ar40xx_priv *priv, int reg, u32 mask, u32 val) -+{ -+ u32 ret; -+ -+ ret = ar40xx_read(priv, reg); -+ ret &= ~mask; -+ ret |= val; -+ ar40xx_write(priv, reg, ret); -+ return ret; -+} -+ -+static void -+ar40xx_psgmii_write(struct ar40xx_priv *priv, int reg, u32 val) -+{ -+ writel(val, priv->psgmii_hw_addr + reg); -+} -+ -+static void -+ar40xx_phy_dbg_write(struct ar40xx_priv *priv, int phy_addr, -+ u16 dbg_addr, u16 dbg_data) -+{ -+ struct mii_bus *bus = priv->mii_bus; -+ -+ mutex_lock(&bus->mdio_lock); -+ bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr); -+ bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA, dbg_data); -+ mutex_unlock(&bus->mdio_lock); -+} -+ -+static void -+ar40xx_phy_dbg_read(struct ar40xx_priv *priv, int phy_addr, -+ u16 dbg_addr, u16 *dbg_data) -+{ -+ struct mii_bus *bus = priv->mii_bus; -+ -+ mutex_lock(&bus->mdio_lock); -+ bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr); -+ *dbg_data = bus->read(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA); -+ mutex_unlock(&bus->mdio_lock); -+} -+ -+static void -+ar40xx_phy_mmd_write(struct ar40xx_priv *priv, u32 phy_id, -+ u16 mmd_num, u16 reg_id, u16 reg_val) -+{ -+ struct mii_bus *bus = priv->mii_bus; -+ -+ mutex_lock(&bus->mdio_lock); -+ bus->write(bus, phy_id, -+ AR40XX_MII_ATH_MMD_ADDR, mmd_num); -+ bus->write(bus, phy_id, -+ AR40XX_MII_ATH_MMD_DATA, reg_id); -+ bus->write(bus, phy_id, -+ AR40XX_MII_ATH_MMD_ADDR, -+ 0x4000 | mmd_num); -+ bus->write(bus, phy_id, -+ AR40XX_MII_ATH_MMD_DATA, reg_val); -+ mutex_unlock(&bus->mdio_lock); -+} -+ -+static u16 -+ar40xx_phy_mmd_read(struct ar40xx_priv *priv, u32 phy_id, -+ u16 mmd_num, u16 reg_id) -+{ -+ u16 value; -+ struct mii_bus *bus = priv->mii_bus; -+ -+ mutex_lock(&bus->mdio_lock); -+ bus->write(bus, phy_id, -+ AR40XX_MII_ATH_MMD_ADDR, mmd_num); -+ bus->write(bus, phy_id, -+ AR40XX_MII_ATH_MMD_DATA, reg_id); -+ bus->write(bus, phy_id, -+ AR40XX_MII_ATH_MMD_ADDR, -+ 0x4000 | mmd_num); -+ value = bus->read(bus, phy_id, AR40XX_MII_ATH_MMD_DATA); -+ mutex_unlock(&bus->mdio_lock); -+ return value; -+} -+ -+/* Start of swconfig support */ -+ -+static void -+ar40xx_phy_poll_reset(struct ar40xx_priv *priv) -+{ -+ u32 i, in_reset, retries = 500; -+ struct mii_bus *bus = priv->mii_bus; -+ -+ /* Assume RESET was recently issued to some or all of the phys */ -+ in_reset = GENMASK(AR40XX_NUM_PHYS - 1, 0); -+ -+ while (retries--) { -+ /* 1ms should be plenty of time. -+ * 802.3 spec allows for a max wait time of 500ms -+ */ -+ usleep_range(1000, 2000); -+ -+ for (i = 0; i < AR40XX_NUM_PHYS; i++) { -+ int val; -+ -+ /* skip devices which have completed reset */ -+ if (!(in_reset & BIT(i))) -+ continue; -+ -+ val = mdiobus_read(bus, i, MII_BMCR); -+ if (val < 0) -+ continue; -+ -+ /* mark when phy is no longer in reset state */ -+ if (!(val & BMCR_RESET)) -+ in_reset &= ~BIT(i); -+ } -+ -+ if (!in_reset) -+ return; -+ } -+ -+ dev_warn(&bus->dev, "Failed to reset all phys! (in_reset: 0x%x)\n", -+ in_reset); -+} -+ -+static void -+ar40xx_phy_init(struct ar40xx_priv *priv) -+{ -+ int i; -+ struct mii_bus *bus; -+ u16 val; -+ -+ bus = priv->mii_bus; -+ for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) { -+ ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val); -+ val &= ~AR40XX_PHY_MANU_CTRL_EN; -+ ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val); -+ mdiobus_write(bus, i, -+ MII_ADVERTISE, ADVERTISE_ALL | -+ ADVERTISE_PAUSE_CAP | -+ ADVERTISE_PAUSE_ASYM); -+ mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL); -+ mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); -+ } -+ -+ ar40xx_phy_poll_reset(priv); -+} -+ -+static void -+ar40xx_port_phy_linkdown(struct ar40xx_priv *priv) -+{ -+ struct mii_bus *bus; -+ int i; -+ u16 val; -+ -+ bus = priv->mii_bus; -+ for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) { -+ mdiobus_write(bus, i, MII_CTRL1000, 0); -+ mdiobus_write(bus, i, MII_ADVERTISE, 0); -+ mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); -+ ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val); -+ val |= AR40XX_PHY_MANU_CTRL_EN; -+ ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val); -+ /* disable transmit */ -+ ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_2, &val); -+ val &= 0xf00f; -+ ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_2, val); -+ } -+} -+ -+static void -+ar40xx_set_mirror_regs(struct ar40xx_priv *priv) -+{ -+ int port; -+ -+ /* reset all mirror registers */ -+ ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0, -+ AR40XX_FWD_CTRL0_MIRROR_PORT, -+ (0xF << AR40XX_FWD_CTRL0_MIRROR_PORT_S)); -+ for (port = 0; port < AR40XX_NUM_PORTS; port++) { -+ ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(port), -+ AR40XX_PORT_LOOKUP_ING_MIRROR_EN, 0); -+ -+ ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(port), -+ AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN, 0); -+ } -+ -+ /* now enable mirroring if necessary */ -+ if (priv->source_port >= AR40XX_NUM_PORTS || -+ priv->monitor_port >= AR40XX_NUM_PORTS || -+ priv->source_port == priv->monitor_port) { -+ return; -+ } -+ -+ ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0, -+ AR40XX_FWD_CTRL0_MIRROR_PORT, -+ (priv->monitor_port << AR40XX_FWD_CTRL0_MIRROR_PORT_S)); -+ -+ if (priv->mirror_rx) -+ ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(priv->source_port), 0, -+ AR40XX_PORT_LOOKUP_ING_MIRROR_EN); -+ -+ if (priv->mirror_tx) -+ ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(priv->source_port), -+ 0, AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN); -+} -+ -+static int -+ar40xx_sw_get_ports(struct switch_dev *dev, struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ u8 ports = priv->vlan_table[val->port_vlan]; -+ int i; -+ -+ val->len = 0; -+ for (i = 0; i < dev->ports; i++) { -+ struct switch_port *p; -+ -+ if (!(ports & BIT(i))) -+ continue; -+ -+ p = &val->value.ports[val->len++]; -+ p->id = i; -+ if ((priv->vlan_tagged & BIT(i)) || -+ (priv->pvid[i] != val->port_vlan)) -+ p->flags = BIT(SWITCH_PORT_FLAG_TAGGED); -+ else -+ p->flags = 0; -+ } -+ return 0; -+} -+ -+static int -+ar40xx_sw_set_ports(struct switch_dev *dev, struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ u8 *vt = &priv->vlan_table[val->port_vlan]; -+ int i; -+ -+ *vt = 0; -+ for (i = 0; i < val->len; i++) { -+ struct switch_port *p = &val->value.ports[i]; -+ -+ if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) { -+ if (val->port_vlan == priv->pvid[p->id]) -+ priv->vlan_tagged |= BIT(p->id); -+ } else { -+ priv->vlan_tagged &= ~BIT(p->id); -+ priv->pvid[p->id] = val->port_vlan; -+ } -+ -+ *vt |= BIT(p->id); -+ } -+ return 0; -+} -+ -+static int -+ar40xx_reg_wait(struct ar40xx_priv *priv, u32 reg, u32 mask, u32 val, -+ unsigned timeout) -+{ -+ int i; -+ -+ for (i = 0; i < timeout; i++) { -+ u32 t; -+ -+ t = ar40xx_read(priv, reg); -+ if ((t & mask) == val) -+ return 0; -+ -+ usleep_range(1000, 2000); -+ } -+ -+ return -ETIMEDOUT; -+} -+ -+static int -+ar40xx_mib_op(struct ar40xx_priv *priv, u32 op) -+{ -+ int ret; -+ -+ lockdep_assert_held(&priv->mib_lock); -+ -+ /* Capture the hardware statistics for all ports */ -+ ar40xx_rmw(priv, AR40XX_REG_MIB_FUNC, -+ AR40XX_MIB_FUNC, (op << AR40XX_MIB_FUNC_S)); -+ -+ /* Wait for the capturing to complete. */ -+ ret = ar40xx_reg_wait(priv, AR40XX_REG_MIB_FUNC, -+ AR40XX_MIB_BUSY, 0, 10); -+ -+ return ret; -+} -+ -+static void -+ar40xx_mib_fetch_port_stat(struct ar40xx_priv *priv, int port, bool flush) -+{ -+ unsigned int base; -+ u64 *mib_stats; -+ int i; -+ u32 num_mibs = ARRAY_SIZE(ar40xx_mibs); -+ -+ WARN_ON(port >= priv->dev.ports); -+ -+ lockdep_assert_held(&priv->mib_lock); -+ -+ base = AR40XX_REG_PORT_STATS_START + -+ AR40XX_REG_PORT_STATS_LEN * port; -+ -+ mib_stats = &priv->mib_stats[port * num_mibs]; -+ if (flush) { -+ u32 len; -+ -+ len = num_mibs * sizeof(*mib_stats); -+ memset(mib_stats, 0, len); -+ return; -+ } -+ for (i = 0; i < num_mibs; i++) { -+ const struct ar40xx_mib_desc *mib; -+ u64 t; -+ -+ mib = &ar40xx_mibs[i]; -+ t = ar40xx_read(priv, base + mib->offset); -+ if (mib->size == 2) { -+ u64 hi; -+ -+ hi = ar40xx_read(priv, base + mib->offset + 4); -+ t |= hi << 32; -+ } -+ -+ mib_stats[i] += t; -+ } -+} -+ -+static int -+ar40xx_mib_capture(struct ar40xx_priv *priv) -+{ -+ return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_CAPTURE); -+} -+ -+static int -+ar40xx_mib_flush(struct ar40xx_priv *priv) -+{ -+ return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_FLUSH); -+} -+ -+static int -+ar40xx_sw_set_reset_mibs(struct switch_dev *dev, -+ const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ unsigned int len; -+ int ret; -+ u32 num_mibs = ARRAY_SIZE(ar40xx_mibs); -+ -+ mutex_lock(&priv->mib_lock); -+ -+ len = priv->dev.ports * num_mibs * sizeof(*priv->mib_stats); -+ memset(priv->mib_stats, 0, len); -+ ret = ar40xx_mib_flush(priv); -+ -+ mutex_unlock(&priv->mib_lock); -+ return ret; -+} -+ -+static int -+ar40xx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ priv->vlan = !!val->value.i; -+ return 0; -+} -+ -+static int -+ar40xx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ val->value.i = priv->vlan; -+ return 0; -+} -+ -+static int -+ar40xx_sw_set_mirror_rx_enable(struct switch_dev *dev, -+ const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ mutex_lock(&priv->reg_mutex); -+ priv->mirror_rx = !!val->value.i; -+ ar40xx_set_mirror_regs(priv); -+ mutex_unlock(&priv->reg_mutex); -+ -+ return 0; -+} -+ -+static int -+ar40xx_sw_get_mirror_rx_enable(struct switch_dev *dev, -+ const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ mutex_lock(&priv->reg_mutex); -+ val->value.i = priv->mirror_rx; -+ mutex_unlock(&priv->reg_mutex); -+ return 0; -+} -+ -+static int -+ar40xx_sw_set_mirror_tx_enable(struct switch_dev *dev, -+ const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ mutex_lock(&priv->reg_mutex); -+ priv->mirror_tx = !!val->value.i; -+ ar40xx_set_mirror_regs(priv); -+ mutex_unlock(&priv->reg_mutex); -+ -+ return 0; -+} -+ -+static int -+ar40xx_sw_get_mirror_tx_enable(struct switch_dev *dev, -+ const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ mutex_lock(&priv->reg_mutex); -+ val->value.i = priv->mirror_tx; -+ mutex_unlock(&priv->reg_mutex); -+ return 0; -+} -+ -+static int -+ar40xx_sw_set_mirror_monitor_port(struct switch_dev *dev, -+ const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ mutex_lock(&priv->reg_mutex); -+ priv->monitor_port = val->value.i; -+ ar40xx_set_mirror_regs(priv); -+ mutex_unlock(&priv->reg_mutex); -+ -+ return 0; -+} -+ -+static int -+ar40xx_sw_get_mirror_monitor_port(struct switch_dev *dev, -+ const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ mutex_lock(&priv->reg_mutex); -+ val->value.i = priv->monitor_port; -+ mutex_unlock(&priv->reg_mutex); -+ return 0; -+} -+ -+static int -+ar40xx_sw_set_mirror_source_port(struct switch_dev *dev, -+ const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ mutex_lock(&priv->reg_mutex); -+ priv->source_port = val->value.i; -+ ar40xx_set_mirror_regs(priv); -+ mutex_unlock(&priv->reg_mutex); -+ -+ return 0; -+} -+ -+static int -+ar40xx_sw_get_mirror_source_port(struct switch_dev *dev, -+ const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ mutex_lock(&priv->reg_mutex); -+ val->value.i = priv->source_port; -+ mutex_unlock(&priv->reg_mutex); -+ return 0; -+} -+ -+static int -+ar40xx_sw_set_linkdown(struct switch_dev *dev, -+ const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ if (val->value.i == 1) -+ ar40xx_port_phy_linkdown(priv); -+ else -+ ar40xx_phy_init(priv); -+ -+ return 0; -+} -+ -+static int -+ar40xx_sw_set_port_reset_mib(struct switch_dev *dev, -+ const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ int port; -+ int ret; -+ -+ port = val->port_vlan; -+ if (port >= dev->ports) -+ return -EINVAL; -+ -+ mutex_lock(&priv->mib_lock); -+ ret = ar40xx_mib_capture(priv); -+ if (ret) -+ goto unlock; -+ -+ ar40xx_mib_fetch_port_stat(priv, port, true); -+ -+unlock: -+ mutex_unlock(&priv->mib_lock); -+ return ret; -+} -+ -+static int -+ar40xx_sw_get_port_mib(struct switch_dev *dev, -+ const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ u64 *mib_stats; -+ int port; -+ int ret; -+ char *buf = priv->buf; -+ int i, len = 0; -+ u32 num_mibs = ARRAY_SIZE(ar40xx_mibs); -+ -+ port = val->port_vlan; -+ if (port >= dev->ports) -+ return -EINVAL; -+ -+ mutex_lock(&priv->mib_lock); -+ ret = ar40xx_mib_capture(priv); -+ if (ret) -+ goto unlock; -+ -+ ar40xx_mib_fetch_port_stat(priv, port, false); -+ -+ len += snprintf(buf + len, sizeof(priv->buf) - len, -+ "Port %d MIB counters\n", -+ port); -+ -+ mib_stats = &priv->mib_stats[port * num_mibs]; -+ for (i = 0; i < num_mibs; i++) -+ len += snprintf(buf + len, sizeof(priv->buf) - len, -+ "%-12s: %llu\n", -+ ar40xx_mibs[i].name, -+ mib_stats[i]); -+ -+ val->value.s = buf; -+ val->len = len; -+ -+unlock: -+ mutex_unlock(&priv->mib_lock); -+ return ret; -+} -+ -+static int -+ar40xx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ priv->vlan_id[val->port_vlan] = val->value.i; -+ return 0; -+} -+ -+static int -+ar40xx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ val->value.i = priv->vlan_id[val->port_vlan]; -+ return 0; -+} -+ -+static int -+ar40xx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ *vlan = priv->pvid[port]; -+ return 0; -+} -+ -+static int -+ar40xx_sw_set_pvid(struct switch_dev *dev, int port, int vlan) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ /* make sure no invalid PVIDs get set */ -+ if (vlan >= dev->vlans) -+ return -EINVAL; -+ -+ priv->pvid[port] = vlan; -+ return 0; -+} -+ -+static void -+ar40xx_read_port_link(struct ar40xx_priv *priv, int port, -+ struct switch_port_link *link) -+{ -+ u32 status; -+ u32 speed; -+ -+ memset(link, 0, sizeof(*link)); -+ -+ status = ar40xx_read(priv, AR40XX_REG_PORT_STATUS(port)); -+ -+ link->aneg = !!(status & AR40XX_PORT_AUTO_LINK_EN); -+ if (link->aneg || (port != AR40XX_PORT_CPU)) -+ link->link = !!(status & AR40XX_PORT_STATUS_LINK_UP); -+ else -+ link->link = true; -+ -+ if (!link->link) -+ return; -+ -+ link->duplex = !!(status & AR40XX_PORT_DUPLEX); -+ link->tx_flow = !!(status & AR40XX_PORT_STATUS_TXFLOW); -+ link->rx_flow = !!(status & AR40XX_PORT_STATUS_RXFLOW); -+ -+ speed = (status & AR40XX_PORT_SPEED) >> -+ AR40XX_PORT_STATUS_SPEED_S; -+ -+ switch (speed) { -+ case AR40XX_PORT_SPEED_10M: -+ link->speed = SWITCH_PORT_SPEED_10; -+ break; -+ case AR40XX_PORT_SPEED_100M: -+ link->speed = SWITCH_PORT_SPEED_100; -+ break; -+ case AR40XX_PORT_SPEED_1000M: -+ link->speed = SWITCH_PORT_SPEED_1000; -+ break; -+ default: -+ link->speed = SWITCH_PORT_SPEED_UNKNOWN; -+ break; -+ } -+} -+ -+static int -+ar40xx_sw_get_port_link(struct switch_dev *dev, int port, -+ struct switch_port_link *link) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ -+ ar40xx_read_port_link(priv, port, link); -+ return 0; -+} -+ -+static const struct switch_attr ar40xx_sw_attr_globals[] = { -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "enable_vlan", -+ .description = "Enable VLAN mode", -+ .set = ar40xx_sw_set_vlan, -+ .get = ar40xx_sw_get_vlan, -+ .max = 1 -+ }, -+ { -+ .type = SWITCH_TYPE_NOVAL, -+ .name = "reset_mibs", -+ .description = "Reset all MIB counters", -+ .set = ar40xx_sw_set_reset_mibs, -+ }, -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "enable_mirror_rx", -+ .description = "Enable mirroring of RX packets", -+ .set = ar40xx_sw_set_mirror_rx_enable, -+ .get = ar40xx_sw_get_mirror_rx_enable, -+ .max = 1 -+ }, -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "enable_mirror_tx", -+ .description = "Enable mirroring of TX packets", -+ .set = ar40xx_sw_set_mirror_tx_enable, -+ .get = ar40xx_sw_get_mirror_tx_enable, -+ .max = 1 -+ }, -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "mirror_monitor_port", -+ .description = "Mirror monitor port", -+ .set = ar40xx_sw_set_mirror_monitor_port, -+ .get = ar40xx_sw_get_mirror_monitor_port, -+ .max = AR40XX_NUM_PORTS - 1 -+ }, -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "mirror_source_port", -+ .description = "Mirror source port", -+ .set = ar40xx_sw_set_mirror_source_port, -+ .get = ar40xx_sw_get_mirror_source_port, -+ .max = AR40XX_NUM_PORTS - 1 -+ }, -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "linkdown", -+ .description = "Link down all the PHYs", -+ .set = ar40xx_sw_set_linkdown, -+ .max = 1 -+ }, -+}; -+ -+static const struct switch_attr ar40xx_sw_attr_port[] = { -+ { -+ .type = SWITCH_TYPE_NOVAL, -+ .name = "reset_mib", -+ .description = "Reset single port MIB counters", -+ .set = ar40xx_sw_set_port_reset_mib, -+ }, -+ { -+ .type = SWITCH_TYPE_STRING, -+ .name = "mib", -+ .description = "Get port's MIB counters", -+ .set = NULL, -+ .get = ar40xx_sw_get_port_mib, -+ }, -+}; -+ -+const struct switch_attr ar40xx_sw_attr_vlan[] = { -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "vid", -+ .description = "VLAN ID (0-4094)", -+ .set = ar40xx_sw_set_vid, -+ .get = ar40xx_sw_get_vid, -+ .max = 4094, -+ }, -+}; -+ -+/* End of swconfig support */ -+ -+static int -+ar40xx_wait_bit(struct ar40xx_priv *priv, int reg, u32 mask, u32 val) -+{ -+ int timeout = 20; -+ u32 t; -+ -+ while (1) { -+ t = ar40xx_read(priv, reg); -+ if ((t & mask) == val) -+ return 0; -+ -+ if (timeout-- <= 0) -+ break; -+ -+ usleep_range(10, 20); -+ } -+ -+ pr_err("ar40xx: timeout for reg %08x: %08x & %08x != %08x\n", -+ (unsigned int)reg, t, mask, val); -+ return -ETIMEDOUT; -+} -+ -+static int -+ar40xx_atu_flush(struct ar40xx_priv *priv) -+{ -+ int ret; -+ -+ ret = ar40xx_wait_bit(priv, AR40XX_REG_ATU_FUNC, -+ AR40XX_ATU_FUNC_BUSY, 0); -+ if (!ret) -+ ar40xx_write(priv, AR40XX_REG_ATU_FUNC, -+ AR40XX_ATU_FUNC_OP_FLUSH | -+ AR40XX_ATU_FUNC_BUSY); -+ -+ return ret; -+} -+ -+static void -+ar40xx_ess_reset(struct ar40xx_priv *priv) -+{ -+ reset_control_assert(priv->ess_rst); -+ mdelay(10); -+ reset_control_deassert(priv->ess_rst); -+ /* Waiting for all inner tables init done. -+ * It cost 5~10ms. -+ */ -+ mdelay(10); -+ -+ pr_info("ESS reset ok!\n"); -+} -+ -+/* Start of psgmii self test */ -+ -+static void -+ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv) -+{ -+ u32 n; -+ struct mii_bus *bus = priv->mii_bus; -+ /* reset phy psgmii */ -+ /* fix phy psgmii RX 20bit */ -+ mdiobus_write(bus, 5, 0x0, 0x005b); -+ /* reset phy psgmii */ -+ mdiobus_write(bus, 5, 0x0, 0x001b); -+ /* release reset phy psgmii */ -+ mdiobus_write(bus, 5, 0x0, 0x005b); -+ -+ for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) { -+ u16 status; -+ -+ status = ar40xx_phy_mmd_read(priv, 5, 1, 0x28); -+ if (status & BIT(0)) -+ break; -+ /* Polling interval to check PSGMII PLL in malibu is ready -+ * the worst time is 8.67ms -+ * for 25MHz reference clock -+ * [512+(128+2048)*49]*80ns+100us -+ */ -+ mdelay(2); -+ } -+ -+ /*check malibu psgmii calibration done end..*/ -+ -+ /*freeze phy psgmii RX CDR*/ -+ mdiobus_write(bus, 5, 0x1a, 0x2230); -+ -+ ar40xx_ess_reset(priv); -+ -+ /*check psgmii calibration done start*/ -+ for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) { -+ u32 status; -+ -+ status = ar40xx_psgmii_read(priv, 0xa0); -+ if (status & BIT(0)) -+ break; -+ /* Polling interval to check PSGMII PLL in ESS is ready */ -+ mdelay(2); -+ } -+ -+ /* check dakota psgmii calibration done end..*/ -+ -+ /* relesae phy psgmii RX CDR */ -+ mdiobus_write(bus, 5, 0x1a, 0x3230); -+ /* release phy psgmii RX 20bit */ -+ mdiobus_write(bus, 5, 0x0, 0x005f); -+} -+ -+static void -+ar40xx_psgmii_single_phy_testing(struct ar40xx_priv *priv, int phy) -+{ -+ int j; -+ u32 tx_ok, tx_error; -+ u32 rx_ok, rx_error; -+ u32 tx_ok_high16; -+ u32 rx_ok_high16; -+ u32 tx_all_ok, rx_all_ok; -+ struct mii_bus *bus = priv->mii_bus; -+ -+ mdiobus_write(bus, phy, 0x0, 0x9000); -+ mdiobus_write(bus, phy, 0x0, 0x4140); -+ -+ for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) { -+ u16 status; -+ -+ status = mdiobus_read(bus, phy, 0x11); -+ if (status & AR40XX_PHY_SPEC_STATUS_LINK) -+ break; -+ /* the polling interval to check if the PHY link up or not -+ * maxwait_timer: 750 ms +/-10 ms -+ * minwait_timer : 1 us +/- 0.1us -+ * time resides in minwait_timer ~ maxwait_timer -+ * see IEEE 802.3 section 40.4.5.2 -+ */ -+ mdelay(8); -+ } -+ -+ /* enable check */ -+ ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0000); -+ ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0003); -+ -+ /* start traffic */ -+ ar40xx_phy_mmd_write(priv, phy, 7, 0x8020, 0xa000); -+ /* wait for all traffic end -+ * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms -+ */ -+ mdelay(50); -+ -+ /* check counter */ -+ tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e); -+ tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d); -+ tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f); -+ rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b); -+ rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a); -+ rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c); -+ tx_all_ok = tx_ok + (tx_ok_high16 << 16); -+ rx_all_ok = rx_ok + (rx_ok_high16 << 16); -+ if (tx_all_ok == 0x1000 && tx_error == 0) { -+ /* success */ -+ priv->phy_t_status &= (~BIT(phy)); -+ } else { -+ pr_info("PHY %d single test PSGMII issue happen!\n", phy); -+ priv->phy_t_status |= BIT(phy); -+ } -+ -+ mdiobus_write(bus, phy, 0x0, 0x1840); -+} -+ -+static void -+ar40xx_psgmii_all_phy_testing(struct ar40xx_priv *priv) -+{ -+ int phy, j; -+ struct mii_bus *bus = priv->mii_bus; -+ -+ mdiobus_write(bus, 0x1f, 0x0, 0x9000); -+ mdiobus_write(bus, 0x1f, 0x0, 0x4140); -+ -+ for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) { -+ for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { -+ u16 status; -+ -+ status = mdiobus_read(bus, phy, 0x11); -+ if (!(status & BIT(10))) -+ break; -+ } -+ -+ if (phy >= (AR40XX_NUM_PORTS - 1)) -+ break; -+ /* The polling interva to check if the PHY link up or not */ -+ mdelay(8); -+ } -+ /* enable check */ -+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0000); -+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0003); -+ -+ /* start traffic */ -+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0xa000); -+ /* wait for all traffic end -+ * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms -+ */ -+ mdelay(50); -+ -+ for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { -+ u32 tx_ok, tx_error; -+ u32 rx_ok, rx_error; -+ u32 tx_ok_high16; -+ u32 rx_ok_high16; -+ u32 tx_all_ok, rx_all_ok; -+ -+ /* check counter */ -+ tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e); -+ tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d); -+ tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f); -+ rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b); -+ rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a); -+ rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c); -+ tx_all_ok = tx_ok + (tx_ok_high16<<16); -+ rx_all_ok = rx_ok + (rx_ok_high16<<16); -+ if (tx_all_ok == 0x1000 && tx_error == 0) { -+ /* success */ -+ priv->phy_t_status &= ~BIT(phy + 8); -+ } else { -+ pr_info("PHY%d test see issue!\n", phy); -+ priv->phy_t_status |= BIT(phy + 8); -+ } -+ } -+ -+ pr_debug("PHY all test 0x%x \r\n", priv->phy_t_status); -+} -+ -+void -+ar40xx_psgmii_self_test(struct ar40xx_priv *priv) -+{ -+ u32 i, phy; -+ struct mii_bus *bus = priv->mii_bus; -+ -+ ar40xx_malibu_psgmii_ess_reset(priv); -+ -+ /* switch to access MII reg for copper */ -+ mdiobus_write(bus, 4, 0x1f, 0x8500); -+ for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { -+ /*enable phy mdio broadcast write*/ -+ ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x801f); -+ } -+ /* force no link by power down */ -+ mdiobus_write(bus, 0x1f, 0x0, 0x1840); -+ /*packet number*/ -+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x1000); -+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8062, 0x05e0); -+ -+ /*fix mdi status */ -+ mdiobus_write(bus, 0x1f, 0x10, 0x6800); -+ for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) { -+ priv->phy_t_status = 0; -+ -+ for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { -+ ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1), -+ AR40XX_PORT_LOOKUP_LOOPBACK, -+ AR40XX_PORT_LOOKUP_LOOPBACK); -+ } -+ -+ for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) -+ ar40xx_psgmii_single_phy_testing(priv, phy); -+ -+ ar40xx_psgmii_all_phy_testing(priv); -+ -+ if (priv->phy_t_status) -+ ar40xx_malibu_psgmii_ess_reset(priv); -+ else -+ break; -+ } -+ -+ if (i >= AR40XX_PSGMII_CALB_NUM) -+ pr_info("PSGMII cannot recover\n"); -+ else -+ pr_debug("PSGMII recovered after %d times reset\n", i); -+ -+ /* configuration recover */ -+ /* packet number */ -+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x0); -+ /* disable check */ -+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0); -+ /* disable traffic */ -+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0x0); -+} -+ -+void -+ar40xx_psgmii_self_test_clean(struct ar40xx_priv *priv) -+{ -+ int phy; -+ struct mii_bus *bus = priv->mii_bus; -+ -+ /* disable phy internal loopback */ -+ mdiobus_write(bus, 0x1f, 0x10, 0x6860); -+ mdiobus_write(bus, 0x1f, 0x0, 0x9040); -+ -+ for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { -+ /* disable mac loop back */ -+ ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1), -+ AR40XX_PORT_LOOKUP_LOOPBACK, 0); -+ /* disable phy mdio broadcast write */ -+ ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x001f); -+ } -+ -+ /* clear fdb entry */ -+ ar40xx_atu_flush(priv); -+} -+ -+/* End of psgmii self test */ -+ -+static void -+ar40xx_mac_mode_init(struct ar40xx_priv *priv, u32 mode) -+{ -+ if (mode == PORT_WRAPPER_PSGMII) { -+ ar40xx_psgmii_write(priv, AR40XX_PSGMII_MODE_CONTROL, 0x2200); -+ ar40xx_psgmii_write(priv, AR40XX_PSGMIIPHY_TX_CONTROL, 0x8380); -+ } -+} -+ -+static -+int ar40xx_cpuport_setup(struct ar40xx_priv *priv) -+{ -+ u32 t; -+ -+ t = AR40XX_PORT_STATUS_TXFLOW | -+ AR40XX_PORT_STATUS_RXFLOW | -+ AR40XX_PORT_TXHALF_FLOW | -+ AR40XX_PORT_DUPLEX | -+ AR40XX_PORT_SPEED_1000M; -+ ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t); -+ usleep_range(10, 20); -+ -+ t |= AR40XX_PORT_TX_EN | -+ AR40XX_PORT_RX_EN; -+ ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t); -+ -+ return 0; -+} -+ -+static void -+ar40xx_init_port(struct ar40xx_priv *priv, int port) -+{ -+ u32 t; -+ -+ ar40xx_rmw(priv, AR40XX_REG_PORT_STATUS(port), -+ AR40XX_PORT_AUTO_LINK_EN, 0); -+ -+ ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0); -+ -+ ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), 0); -+ -+ t = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH << AR40XX_PORT_VLAN1_OUT_MODE_S; -+ ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t); -+ -+ t = AR40XX_PORT_LOOKUP_LEARN; -+ t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S; -+ ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t); -+} -+ -+void -+ar40xx_init_globals(struct ar40xx_priv *priv) -+{ -+ u32 t; -+ -+ /* enable CPU port and disable mirror port */ -+ t = AR40XX_FWD_CTRL0_CPU_PORT_EN | -+ AR40XX_FWD_CTRL0_MIRROR_PORT; -+ ar40xx_write(priv, AR40XX_REG_FWD_CTRL0, t); -+ -+ /* forward multicast and broadcast frames to CPU */ -+ t = (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_UC_FLOOD_S) | -+ (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_MC_FLOOD_S) | -+ (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_BC_FLOOD_S); -+ ar40xx_write(priv, AR40XX_REG_FWD_CTRL1, t); -+ -+ /* enable jumbo frames */ -+ ar40xx_rmw(priv, AR40XX_REG_MAX_FRAME_SIZE, -+ AR40XX_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2); -+ -+ /* Enable MIB counters */ -+ ar40xx_rmw(priv, AR40XX_REG_MODULE_EN, 0, -+ AR40XX_MODULE_EN_MIB); -+ -+ /* Disable AZ */ -+ ar40xx_write(priv, AR40XX_REG_EEE_CTRL, 0); -+ -+ /* set flowctrl thershold for cpu port */ -+ t = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16) | -+ AR40XX_PORT0_FC_THRESH_OFF_DFLT; -+ ar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t); -+} -+ -+static void -+ar40xx_malibu_init(struct ar40xx_priv *priv) -+{ -+ int i; -+ struct mii_bus *bus; -+ u16 val; -+ -+ bus = priv->mii_bus; -+ -+ /* war to enable AZ transmitting ability */ -+ ar40xx_phy_mmd_write(priv, AR40XX_PSGMII_ID, 1, -+ AR40XX_MALIBU_PSGMII_MODE_CTRL, -+ AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL); -+ for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) { -+ /* change malibu control_dac */ -+ val = ar40xx_phy_mmd_read(priv, i, 7, -+ AR40XX_MALIBU_PHY_MMD7_DAC_CTRL); -+ val &= ~AR40XX_MALIBU_DAC_CTRL_MASK; -+ val |= AR40XX_MALIBU_DAC_CTRL_VALUE; -+ ar40xx_phy_mmd_write(priv, i, 7, -+ AR40XX_MALIBU_PHY_MMD7_DAC_CTRL, val); -+ if (i == AR40XX_MALIBU_PHY_LAST_ADDR) { -+ /* to avoid goes into hibernation */ -+ val = ar40xx_phy_mmd_read(priv, i, 3, -+ AR40XX_MALIBU_PHY_RLP_CTRL); -+ val &= (~(1<<1)); -+ ar40xx_phy_mmd_write(priv, i, 3, -+ AR40XX_MALIBU_PHY_RLP_CTRL, val); -+ } -+ } -+ -+ /* adjust psgmii serdes tx amp */ -+ mdiobus_write(bus, AR40XX_PSGMII_ID, AR40XX_PSGMII_TX_DRIVER_1_CTRL, -+ AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP); -+} -+ -+static int -+ar40xx_hw_init(struct ar40xx_priv *priv) -+{ -+ u32 i; -+ -+ ar40xx_ess_reset(priv); -+ -+ if (priv->mii_bus) -+ ar40xx_malibu_init(priv); -+ else -+ return -1; -+ -+ ar40xx_psgmii_self_test(priv); -+ ar40xx_psgmii_self_test_clean(priv); -+ -+ ar40xx_mac_mode_init(priv, priv->mac_mode); -+ -+ for (i = 0; i < priv->dev.ports; i++) -+ ar40xx_init_port(priv, i); -+ -+ ar40xx_init_globals(priv); -+ -+ return 0; -+} -+ -+/* Start of qm error WAR */ -+ -+static -+int ar40xx_force_1g_full(struct ar40xx_priv *priv, u32 port_id) -+{ -+ u32 reg; -+ -+ if (port_id < 0 || port_id > 6) -+ return -1; -+ -+ reg = AR40XX_REG_PORT_STATUS(port_id); -+ return ar40xx_rmw(priv, reg, AR40XX_PORT_SPEED, -+ (AR40XX_PORT_SPEED_1000M | AR40XX_PORT_DUPLEX)); -+} -+ -+static -+int ar40xx_get_qm_status(struct ar40xx_priv *priv, -+ u32 port_id, u32 *qm_buffer_err) -+{ -+ u32 reg; -+ u32 qm_val; -+ -+ if (port_id < 1 || port_id > 5) { -+ *qm_buffer_err = 0; -+ return -1; -+ } -+ -+ if (port_id < 4) { -+ reg = AR40XX_REG_QM_PORT0_3_QNUM; -+ ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg); -+ qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE); -+ /* every 8 bits for each port */ -+ *qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF; -+ } else { -+ reg = AR40XX_REG_QM_PORT4_6_QNUM; -+ ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg); -+ qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE); -+ /* every 8 bits for each port */ -+ *qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF; -+ } -+ -+ return 0; -+} -+ -+static void -+ar40xx_sw_mac_polling_task(struct ar40xx_priv *priv) -+{ -+ static int task_count; -+ u32 i; -+ u32 reg, value; -+ u32 link, speed, duplex; -+ u32 qm_buffer_err; -+ u16 port_phy_status[AR40XX_NUM_PORTS]; -+ static u32 qm_err_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0}; -+ static u32 link_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0}; -+ struct mii_bus *bus = NULL; -+ -+ if (!priv || !priv->mii_bus) -+ return; -+ -+ bus = priv->mii_bus; -+ -+ ++task_count; -+ -+ for (i = 1; i < AR40XX_NUM_PORTS; ++i) { -+ port_phy_status[i] = -+ mdiobus_read(bus, i-1, AR40XX_PHY_SPEC_STATUS); -+ speed = link = duplex = port_phy_status[i]; -+ speed &= AR40XX_PHY_SPEC_STATUS_SPEED; -+ speed >>= 14; -+ link &= AR40XX_PHY_SPEC_STATUS_LINK; -+ link >>= 10; -+ duplex &= AR40XX_PHY_SPEC_STATUS_DUPLEX; -+ duplex >>= 13; -+ -+ if (link != priv->ar40xx_port_old_link[i]) { -+ ++link_cnt[i]; -+ /* Up --> Down */ -+ if ((priv->ar40xx_port_old_link[i] == -+ AR40XX_PORT_LINK_UP) && -+ (link == AR40XX_PORT_LINK_DOWN)) { -+ /* LINK_EN disable(MAC force mode)*/ -+ reg = AR40XX_REG_PORT_STATUS(i); -+ ar40xx_rmw(priv, reg, -+ AR40XX_PORT_AUTO_LINK_EN, 0); -+ -+ /* Check queue buffer */ -+ qm_err_cnt[i] = 0; -+ ar40xx_get_qm_status(priv, i, &qm_buffer_err); -+ if (qm_buffer_err) { -+ priv->ar40xx_port_qm_buf[i] = -+ AR40XX_QM_NOT_EMPTY; -+ } else { -+ u16 phy_val = 0; -+ -+ priv->ar40xx_port_qm_buf[i] = -+ AR40XX_QM_EMPTY; -+ ar40xx_force_1g_full(priv, i); -+ /* Ref:QCA8337 Datasheet,Clearing -+ * MENU_CTRL_EN prevents phy to -+ * stuck in 100BT mode when -+ * bringing up the link -+ */ -+ ar40xx_phy_dbg_read(priv, i-1, -+ AR40XX_PHY_DEBUG_0, -+ &phy_val); -+ phy_val &= (~AR40XX_PHY_MANU_CTRL_EN); -+ ar40xx_phy_dbg_write(priv, i-1, -+ AR40XX_PHY_DEBUG_0, -+ phy_val); -+ } -+ priv->ar40xx_port_old_link[i] = link; -+ } else if ((priv->ar40xx_port_old_link[i] == -+ AR40XX_PORT_LINK_DOWN) && -+ (link == AR40XX_PORT_LINK_UP)) { -+ /* Down --> Up */ -+ if (priv->port_link_up[i] < 1) { -+ ++priv->port_link_up[i]; -+ } else { -+ /* Change port status */ -+ reg = AR40XX_REG_PORT_STATUS(i); -+ value = ar40xx_read(priv, reg); -+ priv->port_link_up[i] = 0; -+ -+ value &= ~(AR40XX_PORT_DUPLEX | -+ AR40XX_PORT_SPEED); -+ value |= speed | (duplex ? BIT(6) : 0); -+ ar40xx_write(priv, reg, value); -+ /* clock switch need such time -+ * to avoid glitch -+ */ -+ usleep_range(100, 200); -+ -+ value |= AR40XX_PORT_AUTO_LINK_EN; -+ ar40xx_write(priv, reg, value); -+ /* HW need such time to make sure link -+ * stable before enable MAC -+ */ -+ usleep_range(100, 200); -+ -+ if (speed == AR40XX_PORT_SPEED_100M) { -+ u16 phy_val = 0; -+ /* Enable @100M, if down to 10M -+ * clock will change smoothly -+ */ -+ ar40xx_phy_dbg_read(priv, i-1, -+ 0, -+ &phy_val); -+ phy_val |= -+ AR40XX_PHY_MANU_CTRL_EN; -+ ar40xx_phy_dbg_write(priv, i-1, -+ 0, -+ phy_val); -+ } -+ priv->ar40xx_port_old_link[i] = link; -+ } -+ } -+ } -+ -+ if (priv->ar40xx_port_qm_buf[i] == AR40XX_QM_NOT_EMPTY) { -+ /* Check QM */ -+ ar40xx_get_qm_status(priv, i, &qm_buffer_err); -+ if (qm_buffer_err) { -+ ++qm_err_cnt[i]; -+ } else { -+ priv->ar40xx_port_qm_buf[i] = -+ AR40XX_QM_EMPTY; -+ qm_err_cnt[i] = 0; -+ ar40xx_force_1g_full(priv, i); -+ } -+ } -+ } -+} -+ -+static void -+ar40xx_qm_err_check_work_task(struct work_struct *work) -+{ -+ struct ar40xx_priv *priv = container_of(work, struct ar40xx_priv, -+ qm_dwork.work); -+ -+ mutex_lock(&priv->qm_lock); -+ -+ ar40xx_sw_mac_polling_task(priv); -+ -+ mutex_unlock(&priv->qm_lock); -+ -+ schedule_delayed_work(&priv->qm_dwork, -+ msecs_to_jiffies(AR40XX_QM_WORK_DELAY)); -+} -+ -+static int -+ar40xx_qm_err_check_work_start(struct ar40xx_priv *priv) -+{ -+ mutex_init(&priv->qm_lock); -+ -+ INIT_DELAYED_WORK(&priv->qm_dwork, ar40xx_qm_err_check_work_task); -+ -+ schedule_delayed_work(&priv->qm_dwork, -+ msecs_to_jiffies(AR40XX_QM_WORK_DELAY)); -+ -+ return 0; -+} -+ -+/* End of qm error WAR */ -+ -+static int -+ar40xx_vlan_init(struct ar40xx_priv *priv) -+{ -+ int port; -+ unsigned long bmp; -+ -+ /* By default Enable VLAN */ -+ priv->vlan = 1; -+ priv->vlan_table[AR40XX_LAN_VLAN] = priv->cpu_bmp | priv->lan_bmp; -+ priv->vlan_table[AR40XX_WAN_VLAN] = priv->cpu_bmp | priv->wan_bmp; -+ priv->vlan_tagged = priv->cpu_bmp; -+ bmp = priv->lan_bmp; -+ for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS) -+ priv->pvid[port] = AR40XX_LAN_VLAN; -+ -+ bmp = priv->wan_bmp; -+ for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS) -+ priv->pvid[port] = AR40XX_WAN_VLAN; -+ -+ return 0; -+} -+ -+static void -+ar40xx_mib_work_func(struct work_struct *work) -+{ -+ struct ar40xx_priv *priv; -+ int err; -+ -+ priv = container_of(work, struct ar40xx_priv, mib_work.work); -+ -+ mutex_lock(&priv->mib_lock); -+ -+ err = ar40xx_mib_capture(priv); -+ if (err) -+ goto next_port; -+ -+ ar40xx_mib_fetch_port_stat(priv, priv->mib_next_port, false); -+ -+next_port: -+ priv->mib_next_port++; -+ if (priv->mib_next_port >= priv->dev.ports) -+ priv->mib_next_port = 0; -+ -+ mutex_unlock(&priv->mib_lock); -+ -+ schedule_delayed_work(&priv->mib_work, -+ msecs_to_jiffies(AR40XX_MIB_WORK_DELAY)); -+} -+ -+static void -+ar40xx_setup_port(struct ar40xx_priv *priv, int port, u32 members) -+{ -+ u32 t; -+ u32 egress, ingress; -+ u32 pvid = priv->vlan_id[priv->pvid[port]]; -+ -+ if (priv->vlan) { -+ egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD; -+ ingress = AR40XX_IN_SECURE; -+ } else { -+ egress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH; -+ ingress = AR40XX_IN_PORT_ONLY; -+ } -+ -+ t = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S; -+ t |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S; -+ ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), t); -+ -+ t = AR40XX_PORT_VLAN1_PORT_VLAN_PROP; -+ t |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S; -+ ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t); -+ -+ t = members; -+ t |= AR40XX_PORT_LOOKUP_LEARN; -+ t |= ingress << AR40XX_PORT_LOOKUP_IN_MODE_S; -+ t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S; -+ ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t); -+} -+ -+static void -+ar40xx_vtu_op(struct ar40xx_priv *priv, u32 op, u32 val) -+{ -+ if (ar40xx_wait_bit(priv, AR40XX_REG_VTU_FUNC1, -+ AR40XX_VTU_FUNC1_BUSY, 0)) -+ return; -+ -+ if ((op & AR40XX_VTU_FUNC1_OP) == AR40XX_VTU_FUNC1_OP_LOAD) -+ ar40xx_write(priv, AR40XX_REG_VTU_FUNC0, val); -+ -+ op |= AR40XX_VTU_FUNC1_BUSY; -+ ar40xx_write(priv, AR40XX_REG_VTU_FUNC1, op); -+} -+ -+static void -+ar40xx_vtu_load_vlan(struct ar40xx_priv *priv, u32 vid, u32 port_mask) -+{ -+ u32 op; -+ u32 val; -+ int i; -+ -+ op = AR40XX_VTU_FUNC1_OP_LOAD | (vid << AR40XX_VTU_FUNC1_VID_S); -+ val = AR40XX_VTU_FUNC0_VALID | AR40XX_VTU_FUNC0_IVL; -+ for (i = 0; i < AR40XX_NUM_PORTS; i++) { -+ u32 mode; -+ -+ if ((port_mask & BIT(i)) == 0) -+ mode = AR40XX_VTU_FUNC0_EG_MODE_NOT; -+ else if (priv->vlan == 0) -+ mode = AR40XX_VTU_FUNC0_EG_MODE_KEEP; -+ else if ((priv->vlan_tagged & BIT(i)) || -+ (priv->vlan_id[priv->pvid[i]] != vid)) -+ mode = AR40XX_VTU_FUNC0_EG_MODE_TAG; -+ else -+ mode = AR40XX_VTU_FUNC0_EG_MODE_UNTAG; -+ -+ val |= mode << AR40XX_VTU_FUNC0_EG_MODE_S(i); -+ } -+ ar40xx_vtu_op(priv, op, val); -+} -+ -+static void -+ar40xx_vtu_flush(struct ar40xx_priv *priv) -+{ -+ ar40xx_vtu_op(priv, AR40XX_VTU_FUNC1_OP_FLUSH, 0); -+} -+ -+static int -+ar40xx_sw_hw_apply(struct switch_dev *dev) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ u8 portmask[AR40XX_NUM_PORTS]; -+ int i, j; -+ -+ mutex_lock(&priv->reg_mutex); -+ /* flush all vlan entries */ -+ ar40xx_vtu_flush(priv); -+ -+ memset(portmask, 0, sizeof(portmask)); -+ if (priv->vlan) { -+ for (j = 0; j < AR40XX_MAX_VLANS; j++) { -+ u8 vp = priv->vlan_table[j]; -+ -+ if (!vp) -+ continue; -+ -+ for (i = 0; i < dev->ports; i++) { -+ u8 mask = BIT(i); -+ -+ if (vp & mask) -+ portmask[i] |= vp & ~mask; -+ } -+ -+ ar40xx_vtu_load_vlan(priv, priv->vlan_id[j], -+ priv->vlan_table[j]); -+ } -+ } else { -+ /* 8021q vlan disabled */ -+ for (i = 0; i < dev->ports; i++) { -+ if (i == AR40XX_PORT_CPU) -+ continue; -+ -+ portmask[i] = BIT(AR40XX_PORT_CPU); -+ portmask[AR40XX_PORT_CPU] |= BIT(i); -+ } -+ } -+ -+ /* update the port destination mask registers and tag settings */ -+ for (i = 0; i < dev->ports; i++) -+ ar40xx_setup_port(priv, i, portmask[i]); -+ -+ ar40xx_set_mirror_regs(priv); -+ -+ mutex_unlock(&priv->reg_mutex); -+ return 0; -+} -+ -+static int -+ar40xx_sw_reset_switch(struct switch_dev *dev) -+{ -+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev); -+ int i, rv; -+ -+ mutex_lock(&priv->reg_mutex); -+ memset(&priv->vlan, 0, sizeof(struct ar40xx_priv) - -+ offsetof(struct ar40xx_priv, vlan)); -+ -+ for (i = 0; i < AR40XX_MAX_VLANS; i++) -+ priv->vlan_id[i] = i; -+ -+ ar40xx_vlan_init(priv); -+ -+ priv->mirror_rx = false; -+ priv->mirror_tx = false; -+ priv->source_port = 0; -+ priv->monitor_port = 0; -+ -+ mutex_unlock(&priv->reg_mutex); -+ -+ rv = ar40xx_sw_hw_apply(dev); -+ return rv; -+} -+ -+static int -+ar40xx_start(struct ar40xx_priv *priv) -+{ -+ int ret; -+ -+ ret = ar40xx_hw_init(priv); -+ if (ret) -+ return ret; -+ -+ ret = ar40xx_sw_reset_switch(&priv->dev); -+ if (ret) -+ return ret; -+ -+ /* at last, setup cpu port */ -+ ret = ar40xx_cpuport_setup(priv); -+ if (ret) -+ return ret; -+ -+ schedule_delayed_work(&priv->mib_work, -+ msecs_to_jiffies(AR40XX_MIB_WORK_DELAY)); -+ -+ ar40xx_qm_err_check_work_start(priv); -+ -+ return 0; -+} -+ -+static const struct switch_dev_ops ar40xx_sw_ops = { -+ .attr_global = { -+ .attr = ar40xx_sw_attr_globals, -+ .n_attr = ARRAY_SIZE(ar40xx_sw_attr_globals), -+ }, -+ .attr_port = { -+ .attr = ar40xx_sw_attr_port, -+ .n_attr = ARRAY_SIZE(ar40xx_sw_attr_port), -+ }, -+ .attr_vlan = { -+ .attr = ar40xx_sw_attr_vlan, -+ .n_attr = ARRAY_SIZE(ar40xx_sw_attr_vlan), -+ }, -+ .get_port_pvid = ar40xx_sw_get_pvid, -+ .set_port_pvid = ar40xx_sw_set_pvid, -+ .get_vlan_ports = ar40xx_sw_get_ports, -+ .set_vlan_ports = ar40xx_sw_set_ports, -+ .apply_config = ar40xx_sw_hw_apply, -+ .reset_switch = ar40xx_sw_reset_switch, -+ .get_port_link = ar40xx_sw_get_port_link, -+}; -+ -+/* Start of phy driver support */ -+ -+static const u32 ar40xx_phy_ids[] = { -+ 0x004dd0b1, -+ 0x004dd0b2, /* AR40xx */ -+}; -+ -+static bool -+ar40xx_phy_match(u32 phy_id) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(ar40xx_phy_ids); i++) -+ if (phy_id == ar40xx_phy_ids[i]) -+ return true; -+ -+ return false; -+} -+ -+static bool -+is_ar40xx_phy(struct mii_bus *bus) -+{ -+ unsigned i; -+ -+ for (i = 0; i < 4; i++) { -+ u32 phy_id; -+ -+ phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16; -+ phy_id |= mdiobus_read(bus, i, MII_PHYSID2); -+ if (!ar40xx_phy_match(phy_id)) -+ return false; -+ } -+ -+ return true; -+} -+ -+static int -+ar40xx_phy_probe(struct phy_device *phydev) -+{ -+ if (!is_ar40xx_phy(phydev->mdio.bus)) -+ return -ENODEV; -+ -+ ar40xx_priv->mii_bus = phydev->mdio.bus; -+ phydev->priv = ar40xx_priv; -+ if (phydev->mdio.addr == 0) -+ ar40xx_priv->phy = phydev; -+ -+ phydev->supported |= SUPPORTED_1000baseT_Full; -+ phydev->advertising |= ADVERTISED_1000baseT_Full; -+ return 0; -+} -+ -+static void -+ar40xx_phy_remove(struct phy_device *phydev) -+{ -+ ar40xx_priv->mii_bus = NULL; -+ phydev->priv = NULL; -+} -+ -+static int -+ar40xx_phy_config_init(struct phy_device *phydev) -+{ -+ return 0; -+} -+ -+static int -+ar40xx_phy_read_status(struct phy_device *phydev) -+{ -+ if (phydev->mdio.addr != 0) -+ return genphy_read_status(phydev); -+ -+ return 0; -+} -+ -+static int -+ar40xx_phy_config_aneg(struct phy_device *phydev) -+{ -+ if (phydev->mdio.addr == 0) -+ return 0; -+ -+ return genphy_config_aneg(phydev); -+} -+ -+static struct phy_driver ar40xx_phy_driver = { -+ .phy_id = 0x004d0000, -+ .name = "QCA Malibu", -+ .phy_id_mask = 0xffff0000, -+ .features = PHY_BASIC_FEATURES, -+ .probe = ar40xx_phy_probe, -+ .remove = ar40xx_phy_remove, -+ .config_init = ar40xx_phy_config_init, -+ .config_aneg = ar40xx_phy_config_aneg, -+ .read_status = ar40xx_phy_read_status, -+}; -+ -+static uint16_t ar40xx_gpio_get_phy(unsigned int offset) -+{ -+ return offset / 4; -+} -+ -+static uint16_t ar40xx_gpio_get_reg(unsigned int offset) -+{ -+ return 0x8074 + offset % 4; -+} -+ -+static void ar40xx_gpio_set(struct gpio_chip *gc, unsigned int offset, -+ int value) -+{ -+ struct ar40xx_priv *priv = gpiochip_get_data(gc); -+ -+ ar40xx_phy_mmd_write(priv, ar40xx_gpio_get_phy(offset), 0x7, -+ ar40xx_gpio_get_reg(offset), -+ value ? 0xA000 : 0x8000); -+} -+ -+static int ar40xx_gpio_get(struct gpio_chip *gc, unsigned offset) -+{ -+ struct ar40xx_priv *priv = gpiochip_get_data(gc); -+ -+ return ar40xx_phy_mmd_read(priv, ar40xx_gpio_get_phy(offset), 0x7, -+ ar40xx_gpio_get_reg(offset)) == 0xA000; -+} -+ -+static int ar40xx_gpio_get_dir(struct gpio_chip *gc, unsigned offset) -+{ -+ return 0; /* only out direction */ -+} -+ -+static int ar40xx_gpio_dir_out(struct gpio_chip *gc, unsigned offset, -+ int value) -+{ -+ /* -+ * the direction out value is used to set the initial value. -+ * support of this function is required by leds-gpio.c -+ */ -+ ar40xx_gpio_set(gc, offset, value); -+ return 0; -+} -+ -+static void ar40xx_register_gpio(struct device *pdev, -+ struct ar40xx_priv *priv, -+ struct device_node *switch_node) -+{ -+ struct gpio_chip *gc; -+ int err; -+ -+ gc = devm_kzalloc(pdev, sizeof(*gc), GFP_KERNEL); -+ if (!gc) -+ return; -+ -+ gc->label = "ar40xx_gpio", -+ gc->base = -1, -+ gc->ngpio = 5 /* mmd 0 - 4 */ * 4 /* 0x8074 - 0x8077 */, -+ gc->parent = pdev; -+ gc->owner = THIS_MODULE; -+ -+ gc->get_direction = ar40xx_gpio_get_dir; -+ gc->direction_output = ar40xx_gpio_dir_out; -+ gc->get = ar40xx_gpio_get; -+ gc->set = ar40xx_gpio_set; -+ gc->can_sleep = true; -+ gc->label = priv->dev.name; -+ gc->of_node = switch_node; -+ -+ err = devm_gpiochip_add_data(pdev, gc, priv); -+ if (err != 0) -+ dev_err(pdev, "Failed to register gpio %d.\n", err); -+} -+ -+/* End of phy driver support */ -+ -+/* Platform driver probe function */ -+ -+static int ar40xx_probe(struct platform_device *pdev) -+{ -+ struct device_node *switch_node; -+ struct device_node *psgmii_node; -+ const __be32 *mac_mode; -+ struct clk *ess_clk; -+ struct switch_dev *swdev; -+ struct ar40xx_priv *priv; -+ u32 len; -+ u32 num_mibs; -+ struct resource psgmii_base = {0}; -+ struct resource switch_base = {0}; -+ int ret; -+ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, priv); -+ ar40xx_priv = priv; -+ -+ switch_node = of_node_get(pdev->dev.of_node); -+ if (of_address_to_resource(switch_node, 0, &switch_base) != 0) -+ return -EIO; -+ -+ priv->hw_addr = devm_ioremap_resource(&pdev->dev, &switch_base); -+ if (IS_ERR(priv->hw_addr)) { -+ dev_err(&pdev->dev, "Failed to ioremap switch_base!\n"); -+ return PTR_ERR(priv->hw_addr); -+ } -+ -+ /*psgmii dts get*/ -+ psgmii_node = of_find_node_by_name(NULL, "ess-psgmii"); -+ if (!psgmii_node) { -+ dev_err(&pdev->dev, "Failed to find ess-psgmii node!\n"); -+ return -EINVAL; -+ } -+ -+ if (of_address_to_resource(psgmii_node, 0, &psgmii_base) != 0) -+ return -EIO; -+ -+ priv->psgmii_hw_addr = devm_ioremap_resource(&pdev->dev, &psgmii_base); -+ if (IS_ERR(priv->psgmii_hw_addr)) { -+ dev_err(&pdev->dev, "psgmii ioremap fail!\n"); -+ return PTR_ERR(priv->psgmii_hw_addr); -+ } -+ -+ mac_mode = of_get_property(switch_node, "switch_mac_mode", &len); -+ if (!mac_mode) { -+ dev_err(&pdev->dev, "Failed to read switch_mac_mode\n"); -+ return -EINVAL; -+ } -+ priv->mac_mode = be32_to_cpup(mac_mode); -+ -+ ess_clk = of_clk_get_by_name(switch_node, "ess_clk"); -+ if (ess_clk) -+ clk_prepare_enable(ess_clk); -+ -+ priv->ess_rst = devm_reset_control_get(&pdev->dev, "ess_rst"); -+ if (IS_ERR(priv->ess_rst)) { -+ dev_err(&pdev->dev, "Failed to get ess_rst control!\n"); -+ return PTR_ERR(priv->ess_rst); -+ } -+ -+ if (of_property_read_u32(switch_node, "switch_cpu_bmp", -+ &priv->cpu_bmp) || -+ of_property_read_u32(switch_node, "switch_lan_bmp", -+ &priv->lan_bmp) || -+ of_property_read_u32(switch_node, "switch_wan_bmp", -+ &priv->wan_bmp)) { -+ dev_err(&pdev->dev, "Failed to read port properties\n"); -+ return -EIO; -+ } -+ -+ ret = phy_driver_register(&ar40xx_phy_driver, THIS_MODULE); -+ if (ret) { -+ dev_err(&pdev->dev, "Failed to register ar40xx phy driver!\n"); -+ return -EIO; -+ } -+ -+ mutex_init(&priv->reg_mutex); -+ mutex_init(&priv->mib_lock); -+ INIT_DELAYED_WORK(&priv->mib_work, ar40xx_mib_work_func); -+ -+ /* register switch */ -+ swdev = &priv->dev; -+ -+ swdev->alias = dev_name(&priv->mii_bus->dev); -+ -+ swdev->cpu_port = AR40XX_PORT_CPU; -+ swdev->name = "QCA AR40xx"; -+ swdev->vlans = AR40XX_MAX_VLANS; -+ swdev->ports = AR40XX_NUM_PORTS; -+ swdev->ops = &ar40xx_sw_ops; -+ ret = register_switch(swdev, NULL); -+ if (ret) -+ goto err_unregister_phy; -+ -+ num_mibs = ARRAY_SIZE(ar40xx_mibs); -+ len = priv->dev.ports * num_mibs * -+ sizeof(*priv->mib_stats); -+ priv->mib_stats = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); -+ if (!priv->mib_stats) { -+ ret = -ENOMEM; -+ goto err_unregister_switch; -+ } -+ -+ ar40xx_start(priv); -+ -+ if (of_property_read_bool(switch_node, "gpio-controller")) -+ ar40xx_register_gpio(&pdev->dev, ar40xx_priv, switch_node); -+ -+ return 0; -+ -+err_unregister_switch: -+ unregister_switch(&priv->dev); -+err_unregister_phy: -+ phy_driver_unregister(&ar40xx_phy_driver); -+ platform_set_drvdata(pdev, NULL); -+ return ret; -+} -+ -+static int ar40xx_remove(struct platform_device *pdev) -+{ -+ struct ar40xx_priv *priv = platform_get_drvdata(pdev); -+ -+ cancel_delayed_work_sync(&priv->qm_dwork); -+ cancel_delayed_work_sync(&priv->mib_work); -+ -+ unregister_switch(&priv->dev); -+ -+ phy_driver_unregister(&ar40xx_phy_driver); -+ -+ return 0; -+} -+ -+static const struct of_device_id ar40xx_of_mtable[] = { -+ {.compatible = "qcom,ess-switch" }, -+ {} -+}; -+ -+struct platform_driver ar40xx_drv = { -+ .probe = ar40xx_probe, -+ .remove = ar40xx_remove, -+ .driver = { -+ .name = "ar40xx", -+ .of_match_table = ar40xx_of_mtable, -+ }, -+}; -+ -+module_platform_driver(ar40xx_drv); -+ -+MODULE_DESCRIPTION("IPQ40XX ESS driver"); -+MODULE_LICENSE("Dual BSD/GPL"); ---- /dev/null -+++ b/drivers/net/phy/ar40xx.h -@@ -0,0 +1,337 @@ -+/* -+ * Copyright (c) 2016, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for -+ * any purpose with or without fee is hereby granted, provided that the -+ * above copyright notice and this permission notice appear in all copies. -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+ #ifndef __AR40XX_H -+#define __AR40XX_H -+ -+#define AR40XX_MAX_VLANS 128 -+#define AR40XX_NUM_PORTS 6 -+#define AR40XX_NUM_PHYS 5 -+ -+#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s) -+ -+struct ar40xx_priv { -+ struct switch_dev dev; -+ -+ u8 __iomem *hw_addr; -+ u8 __iomem *psgmii_hw_addr; -+ u32 mac_mode; -+ struct reset_control *ess_rst; -+ u32 cpu_bmp; -+ u32 lan_bmp; -+ u32 wan_bmp; -+ -+ struct mii_bus *mii_bus; -+ struct phy_device *phy; -+ -+ /* mutex for qm task */ -+ struct mutex qm_lock; -+ struct delayed_work qm_dwork; -+ u32 port_link_up[AR40XX_NUM_PORTS]; -+ u32 ar40xx_port_old_link[AR40XX_NUM_PORTS]; -+ u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS]; -+ -+ u32 phy_t_status; -+ -+ /* mutex for switch reg access */ -+ struct mutex reg_mutex; -+ -+ /* mutex for mib task */ -+ struct mutex mib_lock; -+ struct delayed_work mib_work; -+ int mib_next_port; -+ u64 *mib_stats; -+ -+ char buf[2048]; -+ -+ /* all fields below will be cleared on reset */ -+ bool vlan; -+ u16 vlan_id[AR40XX_MAX_VLANS]; -+ u8 vlan_table[AR40XX_MAX_VLANS]; -+ u8 vlan_tagged; -+ u16 pvid[AR40XX_NUM_PORTS]; -+ -+ /* mirror */ -+ bool mirror_rx; -+ bool mirror_tx; -+ int source_port; -+ int monitor_port; -+}; -+ -+#define AR40XX_PORT_LINK_UP 1 -+#define AR40XX_PORT_LINK_DOWN 0 -+#define AR40XX_QM_NOT_EMPTY 1 -+#define AR40XX_QM_EMPTY 0 -+ -+#define AR40XX_LAN_VLAN 1 -+#define AR40XX_WAN_VLAN 2 -+ -+enum ar40xx_port_wrapper_cfg { -+ PORT_WRAPPER_PSGMII = 0, -+}; -+ -+struct ar40xx_mib_desc { -+ u32 size; -+ u32 offset; -+ const char *name; -+}; -+ -+#define AR40XX_PORT_CPU 0 -+ -+#define AR40XX_PSGMII_MODE_CONTROL 0x1b4 -+#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0) -+ -+#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288 -+ -+#define AR40XX_MII_ATH_MMD_ADDR 0x0d -+#define AR40XX_MII_ATH_MMD_DATA 0x0e -+#define AR40XX_MII_ATH_DBG_ADDR 0x1d -+#define AR40XX_MII_ATH_DBG_DATA 0x1e -+ -+#define AR40XX_STATS_RXBROAD 0x00 -+#define AR40XX_STATS_RXPAUSE 0x04 -+#define AR40XX_STATS_RXMULTI 0x08 -+#define AR40XX_STATS_RXFCSERR 0x0c -+#define AR40XX_STATS_RXALIGNERR 0x10 -+#define AR40XX_STATS_RXRUNT 0x14 -+#define AR40XX_STATS_RXFRAGMENT 0x18 -+#define AR40XX_STATS_RX64BYTE 0x1c -+#define AR40XX_STATS_RX128BYTE 0x20 -+#define AR40XX_STATS_RX256BYTE 0x24 -+#define AR40XX_STATS_RX512BYTE 0x28 -+#define AR40XX_STATS_RX1024BYTE 0x2c -+#define AR40XX_STATS_RX1518BYTE 0x30 -+#define AR40XX_STATS_RXMAXBYTE 0x34 -+#define AR40XX_STATS_RXTOOLONG 0x38 -+#define AR40XX_STATS_RXGOODBYTE 0x3c -+#define AR40XX_STATS_RXBADBYTE 0x44 -+#define AR40XX_STATS_RXOVERFLOW 0x4c -+#define AR40XX_STATS_FILTERED 0x50 -+#define AR40XX_STATS_TXBROAD 0x54 -+#define AR40XX_STATS_TXPAUSE 0x58 -+#define AR40XX_STATS_TXMULTI 0x5c -+#define AR40XX_STATS_TXUNDERRUN 0x60 -+#define AR40XX_STATS_TX64BYTE 0x64 -+#define AR40XX_STATS_TX128BYTE 0x68 -+#define AR40XX_STATS_TX256BYTE 0x6c -+#define AR40XX_STATS_TX512BYTE 0x70 -+#define AR40XX_STATS_TX1024BYTE 0x74 -+#define AR40XX_STATS_TX1518BYTE 0x78 -+#define AR40XX_STATS_TXMAXBYTE 0x7c -+#define AR40XX_STATS_TXOVERSIZE 0x80 -+#define AR40XX_STATS_TXBYTE 0x84 -+#define AR40XX_STATS_TXCOLLISION 0x8c -+#define AR40XX_STATS_TXABORTCOL 0x90 -+#define AR40XX_STATS_TXMULTICOL 0x94 -+#define AR40XX_STATS_TXSINGLECOL 0x98 -+#define AR40XX_STATS_TXEXCDEFER 0x9c -+#define AR40XX_STATS_TXDEFER 0xa0 -+#define AR40XX_STATS_TXLATECOL 0xa4 -+ -+#define AR40XX_REG_MODULE_EN 0x030 -+#define AR40XX_MODULE_EN_MIB BIT(0) -+ -+#define AR40XX_REG_MIB_FUNC 0x034 -+#define AR40XX_MIB_BUSY BIT(17) -+#define AR40XX_MIB_CPU_KEEP BIT(20) -+#define AR40XX_MIB_FUNC BITS(24, 3) -+#define AR40XX_MIB_FUNC_S 24 -+#define AR40XX_MIB_FUNC_NO_OP 0x0 -+#define AR40XX_MIB_FUNC_FLUSH 0x1 -+ -+#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) -+#define AR40XX_PORT_SPEED BITS(0, 2) -+#define AR40XX_PORT_STATUS_SPEED_S 0 -+#define AR40XX_PORT_TX_EN BIT(2) -+#define AR40XX_PORT_RX_EN BIT(3) -+#define AR40XX_PORT_STATUS_TXFLOW BIT(4) -+#define AR40XX_PORT_STATUS_RXFLOW BIT(5) -+#define AR40XX_PORT_DUPLEX BIT(6) -+#define AR40XX_PORT_TXHALF_FLOW BIT(7) -+#define AR40XX_PORT_STATUS_LINK_UP BIT(8) -+#define AR40XX_PORT_AUTO_LINK_EN BIT(9) -+#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12) -+ -+#define AR40XX_REG_MAX_FRAME_SIZE 0x078 -+#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14) -+ -+#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) -+ -+#define AR40XX_REG_EEE_CTRL 0x100 -+#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2) -+ -+#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) -+#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12) -+#define AR40XX_PORT_VLAN0_DEF_SVID_S 0 -+#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12) -+#define AR40XX_PORT_VLAN0_DEF_CVID_S 16 -+ -+#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) -+#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6) -+#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2) -+#define AR40XX_PORT_VLAN1_OUT_MODE_S 12 -+#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0 -+#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1 -+#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2 -+#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3 -+ -+#define AR40XX_REG_VTU_FUNC0 0x0610 -+#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14) -+#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) -+#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0 -+#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1 -+#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2 -+#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3 -+#define AR40XX_VTU_FUNC0_IVL BIT(19) -+#define AR40XX_VTU_FUNC0_VALID BIT(20) -+ -+#define AR40XX_REG_VTU_FUNC1 0x0614 -+#define AR40XX_VTU_FUNC1_OP BITS(0, 3) -+#define AR40XX_VTU_FUNC1_OP_NOOP 0 -+#define AR40XX_VTU_FUNC1_OP_FLUSH 1 -+#define AR40XX_VTU_FUNC1_OP_LOAD 2 -+#define AR40XX_VTU_FUNC1_OP_PURGE 3 -+#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4 -+#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5 -+#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6 -+#define AR40XX_VTU_FUNC1_FULL BIT(4) -+#define AR40XX_VTU_FUNC1_PORT BIT(8, 4) -+#define AR40XX_VTU_FUNC1_PORT_S 8 -+#define AR40XX_VTU_FUNC1_VID BIT(16, 12) -+#define AR40XX_VTU_FUNC1_VID_S 16 -+#define AR40XX_VTU_FUNC1_BUSY BIT(31) -+ -+#define AR40XX_REG_FWD_CTRL0 0x620 -+#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10) -+#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4) -+#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4 -+ -+#define AR40XX_REG_FWD_CTRL1 0x624 -+#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7) -+#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0 -+#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7) -+#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8 -+#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7) -+#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16 -+#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7) -+#define AR40XX_FWD_CTRL1_IGMP_S 24 -+ -+#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) -+#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7) -+#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2) -+#define AR40XX_PORT_LOOKUP_IN_MODE_S 8 -+#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3) -+#define AR40XX_PORT_LOOKUP_STATE_S 16 -+#define AR40XX_PORT_LOOKUP_LEARN BIT(20) -+#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21) -+#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25) -+ -+#define AR40XX_REG_ATU_FUNC 0x60c -+#define AR40XX_ATU_FUNC_OP BITS(0, 4) -+#define AR40XX_ATU_FUNC_OP_NOOP 0x0 -+#define AR40XX_ATU_FUNC_OP_FLUSH 0x1 -+#define AR40XX_ATU_FUNC_OP_LOAD 0x2 -+#define AR40XX_ATU_FUNC_OP_PURGE 0x3 -+#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4 -+#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5 -+#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6 -+#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7 -+#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8 -+#define AR40XX_ATU_FUNC_BUSY BIT(31) -+ -+#define AR40XX_REG_QM_DEBUG_ADDR 0x820 -+#define AR40XX_REG_QM_DEBUG_VALUE 0x824 -+#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d -+#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e -+ -+#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) -+#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) -+ -+#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4) -+#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60 -+#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90 -+ -+#define AR40XX_PHY_DEBUG_0 0 -+#define AR40XX_PHY_MANU_CTRL_EN BIT(12) -+ -+#define AR40XX_PHY_DEBUG_2 2 -+ -+#define AR40XX_PHY_SPEC_STATUS 0x11 -+#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10) -+#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13) -+#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2) -+ -+/* port forwarding state */ -+enum { -+ AR40XX_PORT_STATE_DISABLED = 0, -+ AR40XX_PORT_STATE_BLOCK = 1, -+ AR40XX_PORT_STATE_LISTEN = 2, -+ AR40XX_PORT_STATE_LEARN = 3, -+ AR40XX_PORT_STATE_FORWARD = 4 -+}; -+ -+/* ingress 802.1q mode */ -+enum { -+ AR40XX_IN_PORT_ONLY = 0, -+ AR40XX_IN_PORT_FALLBACK = 1, -+ AR40XX_IN_VLAN_ONLY = 2, -+ AR40XX_IN_SECURE = 3 -+}; -+ -+/* egress 802.1q mode */ -+enum { -+ AR40XX_OUT_KEEP = 0, -+ AR40XX_OUT_STRIP_VLAN = 1, -+ AR40XX_OUT_ADD_VLAN = 2 -+}; -+ -+/* port speed */ -+enum { -+ AR40XX_PORT_SPEED_10M = 0, -+ AR40XX_PORT_SPEED_100M = 1, -+ AR40XX_PORT_SPEED_1000M = 2, -+ AR40XX_PORT_SPEED_ERR = 3, -+}; -+ -+#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */ -+ -+#define AR40XX_QM_WORK_DELAY 100 -+ -+#define AR40XX_MIB_FUNC_CAPTURE 0x3 -+ -+#define AR40XX_REG_PORT_STATS_START 0x1000 -+#define AR40XX_REG_PORT_STATS_LEN 0x100 -+ -+#define AR40XX_PORTS_ALL 0x3f -+ -+#define AR40XX_PSGMII_ID 5 -+#define AR40XX_PSGMII_CALB_NUM 100 -+#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d -+#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c -+#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a -+#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380 -+#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280 -+#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a -+#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb -+#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a -+#define AR40XX_MALIBU_PHY_LAST_ADDR 4 -+ -+static inline struct ar40xx_priv * -+swdev_to_ar40xx(struct switch_dev *swdev) -+{ -+ return container_of(swdev, struct ar40xx_priv, dev); -+} -+ -+#endif diff --git a/target/linux/ipq40xx/patches-4.19/706-ar40xx-abort-probe-on-missig-phy.patch b/target/linux/ipq40xx/patches-4.19/706-ar40xx-abort-probe-on-missig-phy.patch deleted file mode 100644 index 19474bff0d..0000000000 --- a/target/linux/ipq40xx/patches-4.19/706-ar40xx-abort-probe-on-missig-phy.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/drivers/net/phy/ar40xx.c -+++ b/drivers/net/phy/ar40xx.c -@@ -2021,6 +2021,12 @@ static int ar40xx_probe(struct platform_ - /* register switch */ - swdev = &priv->dev; - -+ if (priv->mii_bus == NULL) { -+ dev_err(&pdev->dev, "Probe failed - Missing PHYs!\n"); -+ ret = -ENODEV; -+ goto err_missing_phy; -+ } -+ - swdev->alias = dev_name(&priv->mii_bus->dev); - - swdev->cpu_port = AR40XX_PORT_CPU; -@@ -2052,6 +2058,7 @@ err_unregister_switch: - unregister_switch(&priv->dev); - err_unregister_phy: - phy_driver_unregister(&ar40xx_phy_driver); -+err_missing_phy: - platform_set_drvdata(pdev, NULL); - return ret; - } diff --git a/target/linux/ipq40xx/patches-4.19/710-net-add-qualcomm-essedma-ethernet-driver.patch b/target/linux/ipq40xx/patches-4.19/710-net-add-qualcomm-essedma-ethernet-driver.patch deleted file mode 100644 index 6ccf2cd480..0000000000 --- a/target/linux/ipq40xx/patches-4.19/710-net-add-qualcomm-essedma-ethernet-driver.patch +++ /dev/null @@ -1,4575 +0,0 @@ -From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Thu, 19 Jan 2017 02:01:31 +0100 -Subject: [PATCH 33/38] NET: add qualcomm essedma ethernet driver - -Signed-off-by: Christian Lamparter ---- - drivers/net/ethernet/qualcomm/Kconfig | 9 +++++++++ - drivers/net/ethernet/qualcomm/Makefile | 1 + - 2 files changed, 10 insertions(+) - ---- a/drivers/net/ethernet/qualcomm/Kconfig -+++ b/drivers/net/ethernet/qualcomm/Kconfig -@@ -61,4 +61,13 @@ config QCOM_EMAC - - source "drivers/net/ethernet/qualcomm/rmnet/Kconfig" - -+config ESSEDMA -+ tristate "Qualcomm Atheros ESS Edma support" -+ ---help--- -+ This driver supports ethernet edma adapter. -+ Say Y to build this driver. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called essedma.ko. -+ - endif # NET_VENDOR_QUALCOMM ---- a/drivers/net/ethernet/qualcomm/Makefile -+++ b/drivers/net/ethernet/qualcomm/Makefile -@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o - qcauart-objs := qca_uart.o - - obj-y += emac/ -+obj-$(CONFIG_ESSEDMA) += essedma/ - - obj-$(CONFIG_RMNET) += rmnet/ ---- /dev/null -+++ b/drivers/net/ethernet/qualcomm/essedma/Makefile -@@ -0,0 +1,9 @@ -+# -+## Makefile for the Qualcomm Atheros ethernet edma driver -+# -+ -+ -+obj-$(CONFIG_ESSEDMA) += essedma.o -+ -+essedma-objs := edma_axi.o edma.o edma_ethtool.o -+ ---- /dev/null -+++ b/drivers/net/ethernet/qualcomm/essedma/edma.c -@@ -0,0 +1,2143 @@ -+/* -+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for -+ * any purpose with or without fee is hereby granted, provided that the -+ * above copyright notice and this permission notice appear in all copies. -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+#include -+#include -+#include "ess_edma.h" -+#include "edma.h" -+ -+extern struct net_device *edma_netdev[EDMA_MAX_PORTID_SUPPORTED]; -+bool edma_stp_rstp; -+u16 edma_ath_eth_type; -+ -+/* edma_skb_priority_offset() -+ * get edma skb priority -+ */ -+static unsigned int edma_skb_priority_offset(struct sk_buff *skb) -+{ -+ return (skb->priority >> 2) & 1; -+} -+ -+/* edma_alloc_tx_ring() -+ * Allocate Tx descriptors ring -+ */ -+static int edma_alloc_tx_ring(struct edma_common_info *edma_cinfo, -+ struct edma_tx_desc_ring *etdr) -+{ -+ struct platform_device *pdev = edma_cinfo->pdev; -+ -+ /* Initialize ring */ -+ etdr->size = sizeof(struct edma_sw_desc) * etdr->count; -+ etdr->sw_next_to_fill = 0; -+ etdr->sw_next_to_clean = 0; -+ -+ /* Allocate SW descriptors */ -+ etdr->sw_desc = vzalloc(etdr->size); -+ if (!etdr->sw_desc) { -+ dev_err(&pdev->dev, "buffer alloc of tx ring failed=%p", etdr); -+ return -ENOMEM; -+ } -+ -+ /* Allocate HW descriptors */ -+ etdr->hw_desc = dma_alloc_coherent(&pdev->dev, etdr->size, &etdr->dma, -+ GFP_KERNEL); -+ if (!etdr->hw_desc) { -+ dev_err(&pdev->dev, "descriptor allocation for tx ring failed"); -+ vfree(etdr->sw_desc); -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+/* edma_free_tx_ring() -+ * Free tx rings allocated by edma_alloc_tx_rings -+ */ -+static void edma_free_tx_ring(struct edma_common_info *edma_cinfo, -+ struct edma_tx_desc_ring *etdr) -+{ -+ struct platform_device *pdev = edma_cinfo->pdev; -+ -+ if (likely(etdr->dma)) -+ dma_free_coherent(&pdev->dev, etdr->size, etdr->hw_desc, -+ etdr->dma); -+ -+ vfree(etdr->sw_desc); -+ etdr->sw_desc = NULL; -+} -+ -+/* edma_alloc_rx_ring() -+ * allocate rx descriptor ring -+ */ -+static int edma_alloc_rx_ring(struct edma_common_info *edma_cinfo, -+ struct edma_rfd_desc_ring *erxd) -+{ -+ struct platform_device *pdev = edma_cinfo->pdev; -+ -+ erxd->size = sizeof(struct edma_sw_desc) * erxd->count; -+ erxd->sw_next_to_fill = 0; -+ erxd->sw_next_to_clean = 0; -+ -+ /* Allocate SW descriptors */ -+ erxd->sw_desc = vzalloc(erxd->size); -+ if (!erxd->sw_desc) -+ return -ENOMEM; -+ -+ /* Alloc HW descriptors */ -+ erxd->hw_desc = dma_alloc_coherent(&pdev->dev, erxd->size, &erxd->dma, -+ GFP_KERNEL); -+ if (!erxd->hw_desc) { -+ vfree(erxd->sw_desc); -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+/* edma_free_rx_ring() -+ * Free rx ring allocated by alloc_rx_ring -+ */ -+static void edma_free_rx_ring(struct edma_common_info *edma_cinfo, -+ struct edma_rfd_desc_ring *rxdr) -+{ -+ struct platform_device *pdev = edma_cinfo->pdev; -+ -+ if (likely(rxdr->dma)) -+ dma_free_coherent(&pdev->dev, rxdr->size, rxdr->hw_desc, -+ rxdr->dma); -+ -+ vfree(rxdr->sw_desc); -+ rxdr->sw_desc = NULL; -+} -+ -+/* edma_configure_tx() -+ * Configure transmission control data -+ */ -+static void edma_configure_tx(struct edma_common_info *edma_cinfo) -+{ -+ u32 txq_ctrl_data; -+ -+ txq_ctrl_data = (EDMA_TPD_BURST << EDMA_TXQ_NUM_TPD_BURST_SHIFT); -+ txq_ctrl_data |= EDMA_TXQ_CTRL_TPD_BURST_EN; -+ txq_ctrl_data |= (EDMA_TXF_BURST << EDMA_TXQ_TXF_BURST_NUM_SHIFT); -+ edma_write_reg(EDMA_REG_TXQ_CTRL, txq_ctrl_data); -+} -+ -+ -+/* edma_configure_rx() -+ * configure reception control data -+ */ -+static void edma_configure_rx(struct edma_common_info *edma_cinfo) -+{ -+ struct edma_hw *hw = &edma_cinfo->hw; -+ u32 rss_type, rx_desc1, rxq_ctrl_data; -+ -+ /* Set RSS type */ -+ rss_type = hw->rss_type; -+ edma_write_reg(EDMA_REG_RSS_TYPE, rss_type); -+ -+ /* Set RFD burst number */ -+ rx_desc1 = (EDMA_RFD_BURST << EDMA_RXQ_RFD_BURST_NUM_SHIFT); -+ -+ /* Set RFD prefetch threshold */ -+ rx_desc1 |= (EDMA_RFD_THR << EDMA_RXQ_RFD_PF_THRESH_SHIFT); -+ -+ /* Set RFD in host ring low threshold to generte interrupt */ -+ rx_desc1 |= (EDMA_RFD_LTHR << EDMA_RXQ_RFD_LOW_THRESH_SHIFT); -+ edma_write_reg(EDMA_REG_RX_DESC1, rx_desc1); -+ -+ /* Set Rx FIFO threshold to start to DMA data to host */ -+ rxq_ctrl_data = EDMA_FIFO_THRESH_128_BYTE; -+ -+ /* Set RX remove vlan bit */ -+ rxq_ctrl_data |= EDMA_RXQ_CTRL_RMV_VLAN; -+ -+ edma_write_reg(EDMA_REG_RXQ_CTRL, rxq_ctrl_data); -+} -+ -+/* edma_alloc_rx_buf() -+ * does skb allocation for the received packets. -+ */ -+static int edma_alloc_rx_buf(struct edma_common_info -+ *edma_cinfo, -+ struct edma_rfd_desc_ring *erdr, -+ int cleaned_count, int queue_id) -+{ -+ struct platform_device *pdev = edma_cinfo->pdev; -+ struct edma_rx_free_desc *rx_desc; -+ struct edma_sw_desc *sw_desc; -+ struct sk_buff *skb; -+ unsigned int i; -+ u16 prod_idx, length; -+ u32 reg_data; -+ -+ if (cleaned_count > erdr->count) { -+ dev_err(&pdev->dev, "Incorrect cleaned_count %d", -+ cleaned_count); -+ return -1; -+ } -+ -+ i = erdr->sw_next_to_fill; -+ -+ while (cleaned_count) { -+ sw_desc = &erdr->sw_desc[i]; -+ length = edma_cinfo->rx_head_buffer_len; -+ -+ if (sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_REUSE) { -+ skb = sw_desc->skb; -+ } else { -+ /* alloc skb */ -+ skb = netdev_alloc_skb(edma_netdev[0], length); -+ if (!skb) { -+ /* Better luck next round */ -+ break; -+ } -+ } -+ -+ if (edma_cinfo->page_mode) { -+ struct page *pg = alloc_page(GFP_ATOMIC); -+ -+ if (!pg) { -+ dev_kfree_skb_any(skb); -+ break; -+ } -+ -+ sw_desc->dma = dma_map_page(&pdev->dev, pg, 0, -+ edma_cinfo->rx_page_buffer_len, -+ DMA_FROM_DEVICE); -+ if (dma_mapping_error(&pdev->dev, -+ sw_desc->dma)) { -+ __free_page(pg); -+ dev_kfree_skb_any(skb); -+ break; -+ } -+ -+ skb_fill_page_desc(skb, 0, pg, 0, -+ edma_cinfo->rx_page_buffer_len); -+ sw_desc->flags = EDMA_SW_DESC_FLAG_SKB_FRAG; -+ sw_desc->length = edma_cinfo->rx_page_buffer_len; -+ } else { -+ sw_desc->dma = dma_map_single(&pdev->dev, skb->data, -+ length, DMA_FROM_DEVICE); -+ if (dma_mapping_error(&pdev->dev, -+ sw_desc->dma)) { -+ dev_kfree_skb_any(skb); -+ break; -+ } -+ -+ sw_desc->flags = EDMA_SW_DESC_FLAG_SKB_HEAD; -+ sw_desc->length = length; -+ } -+ -+ /* Update the buffer info */ -+ sw_desc->skb = skb; -+ rx_desc = (&((struct edma_rx_free_desc *)(erdr->hw_desc))[i]); -+ rx_desc->buffer_addr = cpu_to_le64(sw_desc->dma); -+ if (++i == erdr->count) -+ i = 0; -+ cleaned_count--; -+ } -+ -+ erdr->sw_next_to_fill = i; -+ -+ if (i == 0) -+ prod_idx = erdr->count - 1; -+ else -+ prod_idx = i - 1; -+ -+ /* Update the producer index */ -+ edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), ®_data); -+ reg_data &= ~EDMA_RFD_PROD_IDX_BITS; -+ reg_data |= prod_idx; -+ edma_write_reg(EDMA_REG_RFD_IDX_Q(queue_id), reg_data); -+ return cleaned_count; -+} -+ -+/* edma_init_desc() -+ * update descriptor ring size, buffer and producer/consumer index -+ */ -+static void edma_init_desc(struct edma_common_info *edma_cinfo) -+{ -+ struct edma_rfd_desc_ring *rfd_ring; -+ struct edma_tx_desc_ring *etdr; -+ int i = 0, j = 0; -+ u32 data = 0; -+ u16 hw_cons_idx = 0; -+ -+ /* Set the base address of every TPD ring. */ -+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) { -+ etdr = edma_cinfo->tpd_ring[i]; -+ -+ /* Update descriptor ring base address */ -+ edma_write_reg(EDMA_REG_TPD_BASE_ADDR_Q(i), (u32)etdr->dma); -+ edma_read_reg(EDMA_REG_TPD_IDX_Q(i), &data); -+ -+ /* Calculate hardware consumer index */ -+ hw_cons_idx = (data >> EDMA_TPD_CONS_IDX_SHIFT) & 0xffff; -+ etdr->sw_next_to_fill = hw_cons_idx; -+ etdr->sw_next_to_clean = hw_cons_idx; -+ data &= ~(EDMA_TPD_PROD_IDX_MASK << EDMA_TPD_PROD_IDX_SHIFT); -+ data |= hw_cons_idx; -+ -+ /* update producer index */ -+ edma_write_reg(EDMA_REG_TPD_IDX_Q(i), data); -+ -+ /* update SW consumer index register */ -+ edma_write_reg(EDMA_REG_TX_SW_CONS_IDX_Q(i), hw_cons_idx); -+ -+ /* Set TPD ring size */ -+ edma_write_reg(EDMA_REG_TPD_RING_SIZE, -+ edma_cinfo->tx_ring_count & -+ EDMA_TPD_RING_SIZE_MASK); -+ } -+ -+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) { -+ rfd_ring = edma_cinfo->rfd_ring[j]; -+ /* Update Receive Free descriptor ring base address */ -+ edma_write_reg(EDMA_REG_RFD_BASE_ADDR_Q(j), -+ (u32)(rfd_ring->dma)); -+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1); -+ } -+ -+ data = edma_cinfo->rx_head_buffer_len; -+ if (edma_cinfo->page_mode) -+ data = edma_cinfo->rx_page_buffer_len; -+ -+ data &= EDMA_RX_BUF_SIZE_MASK; -+ data <<= EDMA_RX_BUF_SIZE_SHIFT; -+ -+ /* Update RFD ring size and RX buffer size */ -+ data |= (edma_cinfo->rx_ring_count & EDMA_RFD_RING_SIZE_MASK) -+ << EDMA_RFD_RING_SIZE_SHIFT; -+ -+ edma_write_reg(EDMA_REG_RX_DESC0, data); -+ -+ /* Disable TX FIFO low watermark and high watermark */ -+ edma_write_reg(EDMA_REG_TXF_WATER_MARK, 0); -+ -+ /* Load all of base address above */ -+ edma_read_reg(EDMA_REG_TX_SRAM_PART, &data); -+ data |= 1 << EDMA_LOAD_PTR_SHIFT; -+ edma_write_reg(EDMA_REG_TX_SRAM_PART, data); -+} -+ -+/* edma_receive_checksum -+ * Api to check checksum on receive packets -+ */ -+static void edma_receive_checksum(struct edma_rx_return_desc *rd, -+ struct sk_buff *skb) -+{ -+ skb_checksum_none_assert(skb); -+ -+ /* check the RRD IP/L4 checksum bit to see if -+ * its set, which in turn indicates checksum -+ * failure. -+ */ -+ if (rd->rrd6 & EDMA_RRD_CSUM_FAIL_MASK) -+ return; -+ -+ skb->ip_summed = CHECKSUM_UNNECESSARY; -+} -+ -+/* edma_clean_rfd() -+ * clean up rx resourcers on error -+ */ -+static void edma_clean_rfd(struct edma_rfd_desc_ring *erdr, u16 index) -+{ -+ struct edma_rx_free_desc *rx_desc; -+ struct edma_sw_desc *sw_desc; -+ -+ rx_desc = (&((struct edma_rx_free_desc *)(erdr->hw_desc))[index]); -+ sw_desc = &erdr->sw_desc[index]; -+ if (sw_desc->skb) { -+ dev_kfree_skb_any(sw_desc->skb); -+ sw_desc->skb = NULL; -+ } -+ -+ memset(rx_desc, 0, sizeof(struct edma_rx_free_desc)); -+} -+ -+/* edma_rx_complete_fraglist() -+ * Complete Rx processing for fraglist skbs -+ */ -+static void edma_rx_complete_stp_rstp(struct sk_buff *skb, int port_id, struct edma_rx_return_desc *rd) -+{ -+ int i; -+ u32 priority; -+ u16 port_type; -+ u8 mac_addr[EDMA_ETH_HDR_LEN]; -+ -+ port_type = (rd->rrd1 >> EDMA_RRD_PORT_TYPE_SHIFT) -+ & EDMA_RRD_PORT_TYPE_MASK; -+ /* if port type is 0x4, then only proceed with -+ * other stp/rstp calculation -+ */ -+ if (port_type == EDMA_RX_ATH_HDR_RSTP_PORT_TYPE) { -+ u8 bpdu_mac[6] = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x00}; -+ -+ /* calculate the frame priority */ -+ priority = (rd->rrd1 >> EDMA_RRD_PRIORITY_SHIFT) -+ & EDMA_RRD_PRIORITY_MASK; -+ -+ for (i = 0; i < EDMA_ETH_HDR_LEN; i++) -+ mac_addr[i] = skb->data[i]; -+ -+ /* Check if destination mac addr is bpdu addr */ -+ if (!memcmp(mac_addr, bpdu_mac, 6)) { -+ /* destination mac address is BPDU -+ * destination mac address, then add -+ * atheros header to the packet. -+ */ -+ u16 athr_hdr = (EDMA_RX_ATH_HDR_VERSION << EDMA_RX_ATH_HDR_VERSION_SHIFT) | -+ (priority << EDMA_RX_ATH_HDR_PRIORITY_SHIFT) | -+ (EDMA_RX_ATH_HDR_RSTP_PORT_TYPE << EDMA_RX_ATH_PORT_TYPE_SHIFT) | port_id; -+ skb_push(skb, 4); -+ memcpy(skb->data, mac_addr, EDMA_ETH_HDR_LEN); -+ *(uint16_t *)&skb->data[12] = htons(edma_ath_eth_type); -+ *(uint16_t *)&skb->data[14] = htons(athr_hdr); -+ } -+ } -+} -+ -+/* -+ * edma_rx_complete_fraglist() -+ * Complete Rx processing for fraglist skbs -+ */ -+static int edma_rx_complete_fraglist(struct sk_buff *skb, u16 num_rfds, u16 length, u32 sw_next_to_clean, -+ u16 *cleaned_count, struct edma_rfd_desc_ring *erdr, struct edma_common_info *edma_cinfo) -+{ -+ struct platform_device *pdev = edma_cinfo->pdev; -+ struct edma_hw *hw = &edma_cinfo->hw; -+ struct sk_buff *skb_temp; -+ struct edma_sw_desc *sw_desc; -+ int i; -+ u16 size_remaining; -+ -+ skb->data_len = 0; -+ skb->tail += (hw->rx_head_buff_size - 16); -+ skb->len = skb->truesize = length; -+ size_remaining = length - (hw->rx_head_buff_size - 16); -+ -+ /* clean-up all related sw_descs */ -+ for (i = 1; i < num_rfds; i++) { -+ struct sk_buff *skb_prev; -+ sw_desc = &erdr->sw_desc[sw_next_to_clean]; -+ skb_temp = sw_desc->skb; -+ -+ dma_unmap_single(&pdev->dev, sw_desc->dma, -+ sw_desc->length, DMA_FROM_DEVICE); -+ -+ if (size_remaining < hw->rx_head_buff_size) -+ skb_put(skb_temp, size_remaining); -+ else -+ skb_put(skb_temp, hw->rx_head_buff_size); -+ -+ /* -+ * If we are processing the first rfd, we link -+ * skb->frag_list to the skb corresponding to the -+ * first RFD -+ */ -+ if (i == 1) -+ skb_shinfo(skb)->frag_list = skb_temp; -+ else -+ skb_prev->next = skb_temp; -+ skb_prev = skb_temp; -+ skb_temp->next = NULL; -+ -+ skb->data_len += skb_temp->len; -+ size_remaining -= skb_temp->len; -+ -+ /* Increment SW index */ -+ sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1); -+ (*cleaned_count)++; -+ } -+ -+ return sw_next_to_clean; -+} -+ -+/* edma_rx_complete_paged() -+ * Complete Rx processing for paged skbs -+ */ -+static int edma_rx_complete_paged(struct sk_buff *skb, u16 num_rfds, u16 length, u32 sw_next_to_clean, -+ u16 *cleaned_count, struct edma_rfd_desc_ring *erdr, struct edma_common_info *edma_cinfo) -+{ -+ struct platform_device *pdev = edma_cinfo->pdev; -+ struct sk_buff *skb_temp; -+ struct edma_sw_desc *sw_desc; -+ int i; -+ u16 size_remaining; -+ -+ skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; -+ -+ /* Setup skbuff fields */ -+ skb->len = length; -+ -+ if (likely(num_rfds <= 1)) { -+ skb->data_len = length; -+ skb->truesize += edma_cinfo->rx_page_buffer_len; -+ skb_fill_page_desc(skb, 0, skb_frag_page(frag), -+ 16, length); -+ } else { -+ frag->size -= 16; -+ skb->data_len = frag->size; -+ skb->truesize += edma_cinfo->rx_page_buffer_len; -+ size_remaining = length - frag->size; -+ -+ skb_fill_page_desc(skb, 0, skb_frag_page(frag), -+ 16, frag->size); -+ -+ /* clean-up all related sw_descs */ -+ for (i = 1; i < num_rfds; i++) { -+ sw_desc = &erdr->sw_desc[sw_next_to_clean]; -+ skb_temp = sw_desc->skb; -+ frag = &skb_shinfo(skb_temp)->frags[0]; -+ dma_unmap_page(&pdev->dev, sw_desc->dma, -+ sw_desc->length, DMA_FROM_DEVICE); -+ -+ if (size_remaining < edma_cinfo->rx_page_buffer_len) -+ frag->size = size_remaining; -+ -+ skb_fill_page_desc(skb, i, skb_frag_page(frag), -+ 0, frag->size); -+ -+ skb_shinfo(skb_temp)->nr_frags = 0; -+ dev_kfree_skb_any(skb_temp); -+ -+ skb->data_len += frag->size; -+ skb->truesize += edma_cinfo->rx_page_buffer_len; -+ size_remaining -= frag->size; -+ -+ /* Increment SW index */ -+ sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1); -+ (*cleaned_count)++; -+ } -+ } -+ -+ return sw_next_to_clean; -+} -+ -+/* -+ * edma_rx_complete() -+ * Main api called from the poll function to process rx packets. -+ */ -+static void edma_rx_complete(struct edma_common_info *edma_cinfo, -+ int *work_done, int work_to_do, int queue_id, -+ struct napi_struct *napi) -+{ -+ struct platform_device *pdev = edma_cinfo->pdev; -+ struct edma_rfd_desc_ring *erdr = edma_cinfo->rfd_ring[queue_id]; -+ struct net_device *netdev; -+ struct edma_adapter *adapter; -+ struct edma_sw_desc *sw_desc; -+ struct sk_buff *skb; -+ struct edma_rx_return_desc *rd; -+ u16 hash_type, rrd[8], cleaned_count = 0, length = 0, num_rfds = 1, -+ sw_next_to_clean, hw_next_to_clean = 0, vlan = 0, ret_count = 0; -+ u32 data = 0; -+ u8 *vaddr; -+ int port_id, i, drop_count = 0; -+ u32 priority; -+ u16 count = erdr->count, rfd_avail; -+ u8 queue_to_rxid[8] = {0, 0, 1, 1, 2, 2, 3, 3}; -+ -+ sw_next_to_clean = erdr->sw_next_to_clean; -+ -+ edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &data); -+ hw_next_to_clean = (data >> EDMA_RFD_CONS_IDX_SHIFT) & -+ EDMA_RFD_CONS_IDX_MASK; -+ -+ do { -+ while (sw_next_to_clean != hw_next_to_clean) { -+ if (!work_to_do) -+ break; -+ -+ sw_desc = &erdr->sw_desc[sw_next_to_clean]; -+ skb = sw_desc->skb; -+ -+ /* Unmap the allocated buffer */ -+ if (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD)) -+ dma_unmap_single(&pdev->dev, sw_desc->dma, -+ sw_desc->length, DMA_FROM_DEVICE); -+ else -+ dma_unmap_page(&pdev->dev, sw_desc->dma, -+ sw_desc->length, DMA_FROM_DEVICE); -+ -+ /* Get RRD */ -+ if (edma_cinfo->page_mode) { -+ vaddr = kmap_atomic(skb_frag_page(&skb_shinfo(skb)->frags[0])); -+ memcpy((uint8_t *)&rrd[0], vaddr, 16); -+ rd = (struct edma_rx_return_desc *)rrd; -+ kunmap_atomic(vaddr); -+ } else { -+ rd = (struct edma_rx_return_desc *)skb->data; -+ } -+ -+ /* Check if RRD is valid */ -+ if (!(rd->rrd7 & EDMA_RRD_DESC_VALID)) { -+ edma_clean_rfd(erdr, sw_next_to_clean); -+ sw_next_to_clean = (sw_next_to_clean + 1) & -+ (erdr->count - 1); -+ cleaned_count++; -+ continue; -+ } -+ -+ /* Get the number of RFDs from RRD */ -+ num_rfds = rd->rrd1 & EDMA_RRD_NUM_RFD_MASK; -+ -+ /* Get Rx port ID from switch */ -+ port_id = (rd->rrd1 >> EDMA_PORT_ID_SHIFT) & EDMA_PORT_ID_MASK; -+ if ((!port_id) || (port_id > EDMA_MAX_PORTID_SUPPORTED)) { -+ dev_err(&pdev->dev, "Invalid RRD source port bit set"); -+ for (i = 0; i < num_rfds; i++) { -+ edma_clean_rfd(erdr, sw_next_to_clean); -+ sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1); -+ cleaned_count++; -+ } -+ continue; -+ } -+ -+ /* check if we have a sink for the data we receive. -+ * If the interface isn't setup, we have to drop the -+ * incoming data for now. -+ */ -+ netdev = edma_cinfo->portid_netdev_lookup_tbl[port_id]; -+ if (!netdev) { -+ edma_clean_rfd(erdr, sw_next_to_clean); -+ sw_next_to_clean = (sw_next_to_clean + 1) & -+ (erdr->count - 1); -+ cleaned_count++; -+ continue; -+ } -+ adapter = netdev_priv(netdev); -+ -+ /* This code is added to handle a usecase where high -+ * priority stream and a low priority stream are -+ * received simultaneously on DUT. The problem occurs -+ * if one of the Rx rings is full and the corresponding -+ * core is busy with other stuff. This causes ESS CPU -+ * port to backpressure all incoming traffic including -+ * high priority one. We monitor free descriptor count -+ * on each CPU and whenever it reaches threshold (< 80), -+ * we drop all low priority traffic and let only high -+ * priotiy traffic pass through. We can hence avoid -+ * ESS CPU port to send backpressure on high priroity -+ * stream. -+ */ -+ priority = (rd->rrd1 >> EDMA_RRD_PRIORITY_SHIFT) -+ & EDMA_RRD_PRIORITY_MASK; -+ if (likely(!priority && !edma_cinfo->page_mode && (num_rfds <= 1))) { -+ rfd_avail = (count + sw_next_to_clean - hw_next_to_clean - 1) & (count - 1); -+ if (rfd_avail < EDMA_RFD_AVAIL_THR) { -+ sw_desc->flags = EDMA_SW_DESC_FLAG_SKB_REUSE; -+ sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1); -+ adapter->stats.rx_dropped++; -+ cleaned_count++; -+ drop_count++; -+ if (drop_count == 3) { -+ work_to_do--; -+ (*work_done)++; -+ drop_count = 0; -+ } -+ if (cleaned_count == EDMA_RX_BUFFER_WRITE) { -+ /* If buffer clean count reaches 16, we replenish HW buffers. */ -+ ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id); -+ edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id), -+ sw_next_to_clean); -+ cleaned_count = ret_count; -+ } -+ continue; -+ } -+ } -+ -+ work_to_do--; -+ (*work_done)++; -+ -+ /* Increment SW index */ -+ sw_next_to_clean = (sw_next_to_clean + 1) & -+ (erdr->count - 1); -+ -+ cleaned_count++; -+ -+ /* Get the packet size and allocate buffer */ -+ length = rd->rrd6 & EDMA_RRD_PKT_SIZE_MASK; -+ -+ if (edma_cinfo->page_mode) { -+ /* paged skb */ -+ sw_next_to_clean = edma_rx_complete_paged(skb, num_rfds, length, sw_next_to_clean, &cleaned_count, erdr, edma_cinfo); -+ if (!pskb_may_pull(skb, ETH_HLEN)) { -+ dev_kfree_skb_any(skb); -+ continue; -+ } -+ } else { -+ /* single or fraglist skb */ -+ -+ /* Addition of 16 bytes is required, as in the packet -+ * first 16 bytes are rrd descriptors, so actual data -+ * starts from an offset of 16. -+ */ -+ skb_reserve(skb, 16); -+ if (likely((num_rfds <= 1) || !edma_cinfo->fraglist_mode)) { -+ skb_put(skb, length); -+ } else { -+ sw_next_to_clean = edma_rx_complete_fraglist(skb, num_rfds, length, sw_next_to_clean, &cleaned_count, erdr, edma_cinfo); -+ } -+ } -+ -+ if (edma_stp_rstp) { -+ edma_rx_complete_stp_rstp(skb, port_id, rd); -+ } -+ -+ skb->protocol = eth_type_trans(skb, netdev); -+ -+ /* Record Rx queue for RFS/RPS and fill flow hash from HW */ -+ skb_record_rx_queue(skb, queue_to_rxid[queue_id]); -+ if (netdev->features & NETIF_F_RXHASH) { -+ hash_type = (rd->rrd5 >> EDMA_HASH_TYPE_SHIFT); -+ if ((hash_type > EDMA_HASH_TYPE_START) && (hash_type < EDMA_HASH_TYPE_END)) -+ skb_set_hash(skb, rd->rrd2, PKT_HASH_TYPE_L4); -+ } -+ -+#ifdef CONFIG_NF_FLOW_COOKIE -+ skb->flow_cookie = rd->rrd3 & EDMA_RRD_FLOW_COOKIE_MASK; -+#endif -+ edma_receive_checksum(rd, skb); -+ -+ /* Process VLAN HW acceleration indication provided by HW */ -+ if (unlikely(adapter->default_vlan_tag != rd->rrd4)) { -+ vlan = rd->rrd4; -+ if (likely(rd->rrd7 & EDMA_RRD_CVLAN)) -+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan); -+ else if (rd->rrd1 & EDMA_RRD_SVLAN) -+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), vlan); -+ } -+ -+ /* Update rx statistics */ -+ adapter->stats.rx_packets++; -+ adapter->stats.rx_bytes += length; -+ -+ /* Check if we reached refill threshold */ -+ if (cleaned_count == EDMA_RX_BUFFER_WRITE) { -+ ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id); -+ edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id), -+ sw_next_to_clean); -+ cleaned_count = ret_count; -+ } -+ -+ /* At this point skb should go to stack */ -+ napi_gro_receive(napi, skb); -+ } -+ -+ /* Check if we still have NAPI budget */ -+ if (!work_to_do) -+ break; -+ -+ /* Read index once again since we still have NAPI budget */ -+ edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &data); -+ hw_next_to_clean = (data >> EDMA_RFD_CONS_IDX_SHIFT) & -+ EDMA_RFD_CONS_IDX_MASK; -+ } while (hw_next_to_clean != sw_next_to_clean); -+ -+ erdr->sw_next_to_clean = sw_next_to_clean; -+ -+ /* Refill here in case refill threshold wasn't reached */ -+ if (likely(cleaned_count)) { -+ ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id); -+ if (ret_count) -+ dev_dbg(&pdev->dev, "Not all buffers was reallocated"); -+ edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id), -+ erdr->sw_next_to_clean); -+ } -+} -+ -+/* edma_delete_rfs_filter() -+ * Remove RFS filter from switch -+ */ -+static int edma_delete_rfs_filter(struct edma_adapter *adapter, -+ struct edma_rfs_filter_node *filter_node) -+{ -+ int res = -1; -+ -+ struct flow_keys *keys = &filter_node->keys; -+ -+ if (likely(adapter->set_rfs_rule)) -+ res = (*adapter->set_rfs_rule)(adapter->netdev, -+ flow_get_u32_src(keys), flow_get_u32_dst(keys), -+ keys->ports.src, keys->ports.dst, -+ keys->basic.ip_proto, filter_node->rq_id, 0); -+ -+ return res; -+} -+ -+/* edma_add_rfs_filter() -+ * Add RFS filter to switch -+ */ -+static int edma_add_rfs_filter(struct edma_adapter *adapter, -+ struct flow_keys *keys, u16 rq, -+ struct edma_rfs_filter_node *filter_node) -+{ -+ int res = -1; -+ -+ struct flow_keys *dest_keys = &filter_node->keys; -+ -+ memcpy(dest_keys, &filter_node->keys, sizeof(*dest_keys)); -+/* -+ dest_keys->control = keys->control; -+ dest_keys->basic = keys->basic; -+ dest_keys->addrs = keys->addrs; -+ dest_keys->ports = keys->ports; -+ dest_keys.ip_proto = keys->ip_proto; -+*/ -+ /* Call callback registered by ESS driver */ -+ if (likely(adapter->set_rfs_rule)) -+ res = (*adapter->set_rfs_rule)(adapter->netdev, flow_get_u32_src(keys), -+ flow_get_u32_dst(keys), keys->ports.src, keys->ports.dst, -+ keys->basic.ip_proto, rq, 1); -+ -+ return res; -+} -+ -+/* edma_rfs_key_search() -+ * Look for existing RFS entry -+ */ -+static struct edma_rfs_filter_node *edma_rfs_key_search(struct hlist_head *h, -+ struct flow_keys *key) -+{ -+ struct edma_rfs_filter_node *p; -+ -+ hlist_for_each_entry(p, h, node) -+ if (flow_get_u32_src(&p->keys) == flow_get_u32_src(key) && -+ flow_get_u32_dst(&p->keys) == flow_get_u32_dst(key) && -+ p->keys.ports.src == key->ports.src && -+ p->keys.ports.dst == key->ports.dst && -+ p->keys.basic.ip_proto == key->basic.ip_proto) -+ return p; -+ return NULL; -+} -+ -+/* edma_initialise_rfs_flow_table() -+ * Initialise EDMA RFS flow table -+ */ -+static void edma_initialise_rfs_flow_table(struct edma_adapter *adapter) -+{ -+ int i; -+ -+ spin_lock_init(&adapter->rfs.rfs_ftab_lock); -+ -+ /* Initialize EDMA flow hash table */ -+ for (i = 0; i < EDMA_RFS_FLOW_ENTRIES; i++) -+ INIT_HLIST_HEAD(&adapter->rfs.hlist_head[i]); -+ -+ adapter->rfs.max_num_filter = EDMA_RFS_FLOW_ENTRIES; -+ adapter->rfs.filter_available = adapter->rfs.max_num_filter; -+ adapter->rfs.hashtoclean = 0; -+ -+ /* Add timer to get periodic RFS updates from OS */ -+ timer_setup(&adapter->rfs.expire_rfs, edma_flow_may_expire, 0); -+ mod_timer(&adapter->rfs.expire_rfs, jiffies + HZ / 4); -+} -+ -+/* edma_free_rfs_flow_table() -+ * Free EDMA RFS flow table -+ */ -+static void edma_free_rfs_flow_table(struct edma_adapter *adapter) -+{ -+ int i; -+ -+ /* Remove sync timer */ -+ del_timer_sync(&adapter->rfs.expire_rfs); -+ spin_lock_bh(&adapter->rfs.rfs_ftab_lock); -+ -+ /* Free EDMA RFS table entries */ -+ adapter->rfs.filter_available = 0; -+ -+ /* Clean-up EDMA flow hash table */ -+ for (i = 0; i < EDMA_RFS_FLOW_ENTRIES; i++) { -+ struct hlist_head *hhead; -+ struct hlist_node *tmp; -+ struct edma_rfs_filter_node *filter_node; -+ int res; -+ -+ hhead = &adapter->rfs.hlist_head[i]; -+ hlist_for_each_entry_safe(filter_node, tmp, hhead, node) { -+ res = edma_delete_rfs_filter(adapter, filter_node); -+ if (res < 0) -+ dev_warn(&adapter->netdev->dev, -+ "EDMA going down but RFS entry %d not allowed to be flushed by Switch", -+ filter_node->flow_id); -+ hlist_del(&filter_node->node); -+ kfree(filter_node); -+ } -+ } -+ spin_unlock_bh(&adapter->rfs.rfs_ftab_lock); -+} -+ -+/* edma_tx_unmap_and_free() -+ * clean TX buffer -+ */ -+static inline void edma_tx_unmap_and_free(struct platform_device *pdev, -+ struct edma_sw_desc *sw_desc) -+{ -+ struct sk_buff *skb = sw_desc->skb; -+ -+ if (likely((sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD) || -+ (sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_FRAGLIST))) -+ /* unmap_single for skb head area */ -+ dma_unmap_single(&pdev->dev, sw_desc->dma, -+ sw_desc->length, DMA_TO_DEVICE); -+ else if (sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_FRAG) -+ /* unmap page for paged fragments */ -+ dma_unmap_page(&pdev->dev, sw_desc->dma, -+ sw_desc->length, DMA_TO_DEVICE); -+ -+ if (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_LAST)) -+ dev_kfree_skb_any(skb); -+ -+ sw_desc->flags = 0; -+} -+ -+/* edma_tx_complete() -+ * Used to clean tx queues and update hardware and consumer index -+ */ -+static void edma_tx_complete(struct edma_common_info *edma_cinfo, int queue_id) -+{ -+ struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id]; -+ struct edma_sw_desc *sw_desc; -+ struct platform_device *pdev = edma_cinfo->pdev; -+ int i; -+ -+ u16 sw_next_to_clean = etdr->sw_next_to_clean; -+ u16 hw_next_to_clean; -+ u32 data = 0; -+ -+ edma_read_reg(EDMA_REG_TPD_IDX_Q(queue_id), &data); -+ hw_next_to_clean = (data >> EDMA_TPD_CONS_IDX_SHIFT) & EDMA_TPD_CONS_IDX_MASK; -+ -+ /* clean the buffer here */ -+ while (sw_next_to_clean != hw_next_to_clean) { -+ sw_desc = &etdr->sw_desc[sw_next_to_clean]; -+ edma_tx_unmap_and_free(pdev, sw_desc); -+ sw_next_to_clean = (sw_next_to_clean + 1) & (etdr->count - 1); -+ } -+ -+ etdr->sw_next_to_clean = sw_next_to_clean; -+ -+ /* update the TPD consumer index register */ -+ edma_write_reg(EDMA_REG_TX_SW_CONS_IDX_Q(queue_id), sw_next_to_clean); -+ -+ /* Wake the queue if queue is stopped and netdev link is up */ -+ for (i = 0; i < EDMA_MAX_NETDEV_PER_QUEUE && etdr->nq[i] ; i++) { -+ if (netif_tx_queue_stopped(etdr->nq[i])) { -+ if ((etdr->netdev[i]) && netif_carrier_ok(etdr->netdev[i])) -+ netif_tx_wake_queue(etdr->nq[i]); -+ } -+ } -+} -+ -+/* edma_get_tx_buffer() -+ * Get sw_desc corresponding to the TPD -+ */ -+static struct edma_sw_desc *edma_get_tx_buffer(struct edma_common_info *edma_cinfo, -+ struct edma_tx_desc *tpd, int queue_id) -+{ -+ struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id]; -+ return &etdr->sw_desc[tpd - (struct edma_tx_desc *)etdr->hw_desc]; -+} -+ -+/* edma_get_next_tpd() -+ * Return a TPD descriptor for transfer -+ */ -+static struct edma_tx_desc *edma_get_next_tpd(struct edma_common_info *edma_cinfo, -+ int queue_id) -+{ -+ struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id]; -+ u16 sw_next_to_fill = etdr->sw_next_to_fill; -+ struct edma_tx_desc *tpd_desc = -+ (&((struct edma_tx_desc *)(etdr->hw_desc))[sw_next_to_fill]); -+ -+ etdr->sw_next_to_fill = (etdr->sw_next_to_fill + 1) & (etdr->count - 1); -+ -+ return tpd_desc; -+} -+ -+/* edma_tpd_available() -+ * Check number of free TPDs -+ */ -+static inline u16 edma_tpd_available(struct edma_common_info *edma_cinfo, -+ int queue_id) -+{ -+ struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id]; -+ -+ u16 sw_next_to_fill; -+ u16 sw_next_to_clean; -+ u16 count = 0; -+ -+ sw_next_to_clean = etdr->sw_next_to_clean; -+ sw_next_to_fill = etdr->sw_next_to_fill; -+ -+ if (likely(sw_next_to_clean <= sw_next_to_fill)) -+ count = etdr->count; -+ -+ return count + sw_next_to_clean - sw_next_to_fill - 1; -+} -+ -+/* edma_tx_queue_get() -+ * Get the starting number of the queue -+ */ -+static inline int edma_tx_queue_get(struct edma_adapter *adapter, -+ struct sk_buff *skb, int txq_id) -+{ -+ /* skb->priority is used as an index to skb priority table -+ * and based on packet priority, correspong queue is assigned. -+ */ -+ return adapter->tx_start_offset[txq_id] + edma_skb_priority_offset(skb); -+} -+ -+/* edma_tx_update_hw_idx() -+ * update the producer index for the ring transmitted -+ */ -+static void edma_tx_update_hw_idx(struct edma_common_info *edma_cinfo, -+ struct sk_buff *skb, int queue_id) -+{ -+ struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id]; -+ u32 tpd_idx_data; -+ -+ /* Read and update the producer index */ -+ edma_read_reg(EDMA_REG_TPD_IDX_Q(queue_id), &tpd_idx_data); -+ tpd_idx_data &= ~EDMA_TPD_PROD_IDX_BITS; -+ tpd_idx_data |= (etdr->sw_next_to_fill & EDMA_TPD_PROD_IDX_MASK) -+ << EDMA_TPD_PROD_IDX_SHIFT; -+ -+ edma_write_reg(EDMA_REG_TPD_IDX_Q(queue_id), tpd_idx_data); -+} -+ -+/* edma_rollback_tx() -+ * Function to retrieve tx resources in case of error -+ */ -+static void edma_rollback_tx(struct edma_adapter *adapter, -+ struct edma_tx_desc *start_tpd, int queue_id) -+{ -+ struct edma_tx_desc_ring *etdr = adapter->edma_cinfo->tpd_ring[queue_id]; -+ struct edma_sw_desc *sw_desc; -+ struct edma_tx_desc *tpd = NULL; -+ u16 start_index, index; -+ -+ start_index = start_tpd - (struct edma_tx_desc *)(etdr->hw_desc); -+ -+ index = start_index; -+ while (index != etdr->sw_next_to_fill) { -+ tpd = (&((struct edma_tx_desc *)(etdr->hw_desc))[index]); -+ sw_desc = &etdr->sw_desc[index]; -+ edma_tx_unmap_and_free(adapter->pdev, sw_desc); -+ memset(tpd, 0, sizeof(struct edma_tx_desc)); -+ if (++index == etdr->count) -+ index = 0; -+ } -+ etdr->sw_next_to_fill = start_index; -+} -+ -+/* edma_tx_map_and_fill() -+ * gets called from edma_xmit_frame -+ * -+ * This is where the dma of the buffer to be transmitted -+ * gets mapped -+ */ -+static int edma_tx_map_and_fill(struct edma_common_info *edma_cinfo, -+ struct edma_adapter *adapter, struct sk_buff *skb, int queue_id, -+ unsigned int flags_transmit, u16 from_cpu, u16 dp_bitmap, -+ bool packet_is_rstp, int nr_frags) -+{ -+ struct edma_sw_desc *sw_desc = NULL; -+ struct platform_device *pdev = edma_cinfo->pdev; -+ struct edma_tx_desc *tpd = NULL, *start_tpd = NULL; -+ struct sk_buff *iter_skb; -+ int i = 0; -+ u32 word1 = 0, word3 = 0, lso_word1 = 0, svlan_tag = 0; -+ u16 buf_len, lso_desc_len = 0; -+ -+ /* It should either be a nr_frags skb or fraglist skb but not both */ -+ BUG_ON(nr_frags && skb_has_frag_list(skb)); -+ -+ if (skb_is_gso(skb)) { -+ /* TODO: What additional checks need to be performed here */ -+ if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) { -+ lso_word1 |= EDMA_TPD_IPV4_EN; -+ ip_hdr(skb)->check = 0; -+ tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr, -+ ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); -+ } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { -+ lso_word1 |= EDMA_TPD_LSO_V2_EN; -+ ipv6_hdr(skb)->payload_len = 0; -+ tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, -+ &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); -+ } else -+ return -EINVAL; -+ -+ lso_word1 |= EDMA_TPD_LSO_EN | ((skb_shinfo(skb)->gso_size & EDMA_TPD_MSS_MASK) << EDMA_TPD_MSS_SHIFT) | -+ (skb_transport_offset(skb) << EDMA_TPD_HDR_SHIFT); -+ } else if (flags_transmit & EDMA_HW_CHECKSUM) { -+ u8 css, cso; -+ cso = skb_checksum_start_offset(skb); -+ css = cso + skb->csum_offset; -+ -+ word1 |= (EDMA_TPD_CUSTOM_CSUM_EN); -+ word1 |= (cso >> 1) << EDMA_TPD_HDR_SHIFT; -+ word1 |= ((css >> 1) << EDMA_TPD_CUSTOM_CSUM_SHIFT); -+ } -+ -+ if (skb->protocol == htons(ETH_P_PPP_SES)) -+ word1 |= EDMA_TPD_PPPOE_EN; -+ -+ if (flags_transmit & EDMA_VLAN_TX_TAG_INSERT_FLAG) { -+ switch(skb->vlan_proto) { -+ case htons(ETH_P_8021Q): -+ word3 |= (1 << EDMA_TX_INS_CVLAN); -+ word3 |= skb_vlan_tag_get(skb) << EDMA_TX_CVLAN_TAG_SHIFT; -+ break; -+ case htons(ETH_P_8021AD): -+ word1 |= (1 << EDMA_TX_INS_SVLAN); -+ svlan_tag = skb_vlan_tag_get(skb) << EDMA_TX_SVLAN_TAG_SHIFT; -+ break; -+ default: -+ dev_err(&pdev->dev, "no ctag or stag present\n"); -+ goto vlan_tag_error; -+ } -+ } else if (flags_transmit & EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG) { -+ word3 |= (1 << EDMA_TX_INS_CVLAN); -+ word3 |= (adapter->default_vlan_tag) << EDMA_TX_CVLAN_TAG_SHIFT; -+ } -+ -+ if (packet_is_rstp) { -+ word3 |= dp_bitmap << EDMA_TPD_PORT_BITMAP_SHIFT; -+ word3 |= from_cpu << EDMA_TPD_FROM_CPU_SHIFT; -+ } else { -+ word3 |= adapter->dp_bitmap << EDMA_TPD_PORT_BITMAP_SHIFT; -+ } -+ -+ buf_len = skb_headlen(skb); -+ -+ if (lso_word1) { -+ if (lso_word1 & EDMA_TPD_LSO_V2_EN) { -+ -+ /* IPv6 LSOv2 descriptor */ -+ start_tpd = tpd = edma_get_next_tpd(edma_cinfo, queue_id); -+ sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id); -+ sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_NONE; -+ -+ /* LSOv2 descriptor overrides addr field to pass length */ -+ tpd->addr = cpu_to_le16(skb->len); -+ tpd->svlan_tag = svlan_tag; -+ tpd->word1 = word1 | lso_word1; -+ tpd->word3 = word3; -+ } -+ -+ tpd = edma_get_next_tpd(edma_cinfo, queue_id); -+ if (!start_tpd) -+ start_tpd = tpd; -+ sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id); -+ -+ /* The last buffer info contain the skb address, -+ * so skb will be freed after unmap -+ */ -+ sw_desc->length = lso_desc_len; -+ sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD; -+ -+ sw_desc->dma = dma_map_single(&adapter->pdev->dev, -+ skb->data, buf_len, DMA_TO_DEVICE); -+ if (dma_mapping_error(&pdev->dev, sw_desc->dma)) -+ goto dma_error; -+ -+ tpd->addr = cpu_to_le32(sw_desc->dma); -+ tpd->len = cpu_to_le16(buf_len); -+ -+ tpd->svlan_tag = svlan_tag; -+ tpd->word1 = word1 | lso_word1; -+ tpd->word3 = word3; -+ -+ /* The last buffer info contain the skb address, -+ * so it will be freed after unmap -+ */ -+ sw_desc->length = lso_desc_len; -+ sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD; -+ -+ buf_len = 0; -+ } -+ -+ if (likely(buf_len)) { -+ -+ /* TODO Do not dequeue descriptor if there is a potential error */ -+ tpd = edma_get_next_tpd(edma_cinfo, queue_id); -+ -+ if (!start_tpd) -+ start_tpd = tpd; -+ -+ sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id); -+ -+ /* The last buffer info contain the skb address, -+ * so it will be free after unmap -+ */ -+ sw_desc->length = buf_len; -+ sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD; -+ sw_desc->dma = dma_map_single(&adapter->pdev->dev, -+ skb->data, buf_len, DMA_TO_DEVICE); -+ if (dma_mapping_error(&pdev->dev, sw_desc->dma)) -+ goto dma_error; -+ -+ tpd->addr = cpu_to_le32(sw_desc->dma); -+ tpd->len = cpu_to_le16(buf_len); -+ -+ tpd->svlan_tag = svlan_tag; -+ tpd->word1 = word1 | lso_word1; -+ tpd->word3 = word3; -+ } -+ -+ /* Walk through all paged fragments */ -+ while (nr_frags--) { -+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; -+ buf_len = skb_frag_size(frag); -+ tpd = edma_get_next_tpd(edma_cinfo, queue_id); -+ sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id); -+ sw_desc->length = buf_len; -+ sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_FRAG; -+ -+ sw_desc->dma = skb_frag_dma_map(&pdev->dev, frag, 0, buf_len, DMA_TO_DEVICE); -+ -+ if (dma_mapping_error(NULL, sw_desc->dma)) -+ goto dma_error; -+ -+ tpd->addr = cpu_to_le32(sw_desc->dma); -+ tpd->len = cpu_to_le16(buf_len); -+ -+ tpd->svlan_tag = svlan_tag; -+ tpd->word1 = word1 | lso_word1; -+ tpd->word3 = word3; -+ i++; -+ } -+ -+ /* Walk through all fraglist skbs */ -+ skb_walk_frags(skb, iter_skb) { -+ buf_len = iter_skb->len; -+ tpd = edma_get_next_tpd(edma_cinfo, queue_id); -+ sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id); -+ sw_desc->length = buf_len; -+ sw_desc->dma = dma_map_single(&adapter->pdev->dev, -+ iter_skb->data, buf_len, DMA_TO_DEVICE); -+ -+ if (dma_mapping_error(NULL, sw_desc->dma)) -+ goto dma_error; -+ -+ tpd->addr = cpu_to_le32(sw_desc->dma); -+ tpd->len = cpu_to_le16(buf_len); -+ tpd->svlan_tag = svlan_tag; -+ tpd->word1 = word1 | lso_word1; -+ tpd->word3 = word3; -+ sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_FRAGLIST; -+ } -+ -+ if (tpd) -+ tpd->word1 |= 1 << EDMA_TPD_EOP_SHIFT; -+ -+ sw_desc->skb = skb; -+ sw_desc->flags |= EDMA_SW_DESC_FLAG_LAST; -+ -+ return 0; -+ -+dma_error: -+ edma_rollback_tx(adapter, start_tpd, queue_id); -+ dev_err(&pdev->dev, "TX DMA map failed\n"); -+vlan_tag_error: -+ return -ENOMEM; -+} -+ -+/* edma_check_link() -+ * check Link status -+ */ -+static int edma_check_link(struct edma_adapter *adapter) -+{ -+ struct phy_device *phydev = adapter->phydev; -+ -+ if (!(adapter->poll_required)) -+ return __EDMA_LINKUP; -+ -+ if (phydev->link) -+ return __EDMA_LINKUP; -+ -+ return __EDMA_LINKDOWN; -+} -+ -+/* edma_adjust_link() -+ * check for edma link status -+ */ -+void edma_adjust_link(struct net_device *netdev) -+{ -+ int status; -+ struct edma_adapter *adapter = netdev_priv(netdev); -+ struct phy_device *phydev = adapter->phydev; -+ -+ if (!test_bit(__EDMA_UP, &adapter->state_flags)) -+ return; -+ -+ status = edma_check_link(adapter); -+ -+ if (status == __EDMA_LINKUP && adapter->link_state == __EDMA_LINKDOWN) { -+ dev_info(&adapter->pdev->dev, "%s: GMAC Link is up with phy_speed=%d\n", netdev->name, phydev->speed); -+ adapter->link_state = __EDMA_LINKUP; -+ netif_carrier_on(netdev); -+ if (netif_running(netdev)) -+ netif_tx_wake_all_queues(netdev); -+ } else if (status == __EDMA_LINKDOWN && adapter->link_state == __EDMA_LINKUP) { -+ dev_info(&adapter->pdev->dev, "%s: GMAC Link is down\n", netdev->name); -+ adapter->link_state = __EDMA_LINKDOWN; -+ netif_carrier_off(netdev); -+ netif_tx_stop_all_queues(netdev); -+ } -+} -+ -+/* edma_get_stats() -+ * Statistics api used to retreive the tx/rx statistics -+ */ -+struct net_device_stats *edma_get_stats(struct net_device *netdev) -+{ -+ struct edma_adapter *adapter = netdev_priv(netdev); -+ -+ return &adapter->stats; -+} -+ -+/* edma_xmit() -+ * Main api to be called by the core for packet transmission -+ */ -+netdev_tx_t edma_xmit(struct sk_buff *skb, -+ struct net_device *net_dev) -+{ -+ struct edma_adapter *adapter = netdev_priv(net_dev); -+ struct edma_common_info *edma_cinfo = adapter->edma_cinfo; -+ struct edma_tx_desc_ring *etdr; -+ u16 from_cpu, dp_bitmap, txq_id; -+ int ret, nr_frags = 0, num_tpds_needed = 1, queue_id; -+ unsigned int flags_transmit = 0; -+ bool packet_is_rstp = false; -+ struct netdev_queue *nq = NULL; -+ -+ if (skb_shinfo(skb)->nr_frags) { -+ nr_frags = skb_shinfo(skb)->nr_frags; -+ num_tpds_needed += nr_frags; -+ } else if (skb_has_frag_list(skb)) { -+ struct sk_buff *iter_skb; -+ -+ skb_walk_frags(skb, iter_skb) -+ num_tpds_needed++; -+ } -+ -+ if (num_tpds_needed > EDMA_MAX_SKB_FRAGS) { -+ dev_err(&net_dev->dev, -+ "skb received with fragments %d which is more than %lu", -+ num_tpds_needed, EDMA_MAX_SKB_FRAGS); -+ dev_kfree_skb_any(skb); -+ adapter->stats.tx_errors++; -+ return NETDEV_TX_OK; -+ } -+ -+ if (edma_stp_rstp) { -+ u16 ath_hdr, ath_eth_type; -+ u8 mac_addr[EDMA_ETH_HDR_LEN]; -+ ath_eth_type = ntohs(*(uint16_t *)&skb->data[12]); -+ if (ath_eth_type == edma_ath_eth_type) { -+ packet_is_rstp = true; -+ ath_hdr = htons(*(uint16_t *)&skb->data[14]); -+ dp_bitmap = ath_hdr & EDMA_TX_ATH_HDR_PORT_BITMAP_MASK; -+ from_cpu = (ath_hdr & EDMA_TX_ATH_HDR_FROM_CPU_MASK) >> EDMA_TX_ATH_HDR_FROM_CPU_SHIFT; -+ memcpy(mac_addr, skb->data, EDMA_ETH_HDR_LEN); -+ -+ skb_pull(skb, 4); -+ -+ memcpy(skb->data, mac_addr, EDMA_ETH_HDR_LEN); -+ } -+ } -+ -+ /* this will be one of the 4 TX queues exposed to linux kernel */ -+ txq_id = skb_get_queue_mapping(skb); -+ queue_id = edma_tx_queue_get(adapter, skb, txq_id); -+ etdr = edma_cinfo->tpd_ring[queue_id]; -+ nq = netdev_get_tx_queue(net_dev, txq_id); -+ -+ local_bh_disable(); -+ /* Tx is not handled in bottom half context. Hence, we need to protect -+ * Tx from tasks and bottom half -+ */ -+ -+ if (num_tpds_needed > edma_tpd_available(edma_cinfo, queue_id)) { -+ /* not enough descriptor, just stop queue */ -+ netif_tx_stop_queue(nq); -+ local_bh_enable(); -+ dev_dbg(&net_dev->dev, "Not enough descriptors available"); -+ edma_cinfo->edma_ethstats.tx_desc_error++; -+ return NETDEV_TX_BUSY; -+ } -+ -+ /* Check and mark VLAN tag offload */ -+ if (skb_vlan_tag_present(skb)) -+ flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG; -+ else if (adapter->default_vlan_tag) -+ flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG; -+ -+ /* Check and mark checksum offload */ -+ if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) -+ flags_transmit |= EDMA_HW_CHECKSUM; -+ -+ /* Map and fill descriptor for Tx */ -+ ret = edma_tx_map_and_fill(edma_cinfo, adapter, skb, queue_id, -+ flags_transmit, from_cpu, dp_bitmap, packet_is_rstp, nr_frags); -+ if (ret) { -+ dev_kfree_skb_any(skb); -+ adapter->stats.tx_errors++; -+ goto netdev_okay; -+ } -+ -+ /* Update SW producer index */ -+ edma_tx_update_hw_idx(edma_cinfo, skb, queue_id); -+ -+ /* update tx statistics */ -+ adapter->stats.tx_packets++; -+ adapter->stats.tx_bytes += skb->len; -+ -+netdev_okay: -+ local_bh_enable(); -+ return NETDEV_TX_OK; -+} -+ -+/* -+ * edma_flow_may_expire() -+ * Timer function called periodically to delete the node -+ */ -+void edma_flow_may_expire(struct timer_list *t) -+{ -+ struct edma_rfs_flow_table *table = from_timer(table, t, expire_rfs); -+ struct edma_adapter *adapter = -+ container_of(table, typeof(*adapter), rfs); -+ int j; -+ -+ spin_lock_bh(&adapter->rfs.rfs_ftab_lock); -+ for (j = 0; j < EDMA_RFS_EXPIRE_COUNT_PER_CALL; j++) { -+ struct hlist_head *hhead; -+ struct hlist_node *tmp; -+ struct edma_rfs_filter_node *n; -+ bool res; -+ -+ hhead = &adapter->rfs.hlist_head[adapter->rfs.hashtoclean++]; -+ hlist_for_each_entry_safe(n, tmp, hhead, node) { -+ res = rps_may_expire_flow(adapter->netdev, n->rq_id, -+ n->flow_id, n->filter_id); -+ if (res) { -+ int ret; -+ ret = edma_delete_rfs_filter(adapter, n); -+ if (ret < 0) -+ dev_dbg(&adapter->netdev->dev, -+ "RFS entry %d not allowed to be flushed by Switch", -+ n->flow_id); -+ else { -+ hlist_del(&n->node); -+ kfree(n); -+ adapter->rfs.filter_available++; -+ } -+ } -+ } -+ } -+ -+ adapter->rfs.hashtoclean = adapter->rfs.hashtoclean & (EDMA_RFS_FLOW_ENTRIES - 1); -+ spin_unlock_bh(&adapter->rfs.rfs_ftab_lock); -+ mod_timer(&adapter->rfs.expire_rfs, jiffies + HZ / 4); -+} -+ -+/* edma_rx_flow_steer() -+ * Called by core to to steer the flow to CPU -+ */ -+int edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, -+ u16 rxq, u32 flow_id) -+{ -+ struct flow_keys keys; -+ struct edma_rfs_filter_node *filter_node; -+ struct edma_adapter *adapter = netdev_priv(dev); -+ u16 hash_tblid; -+ int res; -+ -+ if (skb->protocol == htons(ETH_P_IPV6)) { -+ dev_err(&adapter->pdev->dev, "IPv6 not supported\n"); -+ res = -EINVAL; -+ goto no_protocol_err; -+ } -+ -+ /* Dissect flow parameters -+ * We only support IPv4 + TCP/UDP -+ */ -+ res = skb_flow_dissect_flow_keys(skb, &keys, 0); -+ if (!((keys.basic.ip_proto == IPPROTO_TCP) || (keys.basic.ip_proto == IPPROTO_UDP))) { -+ res = -EPROTONOSUPPORT; -+ goto no_protocol_err; -+ } -+ -+ /* Check if table entry exists */ -+ hash_tblid = skb_get_hash_raw(skb) & EDMA_RFS_FLOW_ENTRIES_MASK; -+ -+ spin_lock_bh(&adapter->rfs.rfs_ftab_lock); -+ filter_node = edma_rfs_key_search(&adapter->rfs.hlist_head[hash_tblid], &keys); -+ -+ if (filter_node) { -+ if (rxq == filter_node->rq_id) { -+ res = -EEXIST; -+ goto out; -+ } else { -+ res = edma_delete_rfs_filter(adapter, filter_node); -+ if (res < 0) -+ dev_warn(&adapter->netdev->dev, -+ "Cannot steer flow %d to different queue", -+ filter_node->flow_id); -+ else { -+ adapter->rfs.filter_available++; -+ res = edma_add_rfs_filter(adapter, &keys, rxq, filter_node); -+ if (res < 0) { -+ dev_warn(&adapter->netdev->dev, -+ "Cannot steer flow %d to different queue", -+ filter_node->flow_id); -+ } else { -+ adapter->rfs.filter_available--; -+ filter_node->rq_id = rxq; -+ filter_node->filter_id = res; -+ } -+ } -+ } -+ } else { -+ if (adapter->rfs.filter_available == 0) { -+ res = -EBUSY; -+ goto out; -+ } -+ -+ filter_node = kmalloc(sizeof(*filter_node), GFP_ATOMIC); -+ if (!filter_node) { -+ res = -ENOMEM; -+ goto out; -+ } -+ -+ res = edma_add_rfs_filter(adapter, &keys, rxq, filter_node); -+ if (res < 0) { -+ kfree(filter_node); -+ goto out; -+ } -+ -+ adapter->rfs.filter_available--; -+ filter_node->rq_id = rxq; -+ filter_node->filter_id = res; -+ filter_node->flow_id = flow_id; -+ filter_node->keys = keys; -+ INIT_HLIST_NODE(&filter_node->node); -+ hlist_add_head(&filter_node->node, &adapter->rfs.hlist_head[hash_tblid]); -+ } -+ -+out: -+ spin_unlock_bh(&adapter->rfs.rfs_ftab_lock); -+no_protocol_err: -+ return res; -+} -+ -+/* edma_register_rfs_filter() -+ * Add RFS filter callback -+ */ -+int edma_register_rfs_filter(struct net_device *netdev, -+ set_rfs_filter_callback_t set_filter) -+{ -+ struct edma_adapter *adapter = netdev_priv(netdev); -+ -+ spin_lock_bh(&adapter->rfs.rfs_ftab_lock); -+ -+ if (adapter->set_rfs_rule) { -+ spin_unlock_bh(&adapter->rfs.rfs_ftab_lock); -+ return -1; -+ } -+ -+ adapter->set_rfs_rule = set_filter; -+ spin_unlock_bh(&adapter->rfs.rfs_ftab_lock); -+ -+ return 0; -+} -+ -+/* edma_alloc_tx_rings() -+ * Allocate rx rings -+ */ -+int edma_alloc_tx_rings(struct edma_common_info *edma_cinfo) -+{ -+ struct platform_device *pdev = edma_cinfo->pdev; -+ int i, err = 0; -+ -+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) { -+ err = edma_alloc_tx_ring(edma_cinfo, edma_cinfo->tpd_ring[i]); -+ if (err) { -+ dev_err(&pdev->dev, "Tx Queue alloc %u failed\n", i); -+ return err; -+ } -+ } -+ -+ return 0; -+} -+ -+/* edma_free_tx_rings() -+ * Free tx rings -+ */ -+void edma_free_tx_rings(struct edma_common_info *edma_cinfo) -+{ -+ int i; -+ -+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) -+ edma_free_tx_ring(edma_cinfo, edma_cinfo->tpd_ring[i]); -+} -+ -+/* edma_free_tx_resources() -+ * Free buffers associated with tx rings -+ */ -+void edma_free_tx_resources(struct edma_common_info *edma_cinfo) -+{ -+ struct edma_tx_desc_ring *etdr; -+ struct edma_sw_desc *sw_desc; -+ struct platform_device *pdev = edma_cinfo->pdev; -+ int i, j; -+ -+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) { -+ etdr = edma_cinfo->tpd_ring[i]; -+ for (j = 0; j < EDMA_TX_RING_SIZE; j++) { -+ sw_desc = &etdr->sw_desc[j]; -+ if (sw_desc->flags & (EDMA_SW_DESC_FLAG_SKB_HEAD | -+ EDMA_SW_DESC_FLAG_SKB_FRAG | EDMA_SW_DESC_FLAG_SKB_FRAGLIST)) -+ edma_tx_unmap_and_free(pdev, sw_desc); -+ } -+ } -+} -+ -+/* edma_alloc_rx_rings() -+ * Allocate rx rings -+ */ -+int edma_alloc_rx_rings(struct edma_common_info *edma_cinfo) -+{ -+ struct platform_device *pdev = edma_cinfo->pdev; -+ int i, j, err = 0; -+ -+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) { -+ err = edma_alloc_rx_ring(edma_cinfo, edma_cinfo->rfd_ring[j]); -+ if (err) { -+ dev_err(&pdev->dev, "Rx Queue alloc%u failed\n", i); -+ return err; -+ } -+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1); -+ } -+ -+ return 0; -+} -+ -+/* edma_free_rx_rings() -+ * free rx rings -+ */ -+void edma_free_rx_rings(struct edma_common_info *edma_cinfo) -+{ -+ int i, j; -+ -+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) { -+ edma_free_rx_ring(edma_cinfo, edma_cinfo->rfd_ring[j]); -+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1); -+ } -+} -+ -+/* edma_free_queues() -+ * Free the queues allocaated -+ */ -+void edma_free_queues(struct edma_common_info *edma_cinfo) -+{ -+ int i , j; -+ -+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) { -+ if (edma_cinfo->tpd_ring[i]) -+ kfree(edma_cinfo->tpd_ring[i]); -+ edma_cinfo->tpd_ring[i] = NULL; -+ } -+ -+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) { -+ if (edma_cinfo->rfd_ring[j]) -+ kfree(edma_cinfo->rfd_ring[j]); -+ edma_cinfo->rfd_ring[j] = NULL; -+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1); -+ } -+ -+ edma_cinfo->num_rx_queues = 0; -+ edma_cinfo->num_tx_queues = 0; -+ -+ return; -+} -+ -+/* edma_free_rx_resources() -+ * Free buffers associated with tx rings -+ */ -+void edma_free_rx_resources(struct edma_common_info *edma_cinfo) -+{ -+ struct edma_rfd_desc_ring *erdr; -+ struct edma_sw_desc *sw_desc; -+ struct platform_device *pdev = edma_cinfo->pdev; -+ int i, j, k; -+ -+ for (i = 0, k = 0; i < edma_cinfo->num_rx_queues; i++) { -+ erdr = edma_cinfo->rfd_ring[k]; -+ for (j = 0; j < EDMA_RX_RING_SIZE; j++) { -+ sw_desc = &erdr->sw_desc[j]; -+ if (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD)) { -+ dma_unmap_single(&pdev->dev, sw_desc->dma, -+ sw_desc->length, DMA_FROM_DEVICE); -+ edma_clean_rfd(erdr, j); -+ } else if ((sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_FRAG)) { -+ dma_unmap_page(&pdev->dev, sw_desc->dma, -+ sw_desc->length, DMA_FROM_DEVICE); -+ edma_clean_rfd(erdr, j); -+ } -+ } -+ k += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1); -+ -+ } -+} -+ -+/* edma_alloc_queues_tx() -+ * Allocate memory for all rings -+ */ -+int edma_alloc_queues_tx(struct edma_common_info *edma_cinfo) -+{ -+ int i; -+ -+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) { -+ struct edma_tx_desc_ring *etdr; -+ etdr = kzalloc(sizeof(struct edma_tx_desc_ring), GFP_KERNEL); -+ if (!etdr) -+ goto err; -+ etdr->count = edma_cinfo->tx_ring_count; -+ edma_cinfo->tpd_ring[i] = etdr; -+ } -+ -+ return 0; -+err: -+ edma_free_queues(edma_cinfo); -+ return -1; -+} -+ -+/* edma_alloc_queues_rx() -+ * Allocate memory for all rings -+ */ -+int edma_alloc_queues_rx(struct edma_common_info *edma_cinfo) -+{ -+ int i, j; -+ -+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) { -+ struct edma_rfd_desc_ring *rfd_ring; -+ rfd_ring = kzalloc(sizeof(struct edma_rfd_desc_ring), -+ GFP_KERNEL); -+ if (!rfd_ring) -+ goto err; -+ rfd_ring->count = edma_cinfo->rx_ring_count; -+ edma_cinfo->rfd_ring[j] = rfd_ring; -+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1); -+ } -+ return 0; -+err: -+ edma_free_queues(edma_cinfo); -+ return -1; -+} -+ -+/* edma_clear_irq_status() -+ * Clear interrupt status -+ */ -+void edma_clear_irq_status() -+{ -+ edma_write_reg(EDMA_REG_RX_ISR, 0xff); -+ edma_write_reg(EDMA_REG_TX_ISR, 0xffff); -+ edma_write_reg(EDMA_REG_MISC_ISR, 0x1fff); -+ edma_write_reg(EDMA_REG_WOL_ISR, 0x1); -+}; -+ -+/* edma_configure() -+ * Configure skb, edma interrupts and control register. -+ */ -+int edma_configure(struct edma_common_info *edma_cinfo) -+{ -+ struct edma_hw *hw = &edma_cinfo->hw; -+ u32 intr_modrt_data; -+ u32 intr_ctrl_data = 0; -+ int i, j, ret_count; -+ -+ edma_read_reg(EDMA_REG_INTR_CTRL, &intr_ctrl_data); -+ intr_ctrl_data &= ~(1 << EDMA_INTR_SW_IDX_W_TYP_SHIFT); -+ intr_ctrl_data |= hw->intr_sw_idx_w << EDMA_INTR_SW_IDX_W_TYP_SHIFT; -+ edma_write_reg(EDMA_REG_INTR_CTRL, intr_ctrl_data); -+ -+ edma_clear_irq_status(); -+ -+ /* Clear any WOL status */ -+ edma_write_reg(EDMA_REG_WOL_CTRL, 0); -+ intr_modrt_data = (EDMA_TX_IMT << EDMA_IRQ_MODRT_TX_TIMER_SHIFT); -+ intr_modrt_data |= (EDMA_RX_IMT << EDMA_IRQ_MODRT_RX_TIMER_SHIFT); -+ edma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data); -+ edma_configure_tx(edma_cinfo); -+ edma_configure_rx(edma_cinfo); -+ -+ /* Allocate the RX buffer */ -+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) { -+ struct edma_rfd_desc_ring *ring = edma_cinfo->rfd_ring[j]; -+ ret_count = edma_alloc_rx_buf(edma_cinfo, ring, ring->count, j); -+ if (ret_count) { -+ dev_dbg(&edma_cinfo->pdev->dev, "not all rx buffers allocated\n"); -+ } -+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1); -+ } -+ -+ /* Configure descriptor Ring */ -+ edma_init_desc(edma_cinfo); -+ return 0; -+} -+ -+/* edma_irq_enable() -+ * Enable default interrupt generation settings -+ */ -+void edma_irq_enable(struct edma_common_info *edma_cinfo) -+{ -+ struct edma_hw *hw = &edma_cinfo->hw; -+ int i, j; -+ -+ edma_write_reg(EDMA_REG_RX_ISR, 0xff); -+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) { -+ edma_write_reg(EDMA_REG_RX_INT_MASK_Q(j), hw->rx_intr_mask); -+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1); -+ } -+ edma_write_reg(EDMA_REG_TX_ISR, 0xffff); -+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) -+ edma_write_reg(EDMA_REG_TX_INT_MASK_Q(i), hw->tx_intr_mask); -+} -+ -+/* edma_irq_disable() -+ * Disable Interrupt -+ */ -+void edma_irq_disable(struct edma_common_info *edma_cinfo) -+{ -+ int i; -+ -+ for (i = 0; i < EDMA_MAX_RECEIVE_QUEUE; i++) -+ edma_write_reg(EDMA_REG_RX_INT_MASK_Q(i), 0x0); -+ -+ for (i = 0; i < EDMA_MAX_TRANSMIT_QUEUE; i++) -+ edma_write_reg(EDMA_REG_TX_INT_MASK_Q(i), 0x0); -+ edma_write_reg(EDMA_REG_MISC_IMR, 0); -+ edma_write_reg(EDMA_REG_WOL_IMR, 0); -+} -+ -+/* edma_free_irqs() -+ * Free All IRQs -+ */ -+void edma_free_irqs(struct edma_adapter *adapter) -+{ -+ struct edma_common_info *edma_cinfo = adapter->edma_cinfo; -+ int i, j; -+ int k = ((edma_cinfo->num_rx_queues == 4) ? 1 : 2); -+ -+ for (i = 0; i < CONFIG_NR_CPUS; i++) { -+ for (j = edma_cinfo->edma_percpu_info[i].tx_start; j < (edma_cinfo->edma_percpu_info[i].tx_start + 4); j++) -+ free_irq(edma_cinfo->tx_irq[j], &edma_cinfo->edma_percpu_info[i]); -+ -+ for (j = edma_cinfo->edma_percpu_info[i].rx_start; j < (edma_cinfo->edma_percpu_info[i].rx_start + k); j++) -+ free_irq(edma_cinfo->rx_irq[j], &edma_cinfo->edma_percpu_info[i]); -+ } -+} -+ -+/* edma_enable_rx_ctrl() -+ * Enable RX queue control -+ */ -+void edma_enable_rx_ctrl(struct edma_hw *hw) -+{ -+ u32 data; -+ -+ edma_read_reg(EDMA_REG_RXQ_CTRL, &data); -+ data |= EDMA_RXQ_CTRL_EN; -+ edma_write_reg(EDMA_REG_RXQ_CTRL, data); -+} -+ -+ -+/* edma_enable_tx_ctrl() -+ * Enable TX queue control -+ */ -+void edma_enable_tx_ctrl(struct edma_hw *hw) -+{ -+ u32 data; -+ -+ edma_read_reg(EDMA_REG_TXQ_CTRL, &data); -+ data |= EDMA_TXQ_CTRL_TXQ_EN; -+ edma_write_reg(EDMA_REG_TXQ_CTRL, data); -+} -+ -+/* edma_stop_rx_tx() -+ * Disable RX/TQ Queue control -+ */ -+void edma_stop_rx_tx(struct edma_hw *hw) -+{ -+ u32 data; -+ -+ edma_read_reg(EDMA_REG_RXQ_CTRL, &data); -+ data &= ~EDMA_RXQ_CTRL_EN; -+ edma_write_reg(EDMA_REG_RXQ_CTRL, data); -+ edma_read_reg(EDMA_REG_TXQ_CTRL, &data); -+ data &= ~EDMA_TXQ_CTRL_TXQ_EN; -+ edma_write_reg(EDMA_REG_TXQ_CTRL, data); -+} -+ -+/* edma_reset() -+ * Reset the EDMA -+ */ -+int edma_reset(struct edma_common_info *edma_cinfo) -+{ -+ struct edma_hw *hw = &edma_cinfo->hw; -+ -+ edma_irq_disable(edma_cinfo); -+ -+ edma_clear_irq_status(); -+ -+ edma_stop_rx_tx(hw); -+ -+ return 0; -+} -+ -+/* edma_fill_netdev() -+ * Fill netdev for each etdr -+ */ -+int edma_fill_netdev(struct edma_common_info *edma_cinfo, int queue_id, -+ int dev, int txq_id) -+{ -+ struct edma_tx_desc_ring *etdr; -+ int i = 0; -+ -+ etdr = edma_cinfo->tpd_ring[queue_id]; -+ -+ while (etdr->netdev[i]) -+ i++; -+ -+ if (i >= EDMA_MAX_NETDEV_PER_QUEUE) -+ return -1; -+ -+ /* Populate the netdev associated with the tpd ring */ -+ etdr->netdev[i] = edma_netdev[dev]; -+ etdr->nq[i] = netdev_get_tx_queue(edma_netdev[dev], txq_id); -+ -+ return 0; -+} -+ -+/* edma_set_mac() -+ * Change the Ethernet Address of the NIC -+ */ -+int edma_set_mac_addr(struct net_device *netdev, void *p) -+{ -+ struct sockaddr *addr = p; -+ -+ if (!is_valid_ether_addr(addr->sa_data)) -+ return -EINVAL; -+ -+ if (netif_running(netdev)) -+ return -EBUSY; -+ -+ memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); -+ return 0; -+} -+ -+/* edma_set_stp_rstp() -+ * set stp/rstp -+ */ -+void edma_set_stp_rstp(bool rstp) -+{ -+ edma_stp_rstp = rstp; -+} -+ -+/* edma_assign_ath_hdr_type() -+ * assign atheros header eth type -+ */ -+void edma_assign_ath_hdr_type(int eth_type) -+{ -+ edma_ath_eth_type = eth_type & EDMA_ETH_TYPE_MASK; -+} -+ -+/* edma_get_default_vlan_tag() -+ * Used by other modules to get the default vlan tag -+ */ -+int edma_get_default_vlan_tag(struct net_device *netdev) -+{ -+ struct edma_adapter *adapter = netdev_priv(netdev); -+ -+ if (adapter->default_vlan_tag) -+ return adapter->default_vlan_tag; -+ -+ return 0; -+} -+ -+/* edma_open() -+ * gets called when netdevice is up, start the queue. -+ */ -+int edma_open(struct net_device *netdev) -+{ -+ struct edma_adapter *adapter = netdev_priv(netdev); -+ struct platform_device *pdev = adapter->edma_cinfo->pdev; -+ -+ netif_tx_start_all_queues(netdev); -+ edma_initialise_rfs_flow_table(adapter); -+ set_bit(__EDMA_UP, &adapter->state_flags); -+ -+ /* if Link polling is enabled, in our case enabled for WAN, then -+ * do a phy start, else always set link as UP -+ */ -+ if (adapter->poll_required) { -+ if (!IS_ERR(adapter->phydev)) { -+ phy_start(adapter->phydev); -+ phy_start_aneg(adapter->phydev); -+ adapter->link_state = __EDMA_LINKDOWN; -+ } else { -+ dev_dbg(&pdev->dev, "Invalid PHY device for a link polled interface\n"); -+ } -+ } else { -+ adapter->link_state = __EDMA_LINKUP; -+ netif_carrier_on(netdev); -+ } -+ -+ return 0; -+} -+ -+ -+/* edma_close() -+ * gets called when netdevice is down, stops the queue. -+ */ -+int edma_close(struct net_device *netdev) -+{ -+ struct edma_adapter *adapter = netdev_priv(netdev); -+ -+ edma_free_rfs_flow_table(adapter); -+ netif_carrier_off(netdev); -+ netif_tx_stop_all_queues(netdev); -+ -+ if (adapter->poll_required) { -+ if (!IS_ERR(adapter->phydev)) -+ phy_stop(adapter->phydev); -+ } -+ -+ adapter->link_state = __EDMA_LINKDOWN; -+ -+ /* Set GMAC state to UP before link state is checked -+ */ -+ clear_bit(__EDMA_UP, &adapter->state_flags); -+ -+ return 0; -+} -+ -+/* edma_poll -+ * polling function that gets called when the napi gets scheduled. -+ * -+ * Main sequence of task performed in this api -+ * is clear irq status -> clear_tx_irq -> clean_rx_irq-> -+ * enable interrupts. -+ */ -+int edma_poll(struct napi_struct *napi, int budget) -+{ -+ struct edma_per_cpu_queues_info *edma_percpu_info = container_of(napi, -+ struct edma_per_cpu_queues_info, napi); -+ struct edma_common_info *edma_cinfo = edma_percpu_info->edma_cinfo; -+ u32 reg_data; -+ u32 shadow_rx_status, shadow_tx_status; -+ int queue_id; -+ int i, work_done = 0; -+ -+ /* Store the Rx/Tx status by ANDing it with -+ * appropriate CPU RX?TX mask -+ */ -+ edma_read_reg(EDMA_REG_RX_ISR, ®_data); -+ edma_percpu_info->rx_status |= reg_data & edma_percpu_info->rx_mask; -+ shadow_rx_status = edma_percpu_info->rx_status; -+ edma_read_reg(EDMA_REG_TX_ISR, ®_data); -+ edma_percpu_info->tx_status |= reg_data & edma_percpu_info->tx_mask; -+ shadow_tx_status = edma_percpu_info->tx_status; -+ -+ /* Every core will have a start, which will be computed -+ * in probe and stored in edma_percpu_info->tx_start variable. -+ * We will shift the status bit by tx_start to obtain -+ * status bits for the core on which the current processing -+ * is happening. Since, there are 4 tx queues per core, -+ * we will run the loop till we get the correct queue to clear. -+ */ -+ while (edma_percpu_info->tx_status) { -+ queue_id = ffs(edma_percpu_info->tx_status) - 1; -+ edma_tx_complete(edma_cinfo, queue_id); -+ edma_percpu_info->tx_status &= ~(1 << queue_id); -+ } -+ -+ /* Every core will have a start, which will be computed -+ * in probe and stored in edma_percpu_info->tx_start variable. -+ * We will shift the status bit by tx_start to obtain -+ * status bits for the core on which the current processing -+ * is happening. Since, there are 4 tx queues per core, we -+ * will run the loop till we get the correct queue to clear. -+ */ -+ while (edma_percpu_info->rx_status) { -+ queue_id = ffs(edma_percpu_info->rx_status) - 1; -+ edma_rx_complete(edma_cinfo, &work_done, -+ budget, queue_id, napi); -+ -+ if (likely(work_done < budget)) -+ edma_percpu_info->rx_status &= ~(1 << queue_id); -+ else -+ break; -+ } -+ -+ /* Clear the status register, to avoid the interrupts to -+ * reoccur.This clearing of interrupt status register is -+ * done here as writing to status register only takes place -+ * once the producer/consumer index has been updated to -+ * reflect that the packet transmission/reception went fine. -+ */ -+ edma_write_reg(EDMA_REG_RX_ISR, shadow_rx_status); -+ edma_write_reg(EDMA_REG_TX_ISR, shadow_tx_status); -+ -+ /* If budget not fully consumed, exit the polling mode */ -+ if (likely(work_done < budget)) { -+ napi_complete(napi); -+ -+ /* re-enable the interrupts */ -+ for (i = 0; i < edma_cinfo->num_rxq_per_core; i++) -+ edma_write_reg(EDMA_REG_RX_INT_MASK_Q(edma_percpu_info->rx_start + i), 0x1); -+ for (i = 0; i < edma_cinfo->num_txq_per_core; i++) -+ edma_write_reg(EDMA_REG_TX_INT_MASK_Q(edma_percpu_info->tx_start + i), 0x1); -+ } -+ -+ return work_done; -+} -+ -+/* edma interrupt() -+ * interrupt handler -+ */ -+irqreturn_t edma_interrupt(int irq, void *dev) -+{ -+ struct edma_per_cpu_queues_info *edma_percpu_info = (struct edma_per_cpu_queues_info *) dev; -+ struct edma_common_info *edma_cinfo = edma_percpu_info->edma_cinfo; -+ int i; -+ -+ /* Unmask the TX/RX interrupt register */ -+ for (i = 0; i < edma_cinfo->num_rxq_per_core; i++) -+ edma_write_reg(EDMA_REG_RX_INT_MASK_Q(edma_percpu_info->rx_start + i), 0x0); -+ -+ for (i = 0; i < edma_cinfo->num_txq_per_core; i++) -+ edma_write_reg(EDMA_REG_TX_INT_MASK_Q(edma_percpu_info->tx_start + i), 0x0); -+ -+ napi_schedule(&edma_percpu_info->napi); -+ -+ return IRQ_HANDLED; -+} ---- /dev/null -+++ b/drivers/net/ethernet/qualcomm/essedma/edma.h -@@ -0,0 +1,447 @@ -+/* -+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for -+ * any purpose with or without fee is hereby granted, provided that the -+ * above copyright notice and this permission notice appear in all copies. -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+#ifndef _EDMA_H_ -+#define _EDMA_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "ess_edma.h" -+ -+#define EDMA_CPU_CORES_SUPPORTED 4 -+#define EDMA_MAX_PORTID_SUPPORTED 5 -+#define EDMA_MAX_VLAN_SUPPORTED EDMA_MAX_PORTID_SUPPORTED -+#define EDMA_MAX_PORTID_BITMAP_INDEX (EDMA_MAX_PORTID_SUPPORTED + 1) -+#define EDMA_MAX_PORTID_BITMAP_SUPPORTED 0x1f /* 0001_1111 = 0x1f */ -+#define EDMA_MAX_NETDEV_PER_QUEUE 4 /* 3 Netdev per queue, 1 space for indexing */ -+ -+#define EDMA_MAX_RECEIVE_QUEUE 8 -+#define EDMA_MAX_TRANSMIT_QUEUE 16 -+ -+/* WAN/LAN adapter number */ -+#define EDMA_WAN 0 -+#define EDMA_LAN 1 -+ -+/* VLAN tag */ -+#define EDMA_LAN_DEFAULT_VLAN 1 -+#define EDMA_WAN_DEFAULT_VLAN 2 -+ -+#define EDMA_DEFAULT_GROUP1_VLAN 1 -+#define EDMA_DEFAULT_GROUP2_VLAN 2 -+#define EDMA_DEFAULT_GROUP3_VLAN 3 -+#define EDMA_DEFAULT_GROUP4_VLAN 4 -+#define EDMA_DEFAULT_GROUP5_VLAN 5 -+ -+/* Queues exposed to linux kernel */ -+#define EDMA_NETDEV_TX_QUEUE 4 -+#define EDMA_NETDEV_RX_QUEUE 4 -+ -+/* Number of queues per core */ -+#define EDMA_NUM_TXQ_PER_CORE 4 -+#define EDMA_NUM_RXQ_PER_CORE 2 -+ -+#define EDMA_TPD_EOP_SHIFT 31 -+ -+#define EDMA_PORT_ID_SHIFT 12 -+#define EDMA_PORT_ID_MASK 0x7 -+ -+/* tpd word 3 bit 18-28 */ -+#define EDMA_TPD_PORT_BITMAP_SHIFT 18 -+ -+#define EDMA_TPD_FROM_CPU_SHIFT 25 -+ -+#define EDMA_FROM_CPU_MASK 0x80 -+#define EDMA_SKB_PRIORITY_MASK 0x38 -+ -+/* TX/RX descriptor ring count */ -+/* should be a power of 2 */ -+#define EDMA_RX_RING_SIZE 128 -+#define EDMA_TX_RING_SIZE 128 -+ -+/* Flags used in paged/non paged mode */ -+#define EDMA_RX_HEAD_BUFF_SIZE_JUMBO 256 -+#define EDMA_RX_HEAD_BUFF_SIZE 1540 -+ -+/* MAX frame size supported by switch */ -+#define EDMA_MAX_JUMBO_FRAME_SIZE 9216 -+ -+/* Configurations */ -+#define EDMA_INTR_CLEAR_TYPE 0 -+#define EDMA_INTR_SW_IDX_W_TYPE 0 -+#define EDMA_FIFO_THRESH_TYPE 0 -+#define EDMA_RSS_TYPE 0 -+#define EDMA_RX_IMT 0x0020 -+#define EDMA_TX_IMT 0x0050 -+#define EDMA_TPD_BURST 5 -+#define EDMA_TXF_BURST 0x100 -+#define EDMA_RFD_BURST 8 -+#define EDMA_RFD_THR 16 -+#define EDMA_RFD_LTHR 0 -+ -+/* RX/TX per CPU based mask/shift */ -+#define EDMA_TX_PER_CPU_MASK 0xF -+#define EDMA_RX_PER_CPU_MASK 0x3 -+#define EDMA_TX_PER_CPU_MASK_SHIFT 0x2 -+#define EDMA_RX_PER_CPU_MASK_SHIFT 0x1 -+#define EDMA_TX_CPU_START_SHIFT 0x2 -+#define EDMA_RX_CPU_START_SHIFT 0x1 -+ -+/* FLags used in transmit direction */ -+#define EDMA_HW_CHECKSUM 0x00000001 -+#define EDMA_VLAN_TX_TAG_INSERT_FLAG 0x00000002 -+#define EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG 0x00000004 -+ -+#define EDMA_SW_DESC_FLAG_LAST 0x1 -+#define EDMA_SW_DESC_FLAG_SKB_HEAD 0x2 -+#define EDMA_SW_DESC_FLAG_SKB_FRAG 0x4 -+#define EDMA_SW_DESC_FLAG_SKB_FRAGLIST 0x8 -+#define EDMA_SW_DESC_FLAG_SKB_NONE 0x10 -+#define EDMA_SW_DESC_FLAG_SKB_REUSE 0x20 -+ -+ -+#define EDMA_MAX_SKB_FRAGS (MAX_SKB_FRAGS + 1) -+ -+/* Ethtool specific list of EDMA supported features */ -+#define EDMA_SUPPORTED_FEATURES (SUPPORTED_10baseT_Half \ -+ | SUPPORTED_10baseT_Full \ -+ | SUPPORTED_100baseT_Half \ -+ | SUPPORTED_100baseT_Full \ -+ | SUPPORTED_1000baseT_Full) -+ -+/* Recevie side atheros Header */ -+#define EDMA_RX_ATH_HDR_VERSION 0x2 -+#define EDMA_RX_ATH_HDR_VERSION_SHIFT 14 -+#define EDMA_RX_ATH_HDR_PRIORITY_SHIFT 11 -+#define EDMA_RX_ATH_PORT_TYPE_SHIFT 6 -+#define EDMA_RX_ATH_HDR_RSTP_PORT_TYPE 0x4 -+ -+/* Transmit side atheros Header */ -+#define EDMA_TX_ATH_HDR_PORT_BITMAP_MASK 0x7F -+#define EDMA_TX_ATH_HDR_FROM_CPU_MASK 0x80 -+#define EDMA_TX_ATH_HDR_FROM_CPU_SHIFT 7 -+ -+#define EDMA_TXQ_START_CORE0 8 -+#define EDMA_TXQ_START_CORE1 12 -+#define EDMA_TXQ_START_CORE2 0 -+#define EDMA_TXQ_START_CORE3 4 -+ -+#define EDMA_TXQ_IRQ_MASK_CORE0 0x0F00 -+#define EDMA_TXQ_IRQ_MASK_CORE1 0xF000 -+#define EDMA_TXQ_IRQ_MASK_CORE2 0x000F -+#define EDMA_TXQ_IRQ_MASK_CORE3 0x00F0 -+ -+#define EDMA_ETH_HDR_LEN 12 -+#define EDMA_ETH_TYPE_MASK 0xFFFF -+ -+#define EDMA_RX_BUFFER_WRITE 16 -+#define EDMA_RFD_AVAIL_THR 80 -+ -+#define EDMA_GMAC_NO_MDIO_PHY PHY_MAX_ADDR -+ -+extern int ssdk_rfs_ipct_rule_set(__be32 ip_src, __be32 ip_dst, -+ __be16 sport, __be16 dport, -+ uint8_t proto, u16 loadbalance, bool action); -+struct edma_ethtool_statistics { -+ u32 tx_q0_pkt; -+ u32 tx_q1_pkt; -+ u32 tx_q2_pkt; -+ u32 tx_q3_pkt; -+ u32 tx_q4_pkt; -+ u32 tx_q5_pkt; -+ u32 tx_q6_pkt; -+ u32 tx_q7_pkt; -+ u32 tx_q8_pkt; -+ u32 tx_q9_pkt; -+ u32 tx_q10_pkt; -+ u32 tx_q11_pkt; -+ u32 tx_q12_pkt; -+ u32 tx_q13_pkt; -+ u32 tx_q14_pkt; -+ u32 tx_q15_pkt; -+ u32 tx_q0_byte; -+ u32 tx_q1_byte; -+ u32 tx_q2_byte; -+ u32 tx_q3_byte; -+ u32 tx_q4_byte; -+ u32 tx_q5_byte; -+ u32 tx_q6_byte; -+ u32 tx_q7_byte; -+ u32 tx_q8_byte; -+ u32 tx_q9_byte; -+ u32 tx_q10_byte; -+ u32 tx_q11_byte; -+ u32 tx_q12_byte; -+ u32 tx_q13_byte; -+ u32 tx_q14_byte; -+ u32 tx_q15_byte; -+ u32 rx_q0_pkt; -+ u32 rx_q1_pkt; -+ u32 rx_q2_pkt; -+ u32 rx_q3_pkt; -+ u32 rx_q4_pkt; -+ u32 rx_q5_pkt; -+ u32 rx_q6_pkt; -+ u32 rx_q7_pkt; -+ u32 rx_q0_byte; -+ u32 rx_q1_byte; -+ u32 rx_q2_byte; -+ u32 rx_q3_byte; -+ u32 rx_q4_byte; -+ u32 rx_q5_byte; -+ u32 rx_q6_byte; -+ u32 rx_q7_byte; -+ u32 tx_desc_error; -+}; -+ -+struct edma_mdio_data { -+ struct mii_bus *mii_bus; -+ void __iomem *membase; -+ int phy_irq[PHY_MAX_ADDR]; -+}; -+ -+/* EDMA LINK state */ -+enum edma_link_state { -+ __EDMA_LINKUP, /* Indicate link is UP */ -+ __EDMA_LINKDOWN /* Indicate link is down */ -+}; -+ -+/* EDMA GMAC state */ -+enum edma_gmac_state { -+ __EDMA_UP /* use to indicate GMAC is up */ -+}; -+ -+/* edma transmit descriptor */ -+struct edma_tx_desc { -+ __le16 len; /* full packet including CRC */ -+ __le16 svlan_tag; /* vlan tag */ -+ __le32 word1; /* byte 4-7 */ -+ __le32 addr; /* address of buffer */ -+ __le32 word3; /* byte 12 */ -+}; -+ -+/* edma receive return descriptor */ -+struct edma_rx_return_desc { -+ u16 rrd0; -+ u16 rrd1; -+ u16 rrd2; -+ u16 rrd3; -+ u16 rrd4; -+ u16 rrd5; -+ u16 rrd6; -+ u16 rrd7; -+}; -+ -+/* RFD descriptor */ -+struct edma_rx_free_desc { -+ __le32 buffer_addr; /* buffer address */ -+}; -+ -+/* edma hw specific data */ -+struct edma_hw { -+ u32 __iomem *hw_addr; /* inner register address */ -+ struct edma_adapter *adapter; /* netdevice adapter */ -+ u32 rx_intr_mask; /*rx interrupt mask */ -+ u32 tx_intr_mask; /* tx interrupt nask */ -+ u32 misc_intr_mask; /* misc interrupt mask */ -+ u32 wol_intr_mask; /* wake on lan interrupt mask */ -+ bool intr_clear_type; /* interrupt clear */ -+ bool intr_sw_idx_w; /* interrupt software index */ -+ u32 rx_head_buff_size; /* Rx buffer size */ -+ u8 rss_type; /* rss protocol type */ -+}; -+ -+/* edma_sw_desc stores software descriptor -+ * SW descriptor has 1:1 map with HW descriptor -+ */ -+struct edma_sw_desc { -+ struct sk_buff *skb; -+ dma_addr_t dma; /* dma address */ -+ u16 length; /* Tx/Rx buffer length */ -+ u32 flags; -+}; -+ -+/* per core related information */ -+struct edma_per_cpu_queues_info { -+ struct napi_struct napi; /* napi associated with the core */ -+ u32 tx_mask; /* tx interrupt mask */ -+ u32 rx_mask; /* rx interrupt mask */ -+ u32 tx_status; /* tx interrupt status */ -+ u32 rx_status; /* rx interrupt status */ -+ u32 tx_start; /* tx queue start */ -+ u32 rx_start; /* rx queue start */ -+ struct edma_common_info *edma_cinfo; /* edma common info */ -+}; -+ -+/* edma specific common info */ -+struct edma_common_info { -+ struct edma_tx_desc_ring *tpd_ring[16]; /* 16 Tx queues */ -+ struct edma_rfd_desc_ring *rfd_ring[8]; /* 8 Rx queues */ -+ struct platform_device *pdev; /* device structure */ -+ struct net_device *netdev[EDMA_MAX_PORTID_SUPPORTED]; -+ struct net_device *portid_netdev_lookup_tbl[EDMA_MAX_PORTID_BITMAP_INDEX]; -+ struct ctl_table_header *edma_ctl_table_hdr; -+ int num_gmac; -+ struct edma_ethtool_statistics edma_ethstats; /* ethtool stats */ -+ int num_rx_queues; /* number of rx queue */ -+ u32 num_tx_queues; /* number of tx queue */ -+ u32 tx_irq[16]; /* number of tx irq */ -+ u32 rx_irq[8]; /* number of rx irq */ -+ u32 from_cpu; /* from CPU TPD field */ -+ u32 num_rxq_per_core; /* Rx queues per core */ -+ u32 num_txq_per_core; /* Tx queues per core */ -+ u16 tx_ring_count; /* Tx ring count */ -+ u16 rx_ring_count; /* Rx ring*/ -+ u16 rx_head_buffer_len; /* rx buffer length */ -+ u16 rx_page_buffer_len; /* rx buffer length */ -+ u32 page_mode; /* Jumbo frame supported flag */ -+ u32 fraglist_mode; /* fraglist supported flag */ -+ struct edma_hw hw; /* edma hw specific structure */ -+ struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */ -+ spinlock_t stats_lock; /* protect edma stats area for updation */ -+ struct timer_list edma_stats_timer; -+}; -+ -+/* transimit packet descriptor (tpd) ring */ -+struct edma_tx_desc_ring { -+ struct netdev_queue *nq[EDMA_MAX_NETDEV_PER_QUEUE]; /* Linux queue index */ -+ struct net_device *netdev[EDMA_MAX_NETDEV_PER_QUEUE]; -+ /* Array of netdevs associated with the tpd ring */ -+ void *hw_desc; /* descriptor ring virtual address */ -+ struct edma_sw_desc *sw_desc; /* buffer associated with ring */ -+ int netdev_bmp; /* Bitmap for per-ring netdevs */ -+ u32 size; /* descriptor ring length in bytes */ -+ u16 count; /* number of descriptors in the ring */ -+ dma_addr_t dma; /* descriptor ring physical address */ -+ u16 sw_next_to_fill; /* next Tx descriptor to fill */ -+ u16 sw_next_to_clean; /* next Tx descriptor to clean */ -+}; -+ -+/* receive free descriptor (rfd) ring */ -+struct edma_rfd_desc_ring { -+ void *hw_desc; /* descriptor ring virtual address */ -+ struct edma_sw_desc *sw_desc; /* buffer associated with ring */ -+ u16 size; /* bytes allocated to sw_desc */ -+ u16 count; /* number of descriptors in the ring */ -+ dma_addr_t dma; /* descriptor ring physical address */ -+ u16 sw_next_to_fill; /* next descriptor to fill */ -+ u16 sw_next_to_clean; /* next descriptor to clean */ -+}; -+ -+/* edma_rfs_flter_node - rfs filter node in hash table */ -+struct edma_rfs_filter_node { -+ struct flow_keys keys; -+ u32 flow_id; /* flow_id of filter provided by kernel */ -+ u16 filter_id; /* filter id of filter returned by adaptor */ -+ u16 rq_id; /* desired rq index */ -+ struct hlist_node node; /* edma rfs list node */ -+}; -+ -+/* edma_rfs_flow_tbl - rfs flow table */ -+struct edma_rfs_flow_table { -+ u16 max_num_filter; /* Maximum number of filters edma supports */ -+ u16 hashtoclean; /* hash table index to clean next */ -+ int filter_available; /* Number of free filters available */ -+ struct hlist_head hlist_head[EDMA_RFS_FLOW_ENTRIES]; -+ spinlock_t rfs_ftab_lock; -+ struct timer_list expire_rfs; /* timer function for edma_rps_may_expire_flow */ -+}; -+ -+/* EDMA net device structure */ -+struct edma_adapter { -+ struct net_device *netdev; /* netdevice */ -+ struct platform_device *pdev; /* platform device */ -+ struct edma_common_info *edma_cinfo; /* edma common info */ -+ struct phy_device *phydev; /* Phy device */ -+ struct edma_rfs_flow_table rfs; /* edma rfs flow table */ -+ struct net_device_stats stats; /* netdev statistics */ -+ set_rfs_filter_callback_t set_rfs_rule; -+ u32 flags;/* status flags */ -+ unsigned long state_flags; /* GMAC up/down flags */ -+ u32 forced_speed; /* link force speed */ -+ u32 forced_duplex; /* link force duplex */ -+ u32 link_state; /* phy link state */ -+ u32 phy_mdio_addr; /* PHY device address on MII interface */ -+ u32 poll_required; /* check if link polling is required */ -+ u32 tx_start_offset[CONFIG_NR_CPUS]; /* tx queue start */ -+ u32 default_vlan_tag; /* vlan tag */ -+ u32 dp_bitmap; -+ uint8_t phy_id[MII_BUS_ID_SIZE + 3]; -+}; -+ -+int edma_alloc_queues_tx(struct edma_common_info *edma_cinfo); -+int edma_alloc_queues_rx(struct edma_common_info *edma_cinfo); -+int edma_open(struct net_device *netdev); -+int edma_close(struct net_device *netdev); -+void edma_free_tx_resources(struct edma_common_info *edma_c_info); -+void edma_free_rx_resources(struct edma_common_info *edma_c_info); -+int edma_alloc_tx_rings(struct edma_common_info *edma_cinfo); -+int edma_alloc_rx_rings(struct edma_common_info *edma_cinfo); -+void edma_free_tx_rings(struct edma_common_info *edma_cinfo); -+void edma_free_rx_rings(struct edma_common_info *edma_cinfo); -+void edma_free_queues(struct edma_common_info *edma_cinfo); -+void edma_irq_disable(struct edma_common_info *edma_cinfo); -+int edma_reset(struct edma_common_info *edma_cinfo); -+int edma_poll(struct napi_struct *napi, int budget); -+netdev_tx_t edma_xmit(struct sk_buff *skb, -+ struct net_device *netdev); -+int edma_configure(struct edma_common_info *edma_cinfo); -+void edma_irq_enable(struct edma_common_info *edma_cinfo); -+void edma_enable_tx_ctrl(struct edma_hw *hw); -+void edma_enable_rx_ctrl(struct edma_hw *hw); -+void edma_stop_rx_tx(struct edma_hw *hw); -+void edma_free_irqs(struct edma_adapter *adapter); -+irqreturn_t edma_interrupt(int irq, void *dev); -+void edma_write_reg(u16 reg_addr, u32 reg_value); -+void edma_read_reg(u16 reg_addr, volatile u32 *reg_value); -+struct net_device_stats *edma_get_stats(struct net_device *netdev); -+int edma_set_mac_addr(struct net_device *netdev, void *p); -+int edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, -+ u16 rxq, u32 flow_id); -+int edma_register_rfs_filter(struct net_device *netdev, -+ set_rfs_filter_callback_t set_filter); -+void edma_flow_may_expire(struct timer_list *t); -+void edma_set_ethtool_ops(struct net_device *netdev); -+void edma_set_stp_rstp(bool tag); -+void edma_assign_ath_hdr_type(int tag); -+int edma_get_default_vlan_tag(struct net_device *netdev); -+void edma_adjust_link(struct net_device *netdev); -+int edma_fill_netdev(struct edma_common_info *edma_cinfo, int qid, int num, int txq_id); -+void edma_read_append_stats(struct edma_common_info *edma_cinfo); -+void edma_change_tx_coalesce(int usecs); -+void edma_change_rx_coalesce(int usecs); -+void edma_get_tx_rx_coalesce(u32 *reg_val); -+void edma_clear_irq_status(void); -+#endif /* _EDMA_H_ */ ---- /dev/null -+++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c -@@ -0,0 +1,1216 @@ -+/* -+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for -+ * any purpose with or without fee is hereby granted, provided that the -+ * above copyright notice and this permission notice appear in all copies. -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include "edma.h" -+#include "ess_edma.h" -+ -+/* Weight round robin and virtual QID mask */ -+#define EDMA_WRR_VID_SCTL_MASK 0xffff -+ -+/* Weight round robin and virtual QID shift */ -+#define EDMA_WRR_VID_SCTL_SHIFT 16 -+ -+char edma_axi_driver_name[] = "ess_edma"; -+static const u32 default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | -+ NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP; -+ -+static u32 edma_hw_addr; -+ -+char edma_tx_irq[16][64]; -+char edma_rx_irq[8][64]; -+struct net_device *edma_netdev[EDMA_MAX_PORTID_SUPPORTED]; -+static u16 tx_start[4] = {EDMA_TXQ_START_CORE0, EDMA_TXQ_START_CORE1, -+ EDMA_TXQ_START_CORE2, EDMA_TXQ_START_CORE3}; -+static u32 tx_mask[4] = {EDMA_TXQ_IRQ_MASK_CORE0, EDMA_TXQ_IRQ_MASK_CORE1, -+ EDMA_TXQ_IRQ_MASK_CORE2, EDMA_TXQ_IRQ_MASK_CORE3}; -+ -+static u32 edma_default_ltag __read_mostly = EDMA_LAN_DEFAULT_VLAN; -+static u32 edma_default_wtag __read_mostly = EDMA_WAN_DEFAULT_VLAN; -+static u32 edma_default_group1_vtag __read_mostly = EDMA_DEFAULT_GROUP1_VLAN; -+static u32 edma_default_group2_vtag __read_mostly = EDMA_DEFAULT_GROUP2_VLAN; -+static u32 edma_default_group3_vtag __read_mostly = EDMA_DEFAULT_GROUP3_VLAN; -+static u32 edma_default_group4_vtag __read_mostly = EDMA_DEFAULT_GROUP4_VLAN; -+static u32 edma_default_group5_vtag __read_mostly = EDMA_DEFAULT_GROUP5_VLAN; -+static u32 edma_rss_idt_val = EDMA_RSS_IDT_VALUE; -+static u32 edma_rss_idt_idx; -+ -+static int edma_weight_assigned_to_q __read_mostly; -+static int edma_queue_to_virtual_q __read_mostly; -+static bool edma_enable_rstp __read_mostly; -+static int edma_athr_hdr_eth_type __read_mostly; -+ -+static int page_mode; -+module_param(page_mode, int, 0); -+MODULE_PARM_DESC(page_mode, "enable page mode"); -+ -+static int overwrite_mode; -+module_param(overwrite_mode, int, 0); -+MODULE_PARM_DESC(overwrite_mode, "overwrite default page_mode setting"); -+ -+static int jumbo_mru = EDMA_RX_HEAD_BUFF_SIZE; -+module_param(jumbo_mru, int, 0); -+MODULE_PARM_DESC(jumbo_mru, "enable fraglist support"); -+ -+static int num_rxq = 4; -+module_param(num_rxq, int, 0); -+MODULE_PARM_DESC(num_rxq, "change the number of rx queues"); -+ -+void edma_write_reg(u16 reg_addr, u32 reg_value) -+{ -+ writel(reg_value, ((void __iomem *)(edma_hw_addr + reg_addr))); -+} -+ -+void edma_read_reg(u16 reg_addr, volatile u32 *reg_value) -+{ -+ *reg_value = readl((void __iomem *)(edma_hw_addr + reg_addr)); -+} -+ -+/* edma_change_tx_coalesce() -+ * change tx interrupt moderation timer -+ */ -+void edma_change_tx_coalesce(int usecs) -+{ -+ u32 reg_value; -+ -+ /* Here, we right shift the value from the user by 1, this is -+ * done because IMT resolution timer is 2usecs. 1 count -+ * of this register corresponds to 2 usecs. -+ */ -+ edma_read_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, ®_value); -+ reg_value = ((reg_value & 0xffff) | ((usecs >> 1) << 16)); -+ edma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, reg_value); -+} -+ -+/* edma_change_rx_coalesce() -+ * change rx interrupt moderation timer -+ */ -+void edma_change_rx_coalesce(int usecs) -+{ -+ u32 reg_value; -+ -+ /* Here, we right shift the value from the user by 1, this is -+ * done because IMT resolution timer is 2usecs. 1 count -+ * of this register corresponds to 2 usecs. -+ */ -+ edma_read_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, ®_value); -+ reg_value = ((reg_value & 0xffff0000) | (usecs >> 1)); -+ edma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, reg_value); -+} -+ -+/* edma_get_tx_rx_coalesce() -+ * Get tx/rx interrupt moderation value -+ */ -+void edma_get_tx_rx_coalesce(u32 *reg_val) -+{ -+ edma_read_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, reg_val); -+} -+ -+void edma_read_append_stats(struct edma_common_info *edma_cinfo) -+{ -+ uint32_t *p; -+ int i; -+ u32 stat; -+ -+ spin_lock_bh(&edma_cinfo->stats_lock); -+ p = (uint32_t *)&(edma_cinfo->edma_ethstats); -+ -+ for (i = 0; i < EDMA_MAX_TRANSMIT_QUEUE; i++) { -+ edma_read_reg(EDMA_REG_TX_STAT_PKT_Q(i), &stat); -+ *p += stat; -+ p++; -+ } -+ -+ for (i = 0; i < EDMA_MAX_TRANSMIT_QUEUE; i++) { -+ edma_read_reg(EDMA_REG_TX_STAT_BYTE_Q(i), &stat); -+ *p += stat; -+ p++; -+ } -+ -+ for (i = 0; i < EDMA_MAX_RECEIVE_QUEUE; i++) { -+ edma_read_reg(EDMA_REG_RX_STAT_PKT_Q(i), &stat); -+ *p += stat; -+ p++; -+ } -+ -+ for (i = 0; i < EDMA_MAX_RECEIVE_QUEUE; i++) { -+ edma_read_reg(EDMA_REG_RX_STAT_BYTE_Q(i), &stat); -+ *p += stat; -+ p++; -+ } -+ -+ spin_unlock_bh(&edma_cinfo->stats_lock); -+} -+ -+static void edma_statistics_timer(struct timer_list *t) -+{ -+ struct edma_common_info *edma_cinfo = -+ from_timer(edma_cinfo, t, edma_stats_timer); -+ -+ edma_read_append_stats(edma_cinfo); -+ -+ mod_timer(&edma_cinfo->edma_stats_timer, jiffies + 1*HZ); -+} -+ -+static int edma_enable_stp_rstp(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ int ret; -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ if (write) -+ edma_set_stp_rstp(edma_enable_rstp); -+ -+ return ret; -+} -+ -+static int edma_ath_hdr_eth_type(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ int ret; -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ if (write) -+ edma_assign_ath_hdr_type(edma_athr_hdr_eth_type); -+ -+ return ret; -+} -+ -+static int edma_change_default_lan_vlan(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ struct edma_adapter *adapter; -+ int ret; -+ -+ if (!edma_netdev[1]) { -+ pr_err("Netdevice for default_lan does not exist\n"); -+ return -1; -+ } -+ -+ adapter = netdev_priv(edma_netdev[1]); -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ -+ if (write) -+ adapter->default_vlan_tag = edma_default_ltag; -+ -+ return ret; -+} -+ -+static int edma_change_default_wan_vlan(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ struct edma_adapter *adapter; -+ int ret; -+ -+ if (!edma_netdev[0]) { -+ pr_err("Netdevice for default_wan does not exist\n"); -+ return -1; -+ } -+ -+ adapter = netdev_priv(edma_netdev[0]); -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ -+ if (write) -+ adapter->default_vlan_tag = edma_default_wtag; -+ -+ return ret; -+} -+ -+static int edma_change_group1_vtag(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ struct edma_adapter *adapter; -+ struct edma_common_info *edma_cinfo; -+ int ret; -+ -+ if (!edma_netdev[0]) { -+ pr_err("Netdevice for Group 1 does not exist\n"); -+ return -1; -+ } -+ -+ adapter = netdev_priv(edma_netdev[0]); -+ edma_cinfo = adapter->edma_cinfo; -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ -+ if (write) -+ adapter->default_vlan_tag = edma_default_group1_vtag; -+ -+ return ret; -+} -+ -+static int edma_change_group2_vtag(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ struct edma_adapter *adapter; -+ struct edma_common_info *edma_cinfo; -+ int ret; -+ -+ if (!edma_netdev[1]) { -+ pr_err("Netdevice for Group 2 does not exist\n"); -+ return -1; -+ } -+ -+ adapter = netdev_priv(edma_netdev[1]); -+ edma_cinfo = adapter->edma_cinfo; -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ -+ if (write) -+ adapter->default_vlan_tag = edma_default_group2_vtag; -+ -+ return ret; -+} -+ -+static int edma_change_group3_vtag(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ struct edma_adapter *adapter; -+ struct edma_common_info *edma_cinfo; -+ int ret; -+ -+ if (!edma_netdev[2]) { -+ pr_err("Netdevice for Group 3 does not exist\n"); -+ return -1; -+ } -+ -+ adapter = netdev_priv(edma_netdev[2]); -+ edma_cinfo = adapter->edma_cinfo; -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ -+ if (write) -+ adapter->default_vlan_tag = edma_default_group3_vtag; -+ -+ return ret; -+} -+ -+static int edma_change_group4_vtag(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ struct edma_adapter *adapter; -+ struct edma_common_info *edma_cinfo; -+ int ret; -+ -+ if (!edma_netdev[3]) { -+ pr_err("Netdevice for Group 4 does not exist\n"); -+ return -1; -+ } -+ -+ adapter = netdev_priv(edma_netdev[3]); -+ edma_cinfo = adapter->edma_cinfo; -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ -+ if (write) -+ adapter->default_vlan_tag = edma_default_group4_vtag; -+ -+ return ret; -+} -+ -+static int edma_change_group5_vtag(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ struct edma_adapter *adapter; -+ struct edma_common_info *edma_cinfo; -+ int ret; -+ -+ if (!edma_netdev[4]) { -+ pr_err("Netdevice for Group 5 does not exist\n"); -+ return -1; -+ } -+ -+ adapter = netdev_priv(edma_netdev[4]); -+ edma_cinfo = adapter->edma_cinfo; -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ -+ if (write) -+ adapter->default_vlan_tag = edma_default_group5_vtag; -+ -+ return ret; -+} -+ -+static int edma_set_rss_idt_value(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ int ret; -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ if (write && !ret) -+ edma_write_reg(EDMA_REG_RSS_IDT(edma_rss_idt_idx), -+ edma_rss_idt_val); -+ return ret; -+} -+ -+static int edma_set_rss_idt_idx(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ int ret; -+ u32 old_value = edma_rss_idt_idx; -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ if (!write || ret) -+ return ret; -+ -+ if (edma_rss_idt_idx >= EDMA_NUM_IDT) { -+ pr_err("Invalid RSS indirection table index %d\n", -+ edma_rss_idt_idx); -+ edma_rss_idt_idx = old_value; -+ return -EINVAL; -+ } -+ return ret; -+} -+ -+static int edma_weight_assigned_to_queues(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ int ret, queue_id, weight; -+ u32 reg_data, data, reg_addr; -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ if (write) { -+ queue_id = edma_weight_assigned_to_q & EDMA_WRR_VID_SCTL_MASK; -+ if (queue_id < 0 || queue_id > 15) { -+ pr_err("queue_id not within desired range\n"); -+ return -EINVAL; -+ } -+ -+ weight = edma_weight_assigned_to_q >> EDMA_WRR_VID_SCTL_SHIFT; -+ if (weight < 0 || weight > 0xF) { -+ pr_err("queue_id not within desired range\n"); -+ return -EINVAL; -+ } -+ -+ data = weight << EDMA_WRR_SHIFT(queue_id); -+ -+ reg_addr = EDMA_REG_WRR_CTRL_Q0_Q3 + (queue_id & ~0x3); -+ edma_read_reg(reg_addr, ®_data); -+ reg_data &= ~(1 << EDMA_WRR_SHIFT(queue_id)); -+ edma_write_reg(reg_addr, data | reg_data); -+ } -+ -+ return ret; -+} -+ -+static int edma_queue_to_virtual_queue_map(struct ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, -+ loff_t *ppos) -+{ -+ int ret, queue_id, virtual_qid; -+ u32 reg_data, data, reg_addr; -+ -+ ret = proc_dointvec(table, write, buffer, lenp, ppos); -+ if (write) { -+ queue_id = edma_queue_to_virtual_q & EDMA_WRR_VID_SCTL_MASK; -+ if (queue_id < 0 || queue_id > 15) { -+ pr_err("queue_id not within desired range\n"); -+ return -EINVAL; -+ } -+ -+ virtual_qid = edma_queue_to_virtual_q >> -+ EDMA_WRR_VID_SCTL_SHIFT; -+ if (virtual_qid < 0 || virtual_qid > 8) { -+ pr_err("queue_id not within desired range\n"); -+ return -EINVAL; -+ } -+ -+ data = virtual_qid << EDMA_VQ_ID_SHIFT(queue_id); -+ -+ reg_addr = EDMA_REG_VQ_CTRL0 + (queue_id & ~0x3); -+ edma_read_reg(reg_addr, ®_data); -+ reg_data &= ~(1 << EDMA_VQ_ID_SHIFT(queue_id)); -+ edma_write_reg(reg_addr, data | reg_data); -+ } -+ -+ return ret; -+} -+ -+static struct ctl_table edma_table[] = { -+ { -+ .procname = "default_lan_tag", -+ .data = &edma_default_ltag, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_change_default_lan_vlan -+ }, -+ { -+ .procname = "default_wan_tag", -+ .data = &edma_default_wtag, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_change_default_wan_vlan -+ }, -+ { -+ .procname = "weight_assigned_to_queues", -+ .data = &edma_weight_assigned_to_q, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_weight_assigned_to_queues -+ }, -+ { -+ .procname = "queue_to_virtual_queue_map", -+ .data = &edma_queue_to_virtual_q, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_queue_to_virtual_queue_map -+ }, -+ { -+ .procname = "enable_stp_rstp", -+ .data = &edma_enable_rstp, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_enable_stp_rstp -+ }, -+ { -+ .procname = "athr_hdr_eth_type", -+ .data = &edma_athr_hdr_eth_type, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_ath_hdr_eth_type -+ }, -+ { -+ .procname = "default_group1_vlan_tag", -+ .data = &edma_default_group1_vtag, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_change_group1_vtag -+ }, -+ { -+ .procname = "default_group2_vlan_tag", -+ .data = &edma_default_group2_vtag, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_change_group2_vtag -+ }, -+ { -+ .procname = "default_group3_vlan_tag", -+ .data = &edma_default_group3_vtag, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_change_group3_vtag -+ }, -+ { -+ .procname = "default_group4_vlan_tag", -+ .data = &edma_default_group4_vtag, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_change_group4_vtag -+ }, -+ { -+ .procname = "default_group5_vlan_tag", -+ .data = &edma_default_group5_vtag, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_change_group5_vtag -+ }, -+ { -+ .procname = "edma_rss_idt_value", -+ .data = &edma_rss_idt_val, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_set_rss_idt_value -+ }, -+ { -+ .procname = "edma_rss_idt_idx", -+ .data = &edma_rss_idt_idx, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = edma_set_rss_idt_idx -+ }, -+ {} -+}; -+ -+/* edma_axi_netdev_ops -+ * Describe the operations supported by registered netdevices -+ * -+ * static const struct net_device_ops edma_axi_netdev_ops = { -+ * .ndo_open = edma_open, -+ * .ndo_stop = edma_close, -+ * .ndo_start_xmit = edma_xmit_frame, -+ * .ndo_set_mac_address = edma_set_mac_addr, -+ * } -+ */ -+static const struct net_device_ops edma_axi_netdev_ops = { -+ .ndo_open = edma_open, -+ .ndo_stop = edma_close, -+ .ndo_start_xmit = edma_xmit, -+ .ndo_set_mac_address = edma_set_mac_addr, -+#ifdef CONFIG_RFS_ACCEL -+ .ndo_rx_flow_steer = edma_rx_flow_steer, -+ .ndo_register_rfs_filter = edma_register_rfs_filter, -+ .ndo_get_default_vlan_tag = edma_get_default_vlan_tag, -+#endif -+ .ndo_get_stats = edma_get_stats, -+}; -+ -+/* edma_axi_probe() -+ * Initialise an adapter identified by a platform_device structure. -+ * -+ * The OS initialization, configuring of the adapter private structure, -+ * and a hardware reset occur in the probe. -+ */ -+static int edma_axi_probe(struct platform_device *pdev) -+{ -+ struct edma_common_info *edma_cinfo; -+ struct edma_hw *hw; -+ struct edma_adapter *adapter[EDMA_MAX_PORTID_SUPPORTED]; -+ struct resource *res; -+ struct device_node *np = pdev->dev.of_node; -+ struct device_node *pnp; -+ struct device_node *mdio_node = NULL; -+ struct platform_device *mdio_plat = NULL; -+ struct mii_bus *miibus = NULL; -+ struct edma_mdio_data *mdio_data = NULL; -+ int i, j, k, err = 0; -+ int portid_bmp; -+ int idx = 0, idx_mac = 0; -+ -+ if (CONFIG_NR_CPUS != EDMA_CPU_CORES_SUPPORTED) { -+ dev_err(&pdev->dev, "Invalid CPU Cores\n"); -+ return -EINVAL; -+ } -+ -+ if ((num_rxq != 4) && (num_rxq != 8)) { -+ dev_err(&pdev->dev, "Invalid RX queue, edma probe failed\n"); -+ return -EINVAL; -+ } -+ edma_cinfo = kzalloc(sizeof(struct edma_common_info), GFP_KERNEL); -+ if (!edma_cinfo) { -+ err = -ENOMEM; -+ goto err_alloc; -+ } -+ -+ edma_cinfo->pdev = pdev; -+ -+ of_property_read_u32(np, "qcom,num_gmac", &edma_cinfo->num_gmac); -+ if (edma_cinfo->num_gmac > EDMA_MAX_PORTID_SUPPORTED) { -+ pr_err("Invalid DTSI Entry for qcom,num_gmac\n"); -+ err = -EINVAL; -+ goto err_cinfo; -+ } -+ -+ /* Initialize the netdev array before allocation -+ * to avoid double free -+ */ -+ for (i = 0 ; i < edma_cinfo->num_gmac ; i++) -+ edma_netdev[i] = NULL; -+ -+ for (i = 0 ; i < edma_cinfo->num_gmac ; i++) { -+ edma_netdev[i] = alloc_etherdev_mqs(sizeof(struct edma_adapter), -+ EDMA_NETDEV_TX_QUEUE, EDMA_NETDEV_RX_QUEUE); -+ -+ if (!edma_netdev[i]) { -+ dev_err(&pdev->dev, -+ "net device alloc fails for index=%d\n", i); -+ err = -ENODEV; -+ goto err_ioremap; -+ } -+ -+ SET_NETDEV_DEV(edma_netdev[i], &pdev->dev); -+ platform_set_drvdata(pdev, edma_netdev[i]); -+ edma_cinfo->netdev[i] = edma_netdev[i]; -+ } -+ -+ /* Fill ring details */ -+ edma_cinfo->num_tx_queues = EDMA_MAX_TRANSMIT_QUEUE; -+ edma_cinfo->num_txq_per_core = (EDMA_MAX_TRANSMIT_QUEUE / 4); -+ edma_cinfo->tx_ring_count = EDMA_TX_RING_SIZE; -+ -+ /* Update num rx queues based on module parameter */ -+ edma_cinfo->num_rx_queues = num_rxq; -+ edma_cinfo->num_rxq_per_core = ((num_rxq == 4) ? 1 : 2); -+ -+ edma_cinfo->rx_ring_count = EDMA_RX_RING_SIZE; -+ -+ hw = &edma_cinfo->hw; -+ -+ /* Fill HW defaults */ -+ hw->tx_intr_mask = EDMA_TX_IMR_NORMAL_MASK; -+ hw->rx_intr_mask = EDMA_RX_IMR_NORMAL_MASK; -+ -+ of_property_read_u32(np, "qcom,page-mode", &edma_cinfo->page_mode); -+ of_property_read_u32(np, "qcom,rx_head_buf_size", -+ &hw->rx_head_buff_size); -+ -+ if (overwrite_mode) { -+ dev_info(&pdev->dev, "page mode overwritten"); -+ edma_cinfo->page_mode = page_mode; -+ } -+ -+ if (jumbo_mru) -+ edma_cinfo->fraglist_mode = 1; -+ -+ if (edma_cinfo->page_mode) -+ hw->rx_head_buff_size = EDMA_RX_HEAD_BUFF_SIZE_JUMBO; -+ else if (edma_cinfo->fraglist_mode) -+ hw->rx_head_buff_size = jumbo_mru; -+ else if (!hw->rx_head_buff_size) -+ hw->rx_head_buff_size = EDMA_RX_HEAD_BUFF_SIZE; -+ -+ hw->misc_intr_mask = 0; -+ hw->wol_intr_mask = 0; -+ -+ hw->intr_clear_type = EDMA_INTR_CLEAR_TYPE; -+ hw->intr_sw_idx_w = EDMA_INTR_SW_IDX_W_TYPE; -+ -+ /* configure RSS type to the different protocol that can be -+ * supported -+ */ -+ hw->rss_type = EDMA_RSS_TYPE_IPV4TCP | EDMA_RSS_TYPE_IPV6_TCP | -+ EDMA_RSS_TYPE_IPV4_UDP | EDMA_RSS_TYPE_IPV6UDP | -+ EDMA_RSS_TYPE_IPV4 | EDMA_RSS_TYPE_IPV6; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ edma_cinfo->hw.hw_addr = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(edma_cinfo->hw.hw_addr)) { -+ err = PTR_ERR(edma_cinfo->hw.hw_addr); -+ goto err_ioremap; -+ } -+ -+ edma_hw_addr = (u32)edma_cinfo->hw.hw_addr; -+ -+ /* Parse tx queue interrupt number from device tree */ -+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) -+ edma_cinfo->tx_irq[i] = platform_get_irq(pdev, i); -+ -+ /* Parse rx queue interrupt number from device tree -+ * Here we are setting j to point to the point where we -+ * left tx interrupt parsing(i.e 16) and run run the loop -+ * from 0 to 7 to parse rx interrupt number. -+ */ -+ for (i = 0, j = edma_cinfo->num_tx_queues, k = 0; -+ i < edma_cinfo->num_rx_queues; i++) { -+ edma_cinfo->rx_irq[k] = platform_get_irq(pdev, j); -+ k += ((num_rxq == 4) ? 2 : 1); -+ j += ((num_rxq == 4) ? 2 : 1); -+ } -+ -+ edma_cinfo->rx_head_buffer_len = edma_cinfo->hw.rx_head_buff_size; -+ edma_cinfo->rx_page_buffer_len = PAGE_SIZE; -+ -+ err = edma_alloc_queues_tx(edma_cinfo); -+ if (err) { -+ dev_err(&pdev->dev, "Allocation of TX queue failed\n"); -+ goto err_tx_qinit; -+ } -+ -+ err = edma_alloc_queues_rx(edma_cinfo); -+ if (err) { -+ dev_err(&pdev->dev, "Allocation of RX queue failed\n"); -+ goto err_rx_qinit; -+ } -+ -+ err = edma_alloc_tx_rings(edma_cinfo); -+ if (err) { -+ dev_err(&pdev->dev, "Allocation of TX resources failed\n"); -+ goto err_tx_rinit; -+ } -+ -+ err = edma_alloc_rx_rings(edma_cinfo); -+ if (err) { -+ dev_err(&pdev->dev, "Allocation of RX resources failed\n"); -+ goto err_rx_rinit; -+ } -+ -+ /* Initialize netdev and netdev bitmap for transmit descriptor rings */ -+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) { -+ struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[i]; -+ int j; -+ -+ etdr->netdev_bmp = 0; -+ for (j = 0; j < EDMA_MAX_NETDEV_PER_QUEUE; j++) { -+ etdr->netdev[j] = NULL; -+ etdr->nq[j] = NULL; -+ } -+ } -+ -+ if (of_property_read_bool(np, "qcom,mdio_supported")) { -+ mdio_node = of_find_compatible_node(NULL, NULL, -+ "qcom,ipq4019-mdio"); -+ if (!mdio_node) { -+ dev_err(&pdev->dev, "cannot find mdio node by phandle"); -+ err = -EIO; -+ goto err_mdiobus_init_fail; -+ } -+ -+ mdio_plat = of_find_device_by_node(mdio_node); -+ if (!mdio_plat) { -+ dev_err(&pdev->dev, -+ "cannot find platform device from mdio node"); -+ of_node_put(mdio_node); -+ err = -EIO; -+ goto err_mdiobus_init_fail; -+ } -+ -+ mdio_data = dev_get_drvdata(&mdio_plat->dev); -+ if (!mdio_data) { -+ dev_err(&pdev->dev, -+ "cannot get mii bus reference from device data"); -+ of_node_put(mdio_node); -+ err = -EIO; -+ goto err_mdiobus_init_fail; -+ } -+ -+ miibus = mdio_data->mii_bus; -+ } -+ -+ for_each_available_child_of_node(np, pnp) { -+ const char *mac_addr; -+ -+ /* this check is needed if parent and daughter dts have -+ * different number of gmac nodes -+ */ -+ if (idx_mac == edma_cinfo->num_gmac) { -+ of_node_put(np); -+ break; -+ } -+ -+ mac_addr = of_get_mac_address(pnp); -+ if (mac_addr) -+ memcpy(edma_netdev[idx_mac]->dev_addr, mac_addr, ETH_ALEN); -+ -+ idx_mac++; -+ } -+ -+ /* Populate the adapter structure register the netdevice */ -+ for (i = 0; i < edma_cinfo->num_gmac; i++) { -+ int k, m; -+ -+ adapter[i] = netdev_priv(edma_netdev[i]); -+ adapter[i]->netdev = edma_netdev[i]; -+ adapter[i]->pdev = pdev; -+ for (j = 0; j < CONFIG_NR_CPUS; j++) { -+ m = i % 2; -+ adapter[i]->tx_start_offset[j] = -+ ((j << EDMA_TX_CPU_START_SHIFT) + (m << 1)); -+ /* Share the queues with available net-devices. -+ * For instance , with 5 net-devices -+ * eth0/eth2/eth4 will share q0,q1,q4,q5,q8,q9,q12,q13 -+ * and eth1/eth3 will get the remaining. -+ */ -+ for (k = adapter[i]->tx_start_offset[j]; k < -+ (adapter[i]->tx_start_offset[j] + 2); k++) { -+ if (edma_fill_netdev(edma_cinfo, k, i, j)) { -+ pr_err("Netdev overflow Error\n"); -+ goto err_register; -+ } -+ } -+ } -+ -+ adapter[i]->edma_cinfo = edma_cinfo; -+ edma_netdev[i]->netdev_ops = &edma_axi_netdev_ops; -+ edma_netdev[i]->max_mtu = 9000; -+ edma_netdev[i]->features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM -+ | NETIF_F_HW_VLAN_CTAG_TX -+ | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_SG | -+ NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GRO; -+ edma_netdev[i]->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM | -+ NETIF_F_HW_VLAN_CTAG_RX -+ | NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | -+ NETIF_F_GRO; -+ edma_netdev[i]->vlan_features = NETIF_F_HW_CSUM | NETIF_F_SG | -+ NETIF_F_TSO | NETIF_F_TSO6 | -+ NETIF_F_GRO; -+ edma_netdev[i]->wanted_features = NETIF_F_HW_CSUM | NETIF_F_SG | -+ NETIF_F_TSO | NETIF_F_TSO6 | -+ NETIF_F_GRO; -+ -+#ifdef CONFIG_RFS_ACCEL -+ edma_netdev[i]->features |= NETIF_F_RXHASH | NETIF_F_NTUPLE; -+ edma_netdev[i]->hw_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE; -+ edma_netdev[i]->vlan_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE; -+ edma_netdev[i]->wanted_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE; -+#endif -+ edma_set_ethtool_ops(edma_netdev[i]); -+ -+ /* This just fill in some default MAC address -+ */ -+ if (!is_valid_ether_addr(edma_netdev[i]->dev_addr)) { -+ random_ether_addr(edma_netdev[i]->dev_addr); -+ pr_info("EDMA using MAC@ - using"); -+ pr_info("%02x:%02x:%02x:%02x:%02x:%02x\n", -+ *(edma_netdev[i]->dev_addr), -+ *(edma_netdev[i]->dev_addr + 1), -+ *(edma_netdev[i]->dev_addr + 2), -+ *(edma_netdev[i]->dev_addr + 3), -+ *(edma_netdev[i]->dev_addr + 4), -+ *(edma_netdev[i]->dev_addr + 5)); -+ } -+ -+ err = register_netdev(edma_netdev[i]); -+ if (err) -+ goto err_register; -+ -+ /* carrier off reporting is important to -+ * ethtool even BEFORE open -+ */ -+ netif_carrier_off(edma_netdev[i]); -+ -+ /* Allocate reverse irq cpu mapping structure for -+ * receive queues -+ */ -+#ifdef CONFIG_RFS_ACCEL -+ edma_netdev[i]->rx_cpu_rmap = -+ alloc_irq_cpu_rmap(EDMA_NETDEV_RX_QUEUE); -+ if (!edma_netdev[i]->rx_cpu_rmap) { -+ err = -ENOMEM; -+ goto err_rmap_alloc_fail; -+ } -+#endif -+ } -+ -+ for (i = 0; i < EDMA_MAX_PORTID_BITMAP_INDEX; i++) -+ edma_cinfo->portid_netdev_lookup_tbl[i] = NULL; -+ -+ for_each_available_child_of_node(np, pnp) { -+ const uint32_t *vlan_tag = NULL; -+ int len; -+ -+ /* this check is needed if parent and daughter dts have -+ * different number of gmac nodes -+ */ -+ if (idx == edma_cinfo->num_gmac) -+ break; -+ -+ /* Populate port-id to netdev lookup table */ -+ vlan_tag = of_get_property(pnp, "vlan_tag", &len); -+ if (!vlan_tag) { -+ pr_err("Vlan tag parsing Failed.\n"); -+ goto err_rmap_alloc_fail; -+ } -+ -+ adapter[idx]->default_vlan_tag = of_read_number(vlan_tag, 1); -+ vlan_tag++; -+ portid_bmp = of_read_number(vlan_tag, 1); -+ adapter[idx]->dp_bitmap = portid_bmp; -+ -+ portid_bmp = portid_bmp >> 1; /* We ignore CPU Port bit 0 */ -+ while (portid_bmp) { -+ int port_bit = ffs(portid_bmp); -+ -+ if (port_bit > EDMA_MAX_PORTID_SUPPORTED) -+ goto err_rmap_alloc_fail; -+ edma_cinfo->portid_netdev_lookup_tbl[port_bit] = -+ edma_netdev[idx]; -+ portid_bmp &= ~(1 << (port_bit - 1)); -+ } -+ -+ if (!of_property_read_u32(pnp, "qcom,poll_required", -+ &adapter[idx]->poll_required)) { -+ if (adapter[idx]->poll_required) { -+ of_property_read_u32(pnp, "qcom,phy_mdio_addr", -+ &adapter[idx]->phy_mdio_addr); -+ of_property_read_u32(pnp, "qcom,forced_speed", -+ &adapter[idx]->forced_speed); -+ of_property_read_u32(pnp, "qcom,forced_duplex", -+ &adapter[idx]->forced_duplex); -+ -+ /* create a phyid using MDIO bus id -+ * and MDIO bus address -+ */ -+ snprintf(adapter[idx]->phy_id, -+ MII_BUS_ID_SIZE + 3, PHY_ID_FMT, -+ miibus->id, -+ adapter[idx]->phy_mdio_addr); -+ } -+ } else { -+ adapter[idx]->poll_required = 0; -+ adapter[idx]->forced_speed = SPEED_1000; -+ adapter[idx]->forced_duplex = DUPLEX_FULL; -+ } -+ -+ idx++; -+ } -+ -+ edma_cinfo->edma_ctl_table_hdr = register_net_sysctl(&init_net, -+ "net/edma", -+ edma_table); -+ if (!edma_cinfo->edma_ctl_table_hdr) { -+ dev_err(&pdev->dev, "edma sysctl table hdr not registered\n"); -+ goto err_unregister_sysctl_tbl; -+ } -+ -+ /* Disable all 16 Tx and 8 rx irqs */ -+ edma_irq_disable(edma_cinfo); -+ -+ err = edma_reset(edma_cinfo); -+ if (err) { -+ err = -EIO; -+ goto err_reset; -+ } -+ -+ /* populate per_core_info, do a napi_Add, request 16 TX irqs, -+ * 8 RX irqs, do a napi enable -+ */ -+ for (i = 0; i < CONFIG_NR_CPUS; i++) { -+ u8 rx_start; -+ -+ edma_cinfo->edma_percpu_info[i].napi.state = 0; -+ -+ netif_napi_add(edma_netdev[0], -+ &edma_cinfo->edma_percpu_info[i].napi, -+ edma_poll, 64); -+ napi_enable(&edma_cinfo->edma_percpu_info[i].napi); -+ edma_cinfo->edma_percpu_info[i].tx_mask = tx_mask[i]; -+ edma_cinfo->edma_percpu_info[i].rx_mask = EDMA_RX_PER_CPU_MASK -+ << (i << EDMA_RX_PER_CPU_MASK_SHIFT); -+ edma_cinfo->edma_percpu_info[i].tx_start = tx_start[i]; -+ edma_cinfo->edma_percpu_info[i].rx_start = -+ i << EDMA_RX_CPU_START_SHIFT; -+ rx_start = i << EDMA_RX_CPU_START_SHIFT; -+ edma_cinfo->edma_percpu_info[i].tx_status = 0; -+ edma_cinfo->edma_percpu_info[i].rx_status = 0; -+ edma_cinfo->edma_percpu_info[i].edma_cinfo = edma_cinfo; -+ -+ /* Request irq per core */ -+ for (j = edma_cinfo->edma_percpu_info[i].tx_start; -+ j < tx_start[i] + 4; j++) { -+ sprintf(&edma_tx_irq[j][0], "edma_eth_tx%d", j); -+ err = request_irq(edma_cinfo->tx_irq[j], -+ edma_interrupt, -+ 0, -+ &edma_tx_irq[j][0], -+ &edma_cinfo->edma_percpu_info[i]); -+ if (err) -+ goto err_reset; -+ } -+ -+ for (j = edma_cinfo->edma_percpu_info[i].rx_start; -+ j < (rx_start + -+ ((edma_cinfo->num_rx_queues == 4) ? 1 : 2)); -+ j++) { -+ sprintf(&edma_rx_irq[j][0], "edma_eth_rx%d", j); -+ err = request_irq(edma_cinfo->rx_irq[j], -+ edma_interrupt, -+ 0, -+ &edma_rx_irq[j][0], -+ &edma_cinfo->edma_percpu_info[i]); -+ if (err) -+ goto err_reset; -+ } -+ -+#ifdef CONFIG_RFS_ACCEL -+ for (j = edma_cinfo->edma_percpu_info[i].rx_start; -+ j < rx_start + 2; j += 2) { -+ err = irq_cpu_rmap_add(edma_netdev[0]->rx_cpu_rmap, -+ edma_cinfo->rx_irq[j]); -+ if (err) -+ goto err_rmap_add_fail; -+ } -+#endif -+ } -+ -+ /* Used to clear interrupt status, allocate rx buffer, -+ * configure edma descriptors registers -+ */ -+ err = edma_configure(edma_cinfo); -+ if (err) { -+ err = -EIO; -+ goto err_configure; -+ } -+ -+ /* Configure RSS indirection table. -+ * 128 hash will be configured in the following -+ * pattern: hash{0,1,2,3} = {Q0,Q2,Q4,Q6} respectively -+ * and so on -+ */ -+ for (i = 0; i < EDMA_NUM_IDT; i++) -+ edma_write_reg(EDMA_REG_RSS_IDT(i), EDMA_RSS_IDT_VALUE); -+ -+ /* Configure load balance mapping table. -+ * 4 table entry will be configured according to the -+ * following pattern: load_balance{0,1,2,3} = {Q0,Q1,Q3,Q4} -+ * respectively. -+ */ -+ edma_write_reg(EDMA_REG_LB_RING, EDMA_LB_REG_VALUE); -+ -+ /* Configure Virtual queue for Tx rings -+ * User can also change this value runtime through -+ * a sysctl -+ */ -+ edma_write_reg(EDMA_REG_VQ_CTRL0, EDMA_VQ_REG_VALUE); -+ edma_write_reg(EDMA_REG_VQ_CTRL1, EDMA_VQ_REG_VALUE); -+ -+ /* Configure Max AXI Burst write size to 128 bytes*/ -+ edma_write_reg(EDMA_REG_AXIW_CTRL_MAXWRSIZE, -+ EDMA_AXIW_MAXWRSIZE_VALUE); -+ -+ /* Enable All 16 tx and 8 rx irq mask */ -+ edma_irq_enable(edma_cinfo); -+ edma_enable_tx_ctrl(&edma_cinfo->hw); -+ edma_enable_rx_ctrl(&edma_cinfo->hw); -+ -+ for (i = 0; i < edma_cinfo->num_gmac; i++) { -+ if (adapter[i]->poll_required) { -+ adapter[i]->phydev = -+ phy_connect(edma_netdev[i], -+ (const char *)adapter[i]->phy_id, -+ &edma_adjust_link, -+ PHY_INTERFACE_MODE_SGMII); -+ if (IS_ERR(adapter[i]->phydev)) { -+ dev_dbg(&pdev->dev, "PHY attach FAIL"); -+ err = -EIO; -+ goto edma_phy_attach_fail; -+ } else { -+ adapter[i]->phydev->advertising |= -+ ADVERTISED_Pause | -+ ADVERTISED_Asym_Pause; -+ adapter[i]->phydev->supported |= -+ SUPPORTED_Pause | -+ SUPPORTED_Asym_Pause; -+ } -+ } else { -+ adapter[i]->phydev = NULL; -+ } -+ } -+ -+ spin_lock_init(&edma_cinfo->stats_lock); -+ -+ timer_setup(&edma_cinfo->edma_stats_timer, edma_statistics_timer, 0); -+ mod_timer(&edma_cinfo->edma_stats_timer, jiffies + 1*HZ); -+ -+ return 0; -+ -+edma_phy_attach_fail: -+ miibus = NULL; -+err_configure: -+#ifdef CONFIG_RFS_ACCEL -+ for (i = 0; i < edma_cinfo->num_gmac; i++) { -+ free_irq_cpu_rmap(adapter[i]->netdev->rx_cpu_rmap); -+ adapter[i]->netdev->rx_cpu_rmap = NULL; -+ } -+#endif -+err_rmap_add_fail: -+ edma_free_irqs(adapter[0]); -+ for (i = 0; i < CONFIG_NR_CPUS; i++) -+ napi_disable(&edma_cinfo->edma_percpu_info[i].napi); -+err_reset: -+err_unregister_sysctl_tbl: -+err_rmap_alloc_fail: -+ for (i = 0; i < edma_cinfo->num_gmac; i++) -+ unregister_netdev(edma_netdev[i]); -+err_register: -+err_mdiobus_init_fail: -+ edma_free_rx_rings(edma_cinfo); -+err_rx_rinit: -+ edma_free_tx_rings(edma_cinfo); -+err_tx_rinit: -+ edma_free_queues(edma_cinfo); -+err_rx_qinit: -+err_tx_qinit: -+ iounmap(edma_cinfo->hw.hw_addr); -+err_ioremap: -+ for (i = 0; i < edma_cinfo->num_gmac; i++) { -+ if (edma_netdev[i]) -+ free_netdev(edma_netdev[i]); -+ } -+err_cinfo: -+ kfree(edma_cinfo); -+err_alloc: -+ return err; -+} -+ -+/* edma_axi_remove() -+ * Device Removal Routine -+ * -+ * edma_axi_remove is called by the platform subsystem to alert the driver -+ * that it should release a platform device. -+ */ -+static int edma_axi_remove(struct platform_device *pdev) -+{ -+ struct edma_adapter *adapter = netdev_priv(edma_netdev[0]); -+ struct edma_common_info *edma_cinfo = adapter->edma_cinfo; -+ struct edma_hw *hw = &edma_cinfo->hw; -+ int i; -+ -+ for (i = 0; i < edma_cinfo->num_gmac; i++) -+ unregister_netdev(edma_netdev[i]); -+ -+ edma_stop_rx_tx(hw); -+ for (i = 0; i < CONFIG_NR_CPUS; i++) -+ napi_disable(&edma_cinfo->edma_percpu_info[i].napi); -+ -+ edma_irq_disable(edma_cinfo); -+ edma_write_reg(EDMA_REG_RX_ISR, 0xff); -+ edma_write_reg(EDMA_REG_TX_ISR, 0xffff); -+#ifdef CONFIG_RFS_ACCEL -+ for (i = 0; i < edma_cinfo->num_gmac; i++) { -+ free_irq_cpu_rmap(edma_netdev[i]->rx_cpu_rmap); -+ edma_netdev[i]->rx_cpu_rmap = NULL; -+ } -+#endif -+ -+ for (i = 0; i < edma_cinfo->num_gmac; i++) { -+ struct edma_adapter *adapter = netdev_priv(edma_netdev[i]); -+ -+ if (adapter->phydev) -+ phy_disconnect(adapter->phydev); -+ } -+ -+ del_timer_sync(&edma_cinfo->edma_stats_timer); -+ edma_free_irqs(adapter); -+ unregister_net_sysctl_table(edma_cinfo->edma_ctl_table_hdr); -+ edma_free_tx_resources(edma_cinfo); -+ edma_free_rx_resources(edma_cinfo); -+ edma_free_tx_rings(edma_cinfo); -+ edma_free_rx_rings(edma_cinfo); -+ edma_free_queues(edma_cinfo); -+ for (i = 0; i < edma_cinfo->num_gmac; i++) -+ free_netdev(edma_netdev[i]); -+ -+ kfree(edma_cinfo); -+ -+ return 0; -+} -+ -+static const struct of_device_id edma_of_mtable[] = { -+ {.compatible = "qcom,ess-edma" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, edma_of_mtable); -+ -+static struct platform_driver edma_axi_driver = { -+ .driver = { -+ .name = edma_axi_driver_name, -+ .of_match_table = edma_of_mtable, -+ }, -+ .probe = edma_axi_probe, -+ .remove = edma_axi_remove, -+}; -+ -+module_platform_driver(edma_axi_driver); -+ -+MODULE_AUTHOR("Qualcomm Atheros Inc"); -+MODULE_DESCRIPTION("QCA ESS EDMA driver"); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c -@@ -0,0 +1,374 @@ -+/* -+ * Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for -+ * any purpose with or without fee is hereby granted, provided that the -+ * above copyright notice and this permission notice appear in all copies. -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+#include -+#include -+#include -+#include "edma.h" -+ -+struct edma_ethtool_stats { -+ uint8_t stat_string[ETH_GSTRING_LEN]; -+ uint32_t stat_offset; -+}; -+ -+#define EDMA_STAT(m) offsetof(struct edma_ethtool_statistics, m) -+#define DRVINFO_LEN 32 -+ -+/* Array of strings describing statistics -+ */ -+static const struct edma_ethtool_stats edma_gstrings_stats[] = { -+ {"tx_q0_pkt", EDMA_STAT(tx_q0_pkt)}, -+ {"tx_q1_pkt", EDMA_STAT(tx_q1_pkt)}, -+ {"tx_q2_pkt", EDMA_STAT(tx_q2_pkt)}, -+ {"tx_q3_pkt", EDMA_STAT(tx_q3_pkt)}, -+ {"tx_q4_pkt", EDMA_STAT(tx_q4_pkt)}, -+ {"tx_q5_pkt", EDMA_STAT(tx_q5_pkt)}, -+ {"tx_q6_pkt", EDMA_STAT(tx_q6_pkt)}, -+ {"tx_q7_pkt", EDMA_STAT(tx_q7_pkt)}, -+ {"tx_q8_pkt", EDMA_STAT(tx_q8_pkt)}, -+ {"tx_q9_pkt", EDMA_STAT(tx_q9_pkt)}, -+ {"tx_q10_pkt", EDMA_STAT(tx_q10_pkt)}, -+ {"tx_q11_pkt", EDMA_STAT(tx_q11_pkt)}, -+ {"tx_q12_pkt", EDMA_STAT(tx_q12_pkt)}, -+ {"tx_q13_pkt", EDMA_STAT(tx_q13_pkt)}, -+ {"tx_q14_pkt", EDMA_STAT(tx_q14_pkt)}, -+ {"tx_q15_pkt", EDMA_STAT(tx_q15_pkt)}, -+ {"tx_q0_byte", EDMA_STAT(tx_q0_byte)}, -+ {"tx_q1_byte", EDMA_STAT(tx_q1_byte)}, -+ {"tx_q2_byte", EDMA_STAT(tx_q2_byte)}, -+ {"tx_q3_byte", EDMA_STAT(tx_q3_byte)}, -+ {"tx_q4_byte", EDMA_STAT(tx_q4_byte)}, -+ {"tx_q5_byte", EDMA_STAT(tx_q5_byte)}, -+ {"tx_q6_byte", EDMA_STAT(tx_q6_byte)}, -+ {"tx_q7_byte", EDMA_STAT(tx_q7_byte)}, -+ {"tx_q8_byte", EDMA_STAT(tx_q8_byte)}, -+ {"tx_q9_byte", EDMA_STAT(tx_q9_byte)}, -+ {"tx_q10_byte", EDMA_STAT(tx_q10_byte)}, -+ {"tx_q11_byte", EDMA_STAT(tx_q11_byte)}, -+ {"tx_q12_byte", EDMA_STAT(tx_q12_byte)}, -+ {"tx_q13_byte", EDMA_STAT(tx_q13_byte)}, -+ {"tx_q14_byte", EDMA_STAT(tx_q14_byte)}, -+ {"tx_q15_byte", EDMA_STAT(tx_q15_byte)}, -+ {"rx_q0_pkt", EDMA_STAT(rx_q0_pkt)}, -+ {"rx_q1_pkt", EDMA_STAT(rx_q1_pkt)}, -+ {"rx_q2_pkt", EDMA_STAT(rx_q2_pkt)}, -+ {"rx_q3_pkt", EDMA_STAT(rx_q3_pkt)}, -+ {"rx_q4_pkt", EDMA_STAT(rx_q4_pkt)}, -+ {"rx_q5_pkt", EDMA_STAT(rx_q5_pkt)}, -+ {"rx_q6_pkt", EDMA_STAT(rx_q6_pkt)}, -+ {"rx_q7_pkt", EDMA_STAT(rx_q7_pkt)}, -+ {"rx_q0_byte", EDMA_STAT(rx_q0_byte)}, -+ {"rx_q1_byte", EDMA_STAT(rx_q1_byte)}, -+ {"rx_q2_byte", EDMA_STAT(rx_q2_byte)}, -+ {"rx_q3_byte", EDMA_STAT(rx_q3_byte)}, -+ {"rx_q4_byte", EDMA_STAT(rx_q4_byte)}, -+ {"rx_q5_byte", EDMA_STAT(rx_q5_byte)}, -+ {"rx_q6_byte", EDMA_STAT(rx_q6_byte)}, -+ {"rx_q7_byte", EDMA_STAT(rx_q7_byte)}, -+ {"tx_desc_error", EDMA_STAT(tx_desc_error)}, -+}; -+ -+#define EDMA_STATS_LEN ARRAY_SIZE(edma_gstrings_stats) -+ -+/* edma_get_strset_count() -+ * Get strset count -+ */ -+static int edma_get_strset_count(struct net_device *netdev, -+ int sset) -+{ -+ switch (sset) { -+ case ETH_SS_STATS: -+ return EDMA_STATS_LEN; -+ default: -+ netdev_dbg(netdev, "%s: Invalid string set", __func__); -+ return -EOPNOTSUPP; -+ } -+} -+ -+ -+/* edma_get_strings() -+ * get stats string -+ */ -+static void edma_get_strings(struct net_device *netdev, uint32_t stringset, -+ uint8_t *data) -+{ -+ uint8_t *p = data; -+ uint32_t i; -+ -+ switch (stringset) { -+ case ETH_SS_STATS: -+ for (i = 0; i < EDMA_STATS_LEN; i++) { -+ memcpy(p, edma_gstrings_stats[i].stat_string, -+ min((size_t)ETH_GSTRING_LEN, -+ strlen(edma_gstrings_stats[i].stat_string) -+ + 1)); -+ p += ETH_GSTRING_LEN; -+ } -+ break; -+ } -+} -+ -+/* edma_get_ethtool_stats() -+ * Get ethtool statistics -+ */ -+static void edma_get_ethtool_stats(struct net_device *netdev, -+ struct ethtool_stats *stats, uint64_t *data) -+{ -+ struct edma_adapter *adapter = netdev_priv(netdev); -+ struct edma_common_info *edma_cinfo = adapter->edma_cinfo; -+ int i; -+ uint8_t *p = NULL; -+ -+ edma_read_append_stats(edma_cinfo); -+ -+ for(i = 0; i < EDMA_STATS_LEN; i++) { -+ p = (uint8_t *)&(edma_cinfo->edma_ethstats) + -+ edma_gstrings_stats[i].stat_offset; -+ data[i] = *(uint32_t *)p; -+ } -+} -+ -+/* edma_get_drvinfo() -+ * get edma driver info -+ */ -+static void edma_get_drvinfo(struct net_device *dev, -+ struct ethtool_drvinfo *info) -+{ -+ strlcpy(info->driver, "ess_edma", DRVINFO_LEN); -+ strlcpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN); -+} -+ -+/* edma_nway_reset() -+ * Reset the phy, if available. -+ */ -+static int edma_nway_reset(struct net_device *netdev) -+{ -+ return -EINVAL; -+} -+ -+/* edma_get_wol() -+ * get wake on lan info -+ */ -+static void edma_get_wol(struct net_device *netdev, -+ struct ethtool_wolinfo *wol) -+{ -+ wol->supported = 0; -+ wol->wolopts = 0; -+} -+ -+/* edma_get_msglevel() -+ * get message level. -+ */ -+static uint32_t edma_get_msglevel(struct net_device *netdev) -+{ -+ return 0; -+} -+ -+/* edma_get_settings() -+ * Get edma settings -+ */ -+static int edma_get_settings(struct net_device *netdev, -+ struct ethtool_cmd *ecmd) -+{ -+ struct edma_adapter *adapter = netdev_priv(netdev); -+ -+ if (adapter->poll_required) { -+ struct phy_device *phydev = NULL; -+ uint16_t phyreg; -+ -+ if ((adapter->forced_speed != SPEED_UNKNOWN) -+ && !(adapter->poll_required)) -+ return -EPERM; -+ -+ phydev = adapter->phydev; -+ -+ ecmd->advertising = phydev->advertising; -+ ecmd->autoneg = phydev->autoneg; -+ -+ if (adapter->link_state == __EDMA_LINKDOWN) { -+ ecmd->speed = SPEED_UNKNOWN; -+ ecmd->duplex = DUPLEX_UNKNOWN; -+ } else { -+ ecmd->speed = phydev->speed; -+ ecmd->duplex = phydev->duplex; -+ } -+ -+ ecmd->phy_address = adapter->phy_mdio_addr; -+ -+ phyreg = (uint16_t)phy_read(adapter->phydev, MII_LPA); -+ if (phyreg & LPA_10HALF) -+ ecmd->lp_advertising |= ADVERTISED_10baseT_Half; -+ -+ if (phyreg & LPA_10FULL) -+ ecmd->lp_advertising |= ADVERTISED_10baseT_Full; -+ -+ if (phyreg & LPA_100HALF) -+ ecmd->lp_advertising |= ADVERTISED_100baseT_Half; -+ -+ if (phyreg & LPA_100FULL) -+ ecmd->lp_advertising |= ADVERTISED_100baseT_Full; -+ -+ phyreg = (uint16_t)phy_read(adapter->phydev, MII_STAT1000); -+ if (phyreg & LPA_1000HALF) -+ ecmd->lp_advertising |= ADVERTISED_1000baseT_Half; -+ -+ if (phyreg & LPA_1000FULL) -+ ecmd->lp_advertising |= ADVERTISED_1000baseT_Full; -+ } else { -+ /* If the speed/duplex for this GMAC is forced and we -+ * are not polling for link state changes, return the -+ * values as specified by platform. This will be true -+ * for GMACs connected to switch, and interfaces that -+ * do not use a PHY. -+ */ -+ if (!(adapter->poll_required)) { -+ if (adapter->forced_speed != SPEED_UNKNOWN) { -+ /* set speed and duplex */ -+ ethtool_cmd_speed_set(ecmd, SPEED_1000); -+ ecmd->duplex = DUPLEX_FULL; -+ -+ /* Populate capabilities advertised by self */ -+ ecmd->advertising = 0; -+ ecmd->autoneg = 0; -+ ecmd->port = PORT_TP; -+ ecmd->transceiver = XCVR_EXTERNAL; -+ } else { -+ /* non link polled and non -+ * forced speed/duplex interface -+ */ -+ return -EIO; -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+/* edma_set_settings() -+ * Set EDMA settings -+ */ -+static int edma_set_settings(struct net_device *netdev, -+ struct ethtool_cmd *ecmd) -+{ -+ struct edma_adapter *adapter = netdev_priv(netdev); -+ struct phy_device *phydev = NULL; -+ -+ if ((adapter->forced_speed != SPEED_UNKNOWN) && -+ !adapter->poll_required) -+ return -EPERM; -+ -+ phydev = adapter->phydev; -+ phydev->advertising = ecmd->advertising; -+ phydev->autoneg = ecmd->autoneg; -+ phydev->speed = ethtool_cmd_speed(ecmd); -+ phydev->duplex = ecmd->duplex; -+ -+ genphy_config_aneg(phydev); -+ -+ return 0; -+} -+ -+/* edma_get_coalesce -+ * get interrupt mitigation -+ */ -+static int edma_get_coalesce(struct net_device *netdev, -+ struct ethtool_coalesce *ec) -+{ -+ u32 reg_val; -+ -+ edma_get_tx_rx_coalesce(®_val); -+ -+ /* We read the Interrupt Moderation Timer(IMT) register value, -+ * use lower 16 bit for rx and higher 16 bit for Tx. We do a -+ * left shift by 1, because IMT resolution timer is 2usecs. -+ * Hence the value given by the register is multiplied by 2 to -+ * get the actual time in usecs. -+ */ -+ ec->tx_coalesce_usecs = (((reg_val >> 16) & 0xffff) << 1); -+ ec->rx_coalesce_usecs = ((reg_val & 0xffff) << 1); -+ -+ return 0; -+} -+ -+/* edma_set_coalesce -+ * set interrupt mitigation -+ */ -+static int edma_set_coalesce(struct net_device *netdev, -+ struct ethtool_coalesce *ec) -+{ -+ if (ec->tx_coalesce_usecs) -+ edma_change_tx_coalesce(ec->tx_coalesce_usecs); -+ if (ec->rx_coalesce_usecs) -+ edma_change_rx_coalesce(ec->rx_coalesce_usecs); -+ -+ return 0; -+} -+ -+/* edma_set_priv_flags() -+ * Set EDMA private flags -+ */ -+static int edma_set_priv_flags(struct net_device *netdev, u32 flags) -+{ -+ return 0; -+} -+ -+/* edma_get_priv_flags() -+ * get edma driver flags -+ */ -+static u32 edma_get_priv_flags(struct net_device *netdev) -+{ -+ return 0; -+} -+ -+/* edma_get_ringparam() -+ * get ring size -+ */ -+static void edma_get_ringparam(struct net_device *netdev, -+ struct ethtool_ringparam *ring) -+{ -+ struct edma_adapter *adapter = netdev_priv(netdev); -+ struct edma_common_info *edma_cinfo = adapter->edma_cinfo; -+ -+ ring->tx_max_pending = edma_cinfo->tx_ring_count; -+ ring->rx_max_pending = edma_cinfo->rx_ring_count; -+} -+ -+/* Ethtool operations -+ */ -+static const struct ethtool_ops edma_ethtool_ops = { -+ .get_drvinfo = &edma_get_drvinfo, -+ .get_link = ðtool_op_get_link, -+ .get_msglevel = &edma_get_msglevel, -+ .nway_reset = &edma_nway_reset, -+ .get_wol = &edma_get_wol, -+ .get_settings = &edma_get_settings, -+ .set_settings = &edma_set_settings, -+ .get_strings = &edma_get_strings, -+ .get_sset_count = &edma_get_strset_count, -+ .get_ethtool_stats = &edma_get_ethtool_stats, -+ .get_coalesce = &edma_get_coalesce, -+ .set_coalesce = &edma_set_coalesce, -+ .get_priv_flags = edma_get_priv_flags, -+ .set_priv_flags = edma_set_priv_flags, -+ .get_ringparam = edma_get_ringparam, -+}; -+ -+/* edma_set_ethtool_ops -+ * Set ethtool operations -+ */ -+void edma_set_ethtool_ops(struct net_device *netdev) -+{ -+ netdev->ethtool_ops = &edma_ethtool_ops; -+} ---- /dev/null -+++ b/drivers/net/ethernet/qualcomm/essedma/ess_edma.h -@@ -0,0 +1,332 @@ -+/* -+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for -+ * any purpose with or without fee is hereby granted, provided that the -+ * above copyright notice and this permission notice appear in all copies. -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+#ifndef _ESS_EDMA_H_ -+#define _ESS_EDMA_H_ -+ -+#include -+ -+struct edma_adapter; -+struct edma_hw; -+ -+/* register definition */ -+#define EDMA_REG_MAS_CTRL 0x0 -+#define EDMA_REG_TIMEOUT_CTRL 0x004 -+#define EDMA_REG_DBG0 0x008 -+#define EDMA_REG_DBG1 0x00C -+#define EDMA_REG_SW_CTRL0 0x100 -+#define EDMA_REG_SW_CTRL1 0x104 -+ -+/* Interrupt Status Register */ -+#define EDMA_REG_RX_ISR 0x200 -+#define EDMA_REG_TX_ISR 0x208 -+#define EDMA_REG_MISC_ISR 0x210 -+#define EDMA_REG_WOL_ISR 0x218 -+ -+#define EDMA_MISC_ISR_RX_URG_Q(x) (1 << x) -+ -+#define EDMA_MISC_ISR_AXIR_TIMEOUT 0x00000100 -+#define EDMA_MISC_ISR_AXIR_ERR 0x00000200 -+#define EDMA_MISC_ISR_TXF_DEAD 0x00000400 -+#define EDMA_MISC_ISR_AXIW_ERR 0x00000800 -+#define EDMA_MISC_ISR_AXIW_TIMEOUT 0x00001000 -+ -+#define EDMA_WOL_ISR 0x00000001 -+ -+/* Interrupt Mask Register */ -+#define EDMA_REG_MISC_IMR 0x214 -+#define EDMA_REG_WOL_IMR 0x218 -+ -+#define EDMA_RX_IMR_NORMAL_MASK 0x1 -+#define EDMA_TX_IMR_NORMAL_MASK 0x1 -+#define EDMA_MISC_IMR_NORMAL_MASK 0x80001FFF -+#define EDMA_WOL_IMR_NORMAL_MASK 0x1 -+ -+/* Edma receive consumer index */ -+#define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */ -+/* Edma transmit consumer index */ -+#define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */ -+ -+/* IRQ Moderator Initial Timer Register */ -+#define EDMA_REG_IRQ_MODRT_TIMER_INIT 0x280 -+#define EDMA_IRQ_MODRT_TIMER_MASK 0xFFFF -+#define EDMA_IRQ_MODRT_RX_TIMER_SHIFT 0 -+#define EDMA_IRQ_MODRT_TX_TIMER_SHIFT 16 -+ -+/* Interrupt Control Register */ -+#define EDMA_REG_INTR_CTRL 0x284 -+#define EDMA_INTR_CLR_TYP_SHIFT 0 -+#define EDMA_INTR_SW_IDX_W_TYP_SHIFT 1 -+#define EDMA_INTR_CLEAR_TYPE_W1 0 -+#define EDMA_INTR_CLEAR_TYPE_R 1 -+ -+/* RX Interrupt Mask Register */ -+#define EDMA_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */ -+ -+/* TX Interrupt mask register */ -+#define EDMA_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */ -+ -+/* Load Ptr Register -+ * Software sets this bit after the initialization of the head and tail -+ */ -+#define EDMA_REG_TX_SRAM_PART 0x400 -+#define EDMA_LOAD_PTR_SHIFT 16 -+ -+/* TXQ Control Register */ -+#define EDMA_REG_TXQ_CTRL 0x404 -+#define EDMA_TXQ_CTRL_IP_OPTION_EN 0x10 -+#define EDMA_TXQ_CTRL_TXQ_EN 0x20 -+#define EDMA_TXQ_CTRL_ENH_MODE 0x40 -+#define EDMA_TXQ_CTRL_LS_8023_EN 0x80 -+#define EDMA_TXQ_CTRL_TPD_BURST_EN 0x100 -+#define EDMA_TXQ_CTRL_LSO_BREAK_EN 0x200 -+#define EDMA_TXQ_NUM_TPD_BURST_MASK 0xF -+#define EDMA_TXQ_TXF_BURST_NUM_MASK 0xFFFF -+#define EDMA_TXQ_NUM_TPD_BURST_SHIFT 0 -+#define EDMA_TXQ_TXF_BURST_NUM_SHIFT 16 -+ -+#define EDMA_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */ -+#define EDMA_TXF_WATER_MARK_MASK 0x0FFF -+#define EDMA_TXF_LOW_WATER_MARK_SHIFT 0 -+#define EDMA_TXF_HIGH_WATER_MARK_SHIFT 16 -+#define EDMA_TXQ_CTRL_BURST_MODE_EN 0x80000000 -+ -+/* WRR Control Register */ -+#define EDMA_REG_WRR_CTRL_Q0_Q3 0x40c -+#define EDMA_REG_WRR_CTRL_Q4_Q7 0x410 -+#define EDMA_REG_WRR_CTRL_Q8_Q11 0x414 -+#define EDMA_REG_WRR_CTRL_Q12_Q15 0x418 -+ -+/* Weight round robin(WRR), it takes queue as input, and computes -+ * starting bits where we need to write the weight for a particular -+ * queue -+ */ -+#define EDMA_WRR_SHIFT(x) (((x) * 5) % 20) -+ -+/* Tx Descriptor Control Register */ -+#define EDMA_REG_TPD_RING_SIZE 0x41C -+#define EDMA_TPD_RING_SIZE_SHIFT 0 -+#define EDMA_TPD_RING_SIZE_MASK 0xFFFF -+ -+/* Transmit descriptor base address */ -+#define EDMA_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */ -+ -+/* TPD Index Register */ -+#define EDMA_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */ -+ -+#define EDMA_TPD_PROD_IDX_BITS 0x0000FFFF -+#define EDMA_TPD_CONS_IDX_BITS 0xFFFF0000 -+#define EDMA_TPD_PROD_IDX_MASK 0xFFFF -+#define EDMA_TPD_CONS_IDX_MASK 0xFFFF -+#define EDMA_TPD_PROD_IDX_SHIFT 0 -+#define EDMA_TPD_CONS_IDX_SHIFT 16 -+ -+/* TX Virtual Queue Mapping Control Register */ -+#define EDMA_REG_VQ_CTRL0 0x4A0 -+#define EDMA_REG_VQ_CTRL1 0x4A4 -+ -+/* Virtual QID shift, it takes queue as input, and computes -+ * Virtual QID position in virtual qid control register -+ */ -+#define EDMA_VQ_ID_SHIFT(i) (((i) * 3) % 24) -+ -+/* Virtual Queue Default Value */ -+#define EDMA_VQ_REG_VALUE 0x240240 -+ -+/* Tx side Port Interface Control Register */ -+#define EDMA_REG_PORT_CTRL 0x4A8 -+#define EDMA_PAD_EN_SHIFT 15 -+ -+/* Tx side VLAN Configuration Register */ -+#define EDMA_REG_VLAN_CFG 0x4AC -+ -+#define EDMA_TX_CVLAN 16 -+#define EDMA_TX_INS_CVLAN 17 -+#define EDMA_TX_CVLAN_TAG_SHIFT 0 -+ -+#define EDMA_TX_SVLAN 14 -+#define EDMA_TX_INS_SVLAN 15 -+#define EDMA_TX_SVLAN_TAG_SHIFT 16 -+ -+/* Tx Queue Packet Statistic Register */ -+#define EDMA_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */ -+ -+#define EDMA_TX_STAT_PKT_MASK 0xFFFFFF -+ -+/* Tx Queue Byte Statistic Register */ -+#define EDMA_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */ -+ -+/* Load Balance Based Ring Offset Register */ -+#define EDMA_REG_LB_RING 0x800 -+#define EDMA_LB_RING_ENTRY_MASK 0xff -+#define EDMA_LB_RING_ID_MASK 0x7 -+#define EDMA_LB_RING_PROFILE_ID_MASK 0x3 -+#define EDMA_LB_RING_ENTRY_BIT_OFFSET 8 -+#define EDMA_LB_RING_ID_OFFSET 0 -+#define EDMA_LB_RING_PROFILE_ID_OFFSET 3 -+#define EDMA_LB_REG_VALUE 0x6040200 -+ -+/* Load Balance Priority Mapping Register */ -+#define EDMA_REG_LB_PRI_START 0x804 -+#define EDMA_REG_LB_PRI_END 0x810 -+#define EDMA_LB_PRI_REG_INC 4 -+#define EDMA_LB_PRI_ENTRY_BIT_OFFSET 4 -+#define EDMA_LB_PRI_ENTRY_MASK 0xf -+ -+/* RSS Priority Mapping Register */ -+#define EDMA_REG_RSS_PRI 0x820 -+#define EDMA_RSS_PRI_ENTRY_MASK 0xf -+#define EDMA_RSS_RING_ID_MASK 0x7 -+#define EDMA_RSS_PRI_ENTRY_BIT_OFFSET 4 -+ -+/* RSS Indirection Register */ -+#define EDMA_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */ -+#define EDMA_NUM_IDT 16 -+#define EDMA_RSS_IDT_VALUE 0x64206420 -+ -+/* Default RSS Ring Register */ -+#define EDMA_REG_DEF_RSS 0x890 -+#define EDMA_DEF_RSS_MASK 0x7 -+ -+/* RSS Hash Function Type Register */ -+#define EDMA_REG_RSS_TYPE 0x894 -+#define EDMA_RSS_TYPE_NONE 0x01 -+#define EDMA_RSS_TYPE_IPV4TCP 0x02 -+#define EDMA_RSS_TYPE_IPV6_TCP 0x04 -+#define EDMA_RSS_TYPE_IPV4_UDP 0x08 -+#define EDMA_RSS_TYPE_IPV6UDP 0x10 -+#define EDMA_RSS_TYPE_IPV4 0x20 -+#define EDMA_RSS_TYPE_IPV6 0x40 -+#define EDMA_RSS_HASH_MODE_MASK 0x7f -+ -+#define EDMA_REG_RSS_HASH_VALUE 0x8C0 -+ -+#define EDMA_REG_RSS_TYPE_RESULT 0x8C4 -+ -+#define EDMA_HASH_TYPE_START 0 -+#define EDMA_HASH_TYPE_END 5 -+#define EDMA_HASH_TYPE_SHIFT 12 -+ -+#define EDMA_RFS_FLOW_ENTRIES 1024 -+#define EDMA_RFS_FLOW_ENTRIES_MASK (EDMA_RFS_FLOW_ENTRIES - 1) -+#define EDMA_RFS_EXPIRE_COUNT_PER_CALL 128 -+ -+/* RFD Base Address Register */ -+#define EDMA_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */ -+ -+/* RFD Index Register */ -+#define EDMA_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2)) -+ -+#define EDMA_RFD_PROD_IDX_BITS 0x00000FFF -+#define EDMA_RFD_CONS_IDX_BITS 0x0FFF0000 -+#define EDMA_RFD_PROD_IDX_MASK 0xFFF -+#define EDMA_RFD_CONS_IDX_MASK 0xFFF -+#define EDMA_RFD_PROD_IDX_SHIFT 0 -+#define EDMA_RFD_CONS_IDX_SHIFT 16 -+ -+/* Rx Descriptor Control Register */ -+#define EDMA_REG_RX_DESC0 0xA10 -+#define EDMA_RFD_RING_SIZE_MASK 0xFFF -+#define EDMA_RX_BUF_SIZE_MASK 0xFFFF -+#define EDMA_RFD_RING_SIZE_SHIFT 0 -+#define EDMA_RX_BUF_SIZE_SHIFT 16 -+ -+#define EDMA_REG_RX_DESC1 0xA14 -+#define EDMA_RXQ_RFD_BURST_NUM_MASK 0x3F -+#define EDMA_RXQ_RFD_PF_THRESH_MASK 0x1F -+#define EDMA_RXQ_RFD_LOW_THRESH_MASK 0xFFF -+#define EDMA_RXQ_RFD_BURST_NUM_SHIFT 0 -+#define EDMA_RXQ_RFD_PF_THRESH_SHIFT 8 -+#define EDMA_RXQ_RFD_LOW_THRESH_SHIFT 16 -+ -+/* RXQ Control Register */ -+#define EDMA_REG_RXQ_CTRL 0xA18 -+#define EDMA_FIFO_THRESH_TYPE_SHIF 0 -+#define EDMA_FIFO_THRESH_128_BYTE 0x0 -+#define EDMA_FIFO_THRESH_64_BYTE 0x1 -+#define EDMA_RXQ_CTRL_RMV_VLAN 0x00000002 -+#define EDMA_RXQ_CTRL_EN 0x0000FF00 -+ -+/* AXI Burst Size Config */ -+#define EDMA_REG_AXIW_CTRL_MAXWRSIZE 0xA1C -+#define EDMA_AXIW_MAXWRSIZE_VALUE 0x0 -+ -+/* Rx Statistics Register */ -+#define EDMA_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */ -+#define EDMA_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */ -+ -+/* WoL Pattern Length Register */ -+#define EDMA_REG_WOL_PATTERN_LEN0 0xC00 -+#define EDMA_WOL_PT_LEN_MASK 0xFF -+#define EDMA_WOL_PT0_LEN_SHIFT 0 -+#define EDMA_WOL_PT1_LEN_SHIFT 8 -+#define EDMA_WOL_PT2_LEN_SHIFT 16 -+#define EDMA_WOL_PT3_LEN_SHIFT 24 -+ -+#define EDMA_REG_WOL_PATTERN_LEN1 0xC04 -+#define EDMA_WOL_PT4_LEN_SHIFT 0 -+#define EDMA_WOL_PT5_LEN_SHIFT 8 -+#define EDMA_WOL_PT6_LEN_SHIFT 16 -+ -+/* WoL Control Register */ -+#define EDMA_REG_WOL_CTRL 0xC08 -+#define EDMA_WOL_WK_EN 0x00000001 -+#define EDMA_WOL_MG_EN 0x00000002 -+#define EDMA_WOL_PT0_EN 0x00000004 -+#define EDMA_WOL_PT1_EN 0x00000008 -+#define EDMA_WOL_PT2_EN 0x00000010 -+#define EDMA_WOL_PT3_EN 0x00000020 -+#define EDMA_WOL_PT4_EN 0x00000040 -+#define EDMA_WOL_PT5_EN 0x00000080 -+#define EDMA_WOL_PT6_EN 0x00000100 -+ -+/* MAC Control Register */ -+#define EDMA_REG_MAC_CTRL0 0xC20 -+#define EDMA_REG_MAC_CTRL1 0xC24 -+ -+/* WoL Pattern Register */ -+#define EDMA_REG_WOL_PATTERN_START 0x5000 -+#define EDMA_PATTERN_PART_REG_OFFSET 0x40 -+ -+ -+/* TX descriptor fields */ -+#define EDMA_TPD_HDR_SHIFT 0 -+#define EDMA_TPD_PPPOE_EN 0x00000100 -+#define EDMA_TPD_IP_CSUM_EN 0x00000200 -+#define EDMA_TPD_TCP_CSUM_EN 0x0000400 -+#define EDMA_TPD_UDP_CSUM_EN 0x00000800 -+#define EDMA_TPD_CUSTOM_CSUM_EN 0x00000C00 -+#define EDMA_TPD_LSO_EN 0x00001000 -+#define EDMA_TPD_LSO_V2_EN 0x00002000 -+#define EDMA_TPD_IPV4_EN 0x00010000 -+#define EDMA_TPD_MSS_MASK 0x1FFF -+#define EDMA_TPD_MSS_SHIFT 18 -+#define EDMA_TPD_CUSTOM_CSUM_SHIFT 18 -+ -+/* RRD descriptor fields */ -+#define EDMA_RRD_NUM_RFD_MASK 0x000F -+#define EDMA_RRD_SVLAN 0x8000 -+#define EDMA_RRD_FLOW_COOKIE_MASK 0x07FF; -+ -+#define EDMA_RRD_PKT_SIZE_MASK 0x3FFF -+#define EDMA_RRD_CSUM_FAIL_MASK 0xC000 -+#define EDMA_RRD_CVLAN 0x0001 -+#define EDMA_RRD_DESC_VALID 0x8000 -+ -+#define EDMA_RRD_PRIORITY_SHIFT 4 -+#define EDMA_RRD_PRIORITY_MASK 0x7 -+#define EDMA_RRD_PORT_TYPE_SHIFT 7 -+#define EDMA_RRD_PORT_TYPE_MASK 0x1F -+#endif /* _ESS_EDMA_H_ */ diff --git a/target/linux/ipq40xx/patches-4.19/711-dts-ipq4019-add-ethernet-essedma-node.patch b/target/linux/ipq40xx/patches-4.19/711-dts-ipq4019-add-ethernet-essedma-node.patch deleted file mode 100644 index 9f9cb5287c..0000000000 --- a/target/linux/ipq40xx/patches-4.19/711-dts-ipq4019-add-ethernet-essedma-node.patch +++ /dev/null @@ -1,92 +0,0 @@ -From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sun, 20 Nov 2016 01:01:10 +0100 -Subject: [PATCH] dts: ipq4019: add ethernet essedma node - -This patch adds the device-tree node for the ethernet -interfaces. - -Note: The driver isn't anywhere close to be upstream, -so the info might change. - -Signed-off-by: Christian Lamparter ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 60 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -44,6 +44,8 @@ - spi1 = &blsp1_spi2; - i2c0 = &blsp1_i2c3; - i2c1 = &blsp1_i2c4; -+ ethernet0 = &gmac0; -+ ethernet1 = &gmac1; - }; - - cpus { -@@ -644,6 +646,64 @@ - status = "disabled"; - }; - -+ edma@c080000 { -+ compatible = "qcom,ess-edma"; -+ reg = <0xc080000 0x8000>; -+ qcom,page-mode = <0>; -+ qcom,rx_head_buf_size = <1540>; -+ qcom,mdio_supported; -+ qcom,poll_required = <1>; -+ qcom,num_gmac = <2>; -+ interrupts = <0 65 IRQ_TYPE_EDGE_RISING -+ 0 66 IRQ_TYPE_EDGE_RISING -+ 0 67 IRQ_TYPE_EDGE_RISING -+ 0 68 IRQ_TYPE_EDGE_RISING -+ 0 69 IRQ_TYPE_EDGE_RISING -+ 0 70 IRQ_TYPE_EDGE_RISING -+ 0 71 IRQ_TYPE_EDGE_RISING -+ 0 72 IRQ_TYPE_EDGE_RISING -+ 0 73 IRQ_TYPE_EDGE_RISING -+ 0 74 IRQ_TYPE_EDGE_RISING -+ 0 75 IRQ_TYPE_EDGE_RISING -+ 0 76 IRQ_TYPE_EDGE_RISING -+ 0 77 IRQ_TYPE_EDGE_RISING -+ 0 78 IRQ_TYPE_EDGE_RISING -+ 0 79 IRQ_TYPE_EDGE_RISING -+ 0 80 IRQ_TYPE_EDGE_RISING -+ 0 240 IRQ_TYPE_EDGE_RISING -+ 0 241 IRQ_TYPE_EDGE_RISING -+ 0 242 IRQ_TYPE_EDGE_RISING -+ 0 243 IRQ_TYPE_EDGE_RISING -+ 0 244 IRQ_TYPE_EDGE_RISING -+ 0 245 IRQ_TYPE_EDGE_RISING -+ 0 246 IRQ_TYPE_EDGE_RISING -+ 0 247 IRQ_TYPE_EDGE_RISING -+ 0 248 IRQ_TYPE_EDGE_RISING -+ 0 249 IRQ_TYPE_EDGE_RISING -+ 0 250 IRQ_TYPE_EDGE_RISING -+ 0 251 IRQ_TYPE_EDGE_RISING -+ 0 252 IRQ_TYPE_EDGE_RISING -+ 0 253 IRQ_TYPE_EDGE_RISING -+ 0 254 IRQ_TYPE_EDGE_RISING -+ 0 255 IRQ_TYPE_EDGE_RISING>; -+ -+ status = "disabled"; -+ -+ gmac0: gmac0 { -+ local-mac-address = [00 00 00 00 00 00]; -+ vlan_tag = <1 0x1f>; -+ }; -+ -+ gmac1: gmac1 { -+ local-mac-address = [00 00 00 00 00 00]; -+ qcom,phy_mdio_addr = <4>; -+ qcom,poll_required = <1>; -+ qcom,forced_speed = <1000>; -+ qcom,forced_duplex = <1>; -+ vlan_tag = <2 0x20>; -+ }; -+ }; -+ - usb3_ss_phy: ssphy@9a000 { - compatible = "qcom,usb-ss-ipq4019-phy"; - #phy-cells = <0>; diff --git a/target/linux/ipq40xx/patches-4.19/712-mr33-essedma.patch b/target/linux/ipq40xx/patches-4.19/712-mr33-essedma.patch deleted file mode 100644 index ee6452eebb..0000000000 --- a/target/linux/ipq40xx/patches-4.19/712-mr33-essedma.patch +++ /dev/null @@ -1,334 +0,0 @@ ---- a/drivers/net/ethernet/qualcomm/essedma/edma.c -+++ b/drivers/net/ethernet/qualcomm/essedma/edma.c -@@ -161,8 +161,10 @@ static void edma_configure_rx(struct edm - /* Set Rx FIFO threshold to start to DMA data to host */ - rxq_ctrl_data = EDMA_FIFO_THRESH_128_BYTE; - -+ if (!edma_cinfo->is_single_phy) { - /* Set RX remove vlan bit */ - rxq_ctrl_data |= EDMA_RXQ_CTRL_RMV_VLAN; -+ } - - edma_write_reg(EDMA_REG_RXQ_CTRL, rxq_ctrl_data); - } -@@ -1293,6 +1295,10 @@ void edma_adjust_link(struct net_device - if (status == __EDMA_LINKUP && adapter->link_state == __EDMA_LINKDOWN) { - dev_info(&adapter->pdev->dev, "%s: GMAC Link is up with phy_speed=%d\n", netdev->name, phydev->speed); - adapter->link_state = __EDMA_LINKUP; -+ if (adapter->edma_cinfo->is_single_phy) { -+ ess_set_port_status_speed(adapter->edma_cinfo, phydev, -+ ffs(adapter->dp_bitmap) - 1); -+ } - netif_carrier_on(netdev); - if (netif_running(netdev)) - netif_tx_wake_all_queues(netdev); -@@ -1386,10 +1392,12 @@ netdev_tx_t edma_xmit(struct sk_buff *sk - } - - /* Check and mark VLAN tag offload */ -- if (skb_vlan_tag_present(skb)) -- flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG; -- else if (adapter->default_vlan_tag) -- flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG; -+ if (!adapter->edma_cinfo->is_single_phy) { -+ if (unlikely(skb_vlan_tag_present(skb))) -+ flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG; -+ else if (adapter->default_vlan_tag) -+ flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG; -+ } - - /* Check and mark checksum offload */ - if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) ---- a/drivers/net/ethernet/qualcomm/essedma/edma.h -+++ b/drivers/net/ethernet/qualcomm/essedma/edma.h -@@ -31,6 +31,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -332,6 +333,9 @@ struct edma_common_info { - struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */ - spinlock_t stats_lock; /* protect edma stats area for updation */ - struct timer_list edma_stats_timer; -+ bool is_single_phy; -+ void __iomem *ess_hw_addr; -+ struct clk *ess_clk; - }; - - /* transimit packet descriptor (tpd) ring */ -@@ -444,4 +448,6 @@ void edma_change_tx_coalesce(int usecs); - void edma_change_rx_coalesce(int usecs); - void edma_get_tx_rx_coalesce(u32 *reg_val); - void edma_clear_irq_status(void); -+void ess_set_port_status_speed(struct edma_common_info *edma_cinfo, -+ struct phy_device *phydev, uint8_t port_id); - #endif /* _EDMA_H_ */ ---- a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c -+++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c -@@ -17,6 +17,11 @@ - #include - #include - #include -+#include -+#include -+#include -+#include -+#include - #include "edma.h" - #include "ess_edma.h" - -@@ -81,6 +86,101 @@ void edma_read_reg(u16 reg_addr, volatil - *reg_value = readl((void __iomem *)(edma_hw_addr + reg_addr)); - } - -+static void ess_write_reg(struct edma_common_info *edma, u16 reg_addr, u32 reg_value) -+{ -+ writel(reg_value, ((void __iomem *) -+ ((unsigned long)edma->ess_hw_addr + reg_addr))); -+} -+ -+static void ess_read_reg(struct edma_common_info *edma, u16 reg_addr, -+ volatile u32 *reg_value) -+{ -+ *reg_value = readl((void __iomem *) -+ ((unsigned long)edma->ess_hw_addr + reg_addr)); -+} -+ -+static int ess_reset(struct edma_common_info *edma) -+{ -+ struct device_node *switch_node = NULL; -+ struct reset_control *ess_rst; -+ u32 regval; -+ -+ switch_node = of_find_node_by_name(NULL, "ess-switch"); -+ if (!switch_node) { -+ pr_err("switch-node not found\n"); -+ return -EINVAL; -+ } -+ -+ ess_rst = of_reset_control_get(switch_node, "ess_rst"); -+ of_node_put(switch_node); -+ -+ if (IS_ERR(ess_rst)) { -+ pr_err("failed to find ess_rst!\n"); -+ return -ENOENT; -+ } -+ -+ reset_control_assert(ess_rst); -+ msleep(10); -+ reset_control_deassert(ess_rst); -+ msleep(100); -+ reset_control_put(ess_rst); -+ -+ /* Enable only port 5 <--> port 0 -+ * bits 0:6 bitmap of ports it can fwd to */ -+#define SET_PORT_BMP(r,v) \ -+ ess_read_reg(edma, r, ®val); \ -+ ess_write_reg(edma, r, ((regval & ~0x3F) | v)); -+ -+ SET_PORT_BMP(ESS_PORT0_LOOKUP_CTRL,0x20); -+ SET_PORT_BMP(ESS_PORT1_LOOKUP_CTRL,0x00); -+ SET_PORT_BMP(ESS_PORT2_LOOKUP_CTRL,0x00); -+ SET_PORT_BMP(ESS_PORT3_LOOKUP_CTRL,0x00); -+ SET_PORT_BMP(ESS_PORT4_LOOKUP_CTRL,0x00); -+ SET_PORT_BMP(ESS_PORT5_LOOKUP_CTRL,0x01); -+ ess_write_reg(edma, ESS_RGMII_CTRL, 0x400); -+ ess_write_reg(edma, ESS_PORT0_STATUS, ESS_PORT_1G_FDX); -+ ess_write_reg(edma, ESS_PORT5_STATUS, ESS_PORT_1G_FDX); -+ ess_write_reg(edma, ESS_PORT0_HEADER_CTRL, 0); -+#undef SET_PORT_BMP -+ -+ /* forward multicast and broadcast frames to CPU */ -+ ess_write_reg(edma, ESS_FWD_CTRL1, -+ (ESS_PORTS_ALL << ESS_FWD_CTRL1_UC_FLOOD_S) | -+ (ESS_PORTS_ALL << ESS_FWD_CTRL1_MC_FLOOD_S) | -+ (ESS_PORTS_ALL << ESS_FWD_CTRL1_BC_FLOOD_S)); -+ -+ return 0; -+} -+ -+void ess_set_port_status_speed(struct edma_common_info *edma, -+ struct phy_device *phydev, uint8_t port_id) -+{ -+ uint16_t reg_off = ESS_PORT0_STATUS + (4 * port_id); -+ uint32_t reg_val = 0; -+ -+ ess_read_reg(edma, reg_off, ®_val); -+ -+ /* reset the speed bits [0:1] */ -+ reg_val &= ~ESS_PORT_STATUS_SPEED_INV; -+ -+ /* set the new speed */ -+ switch(phydev->speed) { -+ case SPEED_1000: reg_val |= ESS_PORT_STATUS_SPEED_1000; break; -+ case SPEED_100: reg_val |= ESS_PORT_STATUS_SPEED_100; break; -+ case SPEED_10: reg_val |= ESS_PORT_STATUS_SPEED_10; break; -+ default: reg_val |= ESS_PORT_STATUS_SPEED_INV; break; -+ } -+ -+ /* check full/half duplex */ -+ if (phydev->duplex) { -+ reg_val |= ESS_PORT_STATUS_DUPLEX_MODE; -+ } else { -+ reg_val &= ~ESS_PORT_STATUS_DUPLEX_MODE; -+ } -+ -+ ess_write_reg(edma, reg_off, reg_val); -+} -+ - /* edma_change_tx_coalesce() - * change tx interrupt moderation timer - */ -@@ -550,6 +650,31 @@ static struct ctl_table edma_table[] = { - {} - }; - -+static int ess_parse(struct edma_common_info *edma) -+{ -+ struct device_node *switch_node; -+ int ret = -EINVAL; -+ -+ switch_node = of_find_node_by_name(NULL, "ess-switch"); -+ if (!switch_node) { -+ pr_err("cannot find ess-switch node\n"); -+ goto out; -+ } -+ -+ edma->ess_hw_addr = of_io_request_and_map(switch_node, -+ 0, KBUILD_MODNAME); -+ if (!edma->ess_hw_addr) { -+ pr_err("%s ioremap fail.", __func__); -+ goto out; -+ } -+ -+ edma->ess_clk = of_clk_get_by_name(switch_node, "ess_clk"); -+ ret = clk_prepare_enable(edma->ess_clk); -+out: -+ of_node_put(switch_node); -+ return ret; -+} -+ - /* edma_axi_netdev_ops - * Describe the operations supported by registered netdevices - * -@@ -785,6 +910,17 @@ static int edma_axi_probe(struct platfor - miibus = mdio_data->mii_bus; - } - -+ if (of_property_read_bool(np, "qcom,single-phy") && -+ edma_cinfo->num_gmac == 1) { -+ err = ess_parse(edma_cinfo); -+ if (!err) -+ err = ess_reset(edma_cinfo); -+ if (err) -+ goto err_single_phy_init; -+ else -+ edma_cinfo->is_single_phy = true; -+ } -+ - for_each_available_child_of_node(np, pnp) { - const char *mac_addr; - -@@ -1073,11 +1209,15 @@ static int edma_axi_probe(struct platfor - - for (i = 0; i < edma_cinfo->num_gmac; i++) { - if (adapter[i]->poll_required) { -+ int phy_mode = of_get_phy_mode(np); -+ -+ if (phy_mode < 0) -+ phy_mode = PHY_INTERFACE_MODE_SGMII; - adapter[i]->phydev = - phy_connect(edma_netdev[i], - (const char *)adapter[i]->phy_id, - &edma_adjust_link, -- PHY_INTERFACE_MODE_SGMII); -+ phy_mode); - if (IS_ERR(adapter[i]->phydev)) { - dev_dbg(&pdev->dev, "PHY attach FAIL"); - err = -EIO; -@@ -1121,6 +1261,9 @@ err_rmap_alloc_fail: - for (i = 0; i < edma_cinfo->num_gmac; i++) - unregister_netdev(edma_netdev[i]); - err_register: -+err_single_phy_init: -+ iounmap(edma_cinfo->ess_hw_addr); -+ clk_disable_unprepare(edma_cinfo->ess_clk); - err_mdiobus_init_fail: - edma_free_rx_rings(edma_cinfo); - err_rx_rinit: -@@ -1181,6 +1324,8 @@ static int edma_axi_remove(struct platfo - del_timer_sync(&edma_cinfo->edma_stats_timer); - edma_free_irqs(adapter); - unregister_net_sysctl_table(edma_cinfo->edma_ctl_table_hdr); -+ iounmap(edma_cinfo->ess_hw_addr); -+ clk_disable_unprepare(edma_cinfo->ess_clk); - edma_free_tx_resources(edma_cinfo); - edma_free_rx_resources(edma_cinfo); - edma_free_tx_rings(edma_cinfo); ---- a/drivers/net/ethernet/qualcomm/essedma/ess_edma.h -+++ b/drivers/net/ethernet/qualcomm/essedma/ess_edma.h -@@ -329,4 +329,61 @@ struct edma_hw; - #define EDMA_RRD_PRIORITY_MASK 0x7 - #define EDMA_RRD_PORT_TYPE_SHIFT 7 - #define EDMA_RRD_PORT_TYPE_MASK 0x1F -+ -+#define ESS_RGMII_CTRL 0x0004 -+ -+/* Port status registers */ -+#define ESS_PORT0_STATUS 0x007C -+#define ESS_PORT1_STATUS 0x0080 -+#define ESS_PORT2_STATUS 0x0084 -+#define ESS_PORT3_STATUS 0x0088 -+#define ESS_PORT4_STATUS 0x008C -+#define ESS_PORT5_STATUS 0x0090 -+ -+#define ESS_PORT_STATUS_HDX_FLOW_CTL 0x80 -+#define ESS_PORT_STATUS_DUPLEX_MODE 0x40 -+#define ESS_PORT_STATUS_RX_FLOW_EN 0x20 -+#define ESS_PORT_STATUS_TX_FLOW_EN 0x10 -+#define ESS_PORT_STATUS_RX_MAC_EN 0x08 -+#define ESS_PORT_STATUS_TX_MAC_EN 0x04 -+#define ESS_PORT_STATUS_SPEED_INV 0x03 -+#define ESS_PORT_STATUS_SPEED_1000 0x02 -+#define ESS_PORT_STATUS_SPEED_100 0x01 -+#define ESS_PORT_STATUS_SPEED_10 0x00 -+ -+#define ESS_PORT_1G_FDX (ESS_PORT_STATUS_DUPLEX_MODE | ESS_PORT_STATUS_RX_FLOW_EN | \ -+ ESS_PORT_STATUS_TX_FLOW_EN | ESS_PORT_STATUS_RX_MAC_EN | \ -+ ESS_PORT_STATUS_TX_MAC_EN | ESS_PORT_STATUS_SPEED_1000) -+ -+#define PHY_STATUS_REG 0x11 -+#define PHY_STATUS_SPEED 0xC000 -+#define PHY_STATUS_SPEED_SHIFT 14 -+#define PHY_STATUS_DUPLEX 0x2000 -+#define PHY_STATUS_DUPLEX_SHIFT 13 -+#define PHY_STATUS_SPEED_DUPLEX_RESOLVED 0x0800 -+#define PHY_STATUS_CARRIER 0x0400 -+#define PHY_STATUS_CARRIER_SHIFT 10 -+ -+/* Port lookup control registers */ -+#define ESS_PORT0_LOOKUP_CTRL 0x0660 -+#define ESS_PORT1_LOOKUP_CTRL 0x066C -+#define ESS_PORT2_LOOKUP_CTRL 0x0678 -+#define ESS_PORT3_LOOKUP_CTRL 0x0684 -+#define ESS_PORT4_LOOKUP_CTRL 0x0690 -+#define ESS_PORT5_LOOKUP_CTRL 0x069C -+ -+#define ESS_PORT0_HEADER_CTRL 0x009C -+ -+#define ESS_PORTS_ALL 0x3f -+ -+#define ESS_FWD_CTRL1 0x0624 -+#define ESS_FWD_CTRL1_UC_FLOOD BITS(0, 7) -+#define ESS_FWD_CTRL1_UC_FLOOD_S 0 -+#define ESS_FWD_CTRL1_MC_FLOOD BITS(8, 7) -+#define ESS_FWD_CTRL1_MC_FLOOD_S 8 -+#define ESS_FWD_CTRL1_BC_FLOOD BITS(16, 7) -+#define ESS_FWD_CTRL1_BC_FLOOD_S 16 -+#define ESS_FWD_CTRL1_IGMP BITS(24, 7) -+#define ESS_FWD_CTRL1_IGMP_S 24 -+ - #endif /* _ESS_EDMA_H_ */ diff --git a/target/linux/ipq40xx/patches-4.19/713-essedma-alloc-skb-ip-align.patch b/target/linux/ipq40xx/patches-4.19/713-essedma-alloc-skb-ip-align.patch deleted file mode 100644 index 8c70fceb01..0000000000 --- a/target/linux/ipq40xx/patches-4.19/713-essedma-alloc-skb-ip-align.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 17681f0bb474d0d227f07369144149d1555d8bce Mon Sep 17 00:00:00 2001 -From: Chen Minqiang -Date: Sun, 17 Jun 2018 04:14:13 +0800 -Subject: [PATCH] essedma: alloc skb ip align - -Signed-off-by: Chen Minqiang ---- - drivers/net/ethernet/qualcomm/essedma/edma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/qualcomm/essedma/edma.c -+++ b/drivers/net/ethernet/qualcomm/essedma/edma.c -@@ -201,7 +201,7 @@ static int edma_alloc_rx_buf(struct edma - skb = sw_desc->skb; - } else { - /* alloc skb */ -- skb = netdev_alloc_skb(edma_netdev[0], length); -+ skb = netdev_alloc_skb_ip_align(edma_netdev[0], length); - if (!skb) { - /* Better luck next round */ - break; diff --git a/target/linux/ipq40xx/patches-4.19/714-essedma-add-fix-for-memory-allocation.patch b/target/linux/ipq40xx/patches-4.19/714-essedma-add-fix-for-memory-allocation.patch deleted file mode 100644 index 5b9fcf780c..0000000000 --- a/target/linux/ipq40xx/patches-4.19/714-essedma-add-fix-for-memory-allocation.patch +++ /dev/null @@ -1,197 +0,0 @@ -From 72c050acbc425ef99313d5c2e4c866e25567e569 Mon Sep 17 00:00:00 2001 -From: Rakesh Nair -Date: Thu, 8 Jun 2017 14:29:20 +0530 -Subject: [PATCH] CHROMIUM: net: qualcomm: Add fix for memory allocation issues - -Added ethtool counters for memory allocation failures accounting. -Added support to track number of allocation failures that could -not be fulfilled in the current iteration in the rx descriptor -field and use the info to allocate in the subsequent iteration. - -Change-Id: Ie4fd3b6cf25304e5db2c9247a498791e7e9bb4aa -Signed-off-by: Rakesh Nair -Signed-off-by: Kan Yan -Reviewed-on: https://chromium-review.googlesource.com/535419 -Reviewed-by: Grant Grundler ---- - drivers/net/ethernet/qualcomm/essedma/edma.c | 54 ++++++++++++++----- - drivers/net/ethernet/qualcomm/essedma/edma.h | 2 + - .../ethernet/qualcomm/essedma/edma_ethtool.c | 1 + - 3 files changed, 43 insertions(+), 14 deletions(-) - ---- a/drivers/net/ethernet/qualcomm/essedma/edma.c -+++ b/drivers/net/ethernet/qualcomm/essedma/edma.c -@@ -103,6 +103,9 @@ static int edma_alloc_rx_ring(struct edm - return -ENOMEM; - } - -+ /* Initialize pending_fill */ -+ erxd->pending_fill = 0; -+ - return 0; - } - -@@ -185,11 +188,8 @@ static int edma_alloc_rx_buf(struct edma - u16 prod_idx, length; - u32 reg_data; - -- if (cleaned_count > erdr->count) { -- dev_err(&pdev->dev, "Incorrect cleaned_count %d", -- cleaned_count); -- return -1; -- } -+ if (cleaned_count > erdr->count) -+ cleaned_count = erdr->count - 1; - - i = erdr->sw_next_to_fill; - -@@ -199,6 +199,9 @@ static int edma_alloc_rx_buf(struct edma - - if (sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_REUSE) { - skb = sw_desc->skb; -+ -+ /* Clear REUSE Flag */ -+ sw_desc->flags &= ~EDMA_SW_DESC_FLAG_SKB_REUSE; - } else { - /* alloc skb */ - skb = netdev_alloc_skb_ip_align(edma_netdev[0], length); -@@ -264,6 +267,13 @@ static int edma_alloc_rx_buf(struct edma - reg_data &= ~EDMA_RFD_PROD_IDX_BITS; - reg_data |= prod_idx; - edma_write_reg(EDMA_REG_RFD_IDX_Q(queue_id), reg_data); -+ -+ /* If we couldn't allocate all the buffers -+ * we increment the alloc failure counters -+ */ -+ if (cleaned_count) -+ edma_cinfo->edma_ethstats.rx_alloc_fail_ctr++; -+ - return cleaned_count; - } - -@@ -534,7 +544,7 @@ static int edma_rx_complete_paged(struct - * edma_rx_complete() - * Main api called from the poll function to process rx packets. - */ --static void edma_rx_complete(struct edma_common_info *edma_cinfo, -+static u16 edma_rx_complete(struct edma_common_info *edma_cinfo, - int *work_done, int work_to_do, int queue_id, - struct napi_struct *napi) - { -@@ -554,6 +564,7 @@ static void edma_rx_complete(struct edma - u16 count = erdr->count, rfd_avail; - u8 queue_to_rxid[8] = {0, 0, 1, 1, 2, 2, 3, 3}; - -+ cleaned_count = erdr->pending_fill; - sw_next_to_clean = erdr->sw_next_to_clean; - - edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &data); -@@ -652,12 +663,13 @@ static void edma_rx_complete(struct edma - (*work_done)++; - drop_count = 0; - } -- if (cleaned_count == EDMA_RX_BUFFER_WRITE) { -+ if (cleaned_count >= EDMA_RX_BUFFER_WRITE) { - /* If buffer clean count reaches 16, we replenish HW buffers. */ - ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id); - edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id), - sw_next_to_clean); - cleaned_count = ret_count; -+ erdr->pending_fill = ret_count; - } - continue; - } -@@ -730,11 +742,12 @@ static void edma_rx_complete(struct edma - adapter->stats.rx_bytes += length; - - /* Check if we reached refill threshold */ -- if (cleaned_count == EDMA_RX_BUFFER_WRITE) { -+ if (cleaned_count >= EDMA_RX_BUFFER_WRITE) { - ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id); - edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id), - sw_next_to_clean); - cleaned_count = ret_count; -+ erdr->pending_fill = ret_count; - } - - /* At this point skb should go to stack */ -@@ -756,11 +769,17 @@ static void edma_rx_complete(struct edma - /* Refill here in case refill threshold wasn't reached */ - if (likely(cleaned_count)) { - ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id); -- if (ret_count) -- dev_dbg(&pdev->dev, "Not all buffers was reallocated"); -+ erdr->pending_fill = ret_count; -+ if (ret_count) { -+ if (net_ratelimit()) -+ dev_dbg(&pdev->dev, "Not all buffers was reallocated"); -+ } -+ - edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id), - erdr->sw_next_to_clean); - } -+ -+ return erdr->pending_fill; - } - - /* edma_delete_rfs_filter() -@@ -2064,6 +2083,7 @@ int edma_poll(struct napi_struct *napi, - u32 shadow_rx_status, shadow_tx_status; - int queue_id; - int i, work_done = 0; -+ u16 rx_pending_fill; - - /* Store the Rx/Tx status by ANDing it with - * appropriate CPU RX?TX mask -@@ -2097,13 +2117,19 @@ int edma_poll(struct napi_struct *napi, - */ - while (edma_percpu_info->rx_status) { - queue_id = ffs(edma_percpu_info->rx_status) - 1; -- edma_rx_complete(edma_cinfo, &work_done, -- budget, queue_id, napi); -+ rx_pending_fill = edma_rx_complete(edma_cinfo, &work_done, -+ budget, queue_id, napi); - -- if (likely(work_done < budget)) -+ if (likely(work_done < budget)) { -+ if (rx_pending_fill) { -+ /* reschedule poll() to refill rx buffer deficit */ -+ work_done = budget; -+ break; -+ } - edma_percpu_info->rx_status &= ~(1 << queue_id); -- else -+ } else { - break; -+ } - } - - /* Clear the status register, to avoid the interrupts to ---- a/drivers/net/ethernet/qualcomm/essedma/edma.h -+++ b/drivers/net/ethernet/qualcomm/essedma/edma.h -@@ -225,6 +225,7 @@ struct edma_ethtool_statistics { - u32 rx_q6_byte; - u32 rx_q7_byte; - u32 tx_desc_error; -+ u32 rx_alloc_fail_ctr; - }; - - struct edma_mdio_data { -@@ -362,6 +363,7 @@ struct edma_rfd_desc_ring { - dma_addr_t dma; /* descriptor ring physical address */ - u16 sw_next_to_fill; /* next descriptor to fill */ - u16 sw_next_to_clean; /* next descriptor to clean */ -+ u16 pending_fill; /* fill pending from previous iteration */ - }; - - /* edma_rfs_flter_node - rfs filter node in hash table */ ---- a/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c -+++ b/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c -@@ -78,6 +78,7 @@ static const struct edma_ethtool_stats e - {"rx_q6_byte", EDMA_STAT(rx_q6_byte)}, - {"rx_q7_byte", EDMA_STAT(rx_q7_byte)}, - {"tx_desc_error", EDMA_STAT(tx_desc_error)}, -+ {"rx_alloc_fail_ctr", EDMA_STAT(rx_alloc_fail_ctr)}, - }; - - #define EDMA_STATS_LEN ARRAY_SIZE(edma_gstrings_stats) diff --git a/target/linux/ipq40xx/patches-4.19/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq40xx/patches-4.19/850-soc-add-qualcomm-syscon.patch deleted file mode 100644 index 7b4eeff5bb..0000000000 --- a/target/linux/ipq40xx/patches-4.19/850-soc-add-qualcomm-syscon.patch +++ /dev/null @@ -1,180 +0,0 @@ -From: Christian Lamparter -Subject: SoC: add qualcomm syscon ---- a/drivers/soc/qcom/Makefile -+++ b/drivers/soc/qcom/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_st - obj-$(CONFIG_QCOM_SMP2P) += smp2p.o - obj-$(CONFIG_QCOM_SMSM) += smsm.o - obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o -+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o - obj-$(CONFIG_QCOM_APR) += apr.o - obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o - obj-$(CONFIG_QCOM_SDM845_LLCC) += llcc-sdm845.o ---- a/drivers/soc/qcom/Kconfig -+++ b/drivers/soc/qcom/Kconfig -@@ -146,6 +146,13 @@ config QCOM_SMSM - Say yes here to support the Qualcomm Shared Memory State Machine. - The state machine is represented by bits in shared memory. - -+config QCOM_TCSR -+ tristate "QCOM Top Control and Status Registers" -+ depends on ARCH_QCOM -+ help -+ Say y here to enable TCSR support. The TCSR provides control -+ functions for various peripherals. -+ - config QCOM_WCNSS_CTRL - tristate "Qualcomm WCNSS control driver" - depends on ARCH_QCOM ---- /dev/null -+++ b/drivers/soc/qcom/qcom_tcsr.c -@@ -0,0 +1,98 @@ -+/* -+ * Copyright (c) 2014, The Linux foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License rev 2 and -+ * only rev 2 as published by the free Software foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define TCSR_USB_PORT_SEL 0xb0 -+#define TCSR_USB_HSPHY_CONFIG 0xC -+ -+#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0 -+#define TCSR_ESS_INTERFACE_SEL_MASK 0xf -+ -+#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0 -+#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4 -+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4 -+ -+static int tcsr_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ const struct device_node *node = pdev->dev.of_node; -+ void __iomem *base; -+ u32 val; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) { -+ dev_err(&pdev->dev, "setting usb port select = %d\n", val); -+ writel(val, base + TCSR_USB_PORT_SEL); -+ } -+ -+ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) { -+ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val); -+ writel(val, base + TCSR_USB_HSPHY_CONFIG); -+ } -+ -+ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) { -+ u32 tmp = 0; -+ dev_info(&pdev->dev, "setting ess interface select = %x\n", val); -+ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET); -+ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK); -+ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK); -+ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET); -+ } -+ -+ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) { -+ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val); -+ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET); -+ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET); -+ } -+ -+ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) { -+ dev_info(&pdev->dev, -+ "setting wifi_noc_memtype_m0_m2 = %x\n", val); -+ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2); -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id tcsr_dt_match[] = { -+ { .compatible = "qcom,tcsr", }, -+ { }, -+}; -+ -+MODULE_DEVICE_TABLE(of, tcsr_dt_match); -+ -+static struct platform_driver tcsr_driver = { -+ .driver = { -+ .name = "tcsr", -+ .owner = THIS_MODULE, -+ .of_match_table = tcsr_dt_match, -+ }, -+ .probe = tcsr_probe, -+}; -+ -+module_platform_driver(tcsr_driver); -+ -+MODULE_AUTHOR("Andy Gross "); -+MODULE_DESCRIPTION("QCOM TCSR driver"); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/include/dt-bindings/soc/qcom,tcsr.h -@@ -0,0 +1,48 @@ -+/* Copyright (c) 2014, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+#ifndef __DT_BINDINGS_QCOM_TCSR_H -+#define __DT_BINDINGS_QCOM_TCSR_H -+ -+#define TCSR_USB_SELECT_USB3_P0 0x1 -+#define TCSR_USB_SELECT_USB3_P1 0x2 -+#define TCSR_USB_SELECT_USB3_DUAL 0x3 -+ -+/* IPQ40xx HS PHY Mode Select */ -+#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7 -+#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7 -+ -+/* IPQ40xx ess interface mode select */ -+#define TCSR_ESS_PSGMII 0 -+#define TCSR_ESS_PSGMII_RGMII5 1 -+#define TCSR_ESS_PSGMII_RMII0 2 -+#define TCSR_ESS_PSGMII_RMII1 4 -+#define TCSR_ESS_PSGMII_RMII0_RMII1 6 -+#define TCSR_ESS_PSGMII_RGMII4 9 -+ -+/* -+ * IPQ40xx WiFi Global Config -+ * Bit 30:AXID_EN -+ * Enable AXI master bus Axid translating to confirm all txn submitted by order -+ * Bit 24: Use locally generated socslv_wxi_bvalid -+ * 1: use locally generate socslv_wxi_bvalid for performance. -+ * 0: use SNOC socslv_wxi_bvalid. -+ */ -+#define TCSR_WIFI_GLB_CFG 0x41000000 -+ -+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */ -+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222 -+ -+/* TCSR A/B REG */ -+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0 -+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1 -+ -+#endif diff --git a/target/linux/ipq40xx/patches-4.19/900-dts-ipq4019-ap-dk01.1.patch b/target/linux/ipq40xx/patches-4.19/900-dts-ipq4019-ap-dk01.1.patch deleted file mode 100644 index 5157079762..0000000000 --- a/target/linux/ipq40xx/patches-4.19/900-dts-ipq4019-ap-dk01.1.patch +++ /dev/null @@ -1,157 +0,0 @@ ---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -@@ -15,6 +15,7 @@ - */ - - #include "qcom-ipq4019.dtsi" -+#include - - / { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1"; -@@ -29,6 +30,32 @@ - }; - - soc { -+ tcsr@194b000 { -+ /* select hostmode */ -+ compatible = "qcom,tcsr"; -+ reg = <0x194b000 0x100>; -+ qcom,usb-hsphy-mode-select = ; -+ status = "okay"; -+ }; -+ -+ ess_tcsr@1953000 { -+ compatible = "qcom,tcsr"; -+ reg = <0x1953000 0x1000>; -+ qcom,ess-interface-select = ; -+ }; -+ -+ tcsr@1949000 { -+ compatible = "qcom,tcsr"; -+ reg = <0x1949000 0x100>; -+ qcom,wifi_glb_cfg = ; -+ }; -+ -+ tcsr@1957000 { -+ compatible = "qcom,tcsr"; -+ reg = <0x1957000 0x100>; -+ qcom,wifi_noc_memtype_m0_m2 = ; -+ }; -+ - rng@22000 { - status = "ok"; - }; -@@ -74,14 +101,6 @@ - pinctrl-names = "default"; - status = "ok"; - cs-gpios = <&tlmm 54 0>; -- -- mx25l25635e@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- reg = <0>; -- compatible = "mx25l25635e"; -- spi-max-frequency = <24000000>; -- }; - }; - - serial@78af000 { -@@ -110,6 +129,22 @@ - status = "ok"; - }; - -+ mdio@90000 { -+ status = "okay"; -+ }; -+ -+ ess-switch@c000000 { -+ status = "okay"; -+ }; -+ -+ ess-psgmii@98000 { -+ status = "okay"; -+ }; -+ -+ edma@c080000 { -+ status = "okay"; -+ }; -+ - usb3_ss_phy: ssphy@9a000 { - status = "okay"; - }; ---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts -+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts -@@ -18,5 +18,73 @@ - - / { - model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1"; -+ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1"; - -+ memory { -+ device_type = "memory"; -+ reg = <0x80000000 0x10000000>; -+ }; -+}; -+ -+&blsp1_spi1 { -+ mx25l25635f@0 { -+ compatible = "mx25l25635f", "jedec,spi-nor"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0>; -+ spi-max-frequency = <24000000>; -+ -+ SBL1@0 { -+ label = "SBL1"; -+ reg = <0x0 0x40000>; -+ read-only; -+ }; -+ MIBIB@40000 { -+ label = "MIBIB"; -+ reg = <0x40000 0x20000>; -+ read-only; -+ }; -+ QSEE@60000 { -+ label = "QSEE"; -+ reg = <0x60000 0x60000>; -+ read-only; -+ }; -+ CDT@c0000 { -+ label = "CDT"; -+ reg = <0xc0000 0x10000>; -+ read-only; -+ }; -+ DDRPARAMS@d0000 { -+ label = "DDRPARAMS"; -+ reg = <0xd0000 0x10000>; -+ read-only; -+ }; -+ APPSBLENV@e0000 { -+ label = "APPSBLENV"; -+ reg = <0xe0000 0x10000>; -+ read-only; -+ }; -+ APPSBL@f0000 { -+ label = "APPSBL"; -+ reg = <0xf0000 0x80000>; -+ read-only; -+ }; -+ ART@170000 { -+ label = "ART"; -+ reg = <0x170000 0x10000>; -+ read-only; -+ }; -+ kernel@180000 { -+ label = "kernel"; -+ reg = <0x180000 0x400000>; -+ }; -+ rootfs@580000 { -+ label = "rootfs"; -+ reg = <0x580000 0x1600000>; -+ }; -+ firmware@180000 { -+ label = "firmware"; -+ reg = <0x180000 0x1a00000>; -+ }; -+ }; - }; diff --git a/target/linux/ipq40xx/patches-4.19/901-arm-boot-add-dts-files.patch b/target/linux/ipq40xx/patches-4.19/901-arm-boot-add-dts-files.patch deleted file mode 100644 index 77c48a36d6..0000000000 --- a/target/linux/ipq40xx/patches-4.19/901-arm-boot-add-dts-files.patch +++ /dev/null @@ -1,62 +0,0 @@ -From a10fab12a927e60b7141a602e740d70cb4d09e4a Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 11:03:18 +0100 -Subject: [PATCH] arm: boot: add dts files - -Signed-off-by: John Crispin ---- - arch/arm/boot/dts/Makefile | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -785,11 +785,49 @@ dtb-$(CONFIG_ARCH_QCOM) += \ - qcom-apq8074-dragonboard.dtb \ - qcom-apq8084-ifc6540.dtb \ - qcom-apq8084-mtp.dtb \ -+ qcom-ipq4018-a42.dtb \ -+ qcom-ipq4018-ap120c-ac.dtb \ -+ qcom-ipq4018-dap-2610.dtb \ -+ qcom-ipq4018-cs-w3-wd1200g-eup.dtb \ -+ qcom-ipq4018-ea6350v3.dtb \ -+ qcom-ipq4018-eap1300.dtb \ -+ qcom-ipq4018-emd1.dtb \ -+ qcom-ipq4018-ens620ext.dtb \ -+ qcom-ipq4018-ex6100v2.dtb \ -+ qcom-ipq4018-ex6150v2.dtb \ -+ qcom-ipq4018-fritzbox-4040.dtb \ -+ qcom-ipq4018-jalapeno.dtb \ -+ qcom-ipq4018-meshpoint-one.dtb \ -+ qcom-ipq4018-nbg6617.dtb \ -+ qcom-ipq4018-rt-ac58u.dtb \ -+ qcom-ipq4018-wre6606.dtb \ - qcom-ipq4019-ap.dk01.1-c1.dtb \ - qcom-ipq4019-ap.dk04.1-c1.dtb \ - qcom-ipq4019-ap.dk04.1-c3.dtb \ - qcom-ipq4019-ap.dk07.1-c1.dtb \ - qcom-ipq4019-ap.dk07.1-c2.dtb \ -+ qcom-ipq4019-a62.dtb \ -+ qcom-ipq4019-cm520-79f.dtb \ -+ qcom-ipq4019-eap2200.dtb \ -+ qcom-ipq4019-fritzbox-7530.dtb \ -+ qcom-ipq4019-fritzrepeater-1200.dtb \ -+ qcom-ipq4019-fritzrepeater-3000.dtb \ -+ qcom-ipq4019-ea8300.dtb \ -+ qcom-ipq4019-habanero-dvk.dtb \ -+ qcom-ipq4019-map-ac2200.dtb \ -+ qcom-ipq4019-e2600ac-c1.dtb \ -+ qcom-ipq4019-e2600ac-c2.dtb \ -+ qcom-ipq4019-rtl30vw.dtb \ -+ qcom-ipq4019-u4019-32m.dtb \ -+ qcom-ipq4019-wpj419.dtb \ -+ qcom-ipq4019-wtr-m2133hp.dtb \ -+ qcom-ipq4028-wpj428.dtb \ -+ qcom-ipq4029-ap-303.dtb \ -+ qcom-ipq4029-ap-303h.dtb \ -+ qcom-ipq4029-ap-365.dtb \ -+ qcom-ipq4029-gl-b1300.dtb \ -+ qcom-ipq4029-gl-s1300.dtb \ -+ qcom-ipq4029-mr33.dtb \ - qcom-ipq8064-ap148.dtb \ - qcom-msm8660-surf.dtb \ - qcom-msm8960-cdp.dtb \ diff --git a/target/linux/ipq40xx/patches-4.19/997-device_tree_cmdline.patch b/target/linux/ipq40xx/patches-4.19/997-device_tree_cmdline.patch deleted file mode 100644 index 7600b0e83f..0000000000 --- a/target/linux/ipq40xx/patches-4.19/997-device_tree_cmdline.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -1090,6 +1090,9 @@ int __init early_init_dt_scan_chosen(uns - p = of_get_flat_dt_prop(node, "bootargs", &l); - if (p != NULL && l > 0) - strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); -+ p = of_get_flat_dt_prop(node, "bootargs-append", &l); -+ if (p != NULL && l > 0) -+ strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); - - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else From 29ca10e537ee807283cfd8a58817270d233a021d Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Mon, 19 Oct 2020 15:37:54 +0200 Subject: [PATCH 11/15] ipq806x: remove support for kernel 4.19 The target uses 5.4 as default kernel since 04/2020. Kernel 4.19 support is not really maintained anymore, and there has been a lot of changes between 4.19 and 5.4 on this target. Despite, new devices are typically added for 5.4 only anyway. Thus, make maintaining of old stuff and reviewing of new stuff easier by removing support for kernel 4.19. Signed-off-by: Adrian Schmutzler --- target/linux/ipq806x/config-4.19 | 506 ------ .../arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 229 --- .../arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 264 --- .../arch/arm/boot/dts/qcom-ipq8064-c2600.dts | 479 ------ .../arch/arm/boot/dts/qcom-ipq8064-d7800.dts | 396 ----- .../arch/arm/boot/dts/qcom-ipq8064-db149.dts | 216 --- .../arch/arm/boot/dts/qcom-ipq8064-ea8500.dts | 389 ----- .../arch/arm/boot/dts/qcom-ipq8064-r7500.dts | 366 ---- .../arm/boot/dts/qcom-ipq8064-r7500v2.dts | 395 ----- .../arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 30 - .../arm/boot/dts/qcom-ipq8064-vr2600v.dts | 402 ----- .../arm/boot/dts/qcom-ipq8064-wg2600hp.dts | 427 ----- .../arch/arm/boot/dts/qcom-ipq8064-wpq864.dts | 563 ------ .../arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts | 520 ------ .../arch/arm/boot/dts/qcom-ipq8064.dtsi | 1512 ----------------- .../arm/boot/dts/qcom-ipq8065-nbg6817.dts | 371 ---- .../arch/arm/boot/dts/qcom-ipq8065-r7800.dts | 531 ------ .../arch/arm/boot/dts/qcom-ipq8065.dtsi | 128 -- .../arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-c2600.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-d7800.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-db149.dts | 0 .../arm/boot/dts/qcom-ipq8064-ea7500-v1.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-ea8500.dts | 0 .../arm/boot/dts/qcom-ipq8064-eax500.dtsi | 0 .../arch/arm/boot/dts/qcom-ipq8064-r7500.dts | 0 .../arm/boot/dts/qcom-ipq8064-r7500v2.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 0 .../arm/boot/dts/qcom-ipq8064-vr2600v.dts | 0 .../arm/boot/dts/qcom-ipq8064-wg2600hp.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-wpq864.dts | 0 .../arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts | 0 .../arm/boot/dts/qcom-ipq8065-nbg6817.dts | 0 .../arch/arm/boot/dts/qcom-ipq8065-r7800.dts | 0 .../arch/arm/boot/dts/qcom-ipq8065.dtsi | 0 .../arm/boot/dts/qcom-ipq8068-ecw5410.dts | 0 ...ings-qcom_adm-Fix-channel-specifiers.patch | 71 - .../0002-dmaengine-Add-ADM-driver.patch | 966 ----------- ...0030-clk-Disable-i2c-device-on-gsbi4.patch | 40 - ...d-add-SMEM-parser-for-QCOM-platforms.patch | 282 --- .../0032-phy-add-qcom-dwc3-phy.patch | 614 ------- ...ically-select-PCI_DOMAINS-if-PCI-is-.patch | 29 - ...Krait-L2-register-accessor-functions.patch | 115 -- ...pport-for-High-Frequency-PLLs-HFPLLs.patch | 324 ---- .../0034-0003-clk-qcom-Add-HFPLL-driver.patch | 142 -- ...t-bindings-clock-Document-qcom-hfpll.patch | 81 - ...lk-qcom-Add-MSM8960-APQ8064-s-HFPLLs.patch | 236 --- ...4-0006-clk-qcom-Add-IPQ806X-s-HFPLLs.patch | 120 -- ...lk-qcom-Add-support-for-Krait-clocks.patch | 213 --- ...008-clk-qcom-Add-KPSS-ACC-GCC-driver.patch | 134 -- ...-bindings-arm-Document-qcom-kpss-gcc.patch | 99 -- ...om-Add-Krait-clock-controller-driver.patch | 409 ----- ...indings-clock-Document-qcom-krait-cc.patch | 55 - ...afe-switch-hook-for-krait-mux-clocks.patch | 152 -- ...-qcm-kyrp_make_Some_variables_static.patch | 25 - ...vmem-Re-organise-kryo-cpufreq-driver.patch | 579 ------- ...om-cpufreq-nvmem-Refactor-the-driver.patch | 241 --- ...mem-Add-support-for-krait-based-socs.patch | 345 ---- ...rt-adjusting-OPP-voltages-at-runtime.patch | 153 -- ...per-to-get-an-opp-regulator-for-devi.patch | 52 - ...e-voltage-tolerance-when-adjusting-t.patch | 47 - .../0053-regulator-add-smb208-support.patch | 55 - ...-dt-Handle-OPP-voltage-adjust-events.patch | 118 -- ...-dt-Add-L2-frequency-scaling-support.patch | 161 -- ...056-cpufreq-dt-Add-missing-rcu-locks.patch | 23 - ...add-fab-scaling-support-with-cpufreq.patch | 243 --- ...le-Add-cpuidle-support-for-QCOM-cpus.patch | 29 - ...arch-arm-force-ZRELADDR-on-arch-qcom.patch | 62 - ...conflicts-with-OpenWrt-auto-mounting.patch | 23 - ...ed-the-enable-regs-and-mask-for-PRNG.patch | 25 - .../0063-1-ipq806x-tsens-driver.patch | 614 ------- ...sens-support-configurable-interrupts.patch | 434 ----- .../0063-3-tsens-fix-kernel-4_19.patch | 20 - .../0063-4-ip806x-tsense-rework-driver.patch | 107 -- .../patches-4.19/0064-clk-clk-rpm-fixes.patch | 95 -- .../0065-arm-override-compiler-flags.patch | 21 - ...Mangle-bootloader-s-kernel-arguments.patch | 189 --- .../0069-arm-boot-add-dts-files.patch | 31 - .../0070-qcom-spm-fix-probe-order.patch | 16 - ...I-qcom-Fixed-IPQ806x-specific-clocks.patch | 93 - ...com-Fixed-IPQ806x-PCIE-reset-changes.patch | 62 - ...qcom-Fixed-IPQ806x-PCIE-init-changes.patch | 124 -- ...rogramming-the-PCIE-iATU-for-IPQ806x.patch | 112 -- .../0071-6-PCI-qcom-Force-GEN1-support.patch | 59 - ...7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch | 69 - ...qcom-Fixed-pcie_phy_clk-branch-issue.patch | 91 - ...nge-duplicate-pci-reset-to-phy-reset.patch | 25 - .../0072-add-ipq806x-with-no-clocks.patch | 12 - ...e-scm_call-to-route-GPIO-irq-to-Apps.patch | 71 - ...Fixed-missing-RGMII-pincontrol-defin.patch | 50 - ...RM-dts-qcom-add-gpio-ranges-property.patch | 70 - .../850-soc-add-qualcomm-syscon.patch | 121 -- 93 files changed, 16473 deletions(-) delete mode 100644 target/linux/ipq806x/config-4.19 delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ap148.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ap161.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-c2600.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-d7800.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-db149.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-r7500.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065-r7800.dts delete mode 100644 target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065.dtsi rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-ap148.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-ap161.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-c2600.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-d7800.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-db149.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-r7500.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8065-r7800.dts (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8065.dtsi (100%) rename target/linux/ipq806x/{files-5.4 => files}/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts (100%) delete mode 100644 target/linux/ipq806x/patches-4.19/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0002-dmaengine-Add-ADM-driver.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0030-clk-Disable-i2c-device-on-gsbi4.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0031-mtd-add-SMEM-parser-for-QCOM-platforms.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0032-phy-add-qcom-dwc3-phy.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0034-0001-ARM-Add-Krait-L2-register-accessor-functions.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0034-0002-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0034-0003-clk-qcom-Add-HFPLL-driver.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0034-0004-dt-bindings-clock-Document-qcom-hfpll.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0034-0005-clk-qcom-Add-MSM8960-APQ8064-s-HFPLLs.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0034-0006-clk-qcom-Add-IPQ806X-s-HFPLLs.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0034-0007-clk-qcom-Add-support-for-Krait-clocks.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0034-0008-clk-qcom-Add-KPSS-ACC-GCC-driver.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0034-0009-dt-bindings-arm-Document-qcom-kpss-gcc.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0034-0010-clk-qcom-Add-Krait-clock-controller-driver.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0034-0011-dt-bindings-clock-Document-qcom-krait-cc.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0034-0012-clk-qcom-Add-safe-switch-hook-for-krait-mux-clocks.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0035-qcom-cpufreq-nvmem-qcm-kyrp_make_Some_variables_static.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0036-qcom-cpufreq-nvmem-Re-organise-kryo-cpufreq-driver.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0037-qcom-cpufreq-nvmem-Refactor-the-driver.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0038-qcom-cpufreq-nvmem-Add-support-for-krait-based-socs.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0049-PM-OPP-Support-adjusting-OPP-voltages-at-runtime.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0051-PM-OPP-Add-a-helper-to-get-an-opp-regulator-for-devi.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0052-PM-OPP-Update-the-voltage-tolerance-when-adjusting-t.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0053-regulator-add-smb208-support.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0054-cpufreq-dt-Handle-OPP-voltage-adjust-events.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0055-cpufreq-dt-Add-L2-frequency-scaling-support.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0056-cpufreq-dt-Add-missing-rcu-locks.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0057-add-fab-scaling-support-with-cpufreq.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0061-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0062-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0063-1-ipq806x-tsens-driver.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0063-2-tsens-support-configurable-interrupts.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0063-3-tsens-fix-kernel-4_19.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0063-4-ip806x-tsense-rework-driver.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0064-clk-clk-rpm-fixes.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0065-arm-override-compiler-flags.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0067-generic-Mangle-bootloader-s-kernel-arguments.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0069-arm-boot-add-dts-files.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0070-qcom-spm-fix-probe-order.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0071-1-PCI-qcom-Fixed-IPQ806x-specific-clocks.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0071-2-PCI-qcom-Fixed-IPQ806x-PCIE-reset-changes.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0071-6-PCI-qcom-Force-GEN1-support.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0071-8-pcie-qcom-Fixed-pcie_phy_clk-branch-issue.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0071-9-pcie-qcom-change-duplicate-pci-reset-to-phy-reset.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0072-add-ipq806x-with-no-clocks.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch delete mode 100644 target/linux/ipq806x/patches-4.19/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch delete mode 100644 target/linux/ipq806x/patches-4.19/080-ARM-dts-qcom-add-gpio-ranges-property.patch delete mode 100644 target/linux/ipq806x/patches-4.19/850-soc-add-qualcomm-syscon.patch diff --git a/target/linux/ipq806x/config-4.19 b/target/linux/ipq806x/config-4.19 deleted file mode 100644 index b21254ed08..0000000000 --- a/target/linux/ipq806x/config-4.19 +++ /dev/null @@ -1,506 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_APQ_GCC_8084 is not set -# CONFIG_APQ_MMCC_8084 is not set -CONFIG_AR8216_PHY=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_KCOV=y -CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_ARCH_HAS_PHYS_TO_DMA=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -# CONFIG_ARCH_MDM9615 is not set -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MSM8960=y -CONFIG_ARCH_MSM8974=y -CONFIG_ARCH_MSM8X60=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARM=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_CPU_SUSPEND=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -# CONFIG_ARM_LPAE is not set -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y -CONFIG_ARM_QCOM_CPUIDLE=y -# CONFIG_ARM_SMMU is not set -# CONFIG_ARM_SP805_WATCHDOG is not set -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ARM_MODULE_PLTS=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_QCOM=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -# CONFIG_CPU_BIG_ENDIAN is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DEV_QCOM_RNG=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEBUG_USER is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -# CONFIG_DWMAC_DWC_QOS_ETH is not set -# CONFIG_DWMAC_GENERIC is not set -CONFIG_DWMAC_IPQ806X=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_SMP=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HIGHMEM=y -# CONFIG_HIGHPTE is not set -CONFIG_HWMON=y -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_QUP=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -# CONFIG_IPQ_GCC_4019 is not set -CONFIG_IPQ_GCC_806X=y -# CONFIG_IPQ_GCC_8074 is not set -# CONFIG_IPQ_LCC_806X is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_KPSS_XCC=y -CONFIG_KRAITCC=y -CONFIG_KRAIT_CLOCKS=y -CONFIG_KRAIT_L2_ACCESSORS=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_GPIO=y -# CONFIG_MDM_GCC_9615 is not set -# CONFIG_MDM_LCC_9615 is not set -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_QCOM_RPM=y -# CONFIG_MFD_SPMI_PMIC is not set -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGHT_HAVE_PCI=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=16 -CONFIG_MMC_QCOM_DML=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_MSM=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -# CONFIG_MMC_TIFM_SD is not set -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MSCC_OCELOT_SWITCH is not set -CONFIG_MSM_GCC_8660=y -# CONFIG_MSM_GCC_8916 is not set -# CONFIG_MSM_GCC_8960 is not set -# CONFIG_MSM_GCC_8974 is not set -# CONFIG_MSM_GCC_8994 is not set -# CONFIG_MSM_GCC_8996 is not set -# CONFIG_MSM_GCC_8998 is not set -# CONFIG_MSM_IOMMU is not set -# CONFIG_MSM_LCC_8960 is not set -# CONFIG_MSM_MMCC_8960 is not set -# CONFIG_MSM_MMCC_8974 is not set -# CONFIG_MSM_MMCC_8996 is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_QCOM=y -CONFIG_MTD_QCOM_SMEM_PARTS=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -# CONFIG_MTD_UBI_FASTMAP is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_HWMON=y -CONFIG_NET_DSA_QCA8K=y -CONFIG_NET_DSA_TAG_QCA=y -# CONFIG_NET_DSA_VITESSE_VSC73XX is not set -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NO_BOOTMEM=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -# CONFIG_PCI_V3_SEMI is not set -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_QCOM=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_QCOM_APQ8064_SATA is not set -# CONFIG_PHY_QCOM_DWC3 is not set -CONFIG_PHY_QCOM_IPQ806X_SATA=y -# CONFIG_PHY_QCOM_QMP is not set -# CONFIG_PHY_QCOM_QUSB2 is not set -# CONFIG_PHY_QCOM_UFS is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_APQ8064 is not set -# CONFIG_PINCTRL_APQ8084 is not set -# CONFIG_PINCTRL_IPQ4019 is not set -CONFIG_PINCTRL_IPQ8064=y -# CONFIG_PINCTRL_IPQ8074 is not set -# CONFIG_PINCTRL_MDM9615 is not set -CONFIG_PINCTRL_MSM=y -# CONFIG_PINCTRL_MSM8660 is not set -# CONFIG_PINCTRL_MSM8916 is not set -# CONFIG_PINCTRL_MSM8960 is not set -# CONFIG_PINCTRL_MSM8994 is not set -# CONFIG_PINCTRL_MSM8996 is not set -# CONFIG_PINCTRL_MSM8998 is not set -# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set -# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set -# CONFIG_PINCTRL_SDM845 is not set -CONFIG_PLUGIN_HOSTCC="g++" -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_MSM=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK=y -# CONFIG_QCOM_A53PLL is not set -CONFIG_QCOM_ADM=y -CONFIG_QCOM_BAM_DMA=y -CONFIG_QCOM_CLK_RPM=y -# CONFIG_QCOM_COMMAND_DB is not set -# CONFIG_QCOM_EBI2 is not set -# CONFIG_QCOM_GENI_SE is not set -CONFIG_QCOM_GSBI=y -CONFIG_QCOM_HFPLL=y -# CONFIG_QCOM_IOMMU is not set -# CONFIG_QCOM_LLCC is not set -# CONFIG_QCOM_PDC is not set -CONFIG_QCOM_PM=y -CONFIG_QCOM_QFPROM=y -# CONFIG_QCOM_RMTFS_MEM is not set -CONFIG_QCOM_RPMCC=y -CONFIG_QCOM_SCM=y -CONFIG_QCOM_SCM_32=y -# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set -CONFIG_QCOM_SMEM=y -# CONFIG_QCOM_SMSM is not set -CONFIG_QCOM_TCSR=y -CONFIG_QCOM_TSENS=y -CONFIG_QCOM_WDT=y -# CONFIG_QRTR is not set -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_REFCOUNT_FULL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_QCOM_RPM=y -# CONFIG_REGULATOR_QCOM_SPMI is not set -CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_QCOM_AOSS is not set -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_CMOS is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -# CONFIG_SDM_DISPCC_845 is not set -# CONFIG_SDM_GCC_845 is not set -# CONFIG_SDM_VIDEOCC_845 is not set -CONFIG_SERIAL_8250_FSL=y -# CONFIG_SERIAL_AMBA_PL011 is not set -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_QUP=y -CONFIG_SPMI=y -CONFIG_SPMI_MSM_PMIC_ARB=y -# CONFIG_SPMI_PMIC_CLKDIV is not set -CONFIG_SRCU=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -# CONFIG_THUMB2_KERNEL is not set -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ap148.dts deleted file mode 100644 index 02f60c90ee..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ /dev/null @@ -1,229 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; - compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - serial0 = &gsbi4_serial; - mdio-gpio0 = &mdio0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - }; - }; -}; - -&qcom_pinmux { - i2c4_pins: i2c4_pinmux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - bias-disable; - }; - - nand_pins: nand_pins { - disable { - pins = "gpio34", "gpio35", "gpio36", - "gpio37", "gpio38"; - function = "nand"; - drive-strength = <10>; - bias-disable; - }; - - pullups { - pins = "gpio39"; - function = "nand"; - drive-strength = <10>; - bias-pull-up; - }; - - hold { - pins = "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "nand"; - drive-strength = <10>; - bias-bus-hold; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&gsbi4 { - qcom,mode = ; - status = "okay"; - - serial@16340000 { - status = "okay"; - }; - - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - flash: m25p80@0 { - compatible = "s25fl256s1"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "qcom,smem"; - }; - }; - }; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - force_gen1 = <1>; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - cs0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "qcom,smem"; - }; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ap161.dts deleted file mode 100644 index de347643dc..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ap161.dts +++ /dev/null @@ -1,264 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm IPQ8064/AP161"; - compatible = "qcom,ipq8064-ap161", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - serial0 = &gsbi4_serial; - mdio-gpio0 = &mdio0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - pinmux@800000 { - i2c4_pins: i2c4_pinmux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - bias-disable; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; - }; - nand_pins: nand_pins { - disable { - pins = "gpio34", "gpio35", "gpio36", - "gpio37", "gpio38"; - function = "nand"; - drive-strength = <10>; - bias-disable; - }; - - pullups { - pins = "gpio39"; - function = "nand"; - drive-strength = <10>; - bias-pull-up; - }; - - hold { - pins = "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "nand"; - drive-strength = <10>; - bias-bus-hold; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio2", "gpio27", "gpio28", - "gpio29", "gpio30", "gpio31", - "gpio32", "gpio51", "gpio52", - "gpio59", "gpio60", "gpio61", - "gpio62" , "gpio66"; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - }; - }; - - gsbi@16300000 { - qcom,mode = ; - status = "okay"; - serial@16340000 { - status = "okay"; - }; - - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ - }; - - gsbi5: gsbi@1a200000 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - flash: m25p80@0 { - compatible = "s25fl256s1"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "qcom,smem"; - }; - }; - }; - }; - - sata-phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - status = "okay"; - }; - - usb3_0: usb3@110f8800 { - status = "okay"; - }; - - usb3_1: usb3@100f8800 { - status = "okay"; - }; - - pcie0: pci@1b500000 { - status = "okay"; - }; - - pcie1: pci@1b700000 { - status = "okay"; - force_gen1 = <1>; - }; - - pcie2: pci@1b900000 { - status = "okay"; - }; - - nand@1ac00000 { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - cs0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "qcom,smem"; - }; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x20080 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - qca,phy-rgmii-en; - qca,txclk-delay-en; - qca,rxclk-delay-en; - }; - - phy3: ethernet-phy@3 { - device_type = "ethernet-phy"; - reg = <3>; - }; - }; - - gmac0: ethernet@37000000 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - gmac1: ethernet@37200000 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - gmac2: ethernet@37400000 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-c2600.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-c2600.dts deleted file mode 100644 index 027500f038..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-c2600.dts +++ /dev/null @@ -1,479 +0,0 @@ -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - model = "TP-Link Archer C2600"; - compatible = "tplink,c2600", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - serial0 = &gsbi4_serial; - mdio-gpio0 = &mdio0; - - led-boot = &power; - led-failsafe = &general; - led-running = &power; - led-upgrade = &general; - label-mac-device = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - pinmux@800000 { - button_pins: button_pins { - mux { - pins = "gpio16", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - i2c4_pins: i2c4_pinmux { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33", - "gpio53", "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - }; - - usb0_pwr_en_pin: usb0_pwr_en_pin { - mux { - pins = "gpio25"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - output-high; - }; - }; - - usb1_pwr_en_pin: usb1_pwr_en_pin { - mux { - pins = "gpio23"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - output-high; - }; - }; - }; - - gsbi@16300000 { - qcom,mode = ; - status = "okay"; - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ - }; - - gsbi5: gsbi@1a200000 { - qcom,mode = ; - status = "okay"; - - spi5: spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash: m25p80@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - MIBIB@20000 { - label = "MIBIB"; - reg = <0x20000 0x20000>; - read-only; - }; - - SBL2@40000 { - label = "SBL2"; - reg = <0x40000 0x20000>; - read-only; - }; - - SBL3@60000 { - label = "SBL3"; - reg = <0x60000 0x30000>; - read-only; - }; - - DDRCONFIG@90000 { - label = "DDRCONFIG"; - reg = <0x90000 0x10000>; - read-only; - }; - - SSD@a0000 { - label = "SSD"; - reg = <0xa0000 0x10000>; - read-only; - }; - - TZ@b0000 { - label = "TZ"; - reg = <0xb0000 0x30000>; - read-only; - }; - - RPM@e0000 { - label = "RPM"; - reg = <0xe0000 0x20000>; - read-only; - }; - - fs-uboot@100000 { - label = "fs-uboot"; - reg = <0x100000 0x70000>; - read-only; - }; - - uboot-env@170000 { - label = "uboot-env"; - reg = <0x170000 0x40000>; - read-only; - }; - - radio@1b0000 { - label = "radio"; - reg = <0x1b0000 0x40000>; - read-only; - }; - - os-image@1f0000 { - label = "os-image"; - reg = <0x1f0000 0x400000>; - }; - - rootfs@5f0000 { - label = "rootfs"; - reg = <0x5f0000 0x1900000>; - }; - - defaultmac: default-mac@1ef0000 { - label = "default-mac"; - reg = <0x1ef0000 0x00200>; - read-only; - }; - - pin@1ef0200 { - label = "pin"; - reg = <0x1ef0200 0x00200>; - read-only; - }; - - product-info@1ef0400 { - label = "product-info"; - reg = <0x1ef0400 0x0fc00>; - read-only; - }; - - partition-table@1f00000 { - label = "partition-table"; - reg = <0x1f00000 0x10000>; - read-only; - }; - - soft-version@1f10000 { - label = "soft-version"; - reg = <0x1f10000 0x10000>; - read-only; - }; - - support-list@1f20000 { - label = "support-list"; - reg = <0x1f20000 0x10000>; - read-only; - }; - - profile@1f30000 { - label = "profile"; - reg = <0x1f30000 0x10000>; - read-only; - }; - - default-config@1f40000 { - label = "default-config"; - reg = <0x1f40000 0x10000>; - read-only; - }; - - user-config@1f50000 { - label = "user-config"; - reg = <0x1f50000 0x40000>; - read-only; - }; - - qos-db@1f90000 { - label = "qos-db"; - reg = <0x1f90000 0x40000>; - read-only; - }; - - usb-config@1fd0000 { - label = "usb-config"; - reg = <0x1fd0000 0x10000>; - read-only; - }; - - log@1fe0000 { - label = "log"; - reg = <0x1fe0000 0x20000>; - read-only; - }; - }; - }; - }; - - usb3_0: usb3@110f8800 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pin>; - pinctrl-names = "default"; - }; - - usb3_1: usb3@100f8800 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pin>; - pinctrl-names = "default"; - }; - - pcie0: pci@1b500000 { - status = "okay"; - }; - - pcie1: pci@1b700000 { - status = "okay"; - force_gen1 = <1>; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - }; - - gmac1: ethernet@37200000 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - mtd-mac-address = <&defaultmac 0x8>; - mtd-mac-address-increment = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - gmac2: ethernet@37400000 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - mtd-mac-address = <&defaultmac 0x8>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ledswitch { - label = "ledswitch"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - lan { - label = "white:lan"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; - }; - - usb4 { - label = "white:usb_4"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb_2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - general: general { - label = "white:general"; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-d7800.dts deleted file mode 100644 index ba4bb9022d..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-d7800.dts +++ /dev/null @@ -1,396 +0,0 @@ -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - model = "Netgear Nighthawk X4 D7800"; - compatible = "netgear,d7800", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0xe000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - serial0 = &gsbi4_serial; - mdio-gpio0 = &mdio0; - - led-boot = &power_white; - led-failsafe = &power_amber; - led-running = &power_white; - led-upgrade = &power_amber; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - stdout-path = "serial0:115200n8"; - }; - - soc { - pinmux@800000 { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - i2c4_pins: i2c4_pinmux { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - nand_pins: nand_pins { - disable { - pins = "gpio34", "gpio35", "gpio36", - "gpio37", "gpio38"; - function = "nand"; - drive-strength = <10>; - bias-disable; - }; - - pullups { - pins = "gpio39"; - function = "nand"; - drive-strength = <10>; - bias-pull-up; - }; - - hold { - pins = "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "nand"; - drive-strength = <10>; - bias-bus-hold; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio16", "gpio68"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - }; - - gsbi@16300000 { - qcom,mode = ; - status = "okay"; - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ - }; - - sata-phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - ports-implemented = <0x1>; - status = "okay"; - }; - - usb3_0: usb3@110f8800 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; - }; - - usb3_1: usb3@100f8800 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; - }; - - pcie0: pci@1b500000 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - }; - - pcie1: pci@1b700000 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - force_gen1 = <1>; - }; - - nand@1ac00000 { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - cs0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art: art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - }; - - artbak: art@1340000 { - label = "artbak"; - reg = <0x1340000 0x0140000>; - read-only; - }; - - kernel@1480000 { - label = "kernel"; - reg = <0x1480000 0x0400000>; - }; - - ubi@1880000 { - label = "ubi"; - reg = <0x1880000 0x1C00000>; - }; - - netgear@3480000 { - label = "netgear"; - reg = <0x3480000 0x4480000>; - read-only; - }; - - reserve@7900000 { - label = "reserve"; - reg = <0x7900000 0x0700000>; - read-only; - }; - }; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - }; - - gmac1: ethernet@37200000 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy4>; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - mtd-mac-address = <&art 6>; - }; - - gmac2: ethernet@37400000 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - mtd-mac-address = <&art 0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - power_white: power_white { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-db149.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-db149.dts deleted file mode 100644 index 35b7e0ea37..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-db149.dts +++ /dev/null @@ -1,216 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm IPQ8064/DB149"; - compatible = "qcom,ipq8064-db149", "qcom,ipq8064"; - - aliases { - serial0 = &gsbi2_serial; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - pinmux@800000 { - i2c4_pins: i2c4_pinmux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - bias-disable; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - rgmii0_pins: rgmii0_pins { - mux { - pins = "gpio2", "gpio66"; - drive-strength = <8>; - bias-disable; - }; - }; - }; - - gsbi2: gsbi@12480000 { - qcom,mode = ; - status = "okay"; - - gsbi2_serial: serial@12490000 { - status = "okay"; - }; - }; - - gsbi5: gsbi@1a200000 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - flash: m25p80@0 { - compatible = "s25fl256s1"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - m25p,fast-read; - - partition@0 { - label = "lowlevel_init"; - reg = <0x0 0x1b0000>; - }; - - partition@1 { - label = "u-boot"; - reg = <0x1b0000 0x80000>; - }; - - partition@2 { - label = "u-boot-env"; - reg = <0x230000 0x40000>; - }; - - partition@3 { - label = "caldata"; - reg = <0x270000 0x40000>; - }; - - partition@4 { - label = "firmware"; - reg = <0x2b0000 0x1d50000>; - }; - }; - }; - }; - - sata-phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - status = "okay"; - }; - - usb3_0: usb3@110f8800 { - status = "okay"; - }; - - usb3_1: usb3@100f8800 { - status = "okay"; - }; - - pcie0: pci@1b500000 { - status = "okay"; - }; - - pcie1: pci@1b700000 { - status = "okay"; - }; - - pcie2: pci@1b900000 { - status = "okay"; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - - phy6: ethernet-phy@6 { - reg = <6>; - }; - - phy7: ethernet-phy@7 { - reg = <7>; - }; - }; - - gmac0: ethernet@37000000 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - phy-handle = <&phy4>; - - pinctrl-0 = <&rgmii0_pins>; - pinctrl-names = "default"; - }; - - gmac1: ethernet@37200000 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - gmac2: ethernet@37400000 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - phy-handle = <&phy6>; - }; - - gmac3: ethernet@37600000 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <3>; - phy-handle = <&phy7>; - }; - }; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts deleted file mode 100644 index 1b8ab36c4f..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts +++ /dev/null @@ -1,389 +0,0 @@ -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - model = "Linksys EA8500 WiFi Router"; - compatible = "linksys,ea8500", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - serial0 = &gsbi4_serial; - mdio-gpio0 = &mdio0; - - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - bootargs = "console=ttyMSM0,115200n8"; - stdout-path = "serial0:115200n8"; - append-rootblock = "ubi.mtd="; /* append to bootargs adding the root deviceblock nbr from bootloader */ - }; - - soc { - pinmux@800000 { - button_pins: button_pins { - mux { - pins = "gpio65", "gpio67", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - i2c4_pins: i2c4_pinmux { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6", "gpio53", "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - nand_pins: nand_pins { - disable { - pins = "gpio34", "gpio35", "gpio36", - "gpio37", "gpio38"; - function = "nand"; - drive-strength = <10>; - bias-disable; - }; - - pullups { - pins = "gpio39"; - function = "nand"; - drive-strength = <10>; - bias-pull-up; - }; - - hold { - pins = "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "nand"; - drive-strength = <10>; - bias-bus-hold; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - }; - }; - - gsbi@16300000 { - qcom,mode = ; - status = "okay"; - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ - }; - - sata-phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - status = "okay"; - }; - - usb3_0: usb3@110f8800 { - status = "okay"; - }; - - usb3_1: usb3@100f8800 { - status = "okay"; - }; - - pcie0: pci@1b500000 { - status = "okay"; - force_gen1 = <1>; - }; - - pcie1: pci@1b700000 { - status = "okay"; - }; - - pcie2: pci@1b900000 { - status = "okay"; - }; - - nand@1ac00000 { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - cs0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - - MIBIB@40000 { - label = "MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - - SBL2@180000 { - label = "SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - - SBL3@2c0000 { - label = "SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - - DDRCONFIG@540000 { - label = "DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - - SSD@660000 { - label = "SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - - TZ@780000 { - label = "TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - - RPM@a00000 { - label = "RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - - art: art@c80000 { - label = "art"; - reg = <0x0c80000 0x0140000>; - read-only; - }; - - APPSBL@dc0000 { - label = "APPSBL"; - reg = <0x0dc0000 0x0100000>; - read-only; - }; - - u_env@ec0000 { - label = "u_env"; - reg = <0x0ec0000 0x0040000>; - }; - - s_env@f00000 { - label = "s_env"; - reg = <0x0f00000 0x0040000>; - }; - - devinfo@f40000 { - label = "devinfo"; - reg = <0x0f40000 0x0040000>; - }; - - linux@f80000 { - label = "kernel1"; - reg = <0x0f80000 0x2800000>; /* 3 MB spill to rootfs*/ - }; - - rootfs@1280000 { - label = "rootfs1"; - reg = <0x1280000 0x2500000>; - }; - - linux2@3780000 { - label = "kernel2"; - reg = <0x3780000 0x2800000>; - }; - - rootfs2@3a80000 { - label = "rootfs2"; - reg = <0x3a80000 0x2500000>; - }; - - syscfg@5f80000 { - label = "syscfg"; - reg = <0x5f80000 0x2080000>; - }; - }; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x00010 0x2613a0 /* PWS_REG */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - }; - - gmac1: ethernet@37200000 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - qcom,phy_mdio_addr = <4>; - qcom,poll_required = <1>; - qcom,rgmii_delay = <0>; - qcom,emulation = <0>; - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - //lan - gmac2: ethernet@37400000 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - qcom,phy_mdio_addr = <0>; /* none */ - qcom,poll_required = <0>; /* no polling */ - qcom,rgmii_delay = <0>; - qcom,emulation = <0>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - adm_dma: dma@18300000 { - status = "okay"; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - wps { - label = "green:wps"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - wifi { - label = "green:wifi"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; - }; - }; -}; - diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-r7500.dts deleted file mode 100644 index 1d6be1288a..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-r7500.dts +++ /dev/null @@ -1,366 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -#include -#include - -/ { - model = "Netgear Nighthawk X4 R7500"; - compatible = "netgear,r7500", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0xe000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - serial0 = &gsbi4_serial; - mdio-gpio0 = &mdio0; - - led-boot = &power_white; - led-failsafe = &power_amber; - led-running = &power_white; - led-upgrade = &power_amber; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - stdout-path = "serial0:115200n8"; - }; - - soc { - pinmux@800000 { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - i2c4_pins: i2c4_pinmux { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - nand_pins: nand_pins { - disable { - pins = "gpio34", "gpio35", "gpio36", - "gpio37", "gpio38"; - function = "nand"; - drive-strength = <10>; - bias-disable; - }; - - pullups { - pins = "gpio39"; - function = "nand"; - drive-strength = <10>; - bias-pull-up; - }; - - hold { - pins = "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "nand"; - drive-strength = <10>; - bias-bus-hold; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - }; - }; - - gsbi@16300000 { - qcom,mode = ; - status = "okay"; - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ - }; - - sata-phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - status = "okay"; - }; - - usb3_0: usb3@110f8800 { - clocks = <&gcc USB30_1_MASTER_CLK>; - status = "okay"; - }; - - usb3_1: usb3@100f8800 { - clocks = <&gcc USB30_0_MASTER_CLK>; - status = "okay"; - }; - - pcie0: pci@1b500000 { - status = "okay"; - }; - - pcie1: pci@1b700000 { - status = "okay"; - force_gen1 = <1>; - }; - - nand@1ac00000 { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - cs0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art: art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - }; - - kernel@1340000 { - label = "kernel"; - reg = <0x1340000 0x0400000>; - }; - - ubi@1740000 { - label = "ubi"; - reg = <0x1740000 0x1600000>; - }; - - netgear@2d40000 { - label = "netgear"; - reg = <0x2d40000 0x0c00000>; - read-only; - }; - - reserve@3940000 { - label = "reserve"; - reg = <0x3940000 0x46c0000>; - read-only; - }; - }; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - }; - - gmac1: ethernet@37200000 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - mtd-mac-address = <&art 6>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - gmac2: ethernet@37400000 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - mtd-mac-address = <&art 0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - power_white: power_white { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&tcsr { - qcom,usb-ctrl-select = ; - compatible = "qcom,tcsr"; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts deleted file mode 100644 index e9d183a8eb..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts +++ /dev/null @@ -1,395 +0,0 @@ -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - model = "Netgear Nighthawk X4 R7500v2"; - compatible = "netgear,r7500v2", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - - rsvd@5fe00000 { - reg = <0x5fe00000 0x200000>; - reusable; - }; - }; - - aliases { - serial0 = &gsbi4_serial; - mdio-gpio0 = &mdio0; - - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - stdout-path = "serial0:115200n8"; - }; - - soc { - pinmux@800000 { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - i2c4_pins: i2c4_pinmux { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - nand_pins: nand_pins { - disable { - pins = "gpio34", "gpio35", "gpio36", - "gpio37", "gpio38"; - function = "nand"; - drive-strength = <10>; - bias-disable; - }; - - pullups { - pins = "gpio39"; - function = "nand"; - drive-strength = <10>; - bias-pull-up; - }; - - hold { - pins = "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "nand"; - drive-strength = <10>; - bias-bus-hold; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio16", "gpio68"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - }; - - gsbi@16300000 { - qcom,mode = ; - status = "okay"; - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ - }; - - sata-phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - status = "okay"; - }; - - usb3_0: usb3@110f8800 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; - }; - - usb3_1: usb3@100f8800 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; - }; - - pcie0: pci@1b500000 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - }; - - pcie1: pci@1b700000 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - force_gen1 = <1>; - }; - - nand@1ac00000 { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - cs0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art: art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - }; - - artbak: art@1340000 { - label = "artbak"; - reg = <0x1340000 0x0140000>; - read-only; - }; - - kernel@1480000 { - label = "kernel"; - reg = <0x1480000 0x0400000>; - }; - - ubi@1880000 { - label = "ubi"; - reg = <0x1880000 0x6080000>; - }; - - reserve@7900000 { - label = "reserve"; - reg = <0x7900000 0x0700000>; - read-only; - }; - }; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - }; - - gmac1: ethernet@37200000 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - mtd-mac-address = <&art 6>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - gmac2: ethernet@37400000 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - mtd-mac-address = <&art 0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb1 { - label = "amber:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb3 { - label = "amber:usb3"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - status { - label = "amber:status"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - internet { - label = "white:internet"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan { - label = "white:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi deleted file mode 100644 index dd272c7fc7..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - soc: soc { - - pcie0: pci@1b500000 { - phy-tx0-term-offset = <0>; - }; - - pcie1: pci@1b700000 { - phy-tx0-term-offset = <0>; - }; - - pcie2: pci@1b900000 { - phy-tx0-term-offset = <0>; - }; - }; -}; - -&ss_phy_0 { - rx_eq = <2>; - tx_deamp_3_5db = <32>; - mpll = <0xa0>; -}; - -&ss_phy_1 { - rx_eq = <2>; - tx_deamp_3_5db = <32>; - mpll = <0xa0>; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts deleted file mode 100644 index 8c171bc2e3..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts +++ /dev/null @@ -1,402 +0,0 @@ -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - model = "TP-Link Archer VR2600v"; - compatible = "tplink,vr2600v", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - serial0 = &gsbi4_serial; - mdio-gpio0 = &mdio0; - - led-boot = &power; - led-failsafe = &general; - led-running = &power; - led-upgrade = &general; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - pinmux@800000 { - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", - "gpio26", "gpio53", "gpio56", "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - i2c4_pins: i2c4_pinmux { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - }; - }; - - gsbi@16300000 { - qcom,mode = ; - status = "okay"; - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ - }; - - gsbi5: gsbi@1a200000 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash: W25Q128@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - MIBIB@20000 { - label = "MIBIB"; - reg = <0x20000 0x20000>; - read-only; - }; - - SBL2@40000 { - label = "SBL2"; - reg = <0x40000 0x40000>; - read-only; - }; - - SBL3@80000 { - label = "SBL3"; - reg = <0x80000 0x80000>; - read-only; - }; - - DDRCONFIG@100000 { - label = "DDRCONFIG"; - reg = <0x100000 0x10000>; - read-only; - }; - - SSD@110000 { - label = "SSD"; - reg = <0x110000 0x10000>; - read-only; - }; - - TZ@120000 { - label = "TZ"; - reg = <0x120000 0x80000>; - read-only; - }; - - RPM@1a0000 { - label = "RPM"; - reg = <0x1a0000 0x80000>; - read-only; - }; - - APPSBL@220000 { - label = "APPSBL"; - reg = <0x220000 0x80000>; - read-only; - }; - - APPSBLENV@2a0000 { - label = "APPSBLENV"; - reg = <0x2a0000 0x40000>; - read-only; - }; - - OLDART@2e0000 { - label = "OLDART"; - reg = <0x2e0000 0x40000>; - read-only; - }; - - kernel@320000 { - label = "kernel"; - reg = <0x320000 0x300000>; - }; - - rootfs@620000 { - label = "rootfs"; - reg = <0x620000 0x960000>; - }; - - defaultmac: default-mac@0xfaf100 { - label = "default-mac"; - reg = <0xfaf100 0x00200>; - read-only; - }; - - ART@fc0000 { - label = "ART"; - reg = <0xfc0000 0x40000>; - read-only; - }; - }; - }; - }; - - usb3_0: usb3@110f8800 { - status = "okay"; - }; - - usb3_1: usb3@100f8800 { - status = "okay"; - }; - - pcie0: pci@1b500000 { - status = "okay"; - }; - - pcie1: pci@1b700000 { - status = "okay"; - force_gen1 = <1>; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - }; - - gmac1: ethernet@37200000 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - mtd-mac-address = <&defaultmac 0>; - mtd-mac-address-increment = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - gmac2: ethernet@37400000 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - mtd-mac-address = <&defaultmac 0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - dect { - label = "dect"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ledswitch { - label = "ledswitch"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - dsl { - label = "white:dsl"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb { - label = "white:usb"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - lan { - label = "white:lan"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wlan2g { - label = "white:wlan2g"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - wlan5g { - label = "white:wlan5g"; - gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - phone { - label = "white:phone"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - wan { - label = "white:wan"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - general: general { - label = "white:general"; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts deleted file mode 100644 index 58b5296878..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts +++ /dev/null @@ -1,427 +0,0 @@ -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - model = "NEC Aterm WG2600HP"; - compatible = "nec,wg2600hp", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - serial0 = &gsbi4_serial; - mdio-gpio0 = &mdio0; - - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x06000000 /* PAD0_MODE */ - 0x0000c 0x00080080 /* PAD6_MODE */ - 0x000e4 0x0006a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x0000004e /* PORT0_STATUS */ - 0x00094 0x0000004e /* PORT6_STATUS */ - >; - }; - - ethernet-phy@4 { - reg = <4>; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - bridge { - label = "bridge"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - - converter { - label = "converter"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - converter_green { - label = "green:converter"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; - }; - - power_red: power_red { - label = "red:power"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - active_green { - label = "green:active"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - active_red { - label = "red:active"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - power_green: power_green { - label = "green:power"; - gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; - }; - - converter_red { - label = "red:converter"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_green { - label = "green:wlan2g"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_red { - label = "red:wlan2g"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - wlan5g_green { - label = "green:wlan5g"; - gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; - }; - - wlan5g_red { - label = "red:wlan5g"; - gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; - }; - - tv_green { - label = "green:tv"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - tv_red { - label = "red:tv"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - mtd-mac-address = <&PRODUCTDATA 6>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - mtd-mac-address = <&PRODUCTDATA 0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi4 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi4_serial { - status = "okay"; -}; - -&gsbi5 { - status = "okay"; - - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - MIBIB@20000 { - label = "MIBIB"; - reg = <0x20000 0x20000>; - read-only; - }; - - SBL2@40000 { - label = "SBL2"; - reg = <0x40000 0x40000>; - read-only; - }; - - SBL3@80000 { - label = "SBL3"; - reg = <0x80000 0x80000>; - read-only; - }; - - DDRCONFIG@100000 { - label = "DDRCONFIG"; - reg = <0x100000 0x10000>; - read-only; - }; - - SSD@110000 { - label = "SSD"; - reg = <0x110000 0x10000>; - read-only; - }; - - TZ@120000 { - label = "TZ"; - reg = <0x120000 0x80000>; - read-only; - }; - - RPM@1a0000 { - label = "RPM"; - reg = <0x1a0000 0x80000>; - read-only; - }; - - APPSBL@220000 { - label = "APPSBL"; - reg = <0x220000 0x80000>; - read-only; - }; - - APPSBLENV@2a0000 { - label = "APPSBLENV"; - reg = <0x2a0000 0x10000>; - }; - - PRODUCTDATA: PRODUCTDATA@2b0000 { - label = "PRODUCTDATA"; - reg = <0x2b0000 0x30000>; - read-only; - }; - - ART@2e0000 { - label = "ART"; - reg = <0x2e0000 0x40000>; - read-only; - }; - - TP@320000 { - label = "TP"; - reg = <0x320000 0x40000>; - read-only; - }; - - TINY@360000 { - label = "TINY"; - reg = <0x360000 0x500000>; - read-only; - }; - - firmware@860000 { - compatible = "denx,uimage"; - label = "firmware"; - reg = <0x860000 0x17a0000>; - }; - }; - }; - }; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - force_gen1 = <1>; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio16", "gpio54", "gpio24", "gpio25"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - i2c4_pins: i2c4_pinmux { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14", - "gpio15", "gpio55", "gpio56", "gpio57", "gpio58", - "gpio64", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - }; - - usb_pwr_en_pins: usb_pwr_en_pins { - mux { - pins = "gpio22"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-high; - }; - }; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts deleted file mode 100644 index 0347cac430..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts +++ /dev/null @@ -1,563 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright (C) 2017 Christian Mehlis - * Copyright (C) 2018 Mathias Kresin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the names of the copyright holders nor the names of any - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "qcom-ipq8064-v1.0.dtsi" - -#include -#include - -/ { - compatible = "compex,wpq864", "qcom,ipq8064"; - model = "Compex WPQ864"; - - aliases { - mdio-gpio0 = &mdio0; - serial0 = &gsbi4_serial; - ethernet0 = &gmac1; - ethernet1 = &gmac0; - - led-boot = &led_pass; - led-failsafe = &led_fail; - led-running = &led_pass; - led-upgrade = &led_pass; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - rpm@108000 { - pinctrl-0 = <&rpm_pins>; - pinctrl-names = "default"; - }; - - nand@1ac00000 { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - mt29f2g08abbeah4@0 { - compatible = "qcom,nandcs"; - - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - - MIBIB@40000 { - label = "MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - - SBL2@180000 { - label = "SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - - SBL3@2c0000 { - label = "SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - - DDRCONFIG@540000 { - label = "DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - - SSD@660000 { - label = "SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - - TZ@780000 { - label = "TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - - RPM@a00000 { - label = "RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - }; - - ART@1200000 { - label = "ART"; - reg = <0x1200000 0x0140000>; - }; - - ubi@1340000 { - label = "ubi"; - reg = <0x1340000 0x4000000>; - }; - - BOOTCONFIG@5340000 { - label = "BOOTCONFIG"; - reg = <0x5340000 0x0060000>; - }; - - SBL2-1@53a0000- { - label = "SBL2_1"; - reg = <0x53a0000 0x0140000>; - read-only; - }; - - SBL3-1@54e0000 { - label = "SBL3_1"; - reg = <0x54e0000 0x0280000>; - read-only; - }; - - DDRCONFIG-1@5760000 { - label = "DDRCONFIG_1"; - reg = <0x5760000 0x0120000>; - read-only; - }; - - SSD-1@5880000 { - label = "SSD_1"; - reg = <0x5880000 0x0120000>; - read-only; - }; - - TZ-1@59a0000 { - label = "TZ_1"; - reg = <0x59a0000 0x0280000>; - read-only; - }; - - RPM-1@5c20000 { - label = "RPM_1"; - reg = <0x5c20000 0x0280000>; - read-only; - }; - - BOOTCONFIG1@5ea0000 { - label = "BOOTCONFIG1"; - reg = <0x5ea0000 0x0060000>; - }; - - APPSBL-1@5f00000 { - label = "APPSBL_1"; - reg = <0x5f00000 0x0500000>; - read-only; - }; - - ubi-1@6400000 { - label = "ubi_1"; - reg = <0x6400000 0x4000000>; - }; - - unused@a400000 { - label = "unused"; - reg = <0xa400000 0x5c00000>; - }; - }; - }; - }; - }; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "virtual,mdio-gpio"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - ethernet-phy@4 { - reg = <4>; - }; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - rss4 { - label = "green:rss4"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - rss3 { - label = "green:rss3"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - rss2 { - label = "orange:rss2"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; - }; - - rss1 { - label = "red:rss1"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - led_pass: pass { - label = "green:pass"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - led_fail: fail { - label = "green:fail"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - usb { - label = "green:usb"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb-pcie { - label = "green:usb-pcie"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - beeper { - compatible = "gpio-beeper"; - - pinctrl-0 = <&beeper_pins>; - pinctrl-names = "default"; - - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&gmac1 { - status = "okay"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi4 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi4_serial { - status = "okay"; - - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&gsbi5 { - status = "okay"; - - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - s25fl256s1@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <50000000>; - }; - }; -}; - -&ss_phy_0 { /* USB3 port 0 SS phy */ - status = "okay"; - - rx_eq = <2>; - tx_deamp_3_5db = <32>; - mpll = <160>; -}; - -&ss_phy_1 { /* USB3 port 1 SS phy */ - status = "okay"; - - rx_eq = <2>; - tx_deamp_3_5db = <32>; - mpll = <160>; -}; - -&pcie0 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; -}; - -&qcom_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - pcie0_pcie2_perst { - pins = "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-high; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", - "gpio23", "gpio24", "gpio25", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - beeper_pins: beeper_pins { - mux { - pins = "gpio55"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - rpm_pins: rpm_pins { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <10>; - bias-disable; - }; - }; - - uart0_pins: uart0_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gsbi4"; - drive-strength = <10>; - bias-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi5"; - drive-strength = <10>; - bias-pull-down; - }; - - clk { - pins = "gpio21"; - function = "gsbi5"; - drive-strength = <12>; - bias-pull-down; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - nand_pins: nand_pins { - disable { - pins = "gpio34", "gpio35", "gpio36", "gpio37", - "gpio38"; - function = "nand"; - drive-strength = <10>; - bias-disable; - }; - - pullups { - pins = "gpio39"; - function = "nand"; - drive-strength = <10>; - bias-pull-up; - }; - - hold { - pins = "gpio40", "gpio41", "gpio42", "gpio43", - "gpio44", "gpio45", "gpio46", "gpio47"; - function = "nand"; - drive-strength = <10>; - bias-bus-hold; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", - "gpio31", "gpio32", "gpio51", "gpio52", - "gpio59", "gpio60", "gpio61", "gpio62"; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - }; -}; - -&usb3_0 { - status = "okay"; -}; - - -&usb3_1 { - status = "okay"; -}; - -&tcsr { - qcom,usb-ctrl-select = ; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts deleted file mode 100644 index 874e54b4a1..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts +++ /dev/null @@ -1,520 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - model = "Buffalo WXR-2533DHP"; - compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064"; - - memory@42000000 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - serial0 = &gsbi4_serial; - - led-boot = &power; - led-failsafe = &diag; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - /* use "ubi_rootfs" volume in "ubi" partition as rootfs */ - bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs"; - stdout-path = "serial0:115200n8"; - }; - - soc { - nand@1ac00000 { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - cs@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - ubi@0 { - label = "ubi"; - reg = <0x0000000 0x4000000>; - }; - - rootfs_1@4000000 { - label = "rootfs_1"; - reg = <0x4000000 0x4000000>; - }; - }; - }; - }; - - mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x07600000 /* PAD0_MODE */ - 0x00008 0x01000000 /* PAD5_MODE */ - 0x0000c 0x00000080 /* PAD6_MODE */ - 0x00050 0xcc35cc35 /* LED_CTRL0 */ - 0x00054 0xca35ca35 /* LED_CTRL1 */ - 0x00058 0xc935c935 /* LED_CTRL2 */ - 0x0005c 0x03ffff00 /* LED_CTRL3 */ - 0x000e4 0x0006a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x0000007e /* PORT0_STATUS */ - 0x00094 0x0000007e /* PORT6_STATUS */ - >; - }; - - ethernet-phy@4 { - reg = <4>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb { - label = "green:usb"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "usbport"; - trigger-sources = <&hub_port0 &hub_port1>; - }; - - guestport { - label = "green:guestport"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - diag: diag { - label = "orange:diag"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - internet_orange { - label = "orange:internet"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - internet_white { - label = "white:internet"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wireless_orange { - label = "orange:wireless"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wireless_white { - label = "white:wireless"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - router_orange { - label = "orange:router"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; - }; - - router_white { - label = "white:router"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - power { - label = "power"; - gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - eject { - label = "eject"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - guest { - label = "guest"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ap { - label = "ap"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - - router { - label = "router"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - - auto { - label = "auto"; - gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - mtd-mac-address = <&ART 6>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - mtd-mac-address = <&ART 0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi4 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi4_serial { - status = "okay"; - - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&gsbi5 { - status = "okay"; - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0 0x10000>; - read-only; - }; - - MIBIB@10000 { - label = "MIBIB"; - reg = <0x10000 0x20000>; - read-only; - }; - - SBL2@30000 { - label = "SBL2"; - reg = <0x30000 0x30000>; - read-only; - }; - - SBL3@60000 { - label = "SBL3"; - reg = <0x60000 0x30000>; - read-only; - }; - - DDRCONFIG@90000 { - label = "DDRCONFIG"; - reg = <0x90000 0x10000>; - read-only; - }; - - SSD@a0000 { - label = "SSD"; - reg = <0xa0000 0x10000>; - read-only; - }; - - TZ@b0000 { - label = "TZ"; - reg = <0xb0000 0x30000>; - read-only; - }; - - RPM@e0000 { - label = "RPM"; - reg = <0xe0000 0x20000>; - read-only; - }; - - APPSBL@100000 { - label = "APPSBL"; - reg = <0x100000 0x70000>; - read-only; - }; - - APPSBLENV@170000 { - label = "APPSBLENV"; - reg = <0x170000 0x10000>; - read-only; - }; - - ART: ART@180000 { - label = "ART"; - reg = <0x180000 0x40000>; - read-only; - }; - - BOOTCONFIG@1c0000 { - label = "BOOTCONFIG"; - reg = <0x1c0000 0x10000>; - read-only; - }; - - APPSBL_1@1d0000 { - label = "APPSBL_1"; - reg = <0x1d0000 0x70000>; - read-only; - }; - }; - }; - }; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&usb3_1 { - status = "okay"; -}; - -&dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; - - hub_port0: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; -}; - -&dwc3_1 { - #address-cells = <1>; - #size-cells = <0>; - - hub_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - force_gen1 = <1>; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio55", "gpio56", "gpio57", - "gpio58", "gpio64", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22", - "gpio23", "gpio24", "gpio25", "gpio26", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - uart0_pins: uart0_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs{ - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - nand_pins: nand_pins { - disable { - pins = "gpio34", "gpio35", "gpio36", - "gpio37", "gpio38"; - function = "nand"; - drive-strength = <10>; - bias-disable; - }; - - pullups { - pins = "gpio39"; - function = "nand"; - drive-strength = <10>; - bias-pull-up; - }; - - hold { - pins = "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "nand"; - drive-strength = <10>; - bias-bus-hold; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - }; - - usb_pwr_en_pins: usb_pwr_en_pins { - mux{ - pins = "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-high; - }; - }; -}; \ No newline at end of file diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi deleted file mode 100644 index a542af7866..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ /dev/null @@ -1,1512 +0,0 @@ -/dts-v1/; - -#include "skeleton.dtsi" -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - model = "Qualcomm IPQ8064"; - compatible = "qcom,ipq8064"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acpu0_aux>; - qcom,saw = <&saw0>; - clocks = <&kraitcc 0>, <&kraitcc 4>; - clock-names = "cpu", "l2"; - clock-latency = <100000>; - cpu-supply = <&smb208_s2a>; - operating-points-v2 = <&opp_table0>; - voltage-tolerance = <5>; - cooling-min-state = <0>; - cooling-max-state = <10>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu1: cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acpu1_aux>; - qcom,saw = <&saw1>; - clocks = <&kraitcc 1>, <&kraitcc 4>; - clock-names = "cpu", "l2"; - clock-latency = <100000>; - cpu-supply = <&smb208_s2b>; - operating-points-v2 = <&opp_table0>; - voltage-tolerance = <5>; - cooling-min-state = <0>; - cooling-max-state = <10>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SPC>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - qcom,saw = <&saw_l2>; - }; - - qcom,l2 { - qcom,l2-rates = <384000000 1000000000 1200000000>; - qcom,l2-cpufreq = <384000000 600000000 1200000000>; - qcom,l2-volt = <1100000 1100000 1150000>; - qcom,l2-supply = <&smb208_s1a>; - }; - - idle-states { - CPU_SPC: spc { - compatible = "qcom,idle-state-spc", - "arm,idle-state"; - status = "okay"; - entry-latency-us = <400>; - exit-latency-us = <900>; - min-residency-us = <3000>; - }; - }; - }; - - opp_table0: opp_table0 { - compatible = "operating-points-v2-qcom-cpu"; - nvmem-cells = <&speedbin_efuse>; - - opp-384000000 { - opp-hz = /bits/ 64 <384000000>; - opp-microvolt-speed0-pvs0-v0 = <1000000>; - opp-microvolt-speed0-pvs1-v0 = <925000>; - opp-microvolt-speed0-pvs2-v0 = <875000>; - opp-microvolt-speed0-pvs3-v0 = <800000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt-speed0-pvs0-v0 = <1050000>; - opp-microvolt-speed0-pvs1-v0 = <975000>; - opp-microvolt-speed0-pvs2-v0 = <925000>; - opp-microvolt-speed0-pvs3-v0 = <850000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - }; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt-speed0-pvs0-v0 = <1100000>; - opp-microvolt-speed0-pvs1-v0 = <1025000>; - opp-microvolt-speed0-pvs2-v0 = <995000>; - opp-microvolt-speed0-pvs3-v0 = <900000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt-speed0-pvs0-v0 = <1150000>; - opp-microvolt-speed0-pvs1-v0 = <1075000>; - opp-microvolt-speed0-pvs2-v0 = <1025000>; - opp-microvolt-speed0-pvs3-v0 = <950000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt-speed0-pvs0-v0 = <1200000>; - opp-microvolt-speed0-pvs1-v0 = <1125000>; - opp-microvolt-speed0-pvs2-v0 = <1075000>; - opp-microvolt-speed0-pvs3-v0 = <1000000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - }; - - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt-speed0-pvs0-v0 = <1250000>; - opp-microvolt-speed0-pvs1-v0 = <1175000>; - opp-microvolt-speed0-pvs2-v0 = <1125000>; - opp-microvolt-speed0-pvs3-v0 = <1050000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - }; - - }; - - thermal-zones { - tsens_tz_sensor0 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 0>; - - trips { - cpu-critical-hi { - temperature = <125000>; - hysteresis = <2000>; - type = "critical_high"; - }; - - cpu-config-hi { - temperature = <105000>; - hysteresis = <2000>; - type = "configurable_hi"; - }; - - cpu-config-lo { - temperature = <95000>; - hysteresis = <2000>; - type = "configurable_lo"; - }; - - cpu-critical-low { - temperature = <0>; - hysteresis = <2000>; - type = "critical_low"; - }; - }; - }; - - tsens_tz_sensor1 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 1>; - - trips { - cpu-critical-hi { - temperature = <125000>; - hysteresis = <2000>; - type = "critical_high"; - }; - - cpu-config-hi { - temperature = <105000>; - hysteresis = <2000>; - type = "configurable_hi"; - }; - - cpu-config-lo { - temperature = <95000>; - hysteresis = <2000>; - type = "configurable_lo"; - }; - - cpu-critical-low { - temperature = <0>; - hysteresis = <2000>; - type = "critical_low"; - }; - }; - }; - - tsens_tz_sensor2 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 2>; - - trips { - cpu-critical-hi { - temperature = <125000>; - hysteresis = <2000>; - type = "critical_high"; - }; - - cpu-config-hi { - temperature = <105000>; - hysteresis = <2000>; - type = "configurable_hi"; - }; - - cpu-config-lo { - temperature = <95000>; - hysteresis = <2000>; - type = "configurable_lo"; - }; - - cpu-critical-low { - temperature = <0>; - hysteresis = <2000>; - type = "critical_low"; - }; - }; - }; - - tsens_tz_sensor3 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 3>; - - trips { - cpu-critical-hi { - temperature = <125000>; - hysteresis = <2000>; - type = "critical_high"; - }; - - cpu-config-hi { - temperature = <105000>; - hysteresis = <2000>; - type = "configurable_hi"; - }; - - cpu-config-lo { - temperature = <95000>; - hysteresis = <2000>; - type = "configurable_lo"; - }; - - cpu-critical-low { - temperature = <0>; - hysteresis = <2000>; - type = "critical_low"; - }; - }; - }; - - tsens_tz_sensor4 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 4>; - - trips { - cpu-critical-hi { - temperature = <125000>; - hysteresis = <2000>; - type = "critical_high"; - }; - - cpu-config-hi { - temperature = <105000>; - hysteresis = <2000>; - type = "configurable_hi"; - }; - - cpu-config-lo { - temperature = <95000>; - hysteresis = <2000>; - type = "configurable_lo"; - }; - - cpu-critical-low { - temperature = <0>; - hysteresis = <2000>; - type = "critical_low"; - }; - }; - }; - - tsens_tz_sensor5 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 5>; - - trips { - cpu-critical-hi { - temperature = <125000>; - hysteresis = <2000>; - type = "critical_high"; - }; - - cpu-config-hi { - temperature = <105000>; - hysteresis = <2000>; - type = "configurable_hi"; - }; - - cpu-config-lo { - temperature = <95000>; - hysteresis = <2000>; - type = "configurable_lo"; - }; - - cpu-critical-low { - temperature = <0>; - hysteresis = <2000>; - type = "critical_low"; - }; - }; - }; - - tsens_tz_sensor6 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 6>; - - trips { - cpu-critical-hi { - temperature = <125000>; - hysteresis = <2000>; - type = "critical_high"; - }; - - cpu-config-hi { - temperature = <105000>; - hysteresis = <2000>; - type = "configurable_hi"; - }; - - cpu-config-lo { - temperature = <95000>; - hysteresis = <2000>; - type = "configurable_lo"; - }; - - cpu-critical-low { - temperature = <0>; - hysteresis = <2000>; - type = "critical_low"; - }; - }; - }; - - tsens_tz_sensor7 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 7>; - - trips { - cpu-critical-hi { - temperature = <125000>; - hysteresis = <2000>; - type = "critical_high"; - }; - - cpu-config-hi { - temperature = <105000>; - hysteresis = <2000>; - type = "configurable_hi"; - }; - - cpu-config-lo { - temperature = <95000>; - hysteresis = <2000>; - type = "configurable_lo"; - }; - - cpu-critical-low { - temperature = <0>; - hysteresis = <2000>; - type = "critical_low"; - }; - }; - }; - - tsens_tz_sensor8 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 8>; - - trips { - cpu-critical-hi { - temperature = <125000>; - hysteresis = <2000>; - type = "critical_high"; - }; - - cpu-config-hi { - temperature = <105000>; - hysteresis = <2000>; - type = "configurable_hi"; - }; - - cpu-config-lo { - temperature = <95000>; - hysteresis = <2000>; - type = "configurable_lo"; - }; - - cpu-critical-low { - temperature = <0>; - hysteresis = <2000>; - type = "critical_low"; - }; - }; - }; - - tsens_tz_sensor9 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 9>; - - trips { - cpu-critical-hi { - temperature = <125000>; - hysteresis = <2000>; - type = "critical_high"; - }; - - cpu-config-hi { - temperature = <105000>; - hysteresis = <2000>; - type = "configurable_hi"; - }; - - cpu-config-lo { - temperature = <95000>; - hysteresis = <2000>; - type = "configurable_lo"; - }; - - cpu-critical-low { - temperature = <0>; - hysteresis = <2000>; - type = "critical_low"; - }; - }; - }; - - tsens_tz_sensor10 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 10>; - - trips { - cpu-critical-hi { - temperature = <125000>; - hysteresis = <2000>; - type = "critical_high"; - }; - - cpu-config-hi { - temperature = <105000>; - hysteresis = <2000>; - type = "configurable_hi"; - }; - - cpu-config-lo { - temperature = <95000>; - hysteresis = <2000>; - type = "configurable_lo"; - }; - - cpu-critical-low { - temperature = <0>; - hysteresis = <2000>; - type = "critical_low"; - }; - }; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = ; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - nss@40000000 { - reg = <0x40000000 0x1000000>; - no-map; - }; - - smem: smem@41000000 { - reg = <0x41000000 0x200000>; - no-map; - }; - }; - - clocks { - cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - }; - - fab-scaling { - compatible = "qcom,fab-scaling"; - clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>; - clock-names = "apps-fab-clk", "ddr-fab-clk"; - fab_freq_high = <533000000>; - fab_freq_nominal = <400000000>; - cpu_freq_threshold = <1000000000>; - }; - - firmware { - scm { - compatible = "qcom,scm-ipq806x"; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - lpass@28100000 { - compatible = "qcom,lpass-cpu"; - status = "disabled"; - clocks = <&lcc AHBIX_CLK>, - <&lcc MI2S_OSR_CLK>, - <&lcc MI2S_BIT_CLK>; - clock-names = "ahbix-clk", - "mi2s-osr-clk", - "mi2s-bit-clk"; - interrupts = ; - interrupt-names = "lpass-irq-lpaif"; - reg = <0x28100000 0x10000>; - reg-names = "lpass-lpaif"; - }; - - qfprom: qfprom@700000 { - compatible = "qcom,qfprom", "syscon"; - reg = <0x700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - status = "okay"; - tsens_calib: calib@400 { - reg = <0x400 0xb>; - }; - tsens_backup: backup@410 { - reg = <0x410 0xb>; - }; - speedbin_efuse: speedbin@0c0 { - reg = <0x0c0 0x4>; - }; - }; - - rpm@108000 { - compatible = "qcom,rpm-ipq8064"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", - "err", - "wakeup"; - - clocks = <&gcc RPM_MSG_RAM_H_CLK>; - clock-names = "ram"; - - #address-cells = <1>; - #size-cells = <0>; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - regulators { - compatible = "qcom,rpm-smb208-regulators"; - - smb208_s1a: s1a { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - - }; - - smb208_s1b: s1b { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2a: s2a { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1250000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2b: s2b { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1250000>; - - qcom,switch-mode-frequency = <1200000>; - }; - }; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - }; - - qcom_pinmux: pinmux@800000 { - compatible = "qcom,ipq8064-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - - pcie0_pins: pcie0_pinmux { - mux { - pins = "gpio3"; - function = "pcie1_rst"; - drive-strength = <12>; - bias-disable; - }; - }; - - pcie1_pins: pcie1_pinmux { - mux { - pins = "gpio48"; - function = "pcie2_rst"; - drive-strength = <12>; - bias-disable; - }; - }; - - pcie2_pins: pcie2_pinmux { - mux { - pins = "gpio63"; - function = "pcie3_rst"; - drive-strength = <12>; - bias-disable; - output-low; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; - }; - - leds_pins: leds_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", - "gpio26", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-low; - }; - }; - - buttons_pins: buttons_pins { - mux { - pins = "gpio54"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-ipq8064", "qcom,msm-timer"; - interrupts = , - , - , - , - ; - reg = <0x0200a000 0x100>; - clock-frequency = <25000000>, - <32768>; - clocks = <&sleep_clk>; - clock-names = "sleep"; - cpu-offset = <0x80000>; - }; - - acpu0_aux: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - clock-output-names = "acpu0_aux"; - }; - - acpu1_aux: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - clock-output-names = "acpu1_aux"; - }; - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; - clock-output-names = "acpu_l2_aux"; - }; - - kraitcc: clock-controller { - compatible = "qcom,krait-cc-v1"; - #clock-cells = <1>; - }; - - saw0: regulator@2089000 { - compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { - compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw_l2: regulator@02012000 { - compatible = "qcom,saw2", "syscon"; - reg = <0x02012000 0x1000>; - regulator; - }; - - sic_non_secure: sic-non-secure@12100000 { - compatible = "syscon"; - reg = <0x12100000 0x10000>; - }; - - gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; - reg = <0x12480000 0x100>; - clocks = <&gcc GSBI2_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi2_serial: serial@12490000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x12490000 0x1000>, - <0x12480000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - }; - - gsbi4: gsbi@16300000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <4>; - reg = <0x16300000 0x100>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi4_serial: serial@16340000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16340000 0x1000>, - <0x16300000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16380000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi5: gsbi@1a200000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x1a200000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi5_serial: serial@1a240000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a240000 0x1000>, - <0x1a200000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@1a280000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - spi@1a280000 { - compatible = "qcom,spi-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi7: gsbi@16600000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <7>; - reg = <0x16600000 0x100>; - clocks = <&gcc GSBI7_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - syscon-tcsr = <&tcsr>; - - gsbi7_serial: serial@16640000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16640000 0x1000>, - <0x16600000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - sata_phy: sata-phy@1b400000 { - compatible = "qcom,ipq806x-sata-phy"; - reg = <0x1b400000 0x200>; - - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - - #phy-cells = <0>; - status = "disabled"; - }; - - sata: sata@29000000 { - compatible = "qcom,ipq806x-ahci", "generic-ahci"; - reg = <0x29000000 0x180>; - - ports-implemented = <0x1>; - - interrupts = ; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_face", "iface", "core", - "rxoob", "pmalive"; - - assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; - - phys = <&sata_phy>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x00500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - tsens: thermal-sensor@900000 { - compatible = "qcom,ipq8064-tsens"; - reg = <0x900000 0x3680>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - interrupts = ; - #thermal-sensor-cells = <1>; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-ipq8064", "syscon"; - reg = <0x1a400000 0x100>; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-ipq8064"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - sfpb_mutex_block: syscon@1200600 { - compatible = "syscon"; - reg = <0x01200600 0x100>; - }; - - hs_phy_0: hs_phy_0 { - compatible = "qcom,dwc3-hs-usb-phy"; - regmap = <&usb3_0>; - clocks = <&gcc USB30_0_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - }; - - ss_phy_0: ss_phy_0 { - compatible = "qcom,dwc3-ss-usb-phy"; - regmap = <&usb3_0>; - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - }; - - usb3_0: usb3@110f8800 { - compatible = "qcom,dwc3", "syscon"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x110f8800 0x8000>; - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "core"; - - ranges; - - resets = <&gcc USB30_0_MASTER_RESET>; - reset-names = "master"; - - status = "disabled"; - - dwc3_0: dwc3@11000000 { - compatible = "snps,dwc3"; - reg = <0x11000000 0xcd00>; - interrupts = ; - phys = <&hs_phy_0>, <&ss_phy_0>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - snps,dis_u3_susphy_quirk; - }; - }; - - hs_phy_1: hs_phy_1 { - compatible = "qcom,dwc3-hs-usb-phy"; - regmap = <&usb3_1>; - clocks = <&gcc USB30_1_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - }; - - ss_phy_1: ss_phy_1 { - compatible = "qcom,dwc3-ss-usb-phy"; - regmap = <&usb3_1>; - clocks = <&gcc USB30_1_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - }; - - usb3_1: usb3@100f8800 { - compatible = "qcom,dwc3", "syscon"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x100f8800 0x8000>; - clocks = <&gcc USB30_1_MASTER_CLK>; - clock-names = "core"; - - ranges; - - resets = <&gcc USB30_1_MASTER_RESET>; - reset-names = "master"; - - status = "disabled"; - - dwc3_1: dwc3@10000000 { - compatible = "snps,dwc3"; - reg = <0x10000000 0xcd00>; - interrupts = ; - phys = <&hs_phy_1>, <&ss_phy_1>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - snps,dis_u3_susphy_quirk; - }; - }; - - pcie0: pci@1b500000 { - compatible = "qcom,pcie-ipq8064"; - reg = <0x1b500000 0x1000 - 0x1b502000 0x80 - 0x1b600000 0x100 - 0x0ff00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ - 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc PCIE_A_CLK>, - <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>, - <&gcc PCIE_AUX_CLK>, - <&gcc PCIE_ALT_REF_CLK>; - clock-names = "core", "iface", "phy", "aux", "ref"; - - assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc PCIE_ACLK_RESET>, - <&gcc PCIE_HCLK_RESET>, - <&gcc PCIE_POR_RESET>, - <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>, - <&gcc PCIE_EXT_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; - - phy-tx0-term-offset = <7>; - - status = "disabled"; - }; - - pcie1: pci@1b700000 { - compatible = "qcom,pcie-ipq8064"; - reg = <0x1b700000 0x1000 - 0x1b702000 0x80 - 0x1b800000 0x100 - 0x31f00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ - 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc PCIE_1_A_CLK>, - <&gcc PCIE_1_H_CLK>, - <&gcc PCIE_1_PHY_CLK>, - <&gcc PCIE_1_AUX_CLK>, - <&gcc PCIE_1_ALT_REF_CLK>; - clock-names = "core", "iface", "phy", "aux", "ref"; - - assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc PCIE_1_ACLK_RESET>, - <&gcc PCIE_1_HCLK_RESET>, - <&gcc PCIE_1_POR_RESET>, - <&gcc PCIE_1_PCI_RESET>, - <&gcc PCIE_1_PHY_RESET>, - <&gcc PCIE_1_EXT_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - - perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; - - phy-tx0-term-offset = <7>; - - status = "disabled"; - }; - - pcie2: pci@1b900000 { - compatible = "qcom,pcie-ipq8064"; - reg = <0x1b900000 0x1000 - 0x1b902000 0x80 - 0x1ba00000 0x100 - 0x35f00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <2>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ - 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc PCIE_2_A_CLK>, - <&gcc PCIE_2_H_CLK>, - <&gcc PCIE_2_PHY_CLK>, - <&gcc PCIE_2_AUX_CLK>, - <&gcc PCIE_2_ALT_REF_CLK>; - clock-names = "core", "iface", "phy", "aux", "ref"; - - assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc PCIE_2_ACLK_RESET>, - <&gcc PCIE_2_HCLK_RESET>, - <&gcc PCIE_2_POR_RESET>, - <&gcc PCIE_2_PCI_RESET>, - <&gcc PCIE_2_PHY_RESET>, - <&gcc PCIE_2_EXT_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - - pinctrl-0 = <&pcie2_pins>; - pinctrl-names = "default"; - - perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; - - phy-tx0-term-offset = <7>; - - status = "disabled"; - }; - - adm_dma: dma@18300000 { - compatible = "qcom,adm"; - reg = <0x18300000 0x100000>; - interrupts = ; - #dma-cells = <1>; - - clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; - clock-names = "core", "iface"; - - resets = <&gcc ADM0_RESET>, - <&gcc ADM0_PBUS_RESET>, - <&gcc ADM0_C0_RESET>, - <&gcc ADM0_C1_RESET>, - <&gcc ADM0_C2_RESET>; - reset-names = "clk", "pbus", "c0", "c1", "c2"; - qcom,ee = <0>; - - status = "disabled"; - }; - - nand: nand@1ac00000 { - compatible = "qcom,ipq806x-nand"; - reg = <0x1ac00000 0x800>; - - clocks = <&gcc EBI2_CLK>, - <&gcc EBI2_AON_CLK>; - clock-names = "core", "aon"; - - dmas = <&adm_dma 3>; - dma-names = "rxtx"; - qcom,cmd-crci = <15>; - qcom,data-crci = <3>; - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - nss_common: syscon@03000000 { - compatible = "syscon"; - reg = <0x03000000 0x0000FFFF>; - }; - - qsgmii_csr: syscon@1bb00000 { - compatible = "syscon"; - reg = <0x1bb00000 0x000001FF>; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <7>; - snps,rd_osr_lmt = <7>; - snps,blen = <16 0 0 0 0 0 0>; - }; - - gmac0: ethernet@37000000 { - device_type = "network"; - compatible = "qcom,ipq806x-gmac"; - reg = <0x37000000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; - - snps,axi-config = <&stmmac_axi_setup>; - snps,pbl = <32>; - snps,aal = <1>; - - qcom,nss-common = <&nss_common>; - qcom,qsgmii-csr = <&qsgmii_csr>; - - clocks = <&gcc GMAC_CORE1_CLK>; - clock-names = "stmmaceth"; - - resets = <&gcc GMAC_CORE1_RESET>; - reset-names = "stmmaceth"; - - status = "disabled"; - }; - - gmac1: ethernet@37200000 { - device_type = "network"; - compatible = "qcom,ipq806x-gmac"; - reg = <0x37200000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; - - snps,axi-config = <&stmmac_axi_setup>; - snps,pbl = <32>; - snps,aal = <1>; - - qcom,nss-common = <&nss_common>; - qcom,qsgmii-csr = <&qsgmii_csr>; - - clocks = <&gcc GMAC_CORE2_CLK>; - clock-names = "stmmaceth"; - - resets = <&gcc GMAC_CORE2_RESET>; - reset-names = "stmmaceth"; - - status = "disabled"; - }; - - gmac2: ethernet@37400000 { - device_type = "network"; - compatible = "qcom,ipq806x-gmac"; - reg = <0x37400000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; - - snps,axi-config = <&stmmac_axi_setup>; - snps,pbl = <32>; - snps,aal = <1>; - - qcom,nss-common = <&nss_common>; - qcom,qsgmii-csr = <&qsgmii_csr>; - - clocks = <&gcc GMAC_CORE3_CLK>; - clock-names = "stmmaceth"; - - resets = <&gcc GMAC_CORE3_RESET>; - reset-names = "stmmaceth"; - - status = "disabled"; - }; - - gmac3: ethernet@37600000 { - device_type = "network"; - compatible = "qcom,ipq806x-gmac"; - reg = <0x37600000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; - - snps,axi-config = <&stmmac_axi_setup>; - snps,pbl = <32>; - snps,aal = <1>; - - qcom,nss-common = <&nss_common>; - qcom,qsgmii-csr = <&qsgmii_csr>; - - clocks = <&gcc GMAC_CORE4_CLK>; - clock-names = "stmmaceth"; - - resets = <&gcc GMAC_CORE4_RESET>; - reset-names = "stmmaceth"; - - status = "disabled"; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sdcc1bam:dma@12402000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12402000 0x8000>; - interrupts = ; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc3bam:dma@12182000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x8000>; - interrupts = ; - clocks = <&gcc SDC3_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc3: sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - #mmc-ddr-1_8v; - sd-uhs-sdr104; - sd-uhs-ddr50; - vqmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; - dma-names = "tx", "rx"; - }; - }; - }; - - sfpb_mutex: sfpb-mutex { - compatible = "qcom,sfpb-mutex"; - syscon = <&sfpb_mutex_block 4 4>; - - #hwlock-cells = <1>; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem>; - hwlocks = <&sfpb_mutex 3>; - }; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts deleted file mode 100644 index 2cff2f65bc..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts +++ /dev/null @@ -1,371 +0,0 @@ -#include "qcom-ipq8065.dtsi" - -#include - -/ { - model = "ZyXEL NBG6817"; - compatible = "zyxel,nbg6817", "qcom,ipq8065", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - serial0 = &gsbi4_serial; - mdio-gpio0 = &mdio0; - sdcc1 = &sdcc1; - - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd"; - stdout-path = "serial0:115200n8"; - append-rootblock = "root=/dev/mmcblk0p"; - }; - - soc { - pinmux@800000 { - button_pins: button_pins { - mux { - pins = "gpio53", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - i2c4_pins: i2c4_pinmux { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio9", "gpio26", "gpio33", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - - clk { - pins = "gpio1"; - input-disable; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - - tx { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ; - input-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; - - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio16", "gpio17"; - function = "gpio"; - drive-strength = <12>; - }; - - pwr { - pins = "gpio17"; - bias-pull-down; - output-high; - }; - - ovc { - pins = "gpio16"; - bias-pull-up; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio14", "gpio15"; - function = "gpio"; - drive-strength = <12>; - }; - - pwr { - pins = "gpio14"; - bias-pull-down; - output-high; - }; - - ovc { - pins = "gpio15"; - bias-pull-up; - }; - }; - }; - - gsbi@16300000 { - qcom,mode = ; - status = "okay"; - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ - }; - - gsbi5: gsbi@1a200000 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash: m25p80@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <51200000>; - reg = <0>; - - partitions { - compatible = "qcom,smem"; - }; - }; - }; - }; - - usb3_0: usb3@110f8800 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; - }; - - usb3_1: usb3@100f8800 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; - }; - - pcie0: pci@1b500000 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - }; - - pcie1: pci@1b700000 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - force_gen1 = <1>; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */ - 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */ - 0x00978 0x19008643 /* QM_PORT1_CTRL0 */ - 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */ - 0x00980 0x19008643 /* QM_PORT2_CTRL0 */ - 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */ - 0x00988 0x19008643 /* QM_PORT3_CTRL0 */ - 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */ - 0x00990 0x19008643 /* QM_PORT4_CTRL0 */ - 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */ - 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */ - 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */ - 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */ - 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - qca,ar8327-initvals = < - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x0000c 0x80 /* PAD6_MODE */ - >; - }; - }; - - gmac1: ethernet@37200000 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - qcom,phy_mdio_addr = <4>; - qcom,poll_required = <0>; - qcom,rgmii_delay = <1>; - qcom,phy_mii_type = <0>; - qcom,emulation = <0>; - qcom,irq = <255>; - mdiobus = <&mdio0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - gmac2: ethernet@37400000 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - qcom,phy_mdio_addr = <0>; /* none */ - qcom,poll_required = <0>; /* no polling */ - qcom,rgmii_delay = <0>; - qcom,phy_mii_type = <1>; - qcom,emulation = <0>; - qcom,irq = <258>; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - amba { - sdcc1: sdcc@12400000 { - status = "okay"; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - internet { - label = "white:internet"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi2g { - label = "amber:wifi2g"; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; - }; - - /* wifi2g amber from the manual is missing */ - - wifi5g { - label = "amber:wifi5g"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - /* wifi5g amber from the manual is missing */ - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065-r7800.dts b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065-r7800.dts deleted file mode 100644 index 50ffcdab07..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065-r7800.dts +++ /dev/null @@ -1,531 +0,0 @@ -#include "qcom-ipq8065.dtsi" - -#include - -/ { - model = "Netgear Nighthawk X4S R7800"; - compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - - rsvd@5fe00000 { - reg = <0x5fe00000 0x200000>; - reusable; - }; - }; - - aliases { - serial0 = &gsbi4_serial; - mdio-gpio0 = &mdio0; - - led-boot = &power_white; - led-failsafe = &power_amber; - led-running = &power_white; - led-upgrade = &power_amber; - label-mac-device = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - pinmux@800000 { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - i2c4_pins: i2c4_pinmux { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - led_pins: led_pins { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - nand_pins: nand_pins { - disable { - pins = "gpio34", "gpio35", "gpio36", - "gpio37", "gpio38"; - function = "nand"; - drive-strength = <10>; - bias-disable; - }; - - pullups { - pins = "gpio39"; - function = "nand"; - drive-strength = <10>; - bias-pull-up; - }; - - hold { - pins = "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "nand"; - drive-strength = <10>; - bias-bus-hold; - }; - }; - - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - - clk { - pins = "gpio1"; - input-disable; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - - tx { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ; - input-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - spi6_pins: spi6_pins { - mux { - pins = "gpio55", "gpio56", "gpio58"; - function = "gsbi6"; - bias-pull-down; - }; - - mosi { - pins = "gpio55"; - drive-strength = <12>; - }; - - miso { - pins = "gpio56"; - drive-strength = <14>; - }; - - cs { - pins = "gpio57"; - drive-strength = <12>; - bias-pull-up; - }; - - clk { - pins = "gpio58"; - drive-strength = <12>; - }; - - reset { - pins = "gpio33"; - drive-strength = <10>; - bias-pull-down; - output-high; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio16", "gpio68"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - }; - - gsbi@16300000 { - qcom,mode = ; - status = "okay"; - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ - }; - - sata-phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - ports-implemented = <0x1>; - status = "okay"; - }; - - usb3_0: usb3@110f8800 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; - }; - - usb3_1: usb3@100f8800 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; - }; - - pcie0: pci@1b500000 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - - mtd-mac-address = <&art 6>; - mtd-mac-address-increment = <(1)>; - }; - }; - }; - - pcie1: pci@1b700000 { - status = "okay"; - force_gen1 = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - - mtd-mac-address = <&art 6>; - mtd-mac-address-increment = <(2)>; - }; - }; - }; - - nand@1ac00000 { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - cs0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art: art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - }; - - artbak: art@1340000 { - label = "artbak"; - reg = <0x1340000 0x0140000>; - read-only; - }; - - kernel@1480000 { - label = "kernel"; - reg = <0x1480000 0x0400000>; - }; - - ubi@1880000 { - label = "ubi"; - reg = <0x1880000 0x6080000>; - }; - - reserve@7900000 { - label = "reserve"; - reg = <0x7900000 0x0700000>; - read-only; - }; - }; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */ - 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */ - 0x00978 0x19008643 /* QM_PORT1_CTRL0 */ - 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */ - 0x00980 0x19008643 /* QM_PORT2_CTRL0 */ - 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */ - 0x00988 0x19008643 /* QM_PORT3_CTRL0 */ - 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */ - 0x00990 0x19008643 /* QM_PORT4_CTRL0 */ - 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */ - 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */ - 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */ - 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */ - 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */ - >; - qca,ar8327-vlans = < - 0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */ - 0x2 0x21 /* VLAN2 Ports 0/5 */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - qca,ar8327-initvals = < - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x0000c 0x80 /* PAD6_MODE */ - >; - }; - }; - - gmac1: ethernet@37200000 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - qcom,phy_mdio_addr = <4>; - qcom,poll_required = <0>; - qcom,rgmii_delay = <1>; - qcom,phy_mii_type = <0>; - qcom,emulation = <0>; - qcom,irq = <255>; - mdiobus = <&mdio0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - mtd-mac-address = <&art 6>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - gmac2: ethernet@37400000 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - qcom,phy_mdio_addr = <0>; /* none */ - qcom,poll_required = <0>; /* no polling */ - qcom,rgmii_delay = <0>; - qcom,phy_mii_type = <1>; - qcom,emulation = <0>; - qcom,irq = <258>; - mdiobus = <&mdio0>; - - mtd-mac-address = <&art 0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - power_white: power_white { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065.dtsi b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065.dtsi deleted file mode 100644 index fdd4697887..0000000000 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -#include "qcom-ipq8064-v2.0.dtsi" - -/ { - model = "Qualcomm IPQ8065"; - compatible = "qcom,ipq8065", "qcom,ipq8064"; - - soc: soc { - - rpm@108000 { - - regulators { - - smb208_s2a: s2a { - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1275000>; - }; - - smb208_s2b: s2b { - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1275000>; - }; - }; - }; - }; - - cpus { - qcom,l2 { - qcom,l2-cpufreq = <384000000 600000000 1400000000>; - }; - - idle-states { - CPU_SPC: spc { - status = "disabled"; - }; - }; - }; -}; - -&opp_table0 { - compatible = "operating-points-v2-qcom-cpu"; - nvmem-cells = <&speedbin_efuse>; - - /* - * On ipq8065 1.2 ghz freq is not present - * Remove it to make cpufreq work and not - * complain for missing definition - */ - - /delete-node/opp-1200000000; - - opp-384000000 { - opp-hz = /bits/ 64 <384000000>; - opp-microvolt-speed0-pvs0-v0 = <975000>; - opp-microvolt-speed0-pvs1-v0 = <950000>; - opp-microvolt-speed0-pvs2-v0 = <925000>; - opp-microvolt-speed0-pvs3-v0 = <900000>; - opp-microvolt-speed0-pvs4-v0 = <875000>; - opp-microvolt-speed0-pvs5-v0 = <825000>; - opp-microvolt-speed0-pvs6-v0 = <775000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt-speed0-pvs0-v0 = <1000000>; - opp-microvolt-speed0-pvs1-v0 = <975000>; - opp-microvolt-speed0-pvs2-v0 = <950000>; - opp-microvolt-speed0-pvs3-v0 = <925000>; - opp-microvolt-speed0-pvs4-v0 = <900000>; - opp-microvolt-speed0-pvs5-v0 = <850000>; - opp-microvolt-speed0-pvs6-v0 = <800000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - }; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt-speed0-pvs0-v0 = <1050000>; - opp-microvolt-speed0-pvs1-v0 = <1025000>; - opp-microvolt-speed0-pvs2-v0 = <1000000>; - opp-microvolt-speed0-pvs3-v0 = <975000>; - opp-microvolt-speed0-pvs4-v0 = <950000>; - opp-microvolt-speed0-pvs5-v0 = <900000>; - opp-microvolt-speed0-pvs6-v0 = <850000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt-speed0-pvs0-v0 = <1100000>; - opp-microvolt-speed0-pvs1-v0 = <1075000>; - opp-microvolt-speed0-pvs2-v0 = <1050000>; - opp-microvolt-speed0-pvs3-v0 = <1025000>; - opp-microvolt-speed0-pvs4-v0 = <1000000>; - opp-microvolt-speed0-pvs5-v0 = <950000>; - opp-microvolt-speed0-pvs6-v0 = <900000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - }; - - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt-speed0-pvs0-v0 = <1175000>; - opp-microvolt-speed0-pvs1-v0 = <1150000>; - opp-microvolt-speed0-pvs2-v0 = <1125000>; - opp-microvolt-speed0-pvs3-v0 = <1100000>; - opp-microvolt-speed0-pvs4-v0 = <1075000>; - opp-microvolt-speed0-pvs5-v0 = <1025000>; - opp-microvolt-speed0-pvs6-v0 = <975000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - }; - - opp-1725000000 { - opp-hz = /bits/ 64 <1725000000>; - opp-microvolt-speed0-pvs0-v0 = <1262500>; - opp-microvolt-speed0-pvs1-v0 = <1225000>; - opp-microvolt-speed0-pvs2-v0 = <1200000>; - opp-microvolt-speed0-pvs3-v0 = <1175000>; - opp-microvolt-speed0-pvs4-v0 = <1150000>; - opp-microvolt-speed0-pvs5-v0 = <1100000>; - opp-microvolt-speed0-pvs6-v0 = <1050000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - }; -}; diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap148.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-ap148.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap148.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap161.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-ap161.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap161.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-c2600.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-c2600.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-d7800.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-db149.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-db149.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-db149.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-db149.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-r7500.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8065-r7800.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8065-r7800.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8065.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8065.dtsi rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi diff --git a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts similarity index 100% rename from target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts diff --git a/target/linux/ipq806x/patches-4.19/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch b/target/linux/ipq806x/patches-4.19/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch deleted file mode 100644 index 83d7bbc6f4..0000000000 --- a/target/linux/ipq806x/patches-4.19/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 28d0ed88f536dd639adf1b0c7c08e04be3c8f294 Mon Sep 17 00:00:00 2001 -From: Thomas Pedersen -Date: Mon, 16 May 2016 17:58:50 -0700 -Subject: [PATCH 01/69] dtbindings: qcom_adm: Fix channel specifiers - -Original patch from Andy Gross. - -This patch removes the crci information from the dma -channel property. At least one client device requires -using more than one CRCI value for a channel. This does -not match the current binding and the crci information -needs to be removed. - -Instead, the client device will provide this information -via other means. - -Signed-off-by: Andy Gross -Signed-off-by: Thomas Pedersen ---- - Documentation/devicetree/bindings/dma/qcom_adm.txt | 16 ++++++---------- - 1 file changed, 6 insertions(+), 10 deletions(-) - ---- a/Documentation/devicetree/bindings/dma/qcom_adm.txt -+++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt -@@ -4,8 +4,7 @@ Required properties: - - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960 - - reg: Address range for DMA registers - - interrupts: Should contain one interrupt shared by all channels --- #dma-cells: must be <2>. First cell denotes the channel number. Second cell -- denotes CRCI (client rate control interface) flow control assignment. -+- #dma-cells: must be <1>. First cell denotes the channel number. - - clocks: Should contain the core clock and interface clock. - - clock-names: Must contain "core" for the core clock and "iface" for the - interface clock. -@@ -22,7 +21,7 @@ Example: - compatible = "qcom,adm"; - reg = <0x18300000 0x100000>; - interrupts = <0 170 0>; -- #dma-cells = <2>; -+ #dma-cells = <1>; - - clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; - clock-names = "core", "iface"; -@@ -35,15 +34,12 @@ Example: - qcom,ee = <0>; - }; - --DMA clients must use the format descripted in the dma.txt file, using a three -+DMA clients must use the format descripted in the dma.txt file, using a two - cell specifier for each channel. - --Each dmas request consists of 3 cells: -+Each dmas request consists of two cells: - 1. phandle pointing to the DMA controller - 2. channel number -- 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0. -- The CRCI is used for flow control. It identifies the peripheral device that -- is the source/destination for the transferred data. - - Example: - -@@ -55,7 +51,7 @@ Example: - - cs-gpios = <&qcom_pinmux 20 0>; - -- dmas = <&adm_dma 6 9>, -- <&adm_dma 5 10>; -+ dmas = <&adm_dma 6>, -+ <&adm_dma 5>; - dma-names = "rx", "tx"; - }; diff --git a/target/linux/ipq806x/patches-4.19/0002-dmaengine-Add-ADM-driver.patch b/target/linux/ipq806x/patches-4.19/0002-dmaengine-Add-ADM-driver.patch deleted file mode 100644 index fedb8ed798..0000000000 --- a/target/linux/ipq806x/patches-4.19/0002-dmaengine-Add-ADM-driver.patch +++ /dev/null @@ -1,966 +0,0 @@ -From 563fa24db4e529c5a3311928d73a8a90531ee527 Mon Sep 17 00:00:00 2001 -From: Thomas Pedersen -Date: Mon, 16 May 2016 17:58:51 -0700 -Subject: [PATCH 02/69] dmaengine: Add ADM driver - -Original patch by Andy Gross. - -Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA -controller found in the MSM8x60 and IPQ/APQ8064 platforms. - -The ADM supports both memory to memory transactions and memory -to/from peripheral device transactions. The controller also provides flow -control capabilities for transactions to/from peripheral devices. - -The initial release of this driver supports slave transfers to/from peripherals -and also incorporates CRCI (client rate control interface) flow control. - -Signed-off-by: Andy Gross -Signed-off-by: Thomas Pedersen ---- - drivers/dma/qcom/Kconfig | 10 + - drivers/dma/qcom/Makefile | 1 + - drivers/dma/qcom/qcom_adm.c | 900 ++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 911 insertions(+) - create mode 100644 drivers/dma/qcom/qcom_adm.c - ---- a/drivers/dma/qcom/Kconfig -+++ b/drivers/dma/qcom/Kconfig -@@ -27,3 +27,13 @@ config QCOM_HIDMA - (user to kernel, kernel to kernel, etc.). It only supports - memcpy interface. The core is not intended for general - purpose slave DMA. -+ -+config QCOM_ADM -+ tristate "Qualcomm ADM support" -+ depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM) -+ select DMA_ENGINE -+ select DMA_VIRTUAL_CHANNELS -+ ---help--- -+ Enable support for the Qualcomm ADM DMA controller. This controller -+ provides DMA capabilities for both general purpose and on-chip -+ peripheral devices. ---- a/drivers/dma/qcom/Makefile -+++ b/drivers/dma/qcom/Makefile -@@ -4,3 +4,4 @@ obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mg - hdma_mgmt-objs := hidma_mgmt.o hidma_mgmt_sys.o - obj-$(CONFIG_QCOM_HIDMA) += hdma.o - hdma-objs := hidma_ll.o hidma.o hidma_dbg.o -+obj-$(CONFIG_QCOM_ADM) += qcom_adm.o ---- /dev/null -+++ b/drivers/dma/qcom/qcom_adm.c -@@ -0,0 +1,914 @@ -+/* -+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../dmaengine.h" -+#include "../virt-dma.h" -+ -+/* ADM registers - calculated from channel number and security domain */ -+#define ADM_CHAN_MULTI 0x4 -+#define ADM_CI_MULTI 0x4 -+#define ADM_CRCI_MULTI 0x4 -+#define ADM_EE_MULTI 0x800 -+#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * chan) -+#define ADM_EE_OFFS(ee) (ADM_EE_MULTI * ee) -+#define ADM_CHAN_EE_OFFS(chan, ee) (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee)) -+#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * chan) -+#define ADM_CI_OFFS(ci) (ADM_CHAN_OFF(ci)) -+#define ADM_CH_CMD_PTR(chan, ee) (ADM_CHAN_EE_OFFS(chan, ee)) -+#define ADM_CH_RSLT(chan, ee) (0x40 + ADM_CHAN_EE_OFFS(chan, ee)) -+#define ADM_CH_FLUSH_STATE0(chan, ee) (0x80 + ADM_CHAN_EE_OFFS(chan, ee)) -+#define ADM_CH_STATUS_SD(chan, ee) (0x200 + ADM_CHAN_EE_OFFS(chan, ee)) -+#define ADM_CH_CONF(chan) (0x240 + ADM_CHAN_OFFS(chan)) -+#define ADM_CH_RSLT_CONF(chan, ee) (0x300 + ADM_CHAN_EE_OFFS(chan, ee)) -+#define ADM_SEC_DOMAIN_IRQ_STATUS(ee) (0x380 + ADM_EE_OFFS(ee)) -+#define ADM_CI_CONF(ci) (0x390 + ci * ADM_CI_MULTI) -+#define ADM_GP_CTL 0x3d8 -+#define ADM_CRCI_CTL(crci, ee) (0x400 + crci * ADM_CRCI_MULTI + \ -+ ADM_EE_OFFS(ee)) -+ -+/* channel status */ -+#define ADM_CH_STATUS_VALID BIT(1) -+ -+/* channel result */ -+#define ADM_CH_RSLT_VALID BIT(31) -+#define ADM_CH_RSLT_ERR BIT(3) -+#define ADM_CH_RSLT_FLUSH BIT(2) -+#define ADM_CH_RSLT_TPD BIT(1) -+ -+/* channel conf */ -+#define ADM_CH_CONF_SHADOW_EN BIT(12) -+#define ADM_CH_CONF_MPU_DISABLE BIT(11) -+#define ADM_CH_CONF_PERM_MPU_CONF BIT(9) -+#define ADM_CH_CONF_FORCE_RSLT_EN BIT(7) -+#define ADM_CH_CONF_SEC_DOMAIN(ee) (((ee & 0x3) << 4) | ((ee & 0x4) << 11)) -+ -+/* channel result conf */ -+#define ADM_CH_RSLT_CONF_FLUSH_EN BIT(1) -+#define ADM_CH_RSLT_CONF_IRQ_EN BIT(0) -+ -+/* CRCI CTL */ -+#define ADM_CRCI_CTL_MUX_SEL BIT(18) -+#define ADM_CRCI_CTL_RST BIT(17) -+ -+/* CI configuration */ -+#define ADM_CI_RANGE_END(x) (x << 24) -+#define ADM_CI_RANGE_START(x) (x << 16) -+#define ADM_CI_BURST_4_WORDS BIT(2) -+#define ADM_CI_BURST_8_WORDS BIT(3) -+ -+/* GP CTL */ -+#define ADM_GP_CTL_LP_EN BIT(12) -+#define ADM_GP_CTL_LP_CNT(x) (x << 8) -+ -+/* Command pointer list entry */ -+#define ADM_CPLE_LP BIT(31) -+#define ADM_CPLE_CMD_PTR_LIST BIT(29) -+ -+/* Command list entry */ -+#define ADM_CMD_LC BIT(31) -+#define ADM_CMD_DST_CRCI(n) (((n) & 0xf) << 7) -+#define ADM_CMD_SRC_CRCI(n) (((n) & 0xf) << 3) -+ -+#define ADM_CMD_TYPE_SINGLE 0x0 -+#define ADM_CMD_TYPE_BOX 0x3 -+ -+#define ADM_CRCI_MUX_SEL BIT(4) -+#define ADM_DESC_ALIGN 8 -+#define ADM_MAX_XFER (SZ_64K-1) -+#define ADM_MAX_ROWS (SZ_64K-1) -+#define ADM_MAX_CHANNELS 16 -+ -+struct adm_desc_hw_box { -+ u32 cmd; -+ u32 src_addr; -+ u32 dst_addr; -+ u32 row_len; -+ u32 num_rows; -+ u32 row_offset; -+}; -+ -+struct adm_desc_hw_single { -+ u32 cmd; -+ u32 src_addr; -+ u32 dst_addr; -+ u32 len; -+}; -+ -+struct adm_async_desc { -+ struct virt_dma_desc vd; -+ struct adm_device *adev; -+ -+ size_t length; -+ enum dma_transfer_direction dir; -+ dma_addr_t dma_addr; -+ size_t dma_len; -+ -+ void *cpl; -+ dma_addr_t cp_addr; -+ u32 crci; -+ u32 mux; -+ u32 blk_size; -+}; -+ -+struct adm_chan { -+ struct virt_dma_chan vc; -+ struct adm_device *adev; -+ -+ /* parsed from DT */ -+ u32 id; /* channel id */ -+ -+ struct adm_async_desc *curr_txd; -+ struct dma_slave_config slave; -+ struct list_head node; -+ -+ int error; -+ int initialized; -+}; -+ -+static inline struct adm_chan *to_adm_chan(struct dma_chan *common) -+{ -+ return container_of(common, struct adm_chan, vc.chan); -+} -+ -+struct adm_device { -+ void __iomem *regs; -+ struct device *dev; -+ struct dma_device common; -+ struct device_dma_parameters dma_parms; -+ struct adm_chan *channels; -+ -+ u32 ee; -+ -+ struct clk *core_clk; -+ struct clk *iface_clk; -+ -+ struct reset_control *clk_reset; -+ struct reset_control *c0_reset; -+ struct reset_control *c1_reset; -+ struct reset_control *c2_reset; -+ int irq; -+}; -+ -+/** -+ * adm_free_chan - Frees dma resources associated with the specific channel -+ * -+ * Free all allocated descriptors associated with this channel -+ * -+ */ -+static void adm_free_chan(struct dma_chan *chan) -+{ -+ /* free all queued descriptors */ -+ vchan_free_chan_resources(to_virt_chan(chan)); -+} -+ -+/** -+ * adm_get_blksize - Get block size from burst value -+ * -+ */ -+static int adm_get_blksize(unsigned int burst) -+{ -+ int ret; -+ -+ switch (burst) { -+ case 16: -+ case 32: -+ case 64: -+ case 128: -+ ret = ffs(burst>>4) - 1; -+ break; -+ case 192: -+ ret = 4; -+ break; -+ case 256: -+ ret = 5; -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } -+ -+ return ret; -+} -+ -+/** -+ * adm_process_fc_descriptors - Process descriptors for flow controlled xfers -+ * -+ * @achan: ADM channel -+ * @desc: Descriptor memory pointer -+ * @sg: Scatterlist entry -+ * @crci: CRCI value -+ * @burst: Burst size of transaction -+ * @direction: DMA transfer direction -+ */ -+static void *adm_process_fc_descriptors(struct adm_chan *achan, -+ void *desc, struct scatterlist *sg, u32 crci, u32 burst, -+ enum dma_transfer_direction direction) -+{ -+ struct adm_desc_hw_box *box_desc = NULL; -+ struct adm_desc_hw_single *single_desc; -+ u32 remainder = sg_dma_len(sg); -+ u32 rows, row_offset, crci_cmd; -+ u32 mem_addr = sg_dma_address(sg); -+ u32 *incr_addr = &mem_addr; -+ u32 *src, *dst; -+ -+ if (direction == DMA_DEV_TO_MEM) { -+ crci_cmd = ADM_CMD_SRC_CRCI(crci); -+ row_offset = burst; -+ src = &achan->slave.src_addr; -+ dst = &mem_addr; -+ } else { -+ crci_cmd = ADM_CMD_DST_CRCI(crci); -+ row_offset = burst << 16; -+ src = &mem_addr; -+ dst = &achan->slave.dst_addr; -+ } -+ -+ while (remainder >= burst) { -+ box_desc = desc; -+ box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd; -+ box_desc->row_offset = row_offset; -+ box_desc->src_addr = *src; -+ box_desc->dst_addr = *dst; -+ -+ rows = remainder / burst; -+ rows = min_t(u32, rows, ADM_MAX_ROWS); -+ box_desc->num_rows = rows << 16 | rows; -+ box_desc->row_len = burst << 16 | burst; -+ -+ *incr_addr += burst * rows; -+ remainder -= burst * rows; -+ desc += sizeof(*box_desc); -+ } -+ -+ /* if leftover bytes, do one single descriptor */ -+ if (remainder) { -+ single_desc = desc; -+ single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd; -+ single_desc->len = remainder; -+ single_desc->src_addr = *src; -+ single_desc->dst_addr = *dst; -+ desc += sizeof(*single_desc); -+ -+ if (sg_is_last(sg)) -+ single_desc->cmd |= ADM_CMD_LC; -+ } else { -+ if (box_desc && sg_is_last(sg)) -+ box_desc->cmd |= ADM_CMD_LC; -+ } -+ -+ return desc; -+} -+ -+/** -+ * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers -+ * -+ * @achan: ADM channel -+ * @desc: Descriptor memory pointer -+ * @sg: Scatterlist entry -+ * @direction: DMA transfer direction -+ */ -+static void *adm_process_non_fc_descriptors(struct adm_chan *achan, -+ void *desc, struct scatterlist *sg, -+ enum dma_transfer_direction direction) -+{ -+ struct adm_desc_hw_single *single_desc; -+ u32 remainder = sg_dma_len(sg); -+ u32 mem_addr = sg_dma_address(sg); -+ u32 *incr_addr = &mem_addr; -+ u32 *src, *dst; -+ -+ if (direction == DMA_DEV_TO_MEM) { -+ src = &achan->slave.src_addr; -+ dst = &mem_addr; -+ } else { -+ src = &mem_addr; -+ dst = &achan->slave.dst_addr; -+ } -+ -+ do { -+ single_desc = desc; -+ single_desc->cmd = ADM_CMD_TYPE_SINGLE; -+ single_desc->src_addr = *src; -+ single_desc->dst_addr = *dst; -+ single_desc->len = (remainder > ADM_MAX_XFER) ? -+ ADM_MAX_XFER : remainder; -+ -+ remainder -= single_desc->len; -+ *incr_addr += single_desc->len; -+ desc += sizeof(*single_desc); -+ } while (remainder); -+ -+ /* set last command if this is the end of the whole transaction */ -+ if (sg_is_last(sg)) -+ single_desc->cmd |= ADM_CMD_LC; -+ -+ return desc; -+} -+ -+/** -+ * adm_prep_slave_sg - Prep slave sg transaction -+ * -+ * @chan: dma channel -+ * @sgl: scatter gather list -+ * @sg_len: length of sg -+ * @direction: DMA transfer direction -+ * @flags: DMA flags -+ * @context: transfer context (unused) -+ */ -+static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan, -+ struct scatterlist *sgl, unsigned int sg_len, -+ enum dma_transfer_direction direction, unsigned long flags, -+ void *context) -+{ -+ struct adm_chan *achan = to_adm_chan(chan); -+ struct adm_device *adev = achan->adev; -+ struct adm_async_desc *async_desc; -+ struct scatterlist *sg; -+ dma_addr_t cple_addr; -+ u32 i, burst; -+ u32 single_count = 0, box_count = 0, crci = 0; -+ void *desc; -+ u32 *cple; -+ int blk_size = 0; -+ -+ if (!is_slave_direction(direction)) { -+ dev_err(adev->dev, "invalid dma direction\n"); -+ return NULL; -+ } -+ -+ /* -+ * get burst value from slave configuration -+ */ -+ burst = (direction == DMA_MEM_TO_DEV) ? -+ achan->slave.dst_maxburst : -+ achan->slave.src_maxburst; -+ -+ /* if using flow control, validate burst and crci values */ -+ if (achan->slave.device_fc) { -+ -+ blk_size = adm_get_blksize(burst); -+ if (blk_size < 0) { -+ dev_err(adev->dev, "invalid burst value: %d\n", -+ burst); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ crci = achan->slave.slave_id & 0xf; -+ if (!crci || achan->slave.slave_id > 0x1f) { -+ dev_err(adev->dev, "invalid crci value\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ } -+ -+ /* iterate through sgs and compute allocation size of structures */ -+ for_each_sg(sgl, sg, sg_len, i) { -+ if (achan->slave.device_fc) { -+ box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst, -+ ADM_MAX_ROWS); -+ if (sg_dma_len(sg) % burst) -+ single_count++; -+ } else { -+ single_count += DIV_ROUND_UP(sg_dma_len(sg), -+ ADM_MAX_XFER); -+ } -+ } -+ -+ async_desc = kzalloc(sizeof(*async_desc), GFP_ATOMIC); -+ if (!async_desc) -+ return ERR_PTR(-ENOMEM); -+ -+ if (crci) -+ async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ? -+ ADM_CRCI_CTL_MUX_SEL : 0; -+ async_desc->crci = crci; -+ async_desc->blk_size = blk_size; -+ async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) + -+ box_count * sizeof(struct adm_desc_hw_box) + -+ sizeof(*cple) + 2 * ADM_DESC_ALIGN; -+ -+ async_desc->cpl = kzalloc(async_desc->dma_len, GFP_ATOMIC); -+ if (!async_desc->cpl) -+ goto free; -+ -+ async_desc->adev = adev; -+ -+ /* both command list entry and descriptors must be 8 byte aligned */ -+ cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN); -+ desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN); -+ -+ for_each_sg(sgl, sg, sg_len, i) { -+ async_desc->length += sg_dma_len(sg); -+ -+ if (achan->slave.device_fc) -+ desc = adm_process_fc_descriptors(achan, desc, sg, crci, -+ burst, direction); -+ else -+ desc = adm_process_non_fc_descriptors(achan, desc, sg, -+ direction); -+ } -+ -+ async_desc->dma_addr = dma_map_single(adev->dev, async_desc->cpl, -+ async_desc->dma_len, -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(adev->dev, async_desc->dma_addr)) -+ goto free; -+ -+ cple_addr = async_desc->dma_addr + ((void *)cple - async_desc->cpl); -+ -+ /* init cmd list */ -+ dma_sync_single_for_cpu(adev->dev, cple_addr, sizeof(*cple), -+ DMA_TO_DEVICE); -+ *cple = ADM_CPLE_LP; -+ *cple |= (async_desc->dma_addr + ADM_DESC_ALIGN) >> 3; -+ dma_sync_single_for_device(adev->dev, cple_addr, sizeof(*cple), -+ DMA_TO_DEVICE); -+ -+ return vchan_tx_prep(&achan->vc, &async_desc->vd, flags); -+ -+free: -+ kfree(async_desc); -+ return ERR_PTR(-ENOMEM); -+} -+ -+/** -+ * adm_terminate_all - terminate all transactions on a channel -+ * @achan: adm dma channel -+ * -+ * Dequeues and frees all transactions, aborts current transaction -+ * No callbacks are done -+ * -+ */ -+static int adm_terminate_all(struct dma_chan *chan) -+{ -+ struct adm_chan *achan = to_adm_chan(chan); -+ struct adm_device *adev = achan->adev; -+ unsigned long flags; -+ LIST_HEAD(head); -+ -+ spin_lock_irqsave(&achan->vc.lock, flags); -+ vchan_get_all_descriptors(&achan->vc, &head); -+ -+ /* send flush command to terminate current transaction */ -+ writel_relaxed(0x0, -+ adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee)); -+ -+ spin_unlock_irqrestore(&achan->vc.lock, flags); -+ -+ vchan_dma_desc_free_list(&achan->vc, &head); -+ -+ return 0; -+} -+ -+static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) -+{ -+ struct adm_chan *achan = to_adm_chan(chan); -+ unsigned long flag; -+ -+ spin_lock_irqsave(&achan->vc.lock, flag); -+ memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config)); -+ spin_unlock_irqrestore(&achan->vc.lock, flag); -+ -+ return 0; -+} -+ -+/** -+ * adm_start_dma - start next transaction -+ * @achan - ADM dma channel -+ */ -+static void adm_start_dma(struct adm_chan *achan) -+{ -+ struct virt_dma_desc *vd = vchan_next_desc(&achan->vc); -+ struct adm_device *adev = achan->adev; -+ struct adm_async_desc *async_desc; -+ -+ lockdep_assert_held(&achan->vc.lock); -+ -+ if (!vd) -+ return; -+ -+ list_del(&vd->node); -+ -+ /* write next command list out to the CMD FIFO */ -+ async_desc = container_of(vd, struct adm_async_desc, vd); -+ achan->curr_txd = async_desc; -+ -+ /* reset channel error */ -+ achan->error = 0; -+ -+ if (!achan->initialized) { -+ /* enable interrupts */ -+ writel(ADM_CH_CONF_SHADOW_EN | -+ ADM_CH_CONF_PERM_MPU_CONF | -+ ADM_CH_CONF_MPU_DISABLE | -+ ADM_CH_CONF_SEC_DOMAIN(adev->ee), -+ adev->regs + ADM_CH_CONF(achan->id)); -+ -+ writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN, -+ adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); -+ -+ achan->initialized = 1; -+ } -+ -+ /* set the crci block size if this transaction requires CRCI */ -+ if (async_desc->crci) { -+ writel(async_desc->mux | async_desc->blk_size, -+ adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee)); -+ } -+ -+ /* make sure IRQ enable doesn't get reordered */ -+ wmb(); -+ -+ /* write next command list out to the CMD FIFO */ -+ writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3, -+ adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee)); -+} -+ -+/** -+ * adm_dma_irq - irq handler for ADM controller -+ * @irq: IRQ of interrupt -+ * @data: callback data -+ * -+ * IRQ handler for the bam controller -+ */ -+static irqreturn_t adm_dma_irq(int irq, void *data) -+{ -+ struct adm_device *adev = data; -+ u32 srcs, i; -+ struct adm_async_desc *async_desc; -+ unsigned long flags; -+ -+ srcs = readl_relaxed(adev->regs + -+ ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee)); -+ -+ for (i = 0; i < ADM_MAX_CHANNELS; i++) { -+ struct adm_chan *achan = &adev->channels[i]; -+ u32 status, result; -+ -+ if (srcs & BIT(i)) { -+ status = readl_relaxed(adev->regs + -+ ADM_CH_STATUS_SD(i, adev->ee)); -+ -+ /* if no result present, skip */ -+ if (!(status & ADM_CH_STATUS_VALID)) -+ continue; -+ -+ result = readl_relaxed(adev->regs + -+ ADM_CH_RSLT(i, adev->ee)); -+ -+ /* no valid results, skip */ -+ if (!(result & ADM_CH_RSLT_VALID)) -+ continue; -+ -+ /* flag error if transaction was flushed or failed */ -+ if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH)) -+ achan->error = 1; -+ -+ spin_lock_irqsave(&achan->vc.lock, flags); -+ async_desc = achan->curr_txd; -+ -+ achan->curr_txd = NULL; -+ -+ if (async_desc) { -+ vchan_cookie_complete(&async_desc->vd); -+ -+ /* kick off next DMA */ -+ adm_start_dma(achan); -+ } -+ -+ spin_unlock_irqrestore(&achan->vc.lock, flags); -+ } -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/** -+ * adm_tx_status - returns status of transaction -+ * @chan: dma channel -+ * @cookie: transaction cookie -+ * @txstate: DMA transaction state -+ * -+ * Return status of dma transaction -+ */ -+static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie, -+ struct dma_tx_state *txstate) -+{ -+ struct adm_chan *achan = to_adm_chan(chan); -+ struct virt_dma_desc *vd; -+ enum dma_status ret; -+ unsigned long flags; -+ size_t residue = 0; -+ -+ ret = dma_cookie_status(chan, cookie, txstate); -+ if (ret == DMA_COMPLETE || !txstate) -+ return ret; -+ -+ spin_lock_irqsave(&achan->vc.lock, flags); -+ -+ vd = vchan_find_desc(&achan->vc, cookie); -+ if (vd) -+ residue = container_of(vd, struct adm_async_desc, vd)->length; -+ -+ spin_unlock_irqrestore(&achan->vc.lock, flags); -+ -+ /* -+ * residue is either the full length if it is in the issued list, or 0 -+ * if it is in progress. We have no reliable way of determining -+ * anything inbetween -+ */ -+ dma_set_residue(txstate, residue); -+ -+ if (achan->error) -+ return DMA_ERROR; -+ -+ return ret; -+} -+ -+/** -+ * adm_issue_pending - starts pending transactions -+ * @chan: dma channel -+ * -+ * Issues all pending transactions and starts DMA -+ */ -+static void adm_issue_pending(struct dma_chan *chan) -+{ -+ struct adm_chan *achan = to_adm_chan(chan); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&achan->vc.lock, flags); -+ -+ if (vchan_issue_pending(&achan->vc) && !achan->curr_txd) -+ adm_start_dma(achan); -+ spin_unlock_irqrestore(&achan->vc.lock, flags); -+} -+ -+/** -+ * adm_dma_free_desc - free descriptor memory -+ * @vd: virtual descriptor -+ * -+ */ -+static void adm_dma_free_desc(struct virt_dma_desc *vd) -+{ -+ struct adm_async_desc *async_desc = container_of(vd, -+ struct adm_async_desc, vd); -+ -+ dma_unmap_single(async_desc->adev->dev, async_desc->dma_addr, -+ async_desc->dma_len, DMA_TO_DEVICE); -+ kfree(async_desc->cpl); -+ kfree(async_desc); -+} -+ -+static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan, -+ u32 index) -+{ -+ achan->id = index; -+ achan->adev = adev; -+ -+ vchan_init(&achan->vc, &adev->common); -+ achan->vc.desc_free = adm_dma_free_desc; -+} -+ -+static int adm_dma_probe(struct platform_device *pdev) -+{ -+ struct adm_device *adev; -+ struct resource *iores; -+ int ret; -+ u32 i; -+ -+ adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL); -+ if (!adev) -+ return -ENOMEM; -+ -+ adev->dev = &pdev->dev; -+ -+ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ adev->regs = devm_ioremap_resource(&pdev->dev, iores); -+ if (IS_ERR(adev->regs)) -+ return PTR_ERR(adev->regs); -+ -+ adev->irq = platform_get_irq(pdev, 0); -+ if (adev->irq < 0) -+ return adev->irq; -+ -+ ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee); -+ if (ret) { -+ dev_err(adev->dev, "Execution environment unspecified\n"); -+ return ret; -+ } -+ -+ adev->core_clk = devm_clk_get(adev->dev, "core"); -+ if (IS_ERR(adev->core_clk)) -+ return PTR_ERR(adev->core_clk); -+ -+ ret = clk_prepare_enable(adev->core_clk); -+ if (ret) { -+ dev_err(adev->dev, "failed to prepare/enable core clock\n"); -+ return ret; -+ } -+ -+ adev->iface_clk = devm_clk_get(adev->dev, "iface"); -+ if (IS_ERR(adev->iface_clk)) { -+ ret = PTR_ERR(adev->iface_clk); -+ goto err_disable_core_clk; -+ } -+ -+ ret = clk_prepare_enable(adev->iface_clk); -+ if (ret) { -+ dev_err(adev->dev, "failed to prepare/enable iface clock\n"); -+ goto err_disable_core_clk; -+ } -+ -+ adev->clk_reset = devm_reset_control_get(&pdev->dev, "clk"); -+ if (IS_ERR(adev->clk_reset)) { -+ dev_err(adev->dev, "failed to get ADM0 reset\n"); -+ ret = PTR_ERR(adev->clk_reset); -+ goto err_disable_clks; -+ } -+ -+ adev->c0_reset = devm_reset_control_get(&pdev->dev, "c0"); -+ if (IS_ERR(adev->c0_reset)) { -+ dev_err(adev->dev, "failed to get ADM0 C0 reset\n"); -+ ret = PTR_ERR(adev->c0_reset); -+ goto err_disable_clks; -+ } -+ -+ adev->c1_reset = devm_reset_control_get(&pdev->dev, "c1"); -+ if (IS_ERR(adev->c1_reset)) { -+ dev_err(adev->dev, "failed to get ADM0 C1 reset\n"); -+ ret = PTR_ERR(adev->c1_reset); -+ goto err_disable_clks; -+ } -+ -+ adev->c2_reset = devm_reset_control_get(&pdev->dev, "c2"); -+ if (IS_ERR(adev->c2_reset)) { -+ dev_err(adev->dev, "failed to get ADM0 C2 reset\n"); -+ ret = PTR_ERR(adev->c2_reset); -+ goto err_disable_clks; -+ } -+ -+ reset_control_assert(adev->clk_reset); -+ reset_control_assert(adev->c0_reset); -+ reset_control_assert(adev->c1_reset); -+ reset_control_assert(adev->c2_reset); -+ -+ reset_control_deassert(adev->clk_reset); -+ reset_control_deassert(adev->c0_reset); -+ reset_control_deassert(adev->c1_reset); -+ reset_control_deassert(adev->c2_reset); -+ -+ adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS, -+ sizeof(*adev->channels), GFP_KERNEL); -+ -+ if (!adev->channels) { -+ ret = -ENOMEM; -+ goto err_disable_clks; -+ } -+ -+ /* allocate and initialize channels */ -+ INIT_LIST_HEAD(&adev->common.channels); -+ -+ for (i = 0; i < ADM_MAX_CHANNELS; i++) -+ adm_channel_init(adev, &adev->channels[i], i); -+ -+ /* reset CRCIs */ -+ for (i = 0; i < 16; i++) -+ writel(ADM_CRCI_CTL_RST, adev->regs + -+ ADM_CRCI_CTL(i, adev->ee)); -+ -+ /* configure client interfaces */ -+ writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) | -+ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0)); -+ writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) | -+ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1)); -+ writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) | -+ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2)); -+ writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf), -+ adev->regs + ADM_GP_CTL); -+ -+ ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq, -+ 0, "adm_dma", adev); -+ if (ret) -+ goto err_disable_clks; -+ -+ platform_set_drvdata(pdev, adev); -+ -+ adev->common.dev = adev->dev; -+ adev->common.dev->dma_parms = &adev->dma_parms; -+ -+ /* set capabilities */ -+ dma_cap_zero(adev->common.cap_mask); -+ dma_cap_set(DMA_SLAVE, adev->common.cap_mask); -+ dma_cap_set(DMA_PRIVATE, adev->common.cap_mask); -+ -+ /* initialize dmaengine apis */ -+ adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV); -+ adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; -+ adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ adev->common.device_free_chan_resources = adm_free_chan; -+ adev->common.device_prep_slave_sg = adm_prep_slave_sg; -+ adev->common.device_issue_pending = adm_issue_pending; -+ adev->common.device_tx_status = adm_tx_status; -+ adev->common.device_terminate_all = adm_terminate_all; -+ adev->common.device_config = adm_slave_config; -+ -+ ret = dma_async_device_register(&adev->common); -+ if (ret) { -+ dev_err(adev->dev, "failed to register dma async device\n"); -+ goto err_disable_clks; -+ } -+ -+ ret = of_dma_controller_register(pdev->dev.of_node, -+ of_dma_xlate_by_chan_id, -+ &adev->common); -+ if (ret) -+ goto err_unregister_dma; -+ -+ return 0; -+ -+err_unregister_dma: -+ dma_async_device_unregister(&adev->common); -+err_disable_clks: -+ clk_disable_unprepare(adev->iface_clk); -+err_disable_core_clk: -+ clk_disable_unprepare(adev->core_clk); -+ -+ return ret; -+} -+ -+static int adm_dma_remove(struct platform_device *pdev) -+{ -+ struct adm_device *adev = platform_get_drvdata(pdev); -+ struct adm_chan *achan; -+ u32 i; -+ -+ of_dma_controller_free(pdev->dev.of_node); -+ dma_async_device_unregister(&adev->common); -+ -+ for (i = 0; i < ADM_MAX_CHANNELS; i++) { -+ achan = &adev->channels[i]; -+ -+ /* mask IRQs for this channel/EE pair */ -+ writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); -+ -+ adm_terminate_all(&adev->channels[i].vc.chan); -+ } -+ -+ devm_free_irq(adev->dev, adev->irq, adev); -+ -+ clk_disable_unprepare(adev->core_clk); -+ clk_disable_unprepare(adev->iface_clk); -+ -+ return 0; -+} -+ -+static const struct of_device_id adm_of_match[] = { -+ { .compatible = "qcom,adm", }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, adm_of_match); -+ -+static struct platform_driver adm_dma_driver = { -+ .probe = adm_dma_probe, -+ .remove = adm_dma_remove, -+ .driver = { -+ .name = "adm-dma-engine", -+ .of_match_table = adm_of_match, -+ }, -+}; -+ -+module_platform_driver(adm_dma_driver); -+ -+MODULE_AUTHOR("Andy Gross "); -+MODULE_DESCRIPTION("QCOM ADM DMA engine driver"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-4.19/0030-clk-Disable-i2c-device-on-gsbi4.patch b/target/linux/ipq806x/patches-4.19/0030-clk-Disable-i2c-device-on-gsbi4.patch deleted file mode 100644 index b2a6afe0dd..0000000000 --- a/target/linux/ipq806x/patches-4.19/0030-clk-Disable-i2c-device-on-gsbi4.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 0c974b87829e007dc4fae94e20d488204e20e662 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 08:16:10 +0100 -Subject: [PATCH 30/69] clk: Disable i2c device on gsbi4 - -This patch was not annotated and comes from the v4.4 tree. - -Signed-off-by: John Crispin ---- - drivers/clk/qcom/gcc-ipq806x.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -294,7 +294,7 @@ static struct clk_rcg gsbi1_uart_src = { - .parent_names = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, -- .flags = CLK_SET_PARENT_GATE, -+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -312,7 +312,7 @@ static struct clk_branch gsbi1_uart_clk - }, - .num_parents = 1, - .ops = &clk_branch_ops, -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -890,6 +890,7 @@ static struct clk_branch gsbi1_h_clk = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_h_clk", - .ops = &clk_branch_ops, -+ .flags = CLK_IGNORE_UNUSED, - }, - }, - }; diff --git a/target/linux/ipq806x/patches-4.19/0031-mtd-add-SMEM-parser-for-QCOM-platforms.patch b/target/linux/ipq806x/patches-4.19/0031-mtd-add-SMEM-parser-for-QCOM-platforms.patch deleted file mode 100644 index a7e95513fd..0000000000 --- a/target/linux/ipq806x/patches-4.19/0031-mtd-add-SMEM-parser-for-QCOM-platforms.patch +++ /dev/null @@ -1,282 +0,0 @@ -From d8eeb4de90e968ba32d956728c866f20752cf2c3 Mon Sep 17 00:00:00 2001 -From: Mathieu Olivari -Date: Thu, 9 Mar 2017 08:18:08 +0100 -Subject: [PATCH 31/69] mtd: add SMEM parser for QCOM platforms - -On QCOM platforms using MTD devices storage (such as IPQ806x), SMEM is -used to store partition layout. This new parser can now be used to read -SMEM and use it to register an MTD layout according to its content. - -Signed-off-by: Mathieu Olivari -Signed-off-by: Ram Chandra Jangir ---- - drivers/mtd/Kconfig | 7 ++ - drivers/mtd/Makefile | 1 + - drivers/mtd/qcom_smem_part.c | 228 +++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 236 insertions(+) - create mode 100644 drivers/mtd/qcom_smem_part.c - ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -193,6 +193,13 @@ config MTD_MYLOADER_PARTS - You will still need the parsing functions to be called by the driver - for your particular device. It won't happen automatically. - -+config MTD_QCOM_SMEM_PARTS -+ tristate "QCOM SMEM partitioning support" -+ depends on QCOM_SMEM -+ help -+ This provides partitions parser for QCOM devices using SMEM -+ such as IPQ806x. -+ - comment "User Modules And Translation Layers" - - # ---- /dev/null -+++ b/drivers/mtd/qcom_smem_part.c -@@ -0,0 +1,235 @@ -+/* -+ * Copyright (c) 2015, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* Processor/host identifier for the application processor */ -+#define SMEM_HOST_APPS 0 -+ -+/* SMEM items index */ -+#define SMEM_AARM_PARTITION_TABLE 9 -+#define SMEM_BOOT_FLASH_TYPE 421 -+#define SMEM_BOOT_FLASH_BLOCK_SIZE 424 -+ -+/* SMEM Flash types */ -+#define SMEM_FLASH_NAND 2 -+#define SMEM_FLASH_SPI 6 -+ -+#define SMEM_PART_NAME_SZ 16 -+#define SMEM_PARTS_MAX 32 -+ -+struct smem_partition { -+ char name[SMEM_PART_NAME_SZ]; -+ __le32 start; -+ __le32 size; -+ __le32 attr; -+}; -+ -+struct smem_partition_table { -+ u8 magic[8]; -+ __le32 version; -+ __le32 len; -+ struct smem_partition parts[SMEM_PARTS_MAX]; -+}; -+ -+/* SMEM Magic values in partition table */ -+static const u8 SMEM_PTABLE_MAGIC[] = { -+ 0xaa, 0x73, 0xee, 0x55, -+ 0xdb, 0xbd, 0x5e, 0xe3, -+}; -+ -+static int qcom_smem_get_flash_blksz(u64 **smem_blksz) -+{ -+ size_t size; -+ -+ *smem_blksz = qcom_smem_get(SMEM_HOST_APPS, SMEM_BOOT_FLASH_BLOCK_SIZE, -+ &size); -+ -+ if (IS_ERR(*smem_blksz)) { -+ pr_err("Unable to read flash blksz from SMEM\n"); -+ return -ENOENT; -+ } -+ -+ if (size != sizeof(**smem_blksz)) { -+ pr_err("Invalid flash blksz size in SMEM\n"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int qcom_smem_get_flash_type(u64 **smem_flash_type) -+{ -+ size_t size; -+ -+ *smem_flash_type = qcom_smem_get(SMEM_HOST_APPS, SMEM_BOOT_FLASH_TYPE, -+ &size); -+ -+ if (IS_ERR(*smem_flash_type)) { -+ pr_err("Unable to read flash type from SMEM\n"); -+ return -ENOENT; -+ } -+ -+ if (size != sizeof(**smem_flash_type)) { -+ pr_err("Invalid flash type size in SMEM\n"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int qcom_smem_get_flash_partitions(struct smem_partition_table **pparts) -+{ -+ size_t size; -+ -+ *pparts = qcom_smem_get(SMEM_HOST_APPS, SMEM_AARM_PARTITION_TABLE, -+ &size); -+ -+ if (IS_ERR(*pparts)) { -+ pr_err("Unable to read partition table from SMEM\n"); -+ return -ENOENT; -+ } -+ -+ return 0; -+} -+ -+static int of_dev_node_match(struct device *dev, void *data) -+{ -+ return dev->of_node == data; -+} -+ -+static bool is_spi_device(struct device_node *np) -+{ -+ struct device *dev; -+ -+ dev = bus_find_device(&spi_bus_type, NULL, np, of_dev_node_match); -+ if (!dev) -+ return false; -+ -+ put_device(dev); -+ return true; -+} -+ -+static int parse_qcom_smem_partitions(struct mtd_info *master, -+ const struct mtd_partition **pparts, -+ struct mtd_part_parser_data *data) -+{ -+ struct smem_partition_table *smem_parts; -+ u64 *smem_flash_type, *smem_blksz; -+ struct mtd_partition *mtd_parts; -+ struct device_node *of_node = master->dev.of_node; -+ int i, ret; -+ -+ /* -+ * SMEM will only store the partition table of the boot device. -+ * If this is not the boot device, do not return any partition. -+ */ -+ ret = qcom_smem_get_flash_type(&smem_flash_type); -+ if (ret < 0) -+ return ret; -+ -+ if ((*smem_flash_type == SMEM_FLASH_NAND && !mtd_type_is_nand(master)) -+ || (*smem_flash_type == SMEM_FLASH_SPI && !is_spi_device(of_node))) -+ return 0; -+ -+ /* -+ * Just for sanity purpose, make sure the block size in SMEM matches the -+ * block size of the MTD device -+ */ -+ ret = qcom_smem_get_flash_blksz(&smem_blksz); -+ if (ret < 0) -+ return ret; -+ -+ if (*smem_blksz != master->erasesize) { -+ pr_err("SMEM block size differs from MTD block size\n"); -+ return -EINVAL; -+ } -+ -+ /* Get partition pointer from SMEM */ -+ ret = qcom_smem_get_flash_partitions(&smem_parts); -+ if (ret < 0) -+ return ret; -+ -+ if (memcmp(SMEM_PTABLE_MAGIC, smem_parts->magic, -+ sizeof(SMEM_PTABLE_MAGIC))) { -+ pr_err("SMEM partition magic invalid\n"); -+ return -EINVAL; -+ } -+ -+ /* Allocate and populate the mtd structures */ -+ mtd_parts = kcalloc(le32_to_cpu(smem_parts->len), sizeof(*mtd_parts), -+ GFP_KERNEL); -+ if (!mtd_parts) -+ return -ENOMEM; -+ -+ for (i = 0; i < smem_parts->len; i++) { -+ struct smem_partition *s_part = &smem_parts->parts[i]; -+ struct mtd_partition *m_part = &mtd_parts[i]; -+ -+ m_part->name = s_part->name; -+ m_part->size = le32_to_cpu(s_part->size) * (*smem_blksz); -+ m_part->offset = le32_to_cpu(s_part->start) * (*smem_blksz); -+ -+ /* -+ * The last SMEM partition may have its size marked as -+ * something like 0xffffffff, which means "until the end of the -+ * flash device". In this case, truncate it. -+ */ -+ if (m_part->offset + m_part->size > master->size) -+ m_part->size = master->size - m_part->offset; -+ } -+ -+ *pparts = mtd_parts; -+ -+ return smem_parts->len; -+} -+ -+static const struct of_device_id qcom_smem_of_match_table[] = { -+ { .compatible = "qcom,smem" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, qcom_smem_of_match_table); -+ -+static struct mtd_part_parser qcom_smem_parser = { -+ .owner = THIS_MODULE, -+ .parse_fn = parse_qcom_smem_partitions, -+ .name = "qcom-smem", -+ .of_match_table = qcom_smem_of_match_table, -+}; -+ -+static int __init qcom_smem_parser_init(void) -+{ -+ register_mtd_parser(&qcom_smem_parser); -+ return 0; -+} -+ -+static void __exit qcom_smem_parser_exit(void) -+{ -+ deregister_mtd_parser(&qcom_smem_parser); -+} -+ -+module_init(qcom_smem_parser_init); -+module_exit(qcom_smem_parser_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Mathieu Olivari "); -+MODULE_DESCRIPTION("Parsing code for SMEM based partition tables"); ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o - obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o - obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o - obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o -+obj-$(CONFIG_MTD_QCOM_SMEM_PARTS) += qcom_smem_part.o - obj-y += parsers/ - - # 'Users' - code which presents functionality to userspace. diff --git a/target/linux/ipq806x/patches-4.19/0032-phy-add-qcom-dwc3-phy.patch b/target/linux/ipq806x/patches-4.19/0032-phy-add-qcom-dwc3-phy.patch deleted file mode 100644 index 0de0878f86..0000000000 --- a/target/linux/ipq806x/patches-4.19/0032-phy-add-qcom-dwc3-phy.patch +++ /dev/null @@ -1,614 +0,0 @@ -From b9004f4fd23e4c614d71c972f3a9311665480e29 Mon Sep 17 00:00:00 2001 -From: Andy Gross -Date: Thu, 9 Mar 2017 08:19:18 +0100 -Subject: [PATCH 32/69] phy: add qcom dwc3 phy - -Signed-off-by: Andy Gross ---- - ---- a/drivers/phy/qualcomm/Kconfig -+++ b/drivers/phy/qualcomm/Kconfig -@@ -65,3 +65,15 @@ config PHY_QCOM_USB_HSIC - select GENERIC_PHY - help - Support for the USB HSIC ULPI compliant PHY on QCOM chipsets. -+ -+config PHY_QCOM_DWC3 -+ tristate "QCOM DWC3 USB PHY support" -+ depends on ARCH_QCOM -+ depends on HAS_IOMEM -+ depends on OF -+ select GENERIC_PHY -+ help -+ This option enables support for the Synopsis PHYs present inside the -+ Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS -+ PHY controllers. -+ ---- a/drivers/phy/qualcomm/Makefile -+++ b/drivers/phy/qualcomm/Makefile -@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom- - obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o - obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o - obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o -+obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o ---- /dev/null -+++ b/drivers/phy/qualcomm/phy-qcom-dwc3.c -@@ -0,0 +1,578 @@ -+/* Copyright (c) 2014-2015, Code Aurora Forum. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+*/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/** -+ * USB QSCRATCH Hardware registers -+ */ -+#define QSCRATCH_GENERAL_CFG (0x08) -+#define HSUSB_PHY_CTRL_REG (0x10) -+ -+/* PHY_CTRL_REG */ -+#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24) -+#define HSUSB_CTRL_USB2_SUSPEND BIT(23) -+#define HSUSB_CTRL_UTMI_CLK_EN BIT(21) -+#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20) -+#define HSUSB_CTRL_USE_CLKCORE BIT(18) -+#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17) -+#define HSUSB_CTRL_COMMONONN BIT(11) -+#define HSUSB_CTRL_ID_HV_CLAMP BIT(9) -+#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8) -+#define HSUSB_CTRL_CLAMP_EN BIT(7) -+#define HSUSB_CTRL_RETENABLEN BIT(1) -+#define HSUSB_CTRL_POR BIT(0) -+ -+/* QSCRATCH_GENERAL_CFG */ -+#define HSUSB_GCFG_XHCI_REV BIT(2) -+ -+/** -+ * USB QSCRATCH Hardware registers -+ */ -+#define SSUSB_PHY_CTRL_REG (0x30) -+#define SSUSB_PHY_PARAM_CTRL_1 (0x34) -+#define SSUSB_PHY_PARAM_CTRL_2 (0x38) -+#define CR_PROTOCOL_DATA_IN_REG (0x3c) -+#define CR_PROTOCOL_DATA_OUT_REG (0x40) -+#define CR_PROTOCOL_CAP_ADDR_REG (0x44) -+#define CR_PROTOCOL_CAP_DATA_REG (0x48) -+#define CR_PROTOCOL_READ_REG (0x4c) -+#define CR_PROTOCOL_WRITE_REG (0x50) -+ -+/* PHY_CTRL_REG */ -+#define SSUSB_CTRL_REF_USE_PAD BIT(28) -+#define SSUSB_CTRL_TEST_POWERDOWN BIT(27) -+#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24) -+#define SSUSB_CTRL_SS_PHY_EN BIT(8) -+#define SSUSB_CTRL_SS_PHY_RESET BIT(7) -+ -+/* SSPHY control registers - Does this need 0x30? */ -+#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane) -+#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * lane) -+ -+/* SSPHY SoC version specific values */ -+#define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */ -+#define SSPHY_TX_DEEMPH_3_5DB 23 /* Override value for transmit -+ preemphasis */ -+#define SSPHY_MPLL_VALUE 0 /* Override value for mpll */ -+ -+/* QSCRATCH PHY_PARAM_CTRL1 fields */ -+#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK 0x07f00000u -+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK 0x000fc000u -+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK 0x00003f00u -+#define PHY_PARAM_CTRL1_LOS_BIAS_MASK 0x000000f8u -+ -+#define PHY_PARAM_CTRL1_MASK \ -+ (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \ -+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \ -+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \ -+ PHY_PARAM_CTRL1_LOS_BIAS_MASK) -+ -+#define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \ -+ (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK) -+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \ -+ (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK) -+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \ -+ (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK) -+#define PHY_PARAM_CTRL1_LOS_BIAS(x) \ -+ (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK) -+ -+/* RX OVRD IN HI bits */ -+#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13) -+#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12) -+#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11) -+#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700 -+#define RX_OVRD_IN_HI_RX_EQ_SHIFT 8 -+#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7) -+#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6) -+#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5) -+#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK 0x0018 -+#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2) -+#define RX_OVRD_IN_HI_RX_RATE_MASK 0x0003 -+ -+/* TX OVRD DRV LO register bits */ -+#define TX_OVRD_DRV_LO_AMPLITUDE_MASK 0x007F -+#define TX_OVRD_DRV_LO_PREEMPH_MASK 0x3F80 -+#define TX_OVRD_DRV_LO_PREEMPH_SHIFT 7 -+#define TX_OVRD_DRV_LO_EN BIT(14) -+ -+/* SS CAP register bits */ -+#define SS_CR_CAP_ADDR_REG BIT(0) -+#define SS_CR_CAP_DATA_REG BIT(0) -+#define SS_CR_READ_REG BIT(0) -+#define SS_CR_WRITE_REG BIT(0) -+ -+struct qcom_dwc3_usb_phy { -+ struct regmap *base; -+ struct device *dev; -+ struct clk *xo_clk; -+ struct clk *ref_clk; -+ u32 rx_eq; -+ u32 tx_deamp_3_5db; -+ u32 mpll; -+}; -+ -+struct qcom_dwc3_phy_drvdata { -+ struct phy_ops ops; -+ u32 clk_rate; -+}; -+ -+/** -+ * Write register and read back masked value to confirm it is written -+ * -+ * @base - QCOM DWC3 PHY base virtual address. -+ * @offset - register offset. -+ * @mask - register bitmask specifying what should be updated -+ * @val - value to write. -+ */ -+static inline void qcom_dwc3_phy_write_readback( -+ struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset, -+ const u32 mask, u32 val) -+{ -+ u32 write_val, tmp; -+ -+ tmp = regmap_read(phy_dwc3->base, offset, &tmp); -+ tmp &= ~mask; /* retain other bits */ -+ write_val = tmp | val; -+ -+ regmap_write(phy_dwc3->base, offset, write_val); -+ -+ /* Read back to see if val was written */ -+ regmap_read(phy_dwc3->base, offset, &tmp); -+ tmp &= mask; /* clear other bits */ -+ -+ if (tmp != val) -+ dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", -+ val, offset); -+} -+ -+static int wait_for_latch(struct regmap *base, u32 addr) -+{ -+ u32 retry = 10, data; -+ -+ while (true) { -+ regmap_read(base, addr, &data); -+ if (!data) -+ break; -+ -+ if (--retry == 0) -+ return -ETIMEDOUT; -+ -+ usleep_range(10, 20); -+ } -+ -+ return 0; -+} -+ -+/** -+ * Write SSPHY register -+ * -+ * @base - QCOM DWC3 PHY base virtual address. -+ * @addr - SSPHY address to write. -+ * @val - value to write. -+ */ -+static int qcom_dwc3_ss_write_phycreg(struct qcom_dwc3_usb_phy *phy_dwc3, -+ u32 addr, u32 val) -+{ -+ int ret; -+ -+ regmap_write(phy_dwc3->base, CR_PROTOCOL_DATA_IN_REG, addr); -+ regmap_write(phy_dwc3->base, CR_PROTOCOL_CAP_ADDR_REG, SS_CR_CAP_ADDR_REG); -+ -+ ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_CAP_ADDR_REG); -+ if (ret) -+ goto err_wait; -+ -+ regmap_write(phy_dwc3->base, CR_PROTOCOL_DATA_IN_REG, val); -+ regmap_write(phy_dwc3->base, CR_PROTOCOL_CAP_DATA_REG, SS_CR_CAP_DATA_REG); -+ -+ ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_CAP_DATA_REG); -+ if (ret) -+ goto err_wait; -+ -+ regmap_write(phy_dwc3->base, CR_PROTOCOL_WRITE_REG, SS_CR_WRITE_REG); -+ -+ ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_WRITE_REG); -+ -+err_wait: -+ if (ret) -+ dev_err(phy_dwc3->dev, "timeout waiting for latch\n"); -+ return ret; -+} -+ -+/** -+ * Read SSPHY register. -+ * -+ * @base - QCOM DWC3 PHY base virtual address. -+ * @addr - SSPHY address to read. -+ */ -+static int qcom_dwc3_ss_read_phycreg(struct regmap *base, u32 addr, u32 *val) -+{ -+ int ret; -+ -+ regmap_write(base, CR_PROTOCOL_DATA_IN_REG, addr); -+ regmap_write(base, CR_PROTOCOL_CAP_ADDR_REG, SS_CR_CAP_ADDR_REG); -+ -+ ret = wait_for_latch(base, CR_PROTOCOL_CAP_ADDR_REG); -+ if (ret) -+ goto err_wait; -+ -+ /* -+ * Due to hardware bug, first read of SSPHY register might be -+ * incorrect. Hence as workaround, SW should perform SSPHY register -+ * read twice, but use only second read and ignore first read. -+ */ -+ regmap_write(base, CR_PROTOCOL_READ_REG, SS_CR_READ_REG); -+ -+ ret = wait_for_latch(base, CR_PROTOCOL_READ_REG); -+ if (ret) -+ goto err_wait; -+ -+ /* throwaway read */ -+ regmap_read(base, CR_PROTOCOL_DATA_OUT_REG, &ret); -+ -+ regmap_write(base, CR_PROTOCOL_READ_REG, SS_CR_READ_REG); -+ -+ ret = wait_for_latch(base, CR_PROTOCOL_READ_REG); -+ if (ret) -+ goto err_wait; -+ -+ regmap_read(base, CR_PROTOCOL_DATA_OUT_REG, val); -+ -+err_wait: -+ return ret; -+} -+ -+static int qcom_dwc3_hs_phy_init(struct phy *phy) -+{ -+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy); -+ int ret; -+ u32 val; -+ -+ ret = clk_prepare_enable(phy_dwc3->xo_clk); -+ if (ret) -+ return ret; -+ -+ ret = clk_prepare_enable(phy_dwc3->ref_clk); -+ if (ret) { -+ clk_disable_unprepare(phy_dwc3->xo_clk); -+ return ret; -+ } -+ -+ /* -+ * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel -+ * enable clamping, and disable RETENTION (power-on default is ENABLED) -+ */ -+ val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP | -+ HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN | -+ HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP | -+ HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID | -+ HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70; -+ -+ /* use core clock if external reference is not present */ -+ if (!phy_dwc3->xo_clk) -+ val |= HSUSB_CTRL_USE_CLKCORE; -+ -+ regmap_write(phy_dwc3->base, HSUSB_PHY_CTRL_REG, val); -+ usleep_range(2000, 2200); -+ -+ /* Disable (bypass) VBUS and ID filters */ -+ regmap_write(phy_dwc3->base, QSCRATCH_GENERAL_CFG, HSUSB_GCFG_XHCI_REV); -+ -+ return 0; -+} -+ -+static int qcom_dwc3_hs_phy_exit(struct phy *phy) -+{ -+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy); -+ -+ clk_disable_unprepare(phy_dwc3->ref_clk); -+ clk_disable_unprepare(phy_dwc3->xo_clk); -+ -+ return 0; -+} -+ -+static int qcom_dwc3_ss_phy_init(struct phy *phy) -+{ -+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy); -+ int ret; -+ u32 data = 0; -+ -+ ret = clk_prepare_enable(phy_dwc3->xo_clk); -+ if (ret) -+ return ret; -+ -+ ret = clk_prepare_enable(phy_dwc3->ref_clk); -+ if (ret) { -+ clk_disable_unprepare(phy_dwc3->xo_clk); -+ return ret; -+ } -+ -+ /* reset phy */ -+ regmap_read(phy_dwc3->base, SSUSB_PHY_CTRL_REG, &data); -+ regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, -+ data | SSUSB_CTRL_SS_PHY_RESET); -+ usleep_range(2000, 2200); -+ regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data); -+ -+ /* clear REF_PAD if we don't have XO clk */ -+ if (!phy_dwc3->xo_clk) -+ data &= ~SSUSB_CTRL_REF_USE_PAD; -+ else -+ data |= SSUSB_CTRL_REF_USE_PAD; -+ -+ regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data); -+ -+ /* wait for ref clk to become stable, this can take up to 30ms */ -+ msleep(30); -+ -+ data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT; -+ regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data); -+ -+ /* -+ * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates -+ * in HS mode instead of SS mode. Workaround it by asserting -+ * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode -+ */ -+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x102D, &data); -+ if (ret) -+ goto err_phy_trans; -+ -+ data |= (1 << 7); -+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x102D, data); -+ if (ret) -+ goto err_phy_trans; -+ -+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x1010, &data); -+ if (ret) -+ goto err_phy_trans; -+ -+ data &= ~0xff0; -+ data |= 0x20; -+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x1010, data); -+ if (ret) -+ goto err_phy_trans; -+ -+ /* -+ * Fix RX Equalization setting as follows -+ * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 -+ * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 -+ * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version -+ * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 -+ */ -+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, -+ SSPHY_CTRL_RX_OVRD_IN_HI(0), &data); -+ if (ret) -+ goto err_phy_trans; -+ -+ data &= ~RX_OVRD_IN_HI_RX_EQ_EN; -+ data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD; -+ data &= ~RX_OVRD_IN_HI_RX_EQ_MASK; -+ data |= phy_dwc3->rx_eq << RX_OVRD_IN_HI_RX_EQ_SHIFT; -+ data |= RX_OVRD_IN_HI_RX_EQ_OVRD; -+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, -+ SSPHY_CTRL_RX_OVRD_IN_HI(0), data); -+ if (ret) -+ goto err_phy_trans; -+ -+ /* -+ * Set EQ and TX launch amplitudes as follows -+ * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version -+ * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110 -+ * LANE0.TX_OVRD_DRV_LO.EN set to 1. -+ */ -+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, -+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data); -+ if (ret) -+ goto err_phy_trans; -+ -+ data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK; -+ data |= phy_dwc3->tx_deamp_3_5db << TX_OVRD_DRV_LO_PREEMPH_SHIFT; -+ data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK; -+ data |= 0x6E; -+ data |= TX_OVRD_DRV_LO_EN; -+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, -+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), data); -+ if (ret) -+ goto err_phy_trans; -+ -+ qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x30, phy_dwc3->mpll); -+ -+ /* -+ * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows -+ * TX_FULL_SWING [26:20] amplitude to 110 -+ * TX_DEEMPH_6DB [19:14] to 32 -+ * TX_DEEMPH_3_5DB [13:8] set based on SoC version -+ * LOS_BIAS [7:3] to 9 -+ */ -+ regmap_read(phy_dwc3->base, SSUSB_PHY_PARAM_CTRL_1, &data); -+ -+ data &= ~PHY_PARAM_CTRL1_MASK; -+ -+ data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) | -+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) | -+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) | -+ PHY_PARAM_CTRL1_LOS_BIAS(0x9); -+ -+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1, -+ PHY_PARAM_CTRL1_MASK, data); -+ -+err_phy_trans: -+ return ret; -+} -+ -+static int qcom_dwc3_ss_phy_exit(struct phy *phy) -+{ -+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy); -+ -+ /* Sequence to put SSPHY in low power state: -+ * 1. Clear REF_PHY_EN in PHY_CTRL_REG -+ * 2. Clear REF_USE_PAD in PHY_CTRL_REG -+ * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention -+ */ -+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, -+ SSUSB_CTRL_SS_PHY_EN, 0x0); -+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, -+ SSUSB_CTRL_REF_USE_PAD, 0x0); -+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, -+ SSUSB_CTRL_TEST_POWERDOWN, 0x0); -+ -+ clk_disable_unprepare(phy_dwc3->ref_clk); -+ clk_disable_unprepare(phy_dwc3->xo_clk); -+ -+ return 0; -+} -+ -+static const struct qcom_dwc3_phy_drvdata qcom_dwc3_hs_drvdata = { -+ .ops = { -+ .init = qcom_dwc3_hs_phy_init, -+ .exit = qcom_dwc3_hs_phy_exit, -+ .owner = THIS_MODULE, -+ }, -+ .clk_rate = 60000000, -+}; -+ -+static const struct qcom_dwc3_phy_drvdata qcom_dwc3_ss_drvdata = { -+ .ops = { -+ .init = qcom_dwc3_ss_phy_init, -+ .exit = qcom_dwc3_ss_phy_exit, -+ .owner = THIS_MODULE, -+ }, -+ .clk_rate = 125000000, -+}; -+ -+static const struct of_device_id qcom_dwc3_phy_table[] = { -+ { .compatible = "qcom,dwc3-hs-usb-phy", .data = &qcom_dwc3_hs_drvdata }, -+ { .compatible = "qcom,dwc3-ss-usb-phy", .data = &qcom_dwc3_ss_drvdata }, -+ { /* Sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, qcom_dwc3_phy_table); -+ -+static int qcom_dwc3_phy_probe(struct platform_device *pdev) -+{ -+ struct qcom_dwc3_usb_phy *phy_dwc3; -+ struct phy_provider *phy_provider; -+ struct phy *generic_phy; -+ struct resource *res; -+ const struct of_device_id *match; -+ const struct qcom_dwc3_phy_drvdata *data; -+ struct device_node *np; -+ -+ phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL); -+ if (!phy_dwc3) -+ return -ENOMEM; -+ -+ match = of_match_node(qcom_dwc3_phy_table, pdev->dev.of_node); -+ data = match->data; -+ -+ phy_dwc3->dev = &pdev->dev; -+ -+ phy_dwc3->base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap"); -+ if (IS_ERR_OR_NULL(phy_dwc3->base)) -+ return PTR_ERR_OR_ZERO(phy_dwc3->base) ? : -EINVAL; -+ -+ phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref"); -+ if (IS_ERR(phy_dwc3->ref_clk)) { -+ dev_dbg(phy_dwc3->dev, "cannot get reference clock\n"); -+ return PTR_ERR(phy_dwc3->ref_clk); -+ } -+ -+ clk_set_rate(phy_dwc3->ref_clk, data->clk_rate); -+ -+ phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo"); -+ if (IS_ERR(phy_dwc3->xo_clk)) { -+ dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n"); -+ phy_dwc3->xo_clk = NULL; -+ } -+ -+ /* Parse device node to probe HSIO settings */ -+ np = of_node_get(pdev->dev.of_node); -+ if (!of_compat_cmp(match->compatible, "qcom,dwc3-ss-usb-phy", -+ strlen(match->compatible))) { -+ -+ if (of_property_read_u32(np, "rx_eq", &phy_dwc3->rx_eq) || -+ of_property_read_u32(np, "tx_deamp_3_5db", -+ &phy_dwc3->tx_deamp_3_5db) || -+ of_property_read_u32(np, "mpll", &phy_dwc3->mpll)) { -+ -+ dev_err(phy_dwc3->dev, "cannot get HSIO settings from device node, using default values\n"); -+ -+ /* Default HSIO settings */ -+ phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE; -+ phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB; -+ phy_dwc3->mpll = SSPHY_MPLL_VALUE; -+ } -+ } -+ -+ generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, -+ &data->ops); -+ -+ if (IS_ERR(generic_phy)) -+ return PTR_ERR(generic_phy); -+ -+ phy_set_drvdata(generic_phy, phy_dwc3); -+ platform_set_drvdata(pdev, phy_dwc3); -+ -+ phy_provider = devm_of_phy_provider_register(phy_dwc3->dev, -+ of_phy_simple_xlate); -+ -+ if (IS_ERR(phy_provider)) -+ return PTR_ERR(phy_provider); -+ -+ return 0; -+} -+ -+static struct platform_driver qcom_dwc3_phy_driver = { -+ .probe = qcom_dwc3_phy_probe, -+ .driver = { -+ .name = "qcom-dwc3-usb-phy", -+ .owner = THIS_MODULE, -+ .of_match_table = qcom_dwc3_phy_table, -+ }, -+}; -+ -+module_platform_driver(qcom_dwc3_phy_driver); -+ -+MODULE_ALIAS("platform:phy-qcom-dwc3"); -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Andy Gross "); -+MODULE_AUTHOR("Ivan T. Ivanov "); -+MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver"); diff --git a/target/linux/ipq806x/patches-4.19/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch b/target/linux/ipq806x/patches-4.19/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch deleted file mode 100644 index a6c7953aaa..0000000000 --- a/target/linux/ipq806x/patches-4.19/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 48051ece78136e4235a2415a52797db56f8a4478 Mon Sep 17 00:00:00 2001 -From: Mathieu Olivari -Date: Tue, 21 Apr 2015 19:09:07 -0700 -Subject: [PATCH 33/69] ARM: qcom: automatically select PCI_DOMAINS if PCI is - enabled - -If multiple PCIe devices are present in the system, the kernel will -panic at boot time when trying to scan the PCI buses. This happens on -IPQ806x based platforms, which has 3 PCIe ports. - -Enabling this option allows the kernel to assign the pci-domains -according to the device-tree content. This allows multiple PCIe -controllers to coexist in the system. - -Signed-off-by: Mathieu Olivari ---- - arch/arm/mach-qcom/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/mach-qcom/Kconfig -+++ b/arch/arm/mach-qcom/Kconfig -@@ -6,6 +6,7 @@ menuconfig ARCH_QCOM - select ARM_AMBA - select PINCTRL - select QCOM_SCM if SMP -+ select PCI_DOMAINS if PCI - help - Support for Qualcomm's devicetree based systems. - diff --git a/target/linux/ipq806x/patches-4.19/0034-0001-ARM-Add-Krait-L2-register-accessor-functions.patch b/target/linux/ipq806x/patches-4.19/0034-0001-ARM-Add-Krait-L2-register-accessor-functions.patch deleted file mode 100644 index 68acbeeec2..0000000000 --- a/target/linux/ipq806x/patches-4.19/0034-0001-ARM-Add-Krait-L2-register-accessor-functions.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 36d68f64c411e09788687d5919886aadeb92adca Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 14 Aug 2018 17:42:20 +0530 -Subject: [PATCH 01/12] ARM: Add Krait L2 register accessor functions - -Krait CPUs have a handful of L2 cache controller registers that -live behind a cp15 based indirection register. First you program -the indirection register (l2cpselr) to point the L2 'window' -register (l2cpdr) at what you want to read/write. Then you -read/write the 'window' register to do what you want. The -l2cpselr register is not banked per-cpu so we must lock around -accesses to it to prevent other CPUs from re-pointing l2cpdr -underneath us. - -Cc: Mark Rutland -Cc: Russell King -Acked-by: Bjorn Andersson -Signed-off-by: Stephen Boyd -Signed-off-by: Sricharan R -Tested-by: Craig Tatlor -Signed-off-by: Stephen Boyd ---- - arch/arm/common/Kconfig | 3 ++ - arch/arm/common/Makefile | 1 + - arch/arm/common/krait-l2-accessors.c | 48 +++++++++++++++++++++++ - arch/arm/include/asm/krait-l2-accessors.h | 9 +++++ - 4 files changed, 61 insertions(+) - create mode 100644 arch/arm/common/krait-l2-accessors.c - create mode 100644 arch/arm/include/asm/krait-l2-accessors.h - ---- a/arch/arm/common/Kconfig -+++ b/arch/arm/common/Kconfig -@@ -7,6 +7,9 @@ config DMABOUNCE - bool - select ZONE_DMA - -+config KRAIT_L2_ACCESSORS -+ bool -+ - config SHARP_LOCOMO - bool - ---- a/arch/arm/common/Makefile -+++ b/arch/arm/common/Makefile -@@ -7,6 +7,7 @@ obj-y += firmware.o - - obj-$(CONFIG_SA1111) += sa1111.o - obj-$(CONFIG_DMABOUNCE) += dmabounce.o -+obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o - obj-$(CONFIG_SHARP_LOCOMO) += locomo.o - obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o - obj-$(CONFIG_SHARP_SCOOP) += scoop.o ---- /dev/null -+++ b/arch/arm/common/krait-l2-accessors.c -@@ -0,0 +1,48 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// Copyright (c) 2018, The Linux Foundation. All rights reserved. -+ -+#include -+#include -+ -+#include -+#include -+ -+static DEFINE_RAW_SPINLOCK(krait_l2_lock); -+ -+void krait_set_l2_indirect_reg(u32 addr, u32 val) -+{ -+ unsigned long flags; -+ -+ raw_spin_lock_irqsave(&krait_l2_lock, flags); -+ /* -+ * Select the L2 window by poking l2cpselr, then write to the window -+ * via l2cpdr. -+ */ -+ asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr)); -+ isb(); -+ asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val)); -+ isb(); -+ -+ raw_spin_unlock_irqrestore(&krait_l2_lock, flags); -+} -+EXPORT_SYMBOL(krait_set_l2_indirect_reg); -+ -+u32 krait_get_l2_indirect_reg(u32 addr) -+{ -+ u32 val; -+ unsigned long flags; -+ -+ raw_spin_lock_irqsave(&krait_l2_lock, flags); -+ /* -+ * Select the L2 window by poking l2cpselr, then read from the window -+ * via l2cpdr. -+ */ -+ asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr)); -+ isb(); -+ asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val)); -+ -+ raw_spin_unlock_irqrestore(&krait_l2_lock, flags); -+ -+ return val; -+} -+EXPORT_SYMBOL(krait_get_l2_indirect_reg); ---- /dev/null -+++ b/arch/arm/include/asm/krait-l2-accessors.h -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+ -+#ifndef __ASMARM_KRAIT_L2_ACCESSORS_H -+#define __ASMARM_KRAIT_L2_ACCESSORS_H -+ -+extern void krait_set_l2_indirect_reg(u32 addr, u32 val); -+extern u32 krait_get_l2_indirect_reg(u32 addr); -+ -+#endif diff --git a/target/linux/ipq806x/patches-4.19/0034-0002-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch b/target/linux/ipq806x/patches-4.19/0034-0002-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch deleted file mode 100644 index d43d0c89b5..0000000000 --- a/target/linux/ipq806x/patches-4.19/0034-0002-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch +++ /dev/null @@ -1,324 +0,0 @@ -From b3f2f10693aadeacf83ab5be03810941a4b77612 Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 14 Aug 2018 17:42:21 +0530 -Subject: [PATCH 02/12] clk: qcom: Add support for High-Frequency PLLs (HFPLLs) - -HFPLLs are the main frequency source for Krait CPU clocks. Add -support for changing the rate of these PLLs. - -Signed-off-by: Stephen Boyd -Signed-off-by: Sricharan R -Tested-by: Craig Tatlor -Signed-off-by: Stephen Boyd ---- - drivers/clk/qcom/Makefile | 1 + - drivers/clk/qcom/clk-hfpll.c | 244 +++++++++++++++++++++++++++++++++++ - drivers/clk/qcom/clk-hfpll.h | 44 +++++++ - 3 files changed, 289 insertions(+) - create mode 100644 drivers/clk/qcom/clk-hfpll.c - create mode 100644 drivers/clk/qcom/clk-hfpll.h - ---- a/drivers/clk/qcom/Makefile -+++ b/drivers/clk/qcom/Makefile -@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o - clk-qcom-y += clk-regmap-divider.o - clk-qcom-y += clk-regmap-mux.o - clk-qcom-y += clk-regmap-mux-div.o -+clk-qcom-y += clk-hfpll.o - clk-qcom-y += reset.o - clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o - ---- /dev/null -+++ b/drivers/clk/qcom/clk-hfpll.c -@@ -0,0 +1,244 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// Copyright (c) 2018, The Linux Foundation. All rights reserved. -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-regmap.h" -+#include "clk-hfpll.h" -+ -+#define PLL_OUTCTRL BIT(0) -+#define PLL_BYPASSNL BIT(1) -+#define PLL_RESET_N BIT(2) -+ -+/* Initialize a HFPLL at a given rate and enable it. */ -+static void __clk_hfpll_init_once(struct clk_hw *hw) -+{ -+ struct clk_hfpll *h = to_clk_hfpll(hw); -+ struct hfpll_data const *hd = h->d; -+ struct regmap *regmap = h->clkr.regmap; -+ -+ if (likely(h->init_done)) -+ return; -+ -+ /* Configure PLL parameters for integer mode. */ -+ if (hd->config_val) -+ regmap_write(regmap, hd->config_reg, hd->config_val); -+ regmap_write(regmap, hd->m_reg, 0); -+ regmap_write(regmap, hd->n_reg, 1); -+ -+ if (hd->user_reg) { -+ u32 regval = hd->user_val; -+ unsigned long rate; -+ -+ rate = clk_hw_get_rate(hw); -+ -+ /* Pick the right VCO. */ -+ if (hd->user_vco_mask && rate > hd->low_vco_max_rate) -+ regval |= hd->user_vco_mask; -+ regmap_write(regmap, hd->user_reg, regval); -+ } -+ -+ if (hd->droop_reg) -+ regmap_write(regmap, hd->droop_reg, hd->droop_val); -+ -+ h->init_done = true; -+} -+ -+static void __clk_hfpll_enable(struct clk_hw *hw) -+{ -+ struct clk_hfpll *h = to_clk_hfpll(hw); -+ struct hfpll_data const *hd = h->d; -+ struct regmap *regmap = h->clkr.regmap; -+ u32 val; -+ -+ __clk_hfpll_init_once(hw); -+ -+ /* Disable PLL bypass mode. */ -+ regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL); -+ -+ /* -+ * H/W requires a 5us delay between disabling the bypass and -+ * de-asserting the reset. Delay 10us just to be safe. -+ */ -+ udelay(10); -+ -+ /* De-assert active-low PLL reset. */ -+ regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); -+ -+ /* Wait for PLL to lock. */ -+ if (hd->status_reg) { -+ do { -+ regmap_read(regmap, hd->status_reg, &val); -+ } while (!(val & BIT(hd->lock_bit))); -+ } else { -+ udelay(60); -+ } -+ -+ /* Enable PLL output. */ -+ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); -+} -+ -+/* Enable an already-configured HFPLL. */ -+static int clk_hfpll_enable(struct clk_hw *hw) -+{ -+ unsigned long flags; -+ struct clk_hfpll *h = to_clk_hfpll(hw); -+ struct hfpll_data const *hd = h->d; -+ struct regmap *regmap = h->clkr.regmap; -+ u32 mode; -+ -+ spin_lock_irqsave(&h->lock, flags); -+ regmap_read(regmap, hd->mode_reg, &mode); -+ if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) -+ __clk_hfpll_enable(hw); -+ spin_unlock_irqrestore(&h->lock, flags); -+ -+ return 0; -+} -+ -+static void __clk_hfpll_disable(struct clk_hfpll *h) -+{ -+ struct hfpll_data const *hd = h->d; -+ struct regmap *regmap = h->clkr.regmap; -+ -+ /* -+ * Disable the PLL output, disable test mode, enable the bypass mode, -+ * and assert the reset. -+ */ -+ regmap_update_bits(regmap, hd->mode_reg, -+ PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0); -+} -+ -+static void clk_hfpll_disable(struct clk_hw *hw) -+{ -+ struct clk_hfpll *h = to_clk_hfpll(hw); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&h->lock, flags); -+ __clk_hfpll_disable(h); -+ spin_unlock_irqrestore(&h->lock, flags); -+} -+ -+static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *parent_rate) -+{ -+ struct clk_hfpll *h = to_clk_hfpll(hw); -+ struct hfpll_data const *hd = h->d; -+ unsigned long rrate; -+ -+ rate = clamp(rate, hd->min_rate, hd->max_rate); -+ -+ rrate = DIV_ROUND_UP(rate, *parent_rate) * *parent_rate; -+ if (rrate > hd->max_rate) -+ rrate -= *parent_rate; -+ -+ return rrate; -+} -+ -+/* -+ * For optimization reasons, assumes no downstream clocks are actively using -+ * it. -+ */ -+static int clk_hfpll_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct clk_hfpll *h = to_clk_hfpll(hw); -+ struct hfpll_data const *hd = h->d; -+ struct regmap *regmap = h->clkr.regmap; -+ unsigned long flags; -+ u32 l_val, val; -+ bool enabled; -+ -+ l_val = rate / parent_rate; -+ -+ spin_lock_irqsave(&h->lock, flags); -+ -+ enabled = __clk_is_enabled(hw->clk); -+ if (enabled) -+ __clk_hfpll_disable(h); -+ -+ /* Pick the right VCO. */ -+ if (hd->user_reg && hd->user_vco_mask) { -+ regmap_read(regmap, hd->user_reg, &val); -+ if (rate <= hd->low_vco_max_rate) -+ val &= ~hd->user_vco_mask; -+ else -+ val |= hd->user_vco_mask; -+ regmap_write(regmap, hd->user_reg, val); -+ } -+ -+ regmap_write(regmap, hd->l_reg, l_val); -+ -+ if (enabled) -+ __clk_hfpll_enable(hw); -+ -+ spin_unlock_irqrestore(&h->lock, flags); -+ -+ return 0; -+} -+ -+static unsigned long clk_hfpll_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct clk_hfpll *h = to_clk_hfpll(hw); -+ struct hfpll_data const *hd = h->d; -+ struct regmap *regmap = h->clkr.regmap; -+ u32 l_val; -+ -+ regmap_read(regmap, hd->l_reg, &l_val); -+ -+ return l_val * parent_rate; -+} -+ -+static void clk_hfpll_init(struct clk_hw *hw) -+{ -+ struct clk_hfpll *h = to_clk_hfpll(hw); -+ struct hfpll_data const *hd = h->d; -+ struct regmap *regmap = h->clkr.regmap; -+ u32 mode, status; -+ -+ regmap_read(regmap, hd->mode_reg, &mode); -+ if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { -+ __clk_hfpll_init_once(hw); -+ return; -+ } -+ -+ if (hd->status_reg) { -+ regmap_read(regmap, hd->status_reg, &status); -+ if (!(status & BIT(hd->lock_bit))) { -+ WARN(1, "HFPLL %s is ON, but not locked!\n", -+ __clk_get_name(hw->clk)); -+ clk_hfpll_disable(hw); -+ __clk_hfpll_init_once(hw); -+ } -+ } -+} -+ -+static int hfpll_is_enabled(struct clk_hw *hw) -+{ -+ struct clk_hfpll *h = to_clk_hfpll(hw); -+ struct hfpll_data const *hd = h->d; -+ struct regmap *regmap = h->clkr.regmap; -+ u32 mode; -+ -+ regmap_read(regmap, hd->mode_reg, &mode); -+ mode &= 0x7; -+ return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); -+} -+ -+const struct clk_ops clk_ops_hfpll = { -+ .enable = clk_hfpll_enable, -+ .disable = clk_hfpll_disable, -+ .is_enabled = hfpll_is_enabled, -+ .round_rate = clk_hfpll_round_rate, -+ .set_rate = clk_hfpll_set_rate, -+ .recalc_rate = clk_hfpll_recalc_rate, -+ .init = clk_hfpll_init, -+}; -+EXPORT_SYMBOL_GPL(clk_ops_hfpll); ---- /dev/null -+++ b/drivers/clk/qcom/clk-hfpll.h -@@ -0,0 +1,44 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+ -+#ifndef __QCOM_CLK_HFPLL_H__ -+#define __QCOM_CLK_HFPLL_H__ -+ -+#include -+#include -+#include "clk-regmap.h" -+ -+struct hfpll_data { -+ u32 mode_reg; -+ u32 l_reg; -+ u32 m_reg; -+ u32 n_reg; -+ u32 user_reg; -+ u32 droop_reg; -+ u32 config_reg; -+ u32 status_reg; -+ u8 lock_bit; -+ -+ u32 droop_val; -+ u32 config_val; -+ u32 user_val; -+ u32 user_vco_mask; -+ unsigned long low_vco_max_rate; -+ -+ unsigned long min_rate; -+ unsigned long max_rate; -+}; -+ -+struct clk_hfpll { -+ struct hfpll_data const *d; -+ int init_done; -+ -+ struct clk_regmap clkr; -+ spinlock_t lock; -+}; -+ -+#define to_clk_hfpll(_hw) \ -+ container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr) -+ -+extern const struct clk_ops clk_ops_hfpll; -+ -+#endif diff --git a/target/linux/ipq806x/patches-4.19/0034-0003-clk-qcom-Add-HFPLL-driver.patch b/target/linux/ipq806x/patches-4.19/0034-0003-clk-qcom-Add-HFPLL-driver.patch deleted file mode 100644 index 292eb66d67..0000000000 --- a/target/linux/ipq806x/patches-4.19/0034-0003-clk-qcom-Add-HFPLL-driver.patch +++ /dev/null @@ -1,142 +0,0 @@ -From cb546b797a0da4dbb1a0c76a2a357921887b6189 Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 14 Aug 2018 17:42:22 +0530 -Subject: [PATCH 03/12] clk: qcom: Add HFPLL driver - -On some devices (MSM8974 for example), the HFPLLs are -instantiated within the Krait processor subsystem as separate -register regions. Add a driver for these PLLs so that we can -provide HFPLL clocks for use by the system. - -Cc: -Signed-off-by: Stephen Boyd -Signed-off-by: Sricharan R -Tested-by: Craig Tatlor -Signed-off-by: Stephen Boyd ---- - drivers/clk/qcom/Kconfig | 8 ++++ - drivers/clk/qcom/Makefile | 1 + - drivers/clk/qcom/hfpll.c | 96 +++++++++++++++++++++++++++++++++++++++ - 3 files changed, 105 insertions(+) - create mode 100644 drivers/clk/qcom/hfpll.c - ---- a/drivers/clk/qcom/Kconfig -+++ b/drivers/clk/qcom/Kconfig -@@ -272,3 +272,11 @@ config SPMI_PMIC_CLKDIV - Technologies, Inc. SPMI PMIC. It configures the frequency of - clkdiv outputs of the PMIC. These clocks are typically wired - through alternate functions on GPIO pins. -+ -+config QCOM_HFPLL -+ tristate "High-Frequency PLL (HFPLL) Clock Controller" -+ depends on COMMON_CLK_QCOM -+ help -+ Support for the high-frequency PLLs present on Qualcomm devices. -+ Say Y if you want to support CPU frequency scaling on devices -+ such as MSM8974, APQ8084, etc. ---- a/drivers/clk/qcom/Makefile -+++ b/drivers/clk/qcom/Makefile -@@ -44,3 +44,4 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-s - obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o - obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o - obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o -+obj-$(CONFIG_QCOM_HFPLL) += hfpll.o ---- /dev/null -+++ b/drivers/clk/qcom/hfpll.c -@@ -0,0 +1,96 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// Copyright (c) 2018, The Linux Foundation. All rights reserved. -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-regmap.h" -+#include "clk-hfpll.h" -+ -+static const struct hfpll_data hdata = { -+ .mode_reg = 0x00, -+ .l_reg = 0x04, -+ .m_reg = 0x08, -+ .n_reg = 0x0c, -+ .user_reg = 0x10, -+ .config_reg = 0x14, -+ .config_val = 0x430405d, -+ .status_reg = 0x1c, -+ .lock_bit = 16, -+ -+ .user_val = 0x8, -+ .user_vco_mask = 0x100000, -+ .low_vco_max_rate = 1248000000, -+ .min_rate = 537600000UL, -+ .max_rate = 2900000000UL, -+}; -+ -+static const struct of_device_id qcom_hfpll_match_table[] = { -+ { .compatible = "qcom,hfpll" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table); -+ -+static const struct regmap_config hfpll_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .max_register = 0x30, -+ .fast_io = true, -+}; -+ -+static int qcom_hfpll_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ struct device *dev = &pdev->dev; -+ void __iomem *base; -+ struct regmap *regmap; -+ struct clk_hfpll *h; -+ struct clk_init_data init = { -+ .parent_names = (const char *[]){ "xo" }, -+ .num_parents = 1, -+ .ops = &clk_ops_hfpll, -+ }; -+ -+ h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL); -+ if (!h) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(dev, res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config); -+ if (IS_ERR(regmap)) -+ return PTR_ERR(regmap); -+ -+ if (of_property_read_string_index(dev->of_node, "clock-output-names", -+ 0, &init.name)) -+ return -ENODEV; -+ -+ h->d = &hdata; -+ h->clkr.hw.init = &init; -+ spin_lock_init(&h->lock); -+ -+ return devm_clk_register_regmap(&pdev->dev, &h->clkr); -+} -+ -+static struct platform_driver qcom_hfpll_driver = { -+ .probe = qcom_hfpll_probe, -+ .driver = { -+ .name = "qcom-hfpll", -+ .of_match_table = qcom_hfpll_match_table, -+ }, -+}; -+module_platform_driver(qcom_hfpll_driver); -+ -+MODULE_DESCRIPTION("QCOM HFPLL Clock Driver"); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:qcom-hfpll"); diff --git a/target/linux/ipq806x/patches-4.19/0034-0004-dt-bindings-clock-Document-qcom-hfpll.patch b/target/linux/ipq806x/patches-4.19/0034-0004-dt-bindings-clock-Document-qcom-hfpll.patch deleted file mode 100644 index 1db989f6d9..0000000000 --- a/target/linux/ipq806x/patches-4.19/0034-0004-dt-bindings-clock-Document-qcom-hfpll.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 1f924faa8b1e4789ecc06ed0dd58ca3487c89012 Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 14 Aug 2018 17:42:23 +0530 -Subject: [PATCH 04/12] dt-bindings: clock: Document qcom,hfpll - -Adds bindings document for qcom,hfpll instantiated within -the Krait processor subsystem as separate register region. - -Reviewed-by: Rob Herring -Signed-off-by: Stephen Boyd -Signed-off-by: Sricharan R -Tested-by: Craig Tatlor -Signed-off-by: Stephen Boyd ---- - .../devicetree/bindings/clock/qcom,hfpll.txt | 60 +++++++++++++++++++ - 1 file changed, 60 insertions(+) - create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt -@@ -0,0 +1,60 @@ -+High-Frequency PLL (HFPLL) -+ -+PROPERTIES -+ -+- compatible: -+ Usage: required -+ Value type: : -+ shall contain only one of the following. The generic -+ compatible "qcom,hfpll" should be also included. -+ -+ "qcom,hfpll-ipq8064", "qcom,hfpll" -+ "qcom,hfpll-apq8064", "qcom,hfpll" -+ "qcom,hfpll-msm8974", "qcom,hfpll" -+ "qcom,hfpll-msm8960", "qcom,hfpll" -+ -+- reg: -+ Usage: required -+ Value type: -+ Definition: address and size of HPLL registers. An optional second -+ element specifies the address and size of the alias -+ register region. -+ -+- clocks: -+ Usage: required -+ Value type: -+ Definition: reference to the xo clock. -+ -+- clock-names: -+ Usage: required -+ Value type: -+ Definition: must be "xo". -+ -+- clock-output-names: -+ Usage: required -+ Value type: -+ Definition: Name of the PLL. Typically hfpllX where X is a CPU number -+ starting at 0. Otherwise hfpll_Y where Y is more specific -+ such as "l2". -+ -+Example: -+ -+1) An HFPLL for the L2 cache. -+ -+ clock-controller@f9016000 { -+ compatible = "qcom,hfpll-ipq8064", "qcom,hfpll"; -+ reg = <0xf9016000 0x30>; -+ clocks = <&xo_board>; -+ clock-names = "xo"; -+ clock-output-names = "hfpll_l2"; -+ }; -+ -+2) An HFPLL for CPU0. This HFPLL has the alias register region. -+ -+ clock-controller@f908a000 { -+ compatible = "qcom,hfpll-ipq8064", "qcom,hfpll"; -+ reg = <0xf908a000 0x30>, <0xf900a000 0x30>; -+ clocks = <&xo_board>; -+ clock-names = "xo"; -+ clock-output-names = "hfpll0"; -+ }; diff --git a/target/linux/ipq806x/patches-4.19/0034-0005-clk-qcom-Add-MSM8960-APQ8064-s-HFPLLs.patch b/target/linux/ipq806x/patches-4.19/0034-0005-clk-qcom-Add-MSM8960-APQ8064-s-HFPLLs.patch deleted file mode 100644 index 5ed5625f2e..0000000000 --- a/target/linux/ipq806x/patches-4.19/0034-0005-clk-qcom-Add-MSM8960-APQ8064-s-HFPLLs.patch +++ /dev/null @@ -1,236 +0,0 @@ -From 72ad7207954dd622a662ba884dc6c30a820123f2 Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 14 Aug 2018 17:42:24 +0530 -Subject: [PATCH 05/12] clk: qcom: Add MSM8960/APQ8064's HFPLLs - -Describe the HFPLLs present on MSM8960 and APQ8064 devices. - -Acked-by: Rob Herring (bindings) -Signed-off-by: Stephen Boyd -Signed-off-by: Sricharan R -Tested-by: Craig Tatlor -Signed-off-by: Stephen Boyd ---- - drivers/clk/qcom/gcc-msm8960.c | 172 +++++++++++++++++++ - include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 + - 2 files changed, 174 insertions(+) - ---- a/drivers/clk/qcom/gcc-msm8960.c -+++ b/drivers/clk/qcom/gcc-msm8960.c -@@ -30,6 +30,7 @@ - #include "clk-pll.h" - #include "clk-rcg.h" - #include "clk-branch.h" -+#include "clk-hfpll.h" - #include "reset.h" - - static struct clk_pll pll3 = { -@@ -86,6 +87,164 @@ static struct clk_regmap pll8_vote = { - }, - }; - -+static struct hfpll_data hfpll0_data = { -+ .mode_reg = 0x3200, -+ .l_reg = 0x3208, -+ .m_reg = 0x320c, -+ .n_reg = 0x3210, -+ .config_reg = 0x3204, -+ .status_reg = 0x321c, -+ .config_val = 0x7845c665, -+ .droop_reg = 0x3214, -+ .droop_val = 0x0108c000, -+ .min_rate = 600000000UL, -+ .max_rate = 1800000000UL, -+}; -+ -+static struct clk_hfpll hfpll0 = { -+ .d = &hfpll0_data, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .parent_names = (const char *[]){ "pxo" }, -+ .num_parents = 1, -+ .name = "hfpll0", -+ .ops = &clk_ops_hfpll, -+ .flags = CLK_IGNORE_UNUSED, -+ }, -+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock), -+}; -+ -+static struct hfpll_data hfpll1_8064_data = { -+ .mode_reg = 0x3240, -+ .l_reg = 0x3248, -+ .m_reg = 0x324c, -+ .n_reg = 0x3250, -+ .config_reg = 0x3244, -+ .status_reg = 0x325c, -+ .config_val = 0x7845c665, -+ .droop_reg = 0x3254, -+ .droop_val = 0x0108c000, -+ .min_rate = 600000000UL, -+ .max_rate = 1800000000UL, -+}; -+ -+static struct hfpll_data hfpll1_data = { -+ .mode_reg = 0x3300, -+ .l_reg = 0x3308, -+ .m_reg = 0x330c, -+ .n_reg = 0x3310, -+ .config_reg = 0x3304, -+ .status_reg = 0x331c, -+ .config_val = 0x7845c665, -+ .droop_reg = 0x3314, -+ .droop_val = 0x0108c000, -+ .min_rate = 600000000UL, -+ .max_rate = 1800000000UL, -+}; -+ -+static struct clk_hfpll hfpll1 = { -+ .d = &hfpll1_data, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .parent_names = (const char *[]){ "pxo" }, -+ .num_parents = 1, -+ .name = "hfpll1", -+ .ops = &clk_ops_hfpll, -+ .flags = CLK_IGNORE_UNUSED, -+ }, -+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock), -+}; -+ -+static struct hfpll_data hfpll2_data = { -+ .mode_reg = 0x3280, -+ .l_reg = 0x3288, -+ .m_reg = 0x328c, -+ .n_reg = 0x3290, -+ .config_reg = 0x3284, -+ .status_reg = 0x329c, -+ .config_val = 0x7845c665, -+ .droop_reg = 0x3294, -+ .droop_val = 0x0108c000, -+ .min_rate = 600000000UL, -+ .max_rate = 1800000000UL, -+}; -+ -+static struct clk_hfpll hfpll2 = { -+ .d = &hfpll2_data, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .parent_names = (const char *[]){ "pxo" }, -+ .num_parents = 1, -+ .name = "hfpll2", -+ .ops = &clk_ops_hfpll, -+ .flags = CLK_IGNORE_UNUSED, -+ }, -+ .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock), -+}; -+ -+static struct hfpll_data hfpll3_data = { -+ .mode_reg = 0x32c0, -+ .l_reg = 0x32c8, -+ .m_reg = 0x32cc, -+ .n_reg = 0x32d0, -+ .config_reg = 0x32c4, -+ .status_reg = 0x32dc, -+ .config_val = 0x7845c665, -+ .droop_reg = 0x32d4, -+ .droop_val = 0x0108c000, -+ .min_rate = 600000000UL, -+ .max_rate = 1800000000UL, -+}; -+ -+static struct clk_hfpll hfpll3 = { -+ .d = &hfpll3_data, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .parent_names = (const char *[]){ "pxo" }, -+ .num_parents = 1, -+ .name = "hfpll3", -+ .ops = &clk_ops_hfpll, -+ .flags = CLK_IGNORE_UNUSED, -+ }, -+ .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock), -+}; -+ -+static struct hfpll_data hfpll_l2_8064_data = { -+ .mode_reg = 0x3300, -+ .l_reg = 0x3308, -+ .m_reg = 0x330c, -+ .n_reg = 0x3310, -+ .config_reg = 0x3304, -+ .status_reg = 0x331c, -+ .config_val = 0x7845c665, -+ .droop_reg = 0x3314, -+ .droop_val = 0x0108c000, -+ .min_rate = 600000000UL, -+ .max_rate = 1800000000UL, -+}; -+ -+static struct hfpll_data hfpll_l2_data = { -+ .mode_reg = 0x3400, -+ .l_reg = 0x3408, -+ .m_reg = 0x340c, -+ .n_reg = 0x3410, -+ .config_reg = 0x3404, -+ .status_reg = 0x341c, -+ .config_val = 0x7845c665, -+ .droop_reg = 0x3414, -+ .droop_val = 0x0108c000, -+ .min_rate = 600000000UL, -+ .max_rate = 1800000000UL, -+}; -+ -+static struct clk_hfpll hfpll_l2 = { -+ .d = &hfpll_l2_data, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .parent_names = (const char *[]){ "pxo" }, -+ .num_parents = 1, -+ .name = "hfpll_l2", -+ .ops = &clk_ops_hfpll, -+ .flags = CLK_IGNORE_UNUSED, -+ }, -+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock), -+}; -+ - static struct clk_pll pll14 = { - .l_reg = 0x31c4, - .m_reg = 0x31c8, -@@ -3107,6 +3266,9 @@ static struct clk_regmap *gcc_msm8960_cl - [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, - [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, - [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, -+ [PLL9] = &hfpll0.clkr, -+ [PLL10] = &hfpll1.clkr, -+ [PLL12] = &hfpll_l2.clkr, - }; - - static const struct qcom_reset_map gcc_msm8960_resets[] = { -@@ -3318,6 +3480,11 @@ static struct clk_regmap *gcc_apq8064_cl - [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, - [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, - [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, -+ [PLL9] = &hfpll0.clkr, -+ [PLL10] = &hfpll1.clkr, -+ [PLL12] = &hfpll_l2.clkr, -+ [PLL16] = &hfpll2.clkr, -+ [PLL17] = &hfpll3.clkr, - }; - - static const struct qcom_reset_map gcc_apq8064_resets[] = { -@@ -3477,6 +3644,11 @@ static int gcc_msm8960_probe(struct plat - if (ret) - return ret; - -+ if (match->data == &gcc_apq8064_desc) { -+ hfpll1.d = &hfpll1_8064_data; -+ hfpll_l2.d = &hfpll_l2_8064_data; -+ } -+ - tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1, - NULL, 0); - if (IS_ERR(tsens)) ---- a/include/dt-bindings/clock/qcom,gcc-msm8960.h -+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h -@@ -319,5 +319,7 @@ - #define CE3_SRC 303 - #define CE3_CORE_CLK 304 - #define CE3_H_CLK 305 -+#define PLL16 306 -+#define PLL17 307 - - #endif diff --git a/target/linux/ipq806x/patches-4.19/0034-0006-clk-qcom-Add-IPQ806X-s-HFPLLs.patch b/target/linux/ipq806x/patches-4.19/0034-0006-clk-qcom-Add-IPQ806X-s-HFPLLs.patch deleted file mode 100644 index 74c66178a8..0000000000 --- a/target/linux/ipq806x/patches-4.19/0034-0006-clk-qcom-Add-IPQ806X-s-HFPLLs.patch +++ /dev/null @@ -1,120 +0,0 @@ -From 1f79131bfd512f322c16b58dca581ce39beafab9 Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 14 Aug 2018 17:42:25 +0530 -Subject: [PATCH 06/12] clk: qcom: Add IPQ806X's HFPLLs - -Describe the HFPLLs present on IPQ806X devices. - -Signed-off-by: Stephen Boyd -Signed-off-by: Sricharan R -Tested-by: Craig Tatlor -Signed-off-by: Stephen Boyd ---- - drivers/clk/qcom/gcc-ipq806x.c | 82 ++++++++++++++++++++++++++++++++++ - 1 file changed, 82 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -30,6 +30,7 @@ - #include "clk-pll.h" - #include "clk-rcg.h" - #include "clk-branch.h" -+#include "clk-hfpll.h" - #include "reset.h" - - static struct clk_pll pll0 = { -@@ -113,6 +114,84 @@ static struct clk_regmap pll8_vote = { - }, - }; - -+static struct hfpll_data hfpll0_data = { -+ .mode_reg = 0x3200, -+ .l_reg = 0x3208, -+ .m_reg = 0x320c, -+ .n_reg = 0x3210, -+ .config_reg = 0x3204, -+ .status_reg = 0x321c, -+ .config_val = 0x7845c665, -+ .droop_reg = 0x3214, -+ .droop_val = 0x0108c000, -+ .min_rate = 600000000UL, -+ .max_rate = 1800000000UL, -+}; -+ -+static struct clk_hfpll hfpll0 = { -+ .d = &hfpll0_data, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .parent_names = (const char *[]){ "pxo" }, -+ .num_parents = 1, -+ .name = "hfpll0", -+ .ops = &clk_ops_hfpll, -+ .flags = CLK_IGNORE_UNUSED, -+ }, -+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock), -+}; -+ -+static struct hfpll_data hfpll1_data = { -+ .mode_reg = 0x3240, -+ .l_reg = 0x3248, -+ .m_reg = 0x324c, -+ .n_reg = 0x3250, -+ .config_reg = 0x3244, -+ .status_reg = 0x325c, -+ .config_val = 0x7845c665, -+ .droop_reg = 0x3314, -+ .droop_val = 0x0108c000, -+ .min_rate = 600000000UL, -+ .max_rate = 1800000000UL, -+}; -+ -+static struct clk_hfpll hfpll1 = { -+ .d = &hfpll1_data, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .parent_names = (const char *[]){ "pxo" }, -+ .num_parents = 1, -+ .name = "hfpll1", -+ .ops = &clk_ops_hfpll, -+ .flags = CLK_IGNORE_UNUSED, -+ }, -+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock), -+}; -+ -+static struct hfpll_data hfpll_l2_data = { -+ .mode_reg = 0x3300, -+ .l_reg = 0x3308, -+ .m_reg = 0x330c, -+ .n_reg = 0x3310, -+ .config_reg = 0x3304, -+ .status_reg = 0x331c, -+ .config_val = 0x7845c665, -+ .droop_reg = 0x3314, -+ .droop_val = 0x0108c000, -+ .min_rate = 600000000UL, -+ .max_rate = 1800000000UL, -+}; -+ -+static struct clk_hfpll hfpll_l2 = { -+ .d = &hfpll_l2_data, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .parent_names = (const char *[]){ "pxo" }, -+ .num_parents = 1, -+ .name = "hfpll_l2", -+ .ops = &clk_ops_hfpll, -+ .flags = CLK_IGNORE_UNUSED, -+ }, -+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock), -+}; -+ - static struct clk_pll pll14 = { - .l_reg = 0x31c4, - .m_reg = 0x31c8, -@@ -2798,6 +2877,9 @@ static struct clk_regmap *gcc_ipq806x_cl - [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr, - [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr, - [NSSTCM_CLK] = &nss_tcm_clk.clkr, -+ [PLL9] = &hfpll0.clkr, -+ [PLL10] = &hfpll1.clkr, -+ [PLL12] = &hfpll_l2.clkr, - }; - - static const struct qcom_reset_map gcc_ipq806x_resets[] = { diff --git a/target/linux/ipq806x/patches-4.19/0034-0007-clk-qcom-Add-support-for-Krait-clocks.patch b/target/linux/ipq806x/patches-4.19/0034-0007-clk-qcom-Add-support-for-Krait-clocks.patch deleted file mode 100644 index 181b91f6eb..0000000000 --- a/target/linux/ipq806x/patches-4.19/0034-0007-clk-qcom-Add-support-for-Krait-clocks.patch +++ /dev/null @@ -1,213 +0,0 @@ -From 4d7dc77babfef1d6cb8fd825e2f17dc3384c3272 Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 14 Aug 2018 17:42:26 +0530 -Subject: [PATCH 07/12] clk: qcom: Add support for Krait clocks - -The Krait clocks are made up of a series of muxes and a divider -that choose between a fixed rate clock and dedicated HFPLLs for -each CPU. Instead of using mmio accesses to remux parents, the -Krait implementation exposes the remux control via cp15 -registers. Support these clocks. - -Signed-off-by: Stephen Boyd -Signed-off-by: Sricharan R -Tested-by: Craig Tatlor -[sboyd@kernel.org: Move hidden config to top outside of the visible qcom -config zone so that menuconfig looks nice] -Signed-off-by: Stephen Boyd ---- - drivers/clk/qcom/Kconfig | 4 ++ - drivers/clk/qcom/Makefile | 1 + - drivers/clk/qcom/clk-krait.c | 124 +++++++++++++++++++++++++++++++++++ - drivers/clk/qcom/clk-krait.h | 37 +++++++++++ - 4 files changed, 166 insertions(+) - create mode 100644 drivers/clk/qcom/clk-krait.c - create mode 100644 drivers/clk/qcom/clk-krait.h - ---- a/drivers/clk/qcom/Kconfig -+++ b/drivers/clk/qcom/Kconfig -@@ -1,3 +1,7 @@ -+config KRAIT_CLOCKS -+ bool -+ select KRAIT_L2_ACCESSORS -+ - config QCOM_GDSC - bool - select PM_GENERIC_DOMAINS if PM ---- a/drivers/clk/qcom/Makefile -+++ b/drivers/clk/qcom/Makefile -@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o - clk-qcom-y += clk-regmap-divider.o - clk-qcom-y += clk-regmap-mux.o - clk-qcom-y += clk-regmap-mux-div.o -+clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o - clk-qcom-y += clk-hfpll.o - clk-qcom-y += reset.o - clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o ---- /dev/null -+++ b/drivers/clk/qcom/clk-krait.c -@@ -0,0 +1,124 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// Copyright (c) 2018, The Linux Foundation. All rights reserved. -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "clk-krait.h" -+ -+/* Secondary and primary muxes share the same cp15 register */ -+static DEFINE_SPINLOCK(krait_clock_reg_lock); -+ -+#define LPL_SHIFT 8 -+static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) -+{ -+ unsigned long flags; -+ u32 regval; -+ -+ spin_lock_irqsave(&krait_clock_reg_lock, flags); -+ regval = krait_get_l2_indirect_reg(mux->offset); -+ regval &= ~(mux->mask << mux->shift); -+ regval |= (sel & mux->mask) << mux->shift; -+ if (mux->lpl) { -+ regval &= ~(mux->mask << (mux->shift + LPL_SHIFT)); -+ regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); -+ } -+ krait_set_l2_indirect_reg(mux->offset, regval); -+ spin_unlock_irqrestore(&krait_clock_reg_lock, flags); -+ -+ /* Wait for switch to complete. */ -+ mb(); -+ udelay(1); -+} -+ -+static int krait_mux_set_parent(struct clk_hw *hw, u8 index) -+{ -+ struct krait_mux_clk *mux = to_krait_mux_clk(hw); -+ u32 sel; -+ -+ sel = clk_mux_reindex(index, mux->parent_map, 0); -+ mux->en_mask = sel; -+ /* Don't touch mux if CPU is off as it won't work */ -+ if (__clk_is_enabled(hw->clk)) -+ __krait_mux_set_sel(mux, sel); -+ -+ return 0; -+} -+ -+static u8 krait_mux_get_parent(struct clk_hw *hw) -+{ -+ struct krait_mux_clk *mux = to_krait_mux_clk(hw); -+ u32 sel; -+ -+ sel = krait_get_l2_indirect_reg(mux->offset); -+ sel >>= mux->shift; -+ sel &= mux->mask; -+ mux->en_mask = sel; -+ -+ return clk_mux_get_parent(hw, sel, mux->parent_map, 0); -+} -+ -+const struct clk_ops krait_mux_clk_ops = { -+ .set_parent = krait_mux_set_parent, -+ .get_parent = krait_mux_get_parent, -+ .determine_rate = __clk_mux_determine_rate_closest, -+}; -+EXPORT_SYMBOL_GPL(krait_mux_clk_ops); -+ -+/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */ -+static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *parent_rate) -+{ -+ *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2); -+ return DIV_ROUND_UP(*parent_rate, 2); -+} -+ -+static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct krait_div2_clk *d = to_krait_div2_clk(hw); -+ unsigned long flags; -+ u32 val; -+ u32 mask = BIT(d->width) - 1; -+ -+ if (d->lpl) -+ mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift; -+ -+ spin_lock_irqsave(&krait_clock_reg_lock, flags); -+ val = krait_get_l2_indirect_reg(d->offset); -+ val &= ~mask; -+ krait_set_l2_indirect_reg(d->offset, val); -+ spin_unlock_irqrestore(&krait_clock_reg_lock, flags); -+ -+ return 0; -+} -+ -+static unsigned long -+krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -+{ -+ struct krait_div2_clk *d = to_krait_div2_clk(hw); -+ u32 mask = BIT(d->width) - 1; -+ u32 div; -+ -+ div = krait_get_l2_indirect_reg(d->offset); -+ div >>= d->shift; -+ div &= mask; -+ div = (div + 1) * 2; -+ -+ return DIV_ROUND_UP(parent_rate, div); -+} -+ -+const struct clk_ops krait_div2_clk_ops = { -+ .round_rate = krait_div2_round_rate, -+ .set_rate = krait_div2_set_rate, -+ .recalc_rate = krait_div2_recalc_rate, -+}; -+EXPORT_SYMBOL_GPL(krait_div2_clk_ops); ---- /dev/null -+++ b/drivers/clk/qcom/clk-krait.h -@@ -0,0 +1,37 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+ -+#ifndef __QCOM_CLK_KRAIT_H -+#define __QCOM_CLK_KRAIT_H -+ -+#include -+ -+struct krait_mux_clk { -+ unsigned int *parent_map; -+ u32 offset; -+ u32 mask; -+ u32 shift; -+ u32 en_mask; -+ bool lpl; -+ -+ struct clk_hw hw; -+ struct notifier_block clk_nb; -+}; -+ -+#define to_krait_mux_clk(_hw) container_of(_hw, struct krait_mux_clk, hw) -+ -+extern const struct clk_ops krait_mux_clk_ops; -+ -+struct krait_div2_clk { -+ u32 offset; -+ u8 width; -+ u32 shift; -+ bool lpl; -+ -+ struct clk_hw hw; -+}; -+ -+#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw) -+ -+extern const struct clk_ops krait_div2_clk_ops; -+ -+#endif diff --git a/target/linux/ipq806x/patches-4.19/0034-0008-clk-qcom-Add-KPSS-ACC-GCC-driver.patch b/target/linux/ipq806x/patches-4.19/0034-0008-clk-qcom-Add-KPSS-ACC-GCC-driver.patch deleted file mode 100644 index aa19ea2e3f..0000000000 --- a/target/linux/ipq806x/patches-4.19/0034-0008-clk-qcom-Add-KPSS-ACC-GCC-driver.patch +++ /dev/null @@ -1,134 +0,0 @@ -From 3ddc3564d3c9f097986bd4ccbe34152413811335 Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 14 Aug 2018 17:42:27 +0530 -Subject: [PATCH 08/12] clk: qcom: Add KPSS ACC/GCC driver - -The ACC and GCC regions present in KPSSv1 contain registers to -control clocks and power to each Krait CPU and L2. For CPUfreq -purposes probe these devices and expose a mux clock that chooses -between PXO and PLL8. - -Cc: -Signed-off-by: Stephen Boyd -Signed-off-by: Sricharan R -Tested-by: Craig Tatlor -Signed-off-by: Stephen Boyd ---- - drivers/clk/qcom/Kconfig | 8 ++++ - drivers/clk/qcom/Makefile | 1 + - drivers/clk/qcom/kpss-xcc.c | 87 +++++++++++++++++++++++++++++++++++++ - 3 files changed, 96 insertions(+) - create mode 100644 drivers/clk/qcom/kpss-xcc.c - ---- a/drivers/clk/qcom/Kconfig -+++ b/drivers/clk/qcom/Kconfig -@@ -284,3 +284,11 @@ config QCOM_HFPLL - Support for the high-frequency PLLs present on Qualcomm devices. - Say Y if you want to support CPU frequency scaling on devices - such as MSM8974, APQ8084, etc. -+ -+config KPSS_XCC -+ tristate "KPSS Clock Controller" -+ depends on COMMON_CLK_QCOM -+ help -+ Support for the Krait ACC and GCC clock controllers. Say Y -+ if you want to support CPU frequency scaling on devices such -+ as MSM8960, APQ8064, etc. ---- a/drivers/clk/qcom/Makefile -+++ b/drivers/clk/qcom/Makefile -@@ -45,4 +45,5 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-s - obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o - obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o - obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o -+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o - obj-$(CONFIG_QCOM_HFPLL) += hfpll.o ---- /dev/null -+++ b/drivers/clk/qcom/kpss-xcc.c -@@ -0,0 +1,87 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// Copyright (c) 2018, The Linux Foundation. All rights reserved. -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static const char *aux_parents[] = { -+ "pll8_vote", -+ "pxo", -+}; -+ -+static unsigned int aux_parent_map[] = { -+ 3, -+ 0, -+}; -+ -+static const struct of_device_id kpss_xcc_match_table[] = { -+ { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL }, -+ { .compatible = "qcom,kpss-gcc" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table); -+ -+static int kpss_xcc_driver_probe(struct platform_device *pdev) -+{ -+ const struct of_device_id *id; -+ struct clk *clk; -+ struct resource *res; -+ void __iomem *base; -+ const char *name; -+ -+ id = of_match_device(kpss_xcc_match_table, &pdev->dev); -+ if (!id) -+ return -ENODEV; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ if (id->data) { -+ if (of_property_read_string_index(pdev->dev.of_node, -+ "clock-output-names", -+ 0, &name)) -+ return -ENODEV; -+ base += 0x14; -+ } else { -+ name = "acpu_l2_aux"; -+ base += 0x28; -+ } -+ -+ clk = clk_register_mux_table(&pdev->dev, name, aux_parents, -+ ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, -+ 0, aux_parent_map, NULL); -+ -+ platform_set_drvdata(pdev, clk); -+ -+ return PTR_ERR_OR_ZERO(clk); -+} -+ -+static int kpss_xcc_driver_remove(struct platform_device *pdev) -+{ -+ clk_unregister_mux(platform_get_drvdata(pdev)); -+ return 0; -+} -+ -+static struct platform_driver kpss_xcc_driver = { -+ .probe = kpss_xcc_driver_probe, -+ .remove = kpss_xcc_driver_remove, -+ .driver = { -+ .name = "kpss-xcc", -+ .of_match_table = kpss_xcc_match_table, -+ }, -+}; -+module_platform_driver(kpss_xcc_driver); -+ -+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver"); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:kpss-xcc"); diff --git a/target/linux/ipq806x/patches-4.19/0034-0009-dt-bindings-arm-Document-qcom-kpss-gcc.patch b/target/linux/ipq806x/patches-4.19/0034-0009-dt-bindings-arm-Document-qcom-kpss-gcc.patch deleted file mode 100644 index 6af40895bc..0000000000 --- a/target/linux/ipq806x/patches-4.19/0034-0009-dt-bindings-arm-Document-qcom-kpss-gcc.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 40e5ddf4f84869815129551f4a8cfc2c223ebeae Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 14 Aug 2018 17:42:28 +0530 -Subject: [PATCH 09/12] dt-bindings: arm: Document qcom,kpss-gcc - -The ACC and GCC regions present in KPSSv1 contain registers to -control clocks and power to each Krait CPU and L2. Documenting -the bindings here. - -Reviewed-by: Rob Herring -Signed-off-by: Stephen Boyd -Signed-off-by: Sricharan R -Tested-by: Craig Tatlor -Signed-off-by: Stephen Boyd ---- - .../bindings/arm/msm/qcom,kpss-acc.txt | 19 ++++++++ - .../bindings/arm/msm/qcom,kpss-gcc.txt | 44 +++++++++++++++++++ - 2 files changed, 63 insertions(+) - create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt - ---- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt -+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt -@@ -21,10 +21,29 @@ PROPERTIES - the register region. An optional second element specifies - the base address and size of the alias register region. - -+- clocks: -+ Usage: required -+ Value type: -+ Definition: reference to the pll parents. -+ -+- clock-names: -+ Usage: required -+ Value type: -+ Definition: must be "pll8_vote", "pxo". -+ -+- clock-output-names: -+ Usage: optional -+ Value type: -+ Definition: Name of the output clock. Typically acpuX_aux where X is a -+ CPU number starting at 0. -+ - Example: - - clock-controller@2088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x02088000 0x1000>, - <0x02008000 0x1000>; -+ clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; -+ clock-names = "pll8_vote", "pxo"; -+ clock-output-names = "acpu0_aux"; - }; ---- /dev/null -+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt -@@ -0,0 +1,44 @@ -+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) -+ -+PROPERTIES -+ -+- compatible: -+ Usage: required -+ Value type: -+ Definition: should be one of the following. The generic compatible -+ "qcom,kpss-gcc" should also be included. -+ "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc" -+ "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc" -+ "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc" -+ "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc" -+ -+- reg: -+ Usage: required -+ Value type: -+ Definition: base address and size of the register region -+ -+- clocks: -+ Usage: required -+ Value type: -+ Definition: reference to the pll parents. -+ -+- clock-names: -+ Usage: required -+ Value type: -+ Definition: must be "pll8_vote", "pxo". -+ -+- clock-output-names: -+ Usage: required -+ Value type: -+ Definition: Name of the output clock. Typically acpu_l2_aux indicating -+ an L2 cache auxiliary clock. -+ -+Example: -+ -+ l2cc: clock-controller@2011000 { -+ compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; -+ reg = <0x2011000 0x1000>; -+ clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; -+ clock-names = "pll8_vote", "pxo"; -+ clock-output-names = "acpu_l2_aux"; -+ }; diff --git a/target/linux/ipq806x/patches-4.19/0034-0010-clk-qcom-Add-Krait-clock-controller-driver.patch b/target/linux/ipq806x/patches-4.19/0034-0010-clk-qcom-Add-Krait-clock-controller-driver.patch deleted file mode 100644 index 7ee1f50f41..0000000000 --- a/target/linux/ipq806x/patches-4.19/0034-0010-clk-qcom-Add-Krait-clock-controller-driver.patch +++ /dev/null @@ -1,409 +0,0 @@ -From bb5c4a85051e5e0be39c775b6df85521f2ae807d Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 14 Aug 2018 17:42:29 +0530 -Subject: [PATCH 10/12] clk: qcom: Add Krait clock controller driver - -The Krait CPU clocks are made up of a primary mux and secondary -mux for each CPU and the L2, controlled via cp15 accessors. For -Kraits within KPSSv1 each secondary mux accepts a different aux -source, but on KPSSv2 each secondary mux accepts the same aux -source. - -Cc: -Signed-off-by: Stephen Boyd -Signed-off-by: Sricharan R -Tested-by: Craig Tatlor -Signed-off-by: Stephen Boyd ---- - drivers/clk/qcom/Kconfig | 8 + - drivers/clk/qcom/Makefile | 1 + - drivers/clk/qcom/clk-krait.c | 4 +- - drivers/clk/qcom/krait-cc.c | 341 +++++++++++++++++++++++++++++++++++ - 4 files changed, 352 insertions(+), 2 deletions(-) - create mode 100644 drivers/clk/qcom/krait-cc.c - ---- a/drivers/clk/qcom/Kconfig -+++ b/drivers/clk/qcom/Kconfig -@@ -292,3 +292,11 @@ config KPSS_XCC - Support for the Krait ACC and GCC clock controllers. Say Y - if you want to support CPU frequency scaling on devices such - as MSM8960, APQ8064, etc. -+ -+config KRAITCC -+ tristate "Krait Clock Controller" -+ depends on COMMON_CLK_QCOM && ARM -+ select KRAIT_CLOCKS -+ help -+ Support for the Krait CPU clocks on Qualcomm devices. -+ Say Y if you want to support CPU frequency scaling. ---- a/drivers/clk/qcom/Makefile -+++ b/drivers/clk/qcom/Makefile -@@ -47,3 +47,4 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc - obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o - obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o - obj-$(CONFIG_QCOM_HFPLL) += hfpll.o -+obj-$(CONFIG_KRAITCC) += krait-cc.o ---- a/drivers/clk/qcom/clk-krait.c -+++ b/drivers/clk/qcom/clk-krait.c -@@ -44,7 +44,7 @@ static int krait_mux_set_parent(struct c - struct krait_mux_clk *mux = to_krait_mux_clk(hw); - u32 sel; - -- sel = clk_mux_reindex(index, mux->parent_map, 0); -+ sel = clk_mux_index_to_val(mux->parent_map, 0, index); - mux->en_mask = sel; - /* Don't touch mux if CPU is off as it won't work */ - if (__clk_is_enabled(hw->clk)) -@@ -63,7 +63,7 @@ static u8 krait_mux_get_parent(struct cl - sel &= mux->mask; - mux->en_mask = sel; - -- return clk_mux_get_parent(hw, sel, mux->parent_map, 0); -+ return clk_mux_val_to_index(hw, mux->parent_map, 0, sel); - } - - const struct clk_ops krait_mux_clk_ops = { ---- /dev/null -+++ b/drivers/clk/qcom/krait-cc.c -@@ -0,0 +1,341 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// Copyright (c) 2018, The Linux Foundation. All rights reserved. -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-krait.h" -+ -+static unsigned int sec_mux_map[] = { -+ 2, -+ 0, -+}; -+ -+static unsigned int pri_mux_map[] = { -+ 1, -+ 2, -+ 0, -+}; -+ -+static int -+krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) -+{ -+ struct krait_div2_clk *div; -+ struct clk_init_data init = { -+ .num_parents = 1, -+ .ops = &krait_div2_clk_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }; -+ const char *p_names[1]; -+ struct clk *clk; -+ -+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); -+ if (!div) -+ return -ENOMEM; -+ -+ div->width = 2; -+ div->shift = 6; -+ div->lpl = id >= 0; -+ div->offset = offset; -+ div->hw.init = &init; -+ -+ init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); -+ if (!init.name) -+ return -ENOMEM; -+ -+ init.parent_names = p_names; -+ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); -+ if (!p_names[0]) { -+ kfree(init.name); -+ return -ENOMEM; -+ } -+ -+ clk = devm_clk_register(dev, &div->hw); -+ kfree(p_names[0]); -+ kfree(init.name); -+ -+ return PTR_ERR_OR_ZERO(clk); -+} -+ -+static int -+krait_add_sec_mux(struct device *dev, int id, const char *s, -+ unsigned int offset, bool unique_aux) -+{ -+ struct krait_mux_clk *mux; -+ static const char *sec_mux_list[] = { -+ "acpu_aux", -+ "qsb", -+ }; -+ struct clk_init_data init = { -+ .parent_names = sec_mux_list, -+ .num_parents = ARRAY_SIZE(sec_mux_list), -+ .ops = &krait_mux_clk_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }; -+ struct clk *clk; -+ -+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); -+ if (!mux) -+ return -ENOMEM; -+ -+ mux->offset = offset; -+ mux->lpl = id >= 0; -+ mux->mask = 0x3; -+ mux->shift = 2; -+ mux->parent_map = sec_mux_map; -+ mux->hw.init = &init; -+ -+ init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); -+ if (!init.name) -+ return -ENOMEM; -+ -+ if (unique_aux) { -+ sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); -+ if (!sec_mux_list[0]) { -+ clk = ERR_PTR(-ENOMEM); -+ goto err_aux; -+ } -+ } -+ -+ clk = devm_clk_register(dev, &mux->hw); -+ -+ if (unique_aux) -+ kfree(sec_mux_list[0]); -+err_aux: -+ kfree(init.name); -+ return PTR_ERR_OR_ZERO(clk); -+} -+ -+static struct clk * -+krait_add_pri_mux(struct device *dev, int id, const char *s, -+ unsigned int offset) -+{ -+ struct krait_mux_clk *mux; -+ const char *p_names[3]; -+ struct clk_init_data init = { -+ .parent_names = p_names, -+ .num_parents = ARRAY_SIZE(p_names), -+ .ops = &krait_mux_clk_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }; -+ struct clk *clk; -+ -+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); -+ if (!mux) -+ return ERR_PTR(-ENOMEM); -+ -+ mux->mask = 0x3; -+ mux->shift = 0; -+ mux->offset = offset; -+ mux->lpl = id >= 0; -+ mux->parent_map = pri_mux_map; -+ mux->hw.init = &init; -+ -+ init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s); -+ if (!init.name) -+ return ERR_PTR(-ENOMEM); -+ -+ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); -+ if (!p_names[0]) { -+ clk = ERR_PTR(-ENOMEM); -+ goto err_p0; -+ } -+ -+ p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s); -+ if (!p_names[1]) { -+ clk = ERR_PTR(-ENOMEM); -+ goto err_p1; -+ } -+ -+ p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); -+ if (!p_names[2]) { -+ clk = ERR_PTR(-ENOMEM); -+ goto err_p2; -+ } -+ -+ clk = devm_clk_register(dev, &mux->hw); -+ -+ kfree(p_names[2]); -+err_p2: -+ kfree(p_names[1]); -+err_p1: -+ kfree(p_names[0]); -+err_p0: -+ kfree(init.name); -+ return clk; -+} -+ -+/* id < 0 for L2, otherwise id == physical CPU number */ -+static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) -+{ -+ int ret; -+ unsigned int offset; -+ void *p = NULL; -+ const char *s; -+ struct clk *clk; -+ -+ if (id >= 0) { -+ offset = 0x4501 + (0x1000 * id); -+ s = p = kasprintf(GFP_KERNEL, "%d", id); -+ if (!s) -+ return ERR_PTR(-ENOMEM); -+ } else { -+ offset = 0x500; -+ s = "_l2"; -+ } -+ -+ ret = krait_add_div(dev, id, s, offset); -+ if (ret) { -+ clk = ERR_PTR(ret); -+ goto err; -+ } -+ -+ ret = krait_add_sec_mux(dev, id, s, offset, unique_aux); -+ if (ret) { -+ clk = ERR_PTR(ret); -+ goto err; -+ } -+ -+ clk = krait_add_pri_mux(dev, id, s, offset); -+err: -+ kfree(p); -+ return clk; -+} -+ -+static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data) -+{ -+ unsigned int idx = clkspec->args[0]; -+ struct clk **clks = data; -+ -+ if (idx >= 5) { -+ pr_err("%s: invalid clock index %d\n", __func__, idx); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ return clks[idx] ? : ERR_PTR(-ENODEV); -+} -+ -+static const struct of_device_id krait_cc_match_table[] = { -+ { .compatible = "qcom,krait-cc-v1", (void *)1UL }, -+ { .compatible = "qcom,krait-cc-v2" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, krait_cc_match_table); -+ -+static int krait_cc_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ const struct of_device_id *id; -+ unsigned long cur_rate, aux_rate; -+ int cpu; -+ struct clk *clk; -+ struct clk **clks; -+ struct clk *l2_pri_mux_clk; -+ -+ id = of_match_device(krait_cc_match_table, dev); -+ if (!id) -+ return -ENODEV; -+ -+ /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ -+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); -+ if (IS_ERR(clk)) -+ return PTR_ERR(clk); -+ -+ if (!id->data) { -+ clk = clk_register_fixed_factor(dev, "acpu_aux", -+ "gpll0_vote", 0, 1, 2); -+ if (IS_ERR(clk)) -+ return PTR_ERR(clk); -+ } -+ -+ /* Krait configurations have at most 4 CPUs and one L2 */ -+ clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL); -+ if (!clks) -+ return -ENOMEM; -+ -+ for_each_possible_cpu(cpu) { -+ clk = krait_add_clks(dev, cpu, id->data); -+ if (IS_ERR(clk)) -+ return PTR_ERR(clk); -+ clks[cpu] = clk; -+ } -+ -+ l2_pri_mux_clk = krait_add_clks(dev, -1, id->data); -+ if (IS_ERR(l2_pri_mux_clk)) -+ return PTR_ERR(l2_pri_mux_clk); -+ clks[4] = l2_pri_mux_clk; -+ -+ /* -+ * We don't want the CPU or L2 clocks to be turned off at late init -+ * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the -+ * refcount of these clocks. Any cpufreq/hotplug manager can assume -+ * that the clocks have already been prepared and enabled by the time -+ * they take over. -+ */ -+ for_each_online_cpu(cpu) { -+ clk_prepare_enable(l2_pri_mux_clk); -+ WARN(clk_prepare_enable(clks[cpu]), -+ "Unable to turn on CPU%d clock", cpu); -+ } -+ -+ /* -+ * Force reinit of HFPLLs and muxes to overwrite any potential -+ * incorrect configuration of HFPLLs and muxes by the bootloader. -+ * While at it, also make sure the cores are running at known rates -+ * and print the current rate. -+ * -+ * The clocks are set to aux clock rate first to make sure the -+ * secondary mux is not sourcing off of QSB. The rate is then set to -+ * two different rates to force a HFPLL reinit under all -+ * circumstances. -+ */ -+ cur_rate = clk_get_rate(l2_pri_mux_clk); -+ aux_rate = 384000000; -+ if (cur_rate == 1) { -+ pr_info("L2 @ QSB rate. Forcing new rate.\n"); -+ cur_rate = aux_rate; -+ } -+ clk_set_rate(l2_pri_mux_clk, aux_rate); -+ clk_set_rate(l2_pri_mux_clk, 2); -+ clk_set_rate(l2_pri_mux_clk, cur_rate); -+ pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); -+ for_each_possible_cpu(cpu) { -+ clk = clks[cpu]; -+ cur_rate = clk_get_rate(clk); -+ if (cur_rate == 1) { -+ pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); -+ cur_rate = aux_rate; -+ } -+ -+ clk_set_rate(clk, aux_rate); -+ clk_set_rate(clk, 2); -+ clk_set_rate(clk, cur_rate); -+ pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); -+ } -+ -+ of_clk_add_provider(dev->of_node, krait_of_get, clks); -+ -+ return 0; -+} -+ -+static struct platform_driver krait_cc_driver = { -+ .probe = krait_cc_probe, -+ .driver = { -+ .name = "krait-cc", -+ .of_match_table = krait_cc_match_table, -+ }, -+}; -+module_platform_driver(krait_cc_driver); -+ -+MODULE_DESCRIPTION("Krait CPU Clock Driver"); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:krait-cc"); diff --git a/target/linux/ipq806x/patches-4.19/0034-0011-dt-bindings-clock-Document-qcom-krait-cc.patch b/target/linux/ipq806x/patches-4.19/0034-0011-dt-bindings-clock-Document-qcom-krait-cc.patch deleted file mode 100644 index 13e05c425a..0000000000 --- a/target/linux/ipq806x/patches-4.19/0034-0011-dt-bindings-clock-Document-qcom-krait-cc.patch +++ /dev/null @@ -1,55 +0,0 @@ -From bf4503ccf321811192cb07f9711556237c3cf668 Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 14 Aug 2018 17:42:30 +0530 -Subject: [PATCH 11/12] dt-bindings: clock: Document qcom,krait-cc - -The Krait clock controller controls the krait CPU and the L2 clocks -consisting a primary mux and secondary mux. Add document for that. - -Reviewed-by: Rob Herring -Signed-off-by: Stephen Boyd -Signed-off-by: Sricharan R -Tested-by: Craig Tatlor -Signed-off-by: Stephen Boyd ---- - .../bindings/clock/qcom,krait-cc.txt | 34 +++++++++++++++++++ - 1 file changed, 34 insertions(+) - create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt -@@ -0,0 +1,34 @@ -+Krait Clock Controller -+ -+PROPERTIES -+ -+- compatible: -+ Usage: required -+ Value type: -+ Definition: must be one of: -+ "qcom,krait-cc-v1" -+ "qcom,krait-cc-v2" -+ -+- #clock-cells: -+ Usage: required -+ Value type: -+ Definition: must be 1 -+ -+- clocks: -+ Usage: required -+ Value type: -+ Definition: reference to the clock parents of hfpll, secondary muxes. -+ -+- clock-names: -+ Usage: required -+ Value type: -+ Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb". -+ -+Example: -+ -+ kraitcc: clock-controller { -+ compatible = "qcom,krait-cc-v1"; -+ clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, ; -+ clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb"; -+ #clock-cells = <1>; -+ }; diff --git a/target/linux/ipq806x/patches-4.19/0034-0012-clk-qcom-Add-safe-switch-hook-for-krait-mux-clocks.patch b/target/linux/ipq806x/patches-4.19/0034-0012-clk-qcom-Add-safe-switch-hook-for-krait-mux-clocks.patch deleted file mode 100644 index 847b4809a3..0000000000 --- a/target/linux/ipq806x/patches-4.19/0034-0012-clk-qcom-Add-safe-switch-hook-for-krait-mux-clocks.patch +++ /dev/null @@ -1,152 +0,0 @@ -From 77612720a2362230af726baa4149c40ec7a7fb05 Mon Sep 17 00:00:00 2001 -From: Sricharan R -Date: Tue, 14 Aug 2018 17:42:31 +0530 -Subject: [PATCH 12/12] clk: qcom: Add safe switch hook for krait mux clocks - -When the Hfplls are reprogrammed during the rate change, -the primary muxes which are sourced from the same hfpll -for higher frequencies, needs to be switched to the 'safe -secondary mux' as the parent for that small window. This -is done by registering a clk notifier for the muxes and -switching to the safe parent in the PRE_RATE_CHANGE notifier -and back to the original parent in the POST_RATE_CHANGE notifier. - -Signed-off-by: Sricharan R -Tested-by: Craig Tatlor -Signed-off-by: Stephen Boyd ---- - drivers/clk/qcom/clk-krait.c | 2 ++ - drivers/clk/qcom/clk-krait.h | 3 ++ - drivers/clk/qcom/krait-cc.c | 56 ++++++++++++++++++++++++++++++++++++ - 3 files changed, 61 insertions(+) - ---- a/drivers/clk/qcom/clk-krait.c -+++ b/drivers/clk/qcom/clk-krait.c -@@ -50,6 +50,8 @@ static int krait_mux_set_parent(struct c - if (__clk_is_enabled(hw->clk)) - __krait_mux_set_sel(mux, sel); - -+ mux->reparent = true; -+ - return 0; - } - ---- a/drivers/clk/qcom/clk-krait.h -+++ b/drivers/clk/qcom/clk-krait.h -@@ -12,6 +12,9 @@ struct krait_mux_clk { - u32 shift; - u32 en_mask; - bool lpl; -+ u8 safe_sel; -+ u8 old_index; -+ bool reparent; - - struct clk_hw hw; - struct notifier_block clk_nb; ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -26,6 +26,49 @@ static unsigned int pri_mux_map[] = { - 0, - }; - -+/* -+ * Notifier function for switching the muxes to safe parent -+ * while the hfpll is getting reprogrammed. -+ */ -+static int krait_notifier_cb(struct notifier_block *nb, -+ unsigned long event, -+ void *data) -+{ -+ int ret = 0; -+ struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk, -+ clk_nb); -+ /* Switch to safe parent */ -+ if (event == PRE_RATE_CHANGE) { -+ mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw); -+ ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); -+ mux->reparent = false; -+ /* -+ * By the time POST_RATE_CHANGE notifier is called, -+ * clk framework itself would have changed the parent for the new rate. -+ * Only otherwise, put back to the old parent. -+ */ -+ } else if (event == POST_RATE_CHANGE) { -+ if (!mux->reparent) -+ ret = krait_mux_clk_ops.set_parent(&mux->hw, -+ mux->old_index); -+ } -+ -+ return notifier_from_errno(ret); -+} -+ -+static int krait_notifier_register(struct device *dev, struct clk *clk, -+ struct krait_mux_clk *mux) -+{ -+ int ret = 0; -+ -+ mux->clk_nb.notifier_call = krait_notifier_cb; -+ ret = clk_notifier_register(clk, &mux->clk_nb); -+ if (ret) -+ dev_err(dev, "failed to register clock notifier: %d\n", ret); -+ -+ return ret; -+} -+ - static int - krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) - { -@@ -70,6 +113,7 @@ static int - krait_add_sec_mux(struct device *dev, int id, const char *s, - unsigned int offset, bool unique_aux) - { -+ int ret; - struct krait_mux_clk *mux; - static const char *sec_mux_list[] = { - "acpu_aux", -@@ -93,6 +137,7 @@ krait_add_sec_mux(struct device *dev, in - mux->shift = 2; - mux->parent_map = sec_mux_map; - mux->hw.init = &init; -+ mux->safe_sel = 0; - - init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); - if (!init.name) -@@ -108,6 +153,11 @@ krait_add_sec_mux(struct device *dev, in - - clk = devm_clk_register(dev, &mux->hw); - -+ ret = krait_notifier_register(dev, clk, mux); -+ if (ret) -+ goto unique_aux; -+ -+unique_aux: - if (unique_aux) - kfree(sec_mux_list[0]); - err_aux: -@@ -119,6 +169,7 @@ static struct clk * - krait_add_pri_mux(struct device *dev, int id, const char *s, - unsigned int offset) - { -+ int ret; - struct krait_mux_clk *mux; - const char *p_names[3]; - struct clk_init_data init = { -@@ -139,6 +190,7 @@ krait_add_pri_mux(struct device *dev, in - mux->lpl = id >= 0; - mux->parent_map = pri_mux_map; - mux->hw.init = &init; -+ mux->safe_sel = 2; - - init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s); - if (!init.name) -@@ -164,6 +216,10 @@ krait_add_pri_mux(struct device *dev, in - - clk = devm_clk_register(dev, &mux->hw); - -+ ret = krait_notifier_register(dev, clk, mux); -+ if (ret) -+ goto err_p3; -+err_p3: - kfree(p_names[2]); - err_p2: - kfree(p_names[1]); diff --git a/target/linux/ipq806x/patches-4.19/0035-qcom-cpufreq-nvmem-qcm-kyrp_make_Some_variables_static.patch b/target/linux/ipq806x/patches-4.19/0035-qcom-cpufreq-nvmem-qcm-kyrp_make_Some_variables_static.patch deleted file mode 100644 index a51153b2aa..0000000000 --- a/target/linux/ipq806x/patches-4.19/0035-qcom-cpufreq-nvmem-qcm-kyrp_make_Some_variables_static.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 50c0b12f098fb3cfac7abcc0f2b5409f6bac5fa2 Mon Sep 17 00:00:00 2001 -From: Yangtao Li -Date: Mon, 4 Feb 2019 01:13:10 -0500 -Subject: [PATCH] cpufreq: qcom-kryo: make some variables static - -The variables are local to the source and do not -need to be in global scope, so make them static. - -Signed-off-by: Yangtao Li -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/qcom-cpufreq-kryo.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/cpufreq/qcom-cpufreq-kryo.c -+++ b/drivers/cpufreq/qcom-cpufreq-kryo.c -@@ -42,7 +42,7 @@ enum _msm8996_version { - NUM_OF_MSM8996_VERSIONS, - }; - --struct platform_device *cpufreq_dt_pdev, *kryo_cpufreq_pdev; -+static struct platform_device *cpufreq_dt_pdev, *kryo_cpufreq_pdev; - - static enum _msm8996_version qcom_cpufreq_kryo_get_msm_id(void) - { diff --git a/target/linux/ipq806x/patches-4.19/0036-qcom-cpufreq-nvmem-Re-organise-kryo-cpufreq-driver.patch b/target/linux/ipq806x/patches-4.19/0036-qcom-cpufreq-nvmem-Re-organise-kryo-cpufreq-driver.patch deleted file mode 100644 index c7e4569616..0000000000 --- a/target/linux/ipq806x/patches-4.19/0036-qcom-cpufreq-nvmem-Re-organise-kryo-cpufreq-driver.patch +++ /dev/null @@ -1,579 +0,0 @@ -From 7d12709544b8b3fb9727a34a664b8380e1e3493a Mon Sep 17 00:00:00 2001 -From: Sricharan R -Date: Thu, 25 Jul 2019 12:41:31 +0200 -Subject: [PATCH] cpufreq: qcom: Re-organise kryo cpufreq to use it for other - nvmem based qcom socs - -The kryo cpufreq driver reads the nvmem cell and uses that data to -populate the opps. There are other qcom cpufreq socs like krait which -does similar thing. Except for the interpretation of the read data, -rest of the driver is same for both the cases. So pull the common things -out for reuse. - -Signed-off-by: Sricharan R -[niklas.cassel@linaro.org: split dt-binding into a separate patch and -do not rename the compatible string. Update MAINTAINERS file.] -Signed-off-by: Niklas Cassel -Reviewed-by: Ilia Lin -Reviewed-by: Stephen Boyd -Signed-off-by: Viresh Kumar ---- - MAINTAINERS | 4 +- - drivers/cpufreq/Kconfig.arm | 4 +- - drivers/cpufreq/Makefile | 2 +- - ...om-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 122 +++++++++++------- - 4 files changed, 78 insertions(+), 54 deletions(-) - rename drivers/cpufreq/{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} (69%) - ---- a/drivers/cpufreq/Kconfig.arm -+++ b/drivers/cpufreq/Kconfig.arm -@@ -110,8 +110,8 @@ config ARM_OMAP2PLUS_CPUFREQ - depends on ARCH_OMAP2PLUS - default ARCH_OMAP2PLUS - --config ARM_QCOM_CPUFREQ_KRYO -- tristate "Qualcomm Kryo based CPUFreq" -+config ARM_QCOM_CPUFREQ_NVMEM -+ tristate "Qualcomm nvmem based CPUFreq" - depends on ARM64 - depends on QCOM_QFPROM - depends on QCOM_SMEM ---- a/drivers/cpufreq/Makefile -+++ b/drivers/cpufreq/Makefile -@@ -64,7 +64,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cp - obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o - obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o - obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o --obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o -+obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o - obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o - obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o - obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o ---- a/drivers/cpufreq/qcom-cpufreq-kryo.c -+++ /dev/null -@@ -1,249 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0 --/* -- * Copyright (c) 2018, The Linux Foundation. All rights reserved. -- */ -- --/* -- * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, -- * the CPU frequency subset and voltage value of each OPP varies -- * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables -- * defines the voltage and frequency value based on the msm-id in SMEM -- * and speedbin blown in the efuse combination. -- * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC -- * to provide the OPP framework with required information. -- * This is used to determine the voltage and frequency value for each OPP of -- * operating-points-v2 table when it is parsed by the OPP framework. -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include -- --#define MSM_ID_SMEM 137 -- --enum _msm_id { -- MSM8996V3 = 0xF6ul, -- APQ8096V3 = 0x123ul, -- MSM8996SG = 0x131ul, -- APQ8096SG = 0x138ul, --}; -- --enum _msm8996_version { -- MSM8996_V3, -- MSM8996_SG, -- NUM_OF_MSM8996_VERSIONS, --}; -- --static struct platform_device *cpufreq_dt_pdev, *kryo_cpufreq_pdev; -- --static enum _msm8996_version qcom_cpufreq_kryo_get_msm_id(void) --{ -- size_t len; -- u32 *msm_id; -- enum _msm8996_version version; -- -- msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len); -- if (IS_ERR(msm_id)) -- return NUM_OF_MSM8996_VERSIONS; -- -- /* The first 4 bytes are format, next to them is the actual msm-id */ -- msm_id++; -- -- switch ((enum _msm_id)*msm_id) { -- case MSM8996V3: -- case APQ8096V3: -- version = MSM8996_V3; -- break; -- case MSM8996SG: -- case APQ8096SG: -- version = MSM8996_SG; -- break; -- default: -- version = NUM_OF_MSM8996_VERSIONS; -- } -- -- return version; --} -- --static int qcom_cpufreq_kryo_probe(struct platform_device *pdev) --{ -- struct opp_table **opp_tables; -- enum _msm8996_version msm8996_version; -- struct nvmem_cell *speedbin_nvmem; -- struct device_node *np; -- struct device *cpu_dev; -- unsigned cpu; -- u8 *speedbin; -- u32 versions; -- size_t len; -- int ret; -- -- cpu_dev = get_cpu_device(0); -- if (!cpu_dev) -- return -ENODEV; -- -- msm8996_version = qcom_cpufreq_kryo_get_msm_id(); -- if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { -- dev_err(cpu_dev, "Not Snapdragon 820/821!"); -- return -ENODEV; -- } -- -- np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); -- if (!np) -- return -ENOENT; -- -- ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); -- if (!ret) { -- of_node_put(np); -- return -ENOENT; -- } -- -- speedbin_nvmem = of_nvmem_cell_get(np, NULL); -- of_node_put(np); -- if (IS_ERR(speedbin_nvmem)) { -- if (PTR_ERR(speedbin_nvmem) != -EPROBE_DEFER) -- dev_err(cpu_dev, "Could not get nvmem cell: %ld\n", -- PTR_ERR(speedbin_nvmem)); -- return PTR_ERR(speedbin_nvmem); -- } -- -- speedbin = nvmem_cell_read(speedbin_nvmem, &len); -- nvmem_cell_put(speedbin_nvmem); -- if (IS_ERR(speedbin)) -- return PTR_ERR(speedbin); -- -- switch (msm8996_version) { -- case MSM8996_V3: -- versions = 1 << (unsigned int)(*speedbin); -- break; -- case MSM8996_SG: -- versions = 1 << ((unsigned int)(*speedbin) + 4); -- break; -- default: -- BUG(); -- break; -- } -- kfree(speedbin); -- -- opp_tables = kcalloc(num_possible_cpus(), sizeof(*opp_tables), GFP_KERNEL); -- if (!opp_tables) -- return -ENOMEM; -- -- for_each_possible_cpu(cpu) { -- cpu_dev = get_cpu_device(cpu); -- if (NULL == cpu_dev) { -- ret = -ENODEV; -- goto free_opp; -- } -- -- opp_tables[cpu] = dev_pm_opp_set_supported_hw(cpu_dev, -- &versions, 1); -- if (IS_ERR(opp_tables[cpu])) { -- ret = PTR_ERR(opp_tables[cpu]); -- dev_err(cpu_dev, "Failed to set supported hardware\n"); -- goto free_opp; -- } -- } -- -- cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, -- NULL, 0); -- if (!IS_ERR(cpufreq_dt_pdev)) { -- platform_set_drvdata(pdev, opp_tables); -- return 0; -- } -- -- ret = PTR_ERR(cpufreq_dt_pdev); -- dev_err(cpu_dev, "Failed to register platform device\n"); -- --free_opp: -- for_each_possible_cpu(cpu) { -- if (IS_ERR_OR_NULL(opp_tables[cpu])) -- break; -- dev_pm_opp_put_supported_hw(opp_tables[cpu]); -- } -- kfree(opp_tables); -- -- return ret; --} -- --static int qcom_cpufreq_kryo_remove(struct platform_device *pdev) --{ -- struct opp_table **opp_tables = platform_get_drvdata(pdev); -- unsigned int cpu; -- -- platform_device_unregister(cpufreq_dt_pdev); -- -- for_each_possible_cpu(cpu) -- dev_pm_opp_put_supported_hw(opp_tables[cpu]); -- -- kfree(opp_tables); -- -- return 0; --} -- --static struct platform_driver qcom_cpufreq_kryo_driver = { -- .probe = qcom_cpufreq_kryo_probe, -- .remove = qcom_cpufreq_kryo_remove, -- .driver = { -- .name = "qcom-cpufreq-kryo", -- }, --}; -- --static const struct of_device_id qcom_cpufreq_kryo_match_list[] __initconst = { -- { .compatible = "qcom,apq8096", }, -- { .compatible = "qcom,msm8996", }, -- {} --}; -- --/* -- * Since the driver depends on smem and nvmem drivers, which may -- * return EPROBE_DEFER, all the real activity is done in the probe, -- * which may be defered as well. The init here is only registering -- * the driver and the platform device. -- */ --static int __init qcom_cpufreq_kryo_init(void) --{ -- struct device_node *np = of_find_node_by_path("/"); -- const struct of_device_id *match; -- int ret; -- -- if (!np) -- return -ENODEV; -- -- match = of_match_node(qcom_cpufreq_kryo_match_list, np); -- of_node_put(np); -- if (!match) -- return -ENODEV; -- -- ret = platform_driver_register(&qcom_cpufreq_kryo_driver); -- if (unlikely(ret < 0)) -- return ret; -- -- kryo_cpufreq_pdev = platform_device_register_simple( -- "qcom-cpufreq-kryo", -1, NULL, 0); -- ret = PTR_ERR_OR_ZERO(kryo_cpufreq_pdev); -- if (0 == ret) -- return 0; -- -- platform_driver_unregister(&qcom_cpufreq_kryo_driver); -- return ret; --} --module_init(qcom_cpufreq_kryo_init); -- --static void __exit qcom_cpufreq_kryo_exit(void) --{ -- platform_device_unregister(kryo_cpufreq_pdev); -- platform_driver_unregister(&qcom_cpufreq_kryo_driver); --} --module_exit(qcom_cpufreq_kryo_exit); -- --MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver"); --MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c -@@ -0,0 +1,273 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2018, The Linux Foundation. All rights reserved. -+ */ -+ -+/* -+ * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, -+ * the CPU frequency subset and voltage value of each OPP varies -+ * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables -+ * defines the voltage and frequency value based on the msm-id in SMEM -+ * and speedbin blown in the efuse combination. -+ * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC -+ * to provide the OPP framework with required information. -+ * This is used to determine the voltage and frequency value for each OPP of -+ * operating-points-v2 table when it is parsed by the OPP framework. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MSM_ID_SMEM 137 -+ -+enum _msm_id { -+ MSM8996V3 = 0xF6ul, -+ APQ8096V3 = 0x123ul, -+ MSM8996SG = 0x131ul, -+ APQ8096SG = 0x138ul, -+}; -+ -+enum _msm8996_version { -+ MSM8996_V3, -+ MSM8996_SG, -+ NUM_OF_MSM8996_VERSIONS, -+}; -+ -+static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; -+ -+static enum _msm8996_version qcom_cpufreq_get_msm_id(void) -+{ -+ size_t len; -+ u32 *msm_id; -+ enum _msm8996_version version; -+ -+ msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len); -+ if (IS_ERR(msm_id)) -+ return NUM_OF_MSM8996_VERSIONS; -+ -+ /* The first 4 bytes are format, next to them is the actual msm-id */ -+ msm_id++; -+ -+ switch ((enum _msm_id)*msm_id) { -+ case MSM8996V3: -+ case APQ8096V3: -+ version = MSM8996_V3; -+ break; -+ case MSM8996SG: -+ case APQ8096SG: -+ version = MSM8996_SG; -+ break; -+ default: -+ version = NUM_OF_MSM8996_VERSIONS; -+ } -+ -+ return version; -+} -+ -+static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, -+ struct nvmem_cell *speedbin_nvmem, -+ u32 *versions) -+{ -+ size_t len; -+ u8 *speedbin; -+ enum _msm8996_version msm8996_version; -+ -+ msm8996_version = qcom_cpufreq_get_msm_id(); -+ if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { -+ dev_err(cpu_dev, "Not Snapdragon 820/821!"); -+ return -ENODEV; -+ } -+ -+ speedbin = nvmem_cell_read(speedbin_nvmem, &len); -+ if (IS_ERR(speedbin)) -+ return PTR_ERR(speedbin); -+ -+ switch (msm8996_version) { -+ case MSM8996_V3: -+ *versions = 1 << (unsigned int)(*speedbin); -+ break; -+ case MSM8996_SG: -+ *versions = 1 << ((unsigned int)(*speedbin) + 4); -+ break; -+ default: -+ BUG(); -+ break; -+ } -+ -+ kfree(speedbin); -+ return 0; -+} -+ -+static int qcom_cpufreq_probe(struct platform_device *pdev) -+{ -+ struct opp_table **opp_tables; -+ int (*get_version)(struct device *cpu_dev, -+ struct nvmem_cell *speedbin_nvmem, -+ u32 *versions); -+ struct nvmem_cell *speedbin_nvmem; -+ struct device_node *np; -+ struct device *cpu_dev; -+ unsigned cpu; -+ u32 versions; -+ const struct of_device_id *match; -+ int ret; -+ -+ cpu_dev = get_cpu_device(0); -+ if (!cpu_dev) -+ return -ENODEV; -+ -+ match = pdev->dev.platform_data; -+ get_version = match->data; -+ if (!get_version) -+ return -ENODEV; -+ -+ np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); -+ if (!np) -+ return -ENOENT; -+ -+ ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); -+ if (!ret) { -+ of_node_put(np); -+ return -ENOENT; -+ } -+ -+ speedbin_nvmem = of_nvmem_cell_get(np, NULL); -+ of_node_put(np); -+ if (IS_ERR(speedbin_nvmem)) { -+ if (PTR_ERR(speedbin_nvmem) != -EPROBE_DEFER) -+ dev_err(cpu_dev, "Could not get nvmem cell: %ld\n", -+ PTR_ERR(speedbin_nvmem)); -+ return PTR_ERR(speedbin_nvmem); -+ } -+ -+ ret = get_version(cpu_dev, speedbin_nvmem, &versions); -+ nvmem_cell_put(speedbin_nvmem); -+ if (ret) -+ return ret; -+ -+ opp_tables = kcalloc(num_possible_cpus(), sizeof(*opp_tables), GFP_KERNEL); -+ if (!opp_tables) -+ return -ENOMEM; -+ -+ for_each_possible_cpu(cpu) { -+ cpu_dev = get_cpu_device(cpu); -+ if (NULL == cpu_dev) { -+ ret = -ENODEV; -+ goto free_opp; -+ } -+ -+ opp_tables[cpu] = dev_pm_opp_set_supported_hw(cpu_dev, -+ &versions, 1); -+ if (IS_ERR(opp_tables[cpu])) { -+ ret = PTR_ERR(opp_tables[cpu]); -+ dev_err(cpu_dev, "Failed to set supported hardware\n"); -+ goto free_opp; -+ } -+ } -+ -+ cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, -+ NULL, 0); -+ if (!IS_ERR(cpufreq_dt_pdev)) { -+ platform_set_drvdata(pdev, opp_tables); -+ return 0; -+ } -+ -+ ret = PTR_ERR(cpufreq_dt_pdev); -+ dev_err(cpu_dev, "Failed to register platform device\n"); -+ -+free_opp: -+ for_each_possible_cpu(cpu) { -+ if (IS_ERR_OR_NULL(opp_tables[cpu])) -+ break; -+ dev_pm_opp_put_supported_hw(opp_tables[cpu]); -+ } -+ kfree(opp_tables); -+ -+ return ret; -+} -+ -+static int qcom_cpufreq_remove(struct platform_device *pdev) -+{ -+ struct opp_table **opp_tables = platform_get_drvdata(pdev); -+ unsigned int cpu; -+ -+ platform_device_unregister(cpufreq_dt_pdev); -+ -+ for_each_possible_cpu(cpu) -+ dev_pm_opp_put_supported_hw(opp_tables[cpu]); -+ -+ kfree(opp_tables); -+ -+ return 0; -+} -+ -+static struct platform_driver qcom_cpufreq_driver = { -+ .probe = qcom_cpufreq_probe, -+ .remove = qcom_cpufreq_remove, -+ .driver = { -+ .name = "qcom-cpufreq-nvmem", -+ }, -+}; -+ -+static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { -+ { .compatible = "qcom,apq8096", -+ .data = qcom_cpufreq_kryo_name_version }, -+ { .compatible = "qcom,msm8996", -+ .data = qcom_cpufreq_kryo_name_version }, -+ {}, -+}; -+ -+/* -+ * Since the driver depends on smem and nvmem drivers, which may -+ * return EPROBE_DEFER, all the real activity is done in the probe, -+ * which may be defered as well. The init here is only registering -+ * the driver and the platform device. -+ */ -+static int __init qcom_cpufreq_init(void) -+{ -+ struct device_node *np = of_find_node_by_path("/"); -+ const struct of_device_id *match; -+ int ret; -+ -+ if (!np) -+ return -ENODEV; -+ -+ match = of_match_node(qcom_cpufreq_match_list, np); -+ of_node_put(np); -+ if (!match) -+ return -ENODEV; -+ -+ ret = platform_driver_register(&qcom_cpufreq_driver); -+ if (unlikely(ret < 0)) -+ return ret; -+ -+ cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem", -+ -1, match, sizeof(*match)); -+ ret = PTR_ERR_OR_ZERO(cpufreq_pdev); -+ if (0 == ret) -+ return 0; -+ -+ platform_driver_unregister(&qcom_cpufreq_driver); -+ return ret; -+} -+module_init(qcom_cpufreq_init); -+ -+static void __exit qcom_cpufreq_exit(void) -+{ -+ platform_device_unregister(cpufreq_pdev); -+ platform_driver_unregister(&qcom_cpufreq_driver); -+} -+module_exit(qcom_cpufreq_exit); -+ -+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-4.19/0037-qcom-cpufreq-nvmem-Refactor-the-driver.patch b/target/linux/ipq806x/patches-4.19/0037-qcom-cpufreq-nvmem-Refactor-the-driver.patch deleted file mode 100644 index d00b2ccfcb..0000000000 --- a/target/linux/ipq806x/patches-4.19/0037-qcom-cpufreq-nvmem-Refactor-the-driver.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 57f2f8b4aa0c6b41a284da82bfa40dc3b2abe9a5 Mon Sep 17 00:00:00 2001 -From: Niklas Cassel -Date: Thu, 25 Jul 2019 12:41:33 +0200 -Subject: [PATCH] cpufreq: qcom: Refactor the driver to make it easier to - extend - -Refactor the driver to make it easier to extend in a later commit. - -Create a driver struct to collect all common resources, in order to make -it easier to free up all common resources. -Create a driver match_data struct to make it easier to extend the driver -with support for new features that might only be supported on certain SoCs. - -Co-developed-by: Jorge Ramirez-Ortiz -Signed-off-by: Jorge Ramirez-Ortiz -Signed-off-by: Niklas Cassel -Reviewed-by: Ilia Lin -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/qcom-cpufreq-nvmem.c | 123 +++++++++++++++++---------- - 1 file changed, 79 insertions(+), 44 deletions(-) - ---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c -+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c -@@ -43,6 +43,20 @@ enum _msm8996_version { - NUM_OF_MSM8996_VERSIONS, - }; - -+struct qcom_cpufreq_drv; -+ -+struct qcom_cpufreq_match_data { -+ int (*get_version)(struct device *cpu_dev, -+ struct nvmem_cell *speedbin_nvmem, -+ struct qcom_cpufreq_drv *drv); -+}; -+ -+struct qcom_cpufreq_drv { -+ struct opp_table **opp_tables; -+ u32 versions; -+ const struct qcom_cpufreq_match_data *data; -+}; -+ - static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; - - static enum _msm8996_version qcom_cpufreq_get_msm_id(void) -@@ -76,7 +90,7 @@ static enum _msm8996_version qcom_cpufre - - static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, - struct nvmem_cell *speedbin_nvmem, -- u32 *versions) -+ struct qcom_cpufreq_drv *drv) - { - size_t len; - u8 *speedbin; -@@ -94,10 +108,10 @@ static int qcom_cpufreq_kryo_name_versio - - switch (msm8996_version) { - case MSM8996_V3: -- *versions = 1 << (unsigned int)(*speedbin); -+ drv->versions = 1 << (unsigned int)(*speedbin); - break; - case MSM8996_SG: -- *versions = 1 << ((unsigned int)(*speedbin) + 4); -+ drv->versions = 1 << ((unsigned int)(*speedbin) + 4); - break; - default: - BUG(); -@@ -108,17 +122,17 @@ static int qcom_cpufreq_kryo_name_versio - return 0; - } - -+static const struct qcom_cpufreq_match_data match_data_kryo = { -+ .get_version = qcom_cpufreq_kryo_name_version, -+}; -+ - static int qcom_cpufreq_probe(struct platform_device *pdev) - { -- struct opp_table **opp_tables; -- int (*get_version)(struct device *cpu_dev, -- struct nvmem_cell *speedbin_nvmem, -- u32 *versions); -+ struct qcom_cpufreq_drv *drv; - struct nvmem_cell *speedbin_nvmem; - struct device_node *np; - struct device *cpu_dev; - unsigned cpu; -- u32 versions; - const struct of_device_id *match; - int ret; - -@@ -126,11 +140,6 @@ static int qcom_cpufreq_probe(struct pla - if (!cpu_dev) - return -ENODEV; - -- match = pdev->dev.platform_data; -- get_version = match->data; -- if (!get_version) -- return -ENODEV; -- - np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); - if (!np) - return -ENOENT; -@@ -141,23 +150,43 @@ static int qcom_cpufreq_probe(struct pla - return -ENOENT; - } - -- speedbin_nvmem = of_nvmem_cell_get(np, NULL); -- of_node_put(np); -- if (IS_ERR(speedbin_nvmem)) { -- if (PTR_ERR(speedbin_nvmem) != -EPROBE_DEFER) -- dev_err(cpu_dev, "Could not get nvmem cell: %ld\n", -- PTR_ERR(speedbin_nvmem)); -- return PTR_ERR(speedbin_nvmem); -+ drv = kzalloc(sizeof(*drv), GFP_KERNEL); -+ if (!drv) -+ return -ENOMEM; -+ -+ match = pdev->dev.platform_data; -+ drv->data = match->data; -+ if (!drv->data) { -+ ret = -ENODEV; -+ goto free_drv; - } - -- ret = get_version(cpu_dev, speedbin_nvmem, &versions); -- nvmem_cell_put(speedbin_nvmem); -- if (ret) -- return ret; -+ if (drv->data->get_version) { -+ speedbin_nvmem = of_nvmem_cell_get(np, NULL); -+ if (IS_ERR(speedbin_nvmem)) { -+ if (PTR_ERR(speedbin_nvmem) != -EPROBE_DEFER) -+ dev_err(cpu_dev, -+ "Could not get nvmem cell: %ld\n", -+ PTR_ERR(speedbin_nvmem)); -+ ret = PTR_ERR(speedbin_nvmem); -+ goto free_drv; -+ } - -- opp_tables = kcalloc(num_possible_cpus(), sizeof(*opp_tables), GFP_KERNEL); -- if (!opp_tables) -- return -ENOMEM; -+ ret = drv->data->get_version(cpu_dev, speedbin_nvmem, drv); -+ if (ret) { -+ nvmem_cell_put(speedbin_nvmem); -+ goto free_drv; -+ } -+ nvmem_cell_put(speedbin_nvmem); -+ } -+ of_node_put(np); -+ -+ drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables), -+ GFP_KERNEL); -+ if (!drv->opp_tables) { -+ ret = -ENOMEM; -+ goto free_drv; -+ } - - for_each_possible_cpu(cpu) { - cpu_dev = get_cpu_device(cpu); -@@ -166,19 +195,23 @@ static int qcom_cpufreq_probe(struct pla - goto free_opp; - } - -- opp_tables[cpu] = dev_pm_opp_set_supported_hw(cpu_dev, -- &versions, 1); -- if (IS_ERR(opp_tables[cpu])) { -- ret = PTR_ERR(opp_tables[cpu]); -- dev_err(cpu_dev, "Failed to set supported hardware\n"); -- goto free_opp; -+ if (drv->data->get_version) { -+ drv->opp_tables[cpu] = -+ dev_pm_opp_set_supported_hw(cpu_dev, -+ &drv->versions, 1); -+ if (IS_ERR(drv->opp_tables[cpu])) { -+ ret = PTR_ERR(drv->opp_tables[cpu]); -+ dev_err(cpu_dev, -+ "Failed to set supported hardware\n"); -+ goto free_opp; -+ } - } - } - - cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, - NULL, 0); - if (!IS_ERR(cpufreq_dt_pdev)) { -- platform_set_drvdata(pdev, opp_tables); -+ platform_set_drvdata(pdev, drv); - return 0; - } - -@@ -187,26 +220,30 @@ static int qcom_cpufreq_probe(struct pla - - free_opp: - for_each_possible_cpu(cpu) { -- if (IS_ERR_OR_NULL(opp_tables[cpu])) -+ if (IS_ERR_OR_NULL(drv->opp_tables[cpu])) - break; -- dev_pm_opp_put_supported_hw(opp_tables[cpu]); -+ dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]); - } -- kfree(opp_tables); -+ kfree(drv->opp_tables); -+free_drv: -+ kfree(drv); - - return ret; - } - - static int qcom_cpufreq_remove(struct platform_device *pdev) - { -- struct opp_table **opp_tables = platform_get_drvdata(pdev); -+ struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev); - unsigned int cpu; - - platform_device_unregister(cpufreq_dt_pdev); - - for_each_possible_cpu(cpu) -- dev_pm_opp_put_supported_hw(opp_tables[cpu]); -+ if (drv->opp_tables[cpu]) -+ dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]); - -- kfree(opp_tables); -+ kfree(drv->opp_tables); -+ kfree(drv); - - return 0; - } -@@ -220,10 +257,8 @@ static struct platform_driver qcom_cpufr - }; - - static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { -- { .compatible = "qcom,apq8096", -- .data = qcom_cpufreq_kryo_name_version }, -- { .compatible = "qcom,msm8996", -- .data = qcom_cpufreq_kryo_name_version }, -+ { .compatible = "qcom,apq8096", .data = &match_data_kryo }, -+ { .compatible = "qcom,msm8996", .data = &match_data_kryo }, - {}, - }; - diff --git a/target/linux/ipq806x/patches-4.19/0038-qcom-cpufreq-nvmem-Add-support-for-krait-based-socs.patch b/target/linux/ipq806x/patches-4.19/0038-qcom-cpufreq-nvmem-Add-support-for-krait-based-socs.patch deleted file mode 100644 index b8895231d8..0000000000 --- a/target/linux/ipq806x/patches-4.19/0038-qcom-cpufreq-nvmem-Add-support-for-krait-based-socs.patch +++ /dev/null @@ -1,345 +0,0 @@ -Subject: [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs -Date: Tue, 14 Aug 2018 17:42:33 +0530 -Message-Id: <1534248753-2440-15-git-send-email-sricharan@codeaurora.org> -X-Mailer: git-send-email 1.9.1 -In-Reply-To: <1534248753-2440-1-git-send-email-sricharan@codeaurora.org> -References: <1534248753-2440-1-git-send-email-sricharan@codeaurora.org> -Sender: linux-kernel-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-kernel@vger.kernel.org - -In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974 -that has KRAIT processors the voltage/current value of each OPP -varies based on the silicon variant in use. - -The required OPP related data is determined based on -the efuse value. This is similar to the existing code for -kryo cores. So adding support for krait cores here. - -Signed-off-by: Sricharan R ---- - .../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +- - drivers/cpufreq/Kconfig.arm | 2 +- - drivers/cpufreq/cpufreq-dt-platdev.c | 5 + - drivers/cpufreq/qcom-cpufreq-nvmem.c | 151 +++++++++++++++++++-- - 4 files changed, 149 insertions(+), 12 deletions(-) - -# diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt -# index 6dcdfcd..7bc0f1a 100644 -# --- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt -# +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt -# @@ -19,7 +19,8 @@ In 'cpus' nodes: - -# In 'operating-points-v2' table: -# - compatible: Should be -# - - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996. -# + - 'operating-points-v2-qcom-cpu' for apq8096, msm8996, msm8974, -# + apq8064, msm8960 and ipq8074. -# - nvmem-cells: A phandle pointing to a nvmem-cells node representing the -# efuse registers that has information about the -# speedbin that is used to select the right frequency/voltage ---- a/drivers/cpufreq/Kconfig.arm -+++ b/drivers/cpufreq/Kconfig.arm -@@ -112,7 +112,7 @@ config ARM_OMAP2PLUS_CPUFREQ - - config ARM_QCOM_CPUFREQ_NVMEM - tristate "Qualcomm nvmem based CPUFreq" -- depends on ARM64 -+ depends on ARCH_QCOM - depends on QCOM_QFPROM - depends on QCOM_SMEM - select PM_OPP ---- a/drivers/cpufreq/cpufreq-dt-platdev.c -+++ b/drivers/cpufreq/cpufreq-dt-platdev.c -@@ -128,6 +128,11 @@ static const struct of_device_id blackli - { .compatible = "ti,am43", }, - { .compatible = "ti,dra7", }, - -+ { .compatible = "qcom,ipq8064", }, -+ { .compatible = "qcom,apq8064", }, -+ { .compatible = "qcom,msm8974", }, -+ { .compatible = "qcom,msm8960", }, -+ - { } - }; - ---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c -+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c -@@ -48,17 +48,92 @@ struct qcom_cpufreq_drv; - struct qcom_cpufreq_match_data { - int (*get_version)(struct device *cpu_dev, - struct nvmem_cell *speedbin_nvmem, -+ char **pvs_name, - struct qcom_cpufreq_drv *drv); - }; - - struct qcom_cpufreq_drv { -- struct opp_table **opp_tables; -+ struct opp_table **opp_tables1; -+ struct opp_table **opp_tables2; - u32 versions; - const struct qcom_cpufreq_match_data *data; - }; - - static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; - -+static void get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver, -+ struct nvmem_cell *pvs_nvmem, u8 *buf) -+{ -+ u32 pte_efuse; -+ -+ pte_efuse = *((u32 *)buf); -+ -+ *speed = pte_efuse & 0xf; -+ if (*speed == 0xf) -+ *speed = (pte_efuse >> 4) & 0xf; -+ -+ if (*speed == 0xf) { -+ *speed = 0; -+ pr_warn("Speed bin: Defaulting to %d\n", *speed); -+ } else { -+ pr_info("Speed bin: %d\n", *speed); -+ } -+ -+ *pvs = (pte_efuse >> 10) & 0x7; -+ if (*pvs == 0x7) -+ *pvs = (pte_efuse >> 13) & 0x7; -+ -+ if (*pvs == 0x7) { -+ *pvs = 0; -+ pr_warn("PVS bin: Defaulting to %d\n", *pvs); -+ } else { -+ pr_info("PVS bin: %d\n", *pvs); -+ } -+} -+ -+static void get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver, -+ struct nvmem_cell *pvs_nvmem, u8 *buf) -+{ -+ u32 pte_efuse, redundant_sel; -+ -+ pte_efuse = *((u32 *)buf); -+ redundant_sel = (pte_efuse >> 24) & 0x7; -+ *speed = pte_efuse & 0x7; -+ -+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */ -+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); -+ *pvs_ver = (pte_efuse >> 4) & 0x3; -+ -+ switch (redundant_sel) { -+ case 1: -+ *speed = (pte_efuse >> 27) & 0xf; -+ break; -+ case 2: -+ *pvs = (pte_efuse >> 27) & 0xf; -+ break; -+ } -+ -+ /* Check SPEED_BIN_BLOW_STATUS */ -+ if (pte_efuse & BIT(3)) { -+ pr_info("Speed bin: %d\n", *speed); -+ } else { -+ pr_warn("Speed bin not set. Defaulting to 0!\n"); -+ *speed = 0; -+ } -+ -+ /* Check PVS_BLOW_STATUS */ -+ pte_efuse = *(((u32 *)buf) + 4); -+ pte_efuse &= BIT(21); -+ if (pte_efuse) { -+ pr_info("PVS bin: %d\n", *pvs); -+ } else { -+ pr_warn("PVS bin not set. Defaulting to 0!\n"); -+ *pvs = 0; -+ } -+ -+ pr_info("PVS version: %d\n", *pvs_ver); -+} -+ - static enum _msm8996_version qcom_cpufreq_get_msm_id(void) - { - size_t len; -@@ -90,11 +165,13 @@ static enum _msm8996_version qcom_cpufre - - static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, - struct nvmem_cell *speedbin_nvmem, -+ char **pvs_name, - struct qcom_cpufreq_drv *drv) - { - size_t len; - u8 *speedbin; - enum _msm8996_version msm8996_version; -+ *pvs_name = NULL; - - msm8996_version = qcom_cpufreq_get_msm_id(); - if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { -@@ -122,16 +199,51 @@ static int qcom_cpufreq_kryo_name_versio - return 0; - } - -+static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, -+ struct nvmem_cell *speedbin_nvmem, -+ char **pvs_name, -+ struct qcom_cpufreq_drv *drv) -+{ -+ int speed = 0, pvs = 0, pvs_ver = 0; -+ u8 *speedbin; -+ size_t len; -+ -+ speedbin = nvmem_cell_read(speedbin_nvmem, &len); -+ if (len == 4) { -+ get_krait_bin_format_a(&speed, &pvs, &pvs_ver, -+ speedbin_nvmem, speedbin); -+ } else if (len == 8) { -+ get_krait_bin_format_b(&speed, &pvs, &pvs_ver, -+ speedbin_nvmem, speedbin); -+ } else { -+ dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n"); -+ return -ENODEV; -+ } -+ -+ snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d", -+ speed, pvs, pvs_ver); -+ -+ drv->versions = (1 << speed); -+ -+ kfree(speedbin); -+ return 0; -+} -+ - static const struct qcom_cpufreq_match_data match_data_kryo = { - .get_version = qcom_cpufreq_kryo_name_version, - }; - -+static const struct qcom_cpufreq_match_data match_data_krait = { -+ .get_version = qcom_cpufreq_krait_name_version, -+}; -+ - static int qcom_cpufreq_probe(struct platform_device *pdev) - { - struct qcom_cpufreq_drv *drv; - struct nvmem_cell *speedbin_nvmem; - struct device_node *np; - struct device *cpu_dev; -+ char *pvs_name = "speedXX-pvsXX-vXX"; - unsigned cpu; - const struct of_device_id *match; - int ret; -@@ -144,7 +256,7 @@ static int qcom_cpufreq_probe(struct pla - if (!np) - return -ENOENT; - -- ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); -+ ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu"); - if (!ret) { - of_node_put(np); - return -ENOENT; -@@ -172,7 +284,7 @@ static int qcom_cpufreq_probe(struct pla - goto free_drv; - } - -- ret = drv->data->get_version(cpu_dev, speedbin_nvmem, drv); -+ ret = drv->data->get_version(cpu_dev, speedbin_nvmem, &pvs_name, drv); - if (ret) { - nvmem_cell_put(speedbin_nvmem); - goto free_drv; -@@ -181,12 +293,18 @@ static int qcom_cpufreq_probe(struct pla - } - of_node_put(np); - -- drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables), -+ drv->opp_tables1 = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables1), - GFP_KERNEL); -- if (!drv->opp_tables) { -+ if (!drv->opp_tables1) { - ret = -ENOMEM; - goto free_drv; - } -+ drv->opp_tables2 = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables2), -+ GFP_KERNEL); -+ if (!drv->opp_tables2) { -+ ret = -ENOMEM; -+ goto free_opp1; -+ } - - for_each_possible_cpu(cpu) { - cpu_dev = get_cpu_device(cpu); -@@ -196,11 +314,22 @@ static int qcom_cpufreq_probe(struct pla - } - - if (drv->data->get_version) { -- drv->opp_tables[cpu] = -- dev_pm_opp_set_supported_hw(cpu_dev, -+ -+ if (pvs_name) { -+ drv->opp_tables1[cpu] = dev_pm_opp_set_prop_name(cpu_dev, -+ pvs_name); -+ if (IS_ERR(drv->opp_tables1[cpu])) { -+ ret = PTR_ERR(drv->opp_tables1[cpu]); -+ dev_err(cpu_dev, "Failed to add OPP name %s\n", -+ pvs_name); -+ goto free_opp; -+ } -+ } -+ -+ drv->opp_tables2[cpu] = dev_pm_opp_set_supported_hw(cpu_dev, - &drv->versions, 1); -- if (IS_ERR(drv->opp_tables[cpu])) { -- ret = PTR_ERR(drv->opp_tables[cpu]); -+ if (IS_ERR(drv->opp_tables2[cpu])) { -+ ret = PTR_ERR(drv->opp_tables2[cpu]); - dev_err(cpu_dev, - "Failed to set supported hardware\n"); - goto free_opp; -@@ -220,11 +349,18 @@ static int qcom_cpufreq_probe(struct pla - - free_opp: - for_each_possible_cpu(cpu) { -- if (IS_ERR_OR_NULL(drv->opp_tables[cpu])) -+ if (IS_ERR_OR_NULL(drv->opp_tables1[cpu])) - break; -- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]); -+ dev_pm_opp_put_prop_name(drv->opp_tables1[cpu]); - } -- kfree(drv->opp_tables); -+ for_each_possible_cpu(cpu) { -+ if (IS_ERR_OR_NULL(drv->opp_tables2[cpu])) -+ break; -+ dev_pm_opp_put_supported_hw(drv->opp_tables2[cpu]); -+ } -+ kfree(drv->opp_tables2); -+free_opp1: -+ kfree(drv->opp_tables1); - free_drv: - kfree(drv); - -@@ -239,10 +375,14 @@ static int qcom_cpufreq_remove(struct pl - platform_device_unregister(cpufreq_dt_pdev); - - for_each_possible_cpu(cpu) -- if (drv->opp_tables[cpu]) -- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]); -+ if (drv->opp_tables1[cpu]) -+ dev_pm_opp_put_prop_name(drv->opp_tables1[cpu]); -+ for_each_possible_cpu(cpu) -+ if (drv->opp_tables2[cpu]) -+ dev_pm_opp_put_supported_hw(drv->opp_tables2[cpu]); - -- kfree(drv->opp_tables); -+ kfree(drv->opp_tables1); -+ kfree(drv->opp_tables2); - kfree(drv); - - return 0; -@@ -259,6 +399,10 @@ static struct platform_driver qcom_cpufr - static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { - { .compatible = "qcom,apq8096", .data = &match_data_kryo }, - { .compatible = "qcom,msm8996", .data = &match_data_kryo }, -+ { .compatible = "qcom,ipq8064", .data = &match_data_krait }, -+ { .compatible = "qcom,apq8064", .data = &match_data_krait }, -+ { .compatible = "qcom,msm8974", .data = &match_data_krait }, -+ { .compatible = "qcom,msm8960", .data = &match_data_krait }, - {}, - }; - diff --git a/target/linux/ipq806x/patches-4.19/0049-PM-OPP-Support-adjusting-OPP-voltages-at-runtime.patch b/target/linux/ipq806x/patches-4.19/0049-PM-OPP-Support-adjusting-OPP-voltages-at-runtime.patch deleted file mode 100644 index c1cf02e747..0000000000 --- a/target/linux/ipq806x/patches-4.19/0049-PM-OPP-Support-adjusting-OPP-voltages-at-runtime.patch +++ /dev/null @@ -1,153 +0,0 @@ -From: Sylwester Nawrocki -To: krzk@kernel.org, vireshk@kernel.org, robh+dt@kernel.org -Cc: sboyd@kernel.org, roger.lu@mediatek.com, - linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, - linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, - b.zolnierkie@samsung.com, m.szyprowski@samsung.com, - Stephen Boyd , - Sylwester Nawrocki -Subject: [PATCH v5 1/4] PM / OPP: Support adjusting OPP voltages at runtime -Date: Wed, 16 Oct 2019 16:57:53 +0200 -Message-ID: <20191016145756.16004-2-s.nawrocki@samsung.com> (raw) -In-Reply-To: <20191016145756.16004-1-s.nawrocki@samsung.com> - -From: Stephen Boyd - -On some SoCs the Adaptive Voltage Scaling (AVS) technique is -employed to optimize the operating voltage of a device. At a -given frequency, the hardware monitors dynamic factors and either -makes a suggestion for how much to adjust a voltage for the -current frequency, or it automatically adjusts the voltage -without software intervention. Add an API to the OPP library for -the former case, so that AVS type devices can update the voltages -for an OPP when the hardware determines the voltage should -change. The assumption is that drivers like CPUfreq or devfreq -will register for the OPP notifiers and adjust the voltage -according to suggestions that AVS makes. - -This patch is derived from [1] submitted by Stephen. -[1] https://lore.kernel.org/patchwork/patch/599279/ - -Signed-off-by: Stephen Boyd -Signed-off-by: Roger Lu -[s.nawrocki@samsung.com: added handling of OPP min/max voltage] -Signed-off-by: Sylwester Nawrocki ---- - drivers/opp/core.c | 69 ++++++++++++++++++++++++++++++++++++++++++ - include/linux/pm_opp.h | 13 ++++++++ - 2 files changed, 82 insertions(+) - ---- a/drivers/opp/core.c -+++ b/drivers/opp/core.c -@@ -1629,6 +1629,75 @@ put_table: - } - - /** -+ * dev_pm_opp_adjust_voltage() - helper to change the voltage of an OPP -+ * @dev: device for which we do this operation -+ * @freq: OPP frequency to adjust voltage of -+ * @u_volt: new OPP target voltage -+ * @u_volt_min: new OPP min voltage -+ * @u_volt_max: new OPP max voltage -+ * -+ * Return: -EINVAL for bad pointers, -ENOMEM if no memory available for the -+ * copy operation, returns 0 if no modifcation was done OR modification was -+ * successful. -+ */ -+int dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq, -+ unsigned long u_volt, unsigned long u_volt_min, -+ unsigned long u_volt_max) -+ -+{ -+ struct opp_table *opp_table; -+ struct dev_pm_opp *tmp_opp, *opp = ERR_PTR(-ENODEV); -+ int r = 0; -+ -+ /* Find the opp_table */ -+ opp_table = _find_opp_table(dev); -+ if (IS_ERR(opp_table)) { -+ r = PTR_ERR(opp_table); -+ dev_warn(dev, "%s: Device OPP not found (%d)\n", __func__, r); -+ return r; -+ } -+ -+ mutex_lock(&opp_table->lock); -+ -+ /* Do we have the frequency? */ -+ list_for_each_entry(tmp_opp, &opp_table->opp_list, node) { -+ if (tmp_opp->rate == freq) { -+ opp = tmp_opp; -+ break; -+ } -+ } -+ -+ if (IS_ERR(opp)) { -+ r = PTR_ERR(opp); -+ goto adjust_unlock; -+ } -+ -+ /* Is update really needed? */ -+ if (opp->supplies->u_volt == u_volt) -+ goto adjust_unlock; -+ -+ opp->supplies->u_volt = u_volt; -+ opp->supplies->u_volt_min = u_volt_min; -+ opp->supplies->u_volt_max = u_volt_max; -+ -+ dev_pm_opp_get(opp); -+ mutex_unlock(&opp_table->lock); -+ -+ /* Notify the voltage change of the OPP */ -+ blocking_notifier_call_chain(&opp_table->head, OPP_EVENT_ADJUST_VOLTAGE, -+ opp); -+ -+ dev_pm_opp_put(opp); -+ goto adjust_put_table; -+ -+adjust_unlock: -+ mutex_unlock(&opp_table->lock); -+adjust_put_table: -+ dev_pm_opp_put_opp_table(opp_table); -+ return r; -+} -+ -+/** - * dev_pm_opp_enable() - Enable a specific OPP - * @dev: device for which we do this operation - * @freq: OPP frequency to enable ---- a/include/linux/pm_opp.h -+++ b/include/linux/pm_opp.h -@@ -25,6 +25,7 @@ struct opp_table; - - enum dev_pm_opp_event { - OPP_EVENT_ADD, OPP_EVENT_REMOVE, OPP_EVENT_ENABLE, OPP_EVENT_DISABLE, -+ OPP_EVENT_ADJUST_VOLTAGE, - }; - - /** -@@ -108,6 +109,10 @@ int dev_pm_opp_add(struct device *dev, u - unsigned long u_volt); - void dev_pm_opp_remove(struct device *dev, unsigned long freq); - -+int dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq, -+ unsigned long u_volt, unsigned long u_volt_min, -+ unsigned long u_volt_max); -+ - int dev_pm_opp_enable(struct device *dev, unsigned long freq); - - int dev_pm_opp_disable(struct device *dev, unsigned long freq); -@@ -208,6 +213,14 @@ static inline void dev_pm_opp_remove(str - { - } - -+static inline int -+dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq, -+ unsigned long u_volt, unsigned long u_volt_min, -+ unsigned long u_volt_max) -+{ -+ return 0; -+} -+ - static inline int dev_pm_opp_enable(struct device *dev, unsigned long freq) - { - return 0; diff --git a/target/linux/ipq806x/patches-4.19/0051-PM-OPP-Add-a-helper-to-get-an-opp-regulator-for-devi.patch b/target/linux/ipq806x/patches-4.19/0051-PM-OPP-Add-a-helper-to-get-an-opp-regulator-for-devi.patch deleted file mode 100644 index 4312db905a..0000000000 --- a/target/linux/ipq806x/patches-4.19/0051-PM-OPP-Add-a-helper-to-get-an-opp-regulator-for-devi.patch +++ /dev/null @@ -1,52 +0,0 @@ -From d06ca5e7a3cf726f5be5ffd96e93ccd798b8c09a Mon Sep 17 00:00:00 2001 -From: Georgi Djakov -Date: Thu, 12 May 2016 14:41:33 +0300 -Subject: [PATCH 51/69] PM / OPP: Add a helper to get an opp regulator for - device - -Signed-off-by: Georgi Djakov ---- - drivers/opp/core.c | 21 +++++++++++++++++++++ - include/linux/pm_opp.h | 1 + - 2 files changed, 22 insertions(+) - ---- a/drivers/opp/core.c -+++ b/drivers/opp/core.c -@@ -125,6 +125,27 @@ unsigned long dev_pm_opp_get_freq(struct - } - EXPORT_SYMBOL_GPL(dev_pm_opp_get_freq); - -+struct regulator *dev_pm_opp_get_regulator(struct device *dev) -+{ -+ struct opp_table *opp_table; -+ struct regulator *reg; -+ -+ rcu_read_lock(); -+ -+ opp_table = _find_opp_table(dev); -+ if (IS_ERR(opp_table)) { -+ rcu_read_unlock(); -+ return ERR_CAST(opp_table); -+ } -+ -+ reg = opp_table->regulators[0]; -+ -+ rcu_read_unlock(); -+ -+ return reg; -+} -+EXPORT_SYMBOL_GPL(dev_pm_opp_get_regulator); -+ - /** - * dev_pm_opp_is_turbo() - Returns if opp is turbo OPP or not - * @opp: opp for which turbo mode is being verified ---- a/include/linux/pm_opp.h -+++ b/include/linux/pm_opp.h -@@ -85,6 +85,7 @@ void dev_pm_opp_put_opp_table(struct opp - unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp); - - unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp); -+struct regulator *dev_pm_opp_get_regulator(struct device *dev); - - bool dev_pm_opp_is_turbo(struct dev_pm_opp *opp); - diff --git a/target/linux/ipq806x/patches-4.19/0052-PM-OPP-Update-the-voltage-tolerance-when-adjusting-t.patch b/target/linux/ipq806x/patches-4.19/0052-PM-OPP-Update-the-voltage-tolerance-when-adjusting-t.patch deleted file mode 100644 index 9f0b9ec6d3..0000000000 --- a/target/linux/ipq806x/patches-4.19/0052-PM-OPP-Update-the-voltage-tolerance-when-adjusting-t.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 4533c285c2aedce6d4434d7b877066de3b1ecb33 Mon Sep 17 00:00:00 2001 -From: Georgi Djakov -Date: Thu, 25 Aug 2016 18:43:35 +0300 -Subject: [PATCH 52/69] PM / OPP: Update the voltage tolerance when adjusting - the OPP - -When the voltage is adjusted, the voltage tolerance is not updated. -This can lead to situations where the voltage min value is greater -than the voltage max value. The final result is triggering a BUG() -in the regulator core. -Fix this by updating the voltage tolerance values too. - -Signed-off-by: Georgi Djakov ---- - drivers/opp/core.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/opp/core.c -+++ b/drivers/opp/core.c -@@ -1669,6 +1669,7 @@ int dev_pm_opp_adjust_voltage(struct dev - struct opp_table *opp_table; - struct dev_pm_opp *tmp_opp, *opp = ERR_PTR(-ENODEV); - int r = 0; -+ unsigned long tol; - - /* Find the opp_table */ - opp_table = _find_opp_table(dev); -@@ -1698,8 +1699,17 @@ int dev_pm_opp_adjust_voltage(struct dev - goto adjust_unlock; - - opp->supplies->u_volt = u_volt; -- opp->supplies->u_volt_min = u_volt_min; -- opp->supplies->u_volt_max = u_volt_max; -+ -+ tol = u_volt * opp_table->voltage_tolerance_v1 / 100; -+ if ( u_volt_min == u_volt ) -+ opp->supplies->u_volt_min = u_volt - tol; -+ else -+ opp->supplies->u_volt_min = u_volt_min; -+ -+ if ( u_volt_max == u_volt ) -+ opp->supplies->u_volt_max = u_volt + tol; -+ else -+ opp->supplies->u_volt_max = u_volt_max; - - dev_pm_opp_get(opp); - mutex_unlock(&opp_table->lock); diff --git a/target/linux/ipq806x/patches-4.19/0053-regulator-add-smb208-support.patch b/target/linux/ipq806x/patches-4.19/0053-regulator-add-smb208-support.patch deleted file mode 100644 index 0d2862c609..0000000000 --- a/target/linux/ipq806x/patches-4.19/0053-regulator-add-smb208-support.patch +++ /dev/null @@ -1,55 +0,0 @@ -From ef10381ca4d01848ebedb4afb2c78feb8052f103 Mon Sep 17 00:00:00 2001 -From: Adrian Panella -Date: Thu, 9 Mar 2017 08:26:54 +0100 -Subject: [PATCH 53/69] regulator: add smb208 support - -Signed-off-by: Adrian Panella ---- - Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 4 ++++ - drivers/regulator/qcom_rpm-regulator.c | 9 +++++++++ - 2 files changed, 13 insertions(+) - ---- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt -+++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt -@@ -61,6 +61,7 @@ Regulator nodes are identified by their - "qcom,rpm-pm8901-regulators" - "qcom,rpm-pm8921-regulators" - "qcom,rpm-pm8018-regulators" -+ "qcom,rpm-smb208-regulators" - - - vdd_l0_l1_lvs-supply: - - vdd_l2_l11_l12-supply: -@@ -171,6 +172,9 @@ pm8018: - s1, s2, s3, s4, s5, , l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, - l12, l14, lvs1 - -+smb208: -+ s1a, s1b, s2a, s2b -+ - The content of each sub-node is defined by the standard binding for regulators - - see regulator.txt - with additional custom properties described below: - ---- a/drivers/regulator/qcom_rpm-regulator.c -+++ b/drivers/regulator/qcom_rpm-regulator.c -@@ -933,12 +933,21 @@ static const struct rpm_regulator_data r - { } - }; - -+static const struct rpm_regulator_data rpm_smb208_regulators[] = { -+ { "s1a", QCOM_RPM_SMB208_S1a, &smb208_smps, "vin_s1a" }, -+ { "s1b", QCOM_RPM_SMB208_S1b, &smb208_smps, "vin_s1b" }, -+ { "s2a", QCOM_RPM_SMB208_S2a, &smb208_smps, "vin_s2a" }, -+ { "s2b", QCOM_RPM_SMB208_S2b, &smb208_smps, "vin_s2b" }, -+ { } -+}; -+ - static const struct of_device_id rpm_of_match[] = { - { .compatible = "qcom,rpm-pm8018-regulators", - .data = &rpm_pm8018_regulators }, - { .compatible = "qcom,rpm-pm8058-regulators", .data = &rpm_pm8058_regulators }, - { .compatible = "qcom,rpm-pm8901-regulators", .data = &rpm_pm8901_regulators }, - { .compatible = "qcom,rpm-pm8921-regulators", .data = &rpm_pm8921_regulators }, -+ { .compatible = "qcom,rpm-smb208-regulators", .data = &rpm_smb208_regulators }, - { } - }; - MODULE_DEVICE_TABLE(of, rpm_of_match); diff --git a/target/linux/ipq806x/patches-4.19/0054-cpufreq-dt-Handle-OPP-voltage-adjust-events.patch b/target/linux/ipq806x/patches-4.19/0054-cpufreq-dt-Handle-OPP-voltage-adjust-events.patch deleted file mode 100644 index 9620891194..0000000000 --- a/target/linux/ipq806x/patches-4.19/0054-cpufreq-dt-Handle-OPP-voltage-adjust-events.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 10577f74c35bd395951d1b2382c8d821089b5745 Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Fri, 18 Sep 2015 17:52:08 -0700 -Subject: [PATCH 54/69] cpufreq-dt: Handle OPP voltage adjust events - -On some SoCs the Adaptive Voltage Scaling (AVS) technique is -employed to optimize the operating voltage of a device. At a -given frequency, the hardware monitors dynamic factors and either -makes a suggestion for how much to adjust a voltage for the -current frequency, or it automatically adjusts the voltage -without software intervention. - -In the former case, an AVS driver will call -dev_pm_opp_modify_voltage() and update the voltage for the -particular OPP the CPUs are using. Add an OPP notifier to -cpufreq-dt so that we can adjust the voltage of the CPU when AVS -updates the OPP. - -Signed-off-by: Stephen Boyd -Acked-by: Viresh Kumar -Signed-off-by: Georgi Djakov ---- - drivers/cpufreq/cpufreq-dt.c | 68 ++++++++++++++++++++++++++++++++++++++++++-- - 1 file changed, 65 insertions(+), 3 deletions(-) - ---- a/drivers/cpufreq/cpufreq-dt.c -+++ b/drivers/cpufreq/cpufreq-dt.c -@@ -32,6 +32,9 @@ struct private_data { - struct device *cpu_dev; - struct thermal_cooling_device *cdev; - const char *reg_name; -+ struct notifier_block opp_nb; -+ struct mutex lock; -+ unsigned long opp_freq; - bool have_static_opps; - }; - -@@ -47,12 +50,15 @@ static int set_target(struct cpufreq_pol - unsigned long freq = policy->freq_table[index].frequency; - int ret; - -+ mutex_lock(&priv->lock); - ret = dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000); - - if (!ret) { -+ priv->opp_freq = freq * 1000; - arch_set_freq_scale(policy->related_cpus, freq, - policy->cpuinfo.max_freq); - } -+ mutex_unlock(&priv->lock); - - return ret; - } -@@ -95,6 +101,39 @@ node_put: - return name; - } - -+static int opp_notifier(struct notifier_block *nb, unsigned long event, -+ void *data) -+{ -+ struct dev_pm_opp *opp = data; -+ struct private_data *priv = container_of(nb, struct private_data, -+ opp_nb); -+ struct device *cpu_dev = priv->cpu_dev; -+ struct regulator *cpu_reg; -+ unsigned long volt, freq; -+ int ret = 0; -+ -+ if (event == OPP_EVENT_ADJUST_VOLTAGE) { -+ cpu_reg = dev_pm_opp_get_regulator(cpu_dev); -+ if (IS_ERR(cpu_reg)) { -+ ret = PTR_ERR(cpu_reg); -+ goto out; -+ } -+ volt = dev_pm_opp_get_voltage(opp); -+ freq = dev_pm_opp_get_freq(opp); -+ -+ mutex_lock(&priv->lock); -+ if (freq == priv->opp_freq) { -+ ret = regulator_set_voltage_triplet(cpu_reg, volt, volt, volt); -+ } -+ mutex_unlock(&priv->lock); -+ if (ret) -+ dev_err(cpu_dev, "failed to scale voltage: %d\n", ret); -+ } -+ -+out: -+ return notifier_from_errno(ret); -+} -+ - static int resources_available(void) - { - struct device *cpu_dev; -@@ -251,10 +290,14 @@ static int cpufreq_init(struct cpufreq_p - __func__, ret); - } - -+ mutex_init(&priv->lock); -+ priv->opp_nb.notifier_call = opp_notifier; -+ dev_pm_opp_register_notifier(cpu_dev, &priv->opp_nb); -+ - ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); - if (ret) { - dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); -- goto out_free_opp; -+ goto out_unregister_nb; - } - - priv->cpu_dev = cpu_dev; -@@ -284,6 +327,8 @@ static int cpufreq_init(struct cpufreq_p - - out_free_cpufreq_table: - dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); -+out_unregister_nb: -+ dev_pm_opp_unregister_notifier(cpu_dev, &priv->opp_nb); - out_free_opp: - if (priv->have_static_opps) - dev_pm_opp_of_cpumask_remove_table(policy->cpus); diff --git a/target/linux/ipq806x/patches-4.19/0055-cpufreq-dt-Add-L2-frequency-scaling-support.patch b/target/linux/ipq806x/patches-4.19/0055-cpufreq-dt-Add-L2-frequency-scaling-support.patch deleted file mode 100644 index 5f54120b3a..0000000000 --- a/target/linux/ipq806x/patches-4.19/0055-cpufreq-dt-Add-L2-frequency-scaling-support.patch +++ /dev/null @@ -1,161 +0,0 @@ ---- a/drivers/cpufreq/cpufreq-dt.c -+++ b/drivers/cpufreq/cpufreq-dt.c -@@ -48,16 +48,71 @@ static int set_target(struct cpufreq_pol - { - struct private_data *priv = policy->driver_data; - unsigned long freq = policy->freq_table[index].frequency; -+ struct clk *l2_clk = policy->l2_clk; -+ struct regulator *l2_regulator = policy->l2_regulator; -+ unsigned long l2_freq, target_l2_freq; -+ unsigned long l2_vol, target_l2_vol; -+ unsigned long target_freq; - int ret; - - mutex_lock(&priv->lock); - ret = dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000); - - if (!ret) { -+ if (policy->l2_rate_set) { -+ static unsigned long krait_l2[CONFIG_NR_CPUS] = { }; -+ int cpu, l2_index, tol = 0; -+ -+ target_freq = freq * 1000; -+ -+ krait_l2[policy->cpu] = target_freq; -+ for_each_present_cpu(cpu) -+ target_freq = max(target_freq, krait_l2[cpu]); -+ -+ for (l2_index = 2; l2_index >= 0; l2_index--) -+ if (target_freq >= policy->l2_cpufreq[l2_index]) -+ break; -+ -+ l2_freq = clk_get_rate(l2_clk); -+ target_l2_freq = policy->l2_rate[l2_index]; -+ -+ if (l2_freq != target_l2_freq) { -+ -+ /* -+ * Set to idle bin if switching from normal to high bin -+ * or vice versa -+ */ -+ if ( (l2_index == 2 && l2_freq == policy->l2_rate[1]) || -+ (l2_index == 1 && l2_freq == policy->l2_rate[2]) ) { -+ ret = clk_set_rate(l2_clk, policy->l2_rate[0]); -+ if (ret) -+ goto exit; -+ } -+ /* scale l2 with the core */ -+ ret = clk_set_rate(l2_clk, target_l2_freq); -+ if (ret) -+ goto exit; -+ -+ if (policy->l2_volt_set) { -+ -+ l2_vol = regulator_get_voltage(l2_regulator); -+ target_l2_vol = policy->l2_volt[l2_index]; -+ -+ if (l2_vol != target_l2_vol) { -+ tol = target_l2_vol * policy->l2_volt_tol / 100; -+ ret = regulator_set_voltage_tol(l2_regulator,target_l2_vol,tol); -+ if (ret) -+ goto exit; -+ } -+ } -+ } -+ } - priv->opp_freq = freq * 1000; - arch_set_freq_scale(policy->related_cpus, freq, - policy->cpuinfo.max_freq); - } -+ -+exit: - mutex_unlock(&priv->lock); - - return ret; -@@ -200,6 +255,9 @@ static int cpufreq_init(struct cpufreq_p - bool fallback = false; - const char *name; - int ret; -+ struct device_node *np, *l2_np; -+ struct clk *l2_clk = NULL; -+ struct regulator *l2_regulator = NULL; - - cpu_dev = get_cpu_device(policy->cpu); - if (!cpu_dev) { -@@ -307,6 +365,57 @@ static int cpufreq_init(struct cpufreq_p - - policy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu_dev) / 1000; - -+ policy->l2_rate_set = false; -+ policy->l2_volt_set = false; -+ -+ l2_clk = clk_get(cpu_dev, "l2"); -+ if (!IS_ERR(l2_clk)) -+ policy->l2_clk = l2_clk; -+ -+ l2_np = of_find_node_by_name(NULL, "qcom,l2"); -+ if (l2_np) { -+ struct device_node *vdd; -+ np = of_node_get(priv->cpu_dev->of_node); -+ -+ if (np) -+ of_property_read_u32(np, "voltage-tolerance", &policy->l2_volt_tol); -+ -+ of_property_read_u32_array(l2_np, "qcom,l2-rates", policy->l2_rate, 3); -+ if (policy->l2_rate[0] && policy->l2_rate[1] && policy->l2_rate[2]) { -+ policy->l2_rate_set = true; -+ of_property_read_u32_array(l2_np, "qcom,l2-cpufreq", policy->l2_cpufreq, 3); -+ of_property_read_u32_array(l2_np, "qcom,l2-volt", policy->l2_volt, 3); -+ } else -+ pr_warn("L2: failed to parse L2 rates\n"); -+ -+ if (!policy->l2_cpufreq[0] && !policy->l2_cpufreq[1] && -+ !policy->l2_cpufreq[2] && policy->l2_rate_set) { -+ int i; -+ -+ pr_warn("L2: failed to parse target cpu freq, using defaults\n"); -+ for (i = 0; i < 3; i++) -+ policy->l2_cpufreq[i] = policy->l2_rate[i]; -+ } -+ -+ if (policy->l2_volt[0] && policy->l2_volt[1] && policy->l2_volt[2] && -+ policy->l2_volt_tol && policy->l2_rate_set) { -+ vdd = of_parse_phandle(l2_np, "qcom,l2-supply", 0); -+ -+ if (vdd) { -+ l2_regulator = devm_regulator_get(cpu_dev, vdd->name); -+ if (!IS_ERR(l2_regulator)) { -+ policy->l2_regulator = l2_regulator; -+ policy->l2_volt_set = true; -+ } else { -+ pr_warn("failed to get l2 supply\n"); -+ l2_regulator = NULL; -+ } -+ -+ of_node_put(vdd); -+ } -+ } -+ } -+ - /* Support turbo/boost mode */ - if (policy_has_boost_freq(policy)) { - /* This gets disabled by core on driver unregister */ ---- a/include/linux/cpufreq.h -+++ b/include/linux/cpufreq.h -@@ -72,7 +72,15 @@ struct cpufreq_policy { - should set cpufreq */ - unsigned int cpu; /* cpu managing this policy, must be online */ - -- struct clk *clk; -+ struct clk *clk; -+ struct clk *l2_clk; /* L2 clock */ -+ struct regulator *l2_regulator; /* L2 supply */ -+ unsigned int l2_rate[3]; /* L2 bus clock rate */ -+ bool l2_rate_set; -+ unsigned int l2_cpufreq[3]; /* L2 target CPU frequency */ -+ unsigned int l2_volt[3]; /* L2 voltage array */ -+ bool l2_volt_set; -+ unsigned int l2_volt_tol; /* L2 voltage tolerance */ - struct cpufreq_cpuinfo cpuinfo;/* see above */ - - unsigned int min; /* in kHz */ diff --git a/target/linux/ipq806x/patches-4.19/0056-cpufreq-dt-Add-missing-rcu-locks.patch b/target/linux/ipq806x/patches-4.19/0056-cpufreq-dt-Add-missing-rcu-locks.patch deleted file mode 100644 index ef03ba4de8..0000000000 --- a/target/linux/ipq806x/patches-4.19/0056-cpufreq-dt-Add-missing-rcu-locks.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 001a8dcb56ced58c518aaa10a4f0ba5e878705b6 Mon Sep 17 00:00:00 2001 -From: Georgi Djakov -Date: Tue, 17 May 2016 16:15:43 +0300 -Subject: [PATCH 56/69] cpufreq-dt: Add missing rcu locks - -Signed-off-by: Georgi Djakov ---- - drivers/cpufreq/cpufreq-dt.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/cpufreq/cpufreq-dt.c -+++ b/drivers/cpufreq/cpufreq-dt.c -@@ -173,8 +173,10 @@ static int opp_notifier(struct notifier_ - ret = PTR_ERR(cpu_reg); - goto out; - } -+ rcu_read_lock(); - volt = dev_pm_opp_get_voltage(opp); - freq = dev_pm_opp_get_freq(opp); -+ rcu_read_unlock(); - - mutex_lock(&priv->lock); - if (freq == priv->opp_freq) { diff --git a/target/linux/ipq806x/patches-4.19/0057-add-fab-scaling-support-with-cpufreq.patch b/target/linux/ipq806x/patches-4.19/0057-add-fab-scaling-support-with-cpufreq.patch deleted file mode 100644 index dc65230f47..0000000000 --- a/target/linux/ipq806x/patches-4.19/0057-add-fab-scaling-support-with-cpufreq.patch +++ /dev/null @@ -1,243 +0,0 @@ ---- a/drivers/clk/qcom/Makefile -+++ b/drivers/clk/qcom/Makefile -@@ -15,6 +15,7 @@ clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-k - clk-qcom-y += clk-hfpll.o - clk-qcom-y += reset.o - clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o -+clk-qcom-y += fab_scaling.o - - # Keep alphabetically sorted by config - obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o ---- /dev/null -+++ b/drivers/clk/qcom/fab_scaling.c -@@ -0,0 +1,172 @@ -+/* -+ * Copyright (c) 2015, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for any -+ * purpose with or without fee is hereby granted, provided that the above -+ * copyright notice and this permission notice appear in all copies. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct qcom_fab_scaling_data { -+ u32 fab_freq_high; -+ u32 fab_freq_nominal; -+ u32 cpu_freq_threshold; -+ struct clk *apps_fab_clk; -+ struct clk *ddr_fab_clk; -+}; -+ -+static struct qcom_fab_scaling_data *drv_data; -+ -+int scale_fabrics(unsigned long max_cpu_freq) -+{ -+ struct clk *apps_fab_clk = drv_data->apps_fab_clk, -+ *ddr_fab_clk = drv_data->ddr_fab_clk; -+ unsigned long target_freq, cur_freq; -+ int ret; -+ -+ /* Skip fab scaling if the driver is not ready */ -+ if (!apps_fab_clk || !ddr_fab_clk) -+ return 0; -+ -+ if (max_cpu_freq > drv_data->cpu_freq_threshold) -+ target_freq = drv_data->fab_freq_high; -+ else -+ target_freq = drv_data->fab_freq_nominal; -+ -+ cur_freq = clk_get_rate(ddr_fab_clk); -+ -+ if (target_freq != cur_freq) { -+ ret = clk_set_rate(apps_fab_clk, target_freq); -+ if (ret) -+ return ret; -+ ret = clk_set_rate(ddr_fab_clk, target_freq); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(scale_fabrics); -+ -+static int ipq806x_fab_scaling_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct clk *apps_fab_clk, *ddr_fab_clk; -+ int ret; -+ -+ if (!np) -+ return -ENODEV; -+ -+ drv_data = kzalloc(sizeof(*drv_data), GFP_KERNEL); -+ if (!drv_data) -+ return -ENOMEM; -+ -+ if (of_property_read_u32(np, "fab_freq_high", &drv_data->fab_freq_high)) { -+ pr_err("FABRICS turbo freq not found. Using defaults...\n"); -+ drv_data->fab_freq_high = 533000000; -+ } -+ -+ if (of_property_read_u32(np, "fab_freq_nominal", &drv_data->fab_freq_nominal)) { -+ pr_err("FABRICS nominal freq not found. Using defaults...\n"); -+ drv_data->fab_freq_nominal = 400000000; -+ } -+ -+ if (of_property_read_u32(np, "cpu_freq_threshold", &drv_data->cpu_freq_threshold)) { -+ pr_err("FABRICS cpu freq threshold not found. Using defaults...\n"); -+ drv_data->cpu_freq_threshold = 1000000000; -+ } -+ -+ drv_data->apps_fab_clk = devm_clk_get(&pdev->dev, "apps-fab-clk"); -+ apps_fab_clk = drv_data->apps_fab_clk; -+ ret = PTR_ERR_OR_ZERO(apps_fab_clk); -+ if (ret) { -+ /* -+ * If apps fab clk node is present, but clock is not yet -+ * registered, we should try defering probe. -+ */ -+ if (ret != -EPROBE_DEFER) { -+ pr_err("Failed to get APPS FABRIC clock: %d\n", ret); -+ ret = -ENODEV; -+ } -+ goto err; -+ } -+ -+ clk_set_rate(apps_fab_clk, drv_data->fab_freq_high); -+ clk_prepare_enable(apps_fab_clk); -+ -+ drv_data->ddr_fab_clk = devm_clk_get(&pdev->dev, "ddr-fab-clk"); -+ ddr_fab_clk = drv_data->ddr_fab_clk; -+ ret = PTR_ERR_OR_ZERO(ddr_fab_clk); -+ if (ret) { -+ /* -+ * If ddr fab clk node is present, but clock is not yet -+ * registered, we should try defering probe. -+ */ -+ if (ret != -EPROBE_DEFER) { -+ pr_err("Failed to get DDR FABRIC clock: %d\n", ret); -+ ddr_fab_clk = NULL; -+ ret = -ENODEV; -+ } -+ goto err; -+ } -+ -+ clk_set_rate(ddr_fab_clk, drv_data->fab_freq_high); -+ clk_prepare_enable(ddr_fab_clk); -+ -+ return 0; -+err: -+ kfree(drv_data); -+ return ret; -+} -+ -+static int ipq806x_fab_scaling_remove(struct platform_device *pdev) -+{ -+ kfree(drv_data); -+ return 0; -+} -+ -+static const struct of_device_id fab_scaling_ipq806x_match_table[] = { -+ { .compatible = "qcom,fab-scaling" }, -+ { } -+}; -+ -+static struct platform_driver fab_scaling_ipq806x_driver = { -+ .probe = ipq806x_fab_scaling_probe, -+ .remove = ipq806x_fab_scaling_remove, -+ .driver = { -+ .name = "fab-scaling", -+ .of_match_table = fab_scaling_ipq806x_match_table, -+ }, -+}; -+ -+static int __init fab_scaling_ipq806x_init(void) -+{ -+ return platform_driver_register(&fab_scaling_ipq806x_driver); -+} -+late_initcall(fab_scaling_ipq806x_init); -+ -+static void __exit fab_scaling_ipq806x_exit(void) -+{ -+ platform_driver_unregister(&fab_scaling_ipq806x_driver); -+} -+module_exit(fab_scaling_ipq806x_exit); ---- /dev/null -+++ b/include/linux/fab_scaling.h -@@ -0,0 +1,31 @@ -+/* -+ * Copyright (c) 2015, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for any -+ * purpose with or without fee is hereby granted, provided that the above -+ * copyright notice and this permission notice appear in all copies. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+ -+#ifndef __FAB_SCALING_H -+#define __FAB_SCALING_H -+ -+/** -+ * scale_fabrics - Scale DDR and APPS FABRICS -+ * -+ * This function monitors all the registered clocks and does APPS -+ * and DDR FABRIC scaling based on the idle frequencies with which -+ * it was registered. -+ * -+ */ -+int scale_fabrics(unsigned long max_cpu_freq); -+ -+#endif ---- a/drivers/cpufreq/cpufreq-dt.c -+++ b/drivers/cpufreq/cpufreq-dt.c -@@ -24,6 +24,7 @@ - #include - #include - #include -+#include - - #include "cpufreq-dt.h" - -@@ -106,6 +107,13 @@ static int set_target(struct cpufreq_pol - } - } - } -+ -+ /* -+ * Scale fabrics with max freq across all cores -+ */ -+ ret = scale_fabrics(target_freq); -+ if (ret) -+ goto exit; - } - priv->opp_freq = freq * 1000; - arch_set_freq_scale(policy->related_cpus, freq, diff --git a/target/linux/ipq806x/patches-4.19/0059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch b/target/linux/ipq806x/patches-4.19/0059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch deleted file mode 100644 index 5bd58c8137..0000000000 --- a/target/linux/ipq806x/patches-4.19/0059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 04ca10340f1b4d92e849724d322a7ca225d11539 Mon Sep 17 00:00:00 2001 -From: Lina Iyer -Date: Wed, 25 Mar 2015 14:25:29 -0600 -Subject: [PATCH 59/69] ARM: cpuidle: Add cpuidle support for QCOM cpus - -Define ARM_QCOM_CPUIDLE config item to enable cpuidle support. - -Cc: Stephen Boyd -Cc: Arnd Bergmann -Cc: Kevin Hilman -Cc: Daniel Lezcano -Signed-off-by: Lina Iyer ---- - drivers/cpuidle/Kconfig.arm | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/cpuidle/Kconfig.arm -+++ b/drivers/cpuidle/Kconfig.arm -@@ -75,3 +75,10 @@ config ARM_MVEBU_V7_CPUIDLE - depends on ARCH_MVEBU && !ARM64 - help - Select this to enable cpuidle on Armada 370, 38x and XP processors. -+ -+config ARM_QCOM_CPUIDLE -+ bool "CPU Idle Driver for QCOM processors" -+ depends on ARCH_QCOM -+ select ARM_CPUIDLE -+ help -+ Select this to enable cpuidle on QCOM processors. diff --git a/target/linux/ipq806x/patches-4.19/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch b/target/linux/ipq806x/patches-4.19/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch deleted file mode 100644 index 543f18ce4d..0000000000 --- a/target/linux/ipq806x/patches-4.19/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch +++ /dev/null @@ -1,62 +0,0 @@ -From fa71139b55e114aa8c3c4823ff8ee7d49ee810d4 Mon Sep 17 00:00:00 2001 -From: Mathieu Olivari -Date: Wed, 29 Apr 2015 15:21:46 -0700 -Subject: [PATCH 60/69] HACK: arch: arm: force ZRELADDR on arch-qcom - -ARCH_QCOM is using the ARCH_MULTIPLATFORM option, as now recommended -on most ARM architectures. This automatically calculate ZRELADDR by -masking PHYS_OFFSET with 0xf8000000. - -However, on IPQ806x, the first ~20MB of RAM is reserved for the hardware -network accelerators, and the bootloader removes this section from the -layout passed from the ATAGS (when used). - -For newer bootloader, when DT is used, this is not a problem, we just -reserve this memory in the device tree. But if the bootloader doesn't -have DT support, then ATAGS have to be used. In this case, the ARM -decompressor will position the kernel in this low mem, which will not be -in the RAM section mapped by the bootloader, which means the kernel will -freeze in the middle of the boot process trying to map the memory. - -As a work around, this patch allows disabling AUTO_ZRELADDR when -ARCH_QCOM is selected. It makes the zImage usage possible on bootloaders -which don't support device-tree, which is the case on certain early -IPQ806x based designs. - -Signed-off-by: Mathieu Olivari ---- - arch/arm/Kconfig | 2 +- - arch/arm/Makefile | 2 ++ - arch/arm/mach-qcom/Makefile.boot | 1 + - 3 files changed, 4 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/mach-qcom/Makefile.boot - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -331,7 +331,7 @@ config ARCH_MULTIPLATFORM - depends on MMU - select ARM_HAS_SG_CHAIN - select ARM_PATCH_PHYS_VIRT -- select AUTO_ZRELADDR -+ select AUTO_ZRELADDR if !ARCH_QCOM - select TIMER_OF - select COMMON_CLK - select GENERIC_CLOCKEVENTS ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -255,9 +255,11 @@ MACHINE := arch/arm/mach-$(word 1,$(mac - else - MACHINE := - endif -+ifeq ($(CONFIG_ARCH_QCOM),) - ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y) - MACHINE := - endif -+endif - - machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) - platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y))) ---- /dev/null -+++ b/arch/arm/mach-qcom/Makefile.boot -@@ -0,0 +1 @@ -+zreladdr-y+= 0x42208000 diff --git a/target/linux/ipq806x/patches-4.19/0061-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch b/target/linux/ipq806x/patches-4.19/0061-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch deleted file mode 100644 index a4a957545b..0000000000 --- a/target/linux/ipq806x/patches-4.19/0061-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 09:31:44 +0100 -Subject: [PATCH 61/69] mtd: "rootfs" conflicts with OpenWrt auto mounting - -Signed-off-by: John Crispin ---- - drivers/mtd/qcom_smem_part.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mtd/qcom_smem_part.c -+++ b/drivers/mtd/qcom_smem_part.c -@@ -189,6 +189,10 @@ static int parse_qcom_smem_partitions(st - m_part->size = le32_to_cpu(s_part->size) * (*smem_blksz); - m_part->offset = le32_to_cpu(s_part->start) * (*smem_blksz); - -+ /* "rootfs" conflicts with OpenWrt auto mounting */ -+ if (mtd_type_is_nand(master) && !strcmp(m_part->name, "rootfs")) -+ m_part->name = "ubi"; -+ - /* - * The last SMEM partition may have its size marked as - * something like 0xffffffff, which means "until the end of the diff --git a/target/linux/ipq806x/patches-4.19/0062-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch b/target/linux/ipq806x/patches-4.19/0062-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch deleted file mode 100644 index 717934315a..0000000000 --- a/target/linux/ipq806x/patches-4.19/0062-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch +++ /dev/null @@ -1,25 +0,0 @@ -From a16fcf911a020e46439a3bb3e702463fc3159831 Mon Sep 17 00:00:00 2001 -From: Abhishek Sahu -Date: Wed, 18 Nov 2015 12:38:56 +0530 -Subject: [PATCH 62/69] ipq806x: gcc: Added the enable regs and mask for PRNG - -kernel got hanged while reading from /dev/hwrng at the -time of PRNG clock enable - -Change-Id: I89856c7e19e6639508e6a2774304583a3ec91172 -Signed-off-by: Abhishek Sahu ---- - drivers/clk/qcom/gcc-ipq806x.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -1233,6 +1233,8 @@ static struct clk_rcg prng_src = { - .parent_map = gcc_pxo_pll8_map, - }, - .clkr = { -+ .enable_reg = 0x2e80, -+ .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "prng_src", - .parent_names = gcc_pxo_pll8, diff --git a/target/linux/ipq806x/patches-4.19/0063-1-ipq806x-tsens-driver.patch b/target/linux/ipq806x/patches-4.19/0063-1-ipq806x-tsens-driver.patch deleted file mode 100644 index 9ee88533aa..0000000000 --- a/target/linux/ipq806x/patches-4.19/0063-1-ipq806x-tsens-driver.patch +++ /dev/null @@ -1,614 +0,0 @@ -From 3302e1e1a3cfa4e67fda2a61d6f0c42205d40932 Mon Sep 17 00:00:00 2001 -From: Rajith Cherian -Date: Tue, 14 Feb 2017 18:30:43 +0530 -Subject: [PATCH] ipq8064: tsens: Base tsens driver for IPQ8064 - -Add TSENS driver template to support IPQ8064. -This is a base file copied from tsens-8960.c - -Change-Id: I47c573fdfa2d898243c6a6ba952d1632f91391f7 -Signed-off-by: Rajith Cherian - -ipq8064: tsens: TSENS driver support for IPQ8064 - -Support for IPQ8064 tsens driver. The driver works -with the thermal framework. The driver overrides the -following fucntionalities: - -1. Get current temperature. -2. Get/Set trip temperatures. -3. Enabled/Disable trip points. -4. ISR for threshold generated interrupt. -5. Notify userspace when trip points are hit. - -Change-Id: I8bc7204fd627d10875ab13fc1de8cb6c2ed7a918 -Signed-off-by: Rajith Cherian ---- - ---- a/drivers/thermal/qcom/Makefile -+++ b/drivers/thermal/qcom/Makefile -@@ -1,2 +1,3 @@ - obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o --qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-v2.o -+qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-v2.o \ -+ tsens-ipq8064.o ---- /dev/null -+++ b/drivers/thermal/qcom/tsens-ipq8064.c -@@ -0,0 +1,551 @@ -+/* -+ * Copyright (c) 2015, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "tsens.h" -+ -+#define CAL_MDEGC 30000 -+ -+#define CONFIG_ADDR 0x3640 -+/* CONFIG_ADDR bitmasks */ -+#define CONFIG 0x9b -+#define CONFIG_MASK 0xf -+#define CONFIG_SHIFT 0 -+ -+#define STATUS_CNTL_8064 0x3660 -+#define CNTL_ADDR 0x3620 -+/* CNTL_ADDR bitmasks */ -+#define EN BIT(0) -+#define SW_RST BIT(1) -+#define SENSOR0_EN BIT(3) -+#define SLP_CLK_ENA BIT(26) -+#define MEASURE_PERIOD 1 -+#define SENSOR0_SHIFT 3 -+ -+/* INT_STATUS_ADDR bitmasks */ -+#define MIN_STATUS_MASK BIT(0) -+#define LOWER_STATUS_CLR BIT(1) -+#define UPPER_STATUS_CLR BIT(2) -+#define MAX_STATUS_MASK BIT(3) -+ -+#define THRESHOLD_ADDR 0x3624 -+/* THRESHOLD_ADDR bitmasks */ -+#define THRESHOLD_MAX_CODE 0x20000 -+#define THRESHOLD_MIN_CODE 0 -+#define THRESHOLD_MAX_LIMIT_SHIFT 24 -+#define THRESHOLD_MIN_LIMIT_SHIFT 16 -+#define THRESHOLD_UPPER_LIMIT_SHIFT 8 -+#define THRESHOLD_LOWER_LIMIT_SHIFT 0 -+#define THRESHOLD_MAX_LIMIT_MASK (THRESHOLD_MAX_CODE << \ -+ THRESHOLD_MAX_LIMIT_SHIFT) -+#define THRESHOLD_MIN_LIMIT_MASK (THRESHOLD_MAX_CODE << \ -+ THRESHOLD_MIN_LIMIT_SHIFT) -+#define THRESHOLD_UPPER_LIMIT_MASK (THRESHOLD_MAX_CODE << \ -+ THRESHOLD_UPPER_LIMIT_SHIFT) -+#define THRESHOLD_LOWER_LIMIT_MASK (THRESHOLD_MAX_CODE << \ -+ THRESHOLD_LOWER_LIMIT_SHIFT) -+ -+/* Initial temperature threshold values */ -+#define LOWER_LIMIT_TH 0x9d /* 95C */ -+#define UPPER_LIMIT_TH 0xa6 /* 105C */ -+#define MIN_LIMIT_TH 0x0 -+#define MAX_LIMIT_TH 0xff -+ -+#define S0_STATUS_ADDR 0x3628 -+#define STATUS_ADDR_OFFSET 2 -+#define SENSOR_STATUS_SIZE 4 -+#define INT_STATUS_ADDR 0x363c -+#define TRDY_MASK BIT(7) -+#define TIMEOUT_US 100 -+ -+#define TSENS_EN BIT(0) -+#define TSENS_SW_RST BIT(1) -+#define TSENS_ADC_CLK_SEL BIT(2) -+#define SENSOR0_EN BIT(3) -+#define SENSOR1_EN BIT(4) -+#define SENSOR2_EN BIT(5) -+#define SENSOR3_EN BIT(6) -+#define SENSOR4_EN BIT(7) -+#define SENSORS_EN (SENSOR0_EN | SENSOR1_EN | \ -+ SENSOR2_EN | SENSOR3_EN | SENSOR4_EN) -+#define TSENS_8064_SENSOR5_EN BIT(8) -+#define TSENS_8064_SENSOR6_EN BIT(9) -+#define TSENS_8064_SENSOR7_EN BIT(10) -+#define TSENS_8064_SENSOR8_EN BIT(11) -+#define TSENS_8064_SENSOR9_EN BIT(12) -+#define TSENS_8064_SENSOR10_EN BIT(13) -+#define TSENS_8064_SENSORS_EN (SENSORS_EN | \ -+ TSENS_8064_SENSOR5_EN | \ -+ TSENS_8064_SENSOR6_EN | \ -+ TSENS_8064_SENSOR7_EN | \ -+ TSENS_8064_SENSOR8_EN | \ -+ TSENS_8064_SENSOR9_EN | \ -+ TSENS_8064_SENSOR10_EN) -+ -+#define TSENS_8064_SEQ_SENSORS 5 -+#define TSENS_8064_S4_S5_OFFSET 40 -+#define TSENS_FACTOR 1 -+ -+/* Trips: from very hot to very cold */ -+enum tsens_trip_type { -+ TSENS_TRIP_STAGE3 = 0, -+ TSENS_TRIP_STAGE2, -+ TSENS_TRIP_STAGE1, -+ TSENS_TRIP_STAGE0, -+ TSENS_TRIP_NUM, -+}; -+ -+u32 tsens_8064_slope[] = { -+ 1176, 1176, 1154, 1176, -+ 1111, 1132, 1132, 1199, -+ 1132, 1199, 1132 -+ }; -+ -+/* Temperature on y axis and ADC-code on x-axis */ -+static inline int code_to_degC(u32 adc_code, const struct tsens_sensor *s) -+{ -+ int degcbeforefactor, degc; -+ -+ degcbeforefactor = (adc_code * s->slope) + s->offset; -+ -+ if (degcbeforefactor == 0) -+ degc = degcbeforefactor; -+ else if (degcbeforefactor > 0) -+ degc = (degcbeforefactor + TSENS_FACTOR/2) -+ / TSENS_FACTOR; -+ else -+ degc = (degcbeforefactor - TSENS_FACTOR/2) -+ / TSENS_FACTOR; -+ -+ return degc; -+} -+ -+static int degC_to_code(int degC, const struct tsens_sensor *s) -+{ -+ int code = ((degC * TSENS_FACTOR - s->offset) + (s->slope/2)) -+ / s->slope; -+ -+ if (code > THRESHOLD_MAX_CODE) -+ code = THRESHOLD_MAX_CODE; -+ else if (code < THRESHOLD_MIN_CODE) -+ code = THRESHOLD_MIN_CODE; -+ return code; -+} -+ -+static int suspend_ipq8064(struct tsens_device *tmdev) -+{ -+ int ret; -+ unsigned int mask; -+ struct regmap *map = tmdev->map; -+ -+ ret = regmap_read(map, THRESHOLD_ADDR, &tmdev->ctx.threshold); -+ if (ret) -+ return ret; -+ -+ ret = regmap_read(map, CNTL_ADDR, &tmdev->ctx.control); -+ if (ret) -+ return ret; -+ -+ mask = SLP_CLK_ENA | EN; -+ -+ ret = regmap_update_bits(map, CNTL_ADDR, mask, 0); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static int resume_ipq8064(struct tsens_device *tmdev) -+{ -+ int ret; -+ struct regmap *map = tmdev->map; -+ -+ ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST); -+ if (ret) -+ return ret; -+ -+ ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG); -+ if (ret) -+ return ret; -+ -+ ret = regmap_write(map, THRESHOLD_ADDR, tmdev->ctx.threshold); -+ if (ret) -+ return ret; -+ -+ ret = regmap_write(map, CNTL_ADDR, tmdev->ctx.control); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static void notify_uspace_tsens_fn(struct work_struct *work) -+{ -+ struct tsens_sensor *s = container_of(work, struct tsens_sensor, -+ notify_work); -+ -+ sysfs_notify(&s->tzd->device.kobj, NULL, "type"); -+} -+ -+static void tsens_scheduler_fn(struct work_struct *work) -+{ -+ struct tsens_device *tmdev = container_of(work, struct tsens_device, -+ tsens_work); -+ unsigned int threshold, threshold_low, code, reg, sensor, mask; -+ unsigned int sensor_addr; -+ bool upper_th_x, lower_th_x; -+ int adc_code, ret; -+ -+ ret = regmap_read(tmdev->map, STATUS_CNTL_8064, ®); -+ if (ret) -+ return; -+ reg = reg | LOWER_STATUS_CLR | UPPER_STATUS_CLR; -+ ret = regmap_write(tmdev->map, STATUS_CNTL_8064, reg); -+ if (ret) -+ return; -+ -+ mask = ~(LOWER_STATUS_CLR | UPPER_STATUS_CLR); -+ ret = regmap_read(tmdev->map, THRESHOLD_ADDR, &threshold); -+ if (ret) -+ return; -+ threshold_low = (threshold & THRESHOLD_LOWER_LIMIT_MASK) -+ >> THRESHOLD_LOWER_LIMIT_SHIFT; -+ threshold = (threshold & THRESHOLD_UPPER_LIMIT_MASK) -+ >> THRESHOLD_UPPER_LIMIT_SHIFT; -+ -+ ret = regmap_read(tmdev->map, STATUS_CNTL_8064, ®); -+ if (ret) -+ return; -+ -+ ret = regmap_read(tmdev->map, CNTL_ADDR, &sensor); -+ if (ret) -+ return; -+ sensor &= (uint32_t) TSENS_8064_SENSORS_EN; -+ sensor >>= SENSOR0_SHIFT; -+ -+ /* Constraint: There is only 1 interrupt control register for all -+ * 11 temperature sensor. So monitoring more than 1 sensor based -+ * on interrupts will yield inconsistent result. To overcome this -+ * issue we will monitor only sensor 0 which is the master sensor. -+ */ -+ -+ /* Skip if the sensor is disabled */ -+ if (sensor & 1) { -+ ret = regmap_read(tmdev->map, tmdev->sensor[0].status, &code); -+ if (ret) -+ return; -+ upper_th_x = code >= threshold; -+ lower_th_x = code <= threshold_low; -+ if (upper_th_x) -+ mask |= UPPER_STATUS_CLR; -+ if (lower_th_x) -+ mask |= LOWER_STATUS_CLR; -+ if (upper_th_x || lower_th_x) { -+ /* Notify user space */ -+ schedule_work(&tmdev->sensor[0].notify_work); -+ regmap_read(tmdev->map, sensor_addr, &adc_code); -+ pr_debug("Trigger (%d degrees) for sensor %d\n", -+ code_to_degC(adc_code, &tmdev->sensor[0]), 0); -+ } -+ } -+ regmap_write(tmdev->map, STATUS_CNTL_8064, reg & mask); -+ -+ /* force memory to sync */ -+ mb(); -+} -+ -+static irqreturn_t tsens_isr(int irq, void *data) -+{ -+ struct tsens_device *tmdev = data; -+ -+ schedule_work(&tmdev->tsens_work); -+ return IRQ_HANDLED; -+} -+ -+static void hw_init(struct tsens_device *tmdev) -+{ -+ int ret; -+ unsigned int reg_cntl = 0, reg_cfg = 0, reg_thr = 0; -+ unsigned int reg_status_cntl = 0; -+ -+ regmap_read(tmdev->map, CNTL_ADDR, ®_cntl); -+ regmap_write(tmdev->map, CNTL_ADDR, reg_cntl | TSENS_SW_RST); -+ -+ reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18) -+ | (((1 << tmdev->num_sensors) - 1) << SENSOR0_SHIFT); -+ regmap_write(tmdev->map, CNTL_ADDR, reg_cntl); -+ regmap_read(tmdev->map, STATUS_CNTL_8064, ®_status_cntl); -+ reg_status_cntl |= LOWER_STATUS_CLR | UPPER_STATUS_CLR -+ | MIN_STATUS_MASK | MAX_STATUS_MASK; -+ regmap_write(tmdev->map, STATUS_CNTL_8064, reg_status_cntl); -+ reg_cntl |= TSENS_EN; -+ regmap_write(tmdev->map, CNTL_ADDR, reg_cntl); -+ -+ regmap_read(tmdev->map, CONFIG_ADDR, ®_cfg); -+ reg_cfg = (reg_cfg & ~CONFIG_MASK) | (CONFIG << CONFIG_SHIFT); -+ regmap_write(tmdev->map, CONFIG_ADDR, reg_cfg); -+ -+ reg_thr |= (LOWER_LIMIT_TH << THRESHOLD_LOWER_LIMIT_SHIFT) -+ | (UPPER_LIMIT_TH << THRESHOLD_UPPER_LIMIT_SHIFT) -+ | (MIN_LIMIT_TH << THRESHOLD_MIN_LIMIT_SHIFT) -+ | (MAX_LIMIT_TH << THRESHOLD_MAX_LIMIT_SHIFT); -+ -+ regmap_write(tmdev->map, THRESHOLD_ADDR, reg_thr); -+ -+ ret = devm_request_irq(tmdev->dev, tmdev->tsens_irq, tsens_isr, -+ IRQF_TRIGGER_RISING, "tsens_interrupt", tmdev); -+ if (ret < 0) { -+ pr_err("%s: request_irq FAIL: %d\n", __func__, ret); -+ return; -+ } -+ -+ INIT_WORK(&tmdev->tsens_work, tsens_scheduler_fn); -+} -+ -+static int init_ipq8064(struct tsens_device *tmdev) -+{ -+ int ret, i; -+ u32 reg_cntl, offset = 0; -+ -+ init_common(tmdev); -+ if (!tmdev->map) -+ return -ENODEV; -+ -+ /* -+ * The status registers for each sensor are discontiguous -+ * because some SoCs have 5 sensors while others have more -+ * but the control registers stay in the same place, i.e -+ * directly after the first 5 status registers. -+ */ -+ for (i = 0; i < tmdev->num_sensors; i++) { -+ if (i >= TSENS_8064_SEQ_SENSORS) -+ offset = TSENS_8064_S4_S5_OFFSET; -+ -+ tmdev->sensor[i].status = S0_STATUS_ADDR + offset -+ + (i << STATUS_ADDR_OFFSET); -+ tmdev->sensor[i].slope = tsens_8064_slope[i]; -+ INIT_WORK(&tmdev->sensor[i].notify_work, -+ notify_uspace_tsens_fn); -+ } -+ -+ reg_cntl = SW_RST; -+ ret = regmap_update_bits(tmdev->map, CNTL_ADDR, SW_RST, reg_cntl); -+ if (ret) -+ return ret; -+ -+ reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18); -+ reg_cntl &= ~SW_RST; -+ ret = regmap_update_bits(tmdev->map, CONFIG_ADDR, -+ CONFIG_MASK, CONFIG); -+ -+ reg_cntl |= GENMASK(tmdev->num_sensors - 1, 0) << SENSOR0_SHIFT; -+ ret = regmap_write(tmdev->map, CNTL_ADDR, reg_cntl); -+ if (ret) -+ return ret; -+ -+ reg_cntl |= EN; -+ ret = regmap_write(tmdev->map, CNTL_ADDR, reg_cntl); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static int calibrate_ipq8064(struct tsens_device *tmdev) -+{ -+ int i; -+ char *data, *data_backup; -+ -+ ssize_t num_read = tmdev->num_sensors; -+ struct tsens_sensor *s = tmdev->sensor; -+ -+ data = qfprom_read(tmdev->dev, "calib"); -+ if (IS_ERR(data)) { -+ pr_err("Calibration not found.\n"); -+ return PTR_ERR(data); -+ } -+ -+ data_backup = qfprom_read(tmdev->dev, "calib_backup"); -+ if (IS_ERR(data_backup)) { -+ pr_err("Backup calibration not found.\n"); -+ return PTR_ERR(data_backup); -+ } -+ -+ for (i = 0; i < num_read; i++) { -+ s[i].calib_data = readb_relaxed(data + i); -+ s[i].calib_data_backup = readb_relaxed(data_backup + i); -+ -+ if (s[i].calib_data_backup) -+ s[i].calib_data = s[i].calib_data_backup; -+ if (!s[i].calib_data) { -+ pr_err("QFPROM TSENS calibration data not present\n"); -+ return -ENODEV; -+ } -+ s[i].slope = tsens_8064_slope[i]; -+ s[i].offset = CAL_MDEGC - (s[i].calib_data * s[i].slope); -+ } -+ -+ hw_init(tmdev); -+ -+ return 0; -+} -+ -+static int get_temp_ipq8064(struct tsens_device *tmdev, int id, int *temp) -+{ -+ int ret; -+ u32 code, trdy; -+ const struct tsens_sensor *s = &tmdev->sensor[id]; -+ unsigned long timeout; -+ -+ timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); -+ do { -+ ret = regmap_read(tmdev->map, INT_STATUS_ADDR, &trdy); -+ if (ret) -+ return ret; -+ if (!(trdy & TRDY_MASK)) -+ continue; -+ ret = regmap_read(tmdev->map, s->status, &code); -+ if (ret) -+ return ret; -+ *temp = code_to_degC(code, s); -+ return 0; -+ } while (time_before(jiffies, timeout)); -+ -+ return -ETIMEDOUT; -+} -+ -+static int set_trip_temp_ipq8064(void *data, int trip, int temp) -+{ -+ unsigned int reg_th, reg_cntl; -+ int ret, code, code_chk, hi_code, lo_code; -+ const struct tsens_sensor *s = data; -+ struct tsens_device *tmdev = s->tmdev; -+ -+ code_chk = code = degC_to_code(temp, s); -+ -+ if (code < THRESHOLD_MIN_CODE || code > THRESHOLD_MAX_CODE) -+ return -EINVAL; -+ -+ ret = regmap_read(tmdev->map, STATUS_CNTL_8064, ®_cntl); -+ if (ret) -+ return ret; -+ -+ ret = regmap_read(tmdev->map, THRESHOLD_ADDR, ®_th); -+ if (ret) -+ return ret; -+ -+ hi_code = (reg_th & THRESHOLD_UPPER_LIMIT_MASK) -+ >> THRESHOLD_UPPER_LIMIT_SHIFT; -+ lo_code = (reg_th & THRESHOLD_LOWER_LIMIT_MASK) -+ >> THRESHOLD_LOWER_LIMIT_SHIFT; -+ -+ switch (trip) { -+ case TSENS_TRIP_STAGE3: -+ code <<= THRESHOLD_MAX_LIMIT_SHIFT; -+ reg_th &= ~THRESHOLD_MAX_LIMIT_MASK; -+ break; -+ case TSENS_TRIP_STAGE2: -+ if (code_chk <= lo_code) -+ return -EINVAL; -+ code <<= THRESHOLD_UPPER_LIMIT_SHIFT; -+ reg_th &= ~THRESHOLD_UPPER_LIMIT_MASK; -+ break; -+ case TSENS_TRIP_STAGE1: -+ if (code_chk >= hi_code) -+ return -EINVAL; -+ code <<= THRESHOLD_LOWER_LIMIT_SHIFT; -+ reg_th &= ~THRESHOLD_LOWER_LIMIT_MASK; -+ break; -+ case TSENS_TRIP_STAGE0: -+ code <<= THRESHOLD_MIN_LIMIT_SHIFT; -+ reg_th &= ~THRESHOLD_MIN_LIMIT_MASK; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ ret = regmap_write(tmdev->map, THRESHOLD_ADDR, reg_th | code); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static int set_trip_activate_ipq8064(void *data, int trip, -+ enum thermal_trip_activation_mode mode) -+{ -+ unsigned int reg_cntl, mask, val; -+ const struct tsens_sensor *s = data; -+ struct tsens_device *tmdev = s->tmdev; -+ int ret; -+ -+ if (!tmdev || trip < 0) -+ return -EINVAL; -+ -+ ret = regmap_read(tmdev->map, STATUS_CNTL_8064, ®_cntl); -+ if (ret) -+ return ret; -+ -+ switch (trip) { -+ case TSENS_TRIP_STAGE3: -+ mask = MAX_STATUS_MASK; -+ break; -+ case TSENS_TRIP_STAGE2: -+ mask = UPPER_STATUS_CLR; -+ break; -+ case TSENS_TRIP_STAGE1: -+ mask = LOWER_STATUS_CLR; -+ break; -+ case TSENS_TRIP_STAGE0: -+ mask = MIN_STATUS_MASK; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (mode == THERMAL_TRIP_ACTIVATION_DISABLED) -+ val = reg_cntl | mask; -+ else -+ val = reg_cntl & ~mask; -+ -+ ret = regmap_write(tmdev->map, STATUS_CNTL_8064, val); -+ if (ret) -+ return ret; -+ -+ /* force memory to sync */ -+ mb(); -+ return 0; -+} -+ -+const struct tsens_ops ops_ipq8064 = { -+ .init = init_ipq8064, -+ .calibrate = calibrate_ipq8064, -+ .get_temp = get_temp_ipq8064, -+ .suspend = suspend_ipq8064, -+ .resume = resume_ipq8064, -+ .set_trip_temp = set_trip_temp_ipq8064, -+ .set_trip_activate = set_trip_activate_ipq8064, -+}; -+ -+const struct tsens_data data_ipq8064 = { -+ .num_sensors = 11, -+ .ops = &ops_ipq8064, -+}; ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -75,8 +75,11 @@ static const struct of_device_id tsens_t - }, { - .compatible = "qcom,tsens-v2", - .data = &data_tsens_v2, -+ }, { -+ .compatible = "qcom,ipq8064-tsens", -+ .data = &data_ipq8064, - }, -- {} -+ {} - }; - MODULE_DEVICE_TABLE(of, tsens_table); - ---- a/drivers/thermal/qcom/tsens.h -+++ b/drivers/thermal/qcom/tsens.h -@@ -89,7 +89,7 @@ int init_common(struct tsens_device *); - int get_temp_common(struct tsens_device *, int, int *); - - /* TSENS v1 targets */ --extern const struct tsens_data data_8916, data_8974, data_8960; -+extern const struct tsens_data data_8916, data_8974, data_8960, data_ipq8064; - /* TSENS v2 targets */ - extern const struct tsens_data data_8996, data_tsens_v2; - diff --git a/target/linux/ipq806x/patches-4.19/0063-2-tsens-support-configurable-interrupts.patch b/target/linux/ipq806x/patches-4.19/0063-2-tsens-support-configurable-interrupts.patch deleted file mode 100644 index 62e26cbee4..0000000000 --- a/target/linux/ipq806x/patches-4.19/0063-2-tsens-support-configurable-interrupts.patch +++ /dev/null @@ -1,434 +0,0 @@ -From 4e87400732c77765afae2ea89ed43837457aa604 Mon Sep 17 00:00:00 2001 -From: Rajith Cherian -Date: Wed, 1 Feb 2017 19:00:26 +0530 -Subject: [PATCH] ipq8064: tsens: Support for configurable interrupts - -Provide support for adding configurable high and -configurable low trip temperatures. An interrupts is -also triggerred when these trip points are hit. The -interrupts can be activated or deactivated from sysfs. -This functionality is made available only if -CONFIG_THERMAL_WRITABLE_TRIPS is defined. - -Change-Id: Ib73f3f9459de4fffce7bb985a0312a88291f4934 -Signed-off-by: Rajith Cherian ---- - .../devicetree/bindings/thermal/qcom-tsens.txt | 4 ++ - drivers/thermal/of-thermal.c | 63 ++++++++++++++++++---- - drivers/thermal/qcom/tsens.c | 43 ++++++++++++--- - drivers/thermal/qcom/tsens.h | 11 ++++ - drivers/thermal/thermal_core.c | 44 ++++++++++++++- - include/linux/thermal.h | 14 +++++ - 6 files changed, 162 insertions(+), 17 deletions(-) - ---- a/drivers/thermal/of-thermal.c -+++ b/drivers/thermal/of-thermal.c -@@ -77,7 +77,7 @@ static int of_thermal_get_temp(struct th - { - struct __thermal_zone *data = tz->devdata; - -- if (!data->ops->get_temp) -+ if (!data->ops->get_temp || (data->mode == THERMAL_DEVICE_DISABLED)) - return -EINVAL; - - return data->ops->get_temp(data->sensor_data, temp); -@@ -88,7 +88,8 @@ static int of_thermal_set_trips(struct t - { - struct __thermal_zone *data = tz->devdata; - -- if (!data->ops || !data->ops->set_trips) -+ if (!data->ops || !data->ops->set_trips -+ || (data->mode == THERMAL_DEVICE_DISABLED)) - return -EINVAL; - - return data->ops->set_trips(data->sensor_data, low, high); -@@ -174,6 +175,9 @@ static int of_thermal_set_emul_temp(stru - { - struct __thermal_zone *data = tz->devdata; - -+ if (data->mode == THERMAL_DEVICE_DISABLED) -+ return -EINVAL; -+ - return data->ops->set_emul_temp(data->sensor_data, temp); - } - -@@ -182,7 +186,7 @@ static int of_thermal_get_trend(struct t - { - struct __thermal_zone *data = tz->devdata; - -- if (!data->ops->get_trend) -+ if (!data->ops->get_trend || (data->mode == THERMAL_DEVICE_DISABLED)) - return -EINVAL; - - return data->ops->get_trend(data->sensor_data, trip, trend); -@@ -271,7 +275,9 @@ static int of_thermal_set_mode(struct th - mutex_unlock(&tz->lock); - - data->mode = mode; -- thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED); -+ -+ if (mode == THERMAL_DEVICE_ENABLED) -+ thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED); - - return 0; - } -@@ -281,7 +287,8 @@ static int of_thermal_get_trip_type(stru - { - struct __thermal_zone *data = tz->devdata; - -- if (trip >= data->ntrips || trip < 0) -+ if (trip >= data->ntrips || trip < 0 -+ || (data->mode == THERMAL_DEVICE_DISABLED)) - return -EDOM; - - *type = data->trips[trip].type; -@@ -289,12 +296,39 @@ static int of_thermal_get_trip_type(stru - return 0; - } - -+static int of_thermal_activate_trip_type(struct thermal_zone_device *tz, -+ int trip, enum thermal_trip_activation_mode mode) -+{ -+ struct __thermal_zone *data = tz->devdata; -+ -+ if (trip >= data->ntrips || trip < 0 -+ || (data->mode == THERMAL_DEVICE_DISABLED)) -+ return -EDOM; -+ -+ /* -+ * The configurable_hi and configurable_lo trip points can be -+ * activated and deactivated. -+ */ -+ -+ if (data->ops->set_trip_activate) { -+ int ret; -+ -+ ret = data->ops->set_trip_activate(data->sensor_data, -+ trip, mode); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ - static int of_thermal_get_trip_temp(struct thermal_zone_device *tz, int trip, - int *temp) - { - struct __thermal_zone *data = tz->devdata; - -- if (trip >= data->ntrips || trip < 0) -+ if (trip >= data->ntrips || trip < 0 -+ || (data->mode == THERMAL_DEVICE_DISABLED)) - return -EDOM; - - *temp = data->trips[trip].temperature; -@@ -307,7 +341,8 @@ static int of_thermal_set_trip_temp(stru - { - struct __thermal_zone *data = tz->devdata; - -- if (trip >= data->ntrips || trip < 0) -+ if (trip >= data->ntrips || trip < 0 -+ || (data->mode == THERMAL_DEVICE_DISABLED)) - return -EDOM; - - if (data->ops->set_trip_temp) { -@@ -329,7 +364,8 @@ static int of_thermal_get_trip_hyst(stru - { - struct __thermal_zone *data = tz->devdata; - -- if (trip >= data->ntrips || trip < 0) -+ if (trip >= data->ntrips || trip < 0 -+ || (data->mode == THERMAL_DEVICE_DISABLED)) - return -EDOM; - - *hyst = data->trips[trip].hysteresis; -@@ -342,7 +378,8 @@ static int of_thermal_set_trip_hyst(stru - { - struct __thermal_zone *data = tz->devdata; - -- if (trip >= data->ntrips || trip < 0) -+ if (trip >= data->ntrips || trip < 0 -+ || (data->mode == THERMAL_DEVICE_DISABLED)) - return -EDOM; - - /* thermal framework should take care of data->mask & (1 << trip) */ -@@ -417,6 +454,9 @@ thermal_zone_of_add_sensor(struct device - if (ops->set_emul_temp) - tzd->ops->set_emul_temp = of_thermal_set_emul_temp; - -+ if (ops->set_trip_activate) -+ tzd->ops->set_trip_activate = of_thermal_activate_trip_type; -+ - mutex_unlock(&tzd->lock); - - return tzd; -@@ -711,7 +751,10 @@ static const char * const trip_types[] = - [THERMAL_TRIP_ACTIVE] = "active", - [THERMAL_TRIP_PASSIVE] = "passive", - [THERMAL_TRIP_HOT] = "hot", -- [THERMAL_TRIP_CRITICAL] = "critical", -+ [THERMAL_TRIP_CRITICAL] = "critical_high", -+ [THERMAL_TRIP_CONFIGURABLE_HI] = "configurable_hi", -+ [THERMAL_TRIP_CONFIGURABLE_LOW] = "configurable_lo", -+ [THERMAL_TRIP_CRITICAL_LOW] = "critical_low", - }; - - /** ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -31,7 +31,7 @@ static int tsens_get_temp(void *data, in - - static int tsens_get_trend(void *p, int trip, enum thermal_trend *trend) - { -- const struct tsens_sensor *s = p; -+ struct tsens_sensor *s = p; - struct tsens_device *tmdev = s->tmdev; - - if (tmdev->ops->get_trend) -@@ -40,9 +40,10 @@ static int tsens_get_trend(void *p, int - return -ENOTSUPP; - } - --static int __maybe_unused tsens_suspend(struct device *dev) -+static int __maybe_unused tsens_suspend(void *data) - { -- struct tsens_device *tmdev = dev_get_drvdata(dev); -+ struct tsens_sensor *s = data; -+ struct tsens_device *tmdev = s->tmdev; - - if (tmdev->ops && tmdev->ops->suspend) - return tmdev->ops->suspend(tmdev); -@@ -50,9 +51,10 @@ static int __maybe_unused tsens_suspend - return 0; - } - --static int __maybe_unused tsens_resume(struct device *dev) -+static int __maybe_unused tsens_resume(void *data) - { -- struct tsens_device *tmdev = dev_get_drvdata(dev); -+ struct tsens_sensor *s = data; -+ struct tsens_device *tmdev = s->tmdev; - - if (tmdev->ops && tmdev->ops->resume) - return tmdev->ops->resume(tmdev); -@@ -60,6 +62,30 @@ static int __maybe_unused tsens_resume(s - return 0; - } - -+static int __maybe_unused tsens_set_trip_temp(void *data, int trip, int temp) -+{ -+ struct tsens_sensor *s = data; -+ struct tsens_device *tmdev = s->tmdev; -+ -+ if (tmdev->ops && tmdev->ops->set_trip_temp) -+ return tmdev->ops->set_trip_temp(s, trip, temp); -+ -+ return 0; -+} -+ -+static int __maybe_unused tsens_activate_trip_type(void *data, int trip, -+ enum thermal_trip_activation_mode mode) -+{ -+ struct tsens_sensor *s = data; -+ struct tsens_device *tmdev = s->tmdev; -+ -+ if (tmdev->ops && tmdev->ops->set_trip_activate) -+ return tmdev->ops->set_trip_activate(s, trip, mode); -+ -+ return 0; -+} -+ -+ - static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume); - - static const struct of_device_id tsens_table[] = { -@@ -86,6 +112,8 @@ MODULE_DEVICE_TABLE(of, tsens_table); - static const struct thermal_zone_of_device_ops tsens_of_ops = { - .get_temp = tsens_get_temp, - .get_trend = tsens_get_trend, -+ .set_trip_temp = tsens_set_trip_temp, -+ .set_trip_activate = tsens_activate_trip_type, - }; - - static int tsens_register(struct tsens_device *tmdev) -@@ -134,7 +162,7 @@ static int tsens_probe(struct platform_d - if (id) - data = id->data; - else -- data = &data_8960; -+ return -EINVAL; - - num_sensors = data->num_sensors; - -@@ -155,6 +183,9 @@ static int tsens_probe(struct platform_d - tmdev->dev = dev; - tmdev->num_sensors = num_sensors; - tmdev->ops = data->ops; -+ -+ tmdev->tsens_irq = platform_get_irq(pdev, 0); -+ - for (i = 0; i < tmdev->num_sensors; i++) { - if (data->hw_ids) - tmdev->sensor[i].hw_id = data->hw_ids[i]; ---- a/drivers/thermal/qcom/tsens.h -+++ b/drivers/thermal/qcom/tsens.h -@@ -24,9 +24,12 @@ struct tsens_device; - struct tsens_sensor { - struct tsens_device *tmdev; - struct thermal_zone_device *tzd; -+ struct work_struct notify_work; - int offset; - int id; - int hw_id; -+ int calib_data; -+ int calib_data_backup; - int slope; - u32 status; - }; -@@ -41,6 +44,9 @@ struct tsens_sensor { - * @suspend: Function to suspend the tsens device - * @resume: Function to resume the tsens device - * @get_trend: Function to get the thermal/temp trend -+ * @set_trip_temp: Function to set trip temp -+ * @get_trip_temp: Function to get trip temp -+ * @set_trip_activate: Function to activate trip points - */ - struct tsens_ops { - /* mandatory callbacks */ -@@ -53,6 +59,9 @@ struct tsens_ops { - int (*suspend)(struct tsens_device *); - int (*resume)(struct tsens_device *); - int (*get_trend)(struct tsens_device *, int, enum thermal_trend *); -+ int (*set_trip_temp)(void *, int, int); -+ int (*set_trip_activate)(void *, int, -+ enum thermal_trip_activation_mode); - }; - - /** -@@ -76,10 +85,12 @@ struct tsens_context { - struct tsens_device { - struct device *dev; - u32 num_sensors; -+ u32 tsens_irq; - struct regmap *map; - u32 tm_offset; - struct tsens_context ctx; - const struct tsens_ops *ops; -+ struct work_struct tsens_work; - struct tsens_sensor sensor[0]; - }; - ---- a/drivers/thermal/thermal_sysfs.c -+++ b/drivers/thermal/thermal_sysfs.c -@@ -113,12 +113,48 @@ trip_point_type_show(struct device *dev, - return sprintf(buf, "passive\n"); - case THERMAL_TRIP_ACTIVE: - return sprintf(buf, "active\n"); -+ case THERMAL_TRIP_CONFIGURABLE_HI: -+ return sprintf(buf, "configurable_hi\n"); -+ case THERMAL_TRIP_CONFIGURABLE_LOW: -+ return sprintf(buf, "configurable_low\n"); -+ case THERMAL_TRIP_CRITICAL_LOW: -+ return sprintf(buf, "critical_low\n"); - default: - return sprintf(buf, "unknown\n"); - } - } - - static ssize_t -+trip_point_type_activate(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct thermal_zone_device *tz = to_thermal_zone(dev); -+ int trip, ret; -+ char *enabled = "enabled"; -+ char *disabled = "disabled"; -+ -+ if (!tz->ops->set_trip_activate) -+ return -EPERM; -+ -+ if (!sscanf(attr->attr.name, "trip_point_%d_type", &trip)) -+ return -EINVAL; -+ -+ if (!strncmp(buf, enabled, strlen(enabled))) -+ ret = tz->ops->set_trip_activate(tz, trip, -+ THERMAL_TRIP_ACTIVATION_ENABLED); -+ else if (!strncmp(buf, disabled, strlen(disabled))) -+ ret = tz->ops->set_trip_activate(tz, trip, -+ THERMAL_TRIP_ACTIVATION_DISABLED); -+ else -+ ret = -EINVAL; -+ -+ if (ret) -+ return ret; -+ -+ return count; -+} -+ -+static ssize_t - trip_point_temp_store(struct device *dev, struct device_attribute *attr, - const char *buf, size_t count) - { -@@ -559,6 +595,12 @@ static int create_trip_attrs(struct ther - tz->trip_type_attrs[indx].attr.show = trip_point_type_show; - attrs[indx] = &tz->trip_type_attrs[indx].attr.attr; - -+ if (IS_ENABLED(CONFIG_THERMAL_WRITABLE_TRIPS)) { -+ tz->trip_type_attrs[indx].attr.store -+ = trip_point_type_activate; -+ tz->trip_type_attrs[indx].attr.attr.mode |= S_IWUSR; -+ } -+ - /* create trip temp attribute */ - snprintf(tz->trip_temp_attrs[indx].name, THERMAL_NAME_LENGTH, - "trip_point_%d_temp", indx); ---- a/include/linux/thermal.h -+++ b/include/linux/thermal.h -@@ -63,11 +63,19 @@ enum thermal_device_mode { - THERMAL_DEVICE_ENABLED, - }; - -+enum thermal_trip_activation_mode { -+ THERMAL_TRIP_ACTIVATION_DISABLED = 0, -+ THERMAL_TRIP_ACTIVATION_ENABLED, -+}; -+ - enum thermal_trip_type { - THERMAL_TRIP_ACTIVE = 0, - THERMAL_TRIP_PASSIVE, - THERMAL_TRIP_HOT, - THERMAL_TRIP_CRITICAL, -+ THERMAL_TRIP_CONFIGURABLE_HI, -+ THERMAL_TRIP_CONFIGURABLE_LOW, -+ THERMAL_TRIP_CRITICAL_LOW, - }; - - enum thermal_trend { -@@ -105,6 +113,8 @@ struct thermal_zone_device_ops { - enum thermal_trip_type *); - int (*get_trip_temp) (struct thermal_zone_device *, int, int *); - int (*set_trip_temp) (struct thermal_zone_device *, int, int); -+ int (*set_trip_activate) (struct thermal_zone_device *, int, -+ enum thermal_trip_activation_mode); - int (*get_trip_hyst) (struct thermal_zone_device *, int, int *); - int (*set_trip_hyst) (struct thermal_zone_device *, int, int); - int (*get_crit_temp) (struct thermal_zone_device *, int *); -@@ -349,6 +359,8 @@ struct thermal_genl_event { - * temperature. - * @set_trip_temp: a pointer to a function that sets the trip temperature on - * hardware. -+ * @activate_trip_type: a pointer to a function to enable/disable trip -+ * temperature interrupts - */ - struct thermal_zone_of_device_ops { - int (*get_temp)(void *, int *); -@@ -356,6 +368,8 @@ struct thermal_zone_of_device_ops { - int (*set_trips)(void *, int, int); - int (*set_emul_temp)(void *, int); - int (*set_trip_temp)(void *, int, int); -+ int (*set_trip_activate)(void *, int, -+ enum thermal_trip_activation_mode); - }; - - /** diff --git a/target/linux/ipq806x/patches-4.19/0063-3-tsens-fix-kernel-4_19.patch b/target/linux/ipq806x/patches-4.19/0063-3-tsens-fix-kernel-4_19.patch deleted file mode 100644 index a870692906..0000000000 --- a/target/linux/ipq806x/patches-4.19/0063-3-tsens-fix-kernel-4_19.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/thermal/qcom/tsens-common.c -+++ b/drivers/thermal/qcom/tsens-common.c -@@ -128,6 +128,7 @@ int __init init_common(struct tsens_devi - { - void __iomem *base; - struct resource *res; -+ resource_size_t size; - struct platform_device *op = of_find_device_by_node(tmdev->dev->of_node); - - if (!op) -@@ -142,7 +143,8 @@ int __init init_common(struct tsens_devi - } - - res = platform_get_resource(op, IORESOURCE_MEM, 0); -- base = devm_ioremap_resource(&op->dev, res); -+ size = resource_size(res); -+ base = devm_ioremap(&op->dev, res->start, size); - if (IS_ERR(base)) - return PTR_ERR(base); - diff --git a/target/linux/ipq806x/patches-4.19/0063-4-ip806x-tsense-rework-driver.patch b/target/linux/ipq806x/patches-4.19/0063-4-ip806x-tsense-rework-driver.patch deleted file mode 100644 index 951145b3de..0000000000 --- a/target/linux/ipq806x/patches-4.19/0063-4-ip806x-tsense-rework-driver.patch +++ /dev/null @@ -1,107 +0,0 @@ ---- a/drivers/thermal/qcom/tsens-ipq8064.c -+++ b/drivers/thermal/qcom/tsens-ipq8064.c -@@ -13,10 +13,12 @@ - */ - - #include -+#include - #include - #include - #include - #include -+#include - #include - #include - #include -@@ -210,9 +212,8 @@ static void tsens_scheduler_fn(struct wo - struct tsens_device *tmdev = container_of(work, struct tsens_device, - tsens_work); - unsigned int threshold, threshold_low, code, reg, sensor, mask; -- unsigned int sensor_addr; - bool upper_th_x, lower_th_x; -- int adc_code, ret; -+ int ret; - - ret = regmap_read(tmdev->map, STATUS_CNTL_8064, ®); - if (ret) -@@ -261,9 +262,8 @@ static void tsens_scheduler_fn(struct wo - if (upper_th_x || lower_th_x) { - /* Notify user space */ - schedule_work(&tmdev->sensor[0].notify_work); -- regmap_read(tmdev->map, sensor_addr, &adc_code); - pr_debug("Trigger (%d degrees) for sensor %d\n", -- code_to_degC(adc_code, &tmdev->sensor[0]), 0); -+ code_to_degC(code, &tmdev->sensor[0]), 0); - } - } - regmap_write(tmdev->map, STATUS_CNTL_8064, reg & mask); -@@ -372,40 +372,55 @@ static int init_ipq8064(struct tsens_dev - static int calibrate_ipq8064(struct tsens_device *tmdev) - { - int i; -- char *data, *data_backup; -- -+ int ret = 0; -+ u8 *data, *data_backup; -+ struct device *dev = tmdev->dev; - ssize_t num_read = tmdev->num_sensors; - struct tsens_sensor *s = tmdev->sensor; - -- data = qfprom_read(tmdev->dev, "calib"); -+ data = qfprom_read(dev, "calib"); - if (IS_ERR(data)) { -- pr_err("Calibration not found.\n"); -- return PTR_ERR(data); -+ ret = PTR_ERR(data); -+ if (ret != -EPROBE_DEFER) -+ dev_err(dev, "Calibration not found."); -+ goto exit; - } - -- data_backup = qfprom_read(tmdev->dev, "calib_backup"); -+ data_backup = qfprom_read(dev, "calib_backup"); - if (IS_ERR(data_backup)) { -- pr_err("Backup calibration not found.\n"); -- return PTR_ERR(data_backup); -+ ret = PTR_ERR(data_backup); -+ if (ret != -EPROBE_DEFER) -+ dev_err(dev, "Backup Calibration not found."); -+ goto free_data; - } - - for (i = 0; i < num_read; i++) { - s[i].calib_data = readb_relaxed(data + i); -- s[i].calib_data_backup = readb_relaxed(data_backup + i); -+ -+ if (!s[i].calib_data) { -+ s[i].calib_data_backup = readb_relaxed(data_backup + i); -+ -+ if (!s[i].calib_data_backup) { -+ dev_err(dev, "QFPROM TSENS calibration data not present"); -+ ret = -ENODEV; -+ goto free_backup; -+ } - -- if (s[i].calib_data_backup) - s[i].calib_data = s[i].calib_data_backup; -- if (!s[i].calib_data) { -- pr_err("QFPROM TSENS calibration data not present\n"); -- return -ENODEV; - } -+ - s[i].slope = tsens_8064_slope[i]; - s[i].offset = CAL_MDEGC - (s[i].calib_data * s[i].slope); - } - - hw_init(tmdev); - -- return 0; -+free_backup: -+ kfree(data_backup); -+free_data: -+ kfree(data); -+exit: -+ return ret; - } - - static int get_temp_ipq8064(struct tsens_device *tmdev, int id, int *temp) diff --git a/target/linux/ipq806x/patches-4.19/0064-clk-clk-rpm-fixes.patch b/target/linux/ipq806x/patches-4.19/0064-clk-clk-rpm-fixes.patch deleted file mode 100644 index 72217de12e..0000000000 --- a/target/linux/ipq806x/patches-4.19/0064-clk-clk-rpm-fixes.patch +++ /dev/null @@ -1,95 +0,0 @@ -From d30840e2b1cf79d90392e6051b0c0b6006d29d8b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 09:32:40 +0100 -Subject: [PATCH 64/69] clk: clk-rpm fixes - -Signed-off-by: John Crispin ---- - .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 + - drivers/clk/qcom/clk-rpm.c | 35 ++++++++++++++++++++++ - include/dt-bindings/clock/qcom,rpmcc.h | 4 +++ - 3 files changed, 40 insertions(+) - ---- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt -+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt -@@ -16,6 +16,7 @@ Required properties : - "qcom,rpmcc-msm8974", "qcom,rpmcc" - "qcom,rpmcc-apq8064", "qcom,rpmcc" - "qcom,rpmcc-msm8996", "qcom,rpmcc" -+ "qcom,rpmcc-ipq806x", "qcom,rpmcc" - - - #clock-cells : shall contain 1 - ---- a/include/dt-bindings/clock/qcom,rpmcc.h -+++ b/include/dt-bindings/clock/qcom,rpmcc.h -@@ -45,6 +45,10 @@ - #define RPM_XO_A0 27 - #define RPM_XO_A1 28 - #define RPM_XO_A2 29 -+#define RPM_NSS_FABRIC_0_CLK 30 -+#define RPM_NSS_FABRIC_0_A_CLK 31 -+#define RPM_NSS_FABRIC_1_CLK 32 -+#define RPM_NSS_FABRIC_1_A_CLK 33 - - /* SMD RPM clocks */ - #define RPM_SMD_XO_CLK_SRC 0 ---- a/drivers/clk/qcom/clk-rpm.c -+++ b/drivers/clk/qcom/clk-rpm.c -@@ -520,6 +520,16 @@ DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_ - DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, xo_a1_a_clk, 24); - DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, xo_a2_a_clk, 28); - -+/* ipq806x */ -+DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); -+DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); -+DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); -+DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); -+DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); -+DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); -+DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK); -+DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK); -+ - static struct clk_rpm *apq8064_clks[] = { - [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk, - [RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk, -@@ -546,15 +556,40 @@ static struct clk_rpm *apq8064_clks[] = - [RPM_XO_A2] = &apq8064_xo_a2_clk, - }; - -+static struct clk_rpm *ipq806x_clks[] = { -+ [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk, -+ [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk, -+ [RPM_CFPB_CLK] = &ipq806x_cfpb_clk, -+ [RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk, -+ [RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk, -+ [RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk, -+ [RPM_EBI1_CLK] = &ipq806x_ebi1_clk, -+ [RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk, -+ [RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk, -+ [RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk, -+ [RPM_SFPB_CLK] = &ipq806x_sfpb_clk, -+ [RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk, -+ [RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk, -+ [RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk, -+ [RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk, -+ [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk, -+}; -+ - static const struct rpm_clk_desc rpm_clk_apq8064 = { - .clks = apq8064_clks, - .num_clks = ARRAY_SIZE(apq8064_clks), - }; - -+static const struct rpm_clk_desc rpm_clk_ipq806x = { -+ .clks = ipq806x_clks, -+ .num_clks = ARRAY_SIZE(ipq806x_clks), -+}; -+ - static const struct of_device_id rpm_clk_match_table[] = { - { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 }, - { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 }, - { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 }, -+ { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x }, - { } - }; - MODULE_DEVICE_TABLE(of, rpm_clk_match_table); diff --git a/target/linux/ipq806x/patches-4.19/0065-arm-override-compiler-flags.patch b/target/linux/ipq806x/patches-4.19/0065-arm-override-compiler-flags.patch deleted file mode 100644 index 6f1cdcf4d6..0000000000 --- a/target/linux/ipq806x/patches-4.19/0065-arm-override-compiler-flags.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 4d8e29642661397a339ac3485f212c6360445421 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 09:33:32 +0100 -Subject: [PATCH 65/69] arm: override compiler flags - -Signed-off-by: John Crispin ---- - arch/arm/Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -64,7 +64,7 @@ KBUILD_CFLAGS += $(call cc-option,-fno-i - # macro, but instead defines a whole series of macros which makes - # testing for a specific architecture or later rather impossible. - arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m --arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a) -+arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -mcpu=cortex-a15 - arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6) - # Only override the compiler option if ARMv6. The ARMv6K extensions are - # always available in ARMv7 diff --git a/target/linux/ipq806x/patches-4.19/0067-generic-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/ipq806x/patches-4.19/0067-generic-Mangle-bootloader-s-kernel-arguments.patch deleted file mode 100644 index b7b9c991e0..0000000000 --- a/target/linux/ipq806x/patches-4.19/0067-generic-Mangle-bootloader-s-kernel-arguments.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001 -From: Adrian Panella -Date: Thu, 9 Mar 2017 09:37:17 +0100 -Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments - -The command-line arguments provided by the boot loader will be -appended to a new device tree property: bootloader-args. -If there is a property "append-rootblock" in DT under /chosen -and a root= option in bootloaders command line it will be parsed -and added to DT bootargs with the form: XX. -Only command line ATAG will be processed, the rest of the ATAGs -sent by bootloader will be ignored. -This is usefull in dual boot systems, to get the current root partition -without afecting the rest of the system. - -Signed-off-by: Adrian Panella ---- - arch/arm/Kconfig | 11 +++++ - arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++- - init/main.c | 16 ++++++++ - 3 files changed, 98 insertions(+), 1 deletion(-) - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1926,6 +1926,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - The command-line arguments provided by the boot loader will be - appended to the the device tree bootargs property. - -+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ bool "Append rootblock parsing bootloader's kernel arguments" -+ help -+ The command-line arguments provided by the boot loader will be -+ appended to a new device tree property: bootloader-args. -+ If there is a property "append-rootblock" in DT under /chosen -+ and a root= option in bootloaders command line it will be parsed -+ and added to DT bootargs with the form: XX. -+ Only command line ATAG will be processed, the rest of the ATAGs -+ sent by bootloader will be ignored. -+ - endchoice - - config CMDLINE ---- a/arch/arm/boot/compressed/atags_to_fdt.c -+++ b/arch/arm/boot/compressed/atags_to_fdt.c -@@ -4,6 +4,8 @@ - - #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) - #define do_extend_cmdline 1 -+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#define do_extend_cmdline 1 - #else - #define do_extend_cmdline 0 - #endif -@@ -67,6 +69,59 @@ static uint32_t get_cell_size(const void - return cell_size; - } - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ -+static char *append_rootblock(char *dest, const char *str, int len, void *fdt) -+{ -+ char *ptr, *end; -+ char *root="root="; -+ int i, l; -+ const char *rootblock; -+ -+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually -+ ptr = str - 1; -+ -+ do { -+ //first find an 'r' at the begining or after a space -+ do { -+ ptr++; -+ ptr = strchr(ptr, 'r'); -+ if(!ptr) return dest; -+ -+ } while (ptr != str && *(ptr-1) != ' '); -+ -+ //then check for the rest -+ for(i = 1; i <= 4; i++) -+ if(*(ptr+i) != *(root+i)) break; -+ -+ } while (i != 5); -+ -+ end = strchr(ptr, ' '); -+ end = end ? (end - 1) : (strchr(ptr, 0) - 1); -+ -+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX ) -+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++); -+ ptr = end + 1; -+ -+ /* if append-rootblock property is set use it to append to command line */ -+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l); -+ if(rootblock != NULL) { -+ if(*dest != ' ') { -+ *dest = ' '; -+ dest++; -+ len++; -+ } -+ if (len + l + i <= COMMAND_LINE_SIZE) { -+ memcpy(dest, rootblock, l); -+ dest += l - 1; -+ memcpy(dest, ptr, i); -+ dest += i; -+ } -+ } -+ return dest; -+} -+#endif -+ - static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) - { - char cmdline[COMMAND_LINE_SIZE]; -@@ -86,12 +141,21 @@ static void merge_fdt_bootargs(void *fdt - - /* and append the ATAG_CMDLINE */ - if (fdt_cmdline) { -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //save original bootloader args -+ //and append ubi.mtd with root partition number to current cmdline -+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline); -+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt); -+ -+#else - len = strlen(fdt_cmdline); - if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { - *ptr++ = ' '; - memcpy(ptr, fdt_cmdline, len); - ptr += len; - } -+#endif - } - *ptr = '\0'; - -@@ -148,7 +212,9 @@ int atags_to_fdt(void *atag_list, void * - else - setprop_string(fdt, "/chosen", "bootargs", - atag->u.cmdline.cmdline); -- } else if (atag->hdr.tag == ATAG_MEM) { -+ } -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ else if (atag->hdr.tag == ATAG_MEM) { - if (memcount >= sizeof(mem_reg_property)/4) - continue; - if (!atag->u.mem.size) -@@ -187,6 +253,10 @@ int atags_to_fdt(void *atag_list, void * - setprop(fdt, "/memory", "reg", mem_reg_property, - 4 * memcount * memsize); - } -+#else -+ -+ } -+#endif - - return fdt_pack(fdt); - } ---- a/init/main.c -+++ b/init/main.c -@@ -102,6 +102,10 @@ - #define CREATE_TRACE_POINTS - #include - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#include -+#endif -+ - static int kernel_init(void *); - - extern void init_IRQ(void); -@@ -593,6 +597,18 @@ asmlinkage __visible void __init start_k - pr_notice("Kernel command line: %s\n", boot_command_line); - /* parameters may set static keys */ - jump_label_init(); -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //Show bootloader's original command line for reference -+ if(of_chosen) { -+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL); -+ if(prop) -+ pr_notice("Bootloader command line (ignored): %s\n", prop); -+ else -+ pr_notice("Bootloader command line not present\n"); -+ } -+#endif -+ - parse_early_param(); - after_dashes = parse_args("Booting kernel", - static_command_line, __start___param, diff --git a/target/linux/ipq806x/patches-4.19/0069-arm-boot-add-dts-files.patch b/target/linux/ipq806x/patches-4.19/0069-arm-boot-add-dts-files.patch deleted file mode 100644 index 77ce4c4245..0000000000 --- a/target/linux/ipq806x/patches-4.19/0069-arm-boot-add-dts-files.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 8f68331e14dff9a101f2d0e1d6bec84a031f27ee Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 11:03:18 +0100 -Subject: [PATCH 69/69] arm: boot: add dts files - -Signed-off-by: John Crispin ---- - arch/arm/boot/dts/Makefile | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -791,6 +791,18 @@ dtb-$(CONFIG_ARCH_QCOM) += \ - qcom-ipq4019-ap.dk07.1-c1.dtb \ - qcom-ipq4019-ap.dk07.1-c2.dtb \ - qcom-ipq8064-ap148.dtb \ -+ qcom-ipq8064-c2600.dtb \ -+ qcom-ipq8064-d7800.dtb \ -+ qcom-ipq8064-db149.dtb \ -+ qcom-ipq8064-ap161.dtb \ -+ qcom-ipq8064-ea8500.dtb \ -+ qcom-ipq8064-r7500.dtb \ -+ qcom-ipq8064-r7500v2.dtb \ -+ qcom-ipq8064-wg2600hp.dtb \ -+ qcom-ipq8064-wpq864.dtb \ -+ qcom-ipq8064-wxr-2533dhp.dtb \ -+ qcom-ipq8065-nbg6817.dtb \ -+ qcom-ipq8065-r7800.dtb \ - qcom-msm8660-surf.dtb \ - qcom-msm8960-cdp.dtb \ - qcom-msm8974-fairphone-fp2.dtb \ diff --git a/target/linux/ipq806x/patches-4.19/0070-qcom-spm-fix-probe-order.patch b/target/linux/ipq806x/patches-4.19/0070-qcom-spm-fix-probe-order.patch deleted file mode 100644 index b7e375dfb2..0000000000 --- a/target/linux/ipq806x/patches-4.19/0070-qcom-spm-fix-probe-order.patch +++ /dev/null @@ -1,16 +0,0 @@ -Check for SCM availability before attempting to use SPM - -Signed-off-by: Felix Fietkau - ---- a/drivers/soc/qcom/spm.c -+++ b/drivers/soc/qcom/spm.c -@@ -219,6 +219,9 @@ static int __init qcom_cpuidle_init(stru - cpumask_t mask; - bool use_scm_power_down = false; - -+ if (!qcom_scm_is_available()) -+ return -EPROBE_DEFER; -+ - for (i = 0; ; i++) { - state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i); - if (!state_node) diff --git a/target/linux/ipq806x/patches-4.19/0071-1-PCI-qcom-Fixed-IPQ806x-specific-clocks.patch b/target/linux/ipq806x/patches-4.19/0071-1-PCI-qcom-Fixed-IPQ806x-specific-clocks.patch deleted file mode 100644 index 3a3e0a0000..0000000000 --- a/target/linux/ipq806x/patches-4.19/0071-1-PCI-qcom-Fixed-IPQ806x-specific-clocks.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 86655aa14304ca88a8ce8847276147dbc1a83238 Mon Sep 17 00:00:00 2001 -From: Sham Muthayyan -Date: Tue, 19 Jul 2016 18:44:49 +0530 -Subject: PCI: qcom: Fixed IPQ806x specific clocks - -Change-Id: I488e1bc707d6a22b37a338f41935e3922009ba5e -Signed-off-by: Sham Muthayyan ---- - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -85,6 +85,8 @@ struct qcom_pcie_resources_2_1_0 { - struct clk *iface_clk; - struct clk *core_clk; - struct clk *phy_clk; -+ struct clk *aux_clk; -+ struct clk *ref_clk; - struct reset_control *pci_reset; - struct reset_control *axi_reset; - struct reset_control *ahb_reset; -@@ -235,6 +237,14 @@ static int qcom_pcie_get_resources_2_1_0 - if (IS_ERR(res->phy_clk)) - return PTR_ERR(res->phy_clk); - -+ res->aux_clk = devm_clk_get(dev, "aux"); -+ if (IS_ERR(res->aux_clk)) -+ return PTR_ERR(res->aux_clk); -+ -+ res->ref_clk = devm_clk_get(dev, "ref"); -+ if (IS_ERR(res->ref_clk)) -+ return PTR_ERR(res->ref_clk); -+ - res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); - if (IS_ERR(res->pci_reset)) - return PTR_ERR(res->pci_reset); -@@ -267,6 +277,8 @@ static void qcom_pcie_deinit_2_1_0(struc - clk_disable_unprepare(res->iface_clk); - clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->phy_clk); -+ clk_disable_unprepare(res->aux_clk); -+ clk_disable_unprepare(res->ref_clk); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - } - -@@ -296,16 +308,28 @@ static int qcom_pcie_init_2_1_0(struct q - goto err_assert_ahb; - } - -+ ret = clk_prepare_enable(res->core_clk); -+ if (ret) { -+ dev_err(dev, "cannot prepare/enable core clock\n"); -+ goto err_clk_core; -+ } -+ - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_clk_phy; - } - -- ret = clk_prepare_enable(res->core_clk); -+ ret = clk_prepare_enable(res->aux_clk); - if (ret) { -- dev_err(dev, "cannot prepare/enable core clock\n"); -- goto err_clk_core; -+ dev_err(dev, "cannot prepare/enable aux clock\n"); -+ goto err_clk_aux; -+ } -+ -+ ret = clk_prepare_enable(res->ref_clk); -+ if (ret) { -+ dev_err(dev, "cannot prepare/enable ref clock\n"); -+ goto err_clk_ref; - } - - ret = reset_control_deassert(res->ahb_reset); -@@ -361,10 +385,14 @@ static int qcom_pcie_init_2_1_0(struct q - return 0; - - err_deassert_ahb: -- clk_disable_unprepare(res->core_clk); --err_clk_core: -+ clk_disable_unprepare(res->ref_clk); -+err_clk_ref: -+ clk_disable_unprepare(res->aux_clk); -+err_clk_aux: - clk_disable_unprepare(res->phy_clk); - err_clk_phy: -+ clk_disable_unprepare(res->core_clk); -+err_clk_core: - clk_disable_unprepare(res->iface_clk); - err_assert_ahb: - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); diff --git a/target/linux/ipq806x/patches-4.19/0071-2-PCI-qcom-Fixed-IPQ806x-PCIE-reset-changes.patch b/target/linux/ipq806x/patches-4.19/0071-2-PCI-qcom-Fixed-IPQ806x-PCIE-reset-changes.patch deleted file mode 100644 index 5bd865a42e..0000000000 --- a/target/linux/ipq806x/patches-4.19/0071-2-PCI-qcom-Fixed-IPQ806x-PCIE-reset-changes.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 490d103232287eb51c92c49a4ef8865fd0a9d59e Mon Sep 17 00:00:00 2001 -From: Sham Muthayyan -Date: Tue, 19 Jul 2016 18:58:18 +0530 -Subject: PCI: qcom: Fixed IPQ806x PCIE reset changes - -Change-Id: Ia6590e960b9754b1e8b7a51f318788cd63e9e321 -Signed-off-by: Sham Muthayyan ---- - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -92,6 +92,7 @@ struct qcom_pcie_resources_2_1_0 { - struct reset_control *ahb_reset; - struct reset_control *por_reset; - struct reset_control *phy_reset; -+ struct reset_control *ext_reset; - struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; - }; - -@@ -261,6 +262,10 @@ static int qcom_pcie_get_resources_2_1_0 - if (IS_ERR(res->por_reset)) - return PTR_ERR(res->por_reset); - -+ res->ext_reset = devm_reset_control_get(dev, "ext"); -+ if (IS_ERR(res->ext_reset)) -+ return PTR_ERR(res->ext_reset); -+ - res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); - return PTR_ERR_OR_ZERO(res->phy_reset); - } -@@ -274,6 +279,7 @@ static void qcom_pcie_deinit_2_1_0(struc - reset_control_assert(res->ahb_reset); - reset_control_assert(res->por_reset); - reset_control_assert(res->pci_reset); -+ reset_control_assert(res->ext_reset); - clk_disable_unprepare(res->iface_clk); - clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->phy_clk); -@@ -290,15 +296,21 @@ static int qcom_pcie_init_2_1_0(struct q - u32 val; - int ret; - -+ ret = reset_control_assert(res->ahb_reset); -+ if (ret) { -+ dev_err(dev, "cannot assert ahb reset\n"); -+ return ret; -+ } -+ - ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); - if (ret < 0) { - dev_err(dev, "cannot enable regulators\n"); - return ret; - } - -- ret = reset_control_assert(res->ahb_reset); -+ ret = reset_control_deassert(res->ext_reset); - if (ret) { -- dev_err(dev, "cannot assert ahb reset\n"); -+ dev_err(dev, "cannot assert ext reset\n"); - goto err_assert_ahb; - } - diff --git a/target/linux/ipq806x/patches-4.19/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch b/target/linux/ipq806x/patches-4.19/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch deleted file mode 100644 index dde8fbaa7b..0000000000 --- a/target/linux/ipq806x/patches-4.19/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch +++ /dev/null @@ -1,124 +0,0 @@ -From eddd13215d0f2b549ebc5f0e8796d5b1231f90a0 Mon Sep 17 00:00:00 2001 -From: Sham Muthayyan -Date: Tue, 19 Jul 2016 19:58:22 +0530 -Subject: PCI: qcom: Fixed IPQ806x PCIE init changes - -Change-Id: Ic319b1aec27a47809284759f8fcb6a8815b7cf7e -Signed-off-by: Sham Muthayyan ---- - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -45,7 +45,13 @@ - #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 - - #define PCIE20_PARF_PHY_CTRL 0x40 -+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16) -+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16) -+ - #define PCIE20_PARF_PHY_REFCLK 0x4C -+#define REF_SSP_EN BIT(16) -+#define REF_USE_PAD BIT(12) -+ - #define PCIE20_PARF_DBI_BASE_ADDR 0x168 - #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C - #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 -@@ -76,6 +82,18 @@ - #define DBI_RO_WR_EN 1 - - #define PERST_DELAY_US 1000 -+/* PARF registers */ -+#define PCIE20_PARF_PCS_DEEMPH 0x34 -+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16) -+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8) -+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0) -+ -+#define PCIE20_PARF_PCS_SWING 0x38 -+#define PCS_SWING_TX_SWING_FULL(x) (x << 8) -+#define PCS_SWING_TX_SWING_LOW(x) (x << 0) -+ -+#define PCIE20_PARF_CONFIG_BITS 0x50 -+#define PHY_RX0_EQ(x) (x << 24) - - #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 - #define SLV_ADDR_SPACE_SZ 0x10000000 -@@ -94,6 +112,7 @@ struct qcom_pcie_resources_2_1_0 { - struct reset_control *phy_reset; - struct reset_control *ext_reset; - struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; -+ uint8_t phy_tx0_term_offset; - }; - - struct qcom_pcie_resources_1_0_0 { -@@ -173,6 +192,16 @@ struct qcom_pcie { - - #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) - -+static inline void -+writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask) -+{ -+ u32 val = readl(addr); -+ -+ val &= ~clear_mask; -+ val |= set_mask; -+ writel(val, addr); -+} -+ - static void qcom_ep_reset_assert(struct qcom_pcie *pcie) - { - gpiod_set_value_cansleep(pcie->reset, 1); -@@ -266,6 +295,10 @@ static int qcom_pcie_get_resources_2_1_0 - if (IS_ERR(res->ext_reset)) - return PTR_ERR(res->ext_reset); - -+ if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset", -+ &res->phy_tx0_term_offset)) -+ res->phy_tx0_term_offset = 0; -+ - res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); - return PTR_ERR_OR_ZERO(res->phy_reset); - } -@@ -293,7 +326,6 @@ static int qcom_pcie_init_2_1_0(struct q - struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; - struct dw_pcie *pci = pcie->pci; - struct device *dev = pci->dev; -- u32 val; - int ret; - - ret = reset_control_assert(res->ahb_reset); -@@ -350,15 +382,26 @@ static int qcom_pcie_init_2_1_0(struct q - goto err_deassert_ahb; - } - -- /* enable PCIe clocks and resets */ -- val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); -- val &= ~BIT(0); -- writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); -- -- /* enable external reference clock */ -- val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); -- val |= BIT(16); -- writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); -+ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0); -+ -+ /* Set Tx termination offset */ -+ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, -+ PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, -+ PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset)); -+ -+ /* PARF programming */ -+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) | -+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) | -+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22), -+ pcie->parf + PCIE20_PARF_PCS_DEEMPH); -+ writel(PCS_SWING_TX_SWING_FULL(0x78) | -+ PCS_SWING_TX_SWING_LOW(0x78), -+ pcie->parf + PCIE20_PARF_PCS_SWING); -+ writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS); -+ -+ /* Enable reference clock */ -+ writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, -+ REF_USE_PAD, REF_SSP_EN); - - ret = reset_control_deassert(res->phy_reset); - if (ret) { diff --git a/target/linux/ipq806x/patches-4.19/0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x.patch b/target/linux/ipq806x/patches-4.19/0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x.patch deleted file mode 100644 index f6ebe0c0af..0000000000 --- a/target/linux/ipq806x/patches-4.19/0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x.patch +++ /dev/null @@ -1,112 +0,0 @@ -From d27c303e828d7e42f339a459d2abfe30c51698e9 Mon Sep 17 00:00:00 2001 -From: Sham Muthayyan -Date: Tue, 26 Jul 2016 12:28:31 +0530 -Subject: PCI: qcom: Programming the PCIE iATU for IPQ806x - -Resolved PCIE EP detection errors caused due to missing iATU programming. - -Change-Id: Ie95c0f8cb940abc0192a8a3c4e825ddba54b72fe -Signed-off-by: Sham Muthayyan ---- - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -76,6 +76,30 @@ - #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14) - #define PCIE_CAP_LINK1_VAL 0x2FD7F - -+#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10) -+ -+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818 -+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c -+ -+#define PCIE20_PLR_IATU_VIEWPORT 0x900 -+#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31) -+#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0) -+ -+#define PCIE20_PLR_IATU_CTRL1 0x904 -+#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0) -+#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0) -+ -+#define PCIE20_PLR_IATU_CTRL2 0x908 -+#define PCIE20_PLR_IATU_ENABLE BIT(31) -+ -+#define PCIE20_PLR_IATU_LBAR 0x90C -+#define PCIE20_PLR_IATU_UBAR 0x910 -+#define PCIE20_PLR_IATU_LAR 0x914 -+#define PCIE20_PLR_IATU_LTAR 0x918 -+#define PCIE20_PLR_IATU_UTAR 0x91c -+ -+#define MSM_PCIE_DEV_CFG_ADDR 0x01000000 -+ - #define PCIE20_PARF_Q2A_FLUSH 0x1AC - - #define PCIE20_MISC_CONTROL_1_REG 0x8BC -@@ -240,6 +264,57 @@ static void qcom_pcie_2_1_0_ltssm_enable - writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL); - } - -+static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev) -+{ -+ struct pcie_port *pp = &pcie->pci->pp; -+ -+ /* -+ * program and enable address translation region 0 (device config -+ * address space); region type config; -+ * axi config address range to device config address range -+ */ -+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND | -+ PCIE20_PLR_IATU_REGION_INDEX(0), -+ pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT); -+ -+ writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1); -+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2); -+ writel(pp->cfg0_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR); -+ writel((pp->cfg0_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR); -+ writel((pp->cfg0_base + pp->cfg0_size - 1), -+ pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR); -+ writel(busdev, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR); -+ writel(0, pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR); -+} -+ -+static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie) -+{ -+ struct pcie_port *pp = &pcie->pci->pp; -+ -+ /* -+ * program and enable address translation region 2 (device resource -+ * address space); region type memory; -+ * axi device bar address range to device bar address range -+ */ -+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND | -+ PCIE20_PLR_IATU_REGION_INDEX(2), -+ pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT); -+ -+ writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1); -+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2); -+ writel(pp->mem_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR); -+ writel((pp->mem_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR); -+ writel(pp->mem_base + pp->mem_size - 1, -+ pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR); -+ writel(pp->mem_bus_addr, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR); -+ writel(upper_32_bits(pp->mem_bus_addr), -+ pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR); -+ -+ /* 256B PCIE buffer setting */ -+ writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); -+ writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); -+} -+ - static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) - { - struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; -@@ -437,6 +512,9 @@ static int qcom_pcie_init_2_1_0(struct q - writel(CFG_BRIDGE_SB_INIT, - pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); - -+ qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR); -+ qcom_pcie_prog_viewport_mem2_outbound(pcie); -+ - return 0; - - err_deassert_ahb: diff --git a/target/linux/ipq806x/patches-4.19/0071-6-PCI-qcom-Force-GEN1-support.patch b/target/linux/ipq806x/patches-4.19/0071-6-PCI-qcom-Force-GEN1-support.patch deleted file mode 100644 index c1461e68c2..0000000000 --- a/target/linux/ipq806x/patches-4.19/0071-6-PCI-qcom-Force-GEN1-support.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 4910cfd150342ec7b038892262923c725a9c4001 Mon Sep 17 00:00:00 2001 -From: Sham Muthayyan -Date: Wed, 7 Sep 2016 16:44:28 +0530 -Subject: PCI: qcom: Force GEN1 support - -Change-Id: Ica54ddb737d7b851469deab1745f54bf431bd3f0 -Signed-off-by: Sham Muthayyan ---- - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -122,6 +122,8 @@ - #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 - #define SLV_ADDR_SPACE_SZ 0x10000000 - -+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0 -+ - #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 - struct qcom_pcie_resources_2_1_0 { - struct clk *iface_clk; -@@ -212,6 +214,7 @@ struct qcom_pcie { - struct phy *phy; - struct gpio_desc *reset; - const struct qcom_pcie_ops *ops; -+ uint32_t force_gen1; - }; - - #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) -@@ -504,6 +507,11 @@ static int qcom_pcie_init_2_1_0(struct q - - /* wait for clock acquisition */ - usleep_range(1000, 1500); -+ if (pcie->force_gen1) { -+ writel_relaxed((readl_relaxed( -+ pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1), -+ pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); -+ } - - - /* Set the Max TLP size to 2K, instead of using default of 4K */ -@@ -1367,6 +1375,8 @@ static int qcom_pcie_probe(struct platfo - struct dw_pcie *pci; - struct qcom_pcie *pcie; - int ret; -+ uint32_t force_gen1 = 0; -+ struct device_node *np = pdev->dev.of_node; - - pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); - if (!pcie) -@@ -1397,6 +1407,9 @@ static int qcom_pcie_probe(struct platfo - goto err_pm_runtime_put; - } - -+ of_property_read_u32(np, "force_gen1", &force_gen1); -+ pcie->force_gen1 = force_gen1; -+ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); - pcie->parf = devm_ioremap_resource(dev, res); - if (IS_ERR(pcie->parf)) { diff --git a/target/linux/ipq806x/patches-4.19/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch b/target/linux/ipq806x/patches-4.19/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch deleted file mode 100644 index e7b5b6f9af..0000000000 --- a/target/linux/ipq806x/patches-4.19/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch +++ /dev/null @@ -1,69 +0,0 @@ -From edff8f777c6321ca89bb950a382f409c4a126e28 Mon Sep 17 00:00:00 2001 -From: Gokul Sriram Palanisamy -Date: Thu, 15 Dec 2016 17:38:18 +0530 -Subject: pcie: Set PCIE MRRS and MPS to 256B - -Set Max Read Request Size and Max Payload Size to 256 bytes, -per chip team recommendation. - -Change-Id: I097004be2ced1b3096ffc10c318aae0b2bb155e8 -Signed-off-by: Gokul Sriram Palanisamy ---- - drivers/pci/host/pcie-qcom.c | 37 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 37 insertions(+) - -(limited to 'drivers/pci/host/pcie-qcom.c') - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -124,6 +124,14 @@ - - #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0 - -+#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b)) -+#define __mask(a, b) (((1 << ((a) + 1)) - 1) & ~((1 << (b)) - 1)) -+#define PCIE20_DEV_CAS 0x78 -+#define PCIE20_MRRS_MASK __mask(14, 12) -+#define PCIE20_MRRS(x) __set(x, 14, 12) -+#define PCIE20_MPS_MASK __mask(7, 5) -+#define PCIE20_MPS(x) __set(x, 7, 5) -+ - #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 - struct qcom_pcie_resources_2_1_0 { - struct clk *iface_clk; -@@ -1475,6 +1483,35 @@ err_pm_runtime_put: - return ret; - } - -+static void qcom_pcie_fixup_final(struct pci_dev *dev) -+{ -+ int cap, err; -+ u16 ctl, reg_val; -+ -+ cap = pci_pcie_cap(dev); -+ if (!cap) -+ return; -+ -+ err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); -+ -+ if (err) -+ return; -+ -+ reg_val = ctl; -+ -+ if (((reg_val & PCIE20_MRRS_MASK) >> 12) > 1) -+ reg_val = (reg_val & ~(PCIE20_MRRS_MASK)) | PCIE20_MRRS(0x1); -+ -+ if (((ctl & PCIE20_MPS_MASK) >> 5) > 1) -+ reg_val = (reg_val & ~(PCIE20_MPS_MASK)) | PCIE20_MPS(0x1); -+ -+ err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, reg_val); -+ -+ if (err) -+ pr_err("pcie config write failed %d\n", err); -+} -+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, qcom_pcie_fixup_final); -+ - static const struct of_device_id qcom_pcie_match[] = { - { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 }, - { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 }, diff --git a/target/linux/ipq806x/patches-4.19/0071-8-pcie-qcom-Fixed-pcie_phy_clk-branch-issue.patch b/target/linux/ipq806x/patches-4.19/0071-8-pcie-qcom-Fixed-pcie_phy_clk-branch-issue.patch deleted file mode 100644 index 7cbeb3bed7..0000000000 --- a/target/linux/ipq806x/patches-4.19/0071-8-pcie-qcom-Fixed-pcie_phy_clk-branch-issue.patch +++ /dev/null @@ -1,91 +0,0 @@ -From b74bab6186131eea09459eedf5d737645a3559c9 Mon Sep 17 00:00:00 2001 -From: Abhishek Sahu -Date: Thu, 22 Dec 2016 11:18:45 +0530 -Subject: pcie: qcom: Fixed pcie_phy_clk branch issue - -Following backtraces are observed in PCIe deinit operation. - - Hardware name: Qualcomm (Flattened Device Tree) - (unwind_backtrace) from [] (show_stack+0x10/0x14) - (show_stack) from [] (dump_stack+0x84/0x98) - (dump_stack) from [] (warn_slowpath_common+0x9c/0xb8) - (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40) - (warn_slowpath_fmt) from [] (clk_branch_wait+0x114/0x120) - (clk_branch_wait) from [] (clk_core_disable+0xd0/0x1f4) - (clk_core_disable) from [] (clk_disable+0x24/0x30) - (clk_disable) from [] (qcom_pcie_deinit_v0+0x6c/0xb8) - (qcom_pcie_deinit_v0) from [] (qcom_pcie_host_init+0xe0/0xe8) - (qcom_pcie_host_init) from [] (dw_pcie_host_init+0x3b0/0x538) - (dw_pcie_host_init) from [] (qcom_pcie_probe+0x20c/0x2e4) - -pcie_phy_clk is generated for PCIe controller itself and the -GCC controls its branch operation. This error is coming since -the assert operations turn off the parent clock before branch -clock. Now this patch moves clk_disable_unprepare before assert -operations. - -Similarly, during probe function, the clock branch operation -should be done after dessert operation. Currently, it does not -generate any error since bootloader enables the pcie_phy_clk -but the same error is coming during probe, if bootloader -disables pcie_phy_clk. - -Change-Id: Ib29c154d10eb64363d9cc982ce5fd8107af5627d -Signed-off-by: Abhishek Sahu ---- - drivers/pci/host/pcie-qcom.c | 16 +++++++--------- - 1 file changed, 7 insertions(+), 9 deletions(-) - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -393,6 +393,7 @@ static void qcom_pcie_deinit_2_1_0(struc - { - struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; - -+ clk_disable_unprepare(res->phy_clk); - reset_control_assert(res->pci_reset); - reset_control_assert(res->axi_reset); - reset_control_assert(res->ahb_reset); -@@ -401,7 +402,6 @@ static void qcom_pcie_deinit_2_1_0(struc - reset_control_assert(res->ext_reset); - clk_disable_unprepare(res->iface_clk); - clk_disable_unprepare(res->core_clk); -- clk_disable_unprepare(res->phy_clk); - clk_disable_unprepare(res->aux_clk); - clk_disable_unprepare(res->ref_clk); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); -@@ -444,12 +444,6 @@ static int qcom_pcie_init_2_1_0(struct q - goto err_clk_core; - } - -- ret = clk_prepare_enable(res->phy_clk); -- if (ret) { -- dev_err(dev, "cannot prepare/enable phy clock\n"); -- goto err_clk_phy; -- } -- - ret = clk_prepare_enable(res->aux_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); -@@ -513,6 +507,12 @@ static int qcom_pcie_init_2_1_0(struct q - return ret; - } - -+ ret = clk_prepare_enable(res->phy_clk); -+ if (ret) { -+ dev_err(dev, "cannot prepare/enable phy clock\n"); -+ goto err_deassert_ahb; -+ } -+ - /* wait for clock acquisition */ - usleep_range(1000, 1500); - if (pcie->force_gen1) { -@@ -538,8 +538,6 @@ err_deassert_ahb: - err_clk_ref: - clk_disable_unprepare(res->aux_clk); - err_clk_aux: -- clk_disable_unprepare(res->phy_clk); --err_clk_phy: - clk_disable_unprepare(res->core_clk); - err_clk_core: - clk_disable_unprepare(res->iface_clk); diff --git a/target/linux/ipq806x/patches-4.19/0071-9-pcie-qcom-change-duplicate-pci-reset-to-phy-reset.patch b/target/linux/ipq806x/patches-4.19/0071-9-pcie-qcom-change-duplicate-pci-reset-to-phy-reset.patch deleted file mode 100644 index 3fff78bfd4..0000000000 --- a/target/linux/ipq806x/patches-4.19/0071-9-pcie-qcom-change-duplicate-pci-reset-to-phy-reset.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 1a9c48123bd09f75562b6a2ee0f0a7b2d533cd45 Mon Sep 17 00:00:00 2001 -From: Abhishek Sahu -Date: Thu, 22 Dec 2016 11:50:49 +0530 -Subject: pcie: qcom: change duplicate pci reset to phy reset - -The deinit issues reset_control_assert for pci twice and -does not contain phy reset. - -Change-Id: Iba849963c7e5f9a2a1063f0e2e89635df70b8a99 -Signed-off-by: Abhishek Sahu ---- - drivers/pci/host/pcie-qcom.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -394,7 +394,7 @@ static void qcom_pcie_deinit_2_1_0(struc - struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; - - clk_disable_unprepare(res->phy_clk); -- reset_control_assert(res->pci_reset); -+ reset_control_assert(res->phy_reset); - reset_control_assert(res->axi_reset); - reset_control_assert(res->ahb_reset); - reset_control_assert(res->por_reset); diff --git a/target/linux/ipq806x/patches-4.19/0072-add-ipq806x-with-no-clocks.patch b/target/linux/ipq806x/patches-4.19/0072-add-ipq806x-with-no-clocks.patch deleted file mode 100644 index ecd9672d1b..0000000000 --- a/target/linux/ipq806x/patches-4.19/0072-add-ipq806x-with-no-clocks.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- a/drivers/firmware/qcom_scm.c -+++ b/drivers/firmware/qcom_scm.c -@@ -606,6 +606,9 @@ static const struct of_device_id qcom_sc - { .compatible = "qcom,scm-ipq4019", - .data = NULL, /* no clocks */ - }, -+ { .compatible = "qcom,scm-ipq806x", -+ .data = NULL, /* no clocks */ -+ }, - { .compatible = "qcom,scm", - .data = (void *)(SCM_HAS_CORE_CLK - | SCM_HAS_IFACE_CLK diff --git a/target/linux/ipq806x/patches-4.19/0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch b/target/linux/ipq806x/patches-4.19/0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch deleted file mode 100644 index 78a5bb4173..0000000000 --- a/target/linux/ipq806x/patches-4.19/0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 2034addc7e193dc81d7ca60d8884832751b76758 Mon Sep 17 00:00:00 2001 -From: Ajay Kishore -Date: Tue, 24 Jan 2017 14:14:16 +0530 -Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps - -For IPQ806x targets, TZ protects the registers that are used to -configure the routing of interrupts to a target processor. -To resolve this, this patch uses scm call to route GPIO interrupts -to application processor. Also the scm call interface is changed. - -Change-Id: Ib6c06829d04bc8c20483c36e63da92e26cdef9ce -Signed-off-by: Ajay Kishore ---- - ---- a/drivers/pinctrl/qcom/pinctrl-msm.c -+++ b/drivers/pinctrl/qcom/pinctrl-msm.c -@@ -30,7 +30,8 @@ - #include - #include - #include -- -+#include -+#include - #include "../core.h" - #include "../pinconf.h" - #include "pinctrl-msm.h" -@@ -628,6 +629,9 @@ static void msm_gpio_irq_mask(struct irq - const struct msm_pingroup *g; - unsigned long flags; - u32 val; -+ u32 addr; -+ int ret; -+ const __be32 *reg; - - g = &pctrl->soc->groups[d->hwirq]; - -@@ -732,11 +736,30 @@ static int msm_gpio_irq_set_type(struct - else - clear_bit(d->hwirq, pctrl->dual_edge_irqs); - -+ int ret = of_device_is_compatible(pctrl->dev->of_node, -+ "qcom,ipq8064-pinctrl"); - /* Route interrupts to application cpu */ -- val = readl(pctrl->regs + g->intr_target_reg); -- val &= ~(7 << g->intr_target_bit); -- val |= g->intr_target_kpss_val << g->intr_target_bit; -- writel(val, pctrl->regs + g->intr_target_reg); -+ if (!ret) { -+ val = readl(pctrl->regs + g->intr_target_reg); -+ val &= ~(7 << g->intr_target_bit); -+ val |= g->intr_target_kpss_val << g->intr_target_bit; -+ writel(val, pctrl->regs + g->intr_target_reg); -+ } else { -+ const __be32 *reg = of_get_property(pctrl->dev->of_node, "reg", NULL); -+ if (reg) { -+ u32 addr = be32_to_cpup(reg) + g->intr_target_reg; -+ qcom_scm_io_readl(addr, &val); -+ __iormb(); -+ -+ val &= ~(7 << g->intr_target_bit); -+ val |= g->intr_target_kpss_val << g->intr_target_bit; -+ -+ __iowmb(); -+ ret = qcom_scm_io_writel(addr, val); -+ if (ret) -+ pr_err("\n Routing interrupts to Apps proc failed"); -+ } -+ } - - /* Update configuration for gpio. - * RAW_STATUS_EN is left on for all gpio irqs. Due to the diff --git a/target/linux/ipq806x/patches-4.19/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch b/target/linux/ipq806x/patches-4.19/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch deleted file mode 100644 index 2867239d1c..0000000000 --- a/target/linux/ipq806x/patches-4.19/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch +++ /dev/null @@ -1,50 +0,0 @@ -From a3488aa9bed37c56e405967d44e821c484b5d6b9 Mon Sep 17 00:00:00 2001 -From: Ram Chandra Jangir -Date: Fri, 28 Sep 2018 15:19:50 +0530 -Subject: [PATCH] ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions - -Signed-off-by: Ram Chandra Jangir ---- - drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c -+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c -@@ -308,7 +308,7 @@ static const char * const gpio_groups[] - }; - - static const char * const mdio_groups[] = { -- "gpio0", "gpio1", "gpio10", "gpio11", -+ "gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66", - }; - - static const char * const mi2s_groups[] = { -@@ -412,8 +412,8 @@ static const char * const usb2_hsic_grou - }; - - static const char * const rgmii2_groups[] = { -- "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", -- "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", -+ "gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", -+ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66", - }; - - static const char * const sata_groups[] = { -@@ -548,7 +548,7 @@ static const struct msm_function ipq8064 - static const struct msm_pingroup ipq8064_groups[] = { - PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), -- PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA), -+ PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), -@@ -612,7 +612,7 @@ static const struct msm_pingroup ipq8064 - PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA), -- PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), -+ PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6), diff --git a/target/linux/ipq806x/patches-4.19/080-ARM-dts-qcom-add-gpio-ranges-property.patch b/target/linux/ipq806x/patches-4.19/080-ARM-dts-qcom-add-gpio-ranges-property.patch deleted file mode 100644 index 1ab070bdab..0000000000 --- a/target/linux/ipq806x/patches-4.19/080-ARM-dts-qcom-add-gpio-ranges-property.patch +++ /dev/null @@ -1,70 +0,0 @@ -From patchwork Mon May 21 20:57:38 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v5,3/4] ARM: dts: qcom: add gpio-ranges property -X-Patchwork-Submitter: Christian Lamparter -X-Patchwork-Id: 917856 -Message-Id: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com> -To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, - linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org -Cc: Bjorn Andersson , - Linus Walleij , - Stephen Boyd , David Brown , - Rob Herring , Mark Rutland , - Andy Gross , - Sven Eckelmann -Date: Mon, 21 May 2018 22:57:38 +0200 -From: Christian Lamparter -List-Id: - -This patch adds the gpio-ranges property to almost all of -the Qualcomm ARM platforms that utilize the pinctrl-msm -framework. - -The gpio-ranges property is part of the gpiolib subsystem. -As a result, the binding text is available in section -"2.1 gpio- and pin-controller interaction" of -Documentation/devicetree/bindings/gpio/gpio.txt - -For more information please see the patch titled: -"pinctrl: msm: fix gpio-hog related boot issues" from -this series. - -Reported-by: Sven Eckelmann -Tested-by: Sven Eckelmann [ipq4019] -Reviewed-by: Bjorn Andersson -Signed-off-by: Christian Lamparter -Reviewed-by: Linus Walleij ---- -To help with git bisect, the DT update patch has been intentionally -placed after the "pinctrl: msm: fix gpio-hog related boot issues". -Otherwise - if the order was reveresed - and bisect decides to split -between these two patches, the gpiochip_add_pin_ranges() function -will be executed twice with the same parameters for the same pinctrl. ---- - arch/arm/boot/dts/qcom-apq8064.dtsi | 1 + - arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + - arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + - arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 + - arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 + - arch/arm/boot/dts/qcom-msm8660.dtsi | 1 + - arch/arm/boot/dts/qcom-msm8960.dtsi | 1 + - arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++- - arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + - arch/arm64/boot/dts/qcom/msm8992.dtsi | 1 + - arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 + - arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 + - 13 files changed, 14 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -668,6 +668,7 @@ - reg = <0x800000 0x4000>; - - gpio-controller; -+ gpio-ranges = <&qcom_pinmux 0 0 69>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; diff --git a/target/linux/ipq806x/patches-4.19/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq806x/patches-4.19/850-soc-add-qualcomm-syscon.patch deleted file mode 100644 index 50414596d9..0000000000 --- a/target/linux/ipq806x/patches-4.19/850-soc-add-qualcomm-syscon.patch +++ /dev/null @@ -1,121 +0,0 @@ -From: Christian Lamparter -Subject: SoC: add qualcomm syscon ---- a/drivers/soc/qcom/Makefile -+++ b/drivers/soc/qcom/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_st - obj-$(CONFIG_QCOM_SMP2P) += smp2p.o - obj-$(CONFIG_QCOM_SMSM) += smsm.o - obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o -+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o - obj-$(CONFIG_QCOM_APR) += apr.o - obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o - obj-$(CONFIG_QCOM_SDM845_LLCC) += llcc-sdm845.o ---- a/drivers/soc/qcom/Kconfig -+++ b/drivers/soc/qcom/Kconfig -@@ -146,6 +146,13 @@ config QCOM_SMSM - Say yes here to support the Qualcomm Shared Memory State Machine. - The state machine is represented by bits in shared memory. - -+config QCOM_TCSR -+ tristate "QCOM Top Control and Status Registers" -+ depends on ARCH_QCOM -+ help -+ Say y here to enable TCSR support. The TCSR provides control -+ functions for various peripherals. -+ - config QCOM_WCNSS_CTRL - tristate "Qualcomm WCNSS control driver" - depends on ARCH_QCOM ---- /dev/null -+++ b/drivers/soc/qcom/qcom_tcsr.c -@@ -0,0 +1,64 @@ -+/* -+ * Copyright (c) 2014, The Linux foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License rev 2 and -+ * only rev 2 as published by the free Software foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define TCSR_USB_PORT_SEL 0xb0 -+ -+static int tcsr_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ const struct device_node *node = pdev->dev.of_node; -+ void __iomem *base; -+ u32 val; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) { -+ dev_err(&pdev->dev, "setting usb port select = %d\n", val); -+ writel(val, base + TCSR_USB_PORT_SEL); -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id tcsr_dt_match[] = { -+ { .compatible = "qcom,tcsr", }, -+ { }, -+}; -+ -+MODULE_DEVICE_TABLE(of, tcsr_dt_match); -+ -+static struct platform_driver tcsr_driver = { -+ .driver = { -+ .name = "tcsr", -+ .owner = THIS_MODULE, -+ .of_match_table = tcsr_dt_match, -+ }, -+ .probe = tcsr_probe, -+}; -+ -+module_platform_driver(tcsr_driver); -+ -+MODULE_AUTHOR("Andy Gross "); -+MODULE_DESCRIPTION("QCOM TCSR driver"); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/include/dt-bindings/soc/qcom,tcsr.h -@@ -0,0 +1,23 @@ -+/* Copyright (c) 2014, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+#ifndef __DT_BINDINGS_QCOM_TCSR_H -+#define __DT_BINDINGS_QCOM_TCSR_H -+ -+#define TCSR_USB_SELECT_USB3_P0 0x1 -+#define TCSR_USB_SELECT_USB3_P1 0x2 -+#define TCSR_USB_SELECT_USB3_DUAL 0x3 -+ -+/* TCSR A/B REG */ -+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0 -+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1 -+ -+#endif From f47cb405cafd57a25fceb7630af969e08b2f671c Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Tue, 1 Sep 2020 14:59:37 +0200 Subject: [PATCH 12/15] ipq806x: fix pci broken on bootm command Pci is broken when bootm is used instead of the custom bootipq. This is caused by the lack of reset by the bootloader. Make the driver do the reset to fix this specific problem. Signed-off-by: Ansuel Smith --- ...re-PCIe-is-reset-before-init-for-rev.patch | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 target/linux/ipq806x/patches-5.4/096-PCI-qcom-Make-sure-PCIe-is-reset-before-init-for-rev.patch diff --git a/target/linux/ipq806x/patches-5.4/096-PCI-qcom-Make-sure-PCIe-is-reset-before-init-for-rev.patch b/target/linux/ipq806x/patches-5.4/096-PCI-qcom-Make-sure-PCIe-is-reset-before-init-for-rev.patch new file mode 100644 index 0000000000..5c93d3199a --- /dev/null +++ b/target/linux/ipq806x/patches-5.4/096-PCI-qcom-Make-sure-PCIe-is-reset-before-init-for-rev.patch @@ -0,0 +1,51 @@ +From 1960d75e3251659be8276529e4d01cf6993d9f4a Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 1 Sep 2020 14:21:44 +0200 +Subject: [PATCH] PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0 + +Qsdk U-Boot can incorrectly leave the PCIe interface in an undefined +state if bootm command is used instead of bootipq. This is caused by the +not deinit of PCIe when bootm is called. Reset the PCIe before init +anyway to fix this U-Boot bug. + +Signed-off-by: Ansuel Smith +Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") +Cc: stable@vger.kernel.org # v4.19+ +--- + drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c +index 3aac77a295ba..82336bbaf8dc 100644 +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -302,6 +302,9 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) + reset_control_assert(res->por_reset); + reset_control_assert(res->ext_reset); + reset_control_assert(res->phy_reset); ++ ++ writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); ++ + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + } + +@@ -314,6 +317,16 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) + u32 val; + int ret; + ++ /* reset the PCIe interface as uboot can leave it undefined state */ ++ reset_control_assert(res->pci_reset); ++ reset_control_assert(res->axi_reset); ++ reset_control_assert(res->ahb_reset); ++ reset_control_assert(res->por_reset); ++ reset_control_assert(res->ext_reset); ++ reset_control_assert(res->phy_reset); ++ ++ writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); ++ + ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); + if (ret < 0) { + dev_err(dev, "cannot enable regulators\n"); +-- +2.27.0 + From 21cf17bb4ce5cb0cacb15d3659a544c215590001 Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Mon, 19 Oct 2020 15:57:40 +0200 Subject: [PATCH 13/15] lantiq: remove support for kernel 4.19 The target uses 5.4 as default kernel since 06/2020. Kernel 4.19 support is not really maintained anymore, it does not seem to be needed and upcoming changes (mainly DSA) will break backward-compatibility anyway. Thus, make maintaining of old stuff and reviewing of new stuff easier by removing support for kernel 4.19. Signed-off-by: Adrian Schmutzler --- target/linux/lantiq/ase/config-4.19 | 24 - target/linux/lantiq/config-4.19 | 221 - target/linux/lantiq/falcon/config-4.19 | 12 - .../arch/mips/boot/dts/lantiq/amazonse.dtsi | 247 - .../dts/lantiq/amazonse_allnet_all0333cj.dts | 111 - .../dts/lantiq/amazonse_netgear_dgn1000b.dts | 153 - .../arch/mips/boot/dts/lantiq/ar9.dtsi | 422 -- .../boot/dts/lantiq/ar9_avm_fritz7312.dts | 170 - .../boot/dts/lantiq/ar9_avm_fritz7320.dts | 151 - .../boot/dts/lantiq/ar9_bt_homehub-v3a.dts | 191 - .../dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts | 197 - .../boot/dts/lantiq/ar9_netgear_dgn3500.dts | 8 - .../boot/dts/lantiq/ar9_netgear_dgn3500b.dts | 8 - .../mips/boot/dts/lantiq/ar9_zte_h201l.dts | 172 - .../boot/dts/lantiq/ar9_zyxel_p-2601hn.dts | 178 - .../arch/mips/boot/dts/lantiq/danube.dtsi | 325 - .../dts/lantiq/danube_arcadyan_arv4510pw.dts | 214 - .../lantiq/danube_arcadyan_arv4518pwr01.dts | 8 - .../lantiq/danube_arcadyan_arv4518pwr01.dtsi | 200 - .../lantiq/danube_arcadyan_arv4518pwr01a.dts | 12 - .../dts/lantiq/danube_arcadyan_arv4519pw.dts | 205 - .../dts/lantiq/danube_arcadyan_arv4520pw.dts | 222 - .../dts/lantiq/danube_arcadyan_arv4525pw.dts | 151 - .../dts/lantiq/danube_arcadyan_arv452cqw.dts | 240 - .../lantiq/danube_arcadyan_arv7506pw11.dts | 162 - .../lantiq/danube_arcadyan_arv7510pw22.dts | 198 - .../dts/lantiq/danube_arcadyan_arv7518pw.dts | 233 - .../dts/lantiq/danube_arcadyan_arv7519pw.dts | 217 - .../dts/lantiq/danube_arcadyan_arv7525pw.dts | 149 - .../dts/lantiq/danube_arcadyan_arv752dpw.dts | 243 - .../lantiq/danube_arcadyan_arv752dpw22.dts | 261 - .../lantiq/danube_arcadyan_arv8539pw22.dts | 181 - .../dts/lantiq/danube_audiocodes_mp-252.dts | 112 - .../boot/dts/lantiq/danube_bt_homehub-v2b.dts | 238 - .../dts/lantiq/danube_lantiq_easy50712.dts | 72 - .../lantiq/danube_siemens_gigaset-sx76x.dts | 119 - .../arch/mips/boot/dts/lantiq/falcon.dtsi | 366 -- .../dts/lantiq/falcon_lantiq_easy88388.dts | 93 - .../dts/lantiq/falcon_lantiq_easy88444.dts | 72 - .../lantiq/falcon_lantiq_easy98000-nand.dts | 39 - .../lantiq/falcon_lantiq_easy98000-nor.dts | 41 - .../lantiq/falcon_lantiq_easy98000-sflash.dts | 14 - .../dts/lantiq/falcon_lantiq_easy98000.dtsi | 110 - .../lantiq/falcon_lantiq_easy98020-v18.dts | 68 - .../dts/lantiq/falcon_lantiq_easy98020.dts | 85 - .../dts/lantiq/falcon_lantiq_easy98021.dts | 81 - .../lantiq/falcon_lantiq_easy98035synce.dts | 76 - .../falcon_lantiq_easy98035synce1588.dts | 76 - .../dts/lantiq/falcon_lantiq_falcon-mdu.dts | 53 - .../dts/lantiq/falcon_lantiq_falcon-sfp.dts | 76 - .../boot/dts/lantiq/falcon_sflash-16m.dtsi | 41 - .../arch/mips/boot/dts/lantiq/vr9.dtsi | 495 -- .../dts/lantiq/vr9_alphanetworks_asl56026.dts | 155 - .../dts/lantiq/vr9_arcadyan_arv7519rw22.dts | 246 - .../boot/dts/lantiq/vr9_arcadyan_vg3503j.dts | 144 - .../lantiq/vr9_arcadyan_vgv7510kw22-brn.dts | 65 - .../lantiq/vr9_arcadyan_vgv7510kw22-nor.dts | 31 - .../dts/lantiq/vr9_arcadyan_vgv7519-brn.dts | 70 - .../dts/lantiq/vr9_arcadyan_vgv7519-nor.dts | 29 - .../lantiq/vr9_avm_fritz3370-rev2-hynix.dts | 39 - .../lantiq/vr9_avm_fritz3370-rev2-micron.dts | 37 - .../boot/dts/lantiq/vr9_avm_fritz7360-v2.dts | 81 - .../boot/dts/lantiq/vr9_avm_fritz7360sl.dts | 81 - .../boot/dts/lantiq/vr9_avm_fritz7362sl.dts | 113 - .../boot/dts/lantiq/vr9_avm_fritz736x.dtsi | 200 - .../boot/dts/lantiq/vr9_avm_fritz7412.dts | 218 - .../boot/dts/lantiq/vr9_bt_homehub-v5a.dts | 283 - .../dts/lantiq/vr9_buffalo_wbmr-300hpd.dts | 312 - .../dts/lantiq/vr9_lantiq_easy80920-nand.dts | 66 - .../dts/lantiq/vr9_lantiq_easy80920-nor.dts | 37 - .../boot/dts/lantiq/vr9_lantiq_easy80920.dtsi | 279 - .../boot/dts/lantiq/vr9_netgear_dm200.dts | 186 - .../boot/dts/lantiq/vr9_tplink_tdw8970.dts | 8 - .../boot/dts/lantiq/vr9_tplink_tdw8980.dts | 33 - .../boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi | 272 - .../mips/boot/dts/lantiq/vr9_tplink_vr200.dts | 92 - .../boot/dts/lantiq/vr9_tplink_vr200.dtsi | 213 - .../boot/dts/lantiq/vr9_tplink_vr200v.dts | 99 - .../dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts | 71 - .../dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts | 65 - .../boot/dts/lantiq/ar9_netgear_dgn3500.dtsi | 185 - .../dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi | 258 - .../boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi | 295 - .../dts/lantiq/vr9_avm_fritz3370-rev2.dtsi | 279 - .../dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi | 259 - .../arch/mips/boot/dts/lantiq/amazonse.dtsi | 0 .../dts/lantiq/amazonse_allnet_all0333cj.dts | 0 .../dts/lantiq/amazonse_netgear_dgn1000b.dts | 0 .../arch/mips/boot/dts/lantiq/ar9.dtsi | 0 .../boot/dts/lantiq/ar9_avm_fritz7312.dts | 0 .../boot/dts/lantiq/ar9_avm_fritz7320.dts | 0 .../boot/dts/lantiq/ar9_bt_homehub-v3a.dts | 0 .../dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts | 0 .../boot/dts/lantiq/ar9_netgear_dgn3500.dts | 0 .../boot/dts/lantiq/ar9_netgear_dgn3500.dtsi | 0 .../boot/dts/lantiq/ar9_netgear_dgn3500b.dts | 0 .../mips/boot/dts/lantiq/ar9_zte_h201l.dts | 0 .../boot/dts/lantiq/ar9_zyxel_p-2601hn.dts | 0 .../arch/mips/boot/dts/lantiq/danube.dtsi | 0 .../dts/lantiq/danube_arcadyan_arv4510pw.dts | 0 .../lantiq/danube_arcadyan_arv4518pwr01.dts | 0 .../lantiq/danube_arcadyan_arv4518pwr01.dtsi | 0 .../lantiq/danube_arcadyan_arv4518pwr01a.dts | 0 .../dts/lantiq/danube_arcadyan_arv4519pw.dts | 0 .../dts/lantiq/danube_arcadyan_arv4520pw.dts | 0 .../dts/lantiq/danube_arcadyan_arv4525pw.dts | 0 .../dts/lantiq/danube_arcadyan_arv452cqw.dts | 0 .../lantiq/danube_arcadyan_arv7506pw11.dts | 0 .../lantiq/danube_arcadyan_arv7510pw22.dts | 0 .../dts/lantiq/danube_arcadyan_arv7518pw.dts | 0 .../dts/lantiq/danube_arcadyan_arv7519pw.dts | 0 .../dts/lantiq/danube_arcadyan_arv7525pw.dts | 0 .../dts/lantiq/danube_arcadyan_arv752dpw.dts | 0 .../lantiq/danube_arcadyan_arv752dpw22.dts | 0 .../lantiq/danube_arcadyan_arv8539pw22.dts | 0 .../dts/lantiq/danube_audiocodes_mp-252.dts | 0 .../boot/dts/lantiq/danube_bt_homehub-v2b.dts | 0 .../dts/lantiq/danube_lantiq_easy50712.dts | 0 .../lantiq/danube_siemens_gigaset-sx76x.dts | 0 .../arch/mips/boot/dts/lantiq/falcon.dtsi | 0 .../dts/lantiq/falcon_lantiq_easy88388.dts | 0 .../dts/lantiq/falcon_lantiq_easy88444.dts | 0 .../lantiq/falcon_lantiq_easy98000-nand.dts | 0 .../lantiq/falcon_lantiq_easy98000-nor.dts | 0 .../lantiq/falcon_lantiq_easy98000-sflash.dts | 0 .../dts/lantiq/falcon_lantiq_easy98000.dtsi | 0 .../lantiq/falcon_lantiq_easy98020-v18.dts | 0 .../dts/lantiq/falcon_lantiq_easy98020.dts | 0 .../dts/lantiq/falcon_lantiq_easy98021.dts | 0 .../lantiq/falcon_lantiq_easy98035synce.dts | 0 .../falcon_lantiq_easy98035synce1588.dts | 0 .../dts/lantiq/falcon_lantiq_falcon-mdu.dts | 0 .../dts/lantiq/falcon_lantiq_falcon-sfp.dts | 0 .../boot/dts/lantiq/falcon_sflash-16m.dtsi | 0 .../arch/mips/boot/dts/lantiq/vr9.dtsi | 0 .../dts/lantiq/vr9_alphanetworks_asl56026.dts | 0 .../dts/lantiq/vr9_arcadyan_arv7519rw22.dts | 0 .../boot/dts/lantiq/vr9_arcadyan_vg3503j.dts | 0 .../lantiq/vr9_arcadyan_vgv7510kw22-brn.dts | 0 .../lantiq/vr9_arcadyan_vgv7510kw22-nor.dts | 0 .../dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi | 0 .../dts/lantiq/vr9_arcadyan_vgv7519-brn.dts | 0 .../dts/lantiq/vr9_arcadyan_vgv7519-nor.dts | 0 .../boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi | 0 .../lantiq/vr9_avm_fritz3370-rev2-hynix.dts | 0 .../lantiq/vr9_avm_fritz3370-rev2-micron.dts | 0 .../dts/lantiq/vr9_avm_fritz3370-rev2.dtsi | 0 .../boot/dts/lantiq/vr9_avm_fritz7360-v2.dts | 0 .../boot/dts/lantiq/vr9_avm_fritz7360sl.dts | 0 .../boot/dts/lantiq/vr9_avm_fritz7362sl.dts | 0 .../boot/dts/lantiq/vr9_avm_fritz736x.dtsi | 0 .../boot/dts/lantiq/vr9_avm_fritz7412.dts | 0 .../boot/dts/lantiq/vr9_bt_homehub-v5a.dts | 0 .../dts/lantiq/vr9_buffalo_wbmr-300hpd.dts | 0 .../dts/lantiq/vr9_lantiq_easy80920-nand.dts | 0 .../dts/lantiq/vr9_lantiq_easy80920-nor.dts | 0 .../boot/dts/lantiq/vr9_lantiq_easy80920.dtsi | 0 .../boot/dts/lantiq/vr9_netgear_dm200.dts | 0 .../boot/dts/lantiq/vr9_tplink_tdw8970.dts | 0 .../boot/dts/lantiq/vr9_tplink_tdw8980.dts | 0 .../boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi | 0 .../mips/boot/dts/lantiq/vr9_tplink_vr200.dts | 0 .../boot/dts/lantiq/vr9_tplink_vr200.dtsi | 0 .../boot/dts/lantiq/vr9_tplink_vr200v.dts | 0 .../dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts | 0 .../dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts | 0 .../dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi | 0 .../0001-MIPS-lantiq-add-pcie-driver.patch | 5520 ----------------- .../0004-MIPS-lantiq-add-atm-hack.patch | 480 -- ...s-struct-device-to-DMA-API-functions.patch | 43 - ...s-struct-device-to-DMA-API-functions.patch | 50 - ...-MIPS-lantiq-backport-old-timer-code.patch | 1034 --- .../0018-MTD-nand-lots-of-xrx200-fixes.patch | 122 - ...antiq-handle-NO_XIP-on-cfi0001-flash.patch | 25 - ...25p80-allow-loading-mtd-name-from-OF.patch | 44 - ...T-PHY-add-led-support-for-intel-xway.patch | 294 - ...antiq-autoselect-soc-rev-matching-fw.patch | 45 - ...0025-NET-MIPS-lantiq-adds-xrx200-net.patch | 3467 ----------- .../0028-NET-lantiq-various-etop-fixes.patch | 878 --- .../0030-GPIO-add-named-gpio-exports.patch | 169 - ...PS-lantiq-add-FALC-ON-i2c-bus-master.patch | 1034 --- ...iq-wifi-and-ethernet-eeprom-handling.patch | 218 - ...42-arch-mips-increase-io_space_limit.patch | 23 - ...e-lantiq-settings-match-vendor-drive.patch | 78 - ...PS-lantiq-improve-USB-initialization.patch | 49 - .../patches-4.19/0101-find_active_root.patch | 93 - .../0151-lantiq-ifxmips_pcie-use-of.patch | 191 - .../lantiq/patches-4.19/0152-lantiq-VPE.patch | 180 - .../0154-lantiq-pci-bar11mask-fix.patch | 22 - .../patches-4.19/0155-lantiq-VPE-nosmp.patch | 14 - .../0160-owrt-lantiq-multiple-flash.patch | 220 - ...-cmdset-0001-disable-buffered-writes.patch | 11 - ...add-gphy-clk-src-device-tree-binding.patch | 30 - .../0701-NET-lantiq-etop-of-mido.patch | 37 - target/linux/lantiq/xrx200/config-4.19 | 90 - target/linux/lantiq/xway/config-4.19 | 46 - target/linux/lantiq/xway_legacy/config-4.19 | 34 - 197 files changed, 27155 deletions(-) delete mode 100644 target/linux/lantiq/ase/config-4.19 delete mode 100644 target/linux/lantiq/config-4.19 delete mode 100644 target/linux/lantiq/falcon/config-4.19 delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse.dtsi delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9.dtsi delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube.dtsi delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts delete mode 100644 target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi delete mode 100644 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(100%) rename target/linux/lantiq/{files-4.19 => files}/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi (100%) delete mode 100644 target/linux/lantiq/patches-4.19/0001-MIPS-lantiq-add-pcie-driver.patch delete mode 100644 target/linux/lantiq/patches-4.19/0004-MIPS-lantiq-add-atm-hack.patch delete mode 100644 target/linux/lantiq/patches-4.19/0005-lantiq_etop-pass-struct-device-to-DMA-API-functions.patch delete mode 100644 target/linux/lantiq/patches-4.19/0006-MIPS-lantiq-pass-struct-device-to-DMA-API-functions.patch delete mode 100644 target/linux/lantiq/patches-4.19/0008-MIPS-lantiq-backport-old-timer-code.patch delete mode 100644 target/linux/lantiq/patches-4.19/0018-MTD-nand-lots-of-xrx200-fixes.patch delete mode 100644 target/linux/lantiq/patches-4.19/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch delete mode 100644 target/linux/lantiq/patches-4.19/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch delete mode 100644 target/linux/lantiq/patches-4.19/0023-NET-PHY-add-led-support-for-intel-xway.patch delete mode 100644 target/linux/lantiq/patches-4.19/0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch delete mode 100644 target/linux/lantiq/patches-4.19/0025-NET-MIPS-lantiq-adds-xrx200-net.patch delete mode 100644 target/linux/lantiq/patches-4.19/0028-NET-lantiq-various-etop-fixes.patch delete mode 100644 target/linux/lantiq/patches-4.19/0030-GPIO-add-named-gpio-exports.patch delete mode 100644 target/linux/lantiq/patches-4.19/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch delete mode 100644 target/linux/lantiq/patches-4.19/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch delete mode 100644 target/linux/lantiq/patches-4.19/0042-arch-mips-increase-io_space_limit.patch delete mode 100644 target/linux/lantiq/patches-4.19/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch delete mode 100644 target/linux/lantiq/patches-4.19/0051-MIPS-lantiq-improve-USB-initialization.patch delete mode 100644 target/linux/lantiq/patches-4.19/0101-find_active_root.patch delete mode 100644 target/linux/lantiq/patches-4.19/0151-lantiq-ifxmips_pcie-use-of.patch delete mode 100644 target/linux/lantiq/patches-4.19/0152-lantiq-VPE.patch delete mode 100644 target/linux/lantiq/patches-4.19/0154-lantiq-pci-bar11mask-fix.patch delete mode 100644 target/linux/lantiq/patches-4.19/0155-lantiq-VPE-nosmp.patch delete mode 100644 target/linux/lantiq/patches-4.19/0160-owrt-lantiq-multiple-flash.patch delete mode 100644 target/linux/lantiq/patches-4.19/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch delete mode 100644 target/linux/lantiq/patches-4.19/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch delete mode 100644 target/linux/lantiq/patches-4.19/0701-NET-lantiq-etop-of-mido.patch delete mode 100644 target/linux/lantiq/xrx200/config-4.19 delete mode 100644 target/linux/lantiq/xway/config-4.19 delete mode 100644 target/linux/lantiq/xway_legacy/config-4.19 diff --git a/target/linux/lantiq/ase/config-4.19 b/target/linux/lantiq/ase/config-4.19 deleted file mode 100644 index da9c1bc294..0000000000 --- a/target/linux/lantiq/ase/config-4.19 +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -CONFIG_CPU_MIPSR1=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_FIRMWARE_MEMMAP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -# CONFIG_ISDN is not set -# CONFIG_LBDAF is not set -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_MIPS_FPU_EMULATOR=y -CONFIG_NLS=y -# CONFIG_PSB6970_PHY is not set -# CONFIG_RTL8366_SMI is not set -CONFIG_SOC_AMAZON_SE=y -# CONFIG_SOC_XWAY is not set -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/config-4.19 b/target/linux/lantiq/config-4.19 deleted file mode 100644 index 7510e357a2..0000000000 --- a/target/linux/lantiq/config-4.19 +++ /dev/null @@ -1,221 +0,0 @@ -CONFIG_ARCH_BINFMT_ELF_STATE=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_DISCARD_MEMBLOCK=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_R4K_FPU=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_DIRECT_OPS=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y -CONFIG_DMA_NONCOHERENT_MMAP=y -CONFIG_DMA_NONCOHERENT_OPS=y -CONFIG_DTC=y -# CONFIG_DT_EASY50712 is not set -CONFIG_EARLY_PRINTK=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_IPI=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_MM_LANTIQ=y -CONFIG_GPIO_STP_XWAY=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARCH_COMPILER_H=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_CBPF_JIT=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_COPY_THREAD_TLS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_KVM=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HW_HAS_PCI=y -CONFIG_HW_RANDOM=y -CONFIG_HZ=250 -CONFIG_HZ_250=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LANTIQ=y -CONFIG_LANTIQ_DT_NONE=y -CONFIG_LANTIQ_ETOP=y -CONFIG_LANTIQ_WDT=y -# CONFIG_LANTIQ_XRX200 is not set -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_LANTIQ=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_BRNIMAGE_FW=y -CONFIG_MTD_SPLIT_EVA_FW=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHY_LANTIQ_RCU_USB2=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_LANTIQ=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PINCTRL_XWAY=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_PSB6970_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_LANTIQ=y -CONFIG_RTL8366RB_PHY=y -CONFIG_RTL8366_SMI=y -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_LANTIQ=y -# CONFIG_SOC_AMAZON_SE is not set -# CONFIG_SOC_FALCON is not set -CONFIG_SOC_TYPE_XWAY=y -CONFIG_SOC_XWAY=y -CONFIG_SPI=y -CONFIG_SPI_LANTIQ_SSC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRCU=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -CONFIG_SYS_SUPPORTS_VPE_LOADER=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USE_OF=y -# CONFIG_XRX200_PHY_FW is not set diff --git a/target/linux/lantiq/falcon/config-4.19 b/target/linux/lantiq/falcon/config-4.19 deleted file mode 100644 index 84b36d0066..0000000000 --- a/target/linux/lantiq/falcon/config-4.19 +++ /dev/null @@ -1,12 +0,0 @@ -# CONFIG_MFD_CORE is not set -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux" -CONFIG_PINCTRL_FALCON=y -# CONFIG_PSB6970_PHY is not set -# CONFIG_RESET_LANTIQ is not set -# CONFIG_RTL8366_SMI is not set -CONFIG_SOC_FALCON=y -# CONFIG_SOC_TYPE_XWAY is not set -# CONFIG_SOC_XWAY is not set -CONFIG_SPI_FALCON=y diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse.dtsi deleted file mode 100644 index 496150b7a7..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse.dtsi +++ /dev/null @@ -1,247 +0,0 @@ -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,xway", "lantiq,ase"; - - aliases { - serial0 = &asc1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "mips,mips4Kc"; - reg = <0>; - }; - }; - - reboot { - compatible = "syscon-reboot"; - - regmap = <&rcu0>; - offset = <0x10>; - mask = <0x40000000>; - }; - - biu@1f800000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,biu", "simple-bus"; - reg = <0x1f800000 0x800000>; - ranges = <0x0 0x1f800000 0x7fffff>; - - icu0: icu@80200 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,icu"; - reg = <0x80200 0x28 - 0x80228 0x28 - 0x80250 0x28 - 0x80278 0x28 - 0x802a0 0x28>; - }; - - watchdog@803f0 { - compatible = "lantiq,wdt"; - reg = <0x803f0 0x10>; - }; - }; - - sram@1f000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sram", "simple-bus"; - reg = <0x1f000000 0x800000>; - ranges = <0x0 0x1f000000 0x7fffff>; - - eiu0: eiu@101000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,eiu-xway"; - reg = <0x101000 0x1000>; - interrupt-parent = <&icu0>; - lantiq,eiu-irqs = <29 30 31>; - }; - - pmu0: pmu@102000 { - compatible = "lantiq,pmu-xway"; - reg = <0x102000 0x1000>; - }; - - cgu0: cgu@103000 { - compatible = "lantiq,cgu-xway"; - reg = <0x103000 0x1000>; - #clock-cells = <1>; - }; - - rcu0: rcu@203000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,ase-rcu", "simple-mfd", "syscon"; - reg = <0x203000 0x1000>; - ranges = <0x0 0x203000 0x100>; - big-endian; - - reset: reset-controller@10 { - compatible = "lantiq,danube-reset"; - reg = <0x10 4>, <0x14 4>; - - #reset-cells = <2>; - }; - - usb_phy: usb2-phy@18 { - compatible = "lantiq,ase-usb2-phy"; - reg = <0x18 4>; - status = "disabled"; - - resets = <&reset 4 4>; - reset-names = "ctrl"; - #phy-cells = <0>; - }; - }; - }; - - fpi@10000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,fpi", "simple-bus"; - ranges = <0x0 0x10000000 0xeefffff>; - reg = <0x10000000 0xef00000>; - - localbus: localbus@0 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ - 1 0 0x4000000 0x4000010>; /* addsel1 */ - compatible = "lantiq,localbus", "simple-bus"; - }; - - spi: spi@e100800 { - compatible = "lantiq,ase-spi"; - reg = <0xe100800 0x100>; - interrupt-parent = <&icu0>; - interrupts = <24 25 26>; - interrupt-names = "spi_rx", "spi_tx", "spi_err", - "spi_frm"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>; - status = "disabled"; - }; - - gptu@e100a00 { - compatible = "lantiq,gptu-xway"; - reg = <0xe100a00 0x100>; - interrupt-parent = <&icu0>; - interrupts = <33 34 35 36 37 38>; - }; - - gpio: pinmux@e100b10 { - compatible = "lantiq,ase-pinctrl"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xe100b10 0xa0>; - - asc_pins: asc-pins { - mux { - lantiq,groups = "asc"; - lantiq,function = "asc"; - }; - }; - - mdio_pins: mdio { - mux { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - }; - - spi_pins: spi { - mux-0 { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - mux-1 { - lantiq,groups = "spi_do", "spi_clk"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - - spi_cs4_pins: spi-cs4 { - mux { - lantiq,groups = "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - }; - - asc1: serial@e100c00 { - compatible = "lantiq,asc"; - reg = <0xe100c00 0x400>; - interrupt-parent = <&icu0>; - interrupts = <72 74 75>; - pinctrl-0 = <&asc_pins>; - pinctrl-names = "default"; - }; - - mei@e116000 { - compatible = "lantiq,mei-xway"; - reg = <0xe116000 0x400>; - interrupt-parent = <&icu0>; - interrupts = <81>; - }; - - usb: usb@e101000 { - compatible = "lantiq,ase-usb"; - reg = <0xe101000 0x1000 - 0xe120000 0x3f000>; - interrupt-parent = <&icu0>; - interrupts = <39>; - dr_mode = "host"; - phys = <&usb_phy>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - dma0: dma@e104100 { - compatible = "lantiq,dma-xway"; - reg = <0xe104100 0x800>; - }; - - ebu0: ebu@e105300 { - compatible = "lantiq,ebu-xway"; - reg = <0xe105300 0x100>; - }; - - ppe@e234000 { - compatible = "lantiq,ppe-ase"; - reg = <0xe234000 0x40000>; - interrupt-parent = <&icu0>; - interrupts = <85>; - }; - - gsw: etop@e180000 { - compatible = "lantiq,etop-xway"; - reg = <0xe180000 0x40000>; - interrupt-parent = <&icu0>; - interrupts = <105 109>; - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - }; - }; - - adsl { - compatible = "lantiq,adsl-ase"; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts deleted file mode 100644 index bbb33cdca3..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts +++ /dev/null @@ -1,111 +0,0 @@ -/dts-v1/; - -#include "amazonse.dtsi" - -/ { - compatible = "allnet,all0333cj", "lantiq,xway", "lantiq,ase"; - model = "Allnet ALL0333CJ DSL Modem"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - - led-dsl = &dsl; - led-internet = &online_green; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x1000000>; - }; - - leds { - compatible = "gpio-leds"; - - /* power led: red=off, green=on */ - power: power { - label = "green:power"; - gpios = <&gpio 13 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - lan: lan { - label = "green:lan"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - }; - - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - }; - - online_green: online { - label = "green:online"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - }; - online_red { - label = "red:online"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - keys_in { - lantiq,pins = "io0",/* "io25", */"io29"; - lantiq,pull = <2>; - lantiq,open-drain = <1>; - }; - }; -}; - -&gsw { - phy-mode = "mii"; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x400000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "firmware"; - reg = <0x10000 0x3ef200>; - }; - - partition@3ff200 { - label = "u-boot-env"; - reg = <0x3ff200 0xc00>; - read-only; - }; - - partition@3ffe00 { - label = "dummy_bits"; - reg = <0x3ffe00 0x200>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts deleted file mode 100644 index 33658ca512..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts +++ /dev/null @@ -1,153 +0,0 @@ -/dts-v1/; - -#include "amazonse.dtsi" - -#include - -/ { - compatible = "netgear,dgn1000b", "lantiq,xway", "lantiq,ase"; - model = "Netgear DGN1000B"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - - led-dsl = &dsl; - led-internet = &online_green; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x1000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - rfkill { - label = "rfkill"; - gpios = <&gpio 25 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - online_green: online { - label = "green:online"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - online2 { - label = "red:online"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - wps { - label = "green:wps"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - power: power { - label = "green:power"; - gpios = <&gpio 13 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - /* - power red is missing - */ - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - keys_in { - lantiq,pins = "io0",/* "io25", */"io29"; - lantiq,pull = <2>; - lantiq,open-drain = <1>; - }; - }; -}; - -&gsw { - phy-mode = "mii"; - mac-address = [ 00 11 22 33 44 55 ]; -}; - -&spi { - status = "okay"; - - flash@1 { - compatible = "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <5000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x20000>; - label = "SPI (RO) U-Boot Image"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0x10000>; - label = "ENV_MAC"; - read-only; - }; - - partition@30000 { - reg = <0x30000 0x10000>; - label = "DPF"; - read-only; - }; - - partition@40000 { - reg = <0x40000 0x10000>; - label = "NVRAM"; - read-only; - }; - - partition@500000 { - reg = <0x50000 0x003a0000>; - label = "kernel"; - }; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9.dtsi deleted file mode 100644 index 12af82b8ce..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9.dtsi +++ /dev/null @@ -1,422 +0,0 @@ -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,xway", "lantiq,ar9"; - - aliases { - serial0 = &asc1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "mips,mips34K"; - reg = <0>; - }; - }; - - reboot { - compatible = "syscon-reboot"; - - regmap = <&rcu0>; - offset = <0x10>; - mask = <0x40000000>; - }; - - biu@1f800000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,biu", "simple-bus"; - reg = <0x1f800000 0x800000>; - ranges = <0x0 0x1f800000 0x7fffff>; - - icu0: icu@80200 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,icu"; - reg = <0x80200 0x28 - 0x80228 0x28 - 0x80250 0x28 - 0x80278 0x28 - 0x802a0 0x28>; - }; - - watchdog@803f0 { - compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt"; - reg = <0x803f0 0x10>; - - regmap = <&rcu0>; - }; - }; - - sram@1f000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sram", "simple-bus"; - reg = <0x1f000000 0x800000>; - ranges = <0x0 0x1f000000 0x7fffff>; - - eiu0: eiu@101000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,eiu-xway"; - reg = <0x101000 0x1000>; - interrupt-parent = <&icu0>; - lantiq,eiu-irqs = <166 135 66 40 41 42>; - }; - - pmu0: pmu@102000 { - compatible = "lantiq,pmu-xway"; - reg = <0x102000 0x1000>; - }; - - cgu0: cgu@103000 { - compatible = "lantiq,cgu-xway"; - reg = <0x103000 0x1000>; - #clock-cells = <1>; - }; - - rcu0: rcu@203000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,xrx100-rcu", "simple-mfd", "syscon"; - reg = <0x203000 0x1000>; - ranges = <0x0 0x203000 0x100>; - big-endian; - - reset: reset-controller@10 { - compatible = "lantiq,xrx100-reset", "lantiq,danube-reset"; - reg = <0x10 4>, <0x14 4>; - - #reset-cells = <2>; - }; - - usb_phy0: usb2-phy@18 { - compatible = "lantiq,xrx100-usb2-phy"; - reg = <0x18 4>; - status = "disabled"; - - resets = <&reset 4 4>; - reset-names = "ctrl"; - #phy-cells = <0>; - }; - - usb_phy1: usb2-phy@34 { - compatible = "lantiq,xrx100-usb2-phy"; - reg = <0x34 4>; - status = "disabled"; - - resets = <&reset 28 28>; - reset-names = "ctrl"; - #phy-cells = <0>; - }; - }; - }; - - fpi@10000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,fpi", "simple-bus"; - ranges = <0x0 0x10000000 0xeefffff>; - reg = <0x10000000 0xef00000>; - - localbus: localbus@0 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ - 1 0 0x4000000 0x4000010>; /* addsel1 */ - compatible = "lantiq,localbus", "simple-bus"; - }; - - gptu@e100a00 { - compatible = "lantiq,gptu-xway"; - reg = <0xe100a00 0x100>; - interrupt-parent = <&icu0>; - interrupts = <126 127 128 129 130 131>; - }; - - asc0: serial@e100400 { - compatible = "lantiq,asc"; - reg = <0xe100400 0x400>; - interrupt-parent = <&icu0>; - interrupts = <104 105 106>; - status = "disabled"; - }; - - spi: spi@e100800 { - compatible = "lantiq,xrx100-spi"; - reg = <0xe100800 0x100>; - interrupt-parent = <&icu0>; - interrupts = <22 23 24>; - interrupt-names = "spi_rx", "spi_tx", "spi_err", - "spi_frm"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>; - status = "disabled"; - }; - - gpio: pinmux@e100b10 { - compatible = "lantiq,xrx100-pinctrl"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xe100b10 0xa0>; - - mdio_pins: mdio { - mux { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - }; - - nand_pins: nand { - mux-0 { - lantiq,groups = "nand cle", "nand ale", - "nand rd"; - lantiq,function = "ebu"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - mux-1 { - lantiq,groups = "nand rdy"; - lantiq,function = "ebu"; - lantiq,output = <0>; - lantiq,pull = <2>; - }; - }; - - nand_cs1_pins: nand-cs1 { - mux { - lantiq,groups = "nand cs1"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - - pci_gnt1_pins: pci-gnt1 { - mux { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - - pci_gnt2_pins: pci-gnt2 { - mux { - lantiq,groups = "gnt2"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - - pci_gnt3_pins: pci-gnt3 { - mux { - lantiq,groups = "gnt3"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - - pci_gnt4_pins: pci-gnt4 { - mux { - lantiq,groups = "gnt4"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - - pci_req1_pins: pci-req1 { - mux { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - }; - - pci_req2_pins: pci-req2 { - mux { - lantiq,groups = "req2"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - }; - - pci_req3_pins: pci-req3 { - mux { - lantiq,groups = "req3"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - }; - - pci_req4_pins: pci-req4 { - mux { - lantiq,groups = "req4"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - }; - - spi_pins: spi { - mux-0 { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - mux-1 { - lantiq,groups = "spi_do", "spi_clk"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - - spi_cs4_pins: spi-cs4 { - mux { - lantiq,groups = "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - - stp_pins: stp { - mux { - lantiq,groups = "stp"; - lantiq,function = "stp"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - }; - }; - - stp: stp@e100bb0 { - #gpio-cells = <2>; - compatible = "lantiq,gpio-stp-xway"; - gpio-controller; - reg = <0xe100bb0 0x40>; - - pinctrl-0 = <&stp_pins>; - pinctrl-names = "default"; - - status = "disabled"; - }; - - asc1: serial@e100c00 { - compatible = "lantiq,asc"; - reg = <0xe100c00 0x400>; - interrupt-parent = <&icu0>; - interrupts = <112 113 114>; - }; - - usb0: usb@e101000 { - compatible = "lantiq,arx100-usb"; - reg = <0xe101000 0x1000 - 0xe120000 0x3f000>; - interrupt-parent = <&icu0>; - interrupts = <62 91>; - dr_mode = "host"; - phys = <&usb_phy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb1: usb@e106000 { - compatible = "lantiq,arx100-usb"; - reg = <0xe106000 0x1000 - 0xe1e0000 0x3f000>; - interrupt-parent = <&icu0>; - interrupts = <91>; - dr_mode = "host"; - phys = <&usb_phy1>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - deu@e103100 { - compatible = "lantiq,deu-arx100"; - reg = <0xe103100 0xf00>; - }; - - dma0: dma@e104100 { - compatible = "lantiq,dma-xway"; - reg = <0xe104100 0x800>; - }; - - ebu0: ebu@e105300 { - compatible = "lantiq,ebu-xway"; - reg = <0xe105300 0x100>; - }; - - mei@e116000 { - compatible = "lantiq,mei-xway"; - reg = <0xe116000 0x9c>; - interrupt-parent = <&icu0>; - interrupts = <63>; - }; - - gsw: etop@e180000 { - compatible = "lantiq,etop-xway"; - reg = <0xe180000 0x40000 - 0xe108000 0x200>; - interrupt-parent = <&icu0>; - interrupts = <73 72>; - mac-address = [ 00 11 22 33 44 55 ]; - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - }; - - ppe@e234000 { - compatible = "lantiq,ppe-arx100"; - reg = <0xe234000 0x3ffd>; - interrupt-parent = <&icu0>; - interrupts = <96>; - }; - - pci0: pci@e105400 { - status = "disabled"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "lantiq,pci-xway"; - bus-range = <0x0 0x0>; - ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ - 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */ - reg = <0x7000000 0x8000 /* config space */ - 0xe105400 0x400>; /* pci bridge */ - lantiq,bus-clock = <33333333>; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = <0x7000 0 0 1 &icu0 30 1>; - req-mask = <0x1>; - }; - }; - - adsl { - compatible = "lantiq,adsl-arx100"; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts deleted file mode 100644 index 6c5ed277ca..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts +++ /dev/null @@ -1,170 +0,0 @@ -/dts-v1/; - -#include "ar9.dtsi" - -#include - -/ { - compatible = "avm,fritz7312", "lantiq,xway", "lantiq,ar9"; - model = "AVM FRITZ!Box 7312"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - - led-dsl = &info_green; - led-wifi = &wlan; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - wlan { - label = "wlan"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - dect { - label = "dect"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - power: power { - label = "green:power"; - gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - voice { - label = "green:fon"; - gpios = <&gpio 47 GPIO_ACTIVE_LOW>; - }; - dect { - label = "green:dect"; - gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - }; - wlan: wlan { - label = "green:wlan"; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - }; - info_green: info_green { - label = "green:info"; - gpios = <&gpio 35 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ar8030-intr { - lantiq,groups = "exin3"; - lantiq,function = "exin"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - ar8030-clk { - lantiq,groups = "clkout2"; - lantiq,output = <1>; - lantiq,open-drain; - }; - ar8030-rst { - lantiq,pins = "io34"; - lantiq,output = <1>; - lantiq,pull = <2>; - lantiq,open-drain; - }; - }; -}; - -&gsw { - phy-mode = "rmii"; - phy-handle = <&phy0>; - mtd-mac-address = <&ath9k_cal 0xa91>; - mtd-mac-address-increment = <(-2)>; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - reset-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; - max-speed = <100>; - }; - }; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x1000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - ath9k_cal: partition@0 { - label = "urlader"; - reg = <0x00000 0x20000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0xf60000>; - }; - - partition@f80000 { - label = "tffs (1)"; - reg = <0xf80000 0x40000>; - read-only; - }; - - partition@fc0000 { - label = "tffs (2)"; - reg = <0xfc0000 0x40000>; - read-only; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>, - <&pci_gnt3_pins>, <&pci_gnt4_pins>, - <&pci_req1_pins>, <&pci_req2_pins>, - <&pci_req4_pins>; - pinctrl-names = "default"; - - req-mask = <0xf>; - gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>; - - wifi@0,0 { - compatible = "pci0,0"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts deleted file mode 100644 index e215baf6f1..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts +++ /dev/null @@ -1,151 +0,0 @@ -/dts-v1/; - -#include "ar9.dtsi" - -#include - -/ { - compatible = "avm,fritz7320", "lantiq,xway", "lantiq,ar9"; - model = "AVM FRITZ!Box 7320"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - - led-dsl = &info_green; - led-wifi = &wlan; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - dect { - label = "dect"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - power: power { - label = "green:power"; - gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - voice { - label = "green:fon"; - gpios = <&gpio 47 GPIO_ACTIVE_LOW>; - }; - dect { - label = "green:dect"; - gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - }; - wlan: wlan { - label = "green:wlan"; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - }; - info_green: info_green { - label = "green:info"; - gpios = <&gpio 35 GPIO_ACTIVE_LOW>; - }; - info_red { - label = "red:info"; - gpios = <&gpio 45 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gsw { - phy-mode = "mii"; - mtd-mac-address = <&ath9k_cal 0xa91>; - mtd-mac-address-increment = <(-2)>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x1000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - ath9k_cal: partition@0 { - label = "urlader"; - reg = <0x00000 0x20000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0xf60000>; - }; - - partition@f80000 { - label = "tffs (1)"; - reg = <0xf80000 0x40000>; - read-only; - }; - - partition@fc0000 { - label = "tffs (2)"; - reg = <0xfc0000 0x40000>; - read-only; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>, - <&pci_gnt3_pins>, <&pci_gnt4_pins>, - <&pci_req1_pins>, <&pci_req2_pins>, - <&pci_req3_pins>, <&pci_req4_pins>; - - req-mask = <0xf>; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@0,0 { - compatible = "pci0,0"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - }; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_phy1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts deleted file mode 100644 index acfa023154..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts +++ /dev/null @@ -1,191 +0,0 @@ -/dts-v1/; - -#include "ar9.dtsi" - -#include - -/ { - compatible = "bt,homehub-v3a", "lantiq,xway", "lantiq,ar9"; - model = "BT Home Hub 3A"; /* SoC: Lantiq ar9 @ 333MHz */ - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_orange; - led-failsafe = &power_red; - led-running = &power_blue; - led-upgrade = &power_blue; - - led-dsl = &broadband_blue; - led-wifi = &wireless_blue; - }; - - memory@0 { /* RAM: Samsung K4H511638F-LC 64MB */ - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - restart { - label = "restart"; - gpios = <&gpio 52 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 53 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - wireless-red { - label = "red:wireless"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; - wireless-orange { - label = "orange:wireless"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - wireless_blue: wireless-blue { - label = "blue:wireless"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - - broadband-red { - label = "red:broadband"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - }; - broadband-orange { - label = "orange:broadband"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - }; - broadband_blue: broadband-blue { - label = "blue:broadband"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - }; - - power_red: power-red { - label = "red:power"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - }; - power_orange: power-orange { - label = "orange:power"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_blue: power-blue { - label = "blue:power"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci_rst { - lantiq,pins = "io21"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - }; - }; -}; - -&gsw { - phy-mode = "rgmii"; -}; - -&localbus { - flash@1 { /* NAND Flash: Samsung K9F5608U0D-JIB0 32MB */ - compatible = "lantiq,nand-xway"; - lantiq,cs = <1>; - bank-width = <2>; - reg = <1 0x0 0x2000000 >; - req-mask = <0x1>; /* PCI request lines to mask during NAND access */ - - pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; - pinctrl-names = "default"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "preboot"; - reg = <0x00000 0x8000>; - read-only; - }; - partition@8000 { - label = "u-boot"; - reg = <0x8000 0x05c000>; - read-only; - }; - partition@64000 { - label = "u-boot-env"; - reg = <0x64000 0x004000>; - }; - ath9k_cal: partition@68000 { - label = "art-copy"; - reg = <0x68000 0x004000>; - }; - partition@6c000 { - label = "kernel"; - reg = <0x6c000 0x200000>; - }; - partition@26c000 { - label = "ubi"; - reg = <0x26c000 0x1d94000>; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@7000 { - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - }; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts deleted file mode 100644 index d44ebf43ed..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts +++ /dev/null @@ -1,197 +0,0 @@ -/dts-v1/; - -#include "ar9.dtsi" - -#include - -/ { - compatible = "buffalo,wbmr-hp-g300h", "lantiq,xway", "lantiq,ar9"; - model = "Buffalo WBMR-HP-G300H"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &dsl; - led-internet = &online_green; - led-usb = &led_usb; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - eject { - label = "eject"; - gpios = <&gpio 34 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - movie { - label = "movie"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - power_green: power { - label = "green:power"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power2 { - label = "red:power"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - security { - label = "yellow:security"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "green:wireless"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; - }; - online_green: online { - label = "green:internet"; - gpios = <&gpio 17 GPIO_ACTIVE_LOW>; - }; - online2 { - label = "red:internet"; - gpios = <&gpio 18 GPIO_ACTIVE_LOW>; - }; - movie { - label = "blue:movie"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - led_usb: usb { - label = "green:usb"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 36 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci-in { - lantiq,groups = "req1"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci-out { - lantiq,groups = "gnt1"; - lantiq,output = <1>; - lantiq,pull = <0>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; -}; - -&gsw { - phy-mode = "rgmii"; - mtd-mac-address = <&boardconfig 0x10024>; -}; - -&pci0 { - status = "okay"; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x60000 0x1f20000>; - }; - - boardconfig: partition@1fc0000 { - label = "board"; - reg = <0x1fc0000 0x20000>; - read-only; - }; - - partition@1fe0000 { - label = "calibration"; - reg = <0x1fe0000 0x20000>; - read-only; - }; - }; - }; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts deleted file mode 100644 index cbc99fe620..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "ar9_netgear_dgn3500.dtsi" - -/ { - compatible = "netgear,dgn3500", "lantiq,xway", "lantiq,ar9"; - model = "Netgear DGN3500"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts deleted file mode 100644 index b69613e48f..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "ar9_netgear_dgn3500.dtsi" - -/ { - compatible = "netgear,dgn3500b", "lantiq,xway", "lantiq,ar9"; - model = "Netgear DGN3500B"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts deleted file mode 100644 index 3c80edea24..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts +++ /dev/null @@ -1,172 +0,0 @@ -/dts-v1/; - -#include "ar9.dtsi" - -#include - -/ { - compatible = "zte,h201l", "lantiq,xway", "lantiq,ar9"; - model = "ZTE H210L"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_green; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &dsl; - led-internet = &online; - led-usb = &led_usb; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 53 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - rfkill { - label = "rfkill"; - gpios = <&gpio 55 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - power_green: power { - label = "green:power"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - online: online { - label = "green:internet"; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - phone { - label = "green:phone"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - }; - wps { - label = "green:wps"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "green:wlan"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - led_usb: usb { - label = "green:usb"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - switch { - gpio-export,name = "switch"; - gpio-export,output = <1>; - gpios = <&gpio 38 GPIO_ACTIVE_HIGH>; - }; - usb { - gpio-export,name = "usb"; - gpio-export,output = <1>; - gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; - }; - wifi { - gpio-export,name = "wifi"; - gpio-export,output = <1>; - gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 36 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - }; -}; - -&gsw { - phy-mode = "rgmii"; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x20000>; - read-only; - }; - - partition@20000 { - label = "u-boot-env"; - reg = <0x20000 0x10000>; - read-only; - }; - - partition@30000 { - label = "firmware"; - reg = <0x30000 0x7d0000>; - }; - }; - }; -}; - -&usb_phy0 { - status = "okay"; -}; - - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts deleted file mode 100644 index 06bcf94a14..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts +++ /dev/null @@ -1,178 +0,0 @@ -/dts-v1/; - -#include "ar9.dtsi" - -#include - -/ { - compatible = "zyxel,p-2601hn", "lantiq,xway", "lantiq,ar9"; - model = "ZyXEL P-2601HN-Fx"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &dsl; - led-internet = &online; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 53 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - rfkill { - label = "rfkill"; - gpios = <&gpio 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - power_green: power { - label = "green:power"; - gpios = <&stp 11 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power2 { - label = "red:power"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - }; - online: online { - label = "green:internet"; - gpios = <&stp 13 GPIO_ACTIVE_LOW>; - }; - online2 { - label = "red:internet"; - gpios = <&stp 12 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "green:dsl"; - gpios = <&stp 14 GPIO_ACTIVE_LOW>; - }; - phone { - label = "green:phone"; - gpios = <&stp 9 GPIO_ACTIVE_LOW>; - }; - phone2 { - label = "orange:phone"; - gpios = <&stp 8 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "green:wireless"; - gpios = <&stp 15 GPIO_ACTIVE_LOW>; - }; - wifi2 { - label = "orange:wireless"; - gpios = <&stp 10 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - switch { - gpio-export,name = "switch"; - gpio-export,output = <1>; - gpios = <&gpio 50 GPIO_ACTIVE_HIGH>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - }; -}; - -&gsw { - phy-mode = "rmii"; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@60000 { - label = "firmware"; - reg = <0x60000 0xfa0000>; - }; - }; - }; -}; - -&pci0 { - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; -}; - -&stp { - status = "okay"; - lantiq,shadow = <0xfff>; - lantiq,groups = <0x3>; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube.dtsi deleted file mode 100644 index ae8c1c045a..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube.dtsi +++ /dev/null @@ -1,325 +0,0 @@ -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,xway", "lantiq,danube"; - - aliases { - serial0 = &asc1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "mips,mips24Kc"; - reg = <0>; - }; - }; - - reboot { - compatible = "syscon-reboot"; - - regmap = <&rcu0>; - offset = <0x10>; - mask = <0x40000000>; - }; - - biu@1f800000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,biu", "simple-bus"; - reg = <0x1f800000 0x800000>; - ranges = <0x0 0x1f800000 0x7fffff>; - - icu0: icu@80200 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,icu"; - reg = <0x80200 0x28 - 0x80228 0x28 - 0x80250 0x28 - 0x80278 0x28 - 0x802a0 0x28>; - }; - - watchdog@803f0 { - compatible = "lantiq,wdt"; - reg = <0x803f0 0x10>; - }; - }; - - sram@1f000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sram", "simple-bus"; - reg = <0x1f000000 0x800000>; - ranges = <0x0 0x1f000000 0x7fffff>; - - eiu0: eiu@101000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,eiu-xway"; - reg = <0x101000 0x1000>; - interrupt-parent = <&icu0>; - lantiq,eiu-irqs = <166 135 66>; - }; - - pmu0: pmu@102000 { - compatible = "lantiq,pmu-xway"; - reg = <0x102000 0x1000>; - }; - - cgu0: cgu@103000 { - compatible = "lantiq,cgu-xway"; - reg = <0x103000 0x1000>; - #clock-cells = <1>; - }; - - vmmc: vmmc@107000 { - status = "disabled"; - compatible = "lantiq,vmmc-xway"; - reg = <0x107000 0x400>; - interrupt-parent = <&icu0>; - interrupts = <150 151 152 153 154 155>; - }; - - rcu0: rcu@203000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,danube-rcu", "simple-mfd", "syscon"; - reg = <0x203000 0x1000>; - ranges = <0x0 0x203000 0x100>; - big-endian; - - reset: reset-controller@10 { - compatible = "lantiq,danube-reset"; - reg = <0x10 4>, <0x14 4>; - - #reset-cells = <2>; - }; - - usb_phy: usb2-phy@18 { - compatible = "lantiq,danube-usb2-phy"; - reg = <0x18 4>; - status = "disabled"; - - resets = <&reset 4 4>; - reset-names = "ctrl"; - #phy-cells = <0>; - }; - }; - }; - - fpi@10000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,fpi", "simple-bus"; - ranges = <0x0 0x10000000 0xeefffff>; - reg = <0x10000000 0xef00000>; - - localbus: localbus@0 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ - 1 0 0x4000000 0x4000010>; /* addsel1 */ - compatible = "lantiq,localbus", "simple-bus"; - }; - - gptu@e100a00 { - compatible = "lantiq,gptu-xway"; - reg = <0xe100a00 0x100>; - interrupt-parent = <&icu0>; - interrupts = <126 127 128 129 130 131>; - }; - - gpios: stp@e100bb0 { - #gpio-cells = <2>; - compatible = "lantiq,gpio-stp-xway"; - gpio-controller; - reg = <0xe100bb0 0x40>; - - pinctrl-0 = <&stp_pins>; - pinctrl-names = "default"; - - lantiq,shadow = <0xfff>; - lantiq,groups = <0x3>; - status = "disabled"; - }; - - asc0: serial@e100400 { - compatible = "lantiq,asc"; - reg = <0xe100400 0x400>; - interrupt-parent = <&icu0>; - interrupts = <104 105 106>; - status = "disabled"; - }; - - gpio: pinmux@e100b10 { - compatible = "lantiq,danube-pinctrl"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xe100b10 0xa0>; - - nand_pins: nand { - mux-0 { - lantiq,groups = "nand cle", "nand ale", - "nand rd"; - lantiq,function = "ebu"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - mux-1 { - lantiq,groups = "nand rdy"; - lantiq,function = "ebu"; - lantiq,output = <0>; - lantiq,pull = <2>; - }; - }; - - nand_cs1_pins: nand-cs1 { - mux { - lantiq,groups = "nand cs1"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - - pci_gnt1_pins: pci-gnt1 { - mux { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - - pci_gnt2_pins: pci-gnt2 { - mux { - lantiq,groups = "gnt2"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - - pci_req1_pins: pci-req1 { - mux { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - }; - - pci_req2_pins: pci-req2 { - mux { - lantiq,groups = "req2"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - }; - - stp_pins: stp { - mux { - lantiq,groups = "stp"; - lantiq,function = "stp"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - }; - }; - - asc1: serial@e100c00 { - compatible = "lantiq,asc"; - reg = <0xe100c00 0x400>; - interrupt-parent = <&icu0>; - interrupts = <112 113 114>; - }; - - usb: usb@e101000 { - compatible = "lantiq,danube-usb"; - reg = <0xe101000 0x1000 - 0xe120000 0x3f000>; - interrupt-parent = <&icu0>; - interrupts = <62>; - dr_mode = "host"; - phys = <&usb_phy>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - deu@e103100 { - compatible = "lantiq,deu-danube"; - reg = <0xe103100 0xf00>; - }; - - dma0: dma@e104100 { - compatible = "lantiq,dma-xway"; - reg = <0xe104100 0x800>; - }; - - ebu0: ebu@e105300 { - compatible = "lantiq,ebu-xway"; - reg = <0xe105300 0x100>; - }; - - mei@e116000 { - compatible = "lantiq,mei-xway"; - reg = <0xe116000 0x400>; - interrupt-parent = <&icu0>; - interrupts = <63>; - }; - - gsw: etop@e180000 { - compatible = "lantiq,etop-xway"; - reg = <0xe180000 0x40000>; - interrupt-parent = <&icu0>; - interrupts = <73 78>; - mac-address = [ 00 11 22 33 44 55 ]; - }; - - ppe@e234000 { - compatible = "lantiq,ppe-danube"; - reg = <0xe234000 0x40000>; - interrupt-parent = <&icu0>; - interrupts = <96>; - }; - - pci0: pci@e105400 { - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "lantiq,pci-xway"; - bus-range = <0x0 0x0>; - ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ - 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */ - reg = <0x7000000 0x8000 /* config space */ - 0xe105400 0x400>; /* pci bridge */ - lantiq,bus-clock = <33333333>; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */ - req-mask = <0x1>; /* GNT1 */ - }; - }; - - adsl { - compatible = "lantiq,adsl-danube"; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts deleted file mode 100644 index 89a7adcd6c..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts +++ /dev/null @@ -1,214 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv4510pw", "lantiq,xway", "lantiq,danube"; - model = "Wippies, Elisa"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power2; - led-running = &power; - led-upgrade = &power; - - led-dsl = &adsl; - led-internet = &internet; - led-usb = &led_usb; - led-usb2 = &led_usb2; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - power: power { - label = "power"; - gpios = <&gpios 21 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - power2: power2 { - label = "power2"; - gpios = <&gpios 20 GPIO_ACTIVE_HIGH>; - }; - lan1 { - label = "lan1"; - gpios = <&gpios 19 GPIO_ACTIVE_HIGH>; - }; - lan2 { - label = "lan2"; - gpios = <&gpios 18 GPIO_ACTIVE_HIGH>; - }; - lan3 { - label = "lan3"; - gpios = <&gpios 17 GPIO_ACTIVE_HIGH>; - }; - lan4 { - label = "lan4"; - gpios = <&gpios 16 GPIO_ACTIVE_HIGH>; - }; - wifi: wifi { - label = "wifi"; - gpios = <&gpios 15 GPIO_ACTIVE_HIGH>; - }; - adsl: adsl { - label = "adsl"; - gpios = <&gpios 14 GPIO_ACTIVE_HIGH>; - }; - internet: internet { - label = "internet"; - gpios = <&gpios 13 GPIO_ACTIVE_HIGH>; - }; - internet2 { - label = "internet2"; - gpios = <&gpios 12 GPIO_ACTIVE_HIGH>; - }; - voip { - label = "voip"; - gpios = <&gpios 11 GPIO_ACTIVE_HIGH>; - }; - phone { - label = "phone"; - gpios = <&gpios 10 GPIO_ACTIVE_HIGH>; - }; - phone2 { - label = "phone2"; - gpios = <&gpios 9 GPIO_ACTIVE_HIGH>; - }; - led_usb: usb { - label = "usb"; - gpios = <&gpios 8 GPIO_ACTIVE_HIGH>; - }; - led_usb2: usb2 { - label = "usb2"; - gpios = <&gpios 7 GPIO_ACTIVE_HIGH>; - }; - usb3 { - label = "usb3"; - gpios = <&gpios 6 GPIO_ACTIVE_HIGH>; - }; - unlabeled { - label = "unlabeled"; - gpios = <&gpios 5 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu a23"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - exin { - lantiq,groups = "exin1", "exin2"; - lantiq,function = "exin"; - lantiq,output = <0>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - buttons { - lantiq,pins = "io3", "io14"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - }; -}; - -&gpios { - status = "okay"; - lantiq,groups = <0x7>; -}; - -&gsw { - phy-mode = "rmii"; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x1000000>; - - lantiq,noxip; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@60000 { - label = "firmware"; - reg = <0x60000 0xfa0000>; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>, - <&pci_req1_pins>, <&pci_req2_pins>; - pinctrl-names = "default"; - - lantiq,external-clock; - interrupt-map = < - 0x6000 0 0 1 &icu0 135 - 0x7800 0 0 1 &icu0 66 - 0x7800 0 0 2 &icu0 66 - 0x7800 0 0 3 &icu0 66 - >; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - req-mask = <0x7>; -}; - -&vmmc { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts deleted file mode 100644 index ff34068005..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "danube_arcadyan_arv4518pwr01.dtsi" - -/ { - compatible = "arcadyan,arv4518pwr01", "lantiq,xway", "lantiq,danube"; - model = "SMC7908A-ISP"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi deleted file mode 100644 index 39e02d072c..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi +++ /dev/null @@ -1,200 +0,0 @@ -#include "danube.dtsi" - -#include - -/ { - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - - led-dsl = &dsl; - led-internet = &online; - led-usb = &led_usb; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - ath5k_eep { - compatible = "ath5k,eeprom"; - ath,eep-flash = <&boardconfig 0x400>; - ath,mac-offset = <0x16>; - ath,mac-increment = <1>; - ath,eep-swap; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - power: power { - label = "power"; - gpios = <&gpio 3 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - dsl: dsl { - label = "dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - online: online { - label = "online"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "wifi"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - wps { - label = "wps"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - dsl2 { - label = "dsl2"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - led_usb: usb { - label = "usb"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; - voice { - label = "voice"; - gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; - }; - fxs1 { - label = "fxs1"; - gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "fxs2"; - gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; - }; - fxo { - label = "fxo"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - }; -}; - -&gsw { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; /* 64 KB */ - read-only; - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x10000 0x10000>; /* 64 KB */ - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - boardconfig: partition@400000 { - label = "boardconfig"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpio@1 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x0>; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>, - <&pci_req1_pins>, <&pci_req2_pins>; - pinctrl-names = "default"; - - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - req-mask = <0xf>; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts deleted file mode 100644 index b261a2fa91..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts +++ /dev/null @@ -1,12 +0,0 @@ -/dts-v1/; - -#include "danube_arcadyan_arv4518pwr01.dtsi" - -/ { - compatible = "arcadyan,arv4518pwr01a", "lantiq,xway", "lantiq,danube"; - model = "SMC7908A-ISP, Airties WAV-221"; -}; - -&pci0 { - lantiq,external-clock; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts deleted file mode 100644 index 5c27690691..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts +++ /dev/null @@ -1,205 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv4519pw", "lantiq,xway", "lantiq,danube"; - model = "Vodafone Netfaster IAD 2, Pirelli P.RG A4201G"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &dsl; - led-internet = &internet_green; - led-usb = &led_usb; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - power_green: power { - label = "green:power"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power2 { - label = "red:power"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "green:wlan"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - internet_green: online { - label = "green:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - online2 { - label = "red:internet"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - led_usb: usb { - label = "green:usb"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; - voip { - label = "green:voip"; - gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; - }; - fxs1 { - label = "green:phone1"; - gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "green:phone2"; - gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; - }; - fxo { - label = "green:line"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - wps2 { - label = "green:wps"; - gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; - }; - wps { - label = "orange:wps"; - gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; - }; - wps3 { - label = "red:wps"; - gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - }; -}; - -&gsw { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x10000 0x10000>; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - boardconfig: partition@3f0000 { - label = "boardconfig"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpio@1 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x400>; - }; -}; - -&pci0 { - status = "okay"; - lantiq,external-clock; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - req-mask = <0xf>; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts deleted file mode 100644 index 1686695a3a..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts +++ /dev/null @@ -1,222 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv4520pw", "lantiq,xway", "lantiq,danube"; - model = "Easybox 800, WAV-281"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_blue; - led-failsafe = &power_red; - led-running = &power_blue; - led-upgrade = &power_blue; - - led-dsl = &dsl; - led-internet = &internet_blue; - led-usb = &led_usb; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - rfkill { - label = "wps"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - power_blue: power { - label = "blue:power"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - dsl: dsl { - label = "blue:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - internet_blue: internet { - label = "blue:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - power_red: power2 { - label = "red:power"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - wps { - label = "yellow:wps"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - wps2 { - label = "red:wps"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - /* - wps green is missing - */ - fxs1 { - label = "blue:telefon1"; - gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "blue:telefon2"; - gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; - }; - isdn { - label = "blue:isdn"; - gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; - }; - fxo { - label = "blue:line"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - voice { - label = "blue:sprache"; - gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; - }; - led_usb: usb { - label = "blue:usb"; - gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "blue:wifi"; - gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; - }; - internet2 { - label = "red:internet"; - gpios = <&gpiomm 9 GPIO_ACTIVE_LOW>; - }; - /* - info is missing - */ - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 28 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; -}; - -&gsw { - /* gpiomm 10 - switch */ - phy-mode = "rmii"; - mtd-mac-address = <&boardconfig 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x20000>; - read-only; - }; - - partition@20000 { - label = "u-boot-env"; - reg = <0x20000 0x10000>; - read-only; - }; - - partition@30000 { - label = "firmware"; - reg = <0x30000 0x3c0000>; - }; - - boardconfig: partition@7f0000 { - label = "boardconfig"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpio@1 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x400>; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - lantiq,external-clock; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH - &gpiomm 7 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts deleted file mode 100644 index b0de893f3b..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts +++ /dev/null @@ -1,151 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv4525pw", "lantiq,xway", "lantiq,danube"; - model = "Speedport W501V Typ A"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - /* we dont have a power led, lets use the online led */ - led-boot = &online; - led-failsafe = &online; - - led-dsl = &dsl; - led-internet = &online; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - ath5k_eep { - compatible = "ath5k,eeprom"; - ath,eep-flash = <&boardconfig 0x400>; - ath,mac-offset = <0x0>; - ath,eep-swap; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - fxo { - label = "green:festnetz"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - fxs { - label = "green:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "green:t-dsl"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "green:wlan"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - online: online { - label = "green:online"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - relay { - lantiq,pins = "io31"; - lantiq,output = <1>; - }; - }; -}; - -/* #define ARV4525PW_PHYRESET 13 */ -&gsw { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x10000 0x10000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - boardconfig: partition@400000 { - label = "boardconfig"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; -}; - -/* #define ARV4525PW_RELAY 31 */ -&vmmc { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts deleted file mode 100644 index 23f7033a4e..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts +++ /dev/null @@ -1,240 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv452cqw", "lantiq,xway", "lantiq,danube"; - model = "Arcor 801"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_blue; - led-failsafe = &power_red; - led-running = &power_blue; - led-upgrade = &power_blue; - - led-dsl = &dsl_blue; - led-usb = &led_usb; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - ath5k_eep { - compatible = "ath5k,eeprom"; - ath,eep-flash = <&boardconfig 0x400>; - ath,mac-offset = <0x0>; - ath,eep-swap; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - power_blue: power0 { - label = "blue:power"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - dsl_blue: dsl { - label = "blue:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - isdn { - label = "blue:isdn"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - power_red: power1 { - label = "red:power"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - wps { - label = "blue:wps"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - wps1 { - label = "yellow:wps"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - fxs1 { - label = "blue:telefon1"; - gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "blue:telefon2"; - gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; - }; - wps2 { - label = "red:wps"; - gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; - }; - fxo { - label = "blue:line"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - voice { - label = "blue:sprache"; - gpios = <&gpiomm 4 1>; - }; - led_usb: usb { - label = "blue:usb"; - gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "blue:wlan"; - gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; - }; - /* - internet blue and internet red are missing - dsl2 and dsl3 are not referenced in manual - */ - dsl2 { - label = "yellow:dsl"; - gpios = <&gpiomm 8 GPIO_ACTIVE_LOW>; - }; - dsl3 { - label = "red:dsl"; - gpios = <&gpiomm 9 GPIO_ACTIVE_LOW>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 28 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - leds { - lantiq,pins = "io3", "io5", "io6", "io7", "io9"; - lantiq,output = <1>; - }; - }; -}; - -/* -#define ARV452CPW_SWITCH_RESET 110 -*/ -&gsw { - phy-mode = "rmii"; - mtd-mac-address = <&boardconfig 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x400000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x10000 0x10000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - boardconfig: partition@3f0000 { - label = "boardconfig"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpio@1 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x77f>; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - lantiq,external-clock; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH - &gpiomm 7 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts deleted file mode 100644 index 3af34d6d4e..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts +++ /dev/null @@ -1,162 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv7506pw11", "lantiq,xway", "lantiq,danube"; - model = "Alice/O2 IAD 4421"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power_red; - led-running = &power; - led-upgrade = &power; - - led-dsl = &dsl; - led-internet = &internet; - led-wifi = &wlan; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - wlan: wlan { - label = "green:wlan"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; - power: power { - label = "green:power"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - internet: internet { - label = "green:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - power_red: power_red { - label = "red:power"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - internet_red { - label = "red:internet"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - info { - label = "green:info"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - telefon { - label = "green:telefon"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - info_red { - label = "red:info"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - }; -}; - -/* GPIO 19: switch reset */ -&gsw { - phy-mode = "rmii"; - mtd-mac-address = <&boardconfig 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7a0000>; - }; - - boardconfig: partition@7f0000 { - label = "board_config"; - reg = <0x7f0000 0x10000>; - read-only; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - lantiq,external-clock; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@1814,3592 { - compatible = "pci1814,3592"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - mtd-mac-address = <&boardconfig 0x16>; - mtd-mac-address-increment = <1>; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts deleted file mode 100644 index b48559d3cd..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts +++ /dev/null @@ -1,198 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv7510pw22", "lantiq,xway", "lantiq,danube"; - model = "Astoria Networks ARV7510PW22"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - - led-dsl = &internet; - led-usb = &umts; - led-wifi = &wlan; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - restart { - label = "restart"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - power: power { - label = "power"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - internet: internet { - label = "internet"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - wlan: wlan { - label = "wlan"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; - umts: 3g { - label = "3g"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - message { - label = "message"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - pins_out { - lantiq,pins = "io2", "io4", "io8", "io9", "io10", "io15", "io20"; - lantiq,output = <1>; - }; - pins_in { - lantiq,pins = "io11", "io12", "io28"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - }; -}; - -&gsw { - /* Switch reset 19 */ - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x1000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@60000 { - label = "firmware"; - reg = <0x60000 0xf80000>; - }; - - boardconfig: partition@fe0000 { - label = "board_config"; - reg = <0xfe0000 0x20000>; - read-only; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>, <&pci_req2_pins>; - pinctrl-names = "default"; - - lantiq,external-clock; - interrupt-map = < - 0x7000 0 0 1 &icu0 30 - 0x7800 0 0 1 &icu0 135 - 0x7800 0 0 2 &icu0 135 - 0x7800 0 0 3 &icu0 135 - >; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - req-mask = <0x3>; - - wifi@1814,3592 { - compatible = "pci1814,3592"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; - gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts deleted file mode 100644 index 3e2a789192..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts +++ /dev/null @@ -1,233 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv7518pw", "lantiq,xway", "lantiq,danube"; - model = "Astoria Networks ARV7518PW"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &dsl; - led-internet = &online_green; - led-usb = &led_usb; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - power_green: power { - label = "green:power"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - online_green: online { - label = "green:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "green:wlan"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - power_red: power2 { - label = "red:power"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - online2 { - label = "red:internet"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - led_usb: usb { - label = "green:usb"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; - voice { - label = "green:voip"; - gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; - }; - fxs1 { - label = "green:phone1"; - gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "green:phone2"; - gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; - }; - unlabeled { - label = "amber:unlabeled"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - wps { - label = "amber:wps"; - gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; - }; - wps2 { - label = "green:wps"; - gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; - }; - wps3 { - label = "red:wps"; - gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - leds { - lantiq,pins = "io2", "io4", "io5", "io6", "io7", "io8", "io19"; - lantiq,output = <1>; - }; - keys { - lantiq,pins = "io28", "io30"; - lantiq,output = <0>; - lantiq,pull = <2>; - lantiq,open-drain = <1>; - }; - }; -}; - -/* -#define SWITCH_RESET 13 -*/ -&gsw { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x10000 0x10000>; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x7d0000>; - }; - - boardconfig: partition@400000 { - label = "boardconfig"; - reg = <0x7f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpio@1 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x0>; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - lantiq,external-clock; - req-mask = <0xf>; - - wifi@168c,0029 { - compatible = "pci168c,0029"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - mtd-mac-address = <&boardconfig 0x16>; - mtd-mac-address-increment = <1>; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts deleted file mode 100644 index 79019b635b..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts +++ /dev/null @@ -1,217 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv7519pw", "lantiq,xway", "lantiq,danube"; - model = "Astoria Networks ARV7519PW"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power2; - led-running = &power; - led-upgrade = &power; - - led-dsl = &dsl; - led-internet = &online; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - power: power { - label = "power"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power2: power2 { - label = "power2"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - }; - online: online { - label = "online"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - }; - online2 { - label = "online2"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "wifi"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - }; - wifi2 { - label = "wifi2"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; - wifi3 { - label = "wifi3"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - voice { - label = "voice"; - gpios = <&gpio 31 GPIO_ACTIVE_LOW>; - }; - wps { - label = "wps"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - wps2 { - label = "wps2"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - wps3 { - label = "wps3"; - gpios = <&gpio 23 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - lan { - label = "lan"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - }; - tv { - label = "tv"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - upgrade { - label = "upgrade"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - }; - }; - - /* is there another way to "reserve" the GPIO? */ - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - switch { - gpio-export,name = "switch"; - gpio-export,output = <1>; - gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - switch_rst { - lantiq,pins = "io19"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - }; -}; - -&gsw { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x20000>; - }; - - partition@60000 { - label = "firmware"; - reg = <0x60000 0xf80000>; - }; - - boardconfig: partition@fe0000 { - label = "board_config"; - reg = <0xfe0000 0x20000>; - read-only; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - lantiq,external-clock; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - req-mask = <0xf>; - - wifi@0,0 { - compatible = "pci0,0"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - }; -}; - -&usb_phy { - status = "okay"; -}; - -/* warning: passive port only works with active devices */ -&usb { - status = "okay"; -}; - -&vmmc { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts deleted file mode 100644 index a4a78f491b..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts +++ /dev/null @@ -1,149 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv7525pw", "lantiq,xway", "lantiq,danube"; - model = "Speedport W303V Typ A"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &power_green; - led-internet = &online; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - power_green: power { - label = "green:power"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power1 { - label = "red:power"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - online: online { - label = "green:online"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - voice { - label = "green:telefonie"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - voice2 { - label = "red:telefonie"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "green:wlan"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - }; -}; - -&gsw { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x10000 0x10000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - boardconfig: partition@400000 { - label = "board_config"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - interrupt-map = <0x7000 0 0 1 &icu0 135 1>; - - wifi@0,0 { - compatible = "pci0,0"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - }; -}; - -&vmmc { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts deleted file mode 100644 index e39cd4ea46..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts +++ /dev/null @@ -1,243 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv752dpw", "lantiq,xway", "lantiq,danube"; - model = "Arcor 802"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_red; - led-failsafe = &power_blue; - led-running = &power_red; - led-upgrade = &power_red; - - led-dsl = &internet_red; - led-usb = &umts; - led-wifi = &wifi; - - label-mac-device = &wifi0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - restart { - label = "restart"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - dsl { - label = "dsl"; - gpios = <&gpio 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - power_blue: power1 { - label = "blue:power"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - }; - internet_red: internet { - label = "red:internet"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - message { - label = "red:message"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - power_red: power { - label = "red:power"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - voice1 { - label = "red:voice"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - umts: umts { - label = "red:umts"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "red:wifi"; - gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; - }; - fxs1 { - label = "green:tae-n"; - gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "green:tae-u"; - gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; - }; - fxo { - label = "green:isdn"; - gpios = <&gpiomm 7 GPIO_ACTIVE_LOW>; - }; - internet2 { - label = "blue:internet"; - gpios = <&gpiomm 8 GPIO_ACTIVE_LOW>; - }; - voice2 { - label = "blue:voice"; - gpios = <&gpiomm 9 GPIO_ACTIVE_LOW>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpiomm 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - leds { - lantiq,pins = "io3", "io5", "io6", "io8"; - lantiq,output = <1>; - lantiq,pull = <0>; - }; - keys { - lantiq,pins = "io11", "io12", "io13", "io28"; - lantiq,output = <0>; - lantiq,pull = <2>; - lantiq,open-drain = <1>; - }; - }; -}; - -&gsw { - phy-mode = "rmii"; - mtd-mac-address = <&boardconfig 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x10000 0x10000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x7d0000>; - }; - - boardconfig: partition@7f0000 { - label = "board_config"; - reg = <0x7f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpio@1 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x3>; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>, <&pci_req2_pins>; - pinctrl-names = "default"; - - lantiq,external-clock; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - interrupt-map = <0x7000 0 0 1 &icu0 135>; - req-mask = <0x3>; - - wifi0: wifi@1814,0601 { - compatible = "pci1814,0601"; - reg = <0x7000 0 0 0 0>; - mtd-mac-address = <&boardconfig 0x16>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; - gpios = <&gpiomm 1 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts deleted file mode 100644 index 8ac7eea618..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts +++ /dev/null @@ -1,261 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv752dpw22", "lantiq,xway", "lantiq,danube"; - model = "Arcor 803"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_red; - led-failsafe = &power_blue; - led-running = &power_red; - led-upgrade = &power_red; - - led-dsl = &internet_red; - led-usb = &umts; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - restart { - label = "restart"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - dsl { - label = "dsl"; - gpios = <&gpio 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - power_blue: power1 { - label = "blue:power"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - }; - internet_red: internet { - label = "red:internet"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - message { - label = "red:message"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - power_red: power { - label = "red:power"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - voice1 { - label = "red:voice"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - umts: umts { - label = "red:umts"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "red:wifi"; - gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; - }; - fxs1 { - label = "green:tae-n"; - gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "green:tae-u"; - gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; - }; - fxo { - label = "green:isdn"; - gpios = <&gpiomm 7 GPIO_ACTIVE_LOW>; - }; - internet2 { - label = "blue:internet"; - gpios = <&gpiomm 8 GPIO_ACTIVE_LOW>; - }; - voice2 { - label = "blue:voice"; - gpios = <&gpiomm 9 GPIO_ACTIVE_LOW>; - }; - eth1 { - label = "green:lan1"; - gpios = <&gpiomm 11 GPIO_ACTIVE_LOW>; - }; - eth2 { - label = "green:lan2"; - gpios = <&gpiomm 12 GPIO_ACTIVE_LOW>; - }; - eth3 { - label = "green:lan3"; - gpios = <&gpiomm 13 GPIO_ACTIVE_LOW>; - }; - eth4 { - label = "green:lan4"; - gpios = <&gpiomm 14 GPIO_ACTIVE_LOW>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpiomm 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,open-drain = <1>; - lantiq,output = <1>; - }; - leds { - lantiq,pins = "io3", "io5", "io6", "io8"; - lantiq,open-drain = <1>; - lantiq,output = <1>; - }; - buttons { - lantiq,pins = "io11", "io12", "io13", "io28"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - }; -}; - -&gsw { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x30000>; - read-only; - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x40000 0x7b0000>; - }; - - boardconfig: partition@7f0000 { - label = "board_config"; - reg = <0x7f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpio@1 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <3>; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - lantiq,external-clock; - interrupt-map = < - 0x7000 0 0 1 &icu0 30 - 0x7800 0 0 1 &icu0 135 - 0x7800 0 0 2 &icu0 135 - 0x7800 0 0 3 &icu0 135 - >; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - req-mask = <0x3>; - - wifi@1814,3592 { - compatible = "pci1814,3592"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - mtd-mac-address = <&boardconfig 0x16>; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; - gpios = <&gpiomm 1 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts deleted file mode 100644 index 4c9d71fae2..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts +++ /dev/null @@ -1,181 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv8539pw22", "lantiq,xway", "lantiq,danube"; - model = "Speedport W 504V Typ A"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &dsl_green; - led-internet = &online_green; - led-wifi = &wireless_green; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - wlan { - label = "wlan"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - /* key DECT is missing */ - }; - - leds { - compatible = "gpio-leds"; - - power_green: power-green { - label = "green:power"; - gpios = <&gpio 24 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power-red { - label = "red:power"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - - dsl_green: dsl-green { - label = "green:dsl"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - - online_green: online-green { - label = "green:online"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - - wireless_green: wireless-green { - label = "green:wlan"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - /* - telefonie green is missing - */ - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - relay { - lantiq,pins = "io31"; - lantiq,output = <1>; - }; - }; -}; - -&gsw { - phy-mode = "mii"; - mtd-mac-address = <&art 0x16>; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x30000>; /* 192 KiB */ - read-only; - }; - - partition@30000 { - label = "uboot"; - reg = <0x30000 0x10000>; /* 64 KiB */ - read-only; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0x7b0000>; /* 7872 KiB */ - }; - - art: partition@7f0000 { - label = "art"; - reg = <0x7f0000 0x10000>; /* 64 KiB*/ - read-only; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@168c,0029 { - compatible = "pci168c,0029"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - mtd-mac-address = <&art 0x16>; - mtd-mac-address-increment = <1>; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts deleted file mode 100644 index f40d278411..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts +++ /dev/null @@ -1,112 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -/ { - compatible = "audiocodes,mp-252", "lantiq,xway", "lantiq,danube"; - model = "AudioCodes MediaPack MP-252"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - }; -}; - -&gsw { - phy-mode = "rmii"; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "u-boot-env"; - reg = <0x20000 0x20000>; - }; - - partition@40000 { - label = "boardconfig"; - reg = <0x40000 0x60000>; - read-only; - }; - - partition@a0000 { - label = "firmware"; - reg = <0xa0000 0xf20000>; - }; - - partition@fc0000 { - label = "sysconfig"; - reg = <0xfc0000 0x40000>; - }; - - partition@1000000 { - label = "rootfs_data"; - reg = <0x1000000 0x1000000>; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts deleted file mode 100644 index 66ff6f33d5..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts +++ /dev/null @@ -1,238 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "bt,homehub-v2b", "lantiq,xway", "lantiq,danube"; - model = "BT Home Hub 2B"; /* SoC: Lantiq Danube-S PSB 50712 @ 333MHz V1.3/1.5 */ - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_orange; - led-failsafe = &power_red; - led-running = &power_blue; - led-upgrade = &power_blue; - - led-dsl = &broadband_blue; - led-wifi = &wireless_blue; - }; - - memory@0 { /* RAM: Samsung K4H511638F-LC 64MB */ - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - findhandset { - label = "findhandset"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - upgrading-orange { - label = "orange:upgrading"; - gpios = <&gpios 5 GPIO_ACTIVE_HIGH>; - }; - - phone-orange { - label = "orange:phone"; - gpios = <&gpios 6 GPIO_ACTIVE_HIGH>; - }; - phone-blue { - label = "blue:phone"; - gpios = <&gpios 7 GPIO_ACTIVE_HIGH>; - }; - - wireless-orange { - label = "orange:wireless"; - gpios = <&gpios 8 GPIO_ACTIVE_HIGH>; - }; - wireless_blue: wireless-blue { - label = "blue:wireless"; - gpios = <&gpios 9 GPIO_ACTIVE_HIGH>; - }; - - broadband-red { - label = "red:broadband"; - gpios = <&gpios 10 GPIO_ACTIVE_HIGH>; - }; - broadband-orange { - label = "orange:broadband"; - gpios = <&gpios 11 GPIO_ACTIVE_HIGH>; - }; - broadband_blue: broadband-blue { - label = "blue:broadband"; - gpios = <&gpios 12 GPIO_ACTIVE_HIGH>; - }; - - power_red: power-red { - label = "red:power"; - gpios = <&gpios 13 GPIO_ACTIVE_HIGH>; - }; - power_orange: power-orange { - label = "orange:power"; - gpios = <&gpios 14 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - power_blue: power-blue { - label = "blue:power"; - gpios = <&gpios 15 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - - pci_rst { - lantiq,pins = "io21"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - }; - - btn_in { - lantiq,pins = "io2", "io15", "io22"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - }; -}; - -&gpios { - status = "okay"; -}; - -&gsw { - phy-mode = "rmii"; -}; - -&localbus { - flash@0 { /* NOR Flash: Spansion S29AL004D 512KB */ - compatible = "lantiq,nor"; /* "AMD AM29LV400BB" compatible on 3.3.8 */ - lantiq,cs = <0>; - bank-width = <2>; - reg = <0 0x0 0x80000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; /* 256KB */ - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x10000>; /* 64KB */ - }; - - partition@50000 { - label = "rg_conf_1"; - reg = <0x50000 0x10000>; - }; - - partition@60000 { - label = "rg_conf_2"; - reg = <0x60000 0x10000>; - }; - - partition@70000 { - label = "rg_conf_factory"; - reg = <0x70000 0x10000>; - }; - }; - }; - - flash@1 { /* NAND Flash: Samsung K9F5608U0D-JIB0 32MB */ - compatible = "lantiq,nand-xway"; - lantiq,cs = <1>; - bank-width = <2>; - reg = <1 0x0 0x2000000 >; - req-mask = <0x1>; /* PCI request lines to mask during NAND access */ - - pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; - pinctrl-names = "default"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - ath9k_cal: partition@0 { - label = "art"; /* Atheros 9160 wifi b/g/n radio EEPROM */ - reg = <0x00000 0x4000>; - read-only; - }; - - partition@4000 { - label = "kernel"; - reg = <0x4000 0x200000>; - }; - - partition@164000 { - label = "ubi"; - reg = <0x204000 0x1dfc000>; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@168c,0027 { - compatible = "pci168c,0027"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&vmmc { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts deleted file mode 100644 index cba2d7eb84..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts +++ /dev/null @@ -1,72 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -/ { - compatible = "lantiq,easy50712", "lantiq,xway", "lantiq,danube"; - model = "Intel EASY50712 Nand"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - }; -}; - -&gsw { - phy-mode = "rmii"; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; /* 64 KB */ - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x10000 0x10000>; /* 64 KB */ - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - partition@400000 { - label = "rootfs"; - reg = <0x400000 0x400000>; - }; - }; - }; -}; - -&pci0 { - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts deleted file mode 100644 index 4a023d1e3f..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts +++ /dev/null @@ -1,119 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "siemens,gigaset-sx76x", "lantiq,xway", "lantiq,danube"; - model = "Gigaset SX761,SX762,SX763"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - switch { - gpio-export,name = "switch"; - gpio-export,output = <1>; - gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpios { - status = "okay"; -}; - -&gsw { - phy-mode = "rmii"; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0x7c0000>; - }; - }; - }; - - gpiomm: gpio@1 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x3>; - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; - gpios = <&gpiomm 1 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon.dtsi deleted file mode 100644 index dada3bcff2..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon.dtsi +++ /dev/null @@ -1,366 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,falcon"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "mips,mips34kc"; - reg = <0>; - }; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - ebu_cs0: localbus@10000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,localbus", "simple-bus"; - reg = <0x10000000 0x4000000>; - ranges = <0x0 0x10000000 0x4000000>; - }; - ebu_cs1: localbus@14000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,localbus", "simple-bus"; - reg = <0x14000000 0x4000000>; - ranges = <0x0 0x14000000 0x4000000>; - }; - - ebu@18000000 { - compatible = "lantiq,ebu-falcon"; - reg = <0x18000000 0x100>; - }; - - sbs2@1d000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sysb2", "simple-bus"; - reg = <0x1d000000 0x1000000>; - ranges = <0x0 0x1d000000 0x1000000>; - - clock_sysgpe: clock-controller@700000 { - compatible = "lantiq,sysgpe-falcon"; - reg = <0x700000 0x100>; - #clock-cells = <1>; - }; - - mps@4000 { - compatible = "lantiq,mps-falcon", "lantiq,mps-xrx100"; - reg = <0x4000 0x1000>; - interrupt-parent = <&icu0>; - interrupts = <154 155>; - lantiq,mbx = <&mpsmbx>; - }; - - gpio0: gpio@810000 { - compatible = "lantiq,falcon-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&icu0>; - interrupts = <44>; - reg = <0x810000 0x80>; - clocks = <&clock_syseth 16>; - }; - - gpio2: gpio@810100 { - compatible = "lantiq,falcon-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&icu0>; - interrupts = <46>; - reg = <0x810100 0x80>; - clocks = <&clock_syseth 17>; - }; - - clock_syseth: clock-controller@b00000 { - compatible = "lantiq,syseth-falcon"; - reg = <0xb00000 0x100>; - #clock-cells = <1>; - }; - - pad@b01000 { - compatible = "lantiq,pad-falcon"; - reg = <0xb01000 0x100>; - lantiq,bank = <0>; - clocks = <&clock_syseth 20>; - }; - - pad@b02000 { - compatible = "lantiq,pad-falcon"; - reg = <0xb02000 0x100>; - lantiq,bank = <2>; - clocks = <&clock_syseth 21>; - }; - }; - - fpi@1e000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,fpi", "simple-bus"; - reg = <0x1e000000 0x1000000>; - ranges = <0x0 0x1e000000 0x1000000>; - - serial1: serial@100b00 { - status = "disabled"; - compatible = "lantiq,asc"; - reg = <0x100b00 0x100>; - interrupt-parent = <&icu0>; - interrupts = <112 113 114>; - line = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&asc1_pins>; - clocks = <&clock_sys1 11>; - }; - - serial0: serial@100c00 { - compatible = "lantiq,asc"; - reg = <0x100c00 0x100>; - interrupt-parent = <&icu0>; - interrupts = <104 105 106>; - line = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&asc0_pins>; - clocks = <&clock_sys1 12>; - }; - - spi: spi@100d00 { - status = "disabled"; - compatible = "lantiq,falcon-spi", "lantiq,xrx100-spi", "lantiq,spi-lantiq-ssc"; - interrupts = <22 23 24 25>; - interrupt-names = "spi_tx", "spi_rx", "spi_err", "spi_frm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x100d00 0x100>; - interrupt-parent = <&icu0>; - clocks = <&clock_sys1 13>; - base_cs = <1>; - num_cs = <2>; - }; - - gptc@100e00 { - compatible = "lantiq,gptc-falcon"; - reg = <0x100e00 0x100>; - }; - - i2c: i2c@200000 { - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,lantiq-i2c"; - reg = <0x200000 0x10000>; - interrupt-parent = <&icu0>; - interrupts = <18 19 20 21>; - gpios = <&gpio1 7 0 &gpio1 8 0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - clocks = <&clock_sys1 14>; - }; - - gpio1: gpio@800100 { - compatible = "lantiq,falcon-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&icu0>; - interrupts = <45>; - reg = <0x800100 0x100>; - clocks = <&clock_sys1 16>; - }; - - gpio3: gpio@800200 { - compatible = "lantiq,falcon-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&icu0>; - interrupts = <47>; - reg = <0x800200 0x100>; - clocks = <&clock_sys1 17>; - }; - - gpio4: gpio@800300 { - compatible = "lantiq,falcon-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&icu0>; - interrupts = <48>; - reg = <0x800300 0x100>; - clocks = <&clock_sys1 18>; - }; - - pad@800400 { - compatible = "lantiq,pad-falcon"; - reg = <0x800400 0x100>; - lantiq,bank = <1>; - clocks = <&clock_sys1 20>; - }; - - pad@800500 { - compatible = "lantiq,pad-falcon"; - reg = <0x800500 0x100>; - lantiq,bank = <3>; - clocks = <&clock_sys1 21>; - }; - - pad@800600 { - compatible = "lantiq,pad-falcon"; - reg = <0x800600 0x100>; - lantiq,bank = <4>; - clocks = <&clock_sys1 22>; - }; - - status@802000 { - compatible = "lantiq,status-falcon"; - reg = <0x802000 0x80>; - }; - - clock_sys1: clock-controller@f00000 { - compatible = "lantiq,sys1-falcon"; - reg = <0xf00000 0x100>; - #clock-cells = <1>; - }; - }; - - sbs0@1f000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - reg = <0x1f000000 0x400000>; - ranges = <0x0 0x1f000000 0x400000>; - - mpsmbx: mpsmbx@200000 { - reg = <0x200000 0x200>; - }; - }; - - biu@1f800000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,biu", "simple-bus"; - reg = <0x1f800000 0x800000>; - ranges = <0x0 0x1f800000 0x800000>; - - icu0: icu@80200 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,icu"; - reg = <0x80200 0x28 - 0x80228 0x28 - 0x80250 0x28 - 0x80278 0x28 - 0x802a0 0x28>; - }; - - watchdog@803f0 { - compatible = "lantiq,wdt"; - reg = <0x803f0 0x10>; - }; - }; - - pinctrl { - compatible = "lantiq,pinctrl-falcon"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - /*ntr { - lantiq,groups = "ntr8k"; - lantiq,function = "ntr"; - };*/ - hrst { - lantiq,groups = "hrst"; - lantiq,function = "rst"; - }; - }; - - asc0_pins: asc0 { - asc0 { - lantiq,groups = "asc0"; - lantiq,function = "asc"; - }; - }; - asc1_pins: asc1 { - asc1 { - lantiq,groups = "asc1"; - lantiq,function = "asc"; - }; - }; - i2c_pins: i2c_pins { - i2c_pins { - lantiq,groups = "i2c"; - lantiq,function = "i2c"; - }; - }; - bootled_pins: bootled { - bootled { - lantiq,groups = "bootled"; - lantiq,function = "led"; - }; - }; - ntr_ntr8k: ntr8k { - ntr8k { - lantiq,groups = "ntr8k"; - lantiq,function = "ntr"; - }; - }; - ntr_pps: pps { - pps { - lantiq,groups = "pps"; - lantiq,function = "ntr"; - }; - }; - ntr_gpio: gpio { - gpio { - lantiq,pins = "io5"; - lantiq,mux = <1>; - lantiq,output = <0>; - }; - }; - slic_pins: slic { - slic { - lantiq,groups = "slic"; - lantiq,function = "slic"; - }; - }; - }; - - pinselect-ntr { - compatible = "lantiq,onu-ntr","lantiq,pinselect-ntr"; - pinctrl-names = "ntr8k", "pps", "gpio"; - pinctrl-0 = <&ntr_ntr8k>; - pinctrl-1 = <&ntr_pps>; - pinctrl-2 = <&ntr_gpio>; - }; - - pinselect-asc1 { - compatible = "lantiq,onu-asc1","lantiq,pinselect-asc1"; - pinctrl-names = "default", "asc1"; - pinctrl-0 = <&slic_pins>; - pinctrl-1 = <&asc1_pins>; - }; - -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts deleted file mode 100644 index 1661480af4..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts +++ /dev/null @@ -1,93 +0,0 @@ -/dts-v1/; - -#include -#include "falcon.dtsi" -#include "falcon_sflash-16m.dtsi" - -/ { - model = "Lantiq Falcon FTTDP8 Reference Board"; - compatible = "lantiq,easy88388", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - keys { - compatible = "gpio-keys"; - reset { - label = "reset"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - linux,code = <0x198>; - }; - }; - - pinctrl { - led_pins: led-pins { - lantiq,pins = "io34", "io35", "io36", "io37", "io38", - "io39", "io40", "io41"; - lantiq,function = "gpio"; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &bootled_pins>; - - GPON { - label = "green:gpon"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - }; - TEST { - label = "green:test"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - STATUS { - label = "green:status"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - ERROR { - label = "red:error"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - - DSL1 { - label = "dsl:1"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - DSL2 { - label = "dsl:2"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - DSL3 { - label = "dsl:3"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - DSL4 { - label = "dsl:4"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - DSL5 { - label = "dsl:5"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - DSL6 { - label = "dsl:6"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - DSL7 { - label = "dsl:7"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - DSL8 { - label = "dsl:8"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - }; -}; - diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts deleted file mode 100644 index 234c7f005e..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts +++ /dev/null @@ -1,72 +0,0 @@ -/dts-v1/; - -#include -#include "falcon.dtsi" -#include "falcon_sflash-16m.dtsi" - -/ { - model = "Lantiq Falcon FTTdp G.FAST Reference Board"; - compatible = "lantiq,easy88444", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - keys { - compatible = "gpio-keys"; - reset { - label = "reset"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - linux,code = <0x198>; - }; - }; - - pinctrl { - led_pins: led-pins { - lantiq,pins = "io34", "io35", "io37"; - lantiq,function = "gpio"; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &bootled_pins>; - - GPON { - label = "green:gpon"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - }; - TEST { - label = "green:test"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - STATUS { - label = "green:status"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - GFAST1 { - label = "gfast:1"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - GFAST2 { - label = "gfast:2"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - GFAST3 { - label = "gfast:3"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - GFAST4 { - label = "gfast:4"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - }; -}; - diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts deleted file mode 100644 index d2f5c8c16a..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts +++ /dev/null @@ -1,39 +0,0 @@ -/dts-v1/; - -#include "falcon_lantiq_easy98000.dtsi" - -/ { - model = "Lantiq Falcon (NAND)"; - compatible = "lantiq,easy98000-nand", "lantiq,easy98000", "lantiq,falcon"; - - aliases { - spi0 = &spi; - }; -}; - -&ebu_cs0 { - flash@0 { - compatible = "gen_nand", "lantiq,nand-falcon"; - bank-width = <1>; - reg = <0x0 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - linux,mtd-name = "gen_nand"; - bbt-use-flash; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x40000 0x40000>; - }; - - partition@20000 { - label = "linux"; - reg = <0x80000 0x3d0000>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts deleted file mode 100644 index 5e4084f24e..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts +++ /dev/null @@ -1,41 +0,0 @@ -/dts-v1/; - -#include "falcon_lantiq_easy98000.dtsi" - -/ { - model = "Lantiq Falcon (NOR)"; - compatible = "lantiq,easy98000-nor", "lantiq,easy98000", "lantiq,falcon"; - - aliases { - spi0 = &spi; - }; -}; - -&ebu_cs0 { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0x0 0x4000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x40000 0x40000>; - }; - - partition@20000 { - label = "linux"; - reg = <0x80000 0x3d0000>; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts deleted file mode 100644 index 8c931746ed..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; - -#include "falcon_lantiq_easy98000.dtsi" -#include "falcon_sflash-16m.dtsi" - -/ { - model = "Lantiq Falcon (SFLASH)"; - compatible = "lantiq,easy98000-sflash", "lantiq,easy98000", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - spi1 = &spi; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi deleted file mode 100644 index 6d5d3cb8d1..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi +++ /dev/null @@ -1,110 +0,0 @@ -#include -#include - -#include "falcon.dtsi" - -/ { - compatible = "lantiq,easy98000", "lantiq,falcon"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&bootled_pins>; - - LED_0 { - label = "green:gpon"; - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_1 { - label = "red:gpon"; - gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_2 { - label = "green:gpon_tx"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_3 { - label = "green:gpon_rx"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_4 { - label = "green:voice"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_5 { - label = "green:status"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; -}; - -&ebu_cs1 { - eth0: ethernet@3 { - compatible = "davicom,dm9000"; - device_type = "network"; - reg = <0x0000003 0x1>, <0x0000001 0x1>; - reg-names = "addr", "data"; - interrupt-parent = <&gpio1>; - #interrupt-cells = <2>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - - cpld@3c00000 { - compatible = "lantiq,easy98000_addon"; - reg = <0x3c00000 0x2>; - }; - - cpld@3c0000c { - compatible = "lantiq,easy98000_cpld_led"; - reg = <0x3c0000c 0x2>, <0x3c00012 0x2>; - }; -}; - -/* // enable this for second uart: -&serial1 { - status = "okay"; -};*/ - -&spi { - status = "okay"; - - eeprom@2 { - compatible = "atmel,at25", "atmel,at25160n"; - reg = <2>; - spi-max-frequency = <1000000>; - spi-cpha; - spi-cpol; - - pagesize = <32>; - size = <2048>; - address-width = <16>; - }; -}; - -&i2c { - status = "okay"; - - clock-frequency = <100000>; - - /* eeprom-emulation by OMU */ - eeprom@50 { - compatible = "at,24c02"; - reg = <0x50>; - }; - eeprom@51 { - compatible = "at,24c02"; - reg = <0x51>; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts deleted file mode 100644 index eb16cd0b88..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts +++ /dev/null @@ -1,68 +0,0 @@ -/dts-v1/; - -#include - -#include "falcon.dtsi" -#include "falcon_sflash-16m.dtsi" - -/ { - model = "Lantiq Falcon Reference Board V1.8"; - compatible = "lantiq,easy98020-v18", "lantiq,easy98020", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - keys { - compatible = "gpio-keys"; - reset { - label = "reset"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - linux,code = <0x198>; - }; - }; - - pinctrl { - led_pins: led-pins { - lantiq,pins = "io11", "io14", "io36", "io37", "io38"; - lantiq,function = "gpio"; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &bootled_pins>; - - GPON { - label = "green:gpon"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - TEST { - label = "green:test"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - ETH { - label = "green:status"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - VOICE { - label = "green:voice"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - VIDEO { - label = "green:video"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts deleted file mode 100644 index abbb871642..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts +++ /dev/null @@ -1,85 +0,0 @@ -/dts-v1/; - -#include - -#include "falcon.dtsi" -#include "falcon_sflash-16m.dtsi" - -/ { - model = "Lantiq Falcon Reference Board"; - compatible = "lantiq,easy98020", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - keys { - compatible = "gpio-keys"; - reset { - label = "reset"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - linux,code = <0x198>; - }; - }; - - pinctrl { - led_pins: phy-led-pins { - lantiq,pins = "io42", "io41", "io38", "io37"; - lantiq,function = "gpio"; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&bootled_pins>, <&led_pins>; - - GPON { - label = "green:gpon"; - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - TEST { - label = "green:test"; - gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - ETH { - label = "green:status"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - VOICE { - label = "green:voice"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - VIDEO { - label = "green:video"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - GE0_ACT { - label = "ge0_act"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - GE0_LINK { - label = "ge0_link"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - GE1_ACT { - label = "ge1_act"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - GE1_LINK { - label = "ge1_link"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts deleted file mode 100644 index 3f3cb1e2fe..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts +++ /dev/null @@ -1,81 +0,0 @@ -/dts-v1/; - -#include - -#include "falcon.dtsi" -#include "falcon_sflash-16m.dtsi" - -/ { - model = "Lantiq Falcon HGU Reference Board"; - compatible = "lantiq,easy98021", "lantiq,easy98020", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - keys { - compatible = "gpio-keys"; - reset { - label = "reset"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - linux,code = <0x198>; - }; - }; - - gpio-mmc { - /* Place-holder for SIM-Card connector, - to list the used GPIOs, no official binding */ - compatible = "gpio-mmc"; - gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>, - <&gpio0 3 GPIO_ACTIVE_HIGH>, - <&gpio0 2 GPIO_ACTIVE_HIGH>, - <0>; /* no CS */ - gpio-names = "di", "do", "clk", "cs"; - reset-gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; - }; - - pinctrl { - led_pins: led-pins { - lantiq,pins = "io11", "io14", "io36", "io37", "io38"; - lantiq,function = "gpio"; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &bootled_pins>; - - GPON { - label = "green:gpon"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - TEST { - label = "red:test"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - ETH { - label = "green:status"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - VOICE { - label = "green:voice"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - SIMCARD { - label = "green:simcard"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; -}; - diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts deleted file mode 100644 index f1ecebec3b..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts +++ /dev/null @@ -1,76 +0,0 @@ -/dts-v1/; - -#include "falcon.dtsi" -#include "falcon_sflash-16m.dtsi" - -/ { - model = "Lantiq Falcon SFP Stick with SyncE"; - compatible = "lantiq,easy98035synce", "lantiq,falcon-sfp", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - pinctrl { - compatible = "lantiq,pinctrl-falcon"; - - asc0_func1: func1 { - func1_tx { - lantiq,pins = "io32"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - func1_rx { - lantiq,pins = "io33"; - lantiq,mux = <0>; - }; - }; - asc0_func2: func2 { - func2_tx { - lantiq,pins = "io32"; - lantiq,mux = <0>; - }; - func2_rx { - lantiq,pins = "io33"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - }; - asc0_func3: func3 { - func3_tx { - lantiq,pins = "io32"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - func3_rx { - lantiq,pins = "io33"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - }; - }; - - pinselect-asc0 { - compatible = "lantiq,pinselect-asc0"; - pinctrl-names = "asc0", "func1", "func2", "func3"; - pinctrl-0 = <&asc0_pins>; - pinctrl-1 = <&asc0_func1>; - pinctrl-2 = <&asc0_func2>; - pinctrl-3 = <&asc0_func3>; - }; -}; - -&serial0 { - pinctrl-names = "default"; - /* use "empty" pinctrl to leave setting from u-boot enabled */ - pinctrl-0 = < >; -}; - -&i2c { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts deleted file mode 100644 index 98421174d3..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts +++ /dev/null @@ -1,76 +0,0 @@ -/dts-v1/; - -#include "falcon.dtsi" -#include "falcon_sflash-16m.dtsi" - -/ { - model = "Lantiq Falcon SFP Stick with SyncE/1588"; - compatible = "lantiq,easy98035synce1588", "lantiq,falcon-sfp", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - pinctrl { - compatible = "lantiq,pinctrl-falcon"; - - asc0_func1: func1 { - func1_tx { - lantiq,pins = "io32"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - func1_rx { - lantiq,pins = "io33"; - lantiq,mux = <0>; - }; - }; - asc0_func2: func2 { - func2_tx { - lantiq,pins = "io32"; - lantiq,mux = <0>; - }; - func2_rx { - lantiq,pins = "io33"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - }; - asc0_func3: func3 { - func3_tx { - lantiq,pins = "io32"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - func3_rx { - lantiq,pins = "io33"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - }; - }; - - pinselect-asc0 { - compatible = "lantiq,pinselect-asc0"; - pinctrl-names = "asc0", "func1", "func2", "func3"; - pinctrl-0 = <&asc0_pins>; - pinctrl-1 = <&asc0_func1>; - pinctrl-2 = <&asc0_func2>; - pinctrl-3 = <&asc0_func3>; - }; -}; - -&serial0 { - pinctrl-names = "default"; - /* use "empty" pinctrl to leave setting from u-boot enabled */ - pinctrl-0 = < >; -}; - -&i2c { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts deleted file mode 100644 index 12c178ebd9..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts +++ /dev/null @@ -1,53 +0,0 @@ -/dts-v1/; - -#include - -#include "falcon.dtsi" -#include "falcon_sflash-16m.dtsi" - -/ { - model = "Lantiq Falcon / Vinax MDU Board"; - compatible = "lantiq,falcon-mdu", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&bootled_pins>; - - LED_0 { - label = "green:gpon"; - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_1 { - label = "green:status"; - gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_2 { - label = "green:2"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_3 { - label = "green:3"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_4 { - label = "green:4"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; -}; - diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts deleted file mode 100644 index 880c4edca8..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts +++ /dev/null @@ -1,76 +0,0 @@ -/dts-v1/; - -#include "falcon.dtsi" -#include "falcon_sflash-16m.dtsi" - -/ { - model = "Lantiq Falcon SFP Stick"; - compatible = "lantiq,falcon-sfp", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - pinctrl { - compatible = "lantiq,pinctrl-falcon"; - - asc0_func1: func1 { - func1_tx { - lantiq,pins = "io32"; - lantiq,mux = <1>; - lantiq,output = <0>; - }; - func1_rx { - lantiq,pins = "io33"; - lantiq,mux = <0>; - }; - }; - asc0_func2: func2 { - func2_tx { - lantiq,pins = "io32"; - lantiq,mux = <0>; - }; - func2_rx { - lantiq,pins = "io33"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - }; - asc0_func3: func3 { - func3_tx { - lantiq,pins = "io32"; - lantiq,mux = <1>; - lantiq,output = <0>; - }; - func3_rx { - lantiq,pins = "io33"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - }; - }; - - pinselect-asc0 { - compatible = "lantiq,pinselect-asc0"; - pinctrl-names = "asc0", "func1", "func2", "func3"; - pinctrl-0 = <&asc0_pins>; - pinctrl-1 = <&asc0_func1>; - pinctrl-2 = <&asc0_func2>; - pinctrl-3 = <&asc0_func3>; - }; -}; - -&serial0 { - pinctrl-names = "default"; - /* use "empty" pinctrl to leave setting from u-boot enabled */ - pinctrl-0 = < >; -}; - -&i2c { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_sflash-16m.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_sflash-16m.dtsi deleted file mode 100644 index f741ea2b7b..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_sflash-16m.dtsi +++ /dev/null @@ -1,41 +0,0 @@ - -&ebu_cs0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sflash-falcon", "simple-bus"; - - flash@0 { - compatible = "spansion,s25fl129p0", "spansion,s25fl129p1"; - reg = <0 0>; - linux,mtd-name = "sflash"; - spi-max-frequency = <80000000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x40000>; - label = "uboot"; - read-only; - }; - - partition@40000 { - reg = <0x40000 0x80000>; - label = "u-boot-env"; - }; - - partition@c0000 { - reg = <0xc0000 0x740000>; - label = "image0"; - }; - - partition@800000 { - reg = <0x800000 0x800000>; - label = "image1"; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9.dtsi deleted file mode 100644 index 35b1f180a5..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9.dtsi +++ /dev/null @@ -1,495 +0,0 @@ -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,xway", "lantiq,vr9"; - - aliases { - serial0 = &asc1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "mips,mips34Kc"; - reg = <0>; - }; - }; - - cputemp { - compatible = "lantiq,cputemp"; - }; - - reboot { - compatible = "syscon-reboot"; - - regmap = <&rcu0>; - offset = <0x10>; - mask = <0xe0000000>; - }; - - biu@1f800000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,biu", "simple-bus"; - reg = <0x1f800000 0x800000>; - ranges = <0x0 0x1f800000 0x7fffff>; - - icu0: icu@80200 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,icu"; - reg = <0x80200 0x28 - 0x80228 0x28 - 0x80250 0x28 - 0x80278 0x28 - 0x802a0 0x28>; - }; - - watchdog@803f0 { - compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt"; - reg = <0x803f0 0x10>; - - regmap = <&rcu0>; - }; - }; - - sram@1f000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sram", "simple-bus"; - reg = <0x1f000000 0x800000>; - ranges = <0x0 0x1f000000 0x7fffff>; - - eiu0: eiu@101000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,eiu-xway"; - reg = <0x101000 0x1000>; - interrupt-parent = <&icu0>; - lantiq,eiu-irqs = <166 135 66 40 41 42>; - }; - - pmu0: pmu@102000 { - compatible = "lantiq,pmu-xway"; - reg = <0x102000 0x1000>; - }; - - cgu0: cgu@103000 { - compatible = "lantiq,cgu-xway"; - reg = <0x103000 0x1000>; - }; - - dcdc@106a00 { - compatible = "lantiq,dcdc-xrx200"; - reg = <0x106a00 0x200>; - }; - - vmmc: vmmc@107000 { - status = "disabled"; - compatible = "lantiq,vmmc-xway"; - reg = <0x107000 0x300>; - interrupt-parent = <&icu0>; - interrupts = <150 151 152 153 154 155>; - }; - - rcu0: rcu@203000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon"; - reg = <0x203000 0x100>; - ranges = <0x0 0x203000 0x100>; - big-endian; - - gphy0: gphy@20 { - compatible = "lantiq,xrx200-gphy"; - reg = <0x20 0x4>; - - resets = <&reset0 31 30>, <&reset1 7 7>; - reset-names = "gphy", "gphy2"; - }; - - gphy1: gphy@68 { - compatible = "lantiq,xrx200-gphy"; - reg = <0x68 0x4>; - - resets = <&reset0 29 28>, <&reset1 6 6>; - reset-names = "gphy", "gphy2"; - }; - - reset0: reset-controller@10 { - compatible = "lantiq,xrx200-reset"; - reg = <0x10 4>, <0x14 4>; - - #reset-cells = <2>; - }; - - reset1: reset-controller@48 { - compatible = "lantiq,xrx200-reset"; - reg = <0x48 4>, <0x24 4>; - - #reset-cells = <2>; - }; - - usb_phy0: usb2-phy@18 { - compatible = "lantiq,xrx200-usb2-phy"; - reg = <0x18 4>, <0x38 4>; - status = "disabled"; - - resets = <&reset1 4 4>, <&reset0 4 4>; - reset-names = "phy", "ctrl"; - #phy-cells = <0>; - }; - - usb_phy1: usb2-phy@34 { - compatible = "lantiq,xrx200-usb2-phy"; - reg = <0x34 4>, <0x3c 4>; - status = "disabled"; - - resets = <&reset1 5 5>, <&reset0 4 4>; - reset-names = "phy", "ctrl"; - #phy-cells = <0>; - }; - }; - }; - - fpi@10000000 { - compatible = "lantiq,xrx200-fpi", "simple-bus"; - ranges = <0x0 0x10000000 0xf000000>; - reg = <0x1f400000 0x1000>, - <0x10000000 0xf000000>; - regmap = <&rcu0>; - offset-endianness = <0x4c>; - #address-cells = <1>; - #size-cells = <1>; - - localbus: localbus@0 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ - 1 0 0x4000000 0x4000010>; /* addsel1 */ - compatible = "lantiq,localbus", "simple-bus"; - }; - - gptu@e100a00 { - compatible = "lantiq,gptu-xway"; - reg = <0xe100a00 0x100>; - interrupt-parent = <&icu0>; - interrupts = <126 127 128 129 130 131>; - }; - - usif: usif@da00000 { - compatible = "lantiq,usif"; - reg = <0xda00000 0x1000000>; - interrupt-parent = <&icu0>; - interrupts = <29 125 107 108 109 110>; - status = "disabled"; - }; - - spi: spi@e100800 { - compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi"; - reg = <0xe100800 0x100>; - interrupt-parent = <&icu0>; - interrupts = <22 23 24>; - interrupt-names = "spi_rx", "spi_tx", "spi_err", - "spi_frm"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>; - status = "disabled"; - }; - - gpio: pinmux@e100b10 { - compatible = "lantiq,xrx200-pinctrl"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xe100b10 0xa0>; - - gphy0_led0_pins: gphy0-led0 { - mux { - lantiq,groups = "gphy0 led0"; - lantiq,function = "gphy"; - lantiq,open-drain = <0>; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - }; - - gphy0_led1_pins: gphy0-led1 { - mux { - lantiq,groups = "gphy0 led1"; - lantiq,function = "gphy"; - lantiq,open-drain = <0>; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - }; - - gphy0_led2_pins: gphy0-led2 { - mux { - lantiq,groups = "gphy0 led2"; - lantiq,function = "gphy"; - lantiq,open-drain = <0>; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - }; - - gphy1_led0_pins: gphy1-led0 { - mux { - lantiq,groups = "gphy1 led0"; - lantiq,function = "gphy"; - lantiq,open-drain = <0>; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - }; - - gphy1_led1_pins: gphy1-led1 { - mux { - lantiq,groups = "gphy1 led1"; - lantiq,function = "gphy"; - lantiq,open-drain = <0>; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - }; - - gphy1_led2_pins: gphy1-led2 { - mux { - lantiq,groups = "gphy1 led2"; - lantiq,function = "gphy"; - lantiq,open-drain = <0>; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - }; - - mdio_pins: mdio { - mux { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - }; - - nand_pins: nand { - mux-0 { - lantiq,groups = "nand cle", "nand ale", - "nand rd"; - lantiq,function = "ebu"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - mux-1 { - lantiq,groups = "nand rdy"; - lantiq,function = "ebu"; - lantiq,output = <0>; - lantiq,pull = <2>; - }; - }; - - nand_cs1_pins: nand-cs1 { - mux { - lantiq,groups = "nand cs1"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - - pci_gnt1_pins: pci-gnt1 { - mux { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - - pci_req1_pins: pci-req1 { - mux { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - }; - - spi_pins: spi { - mux-0 { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - mux-1 { - lantiq,groups = "spi_do", "spi_clk"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - - spi_cs4_pins: spi-cs4 { - mux { - lantiq,groups = "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - - stp_pins: stp { - mux { - lantiq,groups = "stp"; - lantiq,function = "stp"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - }; - }; - - stp: stp@e100bb0 { - status = "disabled"; - compatible = "lantiq,gpio-stp-xway"; - reg = <0xe100bb0 0x40>; - #gpio-cells = <2>; - gpio-controller; - - pinctrl-0 = <&stp_pins>; - pinctrl-names = "default"; - - lantiq,shadow = <0xffffff>; - lantiq,groups = <0x7>; - lantiq,dsl = <0x0>; - lantiq,phy1 = <0x0>; - lantiq,phy2 = <0x0>; - }; - - asc1: serial@e100c00 { - compatible = "lantiq,asc"; - reg = <0xe100c00 0x400>; - interrupt-parent = <&icu0>; - interrupts = <112 113 114>; - }; - - deu@e103100 { - compatible = "lantiq,deu-xrx200"; - reg = <0xe103100 0xf00>; - }; - - dma0: dma@e104100 { - compatible = "lantiq,dma-xway"; - reg = <0xe104100 0x800>; - }; - - ebu0: ebu@e105300 { - compatible = "lantiq,ebu-xway"; - reg = <0xe105300 0x100>; - }; - - usb0: usb@e101000 { - status = "disabled"; - compatible = "lantiq,xrx200-usb"; - reg = <0xe101000 0x1000 - 0xe120000 0x3f000>; - interrupt-parent = <&icu0>; - interrupts = <62 91>; - dr_mode = "host"; - phys = <&usb_phy0>; - phy-names = "usb2-phy"; - }; - - usb1: usb@e106000 { - status = "disabled"; - compatible = "lantiq,xrx200-usb"; - reg = <0xe106000 0x1000>; - interrupt-parent = <&icu0>; - interrupts = <91>; - dr_mode = "host"; - phys = <&usb_phy1>; - phy-names = "usb2-phy"; - }; - - eth0: eth@e108000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-net"; - reg = < 0xe108000 0x3000 /* switch */ - 0xe10b100 0x70 /* mdio */ - 0xe10b1d8 0x30 /* mii */ - 0xe10b308 0x30 /* pmac */ - >; - interrupt-parent = <&icu0>; - interrupts = <75 73 72>; - resets = <&reset0 21 16>, <&reset0 8 8>; - reset-names = "switch", "ppe"; - lantiq,phys = <&gphy0>, <&gphy1>; - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - }; - - mei@e116000 { - compatible = "lantiq,mei-xrx200"; - reg = <0xe116000 0x9c>; - interrupt-parent = <&icu0>; - interrupts = <63>; - }; - - ppe@e234000 { - compatible = "lantiq,ppe-xrx200"; - reg = <0xe234000 0x3ffd>; - interrupt-parent = <&icu0>; - interrupts = <96>; - resets = <&reset0 3 3>, <&reset0 11 11>, <&reset0 23 23>; - reset-names = "dsp", "dfe", "tc"; - }; - - pcie0: pcie@d900000 { - compatible = "lantiq,pcie-xrx200"; - - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - - reg = <0xd900000 0x1000>; - - interrupt-parent = <&icu0>; - interrupts = <161 144>; - - device_type = "pci"; - - gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>; - }; - - pci0: pci@e105400 { - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "lantiq,pci-xway"; - bus-range = <0x0 0x0>; - ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ - 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */ - reg = <0x7000000 0x8000 /* config space */ - 0xe105400 0x400>; /* pci bridge */ - lantiq,bus-clock = <33333333>; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */ - req-mask = <0x1>; /* GNT1 */ - }; - }; - - vdsl { - compatible = "lantiq,vdsl-vrx200"; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts deleted file mode 100644 index 5418ac675d..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts +++ /dev/null @@ -1,155 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "alphanetworks,asl56026", "lantiq,xway", "lantiq,vr9"; - model = "BT OpenReach VDSL Modem"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &dsl; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 40 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - - /* power-* is a bicolour led */ - power_green: power_green { - label = "green:power"; - gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - power_red: power_red { - label = "red:power"; - gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - power_led_blink { - gpio-export,name = "power_led_blink"; - gpio-export,output = <0>; - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - lantiq,switch; - - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "mii"; - phy-handle = <&phy11>; - }; - - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <3>; - phy-mode = "mii"; - phy-handle = <&phy14>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - - phy14: ethernet-phy@14 { - reg = <0x14>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x0800000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0x750000>; - }; - - partition@790000 { - label = "ddrconfig"; - reg = <0x790000 0x70000>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts deleted file mode 100644 index 2b3d38fd8b..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts +++ /dev/null @@ -1,246 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "arcadyan,arv7519rw22", "lantiq,xway", "lantiq,vr9"; - model = "Orange Livebox 2.1"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_green; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &internet_green; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - rfkill { - label = "rfkill"; - gpios = <&gpio 33 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - lan_green { - label = "green:lan"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; - internet_red { - label = "red:internet"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; - power_green: power_green { - label = "green:power"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - alarm_blue { - label = "blue:alarm"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - internet_orange { - label = "orange:internet"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; - internet_green: internet_green { - label = "green:internet"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - }; - voice_green { - label = "green:voice"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 32 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&boardconfig 0x16>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "mii"; - phy-handle = <&phy13>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "mii"; - phy-handle = <&phy14>; - }; - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "mii"; - phy-handle = <&phy11>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <3>; - phy-mode = "mii"; - phy-handle = <&phy12>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy12: ethernet-phy@12 { - reg = <0x12>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy14: ethernet-phy@14 { - reg = <0x14>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pcie-rst { - lantiq,pins = "io21"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x60000>; - read-only; - }; - - partition@60000 { - label = "u-boot-env"; - reg = <0x60000 0x20000>; - read-only; - }; - - partition@80000 { - label = "firmware"; - reg = <0x80000 0x1f00000>; - }; - - boardconfig: partition@1f80000 { - label = "boardconfig"; - reg = <0x1f80000 0x80000>; - read-only; - }; - }; - }; -}; - -&pcie0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_phy1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&usb1 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts deleted file mode 100644 index a579d98bf2..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts +++ /dev/null @@ -1,144 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "arcadyan,vg3503j", "lantiq,xway", "lantiq,vr9"; - model = "BT OpenReach VDSL Modem"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &dsl; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - power_red: power2 { - label = "red:power"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; - power_green: power { - label = "green:power"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; -}; - -ð0 { - pinctrl-0 = <&mdio_pins>, - <&gphy0_led0_pins>, <&gphy0_led1_pins>, <&gphy0_led2_pins>, - <&gphy1_led0_pins>, <&gphy1_led1_pins>, <&gphy1_led2_pins>; - - interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - lantiq,switch; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "mii"; - phy-handle = <&phy11>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "mii"; - phy-handle = <&phy13>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - lantiq,led1h = <0x70>; - lantiq,led1l = <0x00>; - lantiq,led2h = <0x00>; - lantiq,led2l = <0x03>; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - lantiq,led1h = <0x70>; - lantiq,led1l = <0x00>; - lantiq,led2h = <0x00>; - lantiq,led2l = <0x03>; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x20000>; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x7d0000>; - }; - - partition@7f0000 { - label = "u-boot-env"; - reg = <0x7f0000 0x10000>; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts deleted file mode 100644 index 9f6f405a09..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts +++ /dev/null @@ -1,65 +0,0 @@ -/dts-v1/; - -#include "vr9_arcadyan_vgv7510kw22.dtsi" - -/ { - compatible = "arcadyan,vgv7510kw22-brn", "arcadyan,vgv7510kw22", "lantiq,xway", "lantiq,vr9"; - model = "o2 Box 6431"; - - sram@1f000000 { - cgu@103000 { - lantiq,phy-clk-src = <0x2>; - }; - }; -}; - -&localbus { - flash@0 { - partitions { - partition@0 { - label = "Boot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "Configuration"; - reg = <0x40000 0x40000>; - read-only; - }; - - partition@80000 { - label = "Certificate"; - reg = <0x80000 0x20000>; - read-only; - }; - - partition@a0000 { - label = "Special_Area"; - reg = <0xa0000 0x20000>; - read-only; - }; - - partition@c0000 { - compatible = "brnboot,root-selector"; - label = "Primary_Setting"; - reg = <0xc0000 0x20000>; - read-only; - }; - - partition@e0000 { - label = "Code_Image_0"; - reg = <0xe0000 0x780000>; - brnboot,root-id = <0x00>; - read-only; - }; - - partition@860000 { - label = "Code_Image_1"; - reg = <0x860000 0x780000>; - brnboot,root-id = <0x01>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts deleted file mode 100644 index bbe3b0ed47..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts +++ /dev/null @@ -1,31 +0,0 @@ -/dts-v1/; - -#include "vr9_arcadyan_vgv7510kw22.dtsi" - -/ { - compatible = "arcadyan,vgv7510kw22-nor", "arcadyan,vgv7510kw22", "lantiq,xway", "lantiq,vr9"; - model = "o2 Box 6431"; -}; - -&localbus { - flash@0 { - partitions { - partition@0 { - label = "uboot"; - reg = <0x0 0x60000>; /* 384 KiB */ - read-only; - }; - - partition@60000 { - label = "u-boot-env"; - reg = <0x60000 0x20000>; /* 128 KiB */ - read-only; - }; - - partition@80000 { - label = "firmware"; - reg = <0x80000 0xf60000>; /* 15744 KiB */ - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts deleted file mode 100644 index 051de0c23e..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts +++ /dev/null @@ -1,70 +0,0 @@ -/dts-v1/; - -#include "vr9_arcadyan_vgv7519.dtsi" - -/ { - compatible = "arcadyan,vgv7519-brn", "arcadyan,vgv7519", "lantiq,xway", "lantiq,vr9"; - model = "KPN Experiabox V8"; -}; - -&localbus { - flash@0 { - partitions { - partition@0 { - label = "Boot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@50000 { - label = "Certificate"; - reg = <0x50000 0x10000>; - read-only; - }; - partition@60000 { - label = "Special_Area"; - reg = <0x60000 0x10000>; - read-only; - }; - - partition@70000 { - label = " Reserve_0"; - reg = <0x70000 0x10000>; - read-only; - }; - - partition@80000 { - label = "Code_Image_0"; - reg = <0x80000 0x780000>; - brnboot,root-id = <0x00>; - read-only; - }; - - partition@4000000 { - compatible = "brnboot,root-selector"; - label = "Primary_Setting"; - reg = <0x4000000 0x10000>; - read-only; - }; - - partition@4010000 { - label = "Configuration"; - reg = <0x4010000 0x60000>; - read-only; - }; - - partition@4070000 { - label = " Reserve_1"; - reg = <0x4070000 0x10000>; - read-only; - }; - - partition@4080000 { - label = "Code_Image_1"; - reg = <0x4080000 0x780000>; - brnboot,root-id = <0x01>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts deleted file mode 100644 index e9606e19a2..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts +++ /dev/null @@ -1,29 +0,0 @@ -/dts-v1/; - -#include "vr9_arcadyan_vgv7519.dtsi" - -/ { - compatible = "arcadyan,vgv7519-nor", "arcadyan,vgv7519", "lantiq,xway", "lantiq,vr9"; - model = "KPN Experiabox V8"; -}; - -&localbus { - flash@0 { - partitions { - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - partition@60000 { - label = "u-boot-env"; - reg = <0x60000 0x10000>; - read-only; - }; - partition@80000 { - label = "firmware"; - reg = <0x80000 0xf80000>; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts deleted file mode 100644 index 1aea98260a..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts +++ /dev/null @@ -1,39 +0,0 @@ -/dts-v1/; - -#include "vr9_avm_fritz3370-rev2.dtsi" - -/ { - compatible = "avm,fritz3370-rev2-hynix", "avm,fritz3370-rev2", "lantiq,xway", "lantiq,vr9"; - model = "AVM FRITZ!Box 3370 Rev. 2 (Hynix NAND)"; -}; - -&localbus { - flash@1 { - compatible = "lantiq,nand-xway"; - bank-width = <2>; - reg = <1 0x0 0x2000000>; - - pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; - pinctrl-names = "default"; - - nand-ecc-mode = "soft"; - nand-ecc-strength = <3>; - nand-ecc-step-size = <256>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "kernel"; - reg = <0x0 0x400000>; - }; - - partition@400000 { - label = "ubi"; - reg = <0x400000 0x7c00000>; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts deleted file mode 100644 index a19d168159..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts +++ /dev/null @@ -1,37 +0,0 @@ -/dts-v1/; - -#include "vr9_avm_fritz3370-rev2.dtsi" - -/ { - compatible = "avm,fritz3370-rev2-micron", "avm,fritz3370-rev2", "lantiq,xway", "lantiq,vr9"; - model = "AVM FRITZ!Box 3370 Rev. 2 (Micron NAND)"; -}; - -&localbus { - flash@1 { - compatible = "lantiq,nand-xway"; - bank-width = <2>; - reg = <1 0x0 0x2000000>; - - pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; - pinctrl-names = "default"; - - nand-ecc-mode = "on-die"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "kernel"; - reg = <0x0 0x400000>; - }; - - partition@400000 { - label = "ubi"; - reg = <0x400000 0x7c00000>; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360-v2.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360-v2.dts deleted file mode 100644 index c9a7b2144b..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360-v2.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/dts-v1/; - -#include "vr9_avm_fritz736x.dtsi" - -#include -#include - -/ { - compatible = "avm,fritz7360-v2", "avm,fritz736x", "lantiq,xway", "lantiq,vr9"; - model = "AVM FRITZ!Box 7360 V2"; -}; - -&power_green { - label = "green:power"; -}; - -&power_red { - label = "red:power"; -}; - -&info_green { - label = "green:info"; -}; - -&wifi { - label = "green:wlan"; -}; - -&info_red { - label = "red:info"; -}; - -&dect { - label = "green:dect"; -}; - -&state_default { - pcie-rst { - lantiq,pins = "io21"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fixed-partitions"; - - urlader: partition@0 { - label = "urlader"; - reg = <0x00000 0x20000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x1f60000>; - }; - - partition@1f80000 { - label = "tffs (1)"; - reg = <0x1f80000 0x40000>; - read-only; - }; - - partition@1fc0000 { - label = "tffs (2)"; - reg = <0x1fc0000 0x40000>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts deleted file mode 100644 index 2311891469..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/dts-v1/; - -#include "vr9_avm_fritz736x.dtsi" - -#include -#include - -/ { - compatible = "avm,fritz7360sl", "avm,fritz736x", "lantiq,xway", "lantiq,vr9"; - model = "AVM FRITZ!Box 7360 SL"; -}; - -&power_green { - label = "green:power"; -}; - -&power_red { - label = "red:power"; -}; - -&info_green { - label = "green:info"; -}; - -&wifi { - label = "green:wlan"; -}; - -&info_red { - label = "red:info"; -}; - -&dect { - label = "green:dect"; -}; - -&state_default { - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x1000000>; - - partitions { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fixed-partitions"; - - urlader: partition@0 { - label = "urlader"; - reg = <0x00000 0x20000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0xf60000>; - }; - - partition@f80000 { - label = "tffs (1)"; - reg = <0xf80000 0x40000>; - read-only; - }; - - partition@fc0000 { - label = "tffs (2)"; - reg = <0xfc0000 0x40000>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts deleted file mode 100644 index 496dfcdd3f..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/dts-v1/; - -#include "vr9_avm_fritz736x.dtsi" - -#include -#include - -/ { - compatible = "avm,fritz7362sl", "avm,fritz736x", "lantiq,xway", "lantiq,vr9"; - model = "AVM FRITZ!Box 7362 SL"; -}; - -&power_green { - label = "green:power"; -}; - -&power_red { - label = "red:power"; -}; - -&info_green { - label = "green:info"; -}; - -&wifi { - label = "green:wlan"; -}; - -&info_red { - label = "red:info"; -}; - -&dect { - label = "green:dect"; -}; - -&state_default { - pcie-rst { - lantiq,pins = "io21"; - lantiq,open-drain = <1>; - lantiq,output = <1>; - }; -}; - -&spi { - status = "okay"; - - flash@4 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <4 0>; - spi-max-frequency = <1000000>; - - urlader: partition@0 { - reg = <0x0 0x40000>; - label = "urlader"; - read-only; - }; - - partition@40000 { - reg = <0x40000 0x60000>; - label = "tffs (1)"; - read-only; - }; - - partition@A0000 { - reg = <0xA0000 0x60000>; - label = "tffs (2)"; - read-only; - }; - }; -}; - -&localbus { - flash@1 { - compatible = "lantiq,nand-xway"; - lantiq,cs1 = <1>; - bank-width = <1>; - reg = <1 0x0 0x2000000>; - - pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; - pinctrl-names = "default"; - - nand-ecc-mode = "on-die"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "kernel"; - reg = <0x0 0x400000>; - }; - - partition@400000 { - label = "ubi"; - reg = <0x400000 0x7c00000>; - }; - }; - }; -}; - -&pcie0 { - gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>; - - pcie@0 { - #size-cells = <1>; - #address-cells = <2>; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi deleted file mode 100644 index f12485b3e1..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "avm,fritz736x", "lantiq,xway", "lantiq,vr9"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_red; - - led-dsl = &info_green; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - dect { - label = "dect"; - gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - - wifi { - label = "wifi"; - gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - - power_green: power { - gpios = <&gpio 32 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - power_red: power2 { - gpios = <&gpio 33 GPIO_ACTIVE_LOW>; - }; - - info_green: info_green { - gpios = <&gpio 47 GPIO_ACTIVE_LOW>; - }; - - wifi: wifi { - gpios = <&gpio 36 GPIO_ACTIVE_LOW>; - }; - - info_red: info_red { - gpios = <&gpio 34 GPIO_ACTIVE_LOW>; - }; - - dect: dect { - gpios = <&gpio 35 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&urlader 0xa91>; - mtd-mac-address-increment = <(-2)>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rmii"; - phy-handle = <&phy0>; - }; - - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <1>; - phy-mode = "rmii"; - phy-handle = <&phy1>; - }; - - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy0: ethernet-phy@0 { - reg = <0x00>; - compatible = "ethernet-phy-ieee802.3-c22"; - reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - }; - - phy1: ethernet-phy@1 { - reg = <0x01>; - compatible = "ethernet-phy-ieee802.3-c22"; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; - - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - phy-rst { - lantiq,pins = "io37", "io44"; - lantiq,pull = <0>; - lantiq,open-drain; - lantiq,output = <1>; - }; - }; - -}; - -&pcie0 { - status = "okay"; - - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <1>; - #address-cells = <2>; - device_type = "pci"; - - wifi@168c,002e { - compatible = "pci168c,002e"; - reg = <0 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */ - }; - }; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_phy1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts deleted file mode 100644 index 8fb5fdb2f6..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts +++ /dev/null @@ -1,218 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/dts-v1/; - -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "avm,fritz7412", "lantiq,xway", "lantiq,vr9"; - model = "AVM FRITZ!Box 7412"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_red; - - led-dsl = &info; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - dect { - label = "dect"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - power_green: power_green { - label = "green:power"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - power_red: power_red { - label = "red:power"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - - fon { - label = "green:fon"; - gpios = <&gpio 34 GPIO_ACTIVE_LOW>; - }; - - dect { - label = "green:dect"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - - wifi: wifi { - label = "green:wifi"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - }; - - info: info { - label = "green:info"; - gpios = <&gpio 35 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nand-xway"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - lantiq,cs = <1>; - - pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; - pinctrl-names = "default"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "urlader"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "nand-tffs"; - reg = <0x40000 0x400000>; - read-only; - }; - - partition@440000 { - label = "kernel"; - reg = <0x440000 0x400000>; - }; - - partition@840000 { - label = "ubi"; - reg = <0x840000 0x3000000>; - }; - - partition@3840000 { - label = "reserved-kernel"; - reg = <0x3840000 0x400000>; - read-only; - }; - - partition@3c40000 { - label = "reserved-filesystem"; - reg = <0x3c40000 0x3000000>; - read-only; - }; - - partition@6c40000 { - label = "config"; - reg = <0x6c40000 0x400000>; - read-only; - }; - - partition@6e40000 { - label = "nand-filesystem"; - reg = <0x6e40000 0x400000>; - read-only; - }; - }; - }; -}; - -&pcie0 { - status = "okay"; - gpio-reset = <&gpio 11 GPIO_ACTIVE_HIGH>; - - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - wifi@168c,002e { - compatible = "pci168c,002e"; - reg = <0 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */ - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pcie-rst { - lantiq,pins = "io11"; - lantiq,open-drain = <1>; - lantiq,output = <1>; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -ð0 { - lantiq,phys = <&gphy0>; - - interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mac-address = [ 00 11 22 33 44 55 ]; - lantiq,switch; - - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&vmmc { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts deleted file mode 100644 index 7cb1a1dccb..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts +++ /dev/null @@ -1,283 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "bt,homehub-v5a", "lantiq,xway", "lantiq,vr9"; - model = "BT Home Hub 5A"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_blue; - led-upgrade = &power_blue; - - led-dsl = &broadband_blue; - led-wifi = &wireless_blue; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&gpio 25 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - restart { - label = "restart"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - /* broadband-* is a single RGB led */ - broadband-red { - label = "red:broadband"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - }; - broadband-green { - label = "green:broadband"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - }; - broadband_blue: broadband-blue { - label = "blue:broadband"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - - /* wireless-* is a single RGB led */ - wireless-red { - label = "red:wireless"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - wireless-green { - label = "green:wireless"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; - wireless_blue: wireless-blue { - label = "blue:wireless"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - }; - - /* power-* is a single RGB led */ - power_red: power-red { - label = "red:power"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - }; - power_green: power-green { - label = "green:power"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_blue: power-blue { - label = "blue:power"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - - dimmed { - label = "dimmed"; - gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <1>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <0x5>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci_rst { - lantiq,pins = "io21"; - lantiq,output = <1>; - lantiq,open-drain; - }; - pcie_rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - lantiq,open-drain; - }; - usb_vbus { - lantiq,pins = "io33"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - }; -}; - -&localbus { - flash@1 { - compatible = "lantiq,nand-xway"; - lantiq,cs = <1>; - bank-width = <2>; - reg = <0x1 0x0 0x2000000>; - - pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; - pinctrl-names = "default"; - - nand-on-flash-bbt; - nand-ecc-strength = <3>; - nand-ecc-step-size = <256>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0xa0000>; - read-only; - }; - partition@a0000 { - label = "u-boot-env"; - reg = <0xa0000 0x20000>; - read-only; - }; - partition@c0000 { - label = "unused"; - reg = <0xc0000 0x40000>; - }; - partition@100000 { - label = "ubi"; - reg = <0x100000 0x7e80000>; - }; - /* - * last 512 KiB are for the bad block table, not writable - */ - }; - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@168c,002d { - compatible = "pci168c,002d"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - qca,disable-5ghz; - }; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts deleted file mode 100644 index caa9ff093b..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts +++ /dev/null @@ -1,312 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "buffalo,wbmr-300hpd", "lantiq,xway", "lantiq,vr9"; - model = "Buffalo WBMR-300HPD"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_g; - led-failsafe = &diag_r; - led-running = &power_g; - led-upgrade = &power_g; - - led-dsl = &dsl; - led-internet = &router_g; - led-wifi = &wifi_g; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power { - label = "power"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset { - label = "reset"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&gpio 31 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - auto { - label = "auto"; - gpios = <&gpio 48 GPIO_ACTIVE_HIGH>; - linux,code = ; - linux,input-type = ; - }; - - router { - label = "router"; - gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; - linux,code = ; - linux,input-type = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - diag_r: diag_r { - label = "red:diag"; - gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - default_state = "off"; - }; - - wifi_g: wifi_g { - label = "green:wifi"; - gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - }; - - dsl: dsl { - label = "dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; - }; - - router_y: router_y { - label = "yellow:router"; - gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; - }; - - wifi_y: wifi_y { - label = "yellow:wifi"; - gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; - }; - - lan1: lan1 { - label = "green:lan1"; - gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; - }; - - wan: wan { - label = "green:wan"; - gpios = <&gpio 12 GPIO_ACTIVE_HIGH>; - }; - - lan3: lan3 { - label = "green:lan3"; - gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; - }; - - lan2: lan2 { - label = "green:lan2"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - }; - - internet_g: internet_g { - label = "green:internet"; - gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; - }; - - internet_y: internet_y { - label = "yellow:internet"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - }; - - router_g: router_g { - label = "green:router"; - gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; - }; - - power_g: power_g { - label = "green:power"; - gpios = <&gpio 49 GPIO_ACTIVE_HIGH>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - lantiq,switch; - - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "mii"; - phy-handle = <&phy13>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "mii"; - phy-handle = <&phy14>; - }; - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "mii"; - phy-handle = <&phy11>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <3>; - phy-mode = "mii"; - phy-handle = <&phy12>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy12: ethernet-phy@12 { - reg = <0x12>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy14: ethernet-phy@14 { - reg = <0x14>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - phy-rst { - lantiq,pins = "io42"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; -}; - -&spi { - status = "okay"; - - flash@4 { - compatible = "jedec,spi-nor"; - reg = <4>; - spi-max-frequency = <20000000>; - - partitions { - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x10000>; - label = "u-boot"; - read-only; - }; - - partition@10000 { - reg = <0x10000 0x10000>; - label = "gphyfirmware"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0x80000>; - label = "dsl_fw"; - }; - - partition@de0000 { - reg = <0xa0000 0xf40000>; - label = "firmware"; - }; - - partition@fe0000 { - reg = <0xfe0000 0x10000>; - label = "sysconfig"; - read-only; - }; - - partition@ff0000 { - reg = <0xff0000 0x2000>; - label = "u-boot-env"; - }; - - partition@ff3000 { - reg = <0xff3000 0x2000>; - label = "board_config"; - read-only; - }; - }; - }; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_phy1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&usb1 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nand.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nand.dts deleted file mode 100644 index 7a7ab1cd43..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nand.dts +++ /dev/null @@ -1,66 +0,0 @@ -/dts-v1/; - - -#include "vr9_lantiq_easy80920.dtsi" - -/ { - compatible = "lantiq,easy80920-nand", "lantiq,easy80920", "lantiq,xway", "lantiq,vr9"; - model = "Intel EASY80920 Nand"; - - chosen { - bootargs = "ubi.mtd=ubi ubi.block=0,rootfsA root=/dev/ubiblock0_1"; - }; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nand-xway"; - lantiq,cs = <1>; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x100000>; /* 1024 KB */ - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x100000 0x40000>; /* 256 KB */ - }; - - partition@140000 { - label = "ubootconfigB"; - reg = <0x140000 0x40000>; /* 256 KB */ - }; - - partition@180000 { - label = "gphyfirmware"; - reg = <0x180000 0x40000>; /* 256 KB */ - }; - - partition@1c0000 { - label = "ubi"; - reg = <0x1c0000 0xc800000>; - }; - - partition@c9c0000 { - label = "calibration"; - reg = <0xc9c0000 0x100000>; - }; - - partition@cac0000 { - label = "res"; - reg = <0xcac0000 0x13540000>; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts deleted file mode 100644 index 004ce6f000..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts +++ /dev/null @@ -1,37 +0,0 @@ -/dts-v1/; - -#include "vr9_lantiq_easy80920.dtsi" - -/ { - compatible = "lantiq,easy80920-nor", "lantiq,easy80920", "lantiq,xway", "lantiq,vr9"; - model = "Intel EASY80920 Nor"; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - }; - - partition@10000 { - label = "u-boot-env"; - reg = <0x10000 0x10000>; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x7e0000>; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi deleted file mode 100644 index 79d7a5b410..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi +++ /dev/null @@ -1,279 +0,0 @@ -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "lantiq,easy80920", "lantiq,xway", "lantiq,vr9"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - - led-usb = &led_usb1; - led-usb2 = &led_usb2; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; -/* reset { - label = "reset"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - linux,code = ; - };*/ - paging { - label = "paging"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - power: power { - label = "green:power"; - gpios = <&stp 9 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - warning { - label = "green:warning"; - gpios = <&stp 22 GPIO_ACTIVE_HIGH>; - }; - fxs1 { - label = "green:fxs1"; - gpios = <&stp 21 GPIO_ACTIVE_HIGH>; - }; - fxs2 { - label = "green:fxs2"; - gpios = <&stp 20 GPIO_ACTIVE_HIGH>; - }; - fxo { - label = "green:fxo"; - gpios = <&stp 19 GPIO_ACTIVE_HIGH>; - }; - led_usb1: usb1 { - label = "green:usb1"; - gpios = <&stp 18 GPIO_ACTIVE_HIGH>; - }; - led_usb2: usb2 { - label = "green:usb2"; - gpios = <&stp 15 GPIO_ACTIVE_HIGH>; - }; - sd { - label = "green:sd"; - gpios = <&stp 14 GPIO_ACTIVE_HIGH>; - }; - wps { - label = "green:wps"; - gpios = <&stp 12 GPIO_ACTIVE_HIGH>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - lantiq,switch; - - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <1>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - }; - - wan: interface@1 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - lantiq,wan; - - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <0x5>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin3 { - lantiq,groups = "exin3"; - lantiq,function = "exin"; - }; - conf_out { - lantiq,pins = "io21", - "io33"; - lantiq,open-drain; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - conf_in { - lantiq,pins = "io39"; /* exin3 */ - lantiq,pull = <2>; - }; - }; -}; - -&spi { - status = "okay"; - - flash@4 { - compatible = "jedec,spi-nor"; - reg = <4>; - spi-max-frequency = <1000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x20000>; - label = "SPI (RO) U-Boot Image"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0x10000>; - label = "ENV_MAC"; - read-only; - }; - - partition@30000 { - reg = <0x30000 0x10000>; - label = "DPF"; - read-only; - }; - - partition@40000 { - reg = <0x40000 0x10000>; - label = "NVRAM"; - read-only; - }; - - partition@500000 { - reg = <0x50000 0x003a0000>; - label = "kernel"; - }; - }; - }; -}; - -&pci0 { - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; -}; - -&stp { - status = "okay"; - - lantiq,shadow = <0xffff>; - lantiq,groups = <0x7>; - lantiq,dsl = <0x3>; - lantiq,phy1 = <0x7>; - lantiq,phy2 = <0x7>; - /* lantiq,rising; */ -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts deleted file mode 100644 index 3662433040..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts +++ /dev/null @@ -1,186 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "netgear,dm200", "lantiq,xway", "lantiq,vr9"; - model = "Netgear DM200"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_amber; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &dsl_green; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - annexa { - gpio-export,name = "annexa"; - gpio-export,output = <0>; - gpios = <&gpio 12 GPIO_ACTIVE_HIGH>; - }; - annexb { - gpio-export,name = "annexb"; - gpio-export,output = <0>; - gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - }; - power_green: power_green { - label = "green:power"; - gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - }; - - lan_amber { - label = "amber:lan"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - }; - lan_green { - label = "green:lan"; - gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; - }; - - dsl_amber { - label = "amber:dsl"; - gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; - }; - dsl_green: dsl_green { - label = "green:dsl"; - gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -ð0 { - lantiq,phys = <&gphy1>; - - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "mii"; - phy-handle = <&phy13>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&pcie0 { - status = "disabled"; -}; - -&spi { - status = "okay"; - - flash@4 { - compatible = "jedec,spi-nor"; - reg = <4>; - spi-max-frequency = <10000000>; - - partitions { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fixed-partitions"; - - partition@0 { - reg = <0x0 0x20000>; - label = "uboot"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0x10000>; - label = "gphyfirmware"; - read-only; - }; - - partition@30000 { - reg = <0x30000 0x7b0000>; - label = "firmware"; - }; - - partition@7e0000 { - reg = <0x7e0000 0x10000>; - label = "sysconfig"; - read-only; - }; - - partition@7f0000 { - reg = <0x7f0000 0x2000>; - label = "u-boot-env"; - read-only; - }; - - partition@7f2000 { - reg = <0x7f2000 0x1000>; - label = "ART"; - read-only; - }; - - partition@7f3000 { - reg = <0x7f3000 0x1000>; - label = "pot"; - read-only; - }; - - partition@7f4000 { - reg = <0x7f4000 0xc000>; - label = "ret"; - read-only; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts deleted file mode 100644 index 9b3055983a..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "vr9_tplink_tdw89x0.dtsi" - -/ { - compatible = "tplink,tdw8970", "tplink,tdw89x0", "lantiq,xway", "lantiq,vr9"; - model = "TP-LINK TD-W8970"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts deleted file mode 100644 index acad866199..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts +++ /dev/null @@ -1,33 +0,0 @@ -/dts-v1/; - -#include "vr9_tplink_tdw89x0.dtsi" - -/ { - compatible = "tplink,tdw8980", "tplink,tdw89x0", "lantiq,xway", "lantiq,vr9"; - model = "TP-LINK TD-W8980"; - - gpio-leds { - wifi2 { - label = "green:wlan5ghz"; - gpios = <&gpio 24 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio { - state_default: pinmux { - pci_rst { - lantiq,pins = "io21"; - lantiq,output = <1>; - lantiq,open-drain; - }; - }; -}; - -&pci0 { - status = "okay"; - lantiq,bus-clock = <33333333>; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = <0x7000 0 0 1 &icu0 30 1>; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi deleted file mode 100644 index d057a8c17b..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi +++ /dev/null @@ -1,272 +0,0 @@ -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "tplink,tdw89x0", "lantiq,xway", "lantiq,vr9"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - /* the power led can't be controlled, use the wps led instead */ - led-boot = &wps; - led-failsafe = &wps; - - led-dsl = &dsl; - led-internet = &internet; - led-wifi = &wifi; - led-usb = &led_usb0; - led-usb2 = &led_usb2; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wifi { - label = "wifi"; - gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; - linux,code = ; - linux,input-type = ; - }; - - wps { - label = "wps"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - /* - power is not controllable via gpio - */ - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; - }; - internet: internet { - label = "green:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; - }; - - led_usb0: usb0 { - label = "green:usb"; - gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; - }; - led_usb2: usb2 { - label = "green:usb2"; - gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; - }; - wps: wps { - label = "green:wps"; - gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; - }; - }; - - wifi-leds { - compatible = "gpio-leds"; - - wifi: wifi { - label = "green:wifi"; - gpios = <&ath9k 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tpt"; - }; - }; - - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -ð0 { - pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>; - pinctrl-names = "default"; - - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&ath9k_cal 0xf100>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - // gpios = <&gpio 42 GPIO_ACTIVE_LOW>; - }; - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <0x5>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - phy-rst { - lantiq,pins = "io42"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; -}; - -&pcie0 { - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - ath9k: wifi@168c,002e { - compatible = "pci168c,002e"; - reg = <0 0 0 0 0>; - #gpio-cells = <2>; - gpio-controller; - qca,no-eeprom; - qca,disable-5ghz; - mtd-mac-address = <&ath9k_cal 0xf100>; - mtd-mac-address-increment = <2>; - }; - }; -}; - -&spi { - status = "okay"; - - flash@4 { - compatible = "jedec,spi-nor"; - reg = <4>; - spi-max-frequency = <33250000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x20000>; - label = "u-boot"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0x7a0000>; - label = "firmware"; - }; - - partition@7c0000 { - reg = <0x7c0000 0x10000>; - label = "config"; - read-only; - }; - - ath9k_cal: partition@7d0000 { - reg = <0x7d0000 0x30000>; - label = "boardconfig"; - read-only; - }; - }; - }; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_phy1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&usb1 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts deleted file mode 100644 index 62e32f81d6..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts +++ /dev/null @@ -1,92 +0,0 @@ -/dts-v1/; - -#include "vr9_tplink_vr200.dtsi" - -/ { - compatible = "tplink,vr200", "lantiq,xway", "lantiq,vr9"; - model = "TP-LINK Archer VR200"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - - led-dsl = &dsl; - led-internet = &internet; - led-wifi = &wlan5g; - - led-usb = &led_usb; - led-usb2 = &led_usb; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wifi { - label = "wifi"; - gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - linux,code = ; - linux,input-type = ; - }; - - wps { - label = "wps"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - led { - label = "led"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - power: power { - label = "blue:power"; - gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - dsl: dsl { - label = "blue:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - internet: internet { - label = "blue:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - led_usb: usb { - label = "blue:usb"; - gpios = <&gpio 25 GPIO_ACTIVE_LOW>; - }; - eth { - label = "blue:lan"; - gpios = <&gpio 40 GPIO_ACTIVE_LOW>; - }; - wlan { - label = "blue:wlan"; - gpios = <&gpio 24 GPIO_ACTIVE_LOW>; - }; - wlan5g: wifi { - label = "blue:wlan5g"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - led_wps { - label = "blue:wps"; - gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi deleted file mode 100644 index 77b4f0defb..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi +++ /dev/null @@ -1,213 +0,0 @@ -#include "vr9.dtsi" - -#include -#include - -/ { - memory@0 { - device_type = "memory"; - reg = <0x0 0x7f00000>; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -ð0 { - pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>; - pinctrl-names = "default"; - - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&romfile 0xf100>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - // gpios = <&gpio 42 GPIO_ACTIVE_LOW>; - }; - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <0x5>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - phy-rst { - lantiq,pins = "io42"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; -}; - -&pcie0 { - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - wifi@0,0 { - reg = <0 0 0 0 0>; - mediatek,mtd-eeprom = <&radio 0x0000>; - big-endian; - ieee80211-freq-limit = <5000000 6000000>; - mtd-mac-address = <&romfile 0xf100>; - mtd-mac-address-increment = <2>; - }; - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; -}; - -&spi { - status = "okay"; - - flash@4 { - compatible = "jedec,spi-nor"; - reg = <4>; - spi-max-frequency = <33250000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x20000>; - label = "u-boot"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0xf90000>; - label = "firmware"; - }; - - partition@fb0000 { - reg = <0xfb0000 0x10000>; - label = "radioDECT"; - read-only; - }; - - partition@fc0000 { - reg = <0xfc0000 0x10000>; - label = "config"; - read-only; - }; - - romfile: partition@fd0000 { - reg = <0xfd0000 0x10000>; - label = "romfile"; - read-only; - }; - - partition@fe0000 { - reg = <0xfe0000 0x10000>; - label = "rom"; - read-only; - }; - - radio: partition@ff0000 { - reg = <0xff0000 0x10000>; - label = "radio"; - read-only; - }; - }; - }; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_phy1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&usb1 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts deleted file mode 100644 index 81195988d0..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts +++ /dev/null @@ -1,99 +0,0 @@ -/dts-v1/; - -#include "vr9_tplink_vr200.dtsi" - -/ { - compatible = "tplink,vr200v", "lantiq,xway", "lantiq,vr9"; - model = "TP-LINK Archer VR200v"; - - chosen { - bootargs = "console=ttyLTQ0,115200 mem=126M vpe1_load_addr=0x87e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - - led-dsl = &dsl; - led-internet = &internet; - led-wifi = &wlan5g; - - led-usb = &led_usb; - led-usb2 = &led_usb; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wifi { - label = "wifi"; - gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - linux,code = ; - linux,input-type = ; - }; - - wps { - label = "wps"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - dect_paging { - label = "dect_paging"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - power: power { - label = "blue:power"; - gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - dsl: dsl { - label = "blue:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - internet: internet { - label = "blue:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - led_usb: usb { - label = "blue:usb"; - gpios = <&gpio 25 GPIO_ACTIVE_LOW>; - }; - eth { - label = "blue:lan"; - gpios = <&gpio 40 GPIO_ACTIVE_LOW>; - }; - wlan { - label = "blue:wlan"; - gpios = <&gpio 24 GPIO_ACTIVE_LOW>; - }; - wlan5g: wifi { - label = "blue:wlan5g"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - phone { - label = "blue:phone"; - gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&vmmc { - status = "okay"; - gpios = <&gpio 30 GPIO_ACTIVE_HIGH //fxs relay - &gpio 31 GPIO_ACTIVE_HIGH //still unknown - &gpio 3 GPIO_ACTIVE_HIGH>; //reset_slic? -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts deleted file mode 100644 index 4b1ff7023c..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts +++ /dev/null @@ -1,71 +0,0 @@ -/dts-v1/; - -#include "vr9_zyxel_p-2812hnu-fx.dtsi" - -/ { - compatible = "zyxel,p-2812hnu-f1", "zyxel,p-2812hnu", "lantiq,xway", "lantiq,vr9"; - model = "ZyXEL P-2812HNU-F1"; - - aliases { - led-usb = &led_usb1; - led-usb2 = &led_usb2; - }; - - leds { - led_usb1: usb1 { - label = "green:usb1"; - gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - }; - led_usb2: usb2 { - label = "green:usb2"; - gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nand-xway"; - lantiq,cs = <1>; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - - pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; - pinctrl-names = "default"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x20000>; - }; - partition@60000 { - label = "kernel"; - reg = <0x60000 0x300000>; - }; - partition@360000 { - label = "ubi"; - reg = <0x360000 0x7ca0000>; - }; - }; - }; -}; - -&pci0 { - wifi@1814,3062 { - compatible = "pci1814,3062"; - reg = <0x7000 0 0 0 0>; - ralink,eeprom = "RT3062.eeprom"; - }; -}; - -&pcie0 { - status = "disabled"; -}; diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts deleted file mode 100644 index 46a8137857..0000000000 --- a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts +++ /dev/null @@ -1,65 +0,0 @@ -/dts-v1/; - -#include "vr9_zyxel_p-2812hnu-fx.dtsi" - -/ { - compatible = "zyxel,p-2812hnu-f3", "zyxel,p-2812hnu", "lantiq,xway", "lantiq,vr9"; - model = "ZyXEL P-2812HNU-F3"; -}; - -&pci0 { - wifi@1814,3092 { - compatible = "pci1814,3092"; - reg = <0x7000 0 0 0 0>; - ralink,eeprom = "RT3092.eeprom"; - }; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>; - - pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; - pinctrl-names = "default"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x50000>; - read-only; - }; - partition@50000 { - label = "u-boot-env"; - reg = <0x50000 0x10000>; - }; - partition@60000 { - label = "unused"; - reg = <0x60000 0x7a0000>; - }; - }; - }; - - flash@1 { - compatible = "lantiq,nand-xway"; - lantiq,cs = <1>; - bank-width = <2>; - reg = <1 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "kernel"; - reg = <0x0 0x200000>; - }; - partition@200000 { - label = "ubi"; - reg = <0x200000 0x7e00000>; - }; - }; -}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi deleted file mode 100644 index 18168230b6..0000000000 --- a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi +++ /dev/null @@ -1,185 +0,0 @@ -#include "ar9.dtsi" - -#include - -/ { - chosen { - bootargs = "root= console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &dsl; - led-internet = &internet; - led-usb = &led_usb; - led-wifi = &wifi_green; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - rtl8366rb { - compatible = "realtek,rtl8366rb"; - gpio-sda = <&gpio 35 GPIO_ACTIVE_HIGH>; - gpio-sck = <&gpio 37 GPIO_ACTIVE_HIGH>; - - realtek,initvals = < - 0x0000 0x0830 - 0x0400 0x8130 - 0x000a 0x83ed - 0x0f51 0x0017 - 0x02f5 0x0048 - 0x02fa 0xffdf - 0x02fb 0xffe0 - 0x0450 0x0000 - 0x0401 0x0000 - 0x0431 0x0960 - >; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 36 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 53 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - internet: internet { - label = "green:internet"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; - internet2 { - label = "red:internet"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - led_usb: usb { - label = "green:usb"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - }; - power_green: power { - label = "green:power"; - gpios = <&gpio 34 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power2 { - label = "red:power"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - }; - wifi_green: wifi { - label = "green:wireless"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - }; - wifi2 { - label = "amber:wireless"; - gpios = <&gpio 51 GPIO_ACTIVE_LOW>; - }; - wps { - label = "green:wps"; - gpios = <&gpio 52 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - }; -}; - -&gsw { - phy-mode = "mii"; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@168c,0029 { - compatible = "pci168c,0029"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - }; -}; - -&spi { - status = "okay"; - - flash@4 { - compatible = "jedec,spi-nor"; - reg = <4>; - spi-max-frequency = <20000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x10000>; - label = "uboot"; - read-only; - }; - - partition@10000 { - reg = <0x10000 0x10000>; - label = "u-boot-env"; - read-only; - }; - - ath9k_cal: partition@20000 { - reg = <0x20000 0x10000>; - label = "calibration"; - read-only; - }; - - partition@50000 { - reg = <0x50000 0xfa0000>; - label = "firmware"; - }; - }; - }; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi deleted file mode 100644 index a6206f4a87..0000000000 --- a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi +++ /dev/null @@ -1,258 +0,0 @@ -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "arcadyan,vgv7510kw22", "lantiq,xway", "lantiq,vr9"; - - chosen { - bootargs = "console=ttyLTQ0,115200 mem=62M vpe1_load_addr=0x83e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &dsl; - led-internet = &internet_green; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; - - internet_red { - label = "red:internet"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; - - info_red { - label = "red:info"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - }; - - power_green: power { - label = "green:power"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - info_green { - label = "green:info"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - - internet_green: internet_green { - label = "green:internet"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; - - wifi: wifi { - label = "green:wlan"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - - power_red: power2 { - label = "red:power"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - }; - - phone { - label = "green:telefon"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -ð0 { - pinctrl-0 = <&mdio_pins>, - <&gphy0_led0_pins>, - <&gphy1_led0_pins>, <&gphy1_led1_pins>; - pinctrl-names = "default"; - - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&boardconfig 0x16>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "mii"; - phy-handle = <&phy1>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "mii"; - phy-handle = <&phy11>; - }; - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <3>; - phy-mode = "mii"; - phy-handle = <&phy12>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "mii"; - phy-handle = <&phy13>; - }; - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "mii"; - phy-handle = <&phy14>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy12: ethernet-phy@12 { - reg = <0x12>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy14: ethernet-phy@14 { - reg = <0x14>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>, <&gphy0_led1_pins>; - - state_default: pinmux { - pci-rst { - lantiq,pins = "io21"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x1000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boardconfig: partition@fe0000 { - label = "board_config"; - reg = <0xfe0000 0x20000>; - read-only; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@1814,3592 { - compatible = "pci1814,3592"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - mtd-mac-address = <&boardconfig 0x16>; - mtd-mac-address-increment = <1>; - }; -}; - -&pcie0 { - status = "disabled"; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; - gpios = <&gpio 30 GPIO_ACTIVE_HIGH //fxs relay - &gpio 31 GPIO_ACTIVE_HIGH //still unknown - &gpio 3 GPIO_ACTIVE_HIGH>; //reset_slic? -}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi deleted file mode 100644 index 0cb5244dbc..0000000000 --- a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi +++ /dev/null @@ -1,295 +0,0 @@ -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "arcadyan,vgv7519", "lantiq,xway", "lantiq,vr9"; - - chosen { - bootargs = "console=ttyLTQ0,115200 mem=62M vpe1_load_addr=0x83e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &broadband_green; - led-internet = &internet_green; - led-wifi = &wireless_green; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - eco { - label = "eco"; - gpios = <&gpio 41 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - rfkill { - label = "rfkill"; - gpios = <&gpio 45 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - eco { - label = "blue:eco"; - gpios = <&stp 2 GPIO_ACTIVE_LOW>; - }; - wps_red { - label = "red:wps"; - gpios = <&stp 3 GPIO_ACTIVE_LOW>; - }; - wps_green { - label = "green:wps"; - gpios = <&stp 4 GPIO_ACTIVE_LOW>; - }; - upgrade { - label = "blue:upgrade"; - gpios = <&stp 5 GPIO_ACTIVE_LOW>; - }; - tv { - label = "green:tv"; - gpios = <&stp 6 GPIO_ACTIVE_LOW>; - }; - internet_green: internet_green { - label = "green:internet"; - gpios = <&stp 7 GPIO_ACTIVE_LOW>; - }; - internet_red { - label = "red:internet"; - gpios = <&stp 8 GPIO_ACTIVE_LOW>; - }; - broadband_red { - label = "red:broadband"; - gpios = <&stp 9 GPIO_ACTIVE_LOW>; - }; - broadband_green: broadband_green { - label = "green:broadband"; - gpios = <&stp 10 GPIO_ACTIVE_LOW>; - }; - voice { - label = "green:voice"; - gpios = <&stp 11 GPIO_ACTIVE_LOW>; - }; - wireless_red { - label = "red:wireless"; - gpios = <&stp 12 GPIO_ACTIVE_LOW>; - }; - wireless_green: wireless_green { - label = "green:wireless"; - gpios = <&stp 13 GPIO_ACTIVE_LOW>; - }; - power_green: power2 { - label = "green:power"; - gpios = <&stp 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power { - label = "red:power"; - gpios = <&stp 15 GPIO_ACTIVE_LOW>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 32 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -ð0 { - pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led0_pins>; - pinctrl-names = "default"; - - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&boardconfig 0x16>; - mtd-mac-address-increment = <1>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <1>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <0x5>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci-rst { - lantiq,pins = "io21"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; -}; - -&localbus { - flash@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>, <1 0x800000 0x800000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boardconfig: partition@40000 { - label = "board_config"; - reg = <0x40000 0x10000>; - read-only; - }; - }; - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@1814,3091 { - compatible = "pci1814,3091"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - mtd-mac-address = <&boardconfig 0x16>; - mtd-mac-address-increment = <1>; - }; -}; - -&pcie0 { - status = "disabled"; -}; - -&stp { - status = "okay"; - lantiq,shadow = <0xffff>; - lantiq,groups = <0x3>; - lantiq,dsl = <0x0>; - lantiq,phy1 = <0x0>; - lantiq,phy2 = <0x0>; - /* lantiq,rising; */ -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_phy1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&usb1 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&vmmc { - status = "okay"; - gpios = <&gpio 30 GPIO_ACTIVE_HIGH //fxs relay - &gpio 31 GPIO_ACTIVE_HIGH //still unknown - &gpio 3 GPIO_ACTIVE_HIGH>; //reset_slic? -}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi deleted file mode 100644 index b25d11e1c6..0000000000 --- a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi +++ /dev/null @@ -1,279 +0,0 @@ -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "avm,fritz3370-rev2", "lantiq,xway", "lantiq,vr9"; - model = "AVM FRITZ!Box 3370 Rev. 2"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_red; - - led-dsl = &dsl; - led-internet = &info_green; - led-wifi = &wifi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power { - label = "power"; - gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - - wifi { - label = "wlan"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - power_green: power { - label = "green:power"; - gpios = <&gpio 32 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - power_red: power2 { - label = "red:power"; - gpios = <&gpio 33 GPIO_ACTIVE_LOW>; - }; - - info_red { - label = "red:info"; - gpios = <&gpio 34 GPIO_ACTIVE_LOW>; - }; - - wifi: wifi { - label = "green:wlan"; - gpios = <&gpio 35 GPIO_ACTIVE_LOW>; - }; - - dsl: dsl { - label = "green:dsl"; - gpios = <&gpio 36 GPIO_ACTIVE_LOW>; - }; - - lan { - label = "green:lan"; - gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - }; - - info_green: info_green { - label = "green:info"; - gpios = <&gpio 47 GPIO_ACTIVE_LOW>; - }; - }; - - usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB0_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB1_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; - }; - - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <1>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; - }; - - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - - phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - phy-rst { - lantiq,pins = "io37", "io44"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - - pcie-rst { - lantiq,pins = "io21"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; -}; - -&pcie0 { - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - wifi@0,0 { - compatible = "pci0,0"; - reg = <0 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */ - }; - }; -}; - -&spi { - status = "okay"; - - flash@4 { - compatible = "jedec,spi-nor"; - reg = <4>; - spi-max-frequency = <1000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - urlader: partition@0 { - reg = <0x0 0x20000>; - label = "urlader"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0x10000>; - label = "tffs (1)"; - read-only; - }; - - partition@30000 { - reg = <0x30000 0x10000>; - label = "tffs (2)"; - read-only; - }; - }; - }; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_phy1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb0_vbus>; -}; - -&usb1 { - status = "okay"; - vbus-supply = <&usb1_vbus>; -}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi deleted file mode 100644 index c4f30f5ffc..0000000000 --- a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi +++ /dev/null @@ -1,259 +0,0 @@ -#include "vr9.dtsi" - -#include -#include - -/ { - compatible = "zyxel,p-2812hnu", "lantiq,xway", "lantiq,vr9"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - - led-dsl = &dsl_green; - led-internet = &internet_green; - led-wifi = &wireless_green; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - rfkill { - label = "rfkill"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - internet_red { - label = "red:internet"; - gpios = <&stp 16 GPIO_ACTIVE_LOW>; - }; - internet_green: internet_green { - label = "green:internet"; - gpios = <&stp 17 GPIO_ACTIVE_LOW>; - }; - dsl_green: dsl_green { - label = "green:dsl"; - gpios = <&stp 18 GPIO_ACTIVE_LOW>; - }; - dsl_orange { - label = "orange:dsl"; - gpios = <&stp 19 GPIO_ACTIVE_LOW>; - }; - wireless_orange { - label = "orange:wlan"; - gpios = <&stp 20 GPIO_ACTIVE_LOW>; - }; - wireless_green: wireless_green { - label = "green:wlan"; - gpios = <&stp 21 GPIO_ACTIVE_LOW>; - }; - power_red: power { - label = "red:power"; - gpios = <&stp 22 GPIO_ACTIVE_LOW>; - }; - power_green: power2 { - label = "green:power"; - gpios = <&stp 23 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - phone1 { - label = "green:phone"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - }; - phone1warn { - label = "orange:phone"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - }; - phone2warn { - label = "orange:phone2"; - gpios = <&gpio 26 GPIO_ACTIVE_LOW>; - }; - phone2 { - label = "green:phone2"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - }; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -ð0 { - pinctrl-0 = <&mdio_pins>, - <&gphy0_led1_pins>, <&gphy0_led2_pins>, - <&gphy1_led1_pins>, <&gphy1_led2_pins>; - pinctrl-names = "default"; - - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mac-address = [ 00 11 22 33 44 55 ]; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <1>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <0x5>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&gphy0 { - lantiq,gphy-mode = ; -}; - -&gphy1 { - lantiq,gphy-mode = ; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin3 { - lantiq,groups = "exin3"; - lantiq,function = "exin"; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <2>; - }; - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - ifxhcd-rst { - lantiq,pins = "io33"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - }; -}; - -&pci0 { - status = "okay"; - - pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; - pinctrl-names = "default"; - - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; -}; - -&stp { - status = "okay"; - - lantiq,shadow = <0xffffff>; - lantiq,groups = <0x7>; - lantiq,dsl = <0x0>; - lantiq,phy1 = <0x0>; - lantiq,phy2 = <0x0>; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_phy1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&usb1 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse.dtsi similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse.dtsi diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi similarity index 100% rename from target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon.dtsi similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon.dtsi diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi 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diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts rename to 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a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi similarity index 100% rename from target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi similarity index 100% rename from target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi similarity index 100% rename from target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360-v2.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360-v2.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360-v2.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360-v2.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi similarity index 100% rename from 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target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts similarity index 100% rename from target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi similarity index 100% rename from target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi rename to target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi diff --git a/target/linux/lantiq/patches-4.19/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-4.19/0001-MIPS-lantiq-add-pcie-driver.patch deleted file mode 100644 index 44959af0c3..0000000000 --- a/target/linux/lantiq/patches-4.19/0001-MIPS-lantiq-add-pcie-driver.patch +++ /dev/null @@ -1,5520 +0,0 @@ -From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:12:28 +0200 -Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver - -Signed-off-by: John Crispin ---- - arch/mips/lantiq/Kconfig | 10 + - arch/mips/lantiq/xway/sysctrl.c | 2 + - arch/mips/pci/Makefile | 2 + - arch/mips/pci/fixup-lantiq-pcie.c | 82 +++ - arch/mips/pci/fixup-lantiq.c | 5 +- - arch/mips/pci/ifxmips_pci_common.h | 57 ++ - arch/mips/pci/ifxmips_pcie.c | 1099 ++++++++++++++++++++++++++++++ - arch/mips/pci/ifxmips_pcie.h | 135 ++++ - arch/mips/pci/ifxmips_pcie_ar10.h | 290 ++++++++ - arch/mips/pci/ifxmips_pcie_msi.c | 392 +++++++++++ - arch/mips/pci/ifxmips_pcie_phy.c | 478 +++++++++++++ - arch/mips/pci/ifxmips_pcie_pm.c | 176 +++++ - arch/mips/pci/ifxmips_pcie_pm.h | 36 + - arch/mips/pci/ifxmips_pcie_reg.h | 1001 +++++++++++++++++++++++++++ - arch/mips/pci/ifxmips_pcie_vr9.h | 271 ++++++++ - arch/mips/pci/pci.c | 25 + - arch/mips/pci/pcie-lantiq.h | 1305 ++++++++++++++++++++++++++++++++++++ - drivers/pci/pcie/aer/Kconfig | 2 +- - include/linux/pci.h | 2 + - include/linux/pci_ids.h | 6 + - 20 files changed, 5374 insertions(+), 2 deletions(-) - create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c - create mode 100644 arch/mips/pci/ifxmips_pci_common.h - create mode 100644 arch/mips/pci/ifxmips_pcie.c - create mode 100644 arch/mips/pci/ifxmips_pcie.h - create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h - create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c - create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c - create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c - create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h - create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h - create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h - create mode 100644 arch/mips/pci/pcie-lantiq.h - ---- a/arch/mips/lantiq/Kconfig -+++ b/arch/mips/lantiq/Kconfig -@@ -20,6 +20,7 @@ config SOC_XWAY - bool "XWAY" - select SOC_TYPE_XWAY - select HW_HAS_PCI -+ select ARCH_SUPPORTS_MSI - select MFD_SYSCON - select MFD_CORE - -@@ -52,6 +53,15 @@ config PCI_LANTIQ - bool "PCI Support" - depends on SOC_XWAY && PCI - -+config PCIE_LANTIQ -+ bool "PCIE Support" -+ depends on SOC_XWAY && PCI -+ -+config PCIE_LANTIQ_MSI -+ bool -+ depends on PCIE_LANTIQ && PCI_MSI -+ default y -+ - config XRX200_PHY_FW - bool "XRX200 PHY firmware loader" - depends on SOC_XWAY ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -49,6 +49,8 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o - obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o - obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o - obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o -+obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o -+obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o - obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o - obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o - obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o ---- /dev/null -+++ b/arch/mips/pci/fixup-lantiq-pcie.c -@@ -0,0 +1,74 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_fixup_pcie.c -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+/*! -+ \file ifxmips_fixup_pcie.c -+ \ingroup IFX_PCIE -+ \brief PCIe Fixup functions source file -+*/ -+#include -+#include -+#include -+ -+#include -+ -+#include "pcie-lantiq.h" -+ -+static void -+ifx_pcie_fixup_resource(struct pci_dev *dev) -+{ -+ u32 reg; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); -+ -+ printk("%s: fixup host controller %s (%04x:%04x)\n", -+ __func__, pci_name(dev), dev->vendor, dev->device); -+ -+ /* Setup COMMAND register */ -+ reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | -+ PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; -+ pci_write_config_word(dev, PCI_COMMAND, reg); -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); -+ -+static void -+ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); -+ -+ if (dev->devfn == PCI_DEVFN(0, 0) && -+ (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { -+ -+ dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); -+ -+ printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); -+ } -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); -+ mdelay(10); -+} -+ -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, -+ ifx_pcie_rc_class_early_fixup); -+ -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, -+ ifx_pcie_rc_class_early_fixup); ---- a/arch/mips/pci/fixup-lantiq.c -+++ b/arch/mips/pci/fixup-lantiq.c -@@ -8,12 +8,18 @@ - - #include - #include -+#include "ifxmips_pci_common.h" - - int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; - int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; - - int pcibios_plat_dev_init(struct pci_dev *dev) - { -+#ifdef CONFIG_PCIE_LANTIQ -+ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) -+ ifx_pcie_bios_plat_dev_init(dev); -+#endif -+ - if (ltq_pci_plat_arch_init) - return ltq_pci_plat_arch_init(dev); - -@@ -25,5 +31,10 @@ int pcibios_plat_dev_init(struct pci_dev - - int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) - { -+#ifdef CONFIG_PCIE_LANTIQ -+ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) -+ return ifx_pcie_bios_map_irq(dev, slot, pin); -+#endif -+ - return of_irq_parse_and_map_pci(dev, slot, pin); - } ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pci_common.h -@@ -0,0 +1,57 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pci_common.h -+** PROJECT : IFX UEIP -+** MODULES : PCI subsystem -+** -+** DATE : 30 June 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 30 June,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+ -+#ifndef IFXMIPS_PCI_COMMON_H -+#define IFXMIPS_PCI_COMMON_H -+#include -+/*! -+ \defgroup IFX_PCI_COM IFX PCI/PCIe common parts for OS integration -+ \brief PCI/PCIe common parts -+*/ -+ -+/*! -+ \defgroup IFX_PCI_COM_OS OS APIs -+ \ingroup IFX_PCI_COM -+ \brief PCI/PCIe bus driver OS interface functions -+*/ -+/*! -+ \file ifxmips_pci_common.h -+ \ingroup IFX_PCI_COM -+ \brief PCI/PCIe bus driver common OS header file -+*/ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) -+#define IFX_PCI_CONST -+#else -+#define IFX_PCI_CONST const -+#endif -+#ifdef CONFIG_IFX_PCI -+extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); -+extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev); -+#endif /* COFNIG_IFX_PCI */ -+ -+#ifdef CONFIG_PCIE_LANTIQ -+extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); -+extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev); -+#endif -+ -+#endif /* IFXMIPS_PCI_COMMON_H */ -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie.c -@@ -0,0 +1,1092 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2009 Lei Chuanhua -+ * Copyright (C) 2013 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "ifxmips_pcie.h" -+#include "ifxmips_pcie_reg.h" -+ -+/* Enable 32bit io due to its mem mapped io nature */ -+#define IFX_PCIE_ERROR_INT -+#define IFX_PCIE_IO_32BIT -+ -+#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) -+#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) -+#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) -+#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) -+#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) -+#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) -+#define SM(_v, _f) (((_v) << _f##_S) & (_f)) -+#define IFX_REG_SET_BIT(_f, _r) \ -+ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) -+ -+#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 -+ -+static DEFINE_SPINLOCK(ifx_pcie_lock); -+ -+u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); -+ -+static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { -+ { -+ .ir_irq = { -+ .irq = IFX_PCIE_IR, -+ .name = "ifx_pcie_rc0", -+ }, -+ -+ .legacy_irq = { -+ { -+ .irq_bit = PCIE_IRN_INTA, -+ .irq = IFX_PCIE_INTA, -+ }, -+ { -+ .irq_bit = PCIE_IRN_INTB, -+ .irq = IFX_PCIE_INTB, -+ }, -+ { -+ .irq_bit = PCIE_IRN_INTC, -+ .irq = IFX_PCIE_INTC, -+ }, -+ { -+ .irq_bit = PCIE_IRN_INTD, -+ .irq = IFX_PCIE_INTD, -+ }, -+ }, -+ }, -+ -+}; -+ -+void ifx_pcie_debug(const char *fmt, ...) -+{ -+ static char buf[256] = {0}; /* XXX */ -+ va_list ap; -+ -+ va_start(ap, fmt); -+ vsnprintf(buf, sizeof(buf), fmt, ap); -+ va_end(ap); -+ -+ printk("%s", buf); -+} -+ -+ -+static inline int pcie_ltssm_enable(int pcie_port) -+{ -+ int i; -+ -+ /* Enable LTSSM */ -+ IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); -+ -+ /* Wait for the link to come up */ -+ for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { -+ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) -+ return 0; -+ udelay(10); -+ } -+ -+ printk("%s link timeout!!!!!\n", __func__); -+ return -1; -+} -+ -+static inline void pcie_status_register_clear(int pcie_port) -+{ -+ IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); -+ IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_RSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_UES_R(pcie_port)); -+ IFX_REG_W32(0, PCIE_UEMR(pcie_port)); -+ IFX_REG_W32(0, PCIE_UESR(pcie_port)); -+ IFX_REG_W32(0, PCIE_CESR(pcie_port)); -+ IFX_REG_W32(0, PCIE_CEMR(pcie_port)); -+ IFX_REG_W32(0, PCIE_RESR(pcie_port)); -+ IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); -+ IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); -+ IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); -+ IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); -+ IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); -+ IFX_REG_W32(0, PCIE_QSR(pcie_port)); -+ IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); -+} -+ -+static inline int ifx_pcie_link_up(int pcie_port) -+{ -+ return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; -+} -+ -+ -+static inline void pcie_mem_io_setup(int pcie_port) -+{ -+ u32 reg; -+ /* -+ * BAR[0:1] readonly register -+ * RC contains only minimal BARs for packets mapped to this device -+ * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that -+ * reside on the downstream side fo the bridge. -+ */ -+ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) -+ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); -+ -+ IFX_REG_W32(reg, PCIE_MBML(pcie_port)); -+ -+ -+#ifdef IFX_PCIE_PREFETCH_MEM_64BIT -+ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR) -+ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT) -+ | PCIE_PMBL_64BIT_ADDR; -+ IFX_REG_W32(reg, PCIE_PMBL(pcie_port)); -+ -+ /* Must configure upper 32bit */ -+ IFX_REG_W32(0, PCIE_PMBU32(pcie_port)); -+ IFX_REG_W32(0, PCIE_PMLU32(pcie_port)); -+#else -+ /* PCIe_PBML, same as MBML */ -+ IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); -+#endif -+ -+ /* IO Address Range */ -+ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) -+ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); -+#ifdef IFX_PCIE_IO_32BIT -+ reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; -+#endif /* IFX_PCIE_IO_32BIT */ -+ IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); -+ -+#ifdef IFX_PCIE_IO_32BIT -+ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) -+ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); -+ IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); -+ -+#endif /* IFX_PCIE_IO_32BIT */ -+} -+ -+static inline void -+pcie_device_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Device capability register, set up Maximum payload size */ -+ reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); -+ reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; -+ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); -+ -+ /* Only available for EP */ -+ reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); -+ IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); -+ -+ /* Device control and status register */ -+ /* Set Maximum Read Request size for the device as a Requestor */ -+ reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); -+ -+ /* -+ * Request size can be larger than the MPS used, but the completions returned -+ * for the read will be bounded by the MPS size. -+ * In our system, Max request size depends on AHB burst size. It is 64 bytes. -+ * but we set it as 128 as minimum one. -+ */ -+ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) -+ | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); -+ -+ /* Enable relaxed ordering, no snoop, and all kinds of errors */ -+ reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; -+ -+ IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); -+} -+ -+static inline void -+pcie_link_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* -+ * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM -+ * L0s is reported during link training via TS1 order set by N_FTS -+ */ -+ reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); -+ reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; -+ reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); -+ IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); -+ -+ /* Link control and status register */ -+ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); -+ -+ /* Link Enable, ASPM enabled */ -+ reg &= ~PCIE_LCTLSTS_LINK_DISABLE; -+ -+#ifdef CONFIG_PCIEASPM -+ /* -+ * We use the same physical reference clock that the platform provides on the connector -+ * It paved the way for ASPM to calculate the new exit Latency -+ */ -+ reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; -+ reg |= PCIE_LCTLSTS_COM_CLK_CFG; -+ /* -+ * We should disable ASPM by default except that we have dedicated power management support -+ * Enable ASPM will cause the system hangup/instability, performance degration -+ */ -+ reg |= PCIE_LCTLSTS_ASPM_ENABLE; -+#else -+ reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; -+#endif /* CONFIG_PCIEASPM */ -+ -+ /* -+ * The maximum size of any completion with data packet is bounded by the MPS setting -+ * in device control register -+ */ -+ -+ /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ -+ reg &= ~ PCIE_LCTLSTS_RCB128; -+ -+ IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); -+} -+ -+static inline void pcie_error_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* -+ * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone -+ * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE -+ */ -+ reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); -+ reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; -+ -+ IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); -+ -+ /* Uncorrectable Error Mask Register, Unmask all bits in PCIE_UESR */ -+ reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); -+ reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; -+ IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); -+ -+ /* Uncorrectable Error Severity Register, ALL errors are FATAL */ -+ IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); -+ -+ /* Correctable Error Mask Register, unmask all bits */ -+ reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); -+ reg &= ~PCIE_CORRECTABLE_ERR; -+ IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); -+ -+ /* Advanced Error Capabilities and Control Registr */ -+ reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); -+ reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; -+ IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); -+ -+ /* Root Error Command Register, Report all types of errors */ -+ reg = IFX_REG_R32(PCIE_RECR(pcie_port)); -+ reg |= PCIE_RECR_ERR_REPORT_EN; -+ IFX_REG_W32(reg, PCIE_RECR(pcie_port)); -+ -+ /* Clear the Root status register */ -+ reg = IFX_REG_R32(PCIE_RESR(pcie_port)); -+ IFX_REG_W32(reg, PCIE_RESR(pcie_port)); -+} -+ -+static inline void pcie_port_logic_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ -+ reg = IFX_REG_R32(PCIE_AFR(pcie_port)); -+ reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); -+ reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) -+ | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); -+ /* L0s and L1 entry latency */ -+ reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); -+ reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) -+ | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); -+ IFX_REG_W32(reg, PCIE_AFR(pcie_port)); -+ -+ -+ /* Port Link Control Register */ -+ reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); -+ reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ -+ IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); -+ -+ /* Lane Skew Register */ -+ reg = IFX_REG_R32(PCIE_LSR(pcie_port)); -+ /* Enable ACK/NACK and FC */ -+ reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); -+ IFX_REG_W32(reg, PCIE_LSR(pcie_port)); -+ -+ /* Symbol Timer Register and Filter Mask Register 1 */ -+ reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); -+ -+ /* Default SKP interval is very accurate already, 5us */ -+ /* Enable IO/CFG transaction */ -+ reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; -+ /* Disable FC WDT */ -+ reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; -+ IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); -+ -+ /* Filter Masker Register 2 */ -+ reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); -+ reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; -+ IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); -+ -+ /* VC0 Completion Receive Queue Control Register */ -+ reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); -+ reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; -+ reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); -+ IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); -+} -+ -+static inline void pcie_rc_cfg_reg_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Disable LTSSM */ -+ IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */ -+ -+ pcie_mem_io_setup(pcie_port); -+ -+ /* XXX, MSI stuff should only apply to EP */ -+ /* MSI Capability: Only enable 32-bit addresses */ -+ reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); -+ reg &= ~PCIE_MCAPR_ADDR64_CAP; -+ -+ reg |= PCIE_MCAPR_MSI_ENABLE; -+ -+ /* Disable multiple message */ -+ reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); -+ IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); -+ -+ -+ /* Enable PME, Soft reset enabled */ -+ reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); -+ reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; -+ IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); -+ -+ /* setup the bus */ -+ reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); -+ IFX_REG_W32(reg, PCIE_BNR(pcie_port)); -+ -+ -+ pcie_device_setup(pcie_port); -+ pcie_link_setup(pcie_port); -+ pcie_error_setup(pcie_port); -+ -+ /* Root control and capabilities register */ -+ reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); -+ reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; -+ IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); -+ -+ /* Port VC Capability Register 2 */ -+ reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); -+ reg &= ~PCIE_PVC2_VC_ARB_WRR; -+ reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; -+ IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); -+ -+ /* VC0 Resource Capability Register */ -+ reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); -+ reg &= ~PCIE_VC0_RC_REJECT_SNOOP; -+ IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); -+ -+ pcie_port_logic_setup(pcie_port); -+} -+ -+static int ifx_pcie_wait_phy_link_up(int pcie_port) -+{ -+#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 /* XXX, tunable */ -+ int i; -+ -+ /* Wait for PHY link is up */ -+ for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { -+ if (ifx_pcie_link_up(pcie_port)) { -+ break; -+ } -+ udelay(100); -+ } -+ if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { -+ printk(KERN_ERR "%s timeout\n", __func__); -+ return -1; -+ } -+ -+ /* Check data link up or not */ -+ if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { -+ printk(KERN_ERR "%s DLL link is still down\n", __func__); -+ return -1; -+ } -+ -+ /* Check Data link active or not */ -+ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { -+ printk(KERN_ERR "%s DLL is not active\n", __func__); -+ return -1; -+ } -+ return 0; -+} -+ -+static inline int pcie_app_loigc_setup(int pcie_port) -+{ -+ /* supress ahb bus errrors */ -+ IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); -+ -+ /* Pull PCIe EP out of reset */ -+ pcie_device_rst_deassert(pcie_port); -+ -+ /* Start LTSSM training between RC and EP */ -+ pcie_ltssm_enable(pcie_port); -+ -+ /* Check PHY status after enabling LTSSM */ -+ if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) -+ return -1; -+ -+ return 0; -+} -+ -+/* -+ * The numbers below are directly from the PCIe spec table 3-4/5. -+ */ -+static inline void pcie_replay_time_update(int pcie_port) -+{ -+ u32 reg; -+ int nlw; -+ int rtl; -+ -+ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); -+ -+ nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); -+ switch (nlw) { -+ case PCIE_MAX_LENGTH_WIDTH_X1: -+ rtl = 1677; -+ break; -+ case PCIE_MAX_LENGTH_WIDTH_X2: -+ rtl = 867; -+ break; -+ case PCIE_MAX_LENGTH_WIDTH_X4: -+ rtl = 462; -+ break; -+ case PCIE_MAX_LENGTH_WIDTH_X8: -+ rtl = 258; -+ break; -+ default: -+ rtl = 1677; -+ break; -+ } -+ reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); -+ reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; -+ reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); -+ IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); -+} -+ -+/* -+ * Table 359 Enhanced Configuration Address Mapping1) -+ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 -+ * Memory Address PCI Express Configuration Space -+ * A[(20+n-1):20] Bus Number 1 < n < 8 -+ * A[19:15] Device Number -+ * A[14:12] Function Number -+ * A[11:8] Extended Register Number -+ * A[7:2] Register Number -+ * A[1:0] Along with size of the access, used to generate Byte Enables -+ * For VR9, only the address bits [22:0] are mapped to the configuration space: -+ * . Address bits [22:20] select the target bus (1-of-8)1) -+ * . Address bits [19:15] select the target device (1-of-32) on the bus -+ * . Address bits [14:12] select the target function (1-of-8) within the device. -+ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space -+ * . Address bits [1:0] define the start byte location within the selected dword. -+ */ -+static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where) -+{ -+ u32 addr; -+ u8 bus; -+ -+ if (!bus_num) { -+ /* type 0 */ -+ addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); -+ } else { -+ bus = bus_num; -+ /* type 1, only support 8 buses */ -+ addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | -+ ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); -+ } -+ return addr; -+} -+ -+static int pcie_valid_config(int pcie_port, int bus, int dev) -+{ -+ /* RC itself */ -+ if ((bus == 0) && (dev == 0)) { -+ return 1; -+ } -+ -+ /* No physical link */ -+ if (!ifx_pcie_link_up(pcie_port)) { -+ return 0; -+ } -+ -+ /* Bus zero only has RC itself -+ * XXX, check if EP will be integrated -+ */ -+ if ((bus == 0) && (dev != 0)) { -+ return 0; -+ } -+ -+ /* Maximum 8 buses supported for VRX */ -+ if (bus > 9) { -+ return 0; -+ } -+ -+ /* -+ * PCIe is PtP link, one bus only supports only one device -+ * except bus zero and PCIe switch which is virtual bus device -+ * The following two conditions really depends on the system design -+ * and attached the device. -+ * XXX, how about more new switch -+ */ -+ if ((bus == 1) && (dev != 0)) { -+ return 0; -+ } -+ -+ if ((bus >= 3) && (dev != 0)) { -+ return 0; -+ } -+ return 1; -+} -+ -+static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg) -+{ -+ return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val) -+{ -+ IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg) -+{ -+ return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val) -+{ -+ IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+u32 ifx_pcie_bus_enum_read_hack(int where, u32 value) -+{ -+ u32 tvalue = value; -+ -+ if (where == PCI_PRIMARY_BUS) { -+ u8 primary, secondary, subordinate; -+ -+ primary = tvalue & 0xFF; -+ secondary = (tvalue >> 8) & 0xFF; -+ subordinate = (tvalue >> 16) & 0xFF; -+ primary += pcibios_1st_host_bus_nr(); -+ secondary += pcibios_1st_host_bus_nr(); -+ subordinate += pcibios_1st_host_bus_nr(); -+ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); -+ } -+ return tvalue; -+} -+ -+u32 ifx_pcie_bus_enum_write_hack(int where, u32 value) -+{ -+ u32 tvalue = value; -+ -+ if (where == PCI_PRIMARY_BUS) { -+ u8 primary, secondary, subordinate; -+ -+ primary = tvalue & 0xFF; -+ secondary = (tvalue >> 8) & 0xFF; -+ subordinate = (tvalue >> 16) & 0xFF; -+ if (primary > 0 && primary != 0xFF) { -+ primary -= pcibios_1st_host_bus_nr(); -+ } -+ -+ if (secondary > 0 && secondary != 0xFF) { -+ secondary -= pcibios_1st_host_bus_nr(); -+ } -+ if (subordinate > 0 && subordinate != 0xFF) { -+ subordinate -= pcibios_1st_host_bus_nr(); -+ } -+ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); -+ } -+ else if (where == PCI_SUBORDINATE_BUS) { -+ u8 subordinate = tvalue & 0xFF; -+ -+ subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; -+ tvalue = subordinate; -+ } -+ return tvalue; -+} -+ -+static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn, -+ int where, int size, u32 *value) -+{ -+ u32 data = 0; -+ int bus_number = bus->number; -+ static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; -+ int ret = PCIBIOS_SUCCESSFUL; -+ struct ifx_pci_controller *ctrl = bus->sysdata; -+ int pcie_port = ctrl->port; -+ -+ if (unlikely(size != 1 && size != 2 && size != 4)){ -+ ret = PCIBIOS_BAD_REGISTER_NUMBER; -+ goto out; -+ } -+ -+ /* Make sure the address is aligned to natural boundary */ -+ if (unlikely(((size - 1) & where))) { -+ ret = PCIBIOS_BAD_REGISTER_NUMBER; -+ goto out; -+ } -+ -+ /* -+ * If we are second controller, we have to cheat OS so that it assume -+ * its bus number starts from 0 in host controller -+ */ -+ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); -+ -+ /* -+ * We need to force the bus number to be zero on the root -+ * bus. Linux numbers the 2nd root bus to start after all -+ * busses on root 0. -+ */ -+ if (bus->parent == NULL) { -+ bus_number = 0; -+ } -+ -+ /* -+ * PCIe only has a single device connected to it. It is -+ * always device ID 0. Don't bother doing reads for other -+ * device IDs on the first segment. -+ */ -+ if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { -+ ret = PCIBIOS_FUNC_NOT_SUPPORTED; -+ goto out; -+ } -+ -+ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { -+ *value = 0xffffffff; -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ goto out; -+ } -+ -+ PCIE_IRQ_LOCK(ifx_pcie_lock); -+ if (bus_number == 0) { /* RC itself */ -+ u32 t; -+ -+ t = (where & ~3); -+ data = ifx_pcie_rc_cfg_rd(pcie_port, t); -+ } else { -+ u32 addr = pcie_bus_addr(bus_number, devfn, where); -+ -+ data = ifx_pcie_cfg_rd(pcie_port, addr); -+ #ifdef CONFIG_IFX_PCIE_HW_SWAP -+ data = le32_to_cpu(data); -+ #endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ } -+ /* To get a correct PCI topology, we have to restore the bus number to OS */ -+ data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); -+ -+ PCIE_IRQ_UNLOCK(ifx_pcie_lock); -+ -+ *value = (data >> (8 * (where & 3))) & mask[size & 7]; -+out: -+ return ret; -+} -+ -+static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value) -+{ -+ u32 shift; -+ u32 tdata = data; -+ -+ switch (size) { -+ case 1: -+ shift = (where & 0x3) << 3; -+ tdata &= ~(0xffU << shift); -+ tdata |= ((value & 0xffU) << shift); -+ break; -+ case 2: -+ shift = (where & 3) << 3; -+ tdata &= ~(0xffffU << shift); -+ tdata |= ((value & 0xffffU) << shift); -+ break; -+ case 4: -+ tdata = value; -+ break; -+ } -+ return tdata; -+} -+ -+static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn, -+ int where, int size, u32 value) -+{ -+ int bus_number = bus->number; -+ int ret = PCIBIOS_SUCCESSFUL; -+ struct ifx_pci_controller *ctrl = bus->sysdata; -+ int pcie_port = ctrl->port; -+ u32 tvalue = value; -+ u32 data; -+ -+ /* Make sure the address is aligned to natural boundary */ -+ if (unlikely(((size - 1) & where))) { -+ ret = PCIBIOS_BAD_REGISTER_NUMBER; -+ goto out; -+ } -+ /* -+ * If we are second controller, we have to cheat OS so that it assume -+ * its bus number starts from 0 in host controller -+ */ -+ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); -+ -+ /* -+ * We need to force the bus number to be zero on the root -+ * bus. Linux numbers the 2nd root bus to start after all -+ * busses on root 0. -+ */ -+ if (bus->parent == NULL) { -+ bus_number = 0; -+ } -+ -+ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ goto out; -+ } -+ -+ /* XXX, some PCIe device may need some delay */ -+ PCIE_IRQ_LOCK(ifx_pcie_lock); -+ -+ /* -+ * To configure the correct bus topology using native way, we have to cheat Os so that -+ * it can configure the PCIe hardware correctly. -+ */ -+ tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); -+ -+ if (bus_number == 0) { /* RC itself */ -+ u32 t; -+ -+ t = (where & ~3); -+ data = ifx_pcie_rc_cfg_rd(pcie_port, t); -+ -+ data = ifx_pcie_size_to_value(where, size, data, tvalue); -+ -+ ifx_pcie_rc_cfg_wr(pcie_port, t, data); -+ } else { -+ u32 addr = pcie_bus_addr(bus_number, devfn, where); -+ -+ data = ifx_pcie_cfg_rd(pcie_port, addr); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ data = le32_to_cpu(data); -+#endif -+ -+ data = ifx_pcie_size_to_value(where, size, data, tvalue); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ data = cpu_to_le32(data); -+#endif -+ ifx_pcie_cfg_wr(pcie_port, addr, data); -+ } -+ PCIE_IRQ_UNLOCK(ifx_pcie_lock); -+out: -+ return ret; -+} -+ -+static struct resource ifx_pcie_io_resource = { -+ .name = "PCIe0 I/O space", -+ .start = PCIE_IO_PHY_BASE, -+ .end = PCIE_IO_PHY_END, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct resource ifx_pcie_mem_resource = { -+ .name = "PCIe0 Memory space", -+ .start = PCIE_MEM_PHY_BASE, -+ .end = PCIE_MEM_PHY_END, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct pci_ops ifx_pcie_ops = { -+ .read = ifx_pcie_read_config, -+ .write = ifx_pcie_write_config, -+}; -+ -+static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { -+ { -+ .pcic = { -+ .pci_ops = &ifx_pcie_ops, -+ .mem_resource = &ifx_pcie_mem_resource, -+ .io_resource = &ifx_pcie_io_resource, -+ }, -+ .port = IFX_PCIE_PORT0, -+ }, -+}; -+ -+#ifdef IFX_PCIE_ERROR_INT -+ -+static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) -+{ -+ struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; -+ int pcie_port = ctrl->port; -+ u32 reg; -+ -+ pr_debug("PCIe RC error intr %d\n", irq); -+ reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); -+ reg &= PCIE_RC_CORE_COMBINED_INT; -+ IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); -+ -+ return IRQ_HANDLED; -+} -+ -+static int -+pcie_rc_core_int_init(int pcie_port) -+{ -+ int ret; -+ -+ /* Enable core interrupt */ -+ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); -+ -+ /* Clear it first */ -+ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); -+ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0, -+ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); -+ if (ret) -+ printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); -+ -+ return ret; -+} -+#endif -+ -+int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ u32 irq_bit = 0; -+ int irq = 0; -+ struct ifx_pci_controller *ctrl = dev->bus->sysdata; -+ int pcie_port = ctrl->port; -+ -+ printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); -+ -+ if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { -+ printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); -+ return -1; -+ } -+ -+ /* Pin index so minus one */ -+ irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; -+ irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; -+ IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); -+ IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); -+ printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); -+ return irq; -+} -+ -+int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) -+{ -+ u16 config; -+#ifdef IFX_PCIE_ERROR_INT -+ u32 dconfig; -+ int pos; -+#endif -+ -+ /* Enable reporting System errors and parity errors on all devices */ -+ /* Enable parity checking and error reporting */ -+ pci_read_config_word(dev, PCI_COMMAND, &config); -+ config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | -+ PCI_COMMAND_FAST_BACK*/; -+ pci_write_config_word(dev, PCI_COMMAND, config); -+ -+ if (dev->subordinate) { -+ /* Set latency timers on sub bridges */ -+ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ -+ /* More bridge error detection */ -+ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); -+ config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; -+ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); -+ } -+#ifdef IFX_PCIE_ERROR_INT -+ /* Enable the PCIe normal error reporting */ -+ pos = pci_find_capability(dev, PCI_CAP_ID_EXP); -+ if (pos) { -+ -+ /* Disable system error generation in response to error messages */ -+ pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); -+ config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); -+ pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); -+ -+ /* Clear PCIE Capability's Device Status */ -+ pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); -+ pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); -+ -+ /* Update Device Control */ -+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); -+ /* Correctable Error Reporting */ -+ config |= PCI_EXP_DEVCTL_CERE; -+ /* Non-Fatal Error Reporting */ -+ config |= PCI_EXP_DEVCTL_NFERE; -+ /* Fatal Error Reporting */ -+ config |= PCI_EXP_DEVCTL_FERE; -+ /* Unsupported Request */ -+ config |= PCI_EXP_DEVCTL_URRE; -+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); -+ } -+ -+ /* Find the Advanced Error Reporting capability */ -+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); -+ if (pos) { -+ /* Clear Uncorrectable Error Status */ -+ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); -+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); -+ /* Enable reporting of all uncorrectable errors */ -+ /* Uncorrectable Error Mask - turned on bits disable errors */ -+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); -+ /* -+ * Leave severity at HW default. This only controls if -+ * errors are reported as uncorrectable or -+ * correctable, not if the error is reported. -+ */ -+ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ -+ /* Clear Correctable Error Status */ -+ pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); -+ pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); -+ /* Enable reporting of all correctable errors */ -+ /* Correctable Error Mask - turned on bits disable errors */ -+ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); -+ /* Advanced Error Capabilities */ -+ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); -+ /* ECRC Generation Enable */ -+ if (dconfig & PCI_ERR_CAP_ECRC_GENC) { -+ dconfig |= PCI_ERR_CAP_ECRC_GENE; -+ } -+ /* ECRC Check Enable */ -+ if (dconfig & PCI_ERR_CAP_ECRC_CHKC) { -+ dconfig |= PCI_ERR_CAP_ECRC_CHKE; -+ } -+ pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); -+ -+ /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ -+ /* Enable Root Port's interrupt in response to error messages */ -+ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, -+ PCI_ERR_ROOT_CMD_COR_EN | -+ PCI_ERR_ROOT_CMD_NONFATAL_EN | -+ PCI_ERR_ROOT_CMD_FATAL_EN); -+ /* Clear the Root status register */ -+ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); -+ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); -+ } -+#endif /* IFX_PCIE_ERROR_INT */ -+ /* WAR, only 128 MRRS is supported, force all EPs to support this value */ -+ pcie_set_readrq(dev, 128); -+ return 0; -+} -+ -+static int -+pcie_rc_initialize(int pcie_port) -+{ -+ int i; -+#define IFX_PCIE_PHY_LOOP_CNT 5 -+ -+ pcie_rcu_endian_setup(pcie_port); -+ -+ pcie_ep_gpio_rst_init(pcie_port); -+ -+ /* -+ * XXX, PCIe elastic buffer bug will cause not to be detected. One more -+ * reset PCIe PHY will solve this issue -+ */ -+ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { -+ /* Disable PCIe PHY Analog part for sanity check */ -+ pcie_phy_pmu_disable(pcie_port); -+ -+ pcie_phy_rst_assert(pcie_port); -+ pcie_phy_rst_deassert(pcie_port); -+ -+ /* Make sure PHY PLL is stable */ -+ udelay(20); -+ -+ /* PCIe Core reset enabled, low active, sw programmed */ -+ pcie_core_rst_assert(pcie_port); -+ -+ /* Put PCIe EP in reset status */ -+ pcie_device_rst_assert(pcie_port); -+ -+ /* PCI PHY & Core reset disabled, high active, sw programmed */ -+ pcie_core_rst_deassert(pcie_port); -+ -+ /* Already in a quiet state, program PLL, enable PHY, check ready bit */ -+ pcie_phy_clock_mode_setup(pcie_port); -+ -+ /* Enable PCIe PHY and Clock */ -+ pcie_core_pmu_setup(pcie_port); -+ -+ /* Clear status registers */ -+ pcie_status_register_clear(pcie_port); -+ -+#ifdef CONFIG_PCI_MSI -+ pcie_msi_init(pcie_port); -+#endif /* CONFIG_PCI_MSI */ -+ pcie_rc_cfg_reg_setup(pcie_port); -+ -+ /* Once link is up, break out */ -+ if (pcie_app_loigc_setup(pcie_port) == 0) -+ break; -+ } -+ if (i >= IFX_PCIE_PHY_LOOP_CNT) { -+ printk(KERN_ERR "%s link up failed!!!!!\n", __func__); -+ return -EIO; -+ } -+ /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ -+ pcie_replay_time_update(pcie_port); -+ return 0; -+} -+ -+static int __init ifx_pcie_bios_init(void) -+{ -+ void __iomem *io_map_base; -+ int pcie_port; -+ int startup_port; -+ -+ /* Enable AHB Master/ Slave */ -+ pcie_ahb_pmu_setup(); -+ -+ startup_port = IFX_PCIE_PORT0; -+ -+ for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ -+ if (pcie_rc_initialize(pcie_port) == 0) { -+ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", -+ __func__, PCIE_CFG_PORT_TO_BASE(pcie_port)); -+ /* Otherwise, warning will pop up */ -+ io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); -+ if (io_map_base == NULL) { -+ IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__); -+ return -ENOMEM; -+ } -+ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; -+ -+ register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); -+ /* XXX, clear error status */ -+ -+ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n", -+ __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, -+ &ifx_pcie_controller[pcie_port].pcic.io_resource); -+ -+ #ifdef IFX_PCIE_ERROR_INT -+ pcie_rc_core_int_init(pcie_port); -+ #endif /* IFX_PCIE_ERROR_INT */ -+ } -+ } -+ -+ return 0; -+} -+arch_initcall(ifx_pcie_bios_init); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); -+MODULE_SUPPORTED_DEVICE("Infineon builtin PCIe RC module"); -+MODULE_DESCRIPTION("Infineon builtin PCIe RC driver"); -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie.h -@@ -0,0 +1,135 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie.h -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+#ifndef IFXMIPS_PCIE_H -+#define IFXMIPS_PCIE_H -+#include -+#include -+#include -+#include -+#include "ifxmips_pci_common.h" -+#include "ifxmips_pcie_reg.h" -+ -+/*! -+ \defgroup IFX_PCIE PCI Express bus driver module -+ \brief PCI Express IP module support VRX200 -+*/ -+ -+/*! -+ \defgroup IFX_PCIE_OS OS APIs -+ \ingroup IFX_PCIE -+ \brief PCIe bus driver OS interface functions -+*/ -+ -+/*! -+ \file ifxmips_pcie.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe module common header file -+*/ -+#define PCIE_IRQ_LOCK(lock) do { \ -+ unsigned long flags; \ -+ spin_lock_irqsave(&(lock), flags); -+#define PCIE_IRQ_UNLOCK(lock) \ -+ spin_unlock_irqrestore(&(lock), flags); \ -+} while (0) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) -+#define IRQF_SHARED SA_SHIRQ -+#endif -+ -+#define PCIE_MSG_MSI 0x00000001 -+#define PCIE_MSG_ISR 0x00000002 -+#define PCIE_MSG_FIXUP 0x00000004 -+#define PCIE_MSG_READ_CFG 0x00000008 -+#define PCIE_MSG_WRITE_CFG 0x00000010 -+#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) -+#define PCIE_MSG_REG 0x00000020 -+#define PCIE_MSG_INIT 0x00000040 -+#define PCIE_MSG_ERR 0x00000080 -+#define PCIE_MSG_PHY 0x00000100 -+#define PCIE_MSG_ANY 0x000001ff -+ -+#define IFX_PCIE_PORT0 0 -+#define IFX_PCIE_PORT1 1 -+ -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+#define IFX_PCIE_CORE_NR 2 -+#else -+#define IFX_PCIE_CORE_NR 1 -+#endif -+ -+#define IFX_PCIE_ERROR_INT -+ -+//#define IFX_PCIE_DBG -+ -+#if defined(IFX_PCIE_DBG) -+#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ -+ ifx_pcie_debug((_fmt), ##args); \ -+} while (0) -+ -+#define INLINE -+#else -+#define IFX_PCIE_PRINT(_m, _fmt, args...) \ -+ do {} while(0) -+#define INLINE inline -+#endif -+ -+struct ifx_pci_controller { -+ struct pci_controller pcic; -+ -+ /* RC specific, per host bus information */ -+ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ -+}; -+ -+typedef struct ifx_pcie_ir_irq { -+ const unsigned int irq; -+ const char name[16]; -+}ifx_pcie_ir_irq_t; -+ -+typedef struct ifx_pcie_legacy_irq{ -+ const u32 irq_bit; -+ const int irq; -+}ifx_pcie_legacy_irq_t; -+ -+typedef struct ifx_pcie_irq { -+ ifx_pcie_ir_irq_t ir_irq; -+ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; -+}ifx_pcie_irq_t; -+ -+extern u32 g_pcie_debug_flag; -+extern void ifx_pcie_debug(const char *fmt, ...); -+extern void pcie_phy_clock_mode_setup(int pcie_port); -+extern void pcie_msi_pic_init(int pcie_port); -+extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); -+extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); -+ -+#define CONFIG_VR9 -+ -+#ifdef CONFIG_VR9 -+#include "ifxmips_pcie_vr9.h" -+#elif defined (CONFIG_AR10) -+#include "ifxmips_pcie_ar10.h" -+#else -+#error "PCIE: platform not defined" -+#endif /* CONFIG_VR9 */ -+ -+#endif /* IFXMIPS_PCIE_H */ -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_ar10.h -@@ -0,0 +1,290 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ *****************************************************************************/ -+/*! -+ \file ifxmips_pcie_ar10.h -+ \ingroup IFX_PCIE -+ \brief PCIe RC driver ar10 specific file -+*/ -+ -+#ifndef IFXMIPS_PCIE_AR10_H -+#define IFXMIPS_PCIE_AR10_H -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif /* AUTOCONF_INCLUDED */ -+#include -+#include -+ -+/* Project header file */ -+#include -+#include -+#include -+#include -+ -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+ ifx_ebu_led_enable(); -+ if (pcie_port == 0) { -+ ifx_ebu_led_set_data(11, 1); -+ } -+ else { -+ ifx_ebu_led_set_data(12, 1); -+ } -+} -+ -+static inline void pcie_ahb_pmu_setup(void) -+{ -+ /* XXX, moved to CGU to control AHBM */ -+} -+ -+static inline void pcie_rcu_endian_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+ /* Inbound, big endian */ -+ reg |= IFX_RCU_BE_AHB4S; -+ if (pcie_port == 0) { -+ reg |= IFX_RCU_BE_PCIE0M; -+ -+ #ifdef CONFIG_IFX_PCIE_HW_SWAP -+ /* Outbound, software swap needed */ -+ reg |= IFX_RCU_BE_AHB3M; -+ reg &= ~IFX_RCU_BE_PCIE0S; -+ #else -+ /* Outbound little endian */ -+ reg &= ~IFX_RCU_BE_AHB3M; -+ reg &= ~IFX_RCU_BE_PCIE0S; -+ #endif -+ } -+ else { -+ reg |= IFX_RCU_BE_PCIE1M; -+ #ifdef CONFIG_IFX_PCIE1_HW_SWAP -+ /* Outbound, software swap needed */ -+ reg |= IFX_RCU_BE_AHB3M; -+ reg &= ~IFX_RCU_BE_PCIE1S; -+ #else -+ /* Outbound little endian */ -+ reg &= ~IFX_RCU_BE_AHB3M; -+ reg &= ~IFX_RCU_BE_PCIE1S; -+ #endif -+ } -+ -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); -+} -+ -+static inline void pcie_phy_pmu_enable(int pcie_port) -+{ -+ if (pcie_port == 0) { /* XXX, should use macro*/ -+ PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+ else { -+ PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+} -+ -+static inline void pcie_phy_pmu_disable(int pcie_port) -+{ -+ if (pcie_port == 0) { /* XXX, should use macro*/ -+ PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE); -+ } -+ else { -+ PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE); -+ } -+} -+ -+static inline void pcie_pdi_big_endian(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+ if (pcie_port == 0) { -+ /* Config AHB->PCIe and PDI endianness */ -+ reg |= IFX_RCU_BE_PCIE0_PDI; -+ } -+ else { -+ /* Config AHB->PCIe and PDI endianness */ -+ reg |= IFX_RCU_BE_PCIE1_PDI; -+ } -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+} -+ -+static inline void pcie_pdi_pmu_enable(int pcie_port) -+{ -+ if (pcie_port == 0) { -+ /* Enable PDI to access PCIe PHY register */ -+ PDI0_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+ else { -+ PDI1_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+} -+ -+static inline void pcie_core_rst_assert(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ -+ /* Reset Core, bit 22 */ -+ if (pcie_port == 0) { -+ reg |= 0x00400000; -+ } -+ else { -+ reg |= 0x08000000; /* Bit 27 */ -+ } -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_core_rst_deassert(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Make sure one micro-second delay */ -+ udelay(1); -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ if (pcie_port == 0) { -+ reg &= ~0x00400000; /* bit 22 */ -+ } -+ else { -+ reg &= ~0x08000000; /* Bit 27 */ -+ } -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_phy_rst_assert(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ if (pcie_port == 0) { -+ reg |= 0x00001000; /* Bit 12 */ -+ } -+ else { -+ reg |= 0x00002000; /* Bit 13 */ -+ } -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_phy_rst_deassert(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Make sure one micro-second delay */ -+ udelay(1); -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ if (pcie_port == 0) { -+ reg &= ~0x00001000; /* Bit 12 */ -+ } -+ else { -+ reg &= ~0x00002000; /* Bit 13 */ -+ } -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_device_rst_assert(int pcie_port) -+{ -+ if (pcie_port == 0) { -+ ifx_ebu_led_set_data(11, 0); -+ } -+ else { -+ ifx_ebu_led_set_data(12, 0); -+ } -+} -+ -+static inline void pcie_device_rst_deassert(int pcie_port) -+{ -+ mdelay(100); -+ if (pcie_port == 0) { -+ ifx_ebu_led_set_data(11, 1); -+ } -+ else { -+ ifx_ebu_led_set_data(12, 1); -+ } -+ ifx_ebu_led_disable(); -+} -+ -+static inline void pcie_core_pmu_setup(int pcie_port) -+{ -+ if (pcie_port == 0) { -+ PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+ else { -+ PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+} -+ -+static inline void pcie_msi_init(int pcie_port) -+{ -+ pcie_msi_pic_init(pcie_port); -+ if (pcie_port == 0) { -+ MSI0_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+ else { -+ MSI1_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+} -+ -+static inline u32 -+ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) -+{ -+ u32 tbus_number = bus_number; -+ -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ -+ if (pcibios_host_nr() > 1) { -+ tbus_number -= pcibios_1st_host_bus_nr(); -+ } -+ } -+#endif /* CONFIG_IFX_PCI */ -+ return tbus_number; -+} -+ -+static inline u32 -+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) -+{ -+ struct pci_dev *pdev; -+ u32 tvalue = value; -+ -+ /* Sanity check */ -+ pdev = pci_get_slot(bus, devfn); -+ if (pdev == NULL) { -+ return tvalue; -+ } -+ -+ /* Only care about PCI bridge */ -+ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { -+ return tvalue; -+ } -+ -+ if (read) { /* Read hack */ -+ #ifdef CONFIG_IFX_PCIE_2ND_CORE -+ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); -+ } -+ } -+ #endif /* CONFIG_IFX_PCIE_2ND_CORE */ -+ } -+ else { /* Write hack */ -+ #ifdef CONFIG_IFX_PCIE_2ND_CORE -+ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); -+ } -+ } -+ #endif -+ } -+ return tvalue; -+} -+ -+#endif /* IFXMIPS_PCIE_AR10_H */ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_msi.c -@@ -0,0 +1,392 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_msi.c -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCI MSI sub module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe MSI Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Date $Author $Comment -+** 02 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+/*! -+ \defgroup IFX_PCIE_MSI MSI OS APIs -+ \ingroup IFX_PCIE -+ \brief PCIe bus driver OS interface functions -+*/ -+ -+/*! -+ \file ifxmips_pcie_msi.c -+ \ingroup IFX_PCIE -+ \brief PCIe MSI OS interface file -+*/ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif /* AUTOCONF_INCLUDED */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "ifxmips_pcie_reg.h" -+#include "ifxmips_pcie.h" -+ -+#define IFX_MSI_IRQ_NUM 16 -+ -+enum { -+ IFX_PCIE_MSI_IDX0 = 0, -+ IFX_PCIE_MSI_IDX1, -+ IFX_PCIE_MSI_IDX2, -+ IFX_PCIE_MSI_IDX3, -+}; -+ -+typedef struct ifx_msi_irq_idx { -+ const int irq; -+ const int idx; -+}ifx_msi_irq_idx_t; -+ -+struct ifx_msi_pic { -+ volatile u32 pic_table[IFX_MSI_IRQ_NUM]; -+ volatile u32 pic_endian; /* 0x40 */ -+}; -+typedef struct ifx_msi_pic *ifx_msi_pic_t; -+ -+typedef struct ifx_msi_irq { -+ const volatile ifx_msi_pic_t msi_pic_p; -+ const u32 msi_phy_base; -+ const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; -+ /* -+ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is -+ * in use. -+ */ -+ u16 msi_free_irq_bitmask; -+ -+ /* -+ * Each bit in msi_multiple_irq_bitmask tells that the device using -+ * this bit in msi_free_irq_bitmask is also using the next bit. This -+ * is used so we can disable all of the MSI interrupts when a device -+ * uses multiple. -+ */ -+ u16 msi_multiple_irq_bitmask; -+}ifx_msi_irq_t; -+ -+static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { -+ { -+ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, -+ .msi_phy_base = PCIE_MSI_PHY_BASE, -+ .msi_irq_idx = { -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ }, -+ .msi_free_irq_bitmask = 0, -+ .msi_multiple_irq_bitmask= 0, -+ }, -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+ { -+ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, -+ .msi_phy_base = PCIE1_MSI_PHY_BASE, -+ .msi_irq_idx = { -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ }, -+ .msi_free_irq_bitmask = 0, -+ .msi_multiple_irq_bitmask= 0, -+ -+ }, -+#endif /* CONFIG_IFX_PCIE_2ND_CORE */ -+}; -+ -+/* -+ * This lock controls updates to msi_free_irq_bitmask, -+ * msi_multiple_irq_bitmask and pic register settting -+ */ -+static DEFINE_SPINLOCK(ifx_pcie_msi_lock); -+ -+void pcie_msi_pic_init(int pcie_port) -+{ -+ spin_lock(&ifx_pcie_msi_lock); -+ msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; -+ spin_unlock(&ifx_pcie_msi_lock); -+} -+ -+/** -+ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) -+ * \brief Called when a driver request MSI interrupts instead of the -+ * legacy INT A-D. This routine will allocate multiple interrupts -+ * for MSI devices that support them. A device can override this by -+ * programming the MSI control bits [6:4] before calling -+ * pci_enable_msi(). -+ * -+ * \param[in] pdev Device requesting MSI interrupts -+ * \param[in] desc MSI descriptor -+ * -+ * \return -EINVAL Invalid pcie root port or invalid msi bit -+ * \return 0 OK -+ * \ingroup IFX_PCIE_MSI -+ */ -+int -+arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) -+{ -+ int irq, pos; -+ u16 control; -+ int irq_idx; -+ int irq_step; -+ int configured_private_bits; -+ int request_private_bits; -+ struct msi_msg msg; -+ u16 search_mask; -+ struct ifx_pci_controller *ctrl = pdev->bus->sysdata; -+ int pcie_port = ctrl->port; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); -+ -+ /* XXX, skip RC MSI itself */ -+ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); -+ return -EINVAL; -+ } -+ -+ /* -+ * Read the MSI config to figure out how many IRQs this device -+ * wants. Most devices only want 1, which will give -+ * configured_private_bits and request_private_bits equal 0. -+ */ -+ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); -+ -+ /* -+ * If the number of private bits has been configured then use -+ * that value instead of the requested number. This gives the -+ * driver the chance to override the number of interrupts -+ * before calling pci_enable_msi(). -+ */ -+ configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; -+ if (configured_private_bits == 0) { -+ /* Nothing is configured, so use the hardware requested size */ -+ request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; -+ } -+ else { -+ /* -+ * Use the number of configured bits, assuming the -+ * driver wanted to override the hardware request -+ * value. -+ */ -+ request_private_bits = configured_private_bits; -+ } -+ -+ /* -+ * The PCI 2.3 spec mandates that there are at most 32 -+ * interrupts. If this device asks for more, only give it one. -+ */ -+ if (request_private_bits > 5) { -+ request_private_bits = 0; -+ } -+again: -+ /* -+ * The IRQs have to be aligned on a power of two based on the -+ * number being requested. -+ */ -+ irq_step = (1 << request_private_bits); -+ -+ /* Mask with one bit for each IRQ */ -+ search_mask = (1 << irq_step) - 1; -+ -+ /* -+ * We're going to search msi_free_irq_bitmask_lock for zero -+ * bits. This represents an MSI interrupt number that isn't in -+ * use. -+ */ -+ spin_lock(&ifx_pcie_msi_lock); -+ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { -+ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { -+ msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; -+ msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; -+ break; -+ } -+ } -+ spin_unlock(&ifx_pcie_msi_lock); -+ -+ /* Make sure the search for available interrupts didn't fail */ -+ if (pos >= IFX_MSI_IRQ_NUM) { -+ if (request_private_bits) { -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " -+ "interrupts, trying just one", __func__, 1 << request_private_bits); -+ request_private_bits = 0; -+ goto again; -+ } -+ else { -+ printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); -+ return -EINVAL; -+ } -+ } -+ irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; -+ irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); -+ -+ /* -+ * Initialize MSI. This has to match the memory-write endianess from the device -+ * Address bits [23:12] -+ */ -+ spin_lock(&ifx_pcie_msi_lock); -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | -+ SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | -+ SM((1 << pos), IFX_MSI_PIC_MSG_DATA); -+ -+ /* Enable this entry */ -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; -+ spin_unlock(&ifx_pcie_msi_lock); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", -+ pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); -+ -+ /* Update the number of IRQs the device has available to it */ -+ control &= ~PCI_MSI_FLAGS_QSIZE; -+ control |= (request_private_bits << 4); -+ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); -+ -+ set_irq_msi(irq, desc); -+ msg.address_hi = 0x0; -+ msg.address_lo = msi_irqs[pcie_port].msi_phy_base; -+ msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); -+ -+ write_msi_msg(irq, &msg); -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); -+ return 0; -+} -+ -+static int -+pcie_msi_irq_to_port(unsigned int irq, int *port) -+{ -+ int ret = 0; -+ -+ if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || -+ irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { -+ *port = IFX_PCIE_PORT0; -+ } -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+ else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || -+ irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { -+ *port = IFX_PCIE_PORT1; -+ } -+#endif /* CONFIG_IFX_PCIE_2ND_CORE */ -+ else { -+ printk(KERN_ERR "%s: Attempted to teardown illegal " -+ "MSI interrupt (%d)\n", __func__, irq); -+ ret = -EINVAL; -+ } -+ return ret; -+} -+ -+/** -+ * \fn void arch_teardown_msi_irq(unsigned int irq) -+ * \brief Called when a device no longer needs its MSI interrupts. All -+ * MSI interrupts for the device are freed. -+ * -+ * \param irq The devices first irq number. There may be multple in sequence. -+ * \return none -+ * \ingroup IFX_PCIE_MSI -+ */ -+void -+arch_teardown_msi_irq(unsigned int irq) -+{ -+ int pos; -+ int number_irqs; -+ u16 bitmask; -+ int pcie_port; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); -+ -+ BUG_ON(irq > INT_NUM_IM4_IRL31); -+ -+ if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { -+ return; -+ } -+ -+ /* Shift the mask to the correct bit location, not always correct -+ * Probally, the first match will be chosen. -+ */ -+ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { -+ if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) -+ && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { -+ break; -+ } -+ } -+ if (pos >= IFX_MSI_IRQ_NUM) { -+ printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); -+ return; -+ } -+ spin_lock(&ifx_pcie_msi_lock); -+ /* Disable this entry */ -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); -+ spin_unlock(&ifx_pcie_msi_lock); -+ /* -+ * Count the number of IRQs we need to free by looking at the -+ * msi_multiple_irq_bitmask. Each bit set means that the next -+ * IRQ is also owned by this device. -+ */ -+ number_irqs = 0; -+ while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && -+ (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { -+ number_irqs++; -+ } -+ number_irqs++; -+ -+ /* Mask with one bit for each IRQ */ -+ bitmask = (1 << number_irqs) - 1; -+ -+ bitmask <<= pos; -+ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { -+ printk(KERN_ERR "%s: Attempted to teardown MSI " -+ "interrupt (%d) not in use\n", __func__, irq); -+ return; -+ } -+ /* Checks are done, update the in use bitmask */ -+ spin_lock(&ifx_pcie_msi_lock); -+ msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; -+ msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); -+ spin_unlock(&ifx_pcie_msi_lock); -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); -+} -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); -+MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module"); -+MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_phy.c -@@ -0,0 +1,478 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_phy.c -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe PHY sub module -+** -+** DATE : 14 May 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 14 May,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+/*! -+ \file ifxmips_pcie_phy.c -+ \ingroup IFX_PCIE -+ \brief PCIe PHY PLL register programming source file -+*/ -+#include -+#include -+#include -+#include -+ -+#include "ifxmips_pcie_reg.h" -+#include "ifxmips_pcie.h" -+ -+/* PCIe PDI only supports 16 bit operation */ -+ -+#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ -+ ((*(volatile u16 *) (__addr)) = (__data)) -+ -+#define IFX_PCIE_PHY_REG_READ16(__addr) \ -+ (*(volatile u16 *) (__addr)) -+ -+#define IFX_PCIE_PHY_REG16(__addr) \ -+ (*(volatile u16 *) (__addr)) -+ -+#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ -+ u16 read_data; \ -+ u16 write_data; \ -+ read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ -+ write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ -+ IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ -+} while (0) -+ -+#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ -+ -+//#define IFX_PCI_PHY_REG_DUMP -+ -+#ifdef IFX_PCI_PHY_REG_DUMP -+static void -+pcie_phy_reg_dump(int pcie_port) -+{ -+ printk("PLL REGFILE\n"); -+ printk("PCIE_PHY_PLL_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL4 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL5 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL6 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL7 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port))); -+ printk("PCIE_PHY_PLL_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port))); -+ printk("PCIE_PHY_PLL_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port))); -+ printk("PCIE_PHY_PLL_A_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port))); -+ printk("PCIE_PHY_PLL_STATUS 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port))); -+ -+ printk("TX1 REGFILE\n"); -+ printk("PCIE_PHY_TX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port))); -+ printk("PCIE_PHY_TX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port))); -+ printk("PCIE_PHY_TX1_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port))); -+ printk("PCIE_PHY_TX1_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port))); -+ printk("PCIE_PHY_TX1_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port))); -+ printk("PCIE_PHY_TX1_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port))); -+ printk("PCIE_PHY_TX1_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port))); -+ printk("PCIE_PHY_TX1_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port))); -+ -+ printk("TX2 REGFILE\n"); -+ printk("PCIE_PHY_TX2_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port))); -+ printk("PCIE_PHY_TX2_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port))); -+ printk("PCIE_PHY_TX2_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port))); -+ printk("PCIE_PHY_TX2_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port))); -+ printk("PCIE_PHY_TX2_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port))); -+ printk("PCIE_PHY_TX2_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port))); -+ printk("PCIE_PHY_TX2_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port))); -+ -+ printk("RX1 REGFILE\n"); -+ printk("PCIE_PHY_RX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port))); -+ printk("PCIE_PHY_RX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port))); -+ printk("PCIE_PHY_RX1_CDR 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port))); -+ printk("PCIE_PHY_RX1_EI 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port))); -+ printk("PCIE_PHY_RX1_A_CTRL 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port))); -+} -+#endif /* IFX_PCI_PHY_REG_DUMP */ -+ -+static void -+pcie_phy_comm_setup(int pcie_port) -+{ -+ /* PLL Setting */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); -+ -+ /* increase the bias reference voltage */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); -+ -+ /* Endcnt */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); -+ -+ /* force */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); -+ -+ /* predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); -+ -+ /* ctrl_lim */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); -+ -+ /* ctrl */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); -+ -+ /* predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); -+ -+ /* RTERM*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); -+ -+ /* Improved 100MHz clock output */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); -+ -+ /* Reduced CDR BW to avoid glitches */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); -+} -+ -+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+static void -+pcie_phy_36mhz_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+ -+ /* en_ext_mmd_div_ratio */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); -+ -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); -+ -+ /* const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); -+ -+ /* const sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); -+ -+ /* pllmod */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ -+ -+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE -+static void -+pcie_phy_36mhz_ssc_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+ -+ /* PLL Setting */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); -+ -+ /* Increase the bias reference voltage */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); -+ -+ /* Endcnt */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); -+ -+ /* Force */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); -+ -+ /* Predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); -+ -+ /* ctrl_lim */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); -+ -+ /* ctrl */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); -+ -+ /* predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); -+ -+ /* RTERM*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); -+ -+ /* en_ext_mmd_div_ratio */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); -+ -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); -+ -+ /* const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); -+ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); -+ /* const sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); -+ -+ /* pllmod */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); -+ -+ /* improved 100MHz clock output */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); -+ -+ /* reduced CDR BW to avoid glitches */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ -+ -+#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE -+static void -+pcie_phy_25mhz_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); -+ -+ /* en_ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ -+ -+#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE -+static void -+pcie_phy_100mhz_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+ /* en_ext_mmd_div_ratio */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); -+ -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); -+ -+ /* const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); -+ -+ /* const sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); -+ -+ /* pllmod */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ -+ -+static int -+pcie_phy_wait_startup_ready(int pcie_port) -+{ -+ int i; -+ -+ for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { -+ if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { -+ break; -+ } -+ udelay(10); -+ } -+ if (i >= IFX_PCIE_PLL_TIMEOUT) { -+ printk(KERN_ERR "%s PLL Link timeout\n", __func__); -+ return -1; -+ } -+ return 0; -+} -+ -+static void -+pcie_phy_load_enable(int pcie_port, int slice) -+{ -+ /* Set the load_en of tx/rx slice to '1' */ -+ switch (slice) { -+ case 1: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); -+ break; -+ case 2: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); -+ break; -+ case 3: -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); -+ break; -+ } -+} -+ -+static void -+pcie_phy_load_disable(int pcie_port, int slice) -+{ -+ /* set the load_en of tx/rx slice to '0' */ -+ switch (slice) { -+ case 1: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); -+ break; -+ case 2: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); -+ break; -+ case 3: -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); -+ break; -+ } -+} -+ -+static void -+pcie_phy_load_war(int pcie_port) -+{ -+ int slice; -+ -+ for (slice = 1; slice < 4; slice++) { -+ pcie_phy_load_enable(pcie_port, slice); -+ udelay(1); -+ pcie_phy_load_disable(pcie_port, slice); -+ } -+} -+ -+static void -+pcie_phy_tx2_modulation(int pcie_port) -+{ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); -+ mdelay(1); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); -+} -+ -+static void -+pcie_phy_tx1_modulation(int pcie_port) -+{ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); -+ mdelay(1); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); -+} -+ -+static void -+pcie_phy_tx_modulation_war(int pcie_port) -+{ -+ int i; -+ -+#define PCIE_PHY_MODULATION_NUM 5 -+ for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { -+ pcie_phy_tx2_modulation(pcie_port); -+ pcie_phy_tx1_modulation(pcie_port); -+ } -+#undef PCIE_PHY_MODULATION_NUM -+} -+ -+void -+pcie_phy_clock_mode_setup(int pcie_port) -+{ -+ pcie_pdi_big_endian(pcie_port); -+ -+ /* Enable PDI to access PCIe PHY register */ -+ pcie_pdi_pmu_enable(pcie_port); -+ -+ /* Configure PLL and PHY clock */ -+ pcie_phy_comm_setup(pcie_port); -+ -+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+ pcie_phy_36mhz_mode_setup(pcie_port); -+#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) -+ pcie_phy_36mhz_ssc_mode_setup(pcie_port); -+#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) -+ pcie_phy_25mhz_mode_setup(pcie_port); -+#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) -+ pcie_phy_100mhz_mode_setup(pcie_port); -+#else -+ #error "PCIE PHY Clock Mode must be chosen first!!!!" -+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ -+ -+ /* Enable PCIe PHY and make PLL setting take effect */ -+ pcie_phy_pmu_enable(pcie_port); -+ -+ /* Check if we are in startup_ready status */ -+ pcie_phy_wait_startup_ready(pcie_port); -+ -+ pcie_phy_load_war(pcie_port); -+ -+ /* Apply TX modulation workarounds */ -+ pcie_phy_tx_modulation_war(pcie_port); -+ -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+} -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_pm.c -@@ -0,0 +1,176 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_pm.c -+** PROJECT : IFX UEIP -+** MODULES : PCIE Root Complex Driver -+** -+** DATE : 21 Dec 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIE Root Complex Driver Power Managment -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 21 Dec,2009 Lei Chuanhua First UEIP release -+*******************************************************************************/ -+/*! -+ \defgroup IFX_PCIE_PM Power Management functions -+ \ingroup IFX_PCIE -+ \brief IFX PCIE Root Complex Driver power management functions -+*/ -+ -+/*! -+ \file ifxmips_pcie_pm.c -+ \ingroup IFX_PCIE -+ \brief source file for PCIE Root Complex Driver Power Management -+*/ -+ -+#ifndef EXPORT_SYMTAB -+#define EXPORT_SYMTAB -+#endif -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif /* AUTOCONF_INCLUDED */ -+#include -+#include -+#include -+#include -+#include -+ -+/* Project header */ -+#include -+#include -+#include -+#include -+#include "ifxmips_pcie_pm.h" -+ -+/** -+ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) -+ * \brief the callback function to request pmcu state in the power management hardware-dependent module -+ * -+ * \param pmcuState This parameter is a PMCU state. -+ * -+ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully -+ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. -+ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state -+ * \ingroup IFX_PCIE_PM -+ */ -+static IFX_PMCU_RETURN_t -+ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) -+{ -+ switch(pmcuState) -+ { -+ case IFX_PMCU_STATE_D0: -+ return IFX_PMCU_RETURN_SUCCESS; -+ case IFX_PMCU_STATE_D1: // Not Applicable -+ return IFX_PMCU_RETURN_DENIED; -+ case IFX_PMCU_STATE_D2: // Not Applicable -+ return IFX_PMCU_RETURN_DENIED; -+ case IFX_PMCU_STATE_D3: // Module clock gating and Power gating -+ return IFX_PMCU_RETURN_SUCCESS; -+ default: -+ return IFX_PMCU_RETURN_DENIED; -+ } -+} -+ -+/** -+ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) -+ * \brief the callback function to get pmcu state in the power management hardware-dependent module -+ -+ * \param pmcuState Pointer to return power state. -+ * -+ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully -+ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. -+ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state -+ * \ingroup IFX_PCIE_PM -+ */ -+static IFX_PMCU_RETURN_t -+ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) -+{ -+ return IFX_PMCU_RETURN_SUCCESS; -+} -+ -+/** -+ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) -+ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule -+ * -+ * \param pmcuModule Module -+ * \param newState New state -+ * \param oldState Old state -+ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully -+ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. -+ * \ingroup IFX_PCIE_PM -+ */ -+static IFX_PMCU_RETURN_t -+ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) -+{ -+ return IFX_PMCU_RETURN_SUCCESS; -+} -+ -+/** -+ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) -+ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule -+ * -+ * \param pmcuModule Module -+ * \param newState New state -+ * \param oldState Old state -+ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully -+ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. -+ * \ingroup IFX_PCIE_PM -+ */ -+static IFX_PMCU_RETURN_t -+ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) -+{ -+ return IFX_PMCU_RETURN_SUCCESS; -+} -+ -+/** -+ * \fn static void ifx_pcie_pmcu_init(void) -+ * \brief Register with central PMCU module -+ * \return none -+ * \ingroup IFX_PCIE_PM -+ */ -+void -+ifx_pcie_pmcu_init(void) -+{ -+ IFX_PMCU_REGISTER_t pmcuRegister; -+ -+ /* XXX, hook driver context */ -+ -+ /* State function register */ -+ memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t)); -+ pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; -+ pmcuRegister.pmcuModuleNr = 0; -+ pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change; -+ pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get; -+ pmcuRegister.pre = ifx_pcie_pmcu_prechange; -+ pmcuRegister.post= ifx_pcie_pmcu_postchange; -+ ifx_pmcu_register(&pmcuRegister); -+} -+ -+/** -+ * \fn static void ifx_pcie_pmcu_exit(void) -+ * \brief Unregister with central PMCU module -+ * -+ * \return none -+ * \ingroup IFX_PCIE_PM -+ */ -+void -+ifx_pcie_pmcu_exit(void) -+{ -+ IFX_PMCU_REGISTER_t pmcuUnRegister; -+ -+ /* XXX, hook driver context */ -+ -+ pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; -+ pmcuUnRegister.pmcuModuleNr = 0; -+ ifx_pmcu_unregister(&pmcuUnRegister); -+} -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_pm.h -@@ -0,0 +1,36 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_pm.h -+** PROJECT : IFX UEIP -+** MODULES : PCIe Root Complex Driver -+** -+** DATE : 21 Dec 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver Power Managment -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 21 Dec,2009 Lei Chuanhua First UEIP release -+*******************************************************************************/ -+/*! -+ \file ifxmips_pcie_pm.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe Root Complex Driver Power Management -+*/ -+ -+#ifndef IFXMIPS_PCIE_PM_H -+#define IFXMIPS_PCIE_PM_H -+ -+void ifx_pcie_pmcu_init(void); -+void ifx_pcie_pmcu_exit(void); -+ -+#endif /* IFXMIPS_PCIE_PM_H */ -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_reg.h -@@ -0,0 +1,1001 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_reg.h -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+#ifndef IFXMIPS_PCIE_REG_H -+#define IFXMIPS_PCIE_REG_H -+/*! -+ \file ifxmips_pcie_reg.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe module register definition -+*/ -+/* PCIe Address Mapping Base */ -+#define PCIE_CFG_PHY_BASE 0x1D000000UL -+#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) -+#define PCIE_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE_MEM_PHY_BASE 0x1C000000UL -+#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) -+#define PCIE_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) -+ -+#define PCIE_IO_PHY_BASE 0x1D800000UL -+#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) -+#define PCIE_IO_SIZE (1 * 1024 * 1024) -+#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) -+ -+#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) -+#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) -+#define PCIE_MSI_PHY_BASE 0x1F600000UL -+ -+#define PCIE_PDI_PHY_BASE 0x1F106800UL -+#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) -+#define PCIE_PDI_SIZE 0x400 -+ -+#define PCIE1_CFG_PHY_BASE 0x19000000UL -+#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) -+#define PCIE1_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE1_MEM_PHY_BASE 0x18000000UL -+#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) -+#define PCIE1_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) -+ -+#define PCIE1_IO_PHY_BASE 0x19800000UL -+#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) -+#define PCIE1_IO_SIZE (1 * 1024 * 1024) -+#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) -+ -+#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) -+#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) -+#define PCIE1_MSI_PHY_BASE 0x1F400000UL -+ -+#define PCIE1_PDI_PHY_BASE 0x1F700400UL -+#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) -+#define PCIE1_PDI_SIZE 0x400 -+ -+#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) -+#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) -+#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) -+#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) -+#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) -+#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) -+#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) -+#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) -+ -+/* PCIe Application Logic Register */ -+/* RC Core Control Register */ -+#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) -+/* This should be enabled after initializing configuratin registers -+ * Also should check link status retraining bit -+ */ -+#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ -+ -+/* RC Core Debug Register */ -+#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) -+#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 -+ -+#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ -+#define PCIE_RC_DR_PM_DEV_STATE_S 9 -+ -+#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ -+#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ -+#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ -+ -+/* Current Power State Definition */ -+enum { -+ PCIE_RC_DR_D0 = 0, -+ PCIE_RC_DR_D1, /* Not supported */ -+ PCIE_RC_DR_D2, /* Not supported */ -+ PCIE_RC_DR_D3, -+ PCIE_RC_DR_UN, -+}; -+ -+/* PHY Link Status Register */ -+#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) -+#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ -+ -+/* Electromechanical Control Register */ -+#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) -+#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ -+#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ -+#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ -+#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ -+#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ -+#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ -+#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ -+#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ -+ -+/* Interrupt Status Register */ -+#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) -+#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ -+#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ -+#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ -+#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ -+#define PCIE_IR_SR_AHB_LU_ERR_S 4 -+#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ -+#define PCIE_IR_SR_INT_MSG_NUM_S 9 -+#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 -+ -+/* Message Control Register */ -+#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) -+#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ -+#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ -+ -+#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) -+ -+/* Vendor-Defined Message Requester ID Register */ -+#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) -+#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF -+#define PCIE_VDM_RID_VDMRID_S 0 -+ -+/* ASPM Control Register */ -+#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) -+#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ -+#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ -+#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ -+ -+/* Vendor Message DW0 Register */ -+#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) -+#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ -+#define PCIE_VM_MSG_DW0_TYPE_S 0 -+#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ -+#define PCIE_VM_MSG_DW0_FORMAT_S 5 -+#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ -+#define PCIE_VM_MSG_DW0_TC_S 12 -+#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ -+#define PCIE_VM_MSG_DW0_ATTR_S 18 -+#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ -+#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ -+#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ -+#define PCIE_VM_MSG_DW0_LEN_S 22 -+ -+/* Format Definition */ -+enum { -+ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ -+ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ -+ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ -+ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ -+}; -+ -+/* Traffic Class Definition */ -+enum { -+ PCIE_VM_MSG_TC0 = 0, -+ PCIE_VM_MSG_TC1, -+ PCIE_VM_MSG_TC2, -+ PCIE_VM_MSG_TC3, -+ PCIE_VM_MSG_TC4, -+ PCIE_VM_MSG_TC5, -+ PCIE_VM_MSG_TC6, -+ PCIE_VM_MSG_TC7, -+}; -+ -+/* Attributes Definition */ -+enum { -+ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ -+ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ -+ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ -+ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ -+}; -+ -+/* Payload Size Definition */ -+#define PCIE_VM_MSG_LEN_MIN 0 -+#define PCIE_VM_MSG_LEN_MAX 1024 -+ -+/* Vendor Message DW1 Register */ -+#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) -+#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ -+#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 -+#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ -+#define PCIE_VM_MSG_DW1_CODE_S 16 -+#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ -+#define PCIE_VM_MSG_DW1_TAG_S 24 -+ -+#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) -+#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) -+ -+/* Vendor Message Request Register */ -+#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) -+#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ -+ -+ -+/* AHB Slave Side Band Control Register */ -+#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) -+#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ -+#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ -+#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ -+#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ -+#define PCIE_AHB_SSB_REQ_ATTR_S 3 -+#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ -+#define PCIE_AHB_SSB_REQ_TC_S 5 -+ -+/* AHB Master SideBand Ctrl Register */ -+#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) -+#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ -+#define PCIE_AHB_MSB_RESP_ATTR_S 0 -+#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ -+#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ -+#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ -+#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 -+ -+/* AHB Control Register, fixed bus enumeration exception */ -+#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) -+#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 -+ -+/* Interrupt Enalbe Register */ -+#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) -+#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) -+#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) -+ -+/* PCIe interrupt enable/control/capture register definition */ -+#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ -+#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ -+#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ -+#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ -+#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ -+#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ -+#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ -+#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ -+#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ -+#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ -+#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ -+#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ -+#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ -+#define PCIE_IRN_INTA 0x00002000 /* INTA */ -+#define PCIE_IRN_INTB 0x00004000 /* INTB */ -+#define PCIE_IRN_INTC 0x00008000 /* INTC */ -+#define PCIE_IRN_INTD 0x00010000 /* INTD */ -+#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ -+ -+#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ -+ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ -+ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ -+ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ -+ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) -+/* PCIe RC Configuration Register */ -+#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) -+ -+/* Bit definition from pci_reg.h */ -+#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) -+#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) -+#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ -+/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ -+#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ -+#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ -+ -+#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ -+/* Bus Number Register bits */ -+#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF -+#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 -+#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 -+#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 -+#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 -+#define PCIE_PNR_SUB_BUS_NUM_S 16 -+ -+/* IO Base/Limit Register bits */ -+#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ -+#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 -+#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 -+#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 -+#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 -+ -+/* Non-prefetchable Memory Base/Limit Register bit */ -+#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ -+#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 -+#define PCIE_MBML_MEM_BASE_ADDR_S 4 -+#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 -+#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 -+ -+/* Prefetchable Memory Base/Limit Register bit */ -+#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ -+#define PCIE_PMBL_64BIT_ADDR 0x00000001 -+#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 -+#define PCIE_PMBL_UPPER_12BIT_S 4 -+#define PCIE_PMBL_E64MA 0x00010000 -+#define PCIE_PMBL_END_ADDR 0xFFF00000 -+#define PCIE_PMBL_END_ADDR_S 20 -+#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ -+#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ -+ -+/* I/O Base/Limit Upper 16 bits register */ -+#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 -+ -+#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) -+#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) -+ -+/* Interrupt and Secondary Bridge Control Register */ -+#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) -+ -+#define PCIE_INTRBCTRL_INT_LINE 0x000000FF -+#define PCIE_INTRBCTRL_INT_LINE_S 0 -+#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 -+#define PCIE_INTRBCTRL_INT_PIN_S 8 -+#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ -+#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ -+#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ -+#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ -+#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ -+#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ -+/* Others are read only */ -+enum { -+ PCIE_INTRBCTRL_INT_NON = 0, -+ PCIE_INTRBCTRL_INTA, -+ PCIE_INTRBCTRL_INTB, -+ PCIE_INTRBCTRL_INTC, -+ PCIE_INTRBCTRL_INTD, -+}; -+ -+#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) -+ -+/* Power Management Control and Status Register */ -+#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) -+ -+#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ -+#define PCIE_PM_CSR_POWER_STATE_S 0 -+#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ -+#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ -+#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ -+ -+/* MSI Capability Register for EP */ -+#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) -+ -+#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ -+#define PCIE_MCAPR_MSI_CAP_ID_S 0 -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 -+#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 -+#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ -+#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 -+#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ -+ -+/* MSI Message Address Register */ -+#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) -+ -+#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ -+ -+/* MSI Message Upper Address Register */ -+#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) -+ -+/* MSI Message Data Register */ -+#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) -+ -+#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ -+#define PCIE_MD_DATA_S 0 -+ -+/* PCI Express Capability Register */ -+#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) -+ -+#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ -+#define PCIE_XCAP_ID_S 0 -+#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_XCAP_NEXT_CAP_S 8 -+#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ -+#define PCIE_XCAP_VER_S 16 -+#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ -+#define PCIE_XCAP_DEV_PORT_TYPE_S 20 -+#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ -+#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ -+#define PCIE_XCAP_MSG_INT_NUM_S 25 -+ -+/* Device Capability Register */ -+#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) -+ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 -+#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ -+#define PCIE_DCAP_PHANTOM_FUNC_S 3 -+#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ -+#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ -+#define PCIE_DCAP_EP_L0S_LATENCY_S 6 -+#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ -+#define PCIE_DCAP_EP_L1_LATENCY_S 9 -+#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ -+ -+/* Maximum payload size supported */ -+enum { -+ PCIE_MAX_PAYLOAD_128 = 0, -+ PCIE_MAX_PAYLOAD_256, -+ PCIE_MAX_PAYLOAD_512, -+ PCIE_MAX_PAYLOAD_1024, -+ PCIE_MAX_PAYLOAD_2048, -+ PCIE_MAX_PAYLOAD_4096, -+}; -+ -+/* Device Control and Status Register */ -+#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) -+ -+#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ -+#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ -+#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ -+#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 -+#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ -+#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ -+#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ -+#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 -+#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ -+#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ -+#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ -+#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ -+#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ -+#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ -+ -+#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ -+ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ -+ PCIE_DCTLSYS_UR_REQ_EN) -+ -+/* Link Capability Register */ -+#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) -+#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ -+#define PCIE_LCAP_MAX_LINK_SPEED_S 0 -+#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ -+#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 -+#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ -+#define PCIE_LCAP_ASPM_LEVEL_S 10 -+#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ -+#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 -+#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ -+#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 -+#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ -+#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ -+#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ -+#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ -+#define PCIE_LCAP_PORT_NUM_S 24 -+ -+/* Maximum Length width definition */ -+#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 -+#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ -+#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 -+#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 -+#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 -+#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C -+#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 -+#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 -+ -+/* Active State Link PM definition */ -+enum { -+ PCIE_ASPM_RES0 = 0, -+ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ -+ PCIE_ASPM_RES1, -+ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ -+}; -+ -+/* L0s Exit Latency definition */ -+enum { -+ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ -+ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ -+ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ -+ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ -+ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ -+ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ -+ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ -+ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ -+}; -+ -+/* L1 Exit Latency definition */ -+enum { -+ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ -+ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ -+ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ -+ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ -+ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ -+ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ -+ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ -+ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ -+}; -+ -+/* Link Control and Status Register */ -+#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) -+#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ -+#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 -+#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ -+#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ -+#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ -+#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ -+#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ -+#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ -+#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ -+#define PCIE_LCTLSTS_LINK_SPEED_S 16 -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 -+#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ -+#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ -+#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ -+ -+/* Slot Capabilities Register */ -+#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) -+ -+/* Slot Capabilities */ -+#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) -+ -+/* Root Control and Capability Register */ -+#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) -+#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ -+#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ -+#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ -+#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ -+#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ -+ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) -+/* Root Status Register */ -+#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) -+#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ -+#define PCIE_RSTS_PME_REQ_ID_S 0 -+#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ -+#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ -+ -+/* PCI Express Enhanced Capability Header */ -+#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) -+#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ -+#define PCIE_ENHANCED_CAP_ID_S 0 -+#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ -+#define PCIE_ENHANCED_CAP_VER_S 16 -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 -+ -+/* Uncorrectable Error Status Register */ -+#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) -+#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ -+#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ -+#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ -+#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ -+#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ -+#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ -+#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ -+#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ -+#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ -+#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ -+#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ -+#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ -+ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ -+ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ -+ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) -+ -+/* Uncorrectable Error Mask Register, Mask means no report */ -+#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) -+ -+/* Uncorrectable Error Severity Register */ -+#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) -+ -+/* Correctable Error Status Register */ -+#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) -+#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ -+#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ -+#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ -+#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ -+#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ -+#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ -+#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ -+ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) -+ -+/* Correctable Error Mask Register */ -+#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) -+ -+/* Advanced Error Capabilities and Control Register */ -+#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) -+#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ -+#define PCIE_AECCR_FIRST_ERR_PTR_S 0 -+#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ -+#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ -+#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ -+#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ -+ -+/* Header Log Register 1 */ -+#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) -+ -+/* Header Log Register 2 */ -+#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) -+ -+/* Header Log Register 3 */ -+#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) -+ -+/* Header Log Register 4 */ -+#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) -+ -+/* Root Error Command Register */ -+#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) -+#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ -+#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ -+#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ -+ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) -+ -+/* Root Error Status Register */ -+#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) -+#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ -+#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ -+#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ -+#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ -+#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ -+#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_RESR_AER_INT_MSG_NUM_S 27 -+ -+/* Error Source Indentification Register */ -+#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 -+ -+/* VC Enhanced Capability Header */ -+#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) -+ -+/* Port VC Capability Register */ -+#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) -+#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ -+#define PCIE_PVC1_EXT_VC_CNT_S 0 -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 -+#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ -+#define PCIE_PVC1_REF_CLK_S 8 -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 -+ -+/* Extended Virtual Channel Count Defintion */ -+#define PCIE_EXT_VC_CNT_MIN 0 -+#define PCIE_EXT_VC_CNT_MAX 7 -+ -+/* Port Arbitration Table Entry Size Definition */ -+enum { -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, -+}; -+ -+/* Port VC Capability Register 2 */ -+#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) -+#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ -+#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_PVC2_VC_ARB_WRR 0x0000000F -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 -+ -+/* Port VC Control and Status Register */ -+#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) -+#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ -+#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ -+#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 -+#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ -+ -+/* VC0 Resource Capability Register */ -+#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) -+#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ -+#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ -+ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ -+ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) -+ -+#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 -+ -+/* VC0 Resource Control Register */ -+#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) -+#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ -+#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ -+#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ -+#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ -+#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ -+#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ -+#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ -+#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ -+#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ -+ -+#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 -+#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ -+#define PCIE_VC0_RC0_VC_ID_S 24 -+#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ -+ -+/* VC0 Resource Status Register */ -+#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) -+#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ -+#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ -+ -+/* Ack Latency Timer and Replay Timer Register */ -+#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 -+ -+/* Other Message Register */ -+#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) -+ -+/* Port Force Link Register */ -+#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) -+#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ -+#define PCIE_PFLR_LINK_NUM_S 0 -+#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ -+#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ -+#define PCIE_PFLR_LINK_STATE_S 16 -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 -+ -+/* Ack Frequency Register */ -+#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) -+#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ -+#define PCIE_AFR_AF_S 0 -+#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ -+#define PCIE_AFR_FTS_NUM_S 8 -+#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ -+#define PCIE_AFR_COM_FTS_NUM_S 16 -+#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ -+#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 -+#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ -+#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 -+#define PCIE_AFR_FTS_NUM_DEFAULT 32 -+#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 -+#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 -+ -+/* Port Link Control Register */ -+#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) -+#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ -+#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ -+#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ -+#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ -+#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ -+#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ -+#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ -+#define PCIE_PLCR_LINK_MODE_S 16 -+#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ -+ -+/* Lane Skew Register */ -+#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) -+#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ -+#define PCIE_LSR_LANE_SKEW_NUM_S 0 -+#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ -+#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ -+#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ -+ -+/* Symbol Number Register */ -+#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) -+#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ -+#define PCIE_SNR_TS_S 0 -+#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ -+#define PCIE_SNR_SKP_S 8 -+#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ -+#define PCIE_SNR_REPLAY_TIMER_S 14 -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 -+#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ -+#define PCIE_SNR_FC_TIMER_S 28 -+ -+/* Symbol Timer Register and Filter Mask Register 1 */ -+#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) -+#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ -+#define PCIE_STRFMR_SKP_INTERVAL_S 0 -+#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ -+#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ -+#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ -+#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ -+#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ -+#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ -+#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ -+#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ -+#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ -+#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ -+#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ -+#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ -+ -+#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ -+ -+/* Filter Masker Register 2 */ -+#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) -+#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ -+#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ -+ -+/* Debug Register 0 */ -+#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) -+ -+/* Debug Register 1 */ -+#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) -+ -+/* Transmit Posted FC Credit Status Register */ -+#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Non-Posted FC Credit Status */ -+#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Complete FC Credit Status Register */ -+#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 -+ -+/* Queue Status Register */ -+#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) -+#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ -+#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ -+#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ -+ -+/* VC Transmit Arbitration Register 1 */ -+#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) -+#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ -+ -+/* VC Transmit Arbitration Register 2 */ -+#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) -+#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ -+ -+/* VC0 Posted Receive Queue Control Register */ -+#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 -+#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ -+#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ -+ -+/* VC0 Non-Posted Receive Queue Control */ -+#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 -+ -+/* VC0 Completion Receive Queue Control */ -+#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 -+ -+/* Applicable to the above three registers */ -+enum { -+ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, -+ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, -+ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, -+}; -+ -+/* VC0 Posted Buffer Depth Register */ -+#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Non-Posted Buffer Depth Register */ -+#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Completion Buffer Depth Register */ -+#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 -+ -+/* PHY Status Register, all zeros in VR9 */ -+#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) -+ -+/* PHY Control Register, all zeros in VR9 */ -+#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) -+ -+/* -+ * PCIe PDI PHY register definition, suppose all the following -+ * stuff is confidential. -+ * XXX, detailed bit definition -+ */ -+#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) -+#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) -+#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) -+#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) -+#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) -+#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) -+#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) -+#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) -+#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) -+#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) -+#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) -+ -+#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) -+#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) -+#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) -+#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) -+#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) -+#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) -+#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) -+#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) -+ -+#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) -+#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) -+#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) -+#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) -+#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) -+#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) -+#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) -+ -+#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) -+#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) -+#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) -+#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) -+#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) -+ -+/* Interrupt related stuff */ -+#define PCIE_LEGACY_DISABLE 0 -+#define PCIE_LEGACY_INTA 1 -+#define PCIE_LEGACY_INTB 2 -+#define PCIE_LEGACY_INTC 3 -+#define PCIE_LEGACY_INTD 4 -+#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD -+ -+#endif /* IFXMIPS_PCIE_REG_H */ -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_vr9.h -@@ -0,0 +1,269 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ *****************************************************************************/ -+/*! -+ \file ifxmips_pcie_vr9.h -+ \ingroup IFX_PCIE -+ \brief PCIe RC driver vr9 specific file -+*/ -+ -+#ifndef IFXMIPS_PCIE_VR9_H -+#define IFXMIPS_PCIE_VR9_H -+ -+#include -+#include -+ -+#include -+#include -+ -+#define IFX_PCIE_GPIO_RESET 494 -+ -+#define IFX_REG_R32 ltq_r32 -+#define IFX_REG_W32 ltq_w32 -+#define CONFIG_IFX_PCIE_HW_SWAP -+#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ -+#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ -+#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ -+#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+ -+#define IFX_PMU1_MODULE_PCIE_PHY (0) -+#define IFX_PMU1_MODULE_PCIE_CTRL (1) -+#define IFX_PMU1_MODULE_PDI (4) -+#define IFX_PMU1_MODULE_MSI (5) -+ -+#define IFX_PMU_MODULE_PCIE_L0_CLK (31) -+ -+ -+#define IFX_GPIO (KSEG1 | 0x1E100B00) -+#define ALT0 ((volatile u32*)(IFX_GPIO + 0x007c)) -+#define ALT1 ((volatile u32*)(IFX_GPIO + 0x0080)) -+#define OD ((volatile u32*)(IFX_GPIO + 0x0084)) -+#define DIR ((volatile u32*)(IFX_GPIO + 0x0078)) -+#define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) -+ -+ -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+ -+ gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); -+ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); -+ gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -+ -+/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ -+} -+ -+static inline void pcie_ahb_pmu_setup(void) -+{ -+ /* Enable AHB bus master/slave */ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "ahb"); -+ clk_enable(clk); -+ -+ //AHBM_PMU_SETUP(IFX_PMU_ENABLE); -+ //AHBS_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline void pcie_rcu_endian_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg |= IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#else -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg &= ~IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); -+} -+ -+static inline void pcie_phy_pmu_enable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "phy"); -+ clk_enable(clk); -+ -+ //PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline void pcie_phy_pmu_disable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "phy"); -+ clk_disable(clk); -+ -+// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); -+} -+ -+static inline void pcie_pdi_big_endian(int pcie_port) -+{ -+ u32 reg; -+ -+ /* SRAM2PDI endianness control. */ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+ /* Config AHB->PCIe and PDI endianness */ -+ reg |= IFX_RCU_AHB_BE_PCIE_PDI; -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+} -+ -+static inline void pcie_pdi_pmu_enable(int pcie_port) -+{ -+ /* Enable PDI to access PCIe PHY register */ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "pdi"); -+ clk_enable(clk); -+ //PDI_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline void pcie_core_rst_assert(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ -+ /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ -+ reg |= 0x00400000; -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_core_rst_deassert(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Make sure one micro-second delay */ -+ udelay(1); -+ -+ /* Reset PCIe PHY & Core, bit 22 */ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ reg &= ~0x00400000; -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_phy_rst_assert(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ reg |= 0x00001000; /* Bit 12 */ -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_phy_rst_deassert(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Make sure one micro-second delay */ -+ udelay(1); -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ reg &= ~0x00001000; /* Bit 12 */ -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_device_rst_assert(int pcie_port) -+{ -+ gpio_set_value(IFX_PCIE_GPIO_RESET, 0); -+// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+} -+ -+static inline void pcie_device_rst_deassert(int pcie_port) -+{ -+ mdelay(100); -+ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); -+// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -+ //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+} -+ -+static inline void pcie_core_pmu_setup(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "ctl"); -+ clk_enable(clk); -+ clk = clk_get_sys("1d900000.pcie", "bus"); -+ clk_enable(clk); -+ -+ /* PCIe Core controller enabled */ -+// PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE); -+ -+ /* Enable PCIe L0 Clock */ -+// PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline void pcie_msi_init(int pcie_port) -+{ -+ struct clk *clk; -+ pcie_msi_pic_init(pcie_port); -+ clk = clk_get_sys("ltq_pcie", "msi"); -+ clk_enable(clk); -+// MSI_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline u32 -+ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) -+{ -+ u32 tbus_number = bus_number; -+ -+#ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tbus_number -= pcibios_1st_host_bus_nr(); -+ } -+#endif /* CONFIG_PCI_LANTIQ */ -+ return tbus_number; -+} -+ -+static inline u32 -+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) -+{ -+ struct pci_dev *pdev; -+ u32 tvalue = value; -+ -+ /* Sanity check */ -+ pdev = pci_get_slot(bus, devfn); -+ if (pdev == NULL) { -+ return tvalue; -+ } -+ -+ /* Only care about PCI bridge */ -+ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { -+ return tvalue; -+ } -+ -+ if (read) { /* Read hack */ -+ #ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); -+ } -+ #endif /* CONFIG_PCI_LANTIQ */ -+ } -+ else { /* Write hack */ -+ #ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); -+ } -+ #endif -+ } -+ return tvalue; -+} -+ -+#endif /* IFXMIPS_PCIE_VR9_H */ -+ ---- a/arch/mips/pci/pci-legacy.c -+++ b/arch/mips/pci/pci-legacy.c -@@ -311,3 +311,30 @@ char *__init pcibios_setup(char *str) - return pcibios_plat_setup(str); - return str; - } -+ -+int pcibios_host_nr(void) -+{ -+ int count = 0; -+ struct pci_controller *hose; -+ list_for_each_entry(hose, &controllers, list) { -+ count++; -+ } -+ return count; -+} -+EXPORT_SYMBOL(pcibios_host_nr); -+ -+int pcibios_1st_host_bus_nr(void) -+{ -+ int bus_nr = 0; -+ struct pci_controller *hose; -+ -+ hose = list_first_entry_or_null(&controllers, struct pci_controller, list); -+ -+ if (hose != NULL) { -+ if (hose->bus != NULL) { -+ bus_nr = hose->bus->number + 1; -+ } -+ } -+ return bus_nr; -+} -+EXPORT_SYMBOL(pcibios_1st_host_bus_nr); ---- /dev/null -+++ b/arch/mips/pci/pcie-lantiq.h -@@ -0,0 +1,1305 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_reg.h -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+#ifndef IFXMIPS_PCIE_REG_H -+#define IFXMIPS_PCIE_REG_H -+#include -+#include -+#include -+#include -+/*! -+ \file ifxmips_pcie_reg.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe module register definition -+*/ -+/* PCIe Address Mapping Base */ -+#define PCIE_CFG_PHY_BASE 0x1D000000UL -+#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) -+#define PCIE_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE_MEM_PHY_BASE 0x1C000000UL -+#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) -+#define PCIE_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) -+ -+#define PCIE_IO_PHY_BASE 0x1D800000UL -+#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) -+#define PCIE_IO_SIZE (1 * 1024 * 1024) -+#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) -+ -+#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) -+#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) -+#define PCIE_MSI_PHY_BASE 0x1F600000UL -+ -+#define PCIE_PDI_PHY_BASE 0x1F106800UL -+#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) -+#define PCIE_PDI_SIZE 0x400 -+ -+#define PCIE1_CFG_PHY_BASE 0x19000000UL -+#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) -+#define PCIE1_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE1_MEM_PHY_BASE 0x18000000UL -+#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) -+#define PCIE1_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) -+ -+#define PCIE1_IO_PHY_BASE 0x19800000UL -+#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) -+#define PCIE1_IO_SIZE (1 * 1024 * 1024) -+#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) -+ -+#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) -+#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) -+#define PCIE1_MSI_PHY_BASE 0x1F400000UL -+ -+#define PCIE1_PDI_PHY_BASE 0x1F700400UL -+#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) -+#define PCIE1_PDI_SIZE 0x400 -+ -+#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) -+#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) -+#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) -+#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) -+#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) -+#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) -+#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) -+#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) -+ -+/* PCIe Application Logic Register */ -+/* RC Core Control Register */ -+#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) -+/* This should be enabled after initializing configuratin registers -+ * Also should check link status retraining bit -+ */ -+#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ -+ -+/* RC Core Debug Register */ -+#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) -+#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 -+ -+#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ -+#define PCIE_RC_DR_PM_DEV_STATE_S 9 -+ -+#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ -+#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ -+#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ -+ -+/* Current Power State Definition */ -+enum { -+ PCIE_RC_DR_D0 = 0, -+ PCIE_RC_DR_D1, /* Not supported */ -+ PCIE_RC_DR_D2, /* Not supported */ -+ PCIE_RC_DR_D3, -+ PCIE_RC_DR_UN, -+}; -+ -+/* PHY Link Status Register */ -+#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) -+#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ -+ -+/* Electromechanical Control Register */ -+#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) -+#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ -+#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ -+#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ -+#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ -+#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ -+#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ -+#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ -+#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ -+ -+/* Interrupt Status Register */ -+#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) -+#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ -+#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ -+#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ -+#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ -+#define PCIE_IR_SR_AHB_LU_ERR_S 4 -+#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ -+#define PCIE_IR_SR_INT_MSG_NUM_S 9 -+#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 -+ -+/* Message Control Register */ -+#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) -+#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ -+#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ -+ -+#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) -+ -+/* Vendor-Defined Message Requester ID Register */ -+#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) -+#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF -+#define PCIE_VDM_RID_VDMRID_S 0 -+ -+/* ASPM Control Register */ -+#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) -+#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ -+#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ -+#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ -+ -+/* Vendor Message DW0 Register */ -+#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) -+#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ -+#define PCIE_VM_MSG_DW0_TYPE_S 0 -+#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ -+#define PCIE_VM_MSG_DW0_FORMAT_S 5 -+#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ -+#define PCIE_VM_MSG_DW0_TC_S 12 -+#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ -+#define PCIE_VM_MSG_DW0_ATTR_S 18 -+#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ -+#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ -+#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ -+#define PCIE_VM_MSG_DW0_LEN_S 22 -+ -+/* Format Definition */ -+enum { -+ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ -+ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ -+ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ -+ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ -+}; -+ -+/* Traffic Class Definition */ -+enum { -+ PCIE_VM_MSG_TC0 = 0, -+ PCIE_VM_MSG_TC1, -+ PCIE_VM_MSG_TC2, -+ PCIE_VM_MSG_TC3, -+ PCIE_VM_MSG_TC4, -+ PCIE_VM_MSG_TC5, -+ PCIE_VM_MSG_TC6, -+ PCIE_VM_MSG_TC7, -+}; -+ -+/* Attributes Definition */ -+enum { -+ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ -+ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ -+ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ -+ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ -+}; -+ -+/* Payload Size Definition */ -+#define PCIE_VM_MSG_LEN_MIN 0 -+#define PCIE_VM_MSG_LEN_MAX 1024 -+ -+/* Vendor Message DW1 Register */ -+#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) -+#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ -+#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 -+#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ -+#define PCIE_VM_MSG_DW1_CODE_S 16 -+#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ -+#define PCIE_VM_MSG_DW1_TAG_S 24 -+ -+#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) -+#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) -+ -+/* Vendor Message Request Register */ -+#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) -+#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ -+ -+ -+/* AHB Slave Side Band Control Register */ -+#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) -+#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ -+#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ -+#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ -+#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ -+#define PCIE_AHB_SSB_REQ_ATTR_S 3 -+#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ -+#define PCIE_AHB_SSB_REQ_TC_S 5 -+ -+/* AHB Master SideBand Ctrl Register */ -+#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) -+#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ -+#define PCIE_AHB_MSB_RESP_ATTR_S 0 -+#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ -+#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ -+#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ -+#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 -+ -+/* AHB Control Register, fixed bus enumeration exception */ -+#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) -+#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 -+ -+/* Interrupt Enalbe Register */ -+#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) -+#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) -+#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) -+ -+/* PCIe interrupt enable/control/capture register definition */ -+#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ -+#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ -+#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ -+#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ -+#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ -+#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ -+#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ -+#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ -+#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ -+#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ -+#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ -+#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ -+#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ -+#define PCIE_IRN_INTA 0x00002000 /* INTA */ -+#define PCIE_IRN_INTB 0x00004000 /* INTB */ -+#define PCIE_IRN_INTC 0x00008000 /* INTC */ -+#define PCIE_IRN_INTD 0x00010000 /* INTD */ -+#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ -+ -+#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ -+ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ -+ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ -+ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ -+ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) -+/* PCIe RC Configuration Register */ -+#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) -+ -+/* Bit definition from pci_reg.h */ -+#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) -+#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) -+#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ -+/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ -+#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ -+#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ -+ -+#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ -+/* Bus Number Register bits */ -+#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF -+#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 -+#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 -+#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 -+#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 -+#define PCIE_PNR_SUB_BUS_NUM_S 16 -+ -+/* IO Base/Limit Register bits */ -+#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ -+#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 -+#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 -+#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 -+#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 -+ -+/* Non-prefetchable Memory Base/Limit Register bit */ -+#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ -+#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 -+#define PCIE_MBML_MEM_BASE_ADDR_S 4 -+#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 -+#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 -+ -+/* Prefetchable Memory Base/Limit Register bit */ -+#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ -+#define PCIE_PMBL_64BIT_ADDR 0x00000001 -+#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 -+#define PCIE_PMBL_UPPER_12BIT_S 4 -+#define PCIE_PMBL_E64MA 0x00010000 -+#define PCIE_PMBL_END_ADDR 0xFFF00000 -+#define PCIE_PMBL_END_ADDR_S 20 -+#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ -+#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ -+ -+/* I/O Base/Limit Upper 16 bits register */ -+#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 -+ -+#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) -+#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) -+ -+/* Interrupt and Secondary Bridge Control Register */ -+#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) -+ -+#define PCIE_INTRBCTRL_INT_LINE 0x000000FF -+#define PCIE_INTRBCTRL_INT_LINE_S 0 -+#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 -+#define PCIE_INTRBCTRL_INT_PIN_S 8 -+#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ -+#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ -+#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ -+#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ -+#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ -+#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ -+/* Others are read only */ -+enum { -+ PCIE_INTRBCTRL_INT_NON = 0, -+ PCIE_INTRBCTRL_INTA, -+ PCIE_INTRBCTRL_INTB, -+ PCIE_INTRBCTRL_INTC, -+ PCIE_INTRBCTRL_INTD, -+}; -+ -+#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) -+ -+/* Power Management Control and Status Register */ -+#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) -+ -+#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ -+#define PCIE_PM_CSR_POWER_STATE_S 0 -+#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ -+#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ -+#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ -+ -+/* MSI Capability Register for EP */ -+#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) -+ -+#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ -+#define PCIE_MCAPR_MSI_CAP_ID_S 0 -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 -+#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 -+#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ -+#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 -+#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ -+ -+/* MSI Message Address Register */ -+#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) -+ -+#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ -+ -+/* MSI Message Upper Address Register */ -+#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) -+ -+/* MSI Message Data Register */ -+#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) -+ -+#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ -+#define PCIE_MD_DATA_S 0 -+ -+/* PCI Express Capability Register */ -+#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) -+ -+#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ -+#define PCIE_XCAP_ID_S 0 -+#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_XCAP_NEXT_CAP_S 8 -+#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ -+#define PCIE_XCAP_VER_S 16 -+#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ -+#define PCIE_XCAP_DEV_PORT_TYPE_S 20 -+#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ -+#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ -+#define PCIE_XCAP_MSG_INT_NUM_S 25 -+ -+/* Device Capability Register */ -+#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) -+ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 -+#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ -+#define PCIE_DCAP_PHANTOM_FUNC_S 3 -+#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ -+#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ -+#define PCIE_DCAP_EP_L0S_LATENCY_S 6 -+#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ -+#define PCIE_DCAP_EP_L1_LATENCY_S 9 -+#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ -+ -+/* Maximum payload size supported */ -+enum { -+ PCIE_MAX_PAYLOAD_128 = 0, -+ PCIE_MAX_PAYLOAD_256, -+ PCIE_MAX_PAYLOAD_512, -+ PCIE_MAX_PAYLOAD_1024, -+ PCIE_MAX_PAYLOAD_2048, -+ PCIE_MAX_PAYLOAD_4096, -+}; -+ -+/* Device Control and Status Register */ -+#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) -+ -+#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ -+#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ -+#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ -+#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 -+#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ -+#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ -+#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ -+#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 -+#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ -+#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ -+#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ -+#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ -+#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ -+#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ -+ -+#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ -+ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ -+ PCIE_DCTLSYS_UR_REQ_EN) -+ -+/* Link Capability Register */ -+#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) -+#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ -+#define PCIE_LCAP_MAX_LINK_SPEED_S 0 -+#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ -+#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 -+#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ -+#define PCIE_LCAP_ASPM_LEVEL_S 10 -+#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ -+#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 -+#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ -+#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 -+#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ -+#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ -+#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ -+#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ -+#define PCIE_LCAP_PORT_NUM_S 24 -+ -+/* Maximum Length width definition */ -+#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 -+#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ -+#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 -+#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 -+#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 -+#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C -+#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 -+#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 -+ -+/* Active State Link PM definition */ -+enum { -+ PCIE_ASPM_RES0 = 0, -+ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ -+ PCIE_ASPM_RES1, -+ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ -+}; -+ -+/* L0s Exit Latency definition */ -+enum { -+ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ -+ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ -+ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ -+ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ -+ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ -+ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ -+ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ -+ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ -+}; -+ -+/* L1 Exit Latency definition */ -+enum { -+ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ -+ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ -+ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ -+ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ -+ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ -+ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ -+ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ -+ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ -+}; -+ -+/* Link Control and Status Register */ -+#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) -+#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ -+#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 -+#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ -+#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ -+#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ -+#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ -+#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ -+#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ -+#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ -+#define PCIE_LCTLSTS_LINK_SPEED_S 16 -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 -+#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ -+#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ -+#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ -+ -+/* Slot Capabilities Register */ -+#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) -+ -+/* Slot Capabilities */ -+#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) -+ -+/* Root Control and Capability Register */ -+#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) -+#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ -+#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ -+#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ -+#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ -+#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ -+ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) -+/* Root Status Register */ -+#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) -+#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ -+#define PCIE_RSTS_PME_REQ_ID_S 0 -+#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ -+#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ -+ -+/* PCI Express Enhanced Capability Header */ -+#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) -+#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ -+#define PCIE_ENHANCED_CAP_ID_S 0 -+#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ -+#define PCIE_ENHANCED_CAP_VER_S 16 -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 -+ -+/* Uncorrectable Error Status Register */ -+#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) -+#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ -+#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ -+#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ -+#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ -+#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ -+#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ -+#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ -+#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ -+#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ -+#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ -+#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ -+#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ -+ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ -+ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ -+ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) -+ -+/* Uncorrectable Error Mask Register, Mask means no report */ -+#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) -+ -+/* Uncorrectable Error Severity Register */ -+#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) -+ -+/* Correctable Error Status Register */ -+#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) -+#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ -+#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ -+#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ -+#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ -+#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ -+#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ -+#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ -+ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) -+ -+/* Correctable Error Mask Register */ -+#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) -+ -+/* Advanced Error Capabilities and Control Register */ -+#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) -+#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ -+#define PCIE_AECCR_FIRST_ERR_PTR_S 0 -+#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ -+#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ -+#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ -+#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ -+ -+/* Header Log Register 1 */ -+#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) -+ -+/* Header Log Register 2 */ -+#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) -+ -+/* Header Log Register 3 */ -+#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) -+ -+/* Header Log Register 4 */ -+#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) -+ -+/* Root Error Command Register */ -+#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) -+#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ -+#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ -+#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ -+ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) -+ -+/* Root Error Status Register */ -+#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) -+#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ -+#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ -+#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ -+#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ -+#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ -+#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_RESR_AER_INT_MSG_NUM_S 27 -+ -+/* Error Source Indentification Register */ -+#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 -+ -+/* VC Enhanced Capability Header */ -+#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) -+ -+/* Port VC Capability Register */ -+#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) -+#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ -+#define PCIE_PVC1_EXT_VC_CNT_S 0 -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 -+#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ -+#define PCIE_PVC1_REF_CLK_S 8 -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 -+ -+/* Extended Virtual Channel Count Defintion */ -+#define PCIE_EXT_VC_CNT_MIN 0 -+#define PCIE_EXT_VC_CNT_MAX 7 -+ -+/* Port Arbitration Table Entry Size Definition */ -+enum { -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, -+}; -+ -+/* Port VC Capability Register 2 */ -+#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) -+#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ -+#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_PVC2_VC_ARB_WRR 0x0000000F -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 -+ -+/* Port VC Control and Status Register */ -+#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) -+#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ -+#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ -+#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 -+#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ -+ -+/* VC0 Resource Capability Register */ -+#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) -+#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ -+#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ -+ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ -+ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) -+ -+#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 -+ -+/* VC0 Resource Control Register */ -+#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) -+#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ -+#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ -+#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ -+#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ -+#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ -+#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ -+#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ -+#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ -+#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ -+ -+#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 -+#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ -+#define PCIE_VC0_RC0_VC_ID_S 24 -+#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ -+ -+/* VC0 Resource Status Register */ -+#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) -+#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ -+#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ -+ -+/* Ack Latency Timer and Replay Timer Register */ -+#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 -+ -+/* Other Message Register */ -+#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) -+ -+/* Port Force Link Register */ -+#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) -+#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ -+#define PCIE_PFLR_LINK_NUM_S 0 -+#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ -+#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ -+#define PCIE_PFLR_LINK_STATE_S 16 -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 -+ -+/* Ack Frequency Register */ -+#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) -+#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ -+#define PCIE_AFR_AF_S 0 -+#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ -+#define PCIE_AFR_FTS_NUM_S 8 -+#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ -+#define PCIE_AFR_COM_FTS_NUM_S 16 -+#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ -+#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 -+#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ -+#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 -+#define PCIE_AFR_FTS_NUM_DEFAULT 32 -+#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 -+#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 -+ -+/* Port Link Control Register */ -+#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) -+#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ -+#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ -+#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ -+#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ -+#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ -+#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ -+#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ -+#define PCIE_PLCR_LINK_MODE_S 16 -+#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ -+ -+/* Lane Skew Register */ -+#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) -+#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ -+#define PCIE_LSR_LANE_SKEW_NUM_S 0 -+#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ -+#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ -+#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ -+ -+/* Symbol Number Register */ -+#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) -+#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ -+#define PCIE_SNR_TS_S 0 -+#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ -+#define PCIE_SNR_SKP_S 8 -+#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ -+#define PCIE_SNR_REPLAY_TIMER_S 14 -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 -+#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ -+#define PCIE_SNR_FC_TIMER_S 28 -+ -+/* Symbol Timer Register and Filter Mask Register 1 */ -+#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) -+#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ -+#define PCIE_STRFMR_SKP_INTERVAL_S 0 -+#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ -+#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ -+#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ -+#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ -+#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ -+#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ -+#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ -+#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ -+#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ -+#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ -+#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ -+#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ -+ -+#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ -+ -+/* Filter Masker Register 2 */ -+#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) -+#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ -+#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ -+ -+/* Debug Register 0 */ -+#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) -+ -+/* Debug Register 1 */ -+#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) -+ -+/* Transmit Posted FC Credit Status Register */ -+#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Non-Posted FC Credit Status */ -+#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Complete FC Credit Status Register */ -+#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 -+ -+/* Queue Status Register */ -+#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) -+#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ -+#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ -+#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ -+ -+/* VC Transmit Arbitration Register 1 */ -+#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) -+#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ -+ -+/* VC Transmit Arbitration Register 2 */ -+#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) -+#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ -+ -+/* VC0 Posted Receive Queue Control Register */ -+#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 -+#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ -+#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ -+ -+/* VC0 Non-Posted Receive Queue Control */ -+#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 -+ -+/* VC0 Completion Receive Queue Control */ -+#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 -+ -+/* Applicable to the above three registers */ -+enum { -+ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, -+ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, -+ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, -+}; -+ -+/* VC0 Posted Buffer Depth Register */ -+#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Non-Posted Buffer Depth Register */ -+#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Completion Buffer Depth Register */ -+#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 -+ -+/* PHY Status Register, all zeros in VR9 */ -+#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) -+ -+/* PHY Control Register, all zeros in VR9 */ -+#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) -+ -+/* -+ * PCIe PDI PHY register definition, suppose all the following -+ * stuff is confidential. -+ * XXX, detailed bit definition -+ */ -+#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) -+#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) -+#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) -+#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) -+#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) -+#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) -+#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) -+#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) -+#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) -+#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) -+#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) -+ -+#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) -+#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) -+#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) -+#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) -+#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) -+#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) -+#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) -+#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) -+ -+#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) -+#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) -+#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) -+#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) -+#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) -+#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) -+#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) -+ -+#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) -+#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) -+#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) -+#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) -+#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) -+ -+/* Interrupt related stuff */ -+#define PCIE_LEGACY_DISABLE 0 -+#define PCIE_LEGACY_INTA 1 -+#define PCIE_LEGACY_INTB 2 -+#define PCIE_LEGACY_INTC 3 -+#define PCIE_LEGACY_INTD 4 -+#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD -+ -+#define PCIE_IRQ_LOCK(lock) do { \ -+ unsigned long flags; \ -+ spin_lock_irqsave(&(lock), flags); -+#define PCIE_IRQ_UNLOCK(lock) \ -+ spin_unlock_irqrestore(&(lock), flags); \ -+} while (0) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) -+#define IRQF_SHARED SA_SHIRQ -+#endif -+ -+#define PCIE_MSG_MSI 0x00000001 -+#define PCIE_MSG_ISR 0x00000002 -+#define PCIE_MSG_FIXUP 0x00000004 -+#define PCIE_MSG_READ_CFG 0x00000008 -+#define PCIE_MSG_WRITE_CFG 0x00000010 -+#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) -+#define PCIE_MSG_REG 0x00000020 -+#define PCIE_MSG_INIT 0x00000040 -+#define PCIE_MSG_ERR 0x00000080 -+#define PCIE_MSG_PHY 0x00000100 -+#define PCIE_MSG_ANY 0x000001ff -+ -+#define IFX_PCIE_PORT0 0 -+#define IFX_PCIE_PORT1 1 -+ -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+#define IFX_PCIE_CORE_NR 2 -+#else -+#define IFX_PCIE_CORE_NR 1 -+#endif -+ -+//#define IFX_PCIE_ERROR_INT -+ -+//#define IFX_PCIE_DBG -+ -+#if defined(IFX_PCIE_DBG) -+#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ -+ if (g_pcie_debug_flag & (_m)) { \ -+ ifx_pcie_debug((_fmt), ##args); \ -+ } \ -+} while (0) -+ -+#define INLINE -+#else -+#define IFX_PCIE_PRINT(_m, _fmt, args...) \ -+ do {} while(0) -+#define INLINE inline -+#endif -+ -+struct ifx_pci_controller { -+ struct pci_controller pcic; -+ -+ /* RC specific, per host bus information */ -+ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ -+}; -+ -+typedef struct ifx_pcie_ir_irq { -+ const unsigned int irq; -+ const char name[16]; -+}ifx_pcie_ir_irq_t; -+ -+typedef struct ifx_pcie_legacy_irq{ -+ const u32 irq_bit; -+ const int irq; -+}ifx_pcie_legacy_irq_t; -+ -+typedef struct ifx_pcie_irq { -+ ifx_pcie_ir_irq_t ir_irq; -+ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; -+}ifx_pcie_irq_t; -+ -+extern u32 g_pcie_debug_flag; -+extern void ifx_pcie_debug(const char *fmt, ...); -+extern void pcie_phy_clock_mode_setup(int pcie_port); -+extern void pcie_msi_pic_init(int pcie_port); -+extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); -+extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); -+ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define IFX_PCIE_GPIO_RESET 38 -+#define IFX_REG_R32 ltq_r32 -+#define IFX_REG_W32 ltq_w32 -+#define CONFIG_IFX_PCIE_HW_SWAP -+#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ -+#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ -+#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ -+#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+ -+#define IFX_PMU1_MODULE_PCIE_PHY (0) -+#define IFX_PMU1_MODULE_PCIE_CTRL (1) -+#define IFX_PMU1_MODULE_PDI (4) -+#define IFX_PMU1_MODULE_MSI (5) -+ -+#define IFX_PMU_MODULE_PCIE_L0_CLK (31) -+ -+ -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+} -+ -+static inline void pcie_ahb_pmu_setup(void) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("ltq_pcie", "ahb"); -+ clk_enable(clk); -+ //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); -+} -+ -+static inline void pcie_rcu_endian_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg |= IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#else -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg &= ~IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); -+} -+ -+static inline void pcie_phy_pmu_enable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("ltq_pcie", "phy"); -+ clk_enable(clk); -+ //ltq_pmu1_enable(1<PCIe and PDI endianness */ -+ reg |= IFX_RCU_AHB_BE_PCIE_PDI; -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+} -+ -+static inline void pcie_pdi_pmu_enable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("ltq_pcie", "pdi"); -+ clk_enable(clk); -+ //ltq_pmu1_enable(1< 1) { -+ tbus_number -= pcibios_1st_host_bus_nr(); -+ } -+#endif /* CONFIG_PCI_LANTIQ */ -+ return tbus_number; -+} -+ -+static inline u32 -+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) -+{ -+ struct pci_dev *pdev; -+ u32 tvalue = value; -+ -+ /* Sanity check */ -+ pdev = pci_get_slot(bus, devfn); -+ if (pdev == NULL) { -+ return tvalue; -+ } -+ -+ /* Only care about PCI bridge */ -+ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { -+ return tvalue; -+ } -+ -+ if (read) { /* Read hack */ -+ #ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); -+ } -+ #endif /* CONFIG_PCI_LANTIQ */ -+ } -+ else { /* Write hack */ -+ #ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); -+ } -+ #endif -+ } -+ return tvalue; -+} -+ -+#endif /* IFXMIPS_PCIE_VR9_H */ -+ ---- a/drivers/pci/pcie/Kconfig -+++ b/drivers/pci/pcie/Kconfig -@@ -54,6 +54,7 @@ config PCIEAER_INJECT - config PCIE_ECRC - bool "PCI Express ECRC settings control" - depends on PCIEAER -+ default n - help - Used to override firmware/bios settings for PCI Express ECRC - (transaction layer end-to-end CRC checking). ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -1325,6 +1325,8 @@ void pci_walk_bus(struct pci_bus *top, i - void *userdata); - int pci_cfg_space_size(struct pci_dev *dev); - unsigned char pci_bus_max_busnr(struct pci_bus *bus); -+int pcibios_host_nr(void); -+int pcibios_1st_host_bus_nr(void); - void pci_setup_bridge(struct pci_bus *bus); - resource_size_t pcibios_window_alignment(struct pci_bus *bus, - unsigned long type); ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -1076,6 +1076,12 @@ - #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 - #define PCI_DEVICE_ID_SGI_IOC4 0x100a - -+#define PCI_VENDOR_ID_INFINEON 0x15D1 -+#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F -+#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 -+#define PCI_VENDOR_ID_LANTIQ 0x1BEF -+#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 -+ - #define PCI_VENDOR_ID_WINBOND 0x10ad - #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 - #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 diff --git a/target/linux/lantiq/patches-4.19/0004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-4.19/0004-MIPS-lantiq-add-atm-hack.patch deleted file mode 100644 index b74642af14..0000000000 --- a/target/linux/lantiq/patches-4.19/0004-MIPS-lantiq-add-atm-hack.patch +++ /dev/null @@ -1,480 +0,0 @@ -From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 3 Aug 2012 10:27:25 +0200 -Subject: [PATCH 04/36] MIPS: lantiq: add atm hack - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++ - arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++ - arch/mips/lantiq/irq.c | 2 + - arch/mips/mm/cache.c | 2 + - include/uapi/linux/atm.h | 6 + - net/atm/common.c | 6 + - net/atm/proc.c | 2 +- - 7 files changed, 416 insertions(+), 1 deletion(-) - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h - ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h -@@ -0,0 +1,196 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_atm.h -+** PROJECT : UEIP -+** MODULES : ATM -+** -+** DATE : 17 Jun 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global ATM driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 07 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_ATM_H -+#define IFX_ATM_H -+ -+ -+ -+/*! -+ \defgroup IFX_ATM UEIP Project - ATM driver module -+ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_ATM_IOCTL IOCTL Commands -+ \ingroup IFX_ATM -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_ATM_STRUCT Structures -+ \ingroup IFX_ATM -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_atm.h -+ \ingroup IFX_ATM -+ \brief ATM driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_ATM_STRUCT -+ */ -+/*@{*/ -+ -+/* -+ * ATM MIB -+ */ -+ -+/*! -+ \struct atm_cell_ifEntry_t -+ \brief Structure used for Cell Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". -+ */ -+typedef struct { -+ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ -+ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ -+ __u32 ifInErrors; /*!< counter of error ingress cells */ -+ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ -+ __u32 ifOutErrors; /*!< counter of error egress cells */ -+} atm_cell_ifEntry_t; -+ -+/*! -+ \struct atm_aal5_ifEntry_t -+ \brief Structure used for AAL5 Frame Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". -+ */ -+typedef struct { -+ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ -+ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ -+ __u32 ifInUcastPkts; /*!< counter of ingress packets */ -+ __u32 ifOutUcastPkts; /*!< counter of egress packets */ -+ __u32 ifInErrors; /*!< counter of error ingress packets */ -+ __u32 ifInDiscards; /*!< counter of dropped ingress packets */ -+ __u32 ifOutErros; /*!< counter of error egress packets */ -+ __u32 ifOutDiscards; /*!< counter of dropped egress packets */ -+} atm_aal5_ifEntry_t; -+ -+/*! -+ \struct atm_aal5_vcc_t -+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. -+ -+ This structure is a part of structure "atm_aal5_vcc_x_t". -+ */ -+typedef struct { -+ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ -+ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet -+ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ -+} atm_aal5_vcc_t; -+ -+/*! -+ \struct atm_aal5_vcc_x_t -+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". -+ */ -+typedef struct { -+ int vpi; /*!< VPI of the VCC to get MIB counters */ -+ int vci; /*!< VCI of the VCC to get MIB counters */ -+ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ -+} atm_aal5_vcc_x_t; -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_ATM_IOCTL -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Command -+ */ -+/*! -+ \brief ATM IOCTL Magic Number -+ */ -+#define PPE_ATM_IOC_MAGIC 'o' -+/*! -+ \brief ATM IOCTL Command - Get Cell Level MIB Counters -+ -+ This command is obsolete. User can get cell level MIB from DSL API. -+ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. -+ */ -+#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) -+/*! -+ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters -+ -+ Get AAL5 packet counters. -+ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. -+ */ -+#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) -+/*! -+ \brief ATM IOCTL Command - Get Per PVC MIB Counters -+ -+ Get AAL5 packet counters for each PVC. -+ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. -+ */ -+#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) -+/*! -+ \brief Total Number of ATM IOCTL Commands -+ */ -+#define PPE_ATM_IOC_MAXNR 3 -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+struct port_cell_info { -+ unsigned int port_num; -+ unsigned int tx_link_rate[2]; -+}; -+#endif -+ -+ -+ -+#endif // IFX_ATM_H -+ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h -@@ -0,0 +1,203 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_ptm.h -+** PROJECT : UEIP -+** MODULES : PTM -+** -+** DATE : 17 Jun 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global PTM driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 07 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_PTM_H -+#define IFX_PTM_H -+ -+ -+ -+/*! -+ \defgroup IFX_PTM UEIP Project - PTM driver module -+ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_PTM_IOCTL IOCTL Commands -+ \ingroup IFX_PTM -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_PTM_STRUCT Structures -+ \ingroup IFX_PTM -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_ptm.h -+ \ingroup IFX_PTM -+ \brief PTM driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_PTM_IOCTL -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Command -+ */ -+/*! -+ \brief PTM IOCTL Command - Get codeword MIB counters. -+ -+ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. -+ */ -+#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 -+/*! -+ \brief PTM IOCTL Command - Get packet MIB counters. -+ -+ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. -+ */ -+#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 -+/*! -+ \brief PTM IOCTL Command - Get firmware configuration (CRC). -+ -+ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). -+ */ -+#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 -+/*! -+ \brief PTM IOCTL Command - Set firmware configuration (CRC). -+ -+ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). -+ */ -+#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 -+/*! -+ \brief PTM IOCTL Command - Program priority value to TX queue mapping. -+ -+ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. -+ */ -+#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 -+ -+/*@}*/ -+ -+ -+/*! -+ \addtogroup IFX_PTM_STRUCT -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Data Type -+ */ -+ -+/*! -+ \typedef PTM_CW_IF_ENTRY_T -+ \brief Wrapping of structure "ptm_cw_ifEntry_t". -+ */ -+/*! -+ \struct ptm_cw_ifEntry_t -+ \brief Structure used for CodeWord level MIB counters. -+ */ -+typedef struct ptm_cw_ifEntry_t { -+ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ -+ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ -+ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ -+ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ -+ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ -+} PTM_CW_IF_ENTRY_T; -+ -+/*! -+ \typedef PTM_FRAME_MIB_T -+ \brief Wrapping of structure "ptm_frame_mib_t". -+ */ -+/*! -+ \struct ptm_frame_mib_t -+ \brief Structure used for packet level MIB counters. -+ */ -+typedef struct ptm_frame_mib_t { -+ uint32_t RxCorrect; /*!< output, number of ingress packet */ -+ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ -+ uint32_t RxDropped; /*!< output, number of dropped ingress packet */ -+ uint32_t TxSend; /*!< output, number of egress packet */ -+} PTM_FRAME_MIB_T; -+ -+/*! -+ \typedef IFX_PTM_CFG_T -+ \brief Wrapping of structure "ptm_cfg_t". -+ */ -+/*! -+ \struct ptm_cfg_t -+ \brief Structure used for ETH/TC CRC configuration. -+ */ -+typedef struct ptm_cfg_t { -+ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ -+ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ -+ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ -+ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ -+ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ -+ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ -+ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ -+} IFX_PTM_CFG_T; -+ -+/*! -+ \typedef IFX_PTM_PRIO_Q_MAP_T -+ \brief Wrapping of structure "ppe_prio_q_map". -+ */ -+/*! -+ \struct ppe_prio_q_map -+ \brief Structure used for Priority Value to TX Queue mapping. -+ */ -+typedef struct ppe_prio_q_map { -+ int pkt_prio; -+ int qid; -+ int vpi; // ignored in eth interface -+ int vci; // ignored in eth interface -+} IFX_PTM_PRIO_Q_MAP_T; -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+struct port_cell_info { -+ unsigned int port_num; -+ unsigned int tx_link_rate[2]; -+}; -+#endif -+ -+ -+ -+#endif // IFX_PTM_H -+ ---- a/arch/mips/lantiq/irq.c -+++ b/arch/mips/lantiq/irq.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -96,6 +97,7 @@ void ltq_mask_and_ack_irq(struct irq_dat - ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); - ltq_icu_w32(im, BIT(offset), isr); - } -+EXPORT_SYMBOL(ltq_mask_and_ack_irq); - - static void ltq_ack_irq(struct irq_data *d) - { ---- a/arch/mips/mm/cache.c -+++ b/arch/mips/mm/cache.c -@@ -64,6 +64,8 @@ void (*_dma_cache_wback)(unsigned long s - void (*_dma_cache_inv)(unsigned long start, unsigned long size); - - EXPORT_SYMBOL(_dma_cache_wback_inv); -+EXPORT_SYMBOL(_dma_cache_wback); -+EXPORT_SYMBOL(_dma_cache_inv); - - #endif /* CONFIG_DMA_NONCOHERENT */ - ---- a/include/uapi/linux/atm.h -+++ b/include/uapi/linux/atm.h -@@ -131,8 +131,14 @@ - #define ATM_ABR 4 - #define ATM_ANYCLASS 5 /* compatible with everything */ - -+#define ATM_VBR_NRT ATM_VBR -+#define ATM_VBR_RT 6 -+#define ATM_UBR_PLUS 7 -+#define ATM_GFR 8 -+ - #define ATM_MAX_PCR -1 /* maximum available PCR */ - -+ - struct atm_trafprm { - unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ - int max_pcr; /* maximum PCR in cells per second */ ---- a/net/atm/proc.c -+++ b/net/atm/proc.c -@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil - static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) - { - static const char *const class_name[] = { -- "off", "UBR", "CBR", "VBR", "ABR"}; -+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; - static const char *const aal_name[] = { - "---", "1", "2", "3/4", /* 0- 3 */ - "???", "5", "???", "???", /* 4- 7 */ diff --git a/target/linux/lantiq/patches-4.19/0005-lantiq_etop-pass-struct-device-to-DMA-API-functions.patch b/target/linux/lantiq/patches-4.19/0005-lantiq_etop-pass-struct-device-to-DMA-API-functions.patch deleted file mode 100644 index ccde787d2d..0000000000 --- a/target/linux/lantiq/patches-4.19/0005-lantiq_etop-pass-struct-device-to-DMA-API-functions.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 74e0deb89a8ba27c132b1f0e08643e215b5c1f92 Mon Sep 17 00:00:00 2001 -From: Christoph Hellwig -Date: Mon, 11 Feb 2019 14:20:00 +0100 -Subject: [PATCH] lantiq_etop: pass struct device to DMA API functions - -The DMA API generally relies on a struct device to work properly, and -only barely works without one for legacy reasons. Pass the easily -available struct device from the platform_device to remedy this. - -Note this driver seems to lack dma_unmap_* calls entirely, but fixing -that is left for another time. - -Signed-off-by: Christoph Hellwig -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/lantiq_etop.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -112,10 +112,12 @@ struct ltq_etop_priv { - static int - ltq_etop_alloc_skb(struct ltq_etop_chan *ch) - { -+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); -+ - ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); - if (!ch->skb[ch->dma.desc]) - return -ENOMEM; -- ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, -+ ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev, - ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, - DMA_FROM_DEVICE); - ch->dma.desc_base[ch->dma.desc].addr = -@@ -493,7 +495,7 @@ ltq_etop_tx(struct sk_buff *skb, struct - netif_trans_update(dev); - - spin_lock_irqsave(&priv->lock, flags); -- desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, -+ desc->addr = ((unsigned int) dma_map_single(&priv->pdev->dev, skb->data, len, - DMA_TO_DEVICE)) - byte_offset; - wmb(); - desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | diff --git a/target/linux/lantiq/patches-4.19/0006-MIPS-lantiq-pass-struct-device-to-DMA-API-functions.patch b/target/linux/lantiq/patches-4.19/0006-MIPS-lantiq-pass-struct-device-to-DMA-API-functions.patch deleted file mode 100644 index 412dd62050..0000000000 --- a/target/linux/lantiq/patches-4.19/0006-MIPS-lantiq-pass-struct-device-to-DMA-API-functions.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 74f03104ed465ff71b11076ef620e4eaa53dbf74 Mon Sep 17 00:00:00 2001 -From: Christoph Hellwig -Date: Fri, 1 Feb 2019 09:47:44 +0100 -Subject: [PATCH] MIPS: lantiq: pass struct device to DMA API functions - -The DMA API generally relies on a struct device to work properly, and -only barely works without one for legacy reasons. Pass the easily -available struct device from the platform_device to remedy this. - -Also use GFP_KERNEL instead of GFP_ATOMIC as the gfp_t for the memory -allocation, as we aren't in interrupt context or under a lock. - -Note that this whole function looks somewhat bogus given that we never -even look at the returned dma address, and the CPHYSADDR magic on -a returned noncached mapping looks "interesting". But I'll leave -that to people more familiar with the code to sort out. - -Signed-off-by: Christoph Hellwig -Signed-off-by: Paul Burton -Cc: John Crispin -Cc: Vinod Koul -Cc: Dmitry Tarnyagin -Cc: Nicolas Ferre -Cc: Sudip Mukherjee -Cc: Felipe Balbi -Cc: linux-mips@vger.kernel.org -Cc: linux-kernel@vger.kernel.org -Cc: dmaengine@vger.kernel.org -Cc: netdev@vger.kernel.org -Cc: linux-usb@vger.kernel.org -Cc: linux-fbdev@vger.kernel.org -Cc: alsa-devel@alsa-project.org -Cc: iommu@lists.linux-foundation.org ---- - arch/mips/lantiq/xway/vmmc.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/mips/lantiq/xway/vmmc.c -+++ b/arch/mips/lantiq/xway/vmmc.c -@@ -31,8 +31,8 @@ static int vmmc_probe(struct platform_de - dma_addr_t dma; - - cp1_base = -- (void *) CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, -- &dma, GFP_ATOMIC)); -+ (void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE, -+ &dma, GFP_KERNEL)); - - gpio_count = of_gpio_count(pdev->dev.of_node); - while (gpio_count > 0) { diff --git a/target/linux/lantiq/patches-4.19/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-4.19/0008-MIPS-lantiq-backport-old-timer-code.patch deleted file mode 100644 index 52e4cbeb1b..0000000000 --- a/target/linux/lantiq/patches-4.19/0008-MIPS-lantiq-backport-old-timer-code.patch +++ /dev/null @@ -1,1034 +0,0 @@ -From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:30:56 +0200 -Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ - arch/mips/lantiq/xway/Makefile | 2 +- - arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++ - 3 files changed, 1001 insertions(+), 1 deletion(-) - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h - create mode 100644 arch/mips/lantiq/xway/timer.c - ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h -@@ -0,0 +1,155 @@ -+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -+ -+ -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/* -+ * Available Timer/Counter Index -+ */ -+#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) -+#define TIMER_ANY 0x00 -+#define TIMER1A TIMER(1, 0) -+#define TIMER1B TIMER(1, 1) -+#define TIMER2A TIMER(2, 0) -+#define TIMER2B TIMER(2, 1) -+#define TIMER3A TIMER(3, 0) -+#define TIMER3B TIMER(3, 1) -+ -+/* -+ * Flag of Timer/Counter -+ * These flags specify the way in which timer is configured. -+ */ -+/* Bit size of timer/counter. */ -+#define TIMER_FLAG_16BIT 0x0000 -+#define TIMER_FLAG_32BIT 0x0001 -+/* Switch between timer and counter. */ -+#define TIMER_FLAG_TIMER 0x0000 -+#define TIMER_FLAG_COUNTER 0x0002 -+/* Stop or continue when overflowing/underflowing. */ -+#define TIMER_FLAG_ONCE 0x0000 -+#define TIMER_FLAG_CYCLIC 0x0004 -+/* Count up or counter down. */ -+#define TIMER_FLAG_UP 0x0000 -+#define TIMER_FLAG_DOWN 0x0008 -+/* Count on specific level or edge. */ -+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 -+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 -+#define TIMER_FLAG_RISE_EDGE 0x0010 -+#define TIMER_FLAG_FALL_EDGE 0x0020 -+#define TIMER_FLAG_ANY_EDGE 0x0030 -+/* Signal is syncronous to module clock or not. */ -+#define TIMER_FLAG_UNSYNC 0x0000 -+#define TIMER_FLAG_SYNC 0x0080 -+/* Different interrupt handle type. */ -+#define TIMER_FLAG_NO_HANDLE 0x0000 -+#if defined(__KERNEL__) -+ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 -+#endif // defined(__KERNEL__) -+#define TIMER_FLAG_SIGNAL 0x0300 -+/* Internal clock source or external clock source */ -+#define TIMER_FLAG_INT_SRC 0x0000 -+#define TIMER_FLAG_EXT_SRC 0x1000 -+ -+ -+/* -+ * ioctl Command -+ */ -+#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ -+#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ -+#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ -+#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ -+#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ -+#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ -+#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ -+#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ -+ -+/* -+ * Data Type Used to Call ioctl -+ */ -+struct gptu_ioctl_param { -+ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * -+ * GPTU_SET_COUNTER, this field is ID of expected * -+ * timer/counter. If it's zero, a timer/counter would * -+ * be dynamically allocated and ID would be stored in * -+ * this field. * -+ * In command GPTU_GET_COUNT_VALUE, this field is * -+ * ignored. * -+ * In other command, this field is ID of timer/counter * -+ * allocated. */ -+ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * -+ * GPTU_SET_COUNTER, this field contains flags to * -+ * specify how to configure timer/counter. * -+ * In command GPTU_START_TIMER, zero indicate start * -+ * and non-zero indicate resume timer/counter. * -+ * In other command, this field is ignored. */ -+ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * -+ * init/reload value. * -+ * In command GPTU_SET_TIMER, this field contains * -+ * frequency (0.001Hz) of timer. * -+ * In command GPTU_GET_COUNT_VALUE, current count * -+ * value would be stored in this field. * -+ * In command GPTU_CALCULATE_DIVIDER, this field * -+ * contains frequency wanted, and after calculation, * -+ * divider would be stored in this field to overwrite * -+ * the frequency. * -+ * In other command, this field is ignored. */ -+ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * -+ * if signal is required, this field contains process * -+ * ID to which signal would be sent. * -+ * In other command, this field is ignored. */ -+ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * -+ * if signal is required, this field contains signal * -+ * number which would be sent. * -+ * In other command, this field is ignored. */ -+}; -+ -+/* -+ * #################################### -+ * Data Type -+ * #################################### -+ */ -+typedef void (*timer_callback)(unsigned long arg); -+ -+extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); -+extern int lq_free_timer(unsigned int); -+extern int lq_start_timer(unsigned int, int); -+extern int lq_stop_timer(unsigned int); -+extern int lq_reset_counter_flags(u32 timer, u32 flags); -+extern int lq_get_count_value(unsigned int, unsigned long *); -+extern u32 lq_cal_divider(unsigned long); -+extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); -+extern int lq_set_counter(unsigned int timer, unsigned int flag, -+ u32 reload, unsigned long arg1, unsigned long arg2); -+ -+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -1,3 +1,9 @@ --obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o -+obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o -+ -+ifdef CONFIG_SOC_AMAZON_SE -+obj-y += gptu.o -+else -+obj-y += timer.o -+endif - - obj-y += vmmc.o ---- /dev/null -+++ b/arch/mips/lantiq/xway/timer.c -@@ -0,0 +1,846 @@ -+#ifndef CONFIG_SOC_AMAZON_SE -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "../clk.h" -+ -+#include -+#include -+#include -+ -+#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 -+ -+#ifdef TIMER1A -+#define FIRST_TIMER TIMER1A -+#else -+#define FIRST_TIMER 2 -+#endif -+ -+/* -+ * GPTC divider is set or not. -+ */ -+#define GPTU_CLC_RMC_IS_SET 0 -+ -+/* -+ * Timer Interrupt (IRQ) -+ */ -+/* Must be adjusted when ICU driver is available */ -+#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) -+ -+/* -+ * Bits Operation -+ */ -+#define GET_BITS(x, msb, lsb) \ -+ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) -+#define SET_BITS(x, msb, lsb, value) \ -+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ -+ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) -+ -+/* -+ * GPTU Register Mapping -+ */ -+#define LQ_GPTU (KSEG1 + 0x1E100A00) -+#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) -+#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) -+#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) -+#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) -+#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) -+ -+/* -+ * Clock Control Register -+ */ -+#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) -+#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) -+#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) -+#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) -+#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) -+#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) -+#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) -+ -+#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) -+#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) -+#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) -+#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) -+#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) -+#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) -+ -+/* -+ * ID Register -+ */ -+#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) -+#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) -+#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) -+ -+/* -+ * Control Register of Timer/Counter nX -+ * n is the index of block (1 based index) -+ * X is either A or B -+ */ -+#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) -+#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) -+#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) -+#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) -+#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) -+#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ -+#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) -+#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) -+#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) -+#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) -+ -+#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) -+#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) -+#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) -+#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) -+#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) -+#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) -+#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) -+#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) -+ -+#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) -+#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) -+ -+#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -+#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -+ -+#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) -+#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) -+#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) -+#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) -+#define TIMER_FLAG_NONE_EDGE 0x0000 -+#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) -+#define TIMER_FLAG_REAL 0x0000 -+#define TIMER_FLAG_INVERT 0x0040 -+#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) -+#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) -+#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) -+#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 -+#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) -+#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) -+ -+struct timer_dev_timer { -+ unsigned int f_irq_on; -+ unsigned int irq; -+ unsigned int flag; -+ unsigned long arg1; -+ unsigned long arg2; -+}; -+ -+struct timer_dev { -+ struct mutex gptu_mutex; -+ unsigned int number_of_timers; -+ unsigned int occupation; -+ unsigned int f_gptu_on; -+ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; -+}; -+ -+ -+unsigned int ltq_get_fpi_bus_clock(int fpi) { -+ struct clk *clk = clk_get_fpi(); -+ return clk_get_rate(clk); -+} -+ -+ -+static long gptu_ioctl(struct file *, unsigned int, unsigned long); -+static int gptu_open(struct inode *, struct file *); -+static int gptu_release(struct inode *, struct file *); -+ -+static struct file_operations gptu_fops = { -+ .owner = THIS_MODULE, -+ .unlocked_ioctl = gptu_ioctl, -+ .open = gptu_open, -+ .release = gptu_release -+}; -+ -+static struct miscdevice gptu_miscdev = { -+ .minor = MISC_DYNAMIC_MINOR, -+ .name = "gptu", -+ .fops = &gptu_fops, -+}; -+ -+static struct timer_dev timer_dev; -+ -+static irqreturn_t timer_irq_handler(int irq, void *p) -+{ -+ unsigned int timer; -+ unsigned int flag; -+ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; -+ -+ timer = irq - TIMER_INTERRUPT; -+ if (timer < timer_dev.number_of_timers -+ && dev_timer == &timer_dev.timer[timer]) { -+ /* Clear interrupt. */ -+ ltq_w32(1 << timer, LQ_GPTU_IRNCR); -+ -+ /* Call user hanler or signal. */ -+ flag = dev_timer->flag; -+ if (!(timer & 0x01) -+ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { -+ /* 16-bit timer or timer A of 32-bit timer */ -+ switch (TIMER_FLAG_MASK_HANDLE(flag)) { -+ case TIMER_FLAG_CALLBACK_IN_IRQ: -+ case TIMER_FLAG_CALLBACK_IN_HB: -+ if (dev_timer->arg1) -+ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); -+ break; -+ case TIMER_FLAG_SIGNAL: -+ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); -+ break; -+ } -+ } -+ } -+ return IRQ_HANDLED; -+} -+ -+static inline void lq_enable_gptu(void) -+{ -+ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); -+ clk_enable(clk); -+ -+ //ltq_pmu_enable(PMU_GPT); -+ -+ /* Set divider as 1, disable write protection for SPEN, enable module. */ -+ *LQ_GPTU_CLC = -+ GPTU_CLC_SMC_SET(0x00) | -+ GPTU_CLC_RMC_SET(0x01) | -+ GPTU_CLC_FSOE_SET(0) | -+ GPTU_CLC_SBWE_SET(1) | -+ GPTU_CLC_EDIS_SET(0) | -+ GPTU_CLC_SPEN_SET(0) | -+ GPTU_CLC_DISR_SET(0); -+} -+ -+static inline void lq_disable_gptu(void) -+{ -+ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); -+ ltq_w32(0x00, LQ_GPTU_IRNEN); -+ ltq_w32(0xfff, LQ_GPTU_IRNCR); -+ -+ /* Set divider as 0, enable write protection for SPEN, disable module. */ -+ *LQ_GPTU_CLC = -+ GPTU_CLC_SMC_SET(0x00) | -+ GPTU_CLC_RMC_SET(0x00) | -+ GPTU_CLC_FSOE_SET(0) | -+ GPTU_CLC_SBWE_SET(0) | -+ GPTU_CLC_EDIS_SET(0) | -+ GPTU_CLC_SPEN_SET(0) | -+ GPTU_CLC_DISR_SET(1); -+ -+ clk_enable(clk); -+} -+ -+int lq_request_timer(unsigned int timer, unsigned int flag, -+ unsigned long value, unsigned long arg1, unsigned long arg2) -+{ -+ int ret = 0; -+ unsigned int con_reg, irnen_reg; -+ int n, X; -+ -+ if (timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", -+ timer, flag, value); -+ -+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) -+ value &= 0xFFFF; -+ else -+ timer &= ~0x01; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ /* -+ * Allocate timer. -+ */ -+ if (timer < FIRST_TIMER) { -+ unsigned int mask; -+ unsigned int shift; -+ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ -+ unsigned int offset = TIMER2A; -+ -+ /* -+ * Pick up a free timer. -+ */ -+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { -+ mask = 1 << offset; -+ shift = 1; -+ } else { -+ mask = 3 << offset; -+ shift = 2; -+ } -+ for (timer = offset; -+ timer < offset + timer_dev.number_of_timers; -+ timer += shift, mask <<= shift) -+ if (!(timer_dev.occupation & mask)) { -+ timer_dev.occupation |= mask; -+ break; -+ } -+ if (timer >= offset + timer_dev.number_of_timers) { -+ printk("failed![%d]\n", __LINE__); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } else -+ ret = timer; -+ } else { -+ register unsigned int mask; -+ -+ /* -+ * Check if the requested timer is free. -+ */ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if ((timer_dev.occupation & mask)) { -+ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", -+ __LINE__, mask, timer_dev.occupation); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EBUSY; -+ } else { -+ timer_dev.occupation |= mask; -+ ret = 0; -+ } -+ } -+ -+ /* -+ * Prepare control register value. -+ */ -+ switch (TIMER_FLAG_MASK_EDGE(flag)) { -+ default: -+ case TIMER_FLAG_NONE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x00); -+ break; -+ case TIMER_FLAG_RISE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x01); -+ break; -+ case TIMER_FLAG_FALL_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x02); -+ break; -+ case TIMER_FLAG_ANY_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x03); -+ break; -+ } -+ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) -+ con_reg |= -+ TIMER_FLAG_MASK_SRC(flag) == -+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : -+ GPTU_CON_SRC_EXT_SET(0); -+ else -+ con_reg |= -+ TIMER_FLAG_MASK_SRC(flag) == -+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : -+ GPTU_CON_SRC_EG_SET(0); -+ con_reg |= -+ TIMER_FLAG_MASK_SYNC(flag) == -+ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : -+ GPTU_CON_SYNC_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_INVERT(flag) == -+ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_SIZE(flag) == -+ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : -+ GPTU_CON_EXT_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_STOP(flag) == -+ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); -+ con_reg |= -+ TIMER_FLAG_MASK_TYPE(flag) == -+ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : -+ GPTU_CON_CNT_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_DIR(flag) == -+ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); -+ -+ /* -+ * Fill up running data. -+ */ -+ timer_dev.timer[timer - FIRST_TIMER].flag = flag; -+ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; -+ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; -+ -+ /* -+ * Enable GPTU module. -+ */ -+ if (!timer_dev.f_gptu_on) { -+ lq_enable_gptu(); -+ timer_dev.f_gptu_on = 1; -+ } -+ -+ /* -+ * Enable IRQ. -+ */ -+ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { -+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) -+ timer_dev.timer[timer - FIRST_TIMER].arg1 = -+ (unsigned long) find_task_by_vpid((int) arg1); -+ -+ irnen_reg = 1 << (timer - FIRST_TIMER); -+ -+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL -+ || (TIMER_FLAG_MASK_HANDLE(flag) == -+ TIMER_FLAG_CALLBACK_IN_IRQ -+ && timer_dev.timer[timer - FIRST_TIMER].arg1)) { -+ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); -+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; -+ } -+ } else -+ irnen_reg = 0; -+ -+ /* -+ * Write config register, reload value and enable interrupt. -+ */ -+ n = timer >> 1; -+ X = timer & 0x01; -+ *LQ_GPTU_CON(n, X) = con_reg; -+ *LQ_GPTU_RELOAD(n, X) = value; -+ /* printk("reload value = %d\n", (u32)value); */ -+ *LQ_GPTU_IRNEN |= irnen_reg; -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ printk("successful!\n"); -+ return ret; -+} -+EXPORT_SYMBOL(lq_request_timer); -+ -+int lq_free_timer(unsigned int timer) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ if (GPTU_CON_EN(n, X)) -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); -+ -+ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); -+ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); -+ -+ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { -+ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); -+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; -+ } -+ -+ timer_dev.occupation &= ~mask; -+ if (!timer_dev.occupation && timer_dev.f_gptu_on) { -+ lq_disable_gptu(); -+ timer_dev.f_gptu_on = 0; -+ } -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_free_timer); -+ -+int lq_start_timer(unsigned int timer, int is_resume) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == -+ TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); -+ -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_start_timer); -+ -+int lq_stop_timer(unsigned int timer) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER -+ || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_stop_timer); -+ -+int lq_reset_counter_flags(u32 timer, u32 flags) -+{ -+ unsigned int oflag; -+ unsigned int mask, con_reg; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ oflag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ switch (TIMER_FLAG_MASK_EDGE(flags)) { -+ default: -+ case TIMER_FLAG_NONE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x00); -+ break; -+ case TIMER_FLAG_RISE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x01); -+ break; -+ case TIMER_FLAG_FALL_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x02); -+ break; -+ case TIMER_FLAG_ANY_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x03); -+ break; -+ } -+ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) -+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); -+ else -+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); -+ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); -+ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); -+ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); -+ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); -+ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); -+ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); -+ -+ timer_dev.timer[timer - FIRST_TIMER].flag = flags; -+ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) -+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_CON(n, X) = con_reg; -+ smp_wmb(); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return 0; -+} -+EXPORT_SYMBOL(lq_reset_counter_flags); -+ -+int lq_get_count_value(unsigned int timer, unsigned long *value) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER -+ || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *value = *LQ_GPTU_COUNT(n, X); -+ -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_get_count_value); -+ -+u32 lq_cal_divider(unsigned long freq) -+{ -+ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); -+ u32 clock_divider = 1; -+ module_freq = fpi * 1000; -+ do_div(module_freq, clock_divider * freq); -+ return module_freq; -+} -+EXPORT_SYMBOL(lq_cal_divider); -+ -+int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, -+ int is_ext_src, unsigned int handle_flag, unsigned long arg1, -+ unsigned long arg2) -+{ -+ unsigned long divider; -+ unsigned int flag; -+ -+ divider = lq_cal_divider(freq); -+ if (divider == 0) -+ return -EINVAL; -+ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) -+ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) -+ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) -+ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN -+ | TIMER_FLAG_MASK_HANDLE(handle_flag); -+ -+ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", -+ timer, freq, divider); -+ return lq_request_timer(timer, flag, divider, arg1, arg2); -+} -+EXPORT_SYMBOL(lq_set_timer); -+ -+int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, -+ unsigned long arg1, unsigned long arg2) -+{ -+ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); -+ return lq_request_timer(timer, flag, reload, arg1, arg2); -+} -+EXPORT_SYMBOL(lq_set_counter); -+ -+static long gptu_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ int ret; -+ struct gptu_ioctl_param param; -+ -+ if (!access_ok(VERIFY_READ, (void __user *)arg, sizeof(struct gptu_ioctl_param))) -+ return -EFAULT; -+ copy_from_user(¶m, (void __user *)arg, sizeof(param)); -+ -+ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER -+ || GPTU_SET_COUNTER) && param.timer < 2) -+ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) -+ && !access_ok(VERIFY_WRITE, (void __user *)arg, -+ sizeof(struct gptu_ioctl_param))) -+ return -EFAULT; -+ -+ switch (cmd) { -+ case GPTU_REQUEST_TIMER: -+ ret = lq_request_timer(param.timer, param.flag, param.value, -+ (unsigned long) param.pid, -+ (unsigned long) param.sig); -+ if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; -+ } -+ break; -+ case GPTU_FREE_TIMER: -+ ret = lq_free_timer(param.timer); -+ break; -+ case GPTU_START_TIMER: -+ ret = lq_start_timer(param.timer, param.flag); -+ break; -+ case GPTU_STOP_TIMER: -+ ret = lq_stop_timer(param.timer); -+ break; -+ case GPTU_GET_COUNT_VALUE: -+ ret = lq_get_count_value(param.timer, ¶m.value); -+ if (!ret) -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ value, ¶m.value, -+ sizeof(param.value)); -+ break; -+ case GPTU_CALCULATE_DIVIDER: -+ param.value = lq_cal_divider(param.value); -+ if (param.value == 0) -+ ret = -EINVAL; -+ else { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ value, ¶m.value, -+ sizeof(param.value)); -+ ret = 0; -+ } -+ break; -+ case GPTU_SET_TIMER: -+ ret = lq_set_timer(param.timer, param.value, -+ TIMER_FLAG_MASK_STOP(param.flag) != -+ TIMER_FLAG_ONCE ? 1 : 0, -+ TIMER_FLAG_MASK_SRC(param.flag) == -+ TIMER_FLAG_EXT_SRC ? 1 : 0, -+ TIMER_FLAG_MASK_HANDLE(param.flag) == -+ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : -+ TIMER_FLAG_NO_HANDLE, -+ (unsigned long) param.pid, -+ (unsigned long) param.sig); -+ if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; -+ } -+ break; -+ case GPTU_SET_COUNTER: -+ lq_set_counter(param.timer, param.flag, param.value, 0, 0); -+ if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; -+ } -+ break; -+ default: -+ ret = -ENOTTY; -+ } -+ -+ return ret; -+} -+ -+static int gptu_open(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+static int gptu_release(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+int __init lq_gptu_init(void) -+{ -+ int ret; -+ unsigned int i; -+ -+ ltq_w32(0, LQ_GPTU_IRNEN); -+ ltq_w32(0xfff, LQ_GPTU_IRNCR); -+ -+ memset(&timer_dev, 0, sizeof(timer_dev)); -+ mutex_init(&timer_dev.gptu_mutex); -+ -+ lq_enable_gptu(); -+ timer_dev.number_of_timers = GPTU_ID_CFG * 2; -+ lq_disable_gptu(); -+ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) -+ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; -+ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); -+ -+ ret = misc_register(&gptu_miscdev); -+ if (ret) { -+ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); -+ return ret; -+ } else { -+ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); -+ } -+ -+ for (i = 0; i < timer_dev.number_of_timers; i++) { -+ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); -+ if (ret) { -+ for (; i >= 0; i--) -+ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); -+ misc_deregister(&gptu_miscdev); -+ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); -+ return ret; -+ } else { -+ timer_dev.timer[i].irq = TIMER_INTERRUPT + i; -+ disable_irq(timer_dev.timer[i].irq); -+ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); -+ } -+ } -+ -+ return 0; -+} -+ -+void __exit lq_gptu_exit(void) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < timer_dev.number_of_timers; i++) { -+ if (timer_dev.timer[i].f_irq_on) -+ disable_irq(timer_dev.timer[i].irq); -+ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); -+ } -+ lq_disable_gptu(); -+ misc_deregister(&gptu_miscdev); -+} -+ -+module_init(lq_gptu_init); -+module_exit(lq_gptu_exit); -+ -+#endif diff --git a/target/linux/lantiq/patches-4.19/0018-MTD-nand-lots-of-xrx200-fixes.patch b/target/linux/lantiq/patches-4.19/0018-MTD-nand-lots-of-xrx200-fixes.patch deleted file mode 100644 index 4e34580efc..0000000000 --- a/target/linux/lantiq/patches-4.19/0018-MTD-nand-lots-of-xrx200-fixes.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 9 Sep 2014 23:12:15 +0200 -Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes - -Signed-off-by: John Crispin ---- - drivers/mtd/nand/raw/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 63 insertions(+) - ---- a/drivers/mtd/nand/raw/xway_nand.c -+++ b/drivers/mtd/nand/raw/xway_nand.c -@@ -63,6 +63,24 @@ - #define NAND_CON_CSMUX (1 << 1) - #define NAND_CON_NANDM 1 - -+#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr)) -+#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400) -+#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080) -+ -+/* -+ * req_mask provides a mechanism to prevent interference between -+ * nand and pci (probably only relevant for the BT Home Hub 2B). -+ * Setting it causes the corresponding pci req pins to be masked -+ * during nand access, and also moves ebu locking from the read/write -+ * functions to the chip select function to ensure that the whole -+ * operation runs with interrupts disabled. -+ * In addition it switches on some extra waiting in xway_cmd_ctrl(). -+ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled, -+ * which in turn seems to be necessary for the nor chip to be recognised -+ * reliably, on a board (Home Hub 2B again) which has both nor and nand. -+ */ -+static __be32 req_mask = 0; -+ - struct xway_nand_data { - struct nand_chip chip; - unsigned long csflags; -@@ -94,10 +112,22 @@ static void xway_select_chip(struct mtd_ - case -1: - ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); - ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); -+ -+ if (req_mask) { -+ /* Unmask all external PCI request */ -+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16); -+ } -+ - spin_unlock_irqrestore(&ebu_lock, data->csflags); - break; - case 0: - spin_lock_irqsave(&ebu_lock, data->csflags); -+ -+ if (req_mask) { -+ /* Mask all external PCI request */ -+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16); -+ } -+ - ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); - ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); - break; -@@ -108,6 +138,12 @@ static void xway_select_chip(struct mtd_ - - static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) - { -+ -+ if (req_mask) { -+ if (cmd != NAND_CMD_STATUS) -+ ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */ -+ } -+ - if (cmd == NAND_CMD_NONE) - return; - -@@ -118,6 +154,24 @@ static void xway_cmd_ctrl(struct mtd_inf - - while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) - ; -+ -+ if (req_mask) { -+ /* -+ * program and erase have their own busy handlers -+ * status and sequential in needs no delay -+ */ -+ switch (cmd) { -+ case NAND_CMD_ERASE1: -+ case NAND_CMD_SEQIN: -+ case NAND_CMD_STATUS: -+ case NAND_CMD_READID: -+ return; -+ } -+ -+ /* wait until command is processed */ -+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) -+ ; -+ } - } - - static int xway_dev_ready(struct mtd_info *mtd) -@@ -157,6 +211,7 @@ static int xway_nand_probe(struct platfo - int err; - u32 cs; - u32 cs_flag = 0; -+ const __be32 *req_mask_ptr; - - /* Allocate memory for the device structure (and zero it) */ - data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), -@@ -192,6 +247,15 @@ static int xway_nand_probe(struct platfo - if (!err && cs == 1) - cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; - -+ req_mask_ptr = of_get_property(pdev->dev.of_node, -+ "req-mask", NULL); -+ -+ /* -+ * Load the PCI req lines to mask from the device tree. If the -+ * property is not present, setting req_mask to 0 disables masking. -+ */ -+ req_mask = (req_mask_ptr ? *req_mask_ptr : 0); -+ - /* setup the EBU to run in NAND mode on our base addr */ - ltq_ebu_w32(CPHYSADDR(data->nandaddr) - | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); diff --git a/target/linux/lantiq/patches-4.19/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch b/target/linux/lantiq/patches-4.19/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch deleted file mode 100644 index 502c5af9f2..0000000000 --- a/target/linux/lantiq/patches-4.19/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch +++ /dev/null @@ -1,25 +0,0 @@ -From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:18:00 +0200 -Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash - -Signed-off-by: John Crispin ---- - drivers/mtd/maps/lantiq-flash.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/maps/lantiq-flash.c -+++ b/drivers/mtd/maps/lantiq-flash.c -@@ -131,7 +131,11 @@ ltq_mtd_probe(struct platform_device *pd - if (!ltq_mtd->map) - return -ENOMEM; - -- ltq_mtd->map->phys = ltq_mtd->res->start; -+ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) -+ ltq_mtd->map->phys = NO_XIP; -+ else -+ ltq_mtd->map->phys = ltq_mtd->res->start; -+ ltq_mtd->res->start; - ltq_mtd->map->size = resource_size(ltq_mtd->res); - ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); - if (IS_ERR(ltq_mtd->map->virt)) diff --git a/target/linux/lantiq/patches-4.19/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch b/target/linux/lantiq/patches-4.19/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch deleted file mode 100644 index fbdd117dea..0000000000 --- a/target/linux/lantiq/patches-4.19/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 4400e1f593ea40a51912128adb4f53d59e62cad8 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 10 Sep 2014 22:40:18 +0200 -Subject: [PATCH 22/36] MTD: m25p80: allow loading mtd name from OF - -In accordance with the physmap flash we should honour the linux,mtd-name -property when deciding what name the mtd device has. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin ---- - drivers/mtd/devices/m25p80.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -173,6 +174,10 @@ static int m25p_probe(struct spi_mem *sp - }; - char *flash_name; - int ret; -+ const char __maybe_unused *of_mtd_name = NULL; -+ -+ of_property_read_string(spi->dev.of_node, -+ "linux,mtd-name", &of_mtd_name); - - data = dev_get_platdata(&spimem->spi->dev); - -@@ -211,6 +216,8 @@ static int m25p_probe(struct spi_mem *sp - - if (data && data->name) - nor->mtd.name = data->name; -+ else if (of_mtd_name) -+ nor->mtd.name = of_mtd_name; - - if (!nor->mtd.name) - nor->mtd.name = spi_mem_get_name(spimem); diff --git a/target/linux/lantiq/patches-4.19/0023-NET-PHY-add-led-support-for-intel-xway.patch b/target/linux/lantiq/patches-4.19/0023-NET-PHY-add-led-support-for-intel-xway.patch deleted file mode 100644 index e5ba24c3e7..0000000000 --- a/target/linux/lantiq/patches-4.19/0023-NET-PHY-add-led-support-for-intel-xway.patch +++ /dev/null @@ -1,294 +0,0 @@ -From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:15:36 +0200 -Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G - -Signed-off-by: John Crispin ---- - drivers/net/phy/Kconfig | 5 + - drivers/net/phy/Makefile | 1 + - drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 237 insertions(+) - create mode 100644 drivers/net/phy/lantiq.c - ---- a/drivers/net/phy/intel-xway.c -+++ b/drivers/net/phy/intel-xway.c -@@ -154,6 +154,51 @@ - #define PHY_ID_PHY11G_VR9_1_2 0xD565A409 - #define PHY_ID_PHY22F_VR9_1_2 0xD565A419 - -+#if IS_ENABLED(CONFIG_OF_MDIO) -+static int vr9_gphy_of_reg_init(struct phy_device *phydev) -+{ -+ u32 tmp; -+ -+ /* store the led values if one was passed by the devicetree */ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp); -+ -+ return 0; -+} -+#else -+static int vr9_gphy_of_reg_init(struct phy_device *phydev) -+{ -+ return 0; -+} -+#endif /* CONFIG_OF_MDIO */ -+ - static int xway_gphy_config_init(struct phy_device *phydev) - { - int err; -@@ -192,6 +237,7 @@ static int xway_gphy_config_init(struct - phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); - phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); - -+ vr9_gphy_of_reg_init(phydev); - return 0; - } - ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt -@@ -0,0 +1,216 @@ -+Lanitq PHY binding -+============================================ -+ -+This devicetree binding controls the lantiq ethernet phys led functionality. -+ -+Example: -+ mdio@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "lantiq,xrx200-mdio"; -+ phy5: ethernet-phy@5 { -+ reg = <0x1>; -+ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; -+ }; -+ phy11: ethernet-phy@11 { -+ reg = <0x11>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led2h = <0x00>; -+ lantiq,led2l = <0x03>; -+ }; -+ phy12: ethernet-phy@12 { -+ reg = <0x12>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led1h = <0x00>; -+ lantiq,led1l = <0x03>; -+ }; -+ phy13: ethernet-phy@13 { -+ reg = <0x13>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led2h = <0x00>; -+ lantiq,led2l = <0x03>; -+ }; -+ phy14: ethernet-phy@14 { -+ reg = <0x14>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led1h = <0x00>; -+ lantiq,led1l = <0x03>; -+ }; -+ }; -+ -+Register Description -+============================================ -+ -+LEDCH: -+ -+Name Hardware Reset Value -+LEDCH 0x00C5 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+| FBF | SBF |RES | NACS | -+========================================= -+ -+Field Bits Type Description -+FBF 7:6 RW Fast Blink Frequency -+ --- -+ 0x0 (00b) F02HZ 2 Hz blinking frequency -+ 0x1 (01b) F04HZ 4 Hz blinking frequency -+ 0x2 (10b) F08HZ 8 Hz blinking frequency -+ 0x3 (11b) F16HZ 16 Hz blinking frequency -+ -+SBF 5:4 RW Slow Blink Frequency -+ --- -+ 0x0 (00b) F02HZ 2 Hz blinking frequency -+ 0x1 (01b) F04HZ 4 Hz blinking frequency -+ 0x2 (10b) F08HZ 8 Hz blinking frequency -+ 0x3 (11b) F16HZ 16 Hz blinking frequency -+ -+NACS 2:0 RW Inverse of Scan Function -+ --- -+ 0x0 (000b) NONE No Function -+ 0x1 (001b) LINK Complex function enabled when link is up -+ 0x2 (010b) PDOWN Complex function enabled when device is powered-down -+ 0x3 (011b) EEE Complex function enabled when device is in EEE mode -+ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running -+ 0x5 (101b) ABIST Complex function enabled when analog self-test is running -+ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running -+ 0x7 (111b) TEST Complex function enabled when test mode is running -+ -+LEDCL: -+ -+Name Hardware Reset Value -+LEDCL 0x0067 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+|RES | SCAN |RES | CBLINK | -+========================================= -+ -+Field Bits Type Description -+SCAN 6:4 RW Complex Scan Configuration -+ --- -+ 000 B NONE No Function -+ 001 B LINK Complex function enabled when link is up -+ 010 B PDOWN Complex function enabled when device is powered-down -+ 011 B EEE Complex function enabled when device is in EEE mode -+ 100 B ANEG Complex function enabled when auto-negotiation is running -+ 101 B ABIST Complex function enabled when analog self-test is running -+ 110 B CDIAG Complex function enabled when cable diagnostics are running -+ 111 B TEST Complex function enabled when test mode is running -+ -+CBLINK 2:0 RW Complex Blinking Configuration -+ --- -+ 000 B NONE No Function -+ 001 B LINK Complex function enabled when link is up -+ 010 B PDOWN Complex function enabled when device is powered-down -+ 011 B EEE Complex function enabled when device is in EEE mode -+ 100 B ANEG Complex function enabled when auto-negotiation is running -+ 101 B ABIST Complex function enabled when analog self-test is running -+ 110 B CDIAG Complex function enabled when cable diagnostics are running -+ 111 B TEST Complex function enabled when test mode is running -+ -+LEDxH: -+ -+Name Hardware Reset Value -+LED0H 0x0070 -+LED1H 0x0020 -+LED2H 0x0040 -+LED3H 0x0040 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+| CON | BLINKF | -+========================================= -+ -+Field Bits Type Description -+CON 7:4 RW Constant On Configuration -+ --- -+ 0x0 (0000b) NONE LED does not light up constantly -+ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s -+ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s -+ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s -+ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s -+ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s -+ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s -+ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s -+ 0x8 (1000b) PDOWN LED is on when device is powered-down -+ 0x9 (1001b) EEE LED is on when device is in EEE mode -+ 0xA (1010b) ANEG LED is on when auto-negotiation is running -+ 0xB (1011b) ABIST LED is on when analog self-test is running -+ 0xC (1100b) CDIAG LED is on when cable diagnostics are running -+ -+BLINKF 3:0 RW Fast Blinking Configuration -+ --- -+ 0x0 (0000b) NONE No Blinking -+ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s -+ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s -+ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s -+ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s -+ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s -+ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s -+ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s -+ 0x8 (1000b) PDOWN Blink when device is powered-down -+ 0x9 (1001b) EEE Blink when device is in EEE mode -+ 0xA (1010b) ANEG Blink when auto-negotiation is running -+ 0xB (1011b) ABIST Blink when analog self-test is running -+ 0xC (1100b) CDIAG Blink when cable diagnostics are running -+ -+LEDxL: -+ -+Name Hardware Reset Value -+LED0L 0x0003 -+LED1L 0x0000 -+LED2L 0x0000 -+LED3L 0x0020 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+| BLINKS | PULSE | -+========================================= -+ -+Field Bits Type Description -+BLINKS 7:4 RW Slow Blinkin Configuration -+ --- -+ 0x0 (0000b) NONE No Blinking -+ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s -+ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s -+ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s -+ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s -+ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s -+ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s -+ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s -+ 0x8 (1000b) PDOWN Blink when device is powered-down -+ 0x9 (1001b) EEE Blink when device is in EEE mode -+ 0xA (1010b) ANEG Blink when auto-negotiation is running -+ 0xB (1011b) ABIST Blink when analog self-test is running -+ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning -+ -+PULSE 3:0 RW Pulsing Configuration -+ The pulse field is a mask field by which certain events can be combined -+ --- -+ 0x0 (0000b) NONE No pulsing -+ 0x1 (0001b) TXACT Transmit activity -+ 0x2 (0010b) RXACT Receive activity -+ 0x4 (0100b) COL Collision -+ 0x8 (1000b) RES Reserved diff --git a/target/linux/lantiq/patches-4.19/0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch b/target/linux/lantiq/patches-4.19/0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch deleted file mode 100644 index 7fbd97feca..0000000000 --- a/target/linux/lantiq/patches-4.19/0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch +++ /dev/null @@ -1,45 +0,0 @@ -From ae0c287060749dc72c866484d12bd3cade8c517d Mon Sep 17 00:00:00 2001 -From: Mathias Kresin -Date: Fri, 19 Jan 2018 20:19:06 +0100 -Subject: [PATCH] MIPS: lantiq: autoselect matching vr9 rev gphy firmware - -Add a custom xrx200 ethernet phy compatible to load the firmware matching -the vr9 revision without specifing an expected revision. - -We have quite a few boards in the tree were later produced ones are using -a more recent vr9. It is impossible to distinguish which revision of the -vr9 is used without opening the case and removing a heatsink for some of -them. - -Signed-off-by: Mathias Kresin ---- - drivers/soc/lantiq/gphy.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/drivers/soc/lantiq/gphy.c -+++ b/drivers/soc/lantiq/gphy.c -@@ -55,6 +55,7 @@ static const struct xway_gphy_match_data - }; - - static const struct of_device_id xway_gphy_match[] = { -+ { .compatible = "lantiq,xrx200-gphy", .data = NULL }, - { .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data }, - { .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data }, - { .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data }, -@@ -111,6 +112,16 @@ static int xway_gphy_of_probe(struct pla - - gphy_fw_name_cfg = of_device_get_match_data(dev); - -+ if (of_device_is_compatible(pdev->dev.of_node, "lantiq,xrx200-gphy")) -+ switch (ltq_soc_type()) { -+ case SOC_TYPE_VR9: -+ gphy_fw_name_cfg = &xrx200a1x_gphy_data; -+ break; -+ case SOC_TYPE_VR9_2: -+ gphy_fw_name_cfg = &xrx200a2x_gphy_data; -+ break; -+ } -+ - priv->gphy_clk_gate = devm_clk_get(dev, NULL); - if (IS_ERR(priv->gphy_clk_gate)) { - dev_err(dev, "Failed to lookup gate clock\n"); diff --git a/target/linux/lantiq/patches-4.19/0025-NET-MIPS-lantiq-adds-xrx200-net.patch b/target/linux/lantiq/patches-4.19/0025-NET-MIPS-lantiq-adds-xrx200-net.patch deleted file mode 100644 index 4e5b55eb3e..0000000000 --- a/target/linux/lantiq/patches-4.19/0025-NET-MIPS-lantiq-adds-xrx200-net.patch +++ /dev/null @@ -1,3467 +0,0 @@ -From fb0c9601f4414c39ff68e26b88681bef0bb04954 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 22 Oct 2012 12:22:23 +0200 -Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net - ---- - drivers/net/ethernet/Kconfig | 8 +- - drivers/net/ethernet/Makefile | 1 + - drivers/net/ethernet/lantiq_pce.h | 163 +++ - drivers/net/ethernet/lantiq_xrx200.c | 1798 +++++++++++++++++++++++++++++++ - drivers/net/ethernet/lantiq_xrx200_sw.h | 1328 +++++++++++++++++++++++ - 5 files changed, 3297 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/ethernet/lantiq_pce.h - create mode 100644 drivers/net/ethernet/lantiq_xrx200.c - create mode 100644 drivers/net/ethernet/lantiq_xrx200_sw.h - ---- a/drivers/net/ethernet/Kconfig -+++ b/drivers/net/ethernet/Kconfig -@@ -106,7 +106,13 @@ config LANTIQ_ETOP - tristate "Lantiq SoC ETOP driver" - depends on SOC_TYPE_XWAY - ---help--- -- Support for the MII0 inside the Lantiq SoC -+ Support for the MII0 inside the Lantiq ADSL SoC -+ -+config LANTIQ_XRX200 -+ tristate "Lantiq SoC XRX200 driver" -+ depends on SOC_TYPE_XWAY -+ ---help--- -+ Support for the MII0 inside the Lantiq VDSL SoC - - source "drivers/net/ethernet/marvell/Kconfig" - source "drivers/net/ethernet/mediatek/Kconfig" ---- a/drivers/net/ethernet/Makefile -+++ b/drivers/net/ethernet/Makefile -@@ -49,6 +49,7 @@ obj-$(CONFIG_NET_VENDOR_XSCALE) += xscal - obj-$(CONFIG_JME) += jme.o - obj-$(CONFIG_KORINA) += korina.o - obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o -+obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o - obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ - obj-$(CONFIG_NET_VENDOR_MEDIATEK) += mediatek/ - obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ ---- /dev/null -+++ b/drivers/net/ethernet/lantiq_pce.h -@@ -0,0 +1,163 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2012 John Crispin -+ * -+ * PCE microcode extracted from UGW5.2 switch api -+ */ -+ -+/* Switch API Micro Code V0.3 */ -+enum { -+ OUT_MAC0 = 0, -+ OUT_MAC1, -+ OUT_MAC2, -+ OUT_MAC3, -+ OUT_MAC4, -+ OUT_MAC5, -+ OUT_ETHTYP, -+ OUT_VTAG0, -+ OUT_VTAG1, -+ OUT_ITAG0, -+ OUT_ITAG1, /*10 */ -+ OUT_ITAG2, -+ OUT_ITAG3, -+ OUT_IP0, -+ OUT_IP1, -+ OUT_IP2, -+ OUT_IP3, -+ OUT_SIP0, -+ OUT_SIP1, -+ OUT_SIP2, -+ OUT_SIP3, /*20*/ -+ OUT_SIP4, -+ OUT_SIP5, -+ OUT_SIP6, -+ OUT_SIP7, -+ OUT_DIP0, -+ OUT_DIP1, -+ OUT_DIP2, -+ OUT_DIP3, -+ OUT_DIP4, -+ OUT_DIP5, /*30*/ -+ OUT_DIP6, -+ OUT_DIP7, -+ OUT_SESID, -+ OUT_PROT, -+ OUT_APP0, -+ OUT_APP1, -+ OUT_IGMP0, -+ OUT_IGMP1, -+ OUT_IPOFF, /*39*/ -+ OUT_NONE = 63 -+}; -+ -+/* parser's microcode length type */ -+#define INSTR 0 -+#define IPV6 1 -+#define LENACCU 2 -+ -+/* parser's microcode flag type */ -+enum { -+ FLAG_ITAG = 0, -+ FLAG_VLAN, -+ FLAG_SNAP, -+ FLAG_PPPOE, -+ FLAG_IPV6, -+ FLAG_IPV6FL, -+ FLAG_IPV4, -+ FLAG_IGMP, -+ FLAG_TU, -+ FLAG_HOP, -+ FLAG_NN1, /*10 */ -+ FLAG_NN2, -+ FLAG_END, -+ FLAG_NO, /*13*/ -+}; -+ -+/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */ -+#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \ -+ { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }} -+struct pce_microcode { -+ unsigned short val[4]; -+/* unsigned short val_2; -+ unsigned short val_1; -+ unsigned short val_0;*/ -+} pce_microcode[] = { -+ /* value mask ns fields L type flags ipv4_len */ -+ MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0), -+ MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), -+ MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), -+ MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), -+ MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0), -+ MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1), -+ MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0), -+ MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0), -+ MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0), -+ MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0), -+ MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0), -+ MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0), -+ MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0), -+ MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+}; ---- /dev/null -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -0,0 +1,1924 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2010 Lantiq Deutschland -+ * Copyright (C) 2012 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "lantiq_pce.h" -+#include "lantiq_xrx200_sw.h" -+ -+#define SW_POLLING -+#define SW_ROUTING -+ -+#ifdef SW_ROUTING -+#define XRX200_MAX_DEV 2 -+#else -+#define XRX200_MAX_DEV 1 -+#endif -+ -+#define XRX200_MAX_VLAN 64 -+#define XRX200_PCE_ACTVLAN_IDX 0x01 -+#define XRX200_PCE_VLANMAP_IDX 0x02 -+ -+#define XRX200_MAX_PORT 7 -+#define XRX200_MAX_DMA 8 -+ -+#define XRX200_HEADROOM 4 -+ -+#define XRX200_TX_TIMEOUT (10 * HZ) -+ -+/* port type */ -+#define XRX200_PORT_TYPE_PHY 1 -+#define XRX200_PORT_TYPE_MAC 2 -+ -+/* DMA */ -+#define XRX200_DMA_DATA_LEN 0x600 -+#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0 -+#define XRX200_DMA_RX 0 -+#define XRX200_DMA_TX 1 -+#define XRX200_DMA_TX_2 3 -+#define XRX200_DMA_IS_TX(x) (x%2) -+#define XRX200_DMA_IS_RX(x) (!XRX200_DMA_IS_TX(x)) -+ -+/* fetch / store dma */ -+#define FDMA_PCTRL0 0x2A00 -+#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18)) -+#define SDMA_PCTRL0 0x2F00 -+#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18)) -+ -+/* buffer management */ -+#define BM_PCFG0 0x200 -+#define BM_PCFGx(x) (BM_PCFG0 + (x * 8)) -+ -+/* MDIO */ -+#define MDIO_GLOB 0x0000 -+#define MDIO_CTRL 0x0020 -+#define MDIO_READ 0x0024 -+#define MDIO_WRITE 0x0028 -+#define MDIO_PHY0 0x0054 -+#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned))) -+#define MDIO_CLK_CFG0 0x002C -+#define MDIO_CLK_CFG1 0x0030 -+ -+#define MDIO_GLOB_ENABLE 0x8000 -+#define MDIO_BUSY BIT(12) -+#define MDIO_RD BIT(11) -+#define MDIO_WR BIT(10) -+#define MDIO_MASK 0x1f -+#define MDIO_ADDRSHIFT 5 -+#define MDIO1_25MHZ 9 -+ -+#define MDIO_PHY_LINK_DOWN 0x4000 -+#define MDIO_PHY_LINK_UP 0x2000 -+ -+#define MDIO_PHY_SPEED_M10 0x0000 -+#define MDIO_PHY_SPEED_M100 0x0800 -+#define MDIO_PHY_SPEED_G1 0x1000 -+ -+#define MDIO_PHY_FDUP_EN 0x0200 -+#define MDIO_PHY_FDUP_DIS 0x0600 -+ -+#define MDIO_PHY_LINK_MASK 0x6000 -+#define MDIO_PHY_SPEED_MASK 0x1800 -+#define MDIO_PHY_FDUP_MASK 0x0600 -+#define MDIO_PHY_ADDR_MASK 0x001f -+#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \ -+ MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK -+ -+/* MII */ -+#define MII_CFG(p) (p * 8) -+ -+#define MII_CFG_EN BIT(14) -+ -+#define MII_CFG_MODE_MIIP 0x0 -+#define MII_CFG_MODE_MIIM 0x1 -+#define MII_CFG_MODE_RMIIP 0x2 -+#define MII_CFG_MODE_RMIIM 0x3 -+#define MII_CFG_MODE_RGMII 0x4 -+#define MII_CFG_MODE_MASK 0xf -+ -+#define MII_CFG_RATE_M2P5 0x00 -+#define MII_CFG_RATE_M25 0x10 -+#define MII_CFG_RATE_M125 0x20 -+#define MII_CFG_RATE_M50 0x30 -+#define MII_CFG_RATE_AUTO 0x40 -+#define MII_CFG_RATE_MASK 0x70 -+ -+/* cpu port mac */ -+#define PMAC_HD_CTL 0x0000 -+#define PMAC_RX_IPG 0x0024 -+#define PMAC_EWAN 0x002c -+ -+#define PMAC_IPG_MASK 0xf -+#define PMAC_HD_CTL_AS 0x0008 -+#define PMAC_HD_CTL_AC 0x0004 -+#define PMAC_HD_CTL_RC 0x0010 -+#define PMAC_HD_CTL_RXSH 0x0040 -+#define PMAC_HD_CTL_AST 0x0080 -+#define PMAC_HD_CTL_RST 0x0100 -+ -+/* PCE */ -+#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4)) -+#define PCE_TBL_MASK 0x1120 -+#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4)) -+#define PCE_TBL_ADDR 0x1138 -+#define PCE_TBL_CTRL 0x113c -+#define PCE_PMAP1 0x114c -+#define PCE_PMAP2 0x1150 -+#define PCE_PMAP3 0x1154 -+#define PCE_GCTRL_REG(x) (0x1158 + (x * 4)) -+#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4)) -+ -+#define PCE_TBL_BUSY BIT(15) -+#define PCE_TBL_CFG_ADDR_MASK 0x1f -+#define PCE_TBL_CFG_ADWR 0x20 -+#define PCE_TBL_CFG_ADWR_MASK 0x60 -+#define PCE_INGRESS BIT(11) -+ -+/* MAC */ -+#define MAC_FLEN_REG (0x2314) -+#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4)) -+ -+/* buffer management */ -+#define BM_PCFG(p) (0x200 + (p * 8)) -+ -+/* special tag in TX path header */ -+#define SPID_SHIFT 24 -+#define DPID_SHIFT 16 -+#define DPID_ENABLE 1 -+#define SPID_CPU_PORT 2 -+#define PORT_MAP_SEL BIT(15) -+#define PORT_MAP_EN BIT(14) -+#define PORT_MAP_SHIFT 1 -+#define PORT_MAP_MASK 0x3f -+ -+#define SPPID_MASK 0x7 -+#define SPPID_SHIFT 4 -+ -+/* MII regs not yet in linux */ -+#define MDIO_DEVAD_NONE (-1) -+#define ADVERTIZE_MPD (1 << 10) -+ -+struct xrx200_port { -+ u8 num; -+ u8 phy_addr; -+ u16 flags; -+ phy_interface_t phy_if; -+ -+ int link; -+ int gpio; -+ enum of_gpio_flags gpio_flags; -+ -+ struct phy_device *phydev; -+ struct device_node *phy_node; -+}; -+ -+struct xrx200_chan { -+ int idx; -+ int refcount; -+ int tx_free; -+ -+ struct net_device dummy_dev; -+ struct net_device *devs[XRX200_MAX_DEV]; -+ -+ struct tasklet_struct tasklet; -+ struct napi_struct napi; -+ struct ltq_dma_channel dma; -+ struct sk_buff *skb[LTQ_DESC_NUM]; -+ -+ spinlock_t lock; -+}; -+ -+struct xrx200_hw { -+ struct clk *clk; -+ struct mii_bus *mii_bus; -+ u8 phy_addr[XRX200_MAX_PORT]; -+ -+ struct xrx200_chan chan[XRX200_MAX_DMA]; -+ u16 vlan_vid[XRX200_MAX_VLAN]; -+ u16 vlan_port_map[XRX200_MAX_VLAN]; -+ -+ struct net_device *devs[XRX200_MAX_DEV]; -+ int num_devs; -+ -+ int port_map[XRX200_MAX_PORT]; -+ unsigned short wan_map; -+ -+ struct switch_dev swdev; -+}; -+ -+struct xrx200_priv { -+ struct net_device_stats stats; -+ int id; -+ -+ struct xrx200_port port[XRX200_MAX_PORT]; -+ int num_port; -+ bool wan; -+ bool sw; -+ unsigned short port_map; -+ unsigned char mac[6]; -+ -+ struct xrx200_hw *hw; -+}; -+ -+static __iomem void *xrx200_switch_membase; -+static __iomem void *xrx200_mii_membase; -+static __iomem void *xrx200_mdio_membase; -+static __iomem void *xrx200_pmac_membase; -+ -+#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x)) -+#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y)) -+#define ltq_switch_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, xrx200_switch_membase + (z)) -+ -+#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x)) -+#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y)) -+#define ltq_mdio_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, xrx200_mdio_membase + (z)) -+ -+#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x)) -+#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y)) -+#define ltq_mii_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, xrx200_mii_membase + (z)) -+ -+#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x)) -+#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y)) -+#define ltq_pmac_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, xrx200_pmac_membase + (z)) -+ -+#define XRX200_GLOBAL_REGATTR(reg) \ -+ .id = reg, \ -+ .type = SWITCH_TYPE_INT, \ -+ .set = xrx200_set_global_attr, \ -+ .get = xrx200_get_global_attr -+ -+#define XRX200_PORT_REGATTR(reg) \ -+ .id = reg, \ -+ .type = SWITCH_TYPE_INT, \ -+ .set = xrx200_set_port_attr, \ -+ .get = xrx200_get_port_attr -+ -+static int xrx200sw_read_x(int reg, int x) -+{ -+ int value, mask, addr; -+ -+ addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x); -+ value = ltq_switch_r32(addr); -+ mask = (1 << xrx200sw_reg[reg].size) - 1; -+ value = (value >> xrx200sw_reg[reg].shift); -+ -+ return (value & mask); -+} -+ -+static int xrx200sw_read(int reg) -+{ -+ return xrx200sw_read_x(reg, 0); -+} -+ -+static void xrx200sw_write_x(int value, int reg, int x) -+{ -+ int mask, addr; -+ -+ addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x); -+ mask = (1 << xrx200sw_reg[reg].size) - 1; -+ mask = (mask << xrx200sw_reg[reg].shift); -+ value = (value << xrx200sw_reg[reg].shift) & mask; -+ -+ ltq_switch_w32_mask(mask, value, addr); -+} -+ -+static void xrx200sw_write(int value, int reg) -+{ -+ xrx200sw_write_x(value, reg, 0); -+} -+ -+struct xrx200_pce_table_entry { -+ int index; // PCE_TBL_ADDR.ADDR = pData->table_index -+ int table; // PCE_TBL_CTRL.ADDR = pData->table -+ unsigned short key[8]; -+ unsigned short val[5]; -+ unsigned short mask; -+ unsigned short type; -+ unsigned short valid; -+ unsigned short gmap; -+}; -+ -+static int xrx200_pce_table_entry_read(struct xrx200_pce_table_entry *tbl) -+{ -+ // wait until hardware is ready -+ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; -+ -+ // prepare the table access: -+ // PCE_TBL_ADDR.ADDR = pData->table_index -+ xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR); -+ // PCE_TBL_CTRL.ADDR = pData->table -+ xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR); -+ -+ //(address-based read) -+ xrx200sw_write(0, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD -+ -+ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access -+ -+ // wait until hardware is ready -+ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; -+ -+ // read the keys -+ tbl->key[7] = xrx200sw_read(XRX200_PCE_TBL_KEY_7); -+ tbl->key[6] = xrx200sw_read(XRX200_PCE_TBL_KEY_6); -+ tbl->key[5] = xrx200sw_read(XRX200_PCE_TBL_KEY_5); -+ tbl->key[4] = xrx200sw_read(XRX200_PCE_TBL_KEY_4); -+ tbl->key[3] = xrx200sw_read(XRX200_PCE_TBL_KEY_3); -+ tbl->key[2] = xrx200sw_read(XRX200_PCE_TBL_KEY_2); -+ tbl->key[1] = xrx200sw_read(XRX200_PCE_TBL_KEY_1); -+ tbl->key[0] = xrx200sw_read(XRX200_PCE_TBL_KEY_0); -+ -+ // read the values -+ tbl->val[4] = xrx200sw_read(XRX200_PCE_TBL_VAL_4); -+ tbl->val[3] = xrx200sw_read(XRX200_PCE_TBL_VAL_3); -+ tbl->val[2] = xrx200sw_read(XRX200_PCE_TBL_VAL_2); -+ tbl->val[1] = xrx200sw_read(XRX200_PCE_TBL_VAL_1); -+ tbl->val[0] = xrx200sw_read(XRX200_PCE_TBL_VAL_0); -+ -+ // read the mask -+ tbl->mask = xrx200sw_read(XRX200_PCE_TBL_MASK_0); -+ // read the type -+ tbl->type = xrx200sw_read(XRX200_PCE_TBL_CTRL_TYPE); -+ // read the valid flag -+ tbl->valid = xrx200sw_read(XRX200_PCE_TBL_CTRL_VLD); -+ // read the group map -+ tbl->gmap = xrx200sw_read(XRX200_PCE_TBL_CTRL_GMAP); -+ -+ return 0; -+} -+ -+static int xrx200_pce_table_entry_write(struct xrx200_pce_table_entry *tbl) -+{ -+ // wait until hardware is ready -+ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; -+ -+ // prepare the table access: -+ // PCE_TBL_ADDR.ADDR = pData->table_index -+ xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR); -+ // PCE_TBL_CTRL.ADDR = pData->table -+ xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR); -+ -+ //(address-based write) -+ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD -+ -+ // read the keys -+ xrx200sw_write(tbl->key[7], XRX200_PCE_TBL_KEY_7); -+ xrx200sw_write(tbl->key[6], XRX200_PCE_TBL_KEY_6); -+ xrx200sw_write(tbl->key[5], XRX200_PCE_TBL_KEY_5); -+ xrx200sw_write(tbl->key[4], XRX200_PCE_TBL_KEY_4); -+ xrx200sw_write(tbl->key[3], XRX200_PCE_TBL_KEY_3); -+ xrx200sw_write(tbl->key[2], XRX200_PCE_TBL_KEY_2); -+ xrx200sw_write(tbl->key[1], XRX200_PCE_TBL_KEY_1); -+ xrx200sw_write(tbl->key[0], XRX200_PCE_TBL_KEY_0); -+ -+ // read the values -+ xrx200sw_write(tbl->val[4], XRX200_PCE_TBL_VAL_4); -+ xrx200sw_write(tbl->val[3], XRX200_PCE_TBL_VAL_3); -+ xrx200sw_write(tbl->val[2], XRX200_PCE_TBL_VAL_2); -+ xrx200sw_write(tbl->val[1], XRX200_PCE_TBL_VAL_1); -+ xrx200sw_write(tbl->val[0], XRX200_PCE_TBL_VAL_0); -+ -+ // read the mask -+ xrx200sw_write(tbl->mask, XRX200_PCE_TBL_MASK_0); -+ // read the type -+ xrx200sw_write(tbl->type, XRX200_PCE_TBL_CTRL_TYPE); -+ // read the valid flag -+ xrx200sw_write(tbl->valid, XRX200_PCE_TBL_CTRL_VLD); -+ // read the group map -+ xrx200sw_write(tbl->gmap, XRX200_PCE_TBL_CTRL_GMAP); -+ -+ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access -+ -+ // wait until hardware is ready -+ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; -+ -+ return 0; -+} -+ -+static void xrx200sw_fixup_pvids(void) -+{ -+ int index, p, portmap, untagged; -+ struct xrx200_pce_table_entry tem; -+ struct xrx200_pce_table_entry tev; -+ -+ portmap = 0; -+ for (p = 0; p < XRX200_MAX_PORT; p++) -+ portmap |= BIT(p); -+ -+ tem.table = XRX200_PCE_VLANMAP_IDX; -+ tev.table = XRX200_PCE_ACTVLAN_IDX; -+ -+ for (index = XRX200_MAX_VLAN; index-- > 0;) -+ { -+ tev.index = index; -+ xrx200_pce_table_entry_read(&tev); -+ -+ if (tev.valid == 0) -+ continue; -+ -+ tem.index = index; -+ xrx200_pce_table_entry_read(&tem); -+ -+ if (tem.val[0] == 0) -+ continue; -+ -+ untagged = portmap & (tem.val[1] ^ tem.val[2]); -+ -+ for (p = 0; p < XRX200_MAX_PORT; p++) -+ if (untagged & BIT(p)) -+ { -+ portmap &= ~BIT(p); -+ xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p); -+ } -+ -+ for (p = 0; p < XRX200_MAX_PORT; p++) -+ if (portmap & BIT(p)) -+ xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p); -+ } -+} -+ -+// swconfig interface -+static void xrx200_hw_init(struct xrx200_hw *hw); -+ -+// global -+static int xrx200sw_reset_switch(struct switch_dev *dev) -+{ -+ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); -+ -+ xrx200_hw_init(hw); -+ -+ return 0; -+} -+ -+static int xrx200_set_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ int p; -+ -+ if ((attr->max > 0) && (val->value.i > attr->max)) -+ return -EINVAL; -+ -+ for (p = 0; p < XRX200_MAX_PORT; p++) { -+ xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VEMR, p); -+ xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VIMR, p); -+ } -+ -+ xrx200sw_write(val->value.i, XRX200_PCE_GCTRL_0_VLAN); -+ return 0; -+} -+ -+static int xrx200_get_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ val->value.i = xrx200sw_read(attr->id); -+ return 0; -+} -+ -+static int xrx200_set_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ if ((attr->max > 0) && (val->value.i > attr->max)) -+ return -EINVAL; -+ -+ xrx200sw_write(val->value.i, attr->id); -+ return 0; -+} -+ -+static int xrx200_get_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ val->value.i = xrx200sw_read(attr->id); -+ return 0; -+} -+ -+// vlan -+static int xrx200sw_set_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); -+ int i; -+ struct xrx200_pce_table_entry tev; -+ struct xrx200_pce_table_entry tem; -+ -+ tev.table = XRX200_PCE_ACTVLAN_IDX; -+ -+ for (i = 0; i < XRX200_MAX_VLAN; i++) -+ { -+ tev.index = i; -+ xrx200_pce_table_entry_read(&tev); -+ if (tev.key[0] == val->value.i && i != val->port_vlan) -+ return -EINVAL; -+ } -+ -+ hw->vlan_vid[val->port_vlan] = val->value.i; -+ -+ tev.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tev); -+ tev.key[0] = val->value.i; -+ tev.valid = val->value.i > 0; -+ xrx200_pce_table_entry_write(&tev); -+ -+ tem.table = XRX200_PCE_VLANMAP_IDX; -+ tem.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tem); -+ tem.val[0] = val->value.i; -+ xrx200_pce_table_entry_write(&tem); -+ -+ xrx200sw_fixup_pvids(); -+ return 0; -+} -+ -+static int xrx200sw_get_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct xrx200_pce_table_entry te; -+ -+ te.table = XRX200_PCE_ACTVLAN_IDX; -+ te.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&te); -+ val->value.i = te.key[0]; -+ -+ return 0; -+} -+ -+static int xrx200sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val) -+{ -+ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); -+ int i, portmap, tagmap, untagged; -+ struct xrx200_pce_table_entry tem; -+ -+ portmap = 0; -+ tagmap = 0; -+ for (i = 0; i < val->len; i++) -+ { -+ struct switch_port *p = &val->value.ports[i]; -+ -+ portmap |= (1 << p->id); -+ if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) -+ tagmap |= (1 << p->id); -+ } -+ -+ tem.table = XRX200_PCE_VLANMAP_IDX; -+ -+ untagged = portmap ^ tagmap; -+ for (i = 0; i < XRX200_MAX_VLAN; i++) -+ { -+ tem.index = i; -+ xrx200_pce_table_entry_read(&tem); -+ -+ if (tem.val[0] == 0) -+ continue; -+ -+ if ((untagged & (tem.val[1] ^ tem.val[2])) && (val->port_vlan != i)) -+ return -EINVAL; -+ } -+ -+ tem.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tem); -+ -+ // auto-enable this vlan if not enabled already -+ if (tem.val[0] == 0) -+ { -+ struct switch_val v; -+ v.port_vlan = val->port_vlan; -+ v.value.i = val->port_vlan; -+ if(xrx200sw_set_vlan_vid(dev, NULL, &v)) -+ return -EINVAL; -+ -+ //read updated tem -+ tem.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tem); -+ } -+ -+ tem.val[1] = portmap; -+ tem.val[2] = tagmap; -+ xrx200_pce_table_entry_write(&tem); -+ -+ ltq_switch_w32_mask(0, portmap, PCE_PMAP2); -+ ltq_switch_w32_mask(0, portmap, PCE_PMAP3); -+ hw->vlan_port_map[val->port_vlan] = portmap; -+ -+ xrx200sw_fixup_pvids(); -+ -+ return 0; -+} -+ -+static int xrx200sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val) -+{ -+ int i; -+ unsigned short ports, tags; -+ struct xrx200_pce_table_entry tem; -+ -+ tem.table = XRX200_PCE_VLANMAP_IDX; -+ tem.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tem); -+ -+ ports = tem.val[1]; -+ tags = tem.val[2]; -+ -+ for (i = 0; i < XRX200_MAX_PORT; i++) { -+ struct switch_port *p; -+ -+ if (!(ports & (1 << i))) -+ continue; -+ -+ p = &val->value.ports[val->len++]; -+ p->id = i; -+ if (tags & (1 << i)) -+ p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); -+ else -+ p->flags = 0; -+ } -+ -+ return 0; -+} -+ -+static int xrx200sw_set_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct xrx200_pce_table_entry tev; -+ -+ tev.table = XRX200_PCE_ACTVLAN_IDX; -+ tev.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tev); -+ -+ if (tev.key[0] == 0) -+ return -EINVAL; -+ -+ tev.valid = val->value.i; -+ xrx200_pce_table_entry_write(&tev); -+ -+ xrx200sw_fixup_pvids(); -+ return 0; -+} -+ -+static int xrx200sw_get_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct xrx200_pce_table_entry tev; -+ -+ tev.table = XRX200_PCE_ACTVLAN_IDX; -+ tev.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tev); -+ val->value.i = tev.valid; -+ -+ return 0; -+} -+ -+// port -+static int xrx200sw_get_port_pvid(struct switch_dev *dev, int port, int *val) -+{ -+ struct xrx200_pce_table_entry tev; -+ -+ if (port >= XRX200_MAX_PORT) -+ return -EINVAL; -+ -+ tev.table = XRX200_PCE_ACTVLAN_IDX; -+ tev.index = xrx200sw_read_x(XRX200_PCE_DEFPVID_PVID, port); -+ xrx200_pce_table_entry_read(&tev); -+ -+ *val = tev.key[0]; -+ return 0; -+} -+ -+static int xrx200sw_get_port_link(struct switch_dev *dev, -+ int port, -+ struct switch_port_link *link) -+{ -+ if (port >= XRX200_MAX_PORT) -+ return -EINVAL; -+ -+ link->link = xrx200sw_read_x(XRX200_MAC_PSTAT_LSTAT, port); -+ if (!link->link) -+ return 0; -+ -+ link->duplex = xrx200sw_read_x(XRX200_MAC_PSTAT_FDUP, port); -+ -+ link->rx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0010); -+ link->tx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0020); -+ link->aneg = !(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port)); -+ -+ link->speed = SWITCH_PORT_SPEED_10; -+ if (xrx200sw_read_x(XRX200_MAC_PSTAT_MBIT, port)) -+ link->speed = SWITCH_PORT_SPEED_100; -+ if (xrx200sw_read_x(XRX200_MAC_PSTAT_GBIT, port)) -+ link->speed = SWITCH_PORT_SPEED_1000; -+ -+ return 0; -+} -+ -+static int xrx200sw_set_port_link(struct switch_dev *dev, int port, -+ struct switch_port_link *link) -+{ -+ if (port >= XRX200_MAX_PORT) -+ return -EINVAL; -+ -+ return switch_generic_set_link(dev, port, link); -+} -+ -+static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val); -+static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg); -+ -+static int xrx200sw_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value) -+{ -+ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); -+ -+ *value = xrx200_mdio_rd(hw->mii_bus, hw->phy_addr[addr], reg); -+ -+ return 0; -+} -+ -+static int xrx200sw_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value) -+{ -+ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); -+ -+ return xrx200_mdio_wr(hw->mii_bus, hw->phy_addr[addr], reg, value); -+} -+ -+static int xrx200_set_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ if (val->port_vlan >= XRX200_MAX_PORT) -+ return -EINVAL; -+ -+ if ((attr->max > 0) && (val->value.i > attr->max)) -+ return -EINVAL; -+ -+ xrx200sw_write_x(val->value.i, attr->id, val->port_vlan); -+ return 0; -+} -+ -+static int xrx200_get_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ if (val->port_vlan >= XRX200_MAX_PORT) -+ return -EINVAL; -+ -+ val->value.i = xrx200sw_read_x(attr->id, val->port_vlan); -+ return 0; -+} -+ -+// attributes -+static struct switch_attr xrx200sw_globals[] = { -+ { -+ .type = SWITCH_TYPE_INT, -+ .set = xrx200_set_vlan_mode_enable, -+ .get = xrx200_get_vlan_mode_enable, -+ .name = "enable_vlan", -+ .description = "Enable VLAN mode", -+ .max = 1}, -+}; -+ -+static struct switch_attr xrx200sw_port[] = { -+ { -+ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_UVR), -+ .name = "uvr", -+ .description = "Unknown VLAN Rule", -+ .max = 1, -+ }, -+ { -+ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VSR), -+ .name = "vsr", -+ .description = "VLAN Security Rule", -+ .max = 1, -+ }, -+ { -+ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VINR), -+ .name = "vinr", -+ .description = "VLAN Ingress Tag Rule", -+ .max = 2, -+ }, -+ { -+ XRX200_PORT_REGATTR(XRX200_PCE_PCTRL_0_TVM), -+ .name = "tvm", -+ .description = "Transparent VLAN Mode", -+ .max = 1, -+ }, -+}; -+ -+static struct switch_attr xrx200sw_vlan[] = { -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "vid", -+ .description = "VLAN ID (0-4094)", -+ .set = xrx200sw_set_vlan_vid, -+ .get = xrx200sw_get_vlan_vid, -+ .max = 4094, -+ }, -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "enable", -+ .description = "Enable VLAN", -+ .set = xrx200sw_set_vlan_enable, -+ .get = xrx200sw_get_vlan_enable, -+ .max = 1, -+ }, -+}; -+ -+static const struct switch_dev_ops xrx200sw_ops = { -+ .attr_global = { -+ .attr = xrx200sw_globals, -+ .n_attr = ARRAY_SIZE(xrx200sw_globals), -+ }, -+ .attr_port = { -+ .attr = xrx200sw_port, -+ .n_attr = ARRAY_SIZE(xrx200sw_port), -+ }, -+ .attr_vlan = { -+ .attr = xrx200sw_vlan, -+ .n_attr = ARRAY_SIZE(xrx200sw_vlan), -+ }, -+ .get_vlan_ports = xrx200sw_get_vlan_ports, -+ .set_vlan_ports = xrx200sw_set_vlan_ports, -+ .get_port_pvid = xrx200sw_get_port_pvid, -+ .reset_switch = xrx200sw_reset_switch, -+ .get_port_link = xrx200sw_get_port_link, -+ .set_port_link = xrx200sw_set_port_link, -+// .get_port_stats = xrx200sw_get_port_stats, //TODO -+ .phy_read16 = xrx200sw_phy_read16, -+ .phy_write16 = xrx200sw_phy_write16, -+}; -+ -+static int xrx200sw_init(struct xrx200_hw *hw) -+{ -+ int netdev_num; -+ -+ for (netdev_num = 0; netdev_num < hw->num_devs; netdev_num++) -+ { -+ struct switch_dev *swdev; -+ struct net_device *dev = hw->devs[netdev_num]; -+ struct xrx200_priv *priv = netdev_priv(dev); -+ if (!priv->sw) -+ continue; -+ -+ swdev = &hw->swdev; -+ -+ swdev->name = "Lantiq XRX200 Switch"; -+ swdev->vlans = XRX200_MAX_VLAN; -+ swdev->ports = XRX200_MAX_PORT; -+ swdev->cpu_port = 6; -+ swdev->ops = &xrx200sw_ops; -+ -+ register_switch(swdev, dev); -+ return 0; // enough switches -+ } -+ return 0; -+} -+ -+static int xrx200_open(struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ int i; -+ -+ for (i = 0; i < XRX200_MAX_DMA; i++) { -+ if (!priv->hw->chan[i].dma.irq) -+ continue; -+ spin_lock_bh(&priv->hw->chan[i].lock); -+ if (!priv->hw->chan[i].refcount) { -+ if (XRX200_DMA_IS_RX(i)) -+ napi_enable(&priv->hw->chan[i].napi); -+ ltq_dma_open(&priv->hw->chan[i].dma); -+ } -+ priv->hw->chan[i].refcount++; -+ spin_unlock_bh(&priv->hw->chan[i].lock); -+ } -+ for (i = 0; i < priv->num_port; i++) -+ if (priv->port[i].phydev) -+ phy_start(priv->port[i].phydev); -+ netif_wake_queue(dev); -+ -+ return 0; -+} -+ -+static int xrx200_close(struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ int i; -+ -+ netif_stop_queue(dev); -+ -+ for (i = 0; i < priv->num_port; i++) -+ if (priv->port[i].phydev) -+ phy_stop(priv->port[i].phydev); -+ -+ for (i = 0; i < XRX200_MAX_DMA; i++) { -+ if (!priv->hw->chan[i].dma.irq) -+ continue; -+ -+ priv->hw->chan[i].refcount--; -+ if (!priv->hw->chan[i].refcount) { -+ if (XRX200_DMA_IS_RX(i)) -+ napi_disable(&priv->hw->chan[i].napi); -+ spin_lock_bh(&priv->hw->chan[i].lock); -+ ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma); -+ spin_unlock_bh(&priv->hw->chan[i].lock); -+ } -+ } -+ -+ return 0; -+} -+ -+static int xrx200_alloc_skb(struct xrx200_chan *ch) -+{ -+#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD) -+ ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD); -+ if (!ch->skb[ch->dma.desc]) -+ goto skip; -+ -+ skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD); -+ ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(ch->dma.dev, -+ ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN, -+ DMA_FROM_DEVICE); -+ ch->dma.desc_base[ch->dma.desc].addr = -+ CPHYSADDR(ch->skb[ch->dma.desc]->data); -+ skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); -+ -+skip: -+ ch->dma.desc_base[ch->dma.desc].ctl = -+ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | -+ XRX200_DMA_DATA_LEN; -+ -+ return 0; -+} -+ -+static void xrx200_hw_receive(struct xrx200_chan *ch, int id) -+{ -+ struct net_device *dev = ch->devs[id]; -+ struct xrx200_priv *priv = netdev_priv(dev); -+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -+ struct sk_buff *skb = ch->skb[ch->dma.desc]; -+ int len = (desc->ctl & LTQ_DMA_SIZE_MASK); -+ int ret; -+ -+ ret = xrx200_alloc_skb(ch); -+ -+ ch->dma.desc++; -+ ch->dma.desc %= LTQ_DESC_NUM; -+ -+ if (ret) { -+ netdev_err(dev, -+ "failed to allocate new rx buffer\n"); -+ return; -+ } -+ -+ skb_put(skb, len); -+#ifdef SW_ROUTING -+ skb_pull(skb, 8); -+#endif -+ skb->dev = dev; -+ skb->protocol = eth_type_trans(skb, dev); -+ netif_receive_skb(skb); -+ priv->stats.rx_packets++; -+ priv->stats.rx_bytes+=len; -+} -+ -+static int xrx200_poll_rx(struct napi_struct *napi, int budget) -+{ -+ struct xrx200_chan *ch = container_of(napi, -+ struct xrx200_chan, napi); -+ struct xrx200_priv *priv = netdev_priv(ch->devs[0]); -+ int rx = 0; -+ int complete = 0; -+ -+ while ((rx < budget) && !complete) { -+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { -+#ifdef SW_ROUTING -+ struct sk_buff *skb = ch->skb[ch->dma.desc]; -+ u8 *special_tag = (u8*)skb->data; -+ int port = (special_tag[7] >> SPPID_SHIFT) & SPPID_MASK; -+ xrx200_hw_receive(ch, priv->hw->port_map[port]); -+#else -+ xrx200_hw_receive(ch, 0); -+#endif -+ rx++; -+ } else { -+ complete = 1; -+ } -+ } -+ -+ if (complete || !rx) { -+ napi_complete(&ch->napi); -+ ltq_dma_enable_irq(&ch->dma); -+ } -+ -+ return rx; -+} -+ -+static void xrx200_tx_housekeeping(unsigned long ptr) -+{ -+ struct xrx200_chan *ch = (struct xrx200_chan *) ptr; -+ int pkts = 0; -+ int i; -+ -+ spin_lock_bh(&ch->lock); -+ ltq_dma_ack_irq(&ch->dma); -+ while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { -+ struct sk_buff *skb = ch->skb[ch->tx_free]; -+ -+ pkts++; -+ ch->skb[ch->tx_free] = NULL; -+ dev_kfree_skb(skb); -+ memset(&ch->dma.desc_base[ch->tx_free], 0, -+ sizeof(struct ltq_dma_desc)); -+ ch->tx_free++; -+ ch->tx_free %= LTQ_DESC_NUM; -+ } -+ ltq_dma_enable_irq(&ch->dma); -+ spin_unlock_bh(&ch->lock); -+ -+ if (!pkts) -+ return; -+ -+ for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++) -+ netif_wake_queue(ch->devs[i]); -+} -+ -+static struct net_device_stats *xrx200_get_stats (struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ -+ return &priv->stats; -+} -+ -+static void xrx200_tx_timeout(struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ -+ printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name); -+ -+ priv->stats.tx_errors++; -+ netif_wake_queue(dev); -+} -+ -+static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ struct xrx200_chan *ch; -+ struct ltq_dma_desc *desc; -+ u32 byte_offset; -+ int ret = NETDEV_TX_OK; -+ int len; -+#ifdef SW_ROUTING -+ u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE; -+#endif -+ if(priv->id) -+ ch = &priv->hw->chan[XRX200_DMA_TX_2]; -+ else -+ ch = &priv->hw->chan[XRX200_DMA_TX]; -+ -+ desc = &ch->dma.desc_base[ch->dma.desc]; -+ -+ skb->dev = dev; -+ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; -+ -+#ifdef SW_ROUTING -+ if (is_multicast_ether_addr(eth_hdr(skb)->h_dest)) { -+ u16 port_map = priv->port_map; -+ -+ if (priv->sw && skb->protocol == htons(ETH_P_8021Q)) { -+ u16 vid; -+ int i; -+ -+ port_map = 0; -+ if (!__vlan_get_tag(skb, &vid)) { -+ for (i = 0; i < XRX200_MAX_VLAN; i++) { -+ if (priv->hw->vlan_vid[i] != vid) -+ continue; -+ port_map = priv->hw->vlan_port_map[i]; -+ break; -+ } -+ } -+ } -+ -+ special_tag |= (port_map << PORT_MAP_SHIFT) | -+ PORT_MAP_SEL | PORT_MAP_EN; -+ } -+ if(priv->wan) -+ special_tag |= (1 << DPID_SHIFT); -+ if(skb_headroom(skb) < 4) { -+ struct sk_buff *tmp = skb_realloc_headroom(skb, 4); -+ dev_kfree_skb_any(skb); -+ skb = tmp; -+ } -+ skb_push(skb, 4); -+ memcpy(skb->data, &special_tag, sizeof(u32)); -+ len += 4; -+#endif -+ -+ /* dma needs to start on a 16 byte aligned address */ -+ byte_offset = CPHYSADDR(skb->data) % 16; -+ -+ spin_lock_bh(&ch->lock); -+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { -+ netdev_err(dev, "tx ring full\n"); -+ netif_stop_queue(dev); -+ ret = NETDEV_TX_BUSY; -+ goto out; -+ } -+ -+ ch->skb[ch->dma.desc] = skb; -+ -+ netif_trans_update(dev); -+ -+ desc->addr = ((unsigned int) dma_map_single(ch->dma.dev, skb->data, len, -+ DMA_TO_DEVICE)) - byte_offset; -+ wmb(); -+ desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | -+ LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); -+ ch->dma.desc++; -+ ch->dma.desc %= LTQ_DESC_NUM; -+ if (ch->dma.desc == ch->tx_free) -+ netif_stop_queue(dev); -+ -+ -+ priv->stats.tx_packets++; -+ priv->stats.tx_bytes+=len; -+ -+out: -+ spin_unlock_bh(&ch->lock); -+ -+ return ret; -+} -+ -+static irqreturn_t xrx200_dma_irq(int irq, void *priv) -+{ -+ struct xrx200_hw *hw = priv; -+ int chnr = irq - XRX200_DMA_IRQ; -+ struct xrx200_chan *ch = &hw->chan[chnr]; -+ -+ ltq_dma_disable_irq(&ch->dma); -+ ltq_dma_ack_irq(&ch->dma); -+ -+ if (chnr % 2) -+ tasklet_schedule(&ch->tasklet); -+ else -+ napi_schedule(&ch->napi); -+ -+ return IRQ_HANDLED; -+} -+ -+static int xrx200_dma_init(struct device *dev, struct xrx200_hw *hw) -+{ -+ int i, err = 0; -+ -+ ltq_dma_init_port(DMA_PORT_ETOP); -+ -+ for (i = 0; i < 8 && !err; i++) { -+ int irq = XRX200_DMA_IRQ + i; -+ struct xrx200_chan *ch = &hw->chan[i]; -+ -+ spin_lock_init(&ch->lock); -+ -+ ch->idx = ch->dma.nr = i; -+ ch->dma.dev = dev; -+ -+ if (i == XRX200_DMA_TX) { -+ ltq_dma_alloc_tx(&ch->dma); -+ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw); -+ } else if (i == XRX200_DMA_TX_2) { -+ ltq_dma_alloc_tx(&ch->dma); -+ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx_2", hw); -+ } else if (i == XRX200_DMA_RX) { -+ ltq_dma_alloc_rx(&ch->dma); -+ for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; -+ ch->dma.desc++) -+ if (xrx200_alloc_skb(ch)) -+ err = -ENOMEM; -+ ch->dma.desc = 0; -+ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw); -+ } else -+ continue; -+ -+ if (!err) -+ ch->dma.irq = irq; -+ else -+ pr_err("net-xrx200: failed to request irq %d\n", irq); -+ } -+ -+ return err; -+} -+ -+#ifdef SW_POLLING -+static void xrx200_gmac_update(struct xrx200_port *port) -+{ -+ u16 phyaddr = port->phydev->mdio.addr & MDIO_PHY_ADDR_MASK; -+ u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK; -+ u16 miirate = 0; -+ -+ switch (port->phydev->speed) { -+ case SPEED_1000: -+ phyaddr |= MDIO_PHY_SPEED_G1; -+ miirate = MII_CFG_RATE_M125; -+ break; -+ -+ case SPEED_100: -+ phyaddr |= MDIO_PHY_SPEED_M100; -+ switch (miimode) { -+ case MII_CFG_MODE_RMIIM: -+ case MII_CFG_MODE_RMIIP: -+ miirate = MII_CFG_RATE_M50; -+ break; -+ default: -+ miirate = MII_CFG_RATE_M25; -+ break; -+ } -+ break; -+ -+ default: -+ phyaddr |= MDIO_PHY_SPEED_M10; -+ miirate = MII_CFG_RATE_M2P5; -+ break; -+ } -+ -+ if (port->phydev->link) -+ phyaddr |= MDIO_PHY_LINK_UP; -+ else -+ phyaddr |= MDIO_PHY_LINK_DOWN; -+ -+ if (port->phydev->duplex == DUPLEX_FULL) -+ phyaddr |= MDIO_PHY_FDUP_EN; -+ else -+ phyaddr |= MDIO_PHY_FDUP_DIS; -+ -+ ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num)); -+ ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num)); -+ udelay(1); -+} -+#else -+static void xrx200_gmac_update(struct xrx200_port *port) -+{ -+ -+} -+#endif -+ -+static void xrx200_mdio_link(struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ int i; -+ -+ for (i = 0; i < priv->num_port; i++) { -+ if (!priv->port[i].phydev) -+ continue; -+ -+ if (priv->port[i].link != priv->port[i].phydev->link) { -+ xrx200_gmac_update(&priv->port[i]); -+ priv->port[i].link = priv->port[i].phydev->link; -+ netdev_info(dev, "port %d %s link\n", -+ priv->port[i].num, -+ (priv->port[i].link)?("got"):("lost")); -+ } -+ } -+} -+ -+static inline int xrx200_mdio_poll(struct mii_bus *bus) -+{ -+ unsigned cnt = 10000; -+ -+ while (likely(cnt--)) { -+ unsigned ctrl = ltq_mdio_r32(MDIO_CTRL); -+ if ((ctrl & MDIO_BUSY) == 0) -+ return 0; -+ } -+ -+ return 1; -+} -+ -+static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) -+{ -+ if (xrx200_mdio_poll(bus)) -+ return 1; -+ -+ ltq_mdio_w32(val, MDIO_WRITE); -+ ltq_mdio_w32(MDIO_BUSY | MDIO_WR | -+ ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) | -+ (reg & MDIO_MASK), -+ MDIO_CTRL); -+ -+ return 0; -+} -+ -+static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg) -+{ -+ if (xrx200_mdio_poll(bus)) -+ return -1; -+ -+ ltq_mdio_w32(MDIO_BUSY | MDIO_RD | -+ ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) | -+ (reg & MDIO_MASK), -+ MDIO_CTRL); -+ -+ if (xrx200_mdio_poll(bus)) -+ return -1; -+ -+ return ltq_mdio_r32(MDIO_READ); -+} -+ -+static int xrx200_phy_has_link(struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ int i; -+ -+ for (i = 0; i < priv->num_port; i++) { -+ if (!priv->port[i].phydev) -+ continue; -+ -+ if (priv->port[i].phydev->link) -+ return 1; -+ } -+ -+ return 0; -+} -+ -+static void xrx200_phy_link_change(struct phy_device *phydev, bool up, bool do_carrier) -+{ -+ struct net_device *netdev = phydev->attached_dev; -+ -+ if (do_carrier) { -+ if (up) -+ netif_carrier_on(netdev); -+ else if (!xrx200_phy_has_link(netdev)) -+ netif_carrier_off(netdev); -+ } -+ -+ phydev->adjust_link(netdev); -+} -+ -+static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ struct phy_device *phydev = NULL; -+ unsigned val; -+ -+ phydev = mdiobus_get_phy(priv->hw->mii_bus, port->phy_addr); -+ -+ if (!phydev) { -+ netdev_err(dev, "no PHY found\n"); -+ return -ENODEV; -+ } -+ -+ phydev = phy_connect(dev, phydev_name(phydev), &xrx200_mdio_link, -+ port->phy_if); -+ -+ if (IS_ERR(phydev)) { -+ netdev_err(dev, "Could not attach to PHY\n"); -+ return PTR_ERR(phydev); -+ } -+ -+ phydev->supported &= (SUPPORTED_10baseT_Half -+ | SUPPORTED_10baseT_Full -+ | SUPPORTED_100baseT_Half -+ | SUPPORTED_100baseT_Full -+ | SUPPORTED_1000baseT_Half -+ | SUPPORTED_1000baseT_Full -+ | SUPPORTED_Autoneg -+ | SUPPORTED_MII -+ | SUPPORTED_TP); -+ phydev->advertising = phydev->supported; -+ port->phydev = phydev; -+ phydev->phy_link_change = xrx200_phy_link_change; -+ -+ phy_attached_info(phydev); -+ -+#ifdef SW_POLLING -+ phy_read_status(phydev); -+ -+ val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000); -+ val |= ADVERTIZE_MPD; -+ xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val); -+ xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040); -+ -+ phy_start_aneg(phydev); -+#endif -+ return 0; -+} -+ -+static void xrx200_port_config(struct xrx200_priv *priv, -+ const struct xrx200_port *port) -+{ -+ u16 miimode = 0; -+ -+ switch (port->num) { -+ case 0: /* xMII0 */ -+ case 1: /* xMII1 */ -+ switch (port->phy_if) { -+ case PHY_INTERFACE_MODE_MII: -+ if (port->flags & XRX200_PORT_TYPE_PHY) -+ /* MII MAC mode, connected to external PHY */ -+ miimode = MII_CFG_MODE_MIIM; -+ else -+ /* MII PHY mode, connected to external MAC */ -+ miimode = MII_CFG_MODE_MIIP; -+ break; -+ case PHY_INTERFACE_MODE_RMII: -+ if (port->flags & XRX200_PORT_TYPE_PHY) -+ /* RMII MAC mode, connected to external PHY */ -+ miimode = MII_CFG_MODE_RMIIM; -+ else -+ /* RMII PHY mode, connected to external MAC */ -+ miimode = MII_CFG_MODE_RMIIP; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ /* RGMII MAC mode, connected to external PHY */ -+ miimode = MII_CFG_MODE_RGMII; -+ break; -+ default: -+ break; -+ } -+ break; -+ case 2: /* internal GPHY0 */ -+ case 3: /* internal GPHY0 */ -+ case 4: /* internal GPHY1 */ -+ switch (port->phy_if) { -+ case PHY_INTERFACE_MODE_MII: -+ case PHY_INTERFACE_MODE_GMII: -+ /* MII MAC mode, connected to internal GPHY */ -+ miimode = MII_CFG_MODE_MIIM; -+ break; -+ default: -+ break; -+ } -+ break; -+ case 5: /* internal GPHY1 or xMII2 */ -+ switch (port->phy_if) { -+ case PHY_INTERFACE_MODE_MII: -+ /* MII MAC mode, connected to internal GPHY */ -+ miimode = MII_CFG_MODE_MIIM; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ /* RGMII MAC mode, connected to external PHY */ -+ miimode = MII_CFG_MODE_RGMII; -+ break; -+ default: -+ break; -+ } -+ break; -+ default: -+ break; -+ } -+ -+ ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN, -+ MII_CFG(port->num)); -+} -+ -+static int xrx200_init(struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ struct sockaddr mac; -+ int err, i; -+ -+#ifndef SW_POLLING -+ unsigned int reg = 0; -+ -+ /* enable auto polling */ -+ for (i = 0; i < priv->num_port; i++) -+ reg |= BIT(priv->port[i].num); -+ ltq_mdio_w32(reg, MDIO_CLK_CFG0); -+ ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1); -+#endif -+ -+ /* setup each port */ -+ for (i = 0; i < priv->num_port; i++) -+ xrx200_port_config(priv, &priv->port[i]); -+ -+ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); -+ if (!is_valid_ether_addr(mac.sa_data)) { -+ pr_warn("net-xrx200: invalid MAC, using random\n"); -+ eth_random_addr(mac.sa_data); -+ dev->addr_assign_type |= NET_ADDR_RANDOM; -+ } -+ -+ err = eth_mac_addr(dev, &mac); -+ if (err) -+ goto err_netdev; -+ -+ for (i = 0; i < priv->num_port; i++) -+ if (xrx200_mdio_probe(dev, &priv->port[i])) -+ pr_warn("xrx200-mdio: probing phy of port %d failed\n", -+ priv->port[i].num); -+ -+ return 0; -+ -+err_netdev: -+ unregister_netdev(dev); -+ free_netdev(dev); -+ return err; -+} -+ -+static void xrx200_pci_microcode(void) -+{ -+ int i; -+ -+ ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK, -+ PCE_TBL_CFG_ADWR, PCE_TBL_CTRL); -+ ltq_switch_w32(0, PCE_TBL_MASK); -+ -+ for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) { -+ ltq_switch_w32(i, PCE_TBL_ADDR); -+ ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0)); -+ ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1)); -+ ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2)); -+ ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3)); -+ -+ // start the table access: -+ ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL); -+ while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY); -+ } -+ -+ /* tell the switch that the microcode is loaded */ -+ ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0)); -+} -+ -+static void xrx200_hw_init(struct xrx200_hw *hw) -+{ -+ int i; -+ -+ /* enable clock gate */ -+ clk_enable(hw->clk); -+ -+ ltq_switch_w32(1, 0); -+ mdelay(100); -+ ltq_switch_w32(0, 0); -+ /* -+ * TODO: we should really disbale all phys/miis here and explicitly -+ * enable them in the device secific init function -+ */ -+ -+ /* disable port fetch/store dma */ -+ for (i = 0; i < 7; i++ ) { -+ ltq_switch_w32(0, FDMA_PCTRLx(i)); -+ ltq_switch_w32(0, SDMA_PCTRLx(i)); -+ } -+ -+ /* enable Switch */ -+ ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB); -+ -+ /* load the pce microcode */ -+ xrx200_pci_microcode(); -+ -+ /* Default unknown Broadcat/Multicast/Unicast port maps */ -+ ltq_switch_w32(0x40, PCE_PMAP1); -+ ltq_switch_w32(0x40, PCE_PMAP2); -+ ltq_switch_w32(0x40, PCE_PMAP3); -+ -+ /* RMON Counter Enable for all physical ports */ -+ for (i = 0; i < 7; i++) -+ ltq_switch_w32(0x1, BM_PCFG(i)); -+ -+ /* disable auto polling */ -+ ltq_mdio_w32(0x0, MDIO_CLK_CFG0); -+ -+ /* enable port statistic counters */ -+ for (i = 0; i < 7; i++) -+ ltq_switch_w32(0x1, BM_PCFGx(i)); -+ -+ /* set IPG to 12 */ -+ ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG); -+ -+#ifdef SW_ROUTING -+ /* enable status header, enable CRC */ -+ ltq_pmac_w32_mask(0, -+ PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, -+ PMAC_HD_CTL); -+#else -+ /* disable status header, enable CRC */ -+ ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS, -+ PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, -+ PMAC_HD_CTL); -+#endif -+ -+ /* enable port fetch/store dma & VLAN Modification */ -+ for (i = 0; i < 7; i++ ) { -+ ltq_switch_w32_mask(0, 0x19, FDMA_PCTRLx(i)); -+ ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i)); -+ ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0)); -+ } -+ -+ /* enable special tag insertion on cpu port */ -+ ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6)); -+ ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0)); -+ ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2)); -+ ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG); -+ xrx200sw_write_x(1, XRX200_BM_QUEUE_GCTRL_GL_MOD, 0); -+ -+ for (i = 0; i < XRX200_MAX_VLAN; i++) -+ hw->vlan_vid[i] = i; -+} -+ -+static void xrx200_hw_cleanup(struct xrx200_hw *hw) -+{ -+ int i; -+ -+ /* disable the switch */ -+ ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB); -+ -+ /* free the channels and IRQs */ -+ for (i = 0; i < 2; i++) { -+ ltq_dma_free(&hw->chan[i].dma); -+ if (hw->chan[i].dma.irq) -+ free_irq(hw->chan[i].dma.irq, hw); -+ } -+ -+ /* free the allocated RX ring */ -+ for (i = 0; i < LTQ_DESC_NUM; i++) -+ dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]); -+ -+ /* clear the mdio bus */ -+ mdiobus_unregister(hw->mii_bus); -+ mdiobus_free(hw->mii_bus); -+ -+ /* release the clock */ -+ clk_disable(hw->clk); -+ clk_put(hw->clk); -+} -+ -+static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np) -+{ -+ hw->mii_bus = mdiobus_alloc(); -+ if (!hw->mii_bus) -+ return -ENOMEM; -+ -+ hw->mii_bus->read = xrx200_mdio_rd; -+ hw->mii_bus->write = xrx200_mdio_wr; -+ hw->mii_bus->name = "lantiq,xrx200-mdio"; -+ snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); -+ -+ if (of_mdiobus_register(hw->mii_bus, np)) { -+ mdiobus_free(hw->mii_bus); -+ return -ENXIO; -+ } -+ -+ return 0; -+} -+ -+static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port) -+{ -+ const __be32 *addr, *id = of_get_property(port, "reg", NULL); -+ struct xrx200_port *p = &priv->port[priv->num_port]; -+ -+ if (!id) -+ return; -+ -+ memset(p, 0, sizeof(struct xrx200_port)); -+ p->phy_node = of_parse_phandle(port, "phy-handle", 0); -+ addr = of_get_property(p->phy_node, "reg", NULL); -+ if (!addr) -+ return; -+ -+ p->num = *id; -+ p->phy_addr = *addr; -+ p->phy_if = of_get_phy_mode(port); -+ if (p->phy_addr > 0x10) -+ p->flags = XRX200_PORT_TYPE_MAC; -+ else -+ p->flags = XRX200_PORT_TYPE_PHY; -+ priv->num_port++; -+ -+ p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags); -+ if (gpio_is_valid(p->gpio)) -+ if (!gpio_request(p->gpio, "phy-reset")) { -+ gpio_direction_output(p->gpio, -+ (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (1) : (0)); -+ udelay(100); -+ gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1)); -+ } -+ /* is this port a wan port ? */ -+ if (priv->wan) -+ priv->hw->wan_map |= BIT(p->num); -+ -+ priv->port_map |= BIT(p->num); -+ -+ /* store the port id in the hw struct so we can map ports -> devices */ -+ priv->hw->port_map[p->num] = priv->hw->num_devs; -+ -+ /* store the phy addr in the hw struct so we can map ports -> phys */ -+ priv->hw->phy_addr[p->num] = p->phy_addr; -+} -+ -+static const struct net_device_ops xrx200_netdev_ops = { -+ .ndo_init = xrx200_init, -+ .ndo_open = xrx200_open, -+ .ndo_stop = xrx200_close, -+ .ndo_start_xmit = xrx200_start_xmit, -+ .ndo_set_mac_address = eth_mac_addr, -+ .ndo_validate_addr = eth_validate_addr, -+ .ndo_get_stats = xrx200_get_stats, -+ .ndo_tx_timeout = xrx200_tx_timeout, -+}; -+ -+static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface, struct device *dev) -+{ -+ struct xrx200_priv *priv; -+ struct device_node *port; -+ const __be32 *wan; -+ const u8 *mac; -+ -+ /* alloc the network device */ -+ hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv)); -+ if (!hw->devs[hw->num_devs]) -+ return; -+ -+ /* setup the network device */ -+ strcpy(hw->devs[hw->num_devs]->name, "eth%d"); -+ hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops; -+ hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT; -+ hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM; -+ SET_NETDEV_DEV(hw->devs[hw->num_devs], dev); -+ -+ /* setup our private data */ -+ priv = netdev_priv(hw->devs[hw->num_devs]); -+ priv->hw = hw; -+ priv->id = hw->num_devs; -+ -+ mac = of_get_mac_address(iface); -+ if (mac) -+ memcpy(priv->mac, mac, ETH_ALEN); -+ -+ /* is this the wan interface ? */ -+ wan = of_get_property(iface, "lantiq,wan", NULL); -+ if (wan && (*wan == 1)) -+ priv->wan = 1; -+ -+ /* should the switch be enabled on this interface ? */ -+ if (of_find_property(iface, "lantiq,switch", NULL)) -+ priv->sw = 1; -+ -+ /* load the ports that are part of the interface */ -+ for_each_child_of_node(iface, port) -+ if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port")) -+ xrx200_of_port(priv, port); -+ -+ /* register the actual device */ -+ if (!register_netdev(hw->devs[hw->num_devs])) -+ hw->num_devs++; -+} -+ -+static struct xrx200_hw xrx200_hw; -+ -+static int xrx200_probe(struct platform_device *pdev) -+{ -+ struct resource *res[4]; -+ struct device_node *mdio_np, *iface_np, *phy_np; -+ struct of_phandle_iterator it; -+ int err; -+ int i; -+ -+ /* load the memory ranges */ -+ for (i = 0; i < 4; i++) { -+ res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i); -+ if (!res[i]) { -+ dev_err(&pdev->dev, "failed to get resources\n"); -+ return -ENOENT; -+ } -+ } -+ xrx200_switch_membase = devm_ioremap_resource(&pdev->dev, res[0]); -+ xrx200_mdio_membase = devm_ioremap_resource(&pdev->dev, res[1]); -+ xrx200_mii_membase = devm_ioremap_resource(&pdev->dev, res[2]); -+ xrx200_pmac_membase = devm_ioremap_resource(&pdev->dev, res[3]); -+ if (!xrx200_switch_membase || !xrx200_mdio_membase || -+ !xrx200_mii_membase || !xrx200_pmac_membase) { -+ dev_err(&pdev->dev, "failed to request and remap io ranges \n"); -+ return -ENOMEM; -+ } -+ -+ of_for_each_phandle(&it, err, pdev->dev.of_node, "lantiq,phys", NULL, 0) { -+ phy_np = it.node; -+ if (phy_np) { -+ struct platform_device *phy = of_find_device_by_node(phy_np); -+ -+ of_node_put(phy_np); -+ if (!platform_get_drvdata(phy)) -+ return -EPROBE_DEFER; -+ } -+ } -+ -+ /* get the clock */ -+ xrx200_hw.clk = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(xrx200_hw.clk)) { -+ dev_err(&pdev->dev, "failed to get clock\n"); -+ return PTR_ERR(xrx200_hw.clk); -+ } -+ -+ /* bring up the dma engine and IP core */ -+ xrx200_dma_init(&pdev->dev, &xrx200_hw); -+ xrx200_hw_init(&xrx200_hw); -+ tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX]); -+ tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX_2].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX_2]); -+ -+ /* bring up the mdio bus */ -+ mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL, -+ "lantiq,xrx200-mdio"); -+ if (mdio_np) -+ if (xrx200_of_mdio(&xrx200_hw, mdio_np)) -+ dev_err(&pdev->dev, "mdio probe failed\n"); -+ -+ /* load the interfaces */ -+ for_each_child_of_node(pdev->dev.of_node, iface_np) -+ if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) { -+ if (xrx200_hw.num_devs < XRX200_MAX_DEV) -+ xrx200_of_iface(&xrx200_hw, iface_np, &pdev->dev); -+ else -+ dev_err(&pdev->dev, -+ "only %d interfaces allowed\n", -+ XRX200_MAX_DEV); -+ } -+ -+ if (!xrx200_hw.num_devs) { -+ xrx200_hw_cleanup(&xrx200_hw); -+ dev_err(&pdev->dev, "failed to load interfaces\n"); -+ return -ENOENT; -+ } -+ -+ xrx200sw_init(&xrx200_hw); -+ -+ /* set wan port mask */ -+ ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN); -+ -+ for (i = 0; i < xrx200_hw.num_devs; i++) { -+ xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i]; -+ xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i]; -+ xrx200_hw.chan[XRX200_DMA_TX_2].devs[i] = xrx200_hw.devs[i]; -+ } -+ -+ /* setup NAPI */ -+ init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev); -+ netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev, -+ &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32); -+ -+ platform_set_drvdata(pdev, &xrx200_hw); -+ -+ return 0; -+} -+ -+static int xrx200_remove(struct platform_device *pdev) -+{ -+ struct net_device *dev = platform_get_drvdata(pdev); -+ struct xrx200_priv *priv; -+ -+ if (!dev) -+ return 0; -+ -+ priv = netdev_priv(dev); -+ -+ /* free stack related instances */ -+ netif_stop_queue(dev); -+ netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi); -+ -+ /* shut down hardware */ -+ xrx200_hw_cleanup(&xrx200_hw); -+ -+ /* remove the actual device */ -+ unregister_netdev(dev); -+ free_netdev(dev); -+ -+ return 0; -+} -+ -+static const struct of_device_id xrx200_match[] = { -+ { .compatible = "lantiq,xrx200-net" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, xrx200_match); -+ -+static struct platform_driver xrx200_driver = { -+ .probe = xrx200_probe, -+ .remove = xrx200_remove, -+ .driver = { -+ .name = "lantiq,xrx200-net", -+ .of_match_table = xrx200_match, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+module_platform_driver(xrx200_driver); -+ -+MODULE_AUTHOR("John Crispin "); -+MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet"); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/net/ethernet/lantiq_xrx200_sw.h -@@ -0,0 +1,1328 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2013 Antonios Vamporakis -+ * -+ * VR9 switch registers extracted from 310TUJ0 switch api -+ * WARNING mult values of 0x00 may not be correct -+ * -+ */ -+ -+enum { -+// XRX200_ETHSW_SWRES, /* Ethernet Switch ResetControl Register */ -+// XRX200_ETHSW_SWRES_R1, /* Hardware Reset */ -+// XRX200_ETHSW_SWRES_R0, /* Register Configuration */ -+// XRX200_ETHSW_CLK_MAC_GAT, /* Ethernet Switch Clock ControlRegister */ -+// XRX200_ETHSW_CLK_EXP_SLEEP, /* Exponent to put system into sleep */ -+// XRX200_ETHSW_CLK_EXP_WAKE, /* Exponent to wake up system */ -+// XRX200_ETHSW_CLK_CLK2_EN, /* CLK2 Input for MAC */ -+// XRX200_ETHSW_CLK_EXT_DIV_EN, /* External Clock Divider Enable */ -+// XRX200_ETHSW_CLK_RAM_DBG_EN, /* Clock Gating Enable */ -+// XRX200_ETHSW_CLK_REG_GAT_EN, /* Clock Gating Enable */ -+// XRX200_ETHSW_CLK_GAT_EN, /* Clock Gating Enable */ -+// XRX200_ETHSW_CLK_MAC_GAT_EN, /* Clock Gating Enable */ -+// XRX200_ETHSW_DBG_STEP, /* Ethernet Switch Debug ControlRegister */ -+// XRX200_ETHSW_DBG_CLK_SEL, /* Trigger Enable */ -+// XRX200_ETHSW_DBG_MON_EN, /* Monitoring Enable */ -+// XRX200_ETHSW_DBG_TRIG_EN, /* Trigger Enable */ -+// XRX200_ETHSW_DBG_MODE, /* Debug Mode */ -+// XRX200_ETHSW_DBG_STEP_TIME, /* Clock Step Size */ -+// XRX200_ETHSW_SSB_MODE, /* Ethernet Switch SharedSegment Buffer Mode Register */ -+// XRX200_ETHSW_SSB_MODE_ADDE, /* Memory Address */ -+// XRX200_ETHSW_SSB_MODE_MODE, /* Memory Access Mode */ -+// XRX200_ETHSW_SSB_ADDR, /* Ethernet Switch SharedSegment Buffer Address Register */ -+// XRX200_ETHSW_SSB_ADDR_ADDE, /* Memory Address */ -+// XRX200_ETHSW_SSB_DATA, /* Ethernet Switch SharedSegment Buffer Data Register */ -+// XRX200_ETHSW_SSB_DATA_DATA, /* Data Value */ -+// XRX200_ETHSW_CAP_0, /* Ethernet Switch CapabilityRegister 0 */ -+// XRX200_ETHSW_CAP_0_SPEED, /* Clock frequency */ -+// XRX200_ETHSW_CAP_1, /* Ethernet Switch CapabilityRegister 1 */ -+// XRX200_ETHSW_CAP_1_GMAC, /* MAC operation mode */ -+// XRX200_ETHSW_CAP_1_QUEUE, /* Number of queues */ -+// XRX200_ETHSW_CAP_1_VPORTS, /* Number of virtual ports */ -+// XRX200_ETHSW_CAP_1_PPORTS, /* Number of physical ports */ -+// XRX200_ETHSW_CAP_2, /* Ethernet Switch CapabilityRegister 2 */ -+// XRX200_ETHSW_CAP_2_PACKETS, /* Number of packets */ -+// XRX200_ETHSW_CAP_3, /* Ethernet Switch CapabilityRegister 3 */ -+// XRX200_ETHSW_CAP_3_METERS, /* Number of traffic meters */ -+// XRX200_ETHSW_CAP_3_SHAPERS, /* Number of traffic shapers */ -+// XRX200_ETHSW_CAP_4, /* Ethernet Switch CapabilityRegister 4 */ -+// XRX200_ETHSW_CAP_4_PPPOE, /* PPPoE table size */ -+// XRX200_ETHSW_CAP_4_VLAN, /* Active VLAN table size */ -+// XRX200_ETHSW_CAP_5, /* Ethernet Switch CapabilityRegister 5 */ -+// XRX200_ETHSW_CAP_5_IPPLEN, /* IP packet length table size */ -+// XRX200_ETHSW_CAP_5_PROT, /* Protocol table size */ -+// XRX200_ETHSW_CAP_6, /* Ethernet Switch CapabilityRegister 6 */ -+// XRX200_ETHSW_CAP_6_MACDASA, /* MAC DA/SA table size */ -+// XRX200_ETHSW_CAP_6_APPL, /* Application table size */ -+// XRX200_ETHSW_CAP_7, /* Ethernet Switch CapabilityRegister 7 */ -+// XRX200_ETHSW_CAP_7_IPDASAM, /* IP DA/SA MSB table size */ -+// XRX200_ETHSW_CAP_7_IPDASAL, /* IP DA/SA LSB table size */ -+// XRX200_ETHSW_CAP_8, /* Ethernet Switch CapabilityRegister 8 */ -+// XRX200_ETHSW_CAP_8_MCAST, /* Multicast table size */ -+// XRX200_ETHSW_CAP_9, /* Ethernet Switch CapabilityRegister 9 */ -+// XRX200_ETHSW_CAP_9_FLAGG, /* Flow Aggregation table size */ -+// XRX200_ETHSW_CAP_10, /* Ethernet Switch CapabilityRegister 10 */ -+// XRX200_ETHSW_CAP_10_MACBT, /* MAC bridging table size */ -+// XRX200_ETHSW_CAP_11, /* Ethernet Switch CapabilityRegister 11 */ -+// XRX200_ETHSW_CAP_11_BSIZEL, /* Packet buffer size (lower part, in byte) */ -+// XRX200_ETHSW_CAP_12, /* Ethernet Switch CapabilityRegister 12 */ -+// XRX200_ETHSW_CAP_12_BSIZEH, /* Packet buffer size (higher part, in byte) */ -+// XRX200_ETHSW_VERSION_REV, /* Ethernet Switch VersionRegister */ -+// XRX200_ETHSW_VERSION_MOD_ID, /* Module Identification */ -+// XRX200_ETHSW_VERSION_REV_ID, /* Hardware Revision Identification */ -+// XRX200_ETHSW_IER, /* Interrupt Enable Register */ -+// XRX200_ETHSW_IER_FDMAIE, /* Fetch DMA Interrupt Enable */ -+// XRX200_ETHSW_IER_SDMAIE, /* Store DMA Interrupt Enable */ -+// XRX200_ETHSW_IER_MACIE, /* Ethernet MAC Interrupt Enable */ -+// XRX200_ETHSW_IER_PCEIE, /* Parser and Classification Engine Interrupt Enable */ -+// XRX200_ETHSW_IER_BMIE, /* Buffer Manager Interrupt Enable */ -+// XRX200_ETHSW_ISR, /* Interrupt Status Register */ -+// XRX200_ETHSW_ISR_FDMAINT, /* Fetch DMA Interrupt */ -+// XRX200_ETHSW_ISR_SDMAINT, /* Store DMA Interrupt */ -+// XRX200_ETHSW_ISR_MACINT, /* Ethernet MAC Interrupt */ -+// XRX200_ETHSW_ISR_PCEINT, /* Parser and Classification Engine Interrupt */ -+// XRX200_ETHSW_ISR_BMINT, /* Buffer Manager Interrupt */ -+// XRX200_ETHSW_SPARE_0, /* Ethernet Switch SpareCells 0 */ -+// XRX200_ETHSW_SPARE_0_SPARE, /* SPARE0 */ -+// XRX200_ETHSW_SPARE_1, /* Ethernet Switch SpareCells 1 */ -+// XRX200_ETHSW_SPARE_1_SPARE, /* SPARE1 */ -+// XRX200_ETHSW_SPARE_2, /* Ethernet Switch SpareCells 2 */ -+// XRX200_ETHSW_SPARE_2_SPARE, /* SPARE2 */ -+// XRX200_ETHSW_SPARE_3, /* Ethernet Switch SpareCells 3 */ -+// XRX200_ETHSW_SPARE_3_SPARE, /* SPARE3 */ -+// XRX200_ETHSW_SPARE_4, /* Ethernet Switch SpareCells 4 */ -+// XRX200_ETHSW_SPARE_4_SPARE, /* SPARE4 */ -+// XRX200_ETHSW_SPARE_5, /* Ethernet Switch SpareCells 5 */ -+// XRX200_ETHSW_SPARE_5_SPARE, /* SPARE5 */ -+// XRX200_ETHSW_SPARE_6, /* Ethernet Switch SpareCells 6 */ -+// XRX200_ETHSW_SPARE_6_SPARE, /* SPARE6 */ -+// XRX200_ETHSW_SPARE_7, /* Ethernet Switch SpareCells 7 */ -+// XRX200_ETHSW_SPARE_7_SPARE, /* SPARE7 */ -+// XRX200_ETHSW_SPARE_8, /* Ethernet Switch SpareCells 8 */ -+// XRX200_ETHSW_SPARE_8_SPARE, /* SPARE8 */ -+// XRX200_ETHSW_SPARE_9, /* Ethernet Switch SpareCells 9 */ -+// XRX200_ETHSW_SPARE_9_SPARE, /* SPARE9 */ -+// XRX200_ETHSW_SPARE_10, /* Ethernet Switch SpareCells 10 */ -+// XRX200_ETHSW_SPARE_10_SPARE, /* SPARE10 */ -+// XRX200_ETHSW_SPARE_11, /* Ethernet Switch SpareCells 11 */ -+// XRX200_ETHSW_SPARE_11_SPARE, /* SPARE11 */ -+// XRX200_ETHSW_SPARE_12, /* Ethernet Switch SpareCells 12 */ -+// XRX200_ETHSW_SPARE_12_SPARE, /* SPARE12 */ -+// XRX200_ETHSW_SPARE_13, /* Ethernet Switch SpareCells 13 */ -+// XRX200_ETHSW_SPARE_13_SPARE, /* SPARE13 */ -+// XRX200_ETHSW_SPARE_14, /* Ethernet Switch SpareCells 14 */ -+// XRX200_ETHSW_SPARE_14_SPARE, /* SPARE14 */ -+// XRX200_ETHSW_SPARE_15, /* Ethernet Switch SpareCells 15 */ -+// XRX200_ETHSW_SPARE_15_SPARE, /* SPARE15 */ -+// XRX200_BM_RAM_VAL_3, /* RAM Value Register 3 */ -+// XRX200_BM_RAM_VAL_3_VAL3, /* Data value [15:0] */ -+// XRX200_BM_RAM_VAL_2, /* RAM Value Register 2 */ -+// XRX200_BM_RAM_VAL_2_VAL2, /* Data value [15:0] */ -+// XRX200_BM_RAM_VAL_1, /* RAM Value Register 1 */ -+// XRX200_BM_RAM_VAL_1_VAL1, /* Data value [15:0] */ -+// XRX200_BM_RAM_VAL_0, /* RAM Value Register 0 */ -+// XRX200_BM_RAM_VAL_0_VAL0, /* Data value [15:0] */ -+// XRX200_BM_RAM_ADDR, /* RAM Address Register */ -+// XRX200_BM_RAM_ADDR_ADDR, /* RAM Address */ -+// XRX200_BM_RAM_CTRL, /* RAM Access Control Register */ -+// XRX200_BM_RAM_CTRL_BAS, /* Access Busy/Access Start */ -+// XRX200_BM_RAM_CTRL_OPMOD, /* Lookup Table Access Operation Mode */ -+// XRX200_BM_RAM_CTRL_ADDR, /* Address for RAM selection */ -+// XRX200_BM_FSQM_GCTRL, /* Free Segment Queue ManagerGlobal Control Register */ -+// XRX200_BM_FSQM_GCTRL_SEGNUM, /* Maximum Segment Number */ -+// XRX200_BM_CONS_SEG, /* Number of Consumed SegmentsRegister */ -+// XRX200_BM_CONS_SEG_FSEG, /* Number of Consumed Segments */ -+// XRX200_BM_CONS_PKT, /* Number of Consumed PacketPointers Register */ -+// XRX200_BM_CONS_PKT_FQP, /* Number of Consumed Packet Pointers */ -+// XRX200_BM_GCTRL_F, /* Buffer Manager Global ControlRegister 0 */ -+// XRX200_BM_GCTRL_BM_STA, /* Buffer Manager Initialization Status Bit */ -+// XRX200_BM_GCTRL_SAT, /* RMON Counter Update Mode */ -+// XRX200_BM_GCTRL_FR_RBC, /* Freeze RMON RX Bad Byte 64 Bit Counter */ -+// XRX200_BM_GCTRL_FR_RGC, /* Freeze RMON RX Good Byte 64 Bit Counter */ -+// XRX200_BM_GCTRL_FR_TGC, /* Freeze RMON TX Good Byte 64 Bit Counter */ -+// XRX200_BM_GCTRL_I_FIN, /* RAM initialization finished */ -+// XRX200_BM_GCTRL_CX_INI, /* PQM Context RAM initialization */ -+// XRX200_BM_GCTRL_FP_INI, /* FPQM RAM initialization */ -+// XRX200_BM_GCTRL_FS_INI, /* FSQM RAM initialization */ -+// XRX200_BM_GCTRL_R_SRES, /* Software Reset for RMON */ -+// XRX200_BM_GCTRL_S_SRES, /* Software Reset for Scheduler */ -+// XRX200_BM_GCTRL_A_SRES, /* Software Reset for AVG */ -+// XRX200_BM_GCTRL_P_SRES, /* Software Reset for PQM */ -+// XRX200_BM_GCTRL_F_SRES, /* Software Reset for FSQM */ -+// XRX200_BM_QUEUE_GCTRL, /* Queue Manager GlobalControl Register 0 */ -+ XRX200_BM_QUEUE_GCTRL_GL_MOD, /* WRED Mode Signal */ -+// XRX200_BM_QUEUE_GCTRL_AQUI, /* Average Queue Update Interval */ -+// XRX200_BM_QUEUE_GCTRL_AQWF, /* Average Queue Weight Factor */ -+// XRX200_BM_QUEUE_GCTRL_QAVGEN, /* Queue Average Calculation Enable */ -+// XRX200_BM_QUEUE_GCTRL_DPROB, /* Drop Probability Profile */ -+// XRX200_BM_WRED_RTH_0, /* WRED Red Threshold Register0 */ -+// XRX200_BM_WRED_RTH_0_MINTH, /* Minimum Threshold */ -+// XRX200_BM_WRED_RTH_1, /* WRED Red Threshold Register1 */ -+// XRX200_BM_WRED_RTH_1_MAXTH, /* Maximum Threshold */ -+// XRX200_BM_WRED_YTH_0, /* WRED Yellow ThresholdRegister 0 */ -+// XRX200_BM_WRED_YTH_0_MINTH, /* Minimum Threshold */ -+// XRX200_BM_WRED_YTH_1, /* WRED Yellow ThresholdRegister 1 */ -+// XRX200_BM_WRED_YTH_1_MAXTH, /* Maximum Threshold */ -+// XRX200_BM_WRED_GTH_0, /* WRED Green ThresholdRegister 0 */ -+// XRX200_BM_WRED_GTH_0_MINTH, /* Minimum Threshold */ -+// XRX200_BM_WRED_GTH_1, /* WRED Green ThresholdRegister 1 */ -+// XRX200_BM_WRED_GTH_1_MAXTH, /* Maximum Threshold */ -+// XRX200_BM_DROP_GTH_0_THR, /* Drop Threshold ConfigurationRegister 0 */ -+// XRX200_BM_DROP_GTH_0_THR_FQ, /* Threshold for frames marked red */ -+// XRX200_BM_DROP_GTH_1_THY, /* Drop Threshold ConfigurationRegister 1 */ -+// XRX200_BM_DROP_GTH_1_THY_FQ, /* Threshold for frames marked yellow */ -+// XRX200_BM_DROP_GTH_2_THG, /* Drop Threshold ConfigurationRegister 2 */ -+// XRX200_BM_DROP_GTH_2_THG_FQ, /* Threshold for frames marked green */ -+// XRX200_BM_IER, /* Buffer Manager Global InterruptEnable Register */ -+// XRX200_BM_IER_CNT4, /* Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */ -+// XRX200_BM_IER_CNT3, /* Counter Group 3 (RMON-PQM) Interrupt Enable */ -+// XRX200_BM_IER_CNT2, /* Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */ -+// XRX200_BM_IER_CNT1, /* Counter Group 1 (RMON-QFETCH) Interrupt Enable */ -+// XRX200_BM_IER_CNT0, /* Counter Group 0 (RMON-QSTOR) Interrupt Enable */ -+// XRX200_BM_IER_DEQ, /* PQM dequeue Interrupt Enable */ -+// XRX200_BM_IER_ENQ, /* PQM Enqueue Interrupt Enable */ -+// XRX200_BM_IER_FSQM, /* Buffer Empty Interrupt Enable */ -+// XRX200_BM_ISR, /* Buffer Manager Global InterruptStatus Register */ -+// XRX200_BM_ISR_CNT4, /* Counter Group 4 Interrupt */ -+// XRX200_BM_ISR_CNT3, /* Counter Group 3 Interrupt */ -+// XRX200_BM_ISR_CNT2, /* Counter Group 2 Interrupt */ -+// XRX200_BM_ISR_CNT1, /* Counter Group 1 Interrupt */ -+// XRX200_BM_ISR_CNT0, /* Counter Group 0 Interrupt */ -+// XRX200_BM_ISR_DEQ, /* PQM dequeue Interrupt Enable */ -+// XRX200_BM_ISR_ENQ, /* PQM Enqueue Interrupt */ -+// XRX200_BM_ISR_FSQM, /* Buffer Empty Interrupt */ -+// XRX200_BM_CISEL, /* Buffer Manager RMON CounterInterrupt Select Register */ -+// XRX200_BM_CISEL_PORT, /* Port Number */ -+// XRX200_BM_DEBUG_CTRL_DBG, /* Debug Control Register */ -+// XRX200_BM_DEBUG_CTRL_DBG_SEL, /* Select Signal for Debug Multiplexer */ -+// XRX200_BM_DEBUG_VAL_DBG, /* Debug Value Register */ -+// XRX200_BM_DEBUG_VAL_DBG_DAT, /* Debug Data Value */ -+// XRX200_BM_PCFG, /* Buffer Manager PortConfiguration Register */ -+// XRX200_BM_PCFG_CNTEN, /* RMON Counter Enable */ -+// XRX200_BM_RMON_CTRL_RAM1, /* Buffer ManagerRMON Control Register */ -+// XRX200_BM_RMON_CTRL_RAM2_RES, /* Software Reset for RMON RAM2 */ -+// XRX200_BM_RMON_CTRL_RAM1_RES, /* Software Reset for RMON RAM1 */ -+// XRX200_PQM_DP, /* Packet Queue ManagerDrop Probability Register */ -+// XRX200_PQM_DP_DPROB, /* Drop Probability Profile */ -+// XRX200_PQM_RS, /* Packet Queue ManagerRate Shaper Assignment Register */ -+// XRX200_PQM_RS_EN2, /* Rate Shaper 2 Enable */ -+// XRX200_PQM_RS_RS2, /* Rate Shaper 2 */ -+// XRX200_PQM_RS_EN1, /* Rate Shaper 1 Enable */ -+// XRX200_PQM_RS_RS1, /* Rate Shaper 1 */ -+// XRX200_RS_CTRL, /* Rate Shaper ControlRegister */ -+// XRX200_RS_CTRL_RSEN, /* Rate Shaper Enable */ -+// XRX200_RS_CBS, /* Rate Shaper CommittedBurst Size Register */ -+// XRX200_RS_CBS_CBS, /* Committed Burst Size */ -+// XRX200_RS_IBS, /* Rate Shaper InstantaneousBurst Size Register */ -+// XRX200_RS_IBS_IBS, /* Instantaneous Burst Size */ -+// XRX200_RS_CIR_EXP, /* Rate Shaper RateExponent Register */ -+// XRX200_RS_CIR_EXP_EXP, /* Exponent */ -+// XRX200_RS_CIR_MANT, /* Rate Shaper RateMantissa Register */ -+// XRX200_RS_CIR_MANT_MANT, /* Mantissa */ -+ XRX200_PCE_TBL_KEY_7, /* Table Key Data 7 */ -+// XRX200_PCE_TBL_KEY_7_KEY7, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_KEY_6, /* Table Key Data 6 */ -+// XRX200_PCE_TBL_KEY_6_KEY6, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_KEY_5, /* Table Key Data 5 */ -+// XRX200_PCE_TBL_KEY_5_KEY5, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_KEY_4, /* Table Key Data 4 */ -+// XRX200_PCE_TBL_KEY_4_KEY4, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_KEY_3, /* Table Key Data 3 */ -+// XRX200_PCE_TBL_KEY_3_KEY3, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_KEY_2, /* Table Key Data 2 */ -+// XRX200_PCE_TBL_KEY_2_KEY2, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_KEY_1, /* Table Key Data 1 */ -+// XRX200_PCE_TBL_KEY_1_KEY1, /* Key Value[31:16] */ -+ XRX200_PCE_TBL_KEY_0, /* Table Key Data 0 */ -+// XRX200_PCE_TBL_KEY_0_KEY0, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_MASK_0, /* Table Mask Write Register0 */ -+// XRX200_PCE_TBL_MASK_0_MASK0, /* Mask Pattern [15:0] */ -+ XRX200_PCE_TBL_VAL_4, /* Table Value Register4 */ -+// XRX200_PCE_TBL_VAL_4_VAL4, /* Data value [15:0] */ -+ XRX200_PCE_TBL_VAL_3, /* Table Value Register3 */ -+// XRX200_PCE_TBL_VAL_3_VAL3, /* Data value [15:0] */ -+ XRX200_PCE_TBL_VAL_2, /* Table Value Register2 */ -+// XRX200_PCE_TBL_VAL_2_VAL2, /* Data value [15:0] */ -+ XRX200_PCE_TBL_VAL_1, /* Table Value Register1 */ -+// XRX200_PCE_TBL_VAL_1_VAL1, /* Data value [15:0] */ -+ XRX200_PCE_TBL_VAL_0, /* Table Value Register0 */ -+// XRX200_PCE_TBL_VAL_0_VAL0, /* Data value [15:0] */ -+// XRX200_PCE_TBL_ADDR, /* Table Entry AddressRegister */ -+ XRX200_PCE_TBL_ADDR_ADDR, /* Table Address */ -+// XRX200_PCE_TBL_CTRL, /* Table Access ControlRegister */ -+ XRX200_PCE_TBL_CTRL_BAS, /* Access Busy/Access Start */ -+ XRX200_PCE_TBL_CTRL_TYPE, /* Lookup Entry Type */ -+ XRX200_PCE_TBL_CTRL_VLD, /* Lookup Entry Valid */ -+ XRX200_PCE_TBL_CTRL_GMAP, /* Group Map */ -+ XRX200_PCE_TBL_CTRL_OPMOD, /* Lookup Table Access Operation Mode */ -+ XRX200_PCE_TBL_CTRL_ADDR, /* Lookup Table Address */ -+// XRX200_PCE_TBL_STAT, /* Table General StatusRegister */ -+// XRX200_PCE_TBL_STAT_TBUSY, /* Table Access Busy */ -+// XRX200_PCE_TBL_STAT_TEMPT, /* Table Empty */ -+// XRX200_PCE_TBL_STAT_TFUL, /* Table Full */ -+// XRX200_PCE_AGE_0, /* Aging Counter ConfigurationRegister 0 */ -+// XRX200_PCE_AGE_0_EXP, /* Aging Counter Exponent Value */ -+// XRX200_PCE_AGE_1, /* Aging Counter ConfigurationRegister 1 */ -+// XRX200_PCE_AGE_1_MANT, /* Aging Counter Mantissa Value */ -+// XRX200_PCE_PMAP_1, /* Port Map Register 1 */ -+// XRX200_PCE_PMAP_1_MPMAP, /* Monitoring Port Map */ -+// XRX200_PCE_PMAP_2, /* Port Map Register 2 */ -+// XRX200_PCE_PMAP_2_DMCPMAP, /* Default Multicast Port Map */ -+// XRX200_PCE_PMAP_3, /* Port Map Register 3 */ -+// XRX200_PCE_PMAP_3_UUCMAP, /* Default Unknown Unicast Port Map */ -+// XRX200_PCE_GCTRL_0, /* PCE Global Control Register0 */ -+// XRX200_PCE_GCTRL_0_IGMP, /* IGMP Mode Selection */ -+ XRX200_PCE_GCTRL_0_VLAN, /* VLAN-aware Switching */ -+// XRX200_PCE_GCTRL_0_NOPM, /* No Port Map Forwarding */ -+// XRX200_PCE_GCTRL_0_SCONUC, /* Unknown Unicast Storm Control */ -+// XRX200_PCE_GCTRL_0_SCONMC, /* Multicast Storm Control */ -+// XRX200_PCE_GCTRL_0_SCONBC, /* Broadcast Storm Control */ -+// XRX200_PCE_GCTRL_0_SCONMOD, /* Storm Control Mode */ -+// XRX200_PCE_GCTRL_0_SCONMET, /* Storm Control Metering Instance */ -+// XRX200_PCE_GCTRL_0_MC_VALID, /* Access Request */ -+// XRX200_PCE_GCTRL_0_PLCKMOD, /* Port Lock Mode */ -+// XRX200_PCE_GCTRL_0_PLIMMOD, /* MAC Address Learning Limitation Mode */ -+// XRX200_PCE_GCTRL_0_MTFL, /* MAC Table Flushing */ -+// XRX200_PCE_GCTRL_1, /* PCE Global Control Register1 */ -+// XRX200_PCE_GCTRL_1_PCE_DIS, /* PCE Disable after currently processed packet */ -+// XRX200_PCE_GCTRL_1_LRNMOD, /* MAC Address Learning Mode */ -+// XRX200_PCE_TCM_GLOB_CTRL, /* Three-color MarkerGlobal Control Register */ -+// XRX200_PCE_TCM_GLOB_CTRL_DPRED, /* Re-marking Drop Precedence Red Encoding */ -+// XRX200_PCE_TCM_GLOB_CTRL_DPYEL, /* Re-marking Drop Precedence Yellow Encoding */ -+// XRX200_PCE_TCM_GLOB_CTRL_DPGRN, /* Re-marking Drop Precedence Green Encoding */ -+// XRX200_PCE_IGMP_CTRL, /* IGMP Control Register */ -+// XRX200_PCE_IGMP_CTRL_FAGEEN, /* Force Aging of Table Entries Enable */ -+// XRX200_PCE_IGMP_CTRL_FLEAVE, /* Fast Leave Enable */ -+// XRX200_PCE_IGMP_CTRL_DMRTEN, /* Default Maximum Response Time Enable */ -+// XRX200_PCE_IGMP_CTRL_JASUP, /* Join Aggregation Suppression Enable */ -+// XRX200_PCE_IGMP_CTRL_REPSUP, /* Report Suppression Enable */ -+// XRX200_PCE_IGMP_CTRL_SRPEN, /* Snooping of Router Port Enable */ -+// XRX200_PCE_IGMP_CTRL_ROB, /* Robustness Variable */ -+// XRX200_PCE_IGMP_CTRL_DMRT, /* IGMP Default Maximum Response Time */ -+// XRX200_PCE_IGMP_DRPM, /* IGMP Default RouterPort Map Register */ -+// XRX200_PCE_IGMP_DRPM_DRPM, /* IGMP Default Router Port Map */ -+// XRX200_PCE_IGMP_AGE_0, /* IGMP Aging Register0 */ -+// XRX200_PCE_IGMP_AGE_0_MANT, /* IGMP Group Aging Time Mantissa */ -+// XRX200_PCE_IGMP_AGE_0_EXP, /* IGMP Group Aging Time Exponent */ -+// XRX200_PCE_IGMP_AGE_1, /* IGMP Aging Register1 */ -+// XRX200_PCE_IGMP_AGE_1_MANT, /* IGMP Router Port Aging Time Mantissa */ -+// XRX200_PCE_IGMP_STAT, /* IGMP Status Register */ -+// XRX200_PCE_IGMP_STAT_IGPM, /* IGMP Port Map */ -+// XRX200_WOL_GLB_CTRL, /* Wake-on-LAN ControlRegister */ -+// XRX200_WOL_GLB_CTRL_PASSEN, /* WoL Password Enable */ -+// XRX200_WOL_DA_0, /* Wake-on-LAN DestinationAddress Register 0 */ -+// XRX200_WOL_DA_0_DA0, /* WoL Destination Address [15:0] */ -+// XRX200_WOL_DA_1, /* Wake-on-LAN DestinationAddress Register 1 */ -+// XRX200_WOL_DA_1_DA1, /* WoL Destination Address [31:16] */ -+// XRX200_WOL_DA_2, /* Wake-on-LAN DestinationAddress Register 2 */ -+// XRX200_WOL_DA_2_DA2, /* WoL Destination Address [47:32] */ -+// XRX200_WOL_PW_0, /* Wake-on-LAN Password Register0 */ -+// XRX200_WOL_PW_0_PW0, /* WoL Password [15:0] */ -+// XRX200_WOL_PW_1, /* Wake-on-LAN Password Register1 */ -+// XRX200_WOL_PW_1_PW1, /* WoL Password [31:16] */ -+// XRX200_WOL_PW_2, /* Wake-on-LAN Password Register2 */ -+// XRX200_WOL_PW_2_PW2, /* WoL Password [47:32] */ -+// XRX200_PCE_IER_0_PINT, /* Parser and ClassificationEngine Global Interrupt Enable Register 0 */ -+// XRX200_PCE_IER_0_PINT_15, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_14, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_13, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_12, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_11, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_10, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_9, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_8, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_7, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_6, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_5, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_4, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_3, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_2, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_1, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_0, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_1, /* Parser and ClassificationEngine Global Interrupt Enable Register 1 */ -+// XRX200_PCE_IER_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched Interrupt Enable */ -+// XRX200_PCE_IER_1_CPH2, /* Classification Phase 2 Ready Interrupt Enable */ -+// XRX200_PCE_IER_1_CPH1, /* Classification Phase 1 Ready Interrupt Enable */ -+// XRX200_PCE_IER_1_CPH0, /* Classification Phase 0 Ready Interrupt Enable */ -+// XRX200_PCE_IER_1_PRDY, /* Parser Ready Interrupt Enable */ -+// XRX200_PCE_IER_1_IGTF, /* IGMP Table Full Interrupt Enable */ -+// XRX200_PCE_IER_1_MTF, /* MAC Table Full Interrupt Enable */ -+// XRX200_PCE_ISR_0_PINT, /* Parser and ClassificationEngine Global Interrupt Status Register 0 */ -+// XRX200_PCE_ISR_0_PINT_15, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_14, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_13, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_12, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_11, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_10, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_9, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_8, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_7, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_6, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_5, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_4, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_3, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_2, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_1, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_0, /* Port Interrupt */ -+// XRX200_PCE_ISR_1, /* Parser and ClassificationEngine Global Interrupt Status Register 1 */ -+// XRX200_PCE_ISR_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched */ -+// XRX200_PCE_ISR_1_CPH2, /* Classification Phase 2 Ready Interrupt */ -+// XRX200_PCE_ISR_1_CPH1, /* Classification Phase 1 Ready Interrupt */ -+// XRX200_PCE_ISR_1_CPH0, /* Classification Phase 0 Ready Interrupt */ -+// XRX200_PCE_ISR_1_PRDY, /* Parser Ready Interrupt */ -+// XRX200_PCE_ISR_1_IGTF, /* IGMP Table Full Interrupt */ -+// XRX200_PCE_ISR_1_MTF, /* MAC Table Full Interrupt */ -+// XRX200_PARSER_STAT_FIFO, /* Parser Status Register */ -+// XRX200_PARSER_STAT_FSM_DAT_CNT, /* Parser FSM Data Counter */ -+// XRX200_PARSER_STAT_FSM_STATE, /* Parser FSM State */ -+// XRX200_PARSER_STAT_PKT_ERR, /* Packet error detected */ -+// XRX200_PARSER_STAT_FSM_FIN, /* Parser FSM finished */ -+// XRX200_PARSER_STAT_FSM_START, /* Parser FSM start */ -+// XRX200_PARSER_STAT_FIFO_RDY, /* Parser FIFO ready for read. */ -+// XRX200_PARSER_STAT_FIFO_FULL, /* Parser */ -+// XRX200_PCE_PCTRL_0, /* PCE Port ControlRegister 0 */ -+// XRX200_PCE_PCTRL_0_MCST, /* Multicast Forwarding Mode Selection */ -+// XRX200_PCE_PCTRL_0_EGSTEN, /* Table-based Egress Special Tag Enable */ -+// XRX200_PCE_PCTRL_0_IGSTEN, /* Ingress Special Tag Enable */ -+// XRX200_PCE_PCTRL_0_PCPEN, /* PCP Remarking Mode */ -+// XRX200_PCE_PCTRL_0_CLPEN, /* Class Remarking Mode */ -+// XRX200_PCE_PCTRL_0_DPEN, /* Drop Precedence Remarking Mode */ -+// XRX200_PCE_PCTRL_0_CMOD, /* Three-color Marker Color Mode */ -+// XRX200_PCE_PCTRL_0_VREP, /* VLAN Replacement Mode */ -+ XRX200_PCE_PCTRL_0_TVM, /* Transparent VLAN Mode */ -+// XRX200_PCE_PCTRL_0_PLOCK, /* Port Locking Enable */ -+// XRX200_PCE_PCTRL_0_AGEDIS, /* Aging Disable */ -+// XRX200_PCE_PCTRL_0_PSTATE, /* Port State */ -+// XRX200_PCE_PCTRL_1, /* PCE Port ControlRegister 1 */ -+// XRX200_PCE_PCTRL_1_LRNLIM, /* MAC Address Learning Limit */ -+// XRX200_PCE_PCTRL_2, /* PCE Port ControlRegister 2 */ -+// XRX200_PCE_PCTRL_2_DSCPMOD, /* DSCP Mode Selection */ -+// XRX200_PCE_PCTRL_2_DSCP, /* Enable DSCP to select the Class of Service */ -+// XRX200_PCE_PCTRL_2_PCP, /* Enable VLAN PCP to select the Class of Service */ -+// XRX200_PCE_PCTRL_2_PCLASS, /* Port-based Traffic Class */ -+// XRX200_PCE_PCTRL_3_VIO, /* PCE Port ControlRegister 3 */ -+// XRX200_PCE_PCTRL_3_EDIR, /* Egress Redirection Mode */ -+// XRX200_PCE_PCTRL_3_RXDMIR, /* Receive Mirroring Enable for dropped frames */ -+// XRX200_PCE_PCTRL_3_RXVMIR, /* Receive Mirroring Enable for valid frames */ -+// XRX200_PCE_PCTRL_3_TXMIR, /* Transmit Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_7, /* Violation Type 7 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_6, /* Violation Type 6 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_5, /* Violation Type 5 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_4, /* Violation Type 4 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_3, /* Violation Type 3 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_2, /* Violation Type 2 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_1, /* Violation Type 1 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_0, /* Violation Type 0 Mirroring Enable */ -+// XRX200_WOL_CTRL, /* Wake-on-LAN ControlRegister */ -+// XRX200_WOL_CTRL_PORT, /* WoL Enable */ -+// XRX200_PCE_VCTRL, /* PCE VLAN ControlRegister */ -+ XRX200_PCE_VCTRL_VSR, /* VLAN Security Rule */ -+ XRX200_PCE_VCTRL_VEMR, /* VLAN Egress Member Violation Rule */ -+ XRX200_PCE_VCTRL_VIMR, /* VLAN Ingress Member Violation Rule */ -+ XRX200_PCE_VCTRL_VINR, /* VLAN Ingress Tag Rule */ -+ XRX200_PCE_VCTRL_UVR, /* Unknown VLAN Rule */ -+// XRX200_PCE_DEFPVID, /* PCE Default PortVID Register */ -+ XRX200_PCE_DEFPVID_PVID, /* Default Port VID Index */ -+// XRX200_PCE_PSTAT, /* PCE Port StatusRegister */ -+// XRX200_PCE_PSTAT_LRNCNT, /* Learning Count */ -+// XRX200_PCE_PIER, /* Parser and ClassificationEngine Port Interrupt Enable Register */ -+// XRX200_PCE_PIER_CLDRP, /* Classification Drop Interrupt Enable */ -+// XRX200_PCE_PIER_PTDRP, /* Port Drop Interrupt Enable */ -+// XRX200_PCE_PIER_VLAN, /* VLAN Violation Interrupt Enable */ -+// XRX200_PCE_PIER_WOL, /* Wake-on-LAN Interrupt Enable */ -+// XRX200_PCE_PIER_LOCK, /* Port Limit Alert Interrupt Enable */ -+// XRX200_PCE_PIER_LIM, /* Port Lock Alert Interrupt Enable */ -+// XRX200_PCE_PISR, /* Parser and ClassificationEngine Port Interrupt Status Register */ -+// XRX200_PCE_PISR_CLDRP, /* Classification Drop Interrupt */ -+// XRX200_PCE_PISR_PTDRP, /* Port Drop Interrupt */ -+// XRX200_PCE_PISR_VLAN, /* VLAN Violation Interrupt */ -+// XRX200_PCE_PISR_WOL, /* Wake-on-LAN Interrupt */ -+// XRX200_PCE_PISR_LOCK, /* Port Lock Alert Interrupt */ -+// XRX200_PCE_PISR_LIMIT, /* Port Limitation Alert Interrupt */ -+// XRX200_PCE_TCM_CTRL, /* Three-colorMarker Control Register */ -+// XRX200_PCE_TCM_CTRL_TCMEN, /* Three-color Marker metering instance enable */ -+// XRX200_PCE_TCM_STAT, /* Three-colorMarker Status Register */ -+// XRX200_PCE_TCM_STAT_AL1, /* Three-color Marker Alert 1 Status */ -+// XRX200_PCE_TCM_STAT_AL0, /* Three-color Marker Alert 0 Status */ -+// XRX200_PCE_TCM_CBS, /* Three-color MarkerCommitted Burst Size Register */ -+// XRX200_PCE_TCM_CBS_CBS, /* Committed Burst Size */ -+// XRX200_PCE_TCM_EBS, /* Three-color MarkerExcess Burst Size Register */ -+// XRX200_PCE_TCM_EBS_EBS, /* Excess Burst Size */ -+// XRX200_PCE_TCM_IBS, /* Three-color MarkerInstantaneous Burst Size Register */ -+// XRX200_PCE_TCM_IBS_IBS, /* Instantaneous Burst Size */ -+// XRX200_PCE_TCM_CIR_MANT, /* Three-colorMarker Constant Information Rate Mantissa Register */ -+// XRX200_PCE_TCM_CIR_MANT_MANT, /* Rate Counter Mantissa */ -+// XRX200_PCE_TCM_CIR_EXP, /* Three-colorMarker Constant Information Rate Exponent Register */ -+// XRX200_PCE_TCM_CIR_EXP_EXP, /* Rate Counter Exponent */ -+// XRX200_MAC_TEST, /* MAC Test Register */ -+// XRX200_MAC_TEST_JTP, /* Jitter Test Pattern */ -+// XRX200_MAC_PFAD_CFG, /* MAC Pause FrameSource Address Configuration Register */ -+// XRX200_MAC_PFAD_CFG_SAMOD, /* Source Address Mode */ -+// XRX200_MAC_PFSA_0, /* Pause Frame SourceAddress Part 0 */ -+// XRX200_MAC_PFSA_0_PFAD, /* Pause Frame Source Address Part 0 */ -+// XRX200_MAC_PFSA_1, /* Pause Frame SourceAddress Part 1 */ -+// XRX200_MAC_PFSA_1_PFAD, /* Pause Frame Source Address Part 1 */ -+// XRX200_MAC_PFSA_2, /* Pause Frame SourceAddress Part 2 */ -+// XRX200_MAC_PFSA_2_PFAD, /* Pause Frame Source Address Part 2 */ -+// XRX200_MAC_FLEN, /* MAC Frame Length Register */ -+// XRX200_MAC_FLEN_LEN, /* Maximum Frame Length */ -+// XRX200_MAC_VLAN_ETYPE_0, /* MAC VLAN EthertypeRegister 0 */ -+// XRX200_MAC_VLAN_ETYPE_0_OUTER, /* Ethertype */ -+// XRX200_MAC_VLAN_ETYPE_1, /* MAC VLAN EthertypeRegister 1 */ -+// XRX200_MAC_VLAN_ETYPE_1_INNER, /* Ethertype */ -+// XRX200_MAC_IER, /* MAC Interrupt EnableRegister */ -+// XRX200_MAC_IER_MACIEN, /* MAC Interrupt Enable */ -+// XRX200_MAC_ISR, /* MAC Interrupt StatusRegister */ -+// XRX200_MAC_ISR_MACINT, /* MAC Interrupt */ -+// XRX200_MAC_PSTAT, /* MAC Port Status Register */ -+// XRX200_MAC_PSTAT_PACT, /* PHY Active Status */ -+ XRX200_MAC_PSTAT_GBIT, /* Gigabit Speed Status */ -+ XRX200_MAC_PSTAT_MBIT, /* Megabit Speed Status */ -+ XRX200_MAC_PSTAT_FDUP, /* Full Duplex Status */ -+// XRX200_MAC_PSTAT_RXPAU, /* Receive Pause Status */ -+// XRX200_MAC_PSTAT_TXPAU, /* Transmit Pause Status */ -+// XRX200_MAC_PSTAT_RXPAUEN, /* Receive Pause Enable Status */ -+// XRX200_MAC_PSTAT_TXPAUEN, /* Transmit Pause Enable Status */ -+ XRX200_MAC_PSTAT_LSTAT, /* Link Status */ -+// XRX200_MAC_PSTAT_CRS, /* Carrier Sense Status */ -+// XRX200_MAC_PSTAT_TXLPI, /* Transmit Low-power Idle Status */ -+// XRX200_MAC_PSTAT_RXLPI, /* Receive Low-power Idle Status */ -+// XRX200_MAC_PISR, /* MAC Interrupt Status Register */ -+// XRX200_MAC_PISR_PACT, /* PHY Active Status */ -+// XRX200_MAC_PISR_SPEED, /* Megabit Speed Status */ -+// XRX200_MAC_PISR_FDUP, /* Full Duplex Status */ -+// XRX200_MAC_PISR_RXPAUEN, /* Receive Pause Enable Status */ -+// XRX200_MAC_PISR_TXPAUEN, /* Transmit Pause Enable Status */ -+// XRX200_MAC_PISR_LPIOFF, /* Receive Low-power Idle Mode is left */ -+// XRX200_MAC_PISR_LPION, /* Receive Low-power Idle Mode is entered */ -+// XRX200_MAC_PISR_JAM, /* Jam Status Detected */ -+// XRX200_MAC_PISR_TOOSHORT, /* Too Short Frame Error Detected */ -+// XRX200_MAC_PISR_TOOLONG, /* Too Long Frame Error Detected */ -+// XRX200_MAC_PISR_LENERR, /* Length Mismatch Error Detected */ -+// XRX200_MAC_PISR_FCSERR, /* Frame Checksum Error Detected */ -+// XRX200_MAC_PISR_TXPAUSE, /* Pause Frame Transmitted */ -+// XRX200_MAC_PISR_RXPAUSE, /* Pause Frame Received */ -+// XRX200_MAC_PIER, /* MAC Interrupt Enable Register */ -+// XRX200_MAC_PIER_PACT, /* PHY Active Status */ -+// XRX200_MAC_PIER_SPEED, /* Megabit Speed Status */ -+// XRX200_MAC_PIER_FDUP, /* Full Duplex Status */ -+// XRX200_MAC_PIER_RXPAUEN, /* Receive Pause Enable Status */ -+// XRX200_MAC_PIER_TXPAUEN, /* Transmit Pause Enable Status */ -+// XRX200_MAC_PIER_LPIOFF, /* Low-power Idle Off Interrupt Mask */ -+// XRX200_MAC_PIER_LPION, /* Low-power Idle On Interrupt Mask */ -+// XRX200_MAC_PIER_JAM, /* Jam Status Interrupt Mask */ -+// XRX200_MAC_PIER_TOOSHORT, /* Too Short Frame Error Interrupt Mask */ -+// XRX200_MAC_PIER_TOOLONG, /* Too Long Frame Error Interrupt Mask */ -+// XRX200_MAC_PIER_LENERR, /* Length Mismatch Error Interrupt Mask */ -+// XRX200_MAC_PIER_FCSERR, /* Frame Checksum Error Interrupt Mask */ -+// XRX200_MAC_PIER_TXPAUSE, /* Transmit Pause Frame Interrupt Mask */ -+// XRX200_MAC_PIER_RXPAUSE, /* Receive Pause Frame Interrupt Mask */ -+// XRX200_MAC_CTRL_0, /* MAC Control Register0 */ -+// XRX200_MAC_CTRL_0_LCOL, /* Late Collision Control */ -+// XRX200_MAC_CTRL_0_BM, /* Burst Mode Control */ -+// XRX200_MAC_CTRL_0_APADEN, /* Automatic VLAN Padding Enable */ -+// XRX200_MAC_CTRL_0_VPAD2EN, /* Stacked VLAN Padding Enable */ -+// XRX200_MAC_CTRL_0_VPADEN, /* VLAN Padding Enable */ -+// XRX200_MAC_CTRL_0_PADEN, /* Padding Enable */ -+// XRX200_MAC_CTRL_0_FCS, /* Transmit FCS Control */ -+ XRX200_MAC_CTRL_0_FCON, /* Flow Control Mode */ -+// XRX200_MAC_CTRL_0_FDUP, /* Full Duplex Control */ -+// XRX200_MAC_CTRL_0_GMII, /* GMII/MII interface mode selection */ -+// XRX200_MAC_CTRL_1, /* MAC Control Register1 */ -+// XRX200_MAC_CTRL_1_SHORTPRE, /* Short Preamble Control */ -+// XRX200_MAC_CTRL_1_IPG, /* Minimum Inter Packet Gap Size */ -+// XRX200_MAC_CTRL_2, /* MAC Control Register2 */ -+// XRX200_MAC_CTRL_2_MLEN, /* Maximum Untagged Frame Length */ -+// XRX200_MAC_CTRL_2_LCHKL, /* Frame Length Check Long Enable */ -+// XRX200_MAC_CTRL_2_LCHKS, /* Frame Length Check Short Enable */ -+// XRX200_MAC_CTRL_3, /* MAC Control Register3 */ -+// XRX200_MAC_CTRL_3_RCNT, /* Retry Count */ -+// XRX200_MAC_CTRL_4, /* MAC Control Register4 */ -+// XRX200_MAC_CTRL_4_LPIEN, /* LPI Mode Enable */ -+// XRX200_MAC_CTRL_4_WAIT, /* LPI Wait Time */ -+// XRX200_MAC_CTRL_5_PJPS, /* MAC Control Register5 */ -+// XRX200_MAC_CTRL_5_PJPS_NOBP, /* Prolonged Jam pattern size during no-backpressure state */ -+// XRX200_MAC_CTRL_5_PJPS_BP, /* Prolonged Jam pattern size during backpressure state */ -+// XRX200_MAC_CTRL_6_XBUF, /* Transmit and ReceiveBuffer Control Register */ -+// XRX200_MAC_CTRL_6_RBUF_DLY_WP, /* Delay */ -+// XRX200_MAC_CTRL_6_RBUF_INIT, /* Receive Buffer Initialization */ -+// XRX200_MAC_CTRL_6_RBUF_BYPASS, /* Bypass the Receive Buffer */ -+// XRX200_MAC_CTRL_6_XBUF_DLY_WP, /* Delay */ -+// XRX200_MAC_CTRL_6_XBUF_INIT, /* Initialize the Transmit Buffer */ -+// XRX200_MAC_CTRL_6_XBUF_BYPASS, /* Bypass the Transmit Buffer */ -+// XRX200_MAC_BUFST_XBUF, /* MAC Receive and TransmitBuffer Status Register */ -+// XRX200_MAC_BUFST_RBUF_UFL, /* Receive Buffer Underflow Indicator */ -+// XRX200_MAC_BUFST_RBUF_OFL, /* Receive Buffer Overflow Indicator */ -+// XRX200_MAC_BUFST_XBUF_UFL, /* Transmit Buffer Underflow Indicator */ -+// XRX200_MAC_BUFST_XBUF_OFL, /* Transmit Buffer Overflow Indicator */ -+// XRX200_MAC_TESTEN, /* MAC Test Enable Register */ -+// XRX200_MAC_TESTEN_JTEN, /* Jitter Test Enable */ -+// XRX200_MAC_TESTEN_TXER, /* Transmit Error Insertion */ -+// XRX200_MAC_TESTEN_LOOP, /* MAC Loopback Enable */ -+// XRX200_FDMA_CTRL, /* Ethernet Switch FetchDMA Control Register */ -+// XRX200_FDMA_CTRL_LPI_THRESHOLD, /* Low Power Idle Threshold */ -+// XRX200_FDMA_CTRL_LPI_MODE, /* Low Power Idle Mode */ -+// XRX200_FDMA_CTRL_EGSTAG, /* Egress Special Tag Size */ -+// XRX200_FDMA_CTRL_IGSTAG, /* Ingress Special Tag Size */ -+// XRX200_FDMA_CTRL_EXCOL, /* Excessive Collision Handling */ -+// XRX200_FDMA_STETYPE, /* Special Tag EthertypeControl Register */ -+// XRX200_FDMA_STETYPE_ETYPE, /* Special Tag Ethertype */ -+// XRX200_FDMA_VTETYPE, /* VLAN Tag EthertypeControl Register */ -+// XRX200_FDMA_VTETYPE_ETYPE, /* VLAN Tag Ethertype */ -+// XRX200_FDMA_STAT_0, /* FDMA Status Register0 */ -+// XRX200_FDMA_STAT_0_FSMS, /* FSM states status */ -+// XRX200_FDMA_IER, /* Fetch DMA Global InterruptEnable Register */ -+// XRX200_FDMA_IER_PCKD, /* Packet Drop Interrupt Enable */ -+// XRX200_FDMA_IER_PCKR, /* Packet Ready Interrupt Enable */ -+// XRX200_FDMA_IER_PCKT, /* Packet Sent Interrupt Enable */ -+// XRX200_FDMA_ISR, /* Fetch DMA Global InterruptStatus Register */ -+// XRX200_FDMA_ISR_PCKTD, /* Packet Drop */ -+// XRX200_FDMA_ISR_PCKR, /* Packet is Ready for Transmission */ -+// XRX200_FDMA_ISR_PCKT, /* Packet Sent Event */ -+// XRX200_FDMA_PCTRL, /* Ethernet SwitchFetch DMA Port Control Register */ -+// XRX200_FDMA_PCTRL_VLANMOD, /* VLAN Modification Enable */ -+// XRX200_FDMA_PCTRL_DSCPRM, /* DSCP Re-marking Enable */ -+// XRX200_FDMA_PCTRL_STEN, /* Special Tag Insertion Enable */ -+// XRX200_FDMA_PCTRL_EN, /* FDMA Port Enable */ -+// XRX200_FDMA_PRIO, /* Ethernet SwitchFetch DMA Port Priority Register */ -+// XRX200_FDMA_PRIO_PRIO, /* FDMA PRIO */ -+// XRX200_FDMA_PSTAT0, /* Ethernet SwitchFetch DMA Port Status Register 0 */ -+// XRX200_FDMA_PSTAT0_PKT_AVAIL, /* Port Egress Packet Available */ -+// XRX200_FDMA_PSTAT0_POK, /* Port Status OK */ -+// XRX200_FDMA_PSTAT0_PSEG, /* Port Egress Segment Count */ -+// XRX200_FDMA_PSTAT1_HDR, /* Ethernet SwitchFetch DMA Port Status Register 1 */ -+// XRX200_FDMA_PSTAT1_HDR_PTR, /* Header Pointer */ -+// XRX200_FDMA_TSTAMP0, /* Egress TimeStamp Register 0 */ -+// XRX200_FDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */ -+// XRX200_FDMA_TSTAMP1, /* Egress TimeStamp Register 1 */ -+// XRX200_FDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */ -+// XRX200_SDMA_CTRL, /* Ethernet Switch StoreDMA Control Register */ -+// XRX200_SDMA_CTRL_TSTEN, /* Time Stamp Enable */ -+// XRX200_SDMA_FCTHR1, /* SDMA Flow Control Threshold1 Register */ -+// XRX200_SDMA_FCTHR1_THR1, /* Threshold 1 */ -+// XRX200_SDMA_FCTHR2, /* SDMA Flow Control Threshold2 Register */ -+// XRX200_SDMA_FCTHR2_THR2, /* Threshold 2 */ -+// XRX200_SDMA_FCTHR3, /* SDMA Flow Control Threshold3 Register */ -+// XRX200_SDMA_FCTHR3_THR3, /* Threshold 3 */ -+// XRX200_SDMA_FCTHR4, /* SDMA Flow Control Threshold4 Register */ -+// XRX200_SDMA_FCTHR4_THR4, /* Threshold 4 */ -+// XRX200_SDMA_FCTHR5, /* SDMA Flow Control Threshold5 Register */ -+// XRX200_SDMA_FCTHR5_THR5, /* Threshold 5 */ -+// XRX200_SDMA_FCTHR6, /* SDMA Flow Control Threshold6 Register */ -+// XRX200_SDMA_FCTHR6_THR6, /* Threshold 6 */ -+// XRX200_SDMA_FCTHR7, /* SDMA Flow Control Threshold7 Register */ -+// XRX200_SDMA_FCTHR7_THR7, /* Threshold 7 */ -+// XRX200_SDMA_STAT_0, /* SDMA Status Register0 */ -+// XRX200_SDMA_STAT_0_BPS_FILL, /* Back Pressure Status */ -+// XRX200_SDMA_STAT_0_BPS_PNT, /* Back Pressure Status */ -+// XRX200_SDMA_STAT_0_DROP, /* Back Pressure Status */ -+// XRX200_SDMA_STAT_1, /* SDMA Status Register1 */ -+// XRX200_SDMA_STAT_1_FILL, /* Buffer Filling Level */ -+// XRX200_SDMA_STAT_2, /* SDMA Status Register2 */ -+// XRX200_SDMA_STAT_2_FSMS, /* FSM states status */ -+// XRX200_SDMA_IER, /* SDMA Interrupt Enable Register */ -+// XRX200_SDMA_IER_BPEX, /* Buffer Pointers Exceeded */ -+// XRX200_SDMA_IER_BFULL, /* Buffer Full */ -+// XRX200_SDMA_IER_FERR, /* Frame Error */ -+// XRX200_SDMA_IER_FRX, /* Frame Received Successfully */ -+// XRX200_SDMA_ISR, /* SDMA Interrupt Status Register */ -+// XRX200_SDMA_ISR_BPEX, /* Packet Descriptors Exceeded */ -+// XRX200_SDMA_ISR_BFULL, /* Buffer Full */ -+// XRX200_SDMA_ISR_FERR, /* Frame Error */ -+// XRX200_SDMA_ISR_FRX, /* Frame Received Successfully */ -+// XRX200_SDMA_PCTRL, /* Ethernet SwitchStore DMA Port Control Register */ -+// XRX200_SDMA_PCTRL_DTHR, /* Drop Threshold Selection */ -+// XRX200_SDMA_PCTRL_PTHR, /* Pause Threshold Selection */ -+// XRX200_SDMA_PCTRL_PHYEFWD, /* Forward PHY Error Frames */ -+// XRX200_SDMA_PCTRL_ALGFWD, /* Forward Alignment Error Frames */ -+// XRX200_SDMA_PCTRL_LENFWD, /* Forward Length Errored Frames */ -+// XRX200_SDMA_PCTRL_OSFWD, /* Forward Oversized Frames */ -+// XRX200_SDMA_PCTRL_USFWD, /* Forward Undersized Frames */ -+// XRX200_SDMA_PCTRL_FCSIGN, /* Ignore FCS Errors */ -+// XRX200_SDMA_PCTRL_FCSFWD, /* Forward FCS Errored Frames */ -+// XRX200_SDMA_PCTRL_PAUFWD, /* Pause Frame Forwarding */ -+// XRX200_SDMA_PCTRL_MFCEN, /* Metering Flow Control Enable */ -+// XRX200_SDMA_PCTRL_FCEN, /* Flow Control Enable */ -+// XRX200_SDMA_PCTRL_PEN, /* Port Enable */ -+// XRX200_SDMA_PRIO, /* Ethernet SwitchStore DMA Port Priority Register */ -+// XRX200_SDMA_PRIO_PRIO, /* SDMA PRIO */ -+// XRX200_SDMA_PSTAT0_HDR, /* Ethernet SwitchStore DMA Port Status Register 0 */ -+// XRX200_SDMA_PSTAT0_HDR_PTR, /* Port Ingress Queue Header Pointer */ -+// XRX200_SDMA_PSTAT1, /* Ethernet SwitchStore DMA Port Status Register 1 */ -+// XRX200_SDMA_PSTAT1_PPKT, /* Port Ingress Packet Count */ -+// XRX200_SDMA_TSTAMP0, /* Ingress TimeStamp Register 0 */ -+// XRX200_SDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */ -+// XRX200_SDMA_TSTAMP1, /* Ingress TimeStamp Register 1 */ -+// XRX200_SDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */ -+}; -+ -+ -+struct xrx200sw_reg { -+ int offset; -+ int shift; -+ int size; -+ int mult; -+} xrx200sw_reg[] = { -+// offeset shift size mult -+// {0x0000, 0, 16, 0x00}, /* XRX200_ETHSW_SWRES Ethernet Switch ResetControl Register */ -+// {0x0000, 1, 1, 0x00}, /* XRX200_ETHSW_SWRES_R1 Hardware Reset */ -+// {0x0000, 0, 1, 0x00}, /* XRX200_ETHSW_SWRES_R0 Register Configuration */ -+// {0x0004, 0, 16, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT Ethernet Switch Clock ControlRegister */ -+// {0x0004, 12, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_SLEEP Exponent to put system into sleep */ -+// {0x0004, 8, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_WAKE Exponent to wake up system */ -+// {0x0004, 7, 1, 0x00}, /* XRX200_ETHSW_CLK_CLK2_EN CLK2 Input for MAC */ -+// {0x0004, 6, 1, 0x00}, /* XRX200_ETHSW_CLK_EXT_DIV_EN External Clock Divider Enable */ -+// {0x0004, 5, 1, 0x00}, /* XRX200_ETHSW_CLK_RAM_DBG_EN Clock Gating Enable */ -+// {0x0004, 4, 1, 0x00}, /* XRX200_ETHSW_CLK_REG_GAT_EN Clock Gating Enable */ -+// {0x0004, 3, 1, 0x00}, /* XRX200_ETHSW_CLK_GAT_EN Clock Gating Enable */ -+// {0x0004, 2, 1, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT_EN Clock Gating Enable */ -+// {0x0008, 0, 16, 0x00}, /* XRX200_ETHSW_DBG_STEP Ethernet Switch Debug ControlRegister */ -+// {0x0008, 12, 4, 0x00}, /* XRX200_ETHSW_DBG_CLK_SEL Trigger Enable */ -+// {0x0008, 11, 1, 0x00}, /* XRX200_ETHSW_DBG_MON_EN Monitoring Enable */ -+// {0x0008, 9, 2, 0x00}, /* XRX200_ETHSW_DBG_TRIG_EN Trigger Enable */ -+// {0x0008, 8, 1, 0x00}, /* XRX200_ETHSW_DBG_MODE Debug Mode */ -+// {0x0008, 0, 8, 0x00}, /* XRX200_ETHSW_DBG_STEP_TIME Clock Step Size */ -+// {0x000C, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_MODE Ethernet Switch SharedSegment Buffer Mode Register */ -+// {0x000C, 2, 4, 0x00}, /* XRX200_ETHSW_SSB_MODE_ADDE Memory Address */ -+// {0x000C, 0, 2, 0x00}, /* XRX200_ETHSW_SSB_MODE_MODE Memory Access Mode */ -+// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR Ethernet Switch SharedSegment Buffer Address Register */ -+// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR_ADDE Memory Address */ -+// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA Ethernet Switch SharedSegment Buffer Data Register */ -+// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA_DATA Data Value */ -+// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0 Ethernet Switch CapabilityRegister 0 */ -+// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0_SPEED Clock frequency */ -+// {0x001C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_1 Ethernet Switch CapabilityRegister 1 */ -+// {0x001C, 15, 1, 0x00}, /* XRX200_ETHSW_CAP_1_GMAC MAC operation mode */ -+// {0x001C, 8, 7, 0x00}, /* XRX200_ETHSW_CAP_1_QUEUE Number of queues */ -+// {0x001C, 4, 4, 0x00}, /* XRX200_ETHSW_CAP_1_VPORTS Number of virtual ports */ -+// {0x001C, 0, 4, 0x00}, /* XRX200_ETHSW_CAP_1_PPORTS Number of physical ports */ -+// {0x0020, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_2 Ethernet Switch CapabilityRegister 2 */ -+// {0x0020, 0, 11, 0x00}, /* XRX200_ETHSW_CAP_2_PACKETS Number of packets */ -+// {0x0024, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_3 Ethernet Switch CapabilityRegister 3 */ -+// {0x0024, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_3_METERS Number of traffic meters */ -+// {0x0024, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_3_SHAPERS Number of traffic shapers */ -+// {0x0028, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_4 Ethernet Switch CapabilityRegister 4 */ -+// {0x0028, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_4_PPPOE PPPoE table size */ -+// {0x0028, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_4_VLAN Active VLAN table size */ -+// {0x002C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_5 Ethernet Switch CapabilityRegister 5 */ -+// {0x002C, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_5_IPPLEN IP packet length table size */ -+// {0x002C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_5_PROT Protocol table size */ -+// {0x0030, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_6 Ethernet Switch CapabilityRegister 6 */ -+// {0x0030, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_6_MACDASA MAC DA/SA table size */ -+// {0x0030, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_6_APPL Application table size */ -+// {0x0034, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_7 Ethernet Switch CapabilityRegister 7 */ -+// {0x0034, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAM IP DA/SA MSB table size */ -+// {0x0034, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAL IP DA/SA LSB table size */ -+// {0x0038, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_8 Ethernet Switch CapabilityRegister 8 */ -+// {0x0038, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_8_MCAST Multicast table size */ -+// {0x003C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_9 Ethernet Switch CapabilityRegister 9 */ -+// {0x003C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_9_FLAGG Flow Aggregation table size */ -+// {0x0040, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_10 Ethernet Switch CapabilityRegister 10 */ -+// {0x0040, 0, 13, 0x00}, /* XRX200_ETHSW_CAP_10_MACBT MAC bridging table size */ -+// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11 Ethernet Switch CapabilityRegister 11 */ -+// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11_BSIZEL Packet buffer size (lower part, in byte) */ -+// {0x0048, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_12 Ethernet Switch CapabilityRegister 12 */ -+// {0x0048, 0, 3, 0x00}, /* XRX200_ETHSW_CAP_12_BSIZEH Packet buffer size (higher part, in byte) */ -+// {0x004C, 0, 16, 0x00}, /* XRX200_ETHSW_VERSION_REV Ethernet Switch VersionRegister */ -+// {0x004C, 8, 8, 0x00}, /* XRX200_ETHSW_VERSION_MOD_ID Module Identification */ -+// {0x004C, 0, 8, 0x00}, /* XRX200_ETHSW_VERSION_REV_ID Hardware Revision Identification */ -+// {0x0050, 0, 16, 0x00}, /* XRX200_ETHSW_IER Interrupt Enable Register */ -+// {0x0050, 4, 1, 0x00}, /* XRX200_ETHSW_IER_FDMAIE Fetch DMA Interrupt Enable */ -+// {0x0050, 3, 1, 0x00}, /* XRX200_ETHSW_IER_SDMAIE Store DMA Interrupt Enable */ -+// {0x0050, 2, 1, 0x00}, /* XRX200_ETHSW_IER_MACIE Ethernet MAC Interrupt Enable */ -+// {0x0050, 1, 1, 0x00}, /* XRX200_ETHSW_IER_PCEIE Parser and Classification Engine Interrupt Enable */ -+// {0x0050, 0, 1, 0x00}, /* XRX200_ETHSW_IER_BMIE Buffer Manager Interrupt Enable */ -+// {0x0054, 0, 16, 0x00}, /* XRX200_ETHSW_ISR Interrupt Status Register */ -+// {0x0054, 4, 1, 0x00}, /* XRX200_ETHSW_ISR_FDMAINT Fetch DMA Interrupt */ -+// {0x0054, 3, 1, 0x00}, /* XRX200_ETHSW_ISR_SDMAINT Store DMA Interrupt */ -+// {0x0054, 2, 1, 0x00}, /* XRX200_ETHSW_ISR_MACINT Ethernet MAC Interrupt */ -+// {0x0054, 1, 1, 0x00}, /* XRX200_ETHSW_ISR_PCEINT Parser and Classification Engine Interrupt */ -+// {0x0054, 0, 1, 0x00}, /* XRX200_ETHSW_ISR_BMINT Buffer Manager Interrupt */ -+// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0 Ethernet Switch SpareCells 0 */ -+// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0_SPARE SPARE0 */ -+// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1 Ethernet Switch SpareCells 1 */ -+// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1_SPARE SPARE1 */ -+// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2 Ethernet Switch SpareCells 2 */ -+// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2_SPARE SPARE2 */ -+// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3 Ethernet Switch SpareCells 3 */ -+// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3_SPARE SPARE3 */ -+// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4 Ethernet Switch SpareCells 4 */ -+// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4_SPARE SPARE4 */ -+// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5 Ethernet Switch SpareCells 5 */ -+// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5_SPARE SPARE5 */ -+// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6 Ethernet Switch SpareCells 6 */ -+// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6_SPARE SPARE6 */ -+// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7 Ethernet Switch SpareCells 7 */ -+// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7_SPARE SPARE7 */ -+// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8 Ethernet Switch SpareCells 8 */ -+// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8_SPARE SPARE8 */ -+// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9 Ethernet Switch SpareCells 9 */ -+// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9_SPARE SPARE9 */ -+// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10 Ethernet Switch SpareCells 10 */ -+// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10_SPARE SPARE10 */ -+// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11 Ethernet Switch SpareCells 11 */ -+// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11_SPARE SPARE11 */ -+// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12 Ethernet Switch SpareCells 12 */ -+// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12_SPARE SPARE12 */ -+// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13 Ethernet Switch SpareCells 13 */ -+// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13_SPARE SPARE13 */ -+// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14 Ethernet Switch SpareCells 14 */ -+// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14_SPARE SPARE14 */ -+// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15 Ethernet Switch SpareCells 15 */ -+// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15_SPARE SPARE15 */ -+// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3 RAM Value Register 3 */ -+// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3_VAL3 Data value [15:0] */ -+// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2 RAM Value Register 2 */ -+// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2_VAL2 Data value [15:0] */ -+// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1 RAM Value Register 1 */ -+// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1_VAL1 Data value [15:0] */ -+// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0 RAM Value Register 0 */ -+// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0_VAL0 Data value [15:0] */ -+// {0x0110, 0, 16, 0x00}, /* XRX200_BM_RAM_ADDR RAM Address Register */ -+// {0x0110, 0, 11, 0x00}, /* XRX200_BM_RAM_ADDR_ADDR RAM Address */ -+// {0x0114, 0, 16, 0x00}, /* XRX200_BM_RAM_CTRL RAM Access Control Register */ -+// {0x0114, 15, 1, 0x00}, /* XRX200_BM_RAM_CTRL_BAS Access Busy/Access Start */ -+// {0x0114, 5, 1, 0x00}, /* XRX200_BM_RAM_CTRL_OPMOD Lookup Table Access Operation Mode */ -+// {0x0114, 0, 5, 0x00}, /* XRX200_BM_RAM_CTRL_ADDR Address for RAM selection */ -+// {0x0118, 0, 16, 0x00}, /* XRX200_BM_FSQM_GCTRL Free Segment Queue ManagerGlobal Control Register */ -+// {0x0118, 0, 10, 0x00}, /* XRX200_BM_FSQM_GCTRL_SEGNUM Maximum Segment Number */ -+// {0x011C, 0, 16, 0x00}, /* XRX200_BM_CONS_SEG Number of Consumed SegmentsRegister */ -+// {0x011C, 0, 10, 0x00}, /* XRX200_BM_CONS_SEG_FSEG Number of Consumed Segments */ -+// {0x0120, 0, 16, 0x00}, /* XRX200_BM_CONS_PKT Number of Consumed PacketPointers Register */ -+// {0x0120, 0, 11, 0x00}, /* XRX200_BM_CONS_PKT_FQP Number of Consumed Packet Pointers */ -+// {0x0124, 0, 16, 0x00}, /* XRX200_BM_GCTRL_F Buffer Manager Global ControlRegister 0 */ -+// {0x0124, 13, 1, 0x00}, /* XRX200_BM_GCTRL_BM_STA Buffer Manager Initialization Status Bit */ -+// {0x0124, 12, 1, 0x00}, /* XRX200_BM_GCTRL_SAT RMON Counter Update Mode */ -+// {0x0124, 11, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RBC Freeze RMON RX Bad Byte 64 Bit Counter */ -+// {0x0124, 10, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RGC Freeze RMON RX Good Byte 64 Bit Counter */ -+// {0x0124, 9, 1, 0x00}, /* XRX200_BM_GCTRL_FR_TGC Freeze RMON TX Good Byte 64 Bit Counter */ -+// {0x0124, 8, 1, 0x00}, /* XRX200_BM_GCTRL_I_FIN RAM initialization finished */ -+// {0x0124, 7, 1, 0x00}, /* XRX200_BM_GCTRL_CX_INI PQM Context RAM initialization */ -+// {0x0124, 6, 1, 0x00}, /* XRX200_BM_GCTRL_FP_INI FPQM RAM initialization */ -+// {0x0124, 5, 1, 0x00}, /* XRX200_BM_GCTRL_FS_INI FSQM RAM initialization */ -+// {0x0124, 4, 1, 0x00}, /* XRX200_BM_GCTRL_R_SRES Software Reset for RMON */ -+// {0x0124, 3, 1, 0x00}, /* XRX200_BM_GCTRL_S_SRES Software Reset for Scheduler */ -+// {0x0124, 2, 1, 0x00}, /* XRX200_BM_GCTRL_A_SRES Software Reset for AVG */ -+// {0x0124, 1, 1, 0x00}, /* XRX200_BM_GCTRL_P_SRES Software Reset for PQM */ -+// {0x0124, 0, 1, 0x00}, /* XRX200_BM_GCTRL_F_SRES Software Reset for FSQM */ -+// {0x0128, 0, 16, 0x00}, /* XRX200_BM_QUEUE_GCTRL Queue Manager GlobalControl Register 0 */ -+ {0x0128, 10, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_GL_MOD WRED Mode Signal */ -+// {0x0128, 7, 3, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQUI Average Queue Update Interval */ -+// {0x0128, 3, 4, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQWF Average Queue Weight Factor */ -+// {0x0128, 2, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_QAVGEN Queue Average Calculation Enable */ -+// {0x0128, 0, 2, 0x00}, /* XRX200_BM_QUEUE_GCTRL_DPROB Drop Probability Profile */ -+// {0x012C, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_0 WRED Red Threshold Register0 */ -+// {0x012C, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_0_MINTH Minimum Threshold */ -+// {0x0130, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_1 WRED Red Threshold Register1 */ -+// {0x0130, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_1_MAXTH Maximum Threshold */ -+// {0x0134, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_0 WRED Yellow ThresholdRegister 0 */ -+// {0x0134, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_0_MINTH Minimum Threshold */ -+// {0x0138, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_1 WRED Yellow ThresholdRegister 1 */ -+// {0x0138, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_1_MAXTH Maximum Threshold */ -+// {0x013C, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_0 WRED Green ThresholdRegister 0 */ -+// {0x013C, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_0_MINTH Minimum Threshold */ -+// {0x0140, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_1 WRED Green ThresholdRegister 1 */ -+// {0x0140, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_1_MAXTH Maximum Threshold */ -+// {0x0144, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_0_THR Drop Threshold ConfigurationRegister 0 */ -+// {0x0144, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_0_THR_FQ Threshold for frames marked red */ -+// {0x0148, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_1_THY Drop Threshold ConfigurationRegister 1 */ -+// {0x0148, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_1_THY_FQ Threshold for frames marked yellow */ -+// {0x014C, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_2_THG Drop Threshold ConfigurationRegister 2 */ -+// {0x014C, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_2_THG_FQ Threshold for frames marked green */ -+// {0x0150, 0, 16, 0x00}, /* XRX200_BM_IER Buffer Manager Global InterruptEnable Register */ -+// {0x0150, 7, 1, 0x00}, /* XRX200_BM_IER_CNT4 Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */ -+// {0x0150, 6, 1, 0x00}, /* XRX200_BM_IER_CNT3 Counter Group 3 (RMON-PQM) Interrupt Enable */ -+// {0x0150, 5, 1, 0x00}, /* XRX200_BM_IER_CNT2 Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */ -+// {0x0150, 4, 1, 0x00}, /* XRX200_BM_IER_CNT1 Counter Group 1 (RMON-QFETCH) Interrupt Enable */ -+// {0x0150, 3, 1, 0x00}, /* XRX200_BM_IER_CNT0 Counter Group 0 (RMON-QSTOR) Interrupt Enable */ -+// {0x0150, 2, 1, 0x00}, /* XRX200_BM_IER_DEQ PQM dequeue Interrupt Enable */ -+// {0x0150, 1, 1, 0x00}, /* XRX200_BM_IER_ENQ PQM Enqueue Interrupt Enable */ -+// {0x0150, 0, 1, 0x00}, /* XRX200_BM_IER_FSQM Buffer Empty Interrupt Enable */ -+// {0x0154, 0, 16, 0x00}, /* XRX200_BM_ISR Buffer Manager Global InterruptStatus Register */ -+// {0x0154, 7, 1, 0x00}, /* XRX200_BM_ISR_CNT4 Counter Group 4 Interrupt */ -+// {0x0154, 6, 1, 0x00}, /* XRX200_BM_ISR_CNT3 Counter Group 3 Interrupt */ -+// {0x0154, 5, 1, 0x00}, /* XRX200_BM_ISR_CNT2 Counter Group 2 Interrupt */ -+// {0x0154, 4, 1, 0x00}, /* XRX200_BM_ISR_CNT1 Counter Group 1 Interrupt */ -+// {0x0154, 3, 1, 0x00}, /* XRX200_BM_ISR_CNT0 Counter Group 0 Interrupt */ -+// {0x0154, 2, 1, 0x00}, /* XRX200_BM_ISR_DEQ PQM dequeue Interrupt Enable */ -+// {0x0154, 1, 1, 0x00}, /* XRX200_BM_ISR_ENQ PQM Enqueue Interrupt */ -+// {0x0154, 0, 1, 0x00}, /* XRX200_BM_ISR_FSQM Buffer Empty Interrupt */ -+// {0x0158, 0, 16, 0x00}, /* XRX200_BM_CISEL Buffer Manager RMON CounterInterrupt Select Register */ -+// {0x0158, 0, 3, 0x00}, /* XRX200_BM_CISEL_PORT Port Number */ -+// {0x015C, 0, 16, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG Debug Control Register */ -+// {0x015C, 0, 8, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG_SEL Select Signal for Debug Multiplexer */ -+// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG Debug Value Register */ -+// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG_DAT Debug Data Value */ -+// {0x0200, 0, 16, 0x08}, /* XRX200_BM_PCFG Buffer Manager PortConfiguration Register */ -+// {0x0200, 0, 1, 0x08}, /* XRX200_BM_PCFG_CNTEN RMON Counter Enable */ -+// {0x0204, 0, 16, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1 Buffer ManagerRMON Control Register */ -+// {0x0204, 1, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM2_RES Software Reset for RMON RAM2 */ -+// {0x0204, 0, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1_RES Software Reset for RMON RAM1 */ -+// {0x0400, 0, 16, 0x08}, /* XRX200_PQM_DP Packet Queue ManagerDrop Probability Register */ -+// {0x0400, 0, 2, 0x08}, /* XRX200_PQM_DP_DPROB Drop Probability Profile */ -+// {0x0404, 0, 16, 0x08}, /* XRX200_PQM_RS Packet Queue ManagerRate Shaper Assignment Register */ -+// {0x0404, 15, 1, 0x08}, /* XRX200_PQM_RS_EN2 Rate Shaper 2 Enable */ -+// {0x0404, 8, 6, 0x08}, /* XRX200_PQM_RS_RS2 Rate Shaper 2 */ -+// {0x0404, 7, 1, 0x08}, /* XRX200_PQM_RS_EN1 Rate Shaper 1 Enable */ -+// {0x0404, 0, 6, 0x08}, /* XRX200_PQM_RS_RS1 Rate Shaper 1 */ -+// {0x0500, 0, 16, 0x14}, /* XRX200_RS_CTRL Rate Shaper ControlRegister */ -+// {0x0500, 0, 1, 0x14}, /* XRX200_RS_CTRL_RSEN Rate Shaper Enable */ -+// {0x0504, 0, 16, 0x14}, /* XRX200_RS_CBS Rate Shaper CommittedBurst Size Register */ -+// {0x0504, 0, 10, 0x14}, /* XRX200_RS_CBS_CBS Committed Burst Size */ -+// {0x0508, 0, 16, 0x14}, /* XRX200_RS_IBS Rate Shaper InstantaneousBurst Size Register */ -+// {0x0508, 0, 2, 0x14}, /* XRX200_RS_IBS_IBS Instantaneous Burst Size */ -+// {0x050C, 0, 16, 0x14}, /* XRX200_RS_CIR_EXP Rate Shaper RateExponent Register */ -+// {0x050C, 0, 4, 0x14}, /* XRX200_RS_CIR_EXP_EXP Exponent */ -+// {0x0510, 0, 16, 0x14}, /* XRX200_RS_CIR_MANT Rate Shaper RateMantissa Register */ -+// {0x0510, 0, 10, 0x14}, /* XRX200_RS_CIR_MANT_MANT Mantissa */ -+ {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7 Table Key Data 7 */ -+// {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7_KEY7 Key Value[15:0] */ -+ {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6 Table Key Data 6 */ -+// {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6_KEY6 Key Value[15:0] */ -+ {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5 Table Key Data 5 */ -+// {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5_KEY5 Key Value[15:0] */ -+ {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4 Table Key Data 4 */ -+// {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4_KEY4 Key Value[15:0] */ -+ {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3 Table Key Data 3 */ -+// {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3_KEY3 Key Value[15:0] */ -+ {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2 Table Key Data 2 */ -+// {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2_KEY2 Key Value[15:0] */ -+ {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1 Table Key Data 1 */ -+// {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1_KEY1 Key Value[31:16] */ -+ {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0 Table Key Data 0 */ -+// {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0_KEY0 Key Value[15:0] */ -+ {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0 Table Mask Write Register0 */ -+// {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0_MASK0 Mask Pattern [15:0] */ -+ {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4 Table Value Register4 */ -+// {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4_VAL4 Data value [15:0] */ -+ {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3 Table Value Register3 */ -+// {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3_VAL3 Data value [15:0] */ -+ {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2 Table Value Register2 */ -+// {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2_VAL2 Data value [15:0] */ -+ {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1 Table Value Register1 */ -+// {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1_VAL1 Data value [15:0] */ -+ {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0 Table Value Register0 */ -+// {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0_VAL0 Data value [15:0] */ -+// {0x1138, 0, 16, 0x00}, /* XRX200_PCE_TBL_ADDR Table Entry AddressRegister */ -+ {0x1138, 0, 11, 0x00}, /* XRX200_PCE_TBL_ADDR_ADDR Table Address */ -+// {0x113C, 0, 16, 0x00}, /* XRX200_PCE_TBL_CTRL Table Access ControlRegister */ -+ {0x113C, 15, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_BAS Access Busy/Access Start */ -+ {0x113C, 13, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_TYPE Lookup Entry Type */ -+ {0x113C, 12, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_VLD Lookup Entry Valid */ -+ {0x113C, 7, 4, 0x00}, /* XRX200_PCE_TBL_CTRL_GMAP Group Map */ -+ {0x113C, 5, 2, 0x00}, /* XRX200_PCE_TBL_CTRL_OPMOD Lookup Table Access Operation Mode */ -+ {0x113C, 0, 5, 0x00}, /* XRX200_PCE_TBL_CTRL_ADDR Lookup Table Address */ -+// {0x1140, 0, 16, 0x00}, /* XRX200_PCE_TBL_STAT Table General StatusRegister */ -+// {0x1140, 2, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TBUSY Table Access Busy */ -+// {0x1140, 1, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TEMPT Table Empty */ -+// {0x1140, 0, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TFUL Table Full */ -+// {0x1144, 0, 16, 0x00}, /* XRX200_PCE_AGE_0 Aging Counter ConfigurationRegister 0 */ -+// {0x1144, 0, 4, 0x00}, /* XRX200_PCE_AGE_0_EXP Aging Counter Exponent Value */ -+// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1 Aging Counter ConfigurationRegister 1 */ -+// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1_MANT Aging Counter Mantissa Value */ -+// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1 Port Map Register 1 */ -+// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1_MPMAP Monitoring Port Map */ -+// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2 Port Map Register 2 */ -+// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2_DMCPMAP Default Multicast Port Map */ -+// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3 Port Map Register 3 */ -+// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3_UUCMAP Default Unknown Unicast Port Map */ -+// {0x1158, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_0 PCE Global Control Register0 */ -+// {0x1158, 15, 1, 0x00}, /* XRX200_PCE_GCTRL_0_IGMP IGMP Mode Selection */ -+ {0x1158, 14, 1, 0x00}, /* XRX200_PCE_GCTRL_0_VLAN VLAN-aware Switching */ -+// {0x1158, 13, 1, 0x00}, /* XRX200_PCE_GCTRL_0_NOPM No Port Map Forwarding */ -+// {0x1158, 12, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONUC Unknown Unicast Storm Control */ -+// {0x1158, 11, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMC Multicast Storm Control */ -+// {0x1158, 10, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONBC Broadcast Storm Control */ -+// {0x1158, 8, 2, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMOD Storm Control Mode */ -+// {0x1158, 4, 4, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMET Storm Control Metering Instance */ -+// {0x1158, 3, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MC_VALID Access Request */ -+// {0x1158, 2, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLCKMOD Port Lock Mode */ -+// {0x1158, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLIMMOD MAC Address Learning Limitation Mode */ -+// {0x1158, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MTFL MAC Table Flushing */ -+// {0x115C, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_1 PCE Global Control Register1 */ -+// {0x115C, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_1_PCE_DIS PCE Disable after currently processed packet */ -+// {0x115C, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_1_LRNMOD MAC Address Learning Mode */ -+// {0x1160, 0, 16, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL Three-color MarkerGlobal Control Register */ -+// {0x1160, 6, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPRED Re-marking Drop Precedence Red Encoding */ -+// {0x1160, 3, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPYEL Re-marking Drop Precedence Yellow Encoding */ -+// {0x1160, 0, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPGRN Re-marking Drop Precedence Green Encoding */ -+// {0x1164, 0, 16, 0x00}, /* XRX200_PCE_IGMP_CTRL IGMP Control Register */ -+// {0x1164, 15, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FAGEEN Force Aging of Table Entries Enable */ -+// {0x1164, 14, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FLEAVE Fast Leave Enable */ -+// {0x1164, 13, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRTEN Default Maximum Response Time Enable */ -+// {0x1164, 12, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_JASUP Join Aggregation Suppression Enable */ -+// {0x1164, 11, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_REPSUP Report Suppression Enable */ -+// {0x1164, 10, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_SRPEN Snooping of Router Port Enable */ -+// {0x1164, 8, 2, 0x00}, /* XRX200_PCE_IGMP_CTRL_ROB Robustness Variable */ -+// {0x1164, 0, 8, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRT IGMP Default Maximum Response Time */ -+// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM IGMP Default RouterPort Map Register */ -+// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM_DRPM IGMP Default Router Port Map */ -+// {0x116C, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_0 IGMP Aging Register0 */ -+// {0x116C, 3, 8, 0x00}, /* XRX200_PCE_IGMP_AGE_0_MANT IGMP Group Aging Time Mantissa */ -+// {0x116C, 0, 3, 0x00}, /* XRX200_PCE_IGMP_AGE_0_EXP IGMP Group Aging Time Exponent */ -+// {0x1170, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_1 IGMP Aging Register1 */ -+// {0x1170, 0, 12, 0x00}, /* XRX200_PCE_IGMP_AGE_1_MANT IGMP Router Port Aging Time Mantissa */ -+// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT IGMP Status Register */ -+// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT_IGPM IGMP Port Map */ -+// {0x1178, 0, 16, 0x00}, /* XRX200_WOL_GLB_CTRL Wake-on-LAN ControlRegister */ -+// {0x1178, 0, 1, 0x00}, /* XRX200_WOL_GLB_CTRL_PASSEN WoL Password Enable */ -+// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0 Wake-on-LAN DestinationAddress Register 0 */ -+// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0_DA0 WoL Destination Address [15:0] */ -+// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1 Wake-on-LAN DestinationAddress Register 1 */ -+// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1_DA1 WoL Destination Address [31:16] */ -+// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2 Wake-on-LAN DestinationAddress Register 2 */ -+// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2_DA2 WoL Destination Address [47:32] */ -+// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0 Wake-on-LAN Password Register0 */ -+// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0_PW0 WoL Password [15:0] */ -+// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1 Wake-on-LAN Password Register1 */ -+// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1_PW1 WoL Password [31:16] */ -+// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2 Wake-on-LAN Password Register2 */ -+// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2_PW2 WoL Password [47:32] */ -+// {0x1194, 0, 16, 0x00}, /* XRX200_PCE_IER_0_PINT Parser and ClassificationEngine Global Interrupt Enable Register 0 */ -+// {0x1194, 15, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_15 Port Interrupt Enable */ -+// {0x1194, 14, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_14 Port Interrupt Enable */ -+// {0x1194, 13, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_13 Port Interrupt Enable */ -+// {0x1194, 12, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_12 Port Interrupt Enable */ -+// {0x1194, 11, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_11 Port Interrupt Enable */ -+// {0x1194, 10, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_10 Port Interrupt Enable */ -+// {0x1194, 9, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_9 Port Interrupt Enable */ -+// {0x1194, 8, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_8 Port Interrupt Enable */ -+// {0x1194, 7, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_7 Port Interrupt Enable */ -+// {0x1194, 6, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_6 Port Interrupt Enable */ -+// {0x1194, 5, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_5 Port Interrupt Enable */ -+// {0x1194, 4, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_4 Port Interrupt Enable */ -+// {0x1194, 3, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_3 Port Interrupt Enable */ -+// {0x1194, 2, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_2 Port Interrupt Enable */ -+// {0x1194, 1, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_1 Port Interrupt Enable */ -+// {0x1194, 0, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_0 Port Interrupt Enable */ -+// {0x1198, 0, 16, 0x00}, /* XRX200_PCE_IER_1 Parser and ClassificationEngine Global Interrupt Enable Register 1 */ -+// {0x1198, 6, 1, 0x00}, /* XRX200_PCE_IER_1_FLOWINT Traffic Flow Table Interrupt Rule matched Interrupt Enable */ -+// {0x1198, 5, 1, 0x00}, /* XRX200_PCE_IER_1_CPH2 Classification Phase 2 Ready Interrupt Enable */ -+// {0x1198, 4, 1, 0x00}, /* XRX200_PCE_IER_1_CPH1 Classification Phase 1 Ready Interrupt Enable */ -+// {0x1198, 3, 1, 0x00}, /* XRX200_PCE_IER_1_CPH0 Classification Phase 0 Ready Interrupt Enable */ -+// {0x1198, 2, 1, 0x00}, /* XRX200_PCE_IER_1_PRDY Parser Ready Interrupt Enable */ -+// {0x1198, 1, 1, 0x00}, /* XRX200_PCE_IER_1_IGTF IGMP Table Full Interrupt Enable */ -+// {0x1198, 0, 1, 0x00}, /* XRX200_PCE_IER_1_MTF MAC Table Full Interrupt Enable */ -+// {0x119C, 0, 16, 0x00}, /* XRX200_PCE_ISR_0_PINT Parser and ClassificationEngine Global Interrupt Status Register 0 */ -+// {0x119C, 15, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_15 Port Interrupt */ -+// {0x119C, 14, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_14 Port Interrupt */ -+// {0x119C, 13, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_13 Port Interrupt */ -+// {0x119C, 12, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_12 Port Interrupt */ -+// {0x119C, 11, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_11 Port Interrupt */ -+// {0x119C, 10, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_10 Port Interrupt */ -+// {0x119C, 9, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_9 Port Interrupt */ -+// {0x119C, 8, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_8 Port Interrupt */ -+// {0x119C, 7, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_7 Port Interrupt */ -+// {0x119C, 6, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_6 Port Interrupt */ -+// {0x119C, 5, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_5 Port Interrupt */ -+// {0x119C, 4, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_4 Port Interrupt */ -+// {0x119C, 3, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_3 Port Interrupt */ -+// {0x119C, 2, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_2 Port Interrupt */ -+// {0x119C, 1, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_1 Port Interrupt */ -+// {0x119C, 0, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_0 Port Interrupt */ -+// {0x11A0, 0, 16, 0x00}, /* XRX200_PCE_ISR_1 Parser and ClassificationEngine Global Interrupt Status Register 1 */ -+// {0x11A0, 6, 1, 0x00}, /* XRX200_PCE_ISR_1_FLOWINT Traffic Flow Table Interrupt Rule matched */ -+// {0x11A0, 5, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH2 Classification Phase 2 Ready Interrupt */ -+// {0x11A0, 4, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH1 Classification Phase 1 Ready Interrupt */ -+// {0x11A0, 3, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH0 Classification Phase 0 Ready Interrupt */ -+// {0x11A0, 2, 1, 0x00}, /* XRX200_PCE_ISR_1_PRDY Parser Ready Interrupt */ -+// {0x11A0, 1, 1, 0x00}, /* XRX200_PCE_ISR_1_IGTF IGMP Table Full Interrupt */ -+// {0x11A0, 0, 1, 0x00}, /* XRX200_PCE_ISR_1_MTF MAC Table Full Interrupt */ -+// {0x11A4, 0, 16, 0x00}, /* XRX200_PARSER_STAT_FIFO Parser Status Register */ -+// {0x11A4, 8, 8, 0x00}, /* XRX200_PARSER_STAT_FSM_DAT_CNT Parser FSM Data Counter */ -+// {0x11A4, 5, 3, 0x00}, /* XRX200_PARSER_STAT_FSM_STATE Parser FSM State */ -+// {0x11A4, 4, 1, 0x00}, /* XRX200_PARSER_STAT_PKT_ERR Packet error detected */ -+// {0x11A4, 3, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_FIN Parser FSM finished */ -+// {0x11A4, 2, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_START Parser FSM start */ -+// {0x11A4, 1, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_RDY Parser FIFO ready for read. */ -+// {0x11A4, 0, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_FULL Parser */ -+// {0x1200, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_0 PCE Port ControlRegister 0 */ -+// {0x1200, 13, 1, 0x28}, /* XRX200_PCE_PCTRL_0_MCST Multicast Forwarding Mode Selection */ -+// {0x1200, 12, 1, 0x28}, /* XRX200_PCE_PCTRL_0_EGSTEN Table-based Egress Special Tag Enable */ -+// {0x1200, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_0_IGSTEN Ingress Special Tag Enable */ -+// {0x1200, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PCPEN PCP Remarking Mode */ -+// {0x1200, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CLPEN Class Remarking Mode */ -+// {0x1200, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_0_DPEN Drop Precedence Remarking Mode */ -+// {0x1200, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CMOD Three-color Marker Color Mode */ -+// {0x1200, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_0_VREP VLAN Replacement Mode */ -+ {0x1200, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_0_TVM Transparent VLAN Mode */ -+// {0x1200, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PLOCK Port Locking Enable */ -+// {0x1200, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_0_AGEDIS Aging Disable */ -+// {0x1200, 0, 3, 0x28}, /* XRX200_PCE_PCTRL_0_PSTATE Port State */ -+// {0x1204, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_1 PCE Port ControlRegister 1 */ -+// {0x1204, 0, 8, 0x28}, /* XRX200_PCE_PCTRL_1_LRNLIM MAC Address Learning Limit */ -+// {0x1208, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_2 PCE Port ControlRegister 2 */ -+// {0x1208, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_2_DSCPMOD DSCP Mode Selection */ -+// {0x1208, 5, 2, 0x28}, /* XRX200_PCE_PCTRL_2_DSCP Enable DSCP to select the Class of Service */ -+// {0x1208, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_2_PCP Enable VLAN PCP to select the Class of Service */ -+// {0x1208, 0, 4, 0x28}, /* XRX200_PCE_PCTRL_2_PCLASS Port-based Traffic Class */ -+// {0x120C, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_3_VIO PCE Port ControlRegister 3 */ -+// {0x120C, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_3_EDIR Egress Redirection Mode */ -+// {0x120C, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXDMIR Receive Mirroring Enable for dropped frames */ -+// {0x120C, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXVMIR Receive Mirroring Enable for valid frames */ -+// {0x120C, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_3_TXMIR Transmit Mirroring Enable */ -+// {0x120C, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_7 Violation Type 7 Mirroring Enable */ -+// {0x120C, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_6 Violation Type 6 Mirroring Enable */ -+// {0x120C, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_5 Violation Type 5 Mirroring Enable */ -+// {0x120C, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_4 Violation Type 4 Mirroring Enable */ -+// {0x120C, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_3 Violation Type 3 Mirroring Enable */ -+// {0x120C, 2, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_2 Violation Type 2 Mirroring Enable */ -+// {0x120C, 1, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_1 Violation Type 1 Mirroring Enable */ -+// {0x120C, 0, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_0 Violation Type 0 Mirroring Enable */ -+// {0x1210, 0, 16, 0x28}, /* XRX200_WOL_CTRL Wake-on-LAN ControlRegister */ -+// {0x1210, 0, 1, 0x28}, /* XRX200_WOL_CTRL_PORT WoL Enable */ -+// {0x1214, 0, 16, 0x28}, /* XRX200_PCE_VCTRL PCE VLAN ControlRegister */ -+ {0x1214, 5, 1, 0x28}, /* XRX200_PCE_VCTRL_VSR VLAN Security Rule */ -+ {0x1214, 4, 1, 0x28}, /* XRX200_PCE_VCTRL_VEMR VLAN Egress Member Violation Rule */ -+ {0x1214, 3, 1, 0x28}, /* XRX200_PCE_VCTRL_VIMR VLAN Ingress Member Violation Rule */ -+ {0x1214, 1, 2, 0x28}, /* XRX200_PCE_VCTRL_VINR VLAN Ingress Tag Rule */ -+ {0x1214, 0, 1, 0x28}, /* XRX200_PCE_VCTRL_UVR Unknown VLAN Rule */ -+// {0x1218, 0, 16, 0x28}, /* XRX200_PCE_DEFPVID PCE Default PortVID Register */ -+ {0x1218, 0, 6, 0x28}, /* XRX200_PCE_DEFPVID_PVID Default Port VID Index */ -+// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT PCE Port StatusRegister */ -+// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT_LRNCNT Learning Count */ -+// {0x1220, 0, 16, 0x28}, /* XRX200_PCE_PIER Parser and ClassificationEngine Port Interrupt Enable Register */ -+// {0x1220, 5, 1, 0x28}, /* XRX200_PCE_PIER_CLDRP Classification Drop Interrupt Enable */ -+// {0x1220, 4, 1, 0x28}, /* XRX200_PCE_PIER_PTDRP Port Drop Interrupt Enable */ -+// {0x1220, 3, 1, 0x28}, /* XRX200_PCE_PIER_VLAN VLAN Violation Interrupt Enable */ -+// {0x1220, 2, 1, 0x28}, /* XRX200_PCE_PIER_WOL Wake-on-LAN Interrupt Enable */ -+// {0x1220, 1, 1, 0x28}, /* XRX200_PCE_PIER_LOCK Port Limit Alert Interrupt Enable */ -+// {0x1220, 0, 1, 0x28}, /* XRX200_PCE_PIER_LIM Port Lock Alert Interrupt Enable */ -+// {0x1224, 0, 16, 0x28}, /* XRX200_PCE_PISR Parser and ClassificationEngine Port Interrupt Status Register */ -+// {0x1224, 5, 1, 0x28}, /* XRX200_PCE_PISR_CLDRP Classification Drop Interrupt */ -+// {0x1224, 4, 1, 0x28}, /* XRX200_PCE_PISR_PTDRP Port Drop Interrupt */ -+// {0x1224, 3, 1, 0x28}, /* XRX200_PCE_PISR_VLAN VLAN Violation Interrupt */ -+// {0x1224, 2, 1, 0x28}, /* XRX200_PCE_PISR_WOL Wake-on-LAN Interrupt */ -+// {0x1224, 1, 1, 0x28}, /* XRX200_PCE_PISR_LOCK Port Lock Alert Interrupt */ -+// {0x1224, 0, 1, 0x28}, /* XRX200_PCE_PISR_LIMIT Port Limitation Alert Interrupt */ -+// {0x1600, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CTRL Three-colorMarker Control Register */ -+// {0x1600, 0, 1, 0x1c}, /* XRX200_PCE_TCM_CTRL_TCMEN Three-color Marker metering instance enable */ -+// {0x1604, 0, 16, 0x1c}, /* XRX200_PCE_TCM_STAT Three-colorMarker Status Register */ -+// {0x1604, 1, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL1 Three-color Marker Alert 1 Status */ -+// {0x1604, 0, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL0 Three-color Marker Alert 0 Status */ -+// {0x1608, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CBS Three-color MarkerCommitted Burst Size Register */ -+// {0x1608, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CBS_CBS Committed Burst Size */ -+// {0x160C, 0, 16, 0x1c}, /* XRX200_PCE_TCM_EBS Three-color MarkerExcess Burst Size Register */ -+// {0x160C, 0, 10, 0x1c}, /* XRX200_PCE_TCM_EBS_EBS Excess Burst Size */ -+// {0x1610, 0, 16, 0x1c}, /* XRX200_PCE_TCM_IBS Three-color MarkerInstantaneous Burst Size Register */ -+// {0x1610, 0, 2, 0x1c}, /* XRX200_PCE_TCM_IBS_IBS Instantaneous Burst Size */ -+// {0x1614, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT Three-colorMarker Constant Information Rate Mantissa Register */ -+// {0x1614, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT_MANT Rate Counter Mantissa */ -+// {0x1618, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP Three-colorMarker Constant Information Rate Exponent Register */ -+// {0x1618, 0, 4, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP_EXP Rate Counter Exponent */ -+// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST MAC Test Register */ -+// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST_JTP Jitter Test Pattern */ -+// {0x2304, 0, 16, 0x00}, /* XRX200_MAC_PFAD_CFG MAC Pause FrameSource Address Configuration Register */ -+// {0x2304, 0, 1, 0x00}, /* XRX200_MAC_PFAD_CFG_SAMOD Source Address Mode */ -+// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0 Pause Frame SourceAddress Part 0 */ -+// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0_PFAD Pause Frame Source Address Part 0 */ -+// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1 Pause Frame SourceAddress Part 1 */ -+// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1_PFAD Pause Frame Source Address Part 1 */ -+// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2 Pause Frame SourceAddress Part 2 */ -+// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2_PFAD Pause Frame Source Address Part 2 */ -+// {0x2314, 0, 16, 0x00}, /* XRX200_MAC_FLEN MAC Frame Length Register */ -+// {0x2314, 0, 14, 0x00}, /* XRX200_MAC_FLEN_LEN Maximum Frame Length */ -+// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0 MAC VLAN EthertypeRegister 0 */ -+// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0_OUTER Ethertype */ -+// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1 MAC VLAN EthertypeRegister 1 */ -+// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1_INNER Ethertype */ -+// {0x2320, 0, 16, 0x00}, /* XRX200_MAC_IER MAC Interrupt EnableRegister */ -+// {0x2320, 0, 8, 0x00}, /* XRX200_MAC_IER_MACIEN MAC Interrupt Enable */ -+// {0x2324, 0, 16, 0x00}, /* XRX200_MAC_ISR MAC Interrupt StatusRegister */ -+// {0x2324, 0, 8, 0x00}, /* XRX200_MAC_ISR_MACINT MAC Interrupt */ -+// {0x2400, 0, 16, 0x30}, /* XRX200_MAC_PSTAT MAC Port Status Register */ -+// {0x2400, 11, 1, 0x30}, /* XRX200_MAC_PSTAT_PACT PHY Active Status */ -+ {0x2400, 10, 1, 0x30}, /* XRX200_MAC_PSTAT_GBIT Gigabit Speed Status */ -+ {0x2400, 9, 1, 0x30}, /* XRX200_MAC_PSTAT_MBIT Megabit Speed Status */ -+ {0x2400, 8, 1, 0x30}, /* XRX200_MAC_PSTAT_FDUP Full Duplex Status */ -+// {0x2400, 7, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAU Receive Pause Status */ -+// {0x2400, 6, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAU Transmit Pause Status */ -+// {0x2400, 5, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAUEN Receive Pause Enable Status */ -+// {0x2400, 4, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAUEN Transmit Pause Enable Status */ -+ {0x2400, 3, 1, 0x30}, /* XRX200_MAC_PSTAT_LSTAT Link Status */ -+// {0x2400, 2, 1, 0x30}, /* XRX200_MAC_PSTAT_CRS Carrier Sense Status */ -+// {0x2400, 1, 1, 0x30}, /* XRX200_MAC_PSTAT_TXLPI Transmit Low-power Idle Status */ -+// {0x2400, 0, 1, 0x30}, /* XRX200_MAC_PSTAT_RXLPI Receive Low-power Idle Status */ -+// {0x2404, 0, 16, 0x30}, /* XRX200_MAC_PISR MAC Interrupt Status Register */ -+// {0x2404, 13, 1, 0x30}, /* XRX200_MAC_PISR_PACT PHY Active Status */ -+// {0x2404, 12, 1, 0x30}, /* XRX200_MAC_PISR_SPEED Megabit Speed Status */ -+// {0x2404, 11, 1, 0x30}, /* XRX200_MAC_PISR_FDUP Full Duplex Status */ -+// {0x2404, 10, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUEN Receive Pause Enable Status */ -+// {0x2404, 9, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUEN Transmit Pause Enable Status */ -+// {0x2404, 8, 1, 0x30}, /* XRX200_MAC_PISR_LPIOFF Receive Low-power Idle Mode is left */ -+// {0x2404, 7, 1, 0x30}, /* XRX200_MAC_PISR_LPION Receive Low-power Idle Mode is entered */ -+// {0x2404, 6, 1, 0x30}, /* XRX200_MAC_PISR_JAM Jam Status Detected */ -+// {0x2404, 5, 1, 0x30}, /* XRX200_MAC_PISR_TOOSHORT Too Short Frame Error Detected */ -+// {0x2404, 4, 1, 0x30}, /* XRX200_MAC_PISR_TOOLONG Too Long Frame Error Detected */ -+// {0x2404, 3, 1, 0x30}, /* XRX200_MAC_PISR_LENERR Length Mismatch Error Detected */ -+// {0x2404, 2, 1, 0x30}, /* XRX200_MAC_PISR_FCSERR Frame Checksum Error Detected */ -+// {0x2404, 1, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUSE Pause Frame Transmitted */ -+// {0x2404, 0, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUSE Pause Frame Received */ -+// {0x2408, 0, 16, 0x30}, /* XRX200_MAC_PIER MAC Interrupt Enable Register */ -+// {0x2408, 13, 1, 0x30}, /* XRX200_MAC_PIER_PACT PHY Active Status */ -+// {0x2408, 12, 1, 0x30}, /* XRX200_MAC_PIER_SPEED Megabit Speed Status */ -+// {0x2408, 11, 1, 0x30}, /* XRX200_MAC_PIER_FDUP Full Duplex Status */ -+// {0x2408, 10, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUEN Receive Pause Enable Status */ -+// {0x2408, 9, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUEN Transmit Pause Enable Status */ -+// {0x2408, 8, 1, 0x30}, /* XRX200_MAC_PIER_LPIOFF Low-power Idle Off Interrupt Mask */ -+// {0x2408, 7, 1, 0x30}, /* XRX200_MAC_PIER_LPION Low-power Idle On Interrupt Mask */ -+// {0x2408, 6, 1, 0x30}, /* XRX200_MAC_PIER_JAM Jam Status Interrupt Mask */ -+// {0x2408, 5, 1, 0x30}, /* XRX200_MAC_PIER_TOOSHORT Too Short Frame Error Interrupt Mask */ -+// {0x2408, 4, 1, 0x30}, /* XRX200_MAC_PIER_TOOLONG Too Long Frame Error Interrupt Mask */ -+// {0x2408, 3, 1, 0x30}, /* XRX200_MAC_PIER_LENERR Length Mismatch Error Interrupt Mask */ -+// {0x2408, 2, 1, 0x30}, /* XRX200_MAC_PIER_FCSERR Frame Checksum Error Interrupt Mask */ -+// {0x2408, 1, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUSE Transmit Pause Frame Interrupt Mask */ -+// {0x2408, 0, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUSE Receive Pause Frame Interrupt Mask */ -+// {0x240C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_0 MAC Control Register0 */ -+// {0x240C, 13, 2, 0x30}, /* XRX200_MAC_CTRL_0_LCOL Late Collision Control */ -+// {0x240C, 12, 1, 0x30}, /* XRX200_MAC_CTRL_0_BM Burst Mode Control */ -+// {0x240C, 11, 1, 0x30}, /* XRX200_MAC_CTRL_0_APADEN Automatic VLAN Padding Enable */ -+// {0x240C, 10, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPAD2EN Stacked VLAN Padding Enable */ -+// {0x240C, 9, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPADEN VLAN Padding Enable */ -+// {0x240C, 8, 1, 0x30}, /* XRX200_MAC_CTRL_0_PADEN Padding Enable */ -+// {0x240C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_0_FCS Transmit FCS Control */ -+ {0x240C, 4, 3, 0x30}, /* XRX200_MAC_CTRL_0_FCON Flow Control Mode */ -+// {0x240C, 2, 2, 0x30}, /* XRX200_MAC_CTRL_0_FDUP Full Duplex Control */ -+// {0x240C, 0, 2, 0x30}, /* XRX200_MAC_CTRL_0_GMII GMII/MII interface mode selection */ -+// {0x2410, 0, 16, 0x30}, /* XRX200_MAC_CTRL_1 MAC Control Register1 */ -+// {0x2410, 8, 1, 0x30}, /* XRX200_MAC_CTRL_1_SHORTPRE Short Preamble Control */ -+// {0x2410, 0, 4, 0x30}, /* XRX200_MAC_CTRL_1_IPG Minimum Inter Packet Gap Size */ -+// {0x2414, 0, 16, 0x30}, /* XRX200_MAC_CTRL_2 MAC Control Register2 */ -+// {0x2414, 3, 1, 0x30}, /* XRX200_MAC_CTRL_2_MLEN Maximum Untagged Frame Length */ -+// {0x2414, 2, 1, 0x30}, /* XRX200_MAC_CTRL_2_LCHKL Frame Length Check Long Enable */ -+// {0x2414, 0, 2, 0x30}, /* XRX200_MAC_CTRL_2_LCHKS Frame Length Check Short Enable */ -+// {0x2418, 0, 16, 0x30}, /* XRX200_MAC_CTRL_3 MAC Control Register3 */ -+// {0x2418, 0, 4, 0x30}, /* XRX200_MAC_CTRL_3_RCNT Retry Count */ -+// {0x241C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_4 MAC Control Register4 */ -+// {0x241C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_4_LPIEN LPI Mode Enable */ -+// {0x241C, 0, 7, 0x30}, /* XRX200_MAC_CTRL_4_WAIT LPI Wait Time */ -+// {0x2420, 0, 16, 0x30}, /* XRX200_MAC_CTRL_5_PJPS MAC Control Register5 */ -+// {0x2420, 1, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_NOBP Prolonged Jam pattern size during no-backpressure state */ -+// {0x2420, 0, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_BP Prolonged Jam pattern size during backpressure state */ -+// {0x2424, 0, 16, 0x30}, /* XRX200_MAC_CTRL_6_XBUF Transmit and ReceiveBuffer Control Register */ -+// {0x2424, 9, 3, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_DLY_WP Delay */ -+// {0x2424, 8, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_INIT Receive Buffer Initialization */ -+// {0x2424, 6, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_BYPASS Bypass the Receive Buffer */ -+// {0x2424, 3, 3, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_DLY_WP Delay */ -+// {0x2424, 2, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_INIT Initialize the Transmit Buffer */ -+// {0x2424, 0, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_BYPASS Bypass the Transmit Buffer */ -+// {0x2428, 0, 16, 0x30}, /* XRX200_MAC_BUFST_XBUF MAC Receive and TransmitBuffer Status Register */ -+// {0x2428, 3, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_UFL Receive Buffer Underflow Indicator */ -+// {0x2428, 2, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_OFL Receive Buffer Overflow Indicator */ -+// {0x2428, 1, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_UFL Transmit Buffer Underflow Indicator */ -+// {0x2428, 0, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_OFL Transmit Buffer Overflow Indicator */ -+// {0x242C, 0, 16, 0x30}, /* XRX200_MAC_TESTEN MAC Test Enable Register */ -+// {0x242C, 2, 1, 0x30}, /* XRX200_MAC_TESTEN_JTEN Jitter Test Enable */ -+// {0x242C, 1, 1, 0x30}, /* XRX200_MAC_TESTEN_TXER Transmit Error Insertion */ -+// {0x242C, 0, 1, 0x30}, /* XRX200_MAC_TESTEN_LOOP MAC Loopback Enable */ -+// {0x2900, 0, 16, 0x00}, /* XRX200_FDMA_CTRL Ethernet Switch FetchDMA Control Register */ -+// {0x2900, 7, 5, 0x00}, /* XRX200_FDMA_CTRL_LPI_THRESHOLD Low Power Idle Threshold */ -+// {0x2900, 4, 3, 0x00}, /* XRX200_FDMA_CTRL_LPI_MODE Low Power Idle Mode */ -+// {0x2900, 2, 2, 0x00}, /* XRX200_FDMA_CTRL_EGSTAG Egress Special Tag Size */ -+// {0x2900, 1, 1, 0x00}, /* XRX200_FDMA_CTRL_IGSTAG Ingress Special Tag Size */ -+// {0x2900, 0, 1, 0x00}, /* XRX200_FDMA_CTRL_EXCOL Excessive Collision Handling */ -+// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE Special Tag EthertypeControl Register */ -+// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE_ETYPE Special Tag Ethertype */ -+// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE VLAN Tag EthertypeControl Register */ -+// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE_ETYPE VLAN Tag Ethertype */ -+// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0 FDMA Status Register0 */ -+// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0_FSMS FSM states status */ -+// {0x2910, 0, 16, 0x00}, /* XRX200_FDMA_IER Fetch DMA Global InterruptEnable Register */ -+// {0x2910, 14, 1, 0x00}, /* XRX200_FDMA_IER_PCKD Packet Drop Interrupt Enable */ -+// {0x2910, 13, 1, 0x00}, /* XRX200_FDMA_IER_PCKR Packet Ready Interrupt Enable */ -+// {0x2910, 0, 8, 0x00}, /* XRX200_FDMA_IER_PCKT Packet Sent Interrupt Enable */ -+// {0x2914, 0, 16, 0x00}, /* XRX200_FDMA_ISR Fetch DMA Global InterruptStatus Register */ -+// {0x2914, 14, 1, 0x00}, /* XRX200_FDMA_ISR_PCKTD Packet Drop */ -+// {0x2914, 13, 1, 0x00}, /* XRX200_FDMA_ISR_PCKR Packet is Ready for Transmission */ -+// {0x2914, 0, 8, 0x00}, /* XRX200_FDMA_ISR_PCKT Packet Sent Event */ -+// {0x2A00, 0, 16, 0x18}, /* XRX200_FDMA_PCTRL Ethernet SwitchFetch DMA Port Control Register */ -+// {0x2A00, 3, 2, 0x18}, /* XRX200_FDMA_PCTRL_VLANMOD VLAN Modification Enable */ -+// {0x2A00, 2, 1, 0x18}, /* XRX200_FDMA_PCTRL_DSCPRM DSCP Re-marking Enable */ -+// {0x2A00, 1, 1, 0x18}, /* XRX200_FDMA_PCTRL_STEN Special Tag Insertion Enable */ -+// {0x2A00, 0, 1, 0x18}, /* XRX200_FDMA_PCTRL_EN FDMA Port Enable */ -+// {0x2A04, 0, 16, 0x18}, /* XRX200_FDMA_PRIO Ethernet SwitchFetch DMA Port Priority Register */ -+// {0x2A04, 0, 2, 0x18}, /* XRX200_FDMA_PRIO_PRIO FDMA PRIO */ -+// {0x2A08, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT0 Ethernet SwitchFetch DMA Port Status Register 0 */ -+// {0x2A08, 15, 1, 0x18}, /* XRX200_FDMA_PSTAT0_PKT_AVAIL Port Egress Packet Available */ -+// {0x2A08, 14, 1, 0x18}, /* XRX200_FDMA_PSTAT0_POK Port Status OK */ -+// {0x2A08, 0, 6, 0x18}, /* XRX200_FDMA_PSTAT0_PSEG Port Egress Segment Count */ -+// {0x2A0C, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT1_HDR Ethernet SwitchFetch DMA Port Status Register 1 */ -+// {0x2A0C, 0, 10, 0x18}, /* XRX200_FDMA_PSTAT1_HDR_PTR Header Pointer */ -+// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0 Egress TimeStamp Register 0 */ -+// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0_TSTL Time Stamp [15:0] */ -+// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1 Egress TimeStamp Register 1 */ -+// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1_TSTH Time Stamp [31:16] */ -+// {0x2D00, 0, 16, 0x00}, /* XRX200_SDMA_CTRL Ethernet Switch StoreDMA Control Register */ -+// {0x2D00, 0, 1, 0x00}, /* XRX200_SDMA_CTRL_TSTEN Time Stamp Enable */ -+// {0x2D04, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR1 SDMA Flow Control Threshold1 Register */ -+// {0x2D04, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR1_THR1 Threshold 1 */ -+// {0x2D08, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR2 SDMA Flow Control Threshold2 Register */ -+// {0x2D08, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR2_THR2 Threshold 2 */ -+// {0x2D0C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR3 SDMA Flow Control Threshold3 Register */ -+// {0x2D0C, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR3_THR3 Threshold 3 */ -+// {0x2D10, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR4 SDMA Flow Control Threshold4 Register */ -+// {0x2D10, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR4_THR4 Threshold 4 */ -+// {0x2D14, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR5 SDMA Flow Control Threshold5 Register */ -+// {0x2D14, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR5_THR5 Threshold 5 */ -+// {0x2D18, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR6 SDMA Flow Control Threshold6 Register */ -+// {0x2D18, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR6_THR6 Threshold 6 */ -+// {0x2D1C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR7 SDMA Flow Control Threshold7 Register */ -+// {0x2D1C, 0, 11, 0x00}, /* XRX200_SDMA_FCTHR7_THR7 Threshold 7 */ -+// {0x2D20, 0, 16, 0x00}, /* XRX200_SDMA_STAT_0 SDMA Status Register0 */ -+// {0x2D20, 4, 3, 0x00}, /* XRX200_SDMA_STAT_0_BPS_FILL Back Pressure Status */ -+// {0x2D20, 2, 2, 0x00}, /* XRX200_SDMA_STAT_0_BPS_PNT Back Pressure Status */ -+// {0x2D20, 0, 2, 0x00}, /* XRX200_SDMA_STAT_0_DROP Back Pressure Status */ -+// {0x2D24, 0, 16, 0x00}, /* XRX200_SDMA_STAT_1 SDMA Status Register1 */ -+// {0x2D24, 0, 10, 0x00}, /* XRX200_SDMA_STAT_1_FILL Buffer Filling Level */ -+// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2 SDMA Status Register2 */ -+// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2_FSMS FSM states status */ -+// {0x2D2C, 0, 16, 0x00}, /* XRX200_SDMA_IER SDMA Interrupt Enable Register */ -+// {0x2D2C, 15, 1, 0x00}, /* XRX200_SDMA_IER_BPEX Buffer Pointers Exceeded */ -+// {0x2D2C, 14, 1, 0x00}, /* XRX200_SDMA_IER_BFULL Buffer Full */ -+// {0x2D2C, 13, 1, 0x00}, /* XRX200_SDMA_IER_FERR Frame Error */ -+// {0x2D2C, 0, 8, 0x00}, /* XRX200_SDMA_IER_FRX Frame Received Successfully */ -+// {0x2D30, 0, 16, 0x00}, /* XRX200_SDMA_ISR SDMA Interrupt Status Register */ -+// {0x2D30, 15, 1, 0x00}, /* XRX200_SDMA_ISR_BPEX Packet Descriptors Exceeded */ -+// {0x2D30, 14, 1, 0x00}, /* XRX200_SDMA_ISR_BFULL Buffer Full */ -+// {0x2D30, 13, 1, 0x00}, /* XRX200_SDMA_ISR_FERR Frame Error */ -+// {0x2D30, 0, 8, 0x00}, /* XRX200_SDMA_ISR_FRX Frame Received Successfully */ -+// {0x2F00, 0, 16, 0x18}, /* XRX200_SDMA_PCTRL Ethernet SwitchStore DMA Port Control Register */ -+// {0x2F00, 13, 2, 0x18}, /* XRX200_SDMA_PCTRL_DTHR Drop Threshold Selection */ -+// {0x2F00, 11, 2, 0x18}, /* XRX200_SDMA_PCTRL_PTHR Pause Threshold Selection */ -+// {0x2F00, 10, 1, 0x18}, /* XRX200_SDMA_PCTRL_PHYEFWD Forward PHY Error Frames */ -+// {0x2F00, 9, 1, 0x18}, /* XRX200_SDMA_PCTRL_ALGFWD Forward Alignment Error Frames */ -+// {0x2F00, 8, 1, 0x18}, /* XRX200_SDMA_PCTRL_LENFWD Forward Length Errored Frames */ -+// {0x2F00, 7, 1, 0x18}, /* XRX200_SDMA_PCTRL_OSFWD Forward Oversized Frames */ -+// {0x2F00, 6, 1, 0x18}, /* XRX200_SDMA_PCTRL_USFWD Forward Undersized Frames */ -+// {0x2F00, 5, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSIGN Ignore FCS Errors */ -+// {0x2F00, 4, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSFWD Forward FCS Errored Frames */ -+// {0x2F00, 3, 1, 0x18}, /* XRX200_SDMA_PCTRL_PAUFWD Pause Frame Forwarding */ -+// {0x2F00, 2, 1, 0x18}, /* XRX200_SDMA_PCTRL_MFCEN Metering Flow Control Enable */ -+// {0x2F00, 1, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCEN Flow Control Enable */ -+// {0x2F00, 0, 1, 0x18}, /* XRX200_SDMA_PCTRL_PEN Port Enable */ -+// {0x2F04, 0, 16, 0x18}, /* XRX200_SDMA_PRIO Ethernet SwitchStore DMA Port Priority Register */ -+// {0x2F04, 0, 2, 0x18}, /* XRX200_SDMA_PRIO_PRIO SDMA PRIO */ -+// {0x2F08, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT0_HDR Ethernet SwitchStore DMA Port Status Register 0 */ -+// {0x2F08, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT0_HDR_PTR Port Ingress Queue Header Pointer */ -+// {0x2F0C, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT1 Ethernet SwitchStore DMA Port Status Register 1 */ -+// {0x2F0C, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT1_PPKT Port Ingress Packet Count */ -+// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0 Ingress TimeStamp Register 0 */ -+// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0_TSTL Time Stamp [15:0] */ -+// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1 Ingress TimeStamp Register 1 */ -+// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1_TSTH Time Stamp [31:16] */ -+}; -+ -+ diff --git a/target/linux/lantiq/patches-4.19/0028-NET-lantiq-various-etop-fixes.patch b/target/linux/lantiq/patches-4.19/0028-NET-lantiq-various-etop-fixes.patch deleted file mode 100644 index a336af8a3c..0000000000 --- a/target/linux/lantiq/patches-4.19/0028-NET-lantiq-various-etop-fixes.patch +++ /dev/null @@ -1,878 +0,0 @@ -From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 9 Sep 2014 22:45:34 +0200 -Subject: [PATCH 28/36] NET: lantiq: various etop fixes - -Signed-off-by: John Crispin ---- - drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- - 1 file changed, 389 insertions(+), 166 deletions(-) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -11,7 +11,7 @@ - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - * -- * Copyright (C) 2011 John Crispin -+ * Copyright (C) 2011-12 John Crispin - */ - - #include -@@ -30,11 +30,16 @@ - #include - #include - #include -+#include - #include - #include - #include - #include - #include -+#include -+#include -+#include -+#include - - #include - -@@ -42,7 +47,7 @@ - #include - #include - --#define LTQ_ETOP_MDIO 0x11804 -+#define LTQ_ETOP_MDIO_ACC 0x11804 - #define MDIO_REQUEST 0x80000000 - #define MDIO_READ 0x40000000 - #define MDIO_ADDR_MASK 0x1f -@@ -51,44 +56,91 @@ - #define MDIO_REG_OFFSET 0x10 - #define MDIO_VAL_MASK 0xffff - --#define PPE32_CGEN 0x800 --#define LQ_PPE32_ENET_MAC_CFG 0x1840 -+#define LTQ_ETOP_MDIO_CFG 0x11800 -+#define MDIO_CFG_MASK 0x6 -+ -+#define LTQ_ETOP_CFG 0x11808 -+#define LTQ_ETOP_IGPLEN 0x11820 -+#define LTQ_ETOP_MAC_CFG 0x11840 - - #define LTQ_ETOP_ENETS0 0x11850 - #define LTQ_ETOP_MAC_DA0 0x1186C - #define LTQ_ETOP_MAC_DA1 0x11870 --#define LTQ_ETOP_CFG 0x16020 --#define LTQ_ETOP_IGPLEN 0x16080 -+ -+#define MAC_CFG_MASK 0xfff -+#define MAC_CFG_CGEN (1 << 11) -+#define MAC_CFG_DUPLEX (1 << 2) -+#define MAC_CFG_SPEED (1 << 1) -+#define MAC_CFG_LINK (1 << 0) - - #define MAX_DMA_CHAN 0x8 - #define MAX_DMA_CRC_LEN 0x4 - #define MAX_DMA_DATA_LEN 0x600 - - #define ETOP_FTCU BIT(28) --#define ETOP_MII_MASK 0xf --#define ETOP_MII_NORMAL 0xd --#define ETOP_MII_REVERSE 0xe - #define ETOP_PLEN_UNDER 0x40 --#define ETOP_CGEN 0x800 -+#define ETOP_CFG_MII0 0x01 - --/* use 2 static channels for TX/RX */ --#define LTQ_ETOP_TX_CHANNEL 1 --#define LTQ_ETOP_RX_CHANNEL 6 --#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) --#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) -+#define ETOP_CFG_MASK 0xfff -+#define ETOP_CFG_FEN0 (1 << 8) -+#define ETOP_CFG_SEN0 (1 << 6) -+#define ETOP_CFG_OFF1 (1 << 3) -+#define ETOP_CFG_REMII0 (1 << 1) -+#define ETOP_CFG_OFF0 (1 << 0) -+ -+#define LTQ_GBIT_MDIO_CTL 0xCC -+#define LTQ_GBIT_MDIO_DATA 0xd0 -+#define LTQ_GBIT_GCTL0 0x68 -+#define LTQ_GBIT_PMAC_HD_CTL 0x8c -+#define LTQ_GBIT_P0_CTL 0x4 -+#define LTQ_GBIT_PMAC_RX_IPG 0xa8 -+#define LTQ_GBIT_RGMII_CTL 0x78 -+ -+#define PMAC_HD_CTL_AS (1 << 19) -+#define PMAC_HD_CTL_RXSH (1 << 22) -+ -+/* Switch Enable (0=disable, 1=enable) */ -+#define GCTL0_SE 0x80000000 -+/* Disable MDIO auto polling (0=disable, 1=enable) */ -+#define PX_CTL_DMDIO 0x00400000 -+ -+/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ -+#define MDC_CLOCK_MASK 0xff000000 -+#define MDC_CLOCK_OFFSET 24 -+ -+/* register information for the gbit's MDIO bus */ -+#define MDIO_XR9_REQUEST 0x00008000 -+#define MDIO_XR9_READ 0x00000800 -+#define MDIO_XR9_WRITE 0x00000400 -+#define MDIO_XR9_REG_MASK 0x1f -+#define MDIO_XR9_ADDR_MASK 0x1f -+#define MDIO_XR9_RD_MASK 0xffff -+#define MDIO_XR9_REG_OFFSET 0 -+#define MDIO_XR9_ADDR_OFFSET 5 -+#define MDIO_XR9_WR_OFFSET 16 - -+#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \ -+ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) -+ -+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ - #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) - #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) - #define ltq_etop_w32_mask(x, y, z) \ - ltq_w32_mask(x, y, ltq_etop_membase + (z)) - --#define DRV_VERSION "1.0" -+#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) -+#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) -+#define ltq_gbit_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) -+ -+#define DRV_VERSION "1.2" - - static void __iomem *ltq_etop_membase; -+static void __iomem *ltq_gbit_membase; - - struct ltq_etop_chan { -- int idx; - int tx_free; -+ int irq; - struct net_device *netdev; - struct napi_struct napi; - struct ltq_dma_channel dma; -@@ -98,23 +150,36 @@ struct ltq_etop_chan { - struct ltq_etop_priv { - struct net_device *netdev; - struct platform_device *pdev; -- struct ltq_eth_data *pldata; - struct resource *res; - - struct mii_bus *mii_bus; - -- struct ltq_etop_chan ch[MAX_DMA_CHAN]; -- int tx_free[MAX_DMA_CHAN >> 1]; -+ struct ltq_etop_chan txch; -+ struct ltq_etop_chan rxch; - -- spinlock_t lock; -+ int tx_irq; -+ int rx_irq; -+ -+ unsigned char mac[6]; -+ int mii_mode; -+ -+ spinlock_t lock; -+ -+ struct clk *clk_ppe; -+ struct clk *clk_switch; -+ struct clk *clk_ephy; -+ struct clk *clk_ephycgu; - }; - -+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, -+ int phy_reg, u16 phy_data); -+ - static int - ltq_etop_alloc_skb(struct ltq_etop_chan *ch) - { - struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - -- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); -+ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); - if (!ch->skb[ch->dma.desc]) - return -ENOMEM; - ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev, -@@ -149,8 +214,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan - spin_unlock_irqrestore(&priv->lock, flags); - - skb_put(skb, len); -+ skb->dev = ch->netdev; - skb->protocol = eth_type_trans(skb, ch->netdev); - netif_receive_skb(skb); -+ ch->netdev->stats.rx_packets++; -+ ch->netdev->stats.rx_bytes += len; - } - - static int -@@ -158,7 +226,9 @@ ltq_etop_poll_rx(struct napi_struct *nap - { - struct ltq_etop_chan *ch = container_of(napi, - struct ltq_etop_chan, napi); -+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - int work_done = 0; -+ unsigned long flags; - - while (work_done < budget) { - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -@@ -170,7 +240,9 @@ ltq_etop_poll_rx(struct napi_struct *nap - } - if (work_done < budget) { - napi_complete_done(&ch->napi, work_done); -+ spin_lock_irqsave(&priv->lock, flags); - ltq_dma_ack_irq(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); - } - return work_done; - } -@@ -182,12 +254,14 @@ ltq_etop_poll_tx(struct napi_struct *nap - container_of(napi, struct ltq_etop_chan, napi); - struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - struct netdev_queue *txq = -- netdev_get_tx_queue(ch->netdev, ch->idx >> 1); -+ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); - while ((ch->dma.desc_base[ch->tx_free].ctl & - (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { -+ ch->netdev->stats.tx_packets++; -+ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len; - dev_kfree_skb_any(ch->skb[ch->tx_free]); - ch->skb[ch->tx_free] = NULL; - memset(&ch->dma.desc_base[ch->tx_free], 0, -@@ -200,7 +274,9 @@ ltq_etop_poll_tx(struct napi_struct *nap - if (netif_tx_queue_stopped(txq)) - netif_tx_start_queue(txq); - napi_complete(&ch->napi); -+ spin_lock_irqsave(&priv->lock, flags); - ltq_dma_ack_irq(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); - return 1; - } - -@@ -208,9 +284,10 @@ static irqreturn_t - ltq_etop_dma_irq(int irq, void *_priv) - { - struct ltq_etop_priv *priv = _priv; -- int ch = irq - LTQ_DMA_CH0_INT; -- -- napi_schedule(&priv->ch[ch].napi); -+ if (irq == priv->txch.dma.irq) -+ napi_schedule(&priv->txch.napi); -+ else -+ napi_schedule(&priv->rxch.napi); - return IRQ_HANDLED; - } - -@@ -222,7 +299,7 @@ ltq_etop_free_channel(struct net_device - ltq_dma_free(&ch->dma); - if (ch->dma.irq) - free_irq(ch->dma.irq, priv); -- if (IS_RX(ch->idx)) { -+ if (ch == &priv->txch) { - int desc; - for (desc = 0; desc < LTQ_DESC_NUM; desc++) - dev_kfree_skb_any(ch->skb[ch->dma.desc]); -@@ -233,66 +310,135 @@ static void - ltq_etop_hw_exit(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; - -- ltq_pmu_disable(PMU_PPE); -- for (i = 0; i < MAX_DMA_CHAN; i++) -- if (IS_TX(i) || IS_RX(i)) -- ltq_etop_free_channel(dev, &priv->ch[i]); -+ clk_disable(priv->clk_ppe); -+ -+ if (of_machine_is_compatible("lantiq,ar9")) -+ clk_disable(priv->clk_switch); -+ -+ if (of_machine_is_compatible("lantiq,ase")) { -+ clk_disable(priv->clk_ephy); -+ clk_disable(priv->clk_ephycgu); -+ } -+ -+ ltq_etop_free_channel(dev, &priv->txch); -+ ltq_etop_free_channel(dev, &priv->rxch); -+} -+ -+static void -+ltq_etop_gbit_init(struct net_device *dev) -+{ -+ struct ltq_etop_priv *priv = netdev_priv(dev); -+ -+ clk_enable(priv->clk_switch); -+ -+ /* enable gbit port0 on the SoC */ -+ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL); -+ -+ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); -+ /* disable MDIO auto polling mode */ -+ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); -+ /* set 1522 packet size */ -+ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); -+ /* disable pmac & dmac headers */ -+ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, -+ LTQ_GBIT_PMAC_HD_CTL); -+ /* Due to traffic halt when burst length 8, -+ replace default IPG value with 0x3B */ -+ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); -+ /* set mdc clock to 2.5 MHz */ -+ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, -+ LTQ_GBIT_RGMII_CTL); - } - - static int - ltq_etop_hw_init(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ int mii_mode = priv->mii_mode; -+ -+ clk_enable(priv->clk_ppe); - -- ltq_pmu_enable(PMU_PPE); -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ ltq_etop_gbit_init(dev); -+ /* force the etops link to the gbit to MII */ -+ mii_mode = PHY_INTERFACE_MODE_MII; -+ } -+ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG); -+ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX | -+ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG); - -- switch (priv->pldata->mii_mode) { -+ switch (mii_mode) { - case PHY_INTERFACE_MODE_RMII: -- ltq_etop_w32_mask(ETOP_MII_MASK, -- ETOP_MII_REVERSE, LTQ_ETOP_CFG); -+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 | -+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); - break; - - case PHY_INTERFACE_MODE_MII: -- ltq_etop_w32_mask(ETOP_MII_MASK, -- ETOP_MII_NORMAL, LTQ_ETOP_CFG); -+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 | -+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); - break; - - default: -+ if (of_machine_is_compatible("lantiq,ase")) { -+ clk_enable(priv->clk_ephy); -+ /* disable external MII */ -+ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); -+ /* enable clock for internal PHY */ -+ clk_enable(priv->clk_ephycgu); -+ /* we need to write this magic to the internal phy to -+ make it work */ -+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); -+ pr_info("Selected EPHY mode\n"); -+ break; -+ } - netdev_err(dev, "unknown mii mode %d\n", -- priv->pldata->mii_mode); -+ mii_mode); - return -ENOTSUPP; - } - -- /* enable crc generation */ -- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); -+ return 0; -+} -+ -+static int -+ltq_etop_dma_init(struct net_device *dev) -+{ -+ struct ltq_etop_priv *priv = netdev_priv(dev); -+ int tx = priv->tx_irq - LTQ_DMA_ETOP; -+ int rx = priv->rx_irq - LTQ_DMA_ETOP; -+ int err; - - ltq_dma_init_port(DMA_PORT_ETOP); - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- int irq = LTQ_DMA_CH0_INT + i; -- struct ltq_etop_chan *ch = &priv->ch[i]; -- -- ch->idx = ch->dma.nr = i; -- ch->dma.dev = &priv->pdev->dev; -- -- if (IS_TX(i)) { -- ltq_dma_alloc_tx(&ch->dma); -- request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); -- } else if (IS_RX(i)) { -- ltq_dma_alloc_rx(&ch->dma); -- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; -- ch->dma.desc++) -- if (ltq_etop_alloc_skb(ch)) -- return -ENOMEM; -- ch->dma.desc = 0; -- request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); -+ priv->txch.dma.nr = tx; -+ priv->txch.dma.dev = &priv->pdev->dev; -+ ltq_dma_alloc_tx(&priv->txch.dma); -+ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv); -+ if (err) { -+ netdev_err(dev, "failed to allocate tx irq\n"); -+ goto err_out; -+ } -+ priv->txch.dma.irq = priv->tx_irq; -+ -+ priv->rxch.dma.nr = rx; -+ priv->rxch.dma.dev = &priv->pdev->dev; -+ ltq_dma_alloc_rx(&priv->rxch.dma); -+ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; -+ priv->rxch.dma.desc++) { -+ if (ltq_etop_alloc_skb(&priv->rxch)) { -+ netdev_err(dev, "failed to allocate skbs\n"); -+ err = -ENOMEM; -+ goto err_out; - } -- ch->dma.irq = irq; - } -- return 0; -+ priv->rxch.dma.desc = 0; -+ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv); -+ if (err) -+ netdev_err(dev, "failed to allocate rx irq\n"); -+ else -+ priv->rxch.dma.irq = priv->rx_irq; -+err_out: -+ return err; - } - - static void -@@ -311,6 +457,39 @@ static const struct ethtool_ops ltq_etop - }; - - static int -+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, -+ int phy_reg, u16 phy_data) -+{ -+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | -+ (phy_data << MDIO_XR9_WR_OFFSET) | -+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | -+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); -+ -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ return 0; -+} -+ -+static int -+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) -+{ -+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | -+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | -+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); -+ -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; -+ return val; -+} -+ -+static int - ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) - { - u32 val = MDIO_REQUEST | -@@ -318,9 +497,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in - ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | - phy_data; - -- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) -+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) - ; -- ltq_etop_w32(val, LTQ_ETOP_MDIO); -+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); - return 0; - } - -@@ -331,12 +510,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in - ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | - ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); - -- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) -+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) - ; -- ltq_etop_w32(val, LTQ_ETOP_MDIO); -- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) -+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); -+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) - ; -- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; -+ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK; - return val; - } - -@@ -351,8 +530,18 @@ ltq_etop_mdio_probe(struct net_device *d - { - struct ltq_etop_priv *priv = netdev_priv(dev); - struct phy_device *phydev; -+ u32 phy_supported = (SUPPORTED_10baseT_Half -+ | SUPPORTED_10baseT_Full -+ | SUPPORTED_100baseT_Half -+ | SUPPORTED_100baseT_Full -+ | SUPPORTED_Autoneg -+ | SUPPORTED_MII -+ | SUPPORTED_TP); - -- phydev = phy_find_first(priv->mii_bus); -+ if (of_machine_is_compatible("lantiq,ase")) -+ phydev = mdiobus_get_phy(priv->mii_bus, 8); -+ else -+ phydev = mdiobus_get_phy(priv->mii_bus, 0); - - if (!phydev) { - netdev_err(dev, "no PHY found\n"); -@@ -360,21 +549,18 @@ ltq_etop_mdio_probe(struct net_device *d - } - - phydev = phy_connect(dev, phydev_name(phydev), -- <q_etop_mdio_link, priv->pldata->mii_mode); -+ <q_etop_mdio_link, priv->mii_mode); - - if (IS_ERR(phydev)) { - netdev_err(dev, "Could not attach to PHY\n"); - return PTR_ERR(phydev); - } - -- phydev->supported &= (SUPPORTED_10baseT_Half -- | SUPPORTED_10baseT_Full -- | SUPPORTED_100baseT_Half -- | SUPPORTED_100baseT_Full -- | SUPPORTED_Autoneg -- | SUPPORTED_MII -- | SUPPORTED_TP); -+ if (of_machine_is_compatible("lantiq,ar9")) -+ phy_supported |= SUPPORTED_1000baseT_Half -+ | SUPPORTED_1000baseT_Full; - -+ phydev->supported &= phy_supported; - phydev->advertising = phydev->supported; - phy_attached_info(phydev); - -@@ -395,8 +581,13 @@ ltq_etop_mdio_init(struct net_device *de - } - - priv->mii_bus->priv = dev; -- priv->mii_bus->read = ltq_etop_mdio_rd; -- priv->mii_bus->write = ltq_etop_mdio_wr; -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; -+ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; -+ } else { -+ priv->mii_bus->read = ltq_etop_mdio_rd; -+ priv->mii_bus->write = ltq_etop_mdio_wr; -+ } - priv->mii_bus->name = "ltq_mii"; - snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", - priv->pdev->name, priv->pdev->id); -@@ -433,17 +624,19 @@ static int - ltq_etop_open(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ unsigned long flags; - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- struct ltq_etop_chan *ch = &priv->ch[i]; -+ napi_enable(&priv->txch.napi); -+ napi_enable(&priv->rxch.napi); -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_open(&priv->txch.dma); -+ ltq_dma_open(&priv->rxch.dma); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ -+ if (dev->phydev) -+ phy_start(dev->phydev); - -- if (!IS_TX(i) && (!IS_RX(i))) -- continue; -- ltq_dma_open(&ch->dma); -- napi_enable(&ch->napi); -- } -- phy_start(dev->phydev); - netif_tx_start_all_queues(dev); - return 0; - } -@@ -452,18 +645,19 @@ static int - ltq_etop_stop(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ unsigned long flags; - - netif_tx_stop_all_queues(dev); -- phy_stop(dev->phydev); -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- struct ltq_etop_chan *ch = &priv->ch[i]; -- -- if (!IS_RX(i) && !IS_TX(i)) -- continue; -- napi_disable(&ch->napi); -- ltq_dma_close(&ch->dma); -- } -+ if (dev->phydev) -+ phy_stop(dev->phydev); -+ napi_disable(&priv->txch.napi); -+ napi_disable(&priv->rxch.napi); -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_close(&priv->txch.dma); -+ ltq_dma_close(&priv->rxch.dma); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ - return 0; - } - -@@ -473,16 +667,16 @@ ltq_etop_tx(struct sk_buff *skb, struct - int queue = skb_get_queue_mapping(skb); - struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); - struct ltq_etop_priv *priv = netdev_priv(dev); -- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; -- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -- int len; -+ struct ltq_dma_desc *desc = -+ &priv->txch.dma.desc_base[priv->txch.dma.desc]; - unsigned long flags; - u32 byte_offset; -+ int len; - - len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; - -- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { -- dev_kfree_skb_any(skb); -+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || -+ priv->txch.skb[priv->txch.dma.desc]) { - netdev_err(dev, "tx ring full\n"); - netif_tx_stop_queue(txq); - return NETDEV_TX_BUSY; -@@ -490,7 +684,7 @@ ltq_etop_tx(struct sk_buff *skb, struct - - /* dma needs to start on a 16 byte aligned address */ - byte_offset = CPHYSADDR(skb->data) % 16; -- ch->skb[ch->dma.desc] = skb; -+ priv->txch.skb[priv->txch.dma.desc] = skb; - - netif_trans_update(dev); - -@@ -500,11 +694,11 @@ ltq_etop_tx(struct sk_buff *skb, struct - wmb(); - desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | - LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); -- ch->dma.desc++; -- ch->dma.desc %= LTQ_DESC_NUM; -+ priv->txch.dma.desc++; -+ priv->txch.dma.desc %= LTQ_DESC_NUM; - spin_unlock_irqrestore(&priv->lock, flags); - -- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) -+ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) - netif_tx_stop_queue(txq); - - return NETDEV_TX_OK; -@@ -515,11 +709,14 @@ ltq_etop_change_mtu(struct net_device *d - { - struct ltq_etop_priv *priv = netdev_priv(dev); - unsigned long flags; -+ int max; - - dev->mtu = new_mtu; - -+ max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN; -+ - spin_lock_irqsave(&priv->lock, flags); -- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); -+ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN); - spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -@@ -579,6 +776,9 @@ ltq_etop_init(struct net_device *dev) - if (err) - goto err_hw; - ltq_etop_change_mtu(dev, 1500); -+ err = ltq_etop_dma_init(dev); -+ if (err) -+ goto err_hw; - - memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); - if (!is_valid_ether_addr(mac.sa_data)) { -@@ -596,9 +796,10 @@ ltq_etop_init(struct net_device *dev) - dev->addr_assign_type = NET_ADDR_RANDOM; - - ltq_etop_set_multicast_list(dev); -- err = ltq_etop_mdio_init(dev); -- if (err) -- goto err_netdev; -+ if (!ltq_etop_mdio_init(dev)) -+ dev->ethtool_ops = <q_etop_ethtool_ops; -+ else -+ pr_warn("etop: mdio probe failed\n");; - return 0; - - err_netdev: -@@ -618,6 +819,9 @@ ltq_etop_tx_timeout(struct net_device *d - err = ltq_etop_hw_init(dev); - if (err) - goto err_hw; -+ err = ltq_etop_dma_init(dev); -+ if (err) -+ goto err_hw; - netif_trans_update(dev); - netif_wake_queue(dev); - return; -@@ -641,14 +845,19 @@ static const struct net_device_ops ltq_e - .ndo_tx_timeout = ltq_etop_tx_timeout, - }; - --static int __init --ltq_etop_probe(struct platform_device *pdev) -+static int ltq_etop_probe(struct platform_device *pdev) - { - struct net_device *dev; - struct ltq_etop_priv *priv; -- struct resource *res; -+ struct resource *res, *gbit_res, irqres[2]; -+ const u8 *mac; - int err; -- int i; -+ -+ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2); -+ if (err != 2) { -+ dev_err(&pdev->dev, "failed to get etop irqs\n"); -+ return -EINVAL; -+ } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { -@@ -674,31 +883,62 @@ ltq_etop_probe(struct platform_device *p - goto err_out; - } - -- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); -- if (!dev) { -- err = -ENOMEM; -- goto err_out; -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); -+ if (!gbit_res) { -+ dev_err(&pdev->dev, "failed to get gbit resource\n"); -+ err = -ENOENT; -+ goto err_out; -+ } -+ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev, -+ gbit_res->start, resource_size(gbit_res)); -+ if (!ltq_gbit_membase) { -+ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", -+ pdev->id); -+ err = -ENOMEM; -+ goto err_out; -+ } - } -+ -+ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); - strcpy(dev->name, "eth%d"); - dev->netdev_ops = <q_eth_netdev_ops; -- dev->ethtool_ops = <q_etop_ethtool_ops; - priv = netdev_priv(dev); - priv->res = res; - priv->pdev = pdev; -- priv->pldata = dev_get_platdata(&pdev->dev); - priv->netdev = dev; -+ priv->tx_irq = irqres[0].start; -+ priv->rx_irq = irqres[1].start; -+ priv->mii_mode = of_get_phy_mode(pdev->dev.of_node); -+ -+ mac = of_get_mac_address(pdev->dev.of_node); -+ if (mac) -+ memcpy(priv->mac, mac, ETH_ALEN); -+ -+ priv->clk_ppe = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(priv->clk_ppe)) -+ return PTR_ERR(priv->clk_ppe); -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ priv->clk_switch = clk_get(&pdev->dev, "switch"); -+ if (IS_ERR(priv->clk_switch)) -+ return PTR_ERR(priv->clk_switch); -+ } -+ if (of_machine_is_compatible("lantiq,ase")) { -+ priv->clk_ephy = clk_get(&pdev->dev, "ephy"); -+ if (IS_ERR(priv->clk_ephy)) -+ return PTR_ERR(priv->clk_ephy); -+ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); -+ if (IS_ERR(priv->clk_ephycgu)) -+ return PTR_ERR(priv->clk_ephycgu); -+ } -+ - spin_lock_init(&priv->lock); - SET_NETDEV_DEV(dev, &pdev->dev); - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- if (IS_TX(i)) -- netif_napi_add(dev, &priv->ch[i].napi, -- ltq_etop_poll_tx, 8); -- else if (IS_RX(i)) -- netif_napi_add(dev, &priv->ch[i].napi, -- ltq_etop_poll_rx, 32); -- priv->ch[i].netdev = dev; -- } -+ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); -+ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); -+ priv->txch.netdev = dev; -+ priv->rxch.netdev = dev; - - err = register_netdev(dev); - if (err) -@@ -727,31 +967,22 @@ ltq_etop_remove(struct platform_device * - return 0; - } - -+static const struct of_device_id ltq_etop_match[] = { -+ { .compatible = "lantiq,etop-xway" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ltq_etop_match); -+ - static struct platform_driver ltq_mii_driver = { -+ .probe = ltq_etop_probe, - .remove = ltq_etop_remove, - .driver = { - .name = "ltq_etop", -+ .of_match_table = ltq_etop_match, - }, - }; - --int __init --init_ltq_etop(void) --{ -- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); -- -- if (ret) -- pr_err("ltq_etop: Error registering platform driver!"); -- return ret; --} -- --static void __exit --exit_ltq_etop(void) --{ -- platform_driver_unregister(<q_mii_driver); --} -- --module_init(init_ltq_etop); --module_exit(exit_ltq_etop); -+module_platform_driver(ltq_mii_driver); - - MODULE_AUTHOR("John Crispin "); - MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/target/linux/lantiq/patches-4.19/0030-GPIO-add-named-gpio-exports.patch b/target/linux/lantiq/patches-4.19/0030-GPIO-add-named-gpio-exports.patch deleted file mode 100644 index 8e3060d768..0000000000 --- a/target/linux/lantiq/patches-4.19/0030-GPIO-add-named-gpio-exports.patch +++ /dev/null @@ -1,169 +0,0 @@ -From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 12 Aug 2014 20:49:27 +0200 -Subject: [PATCH 30/36] GPIO: add named gpio exports - -Signed-off-by: John Crispin ---- - drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++ - drivers/gpio/gpiolib.c | 11 +++++-- - include/asm-generic/gpio.h | 5 +++ - include/linux/gpio/consumer.h | 8 +++++ - 4 files changed, 90 insertions(+), 2 deletions(-) - ---- a/drivers/gpio/gpiolib-of.c -+++ b/drivers/gpio/gpiolib-of.c -@@ -23,6 +23,8 @@ - #include - #include - #include -+#include -+#include - - #include "gpiolib.h" - -@@ -660,3 +662,72 @@ void of_gpiochip_remove(struct gpio_chip - gpiochip_remove_pin_ranges(chip); - of_node_put(chip->of_node); - } -+ -+#ifdef CONFIG_GPIO_SYSFS -+ -+static struct of_device_id gpio_export_ids[] = { -+ { .compatible = "gpio-export" }, -+ { /* sentinel */ } -+}; -+ -+static int of_gpio_export_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct device_node *cnp; -+ u32 val; -+ int nb = 0; -+ -+ for_each_child_of_node(np, cnp) { -+ const char *name = NULL; -+ int gpio; -+ bool dmc; -+ int max_gpio = 1; -+ int i; -+ -+ of_property_read_string(cnp, "gpio-export,name", &name); -+ -+ if (!name) -+ max_gpio = of_gpio_count(cnp); -+ -+ for (i = 0; i < max_gpio; i++) { -+ unsigned flags = 0; -+ enum of_gpio_flags of_flags; -+ -+ gpio = of_get_gpio_flags(cnp, i, &of_flags); -+ if (!gpio_is_valid(gpio)) -+ return gpio; -+ -+ if (of_flags == OF_GPIO_ACTIVE_LOW) -+ flags |= GPIOF_ACTIVE_LOW; -+ -+ if (!of_property_read_u32(cnp, "gpio-export,output", &val)) -+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; -+ else -+ flags |= GPIOF_IN; -+ -+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np))) -+ continue; -+ -+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change"); -+ gpio_export_with_name(gpio, dmc, name); -+ nb++; -+ } -+ } -+ -+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb); -+ -+ return 0; -+} -+ -+static struct platform_driver gpio_export_driver = { -+ .driver = { -+ .name = "gpio-export", -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(gpio_export_ids), -+ }, -+ .probe = of_gpio_export_probe, -+}; -+ -+module_platform_driver(gpio_export_driver); -+ -+#endif ---- a/include/asm-generic/gpio.h -+++ b/include/asm-generic/gpio.h -@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g - return gpiod_export(gpio_to_desc(gpio), direction_may_change); - } - -+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); -+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name) -+{ -+ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name); -+} -+ - static inline int gpio_export_link(struct device *dev, const char *name, - unsigned gpio) - { ---- a/include/linux/gpio/consumer.h -+++ b/include/linux/gpio/consumer.h -@@ -533,6 +533,7 @@ struct gpio_desc *devm_fwnode_get_gpiod_ - - #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS) - -+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); - int gpiod_export(struct gpio_desc *desc, bool direction_may_change); - int gpiod_export_link(struct device *dev, const char *name, - struct gpio_desc *desc); -@@ -540,6 +541,13 @@ void gpiod_unexport(struct gpio_desc *de - - #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ - -+static inline int _gpiod_export(struct gpio_desc *desc, -+ bool direction_may_change, -+ const char *name) -+{ -+ return -ENOSYS; -+} -+ - static inline int gpiod_export(struct gpio_desc *desc, - bool direction_may_change) - { ---- a/drivers/gpio/gpiolib-sysfs.c -+++ b/drivers/gpio/gpiolib-sysfs.c -@@ -568,7 +568,7 @@ static struct class gpio_class = { - * - * Returns zero on success, else an error. - */ --int gpiod_export(struct gpio_desc *desc, bool direction_may_change) -+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name) - { - struct gpio_chip *chip; - struct gpio_device *gdev; -@@ -630,6 +630,8 @@ int gpiod_export(struct gpio_desc *desc, - offset = gpio_chip_hwgpio(desc); - if (chip->names && chip->names[offset]) - ioname = chip->names[offset]; -+ if (name) -+ ioname = name; - - dev = device_create_with_groups(&gpio_class, &gdev->dev, - MKDEV(0, 0), data, gpio_groups, -@@ -651,6 +653,12 @@ err_unlock: - gpiod_dbg(desc, "%s: status %d\n", __func__, status); - return status; - } -+EXPORT_SYMBOL_GPL(__gpiod_export); -+ -+int gpiod_export(struct gpio_desc *desc, bool direction_may_change) -+{ -+ return __gpiod_export(desc, direction_may_change, NULL); -+} - EXPORT_SYMBOL_GPL(gpiod_export); - - static int match_export(struct device *dev, const void *desc) diff --git a/target/linux/lantiq/patches-4.19/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-4.19/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch deleted file mode 100644 index eed32d3097..0000000000 --- a/target/linux/lantiq/patches-4.19/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch +++ /dev/null @@ -1,1034 +0,0 @@ -From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:26:42 +0200 -Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master - -This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin ---- - drivers/i2c/busses/Kconfig | 10 + - drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++ - drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++ - 4 files changed, 992 insertions(+) - create mode 100644 drivers/i2c/busses/i2c-lantiq.c - create mode 100644 drivers/i2c/busses/i2c-lantiq.h - ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -691,6 +691,16 @@ config I2C_MESON - If you say yes to this option, support will be included for the - I2C interface on the Amlogic Meson family of SoCs. - -+config I2C_LANTIQ -+ tristate "Lantiq I2C interface" -+ depends on LANTIQ && SOC_FALCON -+ help -+ If you say yes to this option, support will be included for the -+ Lantiq I2C core. -+ -+ This driver can also be built as a module. If so, the module -+ will be called i2c-lantiq. -+ - config I2C_MPC - tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" - depends on PPC ---- a/drivers/i2c/busses/Makefile -+++ b/drivers/i2c/busses/Makefile -@@ -67,6 +67,7 @@ obj-$(CONFIG_I2C_IMX_LPI2C) += i2c-imx-l - obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o - obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o - obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o -+obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o - obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o - obj-$(CONFIG_I2C_MESON) += i2c-meson.o - obj-$(CONFIG_I2C_MPC) += i2c-mpc.o ---- /dev/null -+++ b/drivers/i2c/busses/i2c-lantiq.c -@@ -0,0 +1,747 @@ -+ -+/* -+ * Lantiq I2C bus adapter -+ * -+ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * Copyright (C) 2012 Thomas Langer -+ */ -+ -+#include -+#include -+#include -+#include /* for kzalloc, kfree */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "i2c-lantiq.h" -+ -+/* -+ * CURRENT ISSUES: -+ * - no high speed support -+ * - ten bit mode is not tested (no slave devices) -+ */ -+ -+/* access macros */ -+#define i2c_r32(reg) \ -+ __raw_readl(&(priv->membase)->reg) -+#define i2c_w32(val, reg) \ -+ __raw_writel(val, &(priv->membase)->reg) -+#define i2c_w32_mask(clear, set, reg) \ -+ i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg) -+ -+#define DRV_NAME "i2c-lantiq" -+#define DRV_VERSION "1.00" -+ -+#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */ -+ -+#ifdef DEBUG -+#define LTQ_I2C_XFER_TIMEOUT (25*HZ) -+#else -+#define LTQ_I2C_XFER_TIMEOUT HZ -+#endif -+ -+#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ -+ I2C_IMSC_I2C_ERR_INT_EN) -+ -+#define LTQ_I2C_ARB_LOST (1 << 0) -+#define LTQ_I2C_NACK (1 << 1) -+#define LTQ_I2C_RX_UFL (1 << 2) -+#define LTQ_I2C_RX_OFL (1 << 3) -+#define LTQ_I2C_TX_UFL (1 << 4) -+#define LTQ_I2C_TX_OFL (1 << 5) -+ -+struct ltq_i2c { -+ struct mutex mutex; -+ -+ -+ /* active clock settings */ -+ unsigned int input_clock; /* clock input for i2c hardware block */ -+ unsigned int i2c_clock; /* approximated bus clock in kHz */ -+ -+ struct clk *clk_gate; -+ struct clk *clk_input; -+ -+ -+ /* resources (memory and interrupts) */ -+ int irq_lb; /* last burst irq */ -+ -+ struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */ -+ -+ struct i2c_adapter adap; -+ struct device *dev; -+ -+ struct completion cmd_complete; -+ -+ -+ /* message transfer data */ -+ struct i2c_msg *current_msg; /* current message */ -+ int msgs_num; /* number of messages to handle */ -+ u8 *msg_buf; /* current buffer */ -+ u32 msg_buf_len; /* remaining length of current buffer */ -+ int msg_err; /* error status of the current transfer */ -+ -+ -+ /* master status codes */ -+ enum { -+ STATUS_IDLE, -+ STATUS_ADDR, /* address phase */ -+ STATUS_WRITE, -+ STATUS_READ, -+ STATUS_READ_END, -+ STATUS_STOP -+ } status; -+}; -+ -+static irqreturn_t ltq_i2c_isr(int irq, void *dev_id); -+ -+static inline void enable_burst_irq(struct ltq_i2c *priv) -+{ -+ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); -+} -+static inline void disable_burst_irq(struct ltq_i2c *priv) -+{ -+ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); -+} -+ -+static void prepare_msg_send_addr(struct ltq_i2c *priv) -+{ -+ struct i2c_msg *msg = priv->current_msg; -+ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */ -+ u16 addr = msg->addr; -+ -+ /* new i2c_msg */ -+ priv->msg_buf = msg->buf; -+ priv->msg_buf_len = msg->len; -+ if (rd) -+ priv->status = STATUS_READ; -+ else -+ priv->status = STATUS_WRITE; -+ -+ /* send slave address */ -+ if (msg->flags & I2C_M_TEN) { -+ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); -+ i2c_w32(addr & 0xff, txd); -+ } else { -+ i2c_w32((addr & 0x7f) << 1 | rd, txd); -+ } -+} -+ -+static void ltq_i2c_set_tx_len(struct ltq_i2c *priv) -+{ -+ struct i2c_msg *msg = priv->current_msg; -+ int len = (msg->flags & I2C_M_TEN) ? 2 : 1; -+ -+ pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T'); -+ -+ priv->status = STATUS_ADDR; -+ -+ if (!(msg->flags & I2C_M_RD)) -+ len += msg->len; -+ else -+ /* set maximum received packet size (before rx int!) */ -+ i2c_w32(msg->len, mrps_ctrl); -+ i2c_w32(len, tps_ctrl); -+ enable_burst_irq(priv); -+} -+ -+static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap) -+{ -+ struct ltq_i2c *priv = i2c_get_adapdata(adap); -+ unsigned int input_clock = clk_get_rate(priv->clk_input); -+ u32 dec, inc = 1; -+ -+ /* clock changed? */ -+ if (priv->input_clock == input_clock) -+ return 0; -+ -+ /* -+ * this formula is only an approximation, found by the recommended -+ * values in the "I2C Architecture Specification 1.7.1" -+ */ -+ dec = input_clock / (priv->i2c_clock * 2); -+ if (dec <= 6) -+ return -ENXIO; -+ -+ i2c_w32(0, fdiv_high_cfg); -+ i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) | -+ (dec << I2C_FDIV_CFG_DEC_OFFSET), -+ fdiv_cfg); -+ -+ dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n", -+ input_clock, priv->i2c_clock, dec); -+ -+ priv->input_clock = input_clock; -+ return 0; -+} -+ -+static int ltq_i2c_hw_init(struct i2c_adapter *adap) -+{ -+ int ret = 0; -+ struct ltq_i2c *priv = i2c_get_adapdata(adap); -+ -+ /* disable bus */ -+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); -+ -+#ifndef DEBUG -+ /* set normal operation clock divider */ -+ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); -+#else -+ /* for debugging a higher divider value! */ -+ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); -+#endif -+ -+ /* setup clock */ -+ ret = ltq_i2c_hw_set_clock(adap); -+ if (ret != 0) { -+ dev_warn(priv->dev, "invalid clock settings\n"); -+ return ret; -+ } -+ -+ /* configure fifo */ -+ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ -+ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ -+ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ -+ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ -+ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ -+ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ -+ fifo_cfg); -+ -+ /* configure address */ -+ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in -+ the fifo */ -+ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ -+ I2C_ADDR_CFG_MnS_EN | /* we are master device */ -+ 0, /* our slave address (not used!) */ -+ addr_cfg); -+ -+ /* enable bus */ -+ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); -+ -+ return 0; -+} -+ -+static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv) -+{ -+ unsigned long timeout; -+ -+ timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT); -+ -+ do { -+ u32 stat = i2c_r32(bus_stat); -+ -+ if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE) -+ return 0; -+ -+ cond_resched(); -+ } while (!time_after_eq(jiffies, timeout)); -+ -+ dev_err(priv->dev, "timeout waiting for bus ready\n"); -+ return -ETIMEDOUT; -+} -+ -+static void ltq_i2c_tx(struct ltq_i2c *priv, int last) -+{ -+ if (priv->msg_buf_len && priv->msg_buf) { -+ i2c_w32(*priv->msg_buf, txd); -+ -+ if (--priv->msg_buf_len) -+ priv->msg_buf++; -+ else -+ priv->msg_buf = NULL; -+ } else { -+ last = 1; -+ } -+ -+ if (last) -+ disable_burst_irq(priv); -+} -+ -+static void ltq_i2c_rx(struct ltq_i2c *priv, int last) -+{ -+ u32 fifo_stat, timeout; -+ if (priv->msg_buf_len && priv->msg_buf) { -+ timeout = 5000000; -+ do { -+ fifo_stat = i2c_r32(ffs_stat); -+ } while (!fifo_stat && --timeout); -+ if (!timeout) { -+ last = 1; -+ pr_debug("\nrx timeout\n"); -+ goto err; -+ } -+ while (fifo_stat) { -+ *priv->msg_buf = i2c_r32(rxd); -+ if (--priv->msg_buf_len) { -+ priv->msg_buf++; -+ } else { -+ priv->msg_buf = NULL; -+ last = 1; -+ break; -+ } -+ /* -+ * do not read more than burst size, otherwise no "last -+ * burst" is generated and the transaction is blocked! -+ */ -+ fifo_stat = 0; -+ } -+ } else { -+ last = 1; -+ } -+err: -+ if (last) { -+ disable_burst_irq(priv); -+ -+ if (priv->status == STATUS_READ_END) { -+ /* -+ * do the STATUS_STOP and complete() here, as sometimes -+ * the tx_end is already seen before this is finished -+ */ -+ priv->status = STATUS_STOP; -+ complete(&priv->cmd_complete); -+ } else { -+ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); -+ priv->status = STATUS_READ_END; -+ } -+ } -+} -+ -+static void ltq_i2c_xfer_init(struct ltq_i2c *priv) -+{ -+ /* enable interrupts */ -+ i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc); -+ -+ /* trigger transfer of first msg */ -+ ltq_i2c_set_tx_len(priv); -+} -+ -+static void dump_msgs(struct i2c_msg msgs[], int num, int rx) -+{ -+#if defined(DEBUG) -+ int i, j; -+ pr_debug("Messages %d %s\n", num, rx ? "out" : "in"); -+ for (i = 0; i < num; i++) { -+ pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i, -+ (msgs[i].flags & I2C_M_RD) ? 'R' : 'T', -+ msgs[i].len, msgs[i].addr); -+ if (!(msgs[i].flags & I2C_M_RD) || rx) { -+ for (j = 0; j < msgs[i].len; j++) -+ pr_debug("%02X ", msgs[i].buf[j]); -+ } -+ pr_debug("\n"); -+ } -+#endif -+} -+ -+static void ltq_i2c_release_bus(struct ltq_i2c *priv) -+{ -+ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) -+ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); -+} -+ -+static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], -+ int num) -+{ -+ struct ltq_i2c *priv = i2c_get_adapdata(adap); -+ int ret; -+ -+ dev_dbg(priv->dev, "xfer %u messages\n", num); -+ dump_msgs(msgs, num, 0); -+ -+ mutex_lock(&priv->mutex); -+ -+ init_completion(&priv->cmd_complete); -+ priv->current_msg = msgs; -+ priv->msgs_num = num; -+ priv->msg_err = 0; -+ priv->status = STATUS_IDLE; -+ -+ /* wait for the bus to become ready */ -+ ret = ltq_i2c_wait_bus_not_busy(priv); -+ if (ret) -+ goto done; -+ -+ while (priv->msgs_num) { -+ /* start the transfers */ -+ ltq_i2c_xfer_init(priv); -+ -+ /* wait for transfers to complete */ -+ ret = wait_for_completion_interruptible_timeout( -+ &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT); -+ if (ret == 0) { -+ dev_err(priv->dev, "controller timed out\n"); -+ ltq_i2c_hw_init(adap); -+ ret = -ETIMEDOUT; -+ goto done; -+ } else if (ret < 0) -+ goto done; -+ -+ if (priv->msg_err) { -+ if (priv->msg_err & LTQ_I2C_NACK) -+ ret = -ENXIO; -+ else -+ ret = -EREMOTEIO; -+ goto done; -+ } -+ if (--priv->msgs_num) -+ priv->current_msg++; -+ } -+ /* no error? */ -+ ret = num; -+ -+done: -+ ltq_i2c_release_bus(priv); -+ -+ mutex_unlock(&priv->mutex); -+ -+ if (ret >= 0) -+ dump_msgs(msgs, num, 1); -+ -+ pr_debug("XFER ret %d\n", ret); -+ return ret; -+} -+ -+static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id) -+{ -+ struct ltq_i2c *priv = dev_id; -+ struct i2c_msg *msg = priv->current_msg; -+ int last = (irq == priv->irq_lb); -+ -+ if (last) -+ pr_debug("LB "); -+ else -+ pr_debug("B "); -+ -+ if (msg->flags & I2C_M_RD) { -+ switch (priv->status) { -+ case STATUS_ADDR: -+ pr_debug("X"); -+ prepare_msg_send_addr(priv); -+ disable_burst_irq(priv); -+ break; -+ case STATUS_READ: -+ case STATUS_READ_END: -+ pr_debug("R"); -+ ltq_i2c_rx(priv, last); -+ break; -+ default: -+ disable_burst_irq(priv); -+ pr_warn("Status R %d\n", priv->status); -+ break; -+ } -+ } else { -+ switch (priv->status) { -+ case STATUS_ADDR: -+ pr_debug("x"); -+ prepare_msg_send_addr(priv); -+ break; -+ case STATUS_WRITE: -+ pr_debug("w"); -+ ltq_i2c_tx(priv, last); -+ break; -+ default: -+ disable_burst_irq(priv); -+ pr_warn("Status W %d\n", priv->status); -+ break; -+ } -+ } -+ -+ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); -+ return IRQ_HANDLED; -+} -+ -+static void ltq_i2c_isr_prot(struct ltq_i2c *priv) -+{ -+ u32 i_pro = i2c_r32(p_irqss); -+ -+ pr_debug("i2c-p"); -+ -+ /* not acknowledge */ -+ if (i_pro & I2C_P_IRQSS_NACK) { -+ priv->msg_err |= LTQ_I2C_NACK; -+ pr_debug(" nack"); -+ } -+ -+ /* arbitration lost */ -+ if (i_pro & I2C_P_IRQSS_AL) { -+ priv->msg_err |= LTQ_I2C_ARB_LOST; -+ pr_debug(" arb-lost"); -+ } -+ /* tx -> rx switch */ -+ if (i_pro & I2C_P_IRQSS_RX) -+ pr_debug(" rx"); -+ -+ /* tx end */ -+ if (i_pro & I2C_P_IRQSS_TX_END) -+ pr_debug(" txend"); -+ pr_debug("\n"); -+ -+ if (!priv->msg_err) { -+ /* tx -> rx switch */ -+ if (i_pro & I2C_P_IRQSS_RX) { -+ priv->status = STATUS_READ; -+ enable_burst_irq(priv); -+ } -+ if (i_pro & I2C_P_IRQSS_TX_END) { -+ if (priv->status == STATUS_READ) -+ priv->status = STATUS_READ_END; -+ else { -+ disable_burst_irq(priv); -+ priv->status = STATUS_STOP; -+ } -+ } -+ } -+ -+ i2c_w32(i_pro, p_irqsc); -+} -+ -+static irqreturn_t ltq_i2c_isr(int irq, void *dev_id) -+{ -+ u32 i_raw, i_err = 0; -+ struct ltq_i2c *priv = dev_id; -+ -+ i_raw = i2c_r32(mis); -+ pr_debug("i_raw 0x%08X\n", i_raw); -+ -+ /* error interrupt */ -+ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { -+ i_err = i2c_r32(err_irqss); -+ pr_debug("i_err 0x%08X bus_stat 0x%04X\n", -+ i_err, i2c_r32(bus_stat)); -+ -+ /* tx fifo overflow (8) */ -+ if (i_err & I2C_ERR_IRQSS_TXF_OFL) -+ priv->msg_err |= LTQ_I2C_TX_OFL; -+ -+ /* tx fifo underflow (4) */ -+ if (i_err & I2C_ERR_IRQSS_TXF_UFL) -+ priv->msg_err |= LTQ_I2C_TX_UFL; -+ -+ /* rx fifo overflow (2) */ -+ if (i_err & I2C_ERR_IRQSS_RXF_OFL) -+ priv->msg_err |= LTQ_I2C_RX_OFL; -+ -+ /* rx fifo underflow (1) */ -+ if (i_err & I2C_ERR_IRQSS_RXF_UFL) -+ priv->msg_err |= LTQ_I2C_RX_UFL; -+ -+ i2c_w32(i_err, err_irqsc); -+ } -+ -+ /* protocol interrupt */ -+ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) -+ ltq_i2c_isr_prot(priv); -+ -+ if ((priv->msg_err) || (priv->status == STATUS_STOP)) -+ complete(&priv->cmd_complete); -+ -+ return IRQ_HANDLED; -+} -+ -+static u32 ltq_i2c_functionality(struct i2c_adapter *adap) -+{ -+ return I2C_FUNC_I2C | -+ I2C_FUNC_10BIT_ADDR | -+ I2C_FUNC_SMBUS_EMUL; -+} -+ -+static struct i2c_algorithm ltq_i2c_algorithm = { -+ .master_xfer = ltq_i2c_xfer, -+ .functionality = ltq_i2c_functionality, -+}; -+ -+static int ltq_i2c_probe(struct platform_device *pdev) -+{ -+ struct device_node *node = pdev->dev.of_node; -+ struct ltq_i2c *priv; -+ struct i2c_adapter *adap; -+ struct resource *mmres, irqres[4]; -+ int ret = 0; -+ -+ dev_dbg(&pdev->dev, "probing\n"); -+ -+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ ret = of_irq_to_resource_table(node, irqres, 4); -+ if (!mmres || (ret != 4)) { -+ dev_err(&pdev->dev, "no resources\n"); -+ return -ENODEV; -+ } -+ -+ /* allocate private data */ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) { -+ dev_err(&pdev->dev, "can't allocate private data\n"); -+ return -ENOMEM; -+ } -+ -+ adap = &priv->adap; -+ i2c_set_adapdata(adap, priv); -+ adap->owner = THIS_MODULE; -+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; -+ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); -+ adap->algo = <q_i2c_algorithm; -+ adap->dev.parent = &pdev->dev; -+ adap->dev.of_node = pdev->dev.of_node; -+ -+ if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) { -+ dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n"); -+ priv->i2c_clock = 100000; -+ } -+ -+ init_completion(&priv->cmd_complete); -+ mutex_init(&priv->mutex); -+ -+ priv->membase = devm_ioremap_resource(&pdev->dev, mmres); -+ if (IS_ERR(priv->membase)) -+ return PTR_ERR(priv->membase); -+ -+ priv->dev = &pdev->dev; -+ priv->irq_lb = irqres[0].start; -+ -+ ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst, -+ 0x0, "i2c lb", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", -+ irqres[0].start); -+ return -ENODEV; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst, -+ 0x0, "i2c b", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get burst IRQ %d\n", -+ irqres[1].start); -+ return -ENODEV; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr, -+ 0x0, "i2c err", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get error IRQ %d\n", -+ irqres[2].start); -+ return -ENODEV; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr, -+ 0x0, "i2c p", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", -+ irqres[3].start); -+ return -ENODEV; -+ } -+ -+ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); -+ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start, -+ irqres[1].start, irqres[2].start, irqres[3].start); -+ -+ priv->clk_gate = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(priv->clk_gate)) { -+ dev_err(&pdev->dev, "failed to get i2c clk\n"); -+ return -ENOENT; -+ } -+ -+ /* this is a static clock, which has no refcounting */ -+ priv->clk_input = clk_get_fpi(); -+ if (IS_ERR(priv->clk_input)) { -+ dev_err(&pdev->dev, "failed to get fpi clk\n"); -+ return -ENOENT; -+ } -+ -+ clk_activate(priv->clk_gate); -+ -+ /* add our adapter to the i2c stack */ -+ ret = i2c_add_numbered_adapter(adap); -+ if (ret) { -+ dev_err(&pdev->dev, "can't register I2C adapter\n"); -+ goto out; -+ } -+ -+ platform_set_drvdata(pdev, priv); -+ i2c_set_adapdata(adap, priv); -+ -+ /* print module version information */ -+ dev_dbg(&pdev->dev, "module id=%u revision=%u\n", -+ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, -+ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); -+ -+ /* initialize HW */ -+ ret = ltq_i2c_hw_init(adap); -+ if (ret) { -+ dev_err(&pdev->dev, "can't configure adapter\n"); -+ i2c_del_adapter(adap); -+ platform_set_drvdata(pdev, NULL); -+ goto out; -+ } else { -+ dev_info(&pdev->dev, "version %s\n", DRV_VERSION); -+ } -+ -+out: -+ /* if init failed, we need to deactivate the clock gate */ -+ if (ret) -+ clk_deactivate(priv->clk_gate); -+ -+ return ret; -+} -+ -+static int ltq_i2c_remove(struct platform_device *pdev) -+{ -+ struct ltq_i2c *priv = platform_get_drvdata(pdev); -+ -+ /* disable bus */ -+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); -+ -+ /* power down the core */ -+ clk_deactivate(priv->clk_gate); -+ -+ /* remove driver */ -+ i2c_del_adapter(&priv->adap); -+ kfree(priv); -+ -+ dev_dbg(&pdev->dev, "removed\n"); -+ platform_set_drvdata(pdev, NULL); -+ -+ return 0; -+} -+static const struct of_device_id ltq_i2c_match[] = { -+ { .compatible = "lantiq,lantiq-i2c" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ltq_i2c_match); -+ -+static struct platform_driver ltq_i2c_driver = { -+ .probe = ltq_i2c_probe, -+ .remove = ltq_i2c_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = ltq_i2c_match, -+ }, -+}; -+ -+module_platform_driver(ltq_i2c_driver); -+ -+MODULE_DESCRIPTION("Lantiq I2C bus adapter"); -+MODULE_AUTHOR("Thomas Langer "); -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION(DRV_VERSION); ---- /dev/null -+++ b/drivers/i2c/busses/i2c-lantiq.h -@@ -0,0 +1,234 @@ -+#ifndef I2C_LANTIQ_H -+#define I2C_LANTIQ_H -+ -+/* I2C register structure */ -+struct lantiq_reg_i2c { -+ /* I2C Kernel Clock Control Register */ -+ unsigned int clc; /* 0x00000000 */ -+ /* Reserved */ -+ unsigned int res_0; /* 0x00000004 */ -+ /* I2C Identification Register */ -+ unsigned int id; /* 0x00000008 */ -+ /* Reserved */ -+ unsigned int res_1; /* 0x0000000C */ -+ /* -+ * I2C RUN Control Register -+ * This register enables and disables the I2C peripheral. Before -+ * enabling, the I2C has to be configured properly. After enabling -+ * no configuration is possible -+ */ -+ unsigned int run_ctrl; /* 0x00000010 */ -+ /* -+ * I2C End Data Control Register -+ * This register is used to either turn around the data transmission -+ * direction or to address another slave without sending a stop -+ * condition. Also the software can stop the slave-transmitter by -+ * sending a not-accolade when working as master-receiver or even -+ * stop data transmission immediately when operating as -+ * master-transmitter. The writing to the bits of this control -+ * register is only effective when in MASTER RECEIVES BYTES, MASTER -+ * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state -+ */ -+ unsigned int endd_ctrl; /* 0x00000014 */ -+ /* -+ * I2C Fractional Divider Configuration Register -+ * These register is used to program the fractional divider of the I2C -+ * bus. Before the peripheral is switched on by setting the RUN-bit the -+ * two (fixed) values for the two operating frequencies are programmed -+ * into these (configuration) registers. The Register FDIV_HIGH_CFG has -+ * the same layout as I2C_FDIV_CFG. -+ */ -+ unsigned int fdiv_cfg; /* 0x00000018 */ -+ /* -+ * I2C Fractional Divider (highspeed mode) Configuration Register -+ * These register is used to program the fractional divider of the I2C -+ * bus. Before the peripheral is switched on by setting the RUN-bit the -+ * two (fixed) values for the two operating frequencies are programmed -+ * into these (configuration) registers. The Register FDIV_CFG has the -+ * same layout as I2C_FDIV_CFG. -+ */ -+ unsigned int fdiv_high_cfg; /* 0x0000001C */ -+ /* I2C Address Configuration Register */ -+ unsigned int addr_cfg; /* 0x00000020 */ -+ /* I2C Bus Status Register -+ * This register gives a status information of the I2C. This additional -+ * information can be used by the software to start proper actions. -+ */ -+ unsigned int bus_stat; /* 0x00000024 */ -+ /* I2C FIFO Configuration Register */ -+ unsigned int fifo_cfg; /* 0x00000028 */ -+ /* I2C Maximum Received Packet Size Register */ -+ unsigned int mrps_ctrl; /* 0x0000002C */ -+ /* I2C Received Packet Size Status Register */ -+ unsigned int rps_stat; /* 0x00000030 */ -+ /* I2C Transmit Packet Size Register */ -+ unsigned int tps_ctrl; /* 0x00000034 */ -+ /* I2C Filled FIFO Stages Status Register */ -+ unsigned int ffs_stat; /* 0x00000038 */ -+ /* Reserved */ -+ unsigned int res_2; /* 0x0000003C */ -+ /* I2C Timing Configuration Register */ -+ unsigned int tim_cfg; /* 0x00000040 */ -+ /* Reserved */ -+ unsigned int res_3[7]; /* 0x00000044 */ -+ /* I2C Error Interrupt Request Source Mask Register */ -+ unsigned int err_irqsm; /* 0x00000060 */ -+ /* I2C Error Interrupt Request Source Status Register */ -+ unsigned int err_irqss; /* 0x00000064 */ -+ /* I2C Error Interrupt Request Source Clear Register */ -+ unsigned int err_irqsc; /* 0x00000068 */ -+ /* Reserved */ -+ unsigned int res_4; /* 0x0000006C */ -+ /* I2C Protocol Interrupt Request Source Mask Register */ -+ unsigned int p_irqsm; /* 0x00000070 */ -+ /* I2C Protocol Interrupt Request Source Status Register */ -+ unsigned int p_irqss; /* 0x00000074 */ -+ /* I2C Protocol Interrupt Request Source Clear Register */ -+ unsigned int p_irqsc; /* 0x00000078 */ -+ /* Reserved */ -+ unsigned int res_5; /* 0x0000007C */ -+ /* I2C Raw Interrupt Status Register */ -+ unsigned int ris; /* 0x00000080 */ -+ /* I2C Interrupt Mask Control Register */ -+ unsigned int imsc; /* 0x00000084 */ -+ /* I2C Masked Interrupt Status Register */ -+ unsigned int mis; /* 0x00000088 */ -+ /* I2C Interrupt Clear Register */ -+ unsigned int icr; /* 0x0000008C */ -+ /* I2C Interrupt Set Register */ -+ unsigned int isr; /* 0x00000090 */ -+ /* I2C DMA Enable Register */ -+ unsigned int dmae; /* 0x00000094 */ -+ /* Reserved */ -+ unsigned int res_6[8154]; /* 0x00000098 */ -+ /* I2C Transmit Data Register */ -+ unsigned int txd; /* 0x00008000 */ -+ /* Reserved */ -+ unsigned int res_7[4095]; /* 0x00008004 */ -+ /* I2C Receive Data Register */ -+ unsigned int rxd; /* 0x0000C000 */ -+ /* Reserved */ -+ unsigned int res_8[4095]; /* 0x0000C004 */ -+}; -+ -+/* -+ * Clock Divider for Normal Run Mode -+ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long -+ * as the new divider value RMC is not valid, the register returns 0x0000 00xx -+ * on reading. -+ */ -+#define I2C_CLC_RMC_MASK 0x0000FF00 -+/* field offset */ -+#define I2C_CLC_RMC_OFFSET 8 -+ -+/* Fields of "I2C Identification Register" */ -+/* Module ID */ -+#define I2C_ID_ID_MASK 0x0000FF00 -+/* field offset */ -+#define I2C_ID_ID_OFFSET 8 -+/* Revision */ -+#define I2C_ID_REV_MASK 0x000000FF -+/* field offset */ -+#define I2C_ID_REV_OFFSET 0 -+ -+/* Fields of "I2C Interrupt Mask Control Register" */ -+/* Enable */ -+#define I2C_IMSC_BREQ_INT_EN 0x00000008 -+/* Enable */ -+#define I2C_IMSC_LBREQ_INT_EN 0x00000004 -+ -+/* Fields of "I2C Fractional Divider Configuration Register" */ -+/* field offset */ -+#define I2C_FDIV_CFG_INC_OFFSET 16 -+ -+/* Fields of "I2C Interrupt Mask Control Register" */ -+/* Enable */ -+#define I2C_IMSC_I2C_P_INT_EN 0x00000020 -+/* Enable */ -+#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 -+ -+/* Fields of "I2C Error Interrupt Request Source Status Register" */ -+/* TXF_OFL */ -+#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 -+/* TXF_UFL */ -+#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 -+/* RXF_OFL */ -+#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 -+/* RXF_UFL */ -+#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 -+ -+/* Fields of "I2C Raw Interrupt Status Register" */ -+/* Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 -+/* Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 -+ -+/* Fields of "I2C FIFO Configuration Register" */ -+/* TX FIFO Flow Control */ -+#define I2C_FIFO_CFG_TXFC 0x00020000 -+/* RX FIFO Flow Control */ -+#define I2C_FIFO_CFG_RXFC 0x00010000 -+/* Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 -+/* Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 -+/* 1 word */ -+#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 -+ -+/* Fields of "I2C FIFO Configuration Register" */ -+/* 1 word */ -+#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 -+/* Stop on Packet End Enable */ -+#define I2C_ADDR_CFG_SOPE_EN 0x00200000 -+/* Stop on Not Acknowledge Enable */ -+#define I2C_ADDR_CFG_SONA_EN 0x00100000 -+/* Enable */ -+#define I2C_ADDR_CFG_MnS_EN 0x00080000 -+ -+/* Fields of "I2C Interrupt Clear Register" */ -+/* Clear */ -+#define I2C_ICR_BREQ_INT_CLR 0x00000008 -+/* Clear */ -+#define I2C_ICR_LBREQ_INT_CLR 0x00000004 -+ -+/* Fields of "I2C Fractional Divider Configuration Register" */ -+/* field offset */ -+#define I2C_FDIV_CFG_DEC_OFFSET 0 -+ -+/* Fields of "I2C Bus Status Register" */ -+/* Bus Status */ -+#define I2C_BUS_STAT_BS_MASK 0x00000003 -+/* Read from I2C Bus. */ -+#define I2C_BUS_STAT_RNW_READ 0x00000004 -+/* I2C Bus is free. */ -+#define I2C_BUS_STAT_BS_FREE 0x00000000 -+/* -+ * The device is working as master and has claimed the control on the -+ * I2C-bus (busy master). -+ */ -+#define I2C_BUS_STAT_BS_BM 0x00000002 -+ -+/* Fields of "I2C RUN Control Register" */ -+/* Enable */ -+#define I2C_RUN_CTRL_RUN_EN 0x00000001 -+ -+/* Fields of "I2C End Data Control Register" */ -+/* -+ * Set End of Transmission -+ * Note:Do not write '1' to this bit when bus is free. This will cause an -+ * abort after the first byte when a new transfer is started. -+ */ -+#define I2C_ENDD_CTRL_SETEND 0x00000002 -+ -+/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ -+/* NACK */ -+#define I2C_P_IRQSS_NACK 0x00000010 -+/* AL */ -+#define I2C_P_IRQSS_AL 0x00000008 -+/* RX */ -+#define I2C_P_IRQSS_RX 0x00000040 -+/* TX_END */ -+#define I2C_P_IRQSS_TX_END 0x00000020 -+ -+ -+#endif /* I2C_LANTIQ_H */ diff --git a/target/linux/lantiq/patches-4.19/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-4.19/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch deleted file mode 100644 index a382b9117c..0000000000 --- a/target/linux/lantiq/patches-4.19/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch +++ /dev/null @@ -1,218 +0,0 @@ -From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 10 Sep 2014 22:42:14 +0200 -Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling - -Signed-off-by: John Crispin ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + - arch/mips/lantiq/xway/Makefile | 3 + - arch/mips/lantiq/xway/ath5k_eep.c | 136 +++++++++++++++++++++ - arch/mips/lantiq/xway/eth_mac.c | 25 ++++ - drivers/net/ethernet/lantiq_etop.c | 6 +- - 5 files changed, 172 insertions(+), 1 deletion(-) - create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c - create mode 100644 arch/mips/lantiq/xway/eth_mac.c - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -104,5 +104,8 @@ int xrx200_gphy_boot(struct device *dev, - extern void ltq_pmu_enable(unsigned int module); - extern void ltq_pmu_disable(unsigned int module); - -+/* allow the ethernet driver to load a flash mapped mac addr */ -+const u8* ltq_get_eth_mac(void); -+ - #endif /* CONFIG_SOC_TYPE_XWAY */ - #endif /* _LTQ_XWAY_H__ */ ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -7,3 +7,6 @@ obj-y += timer.o - endif - - obj-y += vmmc.o -+ -+obj-y += eth_mac.o -+obj-$(CONFIG_PCI) += ath5k_eep.o ---- /dev/null -+++ b/arch/mips/lantiq/xway/ath5k_eep.c -@@ -0,0 +1,136 @@ -+/* -+ * Copyright (C) 2011 Luca Olivetti -+ * Copyright (C) 2011 John Crispin -+ * Copyright (C) 2011 Andrej Vlašić -+ * Copyright (C) 2013 Álvaro Fernández Rojas -+ * Copyright (C) 2013 Daniel Gimpelevich -+ * Copyright (C) 2015 Vittorio Gambaletta -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); -+struct ath5k_platform_data ath5k_pdata; -+static u8 athxk_eeprom_mac[6]; -+ -+static int ath5k_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ dev->dev.platform_data = &ath5k_pdata; -+ return 0; -+} -+ -+static int ath5k_eep_load; -+int __init of_ath5k_eeprom_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node, *mtd_np = NULL; -+ int mac_offset; -+ u32 mac_inc = 0; -+ int i; -+ struct mtd_info *the_mtd; -+ size_t flash_readlen; -+ const __be32 *list; -+ const char *part; -+ phandle phandle; -+ -+ list = of_get_property(np, "ath,eep-flash", &i); -+ if (!list || (i != (2 * sizeof(*list)))) -+ return -ENODEV; -+ -+ phandle = be32_to_cpup(list++); -+ if (phandle) -+ mtd_np = of_find_node_by_phandle(phandle); -+ -+ if (!mtd_np) -+ return -ENODEV; -+ -+ part = of_get_property(mtd_np, "label", NULL); -+ if (!part) -+ part = mtd_np->name; -+ -+ the_mtd = get_mtd_device_nm(part); -+ if (IS_ERR(the_mtd)) -+ return -ENODEV; -+ -+ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL); -+ -+ i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1, -+ &flash_readlen, (void *) ath5k_pdata.eeprom_data); -+ -+ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) { -+ size_t mac_readlen; -+ mtd_read(the_mtd, mac_offset, 6, &mac_readlen, -+ (void *) athxk_eeprom_mac); -+ } -+ put_mtd_device(the_mtd); -+ -+ if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) { -+ dev_err(&pdev->dev, "failed to load eeprom from mtd\n"); -+ return -ENODEV; -+ } -+ -+ if (of_find_property(np, "ath,eep-swap", NULL)) -+ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++) -+ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]); -+ -+ if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac()) -+ ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac()); -+ -+ if (!is_valid_ether_addr(athxk_eeprom_mac)) { -+ dev_warn(&pdev->dev, "using random mac\n"); -+ random_ether_addr(athxk_eeprom_mac); -+ } -+ -+ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc)) -+ athxk_eeprom_mac[5] += mac_inc; -+ -+ ath5k_pdata.macaddr = athxk_eeprom_mac; -+ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init; -+ -+ dev_info(&pdev->dev, "loaded ath5k eeprom\n"); -+ -+ return 0; -+} -+ -+static struct of_device_id ath5k_eeprom_ids[] = { -+ { .compatible = "ath5k,eeprom" }, -+ { } -+}; -+ -+static struct platform_driver ath5k_eeprom_driver = { -+ .driver = { -+ .name = "ath5k,eeprom", -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(ath5k_eeprom_ids), -+ }, -+}; -+ -+static int __init of_ath5k_eeprom_init(void) -+{ -+ int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); -+ -+ if (ret) -+ ath5k_eep_load = 1; -+ -+ return ret; -+} -+ -+static int __init of_ath5k_eeprom_init_late(void) -+{ -+ if (!ath5k_eep_load) -+ return 0; -+ -+ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); -+} -+late_initcall(of_ath5k_eeprom_init_late); -+subsys_initcall(of_ath5k_eeprom_init); ---- /dev/null -+++ b/arch/mips/lantiq/xway/eth_mac.c -@@ -0,0 +1,25 @@ -+/* -+ * Copyright (C) 2012 John Crispin -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+static u8 eth_mac[6]; -+static int eth_mac_set; -+ -+const u8* ltq_get_eth_mac(void) -+{ -+ return eth_mac; -+} -+ -+static int __init setup_ethaddr(char *str) -+{ -+ eth_mac_set = mac_pton(str, eth_mac); -+ return !eth_mac_set; -+} -+early_param("ethaddr", setup_ethaddr); ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -780,7 +780,11 @@ ltq_etop_init(struct net_device *dev) - if (err) - goto err_hw; - -- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); -+ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN); -+ -+ if (priv->mac && !is_valid_ether_addr(mac.sa_data)) -+ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); -+ - if (!is_valid_ether_addr(mac.sa_data)) { - pr_warn("etop: invalid MAC, using random\n"); - eth_random_addr(mac.sa_data); diff --git a/target/linux/lantiq/patches-4.19/0042-arch-mips-increase-io_space_limit.patch b/target/linux/lantiq/patches-4.19/0042-arch-mips-increase-io_space_limit.patch deleted file mode 100644 index 7165dd0070..0000000000 --- a/target/linux/lantiq/patches-4.19/0042-arch-mips-increase-io_space_limit.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 3 Jun 2016 13:12:20 +0200 -Subject: [PATCH] arch: mips: increase io_space_limit - -this value comes from x86 and breaks some pci devices - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/io.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/include/asm/io.h -+++ b/arch/mips/include/asm/io.h -@@ -52,7 +52,7 @@ - - /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ - --#define IO_SPACE_LIMIT 0xffff -+#define IO_SPACE_LIMIT 0xffffffff - - /* - * On MIPS I/O ports are memory mapped, so we access them using normal diff --git a/target/linux/lantiq/patches-4.19/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch b/target/linux/lantiq/patches-4.19/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch deleted file mode 100644 index fed65e5321..0000000000 --- a/target/linux/lantiq/patches-4.19/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch +++ /dev/null @@ -1,78 +0,0 @@ -From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Fri, 6 Jan 2017 17:55:24 +0100 -Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs - -The size of the internal RAM of the DesignWare USB controller changed -between the different Lantiq SoCs. We have the following sizes: - -Amazon + Danube: 8 KByte -Amazon SE + arx100: 2 KByte -xrx200 + xrx300: 2.5 KByte - -For Danube SoC we do not provide the params and let the driver decide -to use sane defaults, for the Amazon SE and arx100 we use small fifos -and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo. -The auto detection of max_transfer_size and max_packet_count should -work, so remove it. - -Signed-off-by: Hauke Mehrtens ---- - drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++------- - 1 file changed, 39 insertions(+), 7 deletions(-) - ---- a/drivers/usb/dwc2/params.c -+++ b/drivers/usb/dwc2/params.c -@@ -91,7 +91,14 @@ static void dwc2_set_rk_params(struct dw - p->power_down = 0; - } - --static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) -+static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg) -+{ -+ struct dwc2_core_params *p = &hsotg->params; -+ -+ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; -+} -+ -+static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg) - { - struct dwc2_core_params *p = &hsotg->params; - -@@ -99,12 +106,20 @@ static void dwc2_set_ltq_params(struct d - p->host_rx_fifo_size = 288; - p->host_nperio_tx_fifo_size = 128; - p->host_perio_tx_fifo_size = 96; -- p->max_transfer_size = 65535; -- p->max_packet_count = 511; - p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << - GAHBCFG_HBSTLEN_SHIFT; - } - -+static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg) -+{ -+ struct dwc2_core_params *p = &hsotg->params; -+ -+ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; -+ p->host_rx_fifo_size = 288; -+ p->host_nperio_tx_fifo_size = 128; -+ p->host_perio_tx_fifo_size = 136; -+} -+ - static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) - { - struct dwc2_core_params *p = &hsotg->params; -@@ -156,8 +171,11 @@ const struct of_device_id dwc2_of_match_ - { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, - { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, - { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, -- { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, -- { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, -+ { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params }, -+ { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params }, -+ { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params }, -+ { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params }, -+ { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params }, - { .compatible = "snps,dwc2" }, - { .compatible = "samsung,s3c6400-hsotg", - .data = dwc2_set_s3c6400_params }, diff --git a/target/linux/lantiq/patches-4.19/0051-MIPS-lantiq-improve-USB-initialization.patch b/target/linux/lantiq/patches-4.19/0051-MIPS-lantiq-improve-USB-initialization.patch deleted file mode 100644 index a7bdafd704..0000000000 --- a/target/linux/lantiq/patches-4.19/0051-MIPS-lantiq-improve-USB-initialization.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Fri, 6 Jan 2017 17:40:12 +0100 -Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization - -This adds code to initialize the USB controller and PHY also on Danube, -Amazon SE and AR10. This code is based on the Vendor driver from -different UGW versions and compared to the hardware documentation. - -Signed-off-by: Hauke Mehrtens ---- - arch/mips/lantiq/xway/sysctrl.c | 20 +++++++ - 2 files changed, 110 insertions(+), 30 deletions(-) - - ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -246,6 +246,25 @@ static void pmu_disable(struct clk *clk) - pr_warn("deactivating PMU module failed!"); - } - -+static void usb_set_clock(void) -+{ -+ unsigned int val = ltq_cgu_r32(ifccr); -+ -+ if (of_machine_is_compatible("lantiq,ar10") || -+ of_machine_is_compatible("lantiq,grx390")) { -+ val &= ~0x03; /* XTAL divided by 3 */ -+ } else if (of_machine_is_compatible("lantiq,ar9") || -+ of_machine_is_compatible("lantiq,vr9")) { -+ /* TODO: this depends on the XTAL frequency */ -+ val |= 0x03; /* XTAL divided by 3 */ -+ } else if (of_machine_is_compatible("lantiq,ase")) { -+ val |= 0x20; /* from XTAL */ -+ } else if (of_machine_is_compatible("lantiq,danube")) { -+ val |= 0x30; /* 12 MHz, generated from 36 MHz */ -+ } -+ ltq_cgu_w32(val, ifccr); -+} -+ - /* the pci enable helper */ - static int pci_enable(struct clk *clk) - { -@@ -567,4 +586,5 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); - clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); - } -+ usb_set_clock(); - } diff --git a/target/linux/lantiq/patches-4.19/0101-find_active_root.patch b/target/linux/lantiq/patches-4.19/0101-find_active_root.patch deleted file mode 100644 index f48b5b7c65..0000000000 --- a/target/linux/lantiq/patches-4.19/0101-find_active_root.patch +++ /dev/null @@ -1,93 +0,0 @@ ---- a/drivers/mtd/ofpart.c -+++ b/drivers/mtd/ofpart.c -@@ -25,6 +25,38 @@ static bool node_has_compatible(struct d - return of_get_property(pp, "compatible", NULL); - } - -+static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master, -+ loff_t offset) -+{ -+ static uint8_t root_id; -+ int err, len; -+ -+ err = mtd_read(master, offset, 0x01, &len, &root_id); -+ -+ if (mtd_is_bitflip(err) || !err) -+ return &root_id; -+ -+ return NULL; -+} -+ -+static void brnboot_set_active_root_part(struct mtd_partition *pparts, -+ struct device_node **part_nodes, -+ int nr_parts, -+ uint8_t *root_id) -+{ -+ int i; -+ -+ for (i = 0; i < nr_parts; i++) { -+ int part_root_id; -+ -+ if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id) -+ && part_root_id == *root_id) { -+ pparts[i].name = "firmware"; -+ break; -+ } -+ } -+} -+ - static int parse_fixed_partitions(struct mtd_info *master, - const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) -@@ -36,7 +68,8 @@ static int parse_fixed_partitions(struct - struct device_node *pp; - int nr_parts, i, ret = 0; - bool dedicated = true; -- -+ uint8_t *proot_id = NULL; -+ struct device_node **part_nodes; - - /* Pull of_node from the master device node */ - mtd_node = mtd_get_of_node(master); -@@ -72,7 +105,9 @@ static int parse_fixed_partitions(struct - return 0; - - parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); -- if (!parts) -+ part_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL); -+ -+ if (!parts || !part_nodes) - return -ENOMEM; - - i = 0; -@@ -121,12 +156,22 @@ static int parse_fixed_partitions(struct - if (of_get_property(pp, "lock", &len)) - parts[i].mask_flags |= MTD_POWERUP_LOCK; - -+ if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector")) -+ proot_id = brnboot_get_selected_root_part(master, parts[i].offset); -+ -+ part_nodes[i] = pp; -+ - i++; - } - - if (!nr_parts) - goto ofpart_none; - -+ if (proot_id) -+ brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id); -+ -+ kfree(part_nodes); -+ - *pparts = parts; - return nr_parts; - -@@ -137,6 +182,7 @@ ofpart_fail: - ofpart_none: - of_node_put(pp); - kfree(parts); -+ kfree(part_nodes); - return ret; - } - diff --git a/target/linux/lantiq/patches-4.19/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-4.19/0151-lantiq-ifxmips_pcie-use-of.patch deleted file mode 100644 index b081871191..0000000000 --- a/target/linux/lantiq/patches-4.19/0151-lantiq-ifxmips_pcie-use-of.patch +++ /dev/null @@ -1,191 +0,0 @@ ---- a/arch/mips/pci/ifxmips_pcie.c -+++ b/arch/mips/pci/ifxmips_pcie.c -@@ -18,6 +18,9 @@ - #include - #include - -+#include -+#include -+ - #include "ifxmips_pcie.h" - #include "ifxmips_pcie_reg.h" - -@@ -40,6 +43,7 @@ - static DEFINE_SPINLOCK(ifx_pcie_lock); - - u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); -+static int pcie_reset_gpio; - - static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { - { -@@ -82,6 +86,22 @@ void ifx_pcie_debug(const char *fmt, ... - printk("%s", buf); - } - -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+ gpio_direction_output(pcie_reset_gpio, 1); -+ gpio_set_value(pcie_reset_gpio, 1); -+} -+ -+static inline void pcie_device_rst_assert(int pcie_port) -+{ -+ gpio_set_value(pcie_reset_gpio, 0); -+} -+ -+static inline void pcie_device_rst_deassert(int pcie_port) -+{ -+ mdelay(100); -+ gpio_direction_output(pcie_reset_gpio, 1); -+} - - static inline int pcie_ltssm_enable(int pcie_port) - { -@@ -1045,17 +1065,52 @@ pcie_rc_initialize(int pcie_port) - return 0; - } - --static int __init ifx_pcie_bios_init(void) -+static int ifx_pcie_bios_probe(struct platform_device *pdev) - { -+ struct device_node *node = pdev->dev.of_node; - void __iomem *io_map_base; - int pcie_port; - int startup_port; - -+ struct device_node *np; -+ struct pci_bus *bus; -+ -+ /* -+ * In case a PCI device is physical present, the Lantiq PCI driver need -+ * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them -+ * will work. -+ * -+ * In case the lantiq PCI driver is enabled in the device tree, check if -+ * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already -+ * registered. -+ * -+ * It will fail if there is another PCI controller, this controller is -+ * registered before the Lantiq PCIe driver is probe and the lantiq PCI -+ */ -+ np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway"); -+ -+ if (of_device_is_available(np)) { -+ bus = pci_find_next_bus(bus); -+ -+ if (!bus) -+ return -EPROBE_DEFER; -+ } -+ - /* Enable AHB Master/ Slave */ - pcie_ahb_pmu_setup(); - - startup_port = IFX_PCIE_PORT0; -- -+ -+ pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); -+ if (gpio_is_valid(pcie_reset_gpio)) { -+ int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset"); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio); -+ return ret; -+ } -+ gpio_direction_output(pcie_reset_gpio, 1); -+ } -+ - for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ - if (pcie_rc_initialize(pcie_port) == 0) { - IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", -@@ -1067,6 +1122,7 @@ static int __init ifx_pcie_bios_init(voi - return -ENOMEM; - } - ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; -+ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node); - - register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); - /* XXX, clear error status */ -@@ -1083,6 +1139,30 @@ static int __init ifx_pcie_bios_init(voi - - return 0; - } -+ -+static const struct of_device_id ifxmips_pcie_match[] = { -+ { .compatible = "lantiq,pcie-xrx200" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ifxmips_pcie_match); -+ -+static struct platform_driver ltq_pci_driver = { -+ .probe = ifx_pcie_bios_probe, -+ .driver = { -+ .name = "pcie-xrx200", -+ .owner = THIS_MODULE, -+ .of_match_table = ifxmips_pcie_match, -+ }, -+}; -+ -+int __init ifx_pcie_bios_init(void) -+{ -+ int ret = platform_driver_register(<q_pci_driver); -+ if (ret) -+ pr_info("pcie-xrx200: Error registering platform driver!"); -+ return ret; -+} -+ - arch_initcall(ifx_pcie_bios_init); - - MODULE_LICENSE("GPL"); ---- a/arch/mips/pci/ifxmips_pcie_vr9.h -+++ b/arch/mips/pci/ifxmips_pcie_vr9.h -@@ -22,8 +22,6 @@ - #include - #include - --#define IFX_PCIE_GPIO_RESET 494 -- - #define IFX_REG_R32 ltq_r32 - #define IFX_REG_W32 ltq_w32 - #define CONFIG_IFX_PCIE_HW_SWAP -@@ -53,21 +51,6 @@ - #define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) - - --static inline void pcie_ep_gpio_rst_init(int pcie_port) --{ -- -- gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); -- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); -- gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -- --/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ --} -- - static inline void pcie_ahb_pmu_setup(void) - { - /* Enable AHB bus master/slave */ -@@ -180,20 +163,6 @@ static inline void pcie_phy_rst_deassert - IFX_REG_W32(reg, IFX_RCU_RST_REQ); - } - --static inline void pcie_device_rst_assert(int pcie_port) --{ -- gpio_set_value(IFX_PCIE_GPIO_RESET, 0); --// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); --} -- --static inline void pcie_device_rst_deassert(int pcie_port) --{ -- mdelay(100); -- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); --// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -- //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); --} -- - static inline void pcie_core_pmu_setup(int pcie_port) - { - struct clk *clk; diff --git a/target/linux/lantiq/patches-4.19/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-4.19/0152-lantiq-VPE.patch deleted file mode 100644 index 9e39427c6a..0000000000 --- a/target/linux/lantiq/patches-4.19/0152-lantiq-VPE.patch +++ /dev/null @@ -1,180 +0,0 @@ ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -2318,6 +2318,12 @@ config MIPS_VPE_LOADER - Includes a loader for loading an elf relocatable object - onto another VPE and running it. - -+config IFX_VPE_EXT -+ bool "IFX APRP Extensions" -+ depends on MIPS_VPE_LOADER -+ help -+ IFX included extensions in APRP -+ - config MIPS_VPE_LOADER_CMP - bool - default "y" ---- a/arch/mips/include/asm/vpe.h -+++ b/arch/mips/include/asm/vpe.h -@@ -127,4 +127,13 @@ void cleanup_tc(struct tc *tc); - - int __init vpe_module_init(void); - void __exit vpe_module_exit(void); -+ -+/* For the explanation of the APIs please refer the section "MT APRP Kernel -+ * Programming" in AR9 SW Architecture Specification -+ */ -+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags); -+int32_t vpe1_sw_stop(uint32_t flags); -+uint32_t vpe1_get_load_addr(uint32_t flags); -+uint32_t vpe1_get_max_mem(uint32_t flags); -+ - #endif /* _ASM_VPE_H */ ---- a/arch/mips/kernel/vpe-mt.c -+++ b/arch/mips/kernel/vpe-mt.c -@@ -29,6 +29,7 @@ int vpe_run(struct vpe *v) - struct vpe_notifications *notifier; - unsigned int vpeflags; - struct tc *t; -+ unsigned long physical_memsize = 0L; - - /* check we are the Master VPE */ - local_irq_save(flags); -@@ -417,6 +418,8 @@ int __init vpe_module_init(void) - } - - v->ntcs = hw_tcs - aprp_cpu_index(); -+ write_tc_c0_tcbind((read_tc_c0_tcbind() & -+ ~TCBIND_CURVPE) | 1); - - /* add the tc to the list of this vpe's tc's. */ - list_add(&t->tc, &v->tc); -@@ -519,3 +522,47 @@ void __exit vpe_module_exit(void) - release_vpe(v); - } - } -+ -+#ifdef CONFIG_IFX_VPE_EXT -+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags) -+{ -+ enum vpe_state state; -+ struct vpe *v = get_vpe(tclimit); -+ struct vpe_notifications *not; -+ -+ if (tcmask || flags) { -+ pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n"); -+ return -1; -+ } -+ -+ state = xchg(&v->state, VPE_STATE_INUSE); -+ if (state != VPE_STATE_UNUSED) { -+ vpe_stop(v); -+ -+ list_for_each_entry(not, &v->notify, list) { -+ not->stop(tclimit); -+ } -+ } -+ -+ v->__start = (unsigned long)sw_start_addr; -+ -+ if (!vpe_run(v)) { -+ pr_debug("VPE loader: VPE1 running successfully\n"); -+ return 0; -+ } -+ return -1; -+} -+EXPORT_SYMBOL(vpe1_sw_start); -+ -+int32_t vpe1_sw_stop(uint32_t flags) -+{ -+ struct vpe *v = get_vpe(tclimit); -+ -+ if (!vpe_free(v)) { -+ pr_debug("RP Stopped\n"); -+ return 0; -+ } else -+ return -1; -+} -+EXPORT_SYMBOL(vpe1_sw_stop); -+#endif ---- a/arch/mips/kernel/vpe.c -+++ b/arch/mips/kernel/vpe.c -@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = { - .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) - }; - -+#ifdef CONFIG_IFX_VPE_EXT -+unsigned int vpe1_load_addr; -+ -+static int __init load_address(char *str) -+{ -+ get_option(&str, &vpe1_load_addr); -+ return 1; -+} -+__setup("vpe1_load_addr=", load_address); -+ -+static unsigned int vpe1_mem; -+static int __init vpe1mem(char *str) -+{ -+ vpe1_mem = memparse(str, &str); -+ return 1; -+} -+__setup("vpe1_mem=", vpe1mem); -+ -+uint32_t vpe1_get_load_addr(uint32_t flags) -+{ -+ return vpe1_load_addr; -+} -+EXPORT_SYMBOL(vpe1_get_load_addr); -+ -+uint32_t vpe1_get_max_mem(uint32_t flags) -+{ -+ if (!vpe1_mem) -+ return P_SIZE; -+ else -+ return vpe1_mem; -+} -+EXPORT_SYMBOL(vpe1_get_max_mem); -+ -+#endif -+ - /* get the vpe associated with this minor */ - struct vpe *get_vpe(int minor) - { ---- a/arch/mips/lantiq/prom.c -+++ b/arch/mips/lantiq/prom.c -@@ -36,10 +36,14 @@ unsigned long physical_memsize = 0L; - */ - static struct ltq_soc_info soc_info; - -+/* for Multithreading (APRP), vpe.c will use it */ -+unsigned long cp0_memsize; -+ - const char *get_system_type(void) - { - return soc_info.sys_type; - } -+EXPORT_SYMBOL(ltq_soc_type); - - int ltq_soc_type(void) - { ---- a/arch/mips/include/asm/mipsmtregs.h -+++ b/arch/mips/include/asm/mipsmtregs.h -@@ -32,6 +32,9 @@ - #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) - #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) - -+#define read_c0_vpeopt() __read_32bit_c0_register($1, 7) -+#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val) -+ - #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) - #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) - -@@ -377,6 +380,8 @@ do { \ - #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) - #define read_vpe_c0_vpeconf1() mftc0(1, 3) - #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) -+#define read_vpe_c0_vpeopt() mftc0(1, 7) -+#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val) - #define read_vpe_c0_count() mftc0(9, 0) - #define write_vpe_c0_count(val) mttc0(9, 0, val) - #define read_vpe_c0_status() mftc0(12, 0) diff --git a/target/linux/lantiq/patches-4.19/0154-lantiq-pci-bar11mask-fix.patch b/target/linux/lantiq/patches-4.19/0154-lantiq-pci-bar11mask-fix.patch deleted file mode 100644 index d0acd4bb10..0000000000 --- a/target/linux/lantiq/patches-4.19/0154-lantiq-pci-bar11mask-fix.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/arch/mips/pci/pci-lantiq.c -+++ b/arch/mips/pci/pci-lantiq.c -@@ -61,6 +61,8 @@ - #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) - #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) - -+extern u32 max_low_pfn; -+ - __iomem void *ltq_pci_mapped_cfg; - static __iomem void *ltq_pci_membase; - -@@ -86,8 +88,8 @@ static inline u32 ltq_calc_bar11mask(voi - u32 mem, bar11mask; - - /* BAR11MASK value depends on available memory on system. */ -- mem = get_num_physpages() * PAGE_SIZE; -- bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; -+ mem = max_low_pfn << PAGE_SHIFT; -+ bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8; - - return bar11mask; - } diff --git a/target/linux/lantiq/patches-4.19/0155-lantiq-VPE-nosmp.patch b/target/linux/lantiq/patches-4.19/0155-lantiq-VPE-nosmp.patch deleted file mode 100644 index 898c2d4821..0000000000 --- a/target/linux/lantiq/patches-4.19/0155-lantiq-VPE-nosmp.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/arch/mips/kernel/vpe-mt.c -+++ b/arch/mips/kernel/vpe-mt.c -@@ -132,7 +132,10 @@ int vpe_run(struct vpe *v) - * kernels need to turn it on, even if that wasn't the pre-dvpe() state. - */ - #ifdef CONFIG_SMP -- evpe(vpeflags); -+ if (!setup_max_cpus) /* nosmp is set */ -+ evpe(EVPE_ENABLE); -+ else -+ evpe(vpeflags); - #else - evpe(EVPE_ENABLE); - #endif diff --git a/target/linux/lantiq/patches-4.19/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-4.19/0160-owrt-lantiq-multiple-flash.patch deleted file mode 100644 index 304ff4bac8..0000000000 --- a/target/linux/lantiq/patches-4.19/0160-owrt-lantiq-multiple-flash.patch +++ /dev/null @@ -1,220 +0,0 @@ ---- a/drivers/mtd/maps/lantiq-flash.c -+++ b/drivers/mtd/maps/lantiq-flash.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -38,13 +39,16 @@ enum { - LTQ_NOR_NORMAL - }; - -+#define MAX_RESOURCES 4 -+ - struct ltq_mtd { -- struct resource *res; -- struct mtd_info *mtd; -- struct map_info *map; -+ struct mtd_info *mtd[MAX_RESOURCES]; -+ struct mtd_info *cmtd; -+ struct map_info map[MAX_RESOURCES]; - }; - - static const char ltq_map_name[] = "ltq_nor"; -+static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL }; - - static map_word - ltq_read16(struct map_info *map, unsigned long adr) -@@ -108,11 +112,43 @@ ltq_copy_to(struct map_info *map, unsign - } - - static int -+ltq_mtd_remove(struct platform_device *pdev) -+{ -+ struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); -+ int i; -+ -+ if (ltq_mtd == NULL) -+ return 0; -+ -+ if (ltq_mtd->cmtd) { -+ mtd_device_unregister(ltq_mtd->cmtd); -+ if (ltq_mtd->cmtd != ltq_mtd->mtd[0]) -+ mtd_concat_destroy(ltq_mtd->cmtd); -+ } -+ -+ for (i = 0; i < MAX_RESOURCES; i++) { -+ if (ltq_mtd->mtd[i] != NULL) -+ map_destroy(ltq_mtd->mtd[i]); -+ } -+ -+ kfree(ltq_mtd); -+ -+ return 0; -+} -+ -+static int - ltq_mtd_probe(struct platform_device *pdev) - { - struct ltq_mtd *ltq_mtd; - struct cfi_private *cfi; -- int err; -+ int err = 0; -+ int i; -+ int devices_found = 0; -+ -+ static const char *rom_probe_types[] = { -+ "cfi_probe", "jedec_probe", NULL -+ }; -+ const char **type; - - ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL); - if (!ltq_mtd) -@@ -120,75 +156,89 @@ ltq_mtd_probe(struct platform_device *pd - - platform_set_drvdata(pdev, ltq_mtd); - -- ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- if (!ltq_mtd->res) { -- dev_err(&pdev->dev, "failed to get memory resource\n"); -- return -ENOENT; -+ for (i = 0; i < pdev->num_resources; i++) { -+ printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n", -+ (unsigned long long)resource_size(&pdev->resource[i]), -+ (unsigned long long)pdev->resource[i].start); -+ -+ if (!devm_request_mem_region(&pdev->dev, -+ pdev->resource[i].start, -+ resource_size(&pdev->resource[i]), -+ dev_name(&pdev->dev))) { -+ dev_err(&pdev->dev, "Could not reserve memory region\n"); -+ return -ENOMEM; -+ } -+ -+ ltq_mtd->map[i].name = ltq_map_name; -+ ltq_mtd->map[i].bankwidth = 2; -+ ltq_mtd->map[i].read = ltq_read16; -+ ltq_mtd->map[i].write = ltq_write16; -+ ltq_mtd->map[i].copy_from = ltq_copy_from; -+ ltq_mtd->map[i].copy_to = ltq_copy_to; -+ -+ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) -+ ltq_mtd->map[i].phys = NO_XIP; -+ else -+ ltq_mtd->map[i].phys = pdev->resource[i].start; -+ ltq_mtd->map[i].size = resource_size(&pdev->resource[i]); -+ ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start, -+ ltq_mtd->map[i].size); -+ if (IS_ERR(ltq_mtd->map[i].virt)) -+ return PTR_ERR(ltq_mtd->map[i].virt); -+ -+ if (ltq_mtd->map[i].virt == NULL) { -+ dev_err(&pdev->dev, "Failed to ioremap flash region\n"); -+ err = PTR_ERR(ltq_mtd->map[i].virt); -+ goto err_out; -+ } -+ -+ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING; -+ for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++) -+ ltq_mtd->mtd[i] = do_map_probe(*type, <q_mtd->map[i]); -+ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL; -+ -+ if (!ltq_mtd->mtd[i]) { -+ dev_err(&pdev->dev, "probing failed\n"); -+ return -ENXIO; -+ } else { -+ devices_found++; -+ } -+ -+ ltq_mtd->mtd[i]->owner = THIS_MODULE; -+ ltq_mtd->mtd[i]->dev.parent = &pdev->dev; -+ -+ cfi = ltq_mtd->map[i].fldrv_priv; -+ cfi->addr_unlock1 ^= 1; -+ cfi->addr_unlock2 ^= 1; - } - -- ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info), -- GFP_KERNEL); -- if (!ltq_mtd->map) -- return -ENOMEM; -- -- if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) -- ltq_mtd->map->phys = NO_XIP; -- else -- ltq_mtd->map->phys = ltq_mtd->res->start; -- ltq_mtd->res->start; -- ltq_mtd->map->size = resource_size(ltq_mtd->res); -- ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); -- if (IS_ERR(ltq_mtd->map->virt)) -- return PTR_ERR(ltq_mtd->map->virt); -- -- ltq_mtd->map->name = ltq_map_name; -- ltq_mtd->map->bankwidth = 2; -- ltq_mtd->map->read = ltq_read16; -- ltq_mtd->map->write = ltq_write16; -- ltq_mtd->map->copy_from = ltq_copy_from; -- ltq_mtd->map->copy_to = ltq_copy_to; -- -- ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING; -- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map); -- ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL; -- -- if (!ltq_mtd->mtd) { -- dev_err(&pdev->dev, "probing failed\n"); -- return -ENXIO; -+ if (devices_found == 1) { -+ ltq_mtd->cmtd = ltq_mtd->mtd[0]; -+ } else if (devices_found > 1) { -+ /* -+ * We detected multiple devices. Concatenate them together. -+ */ -+ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev)); -+ if (ltq_mtd->cmtd == NULL) -+ err = -ENXIO; - } - -- ltq_mtd->mtd->dev.parent = &pdev->dev; -- mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node); -- -- cfi = ltq_mtd->map->fldrv_priv; -- cfi->addr_unlock1 ^= 1; -- cfi->addr_unlock2 ^= 1; -+ ltq_mtd->cmtd->dev.parent = &pdev->dev; -+ mtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node); - -- err = mtd_device_register(ltq_mtd->mtd, NULL, 0); -+ err = mtd_device_register(ltq_mtd->cmtd, NULL, 0); - if (err) { - dev_err(&pdev->dev, "failed to add partitions\n"); -- goto err_destroy; -+ goto err_out; - } - - return 0; - --err_destroy: -- map_destroy(ltq_mtd->mtd); -+err_out: -+ ltq_mtd_remove(pdev); - return err; - } - --static int --ltq_mtd_remove(struct platform_device *pdev) --{ -- struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); -- -- if (ltq_mtd && ltq_mtd->mtd) { -- mtd_device_unregister(ltq_mtd->mtd); -- map_destroy(ltq_mtd->mtd); -- } -- return 0; --} -- - static const struct of_device_id ltq_mtd_match[] = { - { .compatible = "lantiq,nor" }, - {}, diff --git a/target/linux/lantiq/patches-4.19/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-4.19/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch deleted file mode 100644 index d153c521d3..0000000000 --- a/target/linux/lantiq/patches-4.19/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/drivers/mtd/chips/cfi_cmdset_0001.c -+++ b/drivers/mtd/chips/cfi_cmdset_0001.c -@@ -39,7 +39,7 @@ - /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ - - // debugging, turns off buffer write mode if set to 1 --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - /* Intel chips */ - #define I82802AB 0x00ad diff --git a/target/linux/lantiq/patches-4.19/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-4.19/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch deleted file mode 100644 index b98abe8b4b..0000000000 --- a/target/linux/lantiq/patches-4.19/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -424,6 +424,20 @@ static void clkdev_add_clkout(void) - } - } - -+static void set_phy_clock_source(struct device_node *np_cgu) -+{ -+ u32 phy_clk_src, ifcc; -+ -+ if (!np_cgu) -+ return; -+ -+ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) -+ return; -+ -+ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); -+ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); -+} -+ - /* bring up all register ranges that we need for basic system control */ - void __init ltq_soc_init(void) - { -@@ -587,4 +601,6 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); - } - usb_set_clock(); -+ -+ set_phy_clock_source(np_cgu); - } diff --git a/target/linux/lantiq/patches-4.19/0701-NET-lantiq-etop-of-mido.patch b/target/linux/lantiq/patches-4.19/0701-NET-lantiq-etop-of-mido.patch deleted file mode 100644 index 05e4ec8328..0000000000 --- a/target/linux/lantiq/patches-4.19/0701-NET-lantiq-etop-of-mido.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -40,6 +40,7 @@ - #include - #include - #include -+#include - - #include - -@@ -571,7 +572,8 @@ static int - ltq_etop_mdio_init(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int err; -+ struct device_node *mdio_np = NULL; -+ int err, ret; - - priv->mii_bus = mdiobus_alloc(); - if (!priv->mii_bus) { -@@ -591,7 +593,15 @@ ltq_etop_mdio_init(struct net_device *de - priv->mii_bus->name = "ltq_mii"; - snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", - priv->pdev->name, priv->pdev->id); -- if (mdiobus_register(priv->mii_bus)) { -+ -+ mdio_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus"); -+ -+ if (mdio_np) -+ ret = of_mdiobus_register(priv->mii_bus, mdio_np); -+ else -+ ret = mdiobus_register(priv->mii_bus); -+ -+ if (ret) { - err = -ENXIO; - goto err_out_free_mdiobus; - } diff --git a/target/linux/lantiq/xrx200/config-4.19 b/target/linux/lantiq/xrx200/config-4.19 deleted file mode 100644 index 1c506f8ae7..0000000000 --- a/target/linux/lantiq/xrx200/config-4.19 +++ /dev/null @@ -1,90 +0,0 @@ -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL2=y -CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin" -CONFIG_EXTRA_FIRMWARE_DIR="firmware" -CONFIG_HWMON=y -CONFIG_ICPLUS_PHY=y -CONFIG_IFX_VPE_EXT=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_POLLDEV=y -CONFIG_INTEL_XWAY_PHY=y -# CONFIG_ISDN is not set -CONFIG_LANTIQ_XRX200=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MIPS_MT=y -# CONFIG_MIPS_MT_FPAFF is not set -CONFIG_MIPS_MT_SMP=y -CONFIG_MIPS_NR_CPU_NR_MAP=2 -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -CONFIG_MIPS_VPE_APSP_API=y -CONFIG_MIPS_VPE_APSP_API_MT=y -CONFIG_MIPS_VPE_LOADER=y -CONFIG_MIPS_VPE_LOADER_MT=y -CONFIG_MIPS_VPE_LOADER_TOM=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_MTD_NAND_XWAY=y -# CONFIG_MTD_PHYSMAP_OF is not set -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -# CONFIG_MTD_UBI_FASTMAP is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NR_CPUS=2 -CONFIG_PADATA=y -CONFIG_PCI=y -# CONFIG_PCIEAER is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_LANTIQ=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_SUPPLY=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_SENSORS_LTQ_CPUTEMP=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SYNC_R4K=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_XPS=y -CONFIG_XRX200_PHY_FW=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/xway/config-4.19 b/target/linux/lantiq/xway/config-4.19 deleted file mode 100644 index 34cd84267a..0000000000 --- a/target/linux/lantiq/xway/config-4.19 +++ /dev/null @@ -1,46 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_AR8216_PHY=y -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_POLLDEV=y -# CONFIG_ISDN is not set -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_MTD_NAND_XWAY=y -# CONFIG_MTD_PHYSMAP_OF is not set -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -# CONFIG_MTD_UBI_FASTMAP is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_NLS=y -CONFIG_PCI=y -# CONFIG_PCIE_LANTIQ is not set -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RTL8306_PHY=y -CONFIG_RTL8366S_PHY=y -CONFIG_RTL8367B_PHY=y -CONFIG_RTL8367_PHY=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/xway_legacy/config-4.19 b/target/linux/lantiq/xway_legacy/config-4.19 deleted file mode 100644 index ad949bdf8b..0000000000 --- a/target/linux/lantiq/xway_legacy/config-4.19 +++ /dev/null @@ -1,34 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_AR8216_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -# CONFIG_GPIO_SYSFS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_POLLDEV=y -# CONFIG_ISDN is not set -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -# CONFIG_LEDS_TRIGGER_TIMER is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MTD_PHYSMAP_OF is not set -CONFIG_NLS=y -CONFIG_PCI=y -# CONFIG_PCIE_LANTIQ is not set -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RTL8306_PHY=y -CONFIG_RTL8366S_PHY=y -CONFIG_RTL8367B_PHY=y -CONFIG_RTL8367_PHY=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y From 33b76d66d1afa9d888f32587b18d78a930593ca5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20Fr=C3=B6hning?= Date: Mon, 17 Aug 2020 13:14:39 +0200 Subject: [PATCH 14/15] ramips: add support for TP-Link RE200 v4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TP-Link RE200 v4 is a wireless range extender with Ethernet and 2.4G and 5G WiFi with internal antennas. It's based on MediaTek MT7628AN+MT7610EN like the v2/v3. Specifications -------------- - MediaTek MT7628AN (580 Mhz) - 64 MB of RAM - 8 MB of FLASH - 2T2R 2.4 GHz and 1T1R 5 GHz - 1x 10/100 Mbps Ethernet - 8x LED (GPIO-controlled), 2x button - UART connection holes on PCB (57600 8n1) There are 2.4G and 5G LEDs in red and green which are controlled separately. MAC addresses ------------- The MAC address assignment matches stock firmware, i.e.: LAN : *:8E 2.4G: *:8D 5G : *:8C MAC address assignment has been done according to the RE200 v2. The label MAC address matches the OpenWrt ethernet address. Installation ------------ Web Interface ------------- It is possible to upgrade to OpenWrt via the web interface. Simply flash the -factory.bin from OEM. In contrast to a stock firmware, this will not overwrite U-Boot. Recovery -------- Unfortunately, this devices does not offer a recovery mode or a tftp installation method. If the web interface upgrade fails, you have to open your device and attach serial console. Instructions for serial console and recovery may be checked out in commit 6d6f36ae787c ("ramips: add support for TP-Link RE200 v2") or on the device's Wiki page. Signed-off-by: Richard Fröhning [removed empty line, fix commit message formatting] Signed-off-by: David Bauer --- .../ramips/dts/mt7628an_tplink_re200-v4.dts | 8 ++++ target/linux/ramips/image/mt76x8.mk | 10 +++++ .../mt76x8/base-files/etc/board.d/01_leds | 1 + .../mt76x8/base-files/etc/board.d/02_network | 1 + tools/firmware-utils/src/tplink-safeloader.c | 44 +++++++++++++++++++ 5 files changed, 64 insertions(+) create mode 100644 target/linux/ramips/dts/mt7628an_tplink_re200-v4.dts diff --git a/target/linux/ramips/dts/mt7628an_tplink_re200-v4.dts b/target/linux/ramips/dts/mt7628an_tplink_re200-v4.dts new file mode 100644 index 0000000000..83f1f3acca --- /dev/null +++ b/target/linux/ramips/dts/mt7628an_tplink_re200-v4.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7628an_tplink_re200.dtsi" + +/ { + compatible = "tplink,re200-v4", "mediatek,mt7628an-soc"; + model = "TP-Link RE200 v4"; +}; diff --git a/target/linux/ramips/image/mt76x8.mk b/target/linux/ramips/image/mt76x8.mk index 326dcd82bb..6327c95bb0 100644 --- a/target/linux/ramips/image/mt76x8.mk +++ b/target/linux/ramips/image/mt76x8.mk @@ -413,6 +413,16 @@ define Device/tplink_re200-v3 endef TARGET_DEVICES += tplink_re200-v3 +define Device/tplink_re200-v4 + $(Device/tplink-safeloader) + IMAGE_SIZE := 7808k + DEVICE_MODEL := RE200 + DEVICE_VARIANT := v4 + DEVICE_PACKAGES := kmod-mt76x0e + TPLINK_BOARD_ID := RE200-V4 +endef +TARGET_DEVICES += tplink_re200-v4 + define Device/tplink_re220-v2 $(Device/tplink-safeloader) IMAGE_SIZE := 7808k diff --git a/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds b/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds index c26d6436e9..e1c3454237 100755 --- a/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds +++ b/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds @@ -62,6 +62,7 @@ tplink,archer-c50-v4) ;; tplink,re200-v2|\ tplink,re200-v3|\ +tplink,re200-v4|\ tplink,re220-v2|\ tplink,tl-mr3020-v3|\ tplink,tl-wa801nd-v5) diff --git a/target/linux/ramips/mt76x8/base-files/etc/board.d/02_network b/target/linux/ramips/mt76x8/base-files/etc/board.d/02_network index f1687c7108..2cda818b2a 100755 --- a/target/linux/ramips/mt76x8/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt76x8/base-files/etc/board.d/02_network @@ -20,6 +20,7 @@ ramips_setup_interfaces() tama,w06|\ tplink,re200-v2|\ tplink,re200-v3|\ + tplink,re200-v4|\ tplink,re220-v2|\ tplink,re305-v1|\ tplink,tl-mr3020-v3|\ diff --git a/tools/firmware-utils/src/tplink-safeloader.c b/tools/firmware-utils/src/tplink-safeloader.c index 31b9c032d1..22427a67e5 100644 --- a/tools/firmware-utils/src/tplink-safeloader.c +++ b/tools/firmware-utils/src/tplink-safeloader.c @@ -1774,6 +1774,50 @@ static struct device_info boards[] = { .last_sysupgrade_partition = "file-system" }, + /** Firmware layout for the RE200 v4 */ + { + .id = "RE200-V4", + .vendor = "", + .support_list = + "SupportList:\n" + "{product_name:RE200,product_ver:4.0.0,special_id:00000000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:45550000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:4A500000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:4B520000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:43410000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:41550000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:42520000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:55530000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:41520000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:52550000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:54570000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:45530000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:49440000}\n" + "{product_name:RE200,product_ver:4.0.0,special_id:45470000}\n", + .support_trail = '\x00', + .soft_ver = "soft_ver:1.1.0\n", + + .partitions = { + {"fs-uboot", 0x00000, 0x20000}, + {"firmware", 0x20000, 0x7a0000}, + {"partition-table", 0x7c0000, 0x02000}, + {"default-mac", 0x7c2000, 0x00020}, + {"pin", 0x7c2100, 0x00020}, + {"product-info", 0x7c3100, 0x01000}, + {"soft-version", 0x7c4200, 0x01000}, + {"support-list", 0x7c5200, 0x01000}, + {"profile", 0x7c6200, 0x08000}, + {"config-info", 0x7ce200, 0x00400}, + {"user-config", 0x7d0000, 0x10000}, + {"default-config", 0x7e0000, 0x10000}, + {"radio", 0x7f0000, 0x10000}, + {NULL, 0, 0} + }, + + .first_sysupgrade_partition = "os-image", + .last_sysupgrade_partition = "file-system" + }, + /** Firmware layout for the RE220 v2 */ { .id = "RE220-V2", From dd20ba98e701bdb519868588c63ec46e62fb768e Mon Sep 17 00:00:00 2001 From: John Audia Date: Sat, 17 Oct 2020 07:53:44 -0400 Subject: [PATCH 15/15] kernel: bump 5.4 to 5.4.72 All modifications made by update_kernel.sh Build system: x86_64 Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711 Run-tested: ipq806x/R7800 No dmesg regressions, everything functional Signed-off-by: John Audia --- include/kernel-version.mk | 4 ++-- ...th-Check-key-sizes-only-when-Secure-Simple-Pa.patch | 4 ++-- ...link-propagate-resolved-link-config-via-mac_l.patch | 10 +++++----- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/kernel-version.mk b/include/kernel-version.mk index bec2b73608..5b9c863041 100644 --- a/include/kernel-version.mk +++ b/include/kernel-version.mk @@ -7,10 +7,10 @@ ifdef CONFIG_TESTING_KERNEL endif LINUX_VERSION-4.19 = .138 -LINUX_VERSION-5.4 = .71 +LINUX_VERSION-5.4 = .72 LINUX_KERNEL_HASH-4.19.138 = d15c27d05f6c527269b75b30cc72972748e55720e7e00ad8abbaa4fe3b1d5e02 -LINUX_KERNEL_HASH-5.4.71 = 737049ef3cf38d46ee3b377354336cdbc1c4dd95b4e54975a70716f96c8d6cc7 +LINUX_KERNEL_HASH-5.4.72 = 0e24645bd56fe5b55a7a662895f5562c103d71b54d097281f0c9c71ff22c1172 remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1)))) sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1))))))) diff --git a/target/linux/bcm27xx/patches-5.4/950-0199-Bluetooth-Check-key-sizes-only-when-Secure-Simple-Pa.patch b/target/linux/bcm27xx/patches-5.4/950-0199-Bluetooth-Check-key-sizes-only-when-Secure-Simple-Pa.patch index a03c7377f2..0de55097c5 100644 --- a/target/linux/bcm27xx/patches-5.4/950-0199-Bluetooth-Check-key-sizes-only-when-Secure-Simple-Pa.patch +++ b/target/linux/bcm27xx/patches-5.4/950-0199-Bluetooth-Check-key-sizes-only-when-Secure-Simple-Pa.patch @@ -21,8 +21,8 @@ Cc: stable@vger.kernel.org --- a/net/bluetooth/hci_conn.c +++ b/net/bluetooth/hci_conn.c -@@ -1285,8 +1285,13 @@ int hci_conn_check_link_mode(struct hci_ - return 0; +@@ -1302,8 +1302,13 @@ int hci_conn_check_link_mode(struct hci_ + return 0; } - if (hci_conn_ssp_enabled(conn) && diff --git a/target/linux/mediatek/patches-5.4/0600-net-phylink-propagate-resolved-link-config-via-mac_l.patch b/target/linux/mediatek/patches-5.4/0600-net-phylink-propagate-resolved-link-config-via-mac_l.patch index 6473dc19c3..45d7999e31 100644 --- a/target/linux/mediatek/patches-5.4/0600-net-phylink-propagate-resolved-link-config-via-mac_l.patch +++ b/target/linux/mediatek/patches-5.4/0600-net-phylink-propagate-resolved-link-config-via-mac_l.patch @@ -199,10 +199,7 @@ Signed-off-by: David S. Miller + * @duplex: link duplex + * @tx_pause: link transmit pause enablement status + * @rx_pause: link receive pause enablement status - * -- * If @mode is not an in-band negotiation mode (as defined by -- * phylink_autoneg_inband()), allow the link to come up. If @phy -- * is non-%NULL, configure Energy Efficient Ethernet by calling ++ * + * Configure the MAC for an established link. + * + * @speed, @duplex, @tx_pause and @rx_pause indicate the finalised link @@ -214,7 +211,10 @@ Signed-off-by: David S. Miller + * Note that when 802.3z in-band negotiation is in use, it is possible + * that the user wishes to override the pause settings, and this should + * be allowed when considering the implementation of this method. -+ * + * +- * If @mode is not an in-band negotiation mode (as defined by +- * phylink_autoneg_inband()), allow the link to come up. If @phy +- * is non-%NULL, configure Energy Efficient Ethernet by calling + * If in-band negotiation mode is disabled, allow the link to come up. If + * @phy is non-%NULL, configure Energy Efficient Ethernet by calling * phy_init_eee() and perform appropriate MAC configuration for EEE.