fish/immortalwrt
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

rockchip: fastrhino: update dts according to latest schema

Browse Source 
Prepare for submitting to upstream kernel.

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2023-04-28 08:18:13 +08:00
parent d45c5d88c4
commit 54fbc6a564
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
5 changed files with 25 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r66s.dts
View File

@ -1,14 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk3568-fastrhino-r6xs.dtsi"
#include "rk3568-fastrhino-r66s.dtsi"
/ {
model = "Lunzn FastRhino R66S";
compatible = "lunzn,fastrhino-r66s", "rockchip,rk3568";
aliases {
ethernet0 = &rtl8125_1;
ethernet1 = &rtl8125_2;
mmc0 = &sdmmc0;
};
};

40
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r6xs.dtsi → package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r66s.dtsi
View File

@ -44,7 +44,7 @@
};
};
dc_12v: dc-12v {
dc_12v: dc-12v-regulator {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
@ -53,7 +53,7 @@
regulator-max-microvolt = <12000000>;
};
vcc3v3_pcie: vcc3v3-pcie {
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
regulator-always-on;
@ -63,7 +63,7 @@
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_sys: vcc3v3-sys {
vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
@ -73,7 +73,7 @@
vin-supply = <&dc_12v>;
};
vcc5v0_sys: vcc5v0-sys {
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
@ -83,7 +83,7 @@
vin-supply = <&dc_12v>;
};
vcc5v0_usb_host: vcc5v0-usb-host {
vcc5v0_usb_host: vcc5v0-usb-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb_host";
regulator-always-on;
@ -92,7 +92,7 @@
regulator-max-microvolt = <5000000>;
};
vcc5v0_usb_otg: vcc5v0-usb-otg {
vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
@ -377,19 +377,6 @@
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@10 {
reg = <0x00100000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_1: pcie-eth@10,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x78>;
};
};
};
&pcie3x2 {
@ -397,19 +384,6 @@
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@20 {
reg = <0x00200000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_2: pcie-eth@20,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x78>;
};
};
};
&pinctrl {
@ -432,7 +406,7 @@
};
usb {
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};

4
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
View File

@ -1,14 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk3568-fastrhino-r6xs.dtsi"
#include "rk3568-fastrhino-r66s.dtsi"
/ {
model = "Lunzn FastRhino R66S";
compatible = "lunzn,fastrhino-r66s", "rockchip,rk3568";
aliases {
ethernet0 = &rtl8125_1;
ethernet1 = &rtl8125_2;
mmc0 = &sdmmc0;
};
};

40
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r6xs.dtsi → target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
View File

@ -44,7 +44,7 @@
};
};
dc_12v: dc-12v {
dc_12v: dc-12v-regulator {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
@ -53,7 +53,7 @@
regulator-max-microvolt = <12000000>;
};
vcc3v3_pcie: vcc3v3-pcie {
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
regulator-always-on;
@ -63,7 +63,7 @@
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_sys: vcc3v3-sys {
vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
@ -73,7 +73,7 @@
vin-supply = <&dc_12v>;
};
vcc5v0_sys: vcc5v0-sys {
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
@ -83,7 +83,7 @@
vin-supply = <&dc_12v>;
};
vcc5v0_usb_host: vcc5v0-usb-host {
vcc5v0_usb_host: vcc5v0-usb-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb_host";
regulator-always-on;
@ -92,7 +92,7 @@
regulator-max-microvolt = <5000000>;
};
vcc5v0_usb_otg: vcc5v0-usb-otg {
vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
@ -377,19 +377,6 @@
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@10 {
reg = <0x00100000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_1: pcie-eth@10,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x78>;
};
};
};
&pcie3x2 {
@ -397,19 +384,6 @@
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@20 {
reg = <0x00200000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_2: pcie-eth@20,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x78>;
};
};
};
&pinctrl {
@ -432,7 +406,7 @@
};
usb {
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};

18
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk3568-fastrhino-r6xs.dtsi"
#include "rk3568-fastrhino-r66s.dtsi"
/ {
model = "Lunzn FastRhino R68S";
@ -9,8 +9,6 @@
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &rtl8125_1;
ethernet3 = &rtl8125_2;
mmc0 = &sdhci;
};
@ -41,6 +39,10 @@
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 15ms, 50ms for rtl8211f */
snps,reset-delays-us = <0 15000 50000>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
status = "okay";
@ -59,6 +61,10 @@
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 15ms, 50ms for rtl8211f */
snps,reset-delays-us = <0 15000 50000>;
tx_delay = <0x4f>;
rx_delay = <0x26>;
status = "okay";
@ -71,9 +77,6 @@
reg = <0>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
};
};
@ -84,9 +87,6 @@
reg = <0>;
pinctrl-0 = <&eth_phy1_reset_pin>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
};
};