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Merge Official Source

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2022-05-27 14:03:47 +08:00
commit 5e1c52f744
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
23 changed files with 906 additions and 79 deletions
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8
package/libs/libnl-tiny/Makefile
View File

@ -12,9 +12,9 @@ PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/libnl-tiny.git
PKG_SOURCE_DATE:=2021-11-21
PKG_SOURCE_VERSION:=8e0555fb39f51a5d6436b4f1370850caa03611ea
PKG_MIRROR_HASH:=2cfbcc62384535674a2c0157cb24a0736520fcb66ed50be23bf9141c8488885f
PKG_SOURCE_DATE:=2022-05-17
PKG_SOURCE_VERSION:=b5b2ba09c4f1c8b3c21580aea7223edc2f5e92be
PKG_MIRROR_HASH:=b957d56aa8c2e7b55184111be69eb8dea734f1feba19e670a91f302459a48a78
CMAKE_INSTALL:=1
PKG_LICENSE:=LGPL-2.1
@ -27,7 +27,7 @@ define Package/libnl-tiny
SECTION:=libs
CATEGORY:=Libraries
TITLE:=netlink socket library
ABI_VERSION:=1
ABI_VERSION:=$(PKG_SOURCE_DATE)
endef
define Package/libnl-tiny/description

6
package/network/config/netifd/Makefile
View File

@ -5,9 +5,9 @@ PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/netifd.git
PKG_SOURCE_DATE:=2022-02-20
PKG_SOURCE_VERSION:=136006b88826feff4f0a36ffab511d1366483cf2
PKG_MIRROR_HASH:=6358738d20e6df27b82c3bdb575fba0fdad8bef45a3c7479b93a5587c465dba4
PKG_SOURCE_DATE:=2022-05-19
PKG_SOURCE_VERSION:=507c0513d1766757d969530c51fe7d368354538d
PKG_MIRROR_HASH:=706ede2ffd787a1f5388f2e80300e8f559a704dda21ebc05356074765593539c
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_LICENSE:=GPL-2.0

4
package/system/selinux-policy/Makefile
View File

@ -8,8 +8,8 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=selinux-policy
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://git.defensec.nl/selinux-policy.git
PKG_VERSION:=1.1
PKG_MIRROR_HASH:=657ec1ff51ab946753fb3559384511a536ac1e018691f3e49cbab21c55d23e08
PKG_VERSION:=1.2.3
PKG_MIRROR_HASH:=ff1ddca168a6631aeac34352657f424bc4acf5d50b8aa7ff8dfa8c9663ba8538
PKG_SOURCE_VERSION:=v$(PKG_VERSION)
PKG_BUILD_DEPENDS:=secilc/host policycoreutils/host

26
target/linux/ath79/dts/ar9342_ubnt_nanobeam-m5-xw.dts Normal file
View File

@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ar9342_ubnt_xw.dtsi"
/ {
compatible = "ubnt,nanobeam-m5-xw", "ubnt,xw", "qca,ar9342";
model = "Ubiquiti NanoBeam M5 (XW)";
};
&mdio0 {
status = "okay";
phy-mask = <0x1>;
phy1: ethernet-phy@1 {
reg = <1>;
phy-mode = "mii";
reset-gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
};
};
&eth0 {
status = "okay";
phy-handle = <&phy1>;
};

8
target/linux/ath79/dts/qca9531_mikrotik_routerboard-951ui-2nd.dts Normal file
View File

@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qca9533_mikrotik_routerboard-95x.dtsi"
/ {
compatible = "mikrotik,routerboard-951ui-2nd", "qca,qca9531";
model = "MikroTik RouterBOARD 951Ui-2nD (hAP)";
};

18
target/linux/ath79/dts/qca9533_mikrotik_routerboard-952ui-5ac2nd.dts Normal file
View File

@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qca9533_mikrotik_routerboard-95x.dtsi"
/ {
compatible = "mikrotik,routerboard-952ui-5ac2nd", "qca,qca9533";
model = "MikroTik RouterBOARD 952Ui-5ac2nD (hAP ac lite)";
};
&pcie0 {
status = "okay";
wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0 0 0 0 0>;
};
};

98
target/linux/ath79/dts/qca9533_mikrotik_routerboard-95x.dtsi Normal file
View File

@ -0,0 +1,98 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qca9533_mikrotik_routerboard-16m.dtsi"
/ {
aliases {
led-boot = &led_user;
led-failsafe = &led_user;
led-running = &led_user;
led-upgrade = &led_user;
};
leds {
compatible = "gpio-leds";
led_user: user {
label = "green:user";
gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
};
port1 {
label = "green:port1";
gpios = <&gpio_ext 0 GPIO_ACTIVE_LOW>;
};
port2 {
label = "green:port2";
gpios = <&gpio_ext 1 GPIO_ACTIVE_LOW>;
};
port3 {
label = "green:port3";
gpios = <&gpio_ext 2 GPIO_ACTIVE_LOW>;
};
port4 {
label = "green:port4";
gpios = <&gpio_ext 3 GPIO_ACTIVE_LOW>;
};
port5 {
label = "green:port5";
gpios = <&gpio_ext 4 GPIO_ACTIVE_LOW>;
};
};
gpio-export {
compatible = "gpio-export";
usb_power {
gpio-export,name = "usb-power";
gpio-export,output = <1>;
gpios = <&gpio_ext 5 GPIO_ACTIVE_LOW>;
};
enable_poe_port5 {
gpio-export,name = "enable-poe:port5";
gpio-export,output = <0>;
gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
};
};
};
&spi {
pinctrl-names = "default";
pinctrl-0 = <&pin_spi_cs1>;
gpio_ext: gpio_ext@1 {
compatible = "fairchild,74hc595";
reg = <1>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <1>;
spi-max-frequency = <25000000>;
};
};
&pinmux {
pin_spi_cs1: pinmux_spi_cs1 {
pinctrl-single,bits = <0x8 0x0a000000 0xff000000>;
};
};
&eth0 {
status = "okay";
phy-handle = <&swphy4>;
};
&usb0 {
status = "okay";
};
&usb_phy {
status = "okay";
};

8
target/linux/ath79/image/generic-ubnt.mk
View File

@ -255,6 +255,14 @@ define Device/ubnt_nanobeam-ac-xc
endef
TARGET_DEVICES += ubnt_nanobeam-ac-xc
define Device/ubnt_nanobeam-m5-xw
$(Device/ubnt-xw)
DEVICE_MODEL := NanoBeam M5
DEVICE_PACKAGES += rssileds
SUPPORTED_DEVICES += loco-m-xw
endef
TARGET_DEVICES += ubnt_nanobeam-m5-xw
define Device/ubnt_nanobridge-m
$(Device/ubnt-xm)
SOC := ar7241

19
target/linux/ath79/image/mikrotik.mk
View File

@ -38,6 +38,25 @@ define Device/mikrotik_routerboard-922uags-5hpacd
endef
TARGET_DEVICES += mikrotik_routerboard-922uags-5hpacd
define Device/mikrotik_routerboard-951ui-2nd
$(Device/mikrotik_nor)
SOC := qca9531
DEVICE_MODEL := RouterBOARD 951Ui-2nD (hAP)
IMAGE_SIZE := 16256k
SUPPORTED_DEVICES += rb-951ui-2nd
endef
TARGET_DEVICES += mikrotik_routerboard-951ui-2nd
define Device/mikrotik_routerboard-952ui-5ac2nd
$(Device/mikrotik_nor)
SOC := qca9533
DEVICE_MODEL := RouterBOARD 952Ui-5ac2nD (hAP ac lite)
DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9887-ct
IMAGE_SIZE := 16256k
SUPPORTED_DEVICES += rb-952ui-5ac2nd
endef
TARGET_DEVICES += mikrotik_routerboard-952ui-5ac2nd
define Device/mikrotik_routerboard-962uigs-5hact2hnt
$(Device/mikrotik_nor)
SOC := qca9558

8
target/linux/ath79/mikrotik/base-files/etc/board.d/01_leds
View File

@ -6,6 +6,14 @@ board_config_update
board=$(board_name)
case "$board" in
mikrotik,routerboard-951ui-2nd|\
mikrotik,routerboard-952ui-5ac2nd)
ucidef_set_led_netdev "port1" "port1" "green:port1" "eth1"
ucidef_set_led_switch "port2" "port2" "green:port2" "switch0" "0x10"
ucidef_set_led_switch "port3" "port3" "green:port3" "switch0" "0x08"
ucidef_set_led_switch "port4" "port4" "green:port4" "switch0" "0x04"
ucidef_set_led_switch "port5" "port5" "green:port5" "switch0" "0x02"
;;
mikrotik,routerboard-lhg-2nd|\
mikrotik,routerboard-mapl-2nd|\
mikrotik,routerboard-wap-2nd)

6
target/linux/ath79/mikrotik/base-files/etc/board.d/02_network
View File

@ -24,6 +24,12 @@ ath79_setup_interfaces()
mikrotik,routerboard-wapr-2nd)
ucidef_set_interface_lan "eth0"
;;
mikrotik,routerboard-951ui-2nd|\
mikrotik,routerboard-952ui-5ac2nd)
ucidef_set_interface_wan "eth1"
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1"
;;
mikrotik,routerboard-962uigs-5hact2hnt)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan" "3:lan" "4:lan" "5:lan" "1:wan"

4
target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
View File

@ -35,6 +35,10 @@ case "$FIRMWARE" in
mikrotik,routerboard-wap-g-5hact2hnd)
caldata_mikrotik_ath9k 0x1000 0x440 $(macaddr_add "$mac_base" 2)
;;
mikrotik,routerboard-951ui-2nd|\
mikrotik,routerboard-952ui-5ac2nd)
caldata_mikrotik_ath9k 0x1000 0x440 $(macaddr_add "$mac_base" 6)
;;
mikrotik,routerboard-962uigs-5hact2hnt)
caldata_mikrotik_ath9k 0x1000 0x440 $(macaddr_add "$mac_base" 7)
;;

2
target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
View File

@ -12,6 +12,8 @@ case "$FIRMWARE" in
"ath10k/cal-pci-0000:00:00.0.bin")
case $board in
mikrotik,routerboard-921gs-5hpacd-15s|\
mikrotik,routerboard-951ui-2nd|\
mikrotik,routerboard-952ui-5ac2nd|\
mikrotik,routerboard-962uigs-5hact2hnt|\
mikrotik,routerboard-wap-g-5hact2hnd)
caldata_sysfsload_from_file $wlan_data 0x5000 0x844

2
target/linux/bcm27xx/modules/other.mk
View File

@ -10,7 +10,7 @@ define KernelPackage/pwm-raspberrypi-poe
CONFIG_PWM_RASPBERRYPI_POE
FILES:=$(LINUX_DIR)/drivers/pwm/pwm-raspberrypi-poe.ko
AUTOLOAD:=$(call AutoLoad,20,pwm-raspberrypi-poe)
DEPENDS:=@TARGET_bcm27xx @LINUX_5_15
DEPENDS:=@TARGET_bcm27xx @LINUX_5_15 +kmod-hwmon-pwmfan
endef
define KernelPackage/pwm-raspberrypi-poe/description

1
target/linux/bmips/nand/base-files/etc/board.d/02_network
View File

@ -10,6 +10,7 @@ comtrend,vr-3032u)
ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
;;
netgear,dgnd3700-v2)
ucidef_set_bridge_device switch
ucidef_set_interface_lan "extsw"
;;
esac

436
target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts Normal file
View File

@ -0,0 +1,436 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "mt7622.dtsi"
#include "mt6380.dtsi"
/ {
model = "ELECOM WRC-X3200GST3";
compatible = "elecom,wrc-x3200gst3", "mediatek,mt7622";
aliases {
serial0 = &uart0;
led-boot = &led_power_green;
led-failsafe = &led_power_red;
led-running = &led_power_green;
led-upgrade = &led_power_green;
label-mac-device = &wan;
};
chosen {
bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
};
memory {
reg = <0 0x40000000 0 0x1f000000>;
};
leds {
compatible = "gpio-leds";
led-0 {
label = "red:wps";
gpios = <&pio 47 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_WPS;
};
led_power_red: led-1 {
label = "red:power";
gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
function-enumerator = <1>;
};
led_power_green: led-2 {
label = "green:power";
gpios = <&pio 49 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
function-enumerator = <2>;
};
led-3 {
label = "blue:power";
gpios = <&pio 50 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_POWER;
function-enumerator = <3>;
};
led-4 {
label = "white:wlan2g";
gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_WLAN;
function-enumerator = <1>;
linux,default-trigger = "phy0tpt";
};
led-5 {
label = "white:wlan5g";
gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_WLAN;
function-enumerator = <2>;
linux,default-trigger = "phy1radio";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
ap {
label = "ap";
gpios = <&pio 42 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
linux,input-type = <EV_SW>;
};
router {
label = "router";
gpios = <&pio 43 GPIO_ACTIVE_LOW>;
linux,code = <BTN_1>;
linux,input-type = <EV_SW>;
};
wps {
label = "wps";
gpios = <&pio 102 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
};
&cpu0 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
&cpu1 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
&pio {
eth_pins: eth-pins {
mux {
function = "eth";
groups = "mdc_mdio", "rgmii_via_gmac2";
};
};
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
groups = "pcie0_pad_perst",
"pcie0_1_waken",
"pcie0_1_clkreq";
};
};
pmic_bus_pins: pmic-bus-pins {
mux {
function = "pmic";
groups = "pmic_bus";
};
};
pwm7_pins: pwm1-2-pins {
mux {
function = "pwm";
groups = "pwm_ch7_2";
};
};
/* Serial NAND is shared pin with SPI-NOR */
serial_nand_pins: serial-nand-pins {
mux {
function = "flash";
groups = "snfi";
};
conf-cmd-data {
pins = "SPI_WP", "SPI_HOLD", "SPI_MOSI",
"SPI_MISO", "SPI_CS";
drive-strength = <16>;
bias-pull-up;
};
conf-clk {
pins = "SPI_CLK";
drive-strength = <16>;
bias-pull-down;
};
};
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0_0_tx_rx" ;
};
};
watchdog_pins: watchdog-pins {
mux {
function = "watchdog";
groups = "watchdog";
};
};
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&eth_pins>;
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-connection-type = "2500base-x";
nvmem-cells = <&macaddr_factory_7fff4>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
compatible = "mediatek,mt7531";
reg = <0>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
wan: port@0 {
reg = <0>;
label = "wan";
nvmem-cells = <&macaddr_factory_7fffa>;
nvmem-cell-names = "mac-address";
};
port@1 {
reg = <1>;
label = "lan4";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan1";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
};
};
&bch {
status = "okay";
};
&snfi {
pinctrl-names = "default";
pinctrl-0 = <&serial_nand_pins>;
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
nand-ecc-engine = <&snfi>;
mediatek,bmt-v2;
mediatek,bmt-table-size = <0x1000>;
mediatek,bmt-remap-range = <0x0 0x8c0000>,
<0x1bc0000 0x30c0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Preloader";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "ATF";
reg = <0x80000 0x40000>;
read-only;
};
partition@c0000 {
label = "u-boot";
reg = <0xc0000 0x80000>;
read-only;
};
partition@140000 {
label = "u-boot-env";
reg = <0x140000 0x80000>;
read-only;
};
factory: partition@1c0000 {
label = "factory";
reg = <0x1c0000 0x100000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_4: macaddr@4 {
reg = <0x4 0x6>;
};
macaddr_factory_7fff4: macaddr@7fff4 {
reg = <0x7fff4 0x6>;
};
macaddr_factory_7fffa: macaddr@7fffa {
reg = <0x7fffa 0x6>;
};
};
partition@2c0000 {
label = "kernel";
reg = <0x2c0000 0x600000>;
};
partition@8c0000 {
label = "ubi";
reg = <0x8c0000 0x1300000>;
};
partition@1bc0000 {
label = "tm_pattern";
reg = <0x1bc0000 0x500000>;
read-only;
};
partition@20c0000 {
label = "tm_key";
reg = <0x20c0000 0x100000>;
read-only;
};
partition@21c0000 {
label = "user_data";
reg = <0x21c0000 0xf00000>;
read-only;
};
partition@30c0000 {
label = "reserved";
reg = <0x30c0000 0x4f40000>;
read-only;
};
};
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "okay";
};
&slot0 {
status = "okay";
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x5000>;
ieee80211-freq-limit = <5000000 6000000>;
nvmem-cells = <&macaddr_factory_4>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm7_pins>;
status = "okay";
};
&pwrap {
pinctrl-names = "default";
pinctrl-0 = <&pmic_bus_pins>;
status = "okay";
};
&rtc {
status = "disabled";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&watchdog {
pinctrl-names = "default";
pinctrl-0 = <&watchdog_pins>;
status = "okay";
};
&wmac {
status = "okay";
mediatek,mtd-eeprom = <&factory 0x0>;
};

20
target/linux/mediatek/image/mt7622.mk
View File

@ -137,6 +137,26 @@ define Device/elecom_wrc-2533gent
endef
TARGET_DEVICES += elecom_wrc-2533gent
define Device/elecom_wrc-x3200gst3
DEVICE_VENDOR := ELECOM
DEVICE_MODEL := WRC-X3200GST3
DEVICE_DTS := mt7622-elecom-wrc-x3200gst3
DEVICE_DTS_DIR := ../dts
IMAGE_SIZE := 25600k
KERNEL_SIZE := 6144k
BLOCKSIZE := 128k
PAGESIZE := 2048
UBINIZE_OPTS := -E 5
IMAGES += factory.bin
IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | \
append-ubi | check-size | \
elecom-wrc-gs-factory WRC-X3200GST3 0.00 -N | \
append-string MT7622_ELECOM_WRC-X3200GST3
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
DEVICE_PACKAGES := kmod-mt7915e
endef
TARGET_DEVICES += elecom_wrc-x3200gst3
define Device/linksys_e8450
DEVICE_VENDOR := Linksys
DEVICE_MODEL := E8450

1
target/linux/mediatek/mt7622/base-files/etc/board.d/02_network
View File

@ -9,6 +9,7 @@ mediatek_setup_interfaces()
case $board in
bananapi,bpi-r64|\
elecom,wrc-x3200gst3|\
linksys,e8450|\
linksys,e8450-ubi|\
mediatek,mt7622-rfb1|\

12
target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
View File

@ -32,6 +32,12 @@ platform_do_upgrade() {
nand_do_upgrade "$1"
fi
;;
elecom,wrc-x3200gst3|\
mediatek,mt7622-rfb1-ubi|\
totolink,a8000ru|\
xiaomi,redmi-router-ax6s)
nand_do_upgrade "$1"
;;
linksys,e8450-ubi)
CI_KERNPART="fit"
nand_do_upgrade "$1"
@ -44,11 +50,6 @@ platform_do_upgrade() {
fi
default_do_upgrade "$1"
;;
mediatek,mt7622-rfb1-ubi|\
totolink,a8000ru|\
xiaomi,redmi-router-ax6s)
nand_do_upgrade "$1"
;;
*)
default_do_upgrade "$1"
;;
@ -67,6 +68,7 @@ platform_check_image() {
buffalo,wsr-2533dhp2)
buffalo_check_image "$board" "$magic" "$1" || return 1
;;
elecom,wrc-x3200gst3|\
mediatek,mt7622-rfb1-ubi|\
totolink,a8000ru|\
xiaomi,redmi-router-ax6s)

86
target/linux/realtek/patches-5.10/320-gpio-add-support-for-RTL930X-and-RTL931X.patch → target/linux/realtek/patches-5.10/021-v5.19-02-gpio-realtek-otto-Support-reversed-port-layouts.patch
View File

@ -1,10 +1,22 @@
From 512c5be35223d9baa2629efa1084cf5210eaee80 Mon Sep 17 00:00:00 2001
From: Sander Vanheule <sander@svanheule.net>
Date: Sat, 9 Apr 2022 21:55:47 +0200
Subject: [PATCH 2/6] gpio: realtek-otto: Support reversed port layouts
The GPIO port layout on the RTL930x SoC series is reversed compared to
the RTL838x and RTL839x SoC series. Add new port offset calculator
functions to ensure the correct order is used when reading port IRQ
data, and ensure bgpio uses the right byte ordering.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
drivers/gpio/gpio-realtek-otto.c | 55 +++++++++++++++++++++++++++++---
1 file changed, 51 insertions(+), 4 deletions(-)
--- a/drivers/gpio/gpio-realtek-otto.c
+++ b/drivers/gpio/gpio-realtek-otto.c
@@ -55,9 +55,12 @@
struct realtek_gpio_ctrl {
struct gpio_chip gc;
void __iomem *base;
+ void __iomem *cpumap_base;
@@ -58,6 +58,8 @@ struct realtek_gpio_ctrl {
raw_spinlock_t lock;
u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK];
u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK];
@ -13,7 +25,7 @@
};
/* Expand with more flags as devices with other quirks are added */
@@ -69,6 +72,16 @@ enum realtek_gpio_flags {
@@ -69,6 +71,11 @@ enum realtek_gpio_flags {
* line the IRQ handler was assigned to, causing uncaught interrupts.
*/
GPIO_INTERRUPTS_DISABLED = BIT(0),
@ -22,15 +34,10 @@
+ * fields, and [BA, DC] for 2-bit fields.
+ */
+ GPIO_PORTS_REVERSED = BIT(1),
+ /*
+ * Interrupts can be enabled per cpu. This requires a secondary IO
+ * range, where the per-cpu enable masks are located.
+ */
+ GPIO_INTERRUPTS_PER_CPU = BIT(2),
};
static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data)
@@ -86,21 +99,50 @@ static struct realtek_gpio_ctrl *irq_dat
@@ -86,21 +93,50 @@ static struct realtek_gpio_ctrl *irq_dat
* port. The two interrupt mask registers store two bits per GPIO, so use u16
* values.
*/
@ -84,34 +91,7 @@
}
/* Set the rising and falling edge mask bits for a GPIO port pin */
@@ -222,6 +264,12 @@ static int realtek_gpio_irq_init(struct
for (port = 0; (port * 8) < gc->ngpio; port++) {
realtek_gpio_write_imr(ctrl, port, 0, 0);
realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0));
+
+ if (ctrl->cpumap_base) {
+ /* Default CPU affinity to the first CPU */
+ iowrite8(GENMASK(7, 0),
+ ctrl->cpumap_base + ctrl->port_offset_u8(port));
+ }
}
return 0;
@@ -246,6 +294,13 @@ static const struct of_device_id realtek
{
.compatible = "realtek,rtl8390-gpio",
},
+ {
+ .compatible = "realtek,rtl9300-gpio",
+ .data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU)
+ },
+ {
+ .compatible = "realtek,rtl9310-gpio",
+ },
{}
};
MODULE_DEVICE_TABLE(of, realtek_gpio_of_match);
@@ -253,12 +308,14 @@ MODULE_DEVICE_TABLE(of, realtek_gpio_of_
@@ -253,6 +289,7 @@ MODULE_DEVICE_TABLE(of, realtek_gpio_of_
static int realtek_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@ -119,14 +99,7 @@
unsigned int dev_flags;
struct gpio_irq_chip *girq;
struct realtek_gpio_ctrl *ctrl;
u32 ngpios;
int err, irq;
+ pr_info("%s probing RTL GPIO\n", __func__);
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
return -ENOMEM;
@@ -280,10 +337,21 @@ static int realtek_gpio_probe(struct pla
@@ -280,10 +317,20 @@ static int realtek_gpio_probe(struct pla
raw_spin_lock_init(&ctrl->lock);
@ -134,8 +107,7 @@
+ bgpio_flags = 0;
+ ctrl->port_offset_u8 = realtek_gpio_port_offset_u8_rev;
+ ctrl->port_offset_u16 = realtek_gpio_port_offset_u16_rev;
+ }
+ else {
+ } else {
+ bgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
+ ctrl->port_offset_u8 = realtek_gpio_port_offset_u8;
+ ctrl->port_offset_u16 = realtek_gpio_port_offset_u16;
@ -149,17 +121,3 @@
if (err) {
dev_err(dev, "unable to init generic GPIO");
return err;
@@ -308,6 +376,13 @@ static int realtek_gpio_probe(struct pla
girq->init_hw = realtek_gpio_irq_init;
}
+ if (dev_flags & GPIO_INTERRUPTS_PER_CPU) {
+ ctrl->cpumap_base = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(ctrl->cpumap_base))
+ return dev_err_probe(dev, PTR_ERR(ctrl->cpumap_base),
+ "IRQ CPU map registers not defined");
+ }
+
return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
}

153
target/linux/realtek/patches-5.10/021-v5.19-03-gpio-realtek-otto-Support-per-cpu-interrupts.patch Normal file
View File

@ -0,0 +1,153 @@
From 95fa6dbe58f286a8f87cb37b7516232eb678de2d Mon Sep 17 00:00:00 2001
From: Sander Vanheule <sander@svanheule.net>
Date: Sat, 9 Apr 2022 21:55:48 +0200
Subject: [PATCH 3/6] gpio: realtek-otto: Support per-cpu interrupts
On SoCs with multiple cores, it is possible that the GPIO interrupt
controller supports assigning specific pins to one or more cores.
IRQ balancing can be performed on a line-by-line basis if the parent
interrupt is routed to all available cores, which is the default upon
initialisation.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
drivers/gpio/gpio-realtek-otto.c | 75 +++++++++++++++++++++++++++++++-
1 file changed, 74 insertions(+), 1 deletion(-)
--- a/drivers/gpio/gpio-realtek-otto.c
+++ b/drivers/gpio/gpio-realtek-otto.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/gpio/driver.h>
+#include <linux/cpumask.h>
#include <linux/irq.h>
#include <linux/minmax.h>
#include <linux/mod_devicetable.h>
@@ -55,6 +56,8 @@
struct realtek_gpio_ctrl {
struct gpio_chip gc;
void __iomem *base;
+ void __iomem *cpumask_base;
+ struct cpumask cpu_irq_maskable;
raw_spinlock_t lock;
u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK];
u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK];
@@ -76,6 +79,11 @@ enum realtek_gpio_flags {
* fields, and [BA, DC] for 2-bit fields.
*/
GPIO_PORTS_REVERSED = BIT(1),
+ /*
+ * Interrupts can be enabled per cpu. This requires a secondary IO
+ * range, where the per-cpu enable masks are located.
+ */
+ GPIO_INTERRUPTS_PER_CPU = BIT(2),
};
static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data)
@@ -250,14 +258,61 @@ static void realtek_gpio_irq_handler(str
chained_irq_exit(irq_chip, desc);
}
+static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl,
+ unsigned int port, int cpu)
+{
+ return ctrl->cpumask_base + ctrl->port_offset_u8(port) +
+ REALTEK_GPIO_PORTS_PER_BANK * cpu;
+}
+
+static int realtek_gpio_irq_set_affinity(struct irq_data *data,
+ const struct cpumask *dest, bool force)
+{
+ struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
+ unsigned int line = irqd_to_hwirq(data);
+ unsigned int port = line / 8;
+ unsigned int port_pin = line % 8;
+ void __iomem *irq_cpu_mask;
+ unsigned long flags;
+ int cpu;
+ u8 v;
+
+ if (!ctrl->cpumask_base)
+ return -ENXIO;
+
+ raw_spin_lock_irqsave(&ctrl->lock, flags);
+
+ for_each_cpu(cpu, &ctrl->cpu_irq_maskable) {
+ irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, port, cpu);
+ v = ioread8(irq_cpu_mask);
+
+ if (cpumask_test_cpu(cpu, dest))
+ v |= BIT(port_pin);
+ else
+ v &= ~BIT(port_pin);
+
+ iowrite8(v, irq_cpu_mask);
+ }
+
+ raw_spin_unlock_irqrestore(&ctrl->lock, flags);
+
+ irq_data_update_effective_affinity(data, dest);
+
+ return 0;
+}
+
static int realtek_gpio_irq_init(struct gpio_chip *gc)
{
struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
unsigned int port;
+ int cpu;
for (port = 0; (port * 8) < gc->ngpio; port++) {
realtek_gpio_write_imr(ctrl, port, 0, 0);
realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0));
+
+ for_each_cpu(cpu, &ctrl->cpu_irq_maskable)
+ iowrite8(GENMASK(7, 0), realtek_gpio_irq_cpu_mask(ctrl, port, cpu));
}
return 0;
@@ -269,6 +324,7 @@ static struct irq_chip realtek_gpio_irq_
.irq_mask = realtek_gpio_irq_mask,
.irq_unmask = realtek_gpio_irq_unmask,
.irq_set_type = realtek_gpio_irq_set_type,
+ .irq_set_affinity = realtek_gpio_irq_set_affinity,
};
static const struct of_device_id realtek_gpio_of_match[] = {
@@ -293,8 +349,10 @@ static int realtek_gpio_probe(struct pla
unsigned int dev_flags;
struct gpio_irq_chip *girq;
struct realtek_gpio_ctrl *ctrl;
+ struct resource *res;
u32 ngpios;
- int err, irq;
+ unsigned int nr_cpus;
+ int cpu, err, irq;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
@@ -355,6 +413,21 @@ static int realtek_gpio_probe(struct pla
girq->init_hw = realtek_gpio_irq_init;
}
+ cpumask_clear(&ctrl->cpu_irq_maskable);
+
+ if ((dev_flags & GPIO_INTERRUPTS_PER_CPU) && irq > 0) {
+ ctrl->cpumask_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
+ if (IS_ERR(ctrl->cpumask_base))
+ return dev_err_probe(dev, PTR_ERR(ctrl->cpumask_base),
+ "missing CPU IRQ mask registers");
+
+ nr_cpus = resource_size(res) / REALTEK_GPIO_PORTS_PER_BANK;
+ nr_cpus = min(nr_cpus, num_present_cpus());
+
+ for (cpu = 0; cpu < nr_cpus; cpu++)
+ cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable);
+ }
+
return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
}

29
target/linux/realtek/patches-5.10/021-v5.19-04-gpio-realtek-otto-Add-RTL930x-support.patch Normal file
View File

@ -0,0 +1,29 @@
From deaf1cecdeb052cdb5e92fd642016198724b44a4 Mon Sep 17 00:00:00 2001
From: Sander Vanheule <sander@svanheule.net>
Date: Sat, 9 Apr 2022 21:55:49 +0200
Subject: [PATCH 4/6] gpio: realtek-otto: Add RTL930x support
The RTL930x SoC series has support for 24 GPIOs, with the port order
reversed compared to RTL838x and RTL839x. The RTL930x series also has
two CPUs (VPEs) and can distribute individual GPIO interrupts between
them.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
drivers/gpio/gpio-realtek-otto.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/gpio/gpio-realtek-otto.c
+++ b/drivers/gpio/gpio-realtek-otto.c
@@ -338,6 +338,10 @@ static const struct of_device_id realtek
{
.compatible = "realtek,rtl8390-gpio",
},
+ {
+ .compatible = "realtek,rtl9300-gpio",
+ .data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU)
+ },
{}
};
MODULE_DEVICE_TABLE(of, realtek_gpio_of_match);

30
target/linux/realtek/patches-5.10/021-v5.19-06-gpio-realtek-otto-Add-RTL931x-support.patch Normal file
View File

@ -0,0 +1,30 @@
From d3bf3dc4bbbf6109bd9b4bd60089d36205ec4a37 Mon Sep 17 00:00:00 2001
From: Sander Vanheule <sander@svanheule.net>
Date: Sat, 9 Apr 2022 21:55:51 +0200
Subject: [PATCH 6/6] gpio: realtek-otto: Add RTL931x support
The RTL931x SoC series has support for 32 GPIOs, although not all lines
may be broken out to a physical pad.
The GPIO bank's parent interrupt can be routed to either or both of the
SoC's CPU cores by the GIC. Line-by-line IRQ balancing is not possible
on these SoCs.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
drivers/gpio/gpio-realtek-otto.c | 3 +++
1 file changed, 3 insertions(+)
--- a/drivers/gpio/gpio-realtek-otto.c
+++ b/drivers/gpio/gpio-realtek-otto.c
@@ -342,6 +342,9 @@ static const struct of_device_id realtek
.compatible = "realtek,rtl9300-gpio",
.data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU)
},
+ {
+ .compatible = "realtek,rtl9310-gpio",
+ },
{}
};
MODULE_DEVICE_TABLE(of, realtek_gpio_of_match);