Merge Official Source

This commit is contained in:
CN_SZTL 2020-03-17 21:25:28 +08:00
commit 5e6df644ac
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
609 changed files with 36537 additions and 7013 deletions

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@ -82,7 +82,28 @@
if ( (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API) ||
(_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API_G997) ||
(_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API_PM) ||
@@ -1058,6 +1065,7 @@ static void DSL_DRV_DebugInit(void)
@@ -828,12 +835,19 @@ DSL_int32_t DSL_DRV_ThreadShutdown(
DSL_uint32_t DSL_DRV_SysTimeGet(DSL_uint32_t nOffset)
{
- struct timeval tv;
DSL_uint32_t nTime = 0;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+ struct timeval tv;
memset(&tv, 0, sizeof(tv));
do_gettimeofday(&tv);
nTime = (DSL_uint32_t)tv.tv_sec;
+#else
+ struct timespec64 now;
+
+ ktime_get_real_ts64(&now);
+ nTime = (DSL_uint32_t)now.tv_sec;
+#endif
if ( (nOffset == 0) || (nOffset > nTime) )
{
@@ -1058,6 +1072,7 @@ static void DSL_DRV_DebugInit(void)
/* Entry point of driver */
int __init DSL_ModuleInit(void)
{
@ -90,7 +111,7 @@
DSL_int_t i;
printk(DSL_DRV_CRLF DSL_DRV_CRLF "Infineon CPE API Driver version: %s" DSL_DRV_CRLF,
@@ -1104,7 +1112,8 @@ int __init DSL_ModuleInit(void)
@@ -1104,7 +1119,8 @@ int __init DSL_ModuleInit(void)
}
DSL_DRV_DevNodeInit();
@ -137,7 +158,7 @@
#ifdef INCLUDE_DSL_CPE_API_IFXOS_SUPPORT
/** IFXOS includes*/
--- /dev/null
+++ b/src/ifxmips_mei_interface.h
+++ b/src/include/ifxmips_mei_interface.h
@@ -0,0 +1,702 @@
+/******************************************************************************
+

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@ -1,14 +1,15 @@
--- a/src/common/drv_dsl_cpe_os_linux.c
+++ b/src/common/drv_dsl_cpe_os_linux.c
@@ -12,6 +12,7 @@
@@ -11,7 +11,7 @@
#ifdef __LINUX__
#define DSL_INTERN
#include <linux/device.h>
+#include <linux/platform_device.h>
-#include <linux/device.h>
+#include <linux/of_platform.h>
#include "drv_dsl_cpe_api.h"
#include "drv_dsl_cpe_api_ioctl.h"
@@ -1063,7 +1064,7 @@ static void DSL_DRV_DebugInit(void)
@@ -1070,7 +1070,7 @@ static void DSL_DRV_DebugInit(void)
#endif
/* Entry point of driver */
@ -17,7 +18,7 @@
{
struct class *dsl_class;
DSL_int_t i;
@@ -1117,7 +1118,7 @@ int __init DSL_ModuleInit(void)
@@ -1124,7 +1124,7 @@ int __init DSL_ModuleInit(void)
return 0;
}
@ -26,7 +27,7 @@
{
printk("Module will be unloaded"DSL_DRV_CRLF);
@@ -1132,7 +1133,7 @@ void __exit DSL_ModuleCleanup(void)
@@ -1139,7 +1139,7 @@ void __exit DSL_ModuleCleanup(void)
(DSL_uint8_t**)&g_BndFpgaBase);
#endif /* defined(INCLUDE_DSL_CPE_API_VINAX) && defined(INCLUDE_DSL_BONDING)*/
@ -35,7 +36,7 @@
}
#ifndef _lint
@@ -1148,8 +1149,30 @@ module_param(debug_level, byte, 0);
@@ -1155,8 +1155,30 @@ module_param(debug_level, byte, 0);
MODULE_PARM_DESC(debug_level, "set to get more (1) or fewer (4) debug outputs");
#endif /* #ifndef DSL_DEBUG_DISABLE*/

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@ -5,10 +5,10 @@
#define DSL_INTERN
+#include <linux/kthread.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
@@ -40,7 +41,7 @@ static DSL_ssize_t DSL_DRV_Write(DSL_DRV
#include "drv_dsl_cpe_api.h"
@@ -39,7 +40,7 @@ static DSL_ssize_t DSL_DRV_Write(DSL_DRV
static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_inode_t * pINode, DSL_DRV_file_t * pFile,
DSL_uint_t nCommand, unsigned long nArg);
#else
@ -17,7 +17,7 @@
DSL_uint_t nCommand, unsigned long nArg);
#endif
static int DSL_DRV_Open(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);
@@ -184,7 +185,7 @@ static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_
@@ -183,7 +184,7 @@ static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_
DSL_uint_t nCommand,
unsigned long nArg)
#else
@ -26,7 +26,7 @@
DSL_DRV_file_t * pFile,
DSL_uint_t nCommand,
unsigned long nArg)
@@ -521,9 +522,9 @@ DSL_void_t* DSL_IoctlMemCpyTo(
@@ -520,9 +521,9 @@ DSL_void_t* DSL_IoctlMemCpyTo(
- IFX_SUCCESS on success
- IFX_ERROR on error
*/
@ -38,7 +38,7 @@
DSL_int32_t retVal = -1;
#ifndef _lint
@@ -546,30 +547,6 @@ DSL_DRV_STATIC DSL_int32_t DSL_DRV_Kerne
@@ -545,30 +546,6 @@ DSL_DRV_STATIC DSL_int32_t DSL_DRV_Kerne
(DSL_NULL, "ENTER - Kernel Thread Startup <%s>" DSL_DRV_CRLF,
pThrCntrl->thrParams.pName));
@ -69,7 +69,7 @@
/*DSL_DRV_ThreadPriorityModify(pThrCntrl->nPriority);*/
pThrCntrl->thrParams.bRunning = 1;
@@ -639,9 +616,7 @@ DSL_int32_t DSL_DRV_ThreadInit(
@@ -638,9 +615,7 @@ DSL_int32_t DSL_DRV_ThreadInit(
init_completion(&pThrCntrl->thrCompletion);
/* start kernel thread via the wrapper function */
@ -80,7 +80,7 @@
pThrCntrl->bValid = DSL_TRUE;
@@ -1064,12 +1039,12 @@ static void DSL_DRV_DebugInit(void)
@@ -1070,12 +1045,12 @@ static void DSL_DRV_DebugInit(void)
#endif
/* Entry point of driver */
@ -95,7 +95,7 @@
&(dsl_cpe_api_version[4]));
DSL_DRV_MemSet( ifxDevices, 0, sizeof(DSL_devCtx_t) * DSL_DRV_MAX_DEVICE_NUMBER );
@@ -1118,7 +1093,7 @@ static int __devinit ltq_adsl_probe(stru
@@ -1124,7 +1099,7 @@ static int __devinit ltq_adsl_probe(stru
return 0;
}
@ -104,7 +104,7 @@
{
printk("Module will be unloaded"DSL_DRV_CRLF);
@@ -1163,7 +1138,7 @@ MODULE_DEVICE_TABLE(of, ltq_adsl_match);
@@ -1169,7 +1144,7 @@ MODULE_DEVICE_TABLE(of, ltq_adsl_match);
static struct platform_driver ltq_adsl_driver = {
.probe = ltq_adsl_probe,

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@ -289,9 +289,17 @@ static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
return -ENOTTY;
if ( _IOC_DIR(cmd) & _IOC_READ )
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0)
ret = !access_ok(arg, _IOC_SIZE(cmd));
#else
ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
#endif
else if ( _IOC_DIR(cmd) & _IOC_WRITE )
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0)
ret = !access_ok(arg, _IOC_SIZE(cmd));
#else
ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
#endif
if ( ret )
return -EFAULT;

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@ -270,7 +270,7 @@ static struct shash_alg ifxdeu_md5_alg = {
.cra_name = "md5",
.cra_driver_name= "ifxdeu-md5",
.cra_priority = 300,
.cra_flags = CRYPTO_ALG_TYPE_DIGEST,
.cra_flags = CRYPTO_ALG_TYPE_HASH,
.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
.cra_module = THIS_MODULE,
}

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@ -346,7 +346,7 @@ static struct shash_alg ifxdeu_md5_hmac_alg = {
.cra_driver_name= "ifxdeu-md5_hmac",
.cra_priority = 400,
.cra_ctxsize = sizeof(struct md5_hmac_ctx),
.cra_flags = CRYPTO_ALG_TYPE_DIGEST,
.cra_flags = CRYPTO_ALG_TYPE_HASH,
.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
.cra_module = THIS_MODULE,
}

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@ -259,7 +259,7 @@ static struct shash_alg ifxdeu_sha1_alg = {
.cra_name = "sha1",
.cra_driver_name= "ifxdeu-sha1",
.cra_priority = 300,
.cra_flags = CRYPTO_ALG_TYPE_DIGEST,
.cra_flags = CRYPTO_ALG_TYPE_HASH,
.cra_blocksize = SHA1_HMAC_BLOCK_SIZE,
.cra_module = THIS_MODULE,
}

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@ -334,7 +334,7 @@ static struct shash_alg ifxdeu_sha1_hmac_alg = {
.cra_driver_name= "ifxdeu-sha1_hmac",
.cra_priority = 400,
.cra_ctxsize = sizeof(struct sha1_hmac_ctx),
.cra_flags = CRYPTO_ALG_TYPE_DIGEST,
.cra_flags = CRYPTO_ALG_TYPE_HASH,
.cra_blocksize = SHA1_HMAC_BLOCK_SIZE,
.cra_module = THIS_MODULE,
}

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@ -6,7 +6,7 @@
#include <linux/sched.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,11,0))
+ #include <linux/sched/signal.h>
+ #include <linux/sched/types.h>
+ #include <uapi/linux/sched/types.h>
+#endif
#undef CONFIG_DEVFS_FS
#ifndef UTS_RELEASE

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@ -35,7 +35,28 @@
#endif
if (pINode == DSL_NULL)
@@ -1203,6 +1197,9 @@ static void DSL_DRV_NlSendMsg(DSL_char_t
@@ -917,12 +911,19 @@ DSL_int32_t DSL_DRV_ThreadShutdown(
DSL_uint32_t DSL_DRV_SysTimeGet(DSL_uint32_t nOffset)
{
- struct timeval tv;
DSL_uint32_t nTime = 0;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+ struct timeval tv;
memset(&tv, 0, sizeof(tv));
do_gettimeofday(&tv);
nTime = (DSL_uint32_t)tv.tv_sec;
+#else
+ struct timespec64 now;
+
+ ktime_get_real_ts64(&now);
+ nTime = (DSL_uint32_t)now.tv_sec;
+#endif
if ( (nOffset == 0) || (nOffset > nTime) )
{
@@ -1203,6 +1204,9 @@ static void DSL_DRV_NlSendMsg(DSL_char_t
}
#endif
@ -45,7 +66,7 @@
/* Entry point of driver */
int __init DSL_ModuleInit(void)
{
@@ -1241,6 +1238,10 @@ int __init DSL_ModuleInit(void)
@@ -1241,6 +1245,10 @@ int __init DSL_ModuleInit(void)
DSL_DRV_DevNodeInit();
@ -56,7 +77,7 @@
return 0;
}
@@ -1248,6 +1249,11 @@ void __exit DSL_ModuleCleanup(void)
@@ -1248,6 +1256,11 @@ void __exit DSL_ModuleCleanup(void)
{
printk("Module will be unloaded"DSL_DRV_CRLF);

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@ -147,7 +147,7 @@ I2C_MUX_GPIO_MODULES:= \
define KernelPackage/i2c-mux-gpio
$(call i2c_defaults,$(I2C_MUX_GPIO_MODULES),51)
TITLE:=GPIO-based I2C mux/switches
DEPENDS:=kmod-i2c-mux
DEPENDS:=+kmod-i2c-mux
endef
define KernelPackage/i2c-mux-gpio/description
@ -163,7 +163,7 @@ I2C_MUX_PCA9541_MODULES:= \
define KernelPackage/i2c-mux-pca9541
$(call i2c_defaults,$(I2C_MUX_PCA9541_MODULES),51)
TITLE:=Philips PCA9541 I2C mux/switches
DEPENDS:=kmod-i2c-mux
DEPENDS:=+kmod-i2c-mux
endef
define KernelPackage/i2c-mux-pca9541/description
@ -178,7 +178,7 @@ I2C_MUX_PCA954x_MODULES:= \
define KernelPackage/i2c-mux-pca954x
$(call i2c_defaults,$(I2C_MUX_PCA954x_MODULES),51)
TITLE:=Philips PCA954x I2C mux/switches
DEPENDS:=kmod-i2c-mux
DEPENDS:=+kmod-i2c-mux
endef
define KernelPackage/i2c-mux-pca954x/description

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@ -732,7 +732,8 @@ define KernelPackage/serial-8250
FILES:= \
$(LINUX_DIR)/drivers/tty/serial/8250/8250.ko \
$(LINUX_DIR)/drivers/tty/serial/8250/8250_base.ko \
$(if $(CONFIG_PCI),$(LINUX_DIR)/drivers/tty/serial/8250/8250_pci.ko)
$(if $(CONFIG_PCI),$(LINUX_DIR)/drivers/tty/serial/8250/8250_pci.ko) \
$(if $(CONFIG_GPIOLIB),$(LINUX_DIR)/drivers/tty/serial/serial_mctrl_gpio.ko@ge5.3)
AUTOLOAD:=$(call AutoProbe,8250 8250_base 8250_pci)
endef

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@ -8,12 +8,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=libnftnl
PKG_VERSION:=1.1.4
PKG_VERSION:=1.1.5
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://netfilter.org/projects/$(PKG_NAME)/files
PKG_HASH:=c8c7988347adf261efac5bba59f8e5f995ffb65f247a88cc144e69620573ed20
PKG_HASH:=66de4d05227c0a1a731c369b193010d18a05b1185c2735211e0ecf658eeb14f3
PKG_MAINTAINER:=Steven Barth <steven@midlink.org>
PKG_LICENSE:=GPL-2.0+
@ -31,7 +31,7 @@ define Package/libnftnl
DEPENDS:=+libmnl
TITLE:=Low-level netlink library for the nf_tables subsystem
URL:=http://www.netfilter.org/projects/libnftnl
ABI_VERSION:=11
ABI_VERSION:=12
endef
define Package/libnftnl/description

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@ -5,9 +5,9 @@ PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/netifd.git
PKG_SOURCE_DATE:=2020-01-18
PKG_SOURCE_VERSION:=1321c1bd8fe921986c4eb39c3783ddd827b79543
PKG_MIRROR_HASH:=7e93ba79727e84cc391121be8a190cfa373dee8e2511f75d6f2fcb179928f5fa
PKG_SOURCE_DATE:=2020-02-05
PKG_SOURCE_VERSION:=dbdef938279ec649b25b98a9b61f81f17953ef21
PKG_MIRROR_HASH:=6138cb72ed1f3c0a4e2b32e0734ed41c65beb4baeed0693153979877c726aad7
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_LICENSE:=GPL-2.0

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@ -1110,6 +1110,7 @@ static struct ubus_object_type daemon_object_type =
void hostapd_ubus_add(struct hapd_interfaces *interfaces)
{
struct ubus_object *obj = &interfaces->ubus;
char *name;
int name_len;
int ret;
@ -1119,12 +1120,14 @@ void hostapd_ubus_add(struct hapd_interfaces *interfaces)
name_len = strlen("hostapd") + 1;
if (interfaces->name)
name_len += strlen(interfaces->name) + 1;
obj->name = malloc(name_len);
strcpy(obj->name, "hostapd");
name = malloc(name_len);
strcpy(name, "hostapd");
if (interfaces->name) {
strcat(obj->name, ".");
strcat(obj->name, interfaces->name);
strcat(name, ".");
strcat(name, interfaces->name);
}
obj->name = name;
obj->type = &daemon_object_type;
obj->methods = daemon_object_type.methods;
@ -1207,7 +1210,7 @@ int hostapd_ubus_handle_event(struct hostapd_data *hapd, struct hostapd_ubus_req
ht_capabilities = (struct ieee80211_ht_capabilities*) req->elems->ht_capabilities;
ht_cap = blobmsg_open_table(&b, "ht_capabilities");
blobmsg_add_u16(&b, "ht_capabilities_info", ht_capabilities->ht_capabilities_info);
ht_cap_mcs_set = blobmsg_open_table(&b, "supported_mcs_set");
ht_cap_mcs_set = blobmsg_open_table(&b, "supported_mcs_set");
blobmsg_add_u16(&b, "a_mpdu_params", ht_capabilities->a_mpdu_params);
blobmsg_add_u16(&b, "ht_extended_capabilities", ht_capabilities->ht_extended_capabilities);
blobmsg_add_u32(&b, "tx_bf_capability_info", ht_capabilities->tx_bf_capability_info);
@ -1218,7 +1221,7 @@ int hostapd_ubus_handle_event(struct hostapd_data *hapd, struct hostapd_ubus_req
}
blobmsg_close_array(&b, mcs_set);
blobmsg_close_table(&b, ht_cap_mcs_set);
blobmsg_close_table(&b, ht_cap);
blobmsg_close_table(&b, ht_cap);
}
if(req->elems->vht_capabilities)
{

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@ -320,6 +320,7 @@ static struct ubus_object_type wpas_daemon_object_type =
void wpas_ubus_add(struct wpa_global *global)
{
struct ubus_object *obj = &global->ubus_global;
char *name;
int name_len;
int ret;
@ -329,15 +330,18 @@ void wpas_ubus_add(struct wpa_global *global)
name_len = strlen("wpa_supplicant") + 1;
if (global->params.name)
name_len += strlen(global->params.name) + 1;
obj->name = malloc(name_len);
strcpy(obj->name, "wpa_supplicant");
name = malloc(name_len);
strcpy(name, "wpa_supplicant");
if (global->params.name)
{
strcat(obj->name, ".");
strcat(obj->name, global->params.name);
strcat(name, ".");
strcat(name, global->params.name);
}
obj->name = name;
obj->type = &wpas_daemon_object_type;
obj->methods = wpas_daemon_object_type.methods;
obj->n_methods = wpas_daemon_object_type.n_methods;

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@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=comgt
PKG_VERSION:=0.32
PKG_RELEASE:=32
PKG_RELEASE:=33
PKG_SOURCE:=$(PKG_NAME).$(PKG_VERSION).tgz
PKG_SOURCE_URL:=@SF/comgt

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@ -15,11 +15,11 @@ find_3g_iface() {
if [ "${dev##*/}" = "${tty##*/}" ]; then
if [ "$ACTION" = add ]; then
available=1
else
available=0
proto_set_available "$cfg" 1
fi
if [ "$ACTION" = remove ]; then
proto_set_available "$cfg" 0
fi
proto_set_available "$cfg" $available
fi
}

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@ -8,7 +8,7 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=curl
PKG_VERSION:=7.69.0
PKG_VERSION:=7.69.1
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
@ -16,7 +16,7 @@ PKG_SOURCE_URL:=https://dl.uxnr.de/mirror/curl/ \
https://curl.mirror.anstey.ca/ \
https://curl.askapache.com/download/ \
https://curl.haxx.se/download/
PKG_HASH:=9fadf2f082c127757808a28ddd5ab9d1bc2c7061ca7ddaf85814285e15e3271f
PKG_HASH:=03c7d5e6697f7b7e40ada1b2256e565a555657398e6c1fcfa4cb251ccd819d4f
PKG_LICENSE:=MIT
PKG_LICENSE_FILES:=COPYING

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@ -2,7 +2,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=wwan
PKG_VERSION:=2019-04-29
PKG_RELEASE=4
PKG_RELEASE=5
PKG_LICENSE:=GPL-2.0
PKG_LICENSE_FILES:=

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@ -17,7 +17,8 @@ find_wwan_iface() {
[ -z "$device" -a "$proto" = wwan ] || [ "$device" = "/dev/$DEVNAME" ] || return 0
if [ "$ACTION" = add ]; then
proto_set_available "$cfg" 1
else
fi
if [ "$ACTION" = remove ]; then
proto_set_available "$cfg" 0
fi
exit 0

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@ -12,7 +12,7 @@ start_service() {
procd_open_instance
procd_set_param command "$PROG" ${socket:+-s "$socket"} ${timeout:+-t "$timeout"}
procd_set_param respawn ${respawn_retry:-0}
procd_set_param respawn
procd_close_instance
}

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@ -9,8 +9,6 @@ BOARD:=apm821xx
BOARDNAME:=AppliedMicro APM821xx
CPU_TYPE:=464fp
FEATURES:=fpu dt gpio
MAINTAINER:=Chris Blake <chrisrblake93@gmail.com>, \
Christian Lamparter <chunkeey@gmail.com>
SUBTARGETS:=nand sata
KERNEL_PATCHVER:=4.19

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@ -742,8 +742,13 @@ platform_do_upgrade_mikrotik_rb() {
local fw_mtd=$(find_mtd_part kernel)
fw_mtd="${fw_mtd/block/}"
[ -n "$fw_mtd" ] || return
local board_dir=$(tar tf "$1" | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
[ -n "$board_dir" ] || return
mtd erase kernel
tar xf "$1" sysupgrade-routerboard/kernel -O | nandwrite -o "$fw_mtd" -
tar xf "$1" ${board_dir}/kernel -O | nandwrite -o "$fw_mtd" -
nand_do_upgrade "$1"
}

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@ -9,7 +9,6 @@ include $(TOPDIR)/rules.mk
ARCH:=arc
BOARD:=arc770
BOARDNAME:=Synopsys DesignWare ARC 770D
MAINTAINER:=Alexey Brodkin <abrodkin@synopsys.com>
SUBTARGETS:=generic
KERNEL_PATCHVER:=4.14

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@ -10,7 +10,6 @@ ARCH:=arc
CPU_TYPE:=archs
BOARD:=archs38
BOARDNAME:=Synopsys DesignWare ARC HS38
MAINTAINER:=Alexey Brodkin <abrodkin@synopsys.com>
SUBTARGETS:=generic
KERNEL_PATCHVER:=4.14

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@ -106,7 +106,6 @@ CONFIG_COMMON_CLK_VERSATILE=y
CONFIG_CPU_IDLE=y
# CONFIG_CPU_IDLE_GOV_LADDER is not set
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_CPU_PM=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_BS=y

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@ -10,7 +10,6 @@ BOARD:=armvirt
BOARDNAME:=QEMU ARM Virtual Machine
FEATURES:=fpu pci rtc usb
FEATURES+=cpiogz ext4 ramdisk squashfs targz
MAINTAINER:=Yousong Zhou <yszhou4tech@gmail.com>
KERNEL_PATCHVER:=5.4

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@ -8,8 +8,6 @@ include $(TOPDIR)/rules.mk
ARCH:=arm
BOARD:=at91
MAINTAINER:=Claudio Mignanti <c.mignanti@gmail.com> \
Sandeep Sheriker <sandeep.sheriker@gmail.com>
BOARDNAME:=Microchip (Atmel AT91)
FEATURES:=ext4 squashfs targz usb usbgadget ubifs
SUBTARGETS:=sama5 sam9x

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@ -10,7 +10,6 @@ ARCH:=mips
BOARD:=ath25
BOARDNAME:=Atheros AR231x/AR5312
FEATURES:=squashfs low_mem small_flash
MAINTAINER:=Sergey Ryazanov <ryazanov.s.a@gmail.com>
KERNEL_PATCHVER:=4.14

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@ -4,7 +4,7 @@ ARCH:=mips
BOARD:=ath79
BOARDNAME:=Atheros ATH79 (DTS)
CPU_TYPE:=24kc
SUBTARGETS:=generic nand tiny
SUBTARGETS:=generic mikrotik nand tiny
FEATURES:=ramdisk

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@ -21,7 +21,6 @@ ath79_setup_interfaces()
dlink,dir-505|\
engenius,ecb1750|\
glinet,gl-ar300m-lite|\
mikrotik,routerboard-wap-g-5hact2hnd|\
netgear,ex6400|\
netgear,ex7300|\
ocedo,koala|\

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@ -3,7 +3,6 @@
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions/caldata.sh
. /lib/functions/mikrotik-caldata.sh
board=$(board_name)
@ -42,10 +41,6 @@ case "$FIRMWARE" in
caldata_extract "art" 0x1000 0x440
ath9k_patch_mac $(mtd_get_mac_ascii u-boot-env ethaddr)
;;
mikrotik,routerboard-wap-g-5hact2hnd)
mikrotik_caldata_extract "art" 0x1000 0x440
ath9k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x10) +2)
;;
nec,wg800hp)
caldata_extract "art" 0x1000 0x440
ath9k_patch_mac $(mtd_get_mac_text board_data 0x680)

View File

@ -4,7 +4,6 @@
. /lib/functions/caldata.sh
. /lib/functions/k2t.sh
. /lib/functions/mikrotik-caldata.sh
board=$(board_name)
@ -66,9 +65,6 @@ case "$FIRMWARE" in
caldata_extract "art" 0x5000 0x844
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) +2)
;;
mikrotik,routerboard-wap-g-5hact2hnd)
mikrotik_caldata_extract "art" 0x5000 0x844
;;
nec,wg800hp)
caldata_extract "art" 0x5000 0x844
ath10k_patch_mac $(mtd_get_mac_text board_data 0x880)

View File

@ -11,7 +11,6 @@ CONFIG_MICREL_PHY=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_SPLIT_EVA_FW=y
CONFIG_MTD_SPLIT_MINOR_FW=y
CONFIG_PHY_AR7100_USB=y
CONFIG_PHY_AR7200_USB=y
CONFIG_REGULATOR=y

View File

@ -1,5 +1,5 @@
BOARDNAME:=Generic
FEATURES += minor squashfs
FEATURES += squashfs
DEFAULT_PACKAGES += wpad-basic

View File

@ -73,6 +73,9 @@ include ./generic.mk
include ./generic-tp-link.mk
include ./generic-ubnt.mk
endif
ifeq ($(SUBTARGET),mikrotik)
include ./mikrotik.mk
endif
ifeq ($(SUBTARGET),nand)
include ./nand.mk
endif

View File

@ -1,5 +1,4 @@
include ./common-buffalo.mk
include ./common-mikrotik.mk
include ./common-netgear.mk
include ./common-tp-link.mk
include ./common-yuncore.mk
@ -765,19 +764,6 @@ define Device/librerouter_librerouter-v1
endef
TARGET_DEVICES += librerouter_librerouter-v1
define Device/mikrotik_routerboard-wap-g-5hact2hnd
$(Device/mikrotik)
SOC := qca9556
DEVICE_MODEL := RouterBOARD wAP G-5HacT2HnD (wAP AC)
IMAGE_SIZE := 16256k
IMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 -e | \
pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \
append-metadata | check-size $$$$(IMAGE_SIZE)
DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct
SUPPORTED_DEVICES += rb-wapg-5hact2hnd
endef
TARGET_DEVICES += mikrotik_routerboard-wap-g-5hact2hnd
define Device/nec_wg1200cr
SOC := qca9563
DEVICE_VENDOR := NEC

View File

@ -0,0 +1,26 @@
include ./common-mikrotik.mk
define Device/mikrotik_routerboard-922uags-5hpacd
$(Device/mikrotik)
SOC := qca9558
DEVICE_MODEL := RouterBOARD 922UAGS-5HPacD
IMAGE/sysupgrade.bin = append-kernel | kernel2minor -s 2048 -e -c | \
sysupgrade-tar kernel=$$$$@ | append-metadata
DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct \
kmod-usb2 nand-utils
SUPPORTED_DEVICES += rb-922uags-5hpacd
endef
TARGET_DEVICES += mikrotik_routerboard-922uags-5hpacd
define Device/mikrotik_routerboard-wap-g-5hact2hnd
$(Device/mikrotik)
SOC := qca9556
DEVICE_MODEL := RouterBOARD wAP G-5HacT2HnD (wAP AC)
IMAGE_SIZE := 16256k
IMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 -e | \
pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \
append-metadata | check-size $$$$(IMAGE_SIZE)
DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct
SUPPORTED_DEVICES += rb-wapg-5hact2hnd
endef
TARGET_DEVICES += mikrotik_routerboard-wap-g-5hact2hnd

View File

@ -1,4 +1,3 @@
include ./common-mikrotik.mk
include ./common-netgear.mk # for netgear-uImage
# attention: only zlib compression is allowed for the boot fs
@ -129,19 +128,6 @@ define Device/glinet_gl-ar750s-nor
endef
TARGET_DEVICES += glinet_gl-ar750s-nor
define Device/mikrotik_routerboard-922uags-5hpacd
$(Device/mikrotik)
SOC := qca9558
DEVICE_MODEL := RouterBOARD 922UAGS-5HPacD
BOARD_NAME := routerboard
IMAGE/sysupgrade.bin = append-kernel | kernel2minor -s 2048 -e -c | \
sysupgrade-tar kernel=$$$$@ | append-metadata
DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct \
kmod-usb2 nand-utils
SUPPORTED_DEVICES += rb-922uags-5hpacd
endef
TARGET_DEVICES += mikrotik_routerboard-922uags-5hpacd
# fake rootfs is mandatory, pad-offset 129 equals (2 * uimage_header + 0xff)
define Device/netgear_ath79_nand
DEVICE_VENDOR := NETGEAR

View File

@ -0,0 +1,39 @@
#!/bin/sh
. /lib/functions/system.sh
. /lib/functions/uci-defaults.sh
ath79_setup_interfaces()
{
local board="$1"
case "$board" in
mikrotik,routerboard-922uags-5hpacd|\
mikrotik,routerboard-wap-g-5hact2hnd)
ucidef_set_interface_lan "eth0"
;;
*)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
;;
esac
}
ath79_setup_macs()
{
local board="$1"
case "$board" in
esac
[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
[ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac
}
board_config_update
board=$(board_name)
ath79_setup_interfaces $board
ath79_setup_macs $board
board_config_flush
exit 0

View File

@ -0,0 +1,22 @@
#!/bin/sh
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions/caldata.sh
. /lib/functions/mikrotik-caldata.sh
board=$(board_name)
case "$FIRMWARE" in
"ath9k-eeprom-ahb-18100000.wmac.bin")
case $board in
mikrotik,routerboard-wap-g-5hact2hnd)
mikrotik_caldata_extract "art" 0x1000 0x440
ath9k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x10) +2)
;;
*)
caldata_die "board $board is not supported yet"
;;
esac
;;
esac

View File

@ -0,0 +1,28 @@
#!/bin/sh
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions/caldata.sh
. /lib/functions/mikrotik-caldata.sh
board=$(board_name)
case "$FIRMWARE" in
"ath10k/cal-pci-0000:00:00.0.bin")
case $board in
mikrotik,routerboard-wap-g-5hact2hnd)
mikrotik_caldata_extract "art" 0x5000 0x844
;;
esac
;;
"ath10k/cal-pci-0000:01:00.0.bin")
case $board in
mikrotik,routerboard-922uags-5hpacd)
mikrotik_caldata_extract "art" 0x5000 0x844
;;
esac
;;
*)
exit 1
;;
esac

View File

@ -0,0 +1,41 @@
# Copyright (C) 2011 OpenWrt.org
PART_NAME=firmware
REQUIRE_IMAGE_METADATA=1
platform_check_image() {
return 0
}
RAMFS_COPY_BIN='fw_printenv fw_setenv nandwrite'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
platform_do_upgrade_mikrotik_nand() {
CI_KERNPART=none
local fw_mtd=$(find_mtd_part kernel)
fw_mtd="${fw_mtd/block/}"
[ -n "$fw_mtd" ] || return
local board_dir=$(tar tf "$1" | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
[ -n "$board_dir" ] || return
mtd erase kernel
tar xf "$1" ${board_dir}/kernel -O | nandwrite -o "$fw_mtd" -
nand_do_upgrade "$1"
}
platform_do_upgrade() {
local board=$(board_name)
case "$board" in
mikrotik,routerboard-922uags-5hpacd)
platform_do_upgrade_mikrotik_nand "$1"
;;
*)
default_do_upgrade "$1"
;;
esac
}

View File

@ -0,0 +1,33 @@
CONFIG_AT803X_PHY=y
CONFIG_CRC16=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_GPIO_LATCH=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_LEDS_RESET=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_AR934X=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_MTD_SPLIT_MINOR_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_PHY_AR7100_USB=y
CONFIG_PHY_AR7200_USB=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_WATCHDOG_CORE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

View File

@ -0,0 +1,18 @@
#
# Copyright (C) 2020 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
define Profile/Default
NAME:=Default Profile (all drivers)
PACKAGES:= \
kmod-usb-ohci kmod-usb2 nand-utils
PRIORITY := 1
endef
define Profile/Default/Description
Default package set compatible with most boards.
endef
$(eval $(call Profile,Default))

View File

@ -0,0 +1,9 @@
BOARDNAME := MikroTik devices
FEATURES += minor nand squashfs
DEFAULT_PACKAGES += wpad-basic
define Target/Description
Build firmware images for MikroTik devices based on Qualcomm Atheros
MIPS SoCs (AR71xx, AR72xx, AR91xx, AR93xx, QCA95xx).
endef

View File

@ -8,8 +8,7 @@ ath79_setup_interfaces()
local board="$1"
case "$board" in
aerohive,hiveap-121|\
mikrotik,routerboard-922uags-5hpacd)
aerohive,hiveap-121)
ucidef_set_interface_lan "eth0"
;;
domywifi,dw33d)

View File

@ -3,7 +3,6 @@
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions/caldata.sh
. /lib/functions/mikrotik-caldata.sh
board=$(board_name)
@ -25,13 +24,6 @@ case "$FIRMWARE" in
;;
esac
;;
"ath10k/cal-pci-0000:01:00.0.bin")
case $board in
mikrotik,routerboard-922uags-5hpacd)
mikrotik_caldata_extract "art" 0x5000 0x844
;;
esac
;;
*)
exit 1
;;

View File

@ -10,24 +10,10 @@ platform_check_image() {
RAMFS_COPY_BIN='fw_printenv fw_setenv nandwrite'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
platform_do_upgrade_mikrotik_nand() {
CI_KERNPART=none
local fw_mtd=$(find_mtd_part kernel)
fw_mtd="${fw_mtd/block/}"
[ -n "$fw_mtd" ] || return
mtd erase kernel
tar xf "$1" sysupgrade-routerboard/kernel -O | nandwrite -o "$fw_mtd" -
nand_do_upgrade "$1"
}
platform_do_upgrade() {
local board=$(board_name)
case "$board" in
mikrotik,routerboard-922uags-5hpacd)
platform_do_upgrade_mikrotik_nand "$1"
;;
glinet,gl-ar300m-nand|\
glinet,gl-ar300m-nor)
glinet_nand_nor_do_upgrade "$1"

View File

@ -10,7 +10,6 @@ CONFIG_MTD_NAND_AR934X=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPLIT_MINOR_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y

View File

@ -1,6 +1,6 @@
BOARDNAME := Generic devices with NAND flash
FEATURES += squashfs nand minor
FEATURES += squashfs nand
DEFAULT_PACKAGES += wpad-basic

View File

@ -11,11 +11,9 @@ ARCH:=arm
BOARD:=bcm27xx
BOARDNAME:=Broadcom BCM27xx
FEATURES:=ext4 audio usb usbgadget display gpio fpu squashfs rootfs-part boot-part
MAINTAINER:=Álvaro Fernández Rojas <noltari@gmail.com>
SUBTARGETS:=bcm2708 bcm2709 bcm2710 bcm2711
KERNEL_PATCHVER:=4.19
KERNEL_TESTING_PATCHVER=5.4
KERNEL_PATCHVER=5.4
define Target/Description
Build firmware image for Broadcom BCM27xx SoC devices.

View File

@ -123,7 +123,6 @@ CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_CPU_PABRT_V6=y
CONFIG_CPU_PM=y
# CONFIG_CPU_THERMAL is not set
@ -184,7 +183,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FREEZER=y
# CONFIG_FSL_QDMA is not set
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FS_POSIX_ACL=y
@ -286,10 +284,7 @@ CONFIG_MAX_RAW_DEVS=256
CONFIG_MEMFD_CREATE=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_MFD_CORE=y
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ROHM_BD70528 is not set
# CONFIG_MFD_RPISENSE_CORE is not set
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y

View File

@ -30,14 +30,12 @@ CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_ARCH_MILBEAUT is not set
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
# CONFIG_ARCH_RDA is not set
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
@ -52,9 +50,6 @@ CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_BCM2835_CPUFREQ is not set
CONFIG_ARM_CPU_SUSPEND=y
# CONFIG_ARM_ERRATA_814220 is not set
# CONFIG_ARM_ERRATA_857271 is not set
# CONFIG_ARM_ERRATA_857272 is not set
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_L1_CACHE_SHIFT=6
@ -154,7 +149,6 @@ CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
@ -212,7 +206,6 @@ CONFIG_DUMMY_CONSOLE=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_ENERGY_MODEL is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
@ -242,7 +235,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FREEZER=y
# CONFIG_FSL_QDMA is not set
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
@ -277,7 +269,6 @@ CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_BCM_VIRT=y
CONFIG_GPIO_RASPBERRYPI_EXP=y
CONFIG_GPIO_SYSFS=y
# CONFIG_GVE is not set
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
@ -370,10 +361,7 @@ CONFIG_MDIO_DEVICE=y
CONFIG_MEMFD_CREATE=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_MFD_CORE=y
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ROHM_BD70528 is not set
# CONFIG_MFD_RPISENSE_CORE is not set
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_SYSCON=y
CONFIG_MICROCHIP_PHY=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
@ -427,11 +415,9 @@ CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_BRCMSTB=y
# CONFIG_PCIE_BW is not set
CONFIG_PCIE_PME=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
# CONFIG_PCI_MESON is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PERF_USE_VMALLOC=y
@ -512,7 +498,6 @@ CONFIG_TIMER_PROBE=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
# CONFIG_TRUSTED_FOUNDATIONS is not set
CONFIG_UEVENT_HELPER_PATH=""
# CONFIG_UID16 is not set
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"

View File

@ -157,6 +157,7 @@ CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BOUNCE=y
CONFIG_BRCMSTB_THERMAL=y
CONFIG_BRCM_CHAR_DRIVERS=y
CONFIG_CAVIUM_ERRATUM_22375=y
@ -202,7 +203,6 @@ CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
# CONFIG_CPU_THERMAL is not set
@ -253,7 +253,6 @@ CONFIG_DUMMY_CONSOLE=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EFI_EARLYCON=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_ENERGY_MODEL is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
@ -283,7 +282,6 @@ CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FRAME_POINTER=y
CONFIG_FREEZER=y
CONFIG_FSL_ERRATUM_A008585=y
# CONFIG_FSL_QDMA is not set
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
@ -323,7 +321,6 @@ CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_BCM_VIRT=y
CONFIG_GPIO_RASPBERRYPI_EXP=y
CONFIG_GPIO_SYSFS=y
# CONFIG_GVE is not set
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
@ -446,10 +443,7 @@ CONFIG_MEMFD_CREATE=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_MEMORY_ISOLATION=y
CONFIG_MFD_CORE=y
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ROHM_BD70528 is not set
# CONFIG_MFD_RPISENSE_CORE is not set
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_SYSCON=y
CONFIG_MICROCHIP_PHY=y
CONFIG_MIGRATION=y
@ -481,7 +475,6 @@ CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
# CONFIG_NUMA is not set
CONFIG_NVMEM=y
# CONFIG_NVMEM_REBOOT_MODE is not set
# CONFIG_OCTEONTX2_AF is not set
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
@ -503,7 +496,6 @@ CONFIG_PCI=y
# CONFIG_PCIE_BRCMSTB is not set
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
# CONFIG_PCI_MESON is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PGTABLE_LEVELS=3

View File

@ -160,6 +160,7 @@ CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BOUNCE=y
CONFIG_BRCMSTB_THERMAL=y
CONFIG_BRCM_CHAR_DRIVERS=y
CONFIG_BROADCOM_PHY=y
@ -206,7 +207,6 @@ CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
# CONFIG_CPU_THERMAL is not set
@ -258,7 +258,6 @@ CONFIG_DUMMY_CONSOLE=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EFI_EARLYCON=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_ENERGY_MODEL is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
@ -288,7 +287,6 @@ CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FRAME_POINTER=y
CONFIG_FREEZER=y
CONFIG_FSL_ERRATUM_A008585=y
# CONFIG_FSL_QDMA is not set
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
@ -329,7 +327,6 @@ CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_BCM_VIRT=y
CONFIG_GPIO_RASPBERRYPI_EXP=y
CONFIG_GPIO_SYSFS=y
# CONFIG_GVE is not set
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
@ -453,10 +450,7 @@ CONFIG_MEMFD_CREATE=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_MEMORY_ISOLATION=y
CONFIG_MFD_CORE=y
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ROHM_BD70528 is not set
# CONFIG_MFD_RPISENSE_CORE is not set
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
@ -487,7 +481,6 @@ CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
# CONFIG_NUMA is not set
CONFIG_NVMEM=y
# CONFIG_NVMEM_REBOOT_MODE is not set
# CONFIG_OCTEONTX2_AF is not set
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
@ -509,11 +502,9 @@ CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIE_AL is not set
CONFIG_PCIE_BRCMSTB=y
# CONFIG_PCIE_BW is not set
CONFIG_PCIE_PME=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
# CONFIG_PCI_MESON is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PGTABLE_LEVELS=3

View File

@ -1,569 +0,0 @@
From d45590eb858ac7a2578d477791881ba7ffb1e615 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 19 Feb 2019 22:06:59 +0000
Subject: [PATCH] PCI: brcmstb: Add dma-range mapping for inbound
traffic
The Broadcom STB PCIe host controller is intimately related to the
memory subsystem. This close relationship adds complexity to how cpu
system memory is mapped to PCIe memory. Ideally, this mapping is an
identity mapping, or an identity mapping off by a constant. Not so in
this case.
Consider the Broadcom reference board BCM97445LCC_4X8 which has 6 GB
of system memory. Here is how the PCIe controller maps the
system memory to PCIe memory:
memc0-a@[ 0....3fffffff] <=> pci@[ 0....3fffffff]
memc0-b@[100000000...13fffffff] <=> pci@[ 40000000....7fffffff]
memc1-a@[ 40000000....7fffffff] <=> pci@[ 80000000....bfffffff]
memc1-b@[300000000...33fffffff] <=> pci@[ c0000000....ffffffff]
memc2-a@[ 80000000....bfffffff] <=> pci@[100000000...13fffffff]
memc2-b@[c00000000...c3fffffff] <=> pci@[140000000...17fffffff]
Although there are some "gaps" that can be added between the
individual mappings by software, the permutation of memory regions for
the most part is fixed by HW. The solution of having something close
to an identity mapping is not possible.
The idea behind this HW design is that the same PCIe module can
act as an RC or EP, and if it acts as an EP it concatenates all
of system memory into a BAR so anything can be accessed. Unfortunately,
when the PCIe block is in the role of an RC it also presents this
"BAR" to downstream PCIe devices, rather than offering an identity map
between its system memory and PCIe space.
Suppose that an endpoint driver allocs some DMA memory. Suppose this
memory is located at 0x6000_0000, which is in the middle of memc1-a.
The driver wants a dma_addr_t value that it can pass on to the EP to
use. Without doing any custom mapping, the EP will use this value for
DMA: the driver will get a dma_addr_t equal to 0x6000_0000. But this
won't work; the device needs a dma_addr_t that reflects the PCIe space
address, namely 0xa000_0000.
So, essentially the solution to this problem must modify the
dma_addr_t returned by the DMA routines routines. There are two
ways (I know of) of doing this:
(a) overriding/redefining the dma_to_phys() and phys_to_dma() calls
that are used by the dma_ops routines. This is the approach of
arch/mips/cavium-octeon/dma-octeon.c
In ARM and ARM64 these two routines are defiend in asm/dma-mapping.h
as static inline functions.
(b) Subscribe to a notifier that notifies when a device is added to a
bus. When this happens, set_dma_ops() can be called for the device.
This method is mentioned in:
http://lxr.free-electrons.com/source/drivers/of/platform.c?v=3.16#L152
where it says as a comment
"In case if platform code need to use own special DMA
configuration, it can use Platform bus notifier and
handle BUS_NOTIFY_ADD_DEVICE event to fix up DMA
configuration."
Solution (b) is what this commit does. It uses its own set of
dma_ops which are wrappers around the arch_dma_ops. The
wrappers translate the dma addresses before/after invoking
the arch_dma_ops, as appropriate.
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
drivers/pci/controller/pcie-brcmstb.c | 420 +++++++++++++++++++++++++-
1 file changed, 411 insertions(+), 9 deletions(-)
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -4,6 +4,7 @@
#include <linux/clk.h>
#include <linux/compiler.h>
#include <linux/delay.h>
+#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
@@ -319,11 +320,307 @@ static struct pci_ops brcm_pcie_ops = {
((val & ~reg##_##field##_MASK) | \
(reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
+static const struct dma_map_ops *arch_dma_ops;
+static const struct dma_map_ops *brcm_dma_ops_ptr;
+static struct of_pci_range *dma_ranges;
+static int num_dma_ranges;
+
static phys_addr_t scb_size[BRCM_MAX_SCB];
static int num_memc;
static int num_pcie;
static DEFINE_MUTEX(brcm_pcie_lock);
+static dma_addr_t brcm_to_pci(dma_addr_t addr)
+{
+ struct of_pci_range *p;
+
+ if (!num_dma_ranges)
+ return addr;
+
+ for (p = dma_ranges; p < &dma_ranges[num_dma_ranges]; p++)
+ if (addr >= p->cpu_addr && addr < (p->cpu_addr + p->size))
+ return addr - p->cpu_addr + p->pci_addr;
+
+ return addr;
+}
+
+static dma_addr_t brcm_to_cpu(dma_addr_t addr)
+{
+ struct of_pci_range *p;
+
+ if (!num_dma_ranges)
+ return addr;
+
+ for (p = dma_ranges; p < &dma_ranges[num_dma_ranges]; p++)
+ if (addr >= p->pci_addr && addr < (p->pci_addr + p->size))
+ return addr - p->pci_addr + p->cpu_addr;
+
+ return addr;
+}
+
+static void *brcm_alloc(struct device *dev, size_t size, dma_addr_t *handle,
+ gfp_t gfp, unsigned long attrs)
+{
+ void *ret;
+
+ ret = arch_dma_ops->alloc(dev, size, handle, gfp, attrs);
+ if (ret)
+ *handle = brcm_to_pci(*handle);
+ return ret;
+}
+
+static void brcm_free(struct device *dev, size_t size, void *cpu_addr,
+ dma_addr_t handle, unsigned long attrs)
+{
+ handle = brcm_to_cpu(handle);
+ arch_dma_ops->free(dev, size, cpu_addr, handle, attrs);
+}
+
+static int brcm_mmap(struct device *dev, struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t dma_addr, size_t size,
+ unsigned long attrs)
+{
+ dma_addr = brcm_to_cpu(dma_addr);
+ return arch_dma_ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
+}
+
+static int brcm_get_sgtable(struct device *dev, struct sg_table *sgt,
+ void *cpu_addr, dma_addr_t handle, size_t size,
+ unsigned long attrs)
+{
+ handle = brcm_to_cpu(handle);
+ return arch_dma_ops->get_sgtable(dev, sgt, cpu_addr, handle, size,
+ attrs);
+}
+
+static dma_addr_t brcm_map_page(struct device *dev, struct page *page,
+ unsigned long offset, size_t size,
+ enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ return brcm_to_pci(arch_dma_ops->map_page(dev, page, offset, size,
+ dir, attrs));
+}
+
+static void brcm_unmap_page(struct device *dev, dma_addr_t handle,
+ size_t size, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ handle = brcm_to_cpu(handle);
+ arch_dma_ops->unmap_page(dev, handle, size, dir, attrs);
+}
+
+static int brcm_map_sg(struct device *dev, struct scatterlist *sgl,
+ int nents, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ int i, j;
+ struct scatterlist *sg;
+
+ for_each_sg(sgl, sg, nents, i) {
+#ifdef CONFIG_NEED_SG_DMA_LENGTH
+ sg->dma_length = sg->length;
+#endif
+ sg->dma_address =
+ brcm_dma_ops_ptr->map_page(dev, sg_page(sg), sg->offset,
+ sg->length, dir, attrs);
+ if (dma_mapping_error(dev, sg->dma_address))
+ goto bad_mapping;
+ }
+ return nents;
+
+bad_mapping:
+ for_each_sg(sgl, sg, i, j)
+ brcm_dma_ops_ptr->unmap_page(dev, sg_dma_address(sg),
+ sg_dma_len(sg), dir, attrs);
+ return 0;
+}
+
+static void brcm_unmap_sg(struct device *dev,
+ struct scatterlist *sgl, int nents,
+ enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ int i;
+ struct scatterlist *sg;
+
+ for_each_sg(sgl, sg, nents, i)
+ brcm_dma_ops_ptr->unmap_page(dev, sg_dma_address(sg),
+ sg_dma_len(sg), dir, attrs);
+}
+
+static void brcm_sync_single_for_cpu(struct device *dev,
+ dma_addr_t handle, size_t size,
+ enum dma_data_direction dir)
+{
+ handle = brcm_to_cpu(handle);
+ arch_dma_ops->sync_single_for_cpu(dev, handle, size, dir);
+}
+
+static void brcm_sync_single_for_device(struct device *dev,
+ dma_addr_t handle, size_t size,
+ enum dma_data_direction dir)
+{
+ handle = brcm_to_cpu(handle);
+ arch_dma_ops->sync_single_for_device(dev, handle, size, dir);
+}
+
+static dma_addr_t brcm_map_resource(struct device *dev, phys_addr_t phys,
+ size_t size,
+ enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ if (arch_dma_ops->map_resource)
+ return brcm_to_pci(arch_dma_ops->map_resource
+ (dev, phys, size, dir, attrs));
+ return brcm_to_pci((dma_addr_t)phys);
+}
+
+static void brcm_unmap_resource(struct device *dev, dma_addr_t handle,
+ size_t size, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ if (arch_dma_ops->unmap_resource)
+ arch_dma_ops->unmap_resource(dev, brcm_to_cpu(handle), size,
+ dir, attrs);
+}
+
+void brcm_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl,
+ int nents, enum dma_data_direction dir)
+{
+ struct scatterlist *sg;
+ int i;
+
+ for_each_sg(sgl, sg, nents, i)
+ brcm_dma_ops_ptr->sync_single_for_cpu(dev, sg_dma_address(sg),
+ sg->length, dir);
+}
+
+void brcm_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
+ int nents, enum dma_data_direction dir)
+{
+ struct scatterlist *sg;
+ int i;
+
+ for_each_sg(sgl, sg, nents, i)
+ brcm_dma_ops_ptr->sync_single_for_device(dev,
+ sg_dma_address(sg),
+ sg->length, dir);
+}
+
+static int brcm_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+ return arch_dma_ops->mapping_error(dev, dma_addr);
+}
+
+static int brcm_dma_supported(struct device *dev, u64 mask)
+{
+ if (num_dma_ranges) {
+ /*
+ * It is our translated addresses that the EP will "see", so
+ * we check all of the ranges for the largest possible value.
+ */
+ int i;
+
+ for (i = 0; i < num_dma_ranges; i++)
+ if (dma_ranges[i].pci_addr + dma_ranges[i].size - 1
+ > mask)
+ return 0;
+ return 1;
+ }
+
+ return arch_dma_ops->dma_supported(dev, mask);
+}
+
+#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
+u64 brcm_get_required_mask)(struct device *dev)
+{
+ return arch_dma_ops->get_required_mask(dev);
+}
+#endif
+
+static const struct dma_map_ops brcm_dma_ops = {
+ .alloc = brcm_alloc,
+ .free = brcm_free,
+ .mmap = brcm_mmap,
+ .get_sgtable = brcm_get_sgtable,
+ .map_page = brcm_map_page,
+ .unmap_page = brcm_unmap_page,
+ .map_sg = brcm_map_sg,
+ .unmap_sg = brcm_unmap_sg,
+ .map_resource = brcm_map_resource,
+ .unmap_resource = brcm_unmap_resource,
+ .sync_single_for_cpu = brcm_sync_single_for_cpu,
+ .sync_single_for_device = brcm_sync_single_for_device,
+ .sync_sg_for_cpu = brcm_sync_sg_for_cpu,
+ .sync_sg_for_device = brcm_sync_sg_for_device,
+ .mapping_error = brcm_mapping_error,
+ .dma_supported = brcm_dma_supported,
+#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
+ .get_required_mask = brcm_get_required_mask,
+#endif
+};
+
+static void brcm_set_dma_ops(struct device *dev)
+{
+ int ret;
+
+ if (IS_ENABLED(CONFIG_ARM64)) {
+ /*
+ * We are going to invoke get_dma_ops(). That
+ * function, at this point in time, invokes
+ * get_arch_dma_ops(), and for ARM64 that function
+ * returns a pointer to dummy_dma_ops. So then we'd
+ * like to call arch_setup_dma_ops(), but that isn't
+ * exported. Instead, we call of_dma_configure(),
+ * which is exported, and this calls
+ * arch_setup_dma_ops(). Once we do this the call to
+ * get_dma_ops() will work properly because
+ * dev->dma_ops will be set.
+ */
+ ret = of_dma_configure(dev, dev->of_node, true);
+ if (ret) {
+ dev_err(dev, "of_dma_configure() failed: %d\n", ret);
+ return;
+ }
+ }
+
+ arch_dma_ops = get_dma_ops(dev);
+ if (!arch_dma_ops) {
+ dev_err(dev, "failed to get arch_dma_ops\n");
+ return;
+ }
+
+ set_dma_ops(dev, &brcm_dma_ops);
+}
+
+static int brcmstb_platform_notifier(struct notifier_block *nb,
+ unsigned long event, void *__dev)
+{
+ struct device *dev = __dev;
+
+ brcm_dma_ops_ptr = &brcm_dma_ops;
+ if (event != BUS_NOTIFY_ADD_DEVICE)
+ return NOTIFY_DONE;
+
+ brcm_set_dma_ops(dev);
+ return NOTIFY_OK;
+}
+
+static struct notifier_block brcmstb_platform_nb = {
+ .notifier_call = brcmstb_platform_notifier,
+};
+
+static int brcm_register_notifier(void)
+{
+ return bus_register_notifier(&pci_bus_type, &brcmstb_platform_nb);
+}
+
+static int brcm_unregister_notifier(void)
+{
+ return bus_unregister_notifier(&pci_bus_type, &brcmstb_platform_nb);
+}
+
static u32 rd_fld(void __iomem *p, u32 mask, int shift)
{
return (bcm_readl(p) & mask) >> shift;
@@ -597,9 +894,71 @@ static inline void brcm_pcie_perst_set(s
WR_FLD_RB(pcie->base, PCIE_MISC_PCIE_CTRL, PCIE_PERSTB, !val);
}
+static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
+ struct device_node *node)
+{
+ const int na = 3, ns = 2;
+ int rlen;
+
+ parser->node = node;
+ parser->pna = of_n_addr_cells(node);
+ parser->np = parser->pna + na + ns;
+
+ parser->range = of_get_property(node, "dma-ranges", &rlen);
+ if (!parser->range)
+ return -ENOENT;
+
+ parser->end = parser->range + rlen / sizeof(__be32);
+
+ return 0;
+}
+
+static int brcm_pcie_parse_map_dma_ranges(struct brcm_pcie *pcie)
+{
+ int i;
+ struct of_pci_range_parser parser;
+ struct device_node *dn = pcie->dn;
+
+ /*
+ * Parse dma-ranges property if present. If there are multiple
+ * PCIe controllers, we only have to parse from one of them since
+ * the others will have an identical mapping.
+ */
+ if (!pci_dma_range_parser_init(&parser, dn)) {
+ unsigned int max_ranges
+ = (parser.end - parser.range) / parser.np;
+
+ dma_ranges = kcalloc(max_ranges, sizeof(struct of_pci_range),
+ GFP_KERNEL);
+ if (!dma_ranges)
+ return -ENOMEM;
+
+ for (i = 0; of_pci_range_parser_one(&parser, dma_ranges + i);
+ i++)
+ num_dma_ranges++;
+ }
+
+ for (i = 0, num_memc = 0; i < BRCM_MAX_SCB; i++) {
+ u64 size = brcmstb_memory_memc_size(i);
+
+ if (size == (u64)-1) {
+ dev_err(pcie->dev, "cannot get memc%d size", i);
+ return -EINVAL;
+ } else if (size) {
+ scb_size[i] = roundup_pow_of_two_64(size);
+ num_memc++;
+ } else {
+ break;
+ }
+ }
+
+ return 0;
+}
+
static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
{
int i, ret = 0;
+ struct device *dev = pcie->dev;
mutex_lock(&brcm_pcie_lock);
if (num_pcie > 0) {
@@ -607,12 +966,21 @@ static int brcm_pcie_add_controller(stru
goto done;
}
+ ret = brcm_register_notifier();
+ if (ret) {
+ dev_err(dev, "failed to register pci bus notifier\n");
+ goto done;
+ }
+ ret = brcm_pcie_parse_map_dma_ranges(pcie);
+ if (ret)
+ goto done;
+
/* Determine num_memc and their sizes */
for (i = 0, num_memc = 0; i < BRCM_MAX_SCB; i++) {
u64 size = brcmstb_memory_memc_size(i);
if (size == (u64)-1) {
- dev_err(pcie->dev, "cannot get memc%d size\n", i);
+ dev_err(dev, "cannot get memc%d size\n", i);
ret = -EINVAL;
goto done;
} else if (size) {
@@ -636,8 +1004,16 @@ done:
static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
{
mutex_lock(&brcm_pcie_lock);
- if (--num_pcie == 0)
- num_memc = 0;
+ if (--num_pcie > 0)
+ goto out;
+
+ if (brcm_unregister_notifier())
+ dev_err(pcie->dev, "failed to unregister pci bus notifier\n");
+ kfree(dma_ranges);
+ dma_ranges = NULL;
+ num_dma_ranges = 0;
+ num_memc = 0;
+out:
mutex_unlock(&brcm_pcie_lock);
}
@@ -757,6 +1133,38 @@ static int brcm_pcie_setup(struct brcm_p
*/
rc_bar2_offset = 0;
+ if (dma_ranges) {
+ /*
+ * The best-case scenario is to place the inbound
+ * region in the first 4GB of pci-space, as some
+ * legacy devices can only address 32bits.
+ * We would also like to put the MSI under 4GB
+ * as well, since some devices require a 32bit
+ * MSI target address.
+ */
+ if (total_mem_size <= 0xc0000000ULL &&
+ rc_bar2_size <= 0x100000000ULL) {
+ rc_bar2_offset = 0;
+ } else {
+ /*
+ * The system memory is 4GB or larger so we
+ * cannot start the inbound region at location
+ * 0 (since we have to allow some space for
+ * outbound memory @ 3GB). So instead we
+ * start it at the 1x multiple of its size
+ */
+ rc_bar2_offset = rc_bar2_size;
+ }
+
+ } else {
+ /*
+ * Set simple configuration based on memory sizes
+ * only. We always start the viewport at address 0,
+ * and set the MSI target address accordingly.
+ */
+ rc_bar2_offset = 0;
+ }
+
tmp = lower_32_bits(rc_bar2_offset);
tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
encode_ibar_size(rc_bar2_size));
@@ -967,7 +1375,6 @@ static int brcm_pcie_probe(struct platfo
struct brcm_pcie *pcie;
struct resource *res;
void __iomem *base;
- u32 tmp;
struct pci_host_bridge *bridge;
struct pci_bus *child;
@@ -984,11 +1391,6 @@ static int brcm_pcie_probe(struct platfo
return -EINVAL;
}
- if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
- dev_err(&pdev->dev, "cannot yet handle dma-ranges\n");
- return -EINVAL;
- }
-
data = of_id->data;
pcie->reg_offsets = data->offsets;
pcie->reg_field_info = data->reg_field_info;

View File

@ -1,543 +0,0 @@
From b1619c83208e7b804e2c3547dbf24bb02b3be239 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 19 Feb 2019 22:06:59 +0000
Subject: [PATCH] PCI: brcmstb: Add MSI capability
This commit adds MSI to the Broadcom STB PCIe host controller. It does
not add MSIX since that functionality is not in the HW. The MSI
controller is physically located within the PCIe block, however, there
is no reason why the MSI controller could not be moved elsewhere in
the future.
Since the internal Brcmstb MSI controller is intertwined with the PCIe
controller, it is not its own platform device but rather part of the
PCIe platform device.
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
drivers/pci/controller/pcie-brcmstb.c | 374 ++++++++++++++++++++++++--
1 file changed, 353 insertions(+), 21 deletions(-)
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2009 - 2017 Broadcom */
+#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/compiler.h>
#include <linux/delay.h>
@@ -9,11 +10,13 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/log2.h>
#include <linux/module.h>
+#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
@@ -47,6 +50,9 @@
#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
+#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
+#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
+#define PCIE_MISC_MSI_DATA_CONFIG 0x404c
#define PCIE_MISC_PCIE_CTRL 0x4064
#define PCIE_MISC_PCIE_STATUS 0x4068
#define PCIE_MISC_REVISION 0x406c
@@ -55,6 +61,7 @@
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
#define PCIE_INTR2_CPU_BASE 0x4300
+#define PCIE_MSI_INTR2_BASE 0x4500
/*
* Broadcom Settop Box PCIe Register Field shift and mask info. The
@@ -115,6 +122,8 @@
#define BRCM_NUM_PCIE_OUT_WINS 0x4
#define BRCM_MAX_SCB 0x4
+#define BRCM_INT_PCI_MSI_NR 32
+#define BRCM_PCIE_HW_REV_33 0x0303
#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
@@ -203,6 +212,33 @@ struct brcm_window {
dma_addr_t size;
};
+struct brcm_msi {
+ struct device *dev;
+ void __iomem *base;
+ struct device_node *dn;
+ struct irq_domain *msi_domain;
+ struct irq_domain *inner_domain;
+ struct mutex lock; /* guards the alloc/free operations */
+ u64 target_addr;
+ int irq;
+
+ /* intr_base is the base pointer for interrupt status/set/clr regs */
+ void __iomem *intr_base;
+
+ /* intr_legacy_mask indicates how many bits are MSI interrupts */
+ u32 intr_legacy_mask;
+
+ /*
+ * intr_legacy_offset indicates bit position of MSI_01. It is
+ * to map the register bit position to a hwirq that starts at 0.
+ */
+ u32 intr_legacy_offset;
+
+ /* used indicates which MSI interrupts have been alloc'd */
+ unsigned long used;
+ unsigned int rev;
+};
+
/* Internal PCIe Host Controller Information.*/
struct brcm_pcie {
struct device *dev;
@@ -217,7 +253,10 @@ struct brcm_pcie {
int num_out_wins;
bool ssc;
int gen;
+ u64 msi_target_addr;
struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
+ struct brcm_msi *msi;
+ bool msi_internal;
unsigned int rev;
const int *reg_offsets;
const int *reg_field_info;
@@ -225,9 +264,9 @@ struct brcm_pcie {
};
struct pcie_cfg_data {
- const int *reg_field_info;
- const int *offsets;
- const enum pcie_type type;
+ const int *reg_field_info;
+ const int *offsets;
+ const enum pcie_type type;
};
static const int pcie_reg_field_info[] = {
@@ -828,6 +867,267 @@ static void brcm_pcie_set_outbound_win(s
}
}
+static struct irq_chip brcm_msi_irq_chip = {
+ .name = "Brcm_MSI",
+ .irq_mask = pci_msi_mask_irq,
+ .irq_unmask = pci_msi_unmask_irq,
+};
+
+static struct msi_domain_info brcm_msi_domain_info = {
+ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+ MSI_FLAG_PCI_MSIX),
+ .chip = &brcm_msi_irq_chip,
+};
+
+static void brcm_pcie_msi_isr(struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct brcm_msi *msi;
+ unsigned long status, virq;
+ u32 mask, bit, hwirq;
+ struct device *dev;
+
+ chained_irq_enter(chip, desc);
+ msi = irq_desc_get_handler_data(desc);
+ mask = msi->intr_legacy_mask;
+ dev = msi->dev;
+
+ while ((status = bcm_readl(msi->intr_base + STATUS) & mask)) {
+ for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) {
+ /* clear the interrupt */
+ bcm_writel(1 << bit, msi->intr_base + CLR);
+
+ /* Account for legacy interrupt offset */
+ hwirq = bit - msi->intr_legacy_offset;
+
+ virq = irq_find_mapping(msi->inner_domain, hwirq);
+ if (virq) {
+ if (msi->used & (1 << hwirq))
+ generic_handle_irq(virq);
+ else
+ dev_info(dev, "unhandled MSI %d\n",
+ hwirq);
+ } else {
+ /* Unknown MSI, just clear it */
+ dev_dbg(dev, "unexpected MSI\n");
+ }
+ }
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static void brcm_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+ struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
+ u32 temp;
+
+ msg->address_lo = lower_32_bits(msi->target_addr);
+ msg->address_hi = upper_32_bits(msi->target_addr);
+ temp = bcm_readl(msi->base + PCIE_MISC_MSI_DATA_CONFIG);
+ msg->data = ((temp >> 16) & (temp & 0xffff)) | data->hwirq;
+}
+
+static int brcm_msi_set_affinity(struct irq_data *irq_data,
+ const struct cpumask *mask, bool force)
+{
+ return -EINVAL;
+}
+
+static struct irq_chip brcm_msi_bottom_irq_chip = {
+ .name = "Brcm_MSI",
+ .irq_compose_msi_msg = brcm_compose_msi_msg,
+ .irq_set_affinity = brcm_msi_set_affinity,
+};
+
+static int brcm_msi_alloc(struct brcm_msi *msi)
+{
+ int bit, hwirq;
+
+ mutex_lock(&msi->lock);
+ bit = ~msi->used ? ffz(msi->used) : -1;
+
+ if (bit >= 0 && bit < BRCM_INT_PCI_MSI_NR) {
+ msi->used |= (1 << bit);
+ hwirq = bit - msi->intr_legacy_offset;
+ } else {
+ hwirq = -ENOSPC;
+ }
+
+ mutex_unlock(&msi->lock);
+ return hwirq;
+}
+
+static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
+{
+ mutex_lock(&msi->lock);
+ msi->used &= ~(1 << (hwirq + msi->intr_legacy_offset));
+ mutex_unlock(&msi->lock);
+}
+
+static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *args)
+{
+ struct brcm_msi *msi = domain->host_data;
+ int hwirq;
+
+ hwirq = brcm_msi_alloc(msi);
+
+ if (hwirq < 0)
+ return hwirq;
+
+ irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
+ &brcm_msi_bottom_irq_chip, domain->host_data,
+ handle_simple_irq, NULL, NULL);
+ return 0;
+}
+
+static void brcm_irq_domain_free(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs)
+{
+ struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+ struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
+
+ brcm_msi_free(msi, d->hwirq);
+}
+
+static void brcm_msi_set_regs(struct brcm_msi *msi)
+{
+ u32 data_val, msi_lo, msi_hi;
+
+ if (msi->rev >= BRCM_PCIE_HW_REV_33) {
+ /*
+ * ffe0 -- least sig 5 bits are 0 indicating 32 msgs
+ * 6540 -- this is our arbitrary unique data value
+ */
+ data_val = 0xffe06540;
+ } else {
+ /*
+ * fff8 -- least sig 3 bits are 0 indicating 8 msgs
+ * 6540 -- this is our arbitrary unique data value
+ */
+ data_val = 0xfff86540;
+ }
+
+ /*
+ * Make sure we are not masking MSIs. Note that MSIs can be masked,
+ * but that occurs on the PCIe EP device
+ */
+ bcm_writel(0xffffffff & msi->intr_legacy_mask,
+ msi->intr_base + MASK_CLR);
+
+ msi_lo = lower_32_bits(msi->target_addr);
+ msi_hi = upper_32_bits(msi->target_addr);
+ /*
+ * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
+ * enable, which we set to 1.
+ */
+ bcm_writel(msi_lo | 1, msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
+ bcm_writel(msi_hi, msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
+ bcm_writel(data_val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
+}
+
+static const struct irq_domain_ops msi_domain_ops = {
+ .alloc = brcm_irq_domain_alloc,
+ .free = brcm_irq_domain_free,
+};
+
+static int brcm_allocate_domains(struct brcm_msi *msi)
+{
+ struct fwnode_handle *fwnode = of_node_to_fwnode(msi->dn);
+ struct device *dev = msi->dev;
+
+ msi->inner_domain = irq_domain_add_linear(NULL, BRCM_INT_PCI_MSI_NR,
+ &msi_domain_ops, msi);
+ if (!msi->inner_domain) {
+ dev_err(dev, "failed to create IRQ domain\n");
+ return -ENOMEM;
+ }
+
+ msi->msi_domain = pci_msi_create_irq_domain(fwnode,
+ &brcm_msi_domain_info,
+ msi->inner_domain);
+ if (!msi->msi_domain) {
+ dev_err(dev, "failed to create MSI domain\n");
+ irq_domain_remove(msi->inner_domain);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static void brcm_free_domains(struct brcm_msi *msi)
+{
+ irq_domain_remove(msi->msi_domain);
+ irq_domain_remove(msi->inner_domain);
+}
+
+static void brcm_msi_remove(struct brcm_pcie *pcie)
+{
+ struct brcm_msi *msi = pcie->msi;
+
+ if (!msi)
+ return;
+ irq_set_chained_handler(msi->irq, NULL);
+ irq_set_handler_data(msi->irq, NULL);
+ brcm_free_domains(msi);
+}
+
+static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
+{
+ struct brcm_msi *msi;
+ int irq, ret;
+ struct device *dev = pcie->dev;
+
+ irq = irq_of_parse_and_map(dev->of_node, 1);
+ if (irq <= 0) {
+ dev_err(dev, "cannot map msi intr\n");
+ return -ENODEV;
+ }
+
+ msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
+ if (!msi)
+ return -ENOMEM;
+
+ msi->dev = dev;
+ msi->base = pcie->base;
+ msi->rev = pcie->rev;
+ msi->dn = pcie->dn;
+ msi->target_addr = pcie->msi_target_addr;
+ msi->irq = irq;
+
+ ret = brcm_allocate_domains(msi);
+ if (ret)
+ return ret;
+
+ irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
+
+ if (msi->rev >= BRCM_PCIE_HW_REV_33) {
+ msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
+ /*
+ * This version of PCIe hw has only 32 intr bits
+ * starting at bit position 0.
+ */
+ msi->intr_legacy_mask = 0xffffffff;
+ msi->intr_legacy_offset = 0x0;
+ msi->used = 0x0;
+
+ } else {
+ msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
+ /*
+ * This version of PCIe hw has only 8 intr bits starting
+ * at bit position 24.
+ */
+ msi->intr_legacy_mask = 0xff000000;
+ msi->intr_legacy_offset = 24;
+ msi->used = 0x00ffffff;
+ }
+
+ brcm_msi_set_regs(msi);
+ pcie->msi = msi;
+
+ return 0;
+}
+
/* Configuration space read/write support */
static int cfg_index(int busnr, int devfn, int reg)
{
@@ -1072,6 +1372,7 @@ static int brcm_pcie_setup(struct brcm_p
u16 nlw, cls, lnksta;
bool ssc_good = false;
struct device *dev = pcie->dev;
+ u64 msi_target_addr;
/* Reset the bridge */
brcm_pcie_bridge_sw_init_set(pcie, 1);
@@ -1116,27 +1417,24 @@ static int brcm_pcie_setup(struct brcm_p
* The PCIe host controller by design must set the inbound
* viewport to be a contiguous arrangement of all of the
* system's memory. In addition, its size mut be a power of
- * two. To further complicate matters, the viewport must
- * start on a pcie-address that is aligned on a multiple of its
- * size. If a portion of the viewport does not represent
- * system memory -- e.g. 3GB of memory requires a 4GB viewport
- * -- we can map the outbound memory in or after 3GB and even
- * though the viewport will overlap the outbound memory the
- * controller will know to send outbound memory downstream and
- * everything else upstream.
+ * two. Further, the MSI target address must NOT be placed
+ * inside this region, as the decoding logic will consider its
+ * address to be inbound memory traffic. To further
+ * complicate matters, the viewport must start on a
+ * pcie-address that is aligned on a multiple of its size.
+ * If a portion of the viewport does not represent system
+ * memory -- e.g. 3GB of memory requires a 4GB viewport --
+ * we can map the outbound memory in or after 3GB and even
+ * though the viewport will overlap the outbound memory
+ * the controller will know to send outbound memory downstream
+ * and everything else upstream.
*/
rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
- /*
- * Set simple configuration based on memory sizes
- * only. We always start the viewport at address 0.
- */
- rc_bar2_offset = 0;
-
if (dma_ranges) {
/*
* The best-case scenario is to place the inbound
- * region in the first 4GB of pci-space, as some
+ * region in the first 4GB of pcie-space, as some
* legacy devices can only address 32bits.
* We would also like to put the MSI under 4GB
* as well, since some devices require a 32bit
@@ -1145,6 +1443,14 @@ static int brcm_pcie_setup(struct brcm_p
if (total_mem_size <= 0xc0000000ULL &&
rc_bar2_size <= 0x100000000ULL) {
rc_bar2_offset = 0;
+ /* If the viewport is less then 4GB we can fit
+ * the MSI target address under 4GB. Otherwise
+ * put it right below 64GB.
+ */
+ msi_target_addr =
+ (rc_bar2_size == 0x100000000ULL)
+ ? BRCM_MSI_TARGET_ADDR_GT_4GB
+ : BRCM_MSI_TARGET_ADDR_LT_4GB;
} else {
/*
* The system memory is 4GB or larger so we
@@ -1154,8 +1460,12 @@ static int brcm_pcie_setup(struct brcm_p
* start it at the 1x multiple of its size
*/
rc_bar2_offset = rc_bar2_size;
- }
+ /* Since we are starting the viewport at 4GB or
+ * higher, put the MSI target address below 4GB
+ */
+ msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
+ }
} else {
/*
* Set simple configuration based on memory sizes
@@ -1163,7 +1473,12 @@ static int brcm_pcie_setup(struct brcm_p
* and set the MSI target address accordingly.
*/
rc_bar2_offset = 0;
+
+ msi_target_addr = (rc_bar2_size >= 0x100000000ULL)
+ ? BRCM_MSI_TARGET_ADDR_GT_4GB
+ : BRCM_MSI_TARGET_ADDR_LT_4GB;
}
+ pcie->msi_target_addr = msi_target_addr;
tmp = lower_32_bits(rc_bar2_offset);
tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
@@ -1333,6 +1648,9 @@ static int brcm_pcie_resume(struct devic
if (ret)
return ret;
+ if (pcie->msi && pcie->msi_internal)
+ brcm_msi_set_regs(pcie->msi);
+
pcie->suspended = false;
return 0;
@@ -1340,6 +1658,7 @@ static int brcm_pcie_resume(struct devic
static void _brcm_pcie_remove(struct brcm_pcie *pcie)
{
+ brcm_msi_remove(pcie);
turn_off(pcie);
clk_disable_unprepare(pcie->clk);
clk_put(pcie->clk);
@@ -1368,7 +1687,7 @@ MODULE_DEVICE_TABLE(of, brcm_pcie_match)
static int brcm_pcie_probe(struct platform_device *pdev)
{
- struct device_node *dn = pdev->dev.of_node;
+ struct device_node *dn = pdev->dev.of_node, *msi_dn;
const struct of_device_id *of_id;
const struct pcie_cfg_data *data;
int ret;
@@ -1448,6 +1767,20 @@ static int brcm_pcie_probe(struct platfo
if (ret)
goto fail;
+ msi_dn = of_parse_phandle(pcie->dn, "msi-parent", 0);
+ /* Use the internal MSI if no msi-parent property */
+ if (!msi_dn)
+ msi_dn = pcie->dn;
+
+ if (pci_msi_enabled() && msi_dn == pcie->dn) {
+ ret = brcm_pcie_enable_msi(pcie);
+ if (ret)
+ dev_err(pcie->dev,
+ "probe of internal MSI failed: %d)", ret);
+ else
+ pcie->msi_internal = true;
+ }
+
list_splice_init(&pcie->resources, &bridge->windows);
bridge->dev.parent = &pdev->dev;
bridge->busnr = 0;
@@ -1470,7 +1803,6 @@ static int brcm_pcie_probe(struct platfo
pcie->root_bus = bridge->bus;
return 0;
-
fail:
_brcm_pcie_remove(pcie);
return ret;

View File

@ -28,17 +28,3 @@ Subject: [PATCH] config: Permit LPAE and PCIE_BRCMSTB on BCM2835
help
This enables support for the Broadcom BCM2835 and BCM2836 SoCs.
This SoC is used in the Raspberry Pi and Roku 2 devices.
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -290,9 +290,9 @@ config PCI_HYPERV_INTERFACE
config PCIE_BRCMSTB
tristate "Broadcom Brcmstb PCIe platform host driver"
- depends on ARCH_BRCMSTB || BMIPS_GENERIC
+ depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM2835
depends on OF
- depends on SOC_BRCMSTB
+ depends on SOC_BRCMSTB || ARCH_BCM2835
default ARCH_BRCMSTB || BMIPS_GENERIC
help
Adds support for Broadcom Settop Box PCIe host controller.

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