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rockchip: adjust irq affinity for fastrhino r68s

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2023-02-16 17:53:31 +08:00
parent 62b45ed79e
commit 68dd426a5d
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
4 changed files with 26 additions and 6 deletions
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20
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r68s.dts
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@ -49,6 +49,7 @@
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
@ -58,7 +59,6 @@
&gmac1m1_rgmii_bus>;
tx_delay = <0x4f>;
rx_delay = <0x26>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
@ -67,6 +67,8 @@
compatible = "ethernet-phy-id001c.c916",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
@ -78,12 +80,28 @@
compatible = "ethernet-phy-id001c.c916",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-0 = <&eth_phy1_reset_pin>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
gmac0 {
eth_phy0_reset_pin: eth-phy0-reset-pin {
rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
gmac1 {
eth_phy1_reset_pin: eth-phy1-reset-pin {
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;

4
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r6xs.dtsi
View File

@ -366,10 +366,6 @@
};
};
&gic {
mbi-ranges = <94 31>, <229 31>, <289 31>;
};
&pinctrl {
gpio-leds {
status_led_pin: status-led-pin {

6
target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity
View File

@ -46,4 +46,10 @@ lunzn,fastrhino-r66s)
set_interface_core 2 "eth0"
set_interface_core 4 "eth1"
;;
lunzn,fastrhino-r68s)
set_interface_core 1 "eth0"
set_interface_core 2 "eth1"
set_interface_core 4 "eth2"
set_interface_core 8 "eth3"
;;
esac

2
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
View File

@ -51,6 +51,7 @@
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
@ -60,7 +61,6 @@
&gmac1m1_rgmii_bus>;
tx_delay = <0x4f>;
rx_delay = <0x26>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};