From 444b107118212b4b5e822b9eb0937019dde1a4a1 Mon Sep 17 00:00:00 2001 From: Lucian Cristian Date: Sun, 28 Jun 2020 21:40:06 +0300 Subject: [PATCH 1/9] atf-rockchip: update to 2.3 also install the firmware for all the supported boards Signed-off-by: Lucian Cristian [fix ATF blob path in uboot-rockchip] Signed-off-by: David Bauer --- package/boot/arm-trusted-firmware-rockchip/Makefile | 6 +++--- package/boot/uboot-rockchip/Makefile | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/package/boot/arm-trusted-firmware-rockchip/Makefile b/package/boot/arm-trusted-firmware-rockchip/Makefile index a1c9e120e7..b712a3530a 100644 --- a/package/boot/arm-trusted-firmware-rockchip/Makefile +++ b/package/boot/arm-trusted-firmware-rockchip/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=arm-trusted-firmware-rockchip -PKG_VERSION:=2.3-rc0 +PKG_VERSION:=2.3 PKG_RELEASE:=1 PKG_SOURCE:=atf-v$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://github.com/atf-builds/atf/releases/download/v$(PKG_VERSION)/atf-v$(PKG_VERSION).tar.gz? -PKG_HASH:=8d0a2bd18adf54f9cf6fe923d10f21c1d21f42a15067757333ff8989b25f100a +PKG_HASH:=bf352298743aed594cf2958dd588e06ab6713fc514bb6f809bf55a85a87134c1 PKG_LICENSE:=BSD-3-Clause PKG_LICENSE_FILES:=license.md @@ -40,7 +40,7 @@ endef define Build/InstallDev $(INSTALL_DIR) -p $(STAGING_DIR_IMAGE) - $(CP) $(PKG_BUILD_DIR)/rk3399_bl31.elf $(STAGING_DIR_IMAGE)/bl31.elf + $(CP) $(PKG_BUILD_DIR)/rk*.elf $(STAGING_DIR_IMAGE)/ endef define Package/arm-trusted-firmware-rockchip/install diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index b99d051fcf..6e4139b098 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -35,7 +35,7 @@ UBOOT_TARGETS := \ UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes UBOOT_MAKE_FLAGS += \ - BL31=$(STAGING_DIR_IMAGE)/bl31.elf + BL31=$(STAGING_DIR_IMAGE)/rk3399_bl31.elf define Build/Configure $(SED) s/subdir.*pylibfdt//g $(PKG_BUILD_DIR)/scripts/dtc/Makefile From 65ac670b792481d921f3aaba685d4c9910e1ad04 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Fri, 10 Jul 2020 15:14:15 +0200 Subject: [PATCH 2/9] uboot-rockchip: update to v2020.07 Update the U-Boot to version v2020.07. Also replace the Makefile rewrite with a proper patch, explaining why this hack is needed. Run-tested: FriendlyARM NanoPi R2S Signed-off-by: David Bauer --- package/boot/uboot-rockchip/Makefile | 5 ++-- ...01-scripts-remove-dependency-on-swig.patch | 24 +++++++++++++++++++ 2 files changed, 26 insertions(+), 3 deletions(-) create mode 100644 package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 6e4139b098..97f651fbbf 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,9 +5,9 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2020.04 +PKG_VERSION:=2020.07 -PKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372 +PKG_HASH:=c1f5bf9ee6bb6e648edbf19ce2ca9452f614b08a9f886f1a566aa42e8cf05f6a PKG_MAINTAINER:=Tobias Maedel @@ -38,7 +38,6 @@ UBOOT_MAKE_FLAGS += \ BL31=$(STAGING_DIR_IMAGE)/rk3399_bl31.elf define Build/Configure - $(SED) s/subdir.*pylibfdt//g $(PKG_BUILD_DIR)/scripts/dtc/Makefile $(call Build/Configure/U-Boot) $(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config diff --git a/package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch b/package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch new file mode 100644 index 0000000000..0505589385 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch @@ -0,0 +1,24 @@ +From b137ca16b54c67d76714ea5a0138741959b0dc29 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Mon, 13 Jul 2020 23:37:37 +0200 +Subject: [PATCH] scripts: remove dependency on swig + +Don't build the libfdt tool, as it has a dependency on swig (which +OpenWrt does not ship). + +This requires more hacks, as of-platdata generation does not work +without it. + +Signed-off-by: David Bauer +--- + scripts/dtc/Makefile | 2 -- + 1 file changed, 2 deletions(-) + +--- a/scripts/dtc/Makefile ++++ b/scripts/dtc/Makefile +@@ -18,5 +18,3 @@ HOSTCFLAGS_dtc-parser.tab.o := -I$(src) + # dependencies on generated files need to be listed explicitly + $(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h + +-# Added for U-Boot +-subdir-$(CONFIG_PYLIBFDT) += pylibfdt From 04f06787f1c0f1d89f6b8c71430d0d0bbb62ffa5 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Fri, 10 Jul 2020 17:38:36 +0200 Subject: [PATCH 3/9] uboot-rockchip: add NanoPi R2S support Add support for the FriendlyARM NanoPi R2S. Signed-off-by: David Bauer --- package/boot/uboot-rockchip/Makefile | 31 +- ...-spl-remove-dtoc-of-pdata-generation.patch | 32 ++ ...Add-support-for-FriendlyARM-NanoPi-R.patch | 530 ++++++++++++++++++ .../nanopi-r2s-rk3328/dt-platdata.c | 149 +++++ .../nanopi-r2s-rk3328/dt-structs-gen.h | 72 +++ 5 files changed, 812 insertions(+), 2 deletions(-) create mode 100644 package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch create mode 100644 package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch create mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c create mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 97f651fbbf..e5c49d00bb 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -20,6 +20,23 @@ define U-Boot/Default HIDDEN:=1 endef + +# RK3328 boards + +define U-Boot/nanopi-r2s-rk3328 + BUILD_SUBTARGET:=armv8 + NAME:=NanoPi R2S + BUILD_DEVICES:= \ + friendlyarm_nanopi-r2s + DEPENDS:=+PACKAGE_u-boot-nanopi-r2s-rk3328:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3328_bl31.elf + OF_PLATDATA:=$(1) +endef + + +# RK3399 boards + define U-Boot/rockpro64-rk3399 BUILD_SUBTARGET:=armv8 NAME:=RockPro64 @@ -27,19 +44,29 @@ define U-Boot/rockpro64-rk3399 pine64_rockpro64 DEPENDS:=+PACKAGE_u-boot-rockpro64-rk3399:arm-trusted-firmware-rockchip PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3399_bl31.elf endef UBOOT_TARGETS := \ - rockpro64-rk3399 + rockpro64-rk3399 \ + nanopi-r2s-rk3328 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes UBOOT_MAKE_FLAGS += \ - BL31=$(STAGING_DIR_IMAGE)/rk3399_bl31.elf + BL31=$(STAGING_DIR_IMAGE)/$(ATF) define Build/Configure $(call Build/Configure/U-Boot) +ifneq ($(OF_PLATDATA),) + mkdir -p $(PKG_BUILD_DIR)/tpl/dts + mkdir -p $(PKG_BUILD_DIR)/include/generated + + $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-platdata.c $(PKG_BUILD_DIR)/tpl/dts/dt-platdata.c + $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h +endif + $(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config endef diff --git a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch new file mode 100644 index 0000000000..4161c46ce2 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch @@ -0,0 +1,32 @@ +From 55273cf6079ddd3b006da69f0113c2c66c03f17e Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Tue, 14 Jul 2020 22:44:22 +0200 +Subject: [PATCH] spl: remove dtoc of-pdata generation + +Remove the dtoc of-pdata generation. This generation is dependant on +libpython-dev. As OpenWrt does not ship with this dependency, use +pre-generated pdata files and remove the generation from the +build-process. + +This only affects RK3328 boards. + +Signed-off-by: David Bauer +--- + scripts/Makefile.spl | 6 ------ + 1 file changed, 6 deletions(-) + +--- a/scripts/Makefile.spl ++++ b/scripts/Makefile.spl +@@ -320,12 +320,6 @@ PHONY += dts_dir + dts_dir: + $(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts) + +-include/generated/dt-structs-gen.h: $(obj)/$(SPL_BIN).dtb dts_dir FORCE +- $(call if_changed,dtoch) +- +-$(obj)/dts/dt-platdata.c: $(obj)/$(SPL_BIN).dtb dts_dir FORCE +- $(call if_changed,dtocc) +- + ifdef CONFIG_SAMSUNG + ifdef CONFIG_VAR_SIZE_SPL + VAR_SIZE_PARAM = --vs diff --git a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 0000000000..bc65fb69ef --- /dev/null +++ b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,530 @@ +From 67f4c228c2bf515386cd54073104dc2e6eae85ea Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Fri, 10 Jul 2020 14:58:30 +0200 +Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S + +This adds support for the NanoPi R2S from FriendlyArm. + +Rockchip RK3328 SoC +1GB DDR4 RAM +Gigabit Ethernet (WAN) +Gigabit Ethernet (USB3) (LAN) +USB 2.0 Host Port +MicroSD slot +Reset button +WAN - LAN - SYS LED + +Signed-off-by: David Bauer +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 34 +++ + arch/arm/dts/rk3328-nanopi-r2s.dts | 334 +++++++++++++++++++++ + board/rockchip/evb_rk3328/MAINTAINERS | 7 + + configs/nanopi-r2s-rk3328_defconfig | 99 ++++++ + 5 files changed, 475 insertions(+) + create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts + create mode 100644 configs/nanopi-r2s-rk3328_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ + + dtb-$(CONFIG_ROCKCHIP_RK3328) += \ + rk3328-evb.dtb \ ++ rk3328-nanopi-r2s.dtb \ + rk3328-roc-cc.dtb \ + rk3328-rock64.dtb \ + rk3328-rock-pi-e.dtb +--- /dev/null ++++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +@@ -0,0 +1,34 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd ++ * (C) Copyright 2020 David Bauer ++ */ ++ ++#include "rk3328-u-boot.dtsi" ++#include "rk3328-sdram-ddr4-666.dtsi" ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; ++ }; ++}; ++ ++&gpio0 { ++ u-boot,dm-spl; ++}; ++ ++&pinctrl { ++ u-boot,dm-spl; ++}; ++ ++&sdmmc0m1_gpio { ++ u-boot,dm-spl; ++}; ++ ++&pcfg_pull_up_4ma { ++ u-boot,dm-spl; ++}; ++ ++/* Need this and all the pinctrl/gpio stuff above to set pinmux */ ++&vcc_sd { ++ u-boot,dm-spl; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3328-nanopi-r2s.dts +@@ -0,0 +1,334 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 David Bauer ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include "rk3328.dtsi" ++ ++/ { ++ model = "FriendlyARM NanoPi R2S"; ++ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac_clkin: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0m1_gpio>; ++ regulator-name = "vcc_sd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_io>; ++ }; ++ ++ vcc_sdio: sdmmcio-regulator { ++ compatible = "regulator-gpio"; ++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio_vcc_pin>; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_sdio"; ++ regulator-settling-time-us = <5000>; ++ regulator-type = "voltage"; ++ vin-supply = <&vcc_io>; ++ }; ++ ++ vcc_sys: vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_pins>; ++ ++ sys { ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r2s:red:sys"; ++ }; ++ ++ lan { ++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r2s:green:lan"; ++ }; ++ ++ wan { ++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r2s:green:wan"; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys-polled"; ++ poll-interval = <100>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&button_pins>; ++ ++ reset { ++ label = "Reset Button"; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <50>; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&gmac2io { ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; ++ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_io>; ++ phy-handle = <&rtl8211e>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmiim1_pins>; ++ snps,aal; ++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x24>; ++ rx_delay = <0x18>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rtl8211e: ethernet-phy@0 { ++ reg = <0>; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ rk805: rk805@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio2>; ++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_io>; ++ vcc6-supply = <&vcc_sys>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io: DCDC_REG4 { ++ regulator-name = "vcc_io"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_18: LDO_REG1 { ++ regulator-name = "vcc_18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc18_emmc: LDO_REG2 { ++ regulator-name = "vcc18_emmc"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_10: LDO_REG3 { ++ regulator-name = "vdd_10"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&io_domains { ++ status = "okay"; ++ ++ vccio1-supply = <&vcc_io>; ++ vccio2-supply = <&vcc18_emmc>; ++ vccio3-supply = <&vcc_sdio>; ++ vccio4-supply = <&vcc_18>; ++ vccio5-supply = <&vcc_io>; ++ vccio6-supply = <&vcc_io>; ++ pmuio-supply = <&vcc_io>; ++}; ++ ++&pinctrl { ++ leds { ++ led_pins: led-pins { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, ++ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, ++ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ button { ++ button_pins: button-pins { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sd { ++ sdio_vcc_pin: sdio-vcc-pin { ++ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; ++ vmmc-supply = <&vcc_sd>; ++ vqmmc-supply = <&vcc_sdio>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <0>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&u2phy { ++ status = "okay"; ++ ++ u2phy_host: host-port { ++ status = "okay"; ++ }; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; +--- a/board/rockchip/evb_rk3328/MAINTAINERS ++++ b/board/rockchip/evb_rk3328/MAINTAINERS +@@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328 + F: include/configs/evb_rk3328.h + F: configs/evb-rk3328_defconfig + ++NANOPI-R2S-RK3328 ++M: David Bauer ++S: Maintained ++F: configs/nanopi-r2s-rk3328_defconfig ++F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi ++F: arch/arm/dts/rk3328-nanopi-r2s.dts ++ + ROC-RK3328-CC + M: Loic Devulder + M: Chen-Yu Tsai +--- /dev/null ++++ b/configs/nanopi-r2s-rk3328_defconfig +@@ -0,0 +1,99 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO_SUPPORT=y ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_ROCKCHIP_RK3328=y ++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_TPL_LIBCOMMON_SUPPORT=y ++CONFIG_TPL_LIBGENERIC_SUPPORT=y ++CONFIG_SPL_DRIVERS_MISC_SUPPORT=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEBUG_UART_BASE=0xFF130000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SMBIOS_PRODUCT_NAME="nanopi_r2s_rk3328" ++CONFIG_DEBUG_UART=y ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 ++# CONFIG_ANDROID_BOOT_IMAGE is not set ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb" ++CONFIG_MISC_INIT_R=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_TPL_SYS_MALLOC_SIMPLE=y ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_I2C_SUPPORT=y ++CONFIG_SPL_POWER_SUPPORT=y ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_TPL_OF_CONTROL=y ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s" ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_TPL_OF_PLATDATA=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_TPL_DM=y ++CONFIG_REGMAP=y ++CONFIG_SPL_REGMAP=y ++CONFIG_TPL_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_SYSCON=y ++CONFIG_TPL_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_FASTBOOT_BUF_ADDR=0x800800 ++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=20000000 ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_SPL_RAM=y ++CONFIG_TPL_RAM=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++# CONFIG_TPL_SYSRESET is not set ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_TPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y ++CONFIG_SMBIOS_MANUFACTURER="pine64" diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c new file mode 100644 index 0000000000..fa42c1a760 --- /dev/null +++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c @@ -0,0 +1,149 @@ +/* + * DO NOT MODIFY + * + * This file was generated by dtoc from a .dtb (device tree binary) file. + */ + +#include +#include +#include + +static const struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { + .reg = {0xff100000, 0x1000}, +}; +U_BOOT_DEVICE(syscon_at_ff100000) = { + .name = "rockchip_rk3328_grf", + .platdata = &dtv_syscon_at_ff100000, + .platdata_size = sizeof(dtv_syscon_at_ff100000), +}; + +static const struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { + .reg = {0xff440000, 0x1000}, + .rockchip_grf = 0x3a, +}; +U_BOOT_DEVICE(clock_controller_at_ff440000) = { + .name = "rockchip_rk3328_cru", + .platdata = &dtv_clock_controller_at_ff440000, + .platdata_size = sizeof(dtv_clock_controller_at_ff440000), +}; + +static const struct dtd_rockchip_rk3328_uart dtv_serial_at_ff130000 = { + .clock_frequency = 0x16e3600, + .clocks = { + {&dtv_clock_controller_at_ff440000, {40}}, + {&dtv_clock_controller_at_ff440000, {212}},}, + .dma_names = {"tx", "rx"}, + .dmas = {0x10, 0x6, 0x10, 0x7}, + .interrupts = {0x0, 0x39, 0x4}, + .pinctrl_0 = 0x26, + .pinctrl_names = "default", + .reg = {0xff130000, 0x100}, + .reg_io_width = 0x4, + .reg_shift = 0x2, +}; +U_BOOT_DEVICE(serial_at_ff130000) = { + .name = "rockchip_rk3328_uart", + .platdata = &dtv_serial_at_ff130000, + .platdata_size = sizeof(dtv_serial_at_ff130000), +}; + +static const struct dtd_rockchip_rk3328_dw_mshc dtv_mmc_at_ff500000 = { + .bus_width = 0x4, + .cap_mmc_highspeed = true, + .cap_sd_highspeed = true, + .clocks = { + {&dtv_clock_controller_at_ff440000, {317}}, + {&dtv_clock_controller_at_ff440000, {33}}, + {&dtv_clock_controller_at_ff440000, {74}}, + {&dtv_clock_controller_at_ff440000, {78}},}, + .disable_wp = true, + .fifo_depth = 0x100, + .interrupts = {0x0, 0xc, 0x4}, + .max_frequency = 0x8f0d180, + .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, + .pinctrl_names = "default", + .reg = {0xff500000, 0x4000}, + .u_boot_spl_fifo_mode = true, + .vmmc_supply = 0x4b, + .vqmmc_supply = 0x1e, +}; +U_BOOT_DEVICE(mmc_at_ff500000) = { + .name = "rockchip_rk3328_dw_mshc", + .platdata = &dtv_mmc_at_ff500000, + .platdata_size = sizeof(dtv_mmc_at_ff500000), +}; + +static const struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = { + .ranges = true, + .rockchip_grf = 0x3a, +}; +U_BOOT_DEVICE(pinctrl) = { + .name = "rockchip_rk3328_pinctrl", + .platdata = &dtv_pinctrl, + .platdata_size = sizeof(dtv_pinctrl), +}; + +static const struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = { + .clocks = { + {&dtv_clock_controller_at_ff440000, {200}},}, + .gpio_controller = true, + .interrupt_controller = true, + .interrupts = {0x0, 0x33, 0x4}, + .reg = {0xff210000, 0x100}, +}; +U_BOOT_DEVICE(gpio0_at_ff210000) = { + .name = "rockchip_gpio_bank", + .platdata = &dtv_gpio0_at_ff210000, + .platdata_size = sizeof(dtv_gpio0_at_ff210000), +}; + +static const struct dtd_regulator_fixed dtv_sdmmc_regulator = { + .gpio = {0x60, 0x1e, 0x1}, + .pinctrl_0 = 0x61, + .pinctrl_names = "default", + .regulator_max_microvolt = 0x325aa0, + .regulator_min_microvolt = 0x325aa0, + .regulator_name = "vcc_sd", + .vin_supply = 0x1c, +}; +U_BOOT_DEVICE(sdmmc_regulator) = { + .name = "regulator_fixed", + .platdata = &dtv_sdmmc_regulator, + .platdata_size = sizeof(dtv_sdmmc_regulator), +}; + +static const struct dtd_rockchip_rk3328_dmc dtv_dmc = { + .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, + 0xff720000, 0x1000, 0xff798000, 0x1000}, + .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, + 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, + 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, + 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, + 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, + 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, + 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, + 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, + 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, + 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, + 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, + 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, + 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, + 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, + 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, + 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, + 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x79, 0x9}, +}; +U_BOOT_DEVICE(dmc) = { + .name = "rockchip_rk3328_dmc", + .platdata = &dtv_dmc, + .platdata_size = sizeof(dtv_dmc), +}; + diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h new file mode 100644 index 0000000000..88291627b8 --- /dev/null +++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h @@ -0,0 +1,72 @@ +/* + * DO NOT MODIFY + * + * This file was generated by dtoc from a .dtb (device tree binary) file. + */ + +#include +#include +struct dtd_regulator_fixed { + fdt32_t gpio[3]; + fdt32_t pinctrl_0; + const char * pinctrl_names; + fdt32_t regulator_max_microvolt; + fdt32_t regulator_min_microvolt; + const char * regulator_name; + fdt32_t vin_supply; +}; +struct dtd_rockchip_gpio_bank { + struct phandle_1_arg clocks[1]; + bool gpio_controller; + bool interrupt_controller; + fdt32_t interrupts[3]; + fdt64_t reg[2]; +}; +struct dtd_rockchip_rk3328_cru { + fdt64_t reg[2]; + fdt32_t rockchip_grf; +}; +struct dtd_rockchip_rk3328_dmc { + fdt64_t reg[12]; + fdt32_t rockchip_sdram_params[196]; +}; +struct dtd_rockchip_rk3328_dw_mshc { + fdt32_t bus_width; + bool cap_mmc_highspeed; + bool cap_sd_highspeed; + struct phandle_1_arg clocks[4]; + bool disable_wp; + fdt32_t fifo_depth; + fdt32_t interrupts[3]; + fdt32_t max_frequency; + fdt32_t pinctrl_0[4]; + const char * pinctrl_names; + fdt64_t reg[2]; + bool u_boot_spl_fifo_mode; + fdt32_t vmmc_supply; + fdt32_t vqmmc_supply; +}; +struct dtd_rockchip_rk3328_grf { + fdt64_t reg[2]; +}; +struct dtd_rockchip_rk3328_pinctrl { + bool ranges; + fdt32_t rockchip_grf; +}; +struct dtd_rockchip_rk3328_uart { + fdt32_t clock_frequency; + struct phandle_1_arg clocks[2]; + const char * dma_names[2]; + fdt32_t dmas[4]; + fdt32_t interrupts[3]; + fdt32_t pinctrl_0; + const char * pinctrl_names; + fdt64_t reg[2]; + fdt32_t reg_io_width; + fdt32_t reg_shift; +}; +#define dtd_syscon dtd_rockchip_rk3328_cru +#define dtd_simple_mfd dtd_rockchip_rk3328_grf +#define dtd_snps_dw_apb_uart dtd_rockchip_rk3328_uart +#define dtd_rockchip_cru dtd_rockchip_rk3328_cru +#define dtd_rockchip_rk3288_dw_mshc dtd_rockchip_rk3328_dw_mshc From c3e252d08032de80e7c82759cc9763a310a97144 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Sat, 11 Jul 2020 13:48:40 +0200 Subject: [PATCH 4/9] base-files: add function for generating random MAC This adds a function for generating a valid random MAC address (unset MC bit / set locally administered bit). It is necessary for devices which do not have a MAC address programmed by the manufacturer. Signed-off-by: David Bauer --- package/base-files/Makefile | 2 +- package/base-files/files/lib/functions/system.sh | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/package/base-files/Makefile b/package/base-files/Makefile index 284899bd69..d32bae8635 100644 --- a/package/base-files/Makefile +++ b/package/base-files/Makefile @@ -12,7 +12,7 @@ include $(INCLUDE_DIR)/version.mk include $(INCLUDE_DIR)/feeds.mk PKG_NAME:=base-files -PKG_RELEASE:=223 +PKG_RELEASE:=224 PKG_FLAGS:=nonshared PKG_FILE_DEPENDS:=$(PLATFORM_DIR)/ $(GENERIC_PLATFORM_DIR)/base-files/ diff --git a/package/base-files/files/lib/functions/system.sh b/package/base-files/files/lib/functions/system.sh index f3c901ff79..80e417182a 100644 --- a/package/base-files/files/lib/functions/system.sh +++ b/package/base-files/files/lib/functions/system.sh @@ -174,6 +174,18 @@ macaddr_setbit_la() { macaddr_setbit $1 7 } +macaddr_unsetbit_mc() { + local mac=$1 + + printf "%02x:%s" $((0x${mac%%:*} & ~0x01)) ${mac#*:} +} + +macaddr_random() { + local randsrc=$(get_mac_binary /dev/urandom 0) + + echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${randsrc}")")" +} + macaddr_2bin() { local mac=$1 From b72f7c64a4eb4aa14f3b632dd4ff77a4802c0311 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Sat, 11 Jul 2020 14:02:23 +0200 Subject: [PATCH 5/9] rockchip: allow for multiple boot-scripts Add support for select a bootscript depending on the device built. This is necessary, as the FriendlyARM NanoPi R2S needs a different bootcmd in order to produce output on the debug UART. Signed-off-by: David Bauer --- target/linux/rockchip/image/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/rockchip/image/Makefile b/target/linux/rockchip/image/Makefile index 22854d9d02..3c17e963be 100644 --- a/target/linux/rockchip/image/Makefile +++ b/target/linux/rockchip/image/Makefile @@ -24,7 +24,7 @@ endef define Build/boot-script # Make an U-boot image and copy it to the boot partition - mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d mmc.bootscript $@.boot/boot.scr + mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d $(if $(1),$(1),mmc).bootscript $@.boot/boot.scr endef define Build/pine64-img From b7a9a183fb44f77d9f95c20bcec1db0edea9e206 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Thu, 16 Jul 2020 10:08:57 +0200 Subject: [PATCH 6/9] rockchip: add NanoPi R2S support Hardware -------- RockChip RK3328 ARM64 (4 cores) 1GB DDR4 RAM 2x 1000 Base-T 3 LEDs (LAN / WAN / SYS) 1 Button (Reset) Micro-SD slot USB 2.0 Port Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card using dd. MAC-address ----------- The vendor code supports reading a MAC address from an EEPROM connected via i2c0 of the SoC. The EEPROM (address 0x51) should contain the MAC address in binary at offset 0xfa. However, my two units didn't come with such an EEPROM soldered on. The EEPROM should be placed between the SoC and the GPIO pins on the board. (U10) Generating rendom MAC addresses works around this issue. Otherwise, all boards running the same image have identical MAC addresses. Signed-off-by: David Bauer --- .../armv8/base-files/etc/board.d/01_leds | 20 + .../armv8/base-files/etc/board.d/02_network | 44 ++- target/linux/rockchip/armv8/config-5.4 | 2 + target/linux/rockchip/image/armv8.mk | 11 + .../rockchip/image/nanopi-r2s.bootscript | 8 + ...Add-support-for-FriendlyARM-NanoPi-R.patch | 370 ++++++++++++++++++ ...-rockchip-use-system-LED-for-OpenWrt.patch | 40 ++ ...usb3-controller-node-for-RK3328-SoCs.patch | 62 +++ ...ckchip-enable-LAN-port-on-NanoPi-R2S.patch | 60 +++ 9 files changed, 610 insertions(+), 7 deletions(-) create mode 100755 target/linux/rockchip/armv8/base-files/etc/board.d/01_leds create mode 100644 target/linux/rockchip/image/nanopi-r2s.bootscript create mode 100644 target/linux/rockchip/patches-5.4/001-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch create mode 100644 target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch create mode 100644 target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch create mode 100644 target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds new file mode 100755 index 0000000000..bba3e2aa56 --- /dev/null +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds @@ -0,0 +1,20 @@ +#!/bin/sh + +. /lib/functions/leds.sh +. /lib/functions/uci-defaults.sh + +board=$(board_name) +boardname="${board##*,}" + +board_config_update + +case $board in +friendlyarm,nanopi-r2s) + ucidef_set_led_netdev "wan" "WAN" "$boardname:green:wan" "eth0" + ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth1" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index c5adda1706..e129fd6a67 100755 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -1,15 +1,45 @@ #!/bin/sh . /lib/functions/uci-defaults.sh +. /lib/functions/system.sh + +rockchip_setup_interfaces() +{ + local board="$1" + + case "$board" in + friendlyarm,nanopi-r2s) + ucidef_set_interfaces_lan_wan 'eth1' 'eth0' + ;; + *) + ucidef_set_interface_lan 'eth0' + ;; + esac +} + +rockchip_setup_macs() +{ + local board="$1" + local lan_mac="" + local wan_mac="" + local label_mac="" + + case "$board" in + friendlyarm,nanopi-r2s) + wan_mac=$(macaddr_random) + lan_mac=$(macaddr_add "$wan_mac" +1) + ;; + esac + + [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac + [ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac +} board_config_update - -case "$(board_name)" in -*) - ucidef_set_interface_lan 'eth0' - ;; -esac - +board=$(board_name) +rockchip_setup_interfaces $board +rockchip_setup_macs $board board_config_flush exit 0 diff --git a/target/linux/rockchip/armv8/config-5.4 b/target/linux/rockchip/armv8/config-5.4 index 4f29204dd2..2615684fed 100644 --- a/target/linux/rockchip/armv8/config-5.4 +++ b/target/linux/rockchip/armv8/config-5.4 @@ -375,6 +375,7 @@ CONFIG_REGMAP_MMIO=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FAN53555=y CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK808=y CONFIG_RELOCATABLE=y @@ -482,6 +483,7 @@ CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_USB=y CONFIG_USB_COMMON=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_DUAL_ROLE=y CONFIG_USB_DWC3_HOST=y CONFIG_USB_DWC3_OF_SIMPLE=y CONFIG_USB_EHCI_HCD=y diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 737c6e4f9a..8e4ba07e0b 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -4,6 +4,17 @@ # This is free software, licensed under the GNU General Public License v2. # See /LICENSE for more information. # + +define Device/friendlyarm_nanopi-r2s + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := NanoPi R2S + SOC := rk3328 + UBOOT_DEVICE_NAME := nanopi-r2s-rk3328 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := kmod-usb-net kmod-usb-net-rtl8152 +endef +TARGET_DEVICES += friendlyarm_nanopi-r2s + define Device/pine64_rockpro64 DEVICE_VENDOR := Pine64 DEVICE_MODEL := RockPro64 diff --git a/target/linux/rockchip/image/nanopi-r2s.bootscript b/target/linux/rockchip/image/nanopi-r2s.bootscript new file mode 100644 index 0000000000..5198881a26 --- /dev/null +++ b/target/linux/rockchip/image/nanopi-r2s.bootscript @@ -0,0 +1,8 @@ +part uuid mmc ${devnum}:2 uuid + +setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff130000 root=PARTUUID=${uuid} rw rootwait" + +load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb +load mmc ${devnum}:1 ${kernel_addr_r} kernel.img + +booti ${kernel_addr_r} - ${fdt_addr_r} diff --git a/target/linux/rockchip/patches-5.4/001-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/target/linux/rockchip/patches-5.4/001-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 0000000000..904a2f31b6 --- /dev/null +++ b/target/linux/rockchip/patches-5.4/001-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,370 @@ +From 749cbb7b1a4bc2244b6af8cd7d8b471d4e33c80f Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Fri, 10 Jul 2020 15:57:46 +0200 +Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S + +This adds support for the NanoPi R2S from FriendlyARM. + +Rockchip RK3328 SoC +1GB DDR4 RAM +Gigabit Ethernet (WAN) +Gigabit Ethernet (USB3) (LAN) +USB 2.0 Host Port +MicroSD slot +Reset button +WAN - LAN - SYS LED + +Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 334 ++++++++++++++++++ + 2 files changed, 335 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -0,0 +1,334 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 David Bauer ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include "rk3328.dtsi" ++ ++/ { ++ model = "FriendlyARM NanoPi R2S"; ++ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac_clkin: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0m1_gpio>; ++ regulator-name = "vcc_sd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_io>; ++ }; ++ ++ vcc_sdio: sdmmcio-regulator { ++ compatible = "regulator-gpio"; ++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio_vcc_pin>; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_sdio"; ++ regulator-settling-time-us = <5000>; ++ regulator-type = "voltage"; ++ vin-supply = <&vcc_io>; ++ }; ++ ++ vcc_sys: vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_pins>; ++ ++ sys { ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r2s:red:sys"; ++ }; ++ ++ lan { ++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r2s:green:lan"; ++ }; ++ ++ wan { ++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r2s:green:wan"; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys-polled"; ++ poll-interval = <100>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&button_pins>; ++ ++ reset { ++ label = "Reset Button"; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <50>; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&gmac2io { ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; ++ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_io>; ++ phy-handle = <&rtl8211e>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmiim1_pins>; ++ snps,aal; ++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x24>; ++ rx_delay = <0x18>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rtl8211e: ethernet-phy@0 { ++ reg = <0>; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ rk805: rk805@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio2>; ++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_io>; ++ vcc6-supply = <&vcc_sys>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io: DCDC_REG4 { ++ regulator-name = "vcc_io"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_18: LDO_REG1 { ++ regulator-name = "vcc_18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc18_emmc: LDO_REG2 { ++ regulator-name = "vcc18_emmc"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_10: LDO_REG3 { ++ regulator-name = "vdd_10"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&io_domains { ++ status = "okay"; ++ ++ vccio1-supply = <&vcc_io>; ++ vccio2-supply = <&vcc18_emmc>; ++ vccio3-supply = <&vcc_sdio>; ++ vccio4-supply = <&vcc_18>; ++ vccio5-supply = <&vcc_io>; ++ vccio6-supply = <&vcc_io>; ++ pmuio-supply = <&vcc_io>; ++}; ++ ++&pinctrl { ++ leds { ++ led_pins: led-pins { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, ++ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, ++ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ button { ++ button_pins: button-pins { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sd { ++ sdio_vcc_pin: sdio-vcc-pin { ++ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; ++ vmmc-supply = <&vcc_sd>; ++ vqmmc-supply = <&vcc_sdio>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <0>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&u2phy { ++ status = "okay"; ++ ++ u2phy_host: host-port { ++ status = "okay"; ++ }; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch new file mode 100644 index 0000000000..1250dbcd9b --- /dev/null +++ b/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch @@ -0,0 +1,40 @@ +From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Fri, 10 Jul 2020 21:38:20 +0200 +Subject: [PATCH] rockchip: use system LED for OpenWrt + +Use the SYS LED on the casing for showing system status. + +This patch is kept seperate from the NanoPi R2S support patch, as i plan +on submitting the device support upstream. + +Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -17,6 +17,13 @@ + stdout-path = "serial2:1500000n8"; + }; + ++ aliases { ++ led-boot = &led_sys; ++ led-failsafe = &led_sys; ++ led-running = &led_sys; ++ led-upgrade = &led_sys; ++ }; ++ + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; +@@ -67,7 +74,7 @@ + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + +- sys { ++ led_sys: sys { + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:red:sys"; + }; diff --git a/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch b/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch new file mode 100644 index 0000000000..316f7c01d3 --- /dev/null +++ b/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch @@ -0,0 +1,62 @@ +From: William Wu + +RK3328 has one USB 3.0 OTG controller which uses DWC_USB3 +core's general architecture. It can act as static xHCI host +controller, static device controller, USB 3.0/2.0 OTG basing +on ID of USB3.0 PHY. + +Signed-off-by: William Wu +Signed-off-by: Leonidas P. Papadakos + +--- + +NOTE: This binding still has issues. From the original thread: + +the rk3328 usb3-phy has an issue with detecting any plugin events +after a previous device got removed - see the inno-usb3-phy driver +in the vendor kernel. + +The current state is good-enough for enabling the USB3 attached LAN +port of the NanoPi R2S. However, it might explode depending on your +use-case. You've been warned. + +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -936,6 +936,33 @@ + status = "disabled"; + }; + ++ usbdrd3: usb@ff600000 { ++ compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3"; ++ clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, ++ <&cru ACLK_USB3OTG>; ++ clock-names = "ref_clk", "suspend_clk", ++ "bus_clk"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ usbdrd_dwc3: dwc3@ff600000 { ++ compatible = "snps,dwc3"; ++ reg = <0x0 0xff600000 0x0 0x100000>; ++ interrupts = ; ++ dr_mode = "otg"; ++ phy_type = "utmi_wide"; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ status = "disabled"; ++ }; ++ }; ++ + gic: interrupt-controller@ff811000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; diff --git a/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch new file mode 100644 index 0000000000..1b52de231e --- /dev/null +++ b/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch @@ -0,0 +1,60 @@ +From 0fc3b9b7619c4878f73a6a7989863f0d1a3fd392 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Fri, 10 Jul 2020 21:12:16 +0200 +Subject: [PATCH] rockchip: enabled LAN port on NanoPi R2S + +Enable the USB3 port on the FriendlyARM NanoPi R2S. +This is required for the USB3 attached LAN port to work. + +Signed-off-by: David Bauer +--- + .../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 27 +++++++++++++++++++ + 1 file changed, 27 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -68,6 +68,18 @@ + regulator-max-microvolt = <5000000>; + }; + ++ vcc_rtl8153: vcc-rtl8153-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtl8153_en_drv>; ++ regulator-always-on; ++ regulator-name = "vcc_rtl8153"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -288,6 +300,12 @@ + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; ++ ++ usb { ++ rtl8153_en_drv: rtl8153-en-drv { ++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; + }; + + &sdmmc { +@@ -328,3 +346,12 @@ + &usb_host0_ohci { + status = "okay"; + }; ++ ++&usbdrd3 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; From 6242ac473546c2305a1dfe2faac7ac610d741b28 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Sun, 26 Jul 2020 19:12:03 +0200 Subject: [PATCH 7/9] rockchip: enable LAN LED configuration This enables the LEDs on the LAN interfaces. Signed-off-by: David Bauer --- ...-r8152-add-LED-configuration-from-OF.patch | 74 +++++++++++++++++++ ...et-add-RTL8152-binding-documentation.patch | 54 ++++++++++++++ ...dd-OF-node-for-USB-eth-on-NanoPi-R2S.patch | 28 +++++++ 3 files changed, 156 insertions(+) create mode 100644 target/linux/rockchip/patches-5.4/002-net-usb-r8152-add-LED-configuration-from-OF.patch create mode 100644 target/linux/rockchip/patches-5.4/003-dt-bindings-net-add-RTL8152-binding-documentation.patch create mode 100644 target/linux/rockchip/patches-5.4/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch diff --git a/target/linux/rockchip/patches-5.4/002-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/rockchip/patches-5.4/002-net-usb-r8152-add-LED-configuration-from-OF.patch new file mode 100644 index 0000000000..53b6413cf3 --- /dev/null +++ b/target/linux/rockchip/patches-5.4/002-net-usb-r8152-add-LED-configuration-from-OF.patch @@ -0,0 +1,74 @@ +From 82985725e071f2a5735052f18e109a32aeac3a0b Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Sun, 26 Jul 2020 02:38:31 +0200 +Subject: [PATCH] net: usb: r8152: add LED configuration from OF + +This adds the ability to configure the LED configuration register using +OF. This way, the correct value for board specific LED configuration can +be determined. + +Signed-off-by: David Bauer +--- + drivers/net/usb/r8152.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -4363,6 +4364,22 @@ static void rtl_tally_reset(struct r8152 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); + } + ++static int r8152_led_configuration(struct r8152 *tp) ++{ ++ u32 led_data; ++ int ret; ++ ++ ret = of_property_read_u32(tp->udev->dev.of_node, "realtek,led-data", ++ &led_data); ++ ++ if (ret) ++ return ret; ++ ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, led_data); ++ ++ return 0; ++} ++ + static void r8152b_init(struct r8152 *tp) + { + u32 ocp_data; +@@ -4404,6 +4421,8 @@ static void r8152b_init(struct r8152 *tp + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); ++ ++ r8152_led_configuration(tp); + } + + static void r8153_init(struct r8152 *tp) +@@ -4533,6 +4552,8 @@ static void r8153_init(struct r8152 *tp) + tp->coalesce = COALESCE_SLOW; + break; + } ++ ++ r8152_led_configuration(tp); + } + + static void r8153b_init(struct r8152 *tp) +@@ -4609,6 +4630,8 @@ static void r8153b_init(struct r8152 *tp + rtl_tally_reset(tp); + + tp->coalesce = 15000; /* 15 us */ ++ ++ r8152_led_configuration(tp); + } + + static int rtl8152_pre_reset(struct usb_interface *intf) diff --git a/target/linux/rockchip/patches-5.4/003-dt-bindings-net-add-RTL8152-binding-documentation.patch b/target/linux/rockchip/patches-5.4/003-dt-bindings-net-add-RTL8152-binding-documentation.patch new file mode 100644 index 0000000000..be262b993c --- /dev/null +++ b/target/linux/rockchip/patches-5.4/003-dt-bindings-net-add-RTL8152-binding-documentation.patch @@ -0,0 +1,54 @@ +From 3ee05f4aa64fc86af3be5bc176ba5808de9260a7 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Sun, 26 Jul 2020 15:30:33 +0200 +Subject: [PATCH] dt-bindings: net: add RTL8152 binding documentation + +Add binding documentation for the Realtek RTL8152 / RTL8153 USB ethernet +adapters. + +Signed-off-by: David Bauer +--- + .../bindings/net/realtek,rtl8152.yaml | 36 +++++++++++++++++++ + 1 file changed, 36 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/realtek,rtl8152.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/realtek,rtl8152.yaml +@@ -0,0 +1,36 @@ ++# SPDX-License-Identifier: GPL-2.0 ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/realtek,rtl8152.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Realtek RTL8152/RTL8153 series USB ethernet ++ ++maintainers: ++ - David Bauer ++ ++properties: ++ compatible: ++ oneOf: ++ - items: ++ - enum: ++ - realtek,rtl8152 ++ - realtek,rtl8153 ++ ++ reg: ++ description: The device number on the USB bus ++ ++ realtek,led-data: ++ description: Value to be written to the LED configuration register. ++ ++required: ++ - compatible ++ - reg ++ ++examples: ++ - | ++ usb-eth@2 { ++ compatible = "realtek,rtl8153"; ++ reg = <2>; ++ realtek,led-data = <0x87>; ++ }; +\ No newline at end of file diff --git a/target/linux/rockchip/patches-5.4/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.4/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch new file mode 100644 index 0000000000..96c7566095 --- /dev/null +++ b/target/linux/rockchip/patches-5.4/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch @@ -0,0 +1,28 @@ +From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Sun, 26 Jul 2020 13:32:59 +0200 +Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S + +This adds the OF node for the USB3 ethernet adapter on the FriendlyARM +NanoPi R2S. Add the correct value for the RTL8153 LED configuration +register to match the blink behavior of the other port on the device. + +Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -354,4 +354,11 @@ + &usbdrd_dwc3 { + dr_mode = "host"; + status = "okay"; ++ ++ usb-eth@2 { ++ compatible = "realtek,rtl8153"; ++ reg = <2>; ++ ++ realtek,led-data = <0x87>; ++ }; + }; From 5a57a1ac1faaa8920ec36f070963b0a976a29525 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Mon, 27 Jul 2020 21:34:24 +0200 Subject: [PATCH 8/9] arm64: dts: rockchip: Add txpbl node for RK3399/RK3328 Some rockchip SoCs like the RK3399 and RK3328 exhibit an issue where tx checksumming does not work with packets larger than 1498. The default Programmable Buffer Length for TX in these GMAC's is not suitable for MTUs higher than 1498. The workaround is to disable TX offloading with 'ethtool -K eth0 tx off rx off' causing performance impacts as it disables hardware checksumming. This patch sets snps,txpbl to 0x4 which is a safe number tested ok for the most popular MTU value of 1500. For reference, see https://lkml.org/lkml/2019/4/1/1382. Signed-off-by: Carlos de Paula Link: https://lore.kernel.org/r/20200218221040.10955-1-me@carlosedp.com Signed-off-by: Heiko Stuebner Signed-off-by: David Bauer --- ...hip-Add-txpbl-node-for-RK3399-RK3328.patch | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 target/linux/rockchip/patches-5.4/004-arm64-dts-rockchip-Add-txpbl-node-for-RK3399-RK3328.patch diff --git a/target/linux/rockchip/patches-5.4/004-arm64-dts-rockchip-Add-txpbl-node-for-RK3399-RK3328.patch b/target/linux/rockchip/patches-5.4/004-arm64-dts-rockchip-Add-txpbl-node-for-RK3399-RK3328.patch new file mode 100644 index 0000000000..8931d5c5a9 --- /dev/null +++ b/target/linux/rockchip/patches-5.4/004-arm64-dts-rockchip-Add-txpbl-node-for-RK3399-RK3328.patch @@ -0,0 +1,54 @@ +From 8a469ee35606ba65448d54e5a2a23302f7e79e3c Mon Sep 17 00:00:00 2001 +From: Carlos de Paula +Date: Tue, 18 Feb 2020 17:10:37 -0500 +Subject: [PATCH] arm64: dts: rockchip: Add txpbl node for RK3399/RK3328 + +Some rockchip SoCs like the RK3399 and RK3328 exhibit an issue +where tx checksumming does not work with packets larger than 1498. + +The default Programmable Buffer Length for TX in these GMAC's is +not suitable for MTUs higher than 1498. The workaround is to disable +TX offloading with 'ethtool -K eth0 tx off rx off' causing performance +impacts as it disables hardware checksumming. + +This patch sets snps,txpbl to 0x4 which is a safe number tested ok for +the most popular MTU value of 1500. + +For reference, see https://lkml.org/lkml/2019/4/1/1382. + +Signed-off-by: Carlos de Paula +Link: https://lore.kernel.org/r/20200218221040.10955-1-me@carlosedp.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 ++ + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + + 2 files changed, 3 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -857,6 +857,7 @@ + resets = <&cru SRST_GMAC2IO_A>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; ++ snps,txpbl = <0x4>; + status = "disabled"; + }; + +@@ -878,6 +879,7 @@ + reset-names = "stmmaceth", "mac-phy"; + phy-mode = "rmii"; + phy-handle = <&phy>; ++ snps,txpbl = <0x4>; + status = "disabled"; + + mdio { +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -288,6 +288,7 @@ + resets = <&cru SRST_A_GMAC>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; ++ snps,txpbl = <0x4>; + status = "disabled"; + }; + From 7a4fc8906cd2256e7381d1c043e19872eeb06883 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Mon, 27 Jul 2020 23:13:02 +0200 Subject: [PATCH 9/9] rockchip: distribute net interrupts This adds a hotplug script for distributing interrupts of eth0 and eth1 across different cores. Otherwise the forwarding performance between eth0 and eth1 is severely affected. The existing SMP distribution mechanic in OpenWrt can't be used here, as the actual device IRQ has to be moved to dedicated cores. In case of eth1, this is in fact the USB3 controller. Signed-off-by: David Bauer --- .../etc/hotplug.d/net/40-net-smp-affinity | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity new file mode 100644 index 0000000000..ab3f954654 --- /dev/null +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -0,0 +1,30 @@ +#!/bin/sh + +[ "$ACTION" = add ] || exit + +get_device_irq() { + local device="$1" + + local line=$(grep -m 1 "${device}\$" /proc/interrupts) + echo $(echo ${line} | sed 's/:.*//') +} + +set_interface_core() { + local core_mask="$1" + local interface="$2" + local device="$3" + + [ -z "${device}" ] && device="$interface" + + local irq=$(get_device_irq "$device") + + echo "${core_mask}" > /proc/irq/${irq}/smp_affinity +} + +case "$(board_name)" in +friendlyarm,nanopi-r2s) + set_interface_core 2 "eth0" + set_interface_core 4 "eth1" "xhci-hcd:usb3" + ;; +esac +