Merge Official Source

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2023-01-04 16:02:24 +08:00
commit 6c36f3daaf
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
94 changed files with 1272 additions and 2677 deletions

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@ -306,6 +306,11 @@ define Build/fit
@mv $@.new $@ @mv $@.new $@
endef endef
define Build/libdeflate-gzip
$(STAGING_DIR_HOST)/bin/libdeflate-gzip -f -12 -c $@ $(1) > $@.new
@mv $@.new $@
endef
define Build/gzip define Build/gzip
$(STAGING_DIR_HOST)/bin/gzip -f -9n -c $@ $(1) > $@.new $(STAGING_DIR_HOST)/bin/gzip -f -9n -c $@ $(1) > $@.new
@mv $@.new $@ @mv $@.new $@

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@ -1,2 +1,2 @@
LINUX_VERSION-5.15 = .85 LINUX_VERSION-5.15 = .86
LINUX_KERNEL_HASH-5.15.85 = 2c0bae29fac98e0a9408914a4551b2971365ac0000351cb255d6bd9aa0849808 LINUX_KERNEL_HASH-5.15.86 = 80fcd9efa443502de9e2750f6dfb59e8de43a5d87a6d2be09dca748d79b5f2ee

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@ -10,9 +10,9 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=bridger PKG_NAME:=bridger
PKG_SOURCE_PROTO:=git PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/nbd168/bridger PKG_SOURCE_URL=https://github.com/nbd168/bridger
PKG_SOURCE_DATE:=2022-04-06 PKG_SOURCE_DATE:=2023-01-03
PKG_SOURCE_VERSION:=e8f6814a85b4ea951657e7018c5d77597400f44a PKG_SOURCE_VERSION:=978c1f9eed07504cc0b84f72ee7384aab722386a
PKG_MIRROR_HASH:=f917e099a9ab2a55745a7254239efabe695a722d5c448342198cdc847a4a24ac PKG_MIRROR_HASH:=2a019b188d8de2fdc95453529d1820b0a7a5576adf161bd19e182c9c1c2b2c85
PKG_LICENSE:=GPL-2.0 PKG_LICENSE:=GPL-2.0
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name> PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>

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@ -10,7 +10,7 @@ Signed-off-by: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>
--- a/drivers/mtd/spi-nor/core.c --- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c
@@ -3095,6 +3095,7 @@ int spi_nor_scan(struct spi_nor *nor, co @@ -3096,6 +3096,7 @@ int spi_nor_scan(struct spi_nor *nor, co
struct device *dev = nor->dev; struct device *dev = nor->dev;
struct mtd_info *mtd = &nor->mtd; struct mtd_info *mtd = &nor->mtd;
struct device_node *np = spi_nor_get_flash_node(nor); struct device_node *np = spi_nor_get_flash_node(nor);
@ -18,7 +18,7 @@ Signed-off-by: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>
int ret; int ret;
int i; int i;
@@ -3149,7 +3150,12 @@ int spi_nor_scan(struct spi_nor *nor, co @@ -3150,7 +3151,12 @@ int spi_nor_scan(struct spi_nor *nor, co
if (ret) if (ret)
return ret; return ret;
@ -34,7 +34,7 @@ Signed-off-by: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>
mtd->type = MTD_NORFLASH; mtd->type = MTD_NORFLASH;
--- a/drivers/mtd/mtdcore.c --- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c
@@ -845,6 +845,17 @@ out_error: @@ -847,6 +847,17 @@ out_error:
*/ */
static void mtd_set_dev_defaults(struct mtd_info *mtd) static void mtd_set_dev_defaults(struct mtd_info *mtd)
{ {

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@ -45,7 +45,7 @@ Submitted-by: Christopher Hill <ch6574@gmail.com>
--- a/drivers/mfd/Kconfig --- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig
@@ -2174,6 +2174,14 @@ config RAVE_SP_CORE @@ -2175,6 +2175,14 @@ config RAVE_SP_CORE
Select this to get support for the Supervisory Processor Select this to get support for the Supervisory Processor
device found on several devices in RAVE line of hardware. device found on several devices in RAVE line of hardware.

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@ -11,7 +11,7 @@ This reverts commit 83b2a8fe43bda0c11981ad6afa5dd0104d78be28.
--- a/drivers/spi/spidev.c --- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c
@@ -402,7 +402,6 @@ spidev_ioctl(struct file *filp, unsigned @@ -413,7 +413,6 @@ spidev_ioctl(struct file *filp, unsigned
else else
retval = get_user(tmp, (u32 __user *)arg); retval = get_user(tmp, (u32 __user *)arg);
if (retval == 0) { if (retval == 0) {
@ -19,7 +19,7 @@ This reverts commit 83b2a8fe43bda0c11981ad6afa5dd0104d78be28.
u32 save = spi->mode; u32 save = spi->mode;
if (tmp & ~SPI_MODE_MASK) { if (tmp & ~SPI_MODE_MASK) {
@@ -410,10 +409,6 @@ spidev_ioctl(struct file *filp, unsigned @@ -421,10 +420,6 @@ spidev_ioctl(struct file *filp, unsigned
break; break;
} }

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@ -13,7 +13,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/spi/spidev.c --- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c
@@ -747,7 +747,7 @@ static int spidev_probe(struct spi_devic @@ -758,7 +758,7 @@ static int spidev_probe(struct spi_devic
* compatible string, it is a Linux implementation thing * compatible string, it is a Linux implementation thing
* rather than a description of the hardware. * rather than a description of the hardware.
*/ */

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@ -14,7 +14,7 @@ use the same logic.
--- a/drivers/tty/serial/amba-pl011.c --- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c
@@ -2744,7 +2744,12 @@ static int pl011_setup_port(struct devic @@ -2756,7 +2756,12 @@ static int pl011_setup_port(struct devic
if (IS_ERR(base)) if (IS_ERR(base))
return PTR_ERR(base); return PTR_ERR(base);

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@ -26,7 +26,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/tty/serial/amba-pl011.c --- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c
@@ -1727,6 +1727,23 @@ static void pl011_put_poll_char(struct u @@ -1730,6 +1730,23 @@ static void pl011_put_poll_char(struct u
#endif /* CONFIG_CONSOLE_POLL */ #endif /* CONFIG_CONSOLE_POLL */
@ -50,7 +50,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
static int pl011_hwinit(struct uart_port *port) static int pl011_hwinit(struct uart_port *port)
{ {
struct uart_amba_port *uap = struct uart_amba_port *uap =
@@ -1743,7 +1760,7 @@ static int pl011_hwinit(struct uart_port @@ -1746,7 +1763,7 @@ static int pl011_hwinit(struct uart_port
if (retval) if (retval)
return retval; return retval;
@ -59,7 +59,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
/* Clear pending error and receive interrupts */ /* Clear pending error and receive interrupts */
pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
@@ -2440,7 +2457,7 @@ static int pl011_console_setup(struct co @@ -2452,7 +2469,7 @@ static int pl011_console_setup(struct co
plat->init(); plat->init();
} }
@ -68,7 +68,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
if (uap->vendor->fixed_options) { if (uap->vendor->fixed_options) {
baud = uap->fixed_baud; baud = uap->fixed_baud;
@@ -2657,6 +2674,7 @@ static struct uart_driver amba_reg = { @@ -2669,6 +2686,7 @@ static struct uart_driver amba_reg = {
.cons = AMBA_CONSOLE, .cons = AMBA_CONSOLE,
}; };
@ -76,7 +76,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
static int pl011_probe_dt_alias(int index, struct device *dev) static int pl011_probe_dt_alias(int index, struct device *dev)
{ {
struct device_node *np; struct device_node *np;
@@ -2688,6 +2706,7 @@ static int pl011_probe_dt_alias(int inde @@ -2700,6 +2718,7 @@ static int pl011_probe_dt_alias(int inde
return ret; return ret;
} }

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@ -17,7 +17,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/tty/serial/amba-pl011.c --- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c
@@ -1432,6 +1432,7 @@ static bool pl011_tx_char(struct uart_am @@ -1435,6 +1435,7 @@ static bool pl011_tx_char(struct uart_am
return false; /* unable to transmit character */ return false; /* unable to transmit character */
pl011_write(c, uap, REG_DR); pl011_write(c, uap, REG_DR);

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@ -36,7 +36,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
- reg - reg
--- a/drivers/tty/serial/amba-pl011.c --- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c
@@ -2835,6 +2835,11 @@ static int pl011_probe(struct amba_devic @@ -2847,6 +2847,11 @@ static int pl011_probe(struct amba_devic
if (IS_ERR(uap->clk)) if (IS_ERR(uap->clk))
return PTR_ERR(uap->clk); return PTR_ERR(uap->clk);

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@ -29,7 +29,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/tty/serial/amba-pl011.c --- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c
@@ -1493,6 +1493,10 @@ static bool pl011_tx_chars(struct uart_a @@ -1496,6 +1496,10 @@ static bool pl011_tx_chars(struct uart_a
if (likely(from_irq) && count-- == 0) if (likely(from_irq) && count-- == 0)
break; break;

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@ -36,7 +36,7 @@ Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
static DEFINE_MUTEX(transaction_lock); static DEFINE_MUTEX(transaction_lock);
static void response_callback(struct mbox_client *cl, void *msg) static void response_callback(struct mbox_client *cl, void *msg)
@@ -279,6 +281,7 @@ static int rpi_firmware_probe(struct pla @@ -280,6 +282,7 @@ static int rpi_firmware_probe(struct pla
kref_init(&fw->consumers); kref_init(&fw->consumers);
platform_set_drvdata(pdev, fw); platform_set_drvdata(pdev, fw);
@ -44,7 +44,7 @@ Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
rpi_firmware_print_firmware_revision(fw); rpi_firmware_print_firmware_revision(fw);
rpi_register_hwmon_driver(dev, fw); rpi_register_hwmon_driver(dev, fw);
@@ -307,6 +310,7 @@ static int rpi_firmware_remove(struct pl @@ -308,6 +311,7 @@ static int rpi_firmware_remove(struct pl
rpi_clk = NULL; rpi_clk = NULL;
rpi_firmware_put(fw); rpi_firmware_put(fw);
@ -52,7 +52,7 @@ Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
return 0; return 0;
} }
@@ -381,7 +385,18 @@ static struct platform_driver rpi_firmwa @@ -382,7 +386,18 @@ static struct platform_driver rpi_firmwa
.shutdown = rpi_firmware_shutdown, .shutdown = rpi_firmware_shutdown,
.remove = rpi_firmware_remove, .remove = rpi_firmware_remove,
}; };

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@ -27,7 +27,7 @@ mfd: Add rpi_sense_core of compatible string
--- a/drivers/input/joystick/Kconfig --- a/drivers/input/joystick/Kconfig
+++ b/drivers/input/joystick/Kconfig +++ b/drivers/input/joystick/Kconfig
@@ -399,4 +399,12 @@ config JOYSTICK_N64 @@ -400,4 +400,12 @@ config JOYSTICK_N64
Say Y here if you want enable support for the four Say Y here if you want enable support for the four
built-in controller ports on the Nintendo 64 console. built-in controller ports on the Nintendo 64 console.

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@ -48,7 +48,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
static void static void
rpi_firmware_print_firmware_revision(struct rpi_firmware *fw) rpi_firmware_print_firmware_revision(struct rpi_firmware *fw)
{ {
@@ -386,15 +407,32 @@ static struct platform_driver rpi_firmwa @@ -387,15 +408,32 @@ static struct platform_driver rpi_firmwa
.remove = rpi_firmware_remove, .remove = rpi_firmware_remove,
}; };

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@ -80,7 +80,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
} }
static void static void
@@ -338,6 +375,7 @@ static int rpi_firmware_probe(struct pla @@ -339,6 +376,7 @@ static int rpi_firmware_probe(struct pla
g_pdev = pdev; g_pdev = pdev;
rpi_firmware_print_firmware_revision(fw); rpi_firmware_print_firmware_revision(fw);

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@ -36,7 +36,7 @@ Co-authored-by: Phil Elwell <phil@raspberrypi.org>
MODULE_DESCRIPTION("BCM2835 clock driver"); MODULE_DESCRIPTION("BCM2835 clock driver");
--- a/drivers/firmware/raspberrypi.c --- a/drivers/firmware/raspberrypi.c
+++ b/drivers/firmware/raspberrypi.c +++ b/drivers/firmware/raspberrypi.c
@@ -498,7 +498,7 @@ out2: @@ -499,7 +499,7 @@ out2:
out1: out1:
return ret; return ret;
} }

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@ -1,55 +0,0 @@
From cf7d5f766e0a9eeb09271c36f546ac0a1fdc0444 Mon Sep 17 00:00:00 2001
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
Date: Fri, 24 Jan 2020 14:22:06 +0000
Subject: [PATCH] drm/fourcc: Add packed 10bit YUV 4:2:0 format
Adds a format that is 3 10bit YUV 4:2:0 samples packed into
a 32bit work (with 2 spare bits).
Supported on Broadcom BCM2711 chips.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
2 files changed, 14 insertions(+)
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -266,6 +266,9 @@ const struct drm_format_info *__drm_form
.num_planes = 3, .char_per_block = { 2, 2, 2 },
.block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0,
.vsub = 0, .is_yuv = true },
+ { .format = DRM_FORMAT_P030, .depth = 0, .num_planes = 2,
+ .char_per_block = { 4, 4, 0 }, .block_w = { 3, 0, 0 }, .block_h = { 1, 0, 0 },
+ .hsub = 2, .vsub = 2, .is_yuv = true},
};
unsigned int i;
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -325,6 +325,13 @@ extern "C" {
#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
/*
+ * 2 plane YCbCr MSB aligned, 3 pixels packed into 4 bytes.
+ * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
+ * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
+ */
+#define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
@@ -842,6 +849,10 @@ drm_fourcc_canonicalize_nvidia_format_mo
* and UV. Some SAND-using hardware stores UV in a separate tiled
* image from Y to reduce the column height, which is not supported
* with these modifiers.
+ *
+ * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
+ * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
+ * wide, but as this is a 10 bpp format that translates to 96 pixels.
*/
#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \

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@ -26,7 +26,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
/* Device and char device-related information */ /* Device and char device-related information */
static DEFINE_IDA(gpio_ida); static DEFINE_IDA(gpio_ida);
static dev_t gpio_devt; static dev_t gpio_devt;
@@ -2392,8 +2394,8 @@ int gpiod_direction_output(struct gpio_d @@ -2395,8 +2397,8 @@ int gpiod_direction_output(struct gpio_d
value = !!value; value = !!value;
/* GPIOs used for enabled IRQs shall not be set as output */ /* GPIOs used for enabled IRQs shall not be set as output */
@ -37,7 +37,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
gpiod_err(desc, gpiod_err(desc,
"%s: tried to set a GPIO tied to an IRQ as output\n", "%s: tried to set a GPIO tied to an IRQ as output\n",
__func__); __func__);
@@ -3211,8 +3213,8 @@ int gpiochip_lock_as_irq(struct gpio_chi @@ -3213,8 +3215,8 @@ int gpiochip_lock_as_irq(struct gpio_chi
} }
/* To be valid for IRQ the line needs to be input or open drain */ /* To be valid for IRQ the line needs to be input or open drain */

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@ -15,7 +15,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
--- a/drivers/spi/spidev.c --- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c
@@ -669,6 +669,7 @@ static const struct file_operations spid @@ -680,6 +680,7 @@ static const struct file_operations spid
static struct class *spidev_class; static struct class *spidev_class;
static const struct spi_device_id spidev_spi_ids[] = { static const struct spi_device_id spidev_spi_ids[] = {

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@ -205,7 +205,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
xhci_err(xhci, "Tried to move enqueue past ring segment\n"); xhci_err(xhci, "Tried to move enqueue past ring segment\n");
return; return;
} }
@@ -3153,7 +3156,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd @@ -3159,7 +3162,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd
* that clears the EHB. * that clears the EHB.
*/ */
while (xhci_handle_event(xhci) > 0) { while (xhci_handle_event(xhci) > 0) {
@ -214,7 +214,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
continue; continue;
xhci_update_erst_dequeue(xhci, event_ring_deq); xhci_update_erst_dequeue(xhci, event_ring_deq);
event_ring_deq = xhci->event_ring->dequeue; event_ring_deq = xhci->event_ring->dequeue;
@@ -3295,7 +3298,8 @@ static int prepare_ring(struct xhci_hcd @@ -3301,7 +3304,8 @@ static int prepare_ring(struct xhci_hcd
} }
} }

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@ -440,9 +440,9 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
st7701->dsi = dsi; st7701->dsi = dsi;
- st7701->desc = desc; - st7701->desc = desc;
return mipi_dsi_attach(dsi); ret = mipi_dsi_attach(dsi);
} if (ret)
@@ -397,21 +639,115 @@ static int st7701_dsi_remove(struct mipi @@ -405,21 +647,115 @@ static int st7701_dsi_remove(struct mipi
return 0; return 0;
} }

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@ -47,7 +47,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
} }
static int spi_gpio_setup(struct spi_device *spi) static int spi_gpio_setup(struct spi_device *spi)
@@ -289,6 +297,7 @@ static int spi_gpio_request(struct devic @@ -299,6 +307,7 @@ static int spi_gpio_request(struct devic
if (IS_ERR(spi_gpio->miso)) if (IS_ERR(spi_gpio->miso))
return PTR_ERR(spi_gpio->miso); return PTR_ERR(spi_gpio->miso);

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@ -36,7 +36,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
--- a/drivers/usb/host/xhci-ring.c --- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c
@@ -3608,14 +3608,15 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3614,14 +3614,15 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
unsigned int num_trbs; unsigned int num_trbs;
unsigned int start_cycle, num_sgs = 0; unsigned int start_cycle, num_sgs = 0;
unsigned int enqd_len, block_len, trb_buff_len, full_len; unsigned int enqd_len, block_len, trb_buff_len, full_len;
@ -54,7 +54,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
full_len = urb->transfer_buffer_length; full_len = urb->transfer_buffer_length;
/* If we have scatter/gather list, we use it. */ /* If we have scatter/gather list, we use it. */
if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) { if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
@@ -3652,6 +3653,17 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3658,6 +3659,17 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
start_cycle = ring->cycle_state; start_cycle = ring->cycle_state;
send_addr = addr; send_addr = addr;
@ -72,7 +72,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
/* Queue the TRBs, even if they are zero-length */ /* Queue the TRBs, even if they are zero-length */
for (enqd_len = 0; first_trb || enqd_len < full_len; for (enqd_len = 0; first_trb || enqd_len < full_len;
enqd_len += trb_buff_len) { enqd_len += trb_buff_len) {
@@ -3664,6 +3676,11 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3670,6 +3682,11 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
if (enqd_len + trb_buff_len > full_len) if (enqd_len + trb_buff_len > full_len)
trb_buff_len = full_len - enqd_len; trb_buff_len = full_len - enqd_len;

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@ -13,7 +13,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
--- a/drivers/usb/host/xhci-ring.c --- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c
@@ -3608,7 +3608,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3614,7 +3614,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
unsigned int num_trbs; unsigned int num_trbs;
unsigned int start_cycle, num_sgs = 0; unsigned int start_cycle, num_sgs = 0;
unsigned int enqd_len, block_len, trb_buff_len, full_len; unsigned int enqd_len, block_len, trb_buff_len, full_len;
@ -22,7 +22,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
u32 field, length_field, remainder, maxpacket; u32 field, length_field, remainder, maxpacket;
u64 addr, send_addr; u64 addr, send_addr;
@@ -3654,14 +3654,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3660,14 +3660,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
send_addr = addr; send_addr = addr;
if (xhci->quirks & XHCI_VLI_SS_BULK_OUT_BUG && if (xhci->quirks & XHCI_VLI_SS_BULK_OUT_BUG &&
@ -40,7 +40,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
} }
/* Queue the TRBs, even if they are zero-length */ /* Queue the TRBs, even if they are zero-length */
@@ -3676,7 +3671,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3682,7 +3677,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
if (enqd_len + trb_buff_len > full_len) if (enqd_len + trb_buff_len > full_len)
trb_buff_len = full_len - enqd_len; trb_buff_len = full_len - enqd_len;

View File

@ -22,7 +22,7 @@ Reviewed-by: Vadim Pasternak <vadimp@nvidia.com>
--- a/drivers/hwmon/Kconfig --- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig
@@ -1684,6 +1684,19 @@ config SENSORS_EMC2103 @@ -1685,6 +1685,19 @@ config SENSORS_EMC2103
This driver can also be built as a module. If so, the module This driver can also be built as a module. If so, the module
will be called emc2103. will be called emc2103.

View File

@ -116,7 +116,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
} }
--- a/drivers/gpio/gpiolib.c --- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c
@@ -1799,7 +1799,8 @@ int gpiochip_add_pingroup_range(struct g @@ -1802,7 +1802,8 @@ int gpiochip_add_pingroup_range(struct g
list_add_tail(&pin_range->node, &gdev->pin_ranges); list_add_tail(&pin_range->node, &gdev->pin_ranges);
@ -126,7 +126,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
} }
EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range); EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range);
@@ -1856,7 +1857,7 @@ int gpiochip_add_pin_range(struct gpio_c @@ -1859,7 +1860,7 @@ int gpiochip_add_pin_range(struct gpio_c
list_add_tail(&pin_range->node, &gdev->pin_ranges); list_add_tail(&pin_range->node, &gdev->pin_ranges);

View File

@ -107,7 +107,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
} }
static struct clk clk_pcie = { static struct clk clk_pcie = {
@@ -548,6 +562,21 @@ static struct clk_lookup bcm6368_clks[] @@ -550,6 +564,21 @@ static struct clk_lookup bcm6368_clks[]
CLKDEV_INIT(NULL, "ipsec", &clk_ipsec), CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
}; };
@ -129,7 +129,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
#define HSSPI_PLL_HZ_6328 133333333 #define HSSPI_PLL_HZ_6328 133333333
#define HSSPI_PLL_HZ_6362 400000000 #define HSSPI_PLL_HZ_6362 400000000
@@ -580,6 +609,10 @@ static int __init bcm63xx_clk_init(void) @@ -582,6 +611,10 @@ static int __init bcm63xx_clk_init(void)
case BCM6368_CPU_ID: case BCM6368_CPU_ID:
clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks)); clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));
break; break;

View File

@ -57,7 +57,7 @@ Subject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318
mask = CKCTL_6328_HSSPI_EN; mask = CKCTL_6328_HSSPI_EN;
else if (BCMCPU_IS_6362()) else if (BCMCPU_IS_6362())
mask = CKCTL_6362_HSSPI_EN; mask = CKCTL_6362_HSSPI_EN;
@@ -456,6 +458,19 @@ static struct clk_lookup bcm3368_clks[] @@ -458,6 +460,19 @@ static struct clk_lookup bcm3368_clks[]
CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1), CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
}; };
@ -77,7 +77,7 @@ Subject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318
static struct clk_lookup bcm6328_clks[] = { static struct clk_lookup bcm6328_clks[] = {
/* fixed rate clocks */ /* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph), CLKDEV_INIT(NULL, "periph", &clk_periph),
@@ -577,6 +592,7 @@ static struct clk_lookup bcm63268_clks[] @@ -579,6 +594,7 @@ static struct clk_lookup bcm63268_clks[]
CLKDEV_INIT(NULL, "pcie", &clk_pcie), CLKDEV_INIT(NULL, "pcie", &clk_pcie),
}; };
@ -85,7 +85,7 @@ Subject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318
#define HSSPI_PLL_HZ_6328 133333333 #define HSSPI_PLL_HZ_6328 133333333
#define HSSPI_PLL_HZ_6362 400000000 #define HSSPI_PLL_HZ_6362 400000000
@@ -586,6 +602,10 @@ static int __init bcm63xx_clk_init(void) @@ -588,6 +604,10 @@ static int __init bcm63xx_clk_init(void)
case BCM3368_CPU_ID: case BCM3368_CPU_ID:
clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks)); clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
break; break;

View File

@ -9,7 +9,7 @@ Subject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree
--- a/arch/mips/bcm63xx/clk.c --- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c
@@ -501,6 +501,8 @@ static struct clk_lookup bcm3368_clks[] @@ -503,6 +503,8 @@ static struct clk_lookup bcm3368_clks[]
CLKDEV_INIT(NULL, "periph", &clk_periph), CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
@ -18,7 +18,7 @@ Subject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree
/* gated clocks */ /* gated clocks */
CLKDEV_INIT(NULL, "enet0", &clk_enet0), CLKDEV_INIT(NULL, "enet0", &clk_enet0),
CLKDEV_INIT(NULL, "enet1", &clk_enet1), CLKDEV_INIT(NULL, "enet1", &clk_enet1),
@@ -517,7 +519,9 @@ static struct clk_lookup bcm6318_clks[] @@ -519,7 +521,9 @@ static struct clk_lookup bcm6318_clks[]
/* fixed rate clocks */ /* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph), CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
@ -28,7 +28,7 @@ Subject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree
/* gated clocks */ /* gated clocks */
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
CLKDEV_INIT(NULL, "usbh", &clk_usbh), CLKDEV_INIT(NULL, "usbh", &clk_usbh),
@@ -531,7 +535,10 @@ static struct clk_lookup bcm6328_clks[] @@ -533,7 +537,10 @@ static struct clk_lookup bcm6328_clks[]
CLKDEV_INIT(NULL, "periph", &clk_periph), CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
@ -39,7 +39,7 @@ Subject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree
/* gated clocks */ /* gated clocks */
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
CLKDEV_INIT(NULL, "usbh", &clk_usbh), CLKDEV_INIT(NULL, "usbh", &clk_usbh),
@@ -544,6 +551,7 @@ static struct clk_lookup bcm6338_clks[] @@ -546,6 +553,7 @@ static struct clk_lookup bcm6338_clks[]
/* fixed rate clocks */ /* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph), CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
@ -47,7 +47,7 @@ Subject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree
/* gated clocks */ /* gated clocks */
CLKDEV_INIT(NULL, "enet0", &clk_enet0), CLKDEV_INIT(NULL, "enet0", &clk_enet0),
CLKDEV_INIT(NULL, "enet1", &clk_enet1), CLKDEV_INIT(NULL, "enet1", &clk_enet1),
@@ -558,6 +566,7 @@ static struct clk_lookup bcm6345_clks[] @@ -560,6 +568,7 @@ static struct clk_lookup bcm6345_clks[]
/* fixed rate clocks */ /* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph), CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
@ -55,7 +55,7 @@ Subject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree
/* gated clocks */ /* gated clocks */
CLKDEV_INIT(NULL, "enet0", &clk_enet0), CLKDEV_INIT(NULL, "enet0", &clk_enet0),
CLKDEV_INIT(NULL, "enet1", &clk_enet1), CLKDEV_INIT(NULL, "enet1", &clk_enet1),
@@ -572,6 +581,7 @@ static struct clk_lookup bcm6348_clks[] @@ -574,6 +583,7 @@ static struct clk_lookup bcm6348_clks[]
/* fixed rate clocks */ /* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph), CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
@ -63,7 +63,7 @@ Subject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree
/* gated clocks */ /* gated clocks */
CLKDEV_INIT(NULL, "enet0", &clk_enet0), CLKDEV_INIT(NULL, "enet0", &clk_enet0),
CLKDEV_INIT(NULL, "enet1", &clk_enet1), CLKDEV_INIT(NULL, "enet1", &clk_enet1),
@@ -588,6 +598,8 @@ static struct clk_lookup bcm6358_clks[] @@ -590,6 +600,8 @@ static struct clk_lookup bcm6358_clks[]
CLKDEV_INIT(NULL, "periph", &clk_periph), CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
@ -72,7 +72,7 @@ Subject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree
/* gated clocks */ /* gated clocks */
CLKDEV_INIT(NULL, "enet0", &clk_enet0), CLKDEV_INIT(NULL, "enet0", &clk_enet0),
CLKDEV_INIT(NULL, "enet1", &clk_enet1), CLKDEV_INIT(NULL, "enet1", &clk_enet1),
@@ -607,7 +619,10 @@ static struct clk_lookup bcm6362_clks[] @@ -609,7 +621,10 @@ static struct clk_lookup bcm6362_clks[]
CLKDEV_INIT(NULL, "periph", &clk_periph), CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
@ -83,7 +83,7 @@ Subject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree
/* gated clocks */ /* gated clocks */
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
CLKDEV_INIT(NULL, "usbh", &clk_usbh), CLKDEV_INIT(NULL, "usbh", &clk_usbh),
@@ -623,6 +638,8 @@ static struct clk_lookup bcm6368_clks[] @@ -625,6 +640,8 @@ static struct clk_lookup bcm6368_clks[]
CLKDEV_INIT(NULL, "periph", &clk_periph), CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
@ -92,7 +92,7 @@ Subject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree
/* gated clocks */ /* gated clocks */
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
CLKDEV_INIT(NULL, "usbh", &clk_usbh), CLKDEV_INIT(NULL, "usbh", &clk_usbh),
@@ -637,7 +654,10 @@ static struct clk_lookup bcm63268_clks[] @@ -639,7 +656,10 @@ static struct clk_lookup bcm63268_clks[]
CLKDEV_INIT(NULL, "periph", &clk_periph), CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),

View File

@ -24,7 +24,7 @@
* Internal peripheral clock * Internal peripheral clock
*/ */
static struct clk clk_periph = { static struct clk clk_periph = {
@@ -624,6 +641,7 @@ static struct clk_lookup bcm6362_clks[] @@ -626,6 +643,7 @@ static struct clk_lookup bcm6362_clks[]
CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll), CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll), CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll),
/* gated clocks */ /* gated clocks */
@ -32,7 +32,7 @@
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
CLKDEV_INIT(NULL, "usbh", &clk_usbh), CLKDEV_INIT(NULL, "usbh", &clk_usbh),
CLKDEV_INIT(NULL, "usbd", &clk_usbd), CLKDEV_INIT(NULL, "usbd", &clk_usbd),
@@ -641,6 +659,7 @@ static struct clk_lookup bcm6368_clks[] @@ -643,6 +661,7 @@ static struct clk_lookup bcm6368_clks[]
CLKDEV_INIT("10000100.serial", "refclk", &clk_periph), CLKDEV_INIT("10000100.serial", "refclk", &clk_periph),
CLKDEV_INIT("10000120.serial", "refclk", &clk_periph), CLKDEV_INIT("10000120.serial", "refclk", &clk_periph),
/* gated clocks */ /* gated clocks */
@ -40,7 +40,7 @@
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
CLKDEV_INIT(NULL, "usbh", &clk_usbh), CLKDEV_INIT(NULL, "usbh", &clk_usbh),
CLKDEV_INIT(NULL, "usbd", &clk_usbd), CLKDEV_INIT(NULL, "usbd", &clk_usbd),
@@ -659,6 +678,7 @@ static struct clk_lookup bcm63268_clks[] @@ -661,6 +680,7 @@ static struct clk_lookup bcm63268_clks[]
CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll), CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll), CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll),
/* gated clocks */ /* gated clocks */

View File

@ -0,0 +1,32 @@
From 94c821c74bf5fe0c25e09df5334a16f98608db90 Mon Sep 17 00:00:00 2001
From: Seth David Schoen <schoen@loyalty.org>
Date: Wed, 12 May 2021 21:37:49 -0700
Subject: [PATCH] ip: Treat IPv4 segment's lowest address as unicast
Treat only the highest, not the lowest, IPv4 address within a local
subnet as a broadcast address.
Signed-off-by: Seth David Schoen <schoen@loyalty.org>
Suggested-by: John Gilmore <gnu@toad.com>
Acked-by: Dave Taht <dave.taht@gmail.com>
Reviewed-by: David Ahern <dsahern@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Link: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=94c821c74bf5
---
net/ipv4/fib_frontend.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
--- a/net/ipv4/fib_frontend.c
+++ b/net/ipv4/fib_frontend.c
@@ -1129,10 +1129,8 @@ void fib_add_ifaddr(struct in_ifaddr *if
prefix, ifa->ifa_prefixlen, prim,
ifa->ifa_rt_priority);
- /* Add network specific broadcasts, when it takes a sense */
+ /* Add the network broadcast address, when it makes sense */
if (ifa->ifa_prefixlen < 31) {
- fib_magic(RTM_NEWROUTE, RTN_BROADCAST, prefix, 32,
- prim, 0);
fib_magic(RTM_NEWROUTE, RTN_BROADCAST, prefix | ~mask,
32, prim, 0);
arp_invalidate(dev, prefix | ~mask, false);

View File

@ -297,7 +297,7 @@ Change-Id: I25d9eda8c6bdc7c3653b9f210a159d6c247c81e8
} }
--- a/kernel/fork.c --- a/kernel/fork.c
+++ b/kernel/fork.c +++ b/kernel/fork.c
@@ -1080,6 +1080,7 @@ static struct mm_struct *mm_init(struct @@ -1083,6 +1083,7 @@ static struct mm_struct *mm_init(struct
goto fail_nocontext; goto fail_nocontext;
mm->user_ns = get_user_ns(user_ns); mm->user_ns = get_user_ns(user_ns);
@ -305,7 +305,7 @@ Change-Id: I25d9eda8c6bdc7c3653b9f210a159d6c247c81e8
return mm; return mm;
fail_nocontext: fail_nocontext:
@@ -1122,6 +1123,7 @@ static inline void __mmput(struct mm_str @@ -1125,6 +1126,7 @@ static inline void __mmput(struct mm_str
} }
if (mm->binfmt) if (mm->binfmt)
module_put(mm->binfmt->module); module_put(mm->binfmt->module);
@ -313,7 +313,7 @@ Change-Id: I25d9eda8c6bdc7c3653b9f210a159d6c247c81e8
mmdrop(mm); mmdrop(mm);
} }
@@ -2617,6 +2619,13 @@ pid_t kernel_clone(struct kernel_clone_a @@ -2622,6 +2624,13 @@ pid_t kernel_clone(struct kernel_clone_a
get_task_struct(p); get_task_struct(p);
} }

View File

@ -103,4 +103,4 @@ Link: https://lore.kernel.org/linux-mtd/20220622010628.30414-4-ansuelsmth@gmail.
+ mtd_check_of_node(mtd); + mtd_check_of_node(mtd);
of_node_get(mtd_get_of_node(mtd)); of_node_get(mtd_get_of_node(mtd));
error = device_register(&mtd->dev); error = device_register(&mtd->dev);
if (error) if (error) {

View File

@ -25,7 +25,7 @@ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
--- a/drivers/mtd/mtdcore.c --- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c
@@ -1227,6 +1227,34 @@ int __get_mtd_device(struct mtd_info *mt @@ -1229,6 +1229,34 @@ int __get_mtd_device(struct mtd_info *mt
EXPORT_SYMBOL_GPL(__get_mtd_device); EXPORT_SYMBOL_GPL(__get_mtd_device);
/** /**

View File

@ -27,7 +27,7 @@ Link: https://lore.kernel.org/linux-mtd/20221022211318.32009-2-zajec5@gmail.com
#include <linux/mtd/mtd.h> #include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h> #include <linux/mtd/partitions.h>
@@ -746,6 +747,17 @@ int add_mtd_device(struct mtd_info *mtd) @@ -748,6 +749,17 @@ int add_mtd_device(struct mtd_info *mtd)
not->add(mtd); not->add(mtd);
mutex_unlock(&mtd_table_mutex); mutex_unlock(&mtd_table_mutex);

View File

@ -233,7 +233,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
static inline void static inline void
--- a/include/linux/netdevice.h --- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h +++ b/include/linux/netdevice.h
@@ -863,6 +863,7 @@ enum net_device_path_type { @@ -870,6 +870,7 @@ enum net_device_path_type {
DEV_PATH_BRIDGE, DEV_PATH_BRIDGE,
DEV_PATH_PPPOE, DEV_PATH_PPPOE,
DEV_PATH_DSA, DEV_PATH_DSA,
@ -241,7 +241,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
}; };
struct net_device_path { struct net_device_path {
@@ -888,6 +889,12 @@ struct net_device_path { @@ -895,6 +896,12 @@ struct net_device_path {
int port; int port;
u16 proto; u16 proto;
} dsa; } dsa;

View File

@ -87,7 +87,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
stmmac_clear_tx_descriptors(priv, queue); stmmac_clear_tx_descriptors(priv, queue);
stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
@@ -7398,6 +7393,25 @@ int stmmac_suspend(struct device *dev) @@ -7400,6 +7395,25 @@ int stmmac_suspend(struct device *dev)
} }
EXPORT_SYMBOL_GPL(stmmac_suspend); EXPORT_SYMBOL_GPL(stmmac_suspend);
@ -113,7 +113,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
/** /**
* stmmac_reset_queues_param - reset queue parameters * stmmac_reset_queues_param - reset queue parameters
* @priv: device pointer * @priv: device pointer
@@ -7408,22 +7422,11 @@ static void stmmac_reset_queues_param(st @@ -7410,22 +7424,11 @@ static void stmmac_reset_queues_param(st
u32 tx_cnt = priv->plat->tx_queues_to_use; u32 tx_cnt = priv->plat->tx_queues_to_use;
u32 queue; u32 queue;

View File

@ -1210,7 +1210,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
if (netif_running(dev)) if (netif_running(dev))
ret = stmmac_open(dev); ret = stmmac_open(dev);
@@ -7344,7 +7348,7 @@ int stmmac_suspend(struct device *dev) @@ -7346,7 +7350,7 @@ int stmmac_suspend(struct device *dev)
stmmac_disable_all_queues(priv); stmmac_disable_all_queues(priv);
for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@ -1219,7 +1219,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
if (priv->eee_enabled) { if (priv->eee_enabled) {
priv->tx_path_in_lpi_mode = false; priv->tx_path_in_lpi_mode = false;
@@ -7395,7 +7399,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend); @@ -7397,7 +7401,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend);
static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue)
{ {
@ -1228,7 +1228,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
rx_q->cur_rx = 0; rx_q->cur_rx = 0;
rx_q->dirty_rx = 0; rx_q->dirty_rx = 0;
@@ -7403,7 +7407,7 @@ static void stmmac_reset_rx_queue(struct @@ -7405,7 +7409,7 @@ static void stmmac_reset_rx_queue(struct
static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue)
{ {
@ -1250,7 +1250,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
stmmac_set_rx_tail_ptr(priv, priv->ioaddr, tail, i); stmmac_set_rx_tail_ptr(priv, priv->ioaddr, tail, i);
stmmac_start_rx(priv, priv->ioaddr, i); stmmac_start_rx(priv, priv->ioaddr, i);
@@ -1680,7 +1680,7 @@ cleanup: @@ -1684,7 +1684,7 @@ cleanup:
static int __stmmac_test_jumbo(struct stmmac_priv *priv, u16 queue) static int __stmmac_test_jumbo(struct stmmac_priv *priv, u16 queue)
{ {
struct stmmac_packet_attrs attr = { }; struct stmmac_packet_attrs attr = { };
@ -1259,7 +1259,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
attr.dst = priv->dev->dev_addr; attr.dst = priv->dev->dev_addr;
attr.max_size = size - ETH_FCS_LEN; attr.max_size = size - ETH_FCS_LEN;
@@ -1763,7 +1763,7 @@ static int stmmac_test_tbs(struct stmmac @@ -1767,7 +1767,7 @@ static int stmmac_test_tbs(struct stmmac
/* Find first TBS enabled Queue, if any */ /* Find first TBS enabled Queue, if any */
for (i = 0; i < priv->plat->tx_queues_to_use; i++) for (i = 0; i < priv->plat->tx_queues_to_use; i++)

View File

@ -1150,7 +1150,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
dma_desc_error: dma_desc_error:
return ret; return ret;
} }
@@ -7490,7 +7606,7 @@ int stmmac_resume(struct device *dev) @@ -7492,7 +7608,7 @@ int stmmac_resume(struct device *dev)
stmmac_reset_queues_param(priv); stmmac_reset_queues_param(priv);
stmmac_free_tx_skbufs(priv); stmmac_free_tx_skbufs(priv);

View File

@ -77,7 +77,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
#include "mtdcore.h" #include "mtdcore.h"
@@ -1079,6 +1080,8 @@ int mtd_device_parse_register(struct mtd @@ -1081,6 +1082,8 @@ int mtd_device_parse_register(struct mtd
ret = mtd_otp_nvmem_add(mtd); ret = mtd_otp_nvmem_add(mtd);

View File

@ -12,7 +12,7 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
--- a/drivers/mtd/mtdcore.c --- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c
@@ -759,7 +759,8 @@ int add_mtd_device(struct mtd_info *mtd) @@ -761,7 +761,8 @@ int add_mtd_device(struct mtd_info *mtd)
mutex_unlock(&mtd_table_mutex); mutex_unlock(&mtd_table_mutex);

View File

@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/include/linux/netdevice.h --- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h +++ b/include/linux/netdevice.h
@@ -1669,6 +1669,10 @@ enum netdev_priv_flags { @@ -1676,6 +1676,10 @@ enum netdev_priv_flags {
IFF_TX_SKB_NO_LINEAR = BIT_ULL(31), IFF_TX_SKB_NO_LINEAR = BIT_ULL(31),
}; };
@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
#define IFF_802_1Q_VLAN IFF_802_1Q_VLAN #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN
#define IFF_EBRIDGE IFF_EBRIDGE #define IFF_EBRIDGE IFF_EBRIDGE
#define IFF_BONDING IFF_BONDING #define IFF_BONDING IFF_BONDING
@@ -1701,6 +1705,7 @@ enum netdev_priv_flags { @@ -1708,6 +1712,7 @@ enum netdev_priv_flags {
#define IFF_L3MDEV_RX_HANDLER IFF_L3MDEV_RX_HANDLER #define IFF_L3MDEV_RX_HANDLER IFF_L3MDEV_RX_HANDLER
#define IFF_LIVE_RENAME_OK IFF_LIVE_RENAME_OK #define IFF_LIVE_RENAME_OK IFF_LIVE_RENAME_OK
#define IFF_TX_SKB_NO_LINEAR IFF_TX_SKB_NO_LINEAR #define IFF_TX_SKB_NO_LINEAR IFF_TX_SKB_NO_LINEAR
@ -38,7 +38,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
/* Specifies the type of the struct net_device::ml_priv pointer */ /* Specifies the type of the struct net_device::ml_priv pointer */
enum netdev_ml_priv_type { enum netdev_ml_priv_type {
@@ -2002,6 +2007,7 @@ struct net_device { @@ -2009,6 +2014,7 @@ struct net_device {
/* Read-mostly cache-line for fast-path access */ /* Read-mostly cache-line for fast-path access */
unsigned int flags; unsigned int flags;
unsigned int priv_flags; unsigned int priv_flags;
@ -46,7 +46,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
const struct net_device_ops *netdev_ops; const struct net_device_ops *netdev_ops;
int ifindex; int ifindex;
unsigned short gflags; unsigned short gflags;
@@ -2062,6 +2068,11 @@ struct net_device { @@ -2069,6 +2075,11 @@ struct net_device {
const struct tlsdev_ops *tlsdev_ops; const struct tlsdev_ops *tlsdev_ops;
#endif #endif
@ -58,7 +58,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
const struct header_ops *header_ops; const struct header_ops *header_ops;
unsigned char operstate; unsigned char operstate;
@@ -2136,6 +2147,10 @@ struct net_device { @@ -2143,6 +2154,10 @@ struct net_device {
struct mctp_dev __rcu *mctp_ptr; struct mctp_dev __rcu *mctp_ptr;
#endif #endif

View File

@ -105,7 +105,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
{ {
--- a/include/linux/gpio/consumer.h --- a/include/linux/gpio/consumer.h
+++ b/include/linux/gpio/consumer.h +++ b/include/linux/gpio/consumer.h
@@ -715,6 +715,7 @@ static inline void devm_acpi_dev_remove_ @@ -712,6 +712,7 @@ static inline void devm_acpi_dev_remove_
#if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS) #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
@ -113,7 +113,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
int gpiod_export(struct gpio_desc *desc, bool direction_may_change); int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
int gpiod_export_link(struct device *dev, const char *name, int gpiod_export_link(struct device *dev, const char *name,
struct gpio_desc *desc); struct gpio_desc *desc);
@@ -722,6 +723,13 @@ void gpiod_unexport(struct gpio_desc *de @@ -719,6 +720,13 @@ void gpiod_unexport(struct gpio_desc *de
#else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */

View File

@ -1,22 +0,0 @@
From d3c5b26768dbe990c4e1bd79e420c11ce7491d51 Mon Sep 17 00:00:00 2001
From: OpenWrt community <openwrt-devel@lists.openwrt.org>
Date: Wed, 13 Jul 2022 11:36:00 +0200
Subject: [PATCH] swab: use stddefs.h instead of compiler.h
Fix an issue with kernel headers that broke perf.
---
include/uapi/linux/swab.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/include/uapi/linux/swab.h
+++ b/include/uapi/linux/swab.h
@@ -3,7 +3,7 @@
#define _UAPI_LINUX_SWAB_H
#include <linux/types.h>
-#include <linux/compiler.h>
+#include <linux/stddef.h>
#include <asm/bitsperlong.h>
#include <asm/swab.h>

View File

@ -8,7 +8,7 @@ Signed-off-by: Giuseppe Lippolis <giu.lippolis@gmail.com>
--- a/drivers/spi/spidev.c --- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c
@@ -696,6 +696,7 @@ static const struct of_device_id spidev_ @@ -707,6 +707,7 @@ static const struct of_device_id spidev_
{ .compatible = "menlo,m53cpld" }, { .compatible = "menlo,m53cpld" },
{ .compatible = "cisco,spi-petra" }, { .compatible = "cisco,spi-petra" },
{ .compatible = "micron,spi-authenta" }, { .compatible = "micron,spi-authenta" },

View File

@ -202,7 +202,7 @@ Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
return !!nor->params->erase_map.uniform_erase_type; return !!nor->params->erase_map.uniform_erase_type;
} }
@@ -2388,6 +2390,7 @@ static int spi_nor_select_erase(struct s @@ -2389,6 +2391,7 @@ static int spi_nor_select_erase(struct s
{ {
struct spi_nor_erase_map *map = &nor->params->erase_map; struct spi_nor_erase_map *map = &nor->params->erase_map;
const struct spi_nor_erase_type *erase = NULL; const struct spi_nor_erase_type *erase = NULL;
@ -210,7 +210,7 @@ Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
struct mtd_info *mtd = &nor->mtd; struct mtd_info *mtd = &nor->mtd;
u32 wanted_size = nor->info->sector_size; u32 wanted_size = nor->info->sector_size;
int i; int i;
@@ -2420,8 +2423,9 @@ static int spi_nor_select_erase(struct s @@ -2421,8 +2424,9 @@ static int spi_nor_select_erase(struct s
*/ */
for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
if (map->erase_type[i].size) { if (map->erase_type[i].size) {
@ -222,7 +222,7 @@ Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
} }
} }
@@ -2429,6 +2433,9 @@ static int spi_nor_select_erase(struct s @@ -2430,6 +2434,9 @@ static int spi_nor_select_erase(struct s
return -EINVAL; return -EINVAL;
mtd->erasesize = erase->size; mtd->erasesize = erase->size;

View File

@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/include/linux/netdevice.h --- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h +++ b/include/linux/netdevice.h
@@ -2089,6 +2089,8 @@ struct net_device { @@ -2096,6 +2096,8 @@ struct net_device {
struct netdev_hw_addr_list mc; struct netdev_hw_addr_list mc;
struct netdev_hw_addr_list dev_addrs; struct netdev_hw_addr_list dev_addrs;

View File

@ -134,7 +134,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
/* /*
* Define if arch has non-standard setup. This is a _PCI_ standard * Define if arch has non-standard setup. This is a _PCI_ standard
@@ -888,6 +891,12 @@ struct ata_port { @@ -894,6 +897,12 @@ struct ata_port {
#ifdef CONFIG_ATA_ACPI #ifdef CONFIG_ATA_ACPI
struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */ struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */
#endif #endif

View File

@ -1,500 +0,0 @@
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_IPQ40XX=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
# CONFIG_ARCH_MDM9615 is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_ARCH_MSM8960 is not set
# CONFIG_ARCH_MSM8974 is not set
# CONFIG_ARCH_MSM8X60 is not set
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_CPUIDLE=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_CRYPTO=y
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_AT803X_PHY=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BCH=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_CMDLINE_PARSER=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_QCOM=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE_PARTITION=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRYPTO_AES_ARM=y
CONFIG_CRYPTO_AES_ARM_BS=y
CONFIG_CRYPTO_BLAKE2S=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEV_QCE=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DEBUG_MISC=y
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_AT24=y
CONFIG_EXTCON=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_74X164=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_GRO_CELLS=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
CONFIG_HIGHPTE=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_OPTEE=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
# CONFIG_I2C_QCOM_CCI is not set
CONFIG_I2C_QUP=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IO_URING=y
# CONFIG_IPQ_APSS_PLL is not set
CONFIG_IPQ_GCC_4019=y
# CONFIG_IPQ_GCC_6018 is not set
# CONFIG_IPQ_GCC_806X is not set
# CONFIG_IPQ_GCC_8074 is not set
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_KPSS_XCC is not set
# CONFIG_KRAITCC is not set
CONFIG_LEDS_LP5523=y
CONFIG_LEDS_LP5562=y
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_TLC591XX=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_IPQ4019=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_MFD_QCOM_RPM is not set
# CONFIG_MFD_SPMI_PMIC is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_REL=y
# CONFIG_MSM_GCC_8660 is not set
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8939 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_GPUCC_8998 is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
# CONFIG_MSM_MMCC_8998 is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_SPLIT_WRGG_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_QCA8K_IPQ4019=y
CONFIG_NET_DSA_TAG_IPQ4019=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
CONFIG_PHY_QCOM_IPQ4019_USB=y
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
# CONFIG_PHY_QCOM_QMP is not set
# CONFIG_PHY_QCOM_QUSB2 is not set
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
CONFIG_PINCTRL_IPQ4019=y
# CONFIG_PINCTRL_IPQ6018 is not set
# CONFIG_PINCTRL_IPQ8064 is not set
# CONFIG_PINCTRL_IPQ8074 is not set
# CONFIG_PINCTRL_MDM9615 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8226 is not set
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
# CONFIG_PINCTRL_MSM8976 is not set
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
# CONFIG_PINCTRL_MSM8998 is not set
# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_QCS404 is not set
# CONFIG_PINCTRL_SC7180 is not set
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SM8150 is not set
# CONFIG_PINCTRL_SM8250 is not set
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_MSM=y
CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_POWER_SUPPLY=y
CONFIG_PPS=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_QCA807X_PHY=y
CONFIG_QCOM_A53PLL=y
CONFIG_QCOM_BAM_DMA=y
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_CPR is not set
# CONFIG_QCOM_EBI2 is not set
# CONFIG_QCOM_GENI_SE is not set
# CONFIG_QCOM_GSBI is not set
# CONFIG_QCOM_HFPLL is not set
# CONFIG_QCOM_IOMMU is not set
CONFIG_QCOM_IPQ4019_ESS_EDMA=y
# CONFIG_QCOM_LLCC is not set
# CONFIG_QCOM_OCMEM is not set
# CONFIG_QCOM_PDC is not set
CONFIG_QCOM_QFPROM=y
# CONFIG_QCOM_RMTFS_MEM is not set
# CONFIG_QCOM_RPMH is not set
CONFIG_QCOM_SCM=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
CONFIG_QCOM_SMEM=y
# CONFIG_QCOM_SMSM is not set
# CONFIG_QCOM_SOCINFO is not set
CONFIG_QCOM_TCSR=y
# CONFIG_QCOM_TSENS is not set
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_Q6SSTOP_404 is not set
# CONFIG_QCS_TURING_404 is not set
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
CONFIG_REGULATOR_VCTRL=y
CONFIG_REGULATOR_VQMMC_IPQ4019=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SC_DISPCC_7180 is not set
# CONFIG_SC_GCC_7180 is not set
# CONFIG_SC_GPUCC_7180 is not set
# CONFIG_SC_LPASS_CORECC_7180 is not set
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SC_VIDEOCC_7180 is not set
# CONFIG_SDM_CAMCC_845 is not set
# CONFIG_SDM_DISPCC_845 is not set
# CONFIG_SDM_GCC_660 is not set
# CONFIG_SDM_GCC_845 is not set
# CONFIG_SDM_GPUCC_845 is not set
# CONFIG_SDM_LPASSCC_845 is not set
# CONFIG_SDM_VIDEOCC_845 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
# CONFIG_SM_GCC_8150 is not set
# CONFIG_SM_GCC_8250 is not set
# CONFIG_SM_GPUCC_8150 is not set
# CONFIG_SM_GPUCC_8250 is not set
# CONFIG_SM_VIDEOCC_8150 is not set
# CONFIG_SM_VIDEOCC_8250 is not set
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_QUP=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
CONFIG_SPMI_MSM_PMIC_ARB=y
# CONFIG_SPMI_PMIC_CLKDIV is not set
CONFIG_SRCU=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_TEE=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

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@ -1,99 +0,0 @@
From b8afc254b40167fd37b4d4263e750dab1f9ef157 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Wed, 9 Sep 2020 18:38:31 +0200
Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes
Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20200909163831.1894142-1-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -606,5 +606,79 @@
reg = <4>;
};
};
+
+ usb3_ss_phy: ssphy@9a000 {
+ compatible = "qcom,usb-ss-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0x9a000 0x800>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
+ reset-names = "por_rst";
+ status = "disabled";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ compatible = "qcom,usb-hs-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0xa6000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ status = "disabled";
+ };
+
+ usb3: usb3@8af8800 {
+ compatible = "qcom,dwc3";
+ reg = <0x8af8800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
+ <&gcc GCC_USB3_SLEEP_CLK>,
+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
+ clock-names = "master", "sleep", "mock_utmi";
+ ranges;
+ status = "disabled";
+
+ dwc3@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xf8000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ };
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ compatible = "qcom,usb-hs-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0xa8000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ status = "disabled";
+ };
+
+ usb2: usb2@60f8800 {
+ compatible = "qcom,dwc3";
+ reg = <0x60f8800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
+ <&gcc GCC_USB2_SLEEP_CLK>,
+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
+ clock-names = "master", "sleep", "mock_utmi";
+ ranges;
+ status = "disabled";
+
+ dwc3@6000000 {
+ compatible = "snps,dwc3";
+ reg = <0x6000000 0xf8000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_hs_phy>;
+ phy-names = "usb2-phy";
+ dr_mode = "host";
+ };
+ };
};
};

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@ -1,44 +0,0 @@
From d1ae4c808e7802008225078d93fbadd4aeea1e2d Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Wed, 9 Sep 2020 21:56:37 +0200
Subject: [PATCH] ARM: dts: qcom: ipq4019: add more labels
Lets add labels to more commonly used nodes for easier modification in board DTS files.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Link: https://lore.kernel.org/r/20200909195640.3127341-2-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -191,7 +191,7 @@
reg = <0x1800000 0x60000>;
};
- rng@22000 {
+ prng: rng@22000 {
compatible = "qcom,prng";
reg = <0x22000 0x140>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
@@ -301,7 +301,7 @@
status = "disabled";
};
- crypto@8e3a000 {
+ crypto: crypto@8e3a000 {
compatible = "qcom,crypto-v5.1";
reg = <0x08e3a000 0x6000>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
@@ -387,7 +387,7 @@
dma-names = "rx", "tx";
};
- watchdog@b017000 {
+ watchdog: watchdog@b017000 {
compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
reg = <0xb017000 0x40>;
clocks = <&sleep_clk>;

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@ -1,35 +0,0 @@
From e14775aa2feac18e7378cb8009b55c13d4236b50 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 7 Sep 2020 12:19:37 +0200
Subject: [PATCH] ARM: dts: qcom: ipq4019: add SDHCI VQMMC LDO node
Since we now have driver for the SDHCI VQMMC LDO needed
for I/0 voltage levels lets introduce the necessary node for it.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Link: https://lore.kernel.org/r/20200907101937.10155-1-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -210,6 +210,16 @@
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
+ vqmmc: regulator@1948000 {
+ compatible = "qcom,vqmmc-ipq4019-regulator";
+ reg = <0x01948000 0x4>;
+ regulator-name = "vqmmc";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ status = "disabled";
+ };
+
sdhci: sdhci@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c>, <0x7824000 0x800>;

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@ -1,115 +0,0 @@
From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@googlemail.com>
Date: Sun, 11 Mar 2018 14:41:31 +0100
Subject: [PATCH 2/2] clk: fix apss cpu overclocking
There's an interaction issue between the clk changes:"
clk: qcom: ipq4019: Add the apss cpu pll divider clock node
clk: qcom: ipq4019: remove fixed clocks and add pll clocks
" and the cpufreq-dt.
cpufreq-dt is now spamming the kernel-log with the following:
[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
for freq 761142857 (-34)
This only happens on certain devices like the Compex WPJ428
and AVM FritzBox!4040. However, other devices like the Asus
RT-AC58U and Meraki MR33 work just fine.
The issue stem from the fact that all higher CPU-Clocks
are achieved by switching the clock-parent to the P_DDRPLLAPSS
(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
as part of the DDR calibration.
For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
at round 533 MHz (ddrpllsdcc = 190285714 Hz).
whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
This patch attempts to fix the issue by modifying
clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
to use a new qcom_find_freq_close() function, which returns the closest
matching frequency, instead of the next higher. This way, the SoC in
the FB4040 (with its max clock speed of 710.4 MHz) will no longer
try to overclock to 761 MHz.
Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
.reg = 0x2f020,
};
+
+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
+ unsigned long rate)
+{
+ const struct freq_tbl *last = NULL;
+
+ for ( ; f->freq; f++) {
+ if (rate == f->freq)
+ return f;
+
+ if (f->freq > rate) {
+ if (!last ||
+ (f->freq - rate) < (rate - last->freq))
+ return f;
+ else
+ return last;
+ }
+ last = f;
+ }
+
+ return last;
+}
+
/*
* Round rate function for APSS CPU PLL Clock divider.
* It looks up the frequency table and returns the next higher frequency
@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
struct clk_hw *p_hw;
const struct freq_tbl *f;
- f = qcom_find_freq(pll->freq_tbl, rate);
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c
u32 mask;
int ret;
- f = qcom_find_freq(pll->freq_tbl, rate);
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
@@ -1305,6 +1328,7 @@ static unsigned long
clk_cpu_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
+ const struct freq_tbl *f;
struct clk_fepll *pll = to_clk_fepll(hw);
u32 cdiv, pre_div;
u64 rate;
@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
do_div(rate, pre_div);
- return rate;
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
+ if (!f)
+ return rate;
+
+ return f->freq;
};
static const struct clk_ops clk_regmap_cpu_div_ops = {

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@ -1,52 +0,0 @@
From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001
From: Ram Chandra Jangir <rjangir@codeaurora.org>
Date: Tue, 28 Mar 2017 22:35:33 +0530
Subject: [PATCH] clk: qcom: ipq4019: add ess reset
Added the ESS reset in IPQ4019 GCC.
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 11 +++++++++++
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++
2 files changed, 22 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i
[GCC_TCSR_BCR] = {0x22000, 0},
[GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0},
+ [ESS_MAC1_ARES] = {0x1200C, 0},
+ [ESS_MAC2_ARES] = {0x1200C, 1},
+ [ESS_MAC3_ARES] = {0x1200C, 2},
+ [ESS_MAC4_ARES] = {0x1200C, 3},
+ [ESS_MAC5_ARES] = {0x1200C, 4},
+ [ESS_PSGMII_ARES] = {0x1200C, 5},
+ [ESS_MAC1_CLK_DIS] = {0x1200C, 8},
+ [ESS_MAC2_CLK_DIS] = {0x1200C, 9},
+ [ESS_MAC3_CLK_DIS] = {0x1200C, 10},
+ [ESS_MAC4_CLK_DIS] = {0x1200C, 11},
+ [ESS_MAC5_CLK_DIS] = {0x1200C, 12},
};
static const struct regmap_config gcc_ipq4019_regmap_config = {
--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -165,5 +165,16 @@
#define GCC_QDSS_BCR 69
#define GCC_MPM_BCR 70
#define GCC_SPDM_BCR 71
+#define ESS_MAC1_ARES 72
+#define ESS_MAC2_ARES 73
+#define ESS_MAC3_ARES 74
+#define ESS_MAC4_ARES 75
+#define ESS_MAC5_ARES 76
+#define ESS_PSGMII_ARES 77
+#define ESS_MAC1_CLK_DIS 78
+#define ESS_MAC2_CLK_DIS 79
+#define ESS_MAC3_CLK_DIS 80
+#define ESS_MAC4_CLK_DIS 81
+#define ESS_MAC5_CLK_DIS 82
#endif

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@ -1,48 +0,0 @@
From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 30 Oct 2020 13:36:31 +0100
Subject: [PATCH] arm: compressed: add appended DTB section
This adds a appended_dtb section to the ARM decompressor
linker script.
This allows using the existing ARM zImage appended DTB support for
appending a DTB to the raw ELF kernel.
Its size is set to 1MB max to match the zImage appended DTB size limit.
To use it to pass the DTB to the kernel, objcopy is used:
objcopy --set-section-flags=.appended_dtb=alloc,contents \
--update-section=.appended_dtb=<target>.dtb vmlinux
This is based off the following patch:
https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/compressed/vmlinux.lds.S
+++ b/arch/arm/boot/compressed/vmlinux.lds.S
@@ -101,6 +101,13 @@ SECTIONS
_edata = .;
+ .appended_dtb : {
+ /* leave space for appended DTB */
+ . += 0x100000;
+ }
+
+ _edata_dtb = .;
+
/*
* The image_end section appears after any additional loadable sections
* that the linker may decide to insert in the binary image. Having
@@ -138,4 +145,4 @@ SECTIONS
ARM_ASSERTS
}
-ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
+ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect");

View File

@ -1,66 +0,0 @@
From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001
From: John Thomson <git@johnthomson.fastmail.com.au>
Date: Fri, 23 Oct 2020 19:42:36 +1000
Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot
For IPQ40XX systems where the SoC watchdog is activated before linux,
the watchdog timer may be too small for linux to finish uncompress,
boot, and watchdog management start.
If the watchdog is enabled, set the timeout for it to 30 seconds.
The functionality and offsets were copied from:
drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start
The watchdog memory address was taken from:
arch/arm/boot/dts/qcom-ipq4019.dtsi
This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's
RouterBoot bootloader.
Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
---
arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -602,6 +602,41 @@ not_relocated: mov r0, #0
bic r4, r4, #1
blne cache_on
+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds
+ * if it is enabled, so that there is time for kernel
+ * to decompress, boot, and take over the watchdog.
+ * data and functionality from drivers/watchdog/qcom-wdt.c
+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi
+ */
+#ifdef CONFIG_ARCH_IPQ40XX
+watchdog_set:
+ /* offsets:
+ * 0x04 reset (=1 resets countdown)
+ * 0x08 enable (=0 disables)
+ * 0x0c status (=1 when SoC was reset by watchdog)
+ * 0x10 bark (=timeout warning in ticks)
+ * 0x14 bite (=timeout reset in ticks)
+ * clock rate is 1<<15 hertz
+ */
+ .equ watchdog, 0x0b017000 @Store watchdog base address
+ movw r0, #:lower16:watchdog
+ movt r0, #:upper16:watchdog
+ ldr r1, [r0, #0x08] @Get enabled?
+ cmp r1, #1 @If not enabled, do not change
+ bne watchdog_finished
+ mov r1, #0
+ str r1, [r0, #0x08] @Disable the watchdog
+ mov r1, #1
+ str r1, [r0, #0x04] @Pet the watchdog
+ mov r1, #30 @30 seconds timeout
+ lsl r1, r1, #15 @converted to ticks
+ str r1, [r0, #0x10] @Set the bark timeout
+ str r1, [r0, #0x14] @Set the bite timeout
+ mov r1, #1
+ str r1, [r0, #0x08] @Enable the watchdog
+watchdog_finished:
+#endif /* CONFIG_ARCH_IPQ40XX */
+
/*
* The C runtime environment should now be setup sufficiently.
* Set up some pointers, and start decompressing.

View File

@ -1,24 +0,0 @@
From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 14 Dec 2020 13:35:35 +0100
Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock
When using sdhci_msm_set_clock clock setting will fail, so lets
use the generic sdhci_set_clock.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/mmc/host/sdhci-msm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -2193,7 +2193,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
static const struct sdhci_ops sdhci_msm_ops = {
.reset = sdhci_msm_reset,
- .set_clock = sdhci_msm_set_clock,
+ .set_clock = sdhci_set_clock,
.get_min_clock = sdhci_msm_get_min_clock,
.get_max_clock = sdhci_msm_get_max_clock,
.set_bus_width = sdhci_set_bus_width,

View File

@ -1,47 +0,0 @@
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -404,6 +404,20 @@ static int __qcom_scm_set_dload_mode(str
return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
}
+static int __qcom_scm_disable_sdi(struct device *dev)
+{
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_CONFIG_SDI,
+ .arginfo = QCOM_SCM_ARGS(2),
+ .args[0] = 1 /* 1: disable watchdog debug */,
+ .args[1] = 0 /* 0: disable SDI */,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+
+ return qcom_scm_call(__scm->dev, &desc, NULL);
+}
+
static void qcom_scm_set_download_mode(bool enable)
{
bool avail;
@@ -1250,6 +1264,13 @@ static int qcom_scm_probe(struct platfor
if (download_mode)
qcom_scm_set_download_mode(true);
+ /*
+ * Factory firmware leaves SDI (a debug interface), which prevents
+ * clean reboot.
+ */
+ if (of_machine_is_compatible("google,wifi"))
+ __qcom_scm_disable_sdi(__scm->dev);
+
return 0;
}
--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
@@ -77,6 +77,7 @@ extern int scm_legacy_call(struct device
#define QCOM_SCM_SVC_BOOT 0x01
#define QCOM_SCM_BOOT_SET_ADDR 0x01
#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
+#define QCOM_SCM_BOOT_CONFIG_SDI 0x09
#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3

View File

@ -1,121 +0,0 @@
--- a/drivers/firmware/qcom_scm-legacy.c
+++ b/drivers/firmware/qcom_scm-legacy.c
@@ -13,6 +13,9 @@
#include <linux/arm-smccc.h>
#include <linux/dma-mapping.h>
+#include <asm/cacheflush.h>
+#include <asm/outercache.h>
+
#include "qcom_scm.h"
static DEFINE_MUTEX(qcom_scm_lock);
@@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct
} while (res->a0 == QCOM_SCM_INTERRUPTED);
}
+static void qcom_scm_inv_range(unsigned long start, unsigned long end)
+{
+ u32 cacheline_size, ctr;
+
+ asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
+ cacheline_size = 4 << ((ctr >> 16) & 0xf);
+
+ start = round_down(start, cacheline_size);
+ end = round_up(end, cacheline_size);
+ outer_inv_range(start, end);
+ while (start < end) {
+ asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
+ : "memory");
+ start += cacheline_size;
+ }
+ dsb();
+ isb();
+}
+
/**
* qcom_scm_call() - Sends a command to the SCM and waits for the command to
* finish processing.
@@ -160,10 +182,16 @@ int scm_legacy_call(struct device *dev,
rsp = scm_legacy_command_to_response(cmd);
- cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
- if (dma_mapping_error(dev, cmd_phys)) {
- kfree(cmd);
- return -ENOMEM;
+ if (dev) {
+ cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
+ if (dma_mapping_error(dev, cmd_phys)) {
+ kfree(cmd);
+ return -ENOMEM;
+ }
+ } else {
+ cmd_phys = virt_to_phys(cmd);
+ __cpuc_flush_dcache_area(cmd, alloc_len);
+ outer_flush_range(cmd_phys, cmd_phys + alloc_len);
}
smc.args[0] = 1;
@@ -179,13 +207,26 @@ int scm_legacy_call(struct device *dev,
goto out;
do {
- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
- sizeof(*rsp), DMA_FROM_DEVICE);
+ if (dev) {
+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) +
+ cmd_len, sizeof(*rsp),
+ DMA_FROM_DEVICE);
+ } else {
+ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) +
+ cmd_len;
+ qcom_scm_inv_range(start, start + sizeof(*rsp));
+ }
} while (!rsp->is_complete);
- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
- le32_to_cpu(rsp->buf_offset),
- resp_len, DMA_FROM_DEVICE);
+ if (dev) {
+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
+ le32_to_cpu(rsp->buf_offset),
+ resp_len, DMA_FROM_DEVICE);
+ } else {
+ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len +
+ le32_to_cpu(rsp->buf_offset);
+ qcom_scm_inv_range(start, start + resp_len);
+ }
if (res) {
res_buf = scm_legacy_get_response_buffer(rsp);
@@ -193,7 +234,8 @@ int scm_legacy_call(struct device *dev,
res->result[i] = le32_to_cpu(res_buf[i]);
}
out:
- dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
+ if (dev)
+ dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
kfree(cmd);
return ret;
}
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -344,6 +344,17 @@ int qcom_scm_set_cold_boot_addr(void *en
desc.args[0] = flags;
desc.args[1] = virt_to_phys(entry);
+ /*
+ * Factory firmware doesn't support the atomic variant. Non-atomic SCMs
+ * require ugly DMA invalidation support that was dropped upstream a
+ * while ago. For more info, see:
+ *
+ * [RFC] qcom_scm: IPQ4019 firmware does not support atomic API?
+ * https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/
+ */
+ if (of_machine_is_compatible("google,wifi"))
+ return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL);
+
return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);

View File

@ -1,29 +0,0 @@
From 35ca7e3e6ccd120d694a3425f37fc6374ad2e11e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20B=C3=B6hler?= <dev@aboehler.at>
Date: Wed, 20 Apr 2022 12:08:38 +0200
Subject: [PATCH] mtd: rawnand: add support for Toshiba TC58NVG0S3HTA00
NAND flash
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The Toshiba TC58NVG0S3HTA00 is detected with 64 byte OOB while the flash
has 128 bytes OOB. This adds a static NAND ID entry to correct this.
Tested on FRITZ!Box 7530 flashed with OpenWrt.
Signed-off-by: Andreas Böhler <dev@aboehler.at>
(changed id_len to 8, added comment about possible counterfeits)
---
--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
@@ -29,6 +29,9 @@ struct nand_flash_dev nand_flash_ids[] =
{"TC58NVG0S3E 1G 3.3V 8-bit",
{ .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
+ {"TC58NVG0S3HTA00 1G 3.3V 8-bit", /* possibly counterfeit chip - see commit */
+ { .id = {0x98, 0xf1, 0x80, 0x15} }, /* should be more bytes */
+ SZ_2K, SZ_128, SZ_128K, 0, 8, 128, NAND_ECC_INFO(8, SZ_512), },
{"TC58NVG2S0F 4G 3.3V 8-bit",
{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },

View File

@ -1,43 +0,0 @@
From da75807ac41175e9db8c95f7a172b4133763b744 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <j4g8y7@gmail.com>
Date: Mon, 11 Jan 2021 17:49:36 +0100
Subject: [PATCH] skbuff: add DSA specific data to struct skb_shared_info
All of the already existing DSA tagging protocol drivers
are storing the tagging data directly into the skb. In most
cases that is the only way to send the required information
to the underlying ethernet switch.
However on certain platforms (like the Qualcomm IPQ40xx
SoCs) the built-in ethernet switch is connected directly
to an ethernet MAC, and the tagging information must be
sent out-of-band which is done directly via the hardware
TX descriptors of the ethernet MAC.
In such cases, putting the information into the skb causes
unneccesary overhead, because the ethernet driver must
remove that before sending the ethernet frame towards to
the hardware.
This change adds two new DSA specific fields to struct
skb_shared_info which makes it possible to send the
tagging information via skb->shinfo. With this approach,
the twofold modifications of the skb data can be avoided.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
---
include/linux/skbuff.h | 3 +++
1 file changed, 3 insertions(+)
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -522,6 +522,9 @@ struct skb_shared_info {
unsigned int gso_type;
u32 tskey;
+ unsigned int dsa_tag_proto;
+ unsigned char dsa_tag_data[8];
+
/*
* Warning : all fields before dataref are cleared in __alloc_skb()
*/

View File

@ -1,188 +0,0 @@
From 29a0c2fae991cab142575c92276c0afdeb260ebe Mon Sep 17 00:00:00 2001
From: Gabor Juhos <j4g8y7@gmail.com>
Date: Thu, 28 Oct 2021 21:44:52 +0200
Subject: [PATCH] net: dsa: tag_ipq4019: add shinfo based tagging driver for
IPQ40xx
This change adds a tagging protocol driver for the built-in
ethernet switch of the Qualcomm Atheros IPQ4019 SoCs.
In comparison to the existing tagging protocols this hardware
requires a slightly different approach because the switch does
not use in-band tags.
On the receive path, the source port information is embedded
into the RX descriptors of the ethernet MAC hardware. Similarly,
the destination port mask must be sent via the TX descriptors
of the ethernet MAC when a packet is sent towards the switch.
In order to support this special requirements, this patch
adds a new tagging protocol driver.
The driver extracts the source port information directly
from the 'receive return descriptor' of the ethernet MAC.
It is possible because that descriptor is part of the skb
received from the ethernet driver.
Unfortunatley, it is not possible to put the destination
port information directly to the TX descriptors, because
those are handled internally by the driver of the ethernet
hardware.
To overcome this limitation, this tagging driver uses the
DSA specific fields in skb->shinfo to send the destination
port information to the ethernet driver.
A similar tagging driver is exist but that uses skb
extensions which causes unnecessary overhead.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
---
include/linux/dsa/ipq4019.h | 11 ++++++
include/net/dsa.h | 2 +
net/dsa/Kconfig | 6 +++
net/dsa/Makefile | 1 +
net/dsa/tag_ipq4019.c | 79 +++++++++++++++++++++++++++++++++++++
5 files changed, 99 insertions(+)
create mode 100644 include/linux/dsa/ipq4019.h
create mode 100644 net/dsa/tag_ipq4019.c
--- /dev/null
+++ b/include/linux/dsa/ipq4019.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DSA_IPQ40XX_H
+#define DSA_IPQ40XX_H
+
+struct ipq40xx_dsa_tag_data {
+ u8 from_cpu;
+ u8 dp;
+};
+
+#endif /* DSA_IPQ40XX_H */
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -46,6 +46,7 @@ struct phylink_link_state;
#define DSA_TAG_PROTO_AR9331_VALUE 16
#define DSA_TAG_PROTO_RTL4_A_VALUE 17
#define DSA_TAG_PROTO_BRCM_LEGACY_VALUE 22
+#define DSA_TAG_PROTO_IPQ4019_VALUE 24
enum dsa_tag_protocol {
DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
@@ -67,6 +68,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_OCELOT = DSA_TAG_PROTO_OCELOT_VALUE,
DSA_TAG_PROTO_AR9331 = DSA_TAG_PROTO_AR9331_VALUE,
DSA_TAG_PROTO_RTL4_A = DSA_TAG_PROTO_RTL4_A_VALUE,
+ DSA_TAG_PROTO_IPQ4019 = DSA_TAG_PROTO_IPQ4019_VALUE,
};
struct packet_type;
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -63,6 +63,12 @@ config NET_DSA_TAG_BRCM_PREPEND
Broadcom switches which places the tag before the Ethernet header
(prepended).
+config NET_DSA_TAG_IPQ4019
+ tristate "Tag driver for Qualcomm Atheros IPQ4019 SoC built-in switch"
+ help
+ Say Y or M if you want to enable support for tagging frames for
+ the built-in switch of the Qualcomm Atheros IPQ4019 SoC-s.
+
config NET_DSA_TAG_GSWIP
tristate "Tag driver for Lantiq / Intel GSWIP switches"
help
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_NET_DSA_TAG_BRCM_COMMON) +=
obj-$(CONFIG_NET_DSA_TAG_DSA) += tag_dsa.o
obj-$(CONFIG_NET_DSA_TAG_EDSA) += tag_edsa.o
obj-$(CONFIG_NET_DSA_TAG_GSWIP) += tag_gswip.o
+obj-$(CONFIG_NET_DSA_TAG_IPQ4019) += tag_ipq4019.o
obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o
obj-$(CONFIG_NET_DSA_TAG_RTL4_A) += tag_rtl4_a.o
obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o
--- /dev/null
+++ b/net/dsa/tag_ipq4019.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* Copyright (c) 2021, Gabor Juhos <j4g8y7@gmail.com> */
+
+#include <linux/bitfield.h>
+#include <linux/dsa/ipq4019.h>
+
+#include "dsa_priv.h"
+
+/* Receive Return Descriptor */
+struct edma_rrd {
+ u16 rrd0;
+ u16 rrd1;
+ u16 rrd2;
+ u16 rrd3;
+ u16 rrd4;
+ u16 rrd5;
+ u16 rrd6;
+ u16 rrd7;
+} __packed;
+
+#define EDMA_RRD_SIZE sizeof(struct edma_rrd)
+
+#define EDMA_RRD1_PORT_ID_MASK GENMASK(14, 12)
+
+static struct sk_buff *ipq4019_sh_tag_xmit(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct dsa_port *dp = dsa_slave_to_port(dev);
+ struct ipq40xx_dsa_tag_data *tag_data;
+
+ BUILD_BUG_ON(sizeof_field(struct skb_shared_info, dsa_tag_data) <
+ sizeof(struct ipq40xx_dsa_tag_data));
+
+ skb_shinfo(skb)->dsa_tag_proto = DSA_TAG_PROTO_IPQ4019;
+ tag_data = (struct ipq40xx_dsa_tag_data *)skb_shinfo(skb)->dsa_tag_data;
+
+ tag_data->from_cpu = 1;
+ /* set the destination port information */
+ tag_data->dp = BIT(dp->index);
+
+ return skb;
+}
+
+static struct sk_buff *ipq4019_sh_tag_rcv(struct sk_buff *skb,
+ struct net_device *dev,
+ struct packet_type *pt)
+{
+ struct edma_rrd *rrd;
+ int offset;
+ int port;
+
+ offset = EDMA_RRD_SIZE + ETH_HLEN;
+ if (unlikely(skb_headroom(skb) < offset))
+ return NULL;
+
+ rrd = (struct edma_rrd *)(skb->data - offset);
+ port = FIELD_GET(EDMA_RRD1_PORT_ID_MASK, rrd->rrd1);
+
+ skb->dev = dsa_master_find_slave(dev, 0, port);
+ if (!skb->dev)
+ return NULL;
+
+ return skb;
+}
+
+const struct dsa_device_ops ipq4019_sh_tag_dsa_ops = {
+ .name = "ipq4019-sh",
+ .proto = DSA_TAG_PROTO_IPQ4019,
+ .xmit = ipq4019_sh_tag_xmit,
+ .rcv = ipq4019_sh_tag_rcv,
+};
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DSA tag driver for the IPQ4019 SoC built-in ethernet switch");
+MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>");
+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_IPQ4019);
+
+module_dsa_tag_driver(ipq4019_sh_tag_dsa_ops);

View File

@ -1,43 +0,0 @@
From 4f488235f498db43f2412116dea6e02c7fb20216 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 1 Nov 2021 12:36:51 +0100
Subject: [PATCH] net: ethernet: qualcomm: add IPQESS support
Allow compiling the IPQESS driver that supports the
Qualcomm IPQ40xx SoC built-in ethernet controller.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/net/ethernet/qualcomm/Kconfig | 11 +++++++++++
drivers/net/ethernet/qualcomm/Makefile | 1 +
2 files changed, 12 insertions(+)
--- a/drivers/net/ethernet/qualcomm/Kconfig
+++ b/drivers/net/ethernet/qualcomm/Kconfig
@@ -60,6 +60,17 @@ config QCOM_EMAC
low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
Precision Clock Synchronization Protocol.
+config QCOM_IPQ4019_ESS_EDMA
+ tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
+ depends on OF
+ select PHYLINK
+ help
+ This driver supports the Qualcomm Atheros IPQ40xx built-in
+ ESS EDMA ethernet controller.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ipqess.
+
source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
endif # NET_VENDOR_QUALCOMM
--- a/drivers/net/ethernet/qualcomm/Makefile
+++ b/drivers/net/ethernet/qualcomm/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
qcauart-objs := qca_uart.o
obj-y += emac/
+obj-y += ipqess/
obj-$(CONFIG_RMNET) += rmnet/

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@ -1,81 +0,0 @@
From 44327d7098d4f32c24ec8c528e5aff6e030956bc Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Wed, 20 Oct 2021 13:21:45 +0200
Subject: [PATCH] arm: dts: ipq4019: add ethernet controller DT node
Since IPQ40xx SoC built-in ethernet controller now has a driver,
add its DT node so it can be used.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -38,6 +38,7 @@
spi1 = &blsp1_spi2;
i2c0 = &blsp1_i2c3;
i2c1 = &blsp1_i2c4;
+ ethernet0 = &gmac;
};
cpus {
@@ -589,6 +590,57 @@
status = "disabled";
};
+ gmac: ethernet@c080000 {
+ compatible = "qcom,ipq4019-ess-edma";
+ reg = <0xc080000 0x8000>;
+ resets = <&gcc ESS_RESET>;
+ reset-names = "ess_rst";
+ clocks = <&gcc GCC_ESS_CLK>;
+ clock-names = "ess_clk";
+ interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
+
+ status = "disabled";
+
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ asym-pause;
+ };
+ };
+
mdio: mdio@90000 {
#address-cells = <1>;
#size-cells = <0>;

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@ -1,61 +0,0 @@
From 3e1825e00dafb68eec25df389b63f3ab3d905b59 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <j4g8y7@gmail.com>
Date: Fri, 25 Dec 2020 08:02:47 +0100
Subject: [PATCH] net: phy: define PSGMII PHY interface mode
The PSGMII interface is similar to QSGMII. The main difference
is that the PSGMII interface combines five SGMII lines into a
single link while in QSGMII only four lines are combined.
Similarly to the QSGMII, this interface mode might also needs
special handling within the MAC driver.
Add definitions for the PHY layer to allow to express this type
of connection between the MAC and PHY.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
---
Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 +
drivers/net/phy/phylink.c | 1 +
include/linux/phy.h | 3 +++
3 files changed, 5 insertions(+)
--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -64,6 +64,7 @@ properties:
- mii
- gmii
- sgmii
+ - psgmii
- qsgmii
- tbi
- rev-mii
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -289,6 +289,7 @@ static int phylink_parse_mode(struct phy
switch (pl->link_config.interface) {
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_PSGMII:
case PHY_INTERFACE_MODE_QSGMII:
phylink_set(pl->supported, 10baseT_Half);
phylink_set(pl->supported, 10baseT_Full);
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -134,6 +134,7 @@ typedef enum {
PHY_INTERFACE_MODE_XGMII,
PHY_INTERFACE_MODE_XLGMII,
PHY_INTERFACE_MODE_MOCA,
+ PHY_INTERFACE_MODE_PSGMII,
PHY_INTERFACE_MODE_QSGMII,
PHY_INTERFACE_MODE_TRGMII,
PHY_INTERFACE_MODE_100BASEX,
@@ -201,6 +202,8 @@ static inline const char *phy_modes(phy_
return "xlgmii";
case PHY_INTERFACE_MODE_MOCA:
return "moca";
+ case PHY_INTERFACE_MODE_PSGMII:
+ return "psgmii";
case PHY_INTERFACE_MODE_QSGMII:
return "qsgmii";
case PHY_INTERFACE_MODE_TRGMII:

View File

@ -1,53 +0,0 @@
From b5f71652b85a85ea53162e9e2b760b84fd0d254f Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 1 Nov 2021 18:10:28 +0100
Subject: [PATCH] net: dsa: add Qualcomm IPQ4019 built-in switch support
Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
It shares most of the stuff with its external counterpart, however it is
modified for the SoC.
Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
instead of 7.
It also has no built-in PHY-s but rather requires external PSGMII based
companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
out calibration before using them.
PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
unfortunately requires some magic values as the datasheet doesnt document
the bits that are being set or the register at all.
Since its built-in it is MMIO like other peripherals and doesn't have its
own MDIO bus but depends on the SoC provided one.
CPU connection is at Port 0 and it uses some kind of a internal connection
and no traditional RGMII/SGMII.
It also doesn't use in-band tagging like other qca8k switches so a shinfo
based tagger is used.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/net/dsa/qca/Kconfig | 9 +++++++++
drivers/net/dsa/qca/Makefile | 1 +
2 files changed, 10 insertions(+)
--- a/drivers/net/dsa/qca/Kconfig
+++ b/drivers/net/dsa/qca/Kconfig
@@ -7,3 +7,12 @@ config NET_DSA_AR9331
help
This enables support for the Qualcomm Atheros AR9331 built-in Ethernet
switch.
+
+config NET_DSA_QCA8K_IPQ4019
+ tristate "Qualcomm Atheros IPQ4019 built-in Ethernet switch support"
+ depends on HAS_IOMEM && NET_DSA
+ select NET_DSA_TAG_IPQ4019
+ select REGMAP
+ help
+ This enables support for the Qualcomm Atheros IPQ4019 SoC built-in
+ Ethernet switch.
--- a/drivers/net/dsa/qca/Makefile
+++ b/drivers/net/dsa/qca/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_NET_DSA_AR9331) += ar9331.o
+obj-$(CONFIG_NET_DSA_QCA8K_IPQ4019) += qca8k-ipq4019.o

View File

@ -1,98 +0,0 @@
From ebb62523990a27b3a25e422fa575619f7f725a20 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 1 Nov 2021 18:15:04 +0100
Subject: [PATCH] arm: dts: ipq4019: add switch node
Since the built-in IPQ40xx switch now has a driver, add the required node
for it to work.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 78 +++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -590,6 +590,82 @@
status = "disabled";
};
+ switch: switch@c000000 {
+ compatible = "qca,ipq4019-qca8337n";
+ reg = <0xc000000 0x80000>, <0x98000 0x800>;
+ reg-names = "base", "psgmii_phy";
+ resets = <&gcc ESS_PSGMII_ARES>;
+ reset-names = "psgmii_rst";
+ mdio = <&mdio>;
+ psgmii-ethphy = <&psgmiiphy>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 { /* MAC0 */
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&gmac>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ asym-pause;
+ };
+ };
+
+ swport1: port@1 { /* MAC1 */
+ reg = <1>;
+ label = "lan1";
+ phy-handle = <&ethphy0>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport2: port@2 { /* MAC2 */
+ reg = <2>;
+ label = "lan2";
+ phy-handle = <&ethphy1>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport3: port@3 { /* MAC3 */
+ reg = <3>;
+ label = "lan3";
+ phy-handle = <&ethphy2>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport4: port@4 { /* MAC4 */
+ reg = <4>;
+ label = "lan4";
+ phy-handle = <&ethphy3>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport5: port@5 { /* MAC5 */
+ reg = <5>;
+ label = "wan";
+ phy-handle = <&ethphy4>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+ };
+ };
+
gmac: ethernet@c080000 {
compatible = "qcom,ipq4019-ess-edma";
reg = <0xc080000 0x8000>;

View File

@ -1,61 +0,0 @@
From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Thu, 1 Oct 2020 15:05:35 +0200
Subject: [PATCH] dt-bindings: net: add QCA807x PHY
Add DT bindings for Qualcomm QCA807x PHY series.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 include/dt-bindings/net/qcom-qca807x.h
--- /dev/null
+++ b/include/dt-bindings/net/qcom-qca807x.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Device Tree constants for the Qualcomm QCA807X PHYs
+ */
+
+#ifndef _DT_BINDINGS_QCOM_QCA807X_H
+#define _DT_BINDINGS_QCOM_QCA807X_H
+
+#define PSGMII_QSGMII_TX_DRIVER_140MV 0
+#define PSGMII_QSGMII_TX_DRIVER_160MV 1
+#define PSGMII_QSGMII_TX_DRIVER_180MV 2
+#define PSGMII_QSGMII_TX_DRIVER_200MV 3
+#define PSGMII_QSGMII_TX_DRIVER_220MV 4
+#define PSGMII_QSGMII_TX_DRIVER_240MV 5
+#define PSGMII_QSGMII_TX_DRIVER_260MV 6
+#define PSGMII_QSGMII_TX_DRIVER_280MV 7
+#define PSGMII_QSGMII_TX_DRIVER_300MV 8
+#define PSGMII_QSGMII_TX_DRIVER_320MV 9
+#define PSGMII_QSGMII_TX_DRIVER_400MV 10
+#define PSGMII_QSGMII_TX_DRIVER_500MV 11
+/* Default value */
+#define PSGMII_QSGMII_TX_DRIVER_600MV 12
+
+/* Full amplitude, full bias current */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0
+/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1
+/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2
+/* Both amplitude and bias current follow DSP */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3
+/* Full amplitude, half bias current */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4
+/* Amplitude follow DSP setting; 1/4 bias current when cable<10m,
+ * otherwise half bias current
+ */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5
+/* Full amplitude; same bias current setting with “010” and “011”,
+ * but half more bias is reduced when cable <10m
+ */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6
+/* Amplitude follow DSP; same bias current setting with “110”, default value */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7
+
+#endif

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@ -1,50 +0,0 @@
From f825cdc8bfde7616a14e2163f16303a8973031d2 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Wed, 7 Oct 2020 17:38:48 +0200
Subject: [PATCH] net: phy: Add Qualcom QCA807x driver
This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s.
They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber.
Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber.
Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s.
But some vendors used these to driver generic LED-s controlled by userspace,
so lets enable registering each PHY as GPIO controller and add driver for it.
These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/net/phy/Kconfig | 6 ++++++
drivers/net/phy/Makefile | 1 +
2 files changed, 7 insertions(+)
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -320,6 +320,12 @@ config AT803X_PHY
Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
QCA8337(Internal qca8k PHY) model
+config QCA807X_PHY
+ tristate "Qualcomm QCA807X PHYs"
+ depends on OF_MDIO
+ help
+ Currently supports the QCA8072 and QCA8075 models.
+
config QSEMI_PHY
tristate "Quality Semiconductor PHYs"
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -88,6 +88,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc/
obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
+obj-$(CONFIG_QCA807X_PHY) += qca807x.o
obj-$(CONFIG_REALTEK_PHY) += realtek.o
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o

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@ -1,61 +0,0 @@
From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Fri, 2 Oct 2020 10:43:26 +0200
Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/net/qcom-qca807x.h>
/ {
#address-cells = <1>;
@@ -726,22 +727,38 @@
ethphy0: ethernet-phy@0 {
reg = <0>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy3: ethernet-phy@3 {
reg = <3>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy4: ethernet-phy@4 {
reg = <4>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ psgmiiphy: psgmii-phy@5 {
+ reg = <5>;
+
+ qcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>;
};
};

View File

@ -1,180 +0,0 @@
From: Christian Lamparter <chunkeey@googlemail.com>
Subject: SoC: add qualcomm syscon
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
obj-$(CONFIG_QCOM_SMSM) += smsm.o
obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
obj-$(CONFIG_QCOM_APR) += apr.o
obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -190,6 +190,13 @@ config QCOM_SOCINFO
Say yes here to support the Qualcomm socinfo driver, providing
information about the SoC to user space.
+config QCOM_TCSR
+ tristate "QCOM Top Control and Status Registers"
+ depends on ARCH_QCOM
+ help
+ Say y here to enable TCSR support. The TCSR provides control
+ functions for various peripherals.
+
config QCOM_WCNSS_CTRL
tristate "Qualcomm WCNSS control driver"
depends on ARCH_QCOM || COMPILE_TEST
--- /dev/null
+++ b/drivers/soc/qcom/qcom_tcsr.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License rev 2 and
+ * only rev 2 as published by the free Software foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#define TCSR_USB_PORT_SEL 0xb0
+#define TCSR_USB_HSPHY_CONFIG 0xC
+
+#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0
+#define TCSR_ESS_INTERFACE_SEL_MASK 0xf
+
+#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0
+#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4
+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4
+
+static int tcsr_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ const struct device_node *node = pdev->dev.of_node;
+ void __iomem *base;
+ u32 val;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
+ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
+ writel(val, base + TCSR_USB_PORT_SEL);
+ }
+
+ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
+ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
+ writel(val, base + TCSR_USB_HSPHY_CONFIG);
+ }
+
+ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
+ u32 tmp = 0;
+ dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
+ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
+ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
+ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
+ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
+ }
+
+ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
+ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
+ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
+ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
+ }
+
+ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
+ dev_info(&pdev->dev,
+ "setting wifi_noc_memtype_m0_m2 = %x\n", val);
+ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id tcsr_dt_match[] = {
+ { .compatible = "qcom,tcsr", },
+ { },
+};
+
+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
+
+static struct platform_driver tcsr_driver = {
+ .driver = {
+ .name = "tcsr",
+ .owner = THIS_MODULE,
+ .of_match_table = tcsr_dt_match,
+ },
+ .probe = tcsr_probe,
+};
+
+module_platform_driver(tcsr_driver);
+
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
+MODULE_DESCRIPTION("QCOM TCSR driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+++ b/include/dt-bindings/soc/qcom,tcsr.h
@@ -0,0 +1,48 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_QCOM_TCSR_H
+#define __DT_BINDINGS_QCOM_TCSR_H
+
+#define TCSR_USB_SELECT_USB3_P0 0x1
+#define TCSR_USB_SELECT_USB3_P1 0x2
+#define TCSR_USB_SELECT_USB3_DUAL 0x3
+
+/* IPQ40xx HS PHY Mode Select */
+#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7
+#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7
+
+/* IPQ40xx ess interface mode select */
+#define TCSR_ESS_PSGMII 0
+#define TCSR_ESS_PSGMII_RGMII5 1
+#define TCSR_ESS_PSGMII_RMII0 2
+#define TCSR_ESS_PSGMII_RMII1 4
+#define TCSR_ESS_PSGMII_RMII0_RMII1 6
+#define TCSR_ESS_PSGMII_RGMII4 9
+
+/*
+ * IPQ40xx WiFi Global Config
+ * Bit 30:AXID_EN
+ * Enable AXI master bus Axid translating to confirm all txn submitted by order
+ * Bit 24: Use locally generated socslv_wxi_bvalid
+ * 1: use locally generate socslv_wxi_bvalid for performance.
+ * 0: use SNOC socslv_wxi_bvalid.
+ */
+#define TCSR_WIFI_GLB_CFG 0x41000000
+
+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222
+
+/* TCSR A/B REG */
+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
+
+#endif

View File

@ -1,176 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -15,6 +15,7 @@
*/
#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
@@ -29,6 +30,32 @@
};
soc {
+ tcsr@194b000 {
+ /* select hostmode */
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "okay";
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
rng@22000 {
status = "ok";
};
@@ -74,14 +101,6 @@
pinctrl-names = "default";
status = "ok";
cs-gpios = <&tlmm 54 0>;
-
- mx25l25635e@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "mx25l25635e";
- spi-max-frequency = <24000000>;
- };
};
serial@78af000 {
@@ -109,5 +128,41 @@
wifi@a800000 {
status = "ok";
};
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+
+ usb3_ss_phy: ssphy@9a000 {
+ status = "okay";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ status = "okay";
+ };
+
+ usb3: usb3@8af8800 {
+ status = "okay";
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ status = "okay";
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+ };
};
};
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -18,5 +18,73 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1";
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&blsp1_spi1 {
+ mx25l25635f@0 {
+ compatible = "mx25l25635f", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ SBL1@0 {
+ label = "SBL1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+ MIBIB@40000 {
+ label = "MIBIB";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+ QSEE@60000 {
+ label = "QSEE";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+ CDT@c0000 {
+ label = "CDT";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+ DDRPARAMS@d0000 {
+ label = "DDRPARAMS";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+ APPSBLENV@e0000 {
+ label = "APPSBLENV";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+ APPSBL@f0000 {
+ label = "APPSBL";
+ reg = <0xf0000 0x80000>;
+ read-only;
+ };
+ ART@170000 {
+ label = "ART";
+ reg = <0x170000 0x10000>;
+ read-only;
+ };
+ kernel@180000 {
+ label = "kernel";
+ reg = <0x180000 0x400000>;
+ };
+ rootfs@580000 {
+ label = "rootfs";
+ reg = <0x580000 0x1600000>;
+ };
+ firmware@180000 {
+ label = "firmware";
+ reg = <0x180000 0x1a00000>;
+ };
+ };
};

View File

@ -1,167 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -17,53 +17,79 @@
stdout-path = "serial0:115200n8";
};
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256MB */
- };
-
soc {
+ rng@22000 {
+ status = "okay";
+ };
+
pinctrl@1000000 {
serial_0_pins: serial0-pinmux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
};
serial_1_pins: serial1-pinmux {
- pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
};
spi_0_pins: spi-0-pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
- bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
+ };
+ pinconf {
+ pins = "gpio13", "gpio14", "gpio15";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pinconf_cs {
+ pins = "gpio12";
+ drive-strength = <2>;
bias-disable;
output-high;
};
};
i2c_0_pins: i2c-0-pinmux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
+ pinmux {
+ function = "blsp_i2c0";
+ pins = "gpio10", "gpio11";
+ };
+ pinconf {
+ pins = "gpio10", "gpio11";
+ drive-strength = <16>;
+ bias-disable;
+ };
};
nand_pins: nand-pins {
- pins = "gpio53", "gpio55", "gpio56",
- "gpio57", "gpio58", "gpio59",
- "gpio60", "gpio62", "gpio63",
- "gpio64", "gpio65", "gpio66",
- "gpio67", "gpio68", "gpio69";
- function = "qpic";
+ pullups {
+ pins = "gpio52", "gpio53", "gpio58",
+ "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
};
};
@@ -89,11 +115,11 @@
status = "ok";
cs-gpios = <&tlmm 12 0>;
- m25p80@0 {
+ mx25l25635e@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
- compatible = "n25q128a11";
+ compatible = "mx25l25635e";
spi-max-frequency = <24000000>;
};
};
@@ -103,9 +129,48 @@
perst-gpio = <&tlmm 38 0x1>;
};
+ i2c0: i2c@78b7000 { /* BLSP1 QUP2 */
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ };
+
qpic-nand@79b0000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
+
+ usb3_ss_phy: ssphy@9a000 {
+ status = "okay";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ status = "okay";
+ };
+
+ usb3: usb3@8af8800 {
+ status = "okay";
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ status = "okay";
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+ };
+
+ cryptobam: dma@8e04000 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
};
};

View File

@ -1,28 +0,0 @@
From 2acc3260050cf17d72ec5fb7a00cd91cf53ef5b6 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Fri, 23 Sep 2022 18:42:29 +0200
Subject: [PATCH 1/4] clk: qcom: clk-krait: fix wrong div2 functions
Currently div2 value is applied to the wrong bits. This is caused by a
bug in the code where the shift is done only for lpl, for anything
else the mask is not shifted to the correct bits.
Fix this by correctly shift if lpl is not supported.
Fixes: 4d7dc77babfe ("clk: qcom: Add support for Krait clocks")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/qcom/clk-krait.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -114,6 +114,8 @@ static int krait_div2_set_rate(struct cl
if (d->lpl)
mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
+ else
+ mask <<= d->shift;
spin_lock_irqsave(&krait_clock_reg_lock, flags);
val = krait_get_l2_indirect_reg(d->offset);

View File

@ -39,7 +39,7 @@
/* check we are the Master VPE */ /* check we are the Master VPE */
local_irq_save(flags); local_irq_save(flags);
@@ -417,6 +418,8 @@ int __init vpe_module_init(void) @@ -416,6 +417,8 @@ int __init vpe_module_init(void)
} }
v->ntcs = hw_tcs - aprp_cpu_index(); v->ntcs = hw_tcs - aprp_cpu_index();

View File

@ -26,7 +26,7 @@ Signed-off-by: Marek Behún <kabel@kernel.org>
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -390,7 +390,8 @@ @@ -396,7 +396,8 @@
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>; reg = <1>;

View File

@ -20,7 +20,7 @@ Signed-off-by: Marek Behún <kabel@kernel.org>
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -188,15 +188,13 @@ @@ -194,15 +194,13 @@
reg = <0x2b>; reg = <0x2b>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -38,7 +38,7 @@ Signed-off-by: Marek Behún <kabel@kernel.org>
* - there are 3 LEDs connected via MCU to PCIe * - there are 3 LEDs connected via MCU to PCIe
* ports. One of these ports supports mSATA. * ports. One of these ports supports mSATA.
* There is no mSATA nor PCIe function. * There is no mSATA nor PCIe function.
@@ -207,7 +205,6 @@ @@ -213,7 +211,6 @@
* B. Again there is no such function defined. * B. Again there is no such function defined.
* For now we use LED_FUNCTION_INDICATOR * For now we use LED_FUNCTION_INDICATOR
*/ */

View File

@ -26,7 +26,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
--- a/drivers/mfd/Kconfig --- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig
@@ -2187,6 +2187,15 @@ config SGI_MFD_IOC3 @@ -2188,6 +2188,15 @@ config SGI_MFD_IOC3
If you have an SGI Origin, Octane, or a PCI IOC3 card, If you have an SGI Origin, Octane, or a PCI IOC3 card,
then say Y. Otherwise say N. then say Y. Otherwise say N.

View File

@ -11,6 +11,7 @@ FEATURES:=targz pcie gpio rtc usb fpu
SUBTARGETS:=generic SUBTARGETS:=generic
KERNEL_PATCHVER:=5.10 KERNEL_PATCHVER:=5.10
KERNEL_TESTING_PATCHVER:=5.15
define Target/Description define Target/Description
Build images for Octeon-TX CN80XX/CN81XX based boards Build images for Octeon-TX CN80XX/CN81XX based boards

View File

@ -0,0 +1,421 @@
CONFIG_64BIT=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_HIBERNATION_HEADER=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_THUNDER=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_CNP=y
CONFIG_ARM64_CRYPTO=y
CONFIG_ARM64_EPAN=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PAN=y
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_ARM64_SVE=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_VA_BITS=48
# CONFIG_ARM64_VA_BITS_39 is not set
CONFIG_ARM64_VA_BITS_48=y
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_ARM_MHU_V2 is not set
CONFIG_ARM_PSCI_FW=y
CONFIG_ARM_SBSA_WATCHDOG=y
CONFIG_ATA=y
# CONFIG_ATA_SFF is not set
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23144=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMA=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_SIZE_MBYTES=16
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_CS2000_CP=y
# CONFIG_COMPAT_32BIT_TIME is not set
CONFIG_CONFIGFS_FS=y
CONFIG_CONTIG_ALLOC=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CRASH_CORE=y
CONFIG_CRASH_DUMP=y
CONFIG_CRC16=y
CONFIG_CRC7=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC_T10DIF=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SIMD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DMADEVICES=y
CONFIG_DMA_CMA=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_PERNUMA_CMA=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
CONFIG_EDAC=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_DMC520 is not set
CONFIG_EDAC_LEGACY_SYSFS=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC_THUNDERX=y
# CONFIG_EDAC_XGENE is not set
CONFIG_EEPROM_AT24=y
CONFIG_FAT_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_FREEZER=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_CACHE=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_NUMA=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GLOB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_THUNDERX=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HIBERNATE_CALLBACKS=y
CONFIG_HIBERNATION=y
CONFIG_HIBERNATION_SNAPSHOT_DEV=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_HWSPINLOCK=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_CAVIUM=y
CONFIG_HW_RANDOM_OPTEE=y
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
CONFIG_I2C_SMBUS=y
CONFIG_I2C_THUNDERX=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
# CONFIG_ISDN is not set
CONFIG_JUMP_LABEL=y
CONFIG_KEXEC=y
CONFIG_KEXEC_CORE=y
CONFIG_KSM=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAILBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_MDIO_BUS=y
CONFIG_MDIO_CAVIUM=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_THUNDER=y
CONFIG_MEMFD_CREATE=y
CONFIG_MEMORY_BALLOON=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_MEMTEST=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CAVIUM_THUNDERX=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MSDOS_FS=y
# CONFIG_MTD is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_SELFTESTS=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NODES_SHIFT=2
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=64
CONFIG_NUMA=y
CONFIG_NUMA_BALANCING=y
CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NUMA=y
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
CONFIG_PADATA=y
CONFIG_PAGE_REPORTING=y
CONFIG_PARAVIRT=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_PME=y
CONFIG_PCI_ATS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCI_HOST_THUNDER_ECAM=y
CONFIG_PCI_HOST_THUNDER_PEM=y
CONFIG_PCI_IOV=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_PHYLIB=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
CONFIG_PM_STD_PARTITION=""
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_SUPPLY=y
CONFIG_PROC_VMCORE=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
# CONFIG_RAVE_SP_CORE is not set
CONFIG_REBOOT_MODE=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1672=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_SATA_HOST=y
CONFIG_SCHED_INFO=y
CONFIG_SCHED_MC=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_PROC_FS is not set
CONFIG_SCSI_SAS_ATA=y
CONFIG_SCSI_SAS_ATTRS=y
CONFIG_SCSI_SAS_HOST_SMP=y
CONFIG_SCSI_SAS_LIBSAS=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_XILINX_PS_UART=y
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_THUNDERX=y
CONFIG_SRAM=y
CONFIG_SRCU=y
CONFIG_SWIOTLB=y
CONFIG_SWPHY=y
CONFIG_SYNC_FILE=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_TASK_XACCT=y
CONFIG_TEE=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_THUNDER_NIC_BGX=y
CONFIG_THUNDER_NIC_PF=y
CONFIG_THUNDER_NIC_RGX=y
CONFIG_THUNDER_NIC_VF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
CONFIG_TRANS_TABLE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_PCI=y
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USE_PERCPU_NUMA_NODE_ID=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_BALLOON=y
# CONFIG_VIRTIO_BLK is not set
CONFIG_VIRTIO_MMIO=y
# CONFIG_VIRTIO_NET is not set
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_PCI_LIB=y
CONFIG_VMAP_STACK=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XARRAY_MULTI=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_ZONE_DMA32=y

View File

@ -0,0 +1,59 @@
From d0ff7a1bcfe886cab1a237895b08ac51ecfe10e7 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 10 Apr 2019 08:00:47 -0700
Subject: [PATCH 04/12] PCI: add quirk for Gateworks PLX PEX860x switch with
GPIO PERST#
Gateworks boards use PLX PEX860x switches where downstream ports
have their PERST# driven from the PEX GPIO.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
drivers/pci/quirks.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
#include <linux/ktime.h>
#include <linux/mm.h>
#include <linux/nvme.h>
+#include <linux/of.h>
#include <linux/platform_data/x86/apple.h>
#include <linux/pm_runtime.h>
#include <linux/suspend.h>
@@ -5831,3 +5832,34 @@ static void nvidia_ion_ahci_fixup(struct
pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
+
+#ifdef CONFIG_PCI_HOST_THUNDER_PEM
+/*
+ * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
+ * as they are used for slots1-7 PERST#
+ */
+static void newport_pciesw_early_fixup(struct pci_dev *dev)
+{
+ u32 dw;
+
+ if (!of_machine_is_compatible("gw,newport"))
+ return;
+
+ if (dev->devfn != 0)
+ return;
+
+ dev_info(&dev->dev, "de-asserting PERST#\n");
+ pci_read_config_dword(dev, 0x62c, &dw);
+ dw |= 0xaaa8; /* GPIO1-7 outputs */
+ pci_write_config_dword(dev, 0x62c, dw);
+
+ pci_read_config_dword(dev, 0x644, &dw);
+ dw |= 0xfe; /* GPIO1-7 output high */
+ pci_write_config_dword(dev, 0x644, dw);
+
+ msleep(100);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, newport_pciesw_early_fixup);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, newport_pciesw_early_fixup);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, newport_pciesw_early_fixup);
+#endif /* CONFIG_PCI_HOST_THUNDER_PEM */

View File

@ -2039,7 +2039,7 @@ static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,
/* if link is occupied, -ENODEV too is an error */ /* if link is occupied, -ENODEV too is an error */
if (rc && (rc != -ENODEV || sata_scr_valid(link))) { if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); ata_link_err(link, "SRST failed (errno=%d)\n", rc);
return rc; return rc;
} }

View File

@ -36,7 +36,7 @@
--- a/include/linux/libata.h --- a/include/linux/libata.h
+++ b/include/linux/libata.h +++ b/include/linux/libata.h
@@ -917,6 +917,8 @@ struct ata_port_operations { @@ -923,6 +923,8 @@ struct ata_port_operations {
enum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *qc); enum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *qc);
unsigned int (*qc_issue)(struct ata_queued_cmd *qc); unsigned int (*qc_issue)(struct ata_queued_cmd *qc);
bool (*qc_fill_rtf)(struct ata_queued_cmd *qc); bool (*qc_fill_rtf)(struct ata_queued_cmd *qc);
@ -45,7 +45,7 @@
/* /*
* Configuration and exception handling * Configuration and exception handling
@@ -1007,6 +1009,9 @@ struct ata_port_operations { @@ -1013,6 +1015,9 @@ struct ata_port_operations {
void (*phy_reset)(struct ata_port *ap); void (*phy_reset)(struct ata_port *ap);
void (*eng_timeout)(struct ata_port *ap); void (*eng_timeout)(struct ata_port *ap);

View File

@ -211,7 +211,7 @@ Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- -
--- a/drivers/staging/mt7621-pci/pci-mt7621.c --- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ /dev/null +++ /dev/null
@@ -1,600 +0,0 @@ @@ -1,601 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ -// SPDX-License-Identifier: GPL-2.0+
-/* -/*
- * BRIEF MODULE DESCRIPTION - * BRIEF MODULE DESCRIPTION
@ -307,8 +307,8 @@ Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- * reset lines are inverted. - * reset lines are inverted.
- */ - */
-struct mt7621_pcie { -struct mt7621_pcie {
- void __iomem *base;
- struct device *dev; - struct device *dev;
- void __iomem *base;
- struct list_head ports; - struct list_head ports;
- bool resets_inverted; - bool resets_inverted;
-}; -};
@ -343,7 +343,7 @@ Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- writel_relaxed(val, port->base + reg); - writel_relaxed(val, port->base + reg);
-} -}
- -
-static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot, -static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int slot,
- unsigned int func, unsigned int where) - unsigned int func, unsigned int where)
-{ -{
- return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) | - return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
@ -354,7 +354,7 @@ Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- unsigned int devfn, int where) - unsigned int devfn, int where)
-{ -{
- struct mt7621_pcie *pcie = bus->sysdata; - struct mt7621_pcie *pcie = bus->sysdata;
- u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), - u32 address = mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn),
- PCI_FUNC(devfn), where); - PCI_FUNC(devfn), where);
- -
- writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR); - writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
@ -362,7 +362,7 @@ Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); - return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
-} -}
- -
-struct pci_ops mt7621_pci_ops = { -struct pci_ops mt7621_pcie_ops = {
- .map_bus = mt7621_pcie_map_bus, - .map_bus = mt7621_pcie_map_bus,
- .read = pci_generic_config_read, - .read = pci_generic_config_read,
- .write = pci_generic_config_write, - .write = pci_generic_config_write,
@ -370,7 +370,7 @@ Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- -
-static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) -static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
-{ -{
- u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); - u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
- -
- pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); - pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); - return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
@ -379,7 +379,7 @@ Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-static void write_config(struct mt7621_pcie *pcie, unsigned int dev, -static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
- u32 reg, u32 val) - u32 reg, u32 val)
-{ -{
- u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); - u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
- -
- pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); - pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); - pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
@ -719,16 +719,17 @@ Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-{ -{
- struct mt7621_pcie *pcie = pci_host_bridge_priv(host); - struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
- -
- host->ops = &mt7621_pci_ops; - host->ops = &mt7621_pcie_ops;
- host->sysdata = pcie; - host->sysdata = pcie;
- return pci_host_probe(host); - return pci_host_probe(host);
-} -}
- -
-static const struct soc_device_attribute mt7621_pci_quirks_match[] = { -static const struct soc_device_attribute mt7621_pcie_quirks_match[] = {
- { .soc_id = "mt7621", .revision = "E2" } - { .soc_id = "mt7621", .revision = "E2" },
- { /* sentinel */ }
-}; -};
- -
-static int mt7621_pci_probe(struct platform_device *pdev) -static int mt7621_pcie_probe(struct platform_device *pdev)
-{ -{
- struct device *dev = &pdev->dev; - struct device *dev = &pdev->dev;
- const struct soc_device_attribute *attr; - const struct soc_device_attribute *attr;
@ -749,7 +750,7 @@ Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- platform_set_drvdata(pdev, pcie); - platform_set_drvdata(pdev, pcie);
- INIT_LIST_HEAD(&pcie->ports); - INIT_LIST_HEAD(&pcie->ports);
- -
- attr = soc_device_match(mt7621_pci_quirks_match); - attr = soc_device_match(mt7621_pcie_quirks_match);
- if (attr) - if (attr)
- pcie->resets_inverted = true; - pcie->resets_inverted = true;
- -
@ -786,7 +787,7 @@ Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- return err; - return err;
-} -}
- -
-static int mt7621_pci_remove(struct platform_device *pdev) -static int mt7621_pcie_remove(struct platform_device *pdev)
-{ -{
- struct mt7621_pcie *pcie = platform_get_drvdata(pdev); - struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
- struct mt7621_pcie_port *port; - struct mt7621_pcie_port *port;
@ -797,21 +798,21 @@ Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- return 0; - return 0;
-} -}
- -
-static const struct of_device_id mt7621_pci_ids[] = { -static const struct of_device_id mt7621_pcie_ids[] = {
- { .compatible = "mediatek,mt7621-pci" }, - { .compatible = "mediatek,mt7621-pci" },
- {}, - {},
-}; -};
-MODULE_DEVICE_TABLE(of, mt7621_pci_ids); -MODULE_DEVICE_TABLE(of, mt7621_pcie_ids);
- -
-static struct platform_driver mt7621_pci_driver = { -static struct platform_driver mt7621_pcie_driver = {
- .probe = mt7621_pci_probe, - .probe = mt7621_pcie_probe,
- .remove = mt7621_pci_remove, - .remove = mt7621_pcie_remove,
- .driver = { - .driver = {
- .name = "mt7621-pci", - .name = "mt7621-pci",
- .of_match_table = of_match_ptr(mt7621_pci_ids), - .of_match_table = of_match_ptr(mt7621_pcie_ids),
- }, - },
-}; -};
-builtin_platform_driver(mt7621_pci_driver); -builtin_platform_driver(mt7621_pcie_driver);
--- /dev/null --- /dev/null
+++ b/drivers/pci/controller/pcie-mt7621.c +++ b/drivers/pci/controller/pcie-mt7621.c
@@ -0,0 +1,600 @@ @@ -0,0 +1,600 @@

View File

@ -28,9 +28,9 @@ Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> # arch/mips
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
@@ -24,6 +26,35 @@ @@ -25,6 +27,35 @@
static u32 detect_magic __initdata; static u32 detect_magic __initdata;
static struct ralink_soc_info *soc_info_ptr;
+int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
+{ +{

View File

@ -0,0 +1,38 @@
From 19098934f910b4d47cb30251dd39ffa57bef9523 Mon Sep 17 00:00:00 2001
From: John Thomson <git@johnthomson.fastmail.com.au>
Date: Tue, 6 Dec 2022 06:46:45 +1000
Subject: [PATCH] PCI: mt7621: Add sentinel to quirks table
Current driver is missing a sentinel in the struct soc_device_attribute
array, which causes an oops when assessed by the
soc_device_match(mt7621_pcie_quirks_match) call.
This was only exposed once the CONFIG_SOC_MT7621 mt7621 soc_dev_attr
was fixed to register the SOC as a device, in:
commit 7c18b64bba3b ("mips: ralink: mt7621: do not use kzalloc too early")
Fix it by adding the required sentinel.
Link: https://lore.kernel.org/lkml/26ebbed1-0fe9-4af9-8466-65f841d0b382@app.fastmail.com
Link: https://lore.kernel.org/r/20221205204645.301301-1-git@johnthomson.fastmail.com.au
Fixes: b483b4e4d3f6 ("staging: mt7621-pci: add quirks for 'E2' revision using 'soc_device_attribute'")
Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
drivers/pci/controller/pcie-mt7621.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/drivers/pci/controller/pcie-mt7621.c
+++ b/drivers/pci/controller/pcie-mt7621.c
@@ -471,7 +471,8 @@ static int mt7621_pcie_register_host(str
}
static const struct soc_device_attribute mt7621_pcie_quirks_match[] = {
- { .soc_id = "mt7621", .revision = "E2" }
+ { .soc_id = "mt7621", .revision = "E2" },
+ { /* sentinel */ }
};
static int mt7621_pcie_probe(struct platform_device *pdev)

View File

@ -90,12 +90,12 @@ define Device/Default
KERNEL := \ KERNEL := \
kernel-bin | \ kernel-bin | \
append-dtb | \ append-dtb | \
gzip | \ libdeflate-gzip | \
uImage gzip uImage gzip
KERNEL_INITRAMFS := \ KERNEL_INITRAMFS := \
kernel-bin | \ kernel-bin | \
append-dtb | \ append-dtb | \
gzip | \ libdeflate-gzip | \
uImage gzip uImage gzip
DEVICE_DTS_DIR := ../dts-$(KERNEL_PATCHVER) DEVICE_DTS_DIR := ../dts-$(KERNEL_PATCHVER)
DEVICE_DTS = $$(SOC)_$(1) DEVICE_DTS = $$(SOC)_$(1)

View File

@ -7,7 +7,7 @@ define Device/d-link_dgs-1210
KERNEL := \ KERNEL := \
kernel-bin | \ kernel-bin | \
append-dtb | \ append-dtb | \
gzip | \ libdeflate-gzip | \
uImage gzip | \ uImage gzip | \
dlink-cameo dlink-cameo
CAMEO_KERNEL_PART := 2 CAMEO_KERNEL_PART := 2
@ -60,7 +60,7 @@ define Device/zyxel_gs1900
KERNEL_INITRAMFS := \ KERNEL_INITRAMFS := \
kernel-bin | \ kernel-bin | \
append-dtb | \ append-dtb | \
gzip | \ libdeflate-gzip | \
zyxel-vers | \ zyxel-vers | \
uImage gzip uImage gzip
endef endef

View File

@ -70,7 +70,7 @@ define Device/engenius_ews2910p
KERNEL_INITRAMFS := \ KERNEL_INITRAMFS := \
kernel-bin | \ kernel-bin | \
append-dtb | \ append-dtb | \
gzip | \ libdeflate-gzip | \
uImage gzip -n 'IMG-0.00.00-c0.0.00' uImage gzip -n 'IMG-0.00.00-c0.0.00'
endef endef
TARGET_DEVICES += engenius_ews2910p TARGET_DEVICES += engenius_ews2910p

View File

@ -19,6 +19,7 @@ define Target/Description
endef endef
KERNEL_PATCHVER:=5.10 KERNEL_PATCHVER:=5.10
KERNEL_TESTING_PATCHVER:=5.15
include $(INCLUDE_DIR)/target.mk include $(INCLUDE_DIR)/target.mk

View File

@ -0,0 +1,551 @@
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_ALTERA_FREEZE_BRIDGE is not set
# CONFIG_ALTERA_PR_IP_CORE is not set
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=1024
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y
# CONFIG_ARCH_VEXPRESS_SPC is not set
CONFIG_ARCH_ZYNQ=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_ARM_ERRATA_643719=y
CONFIG_ARM_ERRATA_720789=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_ARM_ERRATA_754327=y
CONFIG_ARM_ERRATA_764369=y
CONFIG_ARM_ERRATA_775420=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GLOBAL_TIMER=y
CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_PL172_MPMC is not set
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_TIMER_SP804=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_ARM_ZYNQ_CPUIDLE=y
CONFIG_ATAGS=y
CONFIG_AUTO_ZRELADDR=y
# CONFIG_AXI_DMAC is not set
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BOUNCE=y
CONFIG_CACHE_L2X0=y
CONFIG_CADENCE_TTC_TIMER=y
CONFIG_CADENCE_WATCHDOG=y
CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLKSRC_VERSATILE=y
CONFIG_CLK_SP810=y
CONFIG_CLK_VEXPRESS_OSC=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMA=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_SIZE_MBYTES=16
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_SI570=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONNECTOR=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_CONTIG_ALLOC=y
CONFIG_COREDUMP=y
# CONFIG_CPUFREQ_DT is not set
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_RNG2=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DMADEVICES=y
CONFIG_DMA_CMA=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DRM=y
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_PANEL=y
CONFIG_DRM_PANEL_BRIDGE=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DTC=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_E1000E=y
CONFIG_EDAC=y
CONFIG_EDAC_ATOMIC_SCRUB=y
# CONFIG_EDAC_DEBUG is not set
CONFIG_EDAC_LEGACY_SYSFS=y
CONFIG_EDAC_SUPPORT=y
# CONFIG_EDAC_SYNOPSYS is not set
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
CONFIG_ELF_CORE=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_F2FS_FS=y
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_XILINX is not set
CONFIG_FHANDLE=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FPGA=y
CONFIG_FPGA_BRIDGE=y
# CONFIG_FPGA_DFL is not set
# CONFIG_FPGA_MGR_ALTERA_CVP is not set
# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set
# CONFIG_FPGA_MGR_ICE40_SPI is not set
# CONFIG_FPGA_MGR_MACHXO2_SPI is not set
# CONFIG_FPGA_MGR_XILINX_SPI is not set
CONFIG_FPGA_MGR_ZYNQ_FPGA=y
CONFIG_FPGA_REGION=y
CONFIG_FREEZER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_CACHE=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GLOB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_ZYNQ=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAVE_SMP=y
CONFIG_HDMI=y
CONFIG_HID=y
CONFIG_HID_GENERIC=y
CONFIG_HID_MICROSOFT=y
CONFIG_HIGHMEM=y
CONFIG_HIGHPTE=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HWMON=y
CONFIG_HW_CONSOLE=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CADENCE=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_ICST=y
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_KEYBOARD=y
CONFIG_INPUT_MOUSE=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_SPARSEKMAP=y
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_RARP=y
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_ISDN is not set
CONFIG_JBD2=y
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_KCMP=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_XZ is not set
CONFIG_KEYBOARD_ATKBD=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_GPIO_POLLED=y
CONFIG_KMAP_LOCAL=y
CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_MACB=y
# CONFIG_MACB_PCI is not set
CONFIG_MACB_USE_HWSTAMP=y
CONFIG_MARVELL_PHY=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
# CONFIG_MDIO_GPIO is not set
CONFIG_MEMFD_CREATE=y
CONFIG_MEMORY=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_MFD_CORE=y
CONFIG_MFD_SYSCON=y
CONFIG_MFD_VEXPRESS_SYSREG=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_MODULE_STRIPPED is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_CYAPA is not set
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_CYPRESS=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_MTD_SPLIT_FIRMWARE=y
# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NET_SELFTESTS=y
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
CONFIG_NLS=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NO_IOPORT_MAP=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
# CONFIG_OF_FPGA_REGION is not set
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_PCI=y
CONFIG_PCIE_XILINX=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PINCTRL_ZYNQ=y
CONFIG_PL310_ERRATA_588369=y
CONFIG_PL310_ERRATA_727915=y
CONFIG_PL310_ERRATA_753970=y
CONFIG_PL310_ERRATA_769419=y
CONFIG_PL330_DMA=y
# CONFIG_PL353_SMC is not set
CONFIG_PLAT_VERSATILE=y
CONFIG_PM=y
CONFIG_PMBUS=y
CONFIG_PM_CLK=y
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_VEXPRESS=y
CONFIG_POWER_SUPPLY=y
CONFIG_PPS=y
CONFIG_PROC_EVENTS=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_R8169=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REALTEK_PHY=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VEXPRESS is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_ZYNQ=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SCHED_CORE is not set
CONFIG_SCHED_MC=y
CONFIG_SCHED_SMT=y
CONFIG_SENSORS_PMBUS=y
CONFIG_SENSORS_UCD9000=y
CONFIG_SENSORS_UCD9200=y
# CONFIG_SERIAL_8250 is not set
CONFIG_SERIAL_XILINX_PS_UART=y
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
CONFIG_SERIO=y
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_SERPORT=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_BUS=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_CADENCE=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_XILINX=y
CONFIG_SPI_ZYNQ_QSPI=y
CONFIG_SRAM=y
CONFIG_SRAM_EXEC=y
CONFIG_SRCU=y
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYNC_FILE=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
# CONFIG_TEXTSEARCH is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UIO=y
# CONFIG_UIO_AEC is not set
# CONFIG_UIO_CIF is not set
# CONFIG_UIO_DMEM_GENIRQ is not set
# CONFIG_UIO_MF624 is not set
# CONFIG_UIO_NETX is not set
# CONFIG_UIO_PCI_GENERIC is not set
CONFIG_UIO_PDRV_GENIRQ=y
# CONFIG_UIO_PRUSS is not set
# CONFIG_UIO_SERCOS3 is not set
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_COMMON=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_XILINX=y
CONFIG_USB_HID=y
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_OTG=y
CONFIG_USB_OTG_FSM=y
CONFIG_USB_PHY=y
CONFIG_USB_ROLE_SWITCH=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USE_OF=y
CONFIG_VEXPRESS_CONFIG=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_VITESSE_PHY=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_WATCHDOG_CORE=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_XILINX_EMACLITE=y
# CONFIG_XILINX_INTC is not set
# CONFIG_XILINX_PR_DECOUPLER is not set
CONFIG_XILINX_WATCHDOG=y
CONFIG_XILINX_XADC=y
CONFIG_XPS=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_X86=y
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

View File

@ -36,6 +36,7 @@ tools-y += findutils
tools-y += firmware-utils tools-y += firmware-utils
tools-y += flex tools-y += flex
tools-y += gengetopt tools-y += gengetopt
tools-y += libdeflate
tools-y += libressl tools-y += libressl
tools-y += libtool tools-y += libtool
tools-y += lzma tools-y += lzma
@ -90,6 +91,7 @@ $(curdir)/gengetopt/compile := $(curdir)/libtool/compile
$(curdir)/gmp/compile := $(curdir)/libtool/compile $(curdir)/gmp/compile := $(curdir)/libtool/compile
$(curdir)/gptfdisk/compile += $(curdir)/e2fsprogs/compile $(curdir)/popt/compile $(curdir)/gptfdisk/compile += $(curdir)/e2fsprogs/compile $(curdir)/popt/compile
$(curdir)/isl/compile := $(curdir)/gmp/compile $(curdir)/isl/compile := $(curdir)/gmp/compile
$(curdir)/libdeflate/compile := $(curdir)/cmake/compile
$(curdir)/libressl/compile := $(curdir)/pkgconf/compile $(curdir)/libressl/compile := $(curdir)/pkgconf/compile
$(curdir)/libtool/compile := $(curdir)/automake/compile $(curdir)/missing-macros/compile $(curdir)/libtool/compile := $(curdir)/automake/compile $(curdir)/missing-macros/compile
$(curdir)/lzma-old/compile := $(curdir)/zlib/compile $(curdir)/lzma-old/compile := $(curdir)/zlib/compile

31
tools/libdeflate/Makefile Normal file
View File

@ -0,0 +1,31 @@
#
# Copyright (C) 2022 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
include $(TOPDIR)/rules.mk
PKG_NAME:=libdeflate
PKG_VERSION:=1.15
PKG_RELEASE:=1
PKG_SOURCE_URL:=https://github.com/ebiggers/libdeflate.git
PKG_SOURCE_PROTO:=git
PKG_SOURCE_VERSION:=v$(PKG_VERSION)
PKG_MIRROR_HASH:=122feff4543541b547dc89e832adf262c81911ae1acbccdc591f0353a85b600a
include $(INCLUDE_DIR)/host-build.mk
include $(INCLUDE_DIR)/cmake.mk
define Host/Install
$(INSTALL_BIN) $(HOST_BUILD_DIR)/programs/libdeflate-gzip $(STAGING_DIR_HOST)/bin/
$(LN) libdeflate-gzip $(STAGING_DIR_HOST)/bin/libdeflate-gunzip
endef
define Host/Clean
rm -f $(STAGING_DIR_HOST)/bin/libdeflate-gzip
rm -f $(STAGING_DIR_HOST)/bin/libdeflate-gunzip
endef
$(eval $(call HostBuild))