diff --git a/package/boot/uboot-rockchip/patches/010-arm-dts-rockchip-rk356x-sync-with-Linux-6.0.patch b/package/boot/uboot-rockchip/patches/010-arm-dts-rockchip-rk356x-sync-with-Linux-6.0.patch new file mode 100644 index 0000000000..4b36ea1a52 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/010-arm-dts-rockchip-rk356x-sync-with-Linux-6.0.patch @@ -0,0 +1,2839 @@ +From 85a8ef1264fca77827f7702594272d17c7c39ce1 Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Tue, 4 Oct 2022 01:30:30 +0000 +Subject: [PATCH] arm: dts: rockchip: rk356x: sync with Linux 6.0 + +prepare for rk3566 based board + +Signed-off-by: FUKAUMI Naoki +Reviewed-by: Kever Yang +--- + arch/arm/dts/rk3566.dtsi | 35 + + arch/arm/dts/rk3568-evb-u-boot.dtsi | 2 +- + arch/arm/dts/rk3568-pinctrl.dtsi | 9 + + arch/arm/dts/rk3568.dtsi | 848 +------- + ...{rk3568-u-boot.dtsi => rk356x-u-boot.dtsi} | 7 +- + arch/arm/dts/rk356x.dtsi | 1706 +++++++++++++++++ + include/dt-bindings/power/rk3568-power.h | 32 + + 7 files changed, 1891 insertions(+), 748 deletions(-) + create mode 100644 arch/arm/dts/rk3566.dtsi + rename arch/arm/dts/{rk3568-u-boot.dtsi => rk356x-u-boot.dtsi} (94%) + create mode 100644 arch/arm/dts/rk356x.dtsi + create mode 100644 include/dt-bindings/power/rk3568-power.h + +--- /dev/null ++++ b/arch/arm/dts/rk3566.dtsi +@@ -0,0 +1,35 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk356x.dtsi" ++ ++/ { ++ compatible = "rockchip,rk3566"; ++}; ++ ++&pipegrf { ++ compatible = "rockchip,rk3566-pipe-grf", "syscon"; ++}; ++ ++&power { ++ power-domain@RK3568_PD_PIPE { ++ reg = ; ++ clocks = <&cru PCLK_PIPE>; ++ pm_qos = <&qos_pcie2x1>, ++ <&qos_sata1>, ++ <&qos_sata2>, ++ <&qos_usb3_0>, ++ <&qos_usb3_1>; ++ #power-domain-cells = <0>; ++ }; ++}; ++ ++&usb_host0_xhci { ++ phys = <&usb2phy0_otg>; ++ phy-names = "usb2-phy"; ++ extcon = <&usb2phy0>; ++ maximum-speed = "high-speed"; ++}; ++ ++&vop { ++ compatible = "rockchip,rk3566-vop"; ++}; +--- a/arch/arm/dts/rk3568-evb-u-boot.dtsi ++++ b/arch/arm/dts/rk3568-evb-u-boot.dtsi +@@ -3,7 +3,7 @@ + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +-#include "rk3568-u-boot.dtsi" ++#include "rk356x-u-boot.dtsi" + + / { + chosen { +--- a/arch/arm/dts/rk3568-pinctrl.dtsi ++++ b/arch/arm/dts/rk3568-pinctrl.dtsi +@@ -3108,4 +3108,13 @@ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; + }; + }; ++ ++ tsadc { ++ /omit-if-no-ref/ ++ tsadc_pin: tsadc-pin { ++ rockchip,pins = ++ /* tsadc_pin */ ++ <0 RK_PA1 0 &pcfg_pull_none>; ++ }; ++ }; + }; +--- a/arch/arm/dts/rk3568.dtsi ++++ b/arch/arm/dts/rk3568.dtsi +@@ -3,777 +3,141 @@ + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +-#include +-#include +-#include +-#include +-#include +-#include +-#include ++#include "rk356x.dtsi" + + / { + compatible = "rockchip,rk3568"; + +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- gpio3 = &gpio3; +- gpio4 = &gpio4; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; +- serial6 = &uart6; +- serial7 = &uart7; +- serial8 = &uart8; +- serial9 = &uart9; +- }; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x0>; +- clocks = <&scmi_clk 0>; +- enable-method = "psci"; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu1: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x100>; +- enable-method = "psci"; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu2: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x200>; +- enable-method = "psci"; +- operating-points-v2 = <&cpu0_opp_table>; +- }; +- +- cpu3: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0 0x300>; +- enable-method = "psci"; +- operating-points-v2 = <&cpu0_opp_table>; +- }; ++ sata0: sata@fc000000 { ++ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; ++ reg = <0 0xfc000000 0 0x1000>; ++ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, ++ <&cru CLK_SATA0_RXOOB>; ++ clock-names = "sata", "pmalive", "rxoob"; ++ interrupts = ; ++ phys = <&combphy0 PHY_TYPE_SATA>; ++ phy-names = "sata-phy"; ++ ports-implemented = <0x1>; ++ power-domains = <&power RK3568_PD_PIPE>; ++ status = "disabled"; + }; + +- cpu0_opp_table: cpu0-opp-table { +- compatible = "operating-points-v2"; +- opp-shared; +- +- opp-408000000 { +- opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <900000 900000 1150000>; +- clock-latency-ns = <40000>; +- }; +- +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <900000 900000 1150000>; +- }; +- +- opp-816000000 { +- opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <900000 900000 1150000>; +- opp-suspend; +- }; +- +- opp-1104000000 { +- opp-hz = /bits/ 64 <1104000000>; +- opp-microvolt = <900000 900000 1150000>; +- }; +- +- opp-1416000000 { +- opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <900000 900000 1150000>; +- }; +- +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <975000 975000 1150000>; +- }; ++ pipe_phy_grf0: syscon@fdc70000 { ++ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; ++ reg = <0x0 0xfdc70000 0x0 0x1000>; ++ }; ++ ++ qos_pcie3x1: qos@fe190080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190080 0x0 0x20>; ++ }; ++ ++ qos_pcie3x2: qos@fe190100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190100 0x0 0x20>; ++ }; ++ ++ qos_sata0: qos@fe190200 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190200 0x0 0x20>; ++ }; ++ ++ gmac0: ethernet@fe2a0000 { ++ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; ++ reg = <0x0 0xfe2a0000 0x0 0x10000>; ++ interrupts = , ++ ; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, ++ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, ++ <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, ++ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; ++ clock-names = "stmmaceth", "mac_clk_rx", ++ "mac_clk_tx", "clk_mac_refout", ++ "aclk_mac", "pclk_mac", ++ "clk_mac_speed", "ptp_ref"; ++ resets = <&cru SRST_A_GMAC0>; ++ reset-names = "stmmaceth"; ++ rockchip,grf = <&grf>; ++ snps,axi-config = <&gmac0_stmmac_axi_setup>; ++ snps,mixed-burst; ++ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; ++ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; ++ snps,tso; ++ status = "disabled"; + +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1050000 1050000 1150000>; ++ mdio0: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; + }; + +- opp-1992000000 { +- opp-hz = /bits/ 64 <1992000000>; +- opp-microvolt = <1150000 1150000 1150000>; ++ gmac0_stmmac_axi_setup: stmmac-axi-config { ++ snps,blen = <0 0 0 0 16 8 4>; ++ snps,rd_osr_lmt = <8>; ++ snps,wr_osr_lmt = <4>; + }; +- }; + +- firmware { +- scmi: scmi { +- compatible = "arm,scmi-smc"; +- arm,smc-id = <0x82000010>; +- shmem = <&scmi_shmem>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- scmi_clk: protocol@14 { +- reg = <0x14>; +- #clock-cells = <1>; +- }; ++ gmac0_mtl_rx_setup: rx-queues-config { ++ snps,rx-queues-to-use = <1>; ++ queue0 {}; + }; + +- }; +- +- pmu { +- compatible = "arm,cortex-a55-pmu"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- arm,no-tick-in-suspend; +- }; +- +- xin24m: xin24m { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xin24m"; +- #clock-cells = <0>; +- }; +- +- xin32k: xin32k { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- pinctrl-0 = <&clk32k_out0>; +- pinctrl-names = "default"; +- #clock-cells = <0>; +- }; +- +- sram@10f000 { +- compatible = "mmio-sram"; +- reg = <0x0 0x0010f000 0x0 0x100>; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x0010f000 0x100>; +- +- scmi_shmem: sram@0 { +- compatible = "arm,scmi-shmem"; +- reg = <0x0 0x100>; ++ gmac0_mtl_tx_setup: tx-queues-config { ++ snps,tx-queues-to-use = <1>; ++ queue0 {}; + }; + }; + +- gic: interrupt-controller@fd400000 { +- compatible = "arm,gic-v3"; +- reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ +- <0x0 0xfd460000 0 0x80000>; /* GICR */ +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- mbi-alias = <0x0 0xfd100000>; +- mbi-ranges = <296 24>; +- msi-controller; +- }; +- +- pmugrf: syscon@fdc20000 { +- compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; +- reg = <0x0 0xfdc20000 0x0 0x10000>; +- }; +- +- grf: syscon@fdc60000 { +- compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xfdc60000 0x0 0x10000>; +- }; +- +- pmucru: clock-controller@fdd00000 { +- compatible = "rockchip,rk3568-pmucru"; +- reg = <0x0 0xfdd00000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- cru: clock-controller@fdd20000 { +- compatible = "rockchip,rk3568-cru"; +- reg = <0x0 0xfdd20000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- i2c0: i2c@fdd40000 { +- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfdd40000 0x0 0x1000>; +- interrupts = ; +- clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart0: serial@fdd50000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfdd50000 0x0 0x100>; +- interrupts = ; +- clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 0>, <&dmac0 1>; +- pinctrl-0 = <&uart0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- pwm0: pwm@fdd70000 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfdd70000 0x0 0x10>; +- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm0m0_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm1: pwm@fdd70010 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfdd70010 0x0 0x10>; +- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm1m0_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm2: pwm@fdd70020 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfdd70020 0x0 0x10>; +- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm2m0_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm3: pwm@fdd70030 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfdd70030 0x0 0x10>; +- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm3_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- sdmmc2: mmc@fe000000 { +- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xfe000000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, +- <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- resets = <&cru SRST_SDMMC2>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- sdmmc0: mmc@fe2b0000 { +- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xfe2b0000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, +- <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- resets = <&cru SRST_SDMMC0>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- sdmmc1: mmc@fe2c0000 { +- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xfe2c0000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, +- <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <150000000>; +- resets = <&cru SRST_SDMMC1>; +- reset-names = "reset"; +- status = "disabled"; +- }; +- +- sdhci: mmc@fe310000 { +- compatible = "rockchip,rk3568-dwcmshc"; +- reg = <0x0 0xfe310000 0x0 0x10000>; +- interrupts = ; +- assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; +- assigned-clock-rates = <200000000>, <24000000>; +- clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, +- <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, +- <&cru TCLK_EMMC>; +- clock-names = "core", "bus", "axi", "block", "timer"; +- status = "disabled"; +- }; +- +- dmac0: dmac@fe530000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xfe530000 0x0 0x4000>; +- interrupts = , +- ; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_BUS>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- }; +- +- dmac1: dmac@fe550000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xfe550000 0x0 0x4000>; +- interrupts = , +- ; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_BUS>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- }; +- +- i2c1: i2c@fe5a0000 { +- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfe5a0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c1_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@fe5b0000 { +- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfe5b0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c2m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@fe5c0000 { +- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfe5c0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c3m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@fe5d0000 { +- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfe5d0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c4m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@fe5e0000 { +- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfe5e0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c5m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- wdt: watchdog@fe600000 { +- compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; +- reg = <0x0 0xfe600000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; +- clock-names = "tclk", "pclk"; +- }; +- +- uart1: serial@fe650000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe650000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 2>, <&dmac0 3>; +- pinctrl-0 = <&uart1m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart2: serial@fe660000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe660000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 4>, <&dmac0 5>; +- pinctrl-0 = <&uart2m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart3: serial@fe670000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe670000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 6>, <&dmac0 7>; +- pinctrl-0 = <&uart3m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart4: serial@fe680000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe680000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 8>, <&dmac0 9>; +- pinctrl-0 = <&uart4m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart5: serial@fe690000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe690000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 10>, <&dmac0 11>; +- pinctrl-0 = <&uart5m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart6: serial@fe6a0000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe6a0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 12>, <&dmac0 13>; +- pinctrl-0 = <&uart6m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart7: serial@fe6b0000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe6b0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 14>, <&dmac0 15>; +- pinctrl-0 = <&uart7m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart8: serial@fe6c0000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe6c0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 16>, <&dmac0 17>; +- pinctrl-0 = <&uart8m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart9: serial@fe6d0000 { +- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfe6d0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 18>, <&dmac0 19>; +- pinctrl-0 = <&uart9m0_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@fe6e0000 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfe6e0000 0x0 0x10>; +- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm4_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm5: pwm@fe6e0010 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfe6e0010 0x0 0x10>; +- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm5_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm6: pwm@fe6e0020 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfe6e0020 0x0 0x10>; +- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm6_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm7: pwm@fe6e0030 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfe6e0030 0x0 0x10>; +- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm7_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm8: pwm@fe6f0000 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfe6f0000 0x0 0x10>; +- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm8m0_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm9: pwm@fe6f0010 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfe6f0010 0x0 0x10>; +- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm9m0_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm10: pwm@fe6f0020 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfe6f0020 0x0 0x10>; +- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm10m0_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm11: pwm@fe6f0030 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfe6f0030 0x0 0x10>; +- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm11m0_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm12: pwm@fe700000 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfe700000 0x0 0x10>; +- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm12m0_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; ++ combphy0: phy@fe820000 { ++ compatible = "rockchip,rk3568-naneng-combphy"; ++ reg = <0x0 0xfe820000 0x0 0x100>; ++ clocks = <&pmucru CLK_PCIEPHY0_REF>, ++ <&cru PCLK_PIPEPHY0>, ++ <&cru PCLK_PIPE>; ++ clock-names = "ref", "apb", "pipe"; ++ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; ++ assigned-clock-rates = <100000000>; ++ resets = <&cru SRST_PIPEPHY0>; ++ rockchip,pipe-grf = <&pipegrf>; ++ rockchip,pipe-phy-grf = <&pipe_phy_grf0>; ++ #phy-cells = <1>; + status = "disabled"; + }; ++}; + +- pwm13: pwm@fe700010 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfe700010 0x0 0x10>; +- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm13m0_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; ++&cpu0_opp_table { ++ opp-1992000000 { ++ opp-hz = /bits/ 64 <1992000000>; ++ opp-microvolt = <1150000 1150000 1150000>; + }; ++}; + +- pwm14: pwm@fe700020 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfe700020 0x0 0x10>; +- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm14m0_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; ++&pipegrf { ++ compatible = "rockchip,rk3568-pipe-grf", "syscon"; ++}; + +- pwm15: pwm@fe700030 { +- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfe700030 0x0 0x10>; +- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm15m0_pins>; +- pinctrl-names = "active"; +- #pwm-cells = <3>; +- status = "disabled"; ++&power { ++ power-domain@RK3568_PD_PIPE { ++ reg = ; ++ clocks = <&cru PCLK_PIPE>; ++ pm_qos = <&qos_pcie2x1>, ++ <&qos_pcie3x1>, ++ <&qos_pcie3x2>, ++ <&qos_sata0>, ++ <&qos_sata1>, ++ <&qos_sata2>, ++ <&qos_usb3_0>, ++ <&qos_usb3_1>; ++ #power-domain-cells = <0>; + }; ++}; + +- pinctrl: pinctrl { +- compatible = "rockchip,rk3568-pinctrl"; +- rockchip,grf = <&grf>; +- rockchip,pmu = <&pmugrf>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- gpio0: gpio@fdd60000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfdd60000 0x0 0x100>; +- interrupts = ; +- clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@fe740000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfe740000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@fe750000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfe750000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@fe760000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfe760000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@fe770000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfe770000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- }; +- }; ++&usb_host0_xhci { ++ phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; + }; + +-#include "rk3568-pinctrl.dtsi" ++&vop { ++ compatible = "rockchip,rk3568-vop"; ++}; +--- a/arch/arm/dts/rk3568-u-boot.dtsi ++++ /dev/null +@@ -1,56 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * (C) Copyright 2021 Rockchip Electronics Co., Ltd +- */ +- +-#include "rockchip-u-boot.dtsi" +- +-/ { +- aliases { +- mmc0 = &sdhci; +- mmc1 = &sdmmc0; +- }; +- +- chosen { +- u-boot,spl-boot-order = &sdhci, &sdmmc0; +- }; +- +- dmc: dmc { +- compatible = "rockchip,rk3568-dmc"; +- u-boot,dm-pre-reloc; +- status = "okay"; +- }; +-}; +- +-&cru { +- u-boot,dm-pre-reloc; +- status = "okay"; +-}; +- +-&pmucru { +- u-boot,dm-pre-reloc; +- status = "okay"; +-}; +- +-&grf { +- u-boot,dm-pre-reloc; +- status = "okay"; +-}; +- +-&pmugrf { +- u-boot,dm-pre-reloc; +- status = "okay"; +-}; +- +-&sdmmc0 { +- u-boot,dm-spl; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- u-boot,dm-spl; +- mmc-hs200-1_8v; +- status = "okay"; +-}; +- +--- /dev/null ++++ b/arch/arm/dts/rk356x-u-boot.dtsi +@@ -0,0 +1,53 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * (C) Copyright 2021 Rockchip Electronics Co., Ltd ++ */ ++ ++#include "rockchip-u-boot.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ }; ++ ++ chosen { ++ u-boot,spl-boot-order = &sdhci, &sdmmc0; ++ }; ++ ++ dmc: dmc { ++ compatible = "rockchip,rk3568-dmc"; ++ u-boot,dm-pre-reloc; ++ status = "okay"; ++ }; ++}; ++ ++&cru { ++ u-boot,dm-pre-reloc; ++ status = "okay"; ++}; ++ ++&pmucru { ++ u-boot,dm-pre-reloc; ++ status = "okay"; ++}; ++ ++&grf { ++ u-boot,dm-pre-reloc; ++ status = "okay"; ++}; ++ ++&pmugrf { ++ u-boot,dm-pre-reloc; ++ status = "okay"; ++}; ++ ++&sdhci { ++ u-boot,dm-spl; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ u-boot,dm-spl; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk356x.dtsi +@@ -0,0 +1,1706 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/ { ++ interrupt-parent = <&gic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ aliases { ++ gpio0 = &gpio0; ++ gpio1 = &gpio1; ++ gpio2 = &gpio2; ++ gpio3 = &gpio3; ++ gpio4 = &gpio4; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ i2c3 = &i2c3; ++ i2c4 = &i2c4; ++ i2c5 = &i2c5; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ serial4 = &uart4; ++ serial5 = &uart5; ++ serial6 = &uart6; ++ serial7 = &uart7; ++ serial8 = &uart8; ++ serial9 = &uart9; ++ spi0 = &spi0; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi3 = &spi3; ++ }; ++ ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x0 0x0>; ++ clocks = <&scmi_clk 0>; ++ #cooling-cells = <2>; ++ enable-method = "psci"; ++ operating-points-v2 = <&cpu0_opp_table>; ++ }; ++ ++ cpu1: cpu@100 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x0 0x100>; ++ #cooling-cells = <2>; ++ enable-method = "psci"; ++ operating-points-v2 = <&cpu0_opp_table>; ++ }; ++ ++ cpu2: cpu@200 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x0 0x200>; ++ #cooling-cells = <2>; ++ enable-method = "psci"; ++ operating-points-v2 = <&cpu0_opp_table>; ++ }; ++ ++ cpu3: cpu@300 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x0 0x300>; ++ #cooling-cells = <2>; ++ enable-method = "psci"; ++ operating-points-v2 = <&cpu0_opp_table>; ++ }; ++ }; ++ ++ cpu0_opp_table: opp-table-0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <900000 900000 1150000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <900000 900000 1150000>; ++ }; ++ ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <900000 900000 1150000>; ++ opp-suspend; ++ }; ++ ++ opp-1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <900000 900000 1150000>; ++ }; ++ ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <900000 900000 1150000>; ++ }; ++ ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <975000 975000 1150000>; ++ }; ++ ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <1050000 1050000 1150000>; ++ }; ++ }; ++ ++ display_subsystem: display-subsystem { ++ compatible = "rockchip,display-subsystem"; ++ ports = <&vop_out>; ++ }; ++ ++ firmware { ++ scmi: scmi { ++ compatible = "arm,scmi-smc"; ++ arm,smc-id = <0x82000010>; ++ shmem = <&scmi_shmem>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ scmi_clk: protocol@14 { ++ reg = <0x14>; ++ #clock-cells = <1>; ++ }; ++ }; ++ }; ++ ++ gpu_opp_table: opp-table-1 { ++ compatible = "operating-points-v2"; ++ ++ opp-200000000 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <825000>; ++ }; ++ ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <825000>; ++ }; ++ ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <825000>; ++ }; ++ ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <825000>; ++ }; ++ ++ opp-700000000 { ++ opp-hz = /bits/ 64 <700000000>; ++ opp-microvolt = <900000>; ++ }; ++ ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <1000000>; ++ }; ++ }; ++ ++ hdmi_sound: hdmi-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "HDMI"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ status = "disabled"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s0_8ch>; ++ }; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a55-pmu"; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ arm,no-tick-in-suspend; ++ }; ++ ++ xin24m: xin24m { ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ clock-output-names = "xin24m"; ++ #clock-cells = <0>; ++ }; ++ ++ xin32k: xin32k { ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "xin32k"; ++ pinctrl-0 = <&clk32k_out0>; ++ pinctrl-names = "default"; ++ #clock-cells = <0>; ++ }; ++ ++ sram@10f000 { ++ compatible = "mmio-sram"; ++ reg = <0x0 0x0010f000 0x0 0x100>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x0 0x0010f000 0x100>; ++ ++ scmi_shmem: sram@0 { ++ compatible = "arm,scmi-shmem"; ++ reg = <0x0 0x100>; ++ }; ++ }; ++ ++ sata1: sata@fc400000 { ++ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; ++ reg = <0 0xfc400000 0 0x1000>; ++ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, ++ <&cru CLK_SATA1_RXOOB>; ++ clock-names = "sata", "pmalive", "rxoob"; ++ interrupts = ; ++ phys = <&combphy1 PHY_TYPE_SATA>; ++ phy-names = "sata-phy"; ++ ports-implemented = <0x1>; ++ power-domains = <&power RK3568_PD_PIPE>; ++ status = "disabled"; ++ }; ++ ++ sata2: sata@fc800000 { ++ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; ++ reg = <0 0xfc800000 0 0x1000>; ++ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, ++ <&cru CLK_SATA2_RXOOB>; ++ clock-names = "sata", "pmalive", "rxoob"; ++ interrupts = ; ++ phys = <&combphy2 PHY_TYPE_SATA>; ++ phy-names = "sata-phy"; ++ ports-implemented = <0x1>; ++ power-domains = <&power RK3568_PD_PIPE>; ++ status = "disabled"; ++ }; ++ ++ usb_host0_xhci: usb@fcc00000 { ++ compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfcc00000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, ++ <&cru ACLK_USB3OTG0>; ++ clock-names = "ref_clk", "suspend_clk", ++ "bus_clk"; ++ dr_mode = "otg"; ++ phy_type = "utmi_wide"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ resets = <&cru SRST_USB3OTG0>; ++ snps,dis_u2_susphy_quirk; ++ status = "disabled"; ++ }; ++ ++ usb_host1_xhci: usb@fd000000 { ++ compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfd000000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, ++ <&cru ACLK_USB3OTG1>; ++ clock-names = "ref_clk", "suspend_clk", ++ "bus_clk"; ++ dr_mode = "host"; ++ phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi_wide"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ resets = <&cru SRST_USB3OTG1>; ++ snps,dis_u2_susphy_quirk; ++ status = "disabled"; ++ }; ++ ++ gic: interrupt-controller@fd400000 { ++ compatible = "arm,gic-v3"; ++ reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ ++ <0x0 0xfd460000 0 0x80000>; /* GICR */ ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ mbi-alias = <0x0 0xfd410000>; ++ mbi-ranges = <296 24>; ++ msi-controller; ++ }; ++ ++ usb_host0_ehci: usb@fd800000 { ++ compatible = "generic-ehci"; ++ reg = <0x0 0xfd800000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, ++ <&cru PCLK_USB>; ++ phys = <&usb2phy1_otg>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ usb_host0_ohci: usb@fd840000 { ++ compatible = "generic-ohci"; ++ reg = <0x0 0xfd840000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, ++ <&cru PCLK_USB>; ++ phys = <&usb2phy1_otg>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ usb_host1_ehci: usb@fd880000 { ++ compatible = "generic-ehci"; ++ reg = <0x0 0xfd880000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, ++ <&cru PCLK_USB>; ++ phys = <&usb2phy1_host>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ usb_host1_ohci: usb@fd8c0000 { ++ compatible = "generic-ohci"; ++ reg = <0x0 0xfd8c0000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, ++ <&cru PCLK_USB>; ++ phys = <&usb2phy1_host>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ pmugrf: syscon@fdc20000 { ++ compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; ++ reg = <0x0 0xfdc20000 0x0 0x10000>; ++ ++ pmu_io_domains: io-domains { ++ compatible = "rockchip,rk3568-pmu-io-voltage-domain"; ++ status = "disabled"; ++ }; ++ }; ++ ++ pipegrf: syscon@fdc50000 { ++ reg = <0x0 0xfdc50000 0x0 0x1000>; ++ }; ++ ++ grf: syscon@fdc60000 { ++ compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; ++ reg = <0x0 0xfdc60000 0x0 0x10000>; ++ }; ++ ++ pipe_phy_grf1: syscon@fdc80000 { ++ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; ++ reg = <0x0 0xfdc80000 0x0 0x1000>; ++ }; ++ ++ pipe_phy_grf2: syscon@fdc90000 { ++ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; ++ reg = <0x0 0xfdc90000 0x0 0x1000>; ++ }; ++ ++ usb2phy0_grf: syscon@fdca0000 { ++ compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; ++ reg = <0x0 0xfdca0000 0x0 0x8000>; ++ }; ++ ++ usb2phy1_grf: syscon@fdca8000 { ++ compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; ++ reg = <0x0 0xfdca8000 0x0 0x8000>; ++ }; ++ ++ pmucru: clock-controller@fdd00000 { ++ compatible = "rockchip,rk3568-pmucru"; ++ reg = <0x0 0xfdd00000 0x0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ cru: clock-controller@fdd20000 { ++ compatible = "rockchip,rk3568-cru"; ++ reg = <0x0 0xfdd20000 0x0 0x1000>; ++ clocks = <&xin24m>; ++ clock-names = "xin24m"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; ++ assigned-clock-rates = <1200000000>, <200000000>; ++ rockchip,grf = <&grf>; ++ }; ++ ++ i2c0: i2c@fdd40000 { ++ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfdd40000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; ++ clock-names = "i2c", "pclk"; ++ pinctrl-0 = <&i2c0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ uart0: serial@fdd50000 { ++ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfdd50000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 0>, <&dmac0 1>; ++ pinctrl-0 = <&uart0_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ pwm0: pwm@fdd70000 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfdd70000 0x0 0x10>; ++ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm0m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm1: pwm@fdd70010 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfdd70010 0x0 0x10>; ++ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm1m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm2: pwm@fdd70020 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfdd70020 0x0 0x10>; ++ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm2m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm3: pwm@fdd70030 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfdd70030 0x0 0x10>; ++ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm3_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pmu: power-management@fdd90000 { ++ compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; ++ reg = <0x0 0xfdd90000 0x0 0x1000>; ++ ++ power: power-controller { ++ compatible = "rockchip,rk3568-power-controller"; ++ #power-domain-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* These power domains are grouped by VD_GPU */ ++ power-domain@RK3568_PD_GPU { ++ reg = ; ++ clocks = <&cru ACLK_GPU_PRE>, ++ <&cru PCLK_GPU_PRE>; ++ pm_qos = <&qos_gpu>; ++ #power-domain-cells = <0>; ++ }; ++ ++ /* These power domains are grouped by VD_LOGIC */ ++ power-domain@RK3568_PD_VI { ++ reg = ; ++ clocks = <&cru HCLK_VI>, ++ <&cru PCLK_VI>; ++ pm_qos = <&qos_isp>, ++ <&qos_vicap0>, ++ <&qos_vicap1>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_VO { ++ reg = ; ++ clocks = <&cru HCLK_VO>, ++ <&cru PCLK_VO>, ++ <&cru ACLK_VOP_PRE>; ++ pm_qos = <&qos_hdcp>, ++ <&qos_vop_m0>, ++ <&qos_vop_m1>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_RGA { ++ reg = ; ++ clocks = <&cru HCLK_RGA_PRE>, ++ <&cru PCLK_RGA_PRE>; ++ pm_qos = <&qos_ebc>, ++ <&qos_iep>, ++ <&qos_jpeg_dec>, ++ <&qos_jpeg_enc>, ++ <&qos_rga_rd>, ++ <&qos_rga_wr>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_VPU { ++ reg = ; ++ clocks = <&cru HCLK_VPU_PRE>; ++ pm_qos = <&qos_vpu>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_RKVDEC { ++ clocks = <&cru HCLK_RKVDEC_PRE>; ++ reg = ; ++ pm_qos = <&qos_rkvdec>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_RKVENC { ++ reg = ; ++ clocks = <&cru HCLK_RKVENC_PRE>; ++ pm_qos = <&qos_rkvenc_rd_m0>, ++ <&qos_rkvenc_rd_m1>, ++ <&qos_rkvenc_wr_m0>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ }; ++ ++ gpu: gpu@fde60000 { ++ compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; ++ reg = <0x0 0xfde60000 0x0 0x4000>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "job", "mmu", "gpu"; ++ clocks = <&scmi_clk 1>, <&cru CLK_GPU>; ++ clock-names = "gpu", "bus"; ++ #cooling-cells = <2>; ++ operating-points-v2 = <&gpu_opp_table>; ++ power-domains = <&power RK3568_PD_GPU>; ++ status = "disabled"; ++ }; ++ ++ sdmmc2: mmc@fe000000 { ++ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x0 0xfe000000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, ++ <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; ++ fifo-depth = <0x100>; ++ max-frequency = <150000000>; ++ resets = <&cru SRST_SDMMC2>; ++ reset-names = "reset"; ++ status = "disabled"; ++ }; ++ ++ gmac1: ethernet@fe010000 { ++ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; ++ reg = <0x0 0xfe010000 0x0 0x10000>; ++ interrupts = , ++ ; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, ++ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, ++ <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, ++ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; ++ clock-names = "stmmaceth", "mac_clk_rx", ++ "mac_clk_tx", "clk_mac_refout", ++ "aclk_mac", "pclk_mac", ++ "clk_mac_speed", "ptp_ref"; ++ resets = <&cru SRST_A_GMAC1>; ++ reset-names = "stmmaceth"; ++ rockchip,grf = <&grf>; ++ snps,axi-config = <&gmac1_stmmac_axi_setup>; ++ snps,mixed-burst; ++ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; ++ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; ++ snps,tso; ++ status = "disabled"; ++ ++ mdio1: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ }; ++ ++ gmac1_stmmac_axi_setup: stmmac-axi-config { ++ snps,blen = <0 0 0 0 16 8 4>; ++ snps,rd_osr_lmt = <8>; ++ snps,wr_osr_lmt = <4>; ++ }; ++ ++ gmac1_mtl_rx_setup: rx-queues-config { ++ snps,rx-queues-to-use = <1>; ++ queue0 {}; ++ }; ++ ++ gmac1_mtl_tx_setup: tx-queues-config { ++ snps,tx-queues-to-use = <1>; ++ queue0 {}; ++ }; ++ }; ++ ++ vop: vop@fe040000 { ++ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; ++ reg-names = "vop", "gamma-lut"; ++ interrupts = ; ++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, ++ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; ++ clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; ++ iommus = <&vop_mmu>; ++ power-domains = <&power RK3568_PD_VO>; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ ++ vop_out: ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ vp0: port@0 { ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ vp1: port@1 { ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ vp2: port@2 { ++ reg = <2>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ }; ++ ++ vop_mmu: iommu@fe043e00 { ++ compatible = "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; ++ clock-names = "aclk", "iface"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ hdmi: hdmi@fe0a0000 { ++ compatible = "rockchip,rk3568-dw-hdmi"; ++ reg = <0x0 0xfe0a0000 0x0 0x20000>; ++ interrupts = ; ++ clocks = <&cru PCLK_HDMI_HOST>, ++ <&cru CLK_HDMI_SFR>, ++ <&cru CLK_HDMI_CEC>, ++ <&pmucru CLK_HDMI_REF>, ++ <&cru HCLK_VO>; ++ clock-names = "iahb", "isfr", "cec", "ref"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; ++ power-domains = <&power RK3568_PD_VO>; ++ reg-io-width = <4>; ++ rockchip,grf = <&grf>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hdmi_in: port@0 { ++ reg = <0>; ++ }; ++ ++ hdmi_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ ++ qos_gpu: qos@fe128000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe128000 0x0 0x20>; ++ }; ++ ++ qos_rkvenc_rd_m0: qos@fe138080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe138080 0x0 0x20>; ++ }; ++ ++ qos_rkvenc_rd_m1: qos@fe138100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe138100 0x0 0x20>; ++ }; ++ ++ qos_rkvenc_wr_m0: qos@fe138180 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe138180 0x0 0x20>; ++ }; ++ ++ qos_isp: qos@fe148000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe148000 0x0 0x20>; ++ }; ++ ++ qos_vicap0: qos@fe148080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe148080 0x0 0x20>; ++ }; ++ ++ qos_vicap1: qos@fe148100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe148100 0x0 0x20>; ++ }; ++ ++ qos_vpu: qos@fe150000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe150000 0x0 0x20>; ++ }; ++ ++ qos_ebc: qos@fe158000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158000 0x0 0x20>; ++ }; ++ ++ qos_iep: qos@fe158100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158100 0x0 0x20>; ++ }; ++ ++ qos_jpeg_dec: qos@fe158180 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158180 0x0 0x20>; ++ }; ++ ++ qos_jpeg_enc: qos@fe158200 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158200 0x0 0x20>; ++ }; ++ ++ qos_rga_rd: qos@fe158280 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158280 0x0 0x20>; ++ }; ++ ++ qos_rga_wr: qos@fe158300 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158300 0x0 0x20>; ++ }; ++ ++ qos_npu: qos@fe180000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe180000 0x0 0x20>; ++ }; ++ ++ qos_pcie2x1: qos@fe190000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190000 0x0 0x20>; ++ }; ++ ++ qos_sata1: qos@fe190280 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190280 0x0 0x20>; ++ }; ++ ++ qos_sata2: qos@fe190300 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190300 0x0 0x20>; ++ }; ++ ++ qos_usb3_0: qos@fe190380 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190380 0x0 0x20>; ++ }; ++ ++ qos_usb3_1: qos@fe190400 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190400 0x0 0x20>; ++ }; ++ ++ qos_rkvdec: qos@fe198000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe198000 0x0 0x20>; ++ }; ++ ++ qos_hdcp: qos@fe1a8000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe1a8000 0x0 0x20>; ++ }; ++ ++ qos_vop_m0: qos@fe1a8080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe1a8080 0x0 0x20>; ++ }; ++ ++ qos_vop_m1: qos@fe1a8100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe1a8100 0x0 0x20>; ++ }; ++ ++ pcie2x1: pcie@fe260000 { ++ compatible = "rockchip,rk3568-pcie"; ++ reg = <0x3 0xc0000000 0x0 0x00400000>, ++ <0x0 0xfe260000 0x0 0x00010000>, ++ <0x3 0x3f000000 0x0 0x01000000>; ++ reg-names = "dbi", "apb", "config"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msi", "legacy", "err"; ++ bus-range = <0x0 0xf>; ++ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, ++ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, ++ <&cru CLK_PCIE20_AUX_NDFT>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", "aux"; ++ device_type = "pci"; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc 0>, ++ <0 0 0 2 &pcie_intc 1>, ++ <0 0 0 3 &pcie_intc 2>, ++ <0 0 0 4 &pcie_intc 3>; ++ linux,pci-domain = <0>; ++ num-ib-windows = <6>; ++ num-ob-windows = <2>; ++ max-link-speed = <2>; ++ msi-map = <0x0 &gic 0x0 0x1000>; ++ num-lanes = <1>; ++ phys = <&combphy2 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 ++ 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; ++ resets = <&cru SRST_PCIE20_POWERUP>; ++ reset-names = "pipe"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ status = "disabled"; ++ ++ pcie_intc: legacy-interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ ++ sdmmc0: mmc@fe2b0000 { ++ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x0 0xfe2b0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, ++ <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; ++ fifo-depth = <0x100>; ++ max-frequency = <150000000>; ++ resets = <&cru SRST_SDMMC0>; ++ reset-names = "reset"; ++ status = "disabled"; ++ }; ++ ++ sdmmc1: mmc@fe2c0000 { ++ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x0 0xfe2c0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, ++ <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; ++ fifo-depth = <0x100>; ++ max-frequency = <150000000>; ++ resets = <&cru SRST_SDMMC1>; ++ reset-names = "reset"; ++ status = "disabled"; ++ }; ++ ++ sfc: spi@fe300000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0xfe300000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ pinctrl-0 = <&fspi_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ ++ sdhci: mmc@fe310000 { ++ compatible = "rockchip,rk3568-dwcmshc"; ++ reg = <0x0 0xfe310000 0x0 0x10000>; ++ interrupts = ; ++ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; ++ assigned-clock-rates = <200000000>, <24000000>; ++ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, ++ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, ++ <&cru TCLK_EMMC>; ++ clock-names = "core", "bus", "axi", "block", "timer"; ++ status = "disabled"; ++ }; ++ ++ spdif: spdif@fe460000 { ++ compatible = "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfe460000 0x0 0x1000>; ++ interrupts = ; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; ++ dmas = <&dmac1 1>; ++ dma-names = "tx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdifm0_tx>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s0_8ch: i2s@fe400000 { ++ compatible = "rockchip,rk3568-i2s-tdm"; ++ reg = <0x0 0xfe400000 0x0 0x1000>; ++ interrupts = ; ++ assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; ++ assigned-clock-rates = <1188000000>, <1188000000>; ++ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ dmas = <&dmac1 0>; ++ dma-names = "tx"; ++ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; ++ reset-names = "tx-m", "rx-m"; ++ rockchip,grf = <&grf>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s1_8ch: i2s@fe410000 { ++ compatible = "rockchip,rk3568-i2s-tdm"; ++ reg = <0x0 0xfe410000 0x0 0x1000>; ++ interrupts = ; ++ assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; ++ assigned-clock-rates = <1188000000>, <1188000000>; ++ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, ++ <&cru HCLK_I2S1_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ dmas = <&dmac1 3>, <&dmac1 2>; ++ dma-names = "rx", "tx"; ++ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; ++ reset-names = "tx-m", "rx-m"; ++ rockchip,grf = <&grf>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx ++ &i2s1m0_lrcktx &i2s1m0_lrckrx ++ &i2s1m0_sdi0 &i2s1m0_sdi1 ++ &i2s1m0_sdi2 &i2s1m0_sdi3 ++ &i2s1m0_sdo0 &i2s1m0_sdo1 ++ &i2s1m0_sdo2 &i2s1m0_sdo3>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s3_2ch: i2s@fe430000 { ++ compatible = "rockchip,rk3568-i2s-tdm"; ++ reg = <0x0 0xfe430000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, ++ <&cru HCLK_I2S3_2CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ dmas = <&dmac1 6>, <&dmac1 7>; ++ dma-names = "tx", "rx"; ++ resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; ++ reset-names = "tx-m", "rx-m"; ++ rockchip,grf = <&grf>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pdm: pdm@fe440000 { ++ compatible = "rockchip,rk3568-pdm"; ++ reg = <0x0 0xfe440000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; ++ clock-names = "pdm_clk", "pdm_hclk"; ++ dmas = <&dmac1 9>; ++ dma-names = "rx"; ++ pinctrl-0 = <&pdmm0_clk ++ &pdmm0_clk1 ++ &pdmm0_sdi0 ++ &pdmm0_sdi1 ++ &pdmm0_sdi2 ++ &pdmm0_sdi3>; ++ pinctrl-names = "default"; ++ resets = <&cru SRST_M_PDM>; ++ reset-names = "pdm-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ dmac0: dma-controller@fe530000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x0 0xfe530000 0x0 0x4000>; ++ interrupts = , ++ ; ++ arm,pl330-periph-burst; ++ clocks = <&cru ACLK_BUS>; ++ clock-names = "apb_pclk"; ++ #dma-cells = <1>; ++ }; ++ ++ dmac1: dma-controller@fe550000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x0 0xfe550000 0x0 0x4000>; ++ interrupts = , ++ ; ++ arm,pl330-periph-burst; ++ clocks = <&cru ACLK_BUS>; ++ clock-names = "apb_pclk"; ++ #dma-cells = <1>; ++ }; ++ ++ i2c1: i2c@fe5a0000 { ++ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfe5a0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; ++ clock-names = "i2c", "pclk"; ++ pinctrl-0 = <&i2c1_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@fe5b0000 { ++ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfe5b0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; ++ clock-names = "i2c", "pclk"; ++ pinctrl-0 = <&i2c2m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c3: i2c@fe5c0000 { ++ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfe5c0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; ++ clock-names = "i2c", "pclk"; ++ pinctrl-0 = <&i2c3m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c4: i2c@fe5d0000 { ++ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfe5d0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; ++ clock-names = "i2c", "pclk"; ++ pinctrl-0 = <&i2c4m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c5: i2c@fe5e0000 { ++ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfe5e0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; ++ clock-names = "i2c", "pclk"; ++ pinctrl-0 = <&i2c5m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ wdt: watchdog@fe600000 { ++ compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; ++ reg = <0x0 0xfe600000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; ++ clock-names = "tclk", "pclk"; ++ }; ++ ++ spi0: spi@fe610000 { ++ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfe610000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 20>, <&dmac0 21>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@fe620000 { ++ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfe620000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 22>, <&dmac0 23>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@fe630000 { ++ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfe630000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 24>, <&dmac0 25>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi3: spi@fe640000 { ++ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfe640000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 26>, <&dmac0 27>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ uart1: serial@fe650000 { ++ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfe650000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 2>, <&dmac0 3>; ++ pinctrl-0 = <&uart1m0_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@fe660000 { ++ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfe660000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 4>, <&dmac0 5>; ++ pinctrl-0 = <&uart2m0_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@fe670000 { ++ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfe670000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 6>, <&dmac0 7>; ++ pinctrl-0 = <&uart3m0_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@fe680000 { ++ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfe680000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 8>, <&dmac0 9>; ++ pinctrl-0 = <&uart4m0_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart5: serial@fe690000 { ++ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfe690000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 10>, <&dmac0 11>; ++ pinctrl-0 = <&uart5m0_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart6: serial@fe6a0000 { ++ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfe6a0000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 12>, <&dmac0 13>; ++ pinctrl-0 = <&uart6m0_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart7: serial@fe6b0000 { ++ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfe6b0000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 14>, <&dmac0 15>; ++ pinctrl-0 = <&uart7m0_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart8: serial@fe6c0000 { ++ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfe6c0000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 16>, <&dmac0 17>; ++ pinctrl-0 = <&uart8m0_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart9: serial@fe6d0000 { ++ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfe6d0000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 18>, <&dmac0 19>; ++ pinctrl-0 = <&uart9m0_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ thermal_zones: thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsadc 0>; ++ ++ trips { ++ cpu_alert0: cpu_alert0 { ++ temperature = <70000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ cpu_alert1: cpu_alert1 { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ cpu_crit: cpu_crit { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_alert0>; ++ cooling-device = ++ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ gpu_thermal: gpu-thermal { ++ polling-delay-passive = <20>; /* milliseconds */ ++ polling-delay = <1000>; /* milliseconds */ ++ ++ thermal-sensors = <&tsadc 1>; ++ ++ trips { ++ gpu_threshold: gpu-threshold { ++ temperature = <70000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ gpu_target: gpu-target { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ gpu_crit: gpu-crit { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&gpu_target>; ++ cooling-device = ++ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ }; ++ ++ tsadc: tsadc@fe710000 { ++ compatible = "rockchip,rk3568-tsadc"; ++ reg = <0x0 0xfe710000 0x0 0x100>; ++ interrupts = ; ++ assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; ++ assigned-clock-rates = <17000000>, <700000>; ++ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; ++ clock-names = "tsadc", "apb_pclk"; ++ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, ++ <&cru SRST_TSADCPHY>; ++ rockchip,grf = <&grf>; ++ rockchip,hw-tshut-temp = <95000>; ++ pinctrl-names = "init", "default", "sleep"; ++ pinctrl-0 = <&tsadc_pin>; ++ pinctrl-1 = <&tsadc_shutorg>; ++ pinctrl-2 = <&tsadc_pin>; ++ #thermal-sensor-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ saradc: saradc@fe720000 { ++ compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; ++ reg = <0x0 0xfe720000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; ++ clock-names = "saradc", "apb_pclk"; ++ resets = <&cru SRST_P_SARADC>; ++ reset-names = "saradc-apb"; ++ #io-channel-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ pwm4: pwm@fe6e0000 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6e0000 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm4_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm5: pwm@fe6e0010 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6e0010 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm5_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm6: pwm@fe6e0020 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6e0020 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm6_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm7: pwm@fe6e0030 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6e0030 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm7_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm8: pwm@fe6f0000 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6f0000 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm8m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm9: pwm@fe6f0010 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6f0010 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm9m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm10: pwm@fe6f0020 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6f0020 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm10m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm11: pwm@fe6f0030 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6f0030 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm11m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm12: pwm@fe700000 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe700000 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm12m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm13: pwm@fe700010 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe700010 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm13m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm14: pwm@fe700020 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe700020 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm14m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm15: pwm@fe700030 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe700030 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm15m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ combphy1: phy@fe830000 { ++ compatible = "rockchip,rk3568-naneng-combphy"; ++ reg = <0x0 0xfe830000 0x0 0x100>; ++ clocks = <&pmucru CLK_PCIEPHY1_REF>, ++ <&cru PCLK_PIPEPHY1>, ++ <&cru PCLK_PIPE>; ++ clock-names = "ref", "apb", "pipe"; ++ assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; ++ assigned-clock-rates = <100000000>; ++ resets = <&cru SRST_PIPEPHY1>; ++ rockchip,pipe-grf = <&pipegrf>; ++ rockchip,pipe-phy-grf = <&pipe_phy_grf1>; ++ #phy-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ combphy2: phy@fe840000 { ++ compatible = "rockchip,rk3568-naneng-combphy"; ++ reg = <0x0 0xfe840000 0x0 0x100>; ++ clocks = <&pmucru CLK_PCIEPHY2_REF>, ++ <&cru PCLK_PIPEPHY2>, ++ <&cru PCLK_PIPE>; ++ clock-names = "ref", "apb", "pipe"; ++ assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; ++ assigned-clock-rates = <100000000>; ++ resets = <&cru SRST_PIPEPHY2>; ++ rockchip,pipe-grf = <&pipegrf>; ++ rockchip,pipe-phy-grf = <&pipe_phy_grf2>; ++ #phy-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ usb2phy0: usb2phy@fe8a0000 { ++ compatible = "rockchip,rk3568-usb2phy"; ++ reg = <0x0 0xfe8a0000 0x0 0x10000>; ++ clocks = <&pmucru CLK_USBPHY0_REF>; ++ clock-names = "phyclk"; ++ clock-output-names = "clk_usbphy0_480m"; ++ interrupts = ; ++ rockchip,usbgrf = <&usb2phy0_grf>; ++ #clock-cells = <0>; ++ status = "disabled"; ++ ++ usb2phy0_host: host-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ usb2phy0_otg: otg-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ ++ usb2phy1: usb2phy@fe8b0000 { ++ compatible = "rockchip,rk3568-usb2phy"; ++ reg = <0x0 0xfe8b0000 0x0 0x10000>; ++ clocks = <&pmucru CLK_USBPHY1_REF>; ++ clock-names = "phyclk"; ++ clock-output-names = "clk_usbphy1_480m"; ++ interrupts = ; ++ rockchip,usbgrf = <&usb2phy1_grf>; ++ #clock-cells = <0>; ++ status = "disabled"; ++ ++ usb2phy1_host: host-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ usb2phy1_otg: otg-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ ++ pinctrl: pinctrl { ++ compatible = "rockchip,rk3568-pinctrl"; ++ rockchip,grf = <&grf>; ++ rockchip,pmu = <&pmugrf>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ gpio0: gpio@fdd60000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfdd60000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio1: gpio@fe740000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfe740000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio2: gpio@fe750000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfe750000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio3: gpio@fe760000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfe760000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio4: gpio@fe770000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfe770000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ }; ++}; ++ ++#include "rk3568-pinctrl.dtsi" +--- /dev/null ++++ b/include/dt-bindings/power/rk3568-power.h +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ ++#define __DT_BINDINGS_POWER_RK3568_POWER_H__ ++ ++/* VD_CORE */ ++#define RK3568_PD_CPU_0 0 ++#define RK3568_PD_CPU_1 1 ++#define RK3568_PD_CPU_2 2 ++#define RK3568_PD_CPU_3 3 ++#define RK3568_PD_CORE_ALIVE 4 ++ ++/* VD_PMU */ ++#define RK3568_PD_PMU 5 ++ ++/* VD_NPU */ ++#define RK3568_PD_NPU 6 ++ ++/* VD_GPU */ ++#define RK3568_PD_GPU 7 ++ ++/* VD_LOGIC */ ++#define RK3568_PD_VI 8 ++#define RK3568_PD_VO 9 ++#define RK3568_PD_RGA 10 ++#define RK3568_PD_VPU 11 ++#define RK3568_PD_CENTER 12 ++#define RK3568_PD_RKVDEC 13 ++#define RK3568_PD_RKVENC 14 ++#define RK3568_PD_PIPE 15 ++#define RK3568_PD_LOGIC_ALIVE 16 ++ ++#endif diff --git a/package/boot/uboot-rockchip/patches/100-clk-rockchip-rk3568-fix-reset-handler.patch b/package/boot/uboot-rockchip/patches/100-clk-rockchip-rk3568-fix-reset-handler.patch new file mode 100644 index 0000000000..fa98e2ac26 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/100-clk-rockchip-rk3568-fix-reset-handler.patch @@ -0,0 +1,43 @@ +From: Peter Geis +To: Simon Glass , + Philipp Tomsich , + Kever Yang , + Lukasz Majewski , + Sean Anderson , + Elaine Zhang +Cc: Peter Geis , u-boot@lists.denx.de +Subject: [PATCH v1 01/11] clk: rockchip: rk3568: fix reset handler +Date: Mon, 21 Feb 2022 20:31:20 -0500 [thread overview] +Message-ID: <20220222013131.3114990-2-pgwipeout@gmail.com> (raw) +In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> + +The reset handler for rk3568 is missing its private data. This leads to +an abort when a reset is triggered. + +Add the missing dev_set_priv to the rk3568 clk driver. + +Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") + +Signed-off-by: Peter Geis +--- + drivers/clk/rockchip/clk_rk3568.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/clk/rockchip/clk_rk3568.c ++++ b/drivers/clk/rockchip/clk_rk3568.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -2934,6 +2935,7 @@ static int rk3568_clk_bind(struct udevic + glb_srst_fst); + priv->glb_srst_snd_value = offsetof(struct rk3568_cru, + glb_srsr_snd); ++ dev_set_priv(sys_child, priv); + } + + #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) diff --git a/package/boot/uboot-rockchip/patches/101-spl-support-adc-drivers-in-spl.patch b/package/boot/uboot-rockchip/patches/101-spl-support-adc-drivers-in-spl.patch new file mode 100644 index 0000000000..f164cdb6c2 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/101-spl-support-adc-drivers-in-spl.patch @@ -0,0 +1,40 @@ +From: Peter Geis +Cc: Peter Geis , u-boot@lists.denx.de +Subject: [PATCH v1 05/11] spl: support adc drivers in spl +Date: Mon, 21 Feb 2022 20:31:24 -0500 [thread overview] +Message-ID: <20220222013131.3114990-6-pgwipeout@gmail.com> (raw) +In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> + +In order to handle the rockchip recovery handler in spl, we need the adc +code to be available in spl. +Add a toggle to allow adc drivers to function in spl. + +Signed-off-by: Peter Geis +--- + common/spl/Kconfig | 5 +++++ + drivers/Makefile | 1 + + 2 files changed, 6 insertions(+) + +--- a/common/spl/Kconfig ++++ b/common/spl/Kconfig +@@ -578,6 +578,11 @@ config SPL_FIT_IMAGE_TINY + ensure this information is available to the next image + invoked). + ++config SPL_ADC ++ bool "Support ADC drivers in SPL" ++ help ++ Enable ADC drivers in SPL. ++ + config SPL_CACHE + bool "Support CACHE drivers" + help +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -1,5 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0+ + ++obj-$(CONFIG_$(SPL_)ADC) += adc/ + obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ + obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/ + obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/ diff --git a/package/boot/uboot-rockchip/patches/102-rockchip-handle-bootrom-recovery-mode-in-spl.patch b/package/boot/uboot-rockchip/patches/102-rockchip-handle-bootrom-recovery-mode-in-spl.patch new file mode 100644 index 0000000000..3557a23acf --- /dev/null +++ b/package/boot/uboot-rockchip/patches/102-rockchip-handle-bootrom-recovery-mode-in-spl.patch @@ -0,0 +1,95 @@ +From: Peter Geis +To: Simon Glass , + Philipp Tomsich , + Kever Yang +Cc: Peter Geis , u-boot@lists.denx.de +Subject: [PATCH v1 06/11] rockchip: handle bootrom recovery mode in spl +Date: Mon, 21 Feb 2022 20:31:25 -0500 [thread overview] +Message-ID: <20220222013131.3114990-7-pgwipeout@gmail.com> (raw) +In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> + +Fixup the bootrom recovery mode code to function in spl, so we can +handle recovery mode in case u-boot loading is broken. + +Signed-off-by: Peter Geis +--- + arch/arm/mach-rockchip/Makefile | 6 +++--- + arch/arm/mach-rockchip/boot_mode.c | 4 +++- + arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++ + 3 files changed, 29 insertions(+), 4 deletions(-) + +--- a/arch/arm/mach-rockchip/Makefile ++++ b/arch/arm/mach-rockchip/Makefile +@@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30- + + obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o + +-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) +- + # Always include boot_mode.o, as we bypass it (i.e. turn it off) + # inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0. This way, + # we can have the preprocessor correctly recognise both 0x0 and 0 + # meaning "turn it off". +-obj-y += boot_mode.o ++obj-$(CONFIG_ARCH_ROCKCHIP) += boot_mode.o ++ ++ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) + obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o + obj-$(CONFIG_MISC_INIT_R) += misc.o + endif +--- a/arch/arm/mach-rockchip/boot_mode.c ++++ b/arch/arm/mach-rockchip/boot_mode.c +@@ -51,7 +51,7 @@ __weak int rockchip_dnl_key_pressed(void + ret = -ENODEV; + uclass_foreach_dev(dev, uc) { + if (!strncmp(dev->name, "saradc", 6)) { +- ret = adc_channel_single_shot(dev->name, 1, &val); ++ ret = adc_channel_single_shot(dev->name, 0, &val); + break; + } + } +@@ -89,6 +89,7 @@ int setup_boot_mode(void) + boot_mode = readl(reg); + debug("%s: boot mode 0x%08x\n", __func__, boot_mode); + ++#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) + /* Clear boot mode */ + writel(BOOT_NORMAL, reg); + +@@ -102,6 +103,7 @@ int setup_boot_mode(void) + env_set("preboot", "setenv preboot; ums mmc 0"); + break; + } ++#endif + + return 0; + } +--- a/arch/arm/mach-rockchip/rk3568/rk3568.c ++++ b/arch/arm/mach-rockchip/rk3568/rk3568.c +@@ -104,3 +104,26 @@ int arch_cpu_init(void) + #endif + return 0; + } ++ ++#ifdef CONFIG_SPL_BUILD ++ ++void __weak led_setup(void) ++{ ++} ++ ++void spl_board_init(void) ++{ ++ led_setup(); ++ ++#if (CONFIG_IS_ENABLED(DM_REGULATOR)) ++ /* ++ * Turning the eMMC and SPI back on (if disabled via the Qseven ++ * BIOS_ENABLE) signal is done through a always-on regulator). ++ */ ++ if (regulators_enable_boot_on(false)) ++ debug("%s: Cannot enable boot on regulator\n", __func__); ++#endif ++ ++ setup_boot_mode(); ++} ++#endif diff --git a/package/boot/uboot-rockchip/patches/103-rockchip-rk3568-add-boot-device-detection.patch b/package/boot/uboot-rockchip/patches/103-rockchip-rk3568-add-boot-device-detection.patch new file mode 100644 index 0000000000..6e1a135f3b --- /dev/null +++ b/package/boot/uboot-rockchip/patches/103-rockchip-rk3568-add-boot-device-detection.patch @@ -0,0 +1,48 @@ +From: Peter Geis +To: Simon Glass , + Philipp Tomsich , + Kever Yang +Cc: Peter Geis , u-boot@lists.denx.de +Subject: [PATCH v1 07/11] rockchip: rk3568: add boot device detection +Date: Mon, 21 Feb 2022 20:31:26 -0500 [thread overview] +Message-ID: <20220222013131.3114990-8-pgwipeout@gmail.com> (raw) +In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> + +Enable rk3568 spl to detect which device it was booted from. + +Signed-off-by: Peter Geis +--- + arch/arm/mach-rockchip/rk3568/rk3568.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm/mach-rockchip/rk3568/rk3568.c ++++ b/arch/arm/mach-rockchip/rk3568/rk3568.c +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -23,6 +24,7 @@ + #define SGRF_SOC_CON4 0x10 + #define EMMC_HPROT_SECURE_CTRL 0x03 + #define SDMMC0_HPROT_SECURE_CTRL 0x01 ++ + /* PMU_GRF_GPIO0D_IOMUX_L */ + enum { + GPIO0D1_SHIFT = 4, +@@ -43,6 +45,12 @@ enum { + UART2_IO_SEL_M0 = 0, + }; + ++const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { ++ [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000", ++ [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0", ++ [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000", ++}; ++ + static struct mm_region rk3568_mem_map[] = { + { + .virt = 0x0UL, diff --git a/package/boot/uboot-rockchip/patches/104-rockchip-rk3568-enable-automatic-clock-gating.patch b/package/boot/uboot-rockchip/patches/104-rockchip-rk3568-enable-automatic-clock-gating.patch new file mode 100644 index 0000000000..4a9549707d --- /dev/null +++ b/package/boot/uboot-rockchip/patches/104-rockchip-rk3568-enable-automatic-clock-gating.patch @@ -0,0 +1,57 @@ +From: Peter Geis +To: Simon Glass , + Philipp Tomsich , + Kever Yang +Cc: Peter Geis , u-boot@lists.denx.de +Subject: [PATCH v1 08/11] rockchip: rk3568: enable automatic clock gating +Date: Mon, 21 Feb 2022 20:31:27 -0500 [thread overview] +Message-ID: <20220222013131.3114990-9-pgwipeout@gmail.com> (raw) +In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> + +Enable automatic clock gating on rk3568, which solves a 7c temperature +difference on SoQuartz compared to downstream. + +Signed-off-by: Peter Geis +--- + arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/arch/arm/mach-rockchip/rk3568/rk3568.c ++++ b/arch/arm/mach-rockchip/rk3568/rk3568.c +@@ -25,6 +25,15 @@ + #define EMMC_HPROT_SECURE_CTRL 0x03 + #define SDMMC0_HPROT_SECURE_CTRL 0x01 + ++#define PMU_BASE_ADDR 0xfdd90000 ++#define PMU_NOC_AUTO_CON0 (0x70) ++#define PMU_NOC_AUTO_CON1 (0x74) ++#define EDP_PHY_GRF_BASE 0xfdcb0000 ++#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00) ++#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28) ++#define CPU_GRF_BASE 0xfdc30000 ++#define GRF_CORE_PVTPLL_CON0 (0x10) ++ + /* PMU_GRF_GPIO0D_IOMUX_L */ + enum { + GPIO0D1_SHIFT = 4, +@@ -99,6 +108,20 @@ void board_debug_uart_init(void) + int arch_cpu_init(void) + { + #ifdef CONFIG_SPL_BUILD ++ /* ++ * When perform idle operation, corresponding clock can ++ * be opened or gated automatically. ++ */ ++ writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0); ++ writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1); ++ ++ /* Disable eDP phy by default */ ++ writel(0x00070007, EDP_PHY_GRF_CON10); ++ writel(0x0ff10ff1, EDP_PHY_GRF_CON0); ++ ++ /* Set core pvtpll ring length */ ++ writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0); ++ + /* Set the emmc sdmmc0 to secure */ + rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11 + | SDMMC0_HPROT_SECURE_CTRL << 4)); diff --git a/package/boot/uboot-rockchip/patches/105-rockchip-move-dwc3-config-to-chip-specific-handler.patch b/package/boot/uboot-rockchip/patches/105-rockchip-move-dwc3-config-to-chip-specific-handler.patch new file mode 100644 index 0000000000..7dfc3d5f55 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/105-rockchip-move-dwc3-config-to-chip-specific-handler.patch @@ -0,0 +1,87 @@ +From: Peter Geis +To: Simon Glass , + Philipp Tomsich , + Kever Yang +Cc: Peter Geis , u-boot@lists.denx.de +Subject: [PATCH v1 09/11] rockchip: move dwc3 config to chip specific handler +Date: Mon, 21 Feb 2022 20:31:28 -0500 [thread overview] +Message-ID: <20220222013131.3114990-10-pgwipeout@gmail.com> (raw) +In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> + +The dwc3 code in the mach-rockchip board file is specific to the rk3399. +Move it to the rk3399 chip specific code. + +Signed-off-by: Peter Geis +--- + arch/arm/mach-rockchip/board.c | 24 --------------------- + arch/arm/mach-rockchip/rk3399/rk3399.c | 29 ++++++++++++++++++++++++++ + 2 files changed, 29 insertions(+), 24 deletions(-) + +--- a/arch/arm/mach-rockchip/board.c ++++ b/arch/arm/mach-rockchip/board.c +@@ -127,30 +127,6 @@ int board_usb_cleanup(int index, enum us + } + #endif /* CONFIG_USB_GADGET_DWC2_OTG */ + +-#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET) +-#include +- +-static struct dwc3_device dwc3_device_data = { +- .maximum_speed = USB_SPEED_HIGH, +- .base = 0xfe800000, +- .dr_mode = USB_DR_MODE_PERIPHERAL, +- .index = 0, +- .dis_u2_susphy_quirk = 1, +- .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW, +-}; +- +-int usb_gadget_handle_interrupts(int index) +-{ +- dwc3_uboot_handle_interrupt(0); +- return 0; +-} +- +-int board_usb_init(int index, enum usb_init_type init) +-{ +- return dwc3_uboot_init(&dwc3_device_data); +-} +-#endif /* CONFIG_USB_DWC3_GADGET */ +- + #endif /* CONFIG_USB_GADGET */ + + #if CONFIG_IS_ENABLED(FASTBOOT) +--- a/arch/arm/mach-rockchip/rk3399/rk3399.c ++++ b/arch/arm/mach-rockchip/rk3399/rk3399.c +@@ -285,3 +285,32 @@ void spl_board_init(void) + #endif + } + #endif ++ ++#if defined(CONFIG_USB_GADGET) ++#include ++ ++#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET) ++#include ++ ++static struct dwc3_device dwc3_device_data = { ++ .maximum_speed = USB_SPEED_HIGH, ++ .base = 0xfe800000, ++ .dr_mode = USB_DR_MODE_PERIPHERAL, ++ .index = 0, ++ .dis_u2_susphy_quirk = 1, ++ .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW, ++}; ++ ++int usb_gadget_handle_interrupts(int index) ++{ ++ dwc3_uboot_handle_interrupt(0); ++ return 0; ++} ++ ++int board_usb_init(int index, enum usb_init_type init) ++{ ++ return dwc3_uboot_init(&dwc3_device_data); ++} ++#endif /* CONFIG_USB_DWC3_GADGET */ ++ ++#endif /* CONFIG_USB_GADGET */ diff --git a/package/boot/uboot-rockchip/patches/106-rockchip-rk3568-add-dwc3-otg-support.patch b/package/boot/uboot-rockchip/patches/106-rockchip-rk3568-add-dwc3-otg-support.patch new file mode 100644 index 0000000000..52d12c17fa --- /dev/null +++ b/package/boot/uboot-rockchip/patches/106-rockchip-rk3568-add-dwc3-otg-support.patch @@ -0,0 +1,53 @@ +From: Peter Geis +To: Simon Glass , + Philipp Tomsich , + Kever Yang +Cc: Peter Geis , u-boot@lists.denx.de +Subject: [PATCH v1 10/11] rockchip: rk3568: add dwc3 otg support +Date: Mon, 21 Feb 2022 20:31:29 -0500 [thread overview] +Message-ID: <20220222013131.3114990-11-pgwipeout@gmail.com> (raw) +In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> + +Add the required platform data to the rk3568 chip config, in order to +support dwc3 otg on this chip. + +Signed-off-by: Peter Geis +--- + arch/arm/mach-rockchip/rk3568/rk3568.c | 29 ++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +--- a/arch/arm/mach-rockchip/rk3568/rk3568.c ++++ b/arch/arm/mach-rockchip/rk3568/rk3568.c +@@ -158,3 +158,32 @@ void spl_board_init(void) + setup_boot_mode(); + } + #endif ++ ++#if defined(CONFIG_USB_GADGET) ++#include ++ ++#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET) ++#include ++ ++static struct dwc3_device dwc3_device_data = { ++ .maximum_speed = USB_SPEED_HIGH, ++ .base = 0xfcc00000, ++ .dr_mode = USB_DR_MODE_PERIPHERAL, ++ .index = 0, ++ .dis_u2_susphy_quirk = 1, ++ .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW, ++}; ++ ++int usb_gadget_handle_interrupts(int index) ++{ ++ dwc3_uboot_handle_interrupt(0); ++ return 0; ++} ++ ++int board_usb_init(int index, enum usb_init_type init) ++{ ++ return dwc3_uboot_init(&dwc3_device_data); ++} ++#endif /* CONFIG_USB_DWC3_GADGET */ ++ ++#endif /* CONFIG_USB_GADGET */ diff --git a/package/boot/uboot-rockchip/patches/107-gpio-rockchip-rk_gpio-support-v2-gpio-controller.patch.patch b/package/boot/uboot-rockchip/patches/107-gpio-rockchip-rk_gpio-support-v2-gpio-controller.patch.patch new file mode 100644 index 0000000000..3066eaaf43 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/107-gpio-rockchip-rk_gpio-support-v2-gpio-controller.patch.patch @@ -0,0 +1,755 @@ +From 3a4d973a743bc76cc734db9616f9053f45fa922f Mon Sep 17 00:00:00 2001 +From: Jianqun Xu +Date: Thu, 28 May 2020 11:01:58 +0800 +Subject: [PATCH 07/11] gpio/rockchip: rk_gpio support v2 gpio controller + +The v2 gpio controller add write enable bit for some register, +such as data register, data direction register and so on. + +This patch support v2 gpio controller by redefine the read and +write operation functions. + +Also adds support for the rk3568 pinctrl device. + +Squash all fixes into this commit. + +Change-Id: I2adbcca06a37c48e6f494b89833cd034ba0dae29 +Signed-off-by: Jianqun Xu +Signed-off-by: Peter Geis +--- + arch/arm/include/asm/arch-rockchip/gpio.h | 36 ++ + drivers/gpio/Kconfig | 13 + + drivers/gpio/rk_gpio.c | 89 ++++- + drivers/pinctrl/rockchip/Makefile | 1 + + drivers/pinctrl/rockchip/pinctrl-rk3568.c | 360 ++++++++++++++++++ + .../pinctrl/rockchip/pinctrl-rockchip-core.c | 11 +- + drivers/pinctrl/rockchip/pinctrl-rockchip.h | 42 ++ + 7 files changed, 530 insertions(+), 22 deletions(-) + create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c + +--- a/arch/arm/include/asm/arch-rockchip/gpio.h ++++ b/arch/arm/include/asm/arch-rockchip/gpio.h +@@ -6,6 +6,7 @@ + #ifndef _ASM_ARCH_GPIO_H + #define _ASM_ARCH_GPIO_H + ++#ifndef CONFIG_ROCKCHIP_GPIO_V2 + struct rockchip_gpio_regs { + u32 swport_dr; + u32 swport_ddr; +@@ -23,6 +24,41 @@ struct rockchip_gpio_regs { + u32 ls_sync; + }; + check_member(rockchip_gpio_regs, ls_sync, 0x60); ++#else ++struct rockchip_gpio_regs { ++ u32 swport_dr_l; /* ADDRESS OFFSET: 0x0000 */ ++ u32 swport_dr_h; /* ADDRESS OFFSET: 0x0004 */ ++ u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */ ++ u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */ ++ u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */ ++ u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */ ++ u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */ ++ u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */ ++ u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */ ++ u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */ ++ u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */ ++ u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */ ++ u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */ ++ u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */ ++ u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */ ++ u32 debounce_h; /* ADDRESS OFFSET: 0x003c */ ++ u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */ ++ u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */ ++ u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */ ++ u32 reserved004c; /* ADDRESS OFFSET: 0x004c */ ++ u32 int_status; /* ADDRESS OFFSET: 0x0050 */ ++ u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */ ++ u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */ ++ u32 reserved005c; /* ADDRESS OFFSET: 0x005c */ ++ u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */ ++ u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */ ++ u32 reserved0068[2]; /* ADDRESS OFFSET: 0x0068 */ ++ u32 ext_port; /* ADDRESS OFFSET: 0x0070 */ ++ u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */ ++ u32 ver_id; /* ADDRESS OFFSET: 0x0078 */ ++}; ++check_member(rockchip_gpio_regs, ver_id, 0x0078); ++#endif + + enum gpio_pu_pd { + GPIO_PULL_NORMAL = 0, +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -341,6 +341,19 @@ config ROCKCHIP_GPIO + The GPIOs for a device are defined in the device tree with one node + for each bank. + ++config ROCKCHIP_GPIO_V2 ++ bool "Rockchip GPIO driver version 2.0" ++ depends on ROCKCHIP_GPIO ++ default n ++ help ++ Support GPIO access on Rockchip SoCs. The GPIOs are arranged into ++ a number of banks (different for each SoC type) each with 32 GPIOs. ++ The GPIOs for a device are defined in the device tree with one node ++ for each bank. ++ ++ Support version 2.0 GPIO controller, which support write enable bits ++ for some registers, such as dr, ddr. ++ + config SANDBOX_GPIO + bool "Enable sandbox GPIO driver" + depends on SANDBOX && DM && DM_GPIO +--- a/drivers/gpio/rk_gpio.c ++++ b/drivers/gpio/rk_gpio.c +@@ -2,12 +2,15 @@ + /* + * (C) Copyright 2015 Google, Inc + * +- * (C) Copyright 2008-2014 Rockchip Electronics ++ * (C) Copyright 2008-2020 Rockchip Electronics + * Peter, Software Engineering, . ++ * Jianqun Xu, Software Engineering, . + */ + + #include + #include ++#include ++#include + #include + #include + #include +@@ -17,12 +20,34 @@ + #include + #include + +-enum { +- ROCKCHIP_GPIOS_PER_BANK = 32, +-}; ++#include "../pinctrl/rockchip/pinctrl-rockchip.h" + + #define OFFSET_TO_BIT(bit) (1UL << (bit)) + ++#ifdef CONFIG_ROCKCHIP_GPIO_V2 ++#define REG_L(R) (R##_l) ++#define REG_H(R) (R##_h) ++#define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \ ++ ((readl(REG_H(REG)) & 0xFFFF) << 16)) ++#define WRITE_REG(REG, VAL) \ ++{\ ++ writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \ ++ writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\ ++} ++#define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK)) ++#define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK)) ++#define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \ ++ (READ_REG(REG) & ~(MASK)) | (VAL)) ++ ++#else ++#define READ_REG(REG) readl(REG) ++#define WRITE_REG(REG, VAL) writel(VAL, REG) ++#define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK) ++#define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK) ++#define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL) ++#endif ++ ++ + struct rockchip_gpio_priv { + struct rockchip_gpio_regs *regs; + struct udevice *pinctrl; +@@ -35,7 +60,7 @@ static int rockchip_gpio_direction_input + struct rockchip_gpio_priv *priv = dev_get_priv(dev); + struct rockchip_gpio_regs *regs = priv->regs; + +- clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset)); ++ CLRBITS_LE32(®s->swport_ddr, OFFSET_TO_BIT(offset)); + + return 0; + } +@@ -47,8 +72,8 @@ static int rockchip_gpio_direction_outpu + struct rockchip_gpio_regs *regs = priv->regs; + int mask = OFFSET_TO_BIT(offset); + +- clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0); +- setbits_le32(®s->swport_ddr, mask); ++ CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0); ++ SETBITS_LE32(®s->swport_ddr, mask); + + return 0; + } +@@ -68,7 +93,7 @@ static int rockchip_gpio_set_value(struc + struct rockchip_gpio_regs *regs = priv->regs; + int mask = OFFSET_TO_BIT(offset); + +- clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0); ++ CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0); + + return 0; + } +@@ -86,8 +111,8 @@ static int rockchip_gpio_get_function(st + ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset); + if (ret) + return ret; +- is_output = readl(®s->swport_ddr) & OFFSET_TO_BIT(offset); +- ++ is_output = READ_REG(®s->swport_ddr) & OFFSET_TO_BIT(offset); ++ + return is_output ? GPIOF_OUTPUT : GPIOF_INPUT; + #endif + } +@@ -142,19 +167,49 @@ static int rockchip_gpio_probe(struct ud + { + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct rockchip_gpio_priv *priv = dev_get_priv(dev); +- char *end; +- int ret; ++ struct rockchip_pinctrl_priv *pctrl_priv; ++ struct rockchip_pin_bank *bank; ++ char *end = NULL; ++ static int gpio; ++ int id = -1, ret; + + priv->regs = dev_read_addr_ptr(dev); + ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl); +- if (ret) ++ if (ret) { ++ dev_err(dev, "failed to get pinctrl device %d\n", ret); + return ret; ++ } ++ ++ pctrl_priv = dev_get_priv(priv->pinctrl); ++ if (!pctrl_priv) { ++ dev_err(dev, "failed to get pinctrl priv\n"); ++ return -EINVAL; ++ } + +- uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK; + end = strrchr(dev->name, '@'); +- priv->bank = trailing_strtoln(dev->name, end); +- priv->name[0] = 'A' + priv->bank; +- uc_priv->bank_name = priv->name; ++ if (end) ++ id = trailing_strtoln(dev->name, end); ++ else ++ dev_read_alias_seq(dev, &id); ++ ++ if (id < 0) ++ id = gpio++; ++ ++ if (id >= pctrl_priv->ctrl->nr_banks) { ++ dev_err(dev, "bank id invalid\n"); ++ return -EINVAL; ++ } ++ ++ bank = &pctrl_priv->ctrl->pin_banks[id]; ++ if (bank->bank_num != id) { ++ dev_err(dev, "bank id mismatch with pinctrl\n"); ++ return -EINVAL; ++ } ++ ++ priv->bank = bank->bank_num; ++ uc_priv->gpio_count = bank->nr_pins; ++ uc_priv->gpio_base = bank->pin_base; ++ uc_priv->bank_name = bank->name; + + return 0; + } +--- a/drivers/pinctrl/rockchip/Makefile ++++ b/drivers/pinctrl/rockchip/Makefile +@@ -14,4 +14,5 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl + obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o + obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o + obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o ++obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o + obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o +--- /dev/null ++++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c +@@ -0,0 +1,360 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2020 Rockchip Electronics Co., Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "pinctrl-rockchip.h" ++ ++static struct rockchip_mux_route_data rk3568_mux_route_data[] = { ++ MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ ++ MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */ ++ MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */ ++ MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ ++ MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */ ++ MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */ ++ MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */ ++ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */ ++}; ++ ++static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) ++{ ++ struct rockchip_pinctrl_priv *priv = bank->priv; ++ int iomux_num = (pin / 8); ++ struct regmap *regmap; ++ int reg, ret, mask; ++ u8 bit; ++ u32 data; ++ ++ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); ++ ++ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ++ regmap = priv->regmap_pmu; ++ else ++ regmap = priv->regmap_base; ++ ++ reg = bank->iomux[iomux_num].offset; ++ if ((pin % 8) >= 4) ++ reg += 0x4; ++ bit = (pin % 4) * 4; ++ mask = 0xf; ++ ++ data = (mask << (bit + 16)); ++ data |= (mux & mask) << bit; ++ ret = regmap_write(regmap, reg, data); ++ ++ return ret; ++} ++ ++#define RK3568_PULL_PMU_OFFSET 0x20 ++#define RK3568_PULL_GRF_OFFSET 0x80 ++#define RK3568_PULL_BITS_PER_PIN 2 ++#define RK3568_PULL_PINS_PER_REG 8 ++#define RK3568_PULL_BANK_STRIDE 0x10 ++ ++static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl_priv *info = bank->priv; ++ ++ if (bank->bank_num == 0) { ++ *regmap = info->regmap_pmu; ++ *reg = RK3568_PULL_PMU_OFFSET; ++ *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; ++ } else { ++ *regmap = info->regmap_base; ++ *reg = RK3568_PULL_GRF_OFFSET; ++ *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; ++ } ++ ++ *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); ++ *bit = (pin_num % RK3568_PULL_PINS_PER_REG); ++ *bit *= RK3568_PULL_BITS_PER_PIN; ++} ++ ++#define RK3568_DRV_PMU_OFFSET 0x70 ++#define RK3568_DRV_GRF_OFFSET 0x200 ++#define RK3568_DRV_BITS_PER_PIN 8 ++#define RK3568_DRV_PINS_PER_REG 2 ++#define RK3568_DRV_BANK_STRIDE 0x40 ++ ++static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl_priv *info = bank->priv; ++ ++ /* The first 32 pins of the first bank are located in PMU */ ++ if (bank->bank_num == 0) { ++ *regmap = info->regmap_pmu; ++ *reg = RK3568_DRV_PMU_OFFSET; ++ } else { ++ *regmap = info->regmap_base; ++ *reg = RK3568_DRV_GRF_OFFSET; ++ *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; ++ } ++ ++ *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); ++ *bit = (pin_num % RK3568_DRV_PINS_PER_REG); ++ *bit *= RK3568_DRV_BITS_PER_PIN; ++} ++ ++#define RK3568_SCHMITT_BITS_PER_PIN 2 ++#define RK3568_SCHMITT_PINS_PER_REG 8 ++#define RK3568_SCHMITT_BANK_STRIDE 0x10 ++#define RK3568_SCHMITT_GRF_OFFSET 0xc0 ++#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 ++ ++static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl_priv *info = bank->priv; ++ ++ if (bank->bank_num == 0) { ++ *regmap = info->regmap_pmu; ++ *reg = RK3568_SCHMITT_PMUGRF_OFFSET; ++ } else { ++ *regmap = info->regmap_base; ++ *reg = RK3568_SCHMITT_GRF_OFFSET; ++ *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; ++ } ++ ++ *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); ++ *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; ++ *bit *= RK3568_SCHMITT_BITS_PER_PIN; ++ ++ return 0; ++} ++ ++static int rk3568_set_pull(struct rockchip_pin_bank *bank, ++ int pin_num, int pull) ++{ ++ struct regmap *regmap; ++ int reg, ret; ++ u8 bit, type; ++ u32 data; ++ ++ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) ++ return -ENOTSUPP; ++ ++ rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); ++ type = bank->pull_type[pin_num / 8]; ++ ret = rockchip_translate_pull_value(type, pull); ++ if (ret < 0) { ++ debug("unsupported pull setting %d\n", pull); ++ return ret; ++ } ++ ++ /* enable the write to the equivalent lower bits */ ++ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); ++ ++ data |= (ret << bit); ++ ret = regmap_write(regmap, reg, data); ++ ++ return ret; ++} ++ ++static int rk3568_set_drive(struct rockchip_pin_bank *bank, ++ int pin_num, int strength) ++{ ++ struct regmap *regmap; ++ int reg; ++ u32 data; ++ u8 bit; ++ int drv = (1 << (strength + 1)) - 1; ++ int ret = 0; ++ ++ rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); ++ ++ /* enable the write to the equivalent lower bits */ ++ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16); ++ data |= (drv << bit); ++ ++ ret = regmap_write(regmap, reg, data); ++ if (ret) ++ return ret; ++ ++ if (bank->bank_num == 1 && pin_num == 21) ++ reg = 0x0840; ++ else if (bank->bank_num == 2 && pin_num == 2) ++ reg = 0x0844; ++ else if (bank->bank_num == 2 && pin_num == 8) ++ reg = 0x0848; ++ else if (bank->bank_num == 3 && pin_num == 0) ++ reg = 0x084c; ++ else if (bank->bank_num == 3 && pin_num == 6) ++ reg = 0x0850; ++ else if (bank->bank_num == 4 && pin_num == 0) ++ reg = 0x0854; ++ else ++ return 0; ++ ++ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16; ++ data |= drv; ++ ++ return regmap_write(regmap, reg, data); ++} ++ ++static int rk3568_set_schmitt(struct rockchip_pin_bank *bank, ++ int pin_num, int enable) ++{ ++ struct regmap *regmap; ++ int reg; ++ u32 data; ++ u8 bit; ++ ++ rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); ++ ++ /* enable the write to the equivalent lower bits */ ++ data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); ++ data |= (enable << bit); ++ ++ return regmap_write(regmap, reg, data); ++} ++static struct rockchip_pin_bank rk3568_pin_banks[] = { ++ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, ++ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, ++ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, ++ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), ++ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT), ++ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT), ++ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT), ++ PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT), ++}; ++ ++static const struct rockchip_pin_ctrl rk3568_pin_ctrl = { ++ .pin_banks = rk3568_pin_banks, ++ .nr_banks = ARRAY_SIZE(rk3568_pin_banks), ++ .nr_pins = 160, ++ .grf_mux_offset = 0x0, ++ .pmu_mux_offset = 0x0, ++ .iomux_routes = rk3568_mux_route_data, ++ .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), ++ .set_mux = rk3568_set_mux, ++ .set_pull = rk3568_set_pull, ++ .set_drive = rk3568_set_drive, ++ .set_schmitt = rk3568_set_schmitt, ++}; ++ ++static const struct udevice_id rk3568_pinctrl_ids[] = { ++ { ++ .compatible = "rockchip,rk3568-pinctrl", ++ .data = (ulong)&rk3568_pin_ctrl ++ }, ++ { } ++}; ++ ++U_BOOT_DRIVER(pinctrl_rk3568) = { ++ .name = "rockchip_rk3568_pinctrl", ++ .id = UCLASS_PINCTRL, ++ .of_match = rk3568_pinctrl_ids, ++ .priv_auto = sizeof(struct rockchip_pinctrl_priv), ++ .ops = &rockchip_pinctrl_ops, ++#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++ .bind = dm_scan_fdt_dev, ++#endif ++ .probe = rockchip_pinctrl_probe, ++}; +--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c ++++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +@@ -400,7 +400,7 @@ static int rockchip_pinctrl_set_state(st + int prop_len, param; + const u32 *data; + ofnode node; +-#ifdef CONFIG_OF_LIVE ++#if CONFIG_IS_ENABLED(OF_LIVE) + const struct device_node *np; + struct property *pp; + #else +@@ -440,7 +440,7 @@ static int rockchip_pinctrl_set_state(st + node = ofnode_get_by_phandle(conf); + if (!ofnode_valid(node)) + return -ENODEV; +-#ifdef CONFIG_OF_LIVE ++#if CONFIG_IS_ENABLED(OF_LIVE) + np = ofnode_to_np(node); + for (pp = np->properties; pp; pp = pp->next) { + prop_name = pp->name; +@@ -515,13 +515,14 @@ static struct rockchip_pin_ctrl *rockchi + + /* preset iomux offset value, set new start value */ + if (iom->offset >= 0) { +- if (iom->type & IOMUX_SOURCE_PMU) ++ if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) + pmu_offs = iom->offset; + else + grf_offs = iom->offset; + } else { /* set current iomux offset */ +- iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? +- pmu_offs : grf_offs; ++ iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || ++ (iom->type & IOMUX_L_SOURCE_PMU)) ? ++ pmu_offs : grf_offs; + } + + /* preset drv offset value, set new start value */ +--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h ++++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h +@@ -6,9 +6,13 @@ + #ifndef __DRIVERS_PINCTRL_ROCKCHIP_H + #define __DRIVERS_PINCTRL_ROCKCHIP_H + ++#include + #include + #include + ++#define RK_GENMASK_VAL(h, l, v) \ ++ (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) ++ + /** + * Encode variants of iomux registers into a type variable + */ +@@ -18,6 +22,8 @@ + #define IOMUX_UNROUTED BIT(3) + #define IOMUX_WIDTH_3BIT BIT(4) + #define IOMUX_8WIDTH_2BIT BIT(5) ++#define IOMUX_WRITABLE_32BIT BIT(6) ++#define IOMUX_L_SOURCE_PMU BIT(7) + + /** + * Defined some common pins constants +@@ -63,6 +69,21 @@ enum rockchip_pin_pull_type { + }; + + /** ++ * enum mux route register type, should be invalid/default/topgrf/pmugrf. ++ * INVALID: means do not need to set mux route ++ * DEFAULT: means same regmap as pin iomux ++ * TOPGRF: means mux route setting in topgrf ++ * PMUGRF: means mux route setting in pmugrf ++ */ ++enum rockchip_pin_route_type { ++ ROUTE_TYPE_DEFAULT = 0, ++ ROUTE_TYPE_TOPGRF = 1, ++ ROUTE_TYPE_PMUGRF = 2, ++ ++ ROUTE_TYPE_INVALID = -1, ++}; ++ ++/** + * @drv_type: drive strength variant using rockchip_perpin_drv_type + * @offset: if initialized to -1 it will be autocalculated, by specifying + * an initial offset value the relevant source offset can be reset +@@ -220,6 +241,25 @@ struct rockchip_pin_bank { + .pull_type[3] = pull3, \ + } + ++#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ ++ { \ ++ .bank_num = ID, \ ++ .pin = PIN, \ ++ .func = FUNC, \ ++ .route_offset = REG, \ ++ .route_val = VAL, \ ++ .route_type = FLAG, \ ++ } ++ ++#define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ ++ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT) ++ ++#define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ ++ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF) ++ ++#define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ ++ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF) ++ + /** + * struct rockchip_mux_recalced_data: recalculate a pin iomux data. + * @num: bank number. +@@ -241,6 +281,7 @@ struct rockchip_mux_recalced_data { + * @bank_num: bank number. + * @pin: index at register or used to calc index. + * @func: the min pin. ++ * @route_type: the register type. + * @route_offset: the max pin. + * @route_val: the register offset. + */ +@@ -248,6 +289,7 @@ struct rockchip_mux_route_data { + u8 bank_num; + u8 pin; + u8 func; ++ enum rockchip_pin_route_type route_type : 8; + u32 route_offset; + u32 route_val; + }; diff --git a/package/boot/uboot-rockchip/patches/108-hack-fix-build-rk356x-idbloader.patch b/package/boot/uboot-rockchip/patches/108-hack-fix-build-rk356x-idbloader.patch new file mode 100644 index 0000000000..b63c3fbd0d --- /dev/null +++ b/package/boot/uboot-rockchip/patches/108-hack-fix-build-rk356x-idbloader.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/dts/rockchip-u-boot.dtsi ++++ b/arch/arm/dts/rockchip-u-boot.dtsi +@@ -20,7 +20,7 @@ + mkimage { + filename = "idbloader.img"; + args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; +-#ifdef CONFIG_TPL ++#if defined(CONFIG_TPL) || defined(CONFIG_ROCKCHIP_RK3566) || defined(CONFIG_ROCKCHIP_RK3568) + multiple-data-files; + + u-boot-tpl { diff --git a/package/boot/uboot-rockchip/patches/100-arm-add-dts-files.patch b/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch similarity index 100% rename from package/boot/uboot-rockchip/patches/100-arm-add-dts-files.patch rename to package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch