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rockchip: add support for FriendlyARM NanoPi R2S

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Instruction:
- LAN: rtl8153
- WAN: rtl8211E

Signed-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
This commit is contained in:
Jayantajit Gogoi 2020-06-24 03:37:23 +00:00 committed by AmadeusGhost
parent 1544c2246e
commit 767914185d
13 changed files with 4204 additions and 15 deletions
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9
package/boot/uboot-rockchip/Makefile
View File

@ -21,6 +21,14 @@ define U-Boot/Default
HIDDEN:=1
endef
define U-Boot/nanopi-r2s-rk3328
BUILD_SUBTARGET:=armv8
NAME:=NanoPi R2S
BUILD_DEVICES:= \
friendlyarm_nanopi-r2s
BL31=$(STAGING_DIR_IMAGE)/rk3328_bl31.elf
endef
define U-Boot/rock-pi-e-rk3328
BUILD_SUBTARGET:=armv8
NAME:=Rock Pi E
@ -38,6 +46,7 @@ define U-Boot/rockpro64-rk3399
endef
UBOOT_TARGETS := \
nanopi-r2s-rk3328 \
rock-pi-e-rk3328 \
rockpro64-rk3399

792
package/boot/uboot-rockchip/patches/005-add-support-nanopi-r2s.patch Normal file
View File

@ -0,0 +1,792 @@
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0127a91a..c5beaa85 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -104,7 +104,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
+ rk3328-nanopi-r2s.dtb \
rk3328-rock64.dtb \
rk3328-rock-pi-e.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
diff --git a/arch/arm/dts/rk3328-nanopi-r2-common.dtsi b/arch/arm/dts/rk3328-nanopi-r2-common.dtsi
new file mode 100644
index 00000000..bc924346
--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2-common.dtsi
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+/*#include "rk3328-dram-default-timing.dtsi"*/
+#include "rk3328.dtsi"
+
+/ {
+ model = "FriendlyARM boards based on Rockchip RK3328";
+ compatible = "friendlyarm,nanopi-r2", "rockchip,rk3328";
+
+ aliases {
+/* ethernet1 = &r8153;*/
+ };
+
+ chosen {
+ bootargs = "swiotlb=1 coherent_pool=1m consoleblank=0";
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 =<&leds_gpio>;
+ status = "disabled";
+
+ status {
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ label = "nanopi:red:status";
+ linux,default-trigger = "heartbeat";
+ linux,default-trigger-delay-ms = <0>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk805 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+
+/* sdmmc_ext: dwmmc@ff5f0000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };*/
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vccio_sd: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ regulator-name = "vccio_sd";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc_io>;
+ startup-delay-us = <2000>;
+ regulator-settling-time-us = <5000>;
+ enable-active-high;
+ status = "disabled";
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_host_vbus: host-vbus-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_host_vbus";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ dfi: dfi@ff790000 {
+ reg = <0x00 0xff790000 0x00 0x400>;
+ compatible = "rockchip,rk3328-dfi";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+/* dmc: dmc {
+ compatible = "rockchip,rk3328-dmc";
+ devfreq-events = <&dfi>;
+ clocks = <&cru SCLK_DDRCLK>;
+ clock-names = "dmc_clk";
+ operating-points-v2 = <&dmc_opp_table>;
+ ddr_timing = <&ddr_timing>;
+ upthreshold = <40>;
+ downdifferential = <20>;
+ auto-min-freq = <786000>;
+ auto-freq-en = <0>;
+ #cooling-cells = <2>;
+ status = "disabled";
+
+ ddr_power_model: ddr_power_model {
+ compatible = "ddr_power_model";
+ dynamic-power-coefficient = <120>;
+ static-power-coefficient = <200>;
+ ts = <32000 4700 (-80) 2>;
+ thermal-zone = "soc-thermal";
+ };
+ };
+
+ dmc_opp_table: dmc-opp-table {
+ compatible = "operating-points-v2";
+
+ rockchip,leakage-voltage-sel = <
+ 1 10 0
+ 11 254 1
+ >;
+ nvmem-cells = <&logic_leakage>;
+ nvmem-cell-names = "ddr_leakage";
+
+ opp-786000000 {
+ opp-hz = /bits/ 64 <786000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-798000000 {
+ opp-hz = /bits/ 64 <798000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-840000000 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-924000000 {
+ opp-hz = /bits/ 64 <924000000>;
+ opp-microvolt = <1100000>;
+ opp-microvolt-L0 = <1100000>;
+ opp-microvolt-L1 = <1075000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1175000>;
+ opp-microvolt-L0 = <1175000>;
+ opp-microvolt-L1 = <1150000>;
+ };
+ };
+*/};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&dfi {
+ status = "okay";
+};
+
+/*&dmc {
+ center-supply = <&vdd_logic>;
+ status = "okay";
+};*/
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-hs200-1_8v;
+ no-sd;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_emmc>;
+ status = "okay";
+};
+
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ status = "disabled";
+};
+
+&gmac2io {
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ phy-handle = <&rtl8211e>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_phy>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 30000>;
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,aal;
+ snps,rxpbl = <0x4>;
+ snps,txpbl = <0x4>;
+ tx_delay = <0x24>;
+ rx_delay = <0x18>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtl8211e: phy@0 {
+ reg = <0>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ /* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_io>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-init-microvolt = <1075000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-init-microvolt = <1225000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_io>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_18>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0 {
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
+ };
+
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_dectn: sdmmc0-dectn {
+ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ <1 RK_PA0 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA1 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA2 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA3 1 &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0ext {
+ sdmmc0ext_clk: sdmmc0ext-clk {
+ rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_2ma>;
+ };
+
+ sdmmc0ext_cmd: sdmmc0ext-cmd {
+ rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_2ma>;
+ };
+
+ sdmmc0ext_bus4: sdmmc0ext-bus4 {
+ rockchip,pins =
+ <3 RK_PA4 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA5 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA6 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA7 3 &pcfg_pull_up_2ma>;
+ };
+ };
+
+ gmac-1 {
+ rgmiim1_pins: rgmiim1-pins {
+ rockchip,pins =
+ /* mac_txclk */
+ <1 RK_PB4 2 &pcfg_pull_none_4ma>,
+ /* mac_rxclk */
+ <1 RK_PB5 2 &pcfg_pull_none>,
+ /* mac_mdio */
+ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
+ /* mac_txen */
+ <1 RK_PD1 2 &pcfg_pull_none_4ma>,
+ /* mac_clk */
+ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
+ /* mac_rxdv */
+ <1 RK_PC6 2 &pcfg_pull_none>,
+ /* mac_mdc */
+ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
+ /* mac_rxd1 */
+ <1 RK_PB2 2 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <1 RK_PB3 2 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <1 RK_PB0 2 &pcfg_pull_none_4ma>,
+ /* mac_txd0 */
+ <1 RK_PB1 2 &pcfg_pull_none_4ma>,
+ /* mac_rxd3 */
+ <1 RK_PB6 2 &pcfg_pull_none>,
+ /* mac_rxd2 */
+ <1 RK_PB7 2 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <1 RK_PC0 2 &pcfg_pull_none_4ma>,
+ /* mac_txd2 */
+ <1 RK_PC1 2 &pcfg_pull_none_4ma>,
+
+ /* mac_txclk */
+ <0 RK_PB0 1 &pcfg_pull_none>,
+ /* mac_txen */
+ <0 RK_PB4 1 &pcfg_pull_none>,
+ /* mac_clk */
+ <0 RK_PD0 1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <0 RK_PC0 1 &pcfg_pull_none>,
+ /* mac_txd0 */
+ <0 RK_PC1 1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <0 RK_PC7 1 &pcfg_pull_none>,
+ /* mac_txd2 */
+ <0 RK_PC6 1 &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gpio-leds {
+ leds_gpio: leds-gpio {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+/*&sdmmc_ext {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <100000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>;
+ rockchip,default-sample-phase = <120>;
+ supports-sdio;
+ sd-uhs-sdr104;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD2 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+};*/
+
+/*&tsadc {
+ status = "okay";
+};*/
+
+&uart2 {
+ status = "okay";
+};
+
+/*&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&u3phy {
+ vbus-supply = <&vcc_host_vbus>;
+ status = "okay";
+};
+
+&u3phy_utmi {
+ status = "okay";
+};
+
+&u3phy_pipe {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ r8153: device@2 {
+ compatible = "usbbda:8153";
+ reg = <2>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
+};*/
diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts
new file mode 100644
index 00000000..c3313bdc
--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2s.dts
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3328-nanopi-r2-common.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi R2S";
+ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_key1>;
+
+ reset {
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ linux,input-type = <1>;
+ gpio-key,wakeup = <1>;
+ debounce-interval = <100>;
+ };
+ };
+
+ vcc_rtl8153: vcc-rtl8153-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb30_en_drv>;
+ regulator-always-on;
+ regulator-name = "vcc_rtl8153";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ off-on-delay-us = <5000>;
+ enable-active-high;
+ };
+};
+
+&emmc {
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&leds {
+ status = "okay";
+
+ lan {
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ label = "nanopi:green:lan";
+ };
+
+ wan {
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+ label = "nanopi:green:wan";
+ };
+};
+
+&leds_gpio {
+ rockchip,pins =
+ <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+/*&pwm2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-1 = <&pwm2_sleep_pin>;
+ status = "okay";
+};*/
+
+&rk805 {
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&vccio_sd {
+ status = "okay";
+};
+
+&io_domains {
+ vccio3-supply = <&vccio_sd>;
+};
+
+&sdmmc {
+ vqmmc-supply = <&vccio_sd>;
+ max-frequency = <150000000>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+/*&sdmmc_ext {
+ status = "disabled";
+};*/
+
+&sdio_pwrseq {
+ status = "disabled";
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pwm {
+ pwm2_sleep_pin: pwm2-sleep-pin {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+ };
+
+ rockchip-key {
+ gpio_key1: gpio-key1 {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb30_en_drv: usb30-en-drv {
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 060c84e6..eac257b0 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -1386,7 +1386,7 @@
};
};
- gmac2phy {
+ gmac2phy: gmac2phy {
fephyled_speed100: fephyled-speed100 {
rockchip,pins =
<0 31 RK_FUNC_1 &pcfg_pull_none>;

149
package/boot/uboot-rockchip/patches/006-add-support-nanopi-r2s-defconfig.patch Normal file
View File

@ -0,0 +1,149 @@
diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
new file mode 100644
index 00000000..cf3452ea
--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr4-666.dtsi"
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+ };
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+};
+
+&sdmmc0m1_gpio {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_up_4ma {
+ u-boot,dm-spl;
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+&vcc_sd {
+ u-boot,dm-spl;
+};
diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
new file mode 100644
index 00000000..720b5e04
--- /dev/null
+++ b/configs/nanopi-r2s-rk3328_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SMBIOS_PRODUCT_NAME="nanopi-r2s_rk3328"
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
+CONFIG_SMBIOS_MANUFACTURER="friendlyarm"

16
package/boot/uboot-rockchip/patches/009-add-set-eth1-addr.patch Normal file
View File

@ -0,0 +1,16 @@
diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c
index 6dbb9bde..89f3a918 100644
--- a/arch/arm/mach-rockchip/misc.c
+++ b/arch/arm/mach-rockchip/misc.c
@@ -50,6 +50,11 @@ int rockchip_setup_macaddr(void)
mac_addr[0] &= 0xfe; /* clear multicast bit */
mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
eth_env_set_enetaddr("ethaddr", mac_addr);
+
+ /* Make a valid MAC address for eth1 too */
+ mac_addr[5] += 0x20;
+ mac_addr[5] &= 0xff;
+ eth_env_set_enetaddr("eth1addr", mac_addr);
#endif
return 0;
}

18
target/linux/rockchip/armv8/base-files/etc/board.d/01_leds Executable file
View File

@ -0,0 +1,18 @@
#!/bin/sh
#
# Copyright © 2017 OpenWrt.org
#
. /lib/functions/uci-defaults.sh
board_config_update
case "$(board_name)" in
friendlyarm,nanopi-r2s)
ucidef_set_led_netdev "wan" "WAN" "nanopi:green:wan" "eth0"
ucidef_set_led_netdev "lan" "LAN" "nanopi:green:lan" "eth1"
;;
esac
board_config_flush
exit 0

3
target/linux/rockchip/armv8/base-files/etc/board.d/02_network
View File

@ -5,6 +5,9 @@
board_config_update
case "$(board_name)" in
friendlyarm,nanopi-r2s)
ucidef_set_interfaces_lan_wan "eth1" "eth0"
;;
radxa,rock-pi-e)
ucidef_set_interfaces_lan_wan "eth1" "eth0"
;;

19
target/linux/rockchip/armv8/config-5.4
View File

@ -410,6 +410,7 @@ CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK808=y
CONFIG_RELOCATABLE=y
@ -567,18 +568,6 @@ CONFIG_ZLIB_INFLATE=y
CONFIG_ARM64_CRYPTO=y
CONFIG_ARM_ROCKCHIP_CPUFREQ=y
CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_REGULATOR_GPIO=y
CONFIG_ARM_RK3328_DMC_DEVFREQ=y
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y

10
target/linux/rockchip/image/armv8.mk
View File

@ -4,6 +4,16 @@
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
define Device/friendlyarm_nanopi-r2s
DEVICE_VENDOR := FriendlyARM
DEVICE_MODEL := NanoPi R2S
SOC := rk3328
UBOOT_DEVICE_NAME := nanopi-r2s-rk3328
IMAGE/sysupgrade.img.gz := boot-common | boot-script | sdcard-img | gzip | append-metadata
DEVICE_PACKAGES += kmod-phy-realtek kmod-usb-net kmod-usb-net-rtl8152 kmod-macvlan
endef
TARGET_DEVICES += friendlyarm_nanopi-r2s
define Device/radxa_rock-pi-e
DEVICE_VENDOR := Radxa
DEVICE_MODEL := Rock Pi E

1796
target/linux/rockchip/patches-5.4/001-add-rk3328-dmc-driver.patch Normal file
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File diff suppressed because it is too large Load Diff

780
target/linux/rockchip/patches-5.4/003-add-nanopi-r2s-support.patch Normal file
View File

@ -0,0 +1,780 @@
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 92d796a33..24a6c304f 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi
new file mode 100644
index 000000000..36890bb7f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3328-dram-default-timing.dtsi"
+#include "rk3328.dtsi"
+
+/ {
+ model = "FriendlyARM boards based on Rockchip RK3328";
+ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
+
+ aliases {
+ ethernet1 = &r8153;
+ };
+
+ chosen {
+ bootargs = "swiotlb=1 coherent_pool=1m consoleblank=0";
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 =<&leds_gpio>;
+ status = "disabled";
+
+ status {
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ label = "nanopi:red:status";
+ linux,default-trigger = "heartbeat";
+ linux,default-trigger-delay-ms = <0>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk805 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vccio_sd: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ regulator-name = "vccio_sd";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc_io>;
+ startup-delay-us = <2000>;
+ regulator-settling-time-us = <5000>;
+ enable-active-high;
+ status = "disabled";
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_host_vbus: host-vbus-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_host_vbus";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ dfi: dfi@ff790000 {
+ reg = <0x00 0xff790000 0x00 0x400>;
+ compatible = "rockchip,rk3328-dfi";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ dmc: dmc {
+ compatible = "rockchip,rk3328-dmc";
+ devfreq-events = <&dfi>;
+ clocks = <&cru SCLK_DDRCLK>;
+ clock-names = "dmc_clk";
+ operating-points-v2 = <&dmc_opp_table>;
+ ddr_timing = <&ddr_timing>;
+ upthreshold = <40>;
+ downdifferential = <20>;
+ auto-min-freq = <786000>;
+ auto-freq-en = <0>;
+ #cooling-cells = <2>;
+ status = "disabled";
+
+ ddr_power_model: ddr_power_model {
+ compatible = "ddr_power_model";
+ dynamic-power-coefficient = <120>;
+ static-power-coefficient = <200>;
+ ts = <32000 4700 (-80) 2>;
+ thermal-zone = "soc-thermal";
+ };
+ };
+
+ dmc_opp_table: dmc-opp-table {
+ compatible = "operating-points-v2";
+
+ rockchip,leakage-voltage-sel = <
+ 1 10 0
+ 11 254 1
+ >;
+ nvmem-cells = <&logic_leakage>;
+ nvmem-cell-names = "ddr_leakage";
+
+ opp-786000000 {
+ opp-hz = /bits/ 64 <786000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-798000000 {
+ opp-hz = /bits/ 64 <798000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-840000000 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-924000000 {
+ opp-hz = /bits/ 64 <924000000>;
+ opp-microvolt = <1100000>;
+ opp-microvolt-L0 = <1100000>;
+ opp-microvolt-L1 = <1075000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1175000>;
+ opp-microvolt-L0 = <1175000>;
+ opp-microvolt-L1 = <1150000>;
+ };
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ center-supply = <&vdd_logic>;
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-hs200-1_8v;
+ no-sd;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_emmc>;
+ status = "okay";
+};
+
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ status = "disabled";
+};
+
+&gmac2io {
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ phy-handle = <&rtl8211e>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_phy>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 30000>;
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,aal;
+ snps,rxpbl = <0x4>;
+ snps,txpbl = <0x4>;
+ tx_delay = <0x24>;
+ rx_delay = <0x18>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtl8211e: phy@0 {
+ reg = <0>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ /* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_io>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-init-microvolt = <1075000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-init-microvolt = <1225000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_io>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_18>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0 {
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
+ };
+
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_dectn: sdmmc0-dectn {
+ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ <1 RK_PA0 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA1 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA2 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA3 1 &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0ext {
+ sdmmc0ext_clk: sdmmc0ext-clk {
+ rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_2ma>;
+ };
+
+ sdmmc0ext_cmd: sdmmc0ext-cmd {
+ rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_2ma>;
+ };
+
+ sdmmc0ext_bus4: sdmmc0ext-bus4 {
+ rockchip,pins =
+ <3 RK_PA4 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA5 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA6 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA7 3 &pcfg_pull_up_2ma>;
+ };
+ };
+
+ gmac-1 {
+ rgmiim1_pins: rgmiim1-pins {
+ rockchip,pins =
+ /* mac_txclk */
+ <1 RK_PB4 2 &pcfg_pull_none_4ma>,
+ /* mac_rxclk */
+ <1 RK_PB5 2 &pcfg_pull_none>,
+ /* mac_mdio */
+ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
+ /* mac_txen */
+ <1 RK_PD1 2 &pcfg_pull_none_4ma>,
+ /* mac_clk */
+ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
+ /* mac_rxdv */
+ <1 RK_PC6 2 &pcfg_pull_none>,
+ /* mac_mdc */
+ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
+ /* mac_rxd1 */
+ <1 RK_PB2 2 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <1 RK_PB3 2 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <1 RK_PB0 2 &pcfg_pull_none_4ma>,
+ /* mac_txd0 */
+ <1 RK_PB1 2 &pcfg_pull_none_4ma>,
+ /* mac_rxd3 */
+ <1 RK_PB6 2 &pcfg_pull_none>,
+ /* mac_rxd2 */
+ <1 RK_PB7 2 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <1 RK_PC0 2 &pcfg_pull_none_4ma>,
+ /* mac_txd2 */
+ <1 RK_PC1 2 &pcfg_pull_none_4ma>,
+
+ /* mac_txclk */
+ <0 RK_PB0 1 &pcfg_pull_none>,
+ /* mac_txen */
+ <0 RK_PB4 1 &pcfg_pull_none>,
+ /* mac_clk */
+ <0 RK_PD0 1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <0 RK_PC0 1 &pcfg_pull_none>,
+ /* mac_txd0 */
+ <0 RK_PC1 1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <0 RK_PC7 1 &pcfg_pull_none>,
+ /* mac_txd2 */
+ <0 RK_PC6 1 &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gpio-leds {
+ leds_gpio: leds-gpio {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&sdmmc_ext {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <100000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>;
+ rockchip,default-sample-phase = <120>;
+ supports-sdio;
+ sd-uhs-sdr104;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD2 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&u3phy {
+ vbus-supply = <&vcc_host_vbus>;
+ status = "okay";
+};
+
+&u3phy_utmi {
+ status = "okay";
+};
+
+&u3phy_pipe {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ r8153: device@2 {
+ compatible = "usbbda:8153";
+ reg = <2>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
new file mode 100644
index 000000000..971397659
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3328-nanopi-r2-common.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi R2S";
+ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_key1>;
+
+ reset {
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ linux,input-type = <1>;
+ gpio-key,wakeup = <1>;
+ debounce-interval = <100>;
+ };
+ };
+
+ vcc_rtl8153: vcc-rtl8153-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb30_en_drv>;
+ regulator-always-on;
+ regulator-name = "vcc_rtl8153";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ off-on-delay-us = <5000>;
+ enable-active-high;
+ };
+};
+
+&emmc {
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&leds {
+ status = "okay";
+
+ lan {
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ label = "nanopi:green:lan";
+ };
+
+ wan {
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+ label = "nanopi:green:wan";
+ };
+};
+
+&leds_gpio {
+ rockchip,pins =
+ <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+&pwm2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-1 = <&pwm2_sleep_pin>;
+ status = "okay";
+};
+
+&rk805 {
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&vccio_sd {
+ status = "okay";
+};
+
+&io_domains {
+ vccio3-supply = <&vccio_sd>;
+};
+
+&sdmmc {
+ vqmmc-supply = <&vccio_sd>;
+ max-frequency = <150000000>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc_ext {
+ status = "disabled";
+};
+
+&sdio_pwrseq {
+ status = "disabled";
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pwm {
+ pwm2_sleep_pin: pwm2-sleep-pin {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+ };
+
+ rockchip-key {
+ gpio_key1: gpio-key1 {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb30_en_drv: usb30-en-drv {
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};

551
target/linux/rockchip/patches-5.4/003-nanopi-r2s-kernel-patches.patch Normal file
View File

@ -0,0 +1,551 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi
new file mode 100644
index 000000000..a3f5ff4bd
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi
@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <dt-bindings/clock/rockchip-ddr.h>
+#include <dt-bindings/memory/rk3328-dram.h>
+
+/ {
+ ddr_timing: ddr_timing {
+ compatible = "rockchip,ddr-timing";
+ ddr3_speed_bin = <DDR3_DEFAULT>;
+ ddr4_speed_bin = <DDR4_DEFAULT>;
+ pd_idle = <0>;
+ sr_idle = <0>;
+ sr_mc_gate_idle = <0>;
+ srpd_lite_idle = <0>;
+ standby_idle = <0>;
+
+ auto_pd_dis_freq = <1066>;
+ auto_sr_dis_freq = <800>;
+ ddr3_dll_dis_freq = <300>;
+ ddr4_dll_dis_freq = <625>;
+ phy_dll_dis_freq = <400>;
+
+ ddr3_odt_dis_freq = <100>;
+ phy_ddr3_odt_dis_freq = <100>;
+ ddr3_drv = <DDR3_DS_40ohm>;
+ ddr3_odt = <DDR3_ODT_120ohm>;
+ phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
+ phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
+ phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
+ phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
+
+ lpddr3_odt_dis_freq = <666>;
+ phy_lpddr3_odt_dis_freq = <666>;
+ lpddr3_drv = <LP3_DS_40ohm>;
+ lpddr3_odt = <LP3_ODT_240ohm>;
+ phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+ phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
+ phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+ phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
+
+ lpddr4_odt_dis_freq = <800>;
+ phy_lpddr4_odt_dis_freq = <800>;
+ lpddr4_drv = <LP4_PDDS_60ohm>;
+ lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
+ lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
+ phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
+ phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
+ phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
+ phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
+
+ ddr4_odt_dis_freq = <666>;
+ phy_ddr4_odt_dis_freq = <666>;
+ ddr4_drv = <DDR4_DS_34ohm>;
+ ddr4_odt = <DDR4_RTT_NOM_240ohm>;
+ phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+ phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
+ phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+ phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
+
+ /* CA de-skew, one step is 47.8ps, range 0-15 */
+ ddr3a1_ddr4a9_de-skew = <7>;
+ ddr3a0_ddr4a10_de-skew = <7>;
+ ddr3a3_ddr4a6_de-skew = <8>;
+ ddr3a2_ddr4a4_de-skew = <8>;
+ ddr3a5_ddr4a8_de-skew = <7>;
+ ddr3a4_ddr4a5_de-skew = <9>;
+ ddr3a7_ddr4a11_de-skew = <7>;
+ ddr3a6_ddr4a7_de-skew = <9>;
+ ddr3a9_ddr4a0_de-skew = <8>;
+ ddr3a8_ddr4a13_de-skew = <7>;
+ ddr3a11_ddr4a3_de-skew = <9>;
+ ddr3a10_ddr4cs0_de-skew = <7>;
+ ddr3a13_ddr4a2_de-skew = <8>;
+ ddr3a12_ddr4ba1_de-skew = <7>;
+ ddr3a15_ddr4odt0_de-skew = <7>;
+ ddr3a14_ddr4a1_de-skew = <8>;
+ ddr3ba1_ddr4a15_de-skew = <7>;
+ ddr3ba0_ddr4bg0_de-skew = <7>;
+ ddr3ras_ddr4cke_de-skew = <7>;
+ ddr3ba2_ddr4ba0_de-skew = <8>;
+ ddr3we_ddr4bg1_de-skew = <8>;
+ ddr3cas_ddr4a12_de-skew = <7>;
+ ddr3ckn_ddr4ckn_de-skew = <8>;
+ ddr3ckp_ddr4ckp_de-skew = <8>;
+ ddr3cke_ddr4a16_de-skew = <8>;
+ ddr3odt0_ddr4a14_de-skew = <7>;
+ ddr3cs0_ddr4act_de-skew = <8>;
+ ddr3reset_ddr4reset_de-skew = <7>;
+ ddr3cs1_ddr4cs1_de-skew = <7>;
+ ddr3odt1_ddr4odt1_de-skew = <7>;
+
+ /* DATA de-skew
+ * RX one step is 25.1ps, range 0-15
+ * TX one step is 47.8ps, range 0-15
+ */
+ cs0_dm0_rx_de-skew = <7>;
+ cs0_dm0_tx_de-skew = <8>;
+ cs0_dq0_rx_de-skew = <7>;
+ cs0_dq0_tx_de-skew = <8>;
+ cs0_dq1_rx_de-skew = <7>;
+ cs0_dq1_tx_de-skew = <8>;
+ cs0_dq2_rx_de-skew = <7>;
+ cs0_dq2_tx_de-skew = <8>;
+ cs0_dq3_rx_de-skew = <7>;
+ cs0_dq3_tx_de-skew = <8>;
+ cs0_dq4_rx_de-skew = <7>;
+ cs0_dq4_tx_de-skew = <8>;
+ cs0_dq5_rx_de-skew = <7>;
+ cs0_dq5_tx_de-skew = <8>;
+ cs0_dq6_rx_de-skew = <7>;
+ cs0_dq6_tx_de-skew = <8>;
+ cs0_dq7_rx_de-skew = <7>;
+ cs0_dq7_tx_de-skew = <8>;
+ cs0_dqs0_rx_de-skew = <6>;
+ cs0_dqs0p_tx_de-skew = <9>;
+ cs0_dqs0n_tx_de-skew = <9>;
+
+ cs0_dm1_rx_de-skew = <7>;
+ cs0_dm1_tx_de-skew = <7>;
+ cs0_dq8_rx_de-skew = <7>;
+ cs0_dq8_tx_de-skew = <8>;
+ cs0_dq9_rx_de-skew = <7>;
+ cs0_dq9_tx_de-skew = <7>;
+ cs0_dq10_rx_de-skew = <7>;
+ cs0_dq10_tx_de-skew = <8>;
+ cs0_dq11_rx_de-skew = <7>;
+ cs0_dq11_tx_de-skew = <7>;
+ cs0_dq12_rx_de-skew = <7>;
+ cs0_dq12_tx_de-skew = <8>;
+ cs0_dq13_rx_de-skew = <7>;
+ cs0_dq13_tx_de-skew = <7>;
+ cs0_dq14_rx_de-skew = <7>;
+ cs0_dq14_tx_de-skew = <8>;
+ cs0_dq15_rx_de-skew = <7>;
+ cs0_dq15_tx_de-skew = <7>;
+ cs0_dqs1_rx_de-skew = <7>;
+ cs0_dqs1p_tx_de-skew = <9>;
+ cs0_dqs1n_tx_de-skew = <9>;
+
+ cs0_dm2_rx_de-skew = <7>;
+ cs0_dm2_tx_de-skew = <8>;
+ cs0_dq16_rx_de-skew = <7>;
+ cs0_dq16_tx_de-skew = <8>;
+ cs0_dq17_rx_de-skew = <7>;
+ cs0_dq17_tx_de-skew = <8>;
+ cs0_dq18_rx_de-skew = <7>;
+ cs0_dq18_tx_de-skew = <8>;
+ cs0_dq19_rx_de-skew = <7>;
+ cs0_dq19_tx_de-skew = <8>;
+ cs0_dq20_rx_de-skew = <7>;
+ cs0_dq20_tx_de-skew = <8>;
+ cs0_dq21_rx_de-skew = <7>;
+ cs0_dq21_tx_de-skew = <8>;
+ cs0_dq22_rx_de-skew = <7>;
+ cs0_dq22_tx_de-skew = <8>;
+ cs0_dq23_rx_de-skew = <7>;
+ cs0_dq23_tx_de-skew = <8>;
+ cs0_dqs2_rx_de-skew = <6>;
+ cs0_dqs2p_tx_de-skew = <9>;
+ cs0_dqs2n_tx_de-skew = <9>;
+
+ cs0_dm3_rx_de-skew = <7>;
+ cs0_dm3_tx_de-skew = <7>;
+ cs0_dq24_rx_de-skew = <7>;
+ cs0_dq24_tx_de-skew = <8>;
+ cs0_dq25_rx_de-skew = <7>;
+ cs0_dq25_tx_de-skew = <7>;
+ cs0_dq26_rx_de-skew = <7>;
+ cs0_dq26_tx_de-skew = <7>;
+ cs0_dq27_rx_de-skew = <7>;
+ cs0_dq27_tx_de-skew = <7>;
+ cs0_dq28_rx_de-skew = <7>;
+ cs0_dq28_tx_de-skew = <7>;
+ cs0_dq29_rx_de-skew = <7>;
+ cs0_dq29_tx_de-skew = <7>;
+ cs0_dq30_rx_de-skew = <7>;
+ cs0_dq30_tx_de-skew = <7>;
+ cs0_dq31_rx_de-skew = <7>;
+ cs0_dq31_tx_de-skew = <7>;
+ cs0_dqs3_rx_de-skew = <7>;
+ cs0_dqs3p_tx_de-skew = <9>;
+ cs0_dqs3n_tx_de-skew = <9>;
+
+ cs1_dm0_rx_de-skew = <7>;
+ cs1_dm0_tx_de-skew = <8>;
+ cs1_dq0_rx_de-skew = <7>;
+ cs1_dq0_tx_de-skew = <8>;
+ cs1_dq1_rx_de-skew = <7>;
+ cs1_dq1_tx_de-skew = <8>;
+ cs1_dq2_rx_de-skew = <7>;
+ cs1_dq2_tx_de-skew = <8>;
+ cs1_dq3_rx_de-skew = <7>;
+ cs1_dq3_tx_de-skew = <8>;
+ cs1_dq4_rx_de-skew = <7>;
+ cs1_dq4_tx_de-skew = <8>;
+ cs1_dq5_rx_de-skew = <7>;
+ cs1_dq5_tx_de-skew = <8>;
+ cs1_dq6_rx_de-skew = <7>;
+ cs1_dq6_tx_de-skew = <8>;
+ cs1_dq7_rx_de-skew = <7>;
+ cs1_dq7_tx_de-skew = <8>;
+ cs1_dqs0_rx_de-skew = <6>;
+ cs1_dqs0p_tx_de-skew = <9>;
+ cs1_dqs0n_tx_de-skew = <9>;
+
+ cs1_dm1_rx_de-skew = <7>;
+ cs1_dm1_tx_de-skew = <7>;
+ cs1_dq8_rx_de-skew = <7>;
+ cs1_dq8_tx_de-skew = <8>;
+ cs1_dq9_rx_de-skew = <7>;
+ cs1_dq9_tx_de-skew = <7>;
+ cs1_dq10_rx_de-skew = <7>;
+ cs1_dq10_tx_de-skew = <8>;
+ cs1_dq11_rx_de-skew = <7>;
+ cs1_dq11_tx_de-skew = <7>;
+ cs1_dq12_rx_de-skew = <7>;
+ cs1_dq12_tx_de-skew = <8>;
+ cs1_dq13_rx_de-skew = <7>;
+ cs1_dq13_tx_de-skew = <7>;
+ cs1_dq14_rx_de-skew = <7>;
+ cs1_dq14_tx_de-skew = <8>;
+ cs1_dq15_rx_de-skew = <7>;
+ cs1_dq15_tx_de-skew = <7>;
+ cs1_dqs1_rx_de-skew = <7>;
+ cs1_dqs1p_tx_de-skew = <9>;
+ cs1_dqs1n_tx_de-skew = <9>;
+
+ cs1_dm2_rx_de-skew = <7>;
+ cs1_dm2_tx_de-skew = <8>;
+ cs1_dq16_rx_de-skew = <7>;
+ cs1_dq16_tx_de-skew = <8>;
+ cs1_dq17_rx_de-skew = <7>;
+ cs1_dq17_tx_de-skew = <8>;
+ cs1_dq18_rx_de-skew = <7>;
+ cs1_dq18_tx_de-skew = <8>;
+ cs1_dq19_rx_de-skew = <7>;
+ cs1_dq19_tx_de-skew = <8>;
+ cs1_dq20_rx_de-skew = <7>;
+ cs1_dq20_tx_de-skew = <8>;
+ cs1_dq21_rx_de-skew = <7>;
+ cs1_dq21_tx_de-skew = <8>;
+ cs1_dq22_rx_de-skew = <7>;
+ cs1_dq22_tx_de-skew = <8>;
+ cs1_dq23_rx_de-skew = <7>;
+ cs1_dq23_tx_de-skew = <8>;
+ cs1_dqs2_rx_de-skew = <6>;
+ cs1_dqs2p_tx_de-skew = <9>;
+ cs1_dqs2n_tx_de-skew = <9>;
+
+ cs1_dm3_rx_de-skew = <7>;
+ cs1_dm3_tx_de-skew = <7>;
+ cs1_dq24_rx_de-skew = <7>;
+ cs1_dq24_tx_de-skew = <8>;
+ cs1_dq25_rx_de-skew = <7>;
+ cs1_dq25_tx_de-skew = <7>;
+ cs1_dq26_rx_de-skew = <7>;
+ cs1_dq26_tx_de-skew = <7>;
+ cs1_dq27_rx_de-skew = <7>;
+ cs1_dq27_tx_de-skew = <7>;
+ cs1_dq28_rx_de-skew = <7>;
+ cs1_dq28_tx_de-skew = <7>;
+ cs1_dq29_rx_de-skew = <7>;
+ cs1_dq29_tx_de-skew = <7>;
+ cs1_dq30_rx_de-skew = <7>;
+ cs1_dq30_tx_de-skew = <7>;
+ cs1_dq31_rx_de-skew = <7>;
+ cs1_dq31_tx_de-skew = <7>;
+ cs1_dqs3_rx_de-skew = <7>;
+ cs1_dqs3p_tx_de-skew = <9>;
+ cs1_dqs3n_tx_de-skew = <9>;
+ };
+};
diff --git a/include/dt-bindings/clock/rockchip-ddr.h b/include/dt-bindings/clock/rockchip-ddr.h
new file mode 100644
index 000000000..b065432e7
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip-ddr.h
@@ -0,0 +1,63 @@
+/*
+ *
+ * Copyright (C) 2017 ROCKCHIP, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
+#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
+
+#define DDR2_DEFAULT (0)
+
+#define DDR3_800D (0) /* 5-5-5 */
+#define DDR3_800E (1) /* 6-6-6 */
+#define DDR3_1066E (2) /* 6-6-6 */
+#define DDR3_1066F (3) /* 7-7-7 */
+#define DDR3_1066G (4) /* 8-8-8 */
+#define DDR3_1333F (5) /* 7-7-7 */
+#define DDR3_1333G (6) /* 8-8-8 */
+#define DDR3_1333H (7) /* 9-9-9 */
+#define DDR3_1333J (8) /* 10-10-10 */
+#define DDR3_1600G (9) /* 8-8-8 */
+#define DDR3_1600H (10) /* 9-9-9 */
+#define DDR3_1600J (11) /* 10-10-10 */
+#define DDR3_1600K (12) /* 11-11-11 */
+#define DDR3_1866J (13) /* 10-10-10 */
+#define DDR3_1866K (14) /* 11-11-11 */
+#define DDR3_1866L (15) /* 12-12-12 */
+#define DDR3_1866M (16) /* 13-13-13 */
+#define DDR3_2133K (17) /* 11-11-11 */
+#define DDR3_2133L (18) /* 12-12-12 */
+#define DDR3_2133M (19) /* 13-13-13 */
+#define DDR3_2133N (20) /* 14-14-14 */
+#define DDR3_DEFAULT (21)
+#define DDR_DDR2 (22)
+#define DDR_LPDDR (23)
+#define DDR_LPDDR2 (24)
+
+#define DDR4_1600J (0) /* 10-10-10 */
+#define DDR4_1600K (1) /* 11-11-11 */
+#define DDR4_1600L (2) /* 12-12-12 */
+#define DDR4_1866L (3) /* 12-12-12 */
+#define DDR4_1866M (4) /* 13-13-13 */
+#define DDR4_1866N (5) /* 14-14-14 */
+#define DDR4_2133N (6) /* 14-14-14 */
+#define DDR4_2133P (7) /* 15-15-15 */
+#define DDR4_2133R (8) /* 16-16-16 */
+#define DDR4_2400P (9) /* 15-15-15 */
+#define DDR4_2400R (10) /* 16-16-16 */
+#define DDR4_2400U (11) /* 18-18-18 */
+#define DDR4_DEFAULT (12)
+
+#define PAUSE_CPU_STACK_SIZE 16
+
+#endif
diff --git a/include/dt-bindings/memory/rk3328-dram.h b/include/dt-bindings/memory/rk3328-dram.h
new file mode 100644
index 000000000..171f41c25
--- /dev/null
+++ b/include/dt-bindings/memory/rk3328-dram.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
+#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
+
+#define DDR3_DS_34ohm (34)
+#define DDR3_DS_40ohm (40)
+
+#define DDR3_ODT_DIS (0)
+#define DDR3_ODT_40ohm (40)
+#define DDR3_ODT_60ohm (60)
+#define DDR3_ODT_120ohm (120)
+
+#define LP2_DS_34ohm (34)
+#define LP2_DS_40ohm (40)
+#define LP2_DS_48ohm (48)
+#define LP2_DS_60ohm (60)
+#define LP2_DS_68_6ohm (68) /* optional */
+#define LP2_DS_80ohm (80)
+#define LP2_DS_120ohm (120) /* optional */
+
+#define LP3_DS_34ohm (34)
+#define LP3_DS_40ohm (40)
+#define LP3_DS_48ohm (48)
+#define LP3_DS_60ohm (60)
+#define LP3_DS_80ohm (80)
+#define LP3_DS_34D_40U (3440)
+#define LP3_DS_40D_48U (4048)
+#define LP3_DS_34D_48U (3448)
+
+#define LP3_ODT_DIS (0)
+#define LP3_ODT_60ohm (60)
+#define LP3_ODT_120ohm (120)
+#define LP3_ODT_240ohm (240)
+
+#define LP4_PDDS_40ohm (40)
+#define LP4_PDDS_48ohm (48)
+#define LP4_PDDS_60ohm (60)
+#define LP4_PDDS_80ohm (80)
+#define LP4_PDDS_120ohm (120)
+#define LP4_PDDS_240ohm (240)
+
+#define LP4_DQ_ODT_40ohm (40)
+#define LP4_DQ_ODT_48ohm (48)
+#define LP4_DQ_ODT_60ohm (60)
+#define LP4_DQ_ODT_80ohm (80)
+#define LP4_DQ_ODT_120ohm (120)
+#define LP4_DQ_ODT_240ohm (240)
+#define LP4_DQ_ODT_DIS (0)
+
+#define LP4_CA_ODT_40ohm (40)
+#define LP4_CA_ODT_48ohm (48)
+#define LP4_CA_ODT_60ohm (60)
+#define LP4_CA_ODT_80ohm (80)
+#define LP4_CA_ODT_120ohm (120)
+#define LP4_CA_ODT_240ohm (240)
+#define LP4_CA_ODT_DIS (0)
+
+#define DDR4_DS_34ohm (34)
+#define DDR4_DS_48ohm (48)
+#define DDR4_RTT_NOM_DIS (0)
+#define DDR4_RTT_NOM_60ohm (60)
+#define DDR4_RTT_NOM_120ohm (120)
+#define DDR4_RTT_NOM_40ohm (40)
+#define DDR4_RTT_NOM_240ohm (240)
+#define DDR4_RTT_NOM_48ohm (48)
+#define DDR4_RTT_NOM_80ohm (80)
+#define DDR4_RTT_NOM_34ohm (34)
+
+#define PHY_DDR3_RON_RTT_DISABLE (0)
+#define PHY_DDR3_RON_RTT_451ohm (1)
+#define PHY_DDR3_RON_RTT_225ohm (2)
+#define PHY_DDR3_RON_RTT_150ohm (3)
+#define PHY_DDR3_RON_RTT_112ohm (4)
+#define PHY_DDR3_RON_RTT_90ohm (5)
+#define PHY_DDR3_RON_RTT_75ohm (6)
+#define PHY_DDR3_RON_RTT_64ohm (7)
+#define PHY_DDR3_RON_RTT_56ohm (16)
+#define PHY_DDR3_RON_RTT_50ohm (17)
+#define PHY_DDR3_RON_RTT_45ohm (18)
+#define PHY_DDR3_RON_RTT_41ohm (19)
+#define PHY_DDR3_RON_RTT_37ohm (20)
+#define PHY_DDR3_RON_RTT_34ohm (21)
+#define PHY_DDR3_RON_RTT_33ohm (22)
+#define PHY_DDR3_RON_RTT_30ohm (23)
+#define PHY_DDR3_RON_RTT_28ohm (24)
+#define PHY_DDR3_RON_RTT_26ohm (25)
+#define PHY_DDR3_RON_RTT_25ohm (26)
+#define PHY_DDR3_RON_RTT_23ohm (27)
+#define PHY_DDR3_RON_RTT_22ohm (28)
+#define PHY_DDR3_RON_RTT_21ohm (29)
+#define PHY_DDR3_RON_RTT_20ohm (30)
+#define PHY_DDR3_RON_RTT_19ohm (31)
+
+#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
+#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
+#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
+#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
+#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
+#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
+#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
+#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
+#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
+#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
+#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
+#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
+#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
+#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
+#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
+#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
+#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
+#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
+#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
+#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
+#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
+#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
+#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
+#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
+
+#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/

36
target/linux/rockchip/patches-5.4/010-nanopi-r2s-rtl8152-leds.patch Normal file
View File

@ -0,0 +1,36 @@
From 2d4f786f94b331904682c24a792462726d474007 Mon Sep 17 00:00:00 2001
From: hmz007 <hmz007@gmail.com>
Date: Mon, 23 Dec 2019 13:10:06 +0800
Subject: [PATCH] r8152: Add module param for customized LEDs
Signed-off-by: hmz007 <hmz007@gmail.com>
---
drivers/net/usb/r8152.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index eb78f6d9390c..ec737fffcded 100644
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb/r8152.c
@@ -37,6 +37,11 @@
#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
#define MODULENAME "r8152"
+/* LED0: Activity, LED1: Link */
+static int ledsel = 0x78;
+module_param(ledsel, int, 0);
+MODULE_PARM_DESC(ledsel, "Override default LED configuration");
+
#define R8152_PHY_ID 32
#define PLA_IDR 0xc000
@@ -4545,6 +4550,9 @@ static void r8153b_init(struct r8152 *tp)
ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
+ /* set customized led */
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, ledsel);
+
rtl_tally_reset(tp);
tp->coalesce = 15000; /* 15 us */

40
target/linux/rockchip/patches-5.4/011-nanopi-r2s-mac-frfom-dt.patch Normal file
View File

@ -0,0 +1,40 @@
From 27dfe6f4347e883fd618d5a37500c7f6d3652fb9 Mon Sep 17 00:00:00 2001
From: hmz007 <hmz007@gmail.com>
Date: Fri, 22 Nov 2019 19:03:00 +0800
Subject: [PATCH] r8152: support to get MAC address from device tree
Signed-off-by: hmz007 <hmz007@gmail.com>
---
drivers/net/usb/r8152.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index b2507c59ba8b..eb78f6d9390c 100644
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb/r8152.c
@@ -6,6 +6,7 @@
#include <linux/signal.h>
#include <linux/slab.h>
#include <linux/module.h>
+#include <linux/of_net.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/mii.h>
@@ -1298,6 +1299,17 @@ static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
if (ret < 0) {
netif_err(tp, probe, dev, "Get ether addr fail\n");
} else if (!is_valid_ether_addr(sa->sa_data)) {
+ /* try to get MAC address from DT */
+ if (tp->udev->dev.of_node) {
+ const u8 *mac = of_get_mac_address(tp->udev->dev.of_node);
+ if (!IS_ERR(mac) && is_valid_ether_addr(mac)) {
+ ether_addr_copy(sa->sa_data, mac);
+ netif_info(tp, probe, dev, "DT mac addr %pM\n",
+ sa->sa_data);
+ return 0;
+ }
+ }
+
netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
sa->sa_data);
eth_hw_addr_random(dev);