From 77763dd129733540649b1e1dac76db9046d3029c Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@immortalwrt.org>
Date: Sun, 20 Aug 2023 17:31:25 +0800
Subject: [PATCH] rockchip: re-order eth ports for fastrhino r68s

eth0 <-> eth1
eth2 <-> eth3

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
---
 .../armv8/base-files/etc/board.d/02_network   |  6 +--
 .../base-files/etc/board.d/05_compat-version  | 15 ++++++
 target/linux/rockchip/image/armv8.mk          |  6 +++
 ...0-arm64-rockchip-add-OF-node-for-eth.patch | 53 +++++++++++++++++++
 4 files changed, 76 insertions(+), 4 deletions(-)
 create mode 100644 target/linux/rockchip/armv8/base-files/etc/board.d/05_compat-version

diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
index e766cb43d5..e274e2d3c0 100644
--- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
+++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
@@ -36,11 +36,9 @@ rockchip_setup_interfaces()
 	hinlink,opc-h69k)
 		ucidef_set_interfaces_lan_wan 'eth0 eth1' 'eth2'
 		;;
-	hinlink,opc-h68k)
-		ucidef_set_interfaces_lan_wan 'eth0 eth1 eth2' 'eth3'
-		;;
+	hinlink,opc-h68k|\
 	lunzn,fastrhino-r68s)
-		ucidef_set_interfaces_lan_wan 'eth0 eth1 eth3' 'eth2'
+		ucidef_set_interfaces_lan_wan 'eth0 eth1 eth2' 'eth3'
 		;;
 	*)
 		ucidef_set_interface_lan 'eth0'
diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/05_compat-version b/target/linux/rockchip/armv8/base-files/etc/board.d/05_compat-version
new file mode 100644
index 0000000000..e865cf20f2
--- /dev/null
+++ b/target/linux/rockchip/armv8/base-files/etc/board.d/05_compat-version
@@ -0,0 +1,15 @@
+. /lib/functions.sh
+. /lib/functions/uci-defaults.sh
+
+board="$(board_name)"
+board_config_update
+
+case "$board" in
+lunzn,fastrhino-r68s)
+	ucidef_set_compat_version "1.1"
+	;;
+esac
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk
index 2e8d1b4a01..5e7bc72678 100644
--- a/target/linux/rockchip/image/armv8.mk
+++ b/target/linux/rockchip/image/armv8.mk
@@ -5,6 +5,11 @@
 # FIT will be loaded at 0x02080000. Leave 16M for that, align it to 2M and load the kernel after it.
 KERNEL_LOADADDR := 0x03200000
 
+define Device/IfnameMigration
+  DEVICE_COMPAT_VERSION := 1.1
+  DEVICE_COMPAT_MESSAGE := Network interface names have been changed
+endef
+
 define Device/ezpro_mrkaio-m68s
   DEVICE_VENDOR := EZPRO
   DEVICE_MODEL := Mrkaio M68S
@@ -198,6 +203,7 @@ endef
 TARGET_DEVICES += lunzn_fastrhino-r66s
 
 define Device/lunzn_fastrhino-r68s
+  $(Device/IfnameMigration)
   DEVICE_VENDOR := Lunzn
   DEVICE_MODEL := FastRhino R68S
   SOC := rk3568
diff --git a/target/linux/rockchip/patches-6.1/610-arm64-rockchip-add-OF-node-for-eth.patch b/target/linux/rockchip/patches-6.1/610-arm64-rockchip-add-OF-node-for-eth.patch
index 03b6a817a2..36622fd376 100644
--- a/target/linux/rockchip/patches-6.1/610-arm64-rockchip-add-OF-node-for-eth.patch
+++ b/target/linux/rockchip/patches-6.1/610-arm64-rockchip-add-OF-node-for-eth.patch
@@ -86,3 +86,56 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  };
  
  &pinctrl {
+--- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
+@@ -31,6 +31,7 @@
+ 	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+ 	assigned-clock-rates = <0>, <125000000>;
+ 	clock_in_out = "output";
++	label = "eth0";
+ 	phy-handle = <&rgmii_phy0>;
+ 	phy-mode = "rgmii-id";
+ 	pinctrl-names = "default";
+@@ -53,6 +54,7 @@
+ 	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+ 	assigned-clock-rates = <0>, <125000000>;
+ 	clock_in_out = "output";
++	label = "eth1";
+ 	phy-handle = <&rgmii_phy1>;
+ 	phy-mode = "rgmii-id";
+ 	pinctrl-names = "default";
+@@ -88,6 +90,34 @@
+ 	};
+ };
+ 
++&pcie3x1 {
++	pcie@0,0 {
++		reg = <0x00100000 0 0 0 0>;
++		#address-cells = <3>;
++		#size-cells = <2>;
++
++		pcie-eth@10,0 {
++			compatible = "pci10ec,8125";
++			reg = <0x000000 0 0 0 0>;
++			label = "eth3";
++		};
++	};
++};
++
++&pcie3x2 {
++	pcie@0,0 {
++		reg = <0x00100000 0 0 0 0>;
++		#address-cells = <3>;
++		#size-cells = <2>;
++
++		pcie-eth@10,0 {
++			compatible = "pci10ec,8125";
++			reg = <0x000000 0 0 0 0>;
++			label = "eth2";
++		};
++	};
++};
++
+ &pinctrl {
+ 	gmac0 {
+ 		eth_phy0_reset_pin: eth-phy0-reset-pin {