rockchip: port cpuinfo driver from BSP kernel
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
parent
1a5f86bd35
commit
78773bc80c
@ -586,6 +586,7 @@ CONFIG_RELOCATABLE=y
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CONFIG_RESET_CONTROLLER=y
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CONFIG_RESET_SCMI=y
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CONFIG_RFS_ACCEL=y
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CONFIG_ROCKCHIP_CPUINFO=y
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CONFIG_ROCKCHIP_ERRATUM_3588001=y
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CONFIG_ROCKCHIP_GRF=y
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CONFIG_ROCKCHIP_IODOMAIN=y
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@ -0,0 +1,16 @@
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Rockchip cpuinfo device tree bindings
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----------------------------------
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Required properties:
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- compatible: Should be one of the following.
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- "rockchip,cpuinfo"
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- nvmem-cells: A phandle to the ID data provided by a nvmem device.
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- nvmem-cell-names: Should be "id"
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Example:
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cpuinfo {
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compatible = "rockchip,cpuinfo";
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nvmem-cells = <&efuse_id>;
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nvmem-cell-names = "id";
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};
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@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ARM_SYSTEM_INFO_H
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#define __ASM_ARM_SYSTEM_INFO_H
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#ifndef __ASSEMBLY__
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/* information about the system we're running on */
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extern unsigned int system_rev;
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extern unsigned int system_serial_low;
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extern unsigned int system_serial_high;
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_ARM_SYSTEM_INFO_H */
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307
target/linux/rockchip/files/drivers/soc/rockchip/cpuinfo.c
Normal file
307
target/linux/rockchip/files/drivers/soc/rockchip/cpuinfo.c
Normal file
@ -0,0 +1,307 @@
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/*
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* Copyright (C) 2017 Rockchip Electronics Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/crc32.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <asm/system_info.h>
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#include <linux/rockchip/cpu.h>
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unsigned long rockchip_soc_id;
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EXPORT_SYMBOL(rockchip_soc_id);
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static int rockchip_cpuinfo_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct nvmem_cell *cell;
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unsigned char *efuse_buf, buf[16];
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size_t len = 0;
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int i;
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cell = nvmem_cell_get(dev, "cpu-code");
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if (!IS_ERR(cell)) {
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efuse_buf = nvmem_cell_read(cell, &len);
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nvmem_cell_put(cell);
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if (IS_ERR(efuse_buf))
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return PTR_ERR(efuse_buf);
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if (len == 2)
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rockchip_set_cpu((efuse_buf[0] << 8 | efuse_buf[1]));
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kfree(efuse_buf);
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}
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cell = nvmem_cell_get(dev, "cpu-version");
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if (!IS_ERR(cell)) {
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efuse_buf = nvmem_cell_read(cell, &len);
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nvmem_cell_put(cell);
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if (IS_ERR(efuse_buf))
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return PTR_ERR(efuse_buf);
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if ((len == 1) && (efuse_buf[0] > rockchip_get_cpu_version()))
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rockchip_set_cpu_version(efuse_buf[0]);
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kfree(efuse_buf);
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}
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cell = nvmem_cell_get(dev, "id");
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if (IS_ERR(cell))
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return dev_err_probe(dev, PTR_ERR(cell), "failed to get id cell\n");
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efuse_buf = nvmem_cell_read(cell, &len);
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nvmem_cell_put(cell);
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if (IS_ERR(efuse_buf))
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return PTR_ERR(efuse_buf);
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if (len != 16) {
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kfree(efuse_buf);
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dev_err(dev, "invalid id len: %zu\n", len);
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return -EINVAL;
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}
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for (i = 0; i < 8; i++) {
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buf[i] = efuse_buf[1 + (i << 1)];
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buf[i + 8] = efuse_buf[i << 1];
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}
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kfree(efuse_buf);
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dev_info(dev, "SoC\t\t: %lx\n", rockchip_soc_id);
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system_serial_low = crc32(0, buf, 8);
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system_serial_high = crc32(system_serial_low, buf + 8, 8);
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dev_info(dev, "Serial\t\t: %08x%08x\n",
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system_serial_high, system_serial_low);
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return 0;
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}
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static const struct of_device_id rockchip_cpuinfo_of_match[] = {
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{ .compatible = "rockchip,cpuinfo", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, rockchip_cpuinfo_of_match);
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static struct platform_driver rockchip_cpuinfo_driver = {
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.probe = rockchip_cpuinfo_probe,
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.driver = {
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.name = "rockchip-cpuinfo",
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.of_match_table = rockchip_cpuinfo_of_match,
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},
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};
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static void rockchip_set_cpu_version_from_os_reg(u32 reg)
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{
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void __iomem *r = ioremap(reg, 0x4);
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if (r) {
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rockchip_set_cpu_version(readl_relaxed(r) & GENMASK(2, 0));
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iounmap(r);
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}
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}
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static void px30_init(void)
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{
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void __iomem *base;
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rockchip_soc_id = ROCKCHIP_SOC_PX30;
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#define PX30_DDR_GRF_BASE 0xFF630000
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#define PX30_DDR_GRF_CON1 0x04
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base = ioremap(PX30_DDR_GRF_BASE, SZ_4K);
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if (base) {
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unsigned int val = readl_relaxed(base + PX30_DDR_GRF_CON1);
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if (((val >> 14) & 0x03) == 0x03)
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rockchip_soc_id = ROCKCHIP_SOC_PX30S;
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iounmap(base);
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}
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}
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#define RV1106_OS_REG1 0xff020204
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static void rv1103_init(void)
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{
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rockchip_soc_id = ROCKCHIP_SOC_RV1103;
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rockchip_set_cpu_version_from_os_reg(RV1106_OS_REG1);
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}
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static void rv1106_init(void)
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{
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rockchip_soc_id = ROCKCHIP_SOC_RV1106;
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rockchip_set_cpu_version_from_os_reg(RV1106_OS_REG1);
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}
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static void rv1109_init(void)
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{
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rockchip_soc_id = ROCKCHIP_SOC_RV1109;
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}
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static void rv1126_init(void)
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{
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rockchip_soc_id = ROCKCHIP_SOC_RV1126;
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}
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static void rk3288_init(void)
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{
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void __iomem *base;
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rockchip_soc_id = ROCKCHIP_SOC_RK3288;
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#define RK3288_HDMI_PHYS 0xFF980000
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base = ioremap(RK3288_HDMI_PHYS, SZ_4K);
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if (base) {
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/* RK3288W HDMI Revision ID is 0x1A */
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if (readl_relaxed(base + 4) == 0x1A)
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rockchip_soc_id = ROCKCHIP_SOC_RK3288W;
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iounmap(base);
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}
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}
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static void rk3126_init(void)
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{
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void __iomem *base;
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rockchip_soc_id = ROCKCHIP_SOC_RK3126;
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#define RK312X_GRF_PHYS 0x20008000
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#define RK312X_GRF_SOC_CON1 0x00000144
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#define RK312X_GRF_CHIP_TAG 0x00000300
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base = ioremap(RK312X_GRF_PHYS, SZ_4K);
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if (base) {
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if (readl_relaxed(base + RK312X_GRF_CHIP_TAG) == 0x3136) {
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if (readl_relaxed(base + RK312X_GRF_SOC_CON1) & 0x1)
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rockchip_soc_id = ROCKCHIP_SOC_RK3126C;
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else
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rockchip_soc_id = ROCKCHIP_SOC_RK3126B;
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}
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iounmap(base);
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}
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}
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static void rk3308_init(void)
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{
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void __iomem *base;
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rockchip_soc_id = ROCKCHIP_SOC_RK3308;
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#define RK3308_GRF_PHYS 0xFF000000
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#define RK3308_GRF_CHIP_ID 0x800
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base = ioremap(RK3308_GRF_PHYS, SZ_4K);
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if (base) {
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u32 v = readl_relaxed(base + RK3308_GRF_CHIP_ID);
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if (v == 0x3308)
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rockchip_soc_id = ROCKCHIP_SOC_RK3308B;
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if (v == 0x3308c)
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rockchip_soc_id = ROCKCHIP_SOC_RK3308BS;
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iounmap(base);
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}
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}
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static void rk3528_init(void)
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{
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if (of_machine_is_compatible("rockchip,rk3528"))
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rockchip_soc_id = ROCKCHIP_SOC_RK3528;
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else if (of_machine_is_compatible("rockchip,rk3528a"))
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rockchip_soc_id = ROCKCHIP_SOC_RK3528A;
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}
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#define RK356X_PMU_GRF_PHYS 0xfdc20000
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#define RK356X_PMU_GRF_SOC_CON0 0x00000100
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#define RK356X_CHIP_VERSION_MASK 0x00008000
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static void rk356x_set_cpu_version(void)
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{
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void __iomem *base;
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base = ioremap(RK356X_PMU_GRF_PHYS, SZ_4K);
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if (base) {
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if (readl_relaxed(base + RK356X_PMU_GRF_SOC_CON0) & RK356X_CHIP_VERSION_MASK)
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rockchip_set_cpu_version(1);
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iounmap(base);
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}
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}
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static void rk3566_init(void)
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{
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rockchip_soc_id = ROCKCHIP_SOC_RK3566;
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rk356x_set_cpu_version();
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}
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static void rk3567_init(void)
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{
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rockchip_soc_id = ROCKCHIP_SOC_RK3567;
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rk356x_set_cpu_version();
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}
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static void rk3568_init(void)
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{
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rockchip_soc_id = ROCKCHIP_SOC_RK3568;
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rk356x_set_cpu_version();
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}
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int rockchip_soc_id_init(void)
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{
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if (rockchip_soc_id)
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return 0;
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if (cpu_is_rk3288()) {
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rk3288_init();
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} else if (cpu_is_rk312x()) {
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if (of_machine_is_compatible("rockchip,rk3128"))
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rockchip_soc_id = ROCKCHIP_SOC_RK3128;
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else
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rk3126_init();
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} else if (cpu_is_rk3308()) {
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rk3308_init();
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} else if (cpu_is_rv1103()) {
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rv1103_init();
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} else if (cpu_is_rv1106()) {
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rv1106_init();
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} else if (cpu_is_rv1109()) {
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rv1109_init();
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} else if (cpu_is_rv1126()) {
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rv1126_init();
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} else if (cpu_is_rk3528()) {
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rk3528_init();
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} else if (cpu_is_rk3566()) {
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rk3566_init();
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} else if (cpu_is_rk3567()) {
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rk3567_init();
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} else if (cpu_is_rk3568()) {
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rk3568_init();
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} else if (cpu_is_px30()) {
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px30_init();
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}
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return 0;
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}
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EXPORT_SYMBOL(rockchip_soc_id_init);
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#ifndef MODULE
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pure_initcall(rockchip_soc_id_init);
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#endif
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static int __init rockchip_cpuinfo_init(void)
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{
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#ifdef MODULE
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rockchip_soc_id_init();
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#endif
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return platform_driver_register(&rockchip_cpuinfo_driver);
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}
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subsys_initcall_sync(rockchip_cpuinfo_init);
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static void __exit rockchip_cpuinfo_exit(void)
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{
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platform_driver_unregister(&rockchip_cpuinfo_driver);
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}
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module_exit(rockchip_cpuinfo_exit);
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MODULE_LICENSE("GPL");
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234
target/linux/rockchip/files/include/linux/rockchip/cpu.h
Normal file
234
target/linux/rockchip/files/include/linux/rockchip/cpu.h
Normal file
@ -0,0 +1,234 @@
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/*
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* Copyright (C) 2017 Rockchip Electronics Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __LINUX_ROCKCHIP_CPU_H
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#define __LINUX_ROCKCHIP_CPU_H
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#include <linux/of.h>
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#define ROCKCHIP_CPU_MASK 0xffff0000
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#define ROCKCHIP_CPU_SHIFT 16
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#define ROCKCHIP_CPU_PX30 0x33260000
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#define ROCKCHIP_CPU_RV1103 0x11030000
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#define ROCKCHIP_CPU_RV1106 0x11060000
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#define ROCKCHIP_CPU_RV1109 0x11090000
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#define ROCKCHIP_CPU_RV1126 0x11260000
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#define ROCKCHIP_CPU_RK312X 0x31260000
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#define ROCKCHIP_CPU_RK3288 0x32880000
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#define ROCKCHIP_CPU_RK3308 0x33080000
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#define ROCKCHIP_CPU_RK3528 0x35280000
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#define ROCKCHIP_CPU_RK3566 0x35660000
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#define ROCKCHIP_CPU_RK3567 0x35670000
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#define ROCKCHIP_CPU_RK3568 0x35680000
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#if IS_REACHABLE(CONFIG_ROCKCHIP_CPUINFO)
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extern unsigned long rockchip_soc_id;
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#define ROCKCHIP_CPU_VERION_MASK 0x0000f000
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#define ROCKCHIP_CPU_VERION_SHIFT 12
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static inline unsigned long rockchip_get_cpu_version(void)
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{
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return (rockchip_soc_id & ROCKCHIP_CPU_VERION_MASK)
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>> ROCKCHIP_CPU_VERION_SHIFT;
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}
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static inline void rockchip_set_cpu_version(unsigned long ver)
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{
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rockchip_soc_id &= ~ROCKCHIP_CPU_VERION_MASK;
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rockchip_soc_id |=
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(ver << ROCKCHIP_CPU_VERION_SHIFT) & ROCKCHIP_CPU_VERION_MASK;
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}
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static inline void rockchip_set_cpu(unsigned long code)
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{
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if (!code)
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return;
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rockchip_soc_id &= ~ROCKCHIP_CPU_MASK;
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rockchip_soc_id |= (code << ROCKCHIP_CPU_SHIFT) & ROCKCHIP_CPU_MASK;
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}
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int rockchip_soc_id_init(void);
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#else
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#define rockchip_soc_id 0
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static inline unsigned long rockchip_get_cpu_version(void)
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{
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return 0;
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}
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static inline void rockchip_set_cpu_version(unsigned long ver)
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{
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}
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static inline void rockchip_set_cpu(unsigned long code)
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{
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}
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static inline int rockchip_soc_id_init(void)
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{
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return 0;
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}
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#endif
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static inline bool cpu_is_px30(void)
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{
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if (rockchip_soc_id)
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return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_PX30;
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return of_machine_is_compatible("rockchip,px30") ||
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of_machine_is_compatible("rockchip,px30s") ||
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of_machine_is_compatible("rockchip,rk3326") ||
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of_machine_is_compatible("rockchip,rk3326s");
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}
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static inline bool cpu_is_rv1103(void)
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{
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if (rockchip_soc_id)
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return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RV1103;
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return of_machine_is_compatible("rockchip,rv1103");
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}
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static inline bool cpu_is_rv1106(void)
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{
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if (rockchip_soc_id)
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return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RV1106;
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return of_machine_is_compatible("rockchip,rv1106");
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}
|
||||
|
||||
static inline bool cpu_is_rv1109(void)
|
||||
{
|
||||
if (rockchip_soc_id)
|
||||
return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RV1109;
|
||||
return of_machine_is_compatible("rockchip,rv1109");
|
||||
}
|
||||
|
||||
static inline bool cpu_is_rv1126(void)
|
||||
{
|
||||
if (rockchip_soc_id)
|
||||
return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RV1126;
|
||||
return of_machine_is_compatible("rockchip,rv1126");
|
||||
}
|
||||
|
||||
static inline bool cpu_is_rk312x(void)
|
||||
{
|
||||
if (rockchip_soc_id)
|
||||
return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK312X;
|
||||
return of_machine_is_compatible("rockchip,rk3126") ||
|
||||
of_machine_is_compatible("rockchip,rk3126b") ||
|
||||
of_machine_is_compatible("rockchip,rk3126c") ||
|
||||
of_machine_is_compatible("rockchip,rk3128");
|
||||
}
|
||||
|
||||
static inline bool cpu_is_rk3288(void)
|
||||
{
|
||||
if (rockchip_soc_id)
|
||||
return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3288;
|
||||
return of_machine_is_compatible("rockchip,rk3288") ||
|
||||
of_machine_is_compatible("rockchip,rk3288w");
|
||||
}
|
||||
|
||||
static inline bool cpu_is_rk3308(void)
|
||||
{
|
||||
if (rockchip_soc_id)
|
||||
return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3308;
|
||||
|
||||
return of_machine_is_compatible("rockchip,rk3308") ||
|
||||
of_machine_is_compatible("rockchip,rk3308bs");
|
||||
}
|
||||
|
||||
static inline bool cpu_is_rk3528(void)
|
||||
{
|
||||
if (rockchip_soc_id)
|
||||
return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3528;
|
||||
return of_machine_is_compatible("rockchip,rk3528") ||
|
||||
of_machine_is_compatible("rockchip,rk3528a");
|
||||
}
|
||||
|
||||
static inline bool cpu_is_rk3566(void)
|
||||
{
|
||||
if (rockchip_soc_id)
|
||||
return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3566;
|
||||
return of_machine_is_compatible("rockchip,rk3566");
|
||||
}
|
||||
|
||||
static inline bool cpu_is_rk3567(void)
|
||||
{
|
||||
if (rockchip_soc_id)
|
||||
return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3567;
|
||||
return of_machine_is_compatible("rockchip,rk3567");
|
||||
}
|
||||
|
||||
static inline bool cpu_is_rk3568(void)
|
||||
{
|
||||
if (rockchip_soc_id)
|
||||
return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3568;
|
||||
return of_machine_is_compatible("rockchip,rk3568");
|
||||
}
|
||||
|
||||
#define ROCKCHIP_SOC_MASK (ROCKCHIP_CPU_MASK | 0xff)
|
||||
#define ROCKCHIP_SOC_PX30 (ROCKCHIP_CPU_PX30 | 0x00)
|
||||
#define ROCKCHIP_SOC_PX30S (ROCKCHIP_CPU_PX30 | 0x01)
|
||||
#define ROCKCHIP_SOC_RV1103 (ROCKCHIP_CPU_RV1103 | 0x00)
|
||||
#define ROCKCHIP_SOC_RV1106 (ROCKCHIP_CPU_RV1106 | 0x00)
|
||||
#define ROCKCHIP_SOC_RV1109 (ROCKCHIP_CPU_RV1109 | 0x00)
|
||||
#define ROCKCHIP_SOC_RV1126 (ROCKCHIP_CPU_RV1126 | 0x00)
|
||||
#define ROCKCHIP_SOC_RK3126 (ROCKCHIP_CPU_RK312X | 0x00)
|
||||
#define ROCKCHIP_SOC_RK3126B (ROCKCHIP_CPU_RK312X | 0x10)
|
||||
#define ROCKCHIP_SOC_RK3126C (ROCKCHIP_CPU_RK312X | 0x20)
|
||||
#define ROCKCHIP_SOC_RK3128 (ROCKCHIP_CPU_RK312X | 0x01)
|
||||
#define ROCKCHIP_SOC_RK3288 (ROCKCHIP_CPU_RK3288 | 0x00)
|
||||
#define ROCKCHIP_SOC_RK3288W (ROCKCHIP_CPU_RK3288 | 0x01)
|
||||
#define ROCKCHIP_SOC_RK3308 (ROCKCHIP_CPU_RK3308 | 0x00)
|
||||
#define ROCKCHIP_SOC_RK3308B (ROCKCHIP_CPU_RK3308 | 0x01)
|
||||
#define ROCKCHIP_SOC_RK3308BS (ROCKCHIP_CPU_RK3308 | 0x02)
|
||||
#define ROCKCHIP_SOC_RK3528 (ROCKCHIP_CPU_RK3528 | 0x00)
|
||||
#define ROCKCHIP_SOC_RK3528A (ROCKCHIP_CPU_RK3528 | 0x01)
|
||||
#define ROCKCHIP_SOC_RK3566 (ROCKCHIP_CPU_RK3566 | 0x00)
|
||||
#define ROCKCHIP_SOC_RK3567 (ROCKCHIP_CPU_RK3567 | 0x00)
|
||||
#define ROCKCHIP_SOC_RK3568 (ROCKCHIP_CPU_RK3568 | 0x00)
|
||||
|
||||
#define ROCKCHIP_SOC(CPU, id, ID) \
|
||||
static inline bool soc_is_##id(void) \
|
||||
{ \
|
||||
if (rockchip_soc_id) \
|
||||
return ((rockchip_soc_id & ROCKCHIP_SOC_MASK) == ROCKCHIP_SOC_ ##ID); \
|
||||
return of_machine_is_compatible("rockchip,"#id); \
|
||||
}
|
||||
|
||||
ROCKCHIP_SOC(PX30, px30, PX30)
|
||||
ROCKCHIP_SOC(PX30, px30s, PX30S)
|
||||
ROCKCHIP_SOC(RV1106, rv1103, RV1103)
|
||||
ROCKCHIP_SOC(RV1106, rv1106, RV1106)
|
||||
ROCKCHIP_SOC(RV1126, rv1109, RV1109)
|
||||
ROCKCHIP_SOC(RV1126, rv1126, RV1126)
|
||||
ROCKCHIP_SOC(RK312X, rk3126, RK3126)
|
||||
ROCKCHIP_SOC(RK312X, rk3126b, RK3126B)
|
||||
ROCKCHIP_SOC(RK312X, rk3126c, RK3126C)
|
||||
ROCKCHIP_SOC(RK312X, rk3128, RK3128)
|
||||
ROCKCHIP_SOC(RK3288, rk3288, RK3288)
|
||||
ROCKCHIP_SOC(RK3288, rk3288w, RK3288W)
|
||||
ROCKCHIP_SOC(RK3308, rk3308, RK3308)
|
||||
ROCKCHIP_SOC(RK3308, rk3308b, RK3308B)
|
||||
ROCKCHIP_SOC(RK3308, rk3308bs, RK3308BS)
|
||||
ROCKCHIP_SOC(RK3528, rk3528, RK3528)
|
||||
ROCKCHIP_SOC(RK3528, rk3528a, RK3528A)
|
||||
ROCKCHIP_SOC(RK3568, rk3566, RK3566)
|
||||
ROCKCHIP_SOC(RK3567, rk3567, RK3567)
|
||||
ROCKCHIP_SOC(RK3568, rk3568, RK3568)
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,32 @@
|
||||
From: Heiko Stuebner <heiko@sntech.de>
|
||||
To: srinivas.kandagatla@linaro.org
|
||||
Cc: heiko@sntech.de, linux-arm-kernel@lists.infradead.org,
|
||||
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
|
||||
quentin.schulz@cherry.de,
|
||||
Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Subject: [PATCH 1/3] nvmem: rockchip-otp: set add_legacy_fixed_of_cells config option
|
||||
Date: Tue, 7 May 2024 14:22:54 +0200 [thread overview]
|
||||
Message-ID: <20240507122256.3765362-2-heiko@sntech.de> (raw)
|
||||
In-Reply-To: <20240507122256.3765362-1-heiko@sntech.de>
|
||||
|
||||
From: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
|
||||
The Rockchip OTP describes its layout via devicetree subnodes,
|
||||
so set the appropriate property.
|
||||
|
||||
Fixes: 2cc3b37f5b6d ("nvmem: add explicit config option to read old syntax fixed OF cells")
|
||||
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
---
|
||||
drivers/nvmem/rockchip-otp.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/nvmem/rockchip-otp.c
|
||||
+++ b/drivers/nvmem/rockchip-otp.c
|
||||
@@ -255,6 +255,7 @@ static int rockchip_otp_read(void *conte
|
||||
static struct nvmem_config otp_config = {
|
||||
.name = "rockchip-otp",
|
||||
.owner = THIS_MODULE,
|
||||
+ .add_legacy_fixed_of_cells = true,
|
||||
.read_only = true,
|
||||
.stride = 1,
|
||||
.word_size = 1,
|
||||
@ -0,0 +1,30 @@
|
||||
From: Heiko Stuebner <heiko@sntech.de>
|
||||
To: srinivas.kandagatla@linaro.org
|
||||
Cc: heiko@sntech.de, linux-arm-kernel@lists.infradead.org,
|
||||
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
|
||||
quentin.schulz@cherry.de,
|
||||
Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Subject: [PATCH 2/3] nvmem: rockchip-otp: Set type to OTP
|
||||
Date: Tue, 7 May 2024 14:22:55 +0200 [thread overview]
|
||||
Message-ID: <20240507122256.3765362-3-heiko@sntech.de> (raw)
|
||||
In-Reply-To: <20240507122256.3765362-1-heiko@sntech.de>
|
||||
|
||||
From: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
|
||||
The Rockchip OTP is obviously an OTP memory, so document this fact.
|
||||
|
||||
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
---
|
||||
drivers/nvmem/rockchip-otp.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/nvmem/rockchip-otp.c
|
||||
+++ b/drivers/nvmem/rockchip-otp.c
|
||||
@@ -256,6 +256,7 @@ static struct nvmem_config otp_config =
|
||||
.name = "rockchip-otp",
|
||||
.owner = THIS_MODULE,
|
||||
.add_legacy_fixed_of_cells = true,
|
||||
+ .type = NVMEM_TYPE_OTP,
|
||||
.read_only = true,
|
||||
.stride = 1,
|
||||
.word_size = 1,
|
||||
@ -0,0 +1,31 @@
|
||||
From: Heiko Stuebner <heiko@sntech.de>
|
||||
To: srinivas.kandagatla@linaro.org
|
||||
Cc: heiko@sntech.de, linux-arm-kernel@lists.infradead.org,
|
||||
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
|
||||
quentin.schulz@cherry.de,
|
||||
Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Subject: [PATCH 3/3] nvmem: rockchip-efuse: set type to OTP
|
||||
Date: Tue, 7 May 2024 14:22:56 +0200 [thread overview]
|
||||
Message-ID: <20240507122256.3765362-4-heiko@sntech.de> (raw)
|
||||
In-Reply-To: <20240507122256.3765362-1-heiko@sntech.de>
|
||||
|
||||
From: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
|
||||
This device currently reports an "Unknown" type in sysfs.
|
||||
Since it is an eFuse hardware device, set its type to OTP.
|
||||
|
||||
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
---
|
||||
drivers/nvmem/rockchip-efuse.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/nvmem/rockchip-efuse.c
|
||||
+++ b/drivers/nvmem/rockchip-efuse.c
|
||||
@@ -206,6 +206,7 @@ static int rockchip_rk3399_efuse_read(vo
|
||||
static struct nvmem_config econfig = {
|
||||
.name = "rockchip-efuse",
|
||||
.add_legacy_fixed_of_cells = true,
|
||||
+ .type = NVMEM_TYPE_OTP,
|
||||
.stride = 1,
|
||||
.word_size = 1,
|
||||
.read_only = true,
|
||||
@ -0,0 +1,134 @@
|
||||
From 154292ae52bf21c77aa1b81035bd85343b416001 Mon Sep 17 00:00:00 2001
|
||||
From: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
Date: Thu, 12 Nov 2020 16:24:14 +0800
|
||||
Subject: [PATCH] nvmem: rockchip-otp: Add support for rk3568-otp
|
||||
|
||||
This adds the necessary data for handling efuse on the rk3568.
|
||||
|
||||
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
Change-Id: Ia74d77b68a6303223eaccdc08e882851a917f50f
|
||||
---
|
||||
drivers/nvmem/rockchip-otp.c | 90 ++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 90 insertions(+)
|
||||
|
||||
--- a/drivers/nvmem/rockchip-otp.c
|
||||
+++ b/drivers/nvmem/rockchip-otp.c
|
||||
@@ -27,6 +27,7 @@
|
||||
#define OTPC_USER_CTRL 0x0100
|
||||
#define OTPC_USER_ADDR 0x0104
|
||||
#define OTPC_USER_ENABLE 0x0108
|
||||
+#define OTPC_USER_QP 0x0120
|
||||
#define OTPC_USER_Q 0x0124
|
||||
#define OTPC_INT_STATUS 0x0304
|
||||
#define OTPC_SBPI_CMD0_OFFSET 0x1000
|
||||
@@ -53,6 +54,7 @@
|
||||
#define SBPI_ENABLE_MASK GENMASK(16, 16)
|
||||
|
||||
#define OTPC_TIMEOUT 10000
|
||||
+#define RK3568_NBYTES 2
|
||||
|
||||
/* RK3588 Register */
|
||||
#define RK3588_OTPC_AUTO_CTRL 0x04
|
||||
@@ -184,6 +186,73 @@ read_end:
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static int rk3568_otp_read(void *context, unsigned int offset, void *val,
|
||||
+ size_t bytes)
|
||||
+{
|
||||
+ struct rockchip_otp *otp = context;
|
||||
+ unsigned int addr_start, addr_end, addr_offset, addr_len;
|
||||
+ unsigned int otp_qp;
|
||||
+ u32 data;
|
||||
+ u8 *buf;
|
||||
+ int ret, i = 0;
|
||||
+
|
||||
+ addr_start = rounddown(offset, RK3568_NBYTES) / RK3568_NBYTES;
|
||||
+ addr_end = roundup(offset + bytes, RK3568_NBYTES) / RK3568_NBYTES;
|
||||
+ addr_offset = offset % RK3568_NBYTES;
|
||||
+ addr_len = addr_end - addr_start;
|
||||
+
|
||||
+ buf = kzalloc(array3_size(addr_len, RK3568_NBYTES, sizeof(*buf)),
|
||||
+ GFP_KERNEL);
|
||||
+ if (!buf)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ ret = rockchip_otp_reset(otp);
|
||||
+ if (ret) {
|
||||
+ dev_err(otp->dev, "failed to reset otp phy\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = rockchip_otp_ecc_enable(otp, true);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
|
||||
+ udelay(5);
|
||||
+ while (addr_len--) {
|
||||
+ writel(addr_start++ | OTPC_USER_ADDR_MASK,
|
||||
+ otp->base + OTPC_USER_ADDR);
|
||||
+ writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
|
||||
+ otp->base + OTPC_USER_ENABLE);
|
||||
+
|
||||
+ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(otp->dev, "timeout during read setup\n");
|
||||
+ goto read_end;
|
||||
+ }
|
||||
+
|
||||
+ otp_qp = readl(otp->base + OTPC_USER_QP);
|
||||
+ if (((otp_qp & 0xc0) == 0xc0) || (otp_qp & 0x20)) {
|
||||
+ ret = -EIO;
|
||||
+ dev_err(otp->dev, "ecc check error during read setup\n");
|
||||
+ goto read_end;
|
||||
+ }
|
||||
+
|
||||
+ data = readl(otp->base + OTPC_USER_Q);
|
||||
+ memcpy(&buf[i], &data, RK3568_NBYTES);
|
||||
+
|
||||
+ i += RK3568_NBYTES;
|
||||
+ }
|
||||
+
|
||||
+ memcpy(val, buf + addr_offset, bytes);
|
||||
+
|
||||
+read_end:
|
||||
+ writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
static int rk3588_otp_read(void *context, unsigned int offset,
|
||||
void *val, size_t bytes)
|
||||
{
|
||||
@@ -274,6 +343,17 @@ static const struct rockchip_data px30_d
|
||||
.reg_read = px30_otp_read,
|
||||
};
|
||||
|
||||
+static const char * const rk3568_otp_clocks[] = {
|
||||
+ "usr", "sbpi", "apb", "phy",
|
||||
+};
|
||||
+
|
||||
+static const struct rockchip_data rk3568_data = {
|
||||
+ .size = 0x80,
|
||||
+ .clks = rk3568_otp_clocks,
|
||||
+ .num_clks = ARRAY_SIZE(rk3568_otp_clocks),
|
||||
+ .reg_read = rk3568_otp_read,
|
||||
+};
|
||||
+
|
||||
static const char * const rk3588_otp_clocks[] = {
|
||||
"otp", "apb_pclk", "phy", "arb",
|
||||
};
|
||||
@@ -295,6 +375,10 @@ static const struct of_device_id rockchi
|
||||
.data = &px30_data,
|
||||
},
|
||||
{
|
||||
+ .compatible = "rockchip,rk3568-otp",
|
||||
+ .data = &rk3568_data,
|
||||
+ },
|
||||
+ {
|
||||
.compatible = "rockchip,rk3588-otp",
|
||||
.data = &rk3588_data,
|
||||
},
|
||||
@ -0,0 +1,61 @@
|
||||
From e8c0448b695911c5a0cc37cadaacaf71d16b04d2 Mon Sep 17 00:00:00 2001
|
||||
From: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
Date: Thu, 12 Nov 2020 15:43:28 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3568: Add otp device node
|
||||
|
||||
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
Change-Id: I4ec51ba8d4e1381f787c0137cb475a21e546789d
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 29 ++++++++++++++++++++++++
|
||||
1 file changed, 29 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -840,6 +840,47 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ otp: otp@fe38c000 {
|
||||
+ compatible = "rockchip,rk3568-otp";
|
||||
+ reg = <0x0 0xfe38c000 0x0 0x4000>;
|
||||
+ clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>,
|
||||
+ <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>;
|
||||
+ clock-names = "usr", "sbpi", "apb", "phy";
|
||||
+ resets = <&cru SRST_OTPPHY>;
|
||||
+ reset-names = "otp_phy";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ cpu_code: cpu-code@2 {
|
||||
+ reg = <0x02 0x2>;
|
||||
+ };
|
||||
+
|
||||
+ otp_cpu_version: cpu-version@8 {
|
||||
+ reg = <0x08 0x1>;
|
||||
+ bits = <3 3>;
|
||||
+ };
|
||||
+
|
||||
+ otp_id: id@a {
|
||||
+ reg = <0x0a 0x10>;
|
||||
+ };
|
||||
+
|
||||
+ cpu_leakage: cpu-leakage@1a {
|
||||
+ reg = <0x1a 0x1>;
|
||||
+ };
|
||||
+
|
||||
+ log_leakage: log-leakage@1b {
|
||||
+ reg = <0x1b 0x1>;
|
||||
+ };
|
||||
+
|
||||
+ npu_leakage: npu-leakage@1c {
|
||||
+ reg = <0x1c 0x1>;
|
||||
+ };
|
||||
+
|
||||
+ gpu_leakage: gpu-leakage@1d {
|
||||
+ reg = <0x1d 0x1>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
qos_gpu: qos@fe128000 {
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe128000 0x0 0x20>;
|
||||
@ -0,0 +1,36 @@
|
||||
From a21e820a5ae04e1b6619f601430b9602c597db33 Mon Sep 17 00:00:00 2001
|
||||
From: Tao Huang <huangtao@rock-chips.com>
|
||||
Date: Thu, 27 Oct 2016 19:41:45 +0800
|
||||
Subject: [PATCH] arm64: cpuinfo: add system serial support
|
||||
|
||||
Change-Id: I4542f07226e47e67be1f2792cffaa71fd6401442
|
||||
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
|
||||
---
|
||||
arch/arm64/kernel/cpuinfo.c | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/arm64/kernel/cpuinfo.c
|
||||
+++ b/arch/arm64/kernel/cpuinfo.c
|
||||
@@ -25,6 +25,12 @@
|
||||
#include <linux/smp.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
+unsigned int system_serial_low;
|
||||
+EXPORT_SYMBOL(system_serial_low);
|
||||
+
|
||||
+unsigned int system_serial_high;
|
||||
+EXPORT_SYMBOL(system_serial_high);
|
||||
+
|
||||
/*
|
||||
* In case the boot CPU is hotpluggable, we record its initial state and
|
||||
* current state separately. Certain system registers may contain different
|
||||
@@ -237,6 +243,9 @@ static int c_show(struct seq_file *m, vo
|
||||
seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
|
||||
}
|
||||
|
||||
+ seq_printf(m, "Serial\t\t: %08x%08x\n",
|
||||
+ system_serial_high, system_serial_low);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -0,0 +1,48 @@
|
||||
From c336f64cf9a9c1bbeb0027f26c94ecfb29367ee1 Mon Sep 17 00:00:00 2001
|
||||
From: "Huang, Tao" <huangtao@rock-chips.com>
|
||||
Date: Thu, 6 Apr 2017 20:27:14 +0800
|
||||
Subject: [PATCH] soc: rockchip: add cpuinfo support
|
||||
|
||||
Set system_serial_low/high from eFuse ID.
|
||||
Serial can read from /proc/cpuinfo.
|
||||
|
||||
Change-Id: If412fc5a89a5e5092b510452fc5a126fdd374ac2
|
||||
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
|
||||
---
|
||||
.../soc/rockchip/rockchip-cpuinfo.txt | 16 ++++
|
||||
drivers/soc/rockchip/Kconfig | 10 +++
|
||||
drivers/soc/rockchip/Makefile | 1 +
|
||||
drivers/soc/rockchip/rockchip-cpuinfo.c | 75 +++++++++++++++++++
|
||||
4 files changed, 102 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/soc/rockchip/rockchip-cpuinfo.txt
|
||||
create mode 100644 drivers/soc/rockchip/rockchip-cpuinfo.c
|
||||
|
||||
--- a/drivers/soc/rockchip/Kconfig
|
||||
+++ b/drivers/soc/rockchip/Kconfig
|
||||
@@ -5,6 +5,16 @@ if ARCH_ROCKCHIP || COMPILE_TEST
|
||||
# Rockchip Soc drivers
|
||||
#
|
||||
|
||||
+config ROCKCHIP_CPUINFO
|
||||
+ tristate "Rockchip cpuinfo support"
|
||||
+ depends on (NVMEM_ROCKCHIP_EFUSE || NVMEM_ROCKCHIP_OTP) && (ARM64 || ARM)
|
||||
+ help
|
||||
+ Say y here to enable Rockchip cpuinfo support.
|
||||
+ Set system_serial_low/high from eFuse ID.
|
||||
+ Serial can read from /proc/cpuinfo.
|
||||
+
|
||||
+ If unsure, say N.
|
||||
+
|
||||
config ROCKCHIP_GRF
|
||||
bool "Rockchip General Register Files support" if COMPILE_TEST
|
||||
default y if ARCH_ROCKCHIP
|
||||
--- a/drivers/soc/rockchip/Makefile
|
||||
+++ b/drivers/soc/rockchip/Makefile
|
||||
@@ -2,6 +2,7 @@
|
||||
#
|
||||
# Rockchip Soc drivers
|
||||
#
|
||||
+obj-$(CONFIG_ROCKCHIP_CPUINFO) += cpuinfo.o
|
||||
obj-$(CONFIG_ROCKCHIP_GRF) += grf.o
|
||||
obj-$(CONFIG_ROCKCHIP_IODOMAIN) += io-domain.o
|
||||
obj-$(CONFIG_ROCKCHIP_DTPM) += dtpm.o
|
||||
@ -0,0 +1,26 @@
|
||||
From e9c54637e971995d06ac8fd7c6d3b57d62848249 Mon Sep 17 00:00:00 2001
|
||||
From: Chen Liang <cl@rock-chips.com>
|
||||
Date: Fri, 7 Apr 2017 17:25:45 +0800
|
||||
Subject: [PATCH] ARM64: dts: rockchip: add cpuinfo support for rk3328
|
||||
|
||||
Change-Id: Iaaa400c09c2fb7c0d5e96fa4217065fa14066fc1
|
||||
Signed-off-by: Chen Liang <cl@rock-chips.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -169,6 +169,12 @@
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
||||
};
|
||||
|
||||
+ cpuinfo {
|
||||
+ compatible = "rockchip,cpuinfo";
|
||||
+ nvmem-cells = <&efuse_id>, <&efuse_cpu_version>;
|
||||
+ nvmem-cell-names = "id", "cpu-version";
|
||||
+ };
|
||||
+
|
||||
display_subsystem: display-subsystem {
|
||||
compatible = "rockchip,display-subsystem";
|
||||
ports = <&vop_out>;
|
||||
@ -0,0 +1,27 @@
|
||||
From f63140be2575c8ae35fdc29a23a9f4a819ec3cd5 Mon Sep 17 00:00:00 2001
|
||||
From: "Huang, Tao" <huangtao@rock-chips.com>
|
||||
Date: Thu, 6 Apr 2017 20:30:11 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add cpuinfo support for rk3399-android
|
||||
|
||||
Change-Id: I0eba0017a88added1a84f9c3add1705d8079cd00
|
||||
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-android.dtsi | 6 ++++++
|
||||
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 3 +++
|
||||
2 files changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -173,6 +173,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ cpuinfo {
|
||||
+ compatible = "rockchip,cpuinfo";
|
||||
+ nvmem-cells = <&cpu_id>;
|
||||
+ nvmem-cell-names = "id";
|
||||
+ };
|
||||
+
|
||||
display-subsystem {
|
||||
compatible = "rockchip,display-subsystem";
|
||||
ports = <&vopl_out>, <&vopb_out>;
|
||||
@ -0,0 +1,26 @@
|
||||
From cc9529c8ba206aaed6bdd3674572a7eb7126d851 Mon Sep 17 00:00:00 2001
|
||||
From: Liang Chen <cl@rock-chips.com>
|
||||
Date: Tue, 29 Dec 2020 15:22:03 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add cpuinfo node for rk3568
|
||||
|
||||
Change-Id: Ia98489355ca992d19f8c215978dd25699603c6ce
|
||||
Signed-off-by: Liang Chen <cl@rock-chips.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 13 +++++++++++++
|
||||
1 file changed, 13 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -129,6 +129,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ cpuinfo {
|
||||
+ compatible = "rockchip,cpuinfo";
|
||||
+ nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
|
||||
+ nvmem-cell-names = "id", "cpu-version", "cpu-code";
|
||||
+ };
|
||||
+
|
||||
display_subsystem: display-subsystem {
|
||||
compatible = "rockchip,display-subsystem";
|
||||
ports = <&vop_out>;
|
||||
@ -0,0 +1,26 @@
|
||||
From 16b5587b5f6c975c7b546805939dbd563bbc2099 Mon Sep 17 00:00:00 2001
|
||||
From: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
Date: Wed, 22 Dec 2021 17:37:31 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add cpuinfo device node
|
||||
|
||||
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
Change-Id: I050cc7f6398500e705b27c588948201e571817ea
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 18 ++++++++++++++++++
|
||||
1 file changed, 18 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -565,6 +565,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ cpuinfo {
|
||||
+ compatible = "rockchip,cpuinfo";
|
||||
+ nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
|
||||
+ nvmem-cell-names = "id", "cpu-version", "cpu-code";
|
||||
+ };
|
||||
+
|
||||
display_subsystem: display-subsystem {
|
||||
compatible = "rockchip,display-subsystem";
|
||||
ports = <&vop_out>;
|
||||
@ -38,7 +38,7 @@
|
||||
phy-names = "pcie-phy";
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -315,14 +315,21 @@
|
||||
@@ -321,14 +321,21 @@
|
||||
|
||||
gic: interrupt-controller@fd400000 {
|
||||
compatible = "arm,gic-v3";
|
||||
@ -66,7 +66,7 @@
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@fd800000 {
|
||||
@@ -989,7 +996,7 @@
|
||||
@@ -1036,7 +1043,7 @@
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <2>;
|
||||
|
||||
@ -12,7 +12,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -222,6 +222,13 @@
|
||||
@@ -228,6 +228,13 @@
|
||||
arm,no-tick-in-suspend;
|
||||
};
|
||||
|
||||
@ -26,7 +26,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
|
||||
xin24m: xin24m {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
@@ -376,6 +383,12 @@
|
||||
@@ -382,6 +389,12 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -39,7 +39,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
|
||||
pmugrf: syscon@fdc20000 {
|
||||
compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfdc20000 0x0 0x10000>;
|
||||
@@ -675,11 +688,13 @@
|
||||
@@ -681,11 +694,13 @@
|
||||
clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
|
||||
<&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
|
||||
<&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
|
||||
|
||||
@ -11,7 +11,7 @@ Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -281,6 +281,17 @@
|
||||
@@ -287,6 +287,17 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -13,7 +13,7 @@ Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -2114,6 +2114,15 @@
|
||||
@@ -2120,6 +2120,15 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -11,7 +11,7 @@ Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -1034,6 +1034,15 @@
|
||||
@@ -1081,6 +1081,15 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -11,7 +11,7 @@ Change-Id: Ifb8964053daa6b593dd2c2c6a3b8caab8526e56d
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -2252,6 +2252,16 @@
|
||||
@@ -2258,6 +2258,16 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -14,7 +14,7 @@ Change-Id: I49994529fcc209c2bc173c1abc497536fb920302
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -2256,7 +2256,7 @@
|
||||
@@ -2262,7 +2262,7 @@
|
||||
compatible = "rockchip,trngv1";
|
||||
reg = <0x0 0xfe378000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@ -28,7 +28,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3328";
|
||||
@@ -1034,6 +1035,78 @@
|
||||
@@ -1040,6 +1041,78 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user