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rockchip: backport latest rk3588 patches from upstream

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2023-12-14 16:15:45 +08:00
parent 22616d37fe
commit 7dbca5869f
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
17 changed files with 265 additions and 45 deletions
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53
target/linux/rockchip/patches-6.1/050-28-v6.7-arm64-dts-rockchip-Fix-eMMC-Data-Strobe-PD-on-rk3588.patch Normal file
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@ -0,0 +1,53 @@
From 37f3d6108730713c411827ab4af764909f4dfc78 Mon Sep 17 00:00:00 2001
From: Sam Edwards <cfsworks@gmail.com>
Date: Tue, 5 Dec 2023 12:29:00 -0800
Subject: [PATCH] arm64: dts: rockchip: Fix eMMC Data Strobe PD on rk3588
JEDEC standard JESD84-B51 defines the eMMC Data Strobe line, which is
currently used only in HS400 mode, as a device->host clock signal that
"is used only in read operation. The Data Strobe is always High-Z (not
driven by the device and pulled down by RDS) or Driven Low in write
operation, except during CRC status response." RDS is a pull-down
resistor specified in the 10K-100K ohm range. Thus per the standard, the
Data Strobe is always pulled to ground (by the eMMC and/or RDS) during
write operations.
Evidently, the eMMC host controller in the RK3588 considers an active
voltage on the eMMC-DS line during a write to be an error.
The default (i.e. hardware reset, and Rockchip BSP) behavior for the
RK3588 is to activate the eMMC-DS pin's builtin pull-down. As a result,
many RK3588 board designers do not bother adding a dedicated RDS
resistor, instead relying on the RK3588's internal bias. The current
devicetree, however, disables this bias (`pcfg_pull_none`), breaking
HS400-mode writes for boards without a dedicated RDS, but with an eMMC
chip that chooses to High-Z (instead of drive-low) the eMMC-DS line.
(The Turing RK1 is one such board.)
Fix this by changing the bias in the (common) emmc_data_strobe case to
reflect the expected hardware/BSP behavior. This is unlikely to cause
regressions elsewhere: the pull-down is only relevant for High-Z eMMCs,
and if this is redundant with a (dedicated) RDS resistor, the effective
result is only a lower resistance to ground -- where the range of
tolerance is quite high. If it does, it's better fixed in the specific
devicetrees.
Fixes: d85f8a5c798d5 ("arm64: dts: rockchip: Add rk3588 pinctrl data")
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Link: https://lore.kernel.org/r/20231205202900.4617-2-CFSworks@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
@@ -369,7 +369,7 @@
emmc_data_strobe: emmc-data-strobe {
rockchip,pins =
/* emmc_data_strobe */
- <2 RK_PA2 1 &pcfg_pull_none>;
+ <2 RK_PA2 1 &pcfg_pull_down>;
};
};

53
target/linux/rockchip/patches-6.1/050-29-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch Normal file
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@ -0,0 +1,53 @@
From 9918d10d16665527e59fdb87c5acac70cc1cfe8f Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko.stuebner@cherry.de>
Date: Tue, 5 Dec 2023 17:48:39 +0100
Subject: [PATCH] arm64: dts: rockchip: move rk3588 serial aliases to soc dtsi
The serial ports on rk3588 are named uart0 - uart9. Board schematics
also use these exact numbers and we want those names to also reflect
in the OS devices because everything else would just cause confusion.
To prevent each board repeating their list of serial aliases, move them
to the soc dtsi, as all previous Rockchip soc do already.
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20231205164842.556684-2-heiko@sntech.de
---
.../boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts | 4 ----
.../boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts | 4 ----
arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 1 -
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 1 -
.../boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 1 -
arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 1 -
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 -
arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 --
.../boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 1 -
.../boot/dts/rockchip/rk3588s-khadas-edge2.dts | 1 -
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 1 -
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 -
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++
13 files changed, 13 insertions(+), 19 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -18,6 +18,19 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ serial9 = &uart9;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;

38
target/linux/rockchip/patches-6.1/050-30-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch Normal file
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@ -0,0 +1,38 @@
From 328e901b7b03d292c1520ffb38e9164feef4f1ea Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko.stuebner@cherry.de>
Date: Tue, 5 Dec 2023 17:48:40 +0100
Subject: [PATCH] arm64: dts: rockchip: add rk3588 i2c aliases to soc dtsi
The i2c controllers on rk3588 are named i2c0 - i2c8. Board schematics
also use these exact numbers and we want those names to also reflect
in the OS devices because everything else would just cause confusion.
Userspace i2c access is a thing afterall.
To prevent each board repeating their list of i2c aliases, define them
in the soc dtsi, as all previous Rockchip soc do already.
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20231205164842.556684-3-heiko@sntech.de
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -19,6 +19,15 @@
#size-cells = <2>;
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;

34
target/linux/rockchip/patches-6.1/050-31-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch Normal file
View File

@ -0,0 +1,34 @@
From a024abedbca99a20aeb96f5beec9ded13c85dcb3 Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko.stuebner@cherry.de>
Date: Tue, 5 Dec 2023 17:48:41 +0100
Subject: [PATCH] arm64: dts: rockchip: add rk3588 gpio aliases to soc dtsi
The gpio controllers on rk3588 are named gpio0 - gpio4. Board schematics
also use these exact numbers and we want those names to also reflect
in the OS devices because everything else would just cause confusion.
Userspace gpio access is a thing afterall.
To prevent each board repeating their list of gpio aliases, define them
in the soc dtsi, as previous Rockchip soc like the rk356x do already.
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20231205164842.556684-4-heiko@sntech.de
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++
1 file changed, 5 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -19,6 +19,11 @@
#size-cells = <2>;
aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;

34
target/linux/rockchip/patches-6.1/050-32-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch Normal file
View File

@ -0,0 +1,34 @@
From a86e88043de929da76f7f6cf0990ba92aed8391a Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko.stuebner@cherry.de>
Date: Tue, 5 Dec 2023 17:48:42 +0100
Subject: [PATCH] arm64: dts: rockchip: add rk3588 spi aliases to soc dtsi
The spi controllers on rk3588 are named spi0 - spi4. Board schematics
also use these exact numbers and we want those names to also reflect
in the OS devices because everything else would just cause confusion.
Userspace spi access is a thing afterall.
To prevent each board repeating their list of spi aliases, define them
in the soc dtsi, as previous Rockchip soc like the rk356x do already.
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20231205164842.556684-5-heiko@sntech.de
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++
1 file changed, 5 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -43,6 +43,11 @@
serial7 = &uart7;
serial8 = &uart8;
serial9 = &uart9;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ spi4 = &spi4;
};
cpus {

14
target/linux/rockchip/patches-6.1/122-01-arm64-dts-rockchip-rk3588s-rock5a-add-USB3-host.patch → target/linux/rockchip/patches-6.1/052-17-v6.8-arm64-dts-rockchip-add-USB3-host-to-rock-5a.patch
View File

@ -1,22 +1,24 @@
From 26123b03c3188b29cfd4500a9e0ed0d23dc1625f Mon Sep 17 00:00:00 2001
From 0773a4a199aabb60afe50f5a19a6772abf4ad0bf Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Fri, 21 Jul 2023 15:19:37 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588s-rock5a: add USB3 host
Date: Mon, 6 Nov 2023 16:54:32 +0100
Subject: [PATCH] arm64: dts: rockchip: add USB3 host to rock-5a
Enable USB3 host controller for the Radxa ROCK 5 Model A. This adds
USB3 for the lower USB3 port (the one closer to the PCB).
The upper USB3 port uses the RK3588 USB TypeC host controller, which
uses a different PHY that is not yet supported upstream.
use a different PHY without upstream support.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20231106155934.80838-2-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -117,6 +117,10 @@
@@ -113,6 +113,10 @@
};
};
@ -27,7 +29,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
@@ -736,3 +740,7 @@
@@ -733,3 +737,7 @@
&usb_host1_ohci {
status = "okay";
};

2
target/linux/rockchip/patches-6.1/053-15-v6.6-arm64-dts-rockchip-fix-update-sdmmc-properties-for-rock-5.patch
View File

@ -45,7 +45,7 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
serial2 = &uart2;
};
@@ -362,6 +363,7 @@
@@ -366,6 +367,7 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;

17
target/linux/rockchip/patches-6.1/123-04-arm64-dts-rockchip-rk3588-rock5b-add-USB3-host.patch → target/linux/rockchip/patches-6.1/053-23-v6.8-arm64-dts-rockchip-add-USB3-host-to-rock-5b.patch
View File

@ -1,23 +1,24 @@
From 78299f59cc6164ca5d57affa3655358f67d6442b Mon Sep 17 00:00:00 2001
From f97d78b9f6cff4c680206a8c8b03f726f0dc2c8b Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Wed, 19 Jul 2023 15:56:42 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588-rock5b: add USB3 host
Date: Mon, 6 Nov 2023 16:54:31 +0100
Subject: [PATCH] arm64: dts: rockchip: add USB3 host to rock-5b
Enable USB3 host controller for the Radxa ROCK 5 Model B. This adds
USB3 for the upper USB3 port (the one further away from the PCB).
The lower USB3 (closer to the PCB) and the USB-C ports use the RK3588
USB TypeC host controller, which use a different PHY that is not yet
supported upstream.
The lower USB3 and the USB-C ports use the RK3588 USB TypeC host
controller, which use a different PHY without upstream support.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20231106155934.80838-1-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -141,6 +141,10 @@
@@ -138,6 +138,10 @@
status = "okay";
};
@ -28,7 +29,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
@@ -768,3 +772,7 @@
@@ -767,3 +771,7 @@
&usb_host1_ohci {
status = "okay";
};

8
target/linux/rockchip/patches-6.1/103-arm64-dts-rockchip-lower-mmc-speed.patch
View File

@ -57,7 +57,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
status = "okay";
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -360,8 +360,7 @@
@@ -364,8 +364,7 @@
no-sd;
non-removable;
max-frequency = <200000000>;
@ -67,7 +67,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
status = "okay";
};
@@ -372,9 +371,8 @@
@@ -376,9 +375,8 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
@ -80,7 +80,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
status = "okay";
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -357,8 +357,7 @@
@@ -361,8 +361,7 @@
no-sd;
non-removable;
max-frequency = <200000000>;
@ -90,7 +90,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
status = "okay";
};
@@ -366,12 +365,11 @@
@@ -370,12 +369,11 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;

13
target/linux/rockchip/patches-6.1/110-cpufreq-rockchip-Introduce-driver-for-rk3588.patch
View File

@ -1,4 +1,4 @@
From 8da601637e2ed438b83fe56e49dacea84fd3b056 Mon Sep 17 00:00:00 2001
From 8baebef8be9691a28f8efa284dfce9a5b9395130 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 18 Aug 2022 14:21:30 +0200
Subject: [PATCH] cpufreq: rockchip: Introduce driver for rk3588
@ -18,8 +18,8 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
drivers/cpufreq/Kconfig.arm | 10 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/cpufreq-dt-platdev.c | 2 +
drivers/cpufreq/rockchip-cpufreq.c | 640 +++++++++++++++++++++++++++
4 files changed, 653 insertions(+)
drivers/cpufreq/rockchip-cpufreq.c | 645 +++++++++++++++++++++++++++
4 files changed, 658 insertions(+)
create mode 100644 drivers/cpufreq/rockchip-cpufreq.c
--- a/drivers/cpufreq/Kconfig.arm
@ -64,7 +64,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
{ .compatible = "st,stih418", },
--- /dev/null
+++ b/drivers/cpufreq/rockchip-cpufreq.c
@@ -0,0 +1,640 @@
@@ -0,0 +1,645 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Rockchip CPUFreq Driver. This is similar to the generic DT
@ -675,6 +675,11 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+{
+ int ret;
+
+ if (!of_machine_is_compatible("rockchip,rk3588") &&
+ !of_machine_is_compatible("rockchip,rk3588s")) {
+ return -ENODEV;
+ }
+
+ ret = platform_driver_register(&rockchip_cpufreq_platdrv);
+ if (ret)
+ return ret;

26
target/linux/rockchip/patches-6.1/120-01-arm64-dts-rockchip-rk3588-add-cpu-frequency-scaling.patch
View File

@ -25,9 +25,9 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
/ {
compatible = "rockchip,rk3588";
@@ -18,6 +19,215 @@
#address-cells = <2>;
#size-cells = <2>;
@@ -50,6 +51,215 @@
spi4 = &spi4;
};
+ cluster0_opp_table: opp-table-cluster0 {
+ compatible = "operating-points-v2";
@ -241,7 +241,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -64,6 +274,7 @@
@@ -96,6 +306,7 @@
clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clock-rates = <816000000>;
@ -249,7 +249,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -83,6 +294,7 @@
@@ -115,6 +326,7 @@
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
@ -257,7 +257,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -102,6 +314,7 @@
@@ -134,6 +346,7 @@
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
@ -265,7 +265,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -121,6 +334,7 @@
@@ -153,6 +366,7 @@
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
@ -273,7 +273,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -142,6 +356,7 @@
@@ -174,6 +388,7 @@
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clock-rates = <816000000>;
@ -281,7 +281,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -161,6 +376,7 @@
@@ -193,6 +408,7 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
@ -289,7 +289,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -182,6 +398,7 @@
@@ -214,6 +430,7 @@
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clock-rates = <816000000>;
@ -297,7 +297,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -201,6 +418,7 @@
@@ -233,6 +450,7 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
@ -305,7 +305,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -353,6 +571,230 @@
@@ -385,6 +603,230 @@
#clock-cells = <0>;
};
@ -536,7 +536,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
@@ -465,6 +907,16 @@
@@ -497,6 +939,16 @@
reg = <0x0 0xfd58c000 0x0 0x1000>;
};

6
target/linux/rockchip/patches-6.1/120-04-arm64-dts-rockchip-rk3588s-Add-USBDP-phy-nodes.patch
View File

@ -91,7 +91,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
reg = <0x0 0xfee10000 0x0 0x100>;
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -932,6 +932,37 @@
@@ -964,6 +964,37 @@
reg = <0x0 0xfd5c4000 0x0 0x100>;
};
@ -129,7 +129,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5d8000 0x0 0x4000>;
@@ -957,6 +988,17 @@
@@ -989,6 +1020,17 @@
};
};
@ -147,7 +147,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5dc000 0x0 0x4000>;
@@ -2688,6 +2730,37 @@
@@ -2720,6 +2762,37 @@
#dma-cells = <1>;
};

2
target/linux/rockchip/patches-6.1/120-05-arm64-dts-rockchip-rk3588s-Add-USB3-DRD-controllers.patch
View File

@ -42,7 +42,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
reg = <0x0 0xfd5b8000 0x0 0x10000>;
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -832,6 +832,28 @@
@@ -864,6 +864,28 @@
};
};

2
target/linux/rockchip/patches-6.1/120-06-arm64-dts-rockchip-enable-RK3588-tsadc-by-default.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2617,7 +2617,6 @@
@@ -2649,7 +2649,6 @@
pinctrl-1 = <&tsadc_shut>;
pinctrl-names = "gpio", "otpout";
#thermal-sensor-cells = <1>;

2
target/linux/rockchip/patches-6.1/801-05-arm64-dts-rockchip-rk3588s-add-rng-node.patch
View File

@ -11,7 +11,7 @@ Change-Id: Ifb8964053daa6b593dd2c2c6a3b8caab8526e56d
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2030,6 +2030,17 @@
@@ -2062,6 +2062,17 @@
status = "disabled";
};

2
target/linux/rockchip/patches-6.1/801-06-arm64-dts-rockchip-rk3588s-rng-use-scmi_clk.patch
View File

@ -14,7 +14,7 @@ Change-Id: I49994529fcc209c2bc173c1abc497536fb920302
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2034,7 +2034,7 @@
@@ -2066,7 +2066,7 @@
compatible = "rockchip,trngv1";
reg = <0x0 0xfe378000 0x0 0x200>;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;

4
target/linux/rockchip/patches-6.1/994-rockchip-rk3588-unlock-2.4-GHz.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -149,6 +149,12 @@
@@ -181,6 +181,12 @@
<925000 925000 1000000>;
clock-latency-ns = <40000>;
};
@ -13,7 +13,7 @@
};
cluster2_opp_table: opp-table-cluster2 {
@@ -226,6 +232,12 @@
@@ -258,6 +264,12 @@
<925000 925000 1000000>;
clock-latency-ns = <40000>;
};