uboot-rockchip: backport fixes for rkbin
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
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Tianling Shen
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@ -0,0 +1,116 @@
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From eb6c3df5af3fd7d07415a9430138e5f5139b7c31 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Mon, 16 Jan 2023 16:15:05 +0000
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Subject: [PATCH] rockchip: sdram: add basic support for sdram reg info version
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3
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Newer DRAM initialization blobs from vendor can encode sdram info in a
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new version 3 format. The new format makes use of more bits in sys_reg3
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compared to the version 2 format.
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Add basic support for detecting the version 3 format and decoding the
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high bits used for ddrtype.
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This fixes decode of sdram size on my RK3568 boards that have LPDDR4X.
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Details on the new format was deciphered from vendor u-boot commit [1].
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[1] https://github.com/rockchip-linux/u-boot/commit/c69667e0e2bf4290ab1f408fcde58b8806ac266b
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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arch/arm/include/asm/arch-rockchip/sdram.h | 28 +++++++++++++++-------
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arch/arm/mach-rockchip/sdram.c | 9 +++++--
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2 files changed, 26 insertions(+), 11 deletions(-)
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--- a/arch/arm/include/asm/arch-rockchip/sdram.h
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+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
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@@ -8,10 +8,13 @@
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enum {
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DDR4 = 0,
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- DDR3 = 0x3,
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- LPDDR2 = 0x5,
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- LPDDR3 = 0x6,
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- LPDDR4 = 0x7,
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+ DDR3 = 3,
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+ LPDDR2 = 5,
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+ LPDDR3 = 6,
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+ LPDDR4 = 7,
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+ LPDDR4X = 8,
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+ LPDDR5 = 9,
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+ DDR5 = 10,
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UNUSED = 0xFF
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};
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@@ -21,16 +24,16 @@ enum {
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* [30] row_3_4_ch0
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* [29:28] chinfo
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* [27] rank_ch1
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- * [26:25] col_ch1
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+ * [26:25] cs0_col_ch1
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* [24] bk_ch1
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* [23:22] low bits of cs0_row_ch1
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* [21:20] low bits of cs1_row_ch1
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* [19:18] bw_ch1
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- * [17:16] dbw_ch1;
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- * [15:13] ddrtype
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+ * [17:16] dbw_ch1
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+ * [15:13] low bits of ddrtype
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* [12] channelnum
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- * [11] rank_ch0
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- * [10:9] col_ch0,
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+ * [11] low bit of rank_ch0
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+ * [10:9] cs0_col_ch0
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* [8] bk_ch0
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* [7:6] low bits of cs0_row_ch0
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* [5:4] low bits of cs1_row_ch0
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@@ -61,6 +64,11 @@ enum {
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/*
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* sys_reg3 bitfield struct
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+ * [31:28] version
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+ * [16] cs3_delta_row
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+ * [15] cs2_delta_row
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+ * [14] high bit of rank_ch0
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+ * [13:12] high bits of ddrtype
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* [7] high bit of cs0_row_ch1
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* [6] high bit of cs1_row_ch1
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* [5] high bit of cs0_row_ch0
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@@ -70,6 +78,8 @@ enum {
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*/
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#define SYS_REG_VERSION_SHIFT 28
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#define SYS_REG_VERSION_MASK 0xf
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+#define SYS_REG_EXTEND_DDRTYPE_SHIFT 12
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+#define SYS_REG_EXTEND_DDRTYPE_MASK 3
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#define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2)
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#define SYS_REG_EXTEND_CS0_ROW_MASK 1
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#define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) (4 + (ch) * 2)
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--- a/arch/arm/mach-rockchip/sdram.c
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+++ b/arch/arm/mach-rockchip/sdram.c
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@@ -88,9 +88,15 @@ size_t rockchip_sdram_size(phys_addr_t r
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u32 sys_reg3 = readl(reg + 4);
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u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
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& SYS_REG_NUM_CH_MASK);
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+ u32 version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) &
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+ SYS_REG_VERSION_MASK;
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dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
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+ if (version >= 3)
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+ dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
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+ SYS_REG_EXTEND_DDRTYPE_MASK) << 3;
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debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
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+ debug("%s %x %x\n", __func__, (u32)reg + 4, sys_reg3);
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for (ch = 0; ch < ch_num; ch++) {
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rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
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SYS_REG_RANK_MASK);
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@@ -98,8 +104,7 @@ size_t rockchip_sdram_size(phys_addr_t r
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SYS_REG_COL_MASK);
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cs1_col = cs0_col;
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bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
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- if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
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- SYS_REG_VERSION_MASK) == 0x2) {
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+ if (version >= 2) {
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cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
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SYS_REG_CS1_COL_MASK);
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if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
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@ -0,0 +1,38 @@
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From 4ab080257de13d5e859a614bd56c78ff30688588 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sat, 21 Jan 2023 19:01:39 +0000
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Subject: [PATCH] rockchip: Align FIT image data to SD/MMC block length
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SPL load FIT images by reading the data aligned to block length.
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Block length aligned image data is read directly to the load address.
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Unaligned image data is written to an offset of the load address and
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then the data is memcpy to the load address.
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This adds a small overhead of having to memcpy unaligned data, something
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that normally is not an issue.
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However, TF-A may have a segment that should be loaded into SRAM, e.g.
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vendor TF-A for RK3568 has a 8KiB segment that should be loaded into the
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8KiB PMU SRAM. Having the image data for such segment unaligned result
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in segment being written to and memcpy from beyond the SRAM boundary, in
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the end this results in invalid data in SRAM.
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Aligning the FIT and its external data to MMC block length to work
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around such issue.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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Makefile | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/Makefile
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+++ b/Makefile
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@@ -1450,7 +1450,7 @@ MKIMAGEFLAGS_u-boot.itb =
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else
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MKIMAGEFLAGS_u-boot.itb = -E
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endif
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-MKIMAGEFLAGS_u-boot.itb += -B 0x8
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+MKIMAGEFLAGS_u-boot.itb += -B 0x200
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ifdef U_BOOT_ITS
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u-boot.itb: u-boot-nodtb.bin \
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