diff --git a/target/linux/ath79/Makefile b/target/linux/ath79/Makefile index cfdf8c87e5..9b203cf48e 100644 --- a/target/linux/ath79/Makefile +++ b/target/linux/ath79/Makefile @@ -4,11 +4,12 @@ ARCH:=mips BOARD:=ath79 BOARDNAME:=Atheros ATH79 (DTS) CPU_TYPE:=24kc -SUBTARGETS:=generic nand tiny +SUBTARGETS:=generic mikrotik nand tiny FEATURES:=ramdisk KERNEL_PATCHVER:=4.19 +KERNEL_TESTING_PATCHVER:=5.4 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/ath79/config-4.14 b/target/linux/ath79/config-5.4 similarity index 81% rename from target/linux/ath79/config-4.14 rename to target/linux/ath79/config-5.4 index 1ff3f12728..d591f884e7 100644 --- a/target/linux/ath79/config-4.14 +++ b/target/linux/ath79/config-5.4 @@ -3,27 +3,25 @@ CONFIG_AG71XX=y CONFIG_AG71XX_DEBUG_FS=y CONFIG_AR8216_PHY=y CONFIG_AR8216_PHY_LEDS=y -CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_32BIT_OFF_T=y CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y -# CONFIG_ARCH_HAS_SG_CHAIN is not set -# CONFIG_ARCH_HAS_STRICT_KERNEL_RWX is not set -# CONFIG_ARCH_HAS_STRICT_MODULE_RWX is not set +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_ARCH_MMAP_RND_BITS_MAX=15 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_ATH79=y CONFIG_ATH79_WDT=y @@ -36,8 +34,10 @@ CONFIG_CMDLINE_BOOL=y # CONFIG_CMDLINE_OVERRIDE is not set CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_BOSTON is not set +CONFIG_COMPAT_32BIT_TIME=y CONFIG_CPU_BIG_ENDIAN=y CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_LOAD_STORE_LR=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y @@ -46,26 +46,36 @@ CONFIG_CPU_MIPS32_R2=y CONFIG_CPU_MIPSR2=y CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_R4K_FPU=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_CPU_SUPPORTS_MSA=y CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y CONFIG_DTC=y CONFIG_EARLY_PRINTK=y +CONFIG_EFI_EARLYCON=y CONFIG_ETHERNET_PACKET_MANGLE=y CONFIG_FIXED_PHY=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_IO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOMAP=y CONFIG_GENERIC_IRQ_CHIP=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PINCONF=y @@ -80,21 +90,17 @@ CONFIG_GPIO_74X164=y CONFIG_GPIO_ATH79=y CONFIG_GPIO_GENERIC=y CONFIG_GPIO_SYSFS=y -# CONFIG_GRO_CELLS is not set CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HARDWARE_WATCHPOINTS=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_HAVE_ARCH_COMPILER_H=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CBPF_JIT=y -CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_HAVE_CONTEXT_TRACKING=y @@ -102,28 +108,29 @@ CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_API_DEBUG=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FAST_GUP=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_VDSO=y CONFIG_HAVE_IDE=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_KVM=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y CONFIG_HAVE_MEMBLOCK_NODE_MAP=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_HAVE_NET_DSA=y CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PCI=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HW_HAS_PCI=y CONFIG_HZ_PERIODIC=y CONFIG_IMAGE_CMDLINE_HACK=y CONFIG_INITRAMFS_SOURCE="" @@ -135,11 +142,14 @@ CONFIG_IRQ_WORK=y CONFIG_LEDS_GPIO=y # CONFIG_LEDS_RESET is not set CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_MDIO_BITBANG=y CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_GPIO=y +CONFIG_MEMFD_CREATE=y CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y CONFIG_MIPS=y CONFIG_MIPS_ASID_BITS=8 CONFIG_MIPS_ASID_SHIFT=0 @@ -149,9 +159,7 @@ CONFIG_MIPS_CLOCK_VSYSCALL=y # CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set CONFIG_MIPS_CMDLINE_FROM_DTB=y # CONFIG_MIPS_ELF_APPENDED_DTB is not set -# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MACHINE is not set # CONFIG_MIPS_NO_APPENDED_DTB is not set CONFIG_MIPS_RAW_APPENDED_DTB=y CONFIG_MIPS_SPRAM=y @@ -161,13 +169,11 @@ CONFIG_MTD_CFI_GEOMETRY=y # CONFIG_MTD_CFI_I2 is not set # CONFIG_MTD_CFI_INTELEXT is not set CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_M25P80=y # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set # CONFIG_MTD_MAP_BANK_WIDTH_4 is not set CONFIG_MTD_PARSER_CYBERTAN=y CONFIG_MTD_PHYSMAP=y CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y CONFIG_MTD_SPLIT_LZMA_FW=y CONFIG_MTD_SPLIT_SEAMA_FW=y CONFIG_MTD_SPLIT_TPLINK_FW=y @@ -177,18 +183,16 @@ CONFIG_MTD_VIRT_CONCAT=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_PER_CPU_KM=y CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -# CONFIG_NO_IOPORT_MAP is not set +CONFIG_NVMEM=y CONFIG_OF=y CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_FLATTREE=y CONFIG_OF_GPIO=y CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y CONFIG_PCI=y CONFIG_PCI_AR71XX=y CONFIG_PCI_AR724X=y @@ -200,28 +204,27 @@ CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y # CONFIG_PHY_AR7100_USB is not set # CONFIG_PHY_AR7200_USB is not set +# CONFIG_PHY_ATH79_USB is not set CONFIG_PINCTRL=y CONFIG_RATIONAL=y -# CONFIG_RCU_NEED_SEGCBLIST is not set -# CONFIG_RCU_STALL_COMMON is not set CONFIG_REGMAP=y CONFIG_REGMAP_MMIO=y CONFIG_RESET_ATH79=y CONFIG_RESET_CONTROLLER=y -# CONFIG_SCHED_INFO is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SERIAL_8250_FSL is not set CONFIG_SERIAL_8250_NR_UARTS=1 CONFIG_SERIAL_8250_RUNTIME_UARTS=1 CONFIG_SERIAL_AR933X=y CONFIG_SERIAL_AR933X_CONSOLE=y CONFIG_SERIAL_AR933X_NR_UARTS=2 +CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SPI=y +CONFIG_SPI_AR934X=y CONFIG_SPI_ATH79=y CONFIG_SPI_BITBANG=y CONFIG_SPI_GPIO=y CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y # CONFIG_SPI_RB4XX is not set CONFIG_SRCU=y CONFIG_SWCONFIG=y @@ -236,7 +239,9 @@ CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_SYS_SUPPORTS_MIPS16=y CONFIG_SYS_SUPPORTS_ZBOOT=y CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y +CONFIG_TARGET_ISA_REV=2 CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TINY_SRCU=y CONFIG_USB_SUPPORT=y CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dts b/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dts index e87f422051..b3855eff06 100644 --- a/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dts +++ b/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dts @@ -234,14 +234,14 @@ flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <104000000>; + spi-max-frequency = <50000000>; m25p,fast-read; }; flash1: flash@1 { compatible = "jedec,spi-nor"; reg = <1>; - spi-max-frequency = <104000000>; + spi-max-frequency = <50000000>; m25p,fast-read; }; }; diff --git a/target/linux/ath79/dts/ar7240_ubnt_bullet-m-ar7240.dts b/target/linux/ath79/dts/ar7240_ubnt_bullet-m-ar7240.dts new file mode 100644 index 0000000000..58b35f5c8b --- /dev/null +++ b/target/linux/ath79/dts/ar7240_ubnt_bullet-m-ar7240.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "ar7240.dtsi" +#include "ar724x_ubnt_xm.dtsi" +#include "ar724x_ubnt_xm_outdoor.dtsi" + +/ { + compatible = "ubnt,bullet-m-ar7240", "ubnt,xm", "qca,ar7240"; + model = "Ubiquiti Bullet M XM (AR7240)"; +}; + +ð0 { + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +ð1 { + compatible = "syscon", "simple-mfd"; +}; diff --git a/target/linux/ath79/dts/ar7241_ubnt_airrouter.dts b/target/linux/ath79/dts/ar7241_ubnt_airrouter.dts index ad2762e20c..dd2421da8e 100644 --- a/target/linux/ath79/dts/ar7241_ubnt_airrouter.dts +++ b/target/linux/ath79/dts/ar7241_ubnt_airrouter.dts @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include "ar7241_ubnt_xm.dtsi" +#include "ar7241.dtsi" +#include "ar724x_ubnt_xm.dtsi" / { compatible = "ubnt,airrouter", "ubnt,xm", "qca,ar7241"; diff --git a/target/linux/ath79/dts/ar7241_ubnt_bullet-m-ar7241.dts b/target/linux/ath79/dts/ar7241_ubnt_bullet-m-ar7241.dts new file mode 100644 index 0000000000..0e2183c27d --- /dev/null +++ b/target/linux/ath79/dts/ar7241_ubnt_bullet-m-ar7241.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "ar7241.dtsi" +#include "ar724x_ubnt_xm.dtsi" +#include "ar724x_ubnt_xm_outdoor.dtsi" + +/ { + compatible = "ubnt,bullet-m-ar7241", "ubnt,xm", "qca,ar7241"; + model = "Ubiquiti Bullet M XM (AR7241)"; +}; + +ð1 { + compatible = "syscon", "simple-mfd"; +}; diff --git a/target/linux/ath79/dts/ar7241_ubnt_bullet-m.dts b/target/linux/ath79/dts/ar7241_ubnt_bullet-m.dts deleted file mode 100644 index e16b5fa0be..0000000000 --- a/target/linux/ath79/dts/ar7241_ubnt_bullet-m.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/dts-v1/; - -#include "ar7241_ubnt_xm_outdoor.dtsi" - -/ { - compatible = "ubnt,bullet-m", "ubnt,xm", "qca,ar7241"; - model = "Ubiquiti Bullet M"; -}; - -ð1 { - compatible = "syscon", "simple-mfd"; -}; diff --git a/target/linux/ath79/dts/ar7241_ubnt_nanobridge-m.dts b/target/linux/ath79/dts/ar7241_ubnt_nanobridge-m.dts new file mode 100644 index 0000000000..005ef27caa --- /dev/null +++ b/target/linux/ath79/dts/ar7241_ubnt_nanobridge-m.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "ar7241.dtsi" +#include "ar724x_ubnt_xm.dtsi" +#include "ar724x_ubnt_xm_outdoor.dtsi" + +/ { + compatible = "ubnt,nanobridge-m", "ubnt,xm", "qca,ar7241"; + model = "Ubiquiti NanoBridge M"; +}; + +ð1 { + compatible = "syscon", "simple-mfd"; +}; diff --git a/target/linux/ath79/dts/ar7241_ubnt_nanostation-loco-m.dts b/target/linux/ath79/dts/ar7241_ubnt_nanostation-loco-m.dts index 386b7c7073..60d5a21a22 100644 --- a/target/linux/ath79/dts/ar7241_ubnt_nanostation-loco-m.dts +++ b/target/linux/ath79/dts/ar7241_ubnt_nanostation-loco-m.dts @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include "ar7241_ubnt_xm_outdoor.dtsi" +#include "ar7241.dtsi" +#include "ar724x_ubnt_xm.dtsi" +#include "ar724x_ubnt_xm_outdoor.dtsi" / { compatible = "ubnt,nanostation-loco-m", "ubnt,xm", "qca,ar7241"; diff --git a/target/linux/ath79/dts/ar7241_ubnt_nanostation-m.dts b/target/linux/ath79/dts/ar7241_ubnt_nanostation-m.dts index eebe65e53f..82344bb5ea 100644 --- a/target/linux/ath79/dts/ar7241_ubnt_nanostation-m.dts +++ b/target/linux/ath79/dts/ar7241_ubnt_nanostation-m.dts @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include "ar7241_ubnt_xm_outdoor.dtsi" +#include "ar7241.dtsi" +#include "ar724x_ubnt_xm.dtsi" +#include "ar724x_ubnt_xm_outdoor.dtsi" / { compatible = "ubnt,nanostation-m", "ubnt,xm", "qca,ar7241"; diff --git a/target/linux/ath79/dts/ar7241_ubnt_picostation-m.dts b/target/linux/ath79/dts/ar7241_ubnt_picostation-m.dts index e2376a1b92..d05aca3e67 100644 --- a/target/linux/ath79/dts/ar7241_ubnt_picostation-m.dts +++ b/target/linux/ath79/dts/ar7241_ubnt_picostation-m.dts @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include "ar7241_ubnt_xm_outdoor.dtsi" +#include "ar7241.dtsi" +#include "ar724x_ubnt_xm.dtsi" +#include "ar724x_ubnt_xm_outdoor.dtsi" / { compatible = "ubnt,picostation-m", "ubnt,xm", "qca,ar7241"; diff --git a/target/linux/ath79/dts/ar7241_ubnt_rocket-m.dts b/target/linux/ath79/dts/ar7241_ubnt_rocket-m.dts index 35f5205b41..9e342177e2 100644 --- a/target/linux/ath79/dts/ar7241_ubnt_rocket-m.dts +++ b/target/linux/ath79/dts/ar7241_ubnt_rocket-m.dts @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include "ar7241_ubnt_xm_outdoor.dtsi" +#include "ar7241.dtsi" +#include "ar724x_ubnt_xm.dtsi" +#include "ar724x_ubnt_xm_outdoor.dtsi" / { compatible = "ubnt,rocket-m", "ubnt,xm", "qca,ar7241"; diff --git a/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts b/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts index e6ea8b68e2..e85ac8f5f8 100644 --- a/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts +++ b/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts @@ -109,6 +109,7 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <25000000>; + m25p,fast-read; partitions { compatible = "fixed-partitions"; diff --git a/target/linux/ath79/dts/ar724x.dtsi b/target/linux/ath79/dts/ar724x.dtsi index 95832d998a..2d7383c36d 100644 --- a/target/linux/ath79/dts/ar724x.dtsi +++ b/target/linux/ath79/dts/ar724x.dtsi @@ -130,6 +130,9 @@ interrupt-parent = <&cpuintc>; interrupts = <2>; + resets = <&rst 6>, <&rst 7>; + reset-names = "hc", "phy"; + interrupt-controller; #interrupt-cells = <1>; diff --git a/target/linux/ath79/dts/ar7241_ubnt_xm.dtsi b/target/linux/ath79/dts/ar724x_ubnt_xm.dtsi similarity index 92% rename from target/linux/ath79/dts/ar7241_ubnt_xm.dtsi rename to target/linux/ath79/dts/ar724x_ubnt_xm.dtsi index e2b653b3a7..b36b0d4fe2 100644 --- a/target/linux/ath79/dts/ar7241_ubnt_xm.dtsi +++ b/target/linux/ath79/dts/ar724x_ubnt_xm.dtsi @@ -3,12 +3,7 @@ #include #include -#include "ar7241.dtsi" - / { - compatible = "ubnt,xm", "qca,ar7241"; - model = "Ubiquiti Networks XM (rev 1.0) board"; - keys { compatible = "gpio-keys"; diff --git a/target/linux/ath79/dts/ar7241_ubnt_xm_outdoor.dtsi b/target/linux/ath79/dts/ar724x_ubnt_xm_outdoor.dtsi similarity index 94% rename from target/linux/ath79/dts/ar7241_ubnt_xm_outdoor.dtsi rename to target/linux/ath79/dts/ar724x_ubnt_xm_outdoor.dtsi index 75116edc51..a28f8fbcd4 100644 --- a/target/linux/ath79/dts/ar7241_ubnt_xm_outdoor.dtsi +++ b/target/linux/ath79/dts/ar724x_ubnt_xm_outdoor.dtsi @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "ar7241_ubnt_xm.dtsi" - / { aliases { led-boot = &led_link4; diff --git a/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts b/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts index 846e517de8..c16bcb05f7 100644 --- a/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts +++ b/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts @@ -112,6 +112,7 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <25000000>; + m25p,fast-read; partitions { compatible = "fixed-partitions"; diff --git a/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts b/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts index 70754c905e..68e1995c76 100644 --- a/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts +++ b/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts @@ -86,7 +86,7 @@ flash@0 { compatible = "jedec,spi-nor"; - spi-max-frequency = <104000000>; + spi-max-frequency = <50000000>; reg = <0>; partitions { diff --git a/target/linux/ath79/dts/ar9330_pqi_air-pen.dts b/target/linux/ath79/dts/ar9330_pqi_air-pen.dts index 92484f9331..8537faa0f9 100644 --- a/target/linux/ath79/dts/ar9330_pqi_air-pen.dts +++ b/target/linux/ath79/dts/ar9330_pqi_air-pen.dts @@ -75,7 +75,7 @@ flash@0 { compatible = "jedec,spi-nor"; - spi-max-frequency = <104000000>; + spi-max-frequency = <50000000>; reg = <0>; partitions { diff --git a/target/linux/ath79/dts/ar9331_8dev_carambola2.dts b/target/linux/ath79/dts/ar9331_8dev_carambola2.dts index cc0320d652..ef244f0b55 100644 --- a/target/linux/ath79/dts/ar9331_8dev_carambola2.dts +++ b/target/linux/ath79/dts/ar9331_8dev_carambola2.dts @@ -73,7 +73,7 @@ flash@0 { compatible = "jedec,spi-nor"; - spi-max-frequency = <104000000>; + spi-max-frequency = <50000000>; reg = <0>; partitions { diff --git a/target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts b/target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts index 3489a972d4..349c7ffc4d 100644 --- a/target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts +++ b/target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts @@ -33,7 +33,7 @@ wps { label = "wps"; linux,code = ; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; }; reset { @@ -68,7 +68,7 @@ flash@0 { compatible = "jedec,spi-nor"; - spi-max-frequency = <104000000>; + spi-max-frequency = <50000000>; reg = <0>; partitions { diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts b/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts index 3cd5c130c8..97a058edf6 100644 --- a/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts +++ b/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts @@ -120,7 +120,7 @@ /* Spansion S25FL032PIF SPI flash */ flash@0 { compatible = "jedec,spi-nor"; - spi-max-frequency = <104000000>; + spi-max-frequency = <50000000>; reg = <0>; partitions { diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts b/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts index e8a3dfbce7..5918e611dd 100644 --- a/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts +++ b/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts @@ -114,7 +114,7 @@ flash@0 { compatible = "jedec,spi-nor"; - spi-max-frequency = <104000000>; + spi-max-frequency = <50000000>; reg = <0>; partitions { diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr740n-v5.dts b/target/linux/ath79/dts/ar9331_tplink_tl-wr740n-v5.dts new file mode 100644 index 0000000000..a031bf3875 --- /dev/null +++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr740n-v5.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "ar9331_tplink_tl-wr741nd-v4.dtsi" + +/ { + model = "TP-Link TL-WR740N v5"; + compatible = "tplink,tl-wr740n-v5", "qca,ar9331"; +}; diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wa860re-v1.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wa860re-v1.dts new file mode 100644 index 0000000000..237a40d693 --- /dev/null +++ b/target/linux/ath79/dts/ar9341_tplink_tl-wa860re-v1.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "ar9341_tplink_tl-wa.dtsi" + +/ { + model = "TP-Link TL-WA860RE v1"; + compatible = "tplink,tl-wa860re-v1", "qca,ar9341"; + + aliases { + led-boot = &led_power_green; + led-failsafe = &led_power_orange; + led-running = &led_power_green; + led-upgrade = &led_power_orange; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "Reset"; + linux,code = ; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + + onoff { + label = "ONOFF"; + linux,code = ; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + lan { + label = "tp-link:green:lan"; + gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + }; + + led_power_green: power_green { + label = "tp-link:green:power"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_power_orange: power_orange { + label = "tp-link:orange:power"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + + wlan_green { + label = "tp-link:green:wlan"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + wlan_orange { + label = "tp-link:orange:wlan"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/target/linux/ath79/dts/ar9344.dtsi b/target/linux/ath79/dts/ar9344.dtsi index de118e9a3b..e99d962933 100644 --- a/target/linux/ath79/dts/ar9344.dtsi +++ b/target/linux/ath79/dts/ar9344.dtsi @@ -46,6 +46,9 @@ interrupt-parent = <&intc2>; interrupts = <1>; + resets = <&rst 6>, <&rst 7>; + reset-names = "hc", "phy"; + interrupt-controller; #interrupt-cells = <1>; diff --git a/target/linux/ath79/dts/ar9344_devolo_magic-2-wifi.dts b/target/linux/ath79/dts/ar9344_devolo_magic-2-wifi.dts new file mode 100644 index 0000000000..4f58cd5c37 --- /dev/null +++ b/target/linux/ath79/dts/ar9344_devolo_magic-2-wifi.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "ar9344.dtsi" + +/ { + model = "Devolo Magic 2 Wifi"; + compatible = "devolo,magic-2-wifi", "qca,ar9344"; + + aliases { + led-boot = &led_dlan_red; + led-failsafe = &led_dlan_red; + led-running = &led_dlan_white; + led-upgrade = &led_dlan_red; + }; + + leds { + compatible = "gpio-leds"; + + wlan { + label = "devolo:white:wlan"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led_dlan_white: dlan_white { + label = "devolo:white:dlan"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + + led_dlan_red: dlan_red { + label = "devolo:red:dlan"; + gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + panic-indicator; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "Reset button"; + linux,code = ; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + + wifi { + label = "WIFI button"; + linux,code = ; + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; + debounce-interval = <60>; + }; + + dlan { + label = "DLAN button"; + linux,code = ; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; +}; + +&gpio { + status = "okay"; + + wlan_power { + gpio-hog; + line-name = "WLAN power"; + gpios = <&gpio 21 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&spi { + status = "okay"; + + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + uboot: partition@0 { + label = "u-boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "Config1"; + reg = <0x50000 0x10000>; + read-only; + }; + + partition@60000 { + label = "Config2"; + reg = <0x60000 0x10000>; + read-only; + }; + + partition@70000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x70000 0xf80000>; + }; + + art: partition@ff0000 { + label = "art"; + reg = <0xff0000 0x10000>; + read-only; + }; + }; + }; +}; + +&ref { + clock-frequency = <40000000>; +}; + +&uart { + status = "okay"; +}; + +ð0 { + status = "okay"; + + pll-data = <0x02000000 0x00000101 0x00001616>; + + mtd-mac-address = <&art 0x1002>; + mtd-mac-address-increment = <2>; + + phy-mode = "rgmii"; + phy-handle = <&phy0>; +}; + +&wmac { + status = "okay"; + + mtd-cal-data = <&art 0x1000>; +}; + +&pcie { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0 0 0 0 0>; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "rgmii"; + + qca,ar8327-initvals = < + /* PORT0: RGMII, MAC0/6 exchage, tx_delay 01, No rx_delay */ + 0x04 0x06400000 + 0x08 0x00000000 /* PORT5 PAD MODE CTRL */ + 0x0c 0x00000000 /* PORT6 PAD MODE CTRL */ + 0x7c 0x0000007e /* PORT0_STATUS */ + >; + }; +}; diff --git a/target/linux/ath79/dts/ar9344_tplink_tl-wdr4310-v1.dts b/target/linux/ath79/dts/ar9344_tplink_tl-wdr4310-v1.dts new file mode 100644 index 0000000000..3fa4af518b --- /dev/null +++ b/target/linux/ath79/dts/ar9344_tplink_tl-wdr4310-v1.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "ar9344_tplink_tl-wdr4300.dtsi" + +/ { + model = "TP-Link TL-WDR4310 v1"; + compatible = "tplink,tl-wdr4310-v1", "qca,ar9344"; +}; diff --git a/target/linux/ath79/dts/ar934x.dtsi b/target/linux/ath79/dts/ar934x.dtsi index e8c21fb710..0451960a60 100644 --- a/target/linux/ath79/dts/ar934x.dtsi +++ b/target/linux/ath79/dts/ar934x.dtsi @@ -232,6 +232,8 @@ pll-handle = <&pll>; resets = <&rst 9>, <&rst 22>; reset-names = "mac", "mdio"; + clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; + clock-names = "eth", "mdio"; }; &mdio1 { @@ -272,8 +274,10 @@ ð1 { compatible = "qca,ar9340-eth", "syscon"; - resets = <&rst 13>; - reset-names = "mac"; + resets = <&rst 13>, <&rst 23>; + reset-names = "mac", "mdio"; + clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; + clock-names = "eth", "mdio"; phy-mode = "gmii"; fixed-link { diff --git a/target/linux/ath79/dts/ath79.dtsi b/target/linux/ath79/dts/ath79.dtsi index c351272025..1d1424590c 100644 --- a/target/linux/ath79/dts/ath79.dtsi +++ b/target/linux/ath79/dts/ath79.dtsi @@ -49,7 +49,7 @@ interrupts = <4>; phy-mode = "mii"; - mdio0: mdio-bus { + mdio0: mdio { status = "disabled"; compatible = "qca,ath79-mdio"; @@ -72,7 +72,7 @@ interrupts = <5>; phy-mode = "mii"; - mdio1: mdio-bus { + mdio1: mdio { status = "disabled"; compatible = "qca,ath79-mdio"; diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts b/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts new file mode 100644 index 0000000000..06c8f0737e --- /dev/null +++ b/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "qca953x.dtsi" + +/ { + compatible = "comfast,cf-ew72", "qca,qca9531"; + model = "COMFAST CF-EW72"; + + aliases { + serial0 = &uart; + led-boot = &led_wan; + led-failsafe = &led_wan; + led-upgrade = &led_wan; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&jtag_disable_pins>; + + lan { + label = "cf-ew72:blue:lan"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + }; + + led_wan: wan { + label = "cf-ew72:blue:wan"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; + + wlan { + label = "cf-ew72:blue:wlan"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + watchdog { + compatible = "linux,wdt-gpio"; + + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + hw_algo = "toggle"; + hw_margin_ms = <1200>; + always-running; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&spi { + status = "okay"; + + num-cs = <1>; + + flash@0 { + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x010000>; + read-only; + }; + + art: partition@10000 { + label = "art"; + reg = <0x010000 0x010000>; + read-only; + }; + + partition@20000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x020000 0xfd0000>; + }; + + partition@ff0000 { + label = "nvram"; + reg = <0xff0000 0x010000>; + read-only; + }; + }; + }; +}; + +&uart { + status = "okay"; +}; + +ð0 { + status = "okay"; + + phy-handle = <&swphy4>; + mtd-mac-address = <&art 0x0>; + mtd-mac-address-increment = <1>; +}; + +ð1 { + mtd-mac-address = <&art 0x0>; +}; + +&wmac { + status = "okay"; + + mtd-cal-data = <&art 0x1000>; + mtd-mac-address = <&art 0x0>; + mtd-mac-address-increment = <3>; +}; diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts b/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts new file mode 100644 index 0000000000..4530c59031 --- /dev/null +++ b/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "qca953x.dtsi" + +/ { + compatible = "comfast,cf-wr752ac-v1", "qca,qca9531"; + model = "COMFAST CF-WR752AC v1"; + + aliases { + serial0 = &uart; + led-boot = &led_lan; + led-failsafe = &led_lan; + led-upgrade = &led_lan; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&jtag_disable_pins &pinmux_led_rssihigh &pinmux_led_rssilow>; + + led_lan: lan { + label = "cf-wr752ac-v1:blue:lan"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + + rssihigh { + label = "cf-wr752ac-v1:green:rssihigh"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + + rssilow { + label = "cf-wr752ac-v1:red:rssilow"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; + }; + + keys { + compatible = "gpio-keys"; + + button { + label = "reset"; + linux,code = ; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; +}; + +&pinmux { + pinmux_led_rssihigh: pinmux_led_rssihigh { + pinctrl-single,bits = <0xc 0x0 0xff000000>; + }; + + pinmux_led_rssilow: pinmux_led_rssilow { + pinctrl-single,bits = <0x8 0x0 0xff000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&spi { + status = "okay"; + + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x010000>; + read-only; + }; + + art: partition@10000 { + label = "art"; + reg = <0x010000 0x010000>; + read-only; + }; + + partition@20000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x020000 0xfd0000>; + }; + + partition@ff0000 { + label = "nvram"; + reg = <0xff0000 0x010000>; + read-only; + }; + }; + }; +}; + +&uart { + status = "okay"; +}; + +ð0 { + status = "okay"; + + phy-handle = <&swphy4>; + + mtd-mac-address = <&art 0x0>; +}; + +ð1 { + compatible = "syscon", "simple-mfd"; +}; + +&wmac { + status = "okay"; + + mtd-cal-data = <&art 0x1000>; + + mtd-mac-address = <&art 0x0>; + mtd-mac-address-increment = <10>; +}; diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts b/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts index 2697792123..dcffccf0a8 100644 --- a/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts +++ b/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts @@ -11,6 +11,10 @@ model = "GL.iNet GL-AR750"; aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; label-mac-device = ð0; }; @@ -36,7 +40,7 @@ leds { compatible = "gpio-leds"; - power { + led_power: power { label = "gl-ar750:white:power"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; default-state = "on"; diff --git a/target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts b/target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts new file mode 100644 index 0000000000..be0387830a --- /dev/null +++ b/target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "qca953x.dtsi" + +/ { + compatible = "tplink,tl-mr3420-v3", "qca,qca9531"; + model = "TP-Link TL-MR3420 v3"; + + aliases { + led-boot = &led_system; + led-failsafe = &led_system; + led-running = &led_system; + led-upgrade = &led_system; + label-mac-device = &wmac; + + }; + + led_spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio 13 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + led_gpio: led_gpio@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + registers-number = <1>; + spi-max-frequency = <10000000>; + }; + }; + + gpio-export { + compatible = "gpio-export"; + + gpio_shift_register_oe { + gpio-export,name = "tp-link:oe:sr"; + gpio-export,output = <0>; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; + + gpio_shift_register_reset { + gpio-export,name = "tp-link:reset:sr"; + gpio-export,output = <1>; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_system: system { + label = "tp-link:green:system"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + lan4 { + label = "tp-link:green:lan4"; + gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>; + }; + + lan3 { + label = "tp-link:green:lan3"; + gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>; + }; + + lan2 { + label = "tp-link:green:lan2"; + gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>; + }; + + lan1 { + label = "tp-link:green:lan1"; + gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>; + }; + + wan { + label = "tp-link:green:wan"; + gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>; + }; + + wan_fail { + label = "tp-link:orange:wan"; + gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>; + }; + + wlan { + label = "tp-link:green:wlan"; + gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + usb { + label = "tp-link:green:usb"; + gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>; + trigger-sources = <&hub_port>; + linux,default-trigger = "usbport"; + }; + + qss { + label = "tp-link:green:qss"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "Reset button"; + linux,code = ; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + + rfkill { + label = "RF kill button"; + linux,code = ; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + +}; + +&uart { + status = "okay"; +}; + +&spi { + status = "okay"; + + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + uboot: partition@0 { + label = "u-boot"; + reg = <0x000000 0x020000>; + read-only; + }; + + partition@20000 { + compatible = "tplink,firmware"; + label = "firmware"; + reg = <0x020000 0x3d0000>; + }; + + art: partition@3f0000 { + label = "art"; + reg = <0x3f0000 0x010000>; + read-only; + }; + }; + }; +}; + +ð1 { + mtd-mac-address = <&uboot 0x1fc00>; +}; + +ð0 { + status = "okay"; + + phy-handle = <&swphy4>; + + mtd-mac-address = <&uboot 0x1fc00>; + mtd-mac-address-increment = <1>; +}; + +&wmac { + status = "okay"; + + mtd-cal-data = <&art 0x1000>; + mtd-mac-address = <&uboot 0x1fc00>; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_port: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; + +&usb_phy { + status = "okay"; +}; diff --git a/target/linux/ath79/dts/qca953x.dtsi b/target/linux/ath79/dts/qca953x.dtsi index e359badd2b..f7e0703e4e 100644 --- a/target/linux/ath79/dts/qca953x.dtsi +++ b/target/linux/ath79/dts/qca953x.dtsi @@ -164,6 +164,9 @@ interrupt-parent = <&intc2>; interrupts = <1>; + resets = <&rst 6>, <&rst 7>; + reset-names = "hc", "phy"; + interrupt-controller; #interrupt-cells = <1>; diff --git a/target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi b/target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi new file mode 100644 index 0000000000..b1f5f1bdb3 --- /dev/null +++ b/target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "qca9557.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + keys { + compatible = "gpio-keys"; + + wps { + label = "wps"; + linux,code = ; + gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&uart { + status = "okay"; +}; + +&spi { + status = "okay"; + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "urlader"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + compatible = "avm,eva-firmware"; + label = "firmware"; + reg = <0x20000 0xee0000>; + }; + + partition@f00000 { + label = "tffs (1)"; + reg = <0xf00000 0x80000>; + read-only; + }; + + partition@f80000 { + label = "tffs (2)"; + reg = <0xf80000 0x80000>; + read-only; + }; + }; + }; +}; + +&wmac { + status = "okay"; + qca,no-eeprom; +}; + +ð1 { + status = "okay"; + + phy-handle = <&phy0>; + pll-data = <0x3000000 0x101 0x1313>; + + gmac-config { + device = <&gmac>; + ge0-sgmii = <0>; + }; +}; + +&mdio1 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; diff --git a/target/linux/ath79/dts/qca9556_avm_fritz1750e.dts b/target/linux/ath79/dts/qca9556_avm_fritz1750e.dts new file mode 100644 index 0000000000..25d3ae8da4 --- /dev/null +++ b/target/linux/ath79/dts/qca9556_avm_fritz1750e.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include + +#include "qca9556_avm_fritz-repeater.dtsi" + +/ { + compatible = "avm,fritz1750e", "qca,qca9557"; + model = "AVM FRITZ!WLAN Repeater 1750E"; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + led_spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + num-chipselects = <0>; + + spi_gpio: led_gpio@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + registers-number = <1>; + spi-max-frequency = <10000000>; + + gpio_latch_bit { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "gpio-latch-bit"; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_power: power { + label = "fritz1750e:green:power"; + gpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>; + }; + + wlan { + label = "fritz1750e:green:wlan"; + gpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy1tpt"; + }; + + lan { + label = "fritz1750e:green:lan"; + gpios = <&gpio 13 GPIO_ACTIVE_HIGH>; + }; + + rssi0 { + label = "fritz1750e:green:rssi0"; + gpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>; + }; + + rssi1 { + label = "fritz1750e:green:rssi1"; + gpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>; + }; + + rssi2 { + label = "fritz1750e:green:rssi2"; + gpios = <&spi_gpio 2 GPIO_ACTIVE_HIGH>; + }; + + rssi3 { + label = "fritz1750e:green:rssi3"; + gpios = <&spi_gpio 3 GPIO_ACTIVE_HIGH>; + }; + + rssi4 { + label = "fritz1750e:green:rssi4"; + gpios = <&spi_gpio 4 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&phy0 { + reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>; +}; + +&gpio { + reset-pcie-ep { + gpio-hog; + gpios = <17 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE EP reset"; + }; + + reset-pcie { + gpio-hog; + gpios = <18 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE Bus reset"; + }; +}; diff --git a/target/linux/ath79/dts/qca9556_avm_fritz450e.dts b/target/linux/ath79/dts/qca9556_avm_fritz450e.dts new file mode 100644 index 0000000000..60685bd3f1 --- /dev/null +++ b/target/linux/ath79/dts/qca9556_avm_fritz450e.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include + +#include "qca9556_avm_fritz-repeater.dtsi" + +/ { + compatible = "avm,fritz450e", "qca,qca9557"; + model = "AVM FRITZ!WLAN Repeater 450E"; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + leds { + compatible = "gpio-leds"; + + led_power: power { + label = "fritz450e:green:power"; + gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; + }; + + wlan { + label = "fritz450e:green:wlan"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + lan { + label = "fritz450e:green:lan"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + }; + + rssi2 { + label = "fritz450e:green:rssi2"; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + }; + + rssi3 { + label = "fritz450e:green:rssi3"; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + }; + + rssi4 { + label = "fritz450e:green:rssi4"; + gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + /* + * Wondered why rssi0 and rssi1 are missing? + * + * AVM seems to have run low on usable GPIO pins, so + * instead of adding a shift register like they did for + * the 1750E they figured out "Why not use the LEDs on + * the AR8033?". + * + * EVA configures the PHY in a way it does not display + * the link-state using it's LEDs. When we reset the PHY + * using the reset-mechanism of the PHY subsystem, this + * setting is cleared. + * + * We avoid this by keeping the reset line high. + */ + phy-reset { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "phy-reset"; + }; +}; diff --git a/target/linux/ath79/dts/qca9556_mikrotik_routerboard-wap-g-5hact2hnd.dts b/target/linux/ath79/dts/qca9556_mikrotik_routerboard-wap-g-5hact2hnd.dts index e13b58b600..529ac1cf3b 100644 --- a/target/linux/ath79/dts/qca9556_mikrotik_routerboard-wap-g-5hact2hnd.dts +++ b/target/linux/ath79/dts/qca9556_mikrotik_routerboard-wap-g-5hact2hnd.dts @@ -53,7 +53,7 @@ ð1 { status = "okay"; - mtd-mac-address = <&art 0x10>; + mtd-mac-address = <&hard_config 0x10>; pll-data = <0x03000101 0x80000101 0x80001313>; phy-handle = <&phy0>; @@ -73,7 +73,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <104000000>; + spi-max-frequency = <40000000>; partitions { compatible = "fixed-partitions"; @@ -81,32 +81,41 @@ #size-cells = <1>; partition@0 { - label = "routerboot"; - reg = <0x000000 0x00e000>; + label = "RouterBoot"; + reg = <0x0 0x20000>; read-only; - }; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - art: partition@e000 { - label = "art"; - reg = <0x000e000 0x001000>; - read-only; - }; + partition@0 { + label = "bootloader1"; + reg = <0x0 0xe000>; + read-only; + }; - partition@f000 { - label = "bios"; - reg = <0x000f000 0x001000>; - read-only; - }; + hard_config: partition@e000 { + label = "hard_config"; + reg = <0xe000 0x1000>; + read-only; + }; - partition@10000 { - label = "routerboot2"; - reg = <0x010000 0x00f000>; - read-only; - }; + partition@f000 { + label = "bios"; + reg = <0xf000 0x1000>; + read-only; + }; - partition@1f000 { - label = "soft_config"; - reg = <0x001f000 0x001000>; + partition@10000 { + label = "bootloader2"; + reg = <0x10000 0xf000>; + read-only; + }; + + partition@1f000 { + label = "soft_config"; + reg = <0x1f000 0x1000>; + }; }; partition@20000 { diff --git a/target/linux/ath79/dts/qca9557.dtsi b/target/linux/ath79/dts/qca9557.dtsi index 69ea639804..ede658af6d 100644 --- a/target/linux/ath79/dts/qca9557.dtsi +++ b/target/linux/ath79/dts/qca9557.dtsi @@ -202,7 +202,7 @@ }; pcie0: pcie-controller@180c0000 { - compatible = "qcom,ar7240-pci"; + compatible = "qcom,qca9550-pci", "qcom,ar7240-pci"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0x0>; @@ -215,6 +215,9 @@ interrupt-parent = <&intc2>; interrupts = <1>; + resets = <&rst 6>, <&rst 7>; + reset-names = "hc", "phy"; + interrupt-controller; #interrupt-cells = <1>; @@ -234,7 +237,7 @@ }; pcie1: pcie-controller@18250000 { - compatible = "qcom,ar7240-pci"; + compatible = "qcom,qca9550-pci", "qcom,ar7240-pci"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0x0>; @@ -247,6 +250,9 @@ interrupt-parent = <&intc3>; interrupts = <0>; + resets = <&rst2 6>, <&rst2 7>; + reset-names = "hc", "phy"; + interrupt-controller; #interrupt-cells = <1>; diff --git a/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts b/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts new file mode 100644 index 0000000000..b71bec4e04 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "qca9557.dtsi" + +/ { + compatible = "domywifi,dw33d", "qca,qca9558"; + model = "DomyWifi DW33D"; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + aliases { + led-boot = &led_system; + led-failsafe = &led_system; + led-running = &led_system; + led-upgrade = &led_system; + }; + + leds { + compatible = "gpio-leds"; + + led_system: system { + label = "dw33d:blue:system"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + + mmc { + label = "dw33d:blue:mmc"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + trigger-sources = <&hub_port0>; + linux,default-trigger = "usbport"; + }; + + usb { + label = "dw33d:blue:usb"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + trigger-sources = <&hub_port1>; + linux,default-trigger = "usbport"; + }; + + wlan2g { + label = "dw33d:blue:wlan2g"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + internet { + label = "dw33d:blue:internet"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "Reset button"; + linux,code = ; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; +}; + +&pcie0 { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0 0 0 0 0>; + }; +}; + +&uart { + status = "okay"; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_port0: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; + +&spi { + status = "okay"; + + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x10000>; + }; + + partition@50000 { + label = "oem-firmware"; + reg = <0x50000 0xfa0000>; + }; + + art: partition@ff0000 { + label = "art"; + reg = <0xff0000 0x10000>; + read-only; + }; + }; + }; +}; + +&nand { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x500000>; + }; + + partition@500000 { + label = "ubi"; + reg = <0x500000 0x5b00000>; + }; + + partition@6000000 { + label = "oem-backup"; + reg = <0x6000000 0x2000000>; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + + qca,ar8327-initvals = < + 0x04 0x87600000 /* PORT0 PAD MODE CTRL */ + 0x0c 0x00080080 /* PORT6 PAD MODE CTRL */ + 0x7c 0x0000007e /* PORT0_STATUS */ + 0x94 0x0000007e /* PORT6 STATUS */ + >; + }; +}; + +ð0 { + status = "okay"; + + mtd-mac-address = <&art 0x0>; + pll-data = <0x56000000 0x00000101 0x00001616>; + phy-handle = <&phy0>; +}; + +ð1 { + status = "okay"; + + mtd-mac-address = <&art 0x6>; + pll-data = <0x03000101 0x00000101 0x00001616>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&wmac { + status = "okay"; + + mtd-cal-data = <&art 0x1000>; + mtd-mac-address = <&art 0xc>; +}; diff --git a/target/linux/ath79/dts/qca9558_mikrotik_routerboard-922uags-5hpacd.dts b/target/linux/ath79/dts/qca9558_mikrotik_routerboard-922uags-5hpacd.dts new file mode 100644 index 0000000000..3f2a1a51a6 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_mikrotik_routerboard-922uags-5hpacd.dts @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "qca9557.dtsi" + +/ { + compatible = "mikrotik,routerboard-922uags-5hpacd", "qca,qca9558"; + model = "MikroTik RouterBOARD 922UAGS-5HPacD"; + + aliases { + label-mac-device = ð0; + led-boot = &led_user; + led-failsafe = &led_user; + led-upgrade = &led_user; + serial0 = &uart; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led_user: user { + label = "mikrotik:green:user"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + }; + + ath10k-leds { + compatible = "gpio-leds"; + + wlan5g { + label = "mikrotik:green:wlan5g"; + gpios = <&ath10k 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + gpio-export { + compatible = "gpio-export"; + + gpio_usb_power { + gpio-export,name = "mikrotik:power:usb"; + gpio-export,output = <0>; + gpios = <&gpio 13 GPIO_ACTIVE_HIGH>; + }; + + gpio_nand_power { + gpio-export,name = "mikrotik:power:nand"; + gpio-export,output = <0>; + gpios = <&gpio 23 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +ð0 { + status = "okay"; + + mtd-mac-address = <&hard_config 0x10>; + phy-handle = <&phy4>; + pll-data = <0x8f000000 0xa0000101 0xa0001313>; + + gmac-config { + device = <&gmac>; + rgmii-enabled = <1>; + }; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "routerboot"; + reg = <0x0000000 0x000c000>; + read-only; + }; + + hard_config: partition@c000 { + label = "hard_config"; + reg = <0x000c000 0x0001000>; + read-only; + }; + + partition@d000 { + label = "bios"; + reg = <0x000d000 0x0001000>; + read-only; + }; + + partition@e000 { + label = "soft_config"; + reg = <0x000e000 0x0001000>; + read-only; + }; + }; + }; +}; + +&nand { + status = "okay"; + + nand-ecc-mode = "soft"; + qca,nand-swap-dma; + qca,nand-scan-fixup; + + partitions { + compatible = "fixed-partitions"; + #size-cells = <1>; + + partition@0 { + label = "booter"; + reg = <0x0000000 0x0040000>; + read-only; + }; + + partition@40000 { + label = "kernel"; + reg = <0x0040000 0x03c0000>; + }; + + partition@400000 { + label = "ubi"; + reg = <0x0400000 0x7c00000>; + }; + }; +}; + +&uart { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + ath10k: wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0 0 0 0 0>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&pcie1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb_phy0 { + status = "okay"; +}; diff --git a/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts b/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts new file mode 100644 index 0000000000..d3d9635693 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "qca9557.dtsi" + +/ { + model = "Sitecom WLR-8100 (X8 AC1750)"; + compatible = "sitecom,wlr-8100", "qca,qca9558"; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + aliases { + led-boot = &led_status_amber; + led-failsafe = &led_status_amber; + led-running = &led_status_amber; + led-upgrade = &led_status_amber; + }; + + keys { + compatible = "gpio-keys"; + + wifi2g_rfkill { + label = "2.4GHz - RFKILL"; + gpios = <&gpio 21 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wifi5g_restart { + label = "5GHz - RESTART"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_amber: status_amber { + label = "wlr-8100:amber:status"; + gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + ops { + label = "wlr-8100:white:ops"; + gpios = <&gpio 23 GPIO_ACTIVE_LOW>; + }; + + wifi2g { + label = "wlr-8100:blue:wifi2g"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + wifi5g { + label = "wlr-8100:blue:wifi5g"; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + }; +}; + +&spi { + status = "okay"; + + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + uboot: partition@0 { + label = "u-boot"; + reg = <0x000000 0x030000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x030000 0x010000>; + read-only; + }; + + partition@40000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x040000 0xf10000>; + }; + + partition@f50000 { + label = "manufacture"; + reg = <0xf50000 0x040000>; + read-only; + }; + + partition@f90000 { + label = "backup"; + reg = <0xf90000 0x010000>; + read-only; + }; + + partition@fa0000 { + label = "storage"; + reg = <0xfa0000 0x050000>; + read-only; + }; + + art: partition@ff0000 { + label = "art"; + reg = <0xff0000 0x010000>; + read-only; + }; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0 0 0 0 0>; + }; +}; + +&uart { + status = "okay"; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + + qca,ar8327-initvals = < + 0x04 0x87600000 /* PORT0 PAD MODE CTRL */ + 0x50 0xc437c437 /* LED Control Register 0 */ + 0x54 0xc337c337 /* LED Control Register 1 */ + 0x58 0x00000000 /* LED Control Register 2 */ + 0x5c 0x03ffff00 /* LED Control Register 3 */ + 0x7c 0x0000007e /* PORT0_STATUS */ + >; + }; +}; + +ð0 { + status = "okay"; + phy-handle = <&phy0>; + pll-data = <0xa6000000 0x00000101 0x00001616>; + + gmac-config { + device = <&gmac>; + rgmii-enabled = <1>; + }; +}; + +&wmac { + status = "okay"; + qca,no-eeprom; +}; diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts b/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts new file mode 100644 index 0000000000..8fae6545e3 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "qca9558_tplink_archer-d7.dtsi" + +/ { + compatible = "tplink,archer-d7-v1", "qca,qca9558"; + model = "TP-Link Archer D7 v1"; + + aliases { + label-mac-device = &wmac; + }; +}; + +&spi { + status = "okay"; + + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x020000>; + read-only; + }; + + partition@20000 { + compatible = "tplink,firmware"; + label = "firmware"; + reg = <0x020000 0xf90000>; + }; + + partition@fb0000 { + label = "radioDECT"; + reg = <0xfb0000 0x010000>; + read-only; + }; + + partition@fc0000 { + label = "config"; + reg = <0xfc0000 0x010000>; + read-only; + }; + + romfs: partition@fd0000 { + label = "romfs"; + reg = <0xfd0000 0x010000>; + read-only; + }; + + partition@fe0000 { + label = "rom"; + reg = <0xfe0000 0x010000>; + read-only; + }; + + art: partition@ff0000 { + label = "art"; + reg = <0xff0000 0x010000>; + read-only; + }; + }; + }; +}; + +ð0 { + mtd-mac-address = <&romfs 0xf100>; + mtd-mac-address-increment = <1>; +}; + +ð1 { + mtd-mac-address = <&romfs 0xf100>; +}; + +&wmac { + mtd-cal-data = <&art 0x1000>; + mtd-mac-address = <&romfs 0xf100>; +}; diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-d7.dtsi b/target/linux/ath79/dts/qca9558_tplink_archer-d7.dtsi new file mode 100644 index 0000000000..a65d4e2b53 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_tplink_archer-d7.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include + +#include "qca9557.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + aliases { + led-boot = &led_system; + led-failsafe = &led_system; + led-running = &led_system; + led-upgrade = &led_system; + }; + + leds { + compatible = "gpio-leds"; + + led_system: system { + label = "tp-link:white:system"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + wlan { + label = "tp-link:white:wlan"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + + lan { + label = "tp-link:white:lan"; + gpios = <&gpio 23 GPIO_ACTIVE_LOW>; + }; + + usb { + label = "tp-link:white:usb"; + gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + trigger-sources = <&hub_port1>, <&hub_port0>; + linux,default-trigger = "usbport"; + }; + + qss { + label = "tp-link:white:qss"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + }; + + keys { + compatible = "gpio-keys"; + + wifi { + label = "WiFi button"; + linux,code = ; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS button"; + linux,code = ; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset button"; + linux,code = ; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + }; + }; + + reg_usb0_vbus: regulator { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_vbus: regulator { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + + qca,ar8327-initvals = < + 0x04 0x00080080 /* PORT0 PAD MODE CTRL */ + 0x0c 0x07600000 /* PORT6 PAD MODE CTRL */ + 0x50 0xc737c737 /* LED_CTRL0 */ + 0x54 0x00000000 /* LED_CTRL1 */ + 0x58 0x00000000 /* LED_CTRL2 */ + 0x5c 0x0030c300 /* LED_CTRL3 */ + 0x7c 0x0000007e /* PORT0_STATUS */ + 0x94 0x0000007e /* PORT6 STATUS */ + >; + }; +}; + +ð0 { + status = "okay"; + + phy-handle = <&phy0>; + pll-data = <0x56000000 0x00000101 0x00001616>; + + gmac-config { + device = <&gmac>; + rgmii-enabled = <1>; + }; +}; + +ð1 { + status = "okay"; + + pll-data = <0x03000101 0x00000101 0x00001616>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&wmac { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&uart { + status = "okay"; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "host"; + vbus-supply = <®_usb0_vbus>; + status = "okay"; + + hub_port0: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb1 { + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "host"; + vbus-supply = <®_usb1_vbus>; + status = "okay"; + + hub_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts b/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts new file mode 100644 index 0000000000..31563d9c46 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "qca9558_tplink_archer-d7.dtsi" + +/ { + compatible = "tplink,archer-d7b-v1", "qca,qca9558"; + model = "TP-Link Archer D7b v1"; + + aliases { + label-mac-device = &wmac; + }; +}; + +&spi { + status = "okay"; + + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x020000>; + read-only; + }; + + partition@20000 { + compatible = "tplink,firmware"; + label = "firmware"; + reg = <0x020000 0xfa0000>; + }; + + partition@fc0000 { + label = "config"; + reg = <0xfc0000 0x010000>; + read-only; + }; + + romfs: partition@fd0000 { + label = "romfs"; + reg = <0xfd0000 0x010000>; + read-only; + }; + + partition@fe0000 { + label = "reserve"; + reg = <0xfe0000 0x010000>; + read-only; + }; + + art: partition@ff0000 { + label = "art"; + reg = <0xff0000 0x010000>; + read-only; + }; + }; + }; +}; + +ð0 { + mtd-mac-address = <&romfs 0xf100>; + mtd-mac-address-increment = <1>; +}; + +ð1 { + mtd-mac-address = <&romfs 0xf100>; +}; + +&wmac { + mtd-cal-data = <&art 0x1000>; + mtd-mac-address = <&romfs 0xf100>; +}; diff --git a/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts b/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts index 4ad65c31e8..2f00d0ba4d 100644 --- a/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts +++ b/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts @@ -29,7 +29,7 @@ gpios = <&gpio 15 GPIO_ACTIVE_LOW>; }; - wan { + internet { label = "nbg6716:white:internet"; gpios = <&gpio 18 GPIO_ACTIVE_LOW>; }; @@ -38,31 +38,31 @@ label = "nbg6716:white:usb1"; gpios = <&gpio 4 GPIO_ACTIVE_LOW>; linux,default-trigger = "usbport"; - trigger-sources = <&hub_port0>; + trigger-sources = <&hub_port1>; }; usb2 { label = "nbg6716:white:usb2"; gpios = <&gpio 13 GPIO_ACTIVE_LOW>; linux,default-trigger = "usbport"; - trigger-sources = <&hub_port1>; + trigger-sources = <&hub_port0>; }; - wifi2 { - label = "nbg6716:white:wifi2"; + wifi2g { + label = "nbg6716:white:wifi2g"; gpios = <&gpio 19 GPIO_ACTIVE_LOW>; linux,default-trigger = "phy1tpt"; }; - wifi5 { - label = "nbg6716:white:wifi5"; + wifi5g { + label = "nbg6716:white:wifi5g"; gpios = <&gpio 17 GPIO_ACTIVE_LOW>; linux,default-trigger = "phy0tpt"; }; wps { label = "nbg6716:white:wps"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + gpios = <&gpio 21 GPIO_ACTIVE_LOW>; }; }; @@ -79,18 +79,21 @@ wifi { label = "WiFi button"; linux,code = ; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + linux,input-type = ; + gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; debounce-interval = <60>; }; usb1 { label = "USB1 eject button"; + linux,code = ; gpios = <&gpio 0 GPIO_ACTIVE_LOW>; debounce-interval = <60>; }; usb2 { label = "USB2 eject button"; + linux,code = ; gpios = <&gpio 14 GPIO_ACTIVE_LOW>; debounce-interval = <60>; }; @@ -262,6 +265,8 @@ &wmac { status = "okay"; + + mtd-cal-data = <&art 0x1000>; }; &pcie1 { diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts index 85e456bb44..a83b5881d4 100644 --- a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts +++ b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts @@ -8,6 +8,18 @@ model = "TP-Link Archer C60 v1"; }; +&leds { + wan_amber { + label = "tp-link:amber:wan"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "tp-link:green:wps"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + }; +}; + &spi { status = "okay"; num-cs = <1>; diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts index 29f916734e..c19e4e973d 100644 --- a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts +++ b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts @@ -8,6 +8,18 @@ model = "TP-Link Archer C60 v2"; }; +&leds { + wan_amber { + label = "tp-link:amber:wan"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "tp-link:green:wps"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + }; +}; + &spi { status = "okay"; num-cs = <1>; diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts new file mode 100644 index 0000000000..444d54b000 --- /dev/null +++ b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "qca9561_tplink_archer-c6x.dtsi" + +/ { + compatible = "tplink,archer-c60-v3", "qca,qca9561"; + model = "TP-Link Archer C60 v3"; +}; + +&leds { + wan_amber { + label = "tp-link:amber:wan"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + }; +}; +&spi { + status = "okay"; + + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "factory-boot"; + reg = <0x000000 0x01fb00>; + read-only; + }; + + mac: partition@1fb00 { + label = "mac"; + reg = <0x01fb00 0x000500>; + read-only; + }; + + partition@20000 { + label = "u-boot"; + reg = <0x020000 0x010000>; + read-only; + }; + + partition@30000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x030000 0x7a0000>; + }; + + partition@7d0000 { + label = "tplink"; + reg = <0x7d0000 0x020000>; + read-only; + }; + + art: partition@7f0000 { + label = "art"; + reg = <0x7f0000 0x010000>; + read-only; + }; + }; + }; +}; diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c6x.dtsi b/target/linux/ath79/dts/qca9561_tplink_archer-c6x.dtsi index 9b51ebf689..b1b166d89a 100644 --- a/target/linux/ath79/dts/qca9561_tplink_archer-c6x.dtsi +++ b/target/linux/ath79/dts/qca9561_tplink_archer-c6x.dtsi @@ -15,7 +15,7 @@ led-failsafe = &led_power; led-running = &led_power; led-upgrade = &led_power; - label-mac-device = ð0; + label-mac-device = ð1; }; keys { @@ -34,7 +34,7 @@ }; }; - leds { + leds: leds { compatible = "gpio-leds"; led_power: power { @@ -60,20 +60,10 @@ gpios = <&gpio 20 GPIO_ACTIVE_LOW>; }; - wan_amber { - label = "tp-link:amber:wan"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - }; - lan { label = "tp-link:green:lan"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; }; - - wps { - label = "tp-link:green:wps"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; }; }; @@ -91,13 +81,13 @@ phy-handle = <&swphy4>; mtd-mac-address = <&mac 0x8>; + mtd-mac-address-increment = <1>; }; ð1 { status = "okay"; mtd-mac-address = <&mac 0x8>; - mtd-mac-address-increment = <1>; }; &wmac { diff --git a/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts b/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts index 28fefe224d..16bc26c978 100644 --- a/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts +++ b/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts @@ -180,6 +180,7 @@ ð0 { status = "okay"; + phy-mode = "sgmii"; phy-handle = <&phy4>; mtd-mac-address = <&info 0x8>; diff --git a/target/linux/ath79/dts/qca9563_ubnt_unifiac-lite.dtsi b/target/linux/ath79/dts/qca9563_ubnt_unifiac-lite.dtsi index 8248e060c5..b9a5b55cd6 100644 --- a/target/linux/ath79/dts/qca9563_ubnt_unifiac-lite.dtsi +++ b/target/linux/ath79/dts/qca9563_ubnt_unifiac-lite.dtsi @@ -22,5 +22,6 @@ status = "okay"; mtd-mac-address = <&art 0x0>; + phy-mode = "sgmii"; phy-handle = <&phy4>; }; diff --git a/target/linux/ath79/dts/qca956x.dtsi b/target/linux/ath79/dts/qca956x.dtsi index d0ce952ef4..333428443f 100644 --- a/target/linux/ath79/dts/qca956x.dtsi +++ b/target/linux/ath79/dts/qca956x.dtsi @@ -168,6 +168,9 @@ interrupt-parent = <&intc3>; interrupts = <0>; + resets = <&rst 6>, <&rst 7>; + reset-names = "hc", "phy"; + interrupt-controller; #interrupt-cells = <1>; diff --git a/target/linux/ath79/files/drivers/mtd/nand/raw/ar934x_nand.c b/target/linux/ath79/files/drivers/mtd/nand/raw/ar934x_nand.c index 58198e4465..63abc4a8d8 100644 --- a/target/linux/ath79/files/drivers/mtd/nand/raw/ar934x_nand.c +++ b/target/linux/ath79/files/drivers/mtd/nand/raw/ar934x_nand.c @@ -631,11 +631,19 @@ static void ar934x_nfc_read_status(struct ar934x_nfc *nfc) nfc->buf[0] = status; } +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) static void ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column, int page_addr) { struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); struct nand_chip *nand = &nfc->nand_chip; +#else +static void ar934x_nfc_cmdfunc(struct nand_chip *nand, unsigned int command, + int column, int page_addr) +{ + struct mtd_info *mtd = nand_to_mtd(nand); + struct ar934x_nfc *nfc = nand->priv; +#endif nfc->read_id = false; if (command != NAND_CMD_PAGEPROG) @@ -740,16 +748,28 @@ static void ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, } } +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) static int ar934x_nfc_dev_ready(struct mtd_info *mtd) { struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); +#else +static int ar934x_nfc_dev_ready(struct nand_chip *chip) +{ + struct ar934x_nfc *nfc = chip->priv; +#endif return __ar934x_nfc_dev_ready(nfc); } +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) static u8 ar934x_nfc_read_byte(struct mtd_info *mtd) { struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); +#else +static u8 ar934x_nfc_read_byte(struct nand_chip *chip) +{ + struct ar934x_nfc *nfc = chip->priv; +#endif u8 data; WARN_ON(nfc->buf_index >= nfc->buf_size); @@ -764,9 +784,15 @@ static u8 ar934x_nfc_read_byte(struct mtd_info *mtd) return data; } +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) static void ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) { struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); +#else +static void ar934x_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len) +{ + struct ar934x_nfc *nfc = chip->priv; +#endif int i; WARN_ON(nfc->buf_index + len > nfc->buf_size); @@ -784,9 +810,15 @@ static void ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) } } +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) static void ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len) { struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); +#else +static void ar934x_nfc_read_buf(struct nand_chip *chip, u8 *buf, int len) +{ + struct ar934x_nfc *nfc = chip->priv; +#endif int buf_index; int i; @@ -821,10 +853,18 @@ static inline void ar934x_nfc_disable_hwecc(struct ar934x_nfc *nfc) nfc->ctrl_reg |= AR934X_NFC_CTRL_CUSTOM_SIZE_EN; } +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) static int ar934x_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page) { struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); +#else +static int ar934x_nfc_read_oob(struct nand_chip *chip, + int page) +{ + struct ar934x_nfc *nfc = chip->priv; + struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc); +#endif int err; nfc_dbg(nfc, "read_oob: page:%d\n", page); @@ -839,11 +879,18 @@ static int ar934x_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip, return 0; } +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) static int ar934x_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page) { struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); - +#else +static int ar934x_nfc_write_oob(struct nand_chip *chip, + int page) +{ + struct ar934x_nfc *nfc = chip->priv; + struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc); +#endif nfc_dbg(nfc, "write_oob: page:%d\n", page); memcpy(nfc->buf, chip->oob_poi, mtd->oobsize); @@ -852,11 +899,20 @@ static int ar934x_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, page, mtd->oobsize); } +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) static int ar934x_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, u8 *buf, int oob_required, int page) { struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); +#else +static int ar934x_nfc_read_page_raw( + struct nand_chip *chip, u8 *buf, + int oob_required, int page) +{ + struct ar934x_nfc *nfc = chip->priv; + struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc); +#endif int len; int err; @@ -878,10 +934,18 @@ static int ar934x_nfc_read_page_raw(struct mtd_info *mtd, return 0; } +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) static int ar934x_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, u8 *buf, int oob_required, int page) { struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); +#else +static int ar934x_nfc_read_page(struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + struct ar934x_nfc *nfc = chip->priv; + struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc); +#endif u32 ecc_ctrl; int max_bitflips = 0; bool ecc_failed; @@ -950,11 +1014,20 @@ static int ar934x_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, return max_bitflips; } +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) static int ar934x_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, const u8 *buf, int oob_required, int page) { struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); +#else +static int ar934x_nfc_write_page_raw( + struct nand_chip *chip, const u8 *buf, + int oob_required, int page) +{ + struct ar934x_nfc *nfc = chip->priv; + struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc); +#endif int len; nfc_dbg(nfc, "write_page_raw: page:%d oob:%d\n", page, oob_required); @@ -970,10 +1043,18 @@ static int ar934x_nfc_write_page_raw(struct mtd_info *mtd, return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, len); } +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) static int ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, const u8 *buf, int oob_required, int page) { struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); +#else +static int ar934x_nfc_write_page(struct nand_chip *chip, + const u8 *buf, int oob_required, int page) +{ + struct ar934x_nfc *nfc = chip->priv; + struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc); +#endif int err; nfc_dbg(nfc, "write_page: page:%d oob:%d\n", page, oob_required); @@ -981,7 +1062,11 @@ static int ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, /* write OOB first */ if (oob_required && !is_all_ff(chip->oob_poi, mtd->oobsize)) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) err = ar934x_nfc_write_oob(mtd, chip, page); +#else + err = ar934x_nfc_write_oob(chip, page); +#endif if (err) return err; } @@ -997,14 +1082,22 @@ static int ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, return err; } -static int ar934x_nfc_hw_reset_assert(struct ar934x_nfc *nfc) { - reset_control_assert(nfc->rst); +static int ar934x_nfc_hw_reset_assert(struct ar934x_nfc *nfc) +{ + int err; + + err = reset_control_assert(nfc->rst); udelay(250); + return err; } -static int ar934x_nfc_hw_reset_deassert(struct ar934x_nfc *nfc) { - reset_control_deassert(nfc->rst); +static int ar934x_nfc_hw_reset_deassert(struct ar934x_nfc *nfc) +{ + int err; + + err = reset_control_deassert(nfc->rst); udelay(250); + return err; } static int ar934x_nfc_hw_init(struct ar934x_nfc *nfc) @@ -1083,6 +1176,11 @@ static int ar934x_nfc_init_tail(struct mtd_info *mtd) { struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); struct nand_chip *chip = &nfc->nand_chip; +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) + u64 chipsize = chip->chipsize; +#else + u64 chipsize = nanddev_target_size(&chip->base); +#endif u32 ctrl; u32 t; int err; @@ -1169,10 +1267,10 @@ static int ar934x_nfc_init_tail(struct mtd_info *mtd) if (nfc->small_page) { ctrl |= AR934X_NFC_CTRL_SMALL_PAGE; - if (chip->chipsize > (32 << 20)) { + if (chipsize > (32 << 20)) { nfc->addr_count0 = 4; nfc->addr_count1 = 3; - } else if (chip->chipsize > (2 << 16)) { + } else if (chipsize > (2 << 16)) { nfc->addr_count0 = 3; nfc->addr_count1 = 2; } else { @@ -1180,10 +1278,10 @@ static int ar934x_nfc_init_tail(struct mtd_info *mtd) nfc->addr_count1 = 1; } } else { - if (chip->chipsize > (128 << 20)) { + if (chipsize > (128 << 20)) { nfc->addr_count0 = 5; nfc->addr_count1 = 3; - } else if (chip->chipsize > (8 << 16)) { + } else if (chipsize > (8 << 16)) { nfc->addr_count0 = 4; nfc->addr_count1 = 2; } else { @@ -1329,8 +1427,13 @@ static int ar934x_nfc_attach_chip(struct nand_chip *nand) static u64 ar934x_nfc_dma_mask = DMA_BIT_MASK(32); +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) static void ar934x_nfc_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) +#else +static void ar934x_nfc_cmd_ctrl(struct nand_chip *chip, int dat, + unsigned int ctrl) +#endif { WARN_ON(dat != NAND_CMD_NONE); } @@ -1401,6 +1504,7 @@ static int ar934x_nfc_probe(struct platform_device *pdev) nand_set_controller_data(nand, nfc); nand_set_flash_node(nand, pdev->dev.of_node); +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) nand->chip_delay = 25; nand->dev_ready = ar934x_nfc_dev_ready; nand->cmdfunc = ar934x_nfc_cmdfunc; @@ -1408,7 +1512,17 @@ static int ar934x_nfc_probe(struct platform_device *pdev) nand->read_byte = ar934x_nfc_read_byte; nand->write_buf = ar934x_nfc_write_buf; nand->read_buf = ar934x_nfc_read_buf; +#else + nand->legacy.chip_delay = 25; + nand->legacy.dev_ready = ar934x_nfc_dev_ready; + nand->legacy.cmdfunc = ar934x_nfc_cmdfunc; + nand->legacy.cmd_ctrl = ar934x_nfc_cmd_ctrl; /* dummy */ + nand->legacy.read_byte = ar934x_nfc_read_byte; + nand->legacy.write_buf = ar934x_nfc_write_buf; + nand->legacy.read_buf = ar934x_nfc_read_buf; +#endif nand->ecc.mode = NAND_ECC_HW; /* default */ + nand->priv = nfc; platform_set_drvdata(pdev, nfc); ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE); @@ -1421,8 +1535,13 @@ static int ar934x_nfc_probe(struct platform_device *pdev) goto err_free_buf; } +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) nand->dummy_controller.ops = &ar934x_nfc_controller_ops; ret = nand_scan(mtd, 1); +#else + nand->legacy.dummy_controller.ops = &ar934x_nfc_controller_ops; + ret = nand_scan(nand, 1); +#endif if (ret) { dev_err(&pdev->dev, "nand_scan failed, err:%d\n", ret); goto err_free_buf; @@ -1444,12 +1563,18 @@ err_free_buf: static int ar934x_nfc_remove(struct platform_device *pdev) { struct ar934x_nfc *nfc; +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) struct mtd_info *mtd; +#endif nfc = platform_get_drvdata(pdev); if (nfc) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) mtd = ar934x_nfc_to_mtd(nfc); nand_release(mtd); +#else + nand_release(&nfc->nand_chip); +#endif ar934x_nfc_free_buf(nfc); } diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c index 2394ccc90d..edb026544c 100644 --- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c +++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c @@ -1581,11 +1581,15 @@ static int ag71xx_probe(struct platform_device *pdev) ag->stop_desc->next = (u32) ag->stop_desc_dma; mac_addr = of_get_mac_address(np); - if (mac_addr) - memcpy(dev->dev_addr, mac_addr, ETH_ALEN); - if (!mac_addr || !is_valid_ether_addr(dev->dev_addr)) { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0)) + if (!mac_addr || !is_valid_ether_addr(mac_addr)) { +#else + if (IS_ERR(mac_addr) || !is_valid_ether_addr(mac_addr)) { +#endif dev_err(&pdev->dev, "invalid MAC address, using random address\n"); eth_random_addr(dev->dev_addr); + } else { + memcpy(dev->dev_addr, mac_addr, ETH_ALEN); } ag->phy_if_mode = of_get_phy_mode(np); diff --git a/target/linux/ath79/generic/base-files/etc/board.d/01_leds b/target/linux/ath79/generic/base-files/etc/board.d/01_leds index 6668e15a74..ca4bb3dd33 100755 --- a/target/linux/ath79/generic/base-files/etc/board.d/01_leds +++ b/target/linux/ath79/generic/base-files/etc/board.d/01_leds @@ -12,9 +12,19 @@ case "$board" in ucidef_set_led_netdev "lan" "LAN" "$boardname:orange:eth0" "eth0" ucidef_set_led_switch "wan" "WAN" "$boardname:orange:eth1" "switch0" "0x04" ;; -alfa-network,ap121f) +alfa-network,ap121f|\ +avm,fritz450e) ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth0" ;; +avm,fritz1750e) + ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth0" + ucidef_set_rssimon "wlan1" "200000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "$boardname:green:rssi0" "wlan1" "1" "100" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "$boardname:green:rssi1" "wlan1" "20" "100" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "$boardname:green:rssi2" "wlan1" "40" "100" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "$boardname:green:rssi3" "wlan1" "60" "100" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "$boardname:green:rssi4" "wlan1" "80" "100" + ;; avm,fritz300e) ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth0" ucidef_set_rssimon "wlan0" "200000" "1" @@ -80,15 +90,23 @@ comfast,cf-e560ac) ucidef_set_led_switch "lan3" "LAN3" "$boardname:blue:lan3" "switch0" "0x08" ucidef_set_led_switch "lan4" "LAN4" "$boardname:blue:lan4" "switch0" "0x10" ;; +comfast,cf-ew72) + ucidef_set_led_switch "lan" "LAN" "$boardname:blue:lan" "switch0" "0x02" + ucidef_set_led_netdev "wan" "WAN" "$boardname:blue:wan" "eth1" + ;; +comfast,cf-wr752ac-v1|\ +engenius,ecb1750) + ucidef_set_led_netdev "lan" "LAN" "$boardname:blue:lan" "eth0" + ;; +devolo,magic-2-wifi) + ucidef_set_led_netdev "plcw" "dLAN" "devolo:white:dlan" "eth0.1" "rx" + ;; dlink,dir-842-c1|\ dlink,dir-842-c2|\ dlink,dir-842-c3|\ dlink,dir-859-a1) ucidef_set_led_switch "internet" "WAN" "$boardname:green:internet" "switch0" "0x20" ;; -engenius,ecb1750) - ucidef_set_led_netdev "lan" "LAN" "$boardname:blue:lan" "eth0" - ;; engenius,ews511ap) ucidef_set_led_netdev "lan1" "LAN1" "$boardname:blue:lan1" "eth1" ucidef_set_led_netdev "lan2" "LAN2" "$boardname:blue:lan2" "eth0" @@ -174,7 +192,8 @@ tplink,archer-c58-v1|\ tplink,archer-c59-v1|\ tplink,archer-c59-v2|\ tplink,archer-c60-v1|\ -tplink,archer-c60-v2) +tplink,archer-c60-v2|\ +tplink,archer-c60-v3) ucidef_set_led_switch "lan" "LAN" "tp-link:green:lan" "switch0" "0x1E" ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" ;; @@ -183,6 +202,10 @@ tplink,archer-d50-v1) ucidef_set_led_switch "wan_data" "WAN Data" "tp-link:white:internet" "switch0" "0x02" "" "tx rx" ucidef_set_led_switch "wan_link" "WAN Link" "tp-link:white:wan" "switch0" "0x02" "" "link" ;; +tplink,archer-d7-v1|\ +tplink,archer-d7b-v1) + ucidef_set_led_switch "lan" "LAN" "tp-link:white:lan" "switch0" "0x3c" + ;; tplink,cpe210-v1|\ tplink,cpe220-v2|\ tplink,cpe220-v3|\ @@ -242,8 +265,10 @@ tplink,tl-wr842n-v2) trendnet,tew-823dru) ucidef_set_led_netdev "wan" "WAN" "trendnet:green:planet" "eth0" ;; -ubnt,bullet-m|\ +ubnt,bullet-m-ar7240|\ +ubnt,bullet-m-ar7241|\ ubnt,bullet-m-xw|\ +ubnt,nanobridge-m|\ ubnt,nanostation-loco-m|\ ubnt,nanostation-loco-m-xw|\ ubnt,nanostation-m|\ diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index ef58d9e124..543543ad54 100755 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -13,7 +13,9 @@ ath79_setup_interfaces() adtran,bsap1840|\ alfa-network,ap121f|\ aruba,ap-105|\ + avm,fritz1750e|\ avm,fritz300e|\ + comfast,cf-wr752ac-v1|\ devolo,dvl1200i|\ devolo,dvl1750c|\ devolo,dvl1750i|\ @@ -21,7 +23,6 @@ ath79_setup_interfaces() dlink,dir-505|\ engenius,ecb1750|\ glinet,gl-ar300m-lite|\ - mikrotik,routerboard-wap-g-5hact2hnd|\ netgear,ex6400|\ netgear,ex7300|\ ocedo,koala|\ @@ -41,11 +42,13 @@ ath79_setup_interfaces() tplink,re450-v1|\ tplink,re450-v2|\ tplink,tl-wr902ac-v1|\ - ubnt,bullet-m|\ + ubnt,bullet-m-ar7240|\ + ubnt,bullet-m-ar7241|\ ubnt,bullet-m-xw|\ ubnt,lap-120|\ ubnt,litebeam-ac-gen2|\ ubnt,nanobeam-ac|\ + ubnt,nanobridge-m|\ ubnt,nanostation-ac-loco|\ ubnt,nanostation-loco-m|\ ubnt,nanostation-loco-m-xw|\ @@ -80,6 +83,9 @@ ath79_setup_interfaces() ;; buffalo,wzr-hp-ag300h|\ tplink,archer-c25-v1|\ + tplink,archer-c60-v1|\ + tplink,archer-c60-v2|\ + tplink,archer-c60-v3|\ tplink,tl-wdr3500-v1|\ tplink,tl-wr842n-v1|\ tplink,tl-wr842n-v3|\ @@ -106,9 +112,7 @@ ath79_setup_interfaces() ubnt,routerstation) ucidef_set_interfaces_lan_wan "eth1" "eth0" ;; - comfast,cf-e560ac|\ - tplink,archer-c60-v1|\ - tplink,archer-c60-v2) + comfast,cf-e560ac) ucidef_set_interface_wan "eth1" ucidef_add_switch "switch0" \ "0@eth0" "1:lan" "2:lan" "3:lan" "4:lan" @@ -123,6 +127,10 @@ ath79_setup_interfaces() ocedo,ursus) ucidef_set_interface_lan "eth0 eth1" ;; + devolo,magic-2-wifi) + ucidef_add_switch "switch0" \ + "0@eth0" "2:wan" "3:lan" "4:lan" + ;; dlink,dir-825-b1) ucidef_set_interface_wan "eth1" ucidef_add_switch "switch0" \ @@ -142,7 +150,8 @@ ath79_setup_interfaces() "0@eth0" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5:wan" ;; elecom,wrc-1750ghbk2-i|\ - elecom,wrc-300ghbk2-i) + elecom,wrc-300ghbk2-i|\ + sitecom,wlr-8100) ucidef_add_switch "switch0" \ "0@eth0" "2:lan:4" "3:lan:3" "4:lan:2" "5:lan:1" "1:wan" ;; @@ -178,8 +187,6 @@ ath79_setup_interfaces() ;; nec,wg1200cr|\ ubnt,nanostation-ac|\ - ubnt,unifiac-mesh-pro|\ - ubnt,unifiac-pro|\ yuncore,a782|\ yuncore,xd4200) ucidef_add_switch "switch0" \ @@ -232,7 +239,8 @@ ath79_setup_interfaces() tplink,archer-c7-v5|\ tplink,tl-wdr3600-v1|\ tplink,tl-wdr4300-v1|\ - tplink,tl-wdr4300-v1-il) + tplink,tl-wdr4300-v1-il|\ + tplink,tl-wdr4310-v1) ucidef_add_switch "switch0" \ "0@eth0" "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "1:wan" ;; @@ -247,6 +255,11 @@ ath79_setup_interfaces() ucidef_add_switch "switch0" \ "0@eth0" "2:lan:3" "3:lan:2" "4:lan:1" "1:wan" ;; + tplink,archer-d7-v1|\ + tplink,archer-d7b-v1) + ucidef_add_switch "switch0" \ + "0@eth1" "3:lan:3" "4:lan:2" "5:lan:1" "6@eth0" "2:wan:4" "1:wan:5" + ;; tplink,tl-mr6400-v1) ucidef_set_interfaces_lan_wan "eth0.1 eth1" "usb0" ucidef_add_switch "switch0" \ @@ -295,6 +308,11 @@ ath79_setup_interfaces() ucidef_add_switch "switch0" \ "0@eth0" "5:lan" "1:wan" ;; + ubnt,unifiac-mesh-pro|\ + ubnt,unifiac-pro) + ucidef_add_switch "switch0" \ + "0@eth0" "2:lan:1" "3:lan:2" + ;; zbtlink,zbt-wd323|\ xiaomi,mi-router-4q) ucidef_set_interface_wan "eth1" @@ -320,6 +338,10 @@ ath79_setup_macs() alfa-network,ap121f) label_mac=$(mtd_get_mac_binary art 0x1002) ;; + avm,fritz1750e|\ + avm,fritz450e) + label_mac=$(fritz_tffs -n macwlan -i $(find_mtd_part "tffs (1)")) + ;; avm,fritz300e) lan_mac=$(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)")) label_mac=$(fritz_tffs -n macwlan -i $(find_mtd_part "tffs (1)")) @@ -328,6 +350,9 @@ ath79_setup_macs() lan_mac=$(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)")) wan_mac=$(fritz_tffs -n macb -i $(find_mtd_part "tffs (1)")) ;; + devolo,magic-2-wifi) + label_mac=$(macaddr_add "$(mtd_get_mac_binary art 0x1002)" 3) + ;; dlink,dir-825-b1) lan_mac=$(mtd_get_mac_text "caldata" 0xffa0) wan_mac=$(mtd_get_mac_text "caldata" 0xffb4) @@ -407,7 +432,8 @@ ath79_setup_macs() wan_mac=$(mtd_get_mac_binary factory 0x0) lan_mac=$(macaddr_setbit_la "$wan_mac") ;; - sitecom,wlr-7100) + sitecom,wlr-7100|\ + sitecom,wlr-8100) lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr) wan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr) label_mac=$lan_mac @@ -432,7 +458,9 @@ ath79_setup_macs() label_mac=$wan_mac ;; ubnt,airrouter|\ - ubnt,bullet-m|\ + ubnt,bullet-m-ar7240|\ + ubnt,bullet-m-ar7241|\ + ubnt,nanobridge-m|\ ubnt,nanostation-loco-m|\ ubnt,nanostation-m|\ ubnt,picostation-m|\ diff --git a/target/linux/ath79/generic/base-files/etc/board.d/03_gpio_switches b/target/linux/ath79/generic/base-files/etc/board.d/03_gpio_switches index b5b46f16bf..051c468f87 100755 --- a/target/linux/ath79/generic/base-files/etc/board.d/03_gpio_switches +++ b/target/linux/ath79/generic/base-files/etc/board.d/03_gpio_switches @@ -31,6 +31,10 @@ comfast,cf-e5) ucidef_add_gpio_switch "lte_poweroff" "LTE Poweroff" "1" "1" ucidef_add_gpio_switch "lte_reset" "LTE Reset" "12" "1" ;; +devolo,magic-2-wifi) + ucidef_add_gpio_switch "plc_pairing" "PLC pairing" "11" "1" + ucidef_add_gpio_switch "plc_enable" "PLC enable" "13" "1" + ;; dlink,dir-825-c1|\ dlink,dir-835-a1) ucidef_add_gpio_switch "wan_led_auto" "WAN LED Auto" "20" "0" diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom index 6ccdbafc73..c624eac9a2 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom @@ -4,7 +4,6 @@ . /lib/functions.sh . /lib/functions/system.sh -. /lib/functions/mikrotik-caldata.sh ath9k_eeprom_die() { echo "ath9k eeprom: " "$*" @@ -83,7 +82,9 @@ board=$(board_name) case "$FIRMWARE" in "ath9k-eeprom-ahb-18100000.wmac.bin") case $board in - avm,fritz4020) + avm,fritz1750e|\ + avm,fritz4020|\ + avm,fritz450e) ath9k_eeprom_extract_reverse "urlader" 0x1541 0x440 ;; dlink,dir-505|\ @@ -114,10 +115,6 @@ case "$FIRMWARE" in ath9k_eeprom_extract "art" 0x1000 0x440 ath9k_patch_fw_mac $(mtd_get_mac_ascii u-boot-env ethaddr) 0x2 ;; - mikrotik,routerboard-wap-g-5hact2hnd) - mikrotik_caldata_extract "art" 0x1000 0x440 - ath9k_patch_fw_mac $(macaddr_add $(mtd_get_mac_binary art 0x10) +2) - ;; nec,wg800hp) ath9k_eeprom_extract "art" 0x1000 0x440 ath9k_patch_fw_mac $(mtd_get_mac_text board_data 0x680) 0x2 @@ -162,7 +159,9 @@ case "$FIRMWARE" in tplink,tl-wr2543-v1|\ tplink,tl-wr842n-v1|\ ubnt,airrouter|\ - ubnt,bullet-m|\ + ubnt,bullet-m-ar7240|\ + ubnt,bullet-m-ar7241|\ + ubnt,nanobridge-m|\ ubnt,nanostation-loco-m|\ ubnt,nanostation-m|\ ubnt,picostation-m|\ diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index 3450c16340..6f549b4d48 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -2,7 +2,6 @@ . /lib/functions.sh . /lib/functions/k2t.sh -. /lib/functions/mikrotik-caldata.sh ath10kcal_die() { echo "ath10cal: " "$*" @@ -72,8 +71,12 @@ board=$(board_name) case "$FIRMWARE" in "ath10k/cal-pci-0000:00:00.0.bin") case $board in + avm,fritz1750e) + ath10kcal_extract "urlader" 0x198a 0x844 + ;; comfast,cf-wr650ac-v1|\ comfast,cf-wr650ac-v2|\ + devolo,magic-2-wifi|\ ubnt,unifiac-lite|\ ubnt,unifiac-lr|\ ubnt,unifiac-mesh|\ @@ -126,9 +129,6 @@ case "$FIRMWARE" in ath10kcal_extract "art" 0x5000 0x844 ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) +2) ;; - mikrotik,routerboard-wap-g-5hact2hnd) - mikrotik_caldata_extract "art" 0x5000 0x844 - ;; nec,wg800hp) ath10kcal_extract "art" 0x5000 0x844 ath10kcal_patch_mac_crc $(mtd_get_mac_text board_data 0x880) @@ -163,6 +163,11 @@ case "$FIRMWARE" in ath10kcal_extract "art" 0x5000 0x844 ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary romfile 0xf100) +2) ;; + tplink,archer-d7-v1|\ + tplink,archer-d7b-v1) + ath10kcal_extract "art" 0x5000 0x844 + ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary romfs 0xf100) +2) + ;; tplink,re350k-v1) ath10kcal_extract "art" 0x5000 0x844 ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary config 0x10008) +2) @@ -182,6 +187,14 @@ case "$FIRMWARE" in ;; esac ;; +"ath10k/cal-pci-0000:01:00.0.bin") + case $board in + sitecom,wlr-8100) + ath10kcal_extract "art" 0x5000 0x844 + ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) +1) + ;; + esac + ;; "ath10k/pre-cal-pci-0000:00:00.0.bin") case $board in comfast,cf-e313ac) @@ -191,7 +204,9 @@ case "$FIRMWARE" in /lib/firmware/ath10k/QCA9888/hw2.0/board.bin rm /lib/firmware/ath10k/QCA9888/hw2.0/board-2.bin ;; - comfast,cf-e560ac) + comfast,cf-e560ac|\ + comfast,cf-ew72|\ + comfast,cf-wr752ac-v1) ath10kcal_extract "art" 0x5000 0x2f20 ath10kcal_patch_mac_crc $(macaddr_add $(mtd_get_mac_binary art 0x0) +2) ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ @@ -223,6 +238,7 @@ case "$FIRMWARE" in tplink,archer-c59-v2|\ tplink,archer-c60-v1|\ tplink,archer-c60-v2|\ + tplink,archer-c60-v3|\ tplink,archer-c6-v2|\ tplink,archer-c6-v2-us) ath10kcal_extract "art" 0x5000 0x2f20 diff --git a/target/linux/ath79/generic/base-files/etc/uci-defaults/04_led_migration b/target/linux/ath79/generic/base-files/etc/uci-defaults/04_led_migration index 56fac4a36b..cffc2e6c4b 100644 --- a/target/linux/ath79/generic/base-files/etc/uci-defaults/04_led_migration +++ b/target/linux/ath79/generic/base-files/etc/uci-defaults/04_led_migration @@ -24,7 +24,8 @@ tplink,tl-wr902ac-v1) tplink,archer-c7-v2|\ tplink,tl-wdr3600-v1|\ tplink,tl-wdr4300-v1|\ -tplink,tl-wdr4300-v1-il) +tplink,tl-wdr4300-v1-il|\ +tplink,tl-wdr4310-v1) migrate_leds ":blue:=:green:" ;; tplink,re355-v1) diff --git a/target/linux/ath79/generic/base-files/lib/preinit/10_fix_eth_mac.sh b/target/linux/ath79/generic/base-files/lib/preinit/10_fix_eth_mac.sh index a0fb9fc717..b3c3de298e 100644 --- a/target/linux/ath79/generic/base-files/lib/preinit/10_fix_eth_mac.sh +++ b/target/linux/ath79/generic/base-files/lib/preinit/10_fix_eth_mac.sh @@ -4,6 +4,10 @@ preinit_set_mac_address() { case $(board_name) in + avm,fritz1750e|\ + avm,fritz450e) + ip link set dev eth0 address $(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)")) + ;; siemens,ws-ap3610) ip link set dev eth0 address $(mtd_get_mac_ascii cfg1 ethaddr) ;; diff --git a/target/linux/ath79/generic/config-default b/target/linux/ath79/generic/config-default index 6cd1518e3a..5459bafd7d 100644 --- a/target/linux/ath79/generic/config-default +++ b/target/linux/ath79/generic/config-default @@ -1,4 +1,5 @@ CONFIG_AT803X_PHY=y +CONFIG_BCM_NET_PHYLIB=y CONFIG_BROADCOM_PHY=y CONFIG_GPIO_WATCHDOG=y CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y @@ -7,10 +8,9 @@ CONFIG_IP17XX_PHY=y CONFIG_LEDS_RESET=y CONFIG_MARVELL_PHY=y CONFIG_MICREL_PHY=y -CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3 +CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_SPLIT_EVA_FW=y -CONFIG_MTD_SPLIT_MINOR_FW=y CONFIG_PHY_AR7100_USB=y CONFIG_PHY_AR7200_USB=y CONFIG_REGULATOR=y diff --git a/target/linux/ath79/generic/target.mk b/target/linux/ath79/generic/target.mk index 488aa6df16..88346efd2b 100644 --- a/target/linux/ath79/generic/target.mk +++ b/target/linux/ath79/generic/target.mk @@ -1,5 +1,5 @@ BOARDNAME:=Generic -FEATURES += minor squashfs +FEATURES += squashfs DEFAULT_PACKAGES += wpad-basic diff --git a/target/linux/ath79/image/Makefile b/target/linux/ath79/image/Makefile index a28658ec0b..5989f2046f 100644 --- a/target/linux/ath79/image/Makefile +++ b/target/linux/ath79/image/Makefile @@ -73,6 +73,9 @@ include ./generic.mk include ./generic-tp-link.mk include ./generic-ubnt.mk endif +ifeq ($(SUBTARGET),mikrotik) +include ./mikrotik.mk +endif ifeq ($(SUBTARGET),nand) include ./nand.mk endif diff --git a/target/linux/ath79/image/generic-tp-link.mk b/target/linux/ath79/image/generic-tp-link.mk index 33a8ee3f44..2c08f4e37d 100644 --- a/target/linux/ath79/image/generic-tp-link.mk +++ b/target/linux/ath79/image/generic-tp-link.mk @@ -135,6 +135,17 @@ define Device/tplink_archer-c60-v2 endef TARGET_DEVICES += tplink_archer-c60-v2 +define Device/tplink_archer-c60-v3 + $(Device/tplink-safeloader-uimage) + SOC := qca9561 + IMAGE_SIZE := 7808k + DEVICE_MODEL := Archer C60 + DEVICE_VARIANT := v3 + TPLINK_BOARD_ID := ARCHER-C60-V3 + DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9888-ct +endef +TARGET_DEVICES += tplink_archer-c60-v3 + define Device/tplink_archer-c7-v1 $(Device/tplink-8mlzma) SOC := qca9558 @@ -206,6 +217,35 @@ define Device/tplink_archer-d50-v1 endef TARGET_DEVICES += tplink_archer-d50-v1 +define Device/tplink_archer-d7-v1 + $(Device/tplink-v2) + SOC := qca9558 + DEVICE_MODEL := Archer D7 + DEVICE_VARIANT := v1 + DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport \ + kmod-ath10k-ct ath10k-firmware-qca988x-ct + IMAGE_SIZE := 15936k + TPLINK_HWID := 0x89300001 + TPLINK_HWREV := 0x0000002D + TPLINK_FLASHLAYOUT := 16Mqca + TPLINK_HWREVADD := 0x00000002 +endef +TARGET_DEVICES += tplink_archer-d7-v1 + +define Device/tplink_archer-d7b-v1 + $(Device/tplink-v2) + SOC := qca9558 + DEVICE_MODEL := Archer D7b + DEVICE_VARIANT := v1 + DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport \ + kmod-ath10k-ct ath10k-firmware-qca988x-ct + IMAGE_SIZE := 16000k + TPLINK_HWID := 0x89300001 + TPLINK_HWREV := 0x0000003D + TPLINK_FLASHLAYOUT := 16Mqca +endef +TARGET_DEVICES += tplink_archer-d7b-v1 + define Device/tplink_cpe210-v1 $(Device/tplink-safeloader-okli) SOC := ar9344 @@ -416,6 +456,17 @@ define Device/tplink_tl-wdr4300-v1-il endef TARGET_DEVICES += tplink_tl-wdr4300-v1-il +define Device/tplink_tl-wdr4310-v1 + $(Device/tplink-8mlzma) + SOC := ar9344 + DEVICE_MODEL := TL-WDR4310 + DEVICE_VARIANT := v1 + DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport + TPLINK_HWID := 0x43100001 + SUPPORTED_DEVICES += tl-wdr4300 +endef +TARGET_DEVICES += tplink_tl-wdr4310-v1 + define Device/tplink_tl-wdr4900-v2 $(Device/tplink-8mlzma) SOC := qca9558 diff --git a/target/linux/ath79/image/generic-ubnt.mk b/target/linux/ath79/image/generic-ubnt.mk index a4aff09fec..9647e9e86f 100644 --- a/target/linux/ath79/image/generic-ubnt.mk +++ b/target/linux/ath79/image/generic-ubnt.mk @@ -71,7 +71,6 @@ endef define Device/ubnt-xm $(Device/ubnt) - SOC := ar7241 DEVICE_VARIANT := XM DEVICE_PACKAGES += kmod-usb-ohci IMAGE_SIZE := 7448k @@ -108,18 +107,31 @@ TARGET_DEVICES += ubnt_acb-isp define Device/ubnt_airrouter $(Device/ubnt-xm) + SOC := ar7241 DEVICE_MODEL := AirRouter SUPPORTED_DEVICES += airrouter endef TARGET_DEVICES += ubnt_airrouter -define Device/ubnt_bullet-m +define Device/ubnt_bullet-m-ar7240 $(Device/ubnt-xm) + SOC := ar7240 DEVICE_MODEL := Bullet-M + DEVICE_VARIANT := XM (AR7240) DEVICE_PACKAGES += rssileds SUPPORTED_DEVICES += bullet-m endef -TARGET_DEVICES += ubnt_bullet-m +TARGET_DEVICES += ubnt_bullet-m-ar7240 + +define Device/ubnt_bullet-m-ar7241 + $(Device/ubnt-xm) + SOC := ar7241 + DEVICE_MODEL := Bullet-M + DEVICE_VARIANT := XM (AR7241) + DEVICE_PACKAGES += rssileds + SUPPORTED_DEVICES += bullet-m ubnt,bullet-m +endef +TARGET_DEVICES += ubnt_bullet-m-ar7241 define Device/ubnt_bullet-m-xw $(Device/ubnt-xw) @@ -165,6 +177,15 @@ define Device/ubnt_nanobeam-ac endef TARGET_DEVICES += ubnt_nanobeam-ac +define Device/ubnt_nanobridge-m + $(Device/ubnt-xm) + SOC := ar7241 + DEVICE_MODEL := NanoBridge M + DEVICE_PACKAGES += rssileds + SUPPORTED_DEVICES += bullet-m +endef +TARGET_DEVICES += ubnt_nanobridge-m + define Device/ubnt_nanostation-ac $(Device/ubnt-wa) DEVICE_MODEL := Nanostation AC @@ -181,6 +202,7 @@ TARGET_DEVICES += ubnt_nanostation-ac-loco define Device/ubnt_nanostation-loco-m $(Device/ubnt-xm) + SOC := ar7241 DEVICE_MODEL := Nanostation Loco M DEVICE_PACKAGES += rssileds SUPPORTED_DEVICES += bullet-m @@ -197,6 +219,7 @@ TARGET_DEVICES += ubnt_nanostation-loco-m-xw define Device/ubnt_nanostation-m $(Device/ubnt-xm) + SOC := ar7241 DEVICE_MODEL := Nanostation M DEVICE_PACKAGES += rssileds SUPPORTED_DEVICES += nanostation-m @@ -213,6 +236,7 @@ TARGET_DEVICES += ubnt_nanostation-m-xw define Device/ubnt_picostation-m $(Device/ubnt-xm) + SOC := ar7241 DEVICE_MODEL := Picostation M DEVICE_PACKAGES += rssileds SUPPORTED_DEVICES += bullet-m @@ -221,6 +245,7 @@ TARGET_DEVICES += ubnt_picostation-m define Device/ubnt_rocket-m $(Device/ubnt-xm) + SOC := ar7241 DEVICE_MODEL := Rocket-M DEVICE_PACKAGES += rssileds SUPPORTED_DEVICES += rocket-m diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk index cacfa04145..499ce2bb95 100644 --- a/target/linux/ath79/image/generic.mk +++ b/target/linux/ath79/image/generic.mk @@ -1,5 +1,4 @@ include ./common-buffalo.mk -include ./common-mikrotik.mk include ./common-netgear.mk include ./common-tp-link.mk include ./common-yuncore.mk @@ -159,40 +158,58 @@ define Device/aruba_ap-105 DEVICE_VENDOR := Aruba DEVICE_MODEL := AP-105 IMAGE_SIZE := 16000k - DEVICE_PACKAGES := kmod-i2c-core kmod-i2c-gpio kmod-tpm-i2c-atmel + DEVICE_PACKAGES := kmod-i2c-gpio kmod-tpm-i2c-atmel endef TARGET_DEVICES += aruba_ap-105 -define Device/avm_fritz300e - SOC := ar7242 +define Device/avm DEVICE_VENDOR := AVM - DEVICE_MODEL := FRITZ!WLAN Repeater 300E - KERNEL := kernel-bin | append-dtb | lzma | eva-image - KERNEL_INITRAMFS := $$(KERNEL) - IMAGE_SIZE := 15232k - IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | \ - append-squashfs-fakeroot-be | pad-to 256 | append-rootfs | pad-rootfs | \ - append-metadata | check-size $$$$(IMAGE_SIZE) - DEVICE_PACKAGES := fritz-tffs rssileds -swconfig - SUPPORTED_DEVICES += fritz300e -endef -TARGET_DEVICES += avm_fritz300e - -define Device/avm_fritz4020 - SOC := qca9561 - DEVICE_VENDOR := AVM - DEVICE_MODEL := FRITZ!Box 4020 - IMAGE_SIZE := 15232k KERNEL := kernel-bin | append-dtb | lzma | eva-image KERNEL_INITRAMFS := $$(KERNEL) IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | \ append-squashfs-fakeroot-be | pad-to 256 | append-rootfs | pad-rootfs | \ append-metadata | check-size $$$$(IMAGE_SIZE) DEVICE_PACKAGES := fritz-tffs +endef + +define Device/avm_fritz1750e + $(Device/avm) + SOC := qca9556 + IMAGE_SIZE := 15232k + DEVICE_MODEL := FRITZ!WLAN Repeater 1750E + DEVICE_PACKAGES += rssileds kmod-ath10k-ct-smallbuffers \ + ath10k-firmware-qca988x-ct -swconfig +endef +TARGET_DEVICES += avm_fritz1750e + +define Device/avm_fritz300e + $(Device/avm) + SOC := ar7242 + IMAGE_SIZE := 15232k + DEVICE_MODEL := FRITZ!WLAN Repeater 300E + DEVICE_PACKAGES += rssileds -swconfig + SUPPORTED_DEVICES += fritz300e +endef +TARGET_DEVICES += avm_fritz300e + +define Device/avm_fritz4020 + $(Device/avm) + SOC := qca9561 + IMAGE_SIZE := 15232k + DEVICE_MODEL := FRITZ!Box 4020 SUPPORTED_DEVICES += fritz4020 endef TARGET_DEVICES += avm_fritz4020 +define Device/avm_fritz450e + $(Device/avm) + SOC := qca9556 + IMAGE_SIZE := 15232k + DEVICE_MODEL := FRITZ!WLAN Repeater 450E + SUPPORTED_DEVICES += fritz450e +endef +TARGET_DEVICES += avm_fritz450e + define Device/buffalo_bhr-4grv SOC := ar7242 DEVICE_VENDOR := Buffalo @@ -327,6 +344,16 @@ define Device/comfast_cf-e560ac endef TARGET_DEVICES += comfast_cf-e560ac +define Device/comfast_cf-ew72 + SOC := qca9531 + DEVICE_VENDOR := COMFAST + DEVICE_MODEL := CF-EW72 + DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca9888-ct \ + -uboot-envtools -swconfig + IMAGE_SIZE := 16192k +endef +TARGET_DEVICES += comfast_cf-ew72 + define Device/comfast_cf-wr650ac-v1 SOC := qca9558 DEVICE_VENDOR := COMFAST @@ -347,6 +374,17 @@ define Device/comfast_cf-wr650ac-v2 endef TARGET_DEVICES += comfast_cf-wr650ac-v2 +define Device/comfast_cf-wr752ac-v1 + SOC := qca9531 + DEVICE_VENDOR := COMFAST + DEVICE_MODEL := CF-WR752AC + DEVICE_VARIANT := v1 + DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca9888-ct \ + -uboot-envtools + IMAGE_SIZE := 16192k +endef +TARGET_DEVICES += comfast_cf-wr752ac-v1 + define Device/devolo_dvl1200e SOC := qca9558 DEVICE_VENDOR := devolo @@ -401,6 +439,15 @@ define Device/devolo_dvl1750x endef TARGET_DEVICES += devolo_dvl1750x +define Device/devolo_magic-2-wifi + SOC := ar9344 + DEVICE_VENDOR := Devolo + DEVICE_MODEL := Magic 2 WiFi + DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct + IMAGE_SIZE := 15872k +endef +TARGET_DEVICES += devolo_magic-2-wifi + define Device/dlink_dir-505 SOC := ar9330 DEVICE_VENDOR := D-Link @@ -756,19 +803,6 @@ define Device/librerouter_librerouter-v1 endef TARGET_DEVICES += librerouter_librerouter-v1 -define Device/mikrotik_routerboard-wap-g-5hact2hnd - $(Device/mikrotik) - SOC := qca9556 - DEVICE_MODEL := RouterBOARD wAP G-5HacT2HnD (wAP AC) - IMAGE_SIZE := 16256k - IMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 -e | \ - pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \ - append-metadata | check-size $$$$(IMAGE_SIZE) - DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct - SUPPORTED_DEVICES += rb-wapg-5hact2hnd -endef -TARGET_DEVICES += mikrotik_routerboard-wap-g-5hact2hnd - define Device/nec_wg1200cr SOC := qca9563 DEVICE_VENDOR := NEC @@ -1012,7 +1046,7 @@ define Device/pisen_wmb001n DEVICE_VENDOR := PISEN DEVICE_MODEL := WMB001N IMAGE_SIZE := 14080k - DEVICE_PACKAGES := kmod-i2c-core kmod-i2c-gpio kmod-usb2 + DEVICE_PACKAGES := kmod-i2c-gpio kmod-usb2 LOADER_TYPE := bin LOADER_FLASH_OFFS := 0x20000 COMPILE := loader-$(1).bin loader-$(1).uImage @@ -1086,6 +1120,22 @@ define Device/sitecom_wlr-7100 endef TARGET_DEVICES += sitecom_wlr-7100 +define Device/sitecom_wlr-8100 + SOC := qca9558 + DEVICE_VENDOR := Sitecom + DEVICE_MODEL := WLR-8100 + DEVICE_ALT0_VENDOR := Sitecom + DEVICE_ALT0_MODEL := X8 AC1750 + DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct kmod-usb2 kmod-usb3 + SUPPORTED_DEVICES += wlr8100 + IMAGES += factory.dlf + IMAGE/factory.dlf := append-kernel | pad-to $$$$(BLOCKSIZE) | \ + append-rootfs | pad-rootfs | check-size $$$$(IMAGE_SIZE) | \ + senao-header -r 0x222 -p 0x56 -t 2 + IMAGE_SIZE := 15424k +endef +TARGET_DEVICES += sitecom_wlr-8100 + define Device/teltonika_rut955 SOC := ar9344 DEVICE_VENDOR := Teltonika @@ -1157,7 +1207,7 @@ define Device/winchannel_wb2000 DEVICE_VENDOR := Winchannel DEVICE_MODEL := WB2000 IMAGE_SIZE := 15872k - DEVICE_PACKAGES := kmod-i2c-core kmod-i2c-gpio kmod-rtc-ds1307 kmod-usb2 \ + DEVICE_PACKAGES := kmod-i2c-gpio kmod-rtc-ds1307 kmod-usb2 \ kmod-usb-ledtrig-usbport endef TARGET_DEVICES += winchannel_wb2000 @@ -1208,7 +1258,7 @@ define Device/zbtlink_zbt-wd323 DEVICE_VENDOR := ZBT DEVICE_MODEL := WD323 IMAGE_SIZE := 16000k - DEVICE_PACKAGES := kmod-usb2 kmod-i2c-core kmod-i2c-gpio kmod-rtc-pcf8563 \ + DEVICE_PACKAGES := kmod-usb2 kmod-i2c-gpio kmod-rtc-pcf8563 \ kmod-usb-serial kmod-usb-serial-cp210x uqmi endef TARGET_DEVICES += zbtlink_zbt-wd323 diff --git a/target/linux/ath79/image/mikrotik.mk b/target/linux/ath79/image/mikrotik.mk new file mode 100644 index 0000000000..a89dc8c170 --- /dev/null +++ b/target/linux/ath79/image/mikrotik.mk @@ -0,0 +1,26 @@ +include ./common-mikrotik.mk + +define Device/mikrotik_routerboard-922uags-5hpacd + $(Device/mikrotik) + SOC := qca9558 + DEVICE_MODEL := RouterBOARD 922UAGS-5HPacD + IMAGE/sysupgrade.bin = append-kernel | kernel2minor -s 2048 -e -c | \ + sysupgrade-tar kernel=$$$$@ | append-metadata + DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct \ + kmod-usb2 nand-utils + SUPPORTED_DEVICES += rb-922uags-5hpacd +endef +TARGET_DEVICES += mikrotik_routerboard-922uags-5hpacd + +define Device/mikrotik_routerboard-wap-g-5hact2hnd + $(Device/mikrotik) + SOC := qca9556 + DEVICE_MODEL := RouterBOARD wAP G-5HacT2HnD (wAP AC) + IMAGE_SIZE := 16256k + IMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 -e | \ + pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \ + append-metadata | check-size $$$$(IMAGE_SIZE) + DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct + SUPPORTED_DEVICES += rb-wapg-5hact2hnd +endef +TARGET_DEVICES += mikrotik_routerboard-wap-g-5hact2hnd diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk index 95ddca26b0..7d283b54c4 100644 --- a/target/linux/ath79/image/nand.mk +++ b/target/linux/ath79/image/nand.mk @@ -1,5 +1,7 @@ include ./common-netgear.mk # for netgear-uImage +DEVICE_VARS += RAS_ROOTFS_SIZE RAS_BOARD RAS_VERSION + # attention: only zlib compression is allowed for the boot fs define Build/zyxel-buildkerneljffs rm -rf $(KDIR_TMP)/zyxelnbg6716 @@ -46,6 +48,24 @@ define Device/aerohive_hiveap-121 endef TARGET_DEVICES += aerohive_hiveap-121 +define Device/domywifi_dw33d + SOC := qca9558 + DEVICE_VENDOR := DomyWifi + DEVICE_MODEL := DW33D + DEVICE_PACKAGES := kmod-usb2 kmod-usb-storage kmod-usb-ledtrig-usbport \ + kmod-ath10k-ct ath10k-firmware-qca988x-ct + KERNEL_SIZE := 5120k + IMAGE_SIZE := 98304k + BLOCKSIZE := 128k + PAGESIZE := 2048 + UBINIZE_OPTS := -E 5 + IMAGES += factory.bin + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | \ + check-size $$$$(IMAGE_SIZE) +endef +TARGET_DEVICES += domywifi_dw33d + define Device/glinet_gl-ar300m-common-nand SOC := qca9531 DEVICE_VENDOR := GL.iNet @@ -96,7 +116,7 @@ define Device/glinet_gl-ar750s-nor-nand GL_UBOOT_UBI_OFFSET := 2048k IMAGES += factory.img IMAGE/factory.img := append-kernel | pad-to $$$$(GL_UBOOT_UBI_OFFSET) | \ - append-ubi | check-kernel-size $$$$(GL_UBOOT_UBI_OFFSET) + append-ubi | check-kernel-size $$$$(GL_UBOOT_UBI_OFFSET) IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata SUPPORTED_DEVICES += glinet,gl-ar750s-nor endef @@ -198,4 +218,3 @@ define Device/zyxel_nbg6716 UBINIZE_OPTS := -E 5 endef TARGET_DEVICES += zyxel_nbg6716 -DEVICE_VARS += RAS_ROOTFS_SIZE RAS_BOARD RAS_VERSION diff --git a/target/linux/ath79/image/tiny-tp-link.mk b/target/linux/ath79/image/tiny-tp-link.mk index 29fdfec1e5..c6ef224da3 100644 --- a/target/linux/ath79/image/tiny-tp-link.mk +++ b/target/linux/ath79/image/tiny-tp-link.mk @@ -66,6 +66,16 @@ define Device/tplink_tl-mr3420-v2 endef TARGET_DEVICES += tplink_tl-mr3420-v2 +define Device/tplink_tl-mr3420-v3 + $(Device/tplink-4mlzma) + SOC := qca9531 + DEVICE_MODEL := TL-MR3420 + DEVICE_VARIANT := v3 + TPLINK_HWID := 0x34200003 + DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport +endef +TARGET_DEVICES += tplink_tl-mr3420-v3 + define Device/tplink_tl-wa701nd-v1 $(Device/tplink-4m) SOC := ar7240 @@ -130,6 +140,16 @@ define Device/tplink_tl-wa850re-v2 endef TARGET_DEVICES += tplink_tl-wa850re-v2 +define Device/tplink_tl-wa860re-v1 + $(Device/tplink-4mlzma) + SOC := ar9341 + DEVICE_MODEL := TL-WA860RE + DEVICE_VARIANT := v1 + TPLINK_HWID := 0x08600001 + SUPPORTED_DEVICES += tl-wa860re +endef +TARGET_DEVICES += tplink_tl-wa860re-v1 + define Device/tplink_tl-wa901nd-v1 $(Device/tplink-4m) SOC := ar7240 @@ -146,6 +166,7 @@ define Device/tplink_tl-wa901nd-v2 DEVICE_MODEL := TL-WA901ND DEVICE_VARIANT := v2 TPLINK_HWID := 0x09010002 + SUPPORTED_DEVICES += tl-wa901nd-v2 endef TARGET_DEVICES += tplink_tl-wa901nd-v2 @@ -186,6 +207,15 @@ define Device/tplink_tl-wr740n-v4 endef TARGET_DEVICES += tplink_tl-wr740n-v4 +define Device/tplink_tl-wr740n-v5 + $(Device/tplink-4mlzma) + SOC := ar9331 + DEVICE_MODEL := TL-WR740N + DEVICE_VARIANT := v5 + TPLINK_HWID := 0x07400005 +endef +TARGET_DEVICES += tplink_tl-wr740n-v5 + define Device/tplink_tl-wr741-v1 $(Device/tplink-4m) SOC := ar7240 diff --git a/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network b/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network new file mode 100755 index 0000000000..ee795c7496 --- /dev/null +++ b/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network @@ -0,0 +1,39 @@ +#!/bin/sh + +. /lib/functions/system.sh +. /lib/functions/uci-defaults.sh + +ath79_setup_interfaces() +{ + local board="$1" + + case "$board" in + mikrotik,routerboard-922uags-5hpacd|\ + mikrotik,routerboard-wap-g-5hact2hnd) + ucidef_set_interface_lan "eth0" + ;; + *) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ;; + esac +} + +ath79_setup_macs() +{ + local board="$1" + + case "$board" in + esac + + [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac + [ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac +} + +board_config_update +board=$(board_name) +ath79_setup_interfaces $board +ath79_setup_macs $board +board_config_flush + +exit 0 diff --git a/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom new file mode 100644 index 0000000000..6b5e079f7b --- /dev/null +++ b/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom @@ -0,0 +1,54 @@ +#!/bin/sh + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 + +. /lib/functions/caldata.sh +. /lib/functions/mikrotik-caldata.sh + +ath9k_eeprom_die() { + echo "ath9k eeprom: " "$*" + exit 1 +} + +ath9k_patch_fw_mac() { + local mac=$1 + local mac_offset=$(($2)) + local chksum_offset=$3 + local xor_mac + local xor_fw_mac + local xor_fw_chksum + + [ -z "$mac" -o -z "$mac_offset" ] && return + + [ -n "$chksum_offset" ] && { + xor_mac=${mac//:/} + xor_mac="${xor_mac:0:4} ${xor_mac:4:4} ${xor_mac:8:4}" + + xor_fw_mac=$(hexdump -v -n 6 -s $mac_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE) + xor_fw_mac="${xor_fw_mac:0:4} ${xor_fw_mac:4:4} ${xor_fw_mac:8:4}" + + xor_fw_chksum=$(hexdump -v -n 2 -s $chksum_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE) + xor_fw_chksum=$(xor $xor_fw_chksum $xor_fw_mac $xor_mac) + + printf "%b" "\x${xor_fw_chksum:0:2}\x${xor_fw_chksum:2:2}" | \ + dd of=/lib/firmware/$FIRMWARE conv=notrunc bs=1 seek=$(($chksum_offset)) count=2 + } + + macaddr_2bin $mac | dd of=/lib/firmware/$FIRMWARE conv=notrunc oflag=seek_bytes bs=6 seek=$mac_offset count=1 +} + +board=$(board_name) + +case "$FIRMWARE" in +"ath9k-eeprom-ahb-18100000.wmac.bin") + case $board in + mikrotik,routerboard-wap-g-5hact2hnd) + mikrotik_caldata_extract "art" 0x1000 0x440 + ath9k_patch_fw_mac $(macaddr_add $(mtd_get_mac_binary art 0x10) +2) + ;; + *) + ath9k_eeprom_die "board $board is not supported yet" + ;; + esac + ;; +esac diff --git a/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/11-ath10k-caldata new file mode 100644 index 0000000000..2521f0ad96 --- /dev/null +++ b/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -0,0 +1,28 @@ +#!/bin/sh + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 + +. /lib/functions/caldata.sh +. /lib/functions/mikrotik-caldata.sh + +board=$(board_name) + +case "$FIRMWARE" in +"ath10k/cal-pci-0000:00:00.0.bin") + case $board in + mikrotik,routerboard-wap-g-5hact2hnd) + mikrotik_caldata_extract "hard_config" 0x5000 0x844 + ;; + esac + ;; +"ath10k/cal-pci-0000:01:00.0.bin") + case $board in + mikrotik,routerboard-922uags-5hpacd) + mikrotik_caldata_extract "hard_config" 0x5000 0x844 + ;; + esac + ;; +*) + exit 1 + ;; +esac diff --git a/target/linux/ath79/mikrotik/base-files/etc/uci-defaults/04_led_migration b/target/linux/ath79/mikrotik/base-files/etc/uci-defaults/04_led_migration new file mode 100644 index 0000000000..1a7b371a99 --- /dev/null +++ b/target/linux/ath79/mikrotik/base-files/etc/uci-defaults/04_led_migration @@ -0,0 +1,17 @@ +#!/bin/sh + +. /lib/functions.sh +. /lib/functions/migrations.sh + +board=$(board_name) +boardonly="${board##*,}" + +case "$board" in +mikrotik,*) + migrate_leds "^rb:=mikrotik:" + ;; +esac + +migrations_apply system + +exit 0 diff --git a/target/linux/ath79/base-files/lib/functions/mikrotik-caldata.sh b/target/linux/ath79/mikrotik/base-files/lib/functions/mikrotik-caldata.sh similarity index 70% rename from target/linux/ath79/base-files/lib/functions/mikrotik-caldata.sh rename to target/linux/ath79/mikrotik/base-files/lib/functions/mikrotik-caldata.sh index 9c4016ee5d..71a1bf02f3 100644 --- a/target/linux/ath79/base-files/lib/functions/mikrotik-caldata.sh +++ b/target/linux/ath79/mikrotik/base-files/lib/functions/mikrotik-caldata.sh @@ -9,13 +9,18 @@ mikrotik_caldata_extract() { local offset=$(($2)) local count=$(($3)) local mtd - local erdfile="/lib/firmware/erd.bin" + local erdfile="/tmp/erd.bin" + local fwfile="/lib/firmware/${FIRMWARE}" + + [ -e $fwfile ] && exit 0 mtd=$(find_mtd_chardev $part) [ -n "$mtd" ] || caldata_die "no mtd device found for partition $part" rbextract -e $mtd $erdfile - dd if=$erdfile of=/lib/firmware/$FIRMWARE iflag=skip_bytes bs=$count skip=$offset count=1 2>/dev/null || \ + dd if=$erdfile of=$fwfile iflag=skip_bytes bs=$count skip=$offset count=1 2>/dev/null || \ caldata_die "failed to extract calibration data from $mtd" + + rm -f $erdfile } diff --git a/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh b/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000000..d2e43d404f --- /dev/null +++ b/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh @@ -0,0 +1,41 @@ +# Copyright (C) 2011 OpenWrt.org + +PART_NAME=firmware + +REQUIRE_IMAGE_METADATA=1 +platform_check_image() { + return 0 +} + +RAMFS_COPY_BIN='fw_printenv fw_setenv nandwrite' +RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock' + +platform_do_upgrade_mikrotik_nand() { + CI_KERNPART=none + + local fw_mtd=$(find_mtd_part kernel) + fw_mtd="${fw_mtd/block/}" + [ -n "$fw_mtd" ] || return + + local board_dir=$(tar tf "$1" | grep -m 1 '^sysupgrade-.*/$') + board_dir=${board_dir%/} + [ -n "$board_dir" ] || return + + mtd erase kernel + tar xf "$1" ${board_dir}/kernel -O | nandwrite -o "$fw_mtd" - + + nand_do_upgrade "$1" +} + +platform_do_upgrade() { + local board=$(board_name) + + case "$board" in + mikrotik,routerboard-922uags-5hpacd) + platform_do_upgrade_mikrotik_nand "$1" + ;; + *) + default_do_upgrade "$1" + ;; + esac +} diff --git a/target/linux/ath79/mikrotik/config-default b/target/linux/ath79/mikrotik/config-default new file mode 100644 index 0000000000..c0c61985bc --- /dev/null +++ b/target/linux/ath79/mikrotik/config-default @@ -0,0 +1,34 @@ +CONFIG_AT803X_PHY=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_GPIO_LATCH=y +CONFIG_GPIO_WATCHDOG=y +CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y +CONFIG_LEDS_RESET=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_AR934X=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SPLIT_MINOR_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_NET_SWITCHDEV=y +CONFIG_PHY_AR7100_USB=y +CONFIG_PHY_AR7200_USB=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/ath79/mikrotik/profiles/00-default.mk b/target/linux/ath79/mikrotik/profiles/00-default.mk new file mode 100644 index 0000000000..14712da593 --- /dev/null +++ b/target/linux/ath79/mikrotik/profiles/00-default.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2020 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile (all drivers) + PACKAGES:= \ + kmod-usb-ohci kmod-usb2 nand-utils + PRIORITY := 1 +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,Default)) diff --git a/target/linux/ath79/mikrotik/target.mk b/target/linux/ath79/mikrotik/target.mk new file mode 100644 index 0000000000..face016a51 --- /dev/null +++ b/target/linux/ath79/mikrotik/target.mk @@ -0,0 +1,9 @@ +BOARDNAME := MikroTik devices +FEATURES += minor nand squashfs + +DEFAULT_PACKAGES += wpad-basic + +define Target/Description + Build firmware images for MikroTik devices based on Qualcomm Atheros + MIPS SoCs (AR71xx, AR72xx, AR91xx, AR93xx, QCA95xx). +endef diff --git a/target/linux/ath79/nand/base-files/etc/board.d/02_network b/target/linux/ath79/nand/base-files/etc/board.d/02_network index bd02a4b383..b2191eed92 100755 --- a/target/linux/ath79/nand/base-files/etc/board.d/02_network +++ b/target/linux/ath79/nand/base-files/etc/board.d/02_network @@ -11,6 +11,10 @@ ath79_setup_interfaces() aerohive,hiveap-121) ucidef_set_interface_lan "eth0" ;; + domywifi,dw33d) + ucidef_add_switch "switch0" \ + "0@eth0" "1:wan" "2:lan" "3:lan" "4:lan" "5:lan" "6@eth1" + ;; glinet,gl-ar750s-nor|\ glinet,gl-ar750s-nor-nand) ucidef_add_switch "switch0" \ @@ -44,10 +48,6 @@ ath79_setup_macs() netgear,wndr4500-v3) wan_mac=$(mtd_get_mac_binary caldata 0x6) ;; - zyxel,nbg6716) - lan_mac=$(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) +2) - wan_mac=$(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) +3) - ;; esac [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac diff --git a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index 3b09a634ff..bedd02006a 100644 --- a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -32,6 +32,10 @@ board=$(board_name) case "$FIRMWARE" in "ath10k/cal-pci-0000:00:00.0.bin") case $board in + domywifi,dw33d) + ath10kcal_extract "art" 0x5000 0x844 + ath10kcal_patch_mac $(mtd_get_mac_binary art 0x12) + ;; glinet,gl-ar750s-nor|\ glinet,gl-ar750s-nor-nand) ath10kcal_extract "art" 0x5000 0x844 diff --git a/target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac b/target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac new file mode 100644 index 0000000000..6c61e5df00 --- /dev/null +++ b/target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac @@ -0,0 +1,18 @@ +[ "$ACTION" = "add" ] || exit 0 + +PHYNBR=${DEVPATH##*/phy} + +[ -n $PHYNBR ] || exit 0 + +. /lib/functions.sh +. /lib/functions/system.sh + +board=$(board_name) + +case $board in + zyxel,nbg6716) + # Set mac address for 2.4g device + [ "$PHYNBR" -eq 1 ] && \ + mtd_get_mac_ascii u-boot-env ethaddr > /sys${DEVPATH}/macaddress + ;; +esac diff --git a/target/linux/ath79/nand/base-files/lib/preinit/10_fix_eth_mac.sh b/target/linux/ath79/nand/base-files/lib/preinit/10_fix_eth_mac.sh new file mode 100644 index 0000000000..fdd8381f56 --- /dev/null +++ b/target/linux/ath79/nand/base-files/lib/preinit/10_fix_eth_mac.sh @@ -0,0 +1,14 @@ +. /lib/functions.sh +. /lib/functions/system.sh + +preinit_set_mac_address() { + case $(board_name) in + zyxel,nbg6716) + ethaddr=$(mtd_get_mac_ascii u-boot-env ethaddr) + ip link set dev eth0 address $(macaddr_add $ethaddr 2) + ip link set dev eth1 address $(macaddr_add $ethaddr 3) + ;; + esac +} + +boot_hook_add preinit_main preinit_set_mac_address diff --git a/target/linux/ath79/nand/base-files/lib/upgrade/platform.sh b/target/linux/ath79/nand/base-files/lib/upgrade/platform.sh index 15d88a361e..ea77345b06 100644 --- a/target/linux/ath79/nand/base-files/lib/upgrade/platform.sh +++ b/target/linux/ath79/nand/base-files/lib/upgrade/platform.sh @@ -7,7 +7,7 @@ platform_check_image() { return 0 } -RAMFS_COPY_BIN='fw_printenv fw_setenv' +RAMFS_COPY_BIN='fw_printenv fw_setenv nandwrite' RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock' platform_do_upgrade() { diff --git a/target/linux/ath79/nand/config-default b/target/linux/ath79/nand/config-default index 4742ad52d0..738f2f0a5e 100644 --- a/target/linux/ath79/nand/config-default +++ b/target/linux/ath79/nand/config-default @@ -1,18 +1,28 @@ +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LZO=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_AR934X=y CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_RAW_NAND=y CONFIG_MTD_SPI_NAND=y CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y # CONFIG_MTD_UBI_FASTMAP is not set # CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 # CONFIG_PCI_AR71XX is not set -# CONFIG_PHY_AR7100_USB is not set CONFIG_PHY_AR7200_USB=y +CONFIG_SGL_ALLOC=y CONFIG_UBIFS_FS=y CONFIG_UBIFS_FS_ADVANCED_COMPR=y CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_ZSTD is not set +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/ath79/patches-4.14/0001-tty-serial-drop-QCA-pecific-SoC-symbols.patch b/target/linux/ath79/patches-4.14/0001-tty-serial-drop-QCA-pecific-SoC-symbols.patch deleted file mode 100644 index 6c4b907e22..0000000000 --- a/target/linux/ath79/patches-4.14/0001-tty-serial-drop-QCA-pecific-SoC-symbols.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 58812f6d0f1e11b03ed266038ed3b7274ab6f121 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 09:26:32 +0100 -Subject: [PATCH 01/27] tty: serial: drop QCA pecific SoC symbols - -Signed-off-by: John Crispin ---- - drivers/tty/serial/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/tty/serial/Kconfig -+++ b/drivers/tty/serial/Kconfig -@@ -1463,7 +1463,7 @@ config SERIAL_XILINX_PS_UART_CONSOLE - - config SERIAL_AR933X - tristate "AR933X serial port support" -- depends on HAVE_CLK && SOC_AR933X -+ depends on HAVE_CLK && ATH79 - select SERIAL_CORE - help - If you have an Atheros AR933X SOC based board and want to use the diff --git a/target/linux/ath79/patches-4.14/0006-usb-drop-deprecated-symbols.patch b/target/linux/ath79/patches-4.14/0006-usb-drop-deprecated-symbols.patch deleted file mode 100644 index a97fab71f4..0000000000 --- a/target/linux/ath79/patches-4.14/0006-usb-drop-deprecated-symbols.patch +++ /dev/null @@ -1,51 +0,0 @@ -From bd17da5b6297e0e52b787049292d076ad415362a Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 10:04:54 +0100 -Subject: [PATCH 06/27] usb: drop deprecated symbols - -Signed-off-by: John Crispin ---- - drivers/usb/host/Kconfig | 25 ------------------------- - 1 file changed, 25 deletions(-) - ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -297,19 +297,6 @@ config USB_CNS3XXX_EHCI - It is needed for high-speed (480Mbit/sec) USB 2.0 device - support. - --config USB_EHCI_ATH79 -- bool "EHCI support for AR7XXX/AR9XXX SoCs (DEPRECATED)" -- depends on (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X) -- select USB_EHCI_ROOT_HUB_TT -- select USB_EHCI_HCD_PLATFORM -- default y -- ---help--- -- This option is deprecated now and the driver was removed, use -- USB_EHCI_HCD_PLATFORM instead. -- -- Enables support for the built-in EHCI controller present -- on the Atheros AR7XXX/AR9XXX SoCs. -- - config USB_EHCI_HCD_PLATFORM - tristate "Generic EHCI driver for a platform device" - default n -@@ -493,18 +480,6 @@ config USB_OHCI_HCD_DAVINCI - controller. This driver cannot currently be a loadable - module because it lacks a proper PHY abstraction. - --config USB_OHCI_ATH79 -- bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs (DEPRECATED)" -- depends on (SOC_AR71XX || SOC_AR724X) -- select USB_OHCI_HCD_PLATFORM -- default y -- help -- This option is deprecated now and the driver was removed, use -- USB_OHCI_HCD_PLATFORM instead. -- -- Enables support for the built-in OHCI controller present on the -- Atheros AR71XX/AR7240 SoCs. -- - config USB_OHCI_HCD_PPC_OF_BE - bool "OHCI support for OF platform bus (big endian)" - depends on PPC diff --git a/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch b/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch deleted file mode 100644 index a8092177b4..0000000000 --- a/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch +++ /dev/null @@ -1,980 +0,0 @@ -From e93fe20529aeb8738b87533f66c46e2c21524530 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Tue, 6 Mar 2018 10:06:10 +0100 -Subject: [PATCH 09/33] MIPS: ath79: add lots of missing registers - -This patch adds many new registers for various QCA MIPS SoCs. The patch is -an aggragate of many contributions made to OpenWrt. - -Signed-off-by: Gabor Juhos -Signed-off-by: Henryk Heisig -Signed-off-by: Matthias Schiffer -Signed-off-by: Weijie Gao -Signed-off-by: Felix Fietkau -Signed-off-by: Julien Dusser -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 771 ++++++++++++++++++++++++- - 1 file changed, 770 insertions(+), 1 deletion(-) - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -20,6 +20,10 @@ - #include - - #define AR71XX_APB_BASE 0x18000000 -+#define AR71XX_GE0_BASE 0x19000000 -+#define AR71XX_GE0_SIZE 0x10000 -+#define AR71XX_GE1_BASE 0x1a000000 -+#define AR71XX_GE1_SIZE 0x10000 - #define AR71XX_EHCI_BASE 0x1b000000 - #define AR71XX_EHCI_SIZE 0x1000 - #define AR71XX_OHCI_BASE 0x1c000000 -@@ -39,6 +43,8 @@ - #define AR71XX_PLL_SIZE 0x100 - #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) - #define AR71XX_RESET_SIZE 0x100 -+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR71XX_MII_SIZE 0x100 - - #define AR71XX_PCI_MEM_BASE 0x10000000 - #define AR71XX_PCI_MEM_SIZE 0x07000000 -@@ -81,18 +87,39 @@ - - #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) - #define AR933X_UART_SIZE 0x14 -+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR933X_GMAC_SIZE 0x04 - #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define AR933X_WMAC_SIZE 0x20000 - #define AR933X_EHCI_BASE 0x1b000000 - #define AR933X_EHCI_SIZE 0x1000 - -+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR934X_GMAC_SIZE 0x14 - #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define AR934X_WMAC_SIZE 0x20000 - #define AR934X_EHCI_BASE 0x1b000000 - #define AR934X_EHCI_SIZE 0x200 -+#define AR934X_NFC_BASE 0x1b000200 -+#define AR934X_NFC_SIZE 0xb8 - #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) - #define AR934X_SRIF_SIZE 0x1000 - -+#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA953X_GMAC_SIZE 0x14 -+#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -+#define QCA953X_WMAC_SIZE 0x20000 -+#define QCA953X_EHCI_BASE 0x1b000000 -+#define QCA953X_EHCI_SIZE 0x200 -+#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) -+#define QCA953X_SRIF_SIZE 0x1000 -+ -+#define QCA953X_PCI_CFG_BASE0 0x14000000 -+#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) -+#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) -+#define QCA953X_PCI_MEM_BASE0 0x10000000 -+#define QCA953X_PCI_MEM_SIZE 0x02000000 -+ - #define QCA955X_PCI_MEM_BASE0 0x10000000 - #define QCA955X_PCI_MEM_BASE1 0x12000000 - #define QCA955X_PCI_MEM_SIZE 0x02000000 -@@ -106,11 +133,72 @@ - #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) - #define QCA955X_PCI_CTRL_SIZE 0x100 - -+#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA955X_GMAC_SIZE 0x40 - #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define QCA955X_WMAC_SIZE 0x20000 - #define QCA955X_EHCI0_BASE 0x1b000000 - #define QCA955X_EHCI1_BASE 0x1b400000 - #define QCA955X_EHCI_SIZE 0x1000 -+#define QCA955X_NFC_BASE 0x1b800200 -+#define QCA955X_NFC_SIZE 0xb8 -+ -+#define QCA956X_PCI_MEM_BASE1 0x12000000 -+#define QCA956X_PCI_MEM_SIZE 0x02000000 -+#define QCA956X_PCI_CFG_BASE1 0x16000000 -+#define QCA956X_PCI_CFG_SIZE 0x1000 -+#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) -+#define QCA956X_PCI_CRP_SIZE 0x1000 -+#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) -+#define QCA956X_PCI_CTRL_SIZE 0x100 -+ -+#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -+#define QCA956X_WMAC_SIZE 0x20000 -+#define QCA956X_EHCI0_BASE 0x1b000000 -+#define QCA956X_EHCI1_BASE 0x1b400000 -+#define QCA956X_EHCI_SIZE 0x200 -+#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA956X_GMAC_SGMII_SIZE 0x64 -+#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000) -+#define QCA956X_PLL_SIZE 0x50 -+#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA956X_GMAC_SIZE 0x64 -+ -+/* -+ * Hidden Registers -+ */ -+#define QCA956X_MAC_CFG_BASE 0xb9000000 -+#define QCA956X_MAC_CFG_SIZE 0x64 -+ -+#define QCA956X_MAC_CFG1_REG 0x00 -+#define QCA956X_MAC_CFG1_SOFT_RST BIT(31) -+#define QCA956X_MAC_CFG1_RX_RST BIT(19) -+#define QCA956X_MAC_CFG1_TX_RST BIT(18) -+#define QCA956X_MAC_CFG1_LOOPBACK BIT(8) -+#define QCA956X_MAC_CFG1_RX_EN BIT(2) -+#define QCA956X_MAC_CFG1_TX_EN BIT(0) -+ -+#define QCA956X_MAC_CFG2_REG 0x04 -+#define QCA956X_MAC_CFG2_IF_1000 BIT(9) -+#define QCA956X_MAC_CFG2_IF_10_100 BIT(8) -+#define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5) -+#define QCA956X_MAC_CFG2_LEN_CHECK BIT(4) -+#define QCA956X_MAC_CFG2_PAD_CRC_EN BIT(2) -+#define QCA956X_MAC_CFG2_FDX BIT(0) -+ -+#define QCA956X_MAC_MII_MGMT_CFG_REG 0x20 -+#define QCA956X_MGMT_CFG_CLK_DIV_20 0x07 -+ -+#define QCA956X_MAC_FIFO_CFG0_REG 0x48 -+#define QCA956X_MAC_FIFO_CFG1_REG 0x4c -+#define QCA956X_MAC_FIFO_CFG2_REG 0x50 -+#define QCA956X_MAC_FIFO_CFG3_REG 0x54 -+#define QCA956X_MAC_FIFO_CFG4_REG 0x58 -+#define QCA956X_MAC_FIFO_CFG5_REG 0x5c -+ -+#define QCA956X_DAM_RESET_OFFSET 0xb90001bc -+#define QCA956X_DAM_RESET_SIZE 0x4 -+#define QCA956X_INLINE_CHKSUM_ENG BIT(27) - - /* - * DDR_CTRL block -@@ -149,6 +237,12 @@ - #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 - #define AR934X_DDR_REG_FLUSH_WMAC 0xac - -+#define QCA953X_DDR_REG_FLUSH_GE0 0x9c -+#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 -+#define QCA953X_DDR_REG_FLUSH_USB 0xa4 -+#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 -+#define QCA953X_DDR_REG_FLUSH_WMAC 0xac -+ - /* - * PLL block - */ -@@ -166,9 +260,15 @@ - #define AR71XX_AHB_DIV_SHIFT 20 - #define AR71XX_AHB_DIV_MASK 0x7 - -+#define AR71XX_ETH0_PLL_SHIFT 17 -+#define AR71XX_ETH1_PLL_SHIFT 19 -+ - #define AR724X_PLL_REG_CPU_CONFIG 0x00 - #define AR724X_PLL_REG_PCIE_CONFIG 0x10 - -+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16) -+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25) -+ - #define AR724X_PLL_FB_SHIFT 0 - #define AR724X_PLL_FB_MASK 0x3ff - #define AR724X_PLL_REF_DIV_SHIFT 10 -@@ -178,6 +278,8 @@ - #define AR724X_DDR_DIV_SHIFT 22 - #define AR724X_DDR_DIV_MASK 0x3 - -+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c -+ - #define AR913X_PLL_REG_CPU_CONFIG 0x00 - #define AR913X_PLL_REG_ETH_CONFIG 0x04 - #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 -@@ -190,6 +292,9 @@ - #define AR913X_AHB_DIV_SHIFT 19 - #define AR913X_AHB_DIV_MASK 0x1 - -+#define AR913X_ETH0_PLL_SHIFT 20 -+#define AR913X_ETH1_PLL_SHIFT 22 -+ - #define AR933X_PLL_CPU_CONFIG_REG 0x00 - #define AR933X_PLL_CLOCK_CTRL_REG 0x08 - -@@ -211,6 +316,8 @@ - #define AR934X_PLL_CPU_CONFIG_REG 0x00 - #define AR934X_PLL_DDR_CONFIG_REG 0x04 - #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 -+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 -+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c - - #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 - #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -243,9 +350,52 @@ - #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) - #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) -+ -+#define QCA953X_PLL_CPU_CONFIG_REG 0x00 -+#define QCA953X_PLL_DDR_CONFIG_REG 0x04 -+#define QCA953X_PLL_CLK_CTRL_REG 0x08 -+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 -+#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c -+#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48 -+ -+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 -+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 -+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f -+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 -+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff -+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 -+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f -+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) -+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) -+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) -+ - #define QCA955X_PLL_CPU_CONFIG_REG 0x00 - #define QCA955X_PLL_DDR_CONFIG_REG 0x04 - #define QCA955X_PLL_CLK_CTRL_REG 0x08 -+#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 -+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 -+#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c - - #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 - #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -278,6 +428,81 @@ - #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) - #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -+#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2) -+#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1) -+#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0) -+ -+#define QCA956X_PLL_CPU_CONFIG_REG 0x00 -+#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 -+#define QCA956X_PLL_DDR_CONFIG_REG 0x08 -+#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c -+#define QCA956X_PLL_CLK_CTRL_REG 0x10 -+#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28 -+#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30 -+#define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c -+ -+#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -+#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff -+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 -+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff -+ -+#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -+#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff -+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 -+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff -+ -+#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -+#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -+#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) -+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) -+#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) -+ -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8 -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0xf -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP BIT(12) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2 BIT(13) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1 BIT(14) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2 BIT(15) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE BIT(16) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE BIT(17) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL BIT(18) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL BIT(19) -+ -+#define QCA956X_PLL_ETH_XMII_TX_INVERT BIT(1) -+#define QCA956X_PLL_ETH_XMII_GIGE BIT(25) -+#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT 28 -+#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK 0x3 -+#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT 26 -+#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK 3 -+ -+#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2) -+#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1) -+#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0) -+ - /* - * USB_CONFIG block - */ -@@ -317,10 +542,19 @@ - #define AR934X_RESET_REG_BOOTSTRAP 0xb0 - #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac - -+#define QCA953X_RESET_REG_RESET_MODULE 0x1c -+#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 -+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac -+ - #define QCA955X_RESET_REG_RESET_MODULE 0x1c - #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 - #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac - -+#define QCA956X_RESET_REG_RESET_MODULE 0x1c -+#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 -+#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac -+ -+#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) - #define MISC_INT_ETHSW BIT(12) - #define MISC_INT_TIMER4 BIT(10) - #define MISC_INT_TIMER3 BIT(9) -@@ -370,16 +604,123 @@ - #define AR913X_RESET_USB_HOST BIT(5) - #define AR913X_RESET_USB_PHY BIT(4) - -+#define AR933X_RESET_GE1_MDIO BIT(23) -+#define AR933X_RESET_GE0_MDIO BIT(22) -+#define AR933X_RESET_GE1_MAC BIT(13) - #define AR933X_RESET_WMAC BIT(11) -+#define AR933X_RESET_GE0_MAC BIT(9) - #define AR933X_RESET_USB_HOST BIT(5) - #define AR933X_RESET_USB_PHY BIT(4) - #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) - -+#define AR934X_RESET_HOST BIT(31) -+#define AR934X_RESET_SLIC BIT(30) -+#define AR934X_RESET_HDMA BIT(29) -+#define AR934X_RESET_EXTERNAL BIT(28) -+#define AR934X_RESET_RTC BIT(27) -+#define AR934X_RESET_PCIE_EP_INT BIT(26) -+#define AR934X_RESET_CHKSUM_ACC BIT(25) -+#define AR934X_RESET_FULL_CHIP BIT(24) -+#define AR934X_RESET_GE1_MDIO BIT(23) -+#define AR934X_RESET_GE0_MDIO BIT(22) -+#define AR934X_RESET_CPU_NMI BIT(21) -+#define AR934X_RESET_CPU_COLD BIT(20) -+#define AR934X_RESET_HOST_RESET_INT BIT(19) -+#define AR934X_RESET_PCIE_EP BIT(18) -+#define AR934X_RESET_UART1 BIT(17) -+#define AR934X_RESET_DDR BIT(16) -+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -+#define AR934X_RESET_NANDF BIT(14) -+#define AR934X_RESET_GE1_MAC BIT(13) -+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) - #define AR934X_RESET_USB_PHY_ANALOG BIT(11) -+#define AR934X_RESET_HOST_DMA_INT BIT(10) -+#define AR934X_RESET_GE0_MAC BIT(9) -+#define AR934X_RESET_ETH_SWITCH BIT(8) -+#define AR934X_RESET_PCIE_PHY BIT(7) -+#define AR934X_RESET_PCIE BIT(6) - #define AR934X_RESET_USB_HOST BIT(5) - #define AR934X_RESET_USB_PHY BIT(4) - #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) -+#define AR934X_RESET_LUT BIT(2) -+#define AR934X_RESET_MBOX BIT(1) -+#define AR934X_RESET_I2S BIT(0) -+ -+#define QCA953X_RESET_USB_EXT_PWR BIT(29) -+#define QCA953X_RESET_EXTERNAL BIT(28) -+#define QCA953X_RESET_RTC BIT(27) -+#define QCA953X_RESET_FULL_CHIP BIT(24) -+#define QCA953X_RESET_GE1_MDIO BIT(23) -+#define QCA953X_RESET_GE0_MDIO BIT(22) -+#define QCA953X_RESET_CPU_NMI BIT(21) -+#define QCA953X_RESET_CPU_COLD BIT(20) -+#define QCA953X_RESET_DDR BIT(16) -+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -+#define QCA953X_RESET_GE1_MAC BIT(13) -+#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) -+#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) -+#define QCA953X_RESET_GE0_MAC BIT(9) -+#define QCA953X_RESET_ETH_SWITCH BIT(8) -+#define QCA953X_RESET_PCIE_PHY BIT(7) -+#define QCA953X_RESET_PCIE BIT(6) -+#define QCA953X_RESET_USB_HOST BIT(5) -+#define QCA953X_RESET_USB_PHY BIT(4) -+#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) -+ -+#define QCA955X_RESET_HOST BIT(31) -+#define QCA955X_RESET_SLIC BIT(30) -+#define QCA955X_RESET_HDMA BIT(29) -+#define QCA955X_RESET_EXTERNAL BIT(28) -+#define QCA955X_RESET_RTC BIT(27) -+#define QCA955X_RESET_PCIE_EP_INT BIT(26) -+#define QCA955X_RESET_CHKSUM_ACC BIT(25) -+#define QCA955X_RESET_FULL_CHIP BIT(24) -+#define QCA955X_RESET_GE1_MDIO BIT(23) -+#define QCA955X_RESET_GE0_MDIO BIT(22) -+#define QCA955X_RESET_CPU_NMI BIT(21) -+#define QCA955X_RESET_CPU_COLD BIT(20) -+#define QCA955X_RESET_HOST_RESET_INT BIT(19) -+#define QCA955X_RESET_PCIE_EP BIT(18) -+#define QCA955X_RESET_UART1 BIT(17) -+#define QCA955X_RESET_DDR BIT(16) -+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -+#define QCA955X_RESET_NANDF BIT(14) -+#define QCA955X_RESET_GE1_MAC BIT(13) -+#define QCA955X_RESET_SGMII_ANALOG BIT(12) -+#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) -+#define QCA955X_RESET_HOST_DMA_INT BIT(10) -+#define QCA955X_RESET_GE0_MAC BIT(9) -+#define QCA955X_RESET_SGMII BIT(8) -+#define QCA955X_RESET_PCIE_PHY BIT(7) -+#define QCA955X_RESET_PCIE BIT(6) -+#define QCA955X_RESET_USB_HOST BIT(5) -+#define QCA955X_RESET_USB_PHY BIT(4) -+#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) -+#define QCA955X_RESET_LUT BIT(2) -+#define QCA955X_RESET_MBOX BIT(1) -+#define QCA955X_RESET_I2S BIT(0) -+ -+#define QCA956X_RESET_EXTERNAL BIT(28) -+#define QCA956X_RESET_FULL_CHIP BIT(24) -+#define QCA956X_RESET_GE1_MDIO BIT(23) -+#define QCA956X_RESET_GE0_MDIO BIT(22) -+#define QCA956X_RESET_CPU_NMI BIT(21) -+#define QCA956X_RESET_CPU_COLD BIT(20) -+#define QCA956X_RESET_DMA BIT(19) -+#define QCA956X_RESET_DDR BIT(16) -+#define QCA956X_RESET_GE1_MAC BIT(13) -+#define QCA956X_RESET_SGMII_ANALOG BIT(12) -+#define QCA956X_RESET_USB_PHY_ANALOG BIT(11) -+#define QCA956X_RESET_GE0_MAC BIT(9) -+#define QCA956X_RESET_SGMII BIT(8) -+#define QCA956X_RESET_USB_HOST BIT(5) -+#define QCA956X_RESET_USB_PHY BIT(4) -+#define QCA956X_RESET_USBSUS_OVERRIDE BIT(3) -+#define QCA956X_RESET_SWITCH_ANALOG BIT(2) -+#define QCA956X_RESET_SWITCH BIT(0) - -+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) -+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) - #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) - - #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -@@ -398,8 +739,17 @@ - #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) - #define AR934X_BOOTSTRAP_DDR1 BIT(0) - -+#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) -+#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) -+#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) -+#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) -+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) -+#define QCA953X_BOOTSTRAP_DDR1 BIT(0) -+ - #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) - -+#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) -+ - #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) - #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) - #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -@@ -418,6 +768,24 @@ - AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ - AR934X_PCIE_WMAC_INT_PCIE_RC3) - -+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) -+#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) -+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) -+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ -+ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ -+ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) -+ -+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ -+ (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ -+ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ -+ QCA953X_PCIE_WMAC_INT_PCIE_RC3) -+ - #define QCA955X_EXT_INT_WMAC_MISC BIT(0) - #define QCA955X_EXT_INT_WMAC_TX BIT(1) - #define QCA955X_EXT_INT_WMAC_RXLP BIT(2) -@@ -449,6 +817,37 @@ - QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ - QCA955X_EXT_INT_PCIE_RC2_INT3) - -+#define QCA956X_EXT_INT_WMAC_MISC BIT(0) -+#define QCA956X_EXT_INT_WMAC_TX BIT(1) -+#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) -+#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) -+#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) -+#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) -+#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) -+#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) -+#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) -+#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) -+#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) -+#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) -+#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) -+#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) -+#define QCA956X_EXT_INT_USB1 BIT(24) -+#define QCA956X_EXT_INT_USB2 BIT(28) -+ -+#define QCA956X_EXT_INT_WMAC_ALL \ -+ (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ -+ QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) -+ -+#define QCA956X_EXT_INT_PCIE_RC1_ALL \ -+ (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ -+ QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ -+ QCA956X_EXT_INT_PCIE_RC1_INT3) -+ -+#define QCA956X_EXT_INT_PCIE_RC2_ALL \ -+ (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ -+ QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ -+ QCA956X_EXT_INT_PCIE_RC2_INT3) -+ - #define REV_ID_MAJOR_MASK 0xfff0 - #define REV_ID_MAJOR_AR71XX 0x00a0 - #define REV_ID_MAJOR_AR913X 0x00b0 -@@ -460,8 +859,12 @@ - #define REV_ID_MAJOR_AR9341 0x0120 - #define REV_ID_MAJOR_AR9342 0x1120 - #define REV_ID_MAJOR_AR9344 0x2120 -+#define REV_ID_MAJOR_QCA9533 0x0140 -+#define REV_ID_MAJOR_QCA9533_V2 0x0160 - #define REV_ID_MAJOR_QCA9556 0x0130 - #define REV_ID_MAJOR_QCA9558 0x1130 -+#define REV_ID_MAJOR_TP9343 0x0150 -+#define REV_ID_MAJOR_QCA956X 0x1150 - - #define AR71XX_REV_ID_MINOR_MASK 0x3 - #define AR71XX_REV_ID_MINOR_AR7130 0x0 -@@ -482,8 +885,12 @@ - - #define AR934X_REV_ID_REVISION_MASK 0xf - -+#define QCA953X_REV_ID_REVISION_MASK 0xf -+ - #define QCA955X_REV_ID_REVISION_MASK 0xf - -+#define QCA956X_REV_ID_REVISION_MASK 0xf -+ - /* - * SPI block - */ -@@ -521,15 +928,63 @@ - #define AR71XX_GPIO_REG_INT_ENABLE 0x24 - #define AR71XX_GPIO_REG_FUNC 0x28 - -+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c -+#define AR934X_GPIO_REG_OUT_FUNC1 0x30 -+#define AR934X_GPIO_REG_OUT_FUNC2 0x34 -+#define AR934X_GPIO_REG_OUT_FUNC3 0x38 -+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c -+#define AR934X_GPIO_REG_OUT_FUNC5 0x40 - #define AR934X_GPIO_REG_FUNC 0x6c - -+#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c -+#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 -+#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 -+#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 -+#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c -+#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 -+#define QCA953X_GPIO_REG_FUNC 0x6c -+ -+#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 -+#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 -+#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 -+#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 -+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 -+ -+#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c -+#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 -+#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 -+#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 -+#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c -+#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 -+#define QCA955X_GPIO_REG_FUNC 0x6c -+ -+#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c -+#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 -+#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 -+#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 -+#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c -+#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 -+#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 -+#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 -+#define QCA956X_GPIO_REG_FUNC 0x6c -+ -+#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 -+#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 -+ - #define AR71XX_GPIO_COUNT 16 - #define AR7240_GPIO_COUNT 18 - #define AR7241_GPIO_COUNT 20 - #define AR913X_GPIO_COUNT 22 - #define AR933X_GPIO_COUNT 30 - #define AR934X_GPIO_COUNT 23 -+#define QCA953X_GPIO_COUNT 18 - #define QCA955X_GPIO_COUNT 24 -+#define QCA956X_GPIO_COUNT 23 - - /* - * SRIF block -@@ -552,4 +1007,318 @@ - #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 - #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 - -+#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 -+#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 -+#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 -+ -+#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 -+#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 -+#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 -+ -+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 -+#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f -+#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 -+#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff -+#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff -+ -+#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) -+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 -+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 -+ -+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) -+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) -+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) -+#define AR71XX_GPIO_FUNC_UART_EN BIT(8) -+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) -+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) -+ -+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) -+#define AR724X_GPIO_FUNC_SPI_EN BIT(18) -+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) -+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) -+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) -+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) -+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -+#define AR724X_GPIO_FUNC_UART_EN BIT(1) -+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) -+ -+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) -+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) -+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) -+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) -+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) -+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) -+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) -+#define AR913X_GPIO_FUNC_UART_EN BIT(8) -+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) -+ -+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) -+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) -+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) -+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) -+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) -+#define AR933X_GPIO_FUNC_SPI_EN BIT(18) -+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -+#define AR933X_GPIO_FUNC_UART_EN BIT(1) -+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) -+ -+#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) -+#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) -+#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) -+#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) -+#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) -+#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) -+#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) -+#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) -+#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) -+ -+#define AR934X_GPIO_OUT_GPIO 0 -+#define AR934X_GPIO_OUT_SPI_CS1 7 -+#define AR934X_GPIO_OUT_LED_LINK0 41 -+#define AR934X_GPIO_OUT_LED_LINK1 42 -+#define AR934X_GPIO_OUT_LED_LINK2 43 -+#define AR934X_GPIO_OUT_LED_LINK3 44 -+#define AR934X_GPIO_OUT_LED_LINK4 45 -+#define AR934X_GPIO_OUT_EXT_LNA0 46 -+#define AR934X_GPIO_OUT_EXT_LNA1 47 -+ -+#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9) -+#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8) -+#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7) -+#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6) -+#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5) -+#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4) -+#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3) -+#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1) -+ -+#define QCA955X_GPIO_OUT_GPIO 0 -+#define QCA955X_MII_EXT_MDI 1 -+#define QCA955X_SLIC_DATA_OUT 3 -+#define QCA955X_SLIC_PCM_FS 4 -+#define QCA955X_SLIC_PCM_CLK 5 -+#define QCA955X_SPI_CLK 8 -+#define QCA955X_SPI_CS_0 9 -+#define QCA955X_SPI_CS_1 10 -+#define QCA955X_SPI_CS_2 11 -+#define QCA955X_SPI_MISO 12 -+#define QCA955X_I2S_CLK 13 -+#define QCA955X_I2S_WS 14 -+#define QCA955X_I2S_SD 15 -+#define QCA955X_I2S_MCK 16 -+#define QCA955X_SPDIF_OUT 17 -+#define QCA955X_UART1_TD 18 -+#define QCA955X_UART1_RTS 19 -+#define QCA955X_UART1_RD 20 -+#define QCA955X_UART1_CTS 21 -+#define QCA955X_UART0_SOUT 22 -+#define QCA955X_SPDIF2_OUT 23 -+#define QCA955X_LED_SGMII_SPEED0 24 -+#define QCA955X_LED_SGMII_SPEED1 25 -+#define QCA955X_LED_SGMII_DUPLEX 26 -+#define QCA955X_LED_SGMII_LINK_UP 27 -+#define QCA955X_SGMII_SPEED0_INVERT 28 -+#define QCA955X_SGMII_SPEED1_INVERT 29 -+#define QCA955X_SGMII_DUPLEX_INVERT 30 -+#define QCA955X_SGMII_LINK_UP_INVERT 31 -+#define QCA955X_GE1_MII_MDO 32 -+#define QCA955X_GE1_MII_MDC 33 -+#define QCA955X_SWCOM2 38 -+#define QCA955X_SWCOM3 39 -+#define QCA955X_MAC2_GPIO 40 -+#define QCA955X_MAC3_GPIO 41 -+#define QCA955X_ATT_LED 42 -+#define QCA955X_PWR_LED 43 -+#define QCA955X_TX_FRAME 44 -+#define QCA955X_RX_CLEAR_EXTERNAL 45 -+#define QCA955X_LED_NETWORK_EN 46 -+#define QCA955X_LED_POWER_EN 47 -+#define QCA955X_WMAC_GLUE_WOW 68 -+#define QCA955X_RX_CLEAR_EXTENSION 70 -+#define QCA955X_CP_NAND_CS1 73 -+#define QCA955X_USB_SUSPEND 74 -+#define QCA955X_ETH_TX_ERR 75 -+#define QCA955X_DDR_DQ_OE 76 -+#define QCA955X_CLKREQ_N_EP 77 -+#define QCA955X_CLKREQ_N_RC 78 -+#define QCA955X_CLK_OBS0 79 -+#define QCA955X_CLK_OBS1 80 -+#define QCA955X_CLK_OBS2 81 -+#define QCA955X_CLK_OBS3 82 -+#define QCA955X_CLK_OBS4 83 -+#define QCA955X_CLK_OBS5 84 -+ -+/* -+ * MII_CTRL block -+ */ -+#define AR71XX_MII_REG_MII0_CTRL 0x00 -+#define AR71XX_MII_REG_MII1_CTRL 0x04 -+ -+#define AR71XX_MII_CTRL_IF_MASK 3 -+#define AR71XX_MII_CTRL_SPEED_SHIFT 4 -+#define AR71XX_MII_CTRL_SPEED_MASK 3 -+#define AR71XX_MII_CTRL_SPEED_10 0 -+#define AR71XX_MII_CTRL_SPEED_100 1 -+#define AR71XX_MII_CTRL_SPEED_1000 2 -+ -+#define AR71XX_MII0_CTRL_IF_GMII 0 -+#define AR71XX_MII0_CTRL_IF_MII 1 -+#define AR71XX_MII0_CTRL_IF_RGMII 2 -+#define AR71XX_MII0_CTRL_IF_RMII 3 -+ -+#define AR71XX_MII1_CTRL_IF_RGMII 0 -+#define AR71XX_MII1_CTRL_IF_RMII 1 -+ -+/* -+ * AR933X GMAC interface -+ */ -+#define AR933X_GMAC_REG_ETH_CFG 0x00 -+ -+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) -+#define AR933X_ETH_CFG_MII_GE0 BIT(1) -+#define AR933X_ETH_CFG_GMII_GE0 BIT(2) -+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) -+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) -+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) -+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) -+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) -+#define AR933X_ETH_CFG_RMII_GE0 BIT(9) -+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 -+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) -+ -+/* -+ * AR934X GMAC Interface -+ */ -+#define AR934X_GMAC_REG_ETH_CFG 0x00 -+ -+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) -+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) -+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) -+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) -+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) -+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) -+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) -+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) -+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) -+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) -+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) -+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) -+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -+#define AR934X_ETH_CFG_RXD_DELAY BIT(14) -+#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 -+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 -+#define AR934X_ETH_CFG_RDV_DELAY BIT(16) -+#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 -+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 -+ -+/* -+ * QCA953X GMAC Interface -+ */ -+#define QCA953X_GMAC_REG_ETH_CFG 0x00 -+ -+#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) -+#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) -+#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) -+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -+ -+/* -+ * QCA955X GMAC Interface -+ */ -+ -+#define QCA955X_GMAC_REG_ETH_CFG 0x00 -+#define QCA955X_GMAC_REG_SGMII_SERDES 0x18 -+ -+#define QCA955X_ETH_CFG_RGMII_EN BIT(0) -+#define QCA955X_ETH_CFG_MII_GE0 BIT(1) -+#define QCA955X_ETH_CFG_GMII_GE0 BIT(2) -+#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3) -+#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4) -+#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5) -+#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) -+#define QCA955X_ETH_CFG_RMII_GE0 BIT(10) -+#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11) -+#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12) -+#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14 -+#define QCA955X_ETH_CFG_RDV_DELAY BIT(16) -+#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16 -+#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18 -+#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 -+ -+#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) -+#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 -+#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf -+/* -+ * QCA956X GMAC Interface -+ */ -+ -+#define QCA956X_GMAC_REG_ETH_CFG 0x00 -+#define QCA956X_GMAC_REG_SGMII_RESET 0x14 -+#define QCA956X_GMAC_REG_SGMII_SERDES 0x18 -+#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c -+#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34 -+#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58 -+ -+#define QCA956X_ETH_CFG_RGMII_EN BIT(0) -+#define QCA956X_ETH_CFG_GE0_SGMII BIT(6) -+#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7) -+#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8) -+#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9) -+#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10) -+#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -+#define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3 -+#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14 -+#define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3 -+#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16 -+ -+#define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0 -+#define QCA956X_SGMII_RESET_RX_CLK_N BIT(0) -+#define QCA956X_SGMII_RESET_TX_CLK_N BIT(1) -+#define QCA956X_SGMII_RESET_RX_125M_N BIT(2) -+#define QCA956X_SGMII_RESET_TX_125M_N BIT(3) -+#define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4) -+ -+#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3 -+#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1 -+#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7 -+#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4 -+#define QCA956X_SGMII_SERDES_PLL_BW BIT(8) -+#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9) -+#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10) -+#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) -+#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16) -+#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17) -+#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 -+#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf -+#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27 -+#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf -+ -+#define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12) -+#define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15) -+ -+#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 -+#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 -+ - #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ath79/patches-4.14/0010-MIPS-ath79-add-support-for-QCA953x-QCA956x-TP9343.patch b/target/linux/ath79/patches-4.14/0010-MIPS-ath79-add-support-for-QCA953x-QCA956x-TP9343.patch deleted file mode 100644 index 1a87f52d18..0000000000 --- a/target/linux/ath79/patches-4.14/0010-MIPS-ath79-add-support-for-QCA953x-QCA956x-TP9343.patch +++ /dev/null @@ -1,400 +0,0 @@ -From 2741304648dbdab7697d7758166a582b5291c53d Mon Sep 17 00:00:00 2001 -From: Matthias Schiffer -Date: Sat, 23 Jun 2018 15:08:56 +0200 -Subject: [PATCH 10/33] MIPS: ath79: add support for QCA953x QCA956x TP9343 - -This patch adds support for 2 new types of QCA silicon. TP9343 is -essentially the same as the QCA956X but is licensed by TPLink. - -Signed-off-by: Weijie Gao -Signed-off-by: Matthias Schiffer -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 193 +++++++++++++++++++++++++++++++ - arch/mips/ath79/common.c | 8 ++ - arch/mips/ath79/early_printk.c | 4 + - arch/mips/ath79/setup.c | 34 +++++- - arch/mips/include/asm/mach-ath79/ath79.h | 33 ++++++ - 5 files changed, 269 insertions(+), 3 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(vo - iounmap(dpll_base); - } - -+static void __init qca953x_clocks_init(void) -+{ -+ unsigned long ref_rate; -+ unsigned long cpu_rate; -+ unsigned long ddr_rate; -+ unsigned long ahb_rate; -+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; -+ u32 cpu_pll, ddr_pll; -+ u32 bootstrap; -+ -+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); -+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40) -+ ref_rate = 40 * 1000 * 1000; -+ else -+ ref_rate = 25 * 1000 * 1000; -+ -+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG); -+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & -+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -+ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK; -+ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) & -+ QCA953X_PLL_CPU_CONFIG_NINT_MASK; -+ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) & -+ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK; -+ -+ cpu_pll = nint * ref_rate / ref_div; -+ cpu_pll += frac * (ref_rate >> 6) / ref_div; -+ cpu_pll /= (1 << out_div); -+ -+ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG); -+ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & -+ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -+ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK; -+ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) & -+ QCA953X_PLL_DDR_CONFIG_NINT_MASK; -+ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) & -+ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK; -+ -+ ddr_pll = nint * ref_rate / ref_div; -+ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4); -+ ddr_pll /= (1 << out_div); -+ -+ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG); -+ -+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & -+ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS) -+ cpu_rate = ref_rate; -+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) -+ cpu_rate = cpu_pll / (postdiv + 1); -+ else -+ cpu_rate = ddr_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & -+ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS) -+ ddr_rate = ref_rate; -+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) -+ ddr_rate = ddr_pll / (postdiv + 1); -+ else -+ ddr_rate = cpu_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & -+ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS) -+ ahb_rate = ref_rate; -+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) -+ ahb_rate = ddr_pll / (postdiv + 1); -+ else -+ ahb_rate = cpu_pll / (postdiv + 1); -+ -+ ath79_add_sys_clkdev("ref", ref_rate); -+ ath79_add_sys_clkdev("cpu", cpu_rate); -+ ath79_add_sys_clkdev("ddr", ddr_rate); -+ ath79_add_sys_clkdev("ahb", ahb_rate); -+ -+ clk_add_alias("wdt", NULL, "ref", NULL); -+ clk_add_alias("uart", NULL, "ref", NULL); -+} -+ - static void __init qca955x_clocks_init(void) - { - unsigned long ref_rate; -@@ -440,6 +525,110 @@ static void __init qca955x_clocks_init(v - clk_add_alias("uart", NULL, "ref", NULL); - } - -+static void __init qca956x_clocks_init(void) -+{ -+ unsigned long ref_rate; -+ unsigned long cpu_rate; -+ unsigned long ddr_rate; -+ unsigned long ahb_rate; -+ u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; -+ u32 cpu_pll, ddr_pll; -+ u32 bootstrap; -+ -+ /* -+ * QCA956x timer init workaround has to be applied right before setting -+ * up the clock. Else, there will be no jiffies -+ */ -+ u32 misc; -+ -+ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); -+ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK; -+ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); -+ -+ bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP); -+ if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40) -+ ref_rate = 40 * 1000 * 1000; -+ else -+ ref_rate = 25 * 1000 * 1000; -+ -+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG); -+ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK; -+ -+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG); -+ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG1_NINT_MASK; -+ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK; -+ lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK; -+ -+ cpu_pll = nint * ref_rate / ref_div; -+ cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); -+ cpu_pll += (hfrac >> 13) * ref_rate / ref_div; -+ cpu_pll /= (1 << out_div); -+ -+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG); -+ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK; -+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG); -+ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG1_NINT_MASK; -+ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK; -+ lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK; -+ -+ ddr_pll = nint * ref_rate / ref_div; -+ ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); -+ ddr_pll += (hfrac >> 13) * ref_rate / ref_div; -+ ddr_pll /= (1 << out_div); -+ -+ clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG); -+ -+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & -+ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS) -+ cpu_rate = ref_rate; -+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL) -+ cpu_rate = ddr_pll / (postdiv + 1); -+ else -+ cpu_rate = cpu_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & -+ QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS) -+ ddr_rate = ref_rate; -+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL) -+ ddr_rate = cpu_pll / (postdiv + 1); -+ else -+ ddr_rate = ddr_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & -+ QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS) -+ ahb_rate = ref_rate; -+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) -+ ahb_rate = ddr_pll / (postdiv + 1); -+ else -+ ahb_rate = cpu_pll / (postdiv + 1); -+ -+ ath79_add_sys_clkdev("ref", ref_rate); -+ ath79_add_sys_clkdev("cpu", cpu_rate); -+ ath79_add_sys_clkdev("ddr", ddr_rate); -+ ath79_add_sys_clkdev("ahb", ahb_rate); -+ -+ clk_add_alias("wdt", NULL, "ref", NULL); -+ clk_add_alias("uart", NULL, "ref", NULL); -+} -+ - void __init ath79_clocks_init(void) - { - if (soc_is_ar71xx()) -@@ -450,8 +639,12 @@ void __init ath79_clocks_init(void) - ar933x_clocks_init(); - else if (soc_is_ar934x()) - ar934x_clocks_init(); -+ else if (soc_is_qca953x()) -+ qca953x_clocks_init(); - else if (soc_is_qca955x()) - qca955x_clocks_init(); -+ else if (soc_is_qca956x() || soc_is_tp9343()) -+ qca956x_clocks_init(); - else - BUG(); - } ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -103,8 +103,12 @@ void ath79_device_reset_set(u32 mask) - reg = AR933X_RESET_REG_RESET_MODULE; - else if (soc_is_ar934x()) - reg = AR934X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca953x()) -+ reg = QCA953X_RESET_REG_RESET_MODULE; - else if (soc_is_qca955x()) - reg = QCA955X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca956x() || soc_is_tp9343()) -+ reg = QCA956X_RESET_REG_RESET_MODULE; - else - BUG(); - -@@ -131,8 +135,12 @@ void ath79_device_reset_clear(u32 mask) - reg = AR933X_RESET_REG_RESET_MODULE; - else if (soc_is_ar934x()) - reg = AR934X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca953x()) -+ reg = QCA953X_RESET_REG_RESET_MODULE; - else if (soc_is_qca955x()) - reg = QCA955X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca956x() || soc_is_tp9343()) -+ reg = QCA956X_RESET_REG_RESET_MODULE; - else - BUG(); - ---- a/arch/mips/ath79/early_printk.c -+++ b/arch/mips/ath79/early_printk.c -@@ -76,8 +76,12 @@ static void prom_putchar_init(void) - case REV_ID_MAJOR_AR9341: - case REV_ID_MAJOR_AR9342: - case REV_ID_MAJOR_AR9344: -+ case REV_ID_MAJOR_QCA9533: -+ case REV_ID_MAJOR_QCA9533_V2: - case REV_ID_MAJOR_QCA9556: - case REV_ID_MAJOR_QCA9558: -+ case REV_ID_MAJOR_TP9343: -+ case REV_ID_MAJOR_QCA956X: - _prom_putchar = prom_putchar_ar71xx; - break; - ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type - u32 major; - u32 minor; - u32 rev = 0; -+ u32 ver = 1; - - id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); - major = id & REV_ID_MAJOR_MASK; -@@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type - rev = id & AR934X_REV_ID_REVISION_MASK; - break; - -+ case REV_ID_MAJOR_QCA9533_V2: -+ ver = 2; -+ ath79_soc_rev = 2; -+ /* drop through */ -+ -+ case REV_ID_MAJOR_QCA9533: -+ ath79_soc = ATH79_SOC_QCA9533; -+ chip = "9533"; -+ rev = id & QCA953X_REV_ID_REVISION_MASK; -+ break; -+ - case REV_ID_MAJOR_QCA9556: - ath79_soc = ATH79_SOC_QCA9556; - chip = "9556"; -@@ -164,14 +176,30 @@ static void __init ath79_detect_sys_type - rev = id & QCA955X_REV_ID_REVISION_MASK; - break; - -+ case REV_ID_MAJOR_QCA956X: -+ ath79_soc = ATH79_SOC_QCA956X; -+ chip = "956X"; -+ rev = id & QCA956X_REV_ID_REVISION_MASK; -+ break; -+ -+ case REV_ID_MAJOR_TP9343: -+ ath79_soc = ATH79_SOC_TP9343; -+ chip = "9343"; -+ rev = id & QCA956X_REV_ID_REVISION_MASK; -+ break; -+ - default: - panic("ath79: unknown SoC, id:0x%08x", id); - } - -- ath79_soc_rev = rev; -+ if (ver == 1) -+ ath79_soc_rev = rev; - -- if (soc_is_qca955x()) -- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", -+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x()) -+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", -+ chip, ver, rev); -+ else if (soc_is_tp9343()) -+ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u", - chip, rev); - else - sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -32,8 +32,11 @@ enum ath79_soc_type { - ATH79_SOC_AR9341, - ATH79_SOC_AR9342, - ATH79_SOC_AR9344, -+ ATH79_SOC_QCA9533, - ATH79_SOC_QCA9556, - ATH79_SOC_QCA9558, -+ ATH79_SOC_TP9343, -+ ATH79_SOC_QCA956X, - }; - - extern enum ath79_soc_type ath79_soc; -@@ -100,6 +103,16 @@ static inline int soc_is_ar934x(void) - return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); - } - -+static inline int soc_is_qca9533(void) -+{ -+ return ath79_soc == ATH79_SOC_QCA9533; -+} -+ -+static inline int soc_is_qca953x(void) -+{ -+ return soc_is_qca9533(); -+} -+ - static inline int soc_is_qca9556(void) - { - return ath79_soc == ATH79_SOC_QCA9556; -@@ -115,6 +128,26 @@ static inline int soc_is_qca955x(void) - return soc_is_qca9556() || soc_is_qca9558(); - } - -+static inline int soc_is_tp9343(void) -+{ -+ return ath79_soc == ATH79_SOC_TP9343; -+} -+ -+static inline int soc_is_qca9561(void) -+{ -+ return ath79_soc == ATH79_SOC_QCA956X; -+} -+ -+static inline int soc_is_qca9563(void) -+{ -+ return ath79_soc == ATH79_SOC_QCA956X; -+} -+ -+static inline int soc_is_qca956x(void) -+{ -+ return soc_is_qca9561() || soc_is_qca9563(); -+} -+ - void ath79_ddr_wb_flush(unsigned int reg); - void ath79_ddr_set_pci_windows(void); - diff --git a/target/linux/ath79/patches-4.14/0014-MIPS-ath79-finetune-cpu-overrides.patch b/target/linux/ath79/patches-4.14/0014-MIPS-ath79-finetune-cpu-overrides.patch deleted file mode 100644 index 534111c2b0..0000000000 --- a/target/linux/ath79/patches-4.14/0014-MIPS-ath79-finetune-cpu-overrides.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 30dc99e95ac4410072850ae466f696cb56097bb4 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Mon, 5 Mar 2018 11:35:29 +0100 -Subject: [PATCH 14/33] MIPS: ath79: finetune cpu-overrides - -This patch adds a few additional cpu feature overrides so that they do not -need to be probed at runtime. - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h -+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h -@@ -36,6 +36,7 @@ - #define cpu_has_mdmx 0 - #define cpu_has_mips3d 0 - #define cpu_has_smartmips 0 -+#define cpu_has_rixi 0 - - #define cpu_has_mips32r1 1 - #define cpu_has_mips32r2 1 -@@ -43,6 +44,7 @@ - #define cpu_has_mips64r2 0 - - #define cpu_has_mipsmt 0 -+#define cpu_has_userlocal 0 - - #define cpu_has_64bits 0 - #define cpu_has_64bit_zero_reg 0 -@@ -51,5 +53,9 @@ - - #define cpu_dcache_line_size() 32 - #define cpu_icache_line_size() 32 -+#define cpu_has_vtag_icache 0 -+#define cpu_has_dc_aliases 1 -+#define cpu_has_ic_fills_f_dc 0 -+#define cpu_has_pindexed_dcache 0 - - #endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ath79/patches-4.14/0015-MIPS-ath79-enable-uart-during-early_prink.patch b/target/linux/ath79/patches-4.14/0015-MIPS-ath79-enable-uart-during-early_prink.patch deleted file mode 100644 index eaa960a6e6..0000000000 --- a/target/linux/ath79/patches-4.14/0015-MIPS-ath79-enable-uart-during-early_prink.patch +++ /dev/null @@ -1,75 +0,0 @@ -From f55a400f4a691f3750eaf7bfcd6ecbf7ed1622f0 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Mon, 5 Mar 2018 11:38:21 +0100 -Subject: [PATCH 15/33] MIPS: ath79: enable uart during early_prink - -This patch ensures, that the poinmux register is properly setup for the -boot console uart when early_printk is enabled. - -Signed-off-by: Gabor Juhos -Signed-off-by: John Crispin ---- - arch/mips/ath79/early_printk.c | 44 +++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 43 insertions(+), 1 deletion(-) - ---- a/arch/mips/ath79/early_printk.c -+++ b/arch/mips/ath79/early_printk.c -@@ -58,6 +58,46 @@ static void prom_putchar_dummy(unsigned - /* nothing to do */ - } - -+static void prom_enable_uart(u32 id) -+{ -+ void __iomem *gpio_base; -+ u32 uart_en; -+ u32 t; -+ -+ switch (id) { -+ case REV_ID_MAJOR_AR71XX: -+ uart_en = AR71XX_GPIO_FUNC_UART_EN; -+ break; -+ -+ case REV_ID_MAJOR_AR7240: -+ case REV_ID_MAJOR_AR7241: -+ case REV_ID_MAJOR_AR7242: -+ uart_en = AR724X_GPIO_FUNC_UART_EN; -+ break; -+ -+ case REV_ID_MAJOR_AR913X: -+ uart_en = AR913X_GPIO_FUNC_UART_EN; -+ break; -+ -+ case REV_ID_MAJOR_AR9330: -+ case REV_ID_MAJOR_AR9331: -+ uart_en = AR933X_GPIO_FUNC_UART_EN; -+ break; -+ -+ case REV_ID_MAJOR_AR9341: -+ case REV_ID_MAJOR_AR9342: -+ case REV_ID_MAJOR_AR9344: -+ /* TODO */ -+ default: -+ return; -+ } -+ -+ gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE)); -+ t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC); -+ t |= uart_en; -+ __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC); -+} -+ - static void prom_putchar_init(void) - { - void __iomem *base; -@@ -92,8 +132,10 @@ static void prom_putchar_init(void) - - default: - _prom_putchar = prom_putchar_dummy; -- break; -+ return; - } -+ -+ prom_enable_uart(id); - } - - void prom_putchar(unsigned char ch) diff --git a/target/linux/ath79/patches-4.14/0016-MIPS-ath79-get-PCIe-controller-out-of-reset.patch b/target/linux/ath79/patches-4.14/0016-MIPS-ath79-get-PCIe-controller-out-of-reset.patch deleted file mode 100644 index 05f15b1df7..0000000000 --- a/target/linux/ath79/patches-4.14/0016-MIPS-ath79-get-PCIe-controller-out-of-reset.patch +++ /dev/null @@ -1,101 +0,0 @@ -From d3fa9694bc71338161ae2b9c7ee08b57b8140f93 Mon Sep 17 00:00:00 2001 -From: Mathias Kresin -Date: Tue, 6 Mar 2018 08:37:43 +0100 -Subject: [PATCH 16/33] MIPS: ath79: get PCIe controller out of reset - -The ar724x pci driver expects the PCIe controller to be brought out of -reset by the bootloader. - -At least the AVM Fritz 300E bootloader doesn't take care of releasing -the different PCIe controller related resets which causes an endless -hang as soon as either the PCIE Reset register (0x180f0018) or the PCI -Application Control register (0x180f0000) is read from. - -Do the full "PCIE Root Complex Initialization Sequence" if the PCIe -host controller is still in reset during probing. - -The QCA u-boot sleeps 10ms after the PCIE Application Control bit is -set to ready. It has been shown that 10ms might not be enough time if -PCIe should be used right after setting the bit. During my tests it -took up to 20ms till the link was up. Giving the link up to 100ms -should work for all cases. - -Signed-off-by: Mathias Kresin -Signed-off-by: John Crispin ---- - arch/mips/pci/pci-ar724x.c | 42 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 42 insertions(+) - ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -12,14 +12,18 @@ - #include - #include - #include -+#include - #include - #include - #include - -+#define AR724X_PCI_REG_APP 0x00 - #define AR724X_PCI_REG_RESET 0x18 - #define AR724X_PCI_REG_INT_STATUS 0x4c - #define AR724X_PCI_REG_INT_MASK 0x50 - -+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) -+ - #define AR724X_PCI_RESET_LINK_UP BIT(0) - - #define AR724X_PCI_INT_DEV0 BIT(14) -@@ -325,6 +329,37 @@ static void ar724x_pci_irq_init(struct a - apc); - } - -+static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc) -+{ -+ u32 ppl, app; -+ int wait = 0; -+ -+ /* deassert PCIe host controller and PCIe PHY reset */ -+ ath79_device_reset_clear(AR724X_RESET_PCIE); -+ ath79_device_reset_clear(AR724X_RESET_PCIE_PHY); -+ -+ /* remove the reset of the PCIE PLL */ -+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); -+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET; -+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); -+ -+ /* deassert bypass for the PCIE PLL */ -+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); -+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS; -+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); -+ -+ /* set PCIE Application Control to ready */ -+ app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP); -+ app |= AR724X_PCI_APP_LTSSM_ENABLE; -+ __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP); -+ -+ /* wait up to 100ms for PHY link up */ -+ do { -+ mdelay(10); -+ wait++; -+ } while (wait < 10 && !ar724x_pci_check_link(apc)); -+} -+ - static int ar724x_pci_probe(struct platform_device *pdev) - { - struct ar724x_pci_controller *apc; -@@ -383,6 +418,13 @@ static int ar724x_pci_probe(struct platf - apc->pci_controller.io_resource = &apc->io_res; - apc->pci_controller.mem_resource = &apc->mem_res; - -+ /* -+ * Do the full PCIE Root Complex Initialization Sequence if the PCIe -+ * host controller is in reset. -+ */ -+ if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE) -+ ar724x_pci_hw_init(apc); -+ - apc->link_up = ar724x_pci_check_link(apc); - if (!apc->link_up) - dev_warn(&pdev->dev, "PCIe link is down\n"); diff --git a/target/linux/ath79/patches-4.14/0021-MIPS-ath79-add-helpers-for-setting-clocks-and-expose.patch b/target/linux/ath79/patches-4.14/0021-MIPS-ath79-add-helpers-for-setting-clocks-and-expose.patch deleted file mode 100644 index c273140dfc..0000000000 --- a/target/linux/ath79/patches-4.14/0021-MIPS-ath79-add-helpers-for-setting-clocks-and-expose.patch +++ /dev/null @@ -1,243 +0,0 @@ -From 288a8eb0d41f09fda242e05f8a7bd1f5b3489477 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Tue, 6 Mar 2018 13:19:26 +0100 -Subject: [PATCH 21/33] MIPS: ath79: add helpers for setting clocks and expose - the ref clock - -Preparation for transitioning the legacy clock setup code over -to OF. - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 128 ++++++++++++++++++---------------- - include/dt-bindings/clock/ath79-clk.h | 3 +- - 2 files changed, 68 insertions(+), 63 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -37,20 +37,46 @@ static struct clk_onecell_data clk_data - .clk_num = ARRAY_SIZE(clks), - }; - --static struct clk *__init ath79_add_sys_clkdev( -- const char *id, unsigned long rate) -+static const char * const clk_names[ATH79_CLK_END] = { -+ [ATH79_CLK_CPU] = "cpu", -+ [ATH79_CLK_DDR] = "ddr", -+ [ATH79_CLK_AHB] = "ahb", -+ [ATH79_CLK_REF] = "ref", -+}; -+ -+static const char * __init ath79_clk_name(int type) - { -- struct clk *clk; -- int err; -+ BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]); -+ return clk_names[type]; -+} - -- clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate); -+static void __init __ath79_set_clk(int type, const char *name, struct clk *clk) -+{ - if (IS_ERR(clk)) -- panic("failed to allocate %s clock structure", id); -+ panic("failed to allocate %s clock structure", clk_names[type]); - -- err = clk_register_clkdev(clk, id, NULL); -- if (err) -- panic("unable to register %s clock device", id); -+ clks[type] = clk; -+ clk_register_clkdev(clk, name, NULL); -+} - -+static struct clk * __init ath79_set_clk(int type, unsigned long rate) -+{ -+ const char *name = ath79_clk_name(type); -+ struct clk *clk; -+ -+ clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate); -+ __ath79_set_clk(type, name, clk); -+ return clk; -+} -+ -+static struct clk * __init ath79_set_ff_clk(int type, const char *parent, -+ unsigned int mult, unsigned int div) -+{ -+ const char *name = ath79_clk_name(type); -+ struct clk *clk; -+ -+ clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div); -+ __ath79_set_clk(type, name, clk); - return clk; - } - -@@ -80,27 +106,15 @@ static void __init ar71xx_clocks_init(vo - div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; - ahb_rate = cpu_rate / div; - -- ath79_add_sys_clkdev("ref", ref_rate); -- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); -- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); -- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); -+ ath79_set_clk(ATH79_CLK_REF, ref_rate); -+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate); -+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate); -+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - - clk_add_alias("wdt", NULL, "ahb", NULL); - clk_add_alias("uart", NULL, "ahb", NULL); - } - --static struct clk * __init ath79_reg_ffclk(const char *name, -- const char *parent_name, unsigned int mult, unsigned int div) --{ -- struct clk *clk; -- -- clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); -- if (IS_ERR(clk)) -- panic("failed to allocate %s clock structure", name); -- -- return clk; --} -- - static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base) - { - u32 pll; -@@ -114,24 +128,19 @@ static void __init ar724x_clk_init(struc - ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; - ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; - -- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div); -- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div); -- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div); -+ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div); -+ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div); -+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div); - } - - static void __init ar724x_clocks_init(void) - { - struct clk *ref_clk; - -- ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ); -+ ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ); - - ar724x_clk_init(ref_clk, ath79_pll_base); - -- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */ -- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL); -- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL); -- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL); -- - clk_add_alias("wdt", NULL, "ahb", NULL); - clk_add_alias("uart", NULL, "ahb", NULL); - } -@@ -186,12 +195,12 @@ static void __init ar9330_clk_init(struc - AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; - } - -- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", -- ninit_mul, ref_div * out_div * cpu_div); -- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", -- ninit_mul, ref_div * out_div * ddr_div); -- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", -- ninit_mul, ref_div * out_div * ahb_div); -+ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul, -+ ref_div * out_div * cpu_div); -+ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul, -+ ref_div * out_div * ddr_div); -+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul, -+ ref_div * out_div * ahb_div); - } - - static void __init ar933x_clocks_init(void) -@@ -206,15 +215,10 @@ static void __init ar933x_clocks_init(vo - else - ref_rate = (25 * 1000 * 1000); - -- ref_clk = ath79_add_sys_clkdev("ref", ref_rate); -+ ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate); - - ar9330_clk_init(ref_clk, ath79_pll_base); - -- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */ -- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL); -- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL); -- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL); -- - clk_add_alias("wdt", NULL, "ahb", NULL); - clk_add_alias("uart", NULL, "ref", NULL); - } -@@ -344,10 +348,10 @@ static void __init ar934x_clocks_init(vo - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_add_sys_clkdev("ref", ref_rate); -- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); -- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); -- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); -+ ath79_set_clk(ATH79_CLK_REF, ref_rate); -+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate); -+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate); -+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - - clk_add_alias("wdt", NULL, "ref", NULL); - clk_add_alias("uart", NULL, "ref", NULL); -@@ -431,10 +435,10 @@ static void __init qca953x_clocks_init(v - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_add_sys_clkdev("ref", ref_rate); -- ath79_add_sys_clkdev("cpu", cpu_rate); -- ath79_add_sys_clkdev("ddr", ddr_rate); -- ath79_add_sys_clkdev("ahb", ahb_rate); -+ ath79_set_clk(ATH79_CLK_REF, ref_rate); -+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate); -+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate); -+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - - clk_add_alias("wdt", NULL, "ref", NULL); - clk_add_alias("uart", NULL, "ref", NULL); -@@ -516,10 +520,10 @@ static void __init qca955x_clocks_init(v - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_add_sys_clkdev("ref", ref_rate); -- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); -- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); -- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); -+ ath79_set_clk(ATH79_CLK_REF, ref_rate); -+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate); -+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate); -+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - - clk_add_alias("wdt", NULL, "ref", NULL); - clk_add_alias("uart", NULL, "ref", NULL); -@@ -620,10 +624,10 @@ static void __init qca956x_clocks_init(v - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_add_sys_clkdev("ref", ref_rate); -- ath79_add_sys_clkdev("cpu", cpu_rate); -- ath79_add_sys_clkdev("ddr", ddr_rate); -- ath79_add_sys_clkdev("ahb", ahb_rate); -+ ath79_set_clk(ATH79_CLK_REF, ref_rate); -+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate); -+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate); -+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - - clk_add_alias("wdt", NULL, "ref", NULL); - clk_add_alias("uart", NULL, "ref", NULL); ---- a/include/dt-bindings/clock/ath79-clk.h -+++ b/include/dt-bindings/clock/ath79-clk.h -@@ -13,7 +13,8 @@ - #define ATH79_CLK_CPU 0 - #define ATH79_CLK_DDR 1 - #define ATH79_CLK_AHB 2 -+#define ATH79_CLK_REF 3 - --#define ATH79_CLK_END 3 -+#define ATH79_CLK_END 4 - - #endif /* __DT_BINDINGS_ATH79_CLK_H */ diff --git a/target/linux/ath79/patches-4.14/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch b/target/linux/ath79/patches-4.14/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch deleted file mode 100644 index 389edc45a8..0000000000 --- a/target/linux/ath79/patches-4.14/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch +++ /dev/null @@ -1,114 +0,0 @@ -From 339c191a95e978353c9ba3aafab0261e14de109b Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Tue, 6 Mar 2018 13:22:43 +0100 -Subject: [PATCH 22/33] MIPS: ath79: move legacy "wdt" and "uart" clock aliases - out of soc init - -Preparation for reusing functions for DT - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 38 +++++++++++++++++--------------------- - 1 file changed, 17 insertions(+), 21 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -110,9 +110,6 @@ static void __init ar71xx_clocks_init(vo - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -- -- clk_add_alias("wdt", NULL, "ahb", NULL); -- clk_add_alias("uart", NULL, "ahb", NULL); - } - - static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base) -@@ -140,9 +137,6 @@ static void __init ar724x_clocks_init(vo - ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ); - - ar724x_clk_init(ref_clk, ath79_pll_base); -- -- clk_add_alias("wdt", NULL, "ahb", NULL); -- clk_add_alias("uart", NULL, "ahb", NULL); - } - - static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base) -@@ -218,9 +212,6 @@ static void __init ar933x_clocks_init(vo - ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate); - - ar9330_clk_init(ref_clk, ath79_pll_base); -- -- clk_add_alias("wdt", NULL, "ahb", NULL); -- clk_add_alias("uart", NULL, "ref", NULL); - } - - static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, -@@ -353,9 +344,6 @@ static void __init ar934x_clocks_init(vo - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - -- clk_add_alias("wdt", NULL, "ref", NULL); -- clk_add_alias("uart", NULL, "ref", NULL); -- - iounmap(dpll_base); - } - -@@ -439,9 +427,6 @@ static void __init qca953x_clocks_init(v - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -- -- clk_add_alias("wdt", NULL, "ref", NULL); -- clk_add_alias("uart", NULL, "ref", NULL); - } - - static void __init qca955x_clocks_init(void) -@@ -524,9 +509,6 @@ static void __init qca955x_clocks_init(v - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -- -- clk_add_alias("wdt", NULL, "ref", NULL); -- clk_add_alias("uart", NULL, "ref", NULL); - } - - static void __init qca956x_clocks_init(void) -@@ -628,13 +610,13 @@ static void __init qca956x_clocks_init(v - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -- -- clk_add_alias("wdt", NULL, "ref", NULL); -- clk_add_alias("uart", NULL, "ref", NULL); - } - - void __init ath79_clocks_init(void) - { -+ const char *wdt; -+ const char *uart; -+ - if (soc_is_ar71xx()) - ar71xx_clocks_init(); - else if (soc_is_ar724x() || soc_is_ar913x()) -@@ -651,6 +633,20 @@ void __init ath79_clocks_init(void) - qca956x_clocks_init(); - else - BUG(); -+ -+ if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) { -+ wdt = "ahb"; -+ uart = "ahb"; -+ } else if (soc_is_ar933x()) { -+ wdt = "ahb"; -+ uart = "ref"; -+ } else { -+ wdt = "ref"; -+ uart = "ref"; -+ } -+ -+ clk_add_alias("wdt", NULL, wdt, NULL); -+ clk_add_alias("uart", NULL, uart, NULL); - } - - unsigned long __init diff --git a/target/linux/ath79/patches-4.14/0023-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch b/target/linux/ath79/patches-4.14/0023-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch deleted file mode 100644 index 6c0f2ad54c..0000000000 --- a/target/linux/ath79/patches-4.14/0023-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch +++ /dev/null @@ -1,242 +0,0 @@ -From 6350b2c36c522fecbc91a80b63f49319dafd2a72 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Tue, 6 Mar 2018 13:23:20 +0100 -Subject: [PATCH 23/33] MIPS: ath79: pass PLL base to clock init functions - -Preparation for passing the mapped base via DT - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 60 ++++++++++++++++++++++++------------------------- - 1 file changed, 30 insertions(+), 30 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -80,7 +80,7 @@ static struct clk * __init ath79_set_ff_ - return clk; - } - --static void __init ar71xx_clocks_init(void) -+static void __init ar71xx_clocks_init(void __iomem *pll_base) - { - unsigned long ref_rate; - unsigned long cpu_rate; -@@ -92,7 +92,7 @@ static void __init ar71xx_clocks_init(vo - - ref_rate = AR71XX_BASE_FREQ; - -- pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); -+ pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); - - div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; - freq = div * ref_rate; -@@ -130,13 +130,13 @@ static void __init ar724x_clk_init(struc - ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div); - } - --static void __init ar724x_clocks_init(void) -+static void __init ar724x_clocks_init(void __iomem *pll_base) - { - struct clk *ref_clk; - - ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ); - -- ar724x_clk_init(ref_clk, ath79_pll_base); -+ ar724x_clk_init(ref_clk, pll_base); - } - - static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base) -@@ -197,7 +197,7 @@ static void __init ar9330_clk_init(struc - ref_div * out_div * ahb_div); - } - --static void __init ar933x_clocks_init(void) -+static void __init ar933x_clocks_init(void __iomem *pll_base) - { - struct clk *ref_clk; - unsigned long ref_rate; -@@ -234,7 +234,7 @@ static u32 __init ar934x_get_pll_freq(u3 - return ret; - } - --static void __init ar934x_clocks_init(void) -+static void __init ar934x_clocks_init(void __iomem *pll_base) - { - unsigned long ref_rate; - unsigned long cpu_rate; -@@ -265,7 +265,7 @@ static void __init ar934x_clocks_init(vo - AR934X_SRIF_DPLL1_REFDIV_MASK; - frac = 1 << 18; - } else { -- pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); -+ pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); - out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; - ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -@@ -292,7 +292,7 @@ static void __init ar934x_clocks_init(vo - AR934X_SRIF_DPLL1_REFDIV_MASK; - frac = 1 << 18; - } else { -- pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); -+ pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); - out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & - AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; - ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -@@ -307,7 +307,7 @@ static void __init ar934x_clocks_init(vo - ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, - nfrac, frac, out_div); - -- clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); -+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); - - postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & - AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; -@@ -347,7 +347,7 @@ static void __init ar934x_clocks_init(vo - iounmap(dpll_base); - } - --static void __init qca953x_clocks_init(void) -+static void __init qca953x_clocks_init(void __iomem *pll_base) - { - unsigned long ref_rate; - unsigned long cpu_rate; -@@ -363,7 +363,7 @@ static void __init qca953x_clocks_init(v - else - ref_rate = 25 * 1000 * 1000; - -- pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG); -+ pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG); - out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; - ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -@@ -377,7 +377,7 @@ static void __init qca953x_clocks_init(v - cpu_pll += frac * (ref_rate >> 6) / ref_div; - cpu_pll /= (1 << out_div); - -- pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG); -+ pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG); - out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & - QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK; - ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -@@ -391,7 +391,7 @@ static void __init qca953x_clocks_init(v - ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4); - ddr_pll /= (1 << out_div); - -- clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG); -+ clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG); - - postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & - QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -@@ -429,7 +429,7 @@ static void __init qca953x_clocks_init(v - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - } - --static void __init qca955x_clocks_init(void) -+static void __init qca955x_clocks_init(void __iomem *pll_base) - { - unsigned long ref_rate; - unsigned long cpu_rate; -@@ -445,7 +445,7 @@ static void __init qca955x_clocks_init(v - else - ref_rate = 25 * 1000 * 1000; - -- pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); -+ pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG); - out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; - ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -@@ -459,7 +459,7 @@ static void __init qca955x_clocks_init(v - cpu_pll += frac * ref_rate / (ref_div * (1 << 6)); - cpu_pll /= (1 << out_div); - -- pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); -+ pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG); - out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & - QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK; - ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -@@ -473,7 +473,7 @@ static void __init qca955x_clocks_init(v - ddr_pll += frac * ref_rate / (ref_div * (1 << 10)); - ddr_pll /= (1 << out_div); - -- clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); -+ clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG); - - postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & - QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -@@ -511,7 +511,7 @@ static void __init qca955x_clocks_init(v - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - } - --static void __init qca956x_clocks_init(void) -+static void __init qca956x_clocks_init(void __iomem *pll_base) - { - unsigned long ref_rate; - unsigned long cpu_rate; -@@ -537,13 +537,13 @@ static void __init qca956x_clocks_init(v - else - ref_rate = 25 * 1000 * 1000; - -- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG); -+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG); - out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK; - ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) & - QCA956X_PLL_CPU_CONFIG_REFDIV_MASK; - -- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG); -+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG); - nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) & - QCA956X_PLL_CPU_CONFIG1_NINT_MASK; - hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) & -@@ -556,12 +556,12 @@ static void __init qca956x_clocks_init(v - cpu_pll += (hfrac >> 13) * ref_rate / ref_div; - cpu_pll /= (1 << out_div); - -- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG); -+ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG); - out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & - QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK; - ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) & - QCA956X_PLL_DDR_CONFIG_REFDIV_MASK; -- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG); -+ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG); - nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) & - QCA956X_PLL_DDR_CONFIG1_NINT_MASK; - hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) & -@@ -574,7 +574,7 @@ static void __init qca956x_clocks_init(v - ddr_pll += (hfrac >> 13) * ref_rate / ref_div; - ddr_pll /= (1 << out_div); - -- clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG); -+ clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG); - - postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & - QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -@@ -618,19 +618,19 @@ void __init ath79_clocks_init(void) - const char *uart; - - if (soc_is_ar71xx()) -- ar71xx_clocks_init(); -+ ar71xx_clocks_init(ath79_pll_base); - else if (soc_is_ar724x() || soc_is_ar913x()) -- ar724x_clocks_init(); -+ ar724x_clocks_init(ath79_pll_base); - else if (soc_is_ar933x()) -- ar933x_clocks_init(); -+ ar933x_clocks_init(ath79_pll_base); - else if (soc_is_ar934x()) -- ar934x_clocks_init(); -+ ar934x_clocks_init(ath79_pll_base); - else if (soc_is_qca953x()) -- qca953x_clocks_init(); -+ qca953x_clocks_init(ath79_pll_base); - else if (soc_is_qca955x()) -- qca955x_clocks_init(); -+ qca955x_clocks_init(ath79_pll_base); - else if (soc_is_qca956x() || soc_is_tp9343()) -- qca956x_clocks_init(); -+ qca956x_clocks_init(ath79_pll_base); - else - BUG(); - diff --git a/target/linux/ath79/patches-4.14/0024-MIPS-ath79-make-specifying-the-reference-clock-in-DT.patch b/target/linux/ath79/patches-4.14/0024-MIPS-ath79-make-specifying-the-reference-clock-in-DT.patch deleted file mode 100644 index 9ceb643803..0000000000 --- a/target/linux/ath79/patches-4.14/0024-MIPS-ath79-make-specifying-the-reference-clock-in-DT.patch +++ /dev/null @@ -1,229 +0,0 @@ -From 5fadb2544ed0bb72ddddd846aa303bb9ed2d211c Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Tue, 6 Mar 2018 13:24:07 +0100 -Subject: [PATCH 24/33] MIPS: ath79: make specifying the reference clock in DT - optional - -It can be autodetected for many SoCs using the strapping options. -If the clock is specified in DT, the autodetected value is ignored - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 84 +++++++++++++++++++++++-------------------------- - 1 file changed, 40 insertions(+), 44 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -80,6 +80,18 @@ static struct clk * __init ath79_set_ff_ - return clk; - } - -+static unsigned long __init ath79_setup_ref_clk(unsigned long rate) -+{ -+ struct clk *clk = clks[ATH79_CLK_REF]; -+ -+ if (clk) -+ rate = clk_get_rate(clk); -+ else -+ clk = ath79_set_clk(ATH79_CLK_REF, rate); -+ -+ return rate; -+} -+ - static void __init ar71xx_clocks_init(void __iomem *pll_base) - { - unsigned long ref_rate; -@@ -90,7 +102,7 @@ static void __init ar71xx_clocks_init(vo - u32 freq; - u32 div; - -- ref_rate = AR71XX_BASE_FREQ; -+ ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ); - - pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); - -@@ -106,16 +118,17 @@ static void __init ar71xx_clocks_init(vo - div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; - ahb_rate = cpu_rate / div; - -- ath79_set_clk(ATH79_CLK_REF, ref_rate); - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - } - --static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base) -+static void __init ar724x_clocks_init(void __iomem *pll_base) - { -- u32 pll; - u32 mult, div, ddr_div, ahb_div; -+ u32 pll; -+ -+ ath79_setup_ref_clk(AR71XX_BASE_FREQ); - - pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); - -@@ -130,17 +143,9 @@ static void __init ar724x_clk_init(struc - ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div); - } - --static void __init ar724x_clocks_init(void __iomem *pll_base) --{ -- struct clk *ref_clk; -- -- ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ); -- -- ar724x_clk_init(ref_clk, pll_base); --} -- --static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base) -+static void __init ar933x_clocks_init(void __iomem *pll_base) - { -+ unsigned long ref_rate; - u32 clock_ctrl; - u32 ref_div; - u32 ninit_mul; -@@ -149,6 +154,15 @@ static void __init ar9330_clk_init(struc - u32 cpu_div; - u32 ddr_div; - u32 ahb_div; -+ u32 t; -+ -+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); -+ if (t & AR933X_BOOTSTRAP_REF_CLK_40) -+ ref_rate = (40 * 1000 * 1000); -+ else -+ ref_rate = (25 * 1000 * 1000); -+ -+ ath79_setup_ref_clk(ref_rate); - - clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); - if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { -@@ -197,23 +211,6 @@ static void __init ar9330_clk_init(struc - ref_div * out_div * ahb_div); - } - --static void __init ar933x_clocks_init(void __iomem *pll_base) --{ -- struct clk *ref_clk; -- unsigned long ref_rate; -- u32 t; -- -- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); -- if (t & AR933X_BOOTSTRAP_REF_CLK_40) -- ref_rate = (40 * 1000 * 1000); -- else -- ref_rate = (25 * 1000 * 1000); -- -- ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate); -- -- ar9330_clk_init(ref_clk, ath79_pll_base); --} -- - static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, - u32 frac, u32 out_div) - { -@@ -253,6 +250,8 @@ static void __init ar934x_clocks_init(vo - else - ref_rate = 25 * 1000 * 1000; - -+ ref_rate = ath79_setup_ref_clk(ref_rate); -+ - pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); - if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { - out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & -@@ -339,7 +338,6 @@ static void __init ar934x_clocks_init(vo - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_set_clk(ATH79_CLK_REF, ref_rate); - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -@@ -363,6 +361,8 @@ static void __init qca953x_clocks_init(v - else - ref_rate = 25 * 1000 * 1000; - -+ ref_rate = ath79_setup_ref_clk(ref_rate); -+ - pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG); - out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; -@@ -423,7 +423,6 @@ static void __init qca953x_clocks_init(v - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_set_clk(ATH79_CLK_REF, ref_rate); - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -@@ -445,6 +444,8 @@ static void __init qca955x_clocks_init(v - else - ref_rate = 25 * 1000 * 1000; - -+ ref_rate = ath79_setup_ref_clk(ref_rate); -+ - pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG); - out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; -@@ -505,7 +506,6 @@ static void __init qca955x_clocks_init(v - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_set_clk(ATH79_CLK_REF, ref_rate); - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -@@ -537,6 +537,8 @@ static void __init qca956x_clocks_init(v - else - ref_rate = 25 * 1000 * 1000; - -+ ref_rate = ath79_setup_ref_clk(ref_rate); -+ - pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG); - out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK; -@@ -606,7 +608,6 @@ static void __init qca956x_clocks_init(v - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_set_clk(ATH79_CLK_REF, ref_rate); - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -@@ -682,10 +683,8 @@ static void __init ath79_clocks_init_dt_ - void __iomem *pll_base; - - ref_clk = of_clk_get(np, 0); -- if (IS_ERR(ref_clk)) { -- pr_err("%pOF: of_clk_get failed\n", np); -- goto err; -- } -+ if (!IS_ERR(ref_clk)) -+ clks[ATH79_CLK_REF] = ref_clk; - - pll_base = of_iomap(np, 0); - if (!pll_base) { -@@ -694,9 +693,9 @@ static void __init ath79_clocks_init_dt_ - } - - if (of_device_is_compatible(np, "qca,ar9130-pll")) -- ar724x_clk_init(ref_clk, pll_base); -+ ar724x_clocks_init(pll_base); - else if (of_device_is_compatible(np, "qca,ar9330-pll")) -- ar9330_clk_init(ref_clk, pll_base); -+ ar933x_clocks_init(pll_base); - else { - pr_err("%pOF: could not find any appropriate clk_init()\n", np); - goto err_iounmap; -@@ -714,9 +713,6 @@ err_iounmap: - - err_clk: - clk_put(ref_clk); -- --err: -- return; - } - CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng); - CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng); diff --git a/target/linux/ath79/patches-4.14/0025-MIPS-ath79-support-setting-up-clock-via-DT-on-all-So.patch b/target/linux/ath79/patches-4.14/0025-MIPS-ath79-support-setting-up-clock-via-DT-on-all-So.patch deleted file mode 100644 index 13f46a9146..0000000000 --- a/target/linux/ath79/patches-4.14/0025-MIPS-ath79-support-setting-up-clock-via-DT-on-all-So.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 6325626de001df98aebe51f3008b1aca05798d19 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Tue, 6 Mar 2018 13:26:27 +0100 -Subject: [PATCH 25/33] MIPS: ath79: support setting up clock via DT on all SoC - types - -Use the same functions as the legacy code - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 39 ++++++++++++++++++++++----------------- - 1 file changed, 22 insertions(+), 17 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -669,16 +669,6 @@ ath79_get_sys_clk_rate(const char *id) - #ifdef CONFIG_OF - static void __init ath79_clocks_init_dt(struct device_node *np) - { -- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); --} -- --CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt); --CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt); --CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt); --CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt); -- --static void __init ath79_clocks_init_dt_ng(struct device_node *np) --{ - struct clk *ref_clk; - void __iomem *pll_base; - -@@ -692,14 +682,21 @@ static void __init ath79_clocks_init_dt_ - goto err_clk; - } - -- if (of_device_is_compatible(np, "qca,ar9130-pll")) -+ if (of_device_is_compatible(np, "qca,ar7100-pll")) -+ ar71xx_clocks_init(pll_base); -+ else if (of_device_is_compatible(np, "qca,ar7240-pll") || -+ of_device_is_compatible(np, "qca,ar9130-pll")) - ar724x_clocks_init(pll_base); - else if (of_device_is_compatible(np, "qca,ar9330-pll")) - ar933x_clocks_init(pll_base); -- else { -- pr_err("%pOF: could not find any appropriate clk_init()\n", np); -- goto err_iounmap; -- } -+ else if (of_device_is_compatible(np, "qca,ar9340-pll")) -+ ar934x_clocks_init(pll_base); -+ else if (of_device_is_compatible(np, "qca,qca9530-pll")) -+ qca953x_clocks_init(pll_base); -+ else if (of_device_is_compatible(np, "qca,qca9550-pll")) -+ qca955x_clocks_init(pll_base); -+ else if (of_device_is_compatible(np, "qca,qca9560-pll")) -+ qca956x_clocks_init(pll_base); - - if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { - pr_err("%pOF: could not register clk provider\n", np); -@@ -714,6 +711,14 @@ err_iounmap: - err_clk: - clk_put(ref_clk); - } --CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng); --CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng); -+ -+CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt); -+ - #endif diff --git a/target/linux/ath79/patches-4.14/0026-MIPS-ath79-export-switch-MDIO-reference-clock.patch b/target/linux/ath79/patches-4.14/0026-MIPS-ath79-export-switch-MDIO-reference-clock.patch deleted file mode 100644 index 27adb56f56..0000000000 --- a/target/linux/ath79/patches-4.14/0026-MIPS-ath79-export-switch-MDIO-reference-clock.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 78538d673801902108797f2c813e70cfbce280c9 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Tue, 6 Mar 2018 13:27:28 +0100 -Subject: [PATCH 26/33] MIPS: ath79: export switch MDIO reference clock - -On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz -clock. If that feature is not used, it defaults to the main reference -clock, like on all other SoC. - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 8 ++++++++ - include/dt-bindings/clock/ath79-clk.h | 3 ++- - 2 files changed, 10 insertions(+), 1 deletion(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7 - [ATH79_CLK_DDR] = "ddr", - [ATH79_CLK_AHB] = "ahb", - [ATH79_CLK_REF] = "ref", -+ [ATH79_CLK_MDIO] = "mdio", - }; - - static const char * __init ath79_clk_name(int type) -@@ -342,6 +343,10 @@ static void __init ar934x_clocks_init(vo - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - -+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); -+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) -+ ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000); -+ - iounmap(dpll_base); - } - -@@ -698,6 +703,9 @@ static void __init ath79_clocks_init_dt( - else if (of_device_is_compatible(np, "qca,qca9560-pll")) - qca956x_clocks_init(pll_base); - -+ if (!clks[ATH79_CLK_MDIO]) -+ clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF]; -+ - if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { - pr_err("%pOF: could not register clk provider\n", np); - goto err_iounmap; ---- a/include/dt-bindings/clock/ath79-clk.h -+++ b/include/dt-bindings/clock/ath79-clk.h -@@ -14,7 +14,8 @@ - #define ATH79_CLK_DDR 1 - #define ATH79_CLK_AHB 2 - #define ATH79_CLK_REF 3 -+#define ATH79_CLK_MDIO 4 - --#define ATH79_CLK_END 4 -+#define ATH79_CLK_END 5 - - #endif /* __DT_BINDINGS_ATH79_CLK_H */ diff --git a/target/linux/ath79/patches-4.14/0027-MIPS-ath79-drop-legacy-IRQ-code.patch b/target/linux/ath79/patches-4.14/0027-MIPS-ath79-drop-legacy-IRQ-code.patch deleted file mode 100644 index 6586f08431..0000000000 --- a/target/linux/ath79/patches-4.14/0027-MIPS-ath79-drop-legacy-IRQ-code.patch +++ /dev/null @@ -1,233 +0,0 @@ -From 3765b1f79593a0a9098ed15e48074c95403a53ee Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:05:08 +0200 -Subject: [PATCH 27/33] MIPS: ath79: drop legacy IRQ code - -With the target now being fully OF based, we can drop the legacy IRQ code. -All IRQs are now handled via the new irqchip drivers. - -Signed-off-by: John Crispin ---- - arch/mips/ath79/Makefile | 2 +- - arch/mips/ath79/irq.c | 169 ------------------------------- - arch/mips/ath79/setup.c | 6 ++ - arch/mips/include/asm/mach-ath79/ath79.h | 4 - - 4 files changed, 7 insertions(+), 174 deletions(-) - delete mode 100644 arch/mips/ath79/irq.c - ---- a/arch/mips/ath79/Makefile -+++ b/arch/mips/ath79/Makefile -@@ -8,7 +8,7 @@ - # under the terms of the GNU General Public License version 2 as published - # by the Free Software Foundation. - --obj-y := prom.o setup.o irq.o common.o clock.o -+obj-y := prom.o setup.o common.o clock.o - - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o - obj-$(CONFIG_PCI) += pci.o ---- a/arch/mips/ath79/irq.c -+++ /dev/null -@@ -1,169 +0,0 @@ --/* -- * Atheros AR71xx/AR724x/AR913x specific interrupt handling -- * -- * Copyright (C) 2010-2011 Jaiganesh Narayanan -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include -- --#include --#include -- --#include --#include --#include "common.h" --#include "machtypes.h" -- -- --static void ar934x_ip2_irq_dispatch(struct irq_desc *desc) --{ -- u32 status; -- -- status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); -- -- if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) { -- ath79_ddr_wb_flush(3); -- generic_handle_irq(ATH79_IP2_IRQ(0)); -- } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) { -- ath79_ddr_wb_flush(4); -- generic_handle_irq(ATH79_IP2_IRQ(1)); -- } else { -- spurious_interrupt(); -- } --} -- --static void ar934x_ip2_irq_init(void) --{ -- int i; -- -- for (i = ATH79_IP2_IRQ_BASE; -- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, -- handle_level_irq); -- -- irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); --} -- --static void qca955x_ip2_irq_dispatch(struct irq_desc *desc) --{ -- u32 status; -- -- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); -- status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL; -- -- if (status == 0) { -- spurious_interrupt(); -- return; -- } -- -- if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { -- /* TODO: flush DDR? */ -- generic_handle_irq(ATH79_IP2_IRQ(0)); -- } -- -- if (status & QCA955X_EXT_INT_WMAC_ALL) { -- /* TODO: flush DDR? */ -- generic_handle_irq(ATH79_IP2_IRQ(1)); -- } --} -- --static void qca955x_ip3_irq_dispatch(struct irq_desc *desc) --{ -- u32 status; -- -- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); -- status &= QCA955X_EXT_INT_PCIE_RC2_ALL | -- QCA955X_EXT_INT_USB1 | -- QCA955X_EXT_INT_USB2; -- -- if (status == 0) { -- spurious_interrupt(); -- return; -- } -- -- if (status & QCA955X_EXT_INT_USB1) { -- /* TODO: flush DDR? */ -- generic_handle_irq(ATH79_IP3_IRQ(0)); -- } -- -- if (status & QCA955X_EXT_INT_USB2) { -- /* TODO: flush DDR? */ -- generic_handle_irq(ATH79_IP3_IRQ(1)); -- } -- -- if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) { -- /* TODO: flush DDR? */ -- generic_handle_irq(ATH79_IP3_IRQ(2)); -- } --} -- --static void qca955x_irq_init(void) --{ -- int i; -- -- for (i = ATH79_IP2_IRQ_BASE; -- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, -- handle_level_irq); -- -- irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); -- -- for (i = ATH79_IP3_IRQ_BASE; -- i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, -- handle_level_irq); -- -- irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); --} -- --void __init arch_init_irq(void) --{ -- unsigned irq_wb_chan2 = -1; -- unsigned irq_wb_chan3 = -1; -- bool misc_is_ar71xx; -- -- if (mips_machtype == ATH79_MACH_GENERIC_OF) { -- irqchip_init(); -- return; -- } -- -- if (soc_is_ar71xx() || soc_is_ar724x() || -- soc_is_ar913x() || soc_is_ar933x()) { -- irq_wb_chan2 = 3; -- irq_wb_chan3 = 2; -- } else if (soc_is_ar934x()) { -- irq_wb_chan3 = 2; -- } -- -- ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3); -- -- if (soc_is_ar71xx() || soc_is_ar913x()) -- misc_is_ar71xx = true; -- else if (soc_is_ar724x() || -- soc_is_ar933x() || -- soc_is_ar934x() || -- soc_is_qca955x()) -- misc_is_ar71xx = false; -- else -- BUG(); -- ath79_misc_irq_init( -- ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS, -- ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx); -- -- if (soc_is_ar934x()) -- ar934x_ip2_irq_init(); -- else if (soc_is_qca955x()) -- qca955x_irq_init(); --} ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -305,6 +306,11 @@ void __init plat_time_init(void) - mips_hpt_frequency = cpu_clk_rate / 2; - } - -+void __init arch_init_irq(void) -+{ -+ irqchip_init(); -+} -+ - static int __init ath79_setup(void) - { - if (mips_machtype == ATH79_MACH_GENERIC_OF) ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -178,8 +178,4 @@ static inline u32 ath79_reset_rr(unsigne - void ath79_device_reset_set(u32 mask); - void ath79_device_reset_clear(u32 mask); - --void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3); --void ath79_misc_irq_init(void __iomem *regs, int irq, -- int irq_base, bool is_ar71xx); -- - #endif /* __ASM_MACH_ATH79_H */ diff --git a/target/linux/ath79/patches-4.14/0028-MIPS-ath79-drop-machfiles.patch b/target/linux/ath79/patches-4.14/0028-MIPS-ath79-drop-machfiles.patch deleted file mode 100644 index bb5acde8bb..0000000000 --- a/target/linux/ath79/patches-4.14/0028-MIPS-ath79-drop-machfiles.patch +++ /dev/null @@ -1,1042 +0,0 @@ -From badf28957b6dc400dff27bd23ba2ae75d9514be5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:04:09 +0200 -Subject: [PATCH 28/33] MIPS: ath79: drop machfiles - -With the target now being fully OF based, we can drop the legacy mach -files. Boards can now boot fully of devicetree files. - -Signed-off-by: John Crispin ---- - arch/mips/Kconfig | 1 - - arch/mips/ath79/Kconfig | 73 ------------------- - arch/mips/ath79/Makefile | 10 --- - arch/mips/ath79/clock.c | 1 - - arch/mips/ath79/mach-ap121.c | 92 ------------------------ - arch/mips/ath79/mach-ap136.c | 156 ----------------------------------------- - arch/mips/ath79/mach-ap81.c | 100 -------------------------- - arch/mips/ath79/mach-db120.c | 136 ----------------------------------- - arch/mips/ath79/mach-pb44.c | 128 --------------------------------- - arch/mips/ath79/mach-ubnt-xm.c | 126 --------------------------------- - arch/mips/ath79/machtypes.h | 28 -------- - arch/mips/ath79/setup.c | 77 +++----------------- - 12 files changed, 9 insertions(+), 919 deletions(-) - delete mode 100644 arch/mips/ath79/mach-ap121.c - delete mode 100644 arch/mips/ath79/mach-ap136.c - delete mode 100644 arch/mips/ath79/mach-ap81.c - delete mode 100644 arch/mips/ath79/mach-db120.c - delete mode 100644 arch/mips/ath79/mach-pb44.c - delete mode 100644 arch/mips/ath79/mach-ubnt-xm.c - delete mode 100644 arch/mips/ath79/machtypes.h - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -197,7 +197,6 @@ config ATH79 - select COMMON_CLK - select CLKDEV_LOOKUP - select IRQ_MIPS_CPU -- select MIPS_MACHINE - select SYS_HAS_CPU_MIPS32_R2 - select SYS_HAS_EARLY_PRINTK - select SYS_SUPPORTS_32BIT_KERNEL ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -1,79 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0 - if ATH79 - --menu "Atheros AR71XX/AR724X/AR913X machine selection" -- --config ATH79_MACH_AP121 -- bool "Atheros AP121 reference board" -- select SOC_AR933X -- select ATH79_DEV_GPIO_BUTTONS -- select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -- select ATH79_DEV_USB -- select ATH79_DEV_WMAC -- help -- Say 'Y' here if you want your kernel to support the -- Atheros AP121 reference board. -- --config ATH79_MACH_AP136 -- bool "Atheros AP136 reference board" -- select SOC_QCA955X -- select ATH79_DEV_GPIO_BUTTONS -- select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -- select ATH79_DEV_USB -- select ATH79_DEV_WMAC -- help -- Say 'Y' here if you want your kernel to support the -- Atheros AP136 reference board. -- --config ATH79_MACH_AP81 -- bool "Atheros AP81 reference board" -- select SOC_AR913X -- select ATH79_DEV_GPIO_BUTTONS -- select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -- select ATH79_DEV_USB -- select ATH79_DEV_WMAC -- help -- Say 'Y' here if you want your kernel to support the -- Atheros AP81 reference board. -- --config ATH79_MACH_DB120 -- bool "Atheros DB120 reference board" -- select SOC_AR934X -- select ATH79_DEV_GPIO_BUTTONS -- select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -- select ATH79_DEV_USB -- select ATH79_DEV_WMAC -- help -- Say 'Y' here if you want your kernel to support the -- Atheros DB120 reference board. -- --config ATH79_MACH_PB44 -- bool "Atheros PB44 reference board" -- select SOC_AR71XX -- select ATH79_DEV_GPIO_BUTTONS -- select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -- select ATH79_DEV_USB -- help -- Say 'Y' here if you want your kernel to support the -- Atheros PB44 reference board. -- --config ATH79_MACH_UBNT_XM -- bool "Ubiquiti Networks XM (rev 1.0) board" -- select SOC_AR724X -- select ATH79_DEV_GPIO_BUTTONS -- select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -- help -- Say 'Y' here if you want your kernel to support the -- Ubiquiti Networks XM (rev 1.0) board. -- --endmenu -- - config SOC_AR71XX - select HW_HAS_PCI - def_bool n ---- a/arch/mips/ath79/Makefile -+++ b/arch/mips/ath79/Makefile -@@ -22,13 +22,3 @@ obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev - obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o - obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o - obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o -- --# --# Machines --# --obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o --obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o --obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o --obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o --obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o --obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -26,7 +26,6 @@ - #include - #include - #include "common.h" --#include "machtypes.h" - - #define AR71XX_BASE_FREQ 40000000 - #define AR724X_BASE_FREQ 40000000 ---- a/arch/mips/ath79/mach-ap121.c -+++ /dev/null -@@ -1,92 +0,0 @@ --/* -- * Atheros AP121 board support -- * -- * Copyright (C) 2011 Gabor Juhos -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include "machtypes.h" --#include "dev-gpio-buttons.h" --#include "dev-leds-gpio.h" --#include "dev-spi.h" --#include "dev-usb.h" --#include "dev-wmac.h" -- --#define AP121_GPIO_LED_WLAN 0 --#define AP121_GPIO_LED_USB 1 -- --#define AP121_GPIO_BTN_JUMPSTART 11 --#define AP121_GPIO_BTN_RESET 12 -- --#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */ --#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL) -- --#define AP121_CAL_DATA_ADDR 0x1fff1000 -- --static struct gpio_led ap121_leds_gpio[] __initdata = { -- { -- .name = "ap121:green:usb", -- .gpio = AP121_GPIO_LED_USB, -- .active_low = 0, -- }, -- { -- .name = "ap121:green:wlan", -- .gpio = AP121_GPIO_LED_WLAN, -- .active_low = 0, -- }, --}; -- --static struct gpio_keys_button ap121_gpio_keys[] __initdata = { -- { -- .desc = "jumpstart button", -- .type = EV_KEY, -- .code = KEY_WPS_BUTTON, -- .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, -- .gpio = AP121_GPIO_BTN_JUMPSTART, -- .active_low = 1, -- }, -- { -- .desc = "reset button", -- .type = EV_KEY, -- .code = KEY_RESTART, -- .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, -- .gpio = AP121_GPIO_BTN_RESET, -- .active_low = 1, -- } --}; -- --static struct spi_board_info ap121_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "mx25l1606e", -- } --}; -- --static struct ath79_spi_platform_data ap121_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, --}; -- --static void __init ap121_setup(void) --{ -- u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR); -- -- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio), -- ap121_leds_gpio); -- ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(ap121_gpio_keys), -- ap121_gpio_keys); -- -- ath79_register_spi(&ap121_spi_data, ap121_spi_info, -- ARRAY_SIZE(ap121_spi_info)); -- ath79_register_usb(); -- ath79_register_wmac(cal_data); --} -- --MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", -- ap121_setup); ---- a/arch/mips/ath79/mach-ap136.c -+++ /dev/null -@@ -1,156 +0,0 @@ --/* -- * Qualcomm Atheros AP136 reference board support -- * -- * Copyright (c) 2012 Qualcomm Atheros -- * Copyright (c) 2012-2013 Gabor Juhos -- * -- * Permission to use, copy, modify, and/or distribute this software for any -- * purpose with or without fee is hereby granted, provided that the above -- * copyright notice and this permission notice appear in all copies. -- * -- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -- * -- */ -- --#include --#include -- --#include "machtypes.h" --#include "dev-gpio-buttons.h" --#include "dev-leds-gpio.h" --#include "dev-spi.h" --#include "dev-usb.h" --#include "dev-wmac.h" --#include "pci.h" -- --#define AP136_GPIO_LED_STATUS_RED 14 --#define AP136_GPIO_LED_STATUS_GREEN 19 --#define AP136_GPIO_LED_USB 4 --#define AP136_GPIO_LED_WLAN_2G 13 --#define AP136_GPIO_LED_WLAN_5G 12 --#define AP136_GPIO_LED_WPS_RED 15 --#define AP136_GPIO_LED_WPS_GREEN 20 -- --#define AP136_GPIO_BTN_WPS 16 --#define AP136_GPIO_BTN_RFKILL 21 -- --#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ --#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) -- --#define AP136_WMAC_CALDATA_OFFSET 0x1000 --#define AP136_PCIE_CALDATA_OFFSET 0x5000 -- --static struct gpio_led ap136_leds_gpio[] __initdata = { -- { -- .name = "qca:green:status", -- .gpio = AP136_GPIO_LED_STATUS_GREEN, -- .active_low = 1, -- }, -- { -- .name = "qca:red:status", -- .gpio = AP136_GPIO_LED_STATUS_RED, -- .active_low = 1, -- }, -- { -- .name = "qca:green:wps", -- .gpio = AP136_GPIO_LED_WPS_GREEN, -- .active_low = 1, -- }, -- { -- .name = "qca:red:wps", -- .gpio = AP136_GPIO_LED_WPS_RED, -- .active_low = 1, -- }, -- { -- .name = "qca:red:wlan-2g", -- .gpio = AP136_GPIO_LED_WLAN_2G, -- .active_low = 1, -- }, -- { -- .name = "qca:red:usb", -- .gpio = AP136_GPIO_LED_USB, -- .active_low = 1, -- } --}; -- --static struct gpio_keys_button ap136_gpio_keys[] __initdata = { -- { -- .desc = "WPS button", -- .type = EV_KEY, -- .code = KEY_WPS_BUTTON, -- .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, -- .gpio = AP136_GPIO_BTN_WPS, -- .active_low = 1, -- }, -- { -- .desc = "RFKILL button", -- .type = EV_KEY, -- .code = KEY_RFKILL, -- .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, -- .gpio = AP136_GPIO_BTN_RFKILL, -- .active_low = 1, -- }, --}; -- --static struct spi_board_info ap136_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "mx25l6405d", -- } --}; -- --static struct ath79_spi_platform_data ap136_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, --}; -- --#ifdef CONFIG_PCI --static struct ath9k_platform_data ap136_ath9k_data; -- --static int ap136_pci_plat_dev_init(struct pci_dev *dev) --{ -- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) -- dev->dev.platform_data = &ap136_ath9k_data; -- -- return 0; --} -- --static void __init ap136_pci_init(u8 *eeprom) --{ -- memcpy(ap136_ath9k_data.eeprom_data, eeprom, -- sizeof(ap136_ath9k_data.eeprom_data)); -- -- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); -- ath79_register_pci(); --} --#else --static inline void ap136_pci_init(u8 *eeprom) {} --#endif /* CONFIG_PCI */ -- --static void __init ap136_setup(void) --{ -- u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -- -- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), -- ap136_leds_gpio); -- ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(ap136_gpio_keys), -- ap136_gpio_keys); -- ath79_register_spi(&ap136_spi_data, ap136_spi_info, -- ARRAY_SIZE(ap136_spi_info)); -- ath79_register_usb(); -- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); -- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); --} -- --MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", -- "Atheros AP136-010 reference board", -- ap136_setup); ---- a/arch/mips/ath79/mach-ap81.c -+++ /dev/null -@@ -1,100 +0,0 @@ --/* -- * Atheros AP81 board support -- * -- * Copyright (C) 2009-2010 Gabor Juhos -- * Copyright (C) 2009 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include "machtypes.h" --#include "dev-wmac.h" --#include "dev-gpio-buttons.h" --#include "dev-leds-gpio.h" --#include "dev-spi.h" --#include "dev-usb.h" -- --#define AP81_GPIO_LED_STATUS 1 --#define AP81_GPIO_LED_AOSS 3 --#define AP81_GPIO_LED_WLAN 6 --#define AP81_GPIO_LED_POWER 14 -- --#define AP81_GPIO_BTN_SW4 12 --#define AP81_GPIO_BTN_SW1 21 -- --#define AP81_KEYS_POLL_INTERVAL 20 /* msecs */ --#define AP81_KEYS_DEBOUNCE_INTERVAL (3 * AP81_KEYS_POLL_INTERVAL) -- --#define AP81_CAL_DATA_ADDR 0x1fff1000 -- --static struct gpio_led ap81_leds_gpio[] __initdata = { -- { -- .name = "ap81:green:status", -- .gpio = AP81_GPIO_LED_STATUS, -- .active_low = 1, -- }, { -- .name = "ap81:amber:aoss", -- .gpio = AP81_GPIO_LED_AOSS, -- .active_low = 1, -- }, { -- .name = "ap81:green:wlan", -- .gpio = AP81_GPIO_LED_WLAN, -- .active_low = 1, -- }, { -- .name = "ap81:green:power", -- .gpio = AP81_GPIO_LED_POWER, -- .active_low = 1, -- } --}; -- --static struct gpio_keys_button ap81_gpio_keys[] __initdata = { -- { -- .desc = "sw1", -- .type = EV_KEY, -- .code = BTN_0, -- .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, -- .gpio = AP81_GPIO_BTN_SW1, -- .active_low = 1, -- } , { -- .desc = "sw4", -- .type = EV_KEY, -- .code = BTN_1, -- .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, -- .gpio = AP81_GPIO_BTN_SW4, -- .active_low = 1, -- } --}; -- --static struct spi_board_info ap81_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "m25p64", -- } --}; -- --static struct ath79_spi_platform_data ap81_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, --}; -- --static void __init ap81_setup(void) --{ -- u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR); -- -- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), -- ap81_leds_gpio); -- ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(ap81_gpio_keys), -- ap81_gpio_keys); -- ath79_register_spi(&ap81_spi_data, ap81_spi_info, -- ARRAY_SIZE(ap81_spi_info)); -- ath79_register_wmac(cal_data); -- ath79_register_usb(); --} -- --MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", -- ap81_setup); ---- a/arch/mips/ath79/mach-db120.c -+++ /dev/null -@@ -1,136 +0,0 @@ --/* -- * Atheros DB120 reference board support -- * -- * Copyright (c) 2011 Qualcomm Atheros -- * Copyright (c) 2011 Gabor Juhos -- * -- * Permission to use, copy, modify, and/or distribute this software for any -- * purpose with or without fee is hereby granted, provided that the above -- * copyright notice and this permission notice appear in all copies. -- * -- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -- * -- */ -- --#include --#include -- --#include "machtypes.h" --#include "dev-gpio-buttons.h" --#include "dev-leds-gpio.h" --#include "dev-spi.h" --#include "dev-usb.h" --#include "dev-wmac.h" --#include "pci.h" -- --#define DB120_GPIO_LED_WLAN_5G 12 --#define DB120_GPIO_LED_WLAN_2G 13 --#define DB120_GPIO_LED_STATUS 14 --#define DB120_GPIO_LED_WPS 15 -- --#define DB120_GPIO_BTN_WPS 16 -- --#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ --#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) -- --#define DB120_WMAC_CALDATA_OFFSET 0x1000 --#define DB120_PCIE_CALDATA_OFFSET 0x5000 -- --static struct gpio_led db120_leds_gpio[] __initdata = { -- { -- .name = "db120:green:status", -- .gpio = DB120_GPIO_LED_STATUS, -- .active_low = 1, -- }, -- { -- .name = "db120:green:wps", -- .gpio = DB120_GPIO_LED_WPS, -- .active_low = 1, -- }, -- { -- .name = "db120:green:wlan-5g", -- .gpio = DB120_GPIO_LED_WLAN_5G, -- .active_low = 1, -- }, -- { -- .name = "db120:green:wlan-2g", -- .gpio = DB120_GPIO_LED_WLAN_2G, -- .active_low = 1, -- }, --}; -- --static struct gpio_keys_button db120_gpio_keys[] __initdata = { -- { -- .desc = "WPS button", -- .type = EV_KEY, -- .code = KEY_WPS_BUTTON, -- .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL, -- .gpio = DB120_GPIO_BTN_WPS, -- .active_low = 1, -- }, --}; -- --static struct spi_board_info db120_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "s25sl064a", -- } --}; -- --static struct ath79_spi_platform_data db120_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, --}; -- --#ifdef CONFIG_PCI --static struct ath9k_platform_data db120_ath9k_data; -- --static int db120_pci_plat_dev_init(struct pci_dev *dev) --{ -- switch (PCI_SLOT(dev->devfn)) { -- case 0: -- dev->dev.platform_data = &db120_ath9k_data; -- break; -- } -- -- return 0; --} -- --static void __init db120_pci_init(u8 *eeprom) --{ -- memcpy(db120_ath9k_data.eeprom_data, eeprom, -- sizeof(db120_ath9k_data.eeprom_data)); -- -- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); -- ath79_register_pci(); --} --#else --static inline void db120_pci_init(u8 *eeprom) {} --#endif /* CONFIG_PCI */ -- --static void __init db120_setup(void) --{ -- u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -- -- ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), -- db120_leds_gpio); -- ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(db120_gpio_keys), -- db120_gpio_keys); -- ath79_register_spi(&db120_spi_data, db120_spi_info, -- ARRAY_SIZE(db120_spi_info)); -- ath79_register_usb(); -- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); -- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); --} -- --MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", -- db120_setup); ---- a/arch/mips/ath79/mach-pb44.c -+++ /dev/null -@@ -1,122 +0,0 @@ --/* -- * Atheros PB44 reference board support -- * -- * Copyright (C) 2009-2010 Gabor Juhos -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include -- --#include "machtypes.h" --#include "dev-gpio-buttons.h" --#include "dev-leds-gpio.h" --#include "dev-spi.h" --#include "dev-usb.h" --#include "pci.h" -- --#define PB44_GPIO_I2C_SCL 0 --#define PB44_GPIO_I2C_SDA 1 -- --#define PB44_GPIO_EXP_BASE 16 --#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6) --#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8) --#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) --#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + 10) -- --#define PB44_KEYS_POLL_INTERVAL 20 /* msecs */ --#define PB44_KEYS_DEBOUNCE_INTERVAL (3 * PB44_KEYS_POLL_INTERVAL) -- --static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { -- .sda_pin = PB44_GPIO_I2C_SDA, -- .scl_pin = PB44_GPIO_I2C_SCL, --}; -- --static struct platform_device pb44_i2c_gpio_device = { -- .name = "i2c-gpio", -- .id = 0, -- .dev = { -- .platform_data = &pb44_i2c_gpio_data, -- } --}; -- --static struct pcf857x_platform_data pb44_pcf857x_data = { -- .gpio_base = PB44_GPIO_EXP_BASE, --}; -- --static struct i2c_board_info pb44_i2c_board_info[] __initdata = { -- { -- I2C_BOARD_INFO("pcf8575", 0x20), -- .platform_data = &pb44_pcf857x_data, -- }, --}; -- --static struct gpio_led pb44_leds_gpio[] __initdata = { -- { -- .name = "pb44:amber:jump1", -- .gpio = PB44_GPIO_LED_JUMP1, -- .active_low = 1, -- }, { -- .name = "pb44:green:jump2", -- .gpio = PB44_GPIO_LED_JUMP2, -- .active_low = 1, -- }, --}; -- --static struct gpio_keys_button pb44_gpio_keys[] __initdata = { -- { -- .desc = "soft_reset", -- .type = EV_KEY, -- .code = KEY_RESTART, -- .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, -- .gpio = PB44_GPIO_SW_RESET, -- .active_low = 1, -- } , { -- .desc = "jumpstart", -- .type = EV_KEY, -- .code = KEY_WPS_BUTTON, -- .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, -- .gpio = PB44_GPIO_SW_JUMP, -- .active_low = 1, -- } --}; -- --static struct spi_board_info pb44_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "m25p64", -- }, --}; -- --static struct ath79_spi_platform_data pb44_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, --}; -- --static void __init pb44_init(void) --{ -- i2c_register_board_info(0, pb44_i2c_board_info, -- ARRAY_SIZE(pb44_i2c_board_info)); -- platform_device_register(&pb44_i2c_gpio_device); -- -- ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), -- pb44_leds_gpio); -- ath79_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(pb44_gpio_keys), -- pb44_gpio_keys); -- ath79_register_spi(&pb44_spi_data, pb44_spi_info, -- ARRAY_SIZE(pb44_spi_info)); -- ath79_register_usb(); -- ath79_register_pci(); --} -- --MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", -- pb44_init); ---- a/arch/mips/ath79/mach-ubnt-xm.c -+++ /dev/null -@@ -1,126 +0,0 @@ --/* -- * Ubiquiti Networks XM (rev 1.0) board support -- * -- * Copyright (C) 2011 René Bolldorf -- * -- * Derived from: mach-pb44.c -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include -- --#include -- --#include "machtypes.h" --#include "dev-gpio-buttons.h" --#include "dev-leds-gpio.h" --#include "dev-spi.h" --#include "pci.h" -- --#define UBNT_XM_GPIO_LED_L1 0 --#define UBNT_XM_GPIO_LED_L2 1 --#define UBNT_XM_GPIO_LED_L3 11 --#define UBNT_XM_GPIO_LED_L4 7 -- --#define UBNT_XM_GPIO_BTN_RESET 12 -- --#define UBNT_XM_KEYS_POLL_INTERVAL 20 --#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL) -- --#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000) -- --static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { -- { -- .name = "ubnt-xm:red:link1", -- .gpio = UBNT_XM_GPIO_LED_L1, -- .active_low = 0, -- }, { -- .name = "ubnt-xm:orange:link2", -- .gpio = UBNT_XM_GPIO_LED_L2, -- .active_low = 0, -- }, { -- .name = "ubnt-xm:green:link3", -- .gpio = UBNT_XM_GPIO_LED_L3, -- .active_low = 0, -- }, { -- .name = "ubnt-xm:green:link4", -- .gpio = UBNT_XM_GPIO_LED_L4, -- .active_low = 0, -- }, --}; -- --static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = { -- { -- .desc = "reset", -- .type = EV_KEY, -- .code = KEY_RESTART, -- .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, -- .gpio = UBNT_XM_GPIO_BTN_RESET, -- .active_low = 1, -- } --}; -- --static struct spi_board_info ubnt_xm_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "mx25l6405d", -- } --}; -- --static struct ath79_spi_platform_data ubnt_xm_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, --}; -- --#ifdef CONFIG_PCI --static struct ath9k_platform_data ubnt_xm_eeprom_data; -- --static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) --{ -- switch (PCI_SLOT(dev->devfn)) { -- case 0: -- dev->dev.platform_data = &ubnt_xm_eeprom_data; -- break; -- } -- -- return 0; --} -- --static void __init ubnt_xm_pci_init(void) --{ -- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, -- sizeof(ubnt_xm_eeprom_data.eeprom_data)); -- -- ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); -- ath79_register_pci(); --} --#else --static inline void ubnt_xm_pci_init(void) {} --#endif /* CONFIG_PCI */ -- --static void __init ubnt_xm_init(void) --{ -- ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio), -- ubnt_xm_leds_gpio); -- -- ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(ubnt_xm_gpio_keys), -- ubnt_xm_gpio_keys); -- -- ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info, -- ARRAY_SIZE(ubnt_xm_spi_info)); -- -- ubnt_xm_pci_init(); --} -- --MIPS_MACHINE(ATH79_MACH_UBNT_XM, -- "UBNT-XM", -- "Ubiquiti Networks XM (rev 1.0) board", -- ubnt_xm_init); ---- a/arch/mips/ath79/machtypes.h -+++ /dev/null -@@ -1,28 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X machine type definitions -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_MACHTYPE_H --#define _ATH79_MACHTYPE_H -- --#include -- --enum ath79_mach_type { -- ATH79_MACH_GENERIC_OF = -1, /* Device tree board */ -- ATH79_MACH_GENERIC = 0, -- ATH79_MACH_AP121, /* Atheros AP121 reference board */ -- ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ -- ATH79_MACH_AP81, /* Atheros AP81 reference board */ -- ATH79_MACH_DB120, /* Atheros DB120 reference board */ -- ATH79_MACH_PB44, /* Atheros PB44 reference board */ -- ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ --}; -- --#endif /* _ATH79_MACHTYPE_H */ ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -33,7 +33,6 @@ - #include - #include "common.h" - #include "dev-common.h" --#include "machtypes.h" - - #define ATH79_SYS_TYPE_LEN 64 - -@@ -230,25 +229,21 @@ void __init plat_mem_setup(void) - else if (fw_passed_dtb) - __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb)); - -- if (mips_machtype != ATH79_MACH_GENERIC_OF) { -- ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, -- AR71XX_RESET_SIZE); -- ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, -- AR71XX_PLL_SIZE); -- ath79_detect_sys_type(); -- ath79_ddr_ctrl_init(); -+ ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, -+ AR71XX_RESET_SIZE); -+ ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, -+ AR71XX_PLL_SIZE); -+ ath79_detect_sys_type(); -+ ath79_ddr_ctrl_init(); - -- detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); -- -- /* OF machines should use the reset driver */ -- _machine_restart = ath79_restart; -- } -+ detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); - -+ _machine_restart = ath79_restart; - _machine_halt = ath79_halt; - pm_power_off = ath79_halt; - } - --static void __init ath79_of_plat_time_init(void) -+void __init plat_time_init(void) - { - struct device_node *np; - struct clk *clk; -@@ -278,66 +273,12 @@ static void __init ath79_of_plat_time_in - clk_put(clk); - } - --void __init plat_time_init(void) --{ -- unsigned long cpu_clk_rate; -- unsigned long ahb_clk_rate; -- unsigned long ddr_clk_rate; -- unsigned long ref_clk_rate; -- -- if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) { -- ath79_of_plat_time_init(); -- return; -- } -- -- ath79_clocks_init(); -- -- cpu_clk_rate = ath79_get_sys_clk_rate("cpu"); -- ahb_clk_rate = ath79_get_sys_clk_rate("ahb"); -- ddr_clk_rate = ath79_get_sys_clk_rate("ddr"); -- ref_clk_rate = ath79_get_sys_clk_rate("ref"); -- -- pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n", -- cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000, -- ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000, -- ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000, -- ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000); -- -- mips_hpt_frequency = cpu_clk_rate / 2; --} -- - void __init arch_init_irq(void) - { - irqchip_init(); - } - --static int __init ath79_setup(void) --{ -- if (mips_machtype == ATH79_MACH_GENERIC_OF) -- return 0; -- -- ath79_gpio_init(); -- ath79_register_uart(); -- ath79_register_wdt(); -- -- mips_machine_setup(); -- -- return 0; --} -- --arch_initcall(ath79_setup); -- - void __init device_tree_init(void) - { - unflatten_and_copy_device_tree(); - } -- --MIPS_MACHINE(ATH79_MACH_GENERIC, -- "Generic", -- "Generic AR71XX/AR724X/AR913X based board", -- NULL); -- --MIPS_MACHINE(ATH79_MACH_GENERIC_OF, -- "DTB", -- "Generic AR71XX/AR724X/AR913X based board (DT)", -- NULL); diff --git a/target/linux/ath79/patches-4.14/0029-MIPS-ath79-drop-legacy-pci-code.patch b/target/linux/ath79/patches-4.14/0029-MIPS-ath79-drop-legacy-pci-code.patch deleted file mode 100644 index 254f2f9253..0000000000 --- a/target/linux/ath79/patches-4.14/0029-MIPS-ath79-drop-legacy-pci-code.patch +++ /dev/null @@ -1,379 +0,0 @@ -From d0f1420702ed47a82572aaf39e7407055518d14e Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:05:19 +0200 -Subject: [PATCH 29/33] MIPS: ath79: drop legacy pci code - -With the target now being fully OF based, we can drop the legacy pci -platform code. The only bits that we need to keep is the fixup code -which we move to its own code file. - -Signed-off-by: John Crispin ---- - arch/mips/ath79/Makefile | 1 - - arch/mips/ath79/pci.c | 273 -------------------------------------------- - arch/mips/ath79/pci.h | 35 ------ - arch/mips/pci/Makefile | 1 + - arch/mips/pci/fixup-ath79.c | 21 ++++ - 5 files changed, 22 insertions(+), 309 deletions(-) - delete mode 100644 arch/mips/ath79/pci.c - delete mode 100644 arch/mips/ath79/pci.h - create mode 100644 arch/mips/pci/fixup-ath79.c - ---- a/arch/mips/ath79/Makefile -+++ b/arch/mips/ath79/Makefile -@@ -11,7 +11,6 @@ - obj-y := prom.o setup.o common.o clock.o - - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o --obj-$(CONFIG_PCI) += pci.o - - # - # Devices ---- a/arch/mips/ath79/pci.c -+++ /dev/null -@@ -1,273 +0,0 @@ --/* -- * Atheros AR71XX/AR724X specific PCI setup code -- * -- * Copyright (C) 2011 René Bolldorf -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * Parts of this file are based on Atheros' 2.6.15 BSP -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include "pci.h" -- --static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); --static const struct ath79_pci_irq *ath79_pci_irq_map; --static unsigned ath79_pci_nr_irqs; -- --static const struct ath79_pci_irq ar71xx_pci_irq_map[] = { -- { -- .slot = 17, -- .pin = 1, -- .irq = ATH79_PCI_IRQ(0), -- }, { -- .slot = 18, -- .pin = 1, -- .irq = ATH79_PCI_IRQ(1), -- }, { -- .slot = 19, -- .pin = 1, -- .irq = ATH79_PCI_IRQ(2), -- } --}; -- --static const struct ath79_pci_irq ar724x_pci_irq_map[] = { -- { -- .slot = 0, -- .pin = 1, -- .irq = ATH79_PCI_IRQ(0), -- } --}; -- --static const struct ath79_pci_irq qca955x_pci_irq_map[] = { -- { -- .bus = 0, -- .slot = 0, -- .pin = 1, -- .irq = ATH79_PCI_IRQ(0), -- }, -- { -- .bus = 1, -- .slot = 0, -- .pin = 1, -- .irq = ATH79_PCI_IRQ(1), -- }, --}; -- --int pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) --{ -- int irq = -1; -- int i; -- -- if (ath79_pci_nr_irqs == 0 || -- ath79_pci_irq_map == NULL) { -- if (soc_is_ar71xx()) { -- ath79_pci_irq_map = ar71xx_pci_irq_map; -- ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); -- } else if (soc_is_ar724x() || -- soc_is_ar9342() || -- soc_is_ar9344()) { -- ath79_pci_irq_map = ar724x_pci_irq_map; -- ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); -- } else if (soc_is_qca955x()) { -- ath79_pci_irq_map = qca955x_pci_irq_map; -- ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); -- } else { -- pr_crit("pci %s: invalid irq map\n", -- pci_name((struct pci_dev *) dev)); -- return irq; -- } -- } -- -- for (i = 0; i < ath79_pci_nr_irqs; i++) { -- const struct ath79_pci_irq *entry; -- -- entry = &ath79_pci_irq_map[i]; -- if (entry->bus == dev->bus->number && -- entry->slot == slot && -- entry->pin == pin) { -- irq = entry->irq; -- break; -- } -- } -- -- if (irq < 0) -- pr_crit("pci %s: no irq found for pin %u\n", -- pci_name((struct pci_dev *) dev), pin); -- else -- pr_info("pci %s: using irq %d for pin %u\n", -- pci_name((struct pci_dev *) dev), irq, pin); -- -- return irq; --} -- --int pcibios_plat_dev_init(struct pci_dev *dev) --{ -- if (ath79_pci_plat_dev_init) -- return ath79_pci_plat_dev_init(dev); -- -- return 0; --} -- --void __init ath79_pci_set_irq_map(unsigned nr_irqs, -- const struct ath79_pci_irq *map) --{ -- ath79_pci_nr_irqs = nr_irqs; -- ath79_pci_irq_map = map; --} -- --void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) --{ -- ath79_pci_plat_dev_init = func; --} -- --static struct platform_device * --ath79_register_pci_ar71xx(void) --{ -- struct platform_device *pdev; -- struct resource res[4]; -- -- memset(res, 0, sizeof(res)); -- -- res[0].name = "cfg_base"; -- res[0].flags = IORESOURCE_MEM; -- res[0].start = AR71XX_PCI_CFG_BASE; -- res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1; -- -- res[1].flags = IORESOURCE_IRQ; -- res[1].start = ATH79_CPU_IRQ(2); -- res[1].end = ATH79_CPU_IRQ(2); -- -- res[2].name = "io_base"; -- res[2].flags = IORESOURCE_IO; -- res[2].start = 0; -- res[2].end = 0; -- -- res[3].name = "mem_base"; -- res[3].flags = IORESOURCE_MEM; -- res[3].start = AR71XX_PCI_MEM_BASE; -- res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1; -- -- pdev = platform_device_register_simple("ar71xx-pci", -1, -- res, ARRAY_SIZE(res)); -- return pdev; --} -- --static struct platform_device * --ath79_register_pci_ar724x(int id, -- unsigned long cfg_base, -- unsigned long ctrl_base, -- unsigned long crp_base, -- unsigned long mem_base, -- unsigned long mem_size, -- unsigned long io_base, -- int irq) --{ -- struct platform_device *pdev; -- struct resource res[6]; -- -- memset(res, 0, sizeof(res)); -- -- res[0].name = "cfg_base"; -- res[0].flags = IORESOURCE_MEM; -- res[0].start = cfg_base; -- res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1; -- -- res[1].name = "ctrl_base"; -- res[1].flags = IORESOURCE_MEM; -- res[1].start = ctrl_base; -- res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1; -- -- res[2].flags = IORESOURCE_IRQ; -- res[2].start = irq; -- res[2].end = irq; -- -- res[3].name = "mem_base"; -- res[3].flags = IORESOURCE_MEM; -- res[3].start = mem_base; -- res[3].end = mem_base + mem_size - 1; -- -- res[4].name = "io_base"; -- res[4].flags = IORESOURCE_IO; -- res[4].start = io_base; -- res[4].end = io_base; -- -- res[5].name = "crp_base"; -- res[5].flags = IORESOURCE_MEM; -- res[5].start = crp_base; -- res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1; -- -- pdev = platform_device_register_simple("ar724x-pci", id, -- res, ARRAY_SIZE(res)); -- return pdev; --} -- --int __init ath79_register_pci(void) --{ -- struct platform_device *pdev = NULL; -- -- if (soc_is_ar71xx()) { -- pdev = ath79_register_pci_ar71xx(); -- } else if (soc_is_ar724x()) { -- pdev = ath79_register_pci_ar724x(-1, -- AR724X_PCI_CFG_BASE, -- AR724X_PCI_CTRL_BASE, -- AR724X_PCI_CRP_BASE, -- AR724X_PCI_MEM_BASE, -- AR724X_PCI_MEM_SIZE, -- 0, -- ATH79_CPU_IRQ(2)); -- } else if (soc_is_ar9342() || -- soc_is_ar9344()) { -- u32 bootstrap; -- -- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -- if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0) -- return -ENODEV; -- -- pdev = ath79_register_pci_ar724x(-1, -- AR724X_PCI_CFG_BASE, -- AR724X_PCI_CTRL_BASE, -- AR724X_PCI_CRP_BASE, -- AR724X_PCI_MEM_BASE, -- AR724X_PCI_MEM_SIZE, -- 0, -- ATH79_IP2_IRQ(0)); -- } else if (soc_is_qca9558()) { -- pdev = ath79_register_pci_ar724x(0, -- QCA955X_PCI_CFG_BASE0, -- QCA955X_PCI_CTRL_BASE0, -- QCA955X_PCI_CRP_BASE0, -- QCA955X_PCI_MEM_BASE0, -- QCA955X_PCI_MEM_SIZE, -- 0, -- ATH79_IP2_IRQ(0)); -- -- pdev = ath79_register_pci_ar724x(1, -- QCA955X_PCI_CFG_BASE1, -- QCA955X_PCI_CTRL_BASE1, -- QCA955X_PCI_CRP_BASE1, -- QCA955X_PCI_MEM_BASE1, -- QCA955X_PCI_MEM_SIZE, -- 1, -- ATH79_IP3_IRQ(2)); -- } else { -- /* No PCI support */ -- return -ENODEV; -- } -- -- if (!pdev) -- pr_err("unable to register PCI controller device\n"); -- -- return pdev ? 0 : -ENODEV; --} ---- a/arch/mips/ath79/pci.h -+++ /dev/null -@@ -1,35 +0,0 @@ --/* -- * Atheros AR71XX/AR724X PCI support -- * -- * Copyright (C) 2011 René Bolldorf -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_PCI_H --#define _ATH79_PCI_H -- --struct ath79_pci_irq { -- int bus; -- u8 slot; -- u8 pin; -- int irq; --}; -- --#ifdef CONFIG_PCI --void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map); --void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); --int ath79_register_pci(void); --#else --static inline void --ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {} --static inline void --ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {} --static inline int ath79_register_pci(void) { return 0; } --#endif -- --#endif /* _ATH79_PCI_H */ ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -29,6 +29,7 @@ obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-vir - # - # These are still pretty much in the old state, watch, go blind. - # -+obj-$(CONFIG_ATH79) += fixup-ath79.o - obj-$(CONFIG_LASAT) += pci-lasat.o - obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o - obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o ---- /dev/null -+++ b/arch/mips/pci/fixup-ath79.c -@@ -0,0 +1,21 @@ -+/* -+ * Copyright (C) 2018 John Crispin -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+//#include -+#include -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ return of_irq_parse_and_map_pci(dev, slot, pin); -+} diff --git a/target/linux/ath79/patches-4.14/0030-MIPS-ath79-drop-platform-device-registration-code.patch b/target/linux/ath79/patches-4.14/0030-MIPS-ath79-drop-platform-device-registration-code.patch deleted file mode 100644 index 93a133c1df..0000000000 --- a/target/linux/ath79/patches-4.14/0030-MIPS-ath79-drop-platform-device-registration-code.patch +++ /dev/null @@ -1,933 +0,0 @@ -From dce930fba8ad3a90ccd164f199e57c2d61937ccd Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:12:38 +0200 -Subject: [PATCH 30/33] MIPS: ath79: drop platform device registration code - -With the target now being fully OF based, we can drop the legacy platform -device registration code. All devices and their drivers are now probed -via OF. - -Signed-off-by: John Crispin ---- - arch/mips/ath79/Makefile | 10 -- - arch/mips/ath79/common.h | 2 - - arch/mips/ath79/dev-common.c | 159 ------------------------ - arch/mips/ath79/dev-common.h | 18 --- - arch/mips/ath79/dev-gpio-buttons.c | 56 --------- - arch/mips/ath79/dev-gpio-buttons.h | 23 ---- - arch/mips/ath79/dev-leds-gpio.c | 54 --------- - arch/mips/ath79/dev-leds-gpio.h | 21 ---- - arch/mips/ath79/dev-spi.c | 38 ------ - arch/mips/ath79/dev-spi.h | 22 ---- - arch/mips/ath79/dev-usb.c | 242 ------------------------------------- - arch/mips/ath79/dev-usb.h | 17 --- - arch/mips/ath79/dev-wmac.c | 155 ------------------------ - arch/mips/ath79/dev-wmac.h | 17 --- - arch/mips/ath79/setup.c | 1 - - 15 files changed, 835 deletions(-) - delete mode 100644 arch/mips/ath79/dev-common.c - delete mode 100644 arch/mips/ath79/dev-common.h - delete mode 100644 arch/mips/ath79/dev-gpio-buttons.c - delete mode 100644 arch/mips/ath79/dev-gpio-buttons.h - delete mode 100644 arch/mips/ath79/dev-leds-gpio.c - delete mode 100644 arch/mips/ath79/dev-leds-gpio.h - delete mode 100644 arch/mips/ath79/dev-spi.c - delete mode 100644 arch/mips/ath79/dev-spi.h - delete mode 100644 arch/mips/ath79/dev-usb.c - delete mode 100644 arch/mips/ath79/dev-usb.h - delete mode 100644 arch/mips/ath79/dev-wmac.c - delete mode 100644 arch/mips/ath79/dev-wmac.h - ---- a/arch/mips/ath79/Makefile -+++ b/arch/mips/ath79/Makefile -@@ -11,13 +11,3 @@ - obj-y := prom.o setup.o common.o clock.o - - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -- --# --# Devices --# --obj-y += dev-common.o --obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o --obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o --obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o --obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o --obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o ---- a/arch/mips/ath79/common.h -+++ b/arch/mips/ath79/common.h -@@ -24,6 +24,4 @@ unsigned long ath79_get_sys_clk_rate(con - - void ath79_ddr_ctrl_init(void); - --void ath79_gpio_init(void); -- - #endif /* __ATH79_COMMON_H */ ---- a/arch/mips/ath79/dev-common.c -+++ /dev/null -@@ -1,159 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X common devices -- * -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * Parts of this file are based on Atheros' 2.6.15 BSP -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include --#include --#include -- --#include --#include --#include "common.h" --#include "dev-common.h" -- --static struct resource ath79_uart_resources[] = { -- { -- .start = AR71XX_UART_BASE, -- .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, --}; -- --#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) --static struct plat_serial8250_port ath79_uart_data[] = { -- { -- .mapbase = AR71XX_UART_BASE, -- .irq = ATH79_MISC_IRQ(3), -- .flags = AR71XX_UART_FLAGS, -- .iotype = UPIO_MEM32, -- .regshift = 2, -- }, { -- /* terminating entry */ -- } --}; -- --static struct platform_device ath79_uart_device = { -- .name = "serial8250", -- .id = PLAT8250_DEV_PLATFORM, -- .resource = ath79_uart_resources, -- .num_resources = ARRAY_SIZE(ath79_uart_resources), -- .dev = { -- .platform_data = ath79_uart_data -- }, --}; -- --static struct resource ar933x_uart_resources[] = { -- { -- .start = AR933X_UART_BASE, -- .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, -- { -- .start = ATH79_MISC_IRQ(3), -- .end = ATH79_MISC_IRQ(3), -- .flags = IORESOURCE_IRQ, -- }, --}; -- --static struct platform_device ar933x_uart_device = { -- .name = "ar933x-uart", -- .id = -1, -- .resource = ar933x_uart_resources, -- .num_resources = ARRAY_SIZE(ar933x_uart_resources), --}; -- --void __init ath79_register_uart(void) --{ -- unsigned long uart_clk_rate; -- -- uart_clk_rate = ath79_get_sys_clk_rate("uart"); -- -- if (soc_is_ar71xx() || -- soc_is_ar724x() || -- soc_is_ar913x() || -- soc_is_ar934x() || -- soc_is_qca955x()) { -- ath79_uart_data[0].uartclk = uart_clk_rate; -- platform_device_register(&ath79_uart_device); -- } else if (soc_is_ar933x()) { -- platform_device_register(&ar933x_uart_device); -- } else { -- BUG(); -- } --} -- --void __init ath79_register_wdt(void) --{ -- struct resource res; -- -- memset(&res, 0, sizeof(res)); -- -- res.flags = IORESOURCE_MEM; -- res.start = AR71XX_RESET_BASE + AR71XX_RESET_REG_WDOG_CTRL; -- res.end = res.start + 0x8 - 1; -- -- platform_device_register_simple("ath79-wdt", -1, &res, 1); --} -- --static struct ath79_gpio_platform_data ath79_gpio_pdata; -- --static struct resource ath79_gpio_resources[] = { -- { -- .flags = IORESOURCE_MEM, -- .start = AR71XX_GPIO_BASE, -- .end = AR71XX_GPIO_BASE + AR71XX_GPIO_SIZE - 1, -- }, -- { -- .start = ATH79_MISC_IRQ(2), -- .end = ATH79_MISC_IRQ(2), -- .flags = IORESOURCE_IRQ, -- }, --}; -- --static struct platform_device ath79_gpio_device = { -- .name = "ath79-gpio", -- .id = -1, -- .resource = ath79_gpio_resources, -- .num_resources = ARRAY_SIZE(ath79_gpio_resources), -- .dev = { -- .platform_data = &ath79_gpio_pdata -- }, --}; -- --void __init ath79_gpio_init(void) --{ -- if (soc_is_ar71xx()) { -- ath79_gpio_pdata.ngpios = AR71XX_GPIO_COUNT; -- } else if (soc_is_ar7240()) { -- ath79_gpio_pdata.ngpios = AR7240_GPIO_COUNT; -- } else if (soc_is_ar7241() || soc_is_ar7242()) { -- ath79_gpio_pdata.ngpios = AR7241_GPIO_COUNT; -- } else if (soc_is_ar913x()) { -- ath79_gpio_pdata.ngpios = AR913X_GPIO_COUNT; -- } else if (soc_is_ar933x()) { -- ath79_gpio_pdata.ngpios = AR933X_GPIO_COUNT; -- } else if (soc_is_ar934x()) { -- ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT; -- ath79_gpio_pdata.oe_inverted = 1; -- } else if (soc_is_qca955x()) { -- ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT; -- ath79_gpio_pdata.oe_inverted = 1; -- } else { -- BUG(); -- } -- -- platform_device_register(&ath79_gpio_device); --} ---- a/arch/mips/ath79/dev-common.h -+++ /dev/null -@@ -1,18 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X common devices -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_DEV_COMMON_H --#define _ATH79_DEV_COMMON_H -- --void ath79_register_uart(void); --void ath79_register_wdt(void); -- --#endif /* _ATH79_DEV_COMMON_H */ ---- a/arch/mips/ath79/dev-gpio-buttons.c -+++ /dev/null -@@ -1,56 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X GPIO button support -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include "linux/init.h" --#include "linux/slab.h" --#include -- --#include "dev-gpio-buttons.h" -- --void __init ath79_register_gpio_keys_polled(int id, -- unsigned poll_interval, -- unsigned nbuttons, -- struct gpio_keys_button *buttons) --{ -- struct platform_device *pdev; -- struct gpio_keys_platform_data pdata; -- struct gpio_keys_button *p; -- int err; -- -- p = kmemdup(buttons, nbuttons * sizeof(*p), GFP_KERNEL); -- if (!p) -- return; -- -- pdev = platform_device_alloc("gpio-keys-polled", id); -- if (!pdev) -- goto err_free_buttons; -- -- memset(&pdata, 0, sizeof(pdata)); -- pdata.poll_interval = poll_interval; -- pdata.nbuttons = nbuttons; -- pdata.buttons = p; -- -- err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -- if (err) -- goto err_put_pdev; -- -- err = platform_device_add(pdev); -- if (err) -- goto err_put_pdev; -- -- return; -- --err_put_pdev: -- platform_device_put(pdev); -- --err_free_buttons: -- kfree(p); --} ---- a/arch/mips/ath79/dev-gpio-buttons.h -+++ /dev/null -@@ -1,23 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X GPIO button support -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_DEV_GPIO_BUTTONS_H --#define _ATH79_DEV_GPIO_BUTTONS_H -- --#include --#include -- --void ath79_register_gpio_keys_polled(int id, -- unsigned poll_interval, -- unsigned nbuttons, -- struct gpio_keys_button *buttons); -- --#endif /* _ATH79_DEV_GPIO_BUTTONS_H */ ---- a/arch/mips/ath79/dev-leds-gpio.c -+++ /dev/null -@@ -1,54 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include -- --#include "dev-leds-gpio.h" -- --void __init ath79_register_leds_gpio(int id, -- unsigned num_leds, -- struct gpio_led *leds) --{ -- struct platform_device *pdev; -- struct gpio_led_platform_data pdata; -- struct gpio_led *p; -- int err; -- -- p = kmemdup(leds, num_leds * sizeof(*p), GFP_KERNEL); -- if (!p) -- return; -- -- pdev = platform_device_alloc("leds-gpio", id); -- if (!pdev) -- goto err_free_leds; -- -- memset(&pdata, 0, sizeof(pdata)); -- pdata.num_leds = num_leds; -- pdata.leds = p; -- -- err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -- if (err) -- goto err_put_pdev; -- -- err = platform_device_add(pdev); -- if (err) -- goto err_put_pdev; -- -- return; -- --err_put_pdev: -- platform_device_put(pdev); -- --err_free_leds: -- kfree(p); --} ---- a/arch/mips/ath79/dev-leds-gpio.h -+++ /dev/null -@@ -1,21 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_DEV_LEDS_GPIO_H --#define _ATH79_DEV_LEDS_GPIO_H -- --#include -- --void ath79_register_leds_gpio(int id, -- unsigned num_leds, -- struct gpio_led *leds); -- --#endif /* _ATH79_DEV_LEDS_GPIO_H */ ---- a/arch/mips/ath79/dev-spi.c -+++ /dev/null -@@ -1,38 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X SPI controller device -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include "dev-spi.h" -- --static struct resource ath79_spi_resources[] = { -- { -- .start = AR71XX_SPI_BASE, -- .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, --}; -- --static struct platform_device ath79_spi_device = { -- .name = "ath79-spi", -- .id = -1, -- .resource = ath79_spi_resources, -- .num_resources = ARRAY_SIZE(ath79_spi_resources), --}; -- --void __init ath79_register_spi(struct ath79_spi_platform_data *pdata, -- struct spi_board_info const *info, -- unsigned n) --{ -- spi_register_board_info(info, n); -- ath79_spi_device.dev.platform_data = pdata; -- platform_device_register(&ath79_spi_device); --} ---- a/arch/mips/ath79/dev-spi.h -+++ /dev/null -@@ -1,22 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X SPI controller device -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_DEV_SPI_H --#define _ATH79_DEV_SPI_H -- --#include --#include -- --void ath79_register_spi(struct ath79_spi_platform_data *pdata, -- struct spi_board_info const *info, -- unsigned n); -- --#endif /* _ATH79_DEV_SPI_H */ ---- a/arch/mips/ath79/dev-usb.c -+++ /dev/null -@@ -1,242 +0,0 @@ --/* -- * Atheros AR7XXX/AR9XXX USB Host Controller device -- * -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * Parts of this file are based on Atheros' 2.6.15 BSP -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include -- --#include --#include --#include "common.h" --#include "dev-usb.h" -- --static u64 ath79_usb_dmamask = DMA_BIT_MASK(32); -- --static struct usb_ohci_pdata ath79_ohci_pdata = { --}; -- --static struct usb_ehci_pdata ath79_ehci_pdata_v1 = { -- .has_synopsys_hc_bug = 1, --}; -- --static struct usb_ehci_pdata ath79_ehci_pdata_v2 = { -- .caps_offset = 0x100, -- .has_tt = 1, --}; -- --static void __init ath79_usb_register(const char *name, int id, -- unsigned long base, unsigned long size, -- int irq, const void *data, -- size_t data_size) --{ -- struct resource res[2]; -- struct platform_device *pdev; -- -- memset(res, 0, sizeof(res)); -- -- res[0].flags = IORESOURCE_MEM; -- res[0].start = base; -- res[0].end = base + size - 1; -- -- res[1].flags = IORESOURCE_IRQ; -- res[1].start = irq; -- res[1].end = irq; -- -- pdev = platform_device_register_resndata(NULL, name, id, -- res, ARRAY_SIZE(res), -- data, data_size); -- -- if (IS_ERR(pdev)) { -- pr_err("ath79: unable to register USB at %08lx, err=%d\n", -- base, (int) PTR_ERR(pdev)); -- return; -- } -- -- pdev->dev.dma_mask = &ath79_usb_dmamask; -- pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); --} -- --#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ -- AR71XX_RESET_USB_PHY | \ -- AR71XX_RESET_USB_OHCI_DLL) -- --static void __init ath79_usb_setup(void) --{ -- void __iomem *usb_ctrl_base; -- -- ath79_device_reset_set(AR71XX_USB_RESET_MASK); -- mdelay(1000); -- ath79_device_reset_clear(AR71XX_USB_RESET_MASK); -- -- usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE); -- -- /* Turning on the Buff and Desc swap bits */ -- __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG); -- -- /* WAR for HW bug. Here it adjusts the duration between two SOFS */ -- __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); -- -- iounmap(usb_ctrl_base); -- -- mdelay(900); -- -- ath79_usb_register("ohci-platform", -1, -- AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE, -- ATH79_MISC_IRQ(6), -- &ath79_ohci_pdata, sizeof(ath79_ohci_pdata)); -- -- ath79_usb_register("ehci-platform", -1, -- AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1)); --} -- --static void __init ar7240_usb_setup(void) --{ -- void __iomem *usb_ctrl_base; -- -- ath79_device_reset_clear(AR7240_RESET_OHCI_DLL); -- ath79_device_reset_set(AR7240_RESET_USB_HOST); -- -- mdelay(1000); -- -- ath79_device_reset_set(AR7240_RESET_OHCI_DLL); -- ath79_device_reset_clear(AR7240_RESET_USB_HOST); -- -- usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE); -- -- /* WAR for HW bug. Here it adjusts the duration between two SOFS */ -- __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); -- -- iounmap(usb_ctrl_base); -- -- ath79_usb_register("ohci-platform", -1, -- AR7240_OHCI_BASE, AR7240_OHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ohci_pdata, sizeof(ath79_ohci_pdata)); --} -- --static void __init ar724x_usb_setup(void) --{ -- ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE); -- mdelay(10); -- -- ath79_device_reset_clear(AR724X_RESET_USB_HOST); -- mdelay(10); -- -- ath79_device_reset_clear(AR724X_RESET_USB_PHY); -- mdelay(10); -- -- ath79_usb_register("ehci-platform", -1, -- AR724X_EHCI_BASE, AR724X_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); --} -- --static void __init ar913x_usb_setup(void) --{ -- ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE); -- mdelay(10); -- -- ath79_device_reset_clear(AR913X_RESET_USB_HOST); -- mdelay(10); -- -- ath79_device_reset_clear(AR913X_RESET_USB_PHY); -- mdelay(10); -- -- ath79_usb_register("ehci-platform", -1, -- AR913X_EHCI_BASE, AR913X_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); --} -- --static void __init ar933x_usb_setup(void) --{ -- ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE); -- mdelay(10); -- -- ath79_device_reset_clear(AR933X_RESET_USB_HOST); -- mdelay(10); -- -- ath79_device_reset_clear(AR933X_RESET_USB_PHY); -- mdelay(10); -- -- ath79_usb_register("ehci-platform", -1, -- AR933X_EHCI_BASE, AR933X_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); --} -- --static void __init ar934x_usb_setup(void) --{ -- u32 bootstrap; -- -- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) -- return; -- -- ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE); -- udelay(1000); -- -- ath79_device_reset_clear(AR934X_RESET_USB_PHY); -- udelay(1000); -- -- ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG); -- udelay(1000); -- -- ath79_device_reset_clear(AR934X_RESET_USB_HOST); -- udelay(1000); -- -- ath79_usb_register("ehci-platform", -1, -- AR934X_EHCI_BASE, AR934X_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); --} -- --static void __init qca955x_usb_setup(void) --{ -- ath79_usb_register("ehci-platform", 0, -- QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE, -- ATH79_IP3_IRQ(0), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -- -- ath79_usb_register("ehci-platform", 1, -- QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE, -- ATH79_IP3_IRQ(1), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); --} -- --void __init ath79_register_usb(void) --{ -- if (soc_is_ar71xx()) -- ath79_usb_setup(); -- else if (soc_is_ar7240()) -- ar7240_usb_setup(); -- else if (soc_is_ar7241() || soc_is_ar7242()) -- ar724x_usb_setup(); -- else if (soc_is_ar913x()) -- ar913x_usb_setup(); -- else if (soc_is_ar933x()) -- ar933x_usb_setup(); -- else if (soc_is_ar934x()) -- ar934x_usb_setup(); -- else if (soc_is_qca955x()) -- qca955x_usb_setup(); -- else -- BUG(); --} ---- a/arch/mips/ath79/dev-usb.h -+++ /dev/null -@@ -1,17 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X USB Host Controller support -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_DEV_USB_H --#define _ATH79_DEV_USB_H -- --void ath79_register_usb(void); -- --#endif /* _ATH79_DEV_USB_H */ ---- a/arch/mips/ath79/dev-wmac.c -+++ /dev/null -@@ -1,155 +0,0 @@ --/* -- * Atheros AR913X/AR933X SoC built-in WMAC device support -- * -- * Copyright (C) 2010-2011 Jaiganesh Narayanan -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include -- --#include --#include --#include "dev-wmac.h" -- --static struct ath9k_platform_data ath79_wmac_data; -- --static struct resource ath79_wmac_resources[] = { -- { -- /* .start and .end fields are filled dynamically */ -- .flags = IORESOURCE_MEM, -- }, { -- /* .start and .end fields are filled dynamically */ -- .flags = IORESOURCE_IRQ, -- }, --}; -- --static struct platform_device ath79_wmac_device = { -- .name = "ath9k", -- .id = -1, -- .resource = ath79_wmac_resources, -- .num_resources = ARRAY_SIZE(ath79_wmac_resources), -- .dev = { -- .platform_data = &ath79_wmac_data, -- }, --}; -- --static void __init ar913x_wmac_setup(void) --{ -- /* reset the WMAC */ -- ath79_device_reset_set(AR913X_RESET_AMBA2WMAC); -- mdelay(10); -- -- ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC); -- mdelay(10); -- -- ath79_wmac_resources[0].start = AR913X_WMAC_BASE; -- ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; -- ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); -- ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); --} -- -- --static int ar933x_wmac_reset(void) --{ -- ath79_device_reset_set(AR933X_RESET_WMAC); -- ath79_device_reset_clear(AR933X_RESET_WMAC); -- -- return 0; --} -- --static int ar933x_r1_get_wmac_revision(void) --{ -- return ath79_soc_rev; --} -- --static void __init ar933x_wmac_setup(void) --{ -- u32 t; -- -- ar933x_wmac_reset(); -- -- ath79_wmac_device.name = "ar933x_wmac"; -- -- ath79_wmac_resources[0].start = AR933X_WMAC_BASE; -- ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; -- ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); -- ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); -- -- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); -- if (t & AR933X_BOOTSTRAP_REF_CLK_40) -- ath79_wmac_data.is_clk_25mhz = false; -- else -- ath79_wmac_data.is_clk_25mhz = true; -- -- if (ath79_soc_rev == 1) -- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision; -- -- ath79_wmac_data.external_reset = ar933x_wmac_reset; --} -- --static void ar934x_wmac_setup(void) --{ -- u32 t; -- -- ath79_wmac_device.name = "ar934x_wmac"; -- -- ath79_wmac_resources[0].start = AR934X_WMAC_BASE; -- ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; -- ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); -- ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); -- -- t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -- if (t & AR934X_BOOTSTRAP_REF_CLK_40) -- ath79_wmac_data.is_clk_25mhz = false; -- else -- ath79_wmac_data.is_clk_25mhz = true; --} -- --static void qca955x_wmac_setup(void) --{ -- u32 t; -- -- ath79_wmac_device.name = "qca955x_wmac"; -- -- ath79_wmac_resources[0].start = QCA955X_WMAC_BASE; -- ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1; -- ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); -- ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); -- -- t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); -- if (t & QCA955X_BOOTSTRAP_REF_CLK_40) -- ath79_wmac_data.is_clk_25mhz = false; -- else -- ath79_wmac_data.is_clk_25mhz = true; --} -- --void __init ath79_register_wmac(u8 *cal_data) --{ -- if (soc_is_ar913x()) -- ar913x_wmac_setup(); -- else if (soc_is_ar933x()) -- ar933x_wmac_setup(); -- else if (soc_is_ar934x()) -- ar934x_wmac_setup(); -- else if (soc_is_qca955x()) -- qca955x_wmac_setup(); -- else -- BUG(); -- -- if (cal_data) -- memcpy(ath79_wmac_data.eeprom_data, cal_data, -- sizeof(ath79_wmac_data.eeprom_data)); -- -- platform_device_register(&ath79_wmac_device); --} ---- a/arch/mips/ath79/dev-wmac.h -+++ /dev/null -@@ -1,17 +0,0 @@ --/* -- * Atheros AR913X/AR933X SoC built-in WMAC device support -- * -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_DEV_WMAC_H --#define _ATH79_DEV_WMAC_H -- --void ath79_register_wmac(u8 *cal_data); -- --#endif /* _ATH79_DEV_WMAC_H */ ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -32,7 +32,6 @@ - #include - #include - #include "common.h" --#include "dev-common.h" - - #define ATH79_SYS_TYPE_LEN 64 - diff --git a/target/linux/ath79/patches-4.14/0031-MIPS-ath79-drop-OF-clock-code.patch b/target/linux/ath79/patches-4.14/0031-MIPS-ath79-drop-OF-clock-code.patch deleted file mode 100644 index a11be73d7a..0000000000 --- a/target/linux/ath79/patches-4.14/0031-MIPS-ath79-drop-OF-clock-code.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 00e4313da4609074fff134e61dd9ffe3fd37474d Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 24 Jun 2018 09:39:41 +0200 -Subject: [PATCH 31/33] MIPS: ath79: drop !OF clock code - -With the target now being fully OF based, we can drop the legacy clock -registration code. All clocks are now probed via devicetree. - -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 56 ------------------------------------------------ - arch/mips/ath79/common.h | 3 --- - 2 files changed, 59 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -617,60 +617,6 @@ static void __init qca956x_clocks_init(v - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - } - --void __init ath79_clocks_init(void) --{ -- const char *wdt; -- const char *uart; -- -- if (soc_is_ar71xx()) -- ar71xx_clocks_init(ath79_pll_base); -- else if (soc_is_ar724x() || soc_is_ar913x()) -- ar724x_clocks_init(ath79_pll_base); -- else if (soc_is_ar933x()) -- ar933x_clocks_init(ath79_pll_base); -- else if (soc_is_ar934x()) -- ar934x_clocks_init(ath79_pll_base); -- else if (soc_is_qca953x()) -- qca953x_clocks_init(ath79_pll_base); -- else if (soc_is_qca955x()) -- qca955x_clocks_init(ath79_pll_base); -- else if (soc_is_qca956x() || soc_is_tp9343()) -- qca956x_clocks_init(ath79_pll_base); -- else -- BUG(); -- -- if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) { -- wdt = "ahb"; -- uart = "ahb"; -- } else if (soc_is_ar933x()) { -- wdt = "ahb"; -- uart = "ref"; -- } else { -- wdt = "ref"; -- uart = "ref"; -- } -- -- clk_add_alias("wdt", NULL, wdt, NULL); -- clk_add_alias("uart", NULL, uart, NULL); --} -- --unsigned long __init --ath79_get_sys_clk_rate(const char *id) --{ -- struct clk *clk; -- unsigned long rate; -- -- clk = clk_get(NULL, id); -- if (IS_ERR(clk)) -- panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk)); -- -- rate = clk_get_rate(clk); -- clk_put(clk); -- -- return rate; --} -- --#ifdef CONFIG_OF - static void __init ath79_clocks_init_dt(struct device_node *np) - { - struct clk *ref_clk; -@@ -727,5 +673,3 @@ CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-p - CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt); - CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt); - CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt); -- --#endif ---- a/arch/mips/ath79/common.h -+++ b/arch/mips/ath79/common.h -@@ -19,9 +19,6 @@ - #define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) - #define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024) - --void ath79_clocks_init(void); --unsigned long ath79_get_sys_clk_rate(const char *id); -- - void ath79_ddr_ctrl_init(void); - - #endif /* __ATH79_COMMON_H */ diff --git a/target/linux/ath79/patches-4.14/0038-at803x-disable-delays.patch b/target/linux/ath79/patches-4.14/0038-at803x-disable-delays.patch deleted file mode 100644 index cf05d0fc4a..0000000000 --- a/target/linux/ath79/patches-4.14/0038-at803x-disable-delays.patch +++ /dev/null @@ -1,27 +0,0 @@ -Until upstream commit 6d4cd041f0af("net: phy: at803x: disable delay -only for RGMII mode"), delays were not disabled on driver probe -for the Atheros AR803x PHYs, although the RX delay is enabled on -soft and hard reset. - -In addition, the TX delay setting is retained on soft-reset. - -This patch disables both delays on config init to align the behavior -with kernel 5.1 and higher. It can be safely dropped with kernel 5.1. - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -320,6 +320,14 @@ static int at803x_config_init(struct phy - if (ret < 0) - return ret; - -+ /* Disable RX delay */ -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, -+ AT803X_DEBUG_RX_CLK_DLY_EN, 0); -+ -+ /* Disable TX delay */ -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, -+ AT803X_DEBUG_TX_CLK_DLY_EN, 0); -+ - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || - phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - ret = at803x_enable_rx_delay(phydev); diff --git a/target/linux/ath79/patches-4.14/420-net-ar71xx_mac_driver.patch b/target/linux/ath79/patches-4.14/420-net-ar71xx_mac_driver.patch deleted file mode 100644 index 6377db0ac2..0000000000 --- a/target/linux/ath79/patches-4.14/420-net-ar71xx_mac_driver.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/drivers/net/ethernet/atheros/Kconfig -+++ b/drivers/net/ethernet/atheros/Kconfig -@@ -5,7 +5,7 @@ - config NET_VENDOR_ATHEROS - bool "Atheros devices" - default y -- depends on PCI -+ depends on (PCI || ATH79) - ---help--- - If you have a network (Ethernet) card belonging to this class, say Y. - -@@ -78,4 +78,6 @@ config ALX - To compile this driver as a module, choose M here. The module - will be called alx. - -+source drivers/net/ethernet/atheros/ag71xx/Kconfig -+ - endif # NET_VENDOR_ATHEROS ---- a/drivers/net/ethernet/atheros/Makefile -+++ b/drivers/net/ethernet/atheros/Makefile -@@ -3,6 +3,7 @@ - # Makefile for the Atheros network device drivers. - # - -+obj-$(CONFIG_AG71XX) += ag71xx/ - obj-$(CONFIG_ATL1) += atlx/ - obj-$(CONFIG_ATL2) += atlx/ - obj-$(CONFIG_ATL1E) += atl1e/ diff --git a/target/linux/ath79/patches-4.14/461-spi-ath79-add-fast-flash-read.patch b/target/linux/ath79/patches-4.14/461-spi-ath79-add-fast-flash-read.patch deleted file mode 100644 index 7c24fc5e14..0000000000 --- a/target/linux/ath79/patches-4.14/461-spi-ath79-add-fast-flash-read.patch +++ /dev/null @@ -1,60 +0,0 @@ ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -101,9 +101,6 @@ static void ath79_spi_enable(struct ath7 - /* save CTRL register */ - sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); - sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); -- -- /* TODO: setup speed? */ -- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); - } - - static void ath79_spi_disable(struct ath79_spi *sp) -@@ -203,6 +200,38 @@ static u32 ath79_spi_txrx_mode0(struct s - return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); - } - -+static bool ath79_spi_flash_read_supported(struct spi_device *spi) -+{ -+ if (spi->chip_select || gpio_is_valid(spi->cs_gpio)) -+ return false; -+ -+ return true; -+} -+ -+static int ath79_spi_read_flash_data(struct spi_device *spi, -+ struct spi_flash_read_message *msg) -+{ -+ struct ath79_spi *sp = ath79_spidev_to_sp(spi); -+ -+ if (msg->addr_width > 3) -+ return -EOPNOTSUPP; -+ -+ /* disable GPIO mode */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); -+ -+ memcpy_fromio(msg->buf, sp->base + msg->from, msg->len); -+ -+ /* enable GPIO mode */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); -+ -+ /* restore IOC register */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); -+ -+ msg->retlen = msg->len; -+ -+ return 0; -+} -+ - static int ath79_spi_probe(struct platform_device *pdev) - { - struct spi_master *master; -@@ -237,6 +266,8 @@ static int ath79_spi_probe(struct platfo - ret = PTR_ERR(sp->base); - goto err_put_master; - } -+ master->spi_flash_read = ath79_spi_read_flash_data; -+ master->flash_read_supported = ath79_spi_flash_read_supported; - - sp->clk = devm_clk_get(&pdev->dev, "ahb"); - if (IS_ERR(sp->clk)) { diff --git a/target/linux/ath79/patches-4.19/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch b/target/linux/ath79/patches-4.19/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch new file mode 100644 index 0000000000..2c9120f771 --- /dev/null +++ b/target/linux/ath79/patches-4.19/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch @@ -0,0 +1,130 @@ +From: David Bauer +Date: Sat, 11 Apr 2020 14:03:12 +0200 +Subject: MIPS: pci-ar724x: add QCA9550 reset sequence + +The QCA9550 family of SoCs have a slightly different reset +sequence compared to older chips. + +Normally the bootloader performs this sequence, however +some bootloader implementation expect the operating system +to clear the reset. + +Also get the resets from OF to support handling of the second +PCIe root-complex on the QCA9558. + +Signed-off-by: David Bauer + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -394,6 +394,7 @@ + #define QCA955X_PLL_CPU_CONFIG_REG 0x00 + #define QCA955X_PLL_DDR_CONFIG_REG 0x04 + #define QCA955X_PLL_CLK_CTRL_REG 0x08 ++#define QCA955X_PLL_PCIE_CONFIG_REG 0x0c + #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 + #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + #define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c +@@ -479,6 +480,9 @@ + #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) + #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define QCA955X_PLL_PCIE_CONFIG_PLL_PWD BIT(30) ++#define QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS BIT(16) ++ + #define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5) + #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6) + #define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7) +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -11,6 +11,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -58,6 +59,9 @@ struct ar724x_pci_controller { + struct irq_domain *domain; + struct resource io_res; + struct resource mem_res; ++ ++ struct reset_control *hc_reset; ++ struct reset_control *phy_reset; + }; + + static struct irq_chip ar724x_pci_irq_chip; +@@ -343,18 +347,30 @@ static void ar724x_pci_hw_init(struct ar + int wait = 0; + + /* deassert PCIe host controller and PCIe PHY reset */ +- ath79_device_reset_clear(AR724X_RESET_PCIE); +- ath79_device_reset_clear(AR724X_RESET_PCIE_PHY); ++ reset_control_deassert(apc->hc_reset); ++ reset_control_deassert(apc->phy_reset); + +- /* remove the reset of the PCIE PLL */ +- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); +- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET; +- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); +- +- /* deassert bypass for the PCIE PLL */ +- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); +- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS; +- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); ++ if (of_device_is_compatible(apc->np, "qcom,qca9550-pci")) { ++ /* remove the reset of the PCIE PLL */ ++ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG); ++ ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_PWD; ++ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl); ++ ++ /* deassert bypass for the PCIE PLL */ ++ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG); ++ ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS; ++ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl); ++ } else { ++ /* remove the reset of the PCIE PLL */ ++ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); ++ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET; ++ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); ++ ++ /* deassert bypass for the PCIE PLL */ ++ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); ++ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS; ++ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); ++ } + + /* set PCIE Application Control to ready */ + app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP); +@@ -402,6 +418,14 @@ static int ar724x_pci_probe(struct platf + if (apc->irq < 0) + return -EINVAL; + ++ apc->hc_reset = devm_reset_control_get_exclusive(&pdev->dev, "hc"); ++ if (IS_ERR(apc->hc_reset)) ++ return PTR_ERR(apc->hc_reset); ++ ++ apc->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, "phy"); ++ if (IS_ERR(apc->phy_reset)) ++ return PTR_ERR(apc->phy_reset); ++ + apc->np = pdev->dev.of_node; + apc->pci_controller.pci_ops = &ar724x_pci_ops; + apc->pci_controller.io_resource = &apc->io_res; +@@ -412,7 +436,7 @@ static int ar724x_pci_probe(struct platf + * Do the full PCIE Root Complex Initialization Sequence if the PCIe + * host controller is in reset. + */ +- if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE) ++ if (reset_control_status(apc->hc_reset)) + ar724x_pci_hw_init(apc); + + apc->link_up = ar724x_pci_check_link(apc); +@@ -430,6 +454,7 @@ static int ar724x_pci_probe(struct platf + + static const struct of_device_id ar724x_pci_ids[] = { + { .compatible = "qcom,ar7240-pci" }, ++ { .compatible = "qcom,qca9550-pci" }, + {}, + }; + diff --git a/target/linux/ath79/patches-4.14/0002-watchdog-ath79-fix-maximum-timeout.patch b/target/linux/ath79/patches-5.4/0002-watchdog-ath79-fix-maximum-timeout.patch similarity index 92% rename from target/linux/ath79/patches-4.14/0002-watchdog-ath79-fix-maximum-timeout.patch rename to target/linux/ath79/patches-5.4/0002-watchdog-ath79-fix-maximum-timeout.patch index 36234d8d83..495721f609 100644 --- a/target/linux/ath79/patches-4.14/0002-watchdog-ath79-fix-maximum-timeout.patch +++ b/target/linux/ath79/patches-5.4/0002-watchdog-ath79-fix-maximum-timeout.patch @@ -13,7 +13,7 @@ Signed-off-by: John Crispin --- a/drivers/watchdog/ath79_wdt.c +++ b/drivers/watchdog/ath79_wdt.c -@@ -115,10 +115,14 @@ static inline void ath79_wdt_disable(voi +@@ -111,10 +111,14 @@ static inline void ath79_wdt_disable(voi static int ath79_wdt_set_timeout(int val) { diff --git a/target/linux/ath79/patches-4.14/0003-leds-add-reset-controller-based-driver.patch b/target/linux/ath79/patches-5.4/0003-leds-add-reset-controller-based-driver.patch similarity index 89% rename from target/linux/ath79/patches-4.14/0003-leds-add-reset-controller-based-driver.patch rename to target/linux/ath79/patches-5.4/0003-leds-add-reset-controller-based-driver.patch index d15c77a8dd..3249e1e82b 100644 --- a/target/linux/ath79/patches-4.14/0003-leds-add-reset-controller-based-driver.patch +++ b/target/linux/ath79/patches-5.4/0003-leds-add-reset-controller-based-driver.patch @@ -13,9 +13,9 @@ Signed-off-by: John Crispin --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -696,6 +696,17 @@ config LEDS_NIC78BX - To compile this driver as a module, choose M here: the module - will be called leds-nic78bx. +@@ -823,6 +823,17 @@ config LEDS_LM36274 + Say Y to enable the LM36274 LED driver for TI LMU devices. + This supports the LED device LM36274. +config LEDS_RESET + tristate "LED support for reset-controller API" @@ -108,7 +108,7 @@ Signed-off-by: John Crispin + fwnode_handle_put(child); + return ERR_PTR(-EINVAL); + } -+ led->rst = __of_reset_control_get(np, NULL, 0, 0, 0); ++ led->rst = __of_reset_control_get(np, NULL, 0, 0, 0, true); + if (IS_ERR(led->rst)) + return ERR_PTR(-EINVAL); + @@ -116,7 +116,7 @@ Signed-off-by: John Crispin + &led->cdev.default_trigger); + + led->cdev.brightness_set = reset_led_set; -+ ret = devm_of_led_classdev_register(&pdev->dev, np, &led->cdev); ++ ret = devm_led_classdev_register(&pdev->dev, &led->cdev); + if (ret < 0) + return ERR_PTR(ret); + led->cdev.dev->of_node = np; @@ -176,11 +176,11 @@ Signed-off-by: John Crispin +MODULE_ALIAS("platform:leds-reset"); --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile -@@ -73,6 +73,7 @@ obj-$(CONFIG_LEDS_PM8058) += leds-pm805 - obj-$(CONFIG_LEDS_MLXCPLD) += leds-mlxcpld.o - obj-$(CONFIG_LEDS_NIC78BX) += leds-nic78bx.o - obj-$(CONFIG_LEDS_MT6323) += leds-mt6323.o +@@ -85,6 +85,7 @@ obj-$(CONFIG_LEDS_LM3601X) += leds-lm36 + obj-$(CONFIG_LEDS_TI_LMU_COMMON) += leds-ti-lmu-common.o + obj-$(CONFIG_LEDS_LM3697) += leds-lm3697.o + obj-$(CONFIG_LEDS_LM36274) += leds-lm36274.o +obj-$(CONFIG_LEDS_RESET) += leds-reset.o # LED SPI Drivers - obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o + obj-$(CONFIG_LEDS_CR0014114) += leds-cr0014114.o diff --git a/target/linux/ath79/patches-4.14/0004-phy-add-ath79-usb-phys.patch b/target/linux/ath79/patches-5.4/0004-phy-add-ath79-usb-phys.patch similarity index 92% rename from target/linux/ath79/patches-4.14/0004-phy-add-ath79-usb-phys.patch rename to target/linux/ath79/patches-5.4/0004-phy-add-ath79-usb-phys.patch index 6280baf913..7956edb937 100644 --- a/target/linux/ath79/patches-4.14/0004-phy-add-ath79-usb-phys.patch +++ b/target/linux/ath79/patches-5.4/0004-phy-add-ath79-usb-phys.patch @@ -15,9 +15,9 @@ Signed-off-by: John Crispin --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig -@@ -15,6 +15,22 @@ config GENERIC_PHY - phy users can obtain reference to the PHY. All the users of this - framework should select this config. +@@ -24,6 +24,22 @@ config GENERIC_PHY_MIPI_DPHY + Provides a number of helpers a core functions for MIPI D-PHY + drivers to us. +config PHY_AR7100_USB + tristate "Atheros AR7100 USB PHY driver" @@ -46,9 +46,9 @@ Signed-off-by: John Crispin obj-$(CONFIG_GENERIC_PHY) += phy-core.o +obj-$(CONFIG_PHY_AR7100_USB) += phy-ar7100-usb.o +obj-$(CONFIG_PHY_AR7200_USB) += phy-ar7200-usb.o + obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o - obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o --- /dev/null +++ b/drivers/phy/phy-ar7100-usb.c @@ -0,0 +1,140 @@ @@ -194,7 +194,7 @@ Signed-off-by: John Crispin +MODULE_LICENSE("GPL"); --- /dev/null +++ b/drivers/phy/phy-ar7200-usb.c -@@ -0,0 +1,123 @@ +@@ -0,0 +1,135 @@ +/* + * Copyright (C) 2015 Alban Bedel + * @@ -212,6 +212,7 @@ Signed-off-by: John Crispin + +struct ar7200_usb_phy { + struct reset_control *rst_phy; ++ struct reset_control *rst_phy_analog; + struct reset_control *suspend_override; + struct phy *phy; + int gpio; @@ -222,12 +223,12 @@ Signed-off-by: John Crispin + struct ar7200_usb_phy *priv = phy_get_drvdata(phy); + int err = 0; + -+ if (priv->rst_phy) -+ err = reset_control_deassert(priv->rst_phy); -+ if (!err && priv->suspend_override) ++ if (priv->suspend_override) + err = reset_control_assert(priv->suspend_override); -+ if (err && priv->rst_phy) -+ err = reset_control_assert(priv->rst_phy); ++ if (priv->rst_phy) ++ err |= reset_control_deassert(priv->rst_phy); ++ if (priv->rst_phy_analog) ++ err |= reset_control_deassert(priv->rst_phy_analog); + + return err; +} @@ -241,6 +242,8 @@ Signed-off-by: John Crispin + err = reset_control_deassert(priv->suspend_override); + if (priv->rst_phy) + err |= reset_control_assert(priv->rst_phy); ++ if (priv->rst_phy_analog) ++ err |= reset_control_assert(priv->rst_phy_analog); + + return err; +} @@ -266,6 +269,15 @@ Signed-off-by: John Crispin + return PTR_ERR(priv->rst_phy); + } + ++ priv->rst_phy_analog = devm_reset_control_get_optional( ++ &pdev->dev, "usb-phy-analog"); ++ if (IS_ERR(priv->rst_phy_analog)) { ++ if (PTR_ERR(priv->rst_phy_analog) == -ENOENT) ++ priv->rst_phy_analog = NULL; ++ else ++ return PTR_ERR(priv->rst_phy_analog); ++ } ++ + priv->suspend_override = devm_reset_control_get_optional( + &pdev->dev, "usb-suspend-override"); + if (IS_ERR(priv->suspend_override)) { diff --git a/target/linux/ath79/patches-4.14/0005-usb-add-more-OF-quirk-properties.patch b/target/linux/ath79/patches-5.4/0005-usb-add-more-OF-quirk-properties.patch similarity index 92% rename from target/linux/ath79/patches-4.14/0005-usb-add-more-OF-quirk-properties.patch rename to target/linux/ath79/patches-5.4/0005-usb-add-more-OF-quirk-properties.patch index ec1bc3f7f7..83033a117b 100644 --- a/target/linux/ath79/patches-4.14/0005-usb-add-more-OF-quirk-properties.patch +++ b/target/linux/ath79/patches-5.4/0005-usb-add-more-OF-quirk-properties.patch @@ -10,7 +10,7 @@ Signed-off-by: John Crispin --- a/drivers/usb/host/ehci-platform.c +++ b/drivers/usb/host/ehci-platform.c -@@ -187,6 +187,11 @@ static int ehci_platform_probe(struct pl +@@ -159,6 +159,11 @@ static int ehci_platform_probe(struct pl ehci = hcd_to_ehci(hcd); if (pdata == &ehci_platform_defaults && dev->dev.of_node) { diff --git a/target/linux/ath79/patches-4.14/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch b/target/linux/ath79/patches-5.4/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch similarity index 98% rename from target/linux/ath79/patches-4.14/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch rename to target/linux/ath79/patches-5.4/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch index bd26107af5..ceda511c21 100644 --- a/target/linux/ath79/patches-4.14/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch +++ b/target/linux/ath79/patches-5.4/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch @@ -13,8 +13,8 @@ Signed-off-by: John Crispin --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile -@@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o - +@@ -4,6 +4,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o + obj-$(CONFIG_AL_FIC) += irq-al-fic.o obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o obj-$(CONFIG_ATH79) += irq-ath79-cpu.o +obj-$(CONFIG_ATH79) += irq-ath79-intc.o diff --git a/target/linux/ath79/patches-4.14/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch b/target/linux/ath79/patches-5.4/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch similarity index 91% rename from target/linux/ath79/patches-4.14/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch rename to target/linux/ath79/patches-5.4/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch index b5ad731d06..13117d9a8e 100644 --- a/target/linux/ath79/patches-4.14/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch +++ b/target/linux/ath79/patches-5.4/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch @@ -10,7 +10,7 @@ Signed-off-by: John Crispin --- a/drivers/irqchip/irq-ath79-cpu.c +++ b/drivers/irqchip/irq-ath79-cpu.c -@@ -88,10 +88,3 @@ static int __init ar79_cpu_intc_of_init( +@@ -85,10 +85,3 @@ static int __init ar79_cpu_intc_of_init( } IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc", ar79_cpu_intc_of_init); diff --git a/target/linux/ath79/patches-4.14/0011-MIPS-ath79-select-the-PINCTRL-subsystem.patch b/target/linux/ath79/patches-5.4/0011-MIPS-ath79-select-the-PINCTRL-subsystem.patch similarity index 83% rename from target/linux/ath79/patches-4.14/0011-MIPS-ath79-select-the-PINCTRL-subsystem.patch rename to target/linux/ath79/patches-5.4/0011-MIPS-ath79-select-the-PINCTRL-subsystem.patch index c50a473307..4ac58d10c4 100644 --- a/target/linux/ath79/patches-4.14/0011-MIPS-ath79-select-the-PINCTRL-subsystem.patch +++ b/target/linux/ath79/patches-5.4/0011-MIPS-ath79-select-the-PINCTRL-subsystem.patch @@ -14,11 +14,11 @@ Signed-off-by: John Crispin --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -192,6 +192,7 @@ config ATH79 - select CSRC_R4K - select DMA_NONCOHERENT +@@ -295,6 +295,7 @@ config BCM63XX + select SYS_HAS_EARLY_PRINTK + select SWAP_IO_SPACE select GPIOLIB + select PINCTRL select HAVE_CLK - select COMMON_CLK + select MIPS_L1_CACHE_SHIFT_4 select CLKDEV_LOOKUP diff --git a/target/linux/ath79/patches-4.14/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch b/target/linux/ath79/patches-5.4/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch similarity index 100% rename from target/linux/ath79/patches-4.14/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch rename to target/linux/ath79/patches-5.4/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch diff --git a/target/linux/ath79/patches-4.14/0018-MIPS-pci-ar71xx-convert-to-OF.patch b/target/linux/ath79/patches-5.4/0018-MIPS-pci-ar71xx-convert-to-OF.patch similarity index 91% rename from target/linux/ath79/patches-4.14/0018-MIPS-pci-ar71xx-convert-to-OF.patch rename to target/linux/ath79/patches-5.4/0018-MIPS-pci-ar71xx-convert-to-OF.patch index 91796a12f0..e600a4f0d9 100644 --- a/target/linux/ath79/patches-4.14/0018-MIPS-pci-ar71xx-convert-to-OF.patch +++ b/target/linux/ath79/patches-5.4/0018-MIPS-pci-ar71xx-convert-to-OF.patch @@ -15,7 +15,7 @@ Signed-off-by: John Crispin --- a/arch/mips/pci/pci-ar71xx.c +++ b/arch/mips/pci/pci-ar71xx.c -@@ -18,8 +18,11 @@ +@@ -15,8 +15,11 @@ #include #include #include @@ -27,7 +27,7 @@ Signed-off-by: John Crispin #include #include -@@ -49,12 +52,13 @@ +@@ -46,12 +49,13 @@ #define AR71XX_PCI_IRQ_COUNT 5 struct ar71xx_pci_controller { @@ -42,7 +42,7 @@ Signed-off-by: John Crispin }; /* Byte lane enable bits */ -@@ -228,29 +232,30 @@ static struct pci_ops ar71xx_pci_ops = { +@@ -225,29 +229,30 @@ static struct pci_ops ar71xx_pci_ops = { static void ar71xx_pci_irq_handler(struct irq_desc *desc) { @@ -80,7 +80,7 @@ Signed-off-by: John Crispin } static void ar71xx_pci_irq_unmask(struct irq_data *d) -@@ -261,7 +266,7 @@ static void ar71xx_pci_irq_unmask(struct +@@ -258,7 +263,7 @@ static void ar71xx_pci_irq_unmask(struct u32 t; apc = irq_data_get_irq_chip_data(d); @@ -89,7 +89,7 @@ Signed-off-by: John Crispin t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -@@ -278,7 +283,7 @@ static void ar71xx_pci_irq_mask(struct i +@@ -275,7 +280,7 @@ static void ar71xx_pci_irq_mask(struct i u32 t; apc = irq_data_get_irq_chip_data(d); @@ -98,7 +98,7 @@ Signed-off-by: John Crispin t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -@@ -294,24 +299,31 @@ static struct irq_chip ar71xx_pci_irq_ch +@@ -291,24 +296,31 @@ static struct irq_chip ar71xx_pci_irq_ch .irq_mask_ack = ar71xx_pci_irq_mask, }; @@ -141,7 +141,7 @@ Signed-off-by: John Crispin irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler, apc); } -@@ -328,6 +340,11 @@ static void ar71xx_pci_reset(void) +@@ -325,6 +337,11 @@ static void ar71xx_pci_reset(void) mdelay(100); } @@ -153,7 +153,7 @@ Signed-off-by: John Crispin static int ar71xx_pci_probe(struct platform_device *pdev) { struct ar71xx_pci_controller *apc; -@@ -348,26 +365,6 @@ static int ar71xx_pci_probe(struct platf +@@ -345,26 +362,6 @@ static int ar71xx_pci_probe(struct platf if (apc->irq < 0) return -EINVAL; @@ -180,7 +180,7 @@ Signed-off-by: John Crispin ar71xx_pci_reset(); /* setup COMMAND register */ -@@ -380,9 +377,11 @@ static int ar71xx_pci_probe(struct platf +@@ -377,9 +374,11 @@ static int ar71xx_pci_probe(struct platf ar71xx_pci_irq_init(apc); @@ -192,7 +192,7 @@ Signed-off-by: John Crispin register_pci_controller(&apc->pci_ctrl); -@@ -393,6 +392,7 @@ static struct platform_driver ar71xx_pci +@@ -390,6 +389,7 @@ static struct platform_driver ar71xx_pci .probe = ar71xx_pci_probe, .driver = { .name = "ar71xx-pci", diff --git a/target/linux/ath79/patches-4.14/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch b/target/linux/ath79/patches-5.4/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch similarity index 100% rename from target/linux/ath79/patches-4.14/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch rename to target/linux/ath79/patches-5.4/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch diff --git a/target/linux/ath79/patches-4.14/0020-MIPS-pci-ar724x-convert-to-OF.patch b/target/linux/ath79/patches-5.4/0020-MIPS-pci-ar724x-convert-to-OF.patch similarity index 93% rename from target/linux/ath79/patches-4.14/0020-MIPS-pci-ar724x-convert-to-OF.patch rename to target/linux/ath79/patches-5.4/0020-MIPS-pci-ar724x-convert-to-OF.patch index 936bfd4816..b8a877c63d 100644 --- a/target/linux/ath79/patches-4.14/0020-MIPS-pci-ar724x-convert-to-OF.patch +++ b/target/linux/ath79/patches-5.4/0020-MIPS-pci-ar724x-convert-to-OF.patch @@ -15,7 +15,7 @@ Signed-off-by: John Crispin --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c -@@ -14,8 +14,11 @@ +@@ -11,8 +11,11 @@ #include #include #include @@ -27,7 +27,7 @@ Signed-off-by: John Crispin #define AR724X_PCI_REG_APP 0x00 #define AR724X_PCI_REG_RESET 0x18 -@@ -45,17 +48,20 @@ struct ar724x_pci_controller { +@@ -42,17 +45,20 @@ struct ar724x_pci_controller { void __iomem *crp_base; int irq; @@ -49,7 +49,7 @@ Signed-off-by: John Crispin static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc) { u32 reset; -@@ -231,35 +237,31 @@ static struct pci_ops ar724x_pci_ops = { +@@ -228,35 +234,31 @@ static struct pci_ops ar724x_pci_ops = { static void ar724x_pci_irq_handler(struct irq_desc *desc) { @@ -93,7 +93,7 @@ Signed-off-by: John Crispin case 0: t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); __raw_writel(t | AR724X_PCI_INT_DEV0, -@@ -273,14 +275,12 @@ static void ar724x_pci_irq_mask(struct i +@@ -270,14 +272,12 @@ static void ar724x_pci_irq_mask(struct i { struct ar724x_pci_controller *apc; void __iomem *base; @@ -109,7 +109,7 @@ Signed-off-by: John Crispin case 0: t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); __raw_writel(t & ~AR724X_PCI_INT_DEV0, -@@ -305,26 +305,34 @@ static struct irq_chip ar724x_pci_irq_ch +@@ -302,26 +302,34 @@ static struct irq_chip ar724x_pci_irq_ch .irq_mask_ack = ar724x_pci_irq_mask, }; @@ -154,7 +154,7 @@ Signed-off-by: John Crispin irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler, apc); } -@@ -394,29 +402,11 @@ static int ar724x_pci_probe(struct platf +@@ -391,29 +399,11 @@ static int ar724x_pci_probe(struct platf if (apc->irq < 0) return -EINVAL; @@ -186,7 +186,7 @@ Signed-off-by: John Crispin /* * Do the full PCIE Root Complex Initialization Sequence if the PCIe -@@ -438,10 +428,16 @@ static int ar724x_pci_probe(struct platf +@@ -435,10 +425,16 @@ static int ar724x_pci_probe(struct platf return 0; } diff --git a/target/linux/ath79/patches-4.14/0032-MIPS-ath79-sanitize-symbols.patch b/target/linux/ath79/patches-5.4/0032-MIPS-ath79-sanitize-symbols.patch similarity index 89% rename from target/linux/ath79/patches-4.14/0032-MIPS-ath79-sanitize-symbols.patch rename to target/linux/ath79/patches-5.4/0032-MIPS-ath79-sanitize-symbols.patch index eaefc0bd21..382c5e6dfa 100644 --- a/target/linux/ath79/patches-4.14/0032-MIPS-ath79-sanitize-symbols.patch +++ b/target/linux/ath79/patches-5.4/0032-MIPS-ath79-sanitize-symbols.patch @@ -15,15 +15,15 @@ Signed-off-by: John Crispin --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -203,6 +203,8 @@ config ATH79 +@@ -216,6 +216,8 @@ config ATH79 select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_MIPS16 select SYS_SUPPORTS_ZBOOT_UART_PROM -+ select HW_HAS_PCI ++ select HAVE_PCI + select USB_ARCH_HAS_EHCI select USE_OF + select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM help - Support for the Atheros AR71XX/AR724X/AR913X SoCs. --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -1,48 +1,14 @@ @@ -31,11 +31,11 @@ Signed-off-by: John Crispin if ATH79 -config SOC_AR71XX -- select HW_HAS_PCI +- select HAVE_PCI - def_bool n - -config SOC_AR724X -- select HW_HAS_PCI +- select HAVE_PCI - select PCI_AR724X if PCI - def_bool n - @@ -46,12 +46,12 @@ Signed-off-by: John Crispin - def_bool n - -config SOC_AR934X -- select HW_HAS_PCI +- select HAVE_PCI - select PCI_AR724X if PCI - def_bool n - -config SOC_QCA955X -- select HW_HAS_PCI +- select HAVE_PCI - select PCI_AR724X if PCI +config PCI_AR71XX + bool "PCI support for AR7100 type SoCs" @@ -90,4 +90,4 @@ Signed-off-by: John Crispin +obj-$(CONFIG_PCI_AR71XX) += pci-ar71xx.o obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o - # + obj-$(CONFIG_PCI_XTALK_BRIDGE) += pci-xtalk-bridge.o diff --git a/target/linux/ath79/patches-4.14/0033-spi-ath79-drop-pdata-support.patch b/target/linux/ath79/patches-5.4/0033-spi-ath79-drop-pdata-support.patch similarity index 70% rename from target/linux/ath79/patches-4.14/0033-spi-ath79-drop-pdata-support.patch rename to target/linux/ath79/patches-5.4/0033-spi-ath79-drop-pdata-support.patch index aeb50c9b1c..8fd99bd333 100644 --- a/target/linux/ath79/patches-4.14/0033-spi-ath79-drop-pdata-support.patch +++ b/target/linux/ath79/patches-5.4/0033-spi-ath79-drop-pdata-support.patch @@ -10,22 +10,19 @@ Cc: linux-spi@vger.kernel.org Acked-by: Mark Brown Signed-off-by: John Crispin --- - arch/mips/include/asm/mach-ath79/ath79_spi_platform.h | 19 ------------------- + include/linux/platform_data/spi-ath79.h | 16 ------------------- drivers/spi/spi-ath79.c | 8 -------- 2 files changed, 27 deletions(-) delete mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h ---- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h +--- a/include/linux/platform_data/spi-ath79.h +++ /dev/null -@@ -1,19 +0,0 @@ +@@ -1,16 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller - * - * Copyright (C) 2008-2010 Gabor Juhos -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. - */ - -#ifndef _ATH79_SPI_PLATFORM_H @@ -39,31 +36,32 @@ Signed-off-by: John Crispin -#endif /* _ATH79_SPI_PLATFORM_H */ --- a/drivers/spi/spi-ath79.c +++ b/drivers/spi/spi-ath79.c -@@ -26,7 +26,6 @@ +@@ -19,7 +19,6 @@ + #include + #include #include - - #include --#include +-#include #define DRV_NAME "ath79-spi" -@@ -208,7 +207,6 @@ static int ath79_spi_probe(struct platfo +@@ -138,7 +137,6 @@ static int ath79_spi_probe(struct platfo { struct spi_master *master; struct ath79_spi *sp; - struct ath79_spi_platform_data *pdata; - struct resource *r; unsigned long rate; int ret; -@@ -223,15 +221,9 @@ static int ath79_spi_probe(struct platfo + +@@ -152,16 +150,10 @@ static int ath79_spi_probe(struct platfo master->dev.of_node = pdev->dev.of_node; platform_set_drvdata(pdev, sp); - pdata = dev_get_platdata(&pdev->dev); - + master->use_gpio_descriptors = true; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); - master->setup = ath79_spi_setup; - master->cleanup = ath79_spi_cleanup; + master->setup = spi_bitbang_setup; + master->cleanup = spi_bitbang_cleanup; - if (pdata) { - master->bus_num = pdata->bus_num; - master->num_chipselect = pdata->num_chipselect; diff --git a/target/linux/ath79/patches-4.14/0034-MIPS-ath79-ath9k-exports.patch b/target/linux/ath79/patches-5.4/0034-MIPS-ath79-ath9k-exports.patch similarity index 86% rename from target/linux/ath79/patches-4.14/0034-MIPS-ath79-ath9k-exports.patch rename to target/linux/ath79/patches-5.4/0034-MIPS-ath79-ath9k-exports.patch index 6eec142c74..71acc22210 100644 --- a/target/linux/ath79/patches-4.14/0034-MIPS-ath79-ath9k-exports.patch +++ b/target/linux/ath79/patches-5.4/0034-MIPS-ath79-ath9k-exports.patch @@ -1,6 +1,6 @@ --- a/arch/mips/ath79/common.c +++ b/arch/mips/ath79/common.c -@@ -34,11 +34,13 @@ EXPORT_SYMBOL_GPL(ath79_ddr_freq); +@@ -31,11 +31,13 @@ EXPORT_SYMBOL_GPL(ath79_ddr_freq); enum ath79_soc_type ath79_soc; unsigned int ath79_soc_rev; @@ -17,7 +17,7 @@ --- a/arch/mips/include/asm/mach-ath79/ath79.h +++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -152,6 +152,7 @@ void ath79_ddr_wb_flush(unsigned int reg +@@ -149,6 +149,7 @@ void ath79_ddr_wb_flush(unsigned int reg void ath79_ddr_set_pci_windows(void); extern void __iomem *ath79_pll_base; diff --git a/target/linux/ath79/patches-4.14/0036-GPIO-add-named-gpio-exports.patch b/target/linux/ath79/patches-5.4/0036-GPIO-add-named-gpio-exports.patch similarity index 92% rename from target/linux/ath79/patches-4.14/0036-GPIO-add-named-gpio-exports.patch rename to target/linux/ath79/patches-5.4/0036-GPIO-add-named-gpio-exports.patch index 61ed9ea784..d4ea379159 100644 --- a/target/linux/ath79/patches-4.14/0036-GPIO-add-named-gpio-exports.patch +++ b/target/linux/ath79/patches-5.4/0036-GPIO-add-named-gpio-exports.patch @@ -13,7 +13,7 @@ Signed-off-by: John Crispin --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c -@@ -23,6 +23,8 @@ +@@ -19,6 +19,8 @@ #include #include #include @@ -21,9 +21,9 @@ Signed-off-by: John Crispin +#include #include "gpiolib.h" - -@@ -513,3 +515,68 @@ void of_gpiochip_remove(struct gpio_chip - gpiochip_remove_pin_ranges(chip); + #include "gpiolib-of.h" +@@ -915,3 +917,68 @@ void of_gpiochip_remove(struct gpio_chip + { of_node_put(chip->of_node); } + @@ -93,7 +93,7 @@ Signed-off-by: John Crispin +module_platform_driver(gpio_export_driver); --- a/drivers/gpio/gpiolib-sysfs.c +++ b/drivers/gpio/gpiolib-sysfs.c -@@ -553,7 +553,7 @@ static struct class gpio_class = { +@@ -563,7 +563,7 @@ static struct class gpio_class = { * * Returns zero on success, else an error. */ @@ -102,7 +102,7 @@ Signed-off-by: John Crispin { struct gpio_chip *chip; struct gpio_device *gdev; -@@ -615,6 +615,8 @@ int gpiod_export(struct gpio_desc *desc, +@@ -625,6 +625,8 @@ int gpiod_export(struct gpio_desc *desc, offset = gpio_chip_hwgpio(desc); if (chip->names && chip->names[offset]) ioname = chip->names[offset]; @@ -111,7 +111,7 @@ Signed-off-by: John Crispin dev = device_create_with_groups(&gpio_class, &gdev->dev, MKDEV(0, 0), data, gpio_groups, -@@ -636,6 +638,12 @@ err_unlock: +@@ -646,6 +648,12 @@ err_unlock: gpiod_dbg(desc, "%s: status %d\n", __func__, status); return status; } @@ -141,7 +141,7 @@ Signed-off-by: John Crispin { --- a/include/linux/gpio/consumer.h +++ b/include/linux/gpio/consumer.h -@@ -451,6 +451,7 @@ struct gpio_desc *devm_fwnode_get_gpiod_ +@@ -668,6 +668,7 @@ static inline void devm_acpi_dev_remove_ #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS) @@ -149,7 +149,7 @@ Signed-off-by: John Crispin int gpiod_export(struct gpio_desc *desc, bool direction_may_change); int gpiod_export_link(struct device *dev, const char *name, struct gpio_desc *desc); -@@ -458,6 +459,13 @@ void gpiod_unexport(struct gpio_desc *de +@@ -675,6 +676,13 @@ void gpiod_unexport(struct gpio_desc *de #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ diff --git a/target/linux/ath79/patches-4.14/0036-MIPS-ath79-remove-irq-code-from-pci.patch b/target/linux/ath79/patches-5.4/0036-MIPS-ath79-remove-irq-code-from-pci.patch similarity index 94% rename from target/linux/ath79/patches-4.14/0036-MIPS-ath79-remove-irq-code-from-pci.patch rename to target/linux/ath79/patches-5.4/0036-MIPS-ath79-remove-irq-code-from-pci.patch index 460c4580ee..80fcd0a7f5 100644 --- a/target/linux/ath79/patches-4.14/0036-MIPS-ath79-remove-irq-code-from-pci.patch +++ b/target/linux/ath79/patches-5.4/0036-MIPS-ath79-remove-irq-code-from-pci.patch @@ -1,6 +1,6 @@ --- a/arch/mips/pci/pci-ar71xx.c +++ b/arch/mips/pci/pci-ar71xx.c -@@ -54,11 +54,9 @@ +@@ -51,11 +51,9 @@ struct ar71xx_pci_controller { struct device_node *np; void __iomem *cfg_base; @@ -12,7 +12,7 @@ }; /* Byte lane enable bits */ -@@ -230,104 +228,6 @@ static struct pci_ops ar71xx_pci_ops = { +@@ -227,104 +225,6 @@ static struct pci_ops ar71xx_pci_ops = { .write = ar71xx_pci_write_config, }; @@ -117,7 +117,7 @@ static void ar71xx_pci_reset(void) { ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); -@@ -361,10 +261,6 @@ static int ar71xx_pci_probe(struct platf +@@ -358,10 +258,6 @@ static int ar71xx_pci_probe(struct platf if (IS_ERR(apc->cfg_base)) return PTR_ERR(apc->cfg_base); @@ -128,7 +128,7 @@ ar71xx_pci_reset(); /* setup COMMAND register */ -@@ -375,8 +271,6 @@ static int ar71xx_pci_probe(struct platf +@@ -372,8 +268,6 @@ static int ar71xx_pci_probe(struct platf /* clear bus errors */ ar71xx_pci_check_error(apc, 1); diff --git a/target/linux/ath79/patches-4.14/0037-missing-registers.patch b/target/linux/ath79/patches-5.4/0037-missing-registers.patch similarity index 96% rename from target/linux/ath79/patches-4.14/0037-missing-registers.patch rename to target/linux/ath79/patches-5.4/0037-missing-registers.patch index 9fde3d39df..9067e4ca7b 100644 --- a/target/linux/ath79/patches-4.14/0037-missing-registers.patch +++ b/target/linux/ath79/patches-5.4/0037-missing-registers.patch @@ -8,7 +8,7 @@ Date: Fri Aug 10 23:24:47 2018 +0200 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1229,6 +1229,10 @@ +@@ -1226,6 +1226,10 @@ #define AR934X_ETH_CFG_RDV_DELAY BIT(16) #define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 diff --git a/target/linux/ath79/patches-4.14/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch b/target/linux/ath79/patches-5.4/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch similarity index 98% rename from target/linux/ath79/patches-4.14/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch rename to target/linux/ath79/patches-5.4/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch index dc0af2fe9c..bc09062dc5 100644 --- a/target/linux/ath79/patches-4.14/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch +++ b/target/linux/ath79/patches-5.4/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch @@ -16,7 +16,7 @@ Signed-off-by: David Bauer --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1249,7 +1249,12 @@ +@@ -1246,7 +1246,12 @@ */ #define QCA955X_GMAC_REG_ETH_CFG 0x00 @@ -29,7 +29,7 @@ Signed-off-by: David Bauer #define QCA955X_ETH_CFG_RGMII_EN BIT(0) #define QCA955X_ETH_CFG_MII_GE0 BIT(1) -@@ -1271,9 +1276,58 @@ +@@ -1268,9 +1273,58 @@ #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 diff --git a/target/linux/ath79/patches-5.4/0039-MIPS-ath79-export-UART1-reference-clock.patch b/target/linux/ath79/patches-5.4/0039-MIPS-ath79-export-UART1-reference-clock.patch new file mode 100644 index 0000000000..edf888c7e7 --- /dev/null +++ b/target/linux/ath79/patches-5.4/0039-MIPS-ath79-export-UART1-reference-clock.patch @@ -0,0 +1,52 @@ +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -40,6 +40,7 @@ static const char * const clk_names[ATH7 + [ATH79_CLK_AHB] = "ahb", + [ATH79_CLK_REF] = "ref", + [ATH79_CLK_MDIO] = "mdio", ++ [ATH79_CLK_UART1] = "uart1", + }; + + static const char * __init ath79_clk_name(int type) +@@ -344,6 +345,9 @@ static void __init ar934x_clocks_init(vo + if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) + ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000); + ++ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL) ++ ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000); ++ + iounmap(dpll_base); + } + +@@ -649,6 +653,9 @@ static void __init ath79_clocks_init_dt( + if (!clks[ATH79_CLK_MDIO]) + clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF]; + ++ if (!clks[ATH79_CLK_UART1]) ++ clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF]; ++ + if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { + pr_err("%pOF: could not register clk provider\n", np); + goto err_iounmap; +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -348,6 +348,7 @@ + #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + + #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) ++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL BIT(7) + + #define QCA953X_PLL_CPU_CONFIG_REG 0x00 + #define QCA953X_PLL_DDR_CONFIG_REG 0x04 +--- a/include/dt-bindings/clock/ath79-clk.h ++++ b/include/dt-bindings/clock/ath79-clk.h +@@ -11,7 +11,8 @@ + #define ATH79_CLK_AHB 2 + #define ATH79_CLK_REF 3 + #define ATH79_CLK_MDIO 4 ++#define ATH79_CLK_UART1 5 + +-#define ATH79_CLK_END 5 ++#define ATH79_CLK_END 6 + + #endif /* __DT_BINDINGS_ATH79_CLK_H */ diff --git a/target/linux/ath79/patches-4.14/004-register_gpio_driver_earlier.patch b/target/linux/ath79/patches-5.4/004-register_gpio_driver_earlier.patch similarity index 82% rename from target/linux/ath79/patches-4.14/004-register_gpio_driver_earlier.patch rename to target/linux/ath79/patches-5.4/004-register_gpio_driver_earlier.patch index cc30e2d91e..fa4b05f724 100644 --- a/target/linux/ath79/patches-4.14/004-register_gpio_driver_earlier.patch +++ b/target/linux/ath79/patches-5.4/004-register_gpio_driver_earlier.patch @@ -3,8 +3,8 @@ from mach files succeed. --- a/drivers/gpio/gpio-ath79.c +++ b/drivers/gpio/gpio-ath79.c -@@ -322,7 +322,11 @@ static struct platform_driver ath79_gpio - .remove = ath79_gpio_remove, +@@ -310,7 +310,11 @@ static struct platform_driver ath79_gpio + .probe = ath79_gpio_probe, }; -module_platform_driver(ath79_gpio_driver); diff --git a/target/linux/ath79/patches-5.4/0050-spi-ath79-remove-spi-master-setup-and-cleanup-assign.patch b/target/linux/ath79/patches-5.4/0050-spi-ath79-remove-spi-master-setup-and-cleanup-assign.patch new file mode 100644 index 0000000000..a57ac24f29 --- /dev/null +++ b/target/linux/ath79/patches-5.4/0050-spi-ath79-remove-spi-master-setup-and-cleanup-assign.patch @@ -0,0 +1,28 @@ +From b142b1beb199f62d47370c98a3dd8e13f792e9c0 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Thu, 27 Feb 2020 23:03:20 +0100 +Subject: [PATCH] spi: ath79: remove spi-master setup and cleanup assignment + +This removes the assignment of setup and cleanup functions for the ath79 +target. Assigning the setup-method will lead to 'setup_transfer' not +being assigned in spi_bitbang_init. + +Also drop the redundant cleanup assignment, as this also happens in +spi_bitbang_init. + +Signed-off-by: David Bauer +--- + drivers/spi/spi-ath79.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -152,8 +152,6 @@ static int ath79_spi_probe(struct platfo + + master->use_gpio_descriptors = true; + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); +- master->setup = spi_bitbang_setup; +- master->cleanup = spi_bitbang_cleanup; + + sp->bitbang.master = master; + sp->bitbang.chipselect = ath79_spi_chipselect; diff --git a/target/linux/ath79/patches-5.4/0051-spi-add-driver-for-ar934x-spi-controller.patch b/target/linux/ath79/patches-5.4/0051-spi-add-driver-for-ar934x-spi-controller.patch new file mode 100644 index 0000000000..e314fa2cd3 --- /dev/null +++ b/target/linux/ath79/patches-5.4/0051-spi-add-driver-for-ar934x-spi-controller.patch @@ -0,0 +1,283 @@ +From 7e161c423a232ef7ddf6c11b09ebe471dd5a23cf Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Wed, 5 Feb 2020 18:25:37 +0800 +Subject: [PATCH v4 1/2] spi: add driver for ar934x spi controller + +This patch adds driver for SPI controller found in Qualcomm Atheros +AR934x/QCA95xx SoCs. +This controller is a superset of the already supported qca,ar7100-spi. +Besides the bit-bang mode in spi-ath79.c, this new controller added +a new "shift register" mode, allowing faster spi operations. + +Signed-off-by: Chuanhong Guo +--- + drivers/spi/Kconfig | 7 ++ + drivers/spi/Makefile | 1 + + drivers/spi/spi-ar934x.c | 235 +++++++++++++++++++++++++++++++++++++++ + 3 files changed, 243 insertions(+) + create mode 100644 drivers/spi/spi-ar934x.c + +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -62,6 +62,13 @@ config SPI_ALTERA + help + This is the driver for the Altera SPI Controller. + ++config SPI_AR934X ++ tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver" ++ depends on ATH79 || COMPILE_TEST ++ help ++ This enables support for the SPI controller present on the ++ Qualcomm Atheros AR934X/QCA95XX SoCs. ++ + config SPI_ATH79 + tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver" + depends on ATH79 || COMPILE_TEST +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi- + + # SPI master controller drivers (bus) + obj-$(CONFIG_SPI_ALTERA) += spi-altera.o ++obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o + obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o + obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o + obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o +--- /dev/null ++++ b/drivers/spi/spi-ar934x.c +@@ -0,0 +1,235 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// ++// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs ++// ++// Copyright (C) 2020 Chuanhong Guo ++// ++// Based on spi-mt7621.c: ++// Copyright (C) 2011 Sergiy ++// Copyright (C) 2011-2013 Gabor Juhos ++// Copyright (C) 2014-2015 Felix Fietkau ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "spi-ar934x" ++ ++#define AR934X_SPI_REG_FS 0x00 ++#define AR934X_SPI_ENABLE BIT(0) ++ ++#define AR934X_SPI_REG_IOC 0x08 ++#define AR934X_SPI_IOC_INITVAL 0x70000 ++ ++#define AR934X_SPI_REG_CTRL 0x04 ++#define AR934X_SPI_CLK_MASK GENMASK(5, 0) ++ ++#define AR934X_SPI_DATAOUT 0x10 ++ ++#define AR934X_SPI_REG_SHIFT_CTRL 0x14 ++#define AR934X_SPI_SHIFT_EN BIT(31) ++#define AR934X_SPI_SHIFT_CS(n) BIT(28 + (n)) ++#define AR934X_SPI_SHIFT_TERM 26 ++#define AR934X_SPI_SHIFT_VAL(cs, term, count) \ ++ (AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) | \ ++ (term) << AR934X_SPI_SHIFT_TERM | (count)) ++ ++#define AR934X_SPI_DATAIN 0x18 ++ ++struct ar934x_spi { ++ struct spi_controller *ctlr; ++ void __iomem *base; ++ struct clk *clk; ++ unsigned int clk_freq; ++}; ++ ++static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq) ++{ ++ int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1; ++ ++ if (div < 0) ++ return 0; ++ else if (div > AR934X_SPI_CLK_MASK) ++ return -EINVAL; ++ else ++ return div; ++} ++ ++static int ar934x_spi_setup(struct spi_device *spi) ++{ ++ struct ar934x_spi *sp = spi_controller_get_devdata(spi->master); ++ ++ if ((spi->max_speed_hz == 0) || ++ (spi->max_speed_hz > (sp->clk_freq / 2))) { ++ spi->max_speed_hz = sp->clk_freq / 2; ++ } else if (spi->max_speed_hz < (sp->clk_freq / 128)) { ++ dev_err(&spi->dev, "spi clock is too low\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int ar934x_spi_transfer_one_message(struct spi_controller *master, ++ struct spi_message *m) ++{ ++ struct ar934x_spi *sp = spi_controller_get_devdata(master); ++ struct spi_transfer *t = NULL; ++ struct spi_device *spi = m->spi; ++ unsigned long trx_done, trx_cur; ++ int stat = 0; ++ u8 term = 0; ++ int div, i; ++ u32 reg; ++ const u8 *tx_buf; ++ u8 *buf; ++ ++ m->actual_length = 0; ++ list_for_each_entry(t, &m->transfers, transfer_list) { ++ if (t->speed_hz) ++ div = ar934x_spi_clk_div(sp, t->speed_hz); ++ else ++ div = ar934x_spi_clk_div(sp, spi->max_speed_hz); ++ if (div < 0) { ++ stat = -EIO; ++ goto msg_done; ++ } ++ ++ reg = ioread32(sp->base + AR934X_SPI_REG_CTRL); ++ reg &= ~AR934X_SPI_CLK_MASK; ++ reg |= div; ++ iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL); ++ iowrite32(0, sp->base + AR934X_SPI_DATAOUT); ++ ++ for (trx_done = 0; trx_done < t->len; trx_done += 4) { ++ trx_cur = t->len - trx_done; ++ if (trx_cur > 4) ++ trx_cur = 4; ++ else if (list_is_last(&t->transfer_list, &m->transfers)) ++ term = 1; ++ ++ if (t->tx_buf) { ++ tx_buf = t->tx_buf + trx_done; ++ reg = tx_buf[0]; ++ for (i = 1; i < trx_cur; i++) ++ reg = reg << 8 | tx_buf[i]; ++ iowrite32(reg, sp->base + AR934X_SPI_DATAOUT); ++ } ++ ++ reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term, ++ trx_cur * 8); ++ iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL); ++ stat = readl_poll_timeout( ++ sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg, ++ !(reg & AR934X_SPI_SHIFT_EN), 0, 5); ++ if (stat < 0) ++ goto msg_done; ++ ++ if (t->rx_buf) { ++ reg = ioread32(sp->base + AR934X_SPI_DATAIN); ++ buf = t->rx_buf + trx_done; ++ for (i = 0; i < trx_cur; i++) { ++ buf[trx_cur - i - 1] = reg & 0xff; ++ reg >>= 8; ++ } ++ } ++ } ++ m->actual_length += t->len; ++ } ++ ++msg_done: ++ m->status = stat; ++ spi_finalize_current_message(master); ++ ++ return 0; ++} ++ ++static const struct of_device_id ar934x_spi_match[] = { ++ { .compatible = "qca,ar934x-spi" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ar934x_spi_match); ++ ++static int ar934x_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_controller *ctlr; ++ struct ar934x_spi *sp; ++ void __iomem *base; ++ struct clk *clk; ++ int ret; ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ clk = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(clk)) { ++ dev_err(&pdev->dev, "failed to get clock\n"); ++ return PTR_ERR(clk); ++ } ++ ++ ret = clk_prepare_enable(clk); ++ if (ret) ++ return ret; ++ ++ ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp)); ++ if (!ctlr) { ++ dev_info(&pdev->dev, "failed to allocate spi controller\n"); ++ return -ENOMEM; ++ } ++ ++ /* disable flash mapping and expose spi controller registers */ ++ iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS); ++ /* restore pins to default state: CSn=1 DO=CLK=0 */ ++ iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC); ++ ++ ctlr->mode_bits = SPI_LSB_FIRST; ++ ctlr->setup = ar934x_spi_setup; ++ ctlr->transfer_one_message = ar934x_spi_transfer_one_message; ++ ctlr->bits_per_word_mask = SPI_BPW_MASK(8); ++ ctlr->dev.of_node = pdev->dev.of_node; ++ ctlr->num_chipselect = 3; ++ ++ dev_set_drvdata(&pdev->dev, ctlr); ++ ++ sp = spi_controller_get_devdata(ctlr); ++ sp->base = base; ++ sp->clk = clk; ++ sp->clk_freq = clk_get_rate(clk); ++ sp->ctlr = ctlr; ++ ++ return devm_spi_register_controller(&pdev->dev, ctlr); ++} ++ ++static int ar934x_spi_remove(struct platform_device *pdev) ++{ ++ struct spi_controller *ctlr; ++ struct ar934x_spi *sp; ++ ++ ctlr = dev_get_drvdata(&pdev->dev); ++ sp = spi_controller_get_devdata(ctlr); ++ ++ clk_disable_unprepare(sp->clk); ++ ++ return 0; ++} ++ ++static struct platform_driver ar934x_spi_driver = { ++ .driver = { ++ .name = DRIVER_NAME, ++ .of_match_table = ar934x_spi_match, ++ }, ++ .probe = ar934x_spi_probe, ++ .remove = ar934x_spi_remove, ++}; ++ ++module_platform_driver(ar934x_spi_driver); ++ ++MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx"); ++MODULE_AUTHOR("Chuanhong Guo "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/target/linux/ath79/patches-5.4/0060-serial-ar933x_uart-set-UART_CS_-RX-TX-_READY_ORIDE.patch b/target/linux/ath79/patches-5.4/0060-serial-ar933x_uart-set-UART_CS_-RX-TX-_READY_ORIDE.patch new file mode 100644 index 0000000000..30828d693c --- /dev/null +++ b/target/linux/ath79/patches-5.4/0060-serial-ar933x_uart-set-UART_CS_-RX-TX-_READY_ORIDE.patch @@ -0,0 +1,64 @@ +From patchwork Fri Feb 7 09:53:35 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Daniel Golle +X-Patchwork-Id: 1190470 +Date: Fri, 7 Feb 2020 11:53:35 +0200 +From: Daniel Golle +To: linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org +Cc: Greg Kroah-Hartman , + Jiri Slaby , + Chuanhong Guo , + Eitan Cohen , + Ori Gofen +Subject: [PATCH] serial: ar933x_uart: set UART_CS_{RX,TX}_READY_ORIDE +Message-ID: <20200207095335.GA179836@makrotopia.org> +MIME-Version: 1.0 +Content-Disposition: inline +Sender: linux-kernel-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-kernel@vger.kernel.org + +On AR934x this UART is usually not initialized by the bootloader +as it is only used as a secondary serial port while the primary +UART is a newly introduced NS16550-compatible. +In order to make use of the ar933x-uart on AR934x without RTS/CTS +hardware flow control, one needs to set the +UART_CS_{RX,TX}_READY_ORIDE bits as other than on AR933x where this +UART is used as primary/console, the bootloader on AR934x typically +doesn't set those bits. +Setting them explicitely on AR933x should not do any harm, so just +set them unconditionally. + +Tested-by: Chuanhong Guo +Signed-off-by: Daniel Golle +--- + drivers/tty/serial/ar933x_uart.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/tty/serial/ar933x_uart.c ++++ b/drivers/tty/serial/ar933x_uart.c +@@ -290,6 +290,10 @@ static void ar933x_uart_set_termios(stru + ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, + AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE); + ++ /* enable RX and TX ready overide */ ++ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, ++ AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE); ++ + /* reenable the UART */ + ar933x_uart_rmw(up, AR933X_UART_CS_REG, + AR933X_UART_CS_IF_MODE_M << AR933X_UART_CS_IF_MODE_S, +@@ -424,6 +428,10 @@ static int ar933x_uart_startup(struct ua + + /* enable RX and TX ready overide */ + ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, ++ AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE); ++ ++ /* enable RX and TX ready overide */ ++ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, + AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE); + + /* Enable RX interrupts */ diff --git a/target/linux/ath79/patches-5.4/0061-tty-serial-ar933x-uart-rs485-gpio.patch b/target/linux/ath79/patches-5.4/0061-tty-serial-ar933x-uart-rs485-gpio.patch new file mode 100644 index 0000000000..e27c0854f5 --- /dev/null +++ b/target/linux/ath79/patches-5.4/0061-tty-serial-ar933x-uart-rs485-gpio.patch @@ -0,0 +1,267 @@ +From patchwork Fri Feb 21 21:23:31 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Daniel Golle +X-Patchwork-Id: 1198835 +Date: Fri, 21 Feb 2020 22:23:31 +0100 +From: Daniel Golle +To: linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org +Cc: Greg Kroah-Hartman , + Jiri Slaby , Petr =?utf-8?q?=C5=A0tetiar?= , + Chuanhong Guo , Piotr Dymacz +Subject: [PATCH v2] serial: ar933x_uart: add RS485 support +Message-ID: <20200221212331.GA21467@makrotopia.org> +MIME-Version: 1.0 +Content-Disposition: inline +Sender: linux-kernel-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-kernel@vger.kernel.org + +Emulate half-duplex operation and use mctrl_gpio to add support for +RS485 tranceiver with transmit/receive switch hooked to RTS GPIO line. +This is needed to make use of the RS485 port found on Teltonika RUT955. + +Signed-off-by: Daniel Golle +--- +v2: use bool to indicate ongoing half-duplex send, use it afterwards + to decide whether we've just been in a send operation. + + drivers/tty/serial/Kconfig | 1 + + drivers/tty/serial/ar933x_uart.c | 113 +++++++++++++++++++++++++++++-- + 2 files changed, 108 insertions(+), 6 deletions(-) + +--- a/drivers/tty/serial/Kconfig ++++ b/drivers/tty/serial/Kconfig +@@ -1279,6 +1279,7 @@ config SERIAL_AR933X + tristate "AR933X serial port support" + depends on HAVE_CLK && ATH79 + select SERIAL_CORE ++ select SERIAL_MCTRL_GPIO if GPIOLIB + help + If you have an Atheros AR933X SOC based board and want to use the + built-in UART of the SoC, say Y to this option. +--- a/drivers/tty/serial/ar933x_uart.c ++++ b/drivers/tty/serial/ar933x_uart.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -29,6 +30,8 @@ + + #include + ++#include "serial_mctrl_gpio.h" ++ + #define DRIVER_NAME "ar933x-uart" + + #define AR933X_UART_MAX_SCALE 0xff +@@ -47,6 +50,8 @@ struct ar933x_uart_port { + unsigned int min_baud; + unsigned int max_baud; + struct clk *clk; ++ struct mctrl_gpios *gpios; ++ struct gpio_desc *rts_gpiod; + }; + + static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up, +@@ -100,6 +105,18 @@ static inline void ar933x_uart_stop_tx_i + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); + } + ++static inline void ar933x_uart_start_rx_interrupt(struct ar933x_uart_port *up) ++{ ++ up->ier |= AR933X_UART_INT_RX_VALID; ++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); ++} ++ ++static inline void ar933x_uart_stop_rx_interrupt(struct ar933x_uart_port *up) ++{ ++ up->ier &= ~AR933X_UART_INT_RX_VALID; ++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); ++} ++ + static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch) + { + unsigned int rdata; +@@ -125,11 +142,21 @@ static unsigned int ar933x_uart_tx_empty + + static unsigned int ar933x_uart_get_mctrl(struct uart_port *port) + { +- return TIOCM_CAR; ++ struct ar933x_uart_port *up = ++ container_of(port, struct ar933x_uart_port, port); ++ int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; ++ ++ mctrl_gpio_get(up->gpios, &ret); ++ ++ return ret; + } + + static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) + { ++ struct ar933x_uart_port *up = ++ container_of(port, struct ar933x_uart_port, port); ++ ++ mctrl_gpio_set(up->gpios, mctrl); + } + + static void ar933x_uart_start_tx(struct uart_port *port) +@@ -140,6 +167,37 @@ static void ar933x_uart_start_tx(struct + ar933x_uart_start_tx_interrupt(up); + } + ++static void ar933x_uart_wait_tx_complete(struct ar933x_uart_port *up) ++{ ++ unsigned int status; ++ unsigned int timeout = 60000; ++ ++ /* Wait up to 60ms for the character(s) to be sent. */ ++ do { ++ status = ar933x_uart_read(up, AR933X_UART_CS_REG); ++ if (--timeout == 0) ++ break; ++ udelay(1); ++ } while (status & AR933X_UART_CS_TX_BUSY); ++ ++ if (timeout == 0) ++ dev_err(up->port.dev, "waiting for TX timed out\n"); ++} ++ ++static void ar933x_uart_rx_flush(struct ar933x_uart_port *up) ++{ ++ unsigned int status; ++ ++ /* clear RX_VALID interrupt */ ++ ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_RX_VALID); ++ ++ /* remove characters from the RX FIFO */ ++ do { ++ ar933x_uart_write(up, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR); ++ status = ar933x_uart_read(up, AR933X_UART_DATA_REG); ++ } while (status & AR933X_UART_DATA_RX_CSR); ++} ++ + static void ar933x_uart_stop_tx(struct uart_port *port) + { + struct ar933x_uart_port *up = +@@ -153,8 +211,7 @@ static void ar933x_uart_stop_rx(struct u + struct ar933x_uart_port *up = + container_of(port, struct ar933x_uart_port, port); + +- up->ier &= ~AR933X_UART_INT_RX_VALID; +- ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); ++ ar933x_uart_stop_rx_interrupt(up); + } + + static void ar933x_uart_break_ctl(struct uart_port *port, int break_state) +@@ -340,11 +397,20 @@ static void ar933x_uart_rx_chars(struct + static void ar933x_uart_tx_chars(struct ar933x_uart_port *up) + { + struct circ_buf *xmit = &up->port.state->xmit; ++ struct serial_rs485 *rs485conf = &up->port.rs485; + int count; ++ bool half_duplex_send = false; + + if (uart_tx_stopped(&up->port)) + return; + ++ if ((rs485conf->flags & SER_RS485_ENABLED) && ++ (up->port.x_char || !uart_circ_empty(xmit))) { ++ ar933x_uart_stop_rx_interrupt(up); ++ gpiod_set_value(up->rts_gpiod, !!(rs485conf->flags & SER_RS485_RTS_ON_SEND)); ++ half_duplex_send = true; ++ } ++ + count = up->port.fifosize; + do { + unsigned int rdata; +@@ -372,8 +438,14 @@ static void ar933x_uart_tx_chars(struct + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + +- if (!uart_circ_empty(xmit)) ++ if (!uart_circ_empty(xmit)) { + ar933x_uart_start_tx_interrupt(up); ++ } else if (half_duplex_send) { ++ ar933x_uart_wait_tx_complete(up); ++ ar933x_uart_rx_flush(up); ++ ar933x_uart_start_rx_interrupt(up); ++ gpiod_set_value(up->rts_gpiod, !!(rs485conf->flags & SER_RS485_RTS_AFTER_SEND)); ++ } + } + + static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id) +@@ -435,8 +507,7 @@ static int ar933x_uart_startup(struct ua + AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE); + + /* Enable RX interrupts */ +- up->ier = AR933X_UART_INT_RX_VALID; +- ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); ++ ar933x_uart_start_rx_interrupt(up); + + spin_unlock_irqrestore(&up->port.lock, flags); + +@@ -519,6 +590,21 @@ static const struct uart_ops ar933x_uart + .verify_port = ar933x_uart_verify_port, + }; + ++static int ar933x_config_rs485(struct uart_port *port, ++ struct serial_rs485 *rs485conf) ++{ ++ struct ar933x_uart_port *up = ++ container_of(port, struct ar933x_uart_port, port); ++ ++ if ((rs485conf->flags & SER_RS485_ENABLED) && ++ !up->rts_gpiod) { ++ dev_err(port->dev, "RS485 needs rts-gpio\n"); ++ return 1; ++ } ++ port->rs485 = *rs485conf; ++ return 0; ++} ++ + #ifdef CONFIG_SERIAL_AR933X_CONSOLE + static struct ar933x_uart_port * + ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS]; +@@ -688,6 +774,8 @@ static int ar933x_uart_probe(struct plat + goto err_disable_clk; + } + ++ uart_get_rs485_mode(&pdev->dev, &port->rs485); ++ + port->mapbase = mem_res->start; + port->line = id; + port->irq = irq_res->start; +@@ -698,6 +786,7 @@ static int ar933x_uart_probe(struct plat + port->regshift = 2; + port->fifosize = AR933X_UART_FIFO_SIZE; + port->ops = &ar933x_uart_ops; ++ port->rs485_config = ar933x_config_rs485; + + baud = ar933x_uart_get_baud(port->uartclk, AR933X_UART_MAX_SCALE, 1); + up->min_baud = max_t(unsigned int, baud, AR933X_UART_MIN_BAUD); +@@ -705,6 +794,18 @@ static int ar933x_uart_probe(struct plat + baud = ar933x_uart_get_baud(port->uartclk, 0, AR933X_UART_MAX_STEP); + up->max_baud = min_t(unsigned int, baud, AR933X_UART_MAX_BAUD); + ++ up->gpios = mctrl_gpio_init(port, 0); ++ if (IS_ERR(up->gpios) && PTR_ERR(up->gpios) != -ENOSYS) ++ return PTR_ERR(up->gpios); ++ ++ up->rts_gpiod = mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS); ++ ++ if ((port->rs485.flags & SER_RS485_ENABLED) && ++ !up->rts_gpiod) { ++ dev_err(&pdev->dev, "lacking rts-gpio, disabling RS485\n"); ++ port->rs485.flags &= ~SER_RS485_ENABLED; ++ } ++ + #ifdef CONFIG_SERIAL_AR933X_CONSOLE + ar933x_console_ports[up->port.line] = up; + #endif diff --git a/target/linux/ath79/patches-5.4/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch b/target/linux/ath79/patches-5.4/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch new file mode 100644 index 0000000000..13955c62a2 --- /dev/null +++ b/target/linux/ath79/patches-5.4/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch @@ -0,0 +1,130 @@ +From: David Bauer +Date: Sat, 11 Apr 2020 14:03:12 +0200 +Subject: MIPS: pci-ar724x: add QCA9550 reset sequence + +The QCA9550 family of SoCs have a slightly different reset +sequence compared to older chips. + +Normally the bootloader performs this sequence, however +some bootloader implementation expect the operating system +to clear the reset. + +Also get the resets from OF to support handling of the second +PCIe root-complex on the QCA9558. + +Signed-off-by: David Bauer + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -391,6 +391,7 @@ + #define QCA955X_PLL_CPU_CONFIG_REG 0x00 + #define QCA955X_PLL_DDR_CONFIG_REG 0x04 + #define QCA955X_PLL_CLK_CTRL_REG 0x08 ++#define QCA955X_PLL_PCIE_CONFIG_REG 0x0c + #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 + #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + #define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c +@@ -476,6 +477,9 @@ + #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) + #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define QCA955X_PLL_PCIE_CONFIG_PLL_PWD BIT(30) ++#define QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS BIT(16) ++ + #define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5) + #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6) + #define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7) +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -8,6 +8,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -55,6 +56,9 @@ struct ar724x_pci_controller { + struct irq_domain *domain; + struct resource io_res; + struct resource mem_res; ++ ++ struct reset_control *hc_reset; ++ struct reset_control *phy_reset; + }; + + static struct irq_chip ar724x_pci_irq_chip; +@@ -340,18 +344,30 @@ static void ar724x_pci_hw_init(struct ar + int wait = 0; + + /* deassert PCIe host controller and PCIe PHY reset */ +- ath79_device_reset_clear(AR724X_RESET_PCIE); +- ath79_device_reset_clear(AR724X_RESET_PCIE_PHY); ++ reset_control_deassert(apc->hc_reset); ++ reset_control_deassert(apc->phy_reset); + +- /* remove the reset of the PCIE PLL */ +- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); +- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET; +- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); +- +- /* deassert bypass for the PCIE PLL */ +- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); +- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS; +- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); ++ if (of_device_is_compatible(apc->np, "qcom,qca9550-pci")) { ++ /* remove the reset of the PCIE PLL */ ++ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG); ++ ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_PWD; ++ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl); ++ ++ /* deassert bypass for the PCIE PLL */ ++ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG); ++ ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS; ++ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl); ++ } else { ++ /* remove the reset of the PCIE PLL */ ++ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); ++ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET; ++ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); ++ ++ /* deassert bypass for the PCIE PLL */ ++ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); ++ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS; ++ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); ++ } + + /* set PCIE Application Control to ready */ + app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP); +@@ -399,6 +415,14 @@ static int ar724x_pci_probe(struct platf + if (apc->irq < 0) + return -EINVAL; + ++ apc->hc_reset = devm_reset_control_get_exclusive(&pdev->dev, "hc"); ++ if (IS_ERR(apc->hc_reset)) ++ return PTR_ERR(apc->hc_reset); ++ ++ apc->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, "phy"); ++ if (IS_ERR(apc->phy_reset)) ++ return PTR_ERR(apc->phy_reset); ++ + apc->np = pdev->dev.of_node; + apc->pci_controller.pci_ops = &ar724x_pci_ops; + apc->pci_controller.io_resource = &apc->io_res; +@@ -409,7 +433,7 @@ static int ar724x_pci_probe(struct platf + * Do the full PCIE Root Complex Initialization Sequence if the PCIe + * host controller is in reset. + */ +- if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE) ++ if (reset_control_status(apc->hc_reset)) + ar724x_pci_hw_init(apc); + + apc->link_up = ar724x_pci_check_link(apc); +@@ -427,6 +451,7 @@ static int ar724x_pci_probe(struct platf + + static const struct of_device_id ar724x_pci_ids[] = { + { .compatible = "qcom,ar7240-pci" }, ++ { .compatible = "qcom,qca9550-pci" }, + {}, + }; + diff --git a/target/linux/ath79/patches-4.14/404-mtd-cybertan-trx-parser.patch b/target/linux/ath79/patches-5.4/404-mtd-cybertan-trx-parser.patch similarity index 66% rename from target/linux/ath79/patches-4.14/404-mtd-cybertan-trx-parser.patch rename to target/linux/ath79/patches-5.4/404-mtd-cybertan-trx-parser.patch index 3cc0b0dd49..c26ef60725 100644 --- a/target/linux/ath79/patches-4.14/404-mtd-cybertan-trx-parser.patch +++ b/target/linux/ath79/patches-5.4/404-mtd-cybertan-trx-parser.patch @@ -1,11 +1,16 @@ --- a/drivers/mtd/parsers/Makefile +++ b/drivers/mtd/parsers/Makefile -@@ -1 +1,2 @@ +@@ -1,3 +1,4 @@ +obj-$(CONFIG_MTD_PARSER_CYBERTAN) += parser_cybertan.o - obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o + # SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o --- a/drivers/mtd/parsers/Kconfig +++ b/drivers/mtd/parsers/Kconfig -@@ -1,3 +1,11 @@ +@@ -94,6 +94,14 @@ config MTD_AFS_PARTS + for your particular device. It won't happen automatically. The + 'physmap' map driver (CONFIG_MTD_PHYSMAP) does this, for example. + +config MTD_PARSER_CYBERTAN + tristate "Parser for Cybertan format partitions" + depends on MTD && (ATH79 || COMPILE_TEST) diff --git a/target/linux/ath79/patches-4.14/405-mtd-tp-link-partition-parser.patch b/target/linux/ath79/patches-5.4/405-mtd-tp-link-partition-parser.patch similarity index 61% rename from target/linux/ath79/patches-4.14/405-mtd-tp-link-partition-parser.patch rename to target/linux/ath79/patches-5.4/405-mtd-tp-link-partition-parser.patch index 846b7f0a0c..11d1869544 100644 --- a/target/linux/ath79/patches-4.14/405-mtd-tp-link-partition-parser.patch +++ b/target/linux/ath79/patches-5.4/405-mtd-tp-link-partition-parser.patch @@ -1,6 +1,6 @@ --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig -@@ -194,6 +194,12 @@ config MTD_MYLOADER_PARTS +@@ -62,6 +62,12 @@ config MTD_MYLOADER_PARTS You will still need the parsing functions to be called by the driver for your particular device. It won't happen automatically. @@ -15,11 +15,11 @@ # --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63 - obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o - obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o +@@ -8,6 +8,7 @@ obj-$(CONFIG_MTD) += mtd.o + mtd-y := mtdcore.o mtdsuper.o mtdconcat.o mtdpart.o mtdchar.o + obj-y += parsers/ +obj-$(CONFIG_MTD_TPLINK_PARTS) += tplinkpart.o - # 'Users' - code which presents functionality to userspace. - obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o + obj-$(CONFIG_MTD_SPLIT) += mtdsplit/ + diff --git a/target/linux/ath79/patches-4.14/408-mtd-redboot_partition_scan.patch b/target/linux/ath79/patches-5.4/408-mtd-redboot_partition_scan.patch similarity index 76% rename from target/linux/ath79/patches-4.14/408-mtd-redboot_partition_scan.patch rename to target/linux/ath79/patches-5.4/408-mtd-redboot_partition_scan.patch index cd41e7ceb2..8f3ee32f57 100644 --- a/target/linux/ath79/patches-4.14/408-mtd-redboot_partition_scan.patch +++ b/target/linux/ath79/patches-5.4/408-mtd-redboot_partition_scan.patch @@ -1,8 +1,8 @@ ---- a/drivers/mtd/redboot.c -+++ b/drivers/mtd/redboot.c -@@ -76,12 +76,18 @@ static int parse_redboot_partitions(stru - static char nullstring[] = "unallocated"; - #endif +--- a/drivers/mtd/parsers/redboot.c ++++ b/drivers/mtd/parsers/redboot.c +@@ -85,12 +85,18 @@ static int parse_redboot_partitions(stru + + parse_redboot_of(master); + buf = vmalloc(master->erasesize); + if (!buf) @@ -19,7 +19,7 @@ return -EIO; } offset -= master->erasesize; -@@ -94,10 +100,6 @@ static int parse_redboot_partitions(stru +@@ -103,10 +109,6 @@ static int parse_redboot_partitions(stru goto nogood; } } @@ -30,7 +30,7 @@ printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", master->name, offset); -@@ -170,6 +172,11 @@ static int parse_redboot_partitions(stru +@@ -179,6 +181,11 @@ static int parse_redboot_partitions(stru } if (i == numslots) { /* Didn't find it */ diff --git a/target/linux/ath79/patches-5.4/410-spi-ath79-Implement-the-spi_mem-interface.patch b/target/linux/ath79/patches-5.4/410-spi-ath79-Implement-the-spi_mem-interface.patch new file mode 100644 index 0000000000..2a6b9857fb --- /dev/null +++ b/target/linux/ath79/patches-5.4/410-spi-ath79-Implement-the-spi_mem-interface.patch @@ -0,0 +1,68 @@ +From 8d8cdb4a6ccee5b62cc0dc64651c3946364514dc Mon Sep 17 00:00:00 2001 +From: Luiz Angelo Daros de Luca +Date: Mon, 10 Feb 2020 16:11:27 -0300 +Subject: [PATCH] spi: ath79: Implement the spi_mem interface + +Signed-off-by: Luiz Angelo Daros de Luca +--- + drivers/spi/spi-ath79.c | 35 +++++++++++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -133,6 +134,39 @@ static u32 ath79_spi_txrx_mode0(struct s + return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); + } + ++static int ath79_exec_mem_op(struct spi_mem *mem, ++ const struct spi_mem_op *op) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(mem->spi); ++ ++ /* Ensures that reading is performed on device connected ++ to hardware cs0 */ ++ if (mem->spi->chip_select || mem->spi->cs_gpiod) ++ return -ENOTSUPP; ++ ++ /* Only use for fast-read op. */ ++ if (op->cmd.opcode != 0x0b || op->data.dir != SPI_MEM_DATA_IN || ++ op->addr.nbytes != 3 || op->dummy.nbytes != 1) ++ return -ENOTSUPP; ++ ++ /* disable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); ++ ++ memcpy_fromio(op->data.buf.in, sp->base + op->addr.val, op->data.nbytes); ++ ++ /* enable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); ++ ++ /* restore IOC register */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); ++ ++ return 0; ++} ++ ++static const struct spi_controller_mem_ops ath79_mem_ops = { ++ .exec_op = ath79_exec_mem_op, ++}; ++ + static int ath79_spi_probe(struct platform_device *pdev) + { + struct spi_master *master; +@@ -163,6 +197,7 @@ static int ath79_spi_probe(struct platfo + ret = PTR_ERR(sp->base); + goto err_put_master; + } ++ master->mem_ops = &ath79_mem_ops; + + sp->clk = devm_clk_get(&pdev->dev, "ahb"); + if (IS_ERR(sp->clk)) { diff --git a/target/linux/ath79/patches-5.4/420-net-use-downstream-ag71xx.patch b/target/linux/ath79/patches-5.4/420-net-use-downstream-ag71xx.patch new file mode 100644 index 0000000000..17cf3ea957 --- /dev/null +++ b/target/linux/ath79/patches-5.4/420-net-use-downstream-ag71xx.patch @@ -0,0 +1,28 @@ +--- a/drivers/net/ethernet/atheros/Kconfig ++++ b/drivers/net/ethernet/atheros/Kconfig +@@ -17,13 +17,7 @@ config NET_VENDOR_ATHEROS + + if NET_VENDOR_ATHEROS + +-config AG71XX +- tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support" +- depends on ATH79 +- select PHYLIB +- help +- If you wish to compile a kernel for AR7XXX/91XXX and enable +- ethernet support, then you should always answer Y to this. ++source "drivers/net/ethernet/atheros/ag71xx/Kconfig" + + config ATL2 + tristate "Atheros L2 Fast Ethernet support" +--- a/drivers/net/ethernet/atheros/Makefile ++++ b/drivers/net/ethernet/atheros/Makefile +@@ -3,7 +3,7 @@ + # Makefile for the Atheros network device drivers. + # + +-obj-$(CONFIG_AG71XX) += ag71xx.o ++obj-$(CONFIG_AG71XX) += ag71xx/ + obj-$(CONFIG_ATL1) += atlx/ + obj-$(CONFIG_ATL2) += atlx/ + obj-$(CONFIG_ATL1E) += atl1e/ diff --git a/target/linux/ath79/patches-4.14/425-at803x-allow-sgmii-aneg-override.patch b/target/linux/ath79/patches-5.4/425-at803x-allow-sgmii-aneg-override.patch similarity index 77% rename from target/linux/ath79/patches-4.14/425-at803x-allow-sgmii-aneg-override.patch rename to target/linux/ath79/patches-5.4/425-at803x-allow-sgmii-aneg-override.patch index 3b302dcd9e..396b1ee7a2 100644 --- a/target/linux/ath79/patches-4.14/425-at803x-allow-sgmii-aneg-override.patch +++ b/target/linux/ath79/patches-5.4/425-at803x-allow-sgmii-aneg-override.patch @@ -1,8 +1,8 @@ --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c -@@ -472,6 +472,13 @@ static int at803x_aneg_done(struct phy_d +@@ -383,6 +383,13 @@ static int at803x_aneg_done(struct phy_d if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) { - pr_warn("803x_aneg_done: SGMII link is not ok\n"); + phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n"); aneg_done = 0; +#ifdef CONFIG_OF_MDIO + if (phydev->mdio.dev.of_node && diff --git a/target/linux/ath79/patches-4.14/430-drivers-link-spi-before-mtd.patch b/target/linux/ath79/patches-5.4/430-drivers-link-spi-before-mtd.patch similarity index 79% rename from target/linux/ath79/patches-4.14/430-drivers-link-spi-before-mtd.patch rename to target/linux/ath79/patches-5.4/430-drivers-link-spi-before-mtd.patch index 2f1549710b..4c6558db90 100644 --- a/target/linux/ath79/patches-4.14/430-drivers-link-spi-before-mtd.patch +++ b/target/linux/ath79/patches-5.4/430-drivers-link-spi-before-mtd.patch @@ -1,6 +1,6 @@ --- a/drivers/Makefile +++ b/drivers/Makefile -@@ -83,8 +83,8 @@ obj-$(CONFIG_SCSI) += scsi/ +@@ -80,8 +80,8 @@ obj-y += scsi/ obj-y += nvme/ obj-$(CONFIG_ATA) += ata/ obj-$(CONFIG_TARGET_CORE) += target/ @@ -9,4 +9,4 @@ +obj-$(CONFIG_MTD) += mtd/ obj-$(CONFIG_SPMI) += spmi/ obj-$(CONFIG_HSI) += hsi/ - obj-y += net/ + obj-$(CONFIG_SLIMBUS) += slimbus/ diff --git a/target/linux/ath79/patches-5.4/440-mtd-ar934x-nand-driver.patch b/target/linux/ath79/patches-5.4/440-mtd-ar934x-nand-driver.patch new file mode 100644 index 0000000000..8cb47ff703 --- /dev/null +++ b/target/linux/ath79/patches-5.4/440-mtd-ar934x-nand-driver.patch @@ -0,0 +1,25 @@ +--- a/drivers/mtd/nand/raw/Kconfig ++++ b/drivers/mtd/nand/raw/Kconfig +@@ -544,4 +544,12 @@ config MTD_NAND_DISKONCHIP_BBTWRITE + load time (assuming you build diskonchip as a module) with the module + parameter "inftl_bbt_write=1". + ++config MTD_NAND_AR934X ++ tristate "Support for NAND controller on Qualcomm Atheros AR934x/QCA955x SoCs" ++ depends on ATH79 || COMPILE_TEST ++ depends on HAS_IOMEM ++ help ++ Enables support for NAND controller on Qualcomm Atheros SoCs. ++ This controller is found on AR934x and QCA955x SoCs. ++ + endif # MTD_RAW_NAND +--- a/drivers/mtd/nand/raw/Makefile ++++ b/drivers/mtd/nand/raw/Makefile +@@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nan + obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o + obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o + obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o ++obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nand.o + + nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o + nand-objs += nand_onfi.o diff --git a/target/linux/ath79/patches-4.14/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch b/target/linux/ath79/patches-5.4/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch similarity index 95% rename from target/linux/ath79/patches-4.14/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch rename to target/linux/ath79/patches-5.4/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch index 634ce56354..924faec509 100644 --- a/target/linux/ath79/patches-4.14/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch +++ b/target/linux/ath79/patches-5.4/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch @@ -40,7 +40,7 @@ +#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */ --- a/arch/mips/pci/pci-ar71xx.c +++ b/arch/mips/pci/pci-ar71xx.c -@@ -71,6 +71,45 @@ static const u32 ar71xx_pci_read_mask[8] +@@ -68,6 +68,45 @@ static const u32 ar71xx_pci_read_mask[8] 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; @@ -86,7 +86,7 @@ static inline u32 ar71xx_pci_get_ble(int where, int size, int local) { u32 t; -@@ -279,6 +318,9 @@ static int ar71xx_pci_probe(struct platf +@@ -276,6 +315,9 @@ static int ar71xx_pci_probe(struct platf register_pci_controller(&apc->pci_ctrl); diff --git a/target/linux/ath79/patches-4.14/900-mdio_bitbang_ignore_ta_value.patch b/target/linux/ath79/patches-5.4/900-mdio_bitbang_ignore_ta_value.patch similarity index 86% rename from target/linux/ath79/patches-4.14/900-mdio_bitbang_ignore_ta_value.patch rename to target/linux/ath79/patches-5.4/900-mdio_bitbang_ignore_ta_value.patch index 8f8f349a66..148d843518 100644 --- a/target/linux/ath79/patches-4.14/900-mdio_bitbang_ignore_ta_value.patch +++ b/target/linux/ath79/patches-5.4/900-mdio_bitbang_ignore_ta_value.patch @@ -1,6 +1,6 @@ --- a/drivers/net/phy/mdio-bitbang.c +++ b/drivers/net/phy/mdio-bitbang.c -@@ -155,7 +155,7 @@ static int mdiobb_cmd_addr(struct mdiobb +@@ -152,7 +152,7 @@ static int mdiobb_cmd_addr(struct mdiobb static int mdiobb_read(struct mii_bus *bus, int phy, int reg) { struct mdiobb_ctrl *ctrl = bus->priv; @@ -9,7 +9,7 @@ if (reg & MII_ADDR_C45) { reg = mdiobb_cmd_addr(ctrl, phy, reg); -@@ -165,19 +165,7 @@ static int mdiobb_read(struct mii_bus *b +@@ -162,19 +162,7 @@ static int mdiobb_read(struct mii_bus *b ctrl->ops->set_mdio_dir(ctrl, 0); diff --git a/target/linux/ath79/patches-4.14/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch b/target/linux/ath79/patches-5.4/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch similarity index 85% rename from target/linux/ath79/patches-4.14/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch rename to target/linux/ath79/patches-5.4/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch index a830346a31..8c71e5b5ca 100644 --- a/target/linux/ath79/patches-4.14/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch +++ b/target/linux/ath79/patches-5.4/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch @@ -14,15 +14,15 @@ Signed-off-by: Jonas Gorski --- a/drivers/net/phy/mdio-bitbang.c +++ b/drivers/net/phy/mdio-bitbang.c -@@ -17,6 +17,7 @@ - * kind, whether express or implied. +@@ -14,6 +14,7 @@ + * Vitaly Bordug */ +#include #include #include #include -@@ -156,7 +157,9 @@ static int mdiobb_read(struct mii_bus *b +@@ -153,7 +154,9 @@ static int mdiobb_read(struct mii_bus *b { struct mdiobb_ctrl *ctrl = bus->priv; int ret; @@ -32,7 +32,7 @@ Signed-off-by: Jonas Gorski if (reg & MII_ADDR_C45) { reg = mdiobb_cmd_addr(ctrl, phy, reg); mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); -@@ -169,13 +172,17 @@ static int mdiobb_read(struct mii_bus *b +@@ -166,13 +169,17 @@ static int mdiobb_read(struct mii_bus *b ret = mdiobb_get_num(ctrl, 16); mdiobb_get_bit(ctrl); @@ -50,7 +50,7 @@ Signed-off-by: Jonas Gorski if (reg & MII_ADDR_C45) { reg = mdiobb_cmd_addr(ctrl, phy, reg); mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); -@@ -190,6 +197,8 @@ static int mdiobb_write(struct mii_bus * +@@ -187,6 +194,8 @@ static int mdiobb_write(struct mii_bus * ctrl->ops->set_mdio_dir(ctrl, 0); mdiobb_get_bit(ctrl); diff --git a/target/linux/ath79/patches-4.14/910-unaligned_access_hacks.patch b/target/linux/ath79/patches-5.4/910-unaligned_access_hacks.patch similarity index 86% rename from target/linux/ath79/patches-4.14/910-unaligned_access_hacks.patch rename to target/linux/ath79/patches-5.4/910-unaligned_access_hacks.patch index cff52e5add..3ac89f1e5c 100644 --- a/target/linux/ath79/patches-4.14/910-unaligned_access_hacks.patch +++ b/target/linux/ath79/patches-5.4/910-unaligned_access_hacks.patch @@ -169,19 +169,19 @@ /* UDP socket options */ #define UDP_CORK 1 /* Never send partially complete segments */ ---- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c -+++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c -@@ -48,8 +48,8 @@ static bool ipv4_pkt_to_tuple(const stru - if (ap == NULL) - return false; +--- a/net/netfilter/nf_conntrack_core.c ++++ b/net/netfilter/nf_conntrack_core.c +@@ -271,8 +271,8 @@ nf_ct_get_tuple(const struct sk_buff *sk -- tuple->src.u3.ip = ap[0]; -- tuple->dst.u3.ip = ap[1]; -+ tuple->src.u3.ip = net_hdr_word(ap++); -+ tuple->dst.u3.ip = net_hdr_word(ap); - - return true; - } + switch (l3num) { + case NFPROTO_IPV4: +- tuple->src.u3.ip = ap[0]; +- tuple->dst.u3.ip = ap[1]; ++ tuple->src.u3.ip = net_hdr_word(ap++); ++ tuple->dst.u3.ip = net_hdr_word(ap); + break; + case NFPROTO_IPV6: + memcpy(tuple->src.u3.ip6, ap, sizeof(tuple->src.u3.ip6)); --- a/include/uapi/linux/icmp.h +++ b/include/uapi/linux/icmp.h @@ -82,7 +82,7 @@ struct icmphdr { @@ -206,7 +206,7 @@ #if __UAPI_DEF_SOCKADDR_IN6 --- a/net/ipv6/tcp_ipv6.c +++ b/net/ipv6/tcp_ipv6.c -@@ -39,6 +39,7 @@ +@@ -35,6 +35,7 @@ #include #include #include @@ -214,7 +214,7 @@ #include #include #include -@@ -820,10 +821,10 @@ static void tcp_v6_send_response(const s +@@ -849,10 +850,10 @@ static void tcp_v6_send_response(const s topt = (__be32 *)(t1 + 1); if (tsecr) { @@ -241,7 +241,7 @@ */ --- a/net/ipv6/datagram.c +++ b/net/ipv6/datagram.c -@@ -486,7 +486,7 @@ int ipv6_recv_error(struct sock *sk, str +@@ -476,7 +476,7 @@ int ipv6_recv_error(struct sock *sk, str ipv6_iface_scope_id(&sin->sin6_addr, IP6CB(skb)->iif); } else { @@ -250,7 +250,7 @@ &sin->sin6_addr); sin->sin6_scope_id = 0; } -@@ -835,12 +835,12 @@ int ip6_datagram_send_ctl(struct net *ne +@@ -830,12 +830,12 @@ int ip6_datagram_send_ctl(struct net *ne } if (fl6->flowlabel&IPV6_FLOWINFO_MASK) { @@ -265,31 +265,20 @@ break; case IPV6_2292HOPOPTS: ---- a/net/ipv6/ip6_gre.c -+++ b/net/ipv6/ip6_gre.c -@@ -397,7 +397,7 @@ static void ip6gre_err(struct sk_buff *s - return; - ipv6h = (const struct ipv6hdr *)skb->data; - greh = (const struct gre_base_hdr *)(skb->data + offset); -- key = key_off ? *(__be32 *)(skb->data + key_off) : 0; -+ key = key_off ? net_hdr_word((__be32 *)(skb->data + key_off)) : 0; - - t = ip6gre_tunnel_lookup(skb->dev, &ipv6h->daddr, &ipv6h->saddr, - key, greh->protocol); --- a/net/ipv6/exthdrs.c +++ b/net/ipv6/exthdrs.c -@@ -733,7 +733,7 @@ static bool ipv6_hop_jumbo(struct sk_buf +@@ -752,7 +752,7 @@ static bool ipv6_hop_jumbo(struct sk_buf goto drop; } - pkt_len = ntohl(*(__be32 *)(nh + optoff + 2)); + pkt_len = ntohl(net_hdr_word(nh + optoff + 2)); if (pkt_len <= IPV6_MAXPLEN) { - __IP6_INC_STATS(net, ipv6_skb_idev(skb), - IPSTATS_MIB_INHDRERRORS); + __IP6_INC_STATS(net, idev, IPSTATS_MIB_INHDRERRORS); + icmpv6_param_prob(skb, ICMPV6_HDR_FIELD, optoff+2); --- a/include/linux/types.h +++ b/include/linux/types.h -@@ -229,5 +229,11 @@ struct callback_head { +@@ -225,5 +225,11 @@ struct callback_head { typedef void (*rcu_callback_t)(struct rcu_head *head); typedef void (*call_rcu_func_t)(struct rcu_head *head, rcu_callback_t func); @@ -303,7 +292,7 @@ #endif /* _LINUX_TYPES_H */ --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c -@@ -1352,8 +1352,8 @@ struct sk_buff **inet_gro_receive(struct +@@ -1441,8 +1441,8 @@ struct sk_buff *inet_gro_receive(struct if (unlikely(ip_fast_csum((u8 *)iph, 5))) goto out_unlock; @@ -313,21 +302,10 @@ + flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF)); id >>= 16; - for (p = *head; p; p = p->next) { ---- a/net/ipv4/route.c -+++ b/net/ipv4/route.c -@@ -466,7 +466,7 @@ static struct neighbour *ipv4_neigh_look - else if (skb) - pkey = &ip_hdr(skb)->daddr; - -- n = __ipv4_neigh_lookup(dev, *(__force u32 *)pkey); -+ n = __ipv4_neigh_lookup(dev, net_hdr_word(pkey)); - if (n) - return n; - return neigh_create(&arp_tbl, pkey, dev); + list_for_each_entry(p, head, list) { --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c -@@ -454,48 +454,53 @@ static void tcp_options_write(__be32 *pt +@@ -460,48 +460,53 @@ static void tcp_options_write(__be32 *pt u16 options = opts->options; /* mungable copy */ if (unlikely(OPTION_MD5 & options)) { @@ -404,7 +382,7 @@ } if (unlikely(opts->num_sack_blocks)) { -@@ -503,16 +508,17 @@ static void tcp_options_write(__be32 *pt +@@ -509,16 +514,17 @@ static void tcp_options_write(__be32 *pt tp->duplicate_sack : tp->selective_acks; int this_sack; @@ -428,7 +406,7 @@ } tp->rx_opt.dsack = 0; -@@ -525,13 +531,14 @@ static void tcp_options_write(__be32 *pt +@@ -531,13 +537,14 @@ static void tcp_options_write(__be32 *pt if (foc->exp) { len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len; @@ -486,7 +464,7 @@ #define IGMP_HOST_MEMBERSHIP_REPORT 0x12 /* Ditto */ --- a/net/core/flow_dissector.c +++ b/net/core/flow_dissector.c -@@ -109,7 +109,7 @@ __be32 __skb_flow_get_ports(const struct +@@ -196,7 +196,7 @@ __be32 __skb_flow_get_ports(const struct ports = __skb_header_pointer(skb, thoff + poff, sizeof(_ports), data, hlen, &_ports); if (ports) @@ -508,7 +486,7 @@ #define ICMPV6_ROUTER_PREF_LOW 0x3 --- a/include/net/ndisc.h +++ b/include/net/ndisc.h -@@ -89,7 +89,7 @@ struct ra_msg { +@@ -92,7 +92,7 @@ struct ra_msg { struct icmp6hdr icmph; __be32 reachable_time; __be32 retrans_timer; @@ -517,7 +495,7 @@ struct rd_msg { struct icmp6hdr icmph; -@@ -368,10 +368,10 @@ static inline u32 ndisc_hashfn(const voi +@@ -371,10 +371,10 @@ static inline u32 ndisc_hashfn(const voi { const u32 *p32 = pkey; @@ -534,7 +512,7 @@ static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey) --- a/net/sched/cls_u32.c +++ b/net/sched/cls_u32.c -@@ -165,7 +165,7 @@ next_knode: +@@ -155,7 +155,7 @@ next_knode: data = skb_header_pointer(skb, toff, 4, &hdata); if (!data) goto out; @@ -543,7 +521,7 @@ n = rcu_dereference_bh(n->next); goto next_knode; } -@@ -218,8 +218,8 @@ check_terminal: +@@ -206,8 +206,8 @@ check_terminal: &hdata); if (!data) goto out; @@ -556,7 +534,7 @@ goto next_ht; --- a/net/ipv6/ip6_offload.c +++ b/net/ipv6/ip6_offload.c -@@ -221,7 +221,7 @@ static struct sk_buff **ipv6_gro_receive +@@ -240,7 +240,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff * continue; iph2 = (struct ipv6hdr *)(p->data + off); @@ -574,8 +552,8 @@ -}; +} __attribute__((packed, aligned(2))); + #include #include - #include --- a/include/net/inet_ecn.h +++ b/include/net/inet_ecn.h @@ -125,9 +125,9 @@ static inline int IP6_ECN_set_ce(struct @@ -590,18 +568,9 @@ if (skb->ip_summed == CHECKSUM_COMPLETE) skb->csum = csum_add(csum_sub(skb->csum, (__force __wsum)from), (__force __wsum)to); -@@ -136,7 +136,7 @@ static inline int IP6_ECN_set_ce(struct - - static inline void IP6_ECN_clear(struct ipv6hdr *iph) - { -- *(__be32*)iph &= ~htonl(INET_ECN_MASK << 20); -+ net_hdr_word(iph) &= ~htonl(INET_ECN_MASK << 20); - } - - static inline void ipv6_copy_dscp(unsigned int dscp, struct ipv6hdr *inner) --- a/include/net/ipv6.h +++ b/include/net/ipv6.h -@@ -108,7 +108,7 @@ struct frag_hdr { +@@ -146,7 +146,7 @@ struct frag_hdr { __u8 reserved; __be16 frag_off; __be32 identification; @@ -610,7 +579,7 @@ #define IP6_MF 0x0001 #define IP6_OFFSET 0xFFF8 -@@ -437,8 +437,8 @@ static inline void __ipv6_addr_set_half( +@@ -557,8 +557,8 @@ static inline void __ipv6_addr_set_half( } #endif #endif @@ -620,8 +589,8 @@ + net_hdr_word(&addr[1]) = wl; } - static inline void ipv6_addr_set(struct in6_addr *addr, -@@ -497,6 +497,8 @@ static inline bool ipv6_prefix_equal(con + static inline void ipv6_addr_set(struct in6_addr *addr, +@@ -617,6 +617,8 @@ static inline bool ipv6_prefix_equal(con const __be32 *a1 = addr1->s6_addr32; const __be32 *a2 = addr2->s6_addr32; unsigned int pdw, pbi; @@ -630,7 +599,7 @@ /* check complete u32 in prefix */ pdw = prefixlen >> 5; -@@ -505,7 +507,9 @@ static inline bool ipv6_prefix_equal(con +@@ -625,7 +627,9 @@ static inline bool ipv6_prefix_equal(con /* check incomplete u32 in prefix */ pbi = prefixlen & 0x1f; @@ -641,7 +610,7 @@ return false; return true; -@@ -605,13 +609,13 @@ static inline void ipv6_addr_set_v4mappe +@@ -741,13 +745,13 @@ static inline void ipv6_addr_set_v4mappe */ static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen) { @@ -657,7 +626,7 @@ if (xb) return i * 32 + 31 - __fls(ntohl(xb)); } -@@ -780,17 +784,18 @@ static inline int ip6_default_np_autolab +@@ -934,17 +938,18 @@ static inline int ip6_multipath_hash_pol static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass, __be32 flowlabel) { @@ -702,7 +671,7 @@ #define IP_TOS 1 --- a/net/ipv6/ip6_fib.c +++ b/net/ipv6/ip6_fib.c -@@ -137,7 +137,7 @@ static __be32 addr_bit_set(const void *t +@@ -140,7 +140,7 @@ static __be32 addr_bit_set(const void *t * See include/asm-generic/bitops/le.h. */ return (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) & @@ -710,10 +679,10 @@ + net_hdr_word(&addr[fn_bit >> 5]); } - static struct fib6_node *node_alloc(void) + struct fib6_info *fib6_info_alloc(gfp_t gfp_flags, bool with_fib6_nh) --- a/net/netfilter/nf_conntrack_proto_tcp.c +++ b/net/netfilter/nf_conntrack_proto_tcp.c -@@ -447,7 +447,7 @@ static void tcp_sack(const struct sk_buf +@@ -415,7 +415,7 @@ static void tcp_sack(const struct sk_buf /* Fast path for timestamp-only option */ if (length == TCPOLEN_TSTAMP_ALIGNED @@ -724,7 +693,7 @@ | TCPOLEN_TIMESTAMP)) --- a/net/xfrm/xfrm_input.c +++ b/net/xfrm/xfrm_input.c -@@ -193,8 +193,8 @@ int xfrm_parse_spi(struct sk_buff *skb, +@@ -162,8 +162,8 @@ int xfrm_parse_spi(struct sk_buff *skb, if (!pskb_may_pull(skb, hlen)) return -EINVAL; @@ -737,7 +706,7 @@ EXPORT_SYMBOL(xfrm_parse_spi); --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c -@@ -3878,14 +3878,16 @@ static bool tcp_parse_aligned_timestamp( +@@ -3958,14 +3958,16 @@ static bool tcp_parse_aligned_timestamp( { const __be32 *ptr = (const __be32 *)(th + 1); @@ -771,7 +740,7 @@ --- a/net/ipv6/netfilter/nf_log_ipv6.c +++ b/net/ipv6/netfilter/nf_log_ipv6.c -@@ -66,9 +66,9 @@ static void dump_ipv6_packet(struct nf_l +@@ -63,9 +63,9 @@ static void dump_ipv6_packet(struct net /* Max length: 44 "LEN=65535 TC=255 HOPLIMIT=255 FLOWLBL=FFFFF " */ nf_log_buf_add(m, "LEN=%zu TC=%u HOPLIMIT=%u FLOWLBL=%u ", ntohs(ih->payload_len) + sizeof(struct ipv6hdr), @@ -785,7 +754,7 @@ ptr = ip6hoff + sizeof(struct ipv6hdr); --- a/include/net/neighbour.h +++ b/include/net/neighbour.h -@@ -265,8 +265,10 @@ static inline bool neigh_key_eq128(const +@@ -273,8 +273,10 @@ static inline bool neigh_key_eq128(const const u32 *n32 = (const u32 *)n->primary_key; const u32 *p32 = pkey; @@ -811,7 +780,7 @@ * No flags defined yet. --- a/net/core/utils.c +++ b/net/core/utils.c -@@ -441,8 +441,14 @@ void inet_proto_csum_replace16(__sum16 * +@@ -460,8 +460,14 @@ void inet_proto_csum_replace16(__sum16 * bool pseudohdr) { __be32 diff[] = { @@ -830,7 +799,7 @@ *sum = csum_fold(csum_partial(diff, sizeof(diff), --- a/include/linux/etherdevice.h +++ b/include/linux/etherdevice.h -@@ -480,7 +480,7 @@ static inline bool is_etherdev_addr(cons +@@ -489,7 +489,7 @@ static inline bool is_etherdev_addr(cons * @b: Pointer to Ethernet header * * Compare two Ethernet headers, returns 0 if equal. @@ -839,7 +808,7 @@ * aligned OR the platform can handle unaligned access. This is the * case for all packets coming into netif_receive_skb or similar * entry points. -@@ -503,11 +503,12 @@ static inline unsigned long compare_ethe +@@ -512,11 +512,12 @@ static inline unsigned long compare_ethe fold |= *(unsigned long *)(a + 6) ^ *(unsigned long *)(b + 6); return fold; #else @@ -858,7 +827,7 @@ --- a/net/ipv4/tcp_offload.c +++ b/net/ipv4/tcp_offload.c -@@ -226,7 +226,7 @@ struct sk_buff **tcp_gro_receive(struct +@@ -223,7 +223,7 @@ struct sk_buff *tcp_gro_receive(struct l th2 = tcp_hdr(p); @@ -867,7 +836,7 @@ NAPI_GRO_CB(p)->same_flow = 0; continue; } -@@ -244,8 +244,8 @@ found: +@@ -241,8 +241,8 @@ found: ~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH)); flush |= (__force int)(th->ack_seq ^ th2->ack_seq); for (i = sizeof(*th); i < thlen; i += 4) @@ -880,7 +849,7 @@ * continue this flow as an atomic flow with a fixed ID or if we use --- a/net/ipv6/netfilter/ip6table_mangle.c +++ b/net/ipv6/netfilter/ip6table_mangle.c -@@ -50,7 +50,7 @@ ip6t_mangle_out(struct sk_buff *skb, con +@@ -47,7 +47,7 @@ ip6t_mangle_out(struct sk_buff *skb, con hop_limit = ipv6_hdr(skb)->hop_limit; /* flowlabel and prio (includes version, which shouldn't change either */ @@ -889,7 +858,7 @@ ret = ip6t_do_table(skb, state, state->net->ipv6.ip6table_mangle); -@@ -59,7 +59,7 @@ ip6t_mangle_out(struct sk_buff *skb, con +@@ -56,7 +56,7 @@ ip6t_mangle_out(struct sk_buff *skb, con !ipv6_addr_equal(&ipv6_hdr(skb)->daddr, &daddr) || skb->mark != mark || ipv6_hdr(skb)->hop_limit != hop_limit || diff --git a/target/linux/ath79/tiny/base-files/etc/board.d/01_leds b/target/linux/ath79/tiny/base-files/etc/board.d/01_leds index c62fdfd083..30773db332 100755 --- a/target/linux/ath79/tiny/base-files/etc/board.d/01_leds +++ b/target/linux/ath79/tiny/base-files/etc/board.d/01_leds @@ -46,11 +46,13 @@ tplink,tl-wa701nd-v1|\ tplink,tl-wa730re-v1|\ tplink,tl-wa801nd-v1|\ tplink,tl-wa830re-v1|\ +tplink,tl-wa860re-v1|\ tplink,tl-wa901nd-v1) ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" ;; tplink,tl-mr3420-v2|\ tplink,tl-wr740n-v4|\ +tplink,tl-wr740n-v5|\ tplink,tl-wr741nd-v4|\ tplink,tl-wr841-v8) ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" @@ -59,6 +61,17 @@ tplink,tl-wr841-v8) ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" ;; +tplink,tl-mr3420-v3|\ +tplink,tl-wr841-v9|\ +tplink,tl-wr841-v10|\ +tplink,tl-wr841-v11|\ +tplink,tl-wr841-v12) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x10" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x04" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ;; tplink,tl-wa850re-v1|\ tplink,tl-wa850re-v2) ucidef_set_led_netdev "lan" "LAN" "tp-link:blue:lan" "eth0" @@ -81,16 +94,6 @@ tplink,tl-wr941-v4) ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x08" ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x10" ;; -tplink,tl-wr841-v9|\ -tplink,tl-wr841-v10|\ -tplink,tl-wr841-v11|\ -tplink,tl-wr841-v12) - ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" - ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x10" - ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" - ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x04" - ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" - ;; tplink,tl-wr940n-v3|\ tplink,tl-wr940n-v4|\ tplink,tl-wr941nd-v6) diff --git a/target/linux/ath79/tiny/base-files/etc/board.d/02_network b/target/linux/ath79/tiny/base-files/etc/board.d/02_network index 29c55c98a1..53e2a1ebd4 100755 --- a/target/linux/ath79/tiny/base-files/etc/board.d/02_network +++ b/target/linux/ath79/tiny/base-files/etc/board.d/02_network @@ -38,6 +38,7 @@ ath79_setup_interfaces() tplink,tl-wa830re-v1|\ tplink,tl-wa850re-v1|\ tplink,tl-wa850re-v2|\ + tplink,tl-wa860re-v1|\ tplink,tl-wa901nd-v1|\ tplink,tl-wa901nd-v2|\ tplink,tl-wr703n) @@ -45,6 +46,7 @@ ath79_setup_interfaces() ;; tplink,tl-mr3220-v1|\ tplink,tl-mr3420-v1|\ + tplink,tl-mr3420-v3|\ tplink,tl-wr841-v7|\ tplink,tl-wr841-v9|\ tplink,tl-wr841-v10|\ @@ -60,6 +62,7 @@ ath79_setup_interfaces() ;; tplink,tl-mr3420-v2|\ tplink,tl-wr740n-v4|\ + tplink,tl-wr740n-v5|\ tplink,tl-wr741nd-v4|\ tplink,tl-wr841-v8) ucidef_set_interface_wan "eth1" diff --git a/target/linux/ath79/tiny/config-default b/target/linux/ath79/tiny/config-default index 9b845abbff..42243cfc48 100644 --- a/target/linux/ath79/tiny/config-default +++ b/target/linux/ath79/tiny/config-default @@ -1,9 +1,12 @@ CONFIG_LEDS_RESET=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_NET_DEVLINK=y CONFIG_NET_DSA=y CONFIG_NET_DSA_MV88E6060=y +# CONFIG_NET_DSA_TAG_QCA is not set CONFIG_NET_DSA_TAG_TRAILER=y CONFIG_NET_SWITCHDEV=y +CONFIG_PHYLINK=y CONFIG_PHY_AR7100_USB=y CONFIG_PHY_AR7200_USB=y CONFIG_REGULATOR=y