diff --git a/package/libs/mbedtls/Makefile b/package/libs/mbedtls/Makefile index 088d3284da..0ab238962e 100644 --- a/package/libs/mbedtls/Makefile +++ b/package/libs/mbedtls/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mbedtls -PKG_VERSION:=2.16.10 -PKG_RELEASE:=1 +PKG_VERSION:=2.16.11 +PKG_RELEASE:=$(AUTORELEASE) PKG_USE_MIPS16:=0 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://codeload.github.com/ARMmbed/mbedtls/tar.gz/v$(PKG_VERSION)? -PKG_HASH:=96257bb03b30300b2f35f861ffe204ed957e9fd0329d80646fe57fc49f589b29 +PKG_HASH:=c18e7e9abf95e69e425260493720470021384a1728417042060a35d0b7b18b41 PKG_BUILD_PARALLEL:=1 PKG_LICENSE:=GPL-2.0-or-later diff --git a/package/utils/fritz-tools/src/fritz_tffs_nand_read.c b/package/utils/fritz-tools/src/fritz_tffs_nand_read.c index ded0577cf3..22b27336f8 100644 --- a/package/utils/fritz-tools/src/fritz_tffs_nand_read.c +++ b/package/utils/fritz-tools/src/fritz_tffs_nand_read.c @@ -340,7 +340,7 @@ static int show_matching_key_value(struct tffs_key_name_table *key_names) for (uint32_t i = 0; i < key_names->size; i++) { name = key_names->entries[i].val; - if (strncmp(name, name_filter, strlen(name)) == 0) { + if (strcmp(name, name_filter) == 0) { if (find_entry(key_names->entries[i].id, &tmp)) { print_entry_value(&tmp); printf("\n"); diff --git a/package/utils/fritz-tools/src/fritz_tffs_read.c b/package/utils/fritz-tools/src/fritz_tffs_read.c index d1b3038e63..256c34c414 100644 --- a/package/utils/fritz-tools/src/fritz_tffs_read.c +++ b/package/utils/fritz-tools/src/fritz_tffs_read.c @@ -204,7 +204,7 @@ static int show_matching_key_value(uint8_t *buffer, for (i = 0; i < key_names->size; i++) { name = key_names->entries[i].val; - if (strncmp(name, name_filter, strlen(name)) == 0) { + if (strcmp(name, name_filter) == 0) { id = to_entry_header_id(*key_names->entries[i].id); if (find_entry(buffer, id, &tmp)) { diff --git a/target/linux/mvebu/patches-5.4/100-cpufreq-armada-37xx-forbid-cpufreq-for-1.2-GHz-variant.patch b/target/linux/mvebu/patches-5.4/100-cpufreq-armada-37xx-forbid-cpufreq-for-1.2-GHz-variant.patch new file mode 100644 index 0000000000..6a5b8220f8 --- /dev/null +++ b/target/linux/mvebu/patches-5.4/100-cpufreq-armada-37xx-forbid-cpufreq-for-1.2-GHz-variant.patch @@ -0,0 +1,39 @@ +From: =?utf-8?q?Marek_Beh=C3=BAn?= +Subject: [PATCH v2] cpufreq: armada-37xx: forbid cpufreq for 1.2 GHz variant +Date: Thu, 1 Jul 2021 00:56:01 +0200 + +The 1.2 GHz variant of the Armada 3720 SOC is unstable with DVFS: when +the SOC boots, the WTMI firmware sets clocks and AVS values that work +correctly with 1.2 GHz CPU frequency, but random crashes occur once +cpufreq driver starts scaling. + +We do not know currently what is the reason: +- it may be that the voltage value for L0 for 1.2 GHz variant provided + by the vendor in the OTP is simply incorrect when scaling is used, +- it may be that some delay is needed somewhere, +- it may be something else. + +The most sane solution now seems to be to simply forbid the cpufreq +driver on 1.2 GHz variant. + +Signed-off-by: Marek Behún +Fixes: 92ce45fb875d ("cpufreq: Add DVFS support for Armada 37xx") +--- + drivers/cpufreq/armada-37xx-cpufreq.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/cpufreq/armada-37xx-cpufreq.c ++++ b/drivers/cpufreq/armada-37xx-cpufreq.c +@@ -102,7 +102,11 @@ struct armada_37xx_dvfs { + }; + + static struct armada_37xx_dvfs armada_37xx_dvfs[] = { +- {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, ++ /* ++ * The cpufreq scaling for 1.2 GHz variant of the SOC is currently ++ * unstable because we do not know how to configure it properly. ++ */ ++ /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */ + {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} }, + {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} }, + {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} }, diff --git a/target/linux/mvebu/patches-5.4/803-Revert-cpufreq-armada-37xx-Fix-setting-TBG-parent-fo.patch b/target/linux/mvebu/patches-5.4/803-Revert-cpufreq-armada-37xx-Fix-setting-TBG-parent-fo.patch deleted file mode 100644 index 65184df584..0000000000 --- a/target/linux/mvebu/patches-5.4/803-Revert-cpufreq-armada-37xx-Fix-setting-TBG-parent-fo.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 35639bac13927d1476398b740b11cbed0ee3ddb2 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 18 May 2021 13:24:30 +0200 -Subject: [PATCH] Revert "cpufreq: armada-37xx: Fix setting TBG parent for load - levels" - -This reverts commit a13b110e7c9e0dc2edcc7a19d4255fc88abd83cc. - -This patch actually corrects the things so that 1 or 1.2GHz models would -actually get scaled to their native frequency. - -However, due to a AVS setting voltages too low this will cause random -crashes on 1.2GHz models. - -So, until a new safe for everybody voltage is agreed on -lets revert the patch. - -Signed-off-by: Robert Marko ---- - drivers/cpufreq/armada-37xx-cpufreq.c | 35 +++++++++------------------ - 1 file changed, 12 insertions(+), 23 deletions(-) - ---- a/drivers/cpufreq/armada-37xx-cpufreq.c -+++ b/drivers/cpufreq/armada-37xx-cpufreq.c -@@ -25,10 +25,6 @@ - - #include "cpufreq-dt.h" - --/* Clk register set */ --#define ARMADA_37XX_CLK_TBG_SEL 0 --#define ARMADA_37XX_CLK_TBG_SEL_CPU_OFF 22 -- - /* Power management in North Bridge register set */ - #define ARMADA_37XX_NB_L0L1 0x18 - #define ARMADA_37XX_NB_L2L3 0x1C -@@ -126,15 +122,10 @@ static struct armada_37xx_dvfs *armada_3 - * will be configured then the DVFS will be enabled. - */ - static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base, -- struct regmap *clk_base, u8 *divider) -+ struct clk *clk, u8 *divider) - { -- u32 cpu_tbg_sel; - int load_lvl; -- -- /* Determine to which TBG clock is CPU connected */ -- regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel); -- cpu_tbg_sel >>= ARMADA_37XX_CLK_TBG_SEL_CPU_OFF; -- cpu_tbg_sel &= ARMADA_37XX_NB_TBG_SEL_MASK; -+ struct clk *parent; - - for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) { - unsigned int reg, mask, val, offset = 0; -@@ -153,11 +144,6 @@ static void __init armada37xx_cpufreq_dv - mask = (ARMADA_37XX_NB_CLK_SEL_MASK - << ARMADA_37XX_NB_CLK_SEL_OFF); - -- /* Set TBG index, for all levels we use the same TBG */ -- val = cpu_tbg_sel << ARMADA_37XX_NB_TBG_SEL_OFF; -- mask = (ARMADA_37XX_NB_TBG_SEL_MASK -- << ARMADA_37XX_NB_TBG_SEL_OFF); -- - /* - * Set cpu divider based on the pre-computed array in - * order to have balanced step. -@@ -176,6 +162,14 @@ static void __init armada37xx_cpufreq_dv - - regmap_update_bits(base, reg, mask, val); - } -+ -+ /* -+ * Set cpu clock source, for all the level we keep the same -+ * clock source that the one already configured. For this one -+ * we need to use the clock framework -+ */ -+ parent = clk_get_parent(clk); -+ clk_set_parent(clk, parent); - } - - /* -@@ -401,16 +395,11 @@ static int __init armada37xx_cpufreq_dri - struct platform_device *pdev; - unsigned long freq; - unsigned int cur_frequency, base_frequency; -- struct regmap *nb_clk_base, *nb_pm_base, *avs_base; -+ struct regmap *nb_pm_base, *avs_base; - struct device *cpu_dev; - int load_lvl, ret; - struct clk *clk, *parent; - -- nb_clk_base = -- syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb"); -- if (IS_ERR(nb_clk_base)) -- return -ENODEV; -- - nb_pm_base = - syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm"); - -@@ -487,7 +476,7 @@ static int __init armada37xx_cpufreq_dri - armada37xx_cpufreq_avs_configure(avs_base, dvfs); - armada37xx_cpufreq_avs_setup(avs_base, dvfs); - -- armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider); -+ armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider); - clk_put(clk); - - for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR; diff --git a/target/linux/x86/64/config-5.4 b/target/linux/x86/64/config-5.4 index e10b5d0ae0..434cde5d86 100644 --- a/target/linux/x86/64/config-5.4 +++ b/target/linux/x86/64/config-5.4 @@ -310,8 +310,8 @@ CONFIG_ND_CLAIM=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NET_FAILOVER=y CONFIG_NET_FLOW_LIMIT=y -CONFIG_NR_CPUS=64 -CONFIG_NR_CPUS_DEFAULT=64 +CONFIG_NR_CPUS=512 +CONFIG_NR_CPUS_DEFAULT=512 CONFIG_NR_CPUS_RANGE_BEGIN=2 CONFIG_NR_CPUS_RANGE_END=512 # CONFIG_NUMA is not set