diff --git a/package/boot/uboot-envtools/Makefile b/package/boot/uboot-envtools/Makefile index 6840b9c586..5c4d585021 100644 --- a/package/boot/uboot-envtools/Makefile +++ b/package/boot/uboot-envtools/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=uboot-envtools PKG_DISTNAME:=u-boot -PKG_VERSION:=2022.07 +PKG_VERSION:=2022.10 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2 @@ -17,7 +17,7 @@ PKG_SOURCE_URL:= \ https://ftp.denx.de/pub/u-boot \ https://mirror.cyberbits.eu/u-boot \ ftp://ftp.denx.de/pub/u-boot -PKG_HASH:=92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e +PKG_HASH:=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8 PKG_SOURCE_SUBDIR:=$(PKG_DISTNAME)-$(PKG_VERSION) PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_DISTNAME)-$(PKG_VERSION) diff --git a/package/devel/gdb/patches/001-Add-support-for-readline-8.2.patch b/package/devel/gdb/patches/001-Add-support-for-readline-8.2.patch new file mode 100644 index 0000000000..eb93c7f290 --- /dev/null +++ b/package/devel/gdb/patches/001-Add-support-for-readline-8.2.patch @@ -0,0 +1,31 @@ +From 1add37b567a7dee39d99f37b37802034c3fce9c4 Mon Sep 17 00:00:00 2001 +From: Andreas Schwab +Date: Sun, 20 Mar 2022 14:01:54 +0100 +Subject: [PATCH] Add support for readline 8.2 + +In readline 8.2 the type of rl_completer_word_break_characters changed to +include const. +--- + gdb/completer.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/gdb/completer.c ++++ b/gdb/completer.c +@@ -36,7 +36,7 @@ + calling a hook instead so we eliminate the CLI dependency. */ + #include "gdbcmd.h" + +-/* Needed for rl_completer_word_break_characters() and for ++/* Needed for rl_completer_word_break_characters and for + rl_filename_completion_function. */ + #include "readline/readline.h" + +@@ -2011,7 +2011,7 @@ gdb_completion_word_break_characters_thr + rl_basic_quote_characters = NULL; + } + +- return rl_completer_word_break_characters; ++ return (char *) rl_completer_word_break_characters; + } + + char * diff --git a/package/devel/trace-cmd/Makefile b/package/devel/trace-cmd/Makefile index 9e8c46bc6f..b6a28ab93a 100644 --- a/package/devel/trace-cmd/Makefile +++ b/package/devel/trace-cmd/Makefile @@ -1,12 +1,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=trace-cmd -PKG_VERSION:=v3.1.3 -PKG_RELEASE:=2 +PKG_VERSION:=v3.1.4 +PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://git.kernel.org/pub/scm/utils/trace-cmd/trace-cmd.git/snapshot/ -PKG_HASH:=1fd8515f38fc29fd7a66e7b6b5931856906522e8a1845999fc9033fc80d7b676 +PKG_HASH:=447e095dbdfb0d362ab8c2086d62d80c5a2ecf67aef09b8f6b0cc064c0e1bfb5 PKG_LICENSE:=GPL-2.0-only PKG_LICENSE_FILES:=COPYING diff --git a/package/firmware/linux-firmware/Makefile b/package/firmware/linux-firmware/Makefile index f383acf85a..15120b6bc8 100644 --- a/package/firmware/linux-firmware/Makefile +++ b/package/firmware/linux-firmware/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=linux-firmware -PKG_VERSION:=20220913 +PKG_VERSION:=20221012 PKG_RELEASE:=1 PKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz -PKG_HASH:=26fd00f2d8e96c4af6f44269a6b893eb857253044f75ad28ef6706a2250cd8e9 +PKG_HASH:=e9d174af729511c8cccb60ec4e0b223b3c44b67d813b42d1ab9813acfa667fa5 PKG_MAINTAINER:=Felix Fietkau diff --git a/package/kernel/button-hotplug/Makefile b/package/kernel/button-hotplug/Makefile index 55412e5685..8e8c02609c 100644 --- a/package/kernel/button-hotplug/Makefile +++ b/package/kernel/button-hotplug/Makefile @@ -28,23 +28,8 @@ define KernelPackage/button-hotplug/description If your device uses GPIO buttons, see gpio-button-hotplug. endef -EXTRA_KCONFIG:= \ - CONFIG_BUTTON_HOTPLUG=m - -EXTRA_CFLAGS:= \ - $(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=m,%,$(filter %=m,$(EXTRA_KCONFIG)))) \ - $(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=y,%,$(filter %=y,$(EXTRA_KCONFIG)))) \ - -MAKE_OPTS:= \ - $(KERNEL_MAKE_FLAGS) \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - $(EXTRA_KCONFIG) - define Build/Compile - $(MAKE) -C "$(LINUX_DIR)" \ - $(MAKE_OPTS) \ - modules + $(KERNEL_MAKE) M="$(PKG_BUILD_DIR)" modules endef $(eval $(call KernelPackage,button-hotplug)) diff --git a/package/kernel/button-hotplug/src/Kconfig b/package/kernel/button-hotplug/src/Kconfig deleted file mode 100644 index aa292e9c13..0000000000 --- a/package/kernel/button-hotplug/src/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config BUTTON_HOTPLUG - tristate "Button Hotplug driver" diff --git a/package/kernel/button-hotplug/src/Makefile b/package/kernel/button-hotplug/src/Makefile index 230d604f8c..e38fa40bb4 100644 --- a/package/kernel/button-hotplug/src/Makefile +++ b/package/kernel/button-hotplug/src/Makefile @@ -1 +1 @@ -obj-${CONFIG_BUTTON_HOTPLUG} += button-hotplug.o \ No newline at end of file +obj-m := button-hotplug.o diff --git a/package/kernel/ksmbd/Makefile b/package/kernel/ksmbd/Makefile index 0f79644552..86207508e5 100644 --- a/package/kernel/ksmbd/Makefile +++ b/package/kernel/ksmbd/Makefile @@ -1,12 +1,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ksmbd -PKG_VERSION:=3.4.5 +PKG_VERSION:=3.4.6 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://codeload.github.com/cifsd-team/cifsd/tar.gz/$(PKG_VERSION)? -PKG_HASH:=2873c8ba1027fc5b04c5f5344804ef1469ad7019a033456c16ca4aa3f2c161f0 +PKG_HASH:=d742992692dbe164060d2a0ea668895ed2b86252f10427db3d3a002df44c445b PKG_LICENSE:=GPL-2.0-or-later PKG_LICENSE_FILES:=COPYING diff --git a/package/kernel/ksmbd/patches/10-fix-build-on-kernel-5.15.52-or-higher.patch b/package/kernel/ksmbd/patches/10-fix-build-on-kernel-5.15.52-or-higher.patch deleted file mode 100644 index 68cf168569..0000000000 --- a/package/kernel/ksmbd/patches/10-fix-build-on-kernel-5.15.52-or-higher.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 98bc509f92cccedd7d51d5ebadc424e2d7f5cbb4 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Tue, 5 Jul 2022 15:20:10 +0800 -Subject: [PATCH] ksmbd: fixes build on kernel 5.15.52 or higher - -The 5.15.52 kernel downported two commits "fs: remove unused low-level -mapping helpers" and "fs: use low-level mapping helpers", which broken -the compilation[1]. This commit fixed it. - -1. https://cdn.kernel.org/pub/linux/kernel/v5.x/ChangeLog-5.15.52 - -Signed-off-by: Chukun Pan -Signed-off-by: Namjae Jeon ---- - smbacl.c | 6 ++++-- - smbacl.h | 6 ++++-- - 2 files changed, 8 insertions(+), 4 deletions(-) - -diff --git a/smbacl.c b/smbacl.c -index 275e357..19c682a 100644 ---- a/smbacl.c -+++ b/smbacl.c -@@ -281,7 +281,8 @@ static int sid_to_id(struct user_namespace *user_ns, - uid_t id; - - id = le32_to_cpu(psid->sub_auth[psid->num_subauth - 1]); --#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) || \ -+ (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 52) && LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)) - uid = mapped_kuid_user(user_ns, &init_user_ns, KUIDT_INIT(id)); - #else - /* -@@ -304,7 +305,8 @@ static int sid_to_id(struct user_namespace *user_ns, - gid_t id; - - id = le32_to_cpu(psid->sub_auth[psid->num_subauth - 1]); --#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) || \ -+ (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 52) && LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)) - gid = mapped_kgid_user(user_ns, &init_user_ns, KGIDT_INIT(id)); - #else - /* -diff --git a/smbacl.h b/smbacl.h -index f2bcdb4..7368bf4 100644 ---- a/smbacl.h -+++ b/smbacl.h -@@ -221,7 +221,8 @@ static inline uid_t posix_acl_uid_translate(struct user_namespace *mnt_userns, - kuid_t kuid; - - /* If this is an idmapped mount, apply the idmapping. */ --#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) || \ -+ (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 52) && LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)) - kuid = mapped_kuid_fs(mnt_userns, &init_user_ns, pace->e_uid); - #else - kuid = kuid_into_mnt(mnt_userns, pace->e_uid); -@@ -241,7 +242,8 @@ static inline gid_t posix_acl_gid_translate(struct user_namespace *mnt_userns, - kgid_t kgid; - - /* If this is an idmapped mount, apply the idmapping. */ --#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) || \ -+ (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 52) && LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)) - kgid = mapped_kgid_fs(mnt_userns, &init_user_ns, pace->e_gid); - #else - kgid = kgid_into_mnt(mnt_userns, pace->e_gid); --- -2.36.1 - diff --git a/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c b/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c index df04de73e0..2339d919b6 100644 --- a/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c +++ b/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c @@ -28,6 +28,7 @@ #include #include +#include #include #include #include diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c index a102568f97..096b8b5bba 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c @@ -46,6 +46,7 @@ #include #endif #include +#include #include #include #include diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c index a20430c448..0e860b9ab5 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c @@ -43,7 +43,12 @@ #include #include #include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,11,0) #include +#else +#include +#endif #include #include #include diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c index 69504efe93..b58a91a5df 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c @@ -44,7 +44,12 @@ #include #include #include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,11,0) #include +#else +#include +#endif #include #include #include diff --git a/package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch b/package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch index 0fc2c2c5e6..45059890e1 100644 --- a/package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch +++ b/package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch @@ -22,3 +22,71 @@ if (pVirtAddr == IFX_NULL) { IFXOS_PRN_USR_ERR_NL( IFXOS, IFXOS_PRN_LEVEL_ERR, +--- a/src/linux/ifxos_linux_socket_drv.c ++++ b/src/linux/ifxos_linux_socket_drv.c +@@ -165,8 +165,12 @@ IFX_int_t IFXOS_SocketRecvFrom( + IFXOS_sockAddr_t *pSocAddr) + { + struct msghdr msg; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,13,0) + struct iovec iov; + mm_segment_t old_fs; ++#else ++ struct kvec iov; ++#endif + int ret; + + IFXOS_RETURN_IF_POINTER_NULL(pBuffer, IFX_ERROR); +@@ -181,6 +185,8 @@ IFX_int_t IFXOS_SocketRecvFrom( + msg.msg_controllen = 0; + msg.msg_flags = 0; + ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,13,0) ++ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,19,0)) + msg.msg_iov = &iov; + msg.msg_iovlen = 1; +@@ -200,6 +206,10 @@ IFX_int_t IFXOS_SocketRecvFrom( + #endif + set_fs(old_fs); + ++#else ++ ret = kernel_recvmsg (socFd, &msg, &iov, 1, bufSize_byte, 0); ++#endif ++ + return ret; + } + +@@ -229,8 +239,12 @@ IFX_int_t IFXOS_SocketSendTo( + IFXOS_sockAddr_t *pSocAddr) + { + struct msghdr msg; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,13,0) + struct iovec iov; + mm_segment_t old_fs; ++#else ++ struct kvec iov; ++#endif + int ret; + + IFXOS_RETURN_IF_POINTER_NULL(pBuffer, IFX_ERROR); +@@ -245,6 +259,8 @@ IFX_int_t IFXOS_SocketSendTo( + msg.msg_controllen = 0; + msg.msg_flags = MSG_DONTWAIT; + ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,13,0) ++ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,19,0)) + msg.msg_iov = &iov; + msg.msg_iovlen = 1; +@@ -264,6 +280,10 @@ IFX_int_t IFXOS_SocketSendTo( + #endif + set_fs(old_fs); + ++#else ++ ret = kernel_sendmsg(socFd, &msg, &iov, 1, bufSize_byte); ++#endif ++ + return ret; + } + diff --git a/package/kernel/lantiq/ltq-tapi/patches/500-linux-509.patch b/package/kernel/lantiq/ltq-tapi/patches/500-linux-509.patch index 586af59d85..07f61aa632 100644 --- a/package/kernel/lantiq/ltq-tapi/patches/500-linux-509.patch +++ b/package/kernel/lantiq/ltq-tapi/patches/500-linux-509.patch @@ -34,6 +34,16 @@ } +@@ -3800,7 +3808,9 @@ module_exit (ifx_tapi_module_exit); + + MODULE_AUTHOR ("Lantiq Deutschland GmbH"); + MODULE_DESCRIPTION ("TAPI Driver - www.lantiq.com"); ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(5,10,0) + MODULE_SUPPORTED_DEVICE ("TAPI DEVICE"); ++#endif + MODULE_LICENSE ("Dual BSD/GPL"); + + EXPORT_SYMBOL (IFX_TAPI_Register_LL_Drv); --- a/src/drv_tapi_kpi.c +++ b/src/drv_tapi_kpi.c @@ -134,7 +134,11 @@ extern IFX_int32_t block_ingre diff --git a/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/100-compat.patch b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/100-compat.patch index 61ea826cb4..7e7381a346 100644 --- a/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/100-compat.patch +++ b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/100-compat.patch @@ -43,7 +43,18 @@ #ifdef MODULE #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) MODULE_PARM(major_number, "b"); -@@ -1479,7 +1483,11 @@ struct proc_entry { +@@ -1256,7 +1260,9 @@ static long MEI_Ioctl( struct file *filp + MEI_IOCTL_RETURN: + + local_args.drv_ioctl.retCode = ret; +- copy_to_user( ((IOCTL_MEI_arg_t *)nArgument), &local_args, retSize); ++ if ( ret == IFX_SUCCESS && ++ copy_to_user( ((IOCTL_MEI_arg_t *)nArgument), &local_args, retSize) ) ++ ret = -e_MEI_ERR_RETURN_ARG; + + return (ret < 0) ? -1 : 0; + } +@@ -1479,7 +1485,11 @@ struct proc_entry { char name[32]; proc_rd_callback_t rd; proc_wr_callback_t wr; @@ -55,7 +66,7 @@ int entity; }; -@@ -1869,6 +1877,7 @@ static int mei_proc_single_open(struct i +@@ -1869,6 +1879,7 @@ static int mei_proc_single_open(struct i static void mei_proc_entry_create(struct proc_dir_entry *parent_node, struct proc_entry *proc_entry) { @@ -63,7 +74,7 @@ memset(&proc_entry->ops, 0, sizeof(struct file_operations)); proc_entry->ops.owner = THIS_MODULE; -@@ -1879,6 +1888,17 @@ static void mei_proc_entry_create(struct +@@ -1879,6 +1890,17 @@ static void mei_proc_entry_create(struct proc_entry->ops.llseek = seq_lseek; if (proc_entry->wr) proc_entry->ops.write = proc_entry->wr; @@ -81,7 +92,7 @@ proc_create_data(proc_entry->name, (S_IFREG | S_IRUGO), -@@ -2174,9 +2194,11 @@ static int MEI_module_init (void) +@@ -2174,9 +2196,11 @@ static int MEI_module_init (void) return (result); } @@ -93,7 +104,7 @@ return 0; } -@@ -2304,6 +2326,10 @@ static void MEI_module_exit (void) +@@ -2304,6 +2328,10 @@ static void MEI_module_exit (void) #else unregister_chrdev ( major_number , DRV_MEI_NAME ); @@ -104,7 +115,7 @@ #endif #if CONFIG_PROC_FS -@@ -2388,9 +2414,11 @@ static void MEI_module_exit (void) +@@ -2388,9 +2416,11 @@ static void MEI_module_exit (void) ("MEI_DRV: Chipset Basic Exit failed" MEI_DRV_CRLF)); } @@ -116,7 +127,7 @@ #if (MEI_SUPPORT_DEBUG_LOGGER == 1) if (nl_debug_sock) -@@ -2514,6 +2542,10 @@ static int MEI_InitModuleRegCharDev(cons +@@ -2514,6 +2544,10 @@ static int MEI_InitModuleRegCharDev(cons ("Using major number %d" MEI_DRV_CRLF, major_number)); } @@ -127,7 +138,7 @@ return 0; #endif /* CONFIG_DEVFS_FS */ } -@@ -2563,21 +2595,32 @@ static int MEI_InitModuleBasics(void) +@@ -2563,21 +2597,32 @@ static int MEI_InitModuleBasics(void) } #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)) @@ -160,7 +171,7 @@ return 0; } -@@ -2905,11 +2948,15 @@ IFX_int32_t MEI_IoctlInitDevice( +@@ -2905,11 +2950,15 @@ IFX_int32_t MEI_IoctlInitDevice( pMeiDev->eModePoll = e_MEI_DEV_ACCESS_MODE_IRQ; pMeiDev->intMask = ME_ARC2ME_INTERRUPT_UNMASK_ALL; @@ -176,6 +187,46 @@ pTmpXCntrl = MEI_VrxXDevToIrqListAdd( MEI_DRV_LINENUM_GET(pMeiDev), +@@ -3249,9 +3298,11 @@ static int MEI_IoctlMeiDbgAccessWr_Wrap( + ret = MEI_IoctlMeiDbgAccessWr( pMeiDynCntrl, pLocalArgument); + + /* return arguments - count */ +- copy_to_user( (void *)&pUserArgument->count, +- (void *)&pLocalArgument->count, +- sizeof(pUserArgument->count) ) ; ++ if ( ret == IFX_SUCCESS && ++ copy_to_user( (void *)&pUserArgument->count, ++ (void *)&pLocalArgument->count, ++ sizeof(pUserArgument->count) ) ) ++ ret = -e_MEI_ERR_RETURN_ARG; + + return ret; + } +@@ -3278,16 +3329,18 @@ static int MEI_IoctlMeiDbgAccessRd_Wrap( + if ( pLocalArgument->count ) + { + /* return the buffer */ +- copy_to_user( pUserBuf, +- pLocalArgument->pData_32, +- pLocalArgument->count * sizeof(IFX_uint32_t) ) ; ++ if ( copy_to_user( pUserBuf, ++ pLocalArgument->pData_32, ++ pLocalArgument->count * sizeof(IFX_uint32_t) ) ) ++ ret = -e_MEI_ERR_RETURN_ARG; + + } + + /* return count argument */ +- copy_to_user( (void *)&pUserArgument->count, +- (void *)&pLocalArgument->count, +- sizeof(pUserArgument->count) ) ; ++ if ( copy_to_user( (void *)&pUserArgument->count, ++ (void *)&pLocalArgument->count, ++ sizeof(pUserArgument->count) ) ) ++ ret = -e_MEI_ERR_RETURN_ARG; + + return ret; + } --- a/src/drv_mei_cpe_api_atm_ptm_intern.c +++ b/src/drv_mei_cpe_api_atm_ptm_intern.c @@ -147,6 +147,7 @@ IFX_int32_t MEI_InternalXtmSwhowtimeExit diff --git a/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/101_no-date-time.patch b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/101_no-date-time.patch index 055797ad4d..9785bfc4c1 100644 --- a/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/101_no-date-time.patch +++ b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/101_no-date-time.patch @@ -1,6 +1,6 @@ --- a/src/drv_mei_cpe_linux.c +++ b/src/drv_mei_cpe_linux.c -@@ -1503,8 +1503,8 @@ struct proc_entry { +@@ -1505,8 +1505,8 @@ struct proc_entry { static void MEI_GetVersionProc(struct seq_file *s) { seq_printf(s, "%s" MEI_DRV_CRLF, &MEI_WHATVERSION[4]); @@ -11,3 +11,13 @@ } /** +@@ -4233,7 +4233,9 @@ module_exit (MEI_module_exit); + #ifdef MODULE + MODULE_AUTHOR("www.lantiq.com"); + MODULE_DESCRIPTION("MEI CPE Driver - www.lantiq.com"); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,11,0)) + MODULE_SUPPORTED_DEVICE("MEI CPE Interface"); ++#endif + MODULE_LICENSE ("GPL"); + #endif /* #ifdef MODULE*/ + diff --git a/package/kernel/lantiq/ltq-vmmc/patches/200-compat.patch b/package/kernel/lantiq/ltq-vmmc/patches/200-compat.patch index bf9f17ed05..dd6451b52d 100644 --- a/package/kernel/lantiq/ltq-vmmc/patches/200-compat.patch +++ b/package/kernel/lantiq/ltq-vmmc/patches/200-compat.patch @@ -9,6 +9,16 @@ /* ============================= */ /* Local Macros & Definitions */ /* ============================= */ +@@ -862,7 +864,9 @@ void vmmc_module_exit(void) + #ifdef MODULE + MODULE_DESCRIPTION("VMMC(VoiceMacroMipsCore) device driver - www.lantiq.com"); + MODULE_AUTHOR("Lantiq Deutschland GmbH"); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,11,0)) + MODULE_SUPPORTED_DEVICE("DANUBE, TWINPASS, INCA-IP2, AR9, VR9"); ++#endif + MODULE_LICENSE("Dual BSD/GPL"); + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17)) --- a/src/mps/drv_mps_vmmc_linux.c +++ b/src/mps/drv_mps_vmmc_linux.c @@ -80,11 +80,15 @@ diff --git a/package/kernel/linux/modules/crypto.mk b/package/kernel/linux/modules/crypto.mk index f8af5f0a3b..83048e50d3 100644 --- a/package/kernel/linux/modules/crypto.mk +++ b/package/kernel/linux/modules/crypto.mk @@ -727,10 +727,10 @@ ifndef CONFIG_TARGET_x86_64 FILES+= \ $(LINUX_DIR)/arch/x86/crypto/twofish-i586.ko \ $(LINUX_DIR)/arch/x86/crypto/serpent-sse2-i586.ko \ - $(LINUX_DIR)/arch/x86/crypto/glue_helper.ko \ + $(LINUX_DIR)/arch/x86/crypto/glue_helper.ko@lt5.12 \ $(LINUX_DIR)/crypto/cryptd.ko \ $(LINUX_DIR)/crypto/crypto_simd.ko - AUTOLOAD+= $(call AutoLoad,10,cryptd glue_helper \ + AUTOLOAD+= $(call AutoLoad,10,cryptd glue_helper@lt5.12 \ serpent-sse2-i586 twofish-i586 blowfish_generic) endef endif diff --git a/package/kernel/mac80211/Makefile b/package/kernel/mac80211/Makefile index 44428ca89f..91dad18254 100644 --- a/package/kernel/mac80211/Makefile +++ b/package/kernel/mac80211/Makefile @@ -10,10 +10,10 @@ include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=mac80211 -PKG_VERSION:=5.15.58-1 -PKG_RELEASE:=2 -PKG_SOURCE_URL:=@KERNEL/linux/kernel/projects/backports/stable/v5.15.58/ -PKG_HASH:=a3c2a2b7bbaf8943c65fd72f4e7d7ad5e205aeae28b26c835f9d8afa0f9810bf +PKG_VERSION:=5.15.74-1 +PKG_RELEASE:=1 +PKG_SOURCE_URL:=@KERNEL/linux/kernel/projects/backports/stable/v5.15.74/ +PKG_HASH:=98098d0cab24cc76a04db738dc746a0c8d38d180398805481224f141cca06423 PKG_SOURCE:=backports-$(PKG_VERSION).tar.xz PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/backports-$(PKG_VERSION) @@ -426,8 +426,8 @@ ifeq ($(BUILD_VARIANT),smallbuffers) C_DEFINES+= -DCONFIG_ATH10K_SMALLBUFFERS endif -MAKE_OPTS:= -C "$(PKG_BUILD_DIR)" \ - $(KERNEL_MAKE_FLAGS) \ +MAKE_OPTS:= \ + $(subst -C $(LINUX_DIR),-C "$(PKG_BUILD_DIR)",$(KERNEL_MAKEOPTS)) \ EXTRA_CFLAGS="-I$(PKG_BUILD_DIR)/include $(IREMAP_CFLAGS) $(C_DEFINES)" \ KLIB_BUILD="$(LINUX_DIR)" \ MODPROBE=true \ diff --git a/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch b/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch index 8fa3924e60..396e66ac22 100644 --- a/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch +++ b/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch @@ -152,7 +152,7 @@ Signed-off-by: Pali Rohár --- a/drivers/net/wireless/marvell/mwifiex/main.h +++ b/drivers/net/wireless/marvell/mwifiex/main.h -@@ -1106,6 +1106,8 @@ void mwifiex_cancel_all_pending_cmd(stru +@@ -1108,6 +1108,8 @@ void mwifiex_cancel_all_pending_cmd(stru void mwifiex_cancel_pending_scan_cmd(struct mwifiex_adapter *adapter); void mwifiex_cancel_scan(struct mwifiex_adapter *adapter); diff --git a/package/kernel/mac80211/patches/subsys/303-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch b/package/kernel/mac80211/patches/subsys/303-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch index 1ceb2be25c..159aad564b 100644 --- a/package/kernel/mac80211/patches/subsys/303-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch +++ b/package/kernel/mac80211/patches/subsys/303-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch @@ -52,7 +52,7 @@ Signed-off-by: Xing Song --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c -@@ -2948,6 +2948,7 @@ ieee80211_rx_h_mesh_fwding(struct ieee80 +@@ -2950,6 +2950,7 @@ ieee80211_rx_h_mesh_fwding(struct ieee80 if (!fwd_skb) goto out; diff --git a/package/kernel/mac80211/patches/subsys/307-mac80211_hwsim-make-6-GHz-channels-usable.patch b/package/kernel/mac80211/patches/subsys/307-mac80211_hwsim-make-6-GHz-channels-usable.patch index fba0912e80..80c86e3d92 100644 --- a/package/kernel/mac80211/patches/subsys/307-mac80211_hwsim-make-6-GHz-channels-usable.patch +++ b/package/kernel/mac80211/patches/subsys/307-mac80211_hwsim-make-6-GHz-channels-usable.patch @@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/wireless/mac80211_hwsim.c +++ b/drivers/net/wireless/mac80211_hwsim.c -@@ -3004,15 +3004,19 @@ static void mac80211_hwsim_he_capab(stru +@@ -3003,15 +3003,19 @@ static void mac80211_hwsim_he_capab(stru { u16 n_iftype_data; @@ -34,7 +34,7 @@ Signed-off-by: Felix Fietkau return; } -@@ -3302,6 +3306,12 @@ static int mac80211_hwsim_new_radio(stru +@@ -3301,6 +3305,12 @@ static int mac80211_hwsim_new_radio(stru sband->vht_cap.vht_mcs.tx_mcs_map = sband->vht_cap.vht_mcs.rx_mcs_map; break; @@ -47,7 +47,7 @@ Signed-off-by: Felix Fietkau case NL80211_BAND_S1GHZ: memcpy(&sband->s1g_cap, &hwsim_s1g_cap, sizeof(sband->s1g_cap)); -@@ -3312,6 +3322,13 @@ static int mac80211_hwsim_new_radio(stru +@@ -3311,6 +3321,13 @@ static int mac80211_hwsim_new_radio(stru continue; } @@ -61,7 +61,7 @@ Signed-off-by: Felix Fietkau sband->ht_cap.ht_supported = true; sband->ht_cap.cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_GRN_FLD | -@@ -3325,10 +3342,6 @@ static int mac80211_hwsim_new_radio(stru +@@ -3324,10 +3341,6 @@ static int mac80211_hwsim_new_radio(stru sband->ht_cap.mcs.rx_mask[0] = 0xff; sband->ht_cap.mcs.rx_mask[1] = 0xff; sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; diff --git a/package/kernel/mac80211/patches/subsys/308-mac80211-add-support-for-.ndo_fill_forward_path.patch b/package/kernel/mac80211/patches/subsys/308-mac80211-add-support-for-.ndo_fill_forward_path.patch index 4b9d874cfe..a9a6182ab2 100644 --- a/package/kernel/mac80211/patches/subsys/308-mac80211-add-support-for-.ndo_fill_forward_path.patch +++ b/package/kernel/mac80211/patches/subsys/308-mac80211-add-support-for-.ndo_fill_forward_path.patch @@ -69,7 +69,7 @@ Signed-off-by: Johannes Berg #endif /* __MAC80211_DRIVER_OPS */ --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h -@@ -1490,7 +1490,7 @@ struct ieee80211_local { +@@ -1489,7 +1489,7 @@ struct ieee80211_local { }; static inline struct ieee80211_sub_if_data * diff --git a/package/kernel/mac80211/patches/subsys/324-mac80211-MBSSID-beacon-handling-in-AP-mode.patch b/package/kernel/mac80211/patches/subsys/324-mac80211-MBSSID-beacon-handling-in-AP-mode.patch index fdbcce9450..e2b05719db 100644 --- a/package/kernel/mac80211/patches/subsys/324-mac80211-MBSSID-beacon-handling-in-AP-mode.patch +++ b/package/kernel/mac80211/patches/subsys/324-mac80211-MBSSID-beacon-handling-in-AP-mode.patch @@ -246,7 +246,7 @@ Signed-off-by: Johannes Berg struct rcu_head rcu_head; }; -@@ -1083,6 +1084,20 @@ ieee80211_vif_get_shift(struct ieee80211 +@@ -1082,6 +1083,20 @@ ieee80211_vif_get_shift(struct ieee80211 return shift; } diff --git a/package/kernel/mac80211/patches/subsys/330-mac80211-switch-airtime-fairness-back-to-deficit-rou.patch b/package/kernel/mac80211/patches/subsys/330-mac80211-switch-airtime-fairness-back-to-deficit-rou.patch index 0ca53860a5..e59036f5a2 100644 --- a/package/kernel/mac80211/patches/subsys/330-mac80211-switch-airtime-fairness-back-to-deficit-rou.patch +++ b/package/kernel/mac80211/patches/subsys/330-mac80211-switch-airtime-fairness-back-to-deficit-rou.patch @@ -327,7 +327,7 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h -@@ -863,16 +863,20 @@ enum txq_info_flags { +@@ -862,16 +862,20 @@ enum txq_info_flags { * @def_flow: used as a fallback flow when a packet destined to @tin hashes to * a fq_flow which is already owned by a different tin * @def_cvars: codel vars for @def_flow @@ -350,7 +350,7 @@ Signed-off-by: Felix Fietkau unsigned long flags; /* keep last! */ -@@ -949,8 +953,6 @@ struct ieee80211_sub_if_data { +@@ -948,8 +952,6 @@ struct ieee80211_sub_if_data { struct ieee80211_tx_queue_params tx_conf[IEEE80211_NUM_ACS]; struct mac80211_qos_map __rcu *qos_map; @@ -359,7 +359,7 @@ Signed-off-by: Felix Fietkau struct work_struct csa_finalize_work; bool csa_block_tx; /* write-protected by sdata_lock and local->mtx */ struct cfg80211_chan_def csa_chandef; -@@ -1185,44 +1187,6 @@ enum mac80211_scan_state { +@@ -1184,44 +1186,6 @@ enum mac80211_scan_state { SCAN_ABORT, }; @@ -404,7 +404,7 @@ Signed-off-by: Felix Fietkau DECLARE_STATIC_KEY_FALSE(aql_disable); struct ieee80211_local { -@@ -1236,8 +1200,13 @@ struct ieee80211_local { +@@ -1235,8 +1199,13 @@ struct ieee80211_local { struct codel_params cparams; /* protects active_txqs and txqi->schedule_order */ @@ -419,7 +419,7 @@ Signed-off-by: Felix Fietkau u32 aql_threshold; atomic_t aql_total_pending_airtime; -@@ -1654,125 +1623,6 @@ static inline bool txq_has_queue(struct +@@ -1660,125 +1629,6 @@ static inline bool txq_has_queue(struct return !(skb_queue_empty(&txqi->frags) && !txqi->tin.backlog_packets); } @@ -545,7 +545,7 @@ Signed-off-by: Felix Fietkau static inline int ieee80211_bssid_match(const u8 *raddr, const u8 *addr) { return ether_addr_equal(raddr, addr) || -@@ -2018,14 +1868,6 @@ int ieee80211_tx_control_port(struct wip +@@ -2024,14 +1874,6 @@ int ieee80211_tx_control_port(struct wip u64 *cookie); int ieee80211_probe_mesh_link(struct wiphy *wiphy, struct net_device *dev, const u8 *buf, size_t len); diff --git a/package/kernel/mac80211/patches/subsys/334-mac80211-add-a-per-PHY-AQL-limit-to-improve-fairness.patch b/package/kernel/mac80211/patches/subsys/334-mac80211-add-a-per-PHY-AQL-limit-to-improve-fairness.patch index 42e1671ed6..fb6fd6eac6 100644 --- a/package/kernel/mac80211/patches/subsys/334-mac80211-add-a-per-PHY-AQL-limit-to-improve-fairness.patch +++ b/package/kernel/mac80211/patches/subsys/334-mac80211-add-a-per-PHY-AQL-limit-to-improve-fairness.patch @@ -15,7 +15,7 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h -@@ -1216,6 +1216,7 @@ struct ieee80211_local { +@@ -1215,6 +1215,7 @@ struct ieee80211_local { u32 aql_txq_limit_high[IEEE80211_NUM_ACS]; u32 aql_threshold; atomic_t aql_total_pending_airtime; diff --git a/package/kernel/mac80211/patches/subsys/343-wifi-mac80211-fix-decap-offload-for-stations-on-AP_V.patch b/package/kernel/mac80211/patches/subsys/343-wifi-mac80211-fix-decap-offload-for-stations-on-AP_V.patch index 0feb408d21..0246785475 100644 --- a/package/kernel/mac80211/patches/subsys/343-wifi-mac80211-fix-decap-offload-for-stations-on-AP_V.patch +++ b/package/kernel/mac80211/patches/subsys/343-wifi-mac80211-fix-decap-offload-for-stations-on-AP_V.patch @@ -13,7 +13,7 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c -@@ -4265,6 +4265,7 @@ void ieee80211_check_fast_rx(struct sta_ +@@ -4267,6 +4267,7 @@ void ieee80211_check_fast_rx(struct sta_ .vif_type = sdata->vif.type, .control_port_protocol = sdata->control_port_protocol, }, *old, *new = NULL; @@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau bool set_offload = false; bool assign = false; bool offload; -@@ -4380,10 +4381,10 @@ void ieee80211_check_fast_rx(struct sta_ +@@ -4382,10 +4383,10 @@ void ieee80211_check_fast_rx(struct sta_ if (assign) new = kmemdup(&fastrx, sizeof(fastrx), GFP_KERNEL); diff --git a/package/kernel/mac80211/patches/subsys/345-wifi-mac80211-do-not-drop-packets-smaller-than-the-L.patch b/package/kernel/mac80211/patches/subsys/345-wifi-mac80211-do-not-drop-packets-smaller-than-the-L.patch index 16cafc447c..23047f68c9 100644 --- a/package/kernel/mac80211/patches/subsys/345-wifi-mac80211-do-not-drop-packets-smaller-than-the-L.patch +++ b/package/kernel/mac80211/patches/subsys/345-wifi-mac80211-do-not-drop-packets-smaller-than-the-L.patch @@ -14,7 +14,7 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c -@@ -4601,7 +4601,7 @@ static bool ieee80211_invoke_fast_rx(str +@@ -4603,7 +4603,7 @@ static bool ieee80211_invoke_fast_rx(str if (!(status->rx_flags & IEEE80211_RX_AMSDU)) { if (!pskb_may_pull(skb, snap_offs + sizeof(*payload))) diff --git a/package/kernel/mac80211/patches/subsys/346-mac80211-mesh-clean-up-rx_bcn_presp-API.patch b/package/kernel/mac80211/patches/subsys/346-mac80211-mesh-clean-up-rx_bcn_presp-API.patch deleted file mode 100644 index 3fa70b05fd..0000000000 --- a/package/kernel/mac80211/patches/subsys/346-mac80211-mesh-clean-up-rx_bcn_presp-API.patch +++ /dev/null @@ -1,110 +0,0 @@ -From: Johannes Berg -Date: Mon, 20 Sep 2021 15:40:07 +0200 -Subject: [PATCH] mac80211: mesh: clean up rx_bcn_presp API - -commit a5b983c6073140b624f64e79fea6d33c3e4315a0 upstream. - -We currently pass the entire elements to the rx_bcn_presp() -method, but only need mesh_config. Additionally, we use the -length of the elements to calculate back the entire frame's -length, but that's confusing - just pass the length of the -frame instead. - -Link: https://lore.kernel.org/r/20210920154009.a18ed3d2da6c.I1824b773a0fbae4453e1433c184678ca14e8df45@changeid -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/ieee80211_i.h -+++ b/net/mac80211/ieee80211_i.h -@@ -645,10 +645,9 @@ struct ieee80211_if_ocb { - */ - struct ieee802_11_elems; - struct ieee80211_mesh_sync_ops { -- void (*rx_bcn_presp)(struct ieee80211_sub_if_data *sdata, -- u16 stype, -- struct ieee80211_mgmt *mgmt, -- struct ieee802_11_elems *elems, -+ void (*rx_bcn_presp)(struct ieee80211_sub_if_data *sdata, u16 stype, -+ struct ieee80211_mgmt *mgmt, unsigned int len, -+ const struct ieee80211_meshconf_ie *mesh_cfg, - struct ieee80211_rx_status *rx_status); - - /* should be called with beacon_data under RCU read lock */ ---- a/net/mac80211/mesh.c -+++ b/net/mac80211/mesh.c -@@ -1354,8 +1354,8 @@ static void ieee80211_mesh_rx_bcn_presp( - } - - if (ifmsh->sync_ops) -- ifmsh->sync_ops->rx_bcn_presp(sdata, -- stype, mgmt, &elems, rx_status); -+ ifmsh->sync_ops->rx_bcn_presp(sdata, stype, mgmt, len, -+ elems.mesh_config, rx_status); - } - - int ieee80211_mesh_finish_csa(struct ieee80211_sub_if_data *sdata) ---- a/net/mac80211/mesh_sync.c -+++ b/net/mac80211/mesh_sync.c -@@ -3,6 +3,7 @@ - * Copyright 2011-2012, Pavel Zubarev - * Copyright 2011-2012, Marco Porsch - * Copyright 2011-2012, cozybit Inc. -+ * Copyright (C) 2021 Intel Corporation - */ - - #include "ieee80211_i.h" -@@ -35,12 +36,12 @@ struct sync_method { - /** - * mesh_peer_tbtt_adjusting - check if an mp is currently adjusting its TBTT - * -- * @ie: information elements of a management frame from the mesh peer -+ * @cfg: mesh config element from the mesh peer (or %NULL) - */ --static bool mesh_peer_tbtt_adjusting(struct ieee802_11_elems *ie) -+static bool mesh_peer_tbtt_adjusting(const struct ieee80211_meshconf_ie *cfg) - { -- return (ie->mesh_config->meshconf_cap & -- IEEE80211_MESHCONF_CAPAB_TBTT_ADJUSTING) != 0; -+ return cfg && -+ (cfg->meshconf_cap & IEEE80211_MESHCONF_CAPAB_TBTT_ADJUSTING); - } - - void mesh_sync_adjust_tsf(struct ieee80211_sub_if_data *sdata) -@@ -76,11 +77,11 @@ void mesh_sync_adjust_tsf(struct ieee802 - } - } - --static void mesh_sync_offset_rx_bcn_presp(struct ieee80211_sub_if_data *sdata, -- u16 stype, -- struct ieee80211_mgmt *mgmt, -- struct ieee802_11_elems *elems, -- struct ieee80211_rx_status *rx_status) -+static void -+mesh_sync_offset_rx_bcn_presp(struct ieee80211_sub_if_data *sdata, u16 stype, -+ struct ieee80211_mgmt *mgmt, unsigned int len, -+ const struct ieee80211_meshconf_ie *mesh_cfg, -+ struct ieee80211_rx_status *rx_status) - { - struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; - struct ieee80211_local *local = sdata->local; -@@ -101,10 +102,7 @@ static void mesh_sync_offset_rx_bcn_pres - */ - if (ieee80211_have_rx_timestamp(rx_status)) - t_r = ieee80211_calculate_rx_timestamp(local, rx_status, -- 24 + 12 + -- elems->total_len + -- FCS_LEN, -- 24); -+ len + FCS_LEN, 24); - else - t_r = drv_get_tsf(local, sdata); - -@@ -119,7 +117,7 @@ static void mesh_sync_offset_rx_bcn_pres - * dot11MeshNbrOffsetMaxNeighbor non-peer non-MBSS neighbors - */ - -- if (elems->mesh_config && mesh_peer_tbtt_adjusting(elems)) { -+ if (mesh_peer_tbtt_adjusting(mesh_cfg)) { - msync_dbg(sdata, "STA %pM : is adjusting TBTT\n", - sta->sta.addr); - goto no_sync; diff --git a/package/kernel/mac80211/patches/subsys/347-mac80211-move-CRC-into-struct-ieee802_11_elems.patch b/package/kernel/mac80211/patches/subsys/347-mac80211-move-CRC-into-struct-ieee802_11_elems.patch deleted file mode 100644 index e44aac5cba..0000000000 --- a/package/kernel/mac80211/patches/subsys/347-mac80211-move-CRC-into-struct-ieee802_11_elems.patch +++ /dev/null @@ -1,82 +0,0 @@ -From: Johannes Berg -Date: Mon, 20 Sep 2021 15:40:08 +0200 -Subject: [PATCH] mac80211: move CRC into struct ieee802_11_elems - -commit c6e37ed498f958254b5459253199e816b6bfc52f upstream. - -We're currently returning this value, but to prepare for -returning the allocated structure, move it into there. - -Link: https://lore.kernel.org/r/20210920154009.479b8ebf999d.If0d4ba75ee38998dc3eeae25058aa748efcb2fc9@changeid -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/ieee80211_i.h -+++ b/net/mac80211/ieee80211_i.h -@@ -1530,6 +1530,7 @@ struct ieee80211_csa_ie { - struct ieee802_11_elems { - const u8 *ie_start; - size_t total_len; -+ u32 crc; - - /* pointers to IEs */ - const struct ieee80211_tdls_lnkie *lnk_id; -@@ -2089,10 +2090,10 @@ static inline void ieee80211_tx_skb(stru - ieee80211_tx_skb_tid(sdata, skb, 7); - } - --u32 ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, -- struct ieee802_11_elems *elems, -- u64 filter, u32 crc, u8 *transmitter_bssid, -- u8 *bss_bssid); -+void ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, -+ struct ieee802_11_elems *elems, -+ u64 filter, u32 crc, u8 *transmitter_bssid, -+ u8 *bss_bssid); - static inline void ieee802_11_parse_elems(const u8 *start, size_t len, - bool action, - struct ieee802_11_elems *elems, ---- a/net/mac80211/mlme.c -+++ b/net/mac80211/mlme.c -@@ -4102,10 +4102,11 @@ static void ieee80211_rx_mgmt_beacon(str - */ - if (!ieee80211_is_s1g_beacon(hdr->frame_control)) - ncrc = crc32_be(0, (void *)&mgmt->u.beacon.beacon_int, 4); -- ncrc = ieee802_11_parse_elems_crc(variable, -- len - baselen, false, &elems, -- care_about_ies, ncrc, -- mgmt->bssid, bssid); -+ ieee802_11_parse_elems_crc(variable, -+ len - baselen, false, &elems, -+ care_about_ies, ncrc, -+ mgmt->bssid, bssid); -+ ncrc = elems.crc; - - if (ieee80211_hw_check(&local->hw, PS_NULLFUNC_STACK) && - ieee80211_check_tim(elems.tim, elems.tim_len, bss_conf->aid)) { ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -1469,10 +1469,10 @@ static size_t ieee802_11_find_bssid_prof - return found ? profile_len : 0; - } - --u32 ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, -- struct ieee802_11_elems *elems, -- u64 filter, u32 crc, u8 *transmitter_bssid, -- u8 *bss_bssid) -+void ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, -+ struct ieee802_11_elems *elems, -+ u64 filter, u32 crc, u8 *transmitter_bssid, -+ u8 *bss_bssid) - { - const struct element *non_inherit = NULL; - u8 *nontransmitted_profile; -@@ -1524,7 +1524,7 @@ u32 ieee802_11_parse_elems_crc(const u8 - - kfree(nontransmitted_profile); - -- return crc; -+ elems->crc = crc; - } - - void ieee80211_regulatory_limit_wmm_params(struct ieee80211_sub_if_data *sdata, diff --git a/package/kernel/mac80211/patches/subsys/348-mac80211-mlme-find-auth-challenge-directly.patch b/package/kernel/mac80211/patches/subsys/348-mac80211-mlme-find-auth-challenge-directly.patch deleted file mode 100644 index 3432c25a91..0000000000 --- a/package/kernel/mac80211/patches/subsys/348-mac80211-mlme-find-auth-challenge-directly.patch +++ /dev/null @@ -1,80 +0,0 @@ -From: Johannes Berg -Date: Mon, 20 Sep 2021 15:40:09 +0200 -Subject: [PATCH] mac80211: mlme: find auth challenge directly - -commit 49a765d6785e99157ff5091cc37485732496864e upstream. - -There's no need to parse all elements etc. just to find the -authentication challenge - use cfg80211_find_elem() instead. -This also allows us to remove WLAN_EID_CHALLENGE handling -from the element parsing entirely. - -Link: https://lore.kernel.org/r/20210920154009.45f9b3a15722.Ice3159ffad03a007d6154cbf1fb3a8c48489e86f@changeid -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/ieee80211_i.h -+++ b/net/mac80211/ieee80211_i.h -@@ -1540,7 +1540,6 @@ struct ieee802_11_elems { - const u8 *supp_rates; - const u8 *ds_params; - const struct ieee80211_tim_ie *tim; -- const u8 *challenge; - const u8 *rsn; - const u8 *rsnx; - const u8 *erp_info; -@@ -1594,7 +1593,6 @@ struct ieee802_11_elems { - u8 ssid_len; - u8 supp_rates_len; - u8 tim_len; -- u8 challenge_len; - u8 rsn_len; - u8 rsnx_len; - u8 ext_supp_rates_len; ---- a/net/mac80211/mlme.c -+++ b/net/mac80211/mlme.c -@@ -2889,17 +2889,17 @@ static void ieee80211_auth_challenge(str - { - struct ieee80211_local *local = sdata->local; - struct ieee80211_mgd_auth_data *auth_data = sdata->u.mgd.auth_data; -+ const struct element *challenge; - u8 *pos; -- struct ieee802_11_elems elems; - u32 tx_flags = 0; - struct ieee80211_prep_tx_info info = { - .subtype = IEEE80211_STYPE_AUTH, - }; - - pos = mgmt->u.auth.variable; -- ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, &elems, -- mgmt->bssid, auth_data->bss->bssid); -- if (!elems.challenge) -+ challenge = cfg80211_find_elem(WLAN_EID_CHALLENGE, pos, -+ len - (pos - (u8 *)mgmt)); -+ if (!challenge) - return; - auth_data->expected_transaction = 4; - drv_mgd_prepare_tx(sdata->local, sdata, &info); -@@ -2907,7 +2907,8 @@ static void ieee80211_auth_challenge(str - tx_flags = IEEE80211_TX_CTL_REQ_TX_STATUS | - IEEE80211_TX_INTFL_MLME_CONN_TX; - ieee80211_send_auth(sdata, 3, auth_data->algorithm, 0, -- elems.challenge - 2, elems.challenge_len + 2, -+ (void *)challenge, -+ challenge->datalen + sizeof(*challenge), - auth_data->bss->bssid, auth_data->bss->bssid, - auth_data->key, auth_data->key_len, - auth_data->key_idx, tx_flags); ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -1120,10 +1120,6 @@ _ieee802_11_parse_elems_crc(const u8 *st - } else - elem_parse_failed = true; - break; -- case WLAN_EID_CHALLENGE: -- elems->challenge = pos; -- elems->challenge_len = elen; -- break; - case WLAN_EID_VENDOR_SPECIFIC: - if (elen >= 4 && pos[0] == 0x00 && pos[1] == 0x50 && - pos[2] == 0xf2) { diff --git a/package/kernel/mac80211/patches/subsys/349-mac80211-always-allocate-struct-ieee802_11_elems.patch b/package/kernel/mac80211/patches/subsys/349-mac80211-always-allocate-struct-ieee802_11_elems.patch deleted file mode 100644 index 75655279a9..0000000000 --- a/package/kernel/mac80211/patches/subsys/349-mac80211-always-allocate-struct-ieee802_11_elems.patch +++ /dev/null @@ -1,1143 +0,0 @@ -From: Johannes Berg -Date: Mon, 20 Sep 2021 15:40:10 +0200 -Subject: [PATCH] mac80211: always allocate struct ieee802_11_elems - -As the 802.11 spec evolves, we need to parse more and more -elements. This is causing the struct to grow, and we can no -longer get away with putting it on the stack. - -Change the API to always dynamically allocate and return an -allocated pointer that must be kfree()d later. - -As an alternative, I contemplated a scheme whereby we'd say -in the code which elements we needed, e.g. - - DECLARE_ELEMENT_PARSER(elems, - SUPPORTED_CHANNELS, - CHANNEL_SWITCH, - EXT(KEY_DELIVERY)); - - ieee802_11_parse_elems(..., &elems, ...); - -and while I think this is possible and will save us a lot -since most individual places only care about a small subset -of the elements, it ended up being a bit more work since a -lot of places do the parsing and then pass the struct to -other functions, sometimes with multiple levels. - -Link: https://lore.kernel.org/r/20210920154009.26caff6b5998.I05ae58768e990e611aee8eca8abefd9d7bc15e05@changeid -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/agg-rx.c -+++ b/net/mac80211/agg-rx.c -@@ -478,7 +478,7 @@ void ieee80211_process_addba_request(str - size_t len) - { - u16 capab, tid, timeout, ba_policy, buf_size, start_seq_num; -- struct ieee802_11_elems elems = { }; -+ struct ieee802_11_elems *elems = NULL; - u8 dialog_token; - int ies_len; - -@@ -496,16 +496,17 @@ void ieee80211_process_addba_request(str - ies_len = len - offsetof(struct ieee80211_mgmt, - u.action.u.addba_req.variable); - if (ies_len) { -- ieee802_11_parse_elems(mgmt->u.action.u.addba_req.variable, -- ies_len, true, &elems, mgmt->bssid, NULL); -- if (elems.parse_error) -+ elems = ieee802_11_parse_elems(mgmt->u.action.u.addba_req.variable, -+ ies_len, true, mgmt->bssid, NULL); -+ if (!elems || elems->parse_error) - return; - } - - __ieee80211_start_rx_ba_session(sta, dialog_token, timeout, - start_seq_num, ba_policy, tid, - buf_size, true, false, -- elems.addba_ext_ie); -+ elems ? elems->addba_ext_ie : NULL); -+ kfree(elems); - } - - void ieee80211_manage_rx_ba_offl(struct ieee80211_vif *vif, ---- a/net/mac80211/ibss.c -+++ b/net/mac80211/ibss.c -@@ -9,7 +9,7 @@ - * Copyright 2009, Johannes Berg - * Copyright 2013-2014 Intel Mobile Communications GmbH - * Copyright(c) 2016 Intel Deutschland GmbH -- * Copyright(c) 2018-2020 Intel Corporation -+ * Copyright(c) 2018-2021 Intel Corporation - */ - - #include -@@ -1589,7 +1589,7 @@ void ieee80211_rx_mgmt_probe_beacon(stru - struct ieee80211_rx_status *rx_status) - { - size_t baselen; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - - BUILD_BUG_ON(offsetof(typeof(mgmt->u.probe_resp), variable) != - offsetof(typeof(mgmt->u.beacon), variable)); -@@ -1602,10 +1602,14 @@ void ieee80211_rx_mgmt_probe_beacon(stru - if (baselen > len) - return; - -- ieee802_11_parse_elems(mgmt->u.probe_resp.variable, len - baselen, -- false, &elems, mgmt->bssid, NULL); -- -- ieee80211_rx_bss_info(sdata, mgmt, len, rx_status, &elems); -+ elems = ieee802_11_parse_elems(mgmt->u.probe_resp.variable, -+ len - baselen, false, -+ mgmt->bssid, NULL); -+ -+ if (elems) { -+ ieee80211_rx_bss_info(sdata, mgmt, len, rx_status, elems); -+ kfree(elems); -+ } - } - - void ieee80211_ibss_rx_queued_mgmt(struct ieee80211_sub_if_data *sdata, -@@ -1614,7 +1618,7 @@ void ieee80211_ibss_rx_queued_mgmt(struc - struct ieee80211_rx_status *rx_status; - struct ieee80211_mgmt *mgmt; - u16 fc; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - int ies_len; - - rx_status = IEEE80211_SKB_RXCB(skb); -@@ -1651,15 +1655,16 @@ void ieee80211_ibss_rx_queued_mgmt(struc - if (ies_len < 0) - break; - -- ieee802_11_parse_elems( -+ elems = ieee802_11_parse_elems( - mgmt->u.action.u.chan_switch.variable, -- ies_len, true, &elems, mgmt->bssid, NULL); -+ ies_len, true, mgmt->bssid, NULL); - -- if (elems.parse_error) -+ if (!elems || elems->parse_error) - break; - - ieee80211_rx_mgmt_spectrum_mgmt(sdata, mgmt, skb->len, -- rx_status, &elems); -+ rx_status, elems); -+ kfree(elems); - break; - } - } ---- a/net/mac80211/ieee80211_i.h -+++ b/net/mac80211/ieee80211_i.h -@@ -2088,18 +2088,18 @@ static inline void ieee80211_tx_skb(stru - ieee80211_tx_skb_tid(sdata, skb, 7); - } - --void ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, -- struct ieee802_11_elems *elems, -- u64 filter, u32 crc, u8 *transmitter_bssid, -- u8 *bss_bssid); --static inline void ieee802_11_parse_elems(const u8 *start, size_t len, -- bool action, -- struct ieee802_11_elems *elems, -- u8 *transmitter_bssid, -- u8 *bss_bssid) -+struct ieee802_11_elems *ieee802_11_parse_elems_crc(const u8 *start, size_t len, -+ bool action, -+ u64 filter, u32 crc, -+ const u8 *transmitter_bssid, -+ const u8 *bss_bssid); -+static inline struct ieee802_11_elems * -+ieee802_11_parse_elems(const u8 *start, size_t len, bool action, -+ const u8 *transmitter_bssid, -+ const u8 *bss_bssid) - { -- ieee802_11_parse_elems_crc(start, len, action, elems, 0, 0, -- transmitter_bssid, bss_bssid); -+ return ieee802_11_parse_elems_crc(start, len, action, 0, 0, -+ transmitter_bssid, bss_bssid); - } - - ---- a/net/mac80211/mesh.c -+++ b/net/mac80211/mesh.c -@@ -1247,7 +1247,7 @@ ieee80211_mesh_rx_probe_req(struct ieee8 - struct sk_buff *presp; - struct beacon_data *bcn; - struct ieee80211_mgmt *hdr; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - size_t baselen; - u8 *pos; - -@@ -1256,22 +1256,24 @@ ieee80211_mesh_rx_probe_req(struct ieee8 - if (baselen > len) - return; - -- ieee802_11_parse_elems(pos, len - baselen, false, &elems, mgmt->bssid, -- NULL); -- -- if (!elems.mesh_id) -+ elems = ieee802_11_parse_elems(pos, len - baselen, false, mgmt->bssid, -+ NULL); -+ if (!elems) - return; - -+ if (!elems->mesh_id) -+ goto free; -+ - /* 802.11-2012 10.1.4.3.2 */ - if ((!ether_addr_equal(mgmt->da, sdata->vif.addr) && - !is_broadcast_ether_addr(mgmt->da)) || -- elems.ssid_len != 0) -- return; -+ elems->ssid_len != 0) -+ goto free; - -- if (elems.mesh_id_len != 0 && -- (elems.mesh_id_len != ifmsh->mesh_id_len || -- memcmp(elems.mesh_id, ifmsh->mesh_id, ifmsh->mesh_id_len))) -- return; -+ if (elems->mesh_id_len != 0 && -+ (elems->mesh_id_len != ifmsh->mesh_id_len || -+ memcmp(elems->mesh_id, ifmsh->mesh_id, ifmsh->mesh_id_len))) -+ goto free; - - rcu_read_lock(); - bcn = rcu_dereference(ifmsh->beacon); -@@ -1295,6 +1297,8 @@ ieee80211_mesh_rx_probe_req(struct ieee8 - ieee80211_tx_skb(sdata, presp); - out: - rcu_read_unlock(); -+free: -+ kfree(elems); - } - - static void ieee80211_mesh_rx_bcn_presp(struct ieee80211_sub_if_data *sdata, -@@ -1305,7 +1309,7 @@ static void ieee80211_mesh_rx_bcn_presp( - { - struct ieee80211_local *local = sdata->local; - struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - struct ieee80211_channel *channel; - size_t baselen; - int freq; -@@ -1320,42 +1324,47 @@ static void ieee80211_mesh_rx_bcn_presp( - if (baselen > len) - return; - -- ieee802_11_parse_elems(mgmt->u.probe_resp.variable, len - baselen, -- false, &elems, mgmt->bssid, NULL); -+ elems = ieee802_11_parse_elems(mgmt->u.probe_resp.variable, -+ len - baselen, -+ false, mgmt->bssid, NULL); -+ if (!elems) -+ return; - - /* ignore non-mesh or secure / unsecure mismatch */ -- if ((!elems.mesh_id || !elems.mesh_config) || -- (elems.rsn && sdata->u.mesh.security == IEEE80211_MESH_SEC_NONE) || -- (!elems.rsn && sdata->u.mesh.security != IEEE80211_MESH_SEC_NONE)) -- return; -+ if ((!elems->mesh_id || !elems->mesh_config) || -+ (elems->rsn && sdata->u.mesh.security == IEEE80211_MESH_SEC_NONE) || -+ (!elems->rsn && sdata->u.mesh.security != IEEE80211_MESH_SEC_NONE)) -+ goto free; - -- if (elems.ds_params) -- freq = ieee80211_channel_to_frequency(elems.ds_params[0], band); -+ if (elems->ds_params) -+ freq = ieee80211_channel_to_frequency(elems->ds_params[0], band); - else - freq = rx_status->freq; - - channel = ieee80211_get_channel(local->hw.wiphy, freq); - - if (!channel || channel->flags & IEEE80211_CHAN_DISABLED) -- return; -+ goto free; - -- if (mesh_matches_local(sdata, &elems)) { -+ if (mesh_matches_local(sdata, elems)) { - mpl_dbg(sdata, "rssi_threshold=%d,rx_status->signal=%d\n", - sdata->u.mesh.mshcfg.rssi_threshold, rx_status->signal); - if (!sdata->u.mesh.user_mpm || - sdata->u.mesh.mshcfg.rssi_threshold == 0 || - sdata->u.mesh.mshcfg.rssi_threshold < rx_status->signal) -- mesh_neighbour_update(sdata, mgmt->sa, &elems, -+ mesh_neighbour_update(sdata, mgmt->sa, elems, - rx_status); - - if (ifmsh->csa_role != IEEE80211_MESH_CSA_ROLE_INIT && - !sdata->vif.csa_active) -- ieee80211_mesh_process_chnswitch(sdata, &elems, true); -+ ieee80211_mesh_process_chnswitch(sdata, elems, true); - } - - if (ifmsh->sync_ops) - ifmsh->sync_ops->rx_bcn_presp(sdata, stype, mgmt, len, -- elems.mesh_config, rx_status); -+ elems->mesh_config, rx_status); -+free: -+ kfree(elems); - } - - int ieee80211_mesh_finish_csa(struct ieee80211_sub_if_data *sdata) -@@ -1447,7 +1456,7 @@ static void mesh_rx_csa_frame(struct iee - struct ieee80211_mgmt *mgmt, size_t len) - { - struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - u16 pre_value; - bool fwd_csa = true; - size_t baselen; -@@ -1460,33 +1469,37 @@ static void mesh_rx_csa_frame(struct iee - pos = mgmt->u.action.u.chan_switch.variable; - baselen = offsetof(struct ieee80211_mgmt, - u.action.u.chan_switch.variable); -- ieee802_11_parse_elems(pos, len - baselen, true, &elems, -- mgmt->bssid, NULL); -- -- if (!mesh_matches_local(sdata, &elems)) -+ elems = ieee802_11_parse_elems(pos, len - baselen, true, -+ mgmt->bssid, NULL); -+ if (!elems) - return; - -- ifmsh->chsw_ttl = elems.mesh_chansw_params_ie->mesh_ttl; -+ if (!mesh_matches_local(sdata, elems)) -+ goto free; -+ -+ ifmsh->chsw_ttl = elems->mesh_chansw_params_ie->mesh_ttl; - if (!--ifmsh->chsw_ttl) - fwd_csa = false; - -- pre_value = le16_to_cpu(elems.mesh_chansw_params_ie->mesh_pre_value); -+ pre_value = le16_to_cpu(elems->mesh_chansw_params_ie->mesh_pre_value); - if (ifmsh->pre_value >= pre_value) -- return; -+ goto free; - - ifmsh->pre_value = pre_value; - - if (!sdata->vif.csa_active && -- !ieee80211_mesh_process_chnswitch(sdata, &elems, false)) { -+ !ieee80211_mesh_process_chnswitch(sdata, elems, false)) { - mcsa_dbg(sdata, "Failed to process CSA action frame"); -- return; -+ goto free; - } - - /* forward or re-broadcast the CSA frame */ - if (fwd_csa) { -- if (mesh_fwd_csa_frame(sdata, mgmt, len, &elems) < 0) -+ if (mesh_fwd_csa_frame(sdata, mgmt, len, elems) < 0) - mcsa_dbg(sdata, "Failed to forward the CSA frame"); - } -+free: -+ kfree(elems); - } - - static void ieee80211_mesh_rx_mgmt_action(struct ieee80211_sub_if_data *sdata, ---- a/net/mac80211/mesh_hwmp.c -+++ b/net/mac80211/mesh_hwmp.c -@@ -1,7 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0-only - /* - * Copyright (c) 2008, 2009 open80211s Ltd. -- * Copyright (C) 2019 Intel Corporation -+ * Copyright (C) 2019, 2021 Intel Corporation - * Author: Luis Carlos Cobo - */ - -@@ -908,7 +908,7 @@ static void hwmp_rann_frame_process(stru - void mesh_rx_path_sel_frame(struct ieee80211_sub_if_data *sdata, - struct ieee80211_mgmt *mgmt, size_t len) - { -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - size_t baselen; - u32 path_metric; - struct sta_info *sta; -@@ -926,37 +926,41 @@ void mesh_rx_path_sel_frame(struct ieee8 - rcu_read_unlock(); - - baselen = (u8 *) mgmt->u.action.u.mesh_action.variable - (u8 *) mgmt; -- ieee802_11_parse_elems(mgmt->u.action.u.mesh_action.variable, -- len - baselen, false, &elems, mgmt->bssid, NULL); -+ elems = ieee802_11_parse_elems(mgmt->u.action.u.mesh_action.variable, -+ len - baselen, false, mgmt->bssid, NULL); -+ if (!elems) -+ return; - -- if (elems.preq) { -- if (elems.preq_len != 37) -+ if (elems->preq) { -+ if (elems->preq_len != 37) - /* Right now we support just 1 destination and no AE */ -- return; -- path_metric = hwmp_route_info_get(sdata, mgmt, elems.preq, -+ goto free; -+ path_metric = hwmp_route_info_get(sdata, mgmt, elems->preq, - MPATH_PREQ); - if (path_metric) -- hwmp_preq_frame_process(sdata, mgmt, elems.preq, -+ hwmp_preq_frame_process(sdata, mgmt, elems->preq, - path_metric); - } -- if (elems.prep) { -- if (elems.prep_len != 31) -+ if (elems->prep) { -+ if (elems->prep_len != 31) - /* Right now we support no AE */ -- return; -- path_metric = hwmp_route_info_get(sdata, mgmt, elems.prep, -+ goto free; -+ path_metric = hwmp_route_info_get(sdata, mgmt, elems->prep, - MPATH_PREP); - if (path_metric) -- hwmp_prep_frame_process(sdata, mgmt, elems.prep, -+ hwmp_prep_frame_process(sdata, mgmt, elems->prep, - path_metric); - } -- if (elems.perr) { -- if (elems.perr_len != 15) -+ if (elems->perr) { -+ if (elems->perr_len != 15) - /* Right now we support only one destination per PERR */ -- return; -- hwmp_perr_frame_process(sdata, mgmt, elems.perr); -+ goto free; -+ hwmp_perr_frame_process(sdata, mgmt, elems->perr); - } -- if (elems.rann) -- hwmp_rann_frame_process(sdata, mgmt, elems.rann); -+ if (elems->rann) -+ hwmp_rann_frame_process(sdata, mgmt, elems->rann); -+free: -+ kfree(elems); - } - - /** ---- a/net/mac80211/mesh_plink.c -+++ b/net/mac80211/mesh_plink.c -@@ -1,7 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0-only - /* - * Copyright (c) 2008, 2009 open80211s Ltd. -- * Copyright (C) 2019 Intel Corporation -+ * Copyright (C) 2019, 2021 Intel Corporation - * Author: Luis Carlos Cobo - */ - #include -@@ -1200,7 +1200,7 @@ void mesh_rx_plink_frame(struct ieee8021 - struct ieee80211_mgmt *mgmt, size_t len, - struct ieee80211_rx_status *rx_status) - { -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - size_t baselen; - u8 *baseaddr; - -@@ -1228,7 +1228,8 @@ void mesh_rx_plink_frame(struct ieee8021 - if (baselen > len) - return; - } -- ieee802_11_parse_elems(baseaddr, len - baselen, true, &elems, -- mgmt->bssid, NULL); -- mesh_process_plink_frame(sdata, mgmt, &elems, rx_status); -+ elems = ieee802_11_parse_elems(baseaddr, len - baselen, true, -+ mgmt->bssid, NULL); -+ mesh_process_plink_frame(sdata, mgmt, elems, rx_status); -+ kfree(elems); - } ---- a/net/mac80211/mlme.c -+++ b/net/mac80211/mlme.c -@@ -3317,8 +3317,11 @@ static bool ieee80211_assoc_success(stru - aid = 0; /* TODO */ - } - capab_info = le16_to_cpu(mgmt->u.assoc_resp.capab_info); -- ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, elems, -- mgmt->bssid, assoc_data->bss->bssid); -+ elems = ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, -+ mgmt->bssid, assoc_data->bss->bssid); -+ -+ if (!elems) -+ return false; - - if (elems->aid_resp) - aid = le16_to_cpu(elems->aid_resp->aid); -@@ -3340,7 +3343,8 @@ static bool ieee80211_assoc_success(stru - - if (!is_s1g && !elems->supp_rates) { - sdata_info(sdata, "no SuppRates element in AssocResp\n"); -- return false; -+ ret = false; -+ goto out; - } - - sdata->vif.bss_conf.aid = aid; -@@ -3362,7 +3366,7 @@ static bool ieee80211_assoc_success(stru - (!(ifmgd->flags & IEEE80211_STA_DISABLE_VHT) && - (!elems->vht_cap_elem || !elems->vht_operation)))) { - const struct cfg80211_bss_ies *ies; -- struct ieee802_11_elems bss_elems; -+ struct ieee802_11_elems *bss_elems; - - rcu_read_lock(); - ies = rcu_dereference(cbss->ies); -@@ -3373,13 +3377,17 @@ static bool ieee80211_assoc_success(stru - if (!bss_ies) - return false; - -- ieee802_11_parse_elems(bss_ies->data, bss_ies->len, -- false, &bss_elems, -- mgmt->bssid, -- assoc_data->bss->bssid); -+ bss_elems = ieee802_11_parse_elems(bss_ies->data, bss_ies->len, -+ false, mgmt->bssid, -+ assoc_data->bss->bssid); -+ if (!bss_elems) { -+ ret = false; -+ goto out; -+ } -+ - if (assoc_data->wmm && -- !elems->wmm_param && bss_elems.wmm_param) { -- elems->wmm_param = bss_elems.wmm_param; -+ !elems->wmm_param && bss_elems->wmm_param) { -+ elems->wmm_param = bss_elems->wmm_param; - sdata_info(sdata, - "AP bug: WMM param missing from AssocResp\n"); - } -@@ -3388,30 +3396,32 @@ static bool ieee80211_assoc_success(stru - * Also check if we requested HT/VHT, otherwise the AP doesn't - * have to include the IEs in the (re)association response. - */ -- if (!elems->ht_cap_elem && bss_elems.ht_cap_elem && -+ if (!elems->ht_cap_elem && bss_elems->ht_cap_elem && - !(ifmgd->flags & IEEE80211_STA_DISABLE_HT)) { -- elems->ht_cap_elem = bss_elems.ht_cap_elem; -+ elems->ht_cap_elem = bss_elems->ht_cap_elem; - sdata_info(sdata, - "AP bug: HT capability missing from AssocResp\n"); - } -- if (!elems->ht_operation && bss_elems.ht_operation && -+ if (!elems->ht_operation && bss_elems->ht_operation && - !(ifmgd->flags & IEEE80211_STA_DISABLE_HT)) { -- elems->ht_operation = bss_elems.ht_operation; -+ elems->ht_operation = bss_elems->ht_operation; - sdata_info(sdata, - "AP bug: HT operation missing from AssocResp\n"); - } -- if (!elems->vht_cap_elem && bss_elems.vht_cap_elem && -+ if (!elems->vht_cap_elem && bss_elems->vht_cap_elem && - !(ifmgd->flags & IEEE80211_STA_DISABLE_VHT)) { -- elems->vht_cap_elem = bss_elems.vht_cap_elem; -+ elems->vht_cap_elem = bss_elems->vht_cap_elem; - sdata_info(sdata, - "AP bug: VHT capa missing from AssocResp\n"); - } -- if (!elems->vht_operation && bss_elems.vht_operation && -+ if (!elems->vht_operation && bss_elems->vht_operation && - !(ifmgd->flags & IEEE80211_STA_DISABLE_VHT)) { -- elems->vht_operation = bss_elems.vht_operation; -+ elems->vht_operation = bss_elems->vht_operation; - sdata_info(sdata, - "AP bug: VHT operation missing from AssocResp\n"); - } -+ -+ kfree(bss_elems); - } - - /* -@@ -3662,6 +3672,7 @@ static bool ieee80211_assoc_success(stru - - ret = true; - out: -+ kfree(elems); - kfree(bss_ies); - return ret; - } -@@ -3673,7 +3684,7 @@ static void ieee80211_rx_mgmt_assoc_resp - struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; - struct ieee80211_mgd_assoc_data *assoc_data = ifmgd->assoc_data; - u16 capab_info, status_code, aid; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - int ac, uapsd_queues = -1; - u8 *pos; - bool reassoc; -@@ -3730,14 +3741,16 @@ static void ieee80211_rx_mgmt_assoc_resp - fils_decrypt_assoc_resp(sdata, (u8 *)mgmt, &len, assoc_data) < 0) - return; - -- ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, &elems, -- mgmt->bssid, assoc_data->bss->bssid); -+ elems = ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, -+ mgmt->bssid, assoc_data->bss->bssid); -+ if (!elems) -+ goto notify_driver; - - if (status_code == WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY && -- elems.timeout_int && -- elems.timeout_int->type == WLAN_TIMEOUT_ASSOC_COMEBACK) { -+ elems->timeout_int && -+ elems->timeout_int->type == WLAN_TIMEOUT_ASSOC_COMEBACK) { - u32 tu, ms; -- tu = le32_to_cpu(elems.timeout_int->value); -+ tu = le32_to_cpu(elems->timeout_int->value); - ms = tu * 1024 / 1000; - sdata_info(sdata, - "%pM rejected association temporarily; comeback duration %u TU (%u ms)\n", -@@ -3757,7 +3770,7 @@ static void ieee80211_rx_mgmt_assoc_resp - event.u.mlme.reason = status_code; - drv_event_callback(sdata->local, sdata, &event); - } else { -- if (!ieee80211_assoc_success(sdata, cbss, mgmt, len, &elems)) { -+ if (!ieee80211_assoc_success(sdata, cbss, mgmt, len, elems)) { - /* oops -- internal error -- send timeout for now */ - ieee80211_destroy_assoc_data(sdata, false, false); - cfg80211_assoc_timeout(sdata->dev, cbss); -@@ -3787,6 +3800,7 @@ static void ieee80211_rx_mgmt_assoc_resp - ifmgd->assoc_req_ies, ifmgd->assoc_req_ies_len); - notify_driver: - drv_mgd_complete_tx(sdata->local, sdata, &info); -+ kfree(elems); - } - - static void ieee80211_rx_bss_info(struct ieee80211_sub_if_data *sdata, -@@ -3991,7 +4005,7 @@ static void ieee80211_rx_mgmt_beacon(str - struct ieee80211_bss_conf *bss_conf = &sdata->vif.bss_conf; - struct ieee80211_mgmt *mgmt = (void *) hdr; - size_t baselen; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - struct ieee80211_local *local = sdata->local; - struct ieee80211_chanctx_conf *chanctx_conf; - struct ieee80211_channel *chan; -@@ -4037,15 +4051,16 @@ static void ieee80211_rx_mgmt_beacon(str - - if (ifmgd->assoc_data && ifmgd->assoc_data->need_beacon && - ieee80211_rx_our_beacon(bssid, ifmgd->assoc_data->bss)) { -- ieee802_11_parse_elems(variable, -- len - baselen, false, &elems, -- bssid, -- ifmgd->assoc_data->bss->bssid); -+ elems = ieee802_11_parse_elems(variable, len - baselen, false, -+ bssid, -+ ifmgd->assoc_data->bss->bssid); -+ if (!elems) -+ return; - - ieee80211_rx_bss_info(sdata, mgmt, len, rx_status); - -- if (elems.dtim_period) -- ifmgd->dtim_period = elems.dtim_period; -+ if (elems->dtim_period) -+ ifmgd->dtim_period = elems->dtim_period; - ifmgd->have_beacon = true; - ifmgd->assoc_data->need_beacon = false; - if (ieee80211_hw_check(&local->hw, TIMING_BEACON_ONLY)) { -@@ -4053,17 +4068,17 @@ static void ieee80211_rx_mgmt_beacon(str - le64_to_cpu(mgmt->u.beacon.timestamp); - sdata->vif.bss_conf.sync_device_ts = - rx_status->device_timestamp; -- sdata->vif.bss_conf.sync_dtim_count = elems.dtim_count; -+ sdata->vif.bss_conf.sync_dtim_count = elems->dtim_count; - } - -- if (elems.mbssid_config_ie) -+ if (elems->mbssid_config_ie) - bss_conf->profile_periodicity = -- elems.mbssid_config_ie->profile_periodicity; -+ elems->mbssid_config_ie->profile_periodicity; - else - bss_conf->profile_periodicity = 0; - -- if (elems.ext_capab_len >= 11 && -- (elems.ext_capab[10] & WLAN_EXT_CAPA11_EMA_SUPPORT)) -+ if (elems->ext_capab_len >= 11 && -+ (elems->ext_capab[10] & WLAN_EXT_CAPA11_EMA_SUPPORT)) - bss_conf->ema_ap = true; - else - bss_conf->ema_ap = false; -@@ -4072,6 +4087,7 @@ static void ieee80211_rx_mgmt_beacon(str - ifmgd->assoc_data->timeout = jiffies; - ifmgd->assoc_data->timeout_started = true; - run_again(sdata, ifmgd->assoc_data->timeout); -+ kfree(elems); - return; - } - -@@ -4103,14 +4119,15 @@ static void ieee80211_rx_mgmt_beacon(str - */ - if (!ieee80211_is_s1g_beacon(hdr->frame_control)) - ncrc = crc32_be(0, (void *)&mgmt->u.beacon.beacon_int, 4); -- ieee802_11_parse_elems_crc(variable, -- len - baselen, false, &elems, -- care_about_ies, ncrc, -- mgmt->bssid, bssid); -- ncrc = elems.crc; -+ elems = ieee802_11_parse_elems_crc(variable, len - baselen, -+ false, care_about_ies, ncrc, -+ mgmt->bssid, bssid); -+ if (!elems) -+ return; -+ ncrc = elems->crc; - - if (ieee80211_hw_check(&local->hw, PS_NULLFUNC_STACK) && -- ieee80211_check_tim(elems.tim, elems.tim_len, bss_conf->aid)) { -+ ieee80211_check_tim(elems->tim, elems->tim_len, bss_conf->aid)) { - if (local->hw.conf.dynamic_ps_timeout > 0) { - if (local->hw.conf.flags & IEEE80211_CONF_PS) { - local->hw.conf.flags &= ~IEEE80211_CONF_PS; -@@ -4180,12 +4197,12 @@ static void ieee80211_rx_mgmt_beacon(str - le64_to_cpu(mgmt->u.beacon.timestamp); - sdata->vif.bss_conf.sync_device_ts = - rx_status->device_timestamp; -- sdata->vif.bss_conf.sync_dtim_count = elems.dtim_count; -+ sdata->vif.bss_conf.sync_dtim_count = elems->dtim_count; - } - - if ((ncrc == ifmgd->beacon_crc && ifmgd->beacon_crc_valid) || - ieee80211_is_s1g_short_beacon(mgmt->frame_control)) -- return; -+ goto free; - ifmgd->beacon_crc = ncrc; - ifmgd->beacon_crc_valid = true; - -@@ -4193,12 +4210,12 @@ static void ieee80211_rx_mgmt_beacon(str - - ieee80211_sta_process_chanswitch(sdata, rx_status->mactime, - rx_status->device_timestamp, -- &elems, true); -+ elems, true); - - if (!(ifmgd->flags & IEEE80211_STA_DISABLE_WMM) && -- ieee80211_sta_wmm_params(local, sdata, elems.wmm_param, -- elems.wmm_param_len, -- elems.mu_edca_param_set)) -+ ieee80211_sta_wmm_params(local, sdata, elems->wmm_param, -+ elems->wmm_param_len, -+ elems->mu_edca_param_set)) - changed |= BSS_CHANGED_QOS; - - /* -@@ -4207,7 +4224,7 @@ static void ieee80211_rx_mgmt_beacon(str - */ - if (!ifmgd->have_beacon) { - /* a few bogus AP send dtim_period = 0 or no TIM IE */ -- bss_conf->dtim_period = elems.dtim_period ?: 1; -+ bss_conf->dtim_period = elems->dtim_period ?: 1; - - changed |= BSS_CHANGED_BEACON_INFO; - ifmgd->have_beacon = true; -@@ -4219,9 +4236,9 @@ static void ieee80211_rx_mgmt_beacon(str - ieee80211_recalc_ps_vif(sdata); - } - -- if (elems.erp_info) { -+ if (elems->erp_info) { - erp_valid = true; -- erp_value = elems.erp_info[0]; -+ erp_value = elems->erp_info[0]; - } else { - erp_valid = false; - } -@@ -4234,12 +4251,12 @@ static void ieee80211_rx_mgmt_beacon(str - mutex_lock(&local->sta_mtx); - sta = sta_info_get(sdata, bssid); - -- changed |= ieee80211_recalc_twt_req(sdata, sta, &elems); -+ changed |= ieee80211_recalc_twt_req(sdata, sta, elems); - -- if (ieee80211_config_bw(sdata, sta, elems.ht_cap_elem, -- elems.vht_cap_elem, elems.ht_operation, -- elems.vht_operation, elems.he_operation, -- elems.s1g_oper, bssid, &changed)) { -+ if (ieee80211_config_bw(sdata, sta, elems->ht_cap_elem, -+ elems->vht_cap_elem, elems->ht_operation, -+ elems->vht_operation, elems->he_operation, -+ elems->s1g_oper, bssid, &changed)) { - mutex_unlock(&local->sta_mtx); - sdata_info(sdata, - "failed to follow AP %pM bandwidth change, disconnect\n", -@@ -4251,21 +4268,23 @@ static void ieee80211_rx_mgmt_beacon(str - sizeof(deauth_buf), true, - WLAN_REASON_DEAUTH_LEAVING, - false); -- return; -+ goto free; - } - -- if (sta && elems.opmode_notif) -- ieee80211_vht_handle_opmode(sdata, sta, *elems.opmode_notif, -+ if (sta && elems->opmode_notif) -+ ieee80211_vht_handle_opmode(sdata, sta, *elems->opmode_notif, - rx_status->band); - mutex_unlock(&local->sta_mtx); - - changed |= ieee80211_handle_pwr_constr(sdata, chan, mgmt, -- elems.country_elem, -- elems.country_elem_len, -- elems.pwr_constr_elem, -- elems.cisco_dtpc_elem); -+ elems->country_elem, -+ elems->country_elem_len, -+ elems->pwr_constr_elem, -+ elems->cisco_dtpc_elem); - - ieee80211_bss_info_change_notify(sdata, changed); -+free: -+ kfree(elems); - } - - void ieee80211_sta_rx_queued_ext(struct ieee80211_sub_if_data *sdata, -@@ -4294,7 +4313,6 @@ void ieee80211_sta_rx_queued_mgmt(struct - struct ieee80211_rx_status *rx_status; - struct ieee80211_mgmt *mgmt; - u16 fc; -- struct ieee802_11_elems elems; - int ies_len; - - rx_status = (struct ieee80211_rx_status *) skb->cb; -@@ -4326,6 +4344,8 @@ void ieee80211_sta_rx_queued_mgmt(struct - break; - case IEEE80211_STYPE_ACTION: - if (mgmt->u.action.category == WLAN_CATEGORY_SPECTRUM_MGMT) { -+ struct ieee802_11_elems *elems; -+ - ies_len = skb->len - - offsetof(struct ieee80211_mgmt, - u.action.u.chan_switch.variable); -@@ -4334,18 +4354,21 @@ void ieee80211_sta_rx_queued_mgmt(struct - break; - - /* CSA IE cannot be overridden, no need for BSSID */ -- ieee802_11_parse_elems( -- mgmt->u.action.u.chan_switch.variable, -- ies_len, true, &elems, mgmt->bssid, NULL); -+ elems = ieee802_11_parse_elems( -+ mgmt->u.action.u.chan_switch.variable, -+ ies_len, true, mgmt->bssid, NULL); - -- if (elems.parse_error) -+ if (!elems || elems->parse_error) - break; - - ieee80211_sta_process_chanswitch(sdata, - rx_status->mactime, - rx_status->device_timestamp, -- &elems, false); -+ elems, false); -+ kfree(elems); - } else if (mgmt->u.action.category == WLAN_CATEGORY_PUBLIC) { -+ struct ieee802_11_elems *elems; -+ - ies_len = skb->len - - offsetof(struct ieee80211_mgmt, - u.action.u.ext_chan_switch.variable); -@@ -4357,21 +4380,22 @@ void ieee80211_sta_rx_queued_mgmt(struct - * extended CSA IE can't be overridden, no need for - * BSSID - */ -- ieee802_11_parse_elems( -- mgmt->u.action.u.ext_chan_switch.variable, -- ies_len, true, &elems, mgmt->bssid, NULL); -+ elems = ieee802_11_parse_elems( -+ mgmt->u.action.u.ext_chan_switch.variable, -+ ies_len, true, mgmt->bssid, NULL); - -- if (elems.parse_error) -+ if (!elems || elems->parse_error) - break; - - /* for the handling code pretend this was also an IE */ -- elems.ext_chansw_ie = -+ elems->ext_chansw_ie = - &mgmt->u.action.u.ext_chan_switch.data; - - ieee80211_sta_process_chanswitch(sdata, - rx_status->mactime, - rx_status->device_timestamp, -- &elems, false); -+ elems, false); -+ kfree(elems); - } - break; - } ---- a/net/mac80211/scan.c -+++ b/net/mac80211/scan.c -@@ -9,7 +9,7 @@ - * Copyright 2007, Michael Wu - * Copyright 2013-2015 Intel Mobile Communications GmbH - * Copyright 2016-2017 Intel Deutschland GmbH -- * Copyright (C) 2018-2020 Intel Corporation -+ * Copyright (C) 2018-2021 Intel Corporation - */ - - #include -@@ -155,7 +155,7 @@ ieee80211_bss_info_update(struct ieee802 - }; - bool signal_valid; - struct ieee80211_sub_if_data *scan_sdata; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - size_t baselen; - u8 *elements; - -@@ -209,8 +209,10 @@ ieee80211_bss_info_update(struct ieee802 - if (baselen > len) - return NULL; - -- ieee802_11_parse_elems(elements, len - baselen, false, &elems, -- mgmt->bssid, cbss->bssid); -+ elems = ieee802_11_parse_elems(elements, len - baselen, false, -+ mgmt->bssid, cbss->bssid); -+ if (!elems) -+ return NULL; - - /* In case the signal is invalid update the status */ - signal_valid = channel == cbss->channel; -@@ -218,15 +220,17 @@ ieee80211_bss_info_update(struct ieee802 - rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; - - bss = (void *)cbss->priv; -- ieee80211_update_bss_from_elems(local, bss, &elems, rx_status, beacon); -+ ieee80211_update_bss_from_elems(local, bss, elems, rx_status, beacon); - - list_for_each_entry(non_tx_cbss, &cbss->nontrans_list, nontrans_list) { - non_tx_bss = (void *)non_tx_cbss->priv; - -- ieee80211_update_bss_from_elems(local, non_tx_bss, &elems, -+ ieee80211_update_bss_from_elems(local, non_tx_bss, elems, - rx_status, beacon); - } - -+ kfree(elems); -+ - return bss; - } - ---- a/net/mac80211/tdls.c -+++ b/net/mac80211/tdls.c -@@ -6,7 +6,7 @@ - * Copyright 2014, Intel Corporation - * Copyright 2014 Intel Mobile Communications GmbH - * Copyright 2015 - 2016 Intel Deutschland GmbH -- * Copyright (C) 2019 Intel Corporation -+ * Copyright (C) 2019, 2021 Intel Corporation - */ - - #include -@@ -1684,7 +1684,7 @@ ieee80211_process_tdls_channel_switch_re - struct sk_buff *skb) - { - struct ieee80211_local *local = sdata->local; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems = NULL; - struct sta_info *sta; - struct ieee80211_tdls_data *tf = (void *)skb->data; - bool local_initiator; -@@ -1718,16 +1718,20 @@ ieee80211_process_tdls_channel_switch_re - goto call_drv; - } - -- ieee802_11_parse_elems(tf->u.chan_switch_resp.variable, -- skb->len - baselen, false, &elems, -- NULL, NULL); -- if (elems.parse_error) { -+ elems = ieee802_11_parse_elems(tf->u.chan_switch_resp.variable, -+ skb->len - baselen, false, NULL, NULL); -+ if (!elems) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ if (elems->parse_error) { - tdls_dbg(sdata, "Invalid IEs in TDLS channel switch resp\n"); - ret = -EINVAL; - goto out; - } - -- if (!elems.ch_sw_timing || !elems.lnk_id) { -+ if (!elems->ch_sw_timing || !elems->lnk_id) { - tdls_dbg(sdata, "TDLS channel switch resp - missing IEs\n"); - ret = -EINVAL; - goto out; -@@ -1735,15 +1739,15 @@ ieee80211_process_tdls_channel_switch_re - - /* validate the initiator is set correctly */ - local_initiator = -- !memcmp(elems.lnk_id->init_sta, sdata->vif.addr, ETH_ALEN); -+ !memcmp(elems->lnk_id->init_sta, sdata->vif.addr, ETH_ALEN); - if (local_initiator == sta->sta.tdls_initiator) { - tdls_dbg(sdata, "TDLS chan switch invalid lnk-id initiator\n"); - ret = -EINVAL; - goto out; - } - -- params.switch_time = le16_to_cpu(elems.ch_sw_timing->switch_time); -- params.switch_timeout = le16_to_cpu(elems.ch_sw_timing->switch_timeout); -+ params.switch_time = le16_to_cpu(elems->ch_sw_timing->switch_time); -+ params.switch_timeout = le16_to_cpu(elems->ch_sw_timing->switch_timeout); - - params.tmpl_skb = - ieee80211_tdls_ch_sw_resp_tmpl_get(sta, ¶ms.ch_sw_tm_ie); -@@ -1763,6 +1767,7 @@ call_drv: - out: - mutex_unlock(&local->sta_mtx); - dev_kfree_skb_any(params.tmpl_skb); -+ kfree(elems); - return ret; - } - -@@ -1771,7 +1776,7 @@ ieee80211_process_tdls_channel_switch_re - struct sk_buff *skb) - { - struct ieee80211_local *local = sdata->local; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - struct cfg80211_chan_def chandef; - struct ieee80211_channel *chan; - enum nl80211_channel_type chan_type; -@@ -1831,22 +1836,27 @@ ieee80211_process_tdls_channel_switch_re - return -EINVAL; - } - -- ieee802_11_parse_elems(tf->u.chan_switch_req.variable, -- skb->len - baselen, false, &elems, NULL, NULL); -- if (elems.parse_error) { -+ elems = ieee802_11_parse_elems(tf->u.chan_switch_req.variable, -+ skb->len - baselen, false, NULL, NULL); -+ if (!elems) -+ return -ENOMEM; -+ -+ if (elems->parse_error) { - tdls_dbg(sdata, "Invalid IEs in TDLS channel switch req\n"); -- return -EINVAL; -+ ret = -EINVAL; -+ goto free; - } - -- if (!elems.ch_sw_timing || !elems.lnk_id) { -+ if (!elems->ch_sw_timing || !elems->lnk_id) { - tdls_dbg(sdata, "TDLS channel switch req - missing IEs\n"); -- return -EINVAL; -+ ret = -EINVAL; -+ goto free; - } - -- if (!elems.sec_chan_offs) { -+ if (!elems->sec_chan_offs) { - chan_type = NL80211_CHAN_HT20; - } else { -- switch (elems.sec_chan_offs->sec_chan_offs) { -+ switch (elems->sec_chan_offs->sec_chan_offs) { - case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: - chan_type = NL80211_CHAN_HT40PLUS; - break; -@@ -1865,7 +1875,8 @@ ieee80211_process_tdls_channel_switch_re - if (!cfg80211_reg_can_beacon_relax(sdata->local->hw.wiphy, &chandef, - sdata->wdev.iftype)) { - tdls_dbg(sdata, "TDLS chan switch to forbidden channel\n"); -- return -EINVAL; -+ ret = -EINVAL; -+ goto free; - } - - mutex_lock(&local->sta_mtx); -@@ -1881,7 +1892,7 @@ ieee80211_process_tdls_channel_switch_re - - /* validate the initiator is set correctly */ - local_initiator = -- !memcmp(elems.lnk_id->init_sta, sdata->vif.addr, ETH_ALEN); -+ !memcmp(elems->lnk_id->init_sta, sdata->vif.addr, ETH_ALEN); - if (local_initiator == sta->sta.tdls_initiator) { - tdls_dbg(sdata, "TDLS chan switch invalid lnk-id initiator\n"); - ret = -EINVAL; -@@ -1889,16 +1900,16 @@ ieee80211_process_tdls_channel_switch_re - } - - /* peer should have known better */ -- if (!sta->sta.ht_cap.ht_supported && elems.sec_chan_offs && -- elems.sec_chan_offs->sec_chan_offs) { -+ if (!sta->sta.ht_cap.ht_supported && elems->sec_chan_offs && -+ elems->sec_chan_offs->sec_chan_offs) { - tdls_dbg(sdata, "TDLS chan switch - wide chan unsupported\n"); - ret = -ENOTSUPP; - goto out; - } - - params.chandef = &chandef; -- params.switch_time = le16_to_cpu(elems.ch_sw_timing->switch_time); -- params.switch_timeout = le16_to_cpu(elems.ch_sw_timing->switch_timeout); -+ params.switch_time = le16_to_cpu(elems->ch_sw_timing->switch_time); -+ params.switch_timeout = le16_to_cpu(elems->ch_sw_timing->switch_timeout); - - params.tmpl_skb = - ieee80211_tdls_ch_sw_resp_tmpl_get(sta, -@@ -1917,6 +1928,8 @@ ieee80211_process_tdls_channel_switch_re - out: - mutex_unlock(&local->sta_mtx); - dev_kfree_skb_any(params.tmpl_skb); -+free: -+ kfree(elems); - return ret; - } - ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -1399,8 +1399,8 @@ _ieee802_11_parse_elems_crc(const u8 *st - - static size_t ieee802_11_find_bssid_profile(const u8 *start, size_t len, - struct ieee802_11_elems *elems, -- u8 *transmitter_bssid, -- u8 *bss_bssid, -+ const u8 *transmitter_bssid, -+ const u8 *bss_bssid, - u8 *nontransmitted_profile) - { - const struct element *elem, *sub; -@@ -1465,16 +1465,20 @@ static size_t ieee802_11_find_bssid_prof - return found ? profile_len : 0; - } - --void ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, -- struct ieee802_11_elems *elems, -- u64 filter, u32 crc, u8 *transmitter_bssid, -- u8 *bss_bssid) -+struct ieee802_11_elems *ieee802_11_parse_elems_crc(const u8 *start, size_t len, -+ bool action, u64 filter, -+ u32 crc, -+ const u8 *transmitter_bssid, -+ const u8 *bss_bssid) - { -+ struct ieee802_11_elems *elems; - const struct element *non_inherit = NULL; - u8 *nontransmitted_profile; - int nontransmitted_profile_len = 0; - -- memset(elems, 0, sizeof(*elems)); -+ elems = kzalloc(sizeof(*elems), GFP_ATOMIC); -+ if (!elems) -+ return NULL; - elems->ie_start = start; - elems->total_len = len; - -@@ -1521,6 +1525,8 @@ void ieee802_11_parse_elems_crc(const u8 - kfree(nontransmitted_profile); - - elems->crc = crc; -+ -+ return elems; - } - - void ieee80211_regulatory_limit_wmm_params(struct ieee80211_sub_if_data *sdata, diff --git a/package/kernel/mac80211/patches/subsys/350-mac80211-fix-memory-leaks-with-element-parsing.patch b/package/kernel/mac80211/patches/subsys/350-mac80211-fix-memory-leaks-with-element-parsing.patch deleted file mode 100644 index f4906e8c03..0000000000 --- a/package/kernel/mac80211/patches/subsys/350-mac80211-fix-memory-leaks-with-element-parsing.patch +++ /dev/null @@ -1,115 +0,0 @@ -From: Johannes Berg -Date: Fri, 1 Oct 2021 21:11:08 +0200 -Subject: [PATCH] mac80211: fix memory leaks with element parsing - -commit 8223ac199a3849257e86ec27865dc63f034b1cf1 upstream. - -My previous commit 5d24828d05f3 ("mac80211: always allocate -struct ieee802_11_elems") had a few bugs and leaked the new -allocated struct in a few error cases, fix that. - -Fixes: 5d24828d05f3 ("mac80211: always allocate struct ieee802_11_elems") -Signed-off-by: Johannes Berg -Link: https://lore.kernel.org/r/20211001211108.9839928e42e0.Ib81ca187d3d3af7ed1bfeac2e00d08a4637c8025@changeid -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/agg-rx.c -+++ b/net/mac80211/agg-rx.c -@@ -499,13 +499,14 @@ void ieee80211_process_addba_request(str - elems = ieee802_11_parse_elems(mgmt->u.action.u.addba_req.variable, - ies_len, true, mgmt->bssid, NULL); - if (!elems || elems->parse_error) -- return; -+ goto free; - } - - __ieee80211_start_rx_ba_session(sta, dialog_token, timeout, - start_seq_num, ba_policy, tid, - buf_size, true, false, - elems ? elems->addba_ext_ie : NULL); -+free: - kfree(elems); - } - ---- a/net/mac80211/ibss.c -+++ b/net/mac80211/ibss.c -@@ -1659,11 +1659,11 @@ void ieee80211_ibss_rx_queued_mgmt(struc - mgmt->u.action.u.chan_switch.variable, - ies_len, true, mgmt->bssid, NULL); - -- if (!elems || elems->parse_error) -- break; -- -- ieee80211_rx_mgmt_spectrum_mgmt(sdata, mgmt, skb->len, -- rx_status, elems); -+ if (elems && !elems->parse_error) -+ ieee80211_rx_mgmt_spectrum_mgmt(sdata, mgmt, -+ skb->len, -+ rx_status, -+ elems); - kfree(elems); - break; - } ---- a/net/mac80211/mlme.c -+++ b/net/mac80211/mlme.c -@@ -3374,8 +3374,10 @@ static bool ieee80211_assoc_success(stru - bss_ies = kmemdup(ies, sizeof(*ies) + ies->len, - GFP_ATOMIC); - rcu_read_unlock(); -- if (!bss_ies) -- return false; -+ if (!bss_ies) { -+ ret = false; -+ goto out; -+ } - - bss_elems = ieee802_11_parse_elems(bss_ies->data, bss_ies->len, - false, mgmt->bssid, -@@ -4358,13 +4360,11 @@ void ieee80211_sta_rx_queued_mgmt(struct - mgmt->u.action.u.chan_switch.variable, - ies_len, true, mgmt->bssid, NULL); - -- if (!elems || elems->parse_error) -- break; -- -- ieee80211_sta_process_chanswitch(sdata, -- rx_status->mactime, -- rx_status->device_timestamp, -- elems, false); -+ if (elems && !elems->parse_error) -+ ieee80211_sta_process_chanswitch(sdata, -+ rx_status->mactime, -+ rx_status->device_timestamp, -+ elems, false); - kfree(elems); - } else if (mgmt->u.action.category == WLAN_CATEGORY_PUBLIC) { - struct ieee802_11_elems *elems; -@@ -4384,17 +4384,17 @@ void ieee80211_sta_rx_queued_mgmt(struct - mgmt->u.action.u.ext_chan_switch.variable, - ies_len, true, mgmt->bssid, NULL); - -- if (!elems || elems->parse_error) -- break; -+ if (elems && !elems->parse_error) { -+ /* for the handling code pretend it was an IE */ -+ elems->ext_chansw_ie = -+ &mgmt->u.action.u.ext_chan_switch.data; -+ -+ ieee80211_sta_process_chanswitch(sdata, -+ rx_status->mactime, -+ rx_status->device_timestamp, -+ elems, false); -+ } - -- /* for the handling code pretend this was also an IE */ -- elems->ext_chansw_ie = -- &mgmt->u.action.u.ext_chan_switch.data; -- -- ieee80211_sta_process_chanswitch(sdata, -- rx_status->mactime, -- rx_status->device_timestamp, -- elems, false); - kfree(elems); - } - break; diff --git a/package/kernel/mac80211/patches/subsys/351-wifi-cfg80211-fix-u8-overflow-in-cfg80211_update_not.patch b/package/kernel/mac80211/patches/subsys/351-wifi-cfg80211-fix-u8-overflow-in-cfg80211_update_not.patch deleted file mode 100644 index 9e1f781367..0000000000 --- a/package/kernel/mac80211/patches/subsys/351-wifi-cfg80211-fix-u8-overflow-in-cfg80211_update_not.patch +++ /dev/null @@ -1,41 +0,0 @@ -From: Johannes Berg -Date: Wed, 28 Sep 2022 21:56:15 +0200 -Subject: [PATCH] wifi: cfg80211: fix u8 overflow in - cfg80211_update_notlisted_nontrans() - -commit aebe9f4639b13a1f4e9a6b42cdd2e38c617b442d upstream. - -In the copy code of the elements, we do the following calculation -to reach the end of the MBSSID element: - - /* copy the IEs after MBSSID */ - cpy_len = mbssid[1] + 2; - -This looks fine, however, cpy_len is a u8, the same as mbssid[1], -so the addition of two can overflow. In this case the subsequent -memcpy() will overflow the allocated buffer, since it copies 256 -bytes too much due to the way the allocation and memcpy() sizes -are calculated. - -Fix this by using size_t for the cpy_len variable. - -This fixes CVE-2022-41674. - -Reported-by: Soenke Huster -Tested-by: Soenke Huster -Fixes: 0b8fb8235be8 ("cfg80211: Parsing of Multiple BSSID information in scanning") -Reviewed-by: Kees Cook -Signed-off-by: Johannes Berg ---- - ---- a/net/wireless/scan.c -+++ b/net/wireless/scan.c -@@ -2238,7 +2238,7 @@ cfg80211_update_notlisted_nontrans(struc - size_t new_ie_len; - struct cfg80211_bss_ies *new_ies; - const struct cfg80211_bss_ies *old; -- u8 cpy_len; -+ size_t cpy_len; - - lockdep_assert_held(&wiphy_to_rdev(wiphy)->bss_lock); - diff --git a/package/kernel/mac80211/patches/subsys/352-wifi-cfg80211-mac80211-reject-bad-MBSSID-elements.patch b/package/kernel/mac80211/patches/subsys/352-wifi-cfg80211-mac80211-reject-bad-MBSSID-elements.patch deleted file mode 100644 index 4c8e05e9ba..0000000000 --- a/package/kernel/mac80211/patches/subsys/352-wifi-cfg80211-mac80211-reject-bad-MBSSID-elements.patch +++ /dev/null @@ -1,47 +0,0 @@ -From: Johannes Berg -Date: Wed, 28 Sep 2022 22:01:37 +0200 -Subject: [PATCH] wifi: cfg80211/mac80211: reject bad MBSSID elements - -commit 8f033d2becc24aa6bfd2a5c104407963560caabc upstream - -Per spec, the maximum value for the MaxBSSID ('n') indicator is 8, -and the minimum is 1 since a multiple BSSID set with just one BSSID -doesn't make sense (the # of BSSIDs is limited by 2^n). - -Limit this in the parsing in both cfg80211 and mac80211, rejecting -any elements with an invalid value. - -This fixes potentially bad shifts in the processing of these inside -the cfg80211_gen_new_bssid() function later. - -I found this during the investigation of CVE-2022-41674 fixed by the -previous patch. - -Fixes: 0b8fb8235be8 ("cfg80211: Parsing of Multiple BSSID information in scanning") -Fixes: 78ac51f81532 ("mac80211: support multi-bssid") -Reviewed-by: Kees Cook -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -1413,6 +1413,8 @@ static size_t ieee802_11_find_bssid_prof - for_each_element_id(elem, WLAN_EID_MULTIPLE_BSSID, start, len) { - if (elem->datalen < 2) - continue; -+ if (elem->data[0] < 1 || elem->data[0] > 8) -+ continue; - - for_each_element(sub, elem->data + 1, elem->datalen - 1) { - u8 new_bssid[ETH_ALEN]; ---- a/net/wireless/scan.c -+++ b/net/wireless/scan.c -@@ -2103,6 +2103,8 @@ static void cfg80211_parse_mbssid_data(s - for_each_element_id(elem, WLAN_EID_MULTIPLE_BSSID, ie, ielen) { - if (elem->datalen < 4) - continue; -+ if (elem->data[0] < 1 || (int)elem->data[0] > 8) -+ continue; - for_each_element(sub, elem->data + 1, elem->datalen - 1) { - u8 profile_len; - diff --git a/package/kernel/mac80211/patches/subsys/353-wifi-mac80211-fix-MBSSID-parsing-use-after-free.patch b/package/kernel/mac80211/patches/subsys/353-wifi-mac80211-fix-MBSSID-parsing-use-after-free.patch deleted file mode 100644 index 6e97150e90..0000000000 --- a/package/kernel/mac80211/patches/subsys/353-wifi-mac80211-fix-MBSSID-parsing-use-after-free.patch +++ /dev/null @@ -1,94 +0,0 @@ -From: Johannes Berg -Date: Wed, 28 Sep 2022 22:07:15 +0200 -Subject: [PATCH] wifi: mac80211: fix MBSSID parsing use-after-free - -commit ff05d4b45dd89b922578dac497dcabf57cf771c6 - -When we parse a multi-BSSID element, we might point some -element pointers into the allocated nontransmitted_profile. -However, we free this before returning, causing UAF when the -relevant pointers in the parsed elements are accessed. - -Fix this by not allocating the scratch buffer separately but -as part of the returned structure instead, that way, there -are no lifetime issues with it. - -The scratch buffer introduction as part of the returned data -here is taken from MLO feature work done by Ilan. - -This fixes CVE-2022-42719. - -Fixes: 5023b14cf4df ("mac80211: support profile split between elements") -Co-developed-by: Ilan Peer -Signed-off-by: Ilan Peer -Reviewed-by: Kees Cook -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/ieee80211_i.h -+++ b/net/mac80211/ieee80211_i.h -@@ -1611,6 +1611,14 @@ struct ieee802_11_elems { - - /* whether a parse error occurred while retrieving these elements */ - bool parse_error; -+ -+ /* -+ * scratch buffer that can be used for various element parsing related -+ * tasks, e.g., element de-fragmentation etc. -+ */ -+ size_t scratch_len; -+ u8 *scratch_pos; -+ u8 scratch[]; - }; - - static inline struct ieee80211_local *hw_to_local( ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -1478,24 +1478,25 @@ struct ieee802_11_elems *ieee802_11_pars - u8 *nontransmitted_profile; - int nontransmitted_profile_len = 0; - -- elems = kzalloc(sizeof(*elems), GFP_ATOMIC); -+ elems = kzalloc(sizeof(*elems) + len, GFP_ATOMIC); - if (!elems) - return NULL; - elems->ie_start = start; - elems->total_len = len; - -- nontransmitted_profile = kmalloc(len, GFP_ATOMIC); -- if (nontransmitted_profile) { -- nontransmitted_profile_len = -- ieee802_11_find_bssid_profile(start, len, elems, -- transmitter_bssid, -- bss_bssid, -- nontransmitted_profile); -- non_inherit = -- cfg80211_find_ext_elem(WLAN_EID_EXT_NON_INHERITANCE, -- nontransmitted_profile, -- nontransmitted_profile_len); -- } -+ elems->scratch_len = len; -+ elems->scratch_pos = elems->scratch; -+ -+ nontransmitted_profile = elems->scratch_pos; -+ nontransmitted_profile_len = -+ ieee802_11_find_bssid_profile(start, len, elems, -+ transmitter_bssid, -+ bss_bssid, -+ nontransmitted_profile); -+ non_inherit = -+ cfg80211_find_ext_elem(WLAN_EID_EXT_NON_INHERITANCE, -+ nontransmitted_profile, -+ nontransmitted_profile_len); - - crc = _ieee802_11_parse_elems_crc(start, len, action, elems, filter, - crc, non_inherit); -@@ -1524,8 +1525,6 @@ struct ieee802_11_elems *ieee802_11_pars - offsetofend(struct ieee80211_bssid_index, dtim_count)) - elems->dtim_count = elems->bssid_index->dtim_count; - -- kfree(nontransmitted_profile); -- - elems->crc = crc; - - return elems; diff --git a/package/kernel/mac80211/patches/subsys/354-wifi-cfg80211-ensure-length-byte-is-present-before-a.patch b/package/kernel/mac80211/patches/subsys/354-wifi-cfg80211-ensure-length-byte-is-present-before-a.patch deleted file mode 100644 index da94840dac..0000000000 --- a/package/kernel/mac80211/patches/subsys/354-wifi-cfg80211-ensure-length-byte-is-present-before-a.patch +++ /dev/null @@ -1,41 +0,0 @@ -From: Johannes Berg -Date: Thu, 29 Sep 2022 21:50:44 +0200 -Subject: [PATCH] wifi: cfg80211: ensure length byte is present before - access - -commit 567e14e39e8f8c6997a1378bc3be615afca86063 upstream. - -When iterating the elements here, ensure the length byte is -present before checking it to see if the entire element will -fit into the buffer. - -Longer term, we should rewrite this code using the type-safe -element iteration macros that check all of this. - -Fixes: 0b8fb8235be8 ("cfg80211: Parsing of Multiple BSSID information in scanning") -Reported-by: Soenke Huster -Signed-off-by: Johannes Berg ---- - ---- a/net/wireless/scan.c -+++ b/net/wireless/scan.c -@@ -304,7 +304,8 @@ static size_t cfg80211_gen_new_ie(const - tmp_old = cfg80211_find_ie(WLAN_EID_SSID, ie, ielen); - tmp_old = (tmp_old) ? tmp_old + tmp_old[1] + 2 : ie; - -- while (tmp_old + tmp_old[1] + 2 - ie <= ielen) { -+ while (tmp_old + 2 - ie <= ielen && -+ tmp_old + tmp_old[1] + 2 - ie <= ielen) { - if (tmp_old[0] == 0) { - tmp_old++; - continue; -@@ -364,7 +365,8 @@ static size_t cfg80211_gen_new_ie(const - * copied to new ie, skip ssid, capability, bssid-index ie - */ - tmp_new = sub_copy; -- while (tmp_new + tmp_new[1] + 2 - sub_copy <= subie_len) { -+ while (tmp_new + 2 - sub_copy <= subie_len && -+ tmp_new + tmp_new[1] + 2 - sub_copy <= subie_len) { - if (!(tmp_new[0] == WLAN_EID_NON_TX_BSSID_CAP || - tmp_new[0] == WLAN_EID_SSID)) { - memcpy(pos, tmp_new, tmp_new[1] + 2); diff --git a/package/kernel/mac80211/patches/subsys/355-wifi-cfg80211-fix-BSS-refcounting-bugs.patch b/package/kernel/mac80211/patches/subsys/355-wifi-cfg80211-fix-BSS-refcounting-bugs.patch deleted file mode 100644 index 4680e1e815..0000000000 --- a/package/kernel/mac80211/patches/subsys/355-wifi-cfg80211-fix-BSS-refcounting-bugs.patch +++ /dev/null @@ -1,87 +0,0 @@ -From: Johannes Berg -Date: Fri, 30 Sep 2022 23:44:23 +0200 -Subject: [PATCH] wifi: cfg80211: fix BSS refcounting bugs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -commit 0b7808818cb9df6680f98996b8e9a439fa7bcc2f upstream. - -There are multiple refcounting bugs related to multi-BSSID: - - In bss_ref_get(), if the BSS has a hidden_beacon_bss, then - the bss pointer is overwritten before checking for the - transmitted BSS, which is clearly wrong. Fix this by using - the bss_from_pub() macro. - - - In cfg80211_bss_update() we copy the transmitted_bss pointer - from tmp into new, but then if we release new, we'll unref - it erroneously. We already set the pointer and ref it, but - need to NULL it since it was copied from the tmp data. - - - In cfg80211_inform_single_bss_data(), if adding to the non- - transmitted list fails, we unlink the BSS and yet still we - return it, but this results in returning an entry without - a reference. We shouldn't return it anyway if it was broken - enough to not get added there. - -This fixes CVE-2022-42720. - -Reported-by: Sönke Huster -Tested-by: Sönke Huster -Fixes: a3584f56de1c ("cfg80211: Properly track transmitting and non-transmitting BSS") -Signed-off-by: Johannes Berg ---- - ---- a/net/wireless/scan.c -+++ b/net/wireless/scan.c -@@ -143,18 +143,12 @@ static inline void bss_ref_get(struct cf - lockdep_assert_held(&rdev->bss_lock); - - bss->refcount++; -- if (bss->pub.hidden_beacon_bss) { -- bss = container_of(bss->pub.hidden_beacon_bss, -- struct cfg80211_internal_bss, -- pub); -- bss->refcount++; -- } -- if (bss->pub.transmitted_bss) { -- bss = container_of(bss->pub.transmitted_bss, -- struct cfg80211_internal_bss, -- pub); -- bss->refcount++; -- } -+ -+ if (bss->pub.hidden_beacon_bss) -+ bss_from_pub(bss->pub.hidden_beacon_bss)->refcount++; -+ -+ if (bss->pub.transmitted_bss) -+ bss_from_pub(bss->pub.transmitted_bss)->refcount++; - } - - static inline void bss_ref_put(struct cfg80211_registered_device *rdev, -@@ -1743,6 +1737,8 @@ cfg80211_bss_update(struct cfg80211_regi - new->refcount = 1; - INIT_LIST_HEAD(&new->hidden_list); - INIT_LIST_HEAD(&new->pub.nontrans_list); -+ /* we'll set this later if it was non-NULL */ -+ new->pub.transmitted_bss = NULL; - - if (rcu_access_pointer(tmp->pub.proberesp_ies)) { - hidden = rb_find_bss(rdev, tmp, BSS_CMP_HIDE_ZLEN); -@@ -1983,10 +1979,15 @@ cfg80211_inform_single_bss_data(struct w - spin_lock_bh(&rdev->bss_lock); - if (cfg80211_add_nontrans_list(non_tx_data->tx_bss, - &res->pub)) { -- if (__cfg80211_unlink_bss(rdev, res)) -+ if (__cfg80211_unlink_bss(rdev, res)) { - rdev->bss_generation++; -+ res = NULL; -+ } - } - spin_unlock_bh(&rdev->bss_lock); -+ -+ if (!res) -+ return NULL; - } - - trace_cfg80211_return_bss(&res->pub); diff --git a/package/kernel/mac80211/patches/subsys/356-wifi-cfg80211-avoid-nontransmitted-BSS-list-corrupti.patch b/package/kernel/mac80211/patches/subsys/356-wifi-cfg80211-avoid-nontransmitted-BSS-list-corrupti.patch deleted file mode 100644 index db0e51edc2..0000000000 --- a/package/kernel/mac80211/patches/subsys/356-wifi-cfg80211-avoid-nontransmitted-BSS-list-corrupti.patch +++ /dev/null @@ -1,48 +0,0 @@ -From: Johannes Berg -Date: Sat, 1 Oct 2022 00:01:44 +0200 -Subject: [PATCH] wifi: cfg80211: avoid nontransmitted BSS list - corruption -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -commit bcca852027e5878aec911a347407ecc88d6fff7f upstream. - -If a non-transmitted BSS shares enough information (both -SSID and BSSID!) with another non-transmitted BSS of a -different AP, then we can find and update it, and then -try to add it to the non-transmitted BSS list. We do a -search for it on the transmitted BSS, but if it's not -there (but belongs to another transmitted BSS), the list -gets corrupted. - -Since this is an erroneous situation, simply fail the -list insertion in this case and free the non-transmitted -BSS. - -This fixes CVE-2022-42721. - -Reported-by: Sönke Huster -Tested-by: Sönke Huster -Fixes: 0b8fb8235be8 ("cfg80211: Parsing of Multiple BSSID information in scanning") -Signed-off-by: Johannes Berg ---- - ---- a/net/wireless/scan.c -+++ b/net/wireless/scan.c -@@ -425,6 +425,15 @@ cfg80211_add_nontrans_list(struct cfg802 - - rcu_read_unlock(); - -+ /* -+ * This is a bit weird - it's not on the list, but already on another -+ * one! The only way that could happen is if there's some BSSID/SSID -+ * shared by multiple APs in their multi-BSSID profiles, potentially -+ * with hidden SSID mixed in ... ignore it. -+ */ -+ if (!list_empty(&nontrans_bss->nontrans_list)) -+ return -EINVAL; -+ - /* add to the list */ - list_add_tail(&nontrans_bss->nontrans_list, &trans_bss->nontrans_list); - return 0; diff --git a/package/kernel/mac80211/patches/subsys/357-wifi-mac80211_hwsim-avoid-mac80211-warning-on-bad-ra.patch b/package/kernel/mac80211/patches/subsys/357-wifi-mac80211_hwsim-avoid-mac80211-warning-on-bad-ra.patch deleted file mode 100644 index ed834ff296..0000000000 --- a/package/kernel/mac80211/patches/subsys/357-wifi-mac80211_hwsim-avoid-mac80211-warning-on-bad-ra.patch +++ /dev/null @@ -1,31 +0,0 @@ -From: Johannes Berg -Date: Wed, 5 Oct 2022 15:10:09 +0200 -Subject: [PATCH] wifi: mac80211_hwsim: avoid mac80211 warning on bad - rate -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -commit 1833b6f46d7e2830251a063935ab464256defe22 upstream. - -If the tool on the other side (e.g. wmediumd) gets confused -about the rate, we hit a warning in mac80211. Silence that -by effectively duplicating the check here and dropping the -frame silently (in mac80211 it's dropped with the warning). - -Reported-by: Sönke Huster -Tested-by: Sönke Huster -Signed-off-by: Johannes Berg ---- - ---- a/drivers/net/wireless/mac80211_hwsim.c -+++ b/drivers/net/wireless/mac80211_hwsim.c -@@ -3760,6 +3760,8 @@ static int hwsim_cloned_frame_received_n - - rx_status.band = channel->band; - rx_status.rate_idx = nla_get_u32(info->attrs[HWSIM_ATTR_RX_RATE]); -+ if (rx_status.rate_idx >= data2->hw->wiphy->bands[rx_status.band]->n_bitrates) -+ goto out; - rx_status.signal = nla_get_u32(info->attrs[HWSIM_ATTR_SIGNAL]); - - hdr = (void *)skb->data; diff --git a/package/kernel/mac80211/patches/subsys/358-wifi-mac80211-fix-crash-in-beacon-protection-for-P2P.patch b/package/kernel/mac80211/patches/subsys/358-wifi-mac80211-fix-crash-in-beacon-protection-for-P2P.patch deleted file mode 100644 index 44b8729977..0000000000 --- a/package/kernel/mac80211/patches/subsys/358-wifi-mac80211-fix-crash-in-beacon-protection-for-P2P.patch +++ /dev/null @@ -1,52 +0,0 @@ -From: Johannes Berg -Date: Wed, 5 Oct 2022 21:24:10 +0200 -Subject: [PATCH] wifi: mac80211: fix crash in beacon protection for - P2P-device -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -commit b2d03cabe2b2e150ff5a381731ea0355459be09f upstream. - -If beacon protection is active but the beacon cannot be -decrypted or is otherwise malformed, we call the cfg80211 -API to report this to userspace, but that uses a netdev -pointer, which isn't present for P2P-Device. Fix this to -call it only conditionally to ensure cfg80211 won't crash -in the case of P2P-Device. - -This fixes CVE-2022-42722. - -Reported-by: Sönke Huster -Fixes: 9eaf183af741 ("mac80211: Report beacon protection failures to user space") -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/rx.c -+++ b/net/mac80211/rx.c -@@ -1986,10 +1986,11 @@ ieee80211_rx_h_decrypt(struct ieee80211_ - - if (mmie_keyidx < NUM_DEFAULT_KEYS + NUM_DEFAULT_MGMT_KEYS || - mmie_keyidx >= NUM_DEFAULT_KEYS + NUM_DEFAULT_MGMT_KEYS + -- NUM_DEFAULT_BEACON_KEYS) { -- cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, -- skb->data, -- skb->len); -+ NUM_DEFAULT_BEACON_KEYS) { -+ if (rx->sdata->dev) -+ cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, -+ skb->data, -+ skb->len); - return RX_DROP_MONITOR; /* unexpected BIP keyidx */ - } - -@@ -2137,7 +2138,8 @@ ieee80211_rx_h_decrypt(struct ieee80211_ - /* either the frame has been decrypted or will be dropped */ - status->flag |= RX_FLAG_DECRYPTED; - -- if (unlikely(ieee80211_is_beacon(fc) && result == RX_DROP_UNUSABLE)) -+ if (unlikely(ieee80211_is_beacon(fc) && result == RX_DROP_UNUSABLE && -+ rx->sdata->dev)) - cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, - skb->data, skb->len); - diff --git a/package/kernel/mac80211/patches/subsys/359-wifi-cfg80211-update-hidden-BSSes-to-avoid-WARN_ON.patch b/package/kernel/mac80211/patches/subsys/359-wifi-cfg80211-update-hidden-BSSes-to-avoid-WARN_ON.patch deleted file mode 100644 index c689fac854..0000000000 --- a/package/kernel/mac80211/patches/subsys/359-wifi-cfg80211-update-hidden-BSSes-to-avoid-WARN_ON.patch +++ /dev/null @@ -1,85 +0,0 @@ -From: Johannes Berg -Date: Wed, 5 Oct 2022 23:11:43 +0200 -Subject: [PATCH] wifi: cfg80211: update hidden BSSes to avoid WARN_ON -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -commit c90b93b5b782891ebfda49d4e5da36632fefd5d1 upstream. - -When updating beacon elements in a non-transmitted BSS, -also update the hidden sub-entries to the same beacon -elements, so that a future update through other paths -won't trigger a WARN_ON(). - -The warning is triggered because the beacon elements in -the hidden BSSes that are children of the BSS should -always be the same as in the parent. - -Reported-by: Sönke Huster -Tested-by: Sönke Huster -Fixes: 0b8fb8235be8 ("cfg80211: Parsing of Multiple BSSID information in scanning") -Signed-off-by: Johannes Berg ---- - ---- a/net/wireless/scan.c -+++ b/net/wireless/scan.c -@@ -1609,6 +1609,23 @@ struct cfg80211_non_tx_bss { - u8 bssid_index; - }; - -+static void cfg80211_update_hidden_bsses(struct cfg80211_internal_bss *known, -+ const struct cfg80211_bss_ies *new_ies, -+ const struct cfg80211_bss_ies *old_ies) -+{ -+ struct cfg80211_internal_bss *bss; -+ -+ /* Assign beacon IEs to all sub entries */ -+ list_for_each_entry(bss, &known->hidden_list, hidden_list) { -+ const struct cfg80211_bss_ies *ies; -+ -+ ies = rcu_access_pointer(bss->pub.beacon_ies); -+ WARN_ON(ies != old_ies); -+ -+ rcu_assign_pointer(bss->pub.beacon_ies, new_ies); -+ } -+} -+ - static bool - cfg80211_update_known_bss(struct cfg80211_registered_device *rdev, - struct cfg80211_internal_bss *known, -@@ -1632,7 +1649,6 @@ cfg80211_update_known_bss(struct cfg8021 - kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); - } else if (rcu_access_pointer(new->pub.beacon_ies)) { - const struct cfg80211_bss_ies *old; -- struct cfg80211_internal_bss *bss; - - if (known->pub.hidden_beacon_bss && - !list_empty(&known->hidden_list)) { -@@ -1660,16 +1676,7 @@ cfg80211_update_known_bss(struct cfg8021 - if (old == rcu_access_pointer(known->pub.ies)) - rcu_assign_pointer(known->pub.ies, new->pub.beacon_ies); - -- /* Assign beacon IEs to all sub entries */ -- list_for_each_entry(bss, &known->hidden_list, hidden_list) { -- const struct cfg80211_bss_ies *ies; -- -- ies = rcu_access_pointer(bss->pub.beacon_ies); -- WARN_ON(ies != old); -- -- rcu_assign_pointer(bss->pub.beacon_ies, -- new->pub.beacon_ies); -- } -+ cfg80211_update_hidden_bsses(known, new->pub.beacon_ies, old); - - if (old) - kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); -@@ -2319,6 +2326,8 @@ cfg80211_update_notlisted_nontrans(struc - } else { - old = rcu_access_pointer(nontrans_bss->beacon_ies); - rcu_assign_pointer(nontrans_bss->beacon_ies, new_ies); -+ cfg80211_update_hidden_bsses(bss_from_pub(nontrans_bss), -+ new_ies, old); - rcu_assign_pointer(nontrans_bss->ies, new_ies); - if (old) - kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); diff --git a/package/kernel/mac80211/patches/subsys/360-mac80211-fix-a-memory-leak-where-sta_info-is-not-fre.patch b/package/kernel/mac80211/patches/subsys/360-mac80211-fix-a-memory-leak-where-sta_info-is-not-fre.patch deleted file mode 100644 index ff3cb7be53..0000000000 --- a/package/kernel/mac80211/patches/subsys/360-mac80211-fix-a-memory-leak-where-sta_info-is-not-fre.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 4db561ae4a90c2d0e15996634567559e292dc9e5 Mon Sep 17 00:00:00 2001 -From: Ahmed Zaki -Date: Sat, 2 Oct 2021 08:53:29 -0600 -Subject: [PATCH] mac80211: fix a memory leak where sta_info is not freed - -commit 8f9dcc29566626f683843ccac6113a12208315ca upstream. - -The following is from a system that went OOM due to a memory leak: - -wlan0: Allocated STA 74:83:c2:64:0b:87 -wlan0: Allocated STA 74:83:c2:64:0b:87 -wlan0: IBSS finish 74:83:c2:64:0b:87 (---from ieee80211_ibss_add_sta) -wlan0: Adding new IBSS station 74:83:c2:64:0b:87 -wlan0: moving STA 74:83:c2:64:0b:87 to state 2 -wlan0: moving STA 74:83:c2:64:0b:87 to state 3 -wlan0: Inserted STA 74:83:c2:64:0b:87 -wlan0: IBSS finish 74:83:c2:64:0b:87 (---from ieee80211_ibss_work) -wlan0: Adding new IBSS station 74:83:c2:64:0b:87 -wlan0: moving STA 74:83:c2:64:0b:87 to state 2 -wlan0: moving STA 74:83:c2:64:0b:87 to state 3 -. -. -wlan0: expiring inactive not authorized STA 74:83:c2:64:0b:87 -wlan0: moving STA 74:83:c2:64:0b:87 to state 2 -wlan0: moving STA 74:83:c2:64:0b:87 to state 1 -wlan0: Removed STA 74:83:c2:64:0b:87 -wlan0: Destroyed STA 74:83:c2:64:0b:87 - -The ieee80211_ibss_finish_sta() is called twice on the same STA from 2 -different locations. On the second attempt, the allocated STA is not -destroyed creating a kernel memory leak. - -This is happening because sta_info_insert_finish() does not call -sta_info_free() the second time when the STA already exists (returns --EEXIST). Note that the caller sta_info_insert_rcu() assumes STA is -destroyed upon errors. - -Same fix is applied to -ENOMEM. - -Signed-off-by: Ahmed Zaki -Link: https://lore.kernel.org/r/20211002145329.3125293-1-anzaki@gmail.com -[change the error path label to use the existing code] -Signed-off-by: Johannes Berg -Signed-off-by: Viacheslav Sablin -Signed-off-by: Greg Kroah-Hartman ---- - net/mac80211/sta_info.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/net/mac80211/sta_info.c -+++ b/net/mac80211/sta_info.c -@@ -646,13 +646,13 @@ static int sta_info_insert_finish(struct - /* check if STA exists already */ - if (sta_info_get_bss(sdata, sta->sta.addr)) { - err = -EEXIST; -- goto out_err; -+ goto out_cleanup; - } - - sinfo = kzalloc(sizeof(struct station_info), GFP_KERNEL); - if (!sinfo) { - err = -ENOMEM; -- goto out_err; -+ goto out_cleanup; - } - - local->num_sta++; -@@ -708,8 +708,8 @@ static int sta_info_insert_finish(struct - out_drop_sta: - local->num_sta--; - synchronize_net(); -+ out_cleanup: - cleanup_single_sta(sta); -- out_err: - mutex_unlock(&local->sta_mtx); - kfree(sinfo); - rcu_read_lock(); diff --git a/package/kernel/mac80211/patches/subsys/361-wifi-mac80211-Don-t-finalize-CSA-in-IBSS-mode-if-sta.patch b/package/kernel/mac80211/patches/subsys/361-wifi-mac80211-Don-t-finalize-CSA-in-IBSS-mode-if-sta.patch deleted file mode 100644 index dd3e934c00..0000000000 --- a/package/kernel/mac80211/patches/subsys/361-wifi-mac80211-Don-t-finalize-CSA-in-IBSS-mode-if-sta.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 552ba102a6898630a7d16887f29e606d6fabe508 Mon Sep 17 00:00:00 2001 -From: Siddh Raman Pant -Date: Sun, 14 Aug 2022 20:45:12 +0530 -Subject: [PATCH] wifi: mac80211: Don't finalize CSA in IBSS mode if state is - disconnected - -commit 15bc8966b6d3a5b9bfe4c9facfa02f2b69b1e5f0 upstream. - -When we are not connected to a channel, sending channel "switch" -announcement doesn't make any sense. - -The BSS list is empty in that case. This causes the for loop in -cfg80211_get_bss() to be bypassed, so the function returns NULL -(check line 1424 of net/wireless/scan.c), causing the WARN_ON() -in ieee80211_ibss_csa_beacon() to get triggered (check line 500 -of net/mac80211/ibss.c), which was consequently reported on the -syzkaller dashboard. - -Thus, check if we have an existing connection before generating -the CSA beacon in ieee80211_ibss_finish_csa(). - -Cc: stable@vger.kernel.org -Fixes: cd7760e62c2a ("mac80211: add support for CSA in IBSS mode") -Link: https://syzkaller.appspot.com/bug?id=05603ef4ae8926761b678d2939a3b2ad28ab9ca6 -Reported-by: syzbot+b6c9fe29aefe68e4ad34@syzkaller.appspotmail.com -Signed-off-by: Siddh Raman Pant -Tested-by: syzbot+b6c9fe29aefe68e4ad34@syzkaller.appspotmail.com -Link: https://lore.kernel.org/r/20220814151512.9985-1-code@siddh.me -Signed-off-by: Johannes Berg -Signed-off-by: Greg Kroah-Hartman ---- - net/mac80211/ibss.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/net/mac80211/ibss.c -+++ b/net/mac80211/ibss.c -@@ -534,6 +534,10 @@ int ieee80211_ibss_finish_csa(struct iee - - sdata_assert_lock(sdata); - -+ /* When not connected/joined, sending CSA doesn't make sense. */ -+ if (ifibss->state != IEEE80211_IBSS_MLME_JOINED) -+ return -ENOLINK; -+ - /* update cfg80211 bss information with the new channel */ - if (!is_zero_ether_addr(ifibss->bssid)) { - cbss = cfg80211_get_bss(sdata->local->hw.wiphy, diff --git a/package/kernel/mac80211/patches/subsys/362-wifi-mac80211-Fix-UAF-in-ieee80211_scan_rx.patch b/package/kernel/mac80211/patches/subsys/362-wifi-mac80211-Fix-UAF-in-ieee80211_scan_rx.patch deleted file mode 100644 index 50b6b94fbf..0000000000 --- a/package/kernel/mac80211/patches/subsys/362-wifi-mac80211-Fix-UAF-in-ieee80211_scan_rx.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 5d20c6f932f2758078d0454729129c894fe353e7 Mon Sep 17 00:00:00 2001 -From: Siddh Raman Pant -Date: Sat, 20 Aug 2022 01:33:40 +0530 -Subject: [PATCH] wifi: mac80211: Fix UAF in ieee80211_scan_rx() - -commit 60deb9f10eec5c6a20252ed36238b55d8b614a2c upstream. - -ieee80211_scan_rx() tries to access scan_req->flags after a -null check, but a UAF is observed when the scan is completed -and __ieee80211_scan_completed() executes, which then calls -cfg80211_scan_done() leading to the freeing of scan_req. - -Since scan_req is rcu_dereference()'d, prevent the racing in -__ieee80211_scan_completed() by ensuring that from mac80211's -POV it is no longer accessed from an RCU read critical section -before we call cfg80211_scan_done(). - -Cc: stable@vger.kernel.org -Link: https://syzkaller.appspot.com/bug?extid=f9acff9bf08a845f225d -Reported-by: syzbot+f9acff9bf08a845f225d@syzkaller.appspotmail.com -Suggested-by: Johannes Berg -Signed-off-by: Siddh Raman Pant -Link: https://lore.kernel.org/r/20220819200340.34826-1-code@siddh.me -Signed-off-by: Johannes Berg -Signed-off-by: Greg Kroah-Hartman ---- - net/mac80211/scan.c | 11 +++++++---- - 1 file changed, 7 insertions(+), 4 deletions(-) - ---- a/net/mac80211/scan.c -+++ b/net/mac80211/scan.c -@@ -465,16 +465,19 @@ static void __ieee80211_scan_completed(s - scan_req = rcu_dereference_protected(local->scan_req, - lockdep_is_held(&local->mtx)); - -- if (scan_req != local->int_scan_req) { -- local->scan_info.aborted = aborted; -- cfg80211_scan_done(scan_req, &local->scan_info); -- } - RCU_INIT_POINTER(local->scan_req, NULL); - RCU_INIT_POINTER(local->scan_sdata, NULL); - - local->scanning = 0; - local->scan_chandef.chan = NULL; - -+ synchronize_rcu(); -+ -+ if (scan_req != local->int_scan_req) { -+ local->scan_info.aborted = aborted; -+ cfg80211_scan_done(scan_req, &local->scan_info); -+ } -+ - /* Set power back to normal operating levels. */ - ieee80211_hw_config(local, 0); - diff --git a/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch b/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch index 50c24a7746..0e83e9bd8e 100644 --- a/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch +++ b/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch @@ -87,7 +87,7 @@ CFG80211_TESTMODE_DUMP(ieee80211_testmode_dump) --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h -@@ -1448,6 +1448,7 @@ struct ieee80211_local { +@@ -1447,6 +1447,7 @@ struct ieee80211_local { int dynamic_ps_forced_timeout; int user_power_level; /* in dBm, for all interfaces */ diff --git a/package/kernel/mac80211/patches/subsys/800-mac80211-mask-nested-A-MSDU-support-for-mesh.patch b/package/kernel/mac80211/patches/subsys/800-mac80211-mask-nested-A-MSDU-support-for-mesh.patch index e7da94c9cd..a17d6f6161 100644 --- a/package/kernel/mac80211/patches/subsys/800-mac80211-mask-nested-A-MSDU-support-for-mesh.patch +++ b/package/kernel/mac80211/patches/subsys/800-mac80211-mask-nested-A-MSDU-support-for-mesh.patch @@ -24,7 +24,7 @@ Signed-off-by: David Bauer - capab = u16_encode_bits(amsdu, IEEE80211_ADDBA_PARAM_AMSDU_MASK); + capab = 0; -+#ifdef CONFIG_MAC80211_MESH ++#ifdef CPTCFG_MAC80211_MESH + if (!sta->mesh) +#endif + capab = u16_encode_bits(amsdu, IEEE80211_ADDBA_PARAM_AMSDU_MASK); diff --git a/package/kernel/mt76/patches/100-aggregation-definitions.patch b/package/kernel/mt76/patches/100-aggregation-definitions.patch new file mode 100644 index 0000000000..a88d57133f --- /dev/null +++ b/package/kernel/mt76/patches/100-aggregation-definitions.patch @@ -0,0 +1,13 @@ +--- a/mt7915/init.c ++++ b/mt7915/init.c +@@ -327,8 +327,8 @@ mt7915_init_wiphy(struct ieee80211_hw *h + struct mt7915_dev *dev = phy->dev; + + hw->queues = 4; +- hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF; +- hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF; ++ hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; ++ hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; + hw->netdev_features = NETIF_F_RXCSUM; + + hw->radiotap_timestamp.units_pos = diff --git a/package/libs/gettext-full/Makefile b/package/libs/gettext-full/Makefile index f5f5e00542..2319401baf 100644 --- a/package/libs/gettext-full/Makefile +++ b/package/libs/gettext-full/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=gettext-full -PKG_VERSION:=0.21 -PKG_RELEASE:=2 +PKG_VERSION:=0.21.1 +PKG_RELEASE:=1 PKG_SOURCE:=gettext-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=@GNU/gettext -PKG_HASH:=d20fcbb537e02dcf1383197ba05bd0734ef7bf5db06bdb241eb69b7d16b73192 +PKG_HASH:=50dbc8f39797950aa2c98e939947c527e5ac9ebd2c1b99dd7b06ba33a6767ae6 PKG_BUILD_DIR:=$(BUILD_DIR)/gettext-$(PKG_VERSION) HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/gettext-$(PKG_VERSION) diff --git a/package/libs/gettext-full/patches/001-autotools.patch b/package/libs/gettext-full/patches/001-autotools.patch index 034fc938a3..7e1f005dc5 100644 --- a/package/libs/gettext-full/patches/001-autotools.patch +++ b/package/libs/gettext-full/patches/001-autotools.patch @@ -12,7 +12,7 @@ $(INSTALL_DATA) $$dir/$$file $(DESTDIR)$(htmldir)/$$file; \ --- a/gettext-tools/man/Makefile.am +++ b/gettext-tools/man/Makefile.am -@@ -157,8 +157,7 @@ recode-sr-latin.1.html: recode-sr-latin. +@@ -158,8 +158,7 @@ recode-sr-latin.1.html: recode-sr-latin. gettextize.1.html: gettextize.1 autopoint.1.html: autopoint.1 diff --git a/package/libs/gettext-full/patches/010-m4.patch b/package/libs/gettext-full/patches/010-m4.patch index 6d08835e37..fe896db312 100644 --- a/package/libs/gettext-full/patches/010-m4.patch +++ b/package/libs/gettext-full/patches/010-m4.patch @@ -1,14 +1,14 @@ --- a/gettext-runtime/gnulib-m4/stddef_h.m4 +++ b/gettext-runtime/gnulib-m4/stddef_h.m4 -@@ -8,7 +8,7 @@ dnl with or without modifications, as lo - AC_DEFUN([gl_STDDEF_H], +@@ -9,7 +9,7 @@ dnl A placeholder for , for pl + AC_DEFUN_ONCE([gl_STDDEF_H], [ AC_REQUIRE([gl_STDDEF_H_DEFAULTS]) - AC_REQUIRE([gt_TYPE_WCHAR_T]) + AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) - STDDEF_H= - dnl Test whether the type max_align_t exists and whether its alignment + dnl Persuade OpenBSD to declare max_align_t. + AC_REQUIRE([gl_USE_SYSTEM_EXTENSIONS]) --- a/gettext-runtime/gnulib-m4/stdint.m4 +++ b/gettext-runtime/gnulib-m4/stdint.m4 @@ -15,7 +15,7 @@ AC_DEFUN_ONCE([gl_STDINT_H], @@ -22,7 +22,7 @@ dnl macros. --- a/gettext-runtime/gnulib-m4/wchar_h.m4 +++ b/gettext-runtime/gnulib-m4/wchar_h.m4 -@@ -27,7 +27,7 @@ AC_DEFUN([gl_WCHAR_H], +@@ -27,7 +27,7 @@ AC_DEFUN_ONCE([gl_WCHAR_H], AC_REQUIRE([gl_FEATURES_H]) @@ -44,7 +44,7 @@ [AC_COMPILE_IFELSE( --- a/gettext-runtime/gnulib-m4/wctype_h.m4 +++ b/gettext-runtime/gnulib-m4/wctype_h.m4 -@@ -22,7 +22,7 @@ AC_DEFUN([gl_WCTYPE_H], +@@ -22,7 +22,7 @@ AC_DEFUN_ONCE([gl_WCTYPE_H], fi AC_SUBST([HAVE_ISWCNTRL]) @@ -77,26 +77,6 @@ [ AC_CACHE_CHECK([for wint_t], [gt_cv_c_wint_t], [AC_COMPILE_IFELSE( ---- a/gettext-runtime/intl/Makefile.am -+++ b/gettext-runtime/intl/Makefile.am -@@ -274,7 +274,7 @@ libgnuintl.h: $(srcdir)/libgnuintl.in.h - -e 's,@''HAVE_ASPRINTF''@,@HAVE_ASPRINTF@,g' \ - -e 's,@''HAVE_SNPRINTF''@,@HAVE_SNPRINTF@,g' \ - -e 's,@''HAVE_WPRINTF''@,@HAVE_WPRINTF@,g' \ -- -e 's,@''HAVE_NAMELESS_LOCALES''@,@HAVE_NAMELESS_LOCALES@,g' \ -+ -e 's,@''HAVE_NAMELESS_LOCALES''@,0,g' \ - -e 's,@''HAVE_NEWLOCALE''@,@HAVE_NEWLOCALE@,g' \ - < $(srcdir)/libgnuintl.in.h \ - | if test '@WOE32DLL@' = yes; then \ -@@ -294,7 +294,7 @@ libintl.h: $(srcdir)/libgnuintl.in.h - -e 's,@''HAVE_ASPRINTF''@,@HAVE_ASPRINTF@,g' \ - -e 's,@''HAVE_SNPRINTF''@,@HAVE_SNPRINTF@,g' \ - -e 's,@''HAVE_WPRINTF''@,@HAVE_WPRINTF@,g' \ -- -e 's,@''HAVE_NAMELESS_LOCALES''@,@HAVE_NAMELESS_LOCALES@,g' \ -+ -e 's,@''HAVE_NAMELESS_LOCALES''@,0,g' \ - -e 's,@''HAVE_NEWLOCALE''@,@HAVE_NEWLOCALE@,g' \ - < $(srcdir)/libgnuintl.in.h > libintl.h - MOSTLYCLEANFILES += libintl.h --- a/gettext-runtime/libasprintf/configure.ac +++ b/gettext-runtime/libasprintf/configure.ac @@ -76,8 +76,8 @@ dnl Checks for typedefs, structures, and @@ -145,30 +125,6 @@ AC_REQUIRE([gl_AC_HEADER_INTTYPES_H]) AC_REQUIRE([gt_TYPE_INTMAX_T]) AC_REQUIRE([gt_PRINTF_POSIX]) ---- a/gettext-tools/gnulib-m4/gnulib-comp.m4 -+++ b/gettext-tools/gnulib-m4/gnulib-comp.m4 -@@ -1843,8 +1843,8 @@ changequote([, ])dnl - AC_REQUIRE([gl_SOCKETS]) - gl_TYPE_SOCKLEN_T - gl_STDALIGN_H -- AC_REQUIRE([gt_TYPE_WCHAR_T]) -- AC_REQUIRE([gt_TYPE_WINT_T]) -+ AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) -+ AC_REQUIRE([gt_TYPE_WINT_T_GT]) - gl_FUNC_STRERROR_R - if test $HAVE_DECL_STRERROR_R = 0 || test $REPLACE_STRERROR_R = 1; then - AC_LIBOBJ([strerror_r]) ---- a/gettext-tools/gnulib-m4/stddef_h.m4 -+++ b/gettext-tools/gnulib-m4/stddef_h.m4 -@@ -8,7 +8,7 @@ dnl with or without modifications, as lo - AC_DEFUN([gl_STDDEF_H], - [ - AC_REQUIRE([gl_STDDEF_H_DEFAULTS]) -- AC_REQUIRE([gt_TYPE_WCHAR_T]) -+ AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) - STDDEF_H= - - dnl Test whether the type max_align_t exists and whether its alignment --- a/gettext-tools/gnulib-m4/stdint.m4 +++ b/gettext-tools/gnulib-m4/stdint.m4 @@ -15,7 +15,7 @@ AC_DEFUN_ONCE([gl_STDINT_H], @@ -216,7 +172,7 @@ dnl is defined as a weak alias of snprintf; we prefer to use the latter). --- a/gettext-tools/gnulib-m4/wchar_h.m4 +++ b/gettext-tools/gnulib-m4/wchar_h.m4 -@@ -27,7 +27,7 @@ AC_DEFUN([gl_WCHAR_H], +@@ -27,7 +27,7 @@ AC_DEFUN_ONCE([gl_WCHAR_H], AC_REQUIRE([gl_FEATURES_H]) @@ -238,7 +194,7 @@ [AC_COMPILE_IFELSE( --- a/gettext-tools/gnulib-m4/wctype_h.m4 +++ b/gettext-tools/gnulib-m4/wctype_h.m4 -@@ -22,7 +22,7 @@ AC_DEFUN([gl_WCTYPE_H], +@@ -22,7 +22,7 @@ AC_DEFUN_ONCE([gl_WCTYPE_H], fi AC_SUBST([HAVE_ISWCNTRL]) @@ -271,37 +227,6 @@ [ AC_CACHE_CHECK([for wint_t], [gt_cv_c_wint_t], [AC_COMPILE_IFELSE( ---- a/gettext-tools/intl/Makefile.am -+++ b/gettext-tools/intl/Makefile.am -@@ -274,7 +274,7 @@ libgnuintl.h: $(srcdir)/libgnuintl.in.h - -e 's,@''HAVE_ASPRINTF''@,@HAVE_ASPRINTF@,g' \ - -e 's,@''HAVE_SNPRINTF''@,@HAVE_SNPRINTF@,g' \ - -e 's,@''HAVE_WPRINTF''@,@HAVE_WPRINTF@,g' \ -- -e 's,@''HAVE_NAMELESS_LOCALES''@,@HAVE_NAMELESS_LOCALES@,g' \ -+ -e 's,@''HAVE_NAMELESS_LOCALES''@,0,g' \ - -e 's,@''HAVE_NEWLOCALE''@,@HAVE_NEWLOCALE@,g' \ - < $(srcdir)/libgnuintl.in.h \ - | if test '@WOE32DLL@' = yes; then \ -@@ -294,7 +294,7 @@ libintl.h: $(srcdir)/libgnuintl.in.h - -e 's,@''HAVE_ASPRINTF''@,@HAVE_ASPRINTF@,g' \ - -e 's,@''HAVE_SNPRINTF''@,@HAVE_SNPRINTF@,g' \ - -e 's,@''HAVE_WPRINTF''@,@HAVE_WPRINTF@,g' \ -- -e 's,@''HAVE_NAMELESS_LOCALES''@,@HAVE_NAMELESS_LOCALES@,g' \ -+ -e 's,@''HAVE_NAMELESS_LOCALES''@,0,g' \ - -e 's,@''HAVE_NEWLOCALE''@,@HAVE_NEWLOCALE@,g' \ - < $(srcdir)/libgnuintl.in.h > libintl.h - MOSTLYCLEANFILES += libintl.h ---- a/libtextstyle/gnulib-m4/stddef_h.m4 -+++ b/libtextstyle/gnulib-m4/stddef_h.m4 -@@ -8,7 +8,7 @@ dnl with or without modifications, as lo - AC_DEFUN([gl_STDDEF_H], - [ - AC_REQUIRE([gl_STDDEF_H_DEFAULTS]) -- AC_REQUIRE([gt_TYPE_WCHAR_T]) -+ AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) - STDDEF_H= - - dnl Test whether the type max_align_t exists and whether its alignment --- a/libtextstyle/gnulib-m4/stdint.m4 +++ b/libtextstyle/gnulib-m4/stdint.m4 @@ -15,7 +15,7 @@ AC_DEFUN_ONCE([gl_STDINT_H], @@ -349,7 +274,7 @@ dnl is defined as a weak alias of snprintf; we prefer to use the latter). --- a/libtextstyle/gnulib-m4/wchar_h.m4 +++ b/libtextstyle/gnulib-m4/wchar_h.m4 -@@ -27,7 +27,7 @@ AC_DEFUN([gl_WCHAR_H], +@@ -27,7 +27,7 @@ AC_DEFUN_ONCE([gl_WCHAR_H], AC_REQUIRE([gl_FEATURES_H]) @@ -380,3 +305,38 @@ [ AC_CACHE_CHECK([for wint_t], [gt_cv_c_wint_t], [AC_COMPILE_IFELSE( +--- a/gettext-tools/gnulib-m4/gnulib-comp.m4 ++++ b/gettext-tools/gnulib-m4/gnulib-comp.m4 +@@ -2218,8 +2218,8 @@ changequote([, ])dnl + AC_REQUIRE([gl_SOCKETLIB]) + AC_REQUIRE([gl_SOCKETS]) + gl_TYPE_SOCKLEN_T +- AC_REQUIRE([gt_TYPE_WCHAR_T]) +- AC_REQUIRE([gt_TYPE_WINT_T]) ++ AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) ++ AC_REQUIRE([gt_TYPE_WINT_T_GT]) + gl_FUNC_STRERROR_R + AS_IF([test $HAVE_DECL_STRERROR_R = 0 || test $REPLACE_STRERROR_R = 1], [ + AC_LIBOBJ([strerror_r]) +--- a/libtextstyle/gnulib-m4/stddef_h.m4 ++++ b/libtextstyle/gnulib-m4/stddef_h.m4 +@@ -9,7 +9,7 @@ dnl A placeholder for , for pl + AC_DEFUN_ONCE([gl_STDDEF_H], + [ + AC_REQUIRE([gl_STDDEF_H_DEFAULTS]) +- AC_REQUIRE([gt_TYPE_WCHAR_T]) ++ AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) + + dnl Persuade OpenBSD to declare max_align_t. + AC_REQUIRE([gl_USE_SYSTEM_EXTENSIONS]) +--- a/gettext-tools/gnulib-m4/stddef_h.m4 ++++ b/gettext-tools/gnulib-m4/stddef_h.m4 +@@ -9,7 +9,7 @@ dnl A placeholder for , for pl + AC_DEFUN_ONCE([gl_STDDEF_H], + [ + AC_REQUIRE([gl_STDDEF_H_DEFAULTS]) +- AC_REQUIRE([gt_TYPE_WCHAR_T]) ++ AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) + + dnl Persuade OpenBSD to declare max_align_t. + AC_REQUIRE([gl_USE_SYSTEM_EXTENSIONS]) diff --git a/package/libs/libbsd/Makefile b/package/libs/libbsd/Makefile index 47af01f555..789126cb82 100644 --- a/package/libs/libbsd/Makefile +++ b/package/libs/libbsd/Makefile @@ -1,12 +1,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=libbsd -PKG_VERSION:=0.11.6 +PKG_VERSION:=0.11.7 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=https://libbsd.freedesktop.org/releases -PKG_HASH:=19b38f3172eaf693e6e1c68714636190c7e48851e45224d720b3b5bc0499b5df +PKG_HASH:=9baa186059ebbf25c06308e9f991fda31f7183c0f24931826d83aa6abd8a0261 PKG_LICENSE:=BSD-4-Clause PKG_LICENSE_FILES:=COPYING diff --git a/package/libs/readline/Makefile b/package/libs/readline/Makefile index a6ceec1fce..015a1ae2da 100644 --- a/package/libs/readline/Makefile +++ b/package/libs/readline/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=readline -PKG_VERSION:=8.1.2 +PKG_VERSION:=8.2 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@GNU/readline -PKG_HASH:=7589a2381a8419e68654a47623ce7dfcb756815c8fee726b98f90bf668af7bc6 +PKG_HASH:=3feb7171f16a84ee82ca18a36d7b9be109a52c04f492a053331d7d1095007c35 PKG_LICENSE:=GPL-3.0-or-later PKG_LICENSE_FILES:=COPYING diff --git a/package/network/ipv6/thc-ipv6/Makefile b/package/network/ipv6/thc-ipv6/Makefile index 91bacf625e..b26b0507fb 100644 --- a/package/network/ipv6/thc-ipv6/Makefile +++ b/package/network/ipv6/thc-ipv6/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=thc-ipv6 -PKG_VERSION:=2.7 +PKG_VERSION:=3.8 PKG_RELEASE:=1 PKG_LICENSE:=GPL-3.0 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@GITHUB/vanhauser-thc/THC-Archive/master/Tools -PKG_HASH:=440a3ae98b57100c397ec4f8634468dbbb0c3b48788c6b74af2a597a90544a96 +PKG_HASH:=b60be61a8b0a944a66e3b719704b4c03c1bc2c22f32d5d21e99e434c82a9d769 PKG_MAINTAINER:=Jo-Philipp Wich @@ -31,7 +31,7 @@ THC_APPLETS := \ fuzz_dhcps6 implementation6 implementation6d inverse_lookup6 \ kill_router6 ndpexhaust6 node_query6 parasite6 passive_discovery6 \ randicmp6 redir6 rsmurf6 sendpees6 sendpeesmp6 smurf6 thcping6 \ - toobig6 trace6 + toobig6 trace6 toobigsniff6 flood_unreach6 connect6 THC_DEPENDS_dnsdict6 := +libpthread THC_DEPENDS_thcping6 := +librt diff --git a/package/network/ipv6/thc-ipv6/patches/100-no-ssl.patch b/package/network/ipv6/thc-ipv6/patches/100-no-ssl.patch index 1ef1f66be8..118c2a705b 100644 --- a/package/network/ipv6/thc-ipv6/patches/100-no-ssl.patch +++ b/package/network/ipv6/thc-ipv6/patches/100-no-ssl.patch @@ -1,9 +1,10 @@ --- a/Makefile +++ b/Makefile -@@ -1,5 +1,5 @@ +@@ -1,6 +1,6 @@ # Comment out if openssl-dev is not present + # of if you want to compile statc -HAVE_SSL=yes +#HAVE_SSL=yes - CC=gcc - #CFLAGS=-g + # comment in if you want to compile static tools + #STATIC=-static diff --git a/package/network/ipv6/thc-ipv6/patches/000-cflags_override.patch b/package/network/ipv6/thc-ipv6/patches/101-remove-march-native.patch similarity index 69% rename from package/network/ipv6/thc-ipv6/patches/000-cflags_override.patch rename to package/network/ipv6/thc-ipv6/patches/101-remove-march-native.patch index e1c36b6c6c..da6c7caa7c 100644 --- a/package/network/ipv6/thc-ipv6/patches/000-cflags_override.patch +++ b/package/network/ipv6/thc-ipv6/patches/101-remove-march-native.patch @@ -1,12 +1,11 @@ -diff -urN thc-ipv6-2.7/Makefile thc-ipv6-2.7.new/Makefile ---- thc-ipv6-2.7/Makefile 2014-12-27 05:05:30.000000000 -0800 -+++ thc-ipv6-2.7.new/Makefile 2017-02-04 20:55:51.679898101 -0800 -@@ -3,7 +3,7 @@ +--- a/Makefile ++++ b/Makefile +@@ -7,7 +7,7 @@ HAVE_SSL=yes - CC=gcc + #CC=gcc #CFLAGS=-g --CFLAGS=-O2 -+CFLAGS?=-O2 +-CFLAGS+=-g -O3 -march=native -flto -falign-functions -falign-jumps -falign-loops -falign-labels -freorder-blocks ++CFLAGS+=-g -O3 -flto -falign-functions -falign-jumps -falign-loops -falign-labels -freorder-blocks CFLAGS+=$(if $(HAVE_SSL),-D_HAVE_SSL,) LDFLAGS+=-lpcap $(if $(HAVE_SSL),-lssl -lcrypto,) - PROGRAMS=parasite6 dos-new-ip6 detect-new-ip6 fake_router6 fake_advertise6 fake_solicitate6 fake_mld6 fake_mld26 fake_mldrouter6 flood_mldrouter6 fake_mipv6 redir6 smurf6 alive6 toobig6 rsmurf6 implementation6 implementation6d sendpees6 sendpeesmp6 randicmp6 fuzz_ip6 flood_mld6 flood_mld26 flood_router6 flood_advertise6 flood_solicitate6 trace6 exploit6 denial6 fake_dhcps6 flood_dhcpc6 fake_dns6d fragmentation6 kill_router6 fake_dnsupdate6 ndpexhaust6 detect_sniffer6 dump_router6 fake_router26 flood_router26 passive_discovery6 dnsrevenum6 inverse_lookup6 node_query6 address6 covert_send6 covert_send6d inject_alive6 firewall6 ndpexhaust26 fake_pim6 thcsyn6 redirsniff6 flood_redir6 four2six dump_dhcp6 fuzz_dhcps6 flood_rs6 fuzz_dhcpc6 + PROGRAMS=parasite6 dos-new-ip6 detect-new-ip6 fake_router6 fake_advertise6 fake_solicitate6 fake_mld6 fake_mld26 fake_mldrouter6 flood_mldrouter6 fake_mipv6 redir6 smurf6 alive6 toobig6 rsmurf6 implementation6 implementation6d sendpees6 sendpeesmp6 randicmp6 fuzz_ip6 flood_mld6 flood_mld26 flood_router6 flood_advertise6 flood_solicitate6 trace6 exploit6 denial6 fake_dhcps6 flood_dhcpc6 fake_dns6d fragmentation6 kill_router6 fake_dnsupdate6 ndpexhaust6 detect_sniffer6 dump_router6 fake_router26 flood_router26 passive_discovery6 dnsrevenum6 inverse_lookup6 node_query6 address6 covert_send6 covert_send6d inject_alive6 firewall6 ndpexhaust26 fake_pim6 thcsyn6 redirsniff6 flood_redir6 four2six dump_dhcp6 flood_rs6 fuzz_dhcps6 fuzz_dhcpc6 toobigsniff6 flood_unreach6 connect6 diff --git a/package/network/utils/iproute2/Makefile b/package/network/utils/iproute2/Makefile index 5255400513..6ef0b1a96a 100644 --- a/package/network/utils/iproute2/Makefile +++ b/package/network/utils/iproute2/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=iproute2 -PKG_VERSION:=5.19.0 +PKG_VERSION:=6.0.0 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=@KERNEL/linux/utils/net/iproute2 -PKG_HASH:=26b7a34d6a7fd2f7a42e2b39c5a90cb61bac522d1096067ffeb195e5693d7791 +PKG_HASH:=523139e9e72aec996374fa2de74be4c53d2dd05589488934d21ff97bae19580a PKG_BUILD_PARALLEL:=1 PKG_BUILD_DEPENDS:=iptables PKG_LICENSE:=GPL-2.0 diff --git a/package/network/utils/iproute2/patches/010-ipstats-Add-param.h-for-musl.patch b/package/network/utils/iproute2/patches/010-ipstats-Add-param.h-for-musl.patch deleted file mode 100644 index d99ae6e65c..0000000000 --- a/package/network/utils/iproute2/patches/010-ipstats-Add-param.h-for-musl.patch +++ /dev/null @@ -1,23 +0,0 @@ -From cf6b60c504d4be5e1df2b2745e55d677967831d0 Mon Sep 17 00:00:00 2001 -From: Changhyeok Bae -Date: Tue, 9 Aug 2022 04:01:05 +0000 -Subject: [PATCH 1/5] ipstats: Add param.h for musl - -Fix build error for musl -| /usr/src/debug/iproute2/5.19.0-r0/iproute2-5.19.0/ip/ipstats.c:231: undefined reference to `MIN' - -Signed-off-by: Changhyeok Bae ---- - ip/ipstats.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/ip/ipstats.c -+++ b/ip/ipstats.c -@@ -1,6 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0+ - #include - #include -+#include - - #include "list.h" - #include "utils.h" diff --git a/package/network/utils/iproute2/patches/140-keep_libmnl_optional.patch b/package/network/utils/iproute2/patches/140-keep_libmnl_optional.patch index a8cdd103ba..7f68f43616 100644 --- a/package/network/utils/iproute2/patches/140-keep_libmnl_optional.patch +++ b/package/network/utils/iproute2/patches/140-keep_libmnl_optional.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -411,7 +411,7 @@ check_tirpc() +@@ -412,7 +412,7 @@ check_tirpc() check_mnl() { diff --git a/package/network/utils/iproute2/patches/145-keep_libelf_optional.patch b/package/network/utils/iproute2/patches/145-keep_libelf_optional.patch index 0c5c3f59ed..2eaae88198 100644 --- a/package/network/utils/iproute2/patches/145-keep_libelf_optional.patch +++ b/package/network/utils/iproute2/patches/145-keep_libelf_optional.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -266,7 +266,7 @@ EOF +@@ -267,7 +267,7 @@ EOF check_elf() { diff --git a/package/network/utils/iproute2/patches/150-keep_libcap_optional.patch b/package/network/utils/iproute2/patches/150-keep_libcap_optional.patch index 4cce2c3ca6..c574840fa8 100644 --- a/package/network/utils/iproute2/patches/150-keep_libcap_optional.patch +++ b/package/network/utils/iproute2/patches/150-keep_libcap_optional.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -469,7 +469,7 @@ EOF +@@ -470,7 +470,7 @@ EOF check_cap() { diff --git a/package/network/utils/iproute2/patches/155-keep_tirpc_optional.patch b/package/network/utils/iproute2/patches/155-keep_tirpc_optional.patch index 28ba7e5217..4ee6245d3b 100644 --- a/package/network/utils/iproute2/patches/155-keep_tirpc_optional.patch +++ b/package/network/utils/iproute2/patches/155-keep_tirpc_optional.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -398,7 +398,7 @@ check_selinux() +@@ -399,7 +399,7 @@ check_selinux() check_tirpc() { diff --git a/package/network/utils/iproute2/patches/170-ip_tiny.patch b/package/network/utils/iproute2/patches/170-ip_tiny.patch index ba2cb0637a..9e95bcc2d6 100644 --- a/package/network/utils/iproute2/patches/170-ip_tiny.patch +++ b/package/network/utils/iproute2/patches/170-ip_tiny.patch @@ -105,4 +105,4 @@ + UTILOBJ = utils.o utils_math.o rt_names.o ll_map.o ll_types.o ll_proto.o ll_addr.o \ inet_proto.o namespace.o json_writer.o json_print.o json_print_math.o \ - names.o color.o bpf_legacy.o bpf_glue.o exec.o fs.o cg_map.o + names.o color.o bpf_legacy.o bpf_glue.o exec.o fs.o cg_map.o ppp_proto.o diff --git a/package/network/utils/iproute2/patches/190-fix-nls-rpath-link.patch b/package/network/utils/iproute2/patches/190-fix-nls-rpath-link.patch index c7fceb2e22..2f3f90fe1a 100644 --- a/package/network/utils/iproute2/patches/190-fix-nls-rpath-link.patch +++ b/package/network/utils/iproute2/patches/190-fix-nls-rpath-link.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -290,7 +290,7 @@ int main(int argc, char **argv) { +@@ -291,7 +291,7 @@ int main(int argc, char **argv) { } EOF @@ -9,7 +9,7 @@ local ret=$? rm -f $TMPDIR/libbpf_test.c $TMPDIR/libbpf_test -@@ -308,7 +308,7 @@ int main(int argc, char **argv) { +@@ -309,7 +309,7 @@ int main(int argc, char **argv) { } EOF diff --git a/package/network/utils/iproute2/patches/200-drop_libbsd_dependency.patch b/package/network/utils/iproute2/patches/200-drop_libbsd_dependency.patch index d1948860e8..052bdd84eb 100644 --- a/package/network/utils/iproute2/patches/200-drop_libbsd_dependency.patch +++ b/package/network/utils/iproute2/patches/200-drop_libbsd_dependency.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -455,14 +455,8 @@ EOF +@@ -456,14 +456,8 @@ EOF if $CC -I$INCLUDE -o $TMPDIR/strtest $TMPDIR/strtest.c >/dev/null 2>&1; then echo "no" else diff --git a/package/network/utils/iproute2/patches/300-selinux-configurable.patch b/package/network/utils/iproute2/patches/300-selinux-configurable.patch index 817abf7d17..adfa405c7f 100644 --- a/package/network/utils/iproute2/patches/300-selinux-configurable.patch +++ b/package/network/utils/iproute2/patches/300-selinux-configurable.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -385,7 +385,7 @@ check_libbpf() +@@ -386,7 +386,7 @@ check_libbpf() check_selinux() # SELinux is a compile time option in the ss utility { diff --git a/package/utils/mtd-utils/Makefile b/package/utils/mtd-utils/Makefile index 2f54b3ad0d..afbfbceff5 100644 --- a/package/utils/mtd-utils/Makefile +++ b/package/utils/mtd-utils/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mtd-utils -PKG_VERSION:=2.1.4 +PKG_VERSION:=2.1.5 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:=https://infraroot.at/pub/mtd/ -PKG_HASH:=2c6711d15d282c47cb3867b6857340597e26d332c238465134c602e5eef71b99 +PKG_HASH:=386e27fd121699b6b729bc2e8e04dda987b31cca6b16e12fb6cc6dcf26449f46 PKG_INSTALL:=1 PKG_FIXUP:=autoreconf diff --git a/package/utils/mtd-utils/patches/130-lzma_jffs2.patch b/package/utils/mtd-utils/patches/130-lzma_jffs2.patch index 55930ddc86..db683063d5 100644 --- a/package/utils/mtd-utils/patches/130-lzma_jffs2.patch +++ b/package/utils/mtd-utils/patches/130-lzma_jffs2.patch @@ -5020,7 +5020,7 @@ +} --- a/jffsX-utils/mkfs.jffs2.c +++ b/jffsX-utils/mkfs.jffs2.c -@@ -1667,11 +1667,11 @@ int main(int argc, char **argv) +@@ -1668,11 +1668,11 @@ int main(int argc, char **argv) } erase_block_size *= units; diff --git a/target/linux/armvirt/64/config-5.15 b/target/linux/armvirt/64/config-5.15 index 692619daba..19ae3dc0cf 100644 --- a/target/linux/armvirt/64/config-5.15 +++ b/target/linux/armvirt/64/config-5.15 @@ -50,6 +50,7 @@ CONFIG_CLK_VEXPRESS_OSC=y # CONFIG_COMPAT_32BIT_TIME is not set CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_BS=y diff --git a/target/linux/at91/Makefile b/target/linux/at91/Makefile index af0dc3f338..20dc43cb9e 100644 --- a/target/linux/at91/Makefile +++ b/target/linux/at91/Makefile @@ -11,6 +11,7 @@ FEATURES:=ext4 squashfs targz usbgadget ubifs SUBTARGETS:=sama7 sama5 sam9x KERNEL_PATCHVER:=5.10 +KERNEL_TESTING_PATCHVER:=5.15 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/at91/patches-5.15/100-clk-at91-re-factor-clocks-suspend-resume.patch b/target/linux/at91/patches-5.15/100-clk-at91-re-factor-clocks-suspend-resume.patch new file mode 100644 index 0000000000..5d399f6535 --- /dev/null +++ b/target/linux/at91/patches-5.15/100-clk-at91-re-factor-clocks-suspend-resume.patch @@ -0,0 +1,1342 @@ +From 65bb4687b2a5c6f02f44345540c3389d6e7523e7 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:05 +0300 +Subject: [PATCH 234/247] clk: at91: re-factor clocks suspend/resume + +SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where +most of the SoC's components are powered off (including PMC). Resuming +from this mode is done with the help of bootloader. Peripherals are not +aware of the power saving mode thus most of them are disabling clocks in +proper suspend API and re-enable them in resume API without taking into +account the previously setup rate. Moreover some of the peripherals are +acting as wakeup sources and are not disabling the clocks in this +scenario, when suspending. Since backup mode cuts the power for +peripherals, in resume part these clocks needs to be re-configured. + +The initial PMC suspend/resume code was designed only for SAMA5D2's PMC +(as it was the only one supporting backup mode). SAMA7G supports also +backup mode and its PMC is different (few new functionalities, different +registers offsets, different offsets in registers for each +functionalities). To address both SAMA5D2 and SAMA7G5 PMC add +.save_context()/.resume_context() support to each clocks driver and call +this from PMC driver. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-generated.c | 46 +++++-- + drivers/clk/at91/clk-main.c | 66 ++++++++++ + drivers/clk/at91/clk-master.c | 194 ++++++++++++++++++++++++++-- + drivers/clk/at91/clk-peripheral.c | 40 +++++- + drivers/clk/at91/clk-pll.c | 39 ++++++ + drivers/clk/at91/clk-programmable.c | 29 ++++- + drivers/clk/at91/clk-sam9x60-pll.c | 68 +++++++++- + drivers/clk/at91/clk-system.c | 20 +++ + drivers/clk/at91/clk-usb.c | 27 ++++ + drivers/clk/at91/clk-utmi.c | 39 ++++++ + drivers/clk/at91/pmc.c | 147 +-------------------- + drivers/clk/at91/pmc.h | 24 ++-- + 12 files changed, 558 insertions(+), 181 deletions(-) + +--- a/drivers/clk/at91/clk-generated.c ++++ b/drivers/clk/at91/clk-generated.c +@@ -27,6 +27,7 @@ struct clk_generated { + u32 id; + u32 gckdiv; + const struct clk_pcr_layout *layout; ++ struct at91_clk_pms pms; + u8 parent_id; + int chg_pid; + }; +@@ -34,25 +35,35 @@ struct clk_generated { + #define to_clk_generated(hw) \ + container_of(hw, struct clk_generated, hw) + +-static int clk_generated_enable(struct clk_hw *hw) ++static int clk_generated_set(struct clk_generated *gck, int status) + { +- struct clk_generated *gck = to_clk_generated(hw); + unsigned long flags; +- +- pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", +- __func__, gck->gckdiv, gck->parent_id); ++ unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0; + + spin_lock_irqsave(gck->lock, flags); + regmap_write(gck->regmap, gck->layout->offset, + (gck->id & gck->layout->pid_mask)); + regmap_update_bits(gck->regmap, gck->layout->offset, + AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | +- gck->layout->cmd | AT91_PMC_PCR_GCKEN, ++ gck->layout->cmd | enable, + field_prep(gck->layout->gckcss_mask, gck->parent_id) | + gck->layout->cmd | + FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) | +- AT91_PMC_PCR_GCKEN); ++ enable); + spin_unlock_irqrestore(gck->lock, flags); ++ ++ return 0; ++} ++ ++static int clk_generated_enable(struct clk_hw *hw) ++{ ++ struct clk_generated *gck = to_clk_generated(hw); ++ ++ pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", ++ __func__, gck->gckdiv, gck->parent_id); ++ ++ clk_generated_set(gck, 1); ++ + return 0; + } + +@@ -249,6 +260,23 @@ static int clk_generated_set_rate(struct + return 0; + } + ++static int clk_generated_save_context(struct clk_hw *hw) ++{ ++ struct clk_generated *gck = to_clk_generated(hw); ++ ++ gck->pms.status = clk_generated_is_enabled(&gck->hw); ++ ++ return 0; ++} ++ ++static void clk_generated_restore_context(struct clk_hw *hw) ++{ ++ struct clk_generated *gck = to_clk_generated(hw); ++ ++ if (gck->pms.status) ++ clk_generated_set(gck, gck->pms.status); ++} ++ + static const struct clk_ops generated_ops = { + .enable = clk_generated_enable, + .disable = clk_generated_disable, +@@ -258,6 +286,8 @@ static const struct clk_ops generated_op + .get_parent = clk_generated_get_parent, + .set_parent = clk_generated_set_parent, + .set_rate = clk_generated_set_rate, ++ .save_context = clk_generated_save_context, ++ .restore_context = clk_generated_restore_context, + }; + + /** +@@ -324,8 +354,6 @@ at91_clk_register_generated(struct regma + if (ret) { + kfree(gck); + hw = ERR_PTR(ret); +- } else { +- pmc_register_id(id); + } + + return hw; +--- a/drivers/clk/at91/clk-main.c ++++ b/drivers/clk/at91/clk-main.c +@@ -28,6 +28,7 @@ + struct clk_main_osc { + struct clk_hw hw; + struct regmap *regmap; ++ struct at91_clk_pms pms; + }; + + #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw) +@@ -37,6 +38,7 @@ struct clk_main_rc_osc { + struct regmap *regmap; + unsigned long frequency; + unsigned long accuracy; ++ struct at91_clk_pms pms; + }; + + #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw) +@@ -51,6 +53,7 @@ struct clk_rm9200_main { + struct clk_sam9x5_main { + struct clk_hw hw; + struct regmap *regmap; ++ struct at91_clk_pms pms; + u8 parent; + }; + +@@ -120,10 +123,29 @@ static int clk_main_osc_is_prepared(stru + return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp); + } + ++static int clk_main_osc_save_context(struct clk_hw *hw) ++{ ++ struct clk_main_osc *osc = to_clk_main_osc(hw); ++ ++ osc->pms.status = clk_main_osc_is_prepared(hw); ++ ++ return 0; ++} ++ ++static void clk_main_osc_restore_context(struct clk_hw *hw) ++{ ++ struct clk_main_osc *osc = to_clk_main_osc(hw); ++ ++ if (osc->pms.status) ++ clk_main_osc_prepare(hw); ++} ++ + static const struct clk_ops main_osc_ops = { + .prepare = clk_main_osc_prepare, + .unprepare = clk_main_osc_unprepare, + .is_prepared = clk_main_osc_is_prepared, ++ .save_context = clk_main_osc_save_context, ++ .restore_context = clk_main_osc_restore_context, + }; + + struct clk_hw * __init +@@ -240,12 +262,31 @@ static unsigned long clk_main_rc_osc_rec + return osc->accuracy; + } + ++static int clk_main_rc_osc_save_context(struct clk_hw *hw) ++{ ++ struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); ++ ++ osc->pms.status = clk_main_rc_osc_is_prepared(hw); ++ ++ return 0; ++} ++ ++static void clk_main_rc_osc_restore_context(struct clk_hw *hw) ++{ ++ struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); ++ ++ if (osc->pms.status) ++ clk_main_rc_osc_prepare(hw); ++} ++ + static const struct clk_ops main_rc_osc_ops = { + .prepare = clk_main_rc_osc_prepare, + .unprepare = clk_main_rc_osc_unprepare, + .is_prepared = clk_main_rc_osc_is_prepared, + .recalc_rate = clk_main_rc_osc_recalc_rate, + .recalc_accuracy = clk_main_rc_osc_recalc_accuracy, ++ .save_context = clk_main_rc_osc_save_context, ++ .restore_context = clk_main_rc_osc_restore_context, + }; + + struct clk_hw * __init +@@ -465,12 +506,37 @@ static u8 clk_sam9x5_main_get_parent(str + return clk_main_parent_select(status); + } + ++static int clk_sam9x5_main_save_context(struct clk_hw *hw) ++{ ++ struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); ++ ++ clkmain->pms.status = clk_main_rc_osc_is_prepared(&clkmain->hw); ++ clkmain->pms.parent = clk_sam9x5_main_get_parent(&clkmain->hw); ++ ++ return 0; ++} ++ ++static void clk_sam9x5_main_restore_context(struct clk_hw *hw) ++{ ++ struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); ++ int ret; ++ ++ ret = clk_sam9x5_main_set_parent(hw, clkmain->pms.parent); ++ if (ret) ++ return; ++ ++ if (clkmain->pms.status) ++ clk_sam9x5_main_prepare(hw); ++} ++ + static const struct clk_ops sam9x5_main_ops = { + .prepare = clk_sam9x5_main_prepare, + .is_prepared = clk_sam9x5_main_is_prepared, + .recalc_rate = clk_sam9x5_main_recalc_rate, + .set_parent = clk_sam9x5_main_set_parent, + .get_parent = clk_sam9x5_main_get_parent, ++ .save_context = clk_sam9x5_main_save_context, ++ .restore_context = clk_sam9x5_main_restore_context, + }; + + struct clk_hw * __init +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -37,6 +37,7 @@ struct clk_master { + spinlock_t *lock; + const struct clk_master_layout *layout; + const struct clk_master_characteristics *characteristics; ++ struct at91_clk_pms pms; + u32 *mux_table; + u32 mckr; + int chg_pid; +@@ -112,10 +113,52 @@ static unsigned long clk_master_div_reca + return rate; + } + ++static int clk_master_div_save_context(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ struct clk_hw *parent_hw = clk_hw_get_parent(hw); ++ unsigned long flags; ++ unsigned int mckr, div; ++ ++ spin_lock_irqsave(master->lock, flags); ++ regmap_read(master->regmap, master->layout->offset, &mckr); ++ spin_unlock_irqrestore(master->lock, flags); ++ ++ mckr &= master->layout->mask; ++ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ div = master->characteristics->divisors[div]; ++ ++ master->pms.parent_rate = clk_hw_get_rate(parent_hw); ++ master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div); ++ ++ return 0; ++} ++ ++static void clk_master_div_restore_context(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ unsigned long flags; ++ unsigned int mckr; ++ u8 div; ++ ++ spin_lock_irqsave(master->lock, flags); ++ regmap_read(master->regmap, master->layout->offset, &mckr); ++ spin_unlock_irqrestore(master->lock, flags); ++ ++ mckr &= master->layout->mask; ++ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ div = master->characteristics->divisors[div]; ++ ++ if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate)) ++ pr_warn("MCKR DIV not configured properly by firmware!\n"); ++} ++ + static const struct clk_ops master_div_ops = { + .prepare = clk_master_prepare, + .is_prepared = clk_master_is_prepared, + .recalc_rate = clk_master_div_recalc_rate, ++ .save_context = clk_master_div_save_context, ++ .restore_context = clk_master_div_restore_context, + }; + + static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, +@@ -125,7 +168,9 @@ static int clk_master_div_set_rate(struc + const struct clk_master_characteristics *characteristics = + master->characteristics; + unsigned long flags; ++ unsigned int mckr, tmp; + int div, i; ++ int ret; + + div = DIV_ROUND_CLOSEST(parent_rate, rate); + if (div > ARRAY_SIZE(characteristics->divisors)) +@@ -145,11 +190,24 @@ static int clk_master_div_set_rate(struc + return -EINVAL; + + spin_lock_irqsave(master->lock, flags); +- regmap_update_bits(master->regmap, master->layout->offset, +- (MASTER_DIV_MASK << MASTER_DIV_SHIFT), +- (div << MASTER_DIV_SHIFT)); ++ ret = regmap_read(master->regmap, master->layout->offset, &mckr); ++ if (ret) ++ goto unlock; ++ ++ tmp = mckr & master->layout->mask; ++ tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ if (tmp == div) ++ goto unlock; ++ ++ mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT); ++ mckr |= (div << MASTER_DIV_SHIFT); ++ ret = regmap_write(master->regmap, master->layout->offset, mckr); ++ if (ret) ++ goto unlock; ++ + while (!clk_master_ready(master)) + cpu_relax(); ++unlock: + spin_unlock_irqrestore(master->lock, flags); + + return 0; +@@ -197,12 +255,25 @@ static int clk_master_div_determine_rate + return 0; + } + ++static void clk_master_div_restore_context_chg(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ int ret; ++ ++ ret = clk_master_div_set_rate(hw, master->pms.rate, ++ master->pms.parent_rate); ++ if (ret) ++ pr_warn("Failed to restore MCK DIV clock\n"); ++} ++ + static const struct clk_ops master_div_ops_chg = { + .prepare = clk_master_prepare, + .is_prepared = clk_master_is_prepared, + .recalc_rate = clk_master_div_recalc_rate, + .determine_rate = clk_master_div_determine_rate, + .set_rate = clk_master_div_set_rate, ++ .save_context = clk_master_div_save_context, ++ .restore_context = clk_master_div_restore_context_chg, + }; + + static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, +@@ -272,7 +343,8 @@ static int clk_master_pres_set_rate(stru + { + struct clk_master *master = to_clk_master(hw); + unsigned long flags; +- unsigned int pres; ++ unsigned int pres, mckr, tmp; ++ int ret; + + pres = DIV_ROUND_CLOSEST(parent_rate, rate); + if (pres > MASTER_PRES_MAX) +@@ -284,15 +356,27 @@ static int clk_master_pres_set_rate(stru + pres = ffs(pres) - 1; + + spin_lock_irqsave(master->lock, flags); +- regmap_update_bits(master->regmap, master->layout->offset, +- (MASTER_PRES_MASK << master->layout->pres_shift), +- (pres << master->layout->pres_shift)); ++ ret = regmap_read(master->regmap, master->layout->offset, &mckr); ++ if (ret) ++ goto unlock; ++ ++ mckr &= master->layout->mask; ++ tmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK; ++ if (pres == tmp) ++ goto unlock; ++ ++ mckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift); ++ mckr |= (pres << master->layout->pres_shift); ++ ret = regmap_write(master->regmap, master->layout->offset, mckr); ++ if (ret) ++ goto unlock; + + while (!clk_master_ready(master)) + cpu_relax(); ++unlock: + spin_unlock_irqrestore(master->lock, flags); + +- return 0; ++ return ret; + } + + static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, +@@ -330,11 +414,68 @@ static u8 clk_master_pres_get_parent(str + return mckr & AT91_PMC_CSS; + } + ++static int clk_master_pres_save_context(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ struct clk_hw *parent_hw = clk_hw_get_parent(hw); ++ unsigned long flags; ++ unsigned int val, pres; ++ ++ spin_lock_irqsave(master->lock, flags); ++ regmap_read(master->regmap, master->layout->offset, &val); ++ spin_unlock_irqrestore(master->lock, flags); ++ ++ val &= master->layout->mask; ++ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; ++ if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres) ++ pres = 3; ++ else ++ pres = (1 << pres); ++ ++ master->pms.parent = val & AT91_PMC_CSS; ++ master->pms.parent_rate = clk_hw_get_rate(parent_hw); ++ master->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres); ++ ++ return 0; ++} ++ ++static void clk_master_pres_restore_context(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ unsigned long flags; ++ unsigned int val, pres; ++ ++ spin_lock_irqsave(master->lock, flags); ++ regmap_read(master->regmap, master->layout->offset, &val); ++ spin_unlock_irqrestore(master->lock, flags); ++ ++ val &= master->layout->mask; ++ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; ++ if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres) ++ pres = 3; ++ else ++ pres = (1 << pres); ++ ++ if (master->pms.rate != ++ DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) || ++ (master->pms.parent != (val & AT91_PMC_CSS))) ++ pr_warn("MCKR PRES was not configured properly by firmware!\n"); ++} ++ ++static void clk_master_pres_restore_context_chg(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ ++ clk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate); ++} ++ + static const struct clk_ops master_pres_ops = { + .prepare = clk_master_prepare, + .is_prepared = clk_master_is_prepared, + .recalc_rate = clk_master_pres_recalc_rate, + .get_parent = clk_master_pres_get_parent, ++ .save_context = clk_master_pres_save_context, ++ .restore_context = clk_master_pres_restore_context, + }; + + static const struct clk_ops master_pres_ops_chg = { +@@ -344,6 +485,8 @@ static const struct clk_ops master_pres_ + .recalc_rate = clk_master_pres_recalc_rate, + .get_parent = clk_master_pres_get_parent, + .set_rate = clk_master_pres_set_rate, ++ .save_context = clk_master_pres_save_context, ++ .restore_context = clk_master_pres_restore_context_chg, + }; + + static struct clk_hw * __init +@@ -539,20 +682,21 @@ static int clk_sama7g5_master_set_parent + return 0; + } + +-static int clk_sama7g5_master_enable(struct clk_hw *hw) ++static void clk_sama7g5_master_set(struct clk_master *master, ++ unsigned int status) + { +- struct clk_master *master = to_clk_master(hw); + unsigned long flags; + unsigned int val, cparent; ++ unsigned int enable = status ? PMC_MCR_EN : 0; + + spin_lock_irqsave(master->lock, flags); + + regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id)); + regmap_read(master->regmap, PMC_MCR, &val); + regmap_update_bits(master->regmap, PMC_MCR, +- PMC_MCR_EN | PMC_MCR_CSS | PMC_MCR_DIV | ++ enable | PMC_MCR_CSS | PMC_MCR_DIV | + PMC_MCR_CMD | PMC_MCR_ID_MSK, +- PMC_MCR_EN | (master->parent << PMC_MCR_CSS_SHIFT) | ++ enable | (master->parent << PMC_MCR_CSS_SHIFT) | + (master->div << MASTER_DIV_SHIFT) | + PMC_MCR_CMD | PMC_MCR_ID(master->id)); + +@@ -563,6 +707,13 @@ static int clk_sama7g5_master_enable(str + cpu_relax(); + + spin_unlock_irqrestore(master->lock, flags); ++} ++ ++static int clk_sama7g5_master_enable(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ ++ clk_sama7g5_master_set(master, 1); + + return 0; + } +@@ -620,6 +771,23 @@ static int clk_sama7g5_master_set_rate(s + return 0; + } + ++static int clk_sama7g5_master_save_context(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ ++ master->pms.status = clk_sama7g5_master_is_enabled(hw); ++ ++ return 0; ++} ++ ++static void clk_sama7g5_master_restore_context(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ ++ if (master->pms.status) ++ clk_sama7g5_master_set(master, master->pms.status); ++} ++ + static const struct clk_ops sama7g5_master_ops = { + .enable = clk_sama7g5_master_enable, + .disable = clk_sama7g5_master_disable, +@@ -629,6 +797,8 @@ static const struct clk_ops sama7g5_mast + .set_rate = clk_sama7g5_master_set_rate, + .get_parent = clk_sama7g5_master_get_parent, + .set_parent = clk_sama7g5_master_set_parent, ++ .save_context = clk_sama7g5_master_save_context, ++ .restore_context = clk_sama7g5_master_restore_context, + }; + + struct clk_hw * __init +--- a/drivers/clk/at91/clk-peripheral.c ++++ b/drivers/clk/at91/clk-peripheral.c +@@ -37,6 +37,7 @@ struct clk_sam9x5_peripheral { + u32 id; + u32 div; + const struct clk_pcr_layout *layout; ++ struct at91_clk_pms pms; + bool auto_div; + int chg_pid; + }; +@@ -155,10 +156,11 @@ static void clk_sam9x5_peripheral_autodi + periph->div = shift; + } + +-static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) ++static int clk_sam9x5_peripheral_set(struct clk_sam9x5_peripheral *periph, ++ unsigned int status) + { +- struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); + unsigned long flags; ++ unsigned int enable = status ? AT91_PMC_PCR_EN : 0; + + if (periph->id < PERIPHERAL_ID_MIN) + return 0; +@@ -168,15 +170,21 @@ static int clk_sam9x5_peripheral_enable( + (periph->id & periph->layout->pid_mask)); + regmap_update_bits(periph->regmap, periph->layout->offset, + periph->layout->div_mask | periph->layout->cmd | +- AT91_PMC_PCR_EN, ++ enable, + field_prep(periph->layout->div_mask, periph->div) | +- periph->layout->cmd | +- AT91_PMC_PCR_EN); ++ periph->layout->cmd | enable); + spin_unlock_irqrestore(periph->lock, flags); + + return 0; + } + ++static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) ++{ ++ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); ++ ++ return clk_sam9x5_peripheral_set(periph, 1); ++} ++ + static void clk_sam9x5_peripheral_disable(struct clk_hw *hw) + { + struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); +@@ -393,6 +401,23 @@ static int clk_sam9x5_peripheral_set_rat + return -EINVAL; + } + ++static int clk_sam9x5_peripheral_save_context(struct clk_hw *hw) ++{ ++ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); ++ ++ periph->pms.status = clk_sam9x5_peripheral_is_enabled(hw); ++ ++ return 0; ++} ++ ++static void clk_sam9x5_peripheral_restore_context(struct clk_hw *hw) ++{ ++ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); ++ ++ if (periph->pms.status) ++ clk_sam9x5_peripheral_set(periph, periph->pms.status); ++} ++ + static const struct clk_ops sam9x5_peripheral_ops = { + .enable = clk_sam9x5_peripheral_enable, + .disable = clk_sam9x5_peripheral_disable, +@@ -400,6 +425,8 @@ static const struct clk_ops sam9x5_perip + .recalc_rate = clk_sam9x5_peripheral_recalc_rate, + .round_rate = clk_sam9x5_peripheral_round_rate, + .set_rate = clk_sam9x5_peripheral_set_rate, ++ .save_context = clk_sam9x5_peripheral_save_context, ++ .restore_context = clk_sam9x5_peripheral_restore_context, + }; + + static const struct clk_ops sam9x5_peripheral_chg_ops = { +@@ -409,6 +436,8 @@ static const struct clk_ops sam9x5_perip + .recalc_rate = clk_sam9x5_peripheral_recalc_rate, + .determine_rate = clk_sam9x5_peripheral_determine_rate, + .set_rate = clk_sam9x5_peripheral_set_rate, ++ .save_context = clk_sam9x5_peripheral_save_context, ++ .restore_context = clk_sam9x5_peripheral_restore_context, + }; + + struct clk_hw * __init +@@ -460,7 +489,6 @@ at91_clk_register_sam9x5_peripheral(stru + hw = ERR_PTR(ret); + } else { + clk_sam9x5_peripheral_autodiv(periph); +- pmc_register_id(id); + } + + return hw; +--- a/drivers/clk/at91/clk-pll.c ++++ b/drivers/clk/at91/clk-pll.c +@@ -40,6 +40,7 @@ struct clk_pll { + u16 mul; + const struct clk_pll_layout *layout; + const struct clk_pll_characteristics *characteristics; ++ struct at91_clk_pms pms; + }; + + static inline bool clk_pll_ready(struct regmap *regmap, int id) +@@ -260,6 +261,42 @@ static int clk_pll_set_rate(struct clk_h + return 0; + } + ++static int clk_pll_save_context(struct clk_hw *hw) ++{ ++ struct clk_pll *pll = to_clk_pll(hw); ++ struct clk_hw *parent_hw = clk_hw_get_parent(hw); ++ ++ pll->pms.parent_rate = clk_hw_get_rate(parent_hw); ++ pll->pms.rate = clk_pll_recalc_rate(&pll->hw, pll->pms.parent_rate); ++ pll->pms.status = clk_pll_ready(pll->regmap, PLL_REG(pll->id)); ++ ++ return 0; ++} ++ ++static void clk_pll_restore_context(struct clk_hw *hw) ++{ ++ struct clk_pll *pll = to_clk_pll(hw); ++ unsigned long calc_rate; ++ unsigned int pllr, pllr_out, pllr_count; ++ u8 out = 0; ++ ++ if (pll->characteristics->out) ++ out = pll->characteristics->out[pll->range]; ++ ++ regmap_read(pll->regmap, PLL_REG(pll->id), &pllr); ++ ++ calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) * ++ (PLL_MUL(pllr, pll->layout) + 1); ++ pllr_count = (pllr >> PLL_COUNT_SHIFT) & PLL_MAX_COUNT; ++ pllr_out = (pllr >> PLL_OUT_SHIFT) & out; ++ ++ if (pll->pms.rate != calc_rate || ++ pll->pms.status != clk_pll_ready(pll->regmap, PLL_REG(pll->id)) || ++ pllr_count != PLL_MAX_COUNT || ++ (out && pllr_out != out)) ++ pr_warn("PLLAR was not configured properly by firmware\n"); ++} ++ + static const struct clk_ops pll_ops = { + .prepare = clk_pll_prepare, + .unprepare = clk_pll_unprepare, +@@ -267,6 +304,8 @@ static const struct clk_ops pll_ops = { + .recalc_rate = clk_pll_recalc_rate, + .round_rate = clk_pll_round_rate, + .set_rate = clk_pll_set_rate, ++ .save_context = clk_pll_save_context, ++ .restore_context = clk_pll_restore_context, + }; + + struct clk_hw * __init +--- a/drivers/clk/at91/clk-programmable.c ++++ b/drivers/clk/at91/clk-programmable.c +@@ -24,6 +24,7 @@ struct clk_programmable { + u32 *mux_table; + u8 id; + const struct clk_programmable_layout *layout; ++ struct at91_clk_pms pms; + }; + + #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw) +@@ -177,12 +178,38 @@ static int clk_programmable_set_rate(str + return 0; + } + ++static int clk_programmable_save_context(struct clk_hw *hw) ++{ ++ struct clk_programmable *prog = to_clk_programmable(hw); ++ struct clk_hw *parent_hw = clk_hw_get_parent(hw); ++ ++ prog->pms.parent = clk_programmable_get_parent(hw); ++ prog->pms.parent_rate = clk_hw_get_rate(parent_hw); ++ prog->pms.rate = clk_programmable_recalc_rate(hw, prog->pms.parent_rate); ++ ++ return 0; ++} ++ ++static void clk_programmable_restore_context(struct clk_hw *hw) ++{ ++ struct clk_programmable *prog = to_clk_programmable(hw); ++ int ret; ++ ++ ret = clk_programmable_set_parent(hw, prog->pms.parent); ++ if (ret) ++ return; ++ ++ clk_programmable_set_rate(hw, prog->pms.rate, prog->pms.parent_rate); ++} ++ + static const struct clk_ops programmable_ops = { + .recalc_rate = clk_programmable_recalc_rate, + .determine_rate = clk_programmable_determine_rate, + .get_parent = clk_programmable_get_parent, + .set_parent = clk_programmable_set_parent, + .set_rate = clk_programmable_set_rate, ++ .save_context = clk_programmable_save_context, ++ .restore_context = clk_programmable_restore_context, + }; + + struct clk_hw * __init +@@ -221,8 +248,6 @@ at91_clk_register_programmable(struct re + if (ret) { + kfree(prog); + hw = ERR_PTR(ret); +- } else { +- pmc_register_pck(id); + } + + return hw; +--- a/drivers/clk/at91/clk-sam9x60-pll.c ++++ b/drivers/clk/at91/clk-sam9x60-pll.c +@@ -38,12 +38,14 @@ struct sam9x60_pll_core { + + struct sam9x60_frac { + struct sam9x60_pll_core core; ++ struct at91_clk_pms pms; + u32 frac; + u16 mul; + }; + + struct sam9x60_div { + struct sam9x60_pll_core core; ++ struct at91_clk_pms pms; + u8 div; + }; + +@@ -75,9 +77,8 @@ static unsigned long sam9x60_frac_pll_re + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); + } + +-static int sam9x60_frac_pll_prepare(struct clk_hw *hw) ++static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) + { +- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); + struct sam9x60_frac *frac = to_sam9x60_frac(core); + struct regmap *regmap = core->regmap; + unsigned int val, cfrac, cmul; +@@ -141,6 +142,13 @@ unlock: + return 0; + } + ++static int sam9x60_frac_pll_prepare(struct clk_hw *hw) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ ++ return sam9x60_frac_pll_set(core); ++} ++ + static void sam9x60_frac_pll_unprepare(struct clk_hw *hw) + { + struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); +@@ -280,6 +288,25 @@ unlock: + return ret; + } + ++static int sam9x60_frac_pll_save_context(struct clk_hw *hw) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ struct sam9x60_frac *frac = to_sam9x60_frac(core); ++ ++ frac->pms.status = sam9x60_pll_ready(core->regmap, core->id); ++ ++ return 0; ++} ++ ++static void sam9x60_frac_pll_restore_context(struct clk_hw *hw) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ struct sam9x60_frac *frac = to_sam9x60_frac(core); ++ ++ if (frac->pms.status) ++ sam9x60_frac_pll_set(core); ++} ++ + static const struct clk_ops sam9x60_frac_pll_ops = { + .prepare = sam9x60_frac_pll_prepare, + .unprepare = sam9x60_frac_pll_unprepare, +@@ -287,6 +314,8 @@ static const struct clk_ops sam9x60_frac + .recalc_rate = sam9x60_frac_pll_recalc_rate, + .round_rate = sam9x60_frac_pll_round_rate, + .set_rate = sam9x60_frac_pll_set_rate, ++ .save_context = sam9x60_frac_pll_save_context, ++ .restore_context = sam9x60_frac_pll_restore_context, + }; + + static const struct clk_ops sam9x60_frac_pll_ops_chg = { +@@ -296,11 +325,12 @@ static const struct clk_ops sam9x60_frac + .recalc_rate = sam9x60_frac_pll_recalc_rate, + .round_rate = sam9x60_frac_pll_round_rate, + .set_rate = sam9x60_frac_pll_set_rate_chg, ++ .save_context = sam9x60_frac_pll_save_context, ++ .restore_context = sam9x60_frac_pll_restore_context, + }; + +-static int sam9x60_div_pll_prepare(struct clk_hw *hw) ++static int sam9x60_div_pll_set(struct sam9x60_pll_core *core) + { +- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); + struct sam9x60_div *div = to_sam9x60_div(core); + struct regmap *regmap = core->regmap; + unsigned long flags; +@@ -334,6 +364,13 @@ unlock: + return 0; + } + ++static int sam9x60_div_pll_prepare(struct clk_hw *hw) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ ++ return sam9x60_div_pll_set(core); ++} ++ + static void sam9x60_div_pll_unprepare(struct clk_hw *hw) + { + struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); +@@ -482,6 +519,25 @@ unlock: + return 0; + } + ++static int sam9x60_div_pll_save_context(struct clk_hw *hw) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ struct sam9x60_div *div = to_sam9x60_div(core); ++ ++ div->pms.status = sam9x60_div_pll_is_prepared(hw); ++ ++ return 0; ++} ++ ++static void sam9x60_div_pll_restore_context(struct clk_hw *hw) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ struct sam9x60_div *div = to_sam9x60_div(core); ++ ++ if (div->pms.status) ++ sam9x60_div_pll_set(core); ++} ++ + static const struct clk_ops sam9x60_div_pll_ops = { + .prepare = sam9x60_div_pll_prepare, + .unprepare = sam9x60_div_pll_unprepare, +@@ -489,6 +545,8 @@ static const struct clk_ops sam9x60_div_ + .recalc_rate = sam9x60_div_pll_recalc_rate, + .round_rate = sam9x60_div_pll_round_rate, + .set_rate = sam9x60_div_pll_set_rate, ++ .save_context = sam9x60_div_pll_save_context, ++ .restore_context = sam9x60_div_pll_restore_context, + }; + + static const struct clk_ops sam9x60_div_pll_ops_chg = { +@@ -498,6 +556,8 @@ static const struct clk_ops sam9x60_div_ + .recalc_rate = sam9x60_div_pll_recalc_rate, + .round_rate = sam9x60_div_pll_round_rate, + .set_rate = sam9x60_div_pll_set_rate_chg, ++ .save_context = sam9x60_div_pll_save_context, ++ .restore_context = sam9x60_div_pll_restore_context, + }; + + struct clk_hw * __init +--- a/drivers/clk/at91/clk-system.c ++++ b/drivers/clk/at91/clk-system.c +@@ -20,6 +20,7 @@ + struct clk_system { + struct clk_hw hw; + struct regmap *regmap; ++ struct at91_clk_pms pms; + u8 id; + }; + +@@ -77,10 +78,29 @@ static int clk_system_is_prepared(struct + return !!(status & (1 << sys->id)); + } + ++static int clk_system_save_context(struct clk_hw *hw) ++{ ++ struct clk_system *sys = to_clk_system(hw); ++ ++ sys->pms.status = clk_system_is_prepared(hw); ++ ++ return 0; ++} ++ ++static void clk_system_restore_context(struct clk_hw *hw) ++{ ++ struct clk_system *sys = to_clk_system(hw); ++ ++ if (sys->pms.status) ++ clk_system_prepare(&sys->hw); ++} ++ + static const struct clk_ops system_ops = { + .prepare = clk_system_prepare, + .unprepare = clk_system_unprepare, + .is_prepared = clk_system_is_prepared, ++ .save_context = clk_system_save_context, ++ .restore_context = clk_system_restore_context, + }; + + struct clk_hw * __init +--- a/drivers/clk/at91/clk-usb.c ++++ b/drivers/clk/at91/clk-usb.c +@@ -24,6 +24,7 @@ + struct at91sam9x5_clk_usb { + struct clk_hw hw; + struct regmap *regmap; ++ struct at91_clk_pms pms; + u32 usbs_mask; + u8 num_parents; + }; +@@ -148,12 +149,38 @@ static int at91sam9x5_clk_usb_set_rate(s + return 0; + } + ++static int at91sam9x5_usb_save_context(struct clk_hw *hw) ++{ ++ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); ++ struct clk_hw *parent_hw = clk_hw_get_parent(hw); ++ ++ usb->pms.parent = at91sam9x5_clk_usb_get_parent(hw); ++ usb->pms.parent_rate = clk_hw_get_rate(parent_hw); ++ usb->pms.rate = at91sam9x5_clk_usb_recalc_rate(hw, usb->pms.parent_rate); ++ ++ return 0; ++} ++ ++static void at91sam9x5_usb_restore_context(struct clk_hw *hw) ++{ ++ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); ++ int ret; ++ ++ ret = at91sam9x5_clk_usb_set_parent(hw, usb->pms.parent); ++ if (ret) ++ return; ++ ++ at91sam9x5_clk_usb_set_rate(hw, usb->pms.rate, usb->pms.parent_rate); ++} ++ + static const struct clk_ops at91sam9x5_usb_ops = { + .recalc_rate = at91sam9x5_clk_usb_recalc_rate, + .determine_rate = at91sam9x5_clk_usb_determine_rate, + .get_parent = at91sam9x5_clk_usb_get_parent, + .set_parent = at91sam9x5_clk_usb_set_parent, + .set_rate = at91sam9x5_clk_usb_set_rate, ++ .save_context = at91sam9x5_usb_save_context, ++ .restore_context = at91sam9x5_usb_restore_context, + }; + + static int at91sam9n12_clk_usb_enable(struct clk_hw *hw) +--- a/drivers/clk/at91/clk-utmi.c ++++ b/drivers/clk/at91/clk-utmi.c +@@ -23,6 +23,7 @@ struct clk_utmi { + struct clk_hw hw; + struct regmap *regmap_pmc; + struct regmap *regmap_sfr; ++ struct at91_clk_pms pms; + }; + + #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw) +@@ -113,11 +114,30 @@ static unsigned long clk_utmi_recalc_rat + return UTMI_RATE; + } + ++static int clk_utmi_save_context(struct clk_hw *hw) ++{ ++ struct clk_utmi *utmi = to_clk_utmi(hw); ++ ++ utmi->pms.status = clk_utmi_is_prepared(hw); ++ ++ return 0; ++} ++ ++static void clk_utmi_restore_context(struct clk_hw *hw) ++{ ++ struct clk_utmi *utmi = to_clk_utmi(hw); ++ ++ if (utmi->pms.status) ++ clk_utmi_prepare(hw); ++} ++ + static const struct clk_ops utmi_ops = { + .prepare = clk_utmi_prepare, + .unprepare = clk_utmi_unprepare, + .is_prepared = clk_utmi_is_prepared, + .recalc_rate = clk_utmi_recalc_rate, ++ .save_context = clk_utmi_save_context, ++ .restore_context = clk_utmi_restore_context, + }; + + static struct clk_hw * __init +@@ -232,10 +252,29 @@ static int clk_utmi_sama7g5_is_prepared( + return 0; + } + ++static int clk_utmi_sama7g5_save_context(struct clk_hw *hw) ++{ ++ struct clk_utmi *utmi = to_clk_utmi(hw); ++ ++ utmi->pms.status = clk_utmi_sama7g5_is_prepared(hw); ++ ++ return 0; ++} ++ ++static void clk_utmi_sama7g5_restore_context(struct clk_hw *hw) ++{ ++ struct clk_utmi *utmi = to_clk_utmi(hw); ++ ++ if (utmi->pms.status) ++ clk_utmi_sama7g5_prepare(hw); ++} ++ + static const struct clk_ops sama7g5_utmi_ops = { + .prepare = clk_utmi_sama7g5_prepare, + .is_prepared = clk_utmi_sama7g5_is_prepared, + .recalc_rate = clk_utmi_recalc_rate, ++ .save_context = clk_utmi_sama7g5_save_context, ++ .restore_context = clk_utmi_sama7g5_restore_context, + }; + + struct clk_hw * __init +--- a/drivers/clk/at91/pmc.c ++++ b/drivers/clk/at91/pmc.c +@@ -3,6 +3,7 @@ + * Copyright (C) 2013 Boris BREZILLON + */ + ++#include + #include + #include + #include +@@ -14,8 +15,6 @@ + + #include + +-#include +- + #include "pmc.h" + + #define PMC_MAX_IDS 128 +@@ -111,147 +110,19 @@ struct pmc_data *pmc_data_allocate(unsig + } + + #ifdef CONFIG_PM +-static struct regmap *pmcreg; +- +-static u8 registered_ids[PMC_MAX_IDS]; +-static u8 registered_pcks[PMC_MAX_PCKS]; +- +-static struct +-{ +- u32 scsr; +- u32 pcsr0; +- u32 uckr; +- u32 mor; +- u32 mcfr; +- u32 pllar; +- u32 mckr; +- u32 usb; +- u32 imr; +- u32 pcsr1; +- u32 pcr[PMC_MAX_IDS]; +- u32 audio_pll0; +- u32 audio_pll1; +- u32 pckr[PMC_MAX_PCKS]; +-} pmc_cache; +- +-/* +- * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored +- * without alteration in the table, and 0 is for unused clocks. +- */ +-void pmc_register_id(u8 id) ++static int at91_pmc_suspend(void) + { +- int i; +- +- for (i = 0; i < PMC_MAX_IDS; i++) { +- if (registered_ids[i] == 0) { +- registered_ids[i] = id; +- break; +- } +- if (registered_ids[i] == id) +- break; +- } ++ return clk_save_context(); + } + +-/* +- * As Programmable Clock 0 is valid on AT91 chips, there is an offset +- * of 1 between the stored value and the real clock ID. +- */ +-void pmc_register_pck(u8 pck) ++static void at91_pmc_resume(void) + { +- int i; +- +- for (i = 0; i < PMC_MAX_PCKS; i++) { +- if (registered_pcks[i] == 0) { +- registered_pcks[i] = pck + 1; +- break; +- } +- if (registered_pcks[i] == (pck + 1)) +- break; +- } +-} +- +-static int pmc_suspend(void) +-{ +- int i; +- u8 num; +- +- regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr); +- regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0); +- regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr); +- regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor); +- regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr); +- regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar); +- regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr); +- regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb); +- regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr); +- regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1); +- +- for (i = 0; registered_ids[i]; i++) { +- regmap_write(pmcreg, AT91_PMC_PCR, +- (registered_ids[i] & AT91_PMC_PCR_PID_MASK)); +- regmap_read(pmcreg, AT91_PMC_PCR, +- &pmc_cache.pcr[registered_ids[i]]); +- } +- for (i = 0; registered_pcks[i]; i++) { +- num = registered_pcks[i] - 1; +- regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]); +- } +- +- return 0; +-} +- +-static bool pmc_ready(unsigned int mask) +-{ +- unsigned int status; +- +- regmap_read(pmcreg, AT91_PMC_SR, &status); +- +- return ((status & mask) == mask) ? 1 : 0; +-} +- +-static void pmc_resume(void) +-{ +- int i; +- u8 num; +- u32 tmp; +- u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA; +- +- regmap_read(pmcreg, AT91_PMC_MCKR, &tmp); +- if (pmc_cache.mckr != tmp) +- pr_warn("MCKR was not configured properly by the firmware\n"); +- regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp); +- if (pmc_cache.pllar != tmp) +- pr_warn("PLLAR was not configured properly by the firmware\n"); +- +- regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr); +- regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0); +- regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr); +- regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor); +- regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr); +- regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb); +- regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr); +- regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1); +- +- for (i = 0; registered_ids[i]; i++) { +- regmap_write(pmcreg, AT91_PMC_PCR, +- pmc_cache.pcr[registered_ids[i]] | +- AT91_PMC_PCR_CMD); +- } +- for (i = 0; registered_pcks[i]; i++) { +- num = registered_pcks[i] - 1; +- regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]); +- } +- +- if (pmc_cache.uckr & AT91_PMC_UPLLEN) +- mask |= AT91_PMC_LOCKU; +- +- while (!pmc_ready(mask)) +- cpu_relax(); ++ clk_restore_context(); + } + + static struct syscore_ops pmc_syscore_ops = { +- .suspend = pmc_suspend, +- .resume = pmc_resume, ++ .suspend = at91_pmc_suspend, ++ .resume = at91_pmc_resume, + }; + + static const struct of_device_id sama5d2_pmc_dt_ids[] = { +@@ -271,11 +142,7 @@ static int __init pmc_register_ops(void) + of_node_put(np); + return -ENODEV; + } +- +- pmcreg = device_node_to_regmap(np); + of_node_put(np); +- if (IS_ERR(pmcreg)) +- return PTR_ERR(pmcreg); + + register_syscore_ops(&pmc_syscore_ops); + +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -13,6 +13,8 @@ + #include + #include + ++#include ++ + extern spinlock_t pmc_pcr_lock; + + struct pmc_data { +@@ -98,6 +100,20 @@ struct clk_pcr_layout { + u32 pid_mask; + }; + ++/** ++ * struct at91_clk_pms - Power management state for AT91 clock ++ * @rate: clock rate ++ * @parent_rate: clock parent rate ++ * @status: clock status (enabled or disabled) ++ * @parent: clock parent index ++ */ ++struct at91_clk_pms { ++ unsigned long rate; ++ unsigned long parent_rate; ++ unsigned int status; ++ unsigned int parent; ++}; ++ + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +@@ -248,12 +264,4 @@ struct clk_hw * __init + at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name, + const char *parent_name); + +-#ifdef CONFIG_PM +-void pmc_register_id(u8 id); +-void pmc_register_pck(u8 pck); +-#else +-static inline void pmc_register_id(u8 id) {} +-static inline void pmc_register_pck(u8 pck) {} +-#endif +- + #endif /* __PMC_H_ */ diff --git a/target/linux/at91/patches-5.15/101-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch b/target/linux/at91/patches-5.15/101-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch new file mode 100644 index 0000000000..19f1f6fdf2 --- /dev/null +++ b/target/linux/at91/patches-5.15/101-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch @@ -0,0 +1,89 @@ +From 63a0c32028148e91ea91cfbf95841c4ecd69d21b Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:06 +0300 +Subject: [PATCH 235/247] clk: at91: pmc: execute suspend/resume only for + backup mode + +Before going to backup mode architecture specific PM code sets the first +word in securam (file arch/arm/mach-at91/pm.c, function at91_pm_begin()). +Thus take this into account when suspending/resuming clocks. This will +avoid executing unnecessary instructions when suspending to non backup +modes. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-3-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/pmc.c | 39 +++++++++++++++++++++++++++++++++++++++ + 1 file changed, 39 insertions(+) + +--- a/drivers/clk/at91/pmc.c ++++ b/drivers/clk/at91/pmc.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -110,13 +111,35 @@ struct pmc_data *pmc_data_allocate(unsig + } + + #ifdef CONFIG_PM ++ ++/* Address in SECURAM that say if we suspend to backup mode. */ ++static void __iomem *at91_pmc_backup_suspend; ++ + static int at91_pmc_suspend(void) + { ++ unsigned int backup; ++ ++ if (!at91_pmc_backup_suspend) ++ return 0; ++ ++ backup = readl_relaxed(at91_pmc_backup_suspend); ++ if (!backup) ++ return 0; ++ + return clk_save_context(); + } + + static void at91_pmc_resume(void) + { ++ unsigned int backup; ++ ++ if (!at91_pmc_backup_suspend) ++ return; ++ ++ backup = readl_relaxed(at91_pmc_backup_suspend); ++ if (!backup) ++ return; ++ + clk_restore_context(); + } + +@@ -144,6 +167,22 @@ static int __init pmc_register_ops(void) + } + of_node_put(np); + ++ np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); ++ if (!np) ++ return -ENODEV; ++ ++ if (!of_device_is_available(np)) { ++ of_node_put(np); ++ return -ENODEV; ++ } ++ of_node_put(np); ++ ++ at91_pmc_backup_suspend = of_iomap(np, 0); ++ if (!at91_pmc_backup_suspend) { ++ pr_warn("%s(): unable to map securam\n", __func__); ++ return -ENOMEM; ++ } ++ + register_syscore_ops(&pmc_syscore_ops); + + return 0; diff --git a/target/linux/at91/patches-5.15/102-clk-at91-clk-master-add-register-definition-for-sama.patch b/target/linux/at91/patches-5.15/102-clk-at91-clk-master-add-register-definition-for-sama.patch new file mode 100644 index 0000000000..726d9b33e4 --- /dev/null +++ b/target/linux/at91/patches-5.15/102-clk-at91-clk-master-add-register-definition-for-sama.patch @@ -0,0 +1,124 @@ +From c716562753d1e51a1c53647aa77a332f97187d15 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:08 +0300 +Subject: [PATCH 237/247] clk: at91: clk-master: add register definition for + sama7g5's master clock + +SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the +register at offset 0x30 (relative to PMC). In the last/first phase of +suspend/resume procedure (which is architecture specific) the parent +of master clocks are changed (via assembly code) for more power saving +(see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable +and at91_mckx_ps_restore). Thus the macros corresponding to register +at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S. +commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's +master clock") introduced the proper macros but didn't adapted the +clk-master.c as well. Thus, this commit adapt the clk-master.c to use +the macros introduced in commit ec03f18cc222 ("clk: at91: add register +definition for sama7g5's master clock"). + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-master.c | 50 ++++++++++++++++------------------- + 1 file changed, 23 insertions(+), 27 deletions(-) + +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -17,15 +17,7 @@ + #define MASTER_DIV_SHIFT 8 + #define MASTER_DIV_MASK 0x7 + +-#define PMC_MCR 0x30 +-#define PMC_MCR_ID_MSK GENMASK(3, 0) +-#define PMC_MCR_CMD BIT(7) +-#define PMC_MCR_DIV GENMASK(10, 8) +-#define PMC_MCR_CSS GENMASK(20, 16) + #define PMC_MCR_CSS_SHIFT (16) +-#define PMC_MCR_EN BIT(28) +- +-#define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK) + + #define MASTER_MAX_ID 4 + +@@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struc + { + unsigned long flags; + unsigned int val, cparent; +- unsigned int enable = status ? PMC_MCR_EN : 0; ++ unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0; + + spin_lock_irqsave(master->lock, flags); + +- regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id)); +- regmap_read(master->regmap, PMC_MCR, &val); +- regmap_update_bits(master->regmap, PMC_MCR, +- enable | PMC_MCR_CSS | PMC_MCR_DIV | +- PMC_MCR_CMD | PMC_MCR_ID_MSK, ++ regmap_write(master->regmap, AT91_PMC_MCR_V2, ++ AT91_PMC_MCR_V2_ID(master->id)); ++ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); ++ regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, ++ enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV | ++ AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK, + enable | (master->parent << PMC_MCR_CSS_SHIFT) | + (master->div << MASTER_DIV_SHIFT) | +- PMC_MCR_CMD | PMC_MCR_ID(master->id)); ++ AT91_PMC_MCR_V2_CMD | ++ AT91_PMC_MCR_V2_ID(master->id)); + +- cparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT; ++ cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; + + /* Wait here only if parent is being changed. */ + while ((cparent != master->parent) && !clk_master_ready(master)) +@@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(s + + spin_lock_irqsave(master->lock, flags); + +- regmap_write(master->regmap, PMC_MCR, master->id); +- regmap_update_bits(master->regmap, PMC_MCR, +- PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK, +- PMC_MCR_CMD | PMC_MCR_ID(master->id)); ++ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); ++ regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, ++ AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD | ++ AT91_PMC_MCR_V2_ID_MSK, ++ AT91_PMC_MCR_V2_CMD | ++ AT91_PMC_MCR_V2_ID(master->id)); + + spin_unlock_irqrestore(master->lock, flags); + } +@@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled + + spin_lock_irqsave(master->lock, flags); + +- regmap_write(master->regmap, PMC_MCR, master->id); +- regmap_read(master->regmap, PMC_MCR, &val); ++ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); ++ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); + + spin_unlock_irqrestore(master->lock, flags); + +- return !!(val & PMC_MCR_EN); ++ return !!(val & AT91_PMC_MCR_V2_EN); + } + + static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate, +@@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct + master->mux_table = mux_table; + + spin_lock_irqsave(master->lock, flags); +- regmap_write(master->regmap, PMC_MCR, master->id); +- regmap_read(master->regmap, PMC_MCR, &val); +- master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT; +- master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT; ++ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); ++ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); ++ master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; ++ master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT; + spin_unlock_irqrestore(master->lock, flags); + + hw = &master->hw; diff --git a/target/linux/at91/patches-5.15/103-clk-at91-clk-master-improve-readability-by-using-loc.patch b/target/linux/at91/patches-5.15/103-clk-at91-clk-master-improve-readability-by-using-loc.patch new file mode 100644 index 0000000000..a5b57a67ad --- /dev/null +++ b/target/linux/at91/patches-5.15/103-clk-at91-clk-master-improve-readability-by-using-loc.patch @@ -0,0 +1,40 @@ +From 17b53ad1574cb5f41789993289d3d94f7a50f0ce Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:09 +0300 +Subject: [PATCH 238/247] clk: at91: clk-master: improve readability by using + local variables + +Improve readability in clk_sama7g5_master_set() by using local +variables. + +Suggested-by: Nicolas Ferre +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-6-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-master.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -680,6 +680,8 @@ static void clk_sama7g5_master_set(struc + unsigned long flags; + unsigned int val, cparent; + unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0; ++ unsigned int parent = master->parent << PMC_MCR_CSS_SHIFT; ++ unsigned int div = master->div << MASTER_DIV_SHIFT; + + spin_lock_irqsave(master->lock, flags); + +@@ -689,9 +691,7 @@ static void clk_sama7g5_master_set(struc + regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, + enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV | + AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK, +- enable | (master->parent << PMC_MCR_CSS_SHIFT) | +- (master->div << MASTER_DIV_SHIFT) | +- AT91_PMC_MCR_V2_CMD | ++ enable | parent | div | AT91_PMC_MCR_V2_CMD | + AT91_PMC_MCR_V2_ID(master->id)); + + cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; diff --git a/target/linux/at91/patches-5.15/104-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch b/target/linux/at91/patches-5.15/104-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch new file mode 100644 index 0000000000..2918de1700 --- /dev/null +++ b/target/linux/at91/patches-5.15/104-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch @@ -0,0 +1,39 @@ +From 8a38e0dda46c9d941a61d8b2e6c14704531b7871 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:10 +0300 +Subject: [PATCH 239/247] clk: at91: pmc: add sama7g5 to the list of available + pmcs + +Add SAMA7G5 to the list of available PMCs such that the suspend/resume +code for clocks to be used on backup mode. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-7-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/pmc.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/clk/at91/pmc.c ++++ b/drivers/clk/at91/pmc.c +@@ -148,8 +148,9 @@ static struct syscore_ops pmc_syscore_op + .resume = at91_pmc_resume, + }; + +-static const struct of_device_id sama5d2_pmc_dt_ids[] = { ++static const struct of_device_id pmc_dt_ids[] = { + { .compatible = "atmel,sama5d2-pmc" }, ++ { .compatible = "microchip,sama7g5-pmc", }, + { /* sentinel */ } + }; + +@@ -157,7 +158,7 @@ static int __init pmc_register_ops(void) + { + struct device_node *np; + +- np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids); ++ np = of_find_matching_node(NULL, pmc_dt_ids); + if (!np) + return -ENODEV; + diff --git a/target/linux/at91/patches-5.15/105-clk-at91-clk-master-mask-mckr-against-layout-mask.patch b/target/linux/at91/patches-5.15/105-clk-at91-clk-master-mask-mckr-against-layout-mask.patch new file mode 100644 index 0000000000..ea869c9485 --- /dev/null +++ b/target/linux/at91/patches-5.15/105-clk-at91-clk-master-mask-mckr-against-layout-mask.patch @@ -0,0 +1,46 @@ +From 27c11c09346b7b9f67eeb39db1b943f4a9742ff3 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:13 +0300 +Subject: [PATCH 241/247] clk: at91: clk-master: mask mckr against layout->mask + +Mask values read/written from/to MCKR against layout->mask as this +mask may be different b/w PMC versions. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-10-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-master.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -186,8 +186,8 @@ static int clk_master_div_set_rate(struc + if (ret) + goto unlock; + +- tmp = mckr & master->layout->mask; +- tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ mckr &= master->layout->mask; ++ tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + if (tmp == div) + goto unlock; + +@@ -384,6 +384,7 @@ static unsigned long clk_master_pres_rec + regmap_read(master->regmap, master->layout->offset, &val); + spin_unlock_irqrestore(master->lock, flags); + ++ val &= master->layout->mask; + pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; + if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres) + pres = 3; +@@ -403,6 +404,8 @@ static u8 clk_master_pres_get_parent(str + regmap_read(master->regmap, master->layout->offset, &mckr); + spin_unlock_irqrestore(master->lock, flags); + ++ mckr &= master->layout->mask; ++ + return mckr & AT91_PMC_CSS; + } + diff --git a/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch b/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch new file mode 100644 index 0000000000..e5ebdc4ea4 --- /dev/null +++ b/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch @@ -0,0 +1,312 @@ +From e76d2af5009f52aa02d3db7ae32d150ad66398f9 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:15 +0300 +Subject: [PATCH 243/247] clk: at91: clk-sam9x60-pll: add notifier for div part + of PLL + +SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts: +one fractional part and one divider. On SAMA7G5 the CPU PLL could be +changed at run-time to implement DVFS. The hardware clock tree on +SAMA7G5 for CPU PLL is as follows: + + +---- div1 ----------------> cpuck + | +FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0 + +The div1 block is not implemented in Linux; on prescaler block it has +been discovered a bug on some scenarios and will be removed from Linux +in next commits. Thus, the final clock tree that will be used in Linux +will be as follows: + + +-----------> cpuck + | +FRAC PLL ---> DIV PLL -+-> div0 ---> mck0 + +It has been proposed in [1] to not introduce a new CPUFreq driver but +to overload the proper clock drivers with proper operation such that +cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement +clock notifiers which applies safe dividers before FRAC PLL is changed. +The current commit treats only the DIV PLL by adding a notifier that +sets a safe divider on PRE_RATE_CHANGE events. The safe divider is +provided by initialization clock code (sama7g5.c). The div0 is treated +in next commits (to keep the changes as clean as possible). + +[1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/ + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-12-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-sam9x60-pll.c | 102 ++++++++++++++++++++++------- + drivers/clk/at91/pmc.h | 3 +- + drivers/clk/at91/sam9x60.c | 6 +- + drivers/clk/at91/sama7g5.c | 13 +++- + 4 files changed, 95 insertions(+), 29 deletions(-) + +--- a/drivers/clk/at91/clk-sam9x60-pll.c ++++ b/drivers/clk/at91/clk-sam9x60-pll.c +@@ -5,6 +5,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -47,12 +48,15 @@ struct sam9x60_div { + struct sam9x60_pll_core core; + struct at91_clk_pms pms; + u8 div; ++ u8 safe_div; + }; + + #define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw) + #define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core) + #define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core) + ++static struct sam9x60_div *notifier_div; ++ + static inline bool sam9x60_pll_ready(struct regmap *regmap, int id) + { + unsigned int status; +@@ -329,6 +333,26 @@ static const struct clk_ops sam9x60_frac + .restore_context = sam9x60_frac_pll_restore_context, + }; + ++/* This function should be called with spinlock acquired. */ ++static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div, ++ bool enable) ++{ ++ struct regmap *regmap = core->regmap; ++ u32 ena_msk = enable ? core->layout->endiv_mask : 0; ++ u32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0; ++ ++ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, ++ core->layout->div_mask | ena_msk, ++ (div << core->layout->div_shift) | ena_val); ++ ++ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, ++ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, ++ AT91_PMC_PLL_UPDT_UPDATE | core->id); ++ ++ while (!sam9x60_pll_ready(regmap, core->id)) ++ cpu_relax(); ++} ++ + static int sam9x60_div_pll_set(struct sam9x60_pll_core *core) + { + struct sam9x60_div *div = to_sam9x60_div(core); +@@ -346,17 +370,7 @@ static int sam9x60_div_pll_set(struct sa + if (!!(val & core->layout->endiv_mask) && cdiv == div->div) + goto unlock; + +- regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, +- core->layout->div_mask | core->layout->endiv_mask, +- (div->div << core->layout->div_shift) | +- (1 << core->layout->endiv_shift)); +- +- regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, +- AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, +- AT91_PMC_PLL_UPDT_UPDATE | core->id); +- +- while (!sam9x60_pll_ready(regmap, core->id)) +- cpu_relax(); ++ sam9x60_div_pll_set_div(core, div->div, 1); + + unlock: + spin_unlock_irqrestore(core->lock, flags); +@@ -502,16 +516,7 @@ static int sam9x60_div_pll_set_rate_chg( + if (cdiv == div->div) + goto unlock; + +- regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, +- core->layout->div_mask, +- (div->div << core->layout->div_shift)); +- +- regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, +- AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, +- AT91_PMC_PLL_UPDT_UPDATE | core->id); +- +- while (!sam9x60_pll_ready(regmap, core->id)) +- cpu_relax(); ++ sam9x60_div_pll_set_div(core, div->div, 0); + + unlock: + spin_unlock_irqrestore(core->lock, irqflags); +@@ -538,6 +543,48 @@ static void sam9x60_div_pll_restore_cont + sam9x60_div_pll_set(core); + } + ++static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier, ++ unsigned long code, void *data) ++{ ++ struct sam9x60_div *div = notifier_div; ++ struct sam9x60_pll_core core = div->core; ++ struct regmap *regmap = core.regmap; ++ unsigned long irqflags; ++ u32 val, cdiv; ++ int ret = NOTIFY_DONE; ++ ++ if (code != PRE_RATE_CHANGE) ++ return ret; ++ ++ /* ++ * We switch to safe divider to avoid overclocking of other domains ++ * feed by us while the frac PLL (our parent) is changed. ++ */ ++ div->div = div->safe_div; ++ ++ spin_lock_irqsave(core.lock, irqflags); ++ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, ++ core.id); ++ regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); ++ cdiv = (val & core.layout->div_mask) >> core.layout->div_shift; ++ ++ /* Stop if nothing changed. */ ++ if (cdiv == div->safe_div) ++ goto unlock; ++ ++ sam9x60_div_pll_set_div(&core, div->div, 0); ++ ret = NOTIFY_OK; ++ ++unlock: ++ spin_unlock_irqrestore(core.lock, irqflags); ++ ++ return ret; ++} ++ ++static struct notifier_block sam9x60_div_pll_notifier = { ++ .notifier_call = sam9x60_div_pll_notifier_fn, ++}; ++ + static const struct clk_ops sam9x60_div_pll_ops = { + .prepare = sam9x60_div_pll_prepare, + .unprepare = sam9x60_div_pll_unprepare, +@@ -647,7 +694,8 @@ struct clk_hw * __init + sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, + const char *name, const char *parent_name, u8 id, + const struct clk_pll_characteristics *characteristics, +- const struct clk_pll_layout *layout, u32 flags) ++ const struct clk_pll_layout *layout, u32 flags, ++ u32 safe_div) + { + struct sam9x60_div *div; + struct clk_hw *hw; +@@ -656,9 +704,13 @@ sam9x60_clk_register_div_pll(struct regm + unsigned int val; + int ret; + +- if (id > PLL_MAX_ID || !lock) ++ /* We only support one changeable PLL. */ ++ if (id > PLL_MAX_ID || !lock || (safe_div && notifier_div)) + return ERR_PTR(-EINVAL); + ++ if (safe_div >= PLL_DIV_MAX) ++ safe_div = PLL_DIV_MAX - 1; ++ + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); +@@ -678,6 +730,7 @@ sam9x60_clk_register_div_pll(struct regm + div->core.layout = layout; + div->core.regmap = regmap; + div->core.lock = lock; ++ div->safe_div = safe_div; + + spin_lock_irqsave(div->core.lock, irqflags); + +@@ -693,6 +746,9 @@ sam9x60_clk_register_div_pll(struct regm + if (ret) { + kfree(div); + hw = ERR_PTR(ret); ++ } else if (div->safe_div) { ++ notifier_div = div; ++ clk_notifier_register(hw->clk, &sam9x60_div_pll_notifier); + } + + return hw; +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -214,7 +214,8 @@ struct clk_hw * __init + sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, + const char *name, const char *parent_name, u8 id, + const struct clk_pll_characteristics *characteristics, +- const struct clk_pll_layout *layout, u32 flags); ++ const struct clk_pll_layout *layout, u32 flags, ++ u32 safe_div); + + struct clk_hw * __init + sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, +--- a/drivers/clk/at91/sam9x60.c ++++ b/drivers/clk/at91/sam9x60.c +@@ -242,7 +242,7 @@ static void __init sam9x60_pmc_setup(str + * This feeds CPU. It should not + * be disabled. + */ +- CLK_IS_CRITICAL | CLK_SET_RATE_GATE); ++ CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +@@ -260,7 +260,7 @@ static void __init sam9x60_pmc_setup(str + &pll_div_layout, + CLK_SET_RATE_GATE | + CLK_SET_PARENT_GATE | +- CLK_SET_RATE_PARENT); ++ CLK_SET_RATE_PARENT, 0); + if (IS_ERR(hw)) + goto err_free; + +@@ -279,7 +279,7 @@ static void __init sam9x60_pmc_setup(str + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", &sam9x60_master_layout, + &mck_characteristics, &mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -127,6 +127,8 @@ static const struct clk_pll_characterist + * @t: clock type + * @f: clock flags + * @eid: export index in sama7g5->chws[] array ++ * @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE ++ * notification + */ + static const struct { + const char *n; +@@ -136,6 +138,7 @@ static const struct { + unsigned long f; + u8 t; + u8 eid; ++ u8 safe_div; + } sama7g5_plls[][PLL_ID_MAX] = { + [PLL_ID_CPU] = { + { .n = "cpupll_fracck", +@@ -156,7 +159,12 @@ static const struct { + .t = PLL_TYPE_DIV, + /* This feeds CPU. It should not be disabled. */ + .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, +- .eid = PMC_CPUPLL, }, ++ .eid = PMC_CPUPLL, ++ /* ++ * Safe div=15 should be safe even for switching b/w 1GHz and ++ * 90MHz (frac pll might go up to 1.2GHz). ++ */ ++ .safe_div = 15, }, + }, + + [PLL_ID_SYS] = { +@@ -966,7 +974,8 @@ static void __init sama7g5_pmc_setup(str + sama7g5_plls[i][j].p, i, + sama7g5_plls[i][j].c, + sama7g5_plls[i][j].l, +- sama7g5_plls[i][j].f); ++ sama7g5_plls[i][j].f, ++ sama7g5_plls[i][j].safe_div); + break; + + default: diff --git a/target/linux/at91/patches-5.15/107-clk-at91-clk-master-add-notifier-for-divider.patch b/target/linux/at91/patches-5.15/107-clk-at91-clk-master-add-notifier-for-divider.patch new file mode 100644 index 0000000000..83839e6a74 --- /dev/null +++ b/target/linux/at91/patches-5.15/107-clk-at91-clk-master-add-notifier-for-divider.patch @@ -0,0 +1,519 @@ +From 75d5d1d584ae73ba0c36d1d7255db6153ca4d3f3 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:16 +0300 +Subject: [PATCH 244/247] clk: at91: clk-master: add notifier for divider + +SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same +parent with cpuck as seen in the following clock tree: + + +----------> cpuck + | +FRAC PLL ---> DIV PLL -+-> DIV ---> mck0 + +mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking +while changing FRAC PLL or DIV PLL the commit implements a notifier for +mck0 which applies a safe divider to register (maximum value of the divider +which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not +overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE +events. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/at91rm9200.c | 2 +- + drivers/clk/at91/at91sam9260.c | 2 +- + drivers/clk/at91/at91sam9g45.c | 2 +- + drivers/clk/at91/at91sam9n12.c | 2 +- + drivers/clk/at91/at91sam9rl.c | 2 +- + drivers/clk/at91/at91sam9x5.c | 2 +- + drivers/clk/at91/clk-master.c | 244 +++++++++++++++++++++++---------- + drivers/clk/at91/dt-compat.c | 2 +- + drivers/clk/at91/pmc.h | 2 +- + drivers/clk/at91/sama5d2.c | 2 +- + drivers/clk/at91/sama5d3.c | 2 +- + drivers/clk/at91/sama5d4.c | 2 +- + drivers/clk/at91/sama7g5.c | 2 +- + 13 files changed, 186 insertions(+), 82 deletions(-) + +--- a/drivers/clk/at91/at91rm9200.c ++++ b/drivers/clk/at91/at91rm9200.c +@@ -152,7 +152,7 @@ static void __init at91rm9200_pmc_setup( + "masterck_pres", + &at91rm9200_master_layout, + &rm9200_mck_characteristics, +- &rm9200_mck_lock, CLK_SET_RATE_GATE); ++ &rm9200_mck_lock, CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/at91sam9260.c ++++ b/drivers/clk/at91/at91sam9260.c +@@ -429,7 +429,7 @@ static void __init at91sam926x_pmc_setup + &at91rm9200_master_layout, + data->mck_characteristics, + &at91sam9260_mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/at91sam9g45.c ++++ b/drivers/clk/at91/at91sam9g45.c +@@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup + &at91rm9200_master_layout, + &mck_characteristics, + &at91sam9g45_mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/at91sam9n12.c ++++ b/drivers/clk/at91/at91sam9n12.c +@@ -191,7 +191,7 @@ static void __init at91sam9n12_pmc_setup + &at91sam9x5_master_layout, + &mck_characteristics, + &at91sam9n12_mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/at91sam9rl.c ++++ b/drivers/clk/at91/at91sam9rl.c +@@ -132,7 +132,7 @@ static void __init at91sam9rl_pmc_setup( + "masterck_pres", + &at91rm9200_master_layout, + &sam9rl_mck_characteristics, +- &sam9rl_mck_lock, CLK_SET_RATE_GATE); ++ &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/at91sam9x5.c ++++ b/drivers/clk/at91/at91sam9x5.c +@@ -210,7 +210,7 @@ static void __init at91sam9x5_pmc_setup( + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -5,6 +5,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -36,8 +37,12 @@ struct clk_master { + u8 id; + u8 parent; + u8 div; ++ u32 safe_div; + }; + ++/* MCK div reference to be used by notifier. */ ++static struct clk_master *master_div; ++ + static inline bool clk_master_ready(struct clk_master *master) + { + unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY; +@@ -153,107 +158,81 @@ static const struct clk_ops master_div_o + .restore_context = clk_master_div_restore_context, + }; + +-static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, +- unsigned long parent_rate) ++/* This function must be called with lock acquired. */ ++static int clk_master_div_set(struct clk_master *master, ++ unsigned long parent_rate, int div) + { +- struct clk_master *master = to_clk_master(hw); + const struct clk_master_characteristics *characteristics = + master->characteristics; +- unsigned long flags; +- unsigned int mckr, tmp; +- int div, i; ++ unsigned long rate = parent_rate; ++ unsigned int max_div = 0, div_index = 0, max_div_index = 0; ++ unsigned int i, mckr, tmp; + int ret; + +- div = DIV_ROUND_CLOSEST(parent_rate, rate); +- if (div > ARRAY_SIZE(characteristics->divisors)) +- return -EINVAL; +- + for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { + if (!characteristics->divisors[i]) + break; + +- if (div == characteristics->divisors[i]) { +- div = i; +- break; ++ if (div == characteristics->divisors[i]) ++ div_index = i; ++ ++ if (max_div < characteristics->divisors[i]) { ++ max_div = characteristics->divisors[i]; ++ max_div_index = i; + } + } + +- if (i == ARRAY_SIZE(characteristics->divisors)) +- return -EINVAL; ++ if (div > max_div) ++ div_index = max_div_index; + +- spin_lock_irqsave(master->lock, flags); + ret = regmap_read(master->regmap, master->layout->offset, &mckr); + if (ret) +- goto unlock; ++ return ret; + + mckr &= master->layout->mask; + tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; +- if (tmp == div) +- goto unlock; ++ if (tmp == div_index) ++ return 0; ++ ++ rate /= characteristics->divisors[div_index]; ++ if (rate < characteristics->output.min) ++ pr_warn("master clk div is underclocked"); ++ else if (rate > characteristics->output.max) ++ pr_warn("master clk div is overclocked"); + + mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT); +- mckr |= (div << MASTER_DIV_SHIFT); ++ mckr |= (div_index << MASTER_DIV_SHIFT); + ret = regmap_write(master->regmap, master->layout->offset, mckr); + if (ret) +- goto unlock; ++ return ret; + + while (!clk_master_ready(master)) + cpu_relax(); +-unlock: +- spin_unlock_irqrestore(master->lock, flags); ++ ++ master->div = characteristics->divisors[div_index]; + + return 0; + } + +-static int clk_master_div_determine_rate(struct clk_hw *hw, +- struct clk_rate_request *req) ++static unsigned long clk_master_div_recalc_rate_chg(struct clk_hw *hw, ++ unsigned long parent_rate) + { + struct clk_master *master = to_clk_master(hw); +- const struct clk_master_characteristics *characteristics = +- master->characteristics; +- struct clk_hw *parent; +- unsigned long parent_rate, tmp_rate, best_rate = 0; +- int i, best_diff = INT_MIN, tmp_diff; +- +- parent = clk_hw_get_parent(hw); +- if (!parent) +- return -EINVAL; +- +- parent_rate = clk_hw_get_rate(parent); +- if (!parent_rate) +- return -EINVAL; + +- for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { +- if (!characteristics->divisors[i]) +- break; +- +- tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate, +- characteristics->divisors[i]); +- tmp_diff = abs(tmp_rate - req->rate); +- +- if (!best_rate || best_diff > tmp_diff) { +- best_diff = tmp_diff; +- best_rate = tmp_rate; +- } +- +- if (!best_diff) +- break; +- } +- +- req->best_parent_rate = best_rate; +- req->best_parent_hw = parent; +- req->rate = best_rate; +- +- return 0; ++ return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div); + } + + static void clk_master_div_restore_context_chg(struct clk_hw *hw) + { + struct clk_master *master = to_clk_master(hw); ++ unsigned long flags; + int ret; + +- ret = clk_master_div_set_rate(hw, master->pms.rate, +- master->pms.parent_rate); ++ spin_lock_irqsave(master->lock, flags); ++ ret = clk_master_div_set(master, master->pms.parent_rate, ++ DIV_ROUND_CLOSEST(master->pms.parent_rate, ++ master->pms.rate)); ++ spin_unlock_irqrestore(master->lock, flags); + if (ret) + pr_warn("Failed to restore MCK DIV clock\n"); + } +@@ -261,13 +240,116 @@ static void clk_master_div_restore_conte + static const struct clk_ops master_div_ops_chg = { + .prepare = clk_master_prepare, + .is_prepared = clk_master_is_prepared, +- .recalc_rate = clk_master_div_recalc_rate, +- .determine_rate = clk_master_div_determine_rate, +- .set_rate = clk_master_div_set_rate, ++ .recalc_rate = clk_master_div_recalc_rate_chg, + .save_context = clk_master_div_save_context, + .restore_context = clk_master_div_restore_context_chg, + }; + ++static int clk_master_div_notifier_fn(struct notifier_block *notifier, ++ unsigned long code, void *data) ++{ ++ const struct clk_master_characteristics *characteristics = ++ master_div->characteristics; ++ struct clk_notifier_data *cnd = data; ++ unsigned long flags, new_parent_rate, new_rate; ++ unsigned int mckr, div, new_div = 0; ++ int ret, i; ++ long tmp_diff; ++ long best_diff = -1; ++ ++ spin_lock_irqsave(master_div->lock, flags); ++ switch (code) { ++ case PRE_RATE_CHANGE: ++ /* ++ * We want to avoid any overclocking of MCK DIV domain. To do ++ * this we set a safe divider (the underclocking is not of ++ * interest as we can go as low as 32KHz). The relation ++ * b/w this clock and its parents are as follows: ++ * ++ * FRAC PLL -> DIV PLL -> MCK DIV ++ * ++ * With the proper safe divider we should be good even with FRAC ++ * PLL at its maximum value. ++ */ ++ ret = regmap_read(master_div->regmap, master_div->layout->offset, ++ &mckr); ++ if (ret) { ++ ret = NOTIFY_STOP_MASK; ++ goto unlock; ++ } ++ ++ mckr &= master_div->layout->mask; ++ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ ++ /* Switch to safe divider. */ ++ clk_master_div_set(master_div, ++ cnd->old_rate * characteristics->divisors[div], ++ master_div->safe_div); ++ break; ++ ++ case POST_RATE_CHANGE: ++ /* ++ * At this point we want to restore MCK DIV domain to its maximum ++ * allowed rate. ++ */ ++ ret = regmap_read(master_div->regmap, master_div->layout->offset, ++ &mckr); ++ if (ret) { ++ ret = NOTIFY_STOP_MASK; ++ goto unlock; ++ } ++ ++ mckr &= master_div->layout->mask; ++ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ new_parent_rate = cnd->new_rate * characteristics->divisors[div]; ++ ++ for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { ++ if (!characteristics->divisors[i]) ++ break; ++ ++ new_rate = DIV_ROUND_CLOSEST_ULL(new_parent_rate, ++ characteristics->divisors[i]); ++ ++ tmp_diff = characteristics->output.max - new_rate; ++ if (tmp_diff < 0) ++ continue; ++ ++ if (best_diff < 0 || best_diff > tmp_diff) { ++ new_div = characteristics->divisors[i]; ++ best_diff = tmp_diff; ++ } ++ ++ if (!tmp_diff) ++ break; ++ } ++ ++ if (!new_div) { ++ ret = NOTIFY_STOP_MASK; ++ goto unlock; ++ } ++ ++ /* Update the div to preserve MCK DIV clock rate. */ ++ clk_master_div_set(master_div, new_parent_rate, ++ new_div); ++ ++ ret = NOTIFY_OK; ++ break; ++ ++ default: ++ ret = NOTIFY_DONE; ++ break; ++ } ++ ++unlock: ++ spin_unlock_irqrestore(master_div->lock, flags); ++ ++ return ret; ++} ++ ++static struct notifier_block clk_master_div_notifier = { ++ .notifier_call = clk_master_div_notifier_fn, ++}; ++ + static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, + struct clk_hw *parent, + unsigned long parent_rate, +@@ -496,6 +578,8 @@ at91_clk_register_master_internal(struct + struct clk_master *master; + struct clk_init_data init; + struct clk_hw *hw; ++ unsigned int mckr; ++ unsigned long irqflags; + int ret; + + if (!name || !num_parents || !parent_names || !lock) +@@ -518,6 +602,16 @@ at91_clk_register_master_internal(struct + master->chg_pid = chg_pid; + master->lock = lock; + ++ if (ops == &master_div_ops_chg) { ++ spin_lock_irqsave(master->lock, irqflags); ++ regmap_read(master->regmap, master->layout->offset, &mckr); ++ spin_unlock_irqrestore(master->lock, irqflags); ++ ++ mckr &= layout->mask; ++ mckr = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ master->div = characteristics->divisors[mckr]; ++ } ++ + hw = &master->hw; + ret = clk_hw_register(NULL, &master->hw); + if (ret) { +@@ -554,19 +648,29 @@ at91_clk_register_master_div(struct regm + const char *name, const char *parent_name, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics, +- spinlock_t *lock, u32 flags) ++ spinlock_t *lock, u32 flags, u32 safe_div) + { + const struct clk_ops *ops; ++ struct clk_hw *hw; + + if (flags & CLK_SET_RATE_GATE) + ops = &master_div_ops; + else + ops = &master_div_ops_chg; + +- return at91_clk_register_master_internal(regmap, name, 1, +- &parent_name, layout, +- characteristics, ops, +- lock, flags, -EINVAL); ++ hw = at91_clk_register_master_internal(regmap, name, 1, ++ &parent_name, layout, ++ characteristics, ops, ++ lock, flags, -EINVAL); ++ ++ if (!IS_ERR(hw) && safe_div) { ++ master_div = to_clk_master(hw); ++ master_div->safe_div = safe_div; ++ clk_notifier_register(hw->clk, ++ &clk_master_div_notifier); ++ } ++ ++ return hw; + } + + static unsigned long +--- a/drivers/clk/at91/dt-compat.c ++++ b/drivers/clk/at91/dt-compat.c +@@ -399,7 +399,7 @@ of_at91_clk_master_setup(struct device_n + + hw = at91_clk_register_master_div(regmap, name, "masterck_pres", + layout, characteristics, +- &mck_lock, CLK_SET_RATE_GATE); ++ &mck_lock, CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto out_free_characteristics; + +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -182,7 +182,7 @@ at91_clk_register_master_div(struct regm + const char *parent_names, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics, +- spinlock_t *lock, u32 flags); ++ spinlock_t *lock, u32 flags, u32 safe_div); + + struct clk_hw * __init + at91_clk_sama7g5_register_master(struct regmap *regmap, +--- a/drivers/clk/at91/sama5d2.c ++++ b/drivers/clk/at91/sama5d2.c +@@ -249,7 +249,7 @@ static void __init sama5d2_pmc_setup(str + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/sama5d3.c ++++ b/drivers/clk/at91/sama5d3.c +@@ -184,7 +184,7 @@ static void __init sama5d3_pmc_setup(str + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/sama5d4.c ++++ b/drivers/clk/at91/sama5d4.c +@@ -199,7 +199,7 @@ static void __init sama5d4_pmc_setup(str + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -993,7 +993,7 @@ static void __init sama7g5_pmc_setup(str + parent_names[0] = "cpupll_divpmcck"; + hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck", + &mck0_layout, &mck0_characteristics, +- &pmc_mck0_lock, 0); ++ &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); + if (IS_ERR(hw)) + goto err_free; + diff --git a/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch b/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch new file mode 100644 index 0000000000..6cdec0add7 --- /dev/null +++ b/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch @@ -0,0 +1,26 @@ +From 9fd5a49f6da9de5da83f4a53eccefad647ab15ed Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:18 +0300 +Subject: [PATCH 246/247] clk: at91: sama7g5: set low limit for mck0 at 32KHz + +MCK0 could go as low as 32KHz. Set this limit. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-15-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -849,7 +849,7 @@ static const struct { + + /* MCK0 characteristics. */ + static const struct clk_master_characteristics mck0_characteristics = { +- .output = { .min = 50000000, .max = 200000000 }, ++ .output = { .min = 32768, .max = 200000000 }, + .divisors = { 1, 2, 4, 3, 5 }, + .have_div3_pres = 1, + }; diff --git a/target/linux/at91/patches-5.15/109-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch b/target/linux/at91/patches-5.15/109-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch new file mode 100644 index 0000000000..32e760ac17 --- /dev/null +++ b/target/linux/at91/patches-5.15/109-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch @@ -0,0 +1,32 @@ +From fe07791494a78d5a4be1363385e6ba7940740644 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:19 +0300 +Subject: [PATCH 247/247] clk: use clk_core_get_rate_recalc() in clk_rate_get() + +In case clock flags contains CLK_GET_RATE_NOCACHE the clk_rate_get() +will return the cached rate. Thus, use clk_core_get_rate_recalc() which +takes proper action when clock flags contains CLK_GET_RATE_NOCACHE. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-16-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +[sboyd@kernel.org: Grab prepare lock around operation] +Signed-off-by: Stephen Boyd +--- + drivers/clk/clk.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -3131,7 +3131,10 @@ static int clk_rate_get(void *data, u64 + { + struct clk_core *core = data; + +- *val = core->rate; ++ clk_prepare_lock(); ++ *val = clk_core_get_rate_recalc(core); ++ clk_prepare_unlock(); ++ + return 0; + } + diff --git a/target/linux/at91/sam9x/config-default b/target/linux/at91/sam9x/config-5.10 similarity index 99% rename from target/linux/at91/sam9x/config-default rename to target/linux/at91/sam9x/config-5.10 index 609e182905..63575c6093 100644 --- a/target/linux/at91/sam9x/config-default +++ b/target/linux/at91/sam9x/config-5.10 @@ -21,7 +21,6 @@ CONFIG_ARM_L1_CACHE_SHIFT=5 CONFIG_ARM_PATCH_PHYS_VIRT=y CONFIG_ARM_THUMB=y CONFIG_ARM_UNWIND=y -# CONFIG_ASN1 is not set # CONFIG_AT91RM9200_WATCHDOG is not set CONFIG_AT91SAM9X_WATCHDOG=y # CONFIG_AT91_ADC is not set diff --git a/target/linux/at91/sam9x/config-5.15 b/target/linux/at91/sam9x/config-5.15 new file mode 100644 index 0000000000..ffbd2aba62 --- /dev/null +++ b/target/linux/at91/sam9x/config-5.15 @@ -0,0 +1,319 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_AT91=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_V4 is not set +CONFIG_ARCH_MULTI_V4T=y +CONFIG_ARCH_MULTI_V4_V5=y +CONFIG_ARCH_MULTI_V5=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +# CONFIG_AT91RM9200_WATCHDOG is not set +CONFIG_AT91SAM9X_WATCHDOG=y +# CONFIG_AT91_ADC is not set +CONFIG_AT91_SAMA5D2_ADC=y +CONFIG_AT91_SOC_ID=y +# CONFIG_AT91_SOC_SFR is not set +CONFIG_ATMEL_AIC5_IRQ=y +CONFIG_ATMEL_AIC_IRQ=y +CONFIG_ATMEL_CLOCKSOURCE_PIT=y +CONFIG_ATMEL_CLOCKSOURCE_TCB=y +CONFIG_ATMEL_EBI=y +CONFIG_ATMEL_PIT=y +CONFIG_ATMEL_PM=y +CONFIG_ATMEL_SDRAMC=y +CONFIG_ATMEL_SSC=y +CONFIG_ATMEL_ST=y +CONFIG_ATMEL_TCB_CLKSRC=y +CONFIG_AT_HDMAC=y +CONFIG_AT_XDMAC=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_PM=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_AT91=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CPU_32v4T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_ARM920T=y +CONFIG_CPU_ARM926T=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_CPU_CACHE_V4WT=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +CONFIG_CPU_NO_EFFICIENT_FFS=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_PM=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CRC16=y +CONFIG_CRC7=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DTC=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_EXT4_FS=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ATMEL=y +CONFIG_HZ=128 +CONFIG_HZ_FIXED=128 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_AT91=y +# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_GPIO=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACB=y +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MFD_AT91_USART=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_MFD_ATMEL_HLCDC=y +CONFIG_MFD_ATMEL_SMC=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MICROCHIP_PIT64B=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_AT91=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_OTP is not set +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_GLUEBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NLS=y +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +# CONFIG_PINCTRL_AT91PIO4 is not set +CONFIG_PINCTRL_MCP23S08=y +CONFIG_PINCTRL_MCP23S08_I2C=y +CONFIG_PINCTRL_MCP23S08_SPI=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_SLEEP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_AT91_POWEROFF=y +CONFIG_POWER_RESET_AT91_RESET=y +CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_ATMEL=y +CONFIG_PWM_ATMEL_HLCDC_PWM=y +CONFIG_PWM_ATMEL_TCB=y +CONFIG_PWM_SYSFS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +CONFIG_RTC_DRV_AT91SAM9=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_SAMA5D4_WATCHDOG=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SGL_ALLOC=y +CONFIG_SOC_AT91RM9200=y +CONFIG_SOC_AT91SAM9=y +CONFIG_SOC_BUS=y +CONFIG_SOC_SAM9X60=y +CONFIG_SOC_SAM_V4_V5=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_AT91_USART is not set +CONFIG_SPI_ATMEL=y +CONFIG_SPI_ATMEL_QUADSPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +CONFIG_SRCU=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWPHY=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_ACM=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +# CONFIG_USB_AT91 is not set +# CONFIG_USB_ATMEL_USBA is not set +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_AT91=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_GADGET=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_AT91=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +# CONFIG_VFP is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_XXHASH=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/at91/sama5/config-default b/target/linux/at91/sama5/config-5.10 similarity index 99% rename from target/linux/at91/sama5/config-default rename to target/linux/at91/sama5/config-5.10 index e7478cf5c7..ee607b484f 100644 --- a/target/linux/at91/sama5/config-default +++ b/target/linux/at91/sama5/config-5.10 @@ -25,7 +25,6 @@ CONFIG_ARM_PATCH_PHYS_VIRT=y CONFIG_ARM_THUMB=y CONFIG_ARM_UNWIND=y CONFIG_ARM_VIRT_EXT=y -# CONFIG_ASN1 is not set CONFIG_AT91SAM9X_WATCHDOG=y CONFIG_AT91_ADC=y CONFIG_AT91_SAMA5D2_ADC=y @@ -172,6 +171,7 @@ CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IDLE_POLL_SETUP=y diff --git a/target/linux/at91/sama5/config-5.15 b/target/linux/at91/sama5/config-5.15 new file mode 100644 index 0000000000..e2fbc5ba7d --- /dev/null +++ b/target/linux/at91/sama5/config-5.15 @@ -0,0 +1,489 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_AT91=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_AT91_CPUIDLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_AT91SAM9X_WATCHDOG=y +CONFIG_AT91_ADC=y +CONFIG_AT91_SAMA5D2_ADC=y +CONFIG_AT91_SOC_ID=y +# CONFIG_AT91_SOC_SFR is not set +CONFIG_ATMEL_AIC5_IRQ=y +# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set +CONFIG_ATMEL_CLOCKSOURCE_TCB=y +CONFIG_ATMEL_EBI=y +CONFIG_ATMEL_PM=y +CONFIG_ATMEL_SDRAMC=y +CONFIG_ATMEL_SSC=y +CONFIG_ATMEL_TCB_CLKSRC=y +CONFIG_AT_HDMAC=y +CONFIG_AT_XDMAC=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BATTERY_ACT8945A=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_PM=y +CONFIG_CACHE_L2X0=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_AT91=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONTIG_ALLOC=y +CONFIG_COREDUMP=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRASH_CORE=y +CONFIG_CRASH_DUMP=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_USER=y +CONFIG_DMADEVICES=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DNOTIFY=y +CONFIG_DRM=y +CONFIG_DRM_ATMEL_HLCDC=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_DP_AUX_BUS=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_KMS_CMA_HELPER=y +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_BRIDGE=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DTC=y +CONFIG_DVB_CORE=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_ELF_CORE=y +CONFIG_EXT4_FS=y +CONFIG_FAT_FS=y +CONFIG_FB=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FORCE_MAX_ZONEORDER=15 +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HDMI=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ATMEL=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_AT91=y +# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +# CONFIG_JFFS2_FS is not set +CONFIG_KCMP=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_QT1070=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACB=y +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +CONFIG_MEDIA_TUNER=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MFD_ACT8945A=y +CONFIG_MFD_AT91_USART=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_MFD_ATMEL_HLCDC=y +CONFIG_MFD_ATMEL_SMC=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_AT91=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_NEON is not set +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_PINCTRL_AT91PIO4=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_SLEEP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_AT91_POWEROFF=y +CONFIG_POWER_RESET_AT91_RESET=y +CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_PRINTK_TIME=y +CONFIG_PROC_VMCORE=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_ATMEL=y +CONFIG_PWM_ATMEL_HLCDC_PWM=y +CONFIG_PWM_ATMEL_TCB=y +CONFIG_PWM_SYSFS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_ACT8865=y +CONFIG_REGULATOR_ACT8945A=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +# CONFIG_RTC_DRV_AT91SAM9 is not set +# CONFIG_RTC_DRV_CMOS is not set +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_SAMA5D4_WATCHDOG=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SND=y +CONFIG_SND_ARM=y +# CONFIG_SND_AT73C213 is not set +# CONFIG_SND_AT91_SOC_SAM9G20_WM8731 is not set +# CONFIG_SND_AT91_SOC_SAM9X5_WM8731 is not set +CONFIG_SND_ATMEL_SOC=y +CONFIG_SND_ATMEL_SOC_CLASSD=y +CONFIG_SND_ATMEL_SOC_DMA=y +CONFIG_SND_ATMEL_SOC_I2S=y +CONFIG_SND_ATMEL_SOC_PDC=y +# CONFIG_SND_ATMEL_SOC_PDMIC is not set +CONFIG_SND_ATMEL_SOC_SSC=y +CONFIG_SND_ATMEL_SOC_SSC_DMA=y +# CONFIG_SND_ATMEL_SOC_SSC_PDC is not set +# CONFIG_SND_ATMEL_SOC_TSE850_PCM5142 is not set +CONFIG_SND_ATMEL_SOC_WM8904=y +# CONFIG_SND_COMPRESS_OFFLOAD is not set +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_MCHP_SOC_I2S_MCC is not set +# CONFIG_SND_MCHP_SOC_SPDIFRX is not set +# CONFIG_SND_MCHP_SOC_SPDIFTX is not set +CONFIG_SND_PCM=y +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_I2C_AND_SPI=y +CONFIG_SND_SOC_MIKROE_PROTO=y +CONFIG_SND_SOC_WM8731=y +CONFIG_SND_SOC_WM8904=y +CONFIG_SND_SPI=y +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_TIMER=y +CONFIG_SOC_BUS=y +CONFIG_SOC_SAMA5=y +CONFIG_SOC_SAMA5D2=y +CONFIG_SOC_SAMA5D3=y +CONFIG_SOC_SAMA5D4=y +# CONFIG_SOC_SAMA7G5 is not set +CONFIG_SOC_SAM_V7=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_AT91_USART is not set +CONFIG_SPI_ATMEL=y +CONFIG_SPI_ATMEL_QUADSPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SQUASHFS is not set +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +CONFIG_SRCU=y +# CONFIG_STANDALONE is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWPHY=y +# CONFIG_SWP_EMULATE is not set +CONFIG_SYNC_FILE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_UBIFS_FS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_ACM=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +# CONFIG_USB_AT91 is not set +# CONFIG_USB_ATMEL_USBA is not set +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_AT91=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_GADGET=y +CONFIG_USB_HID=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_AT91=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +# CONFIG_USB_PWC is not set +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VFAT_FS=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VIDEOMODE_HELPERS=y +# CONFIG_VIDEO_CPIA2 is not set +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XXHASH=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/at91/sama7/config-default b/target/linux/at91/sama7/config-5.10 similarity index 100% rename from target/linux/at91/sama7/config-default rename to target/linux/at91/sama7/config-5.10 diff --git a/target/linux/at91/sama7/config-5.15 b/target/linux/at91/sama7/config-5.15 new file mode 100644 index 0000000000..4ff0d3df23 --- /dev/null +++ b/target/linux/at91/sama7/config-5.15 @@ -0,0 +1,403 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_AT91=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_PATCH_IDIV is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +# CONFIG_AT91SAM9X_WATCHDOG is not set +# CONFIG_AT91_ADC is not set +CONFIG_AT91_SAMA5D2_ADC=y +CONFIG_AT91_SOC_ID=y +# CONFIG_AT91_SOC_SFR is not set +CONFIG_ATMEL_CLOCKSOURCE_TCB=y +# CONFIG_ATMEL_EBI is not set +CONFIG_ATMEL_SDRAMC=y +CONFIG_ATMEL_TCB_CLKSRC=y +# CONFIG_AT_HDMAC is not set +CONFIG_AT_XDMAC=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_SD=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CAN=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=9 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=256 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk nocache ignore_loglevel" +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_AT91=y +# CONFIG_COMPACTION is not set +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTIG_ALLOC=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_SPECTRE=y +# CONFIG_CPU_SW_DOMAIN_PAN is not set +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_AT91_SAMA7G5_FLEXCOM3=y +CONFIG_DEBUG_AT91_UART=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/at91.S" +CONFIG_DEBUG_UART_PHYS=0xe1824200 +CONFIG_DEBUG_UART_VIRT=0xe0824200 +# CONFIG_DEBUG_UNCOMPRESS is not set +CONFIG_DEBUG_USER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMADEVICES=y +CONFIG_DMATEST=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EARLY_PRINTK=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +# CONFIG_EFI_PARTITION is not set +CONFIG_EXT4_FS=y +CONFIG_FANOTIFY=y +CONFIG_FAT_FS=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FORCE_MAX_ZONEORDER=15 +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GRACE_PERIOD=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_AT91=y +# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_CONFIGFS=y +# CONFIG_IIO_HRTIMER_TRIGGER is not set +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_SW_TRIGGER=y +# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_BOOTP is not set +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCKD=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_LSM="N" +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACB=y +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_MFD_AT91_USART=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MICROCHIP_PIT64B=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +# CONFIG_MMC_ATMELMCI is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_AT91=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NEON=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NFS_FS=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCCARD=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_PM_OPP=y +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_AT91_POWEROFF is not set +CONFIG_POWER_RESET_AT91_RESET=y +CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y +CONFIG_PPS=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_ATMEL=y +CONFIG_PWM_SYSFS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MCP16502=y +CONFIG_ROOT_NFS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +CONFIG_RTC_DRV_AT91SAM9=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_SAMA5D4_WATCHDOG=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SND=y +CONFIG_SND_ATMEL_SOC=y +# CONFIG_SND_ATMEL_SOC_CLASSD is not set +# CONFIG_SND_ATMEL_SOC_I2S is not set +# CONFIG_SND_ATMEL_SOC_PDMIC is not set +# CONFIG_SND_COMPRESS_OFFLOAD is not set +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_MCHP_SOC_I2S_MCC=y +CONFIG_SND_MCHP_SOC_SPDIFRX=y +CONFIG_SND_MCHP_SOC_SPDIFTX=y +CONFIG_SND_PCM=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_SIMPLE_CARD_UTILS=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_MIKROE_PROTO is not set +CONFIG_SND_SOC_PCM5102A=y +CONFIG_SND_SOC_SPDIF=y +CONFIG_SOC_BUS=y +# CONFIG_SOC_SAMA5D2 is not set +# CONFIG_SOC_SAMA5D3 is not set +# CONFIG_SOC_SAMA5D4 is not set +CONFIG_SOC_SAMA7=y +CONFIG_SOC_SAMA7G5=y +CONFIG_SOC_SAM_V7=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_AT91_USART is not set +CONFIG_SPI_ATMEL=y +# CONFIG_SPI_ATMEL_QUADSPI is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SRCU=y +CONFIG_STACKTRACE=y +# CONFIG_STANDALONE is not set +CONFIG_SUNRPC=y +# CONFIG_SWAP is not set +CONFIG_SWPHY=y +# CONFIG_SWP_EMULATE is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USE_OF=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VFAT_FS=y +CONFIG_VFP=y +CONFIG_VFPv3=y +# CONFIG_VIDEO_ATMEL_XISC is not set +CONFIG_VIDEO_DEV=y +# CONFIG_VIDEO_IMX208 is not set +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912uag-2hpnd.dts b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912uag-2hpnd.dts index 6435393a73..28a88db5df 100644 --- a/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912uag-2hpnd.dts +++ b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912uag-2hpnd.dts @@ -147,7 +147,7 @@ }; &ref { - clock-frequency = <25000000>; + clock-frequency = <40000000>; }; &spi { diff --git a/target/linux/bcm27xx/bcm2710/config-5.15 b/target/linux/bcm27xx/bcm2710/config-5.15 index 2f1b82484e..2e8b4a4360 100644 --- a/target/linux/bcm27xx/bcm2710/config-5.15 +++ b/target/linux/bcm27xx/bcm2710/config-5.15 @@ -120,6 +120,7 @@ CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CRC16=y diff --git a/target/linux/bcm27xx/bcm2711/config-5.15 b/target/linux/bcm27xx/bcm2711/config-5.15 index 61ced4508a..d98d76c333 100644 --- a/target/linux/bcm27xx/bcm2711/config-5.15 +++ b/target/linux/bcm27xx/bcm2711/config-5.15 @@ -124,6 +124,7 @@ CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CRC16=y diff --git a/target/linux/bcm4908/config-5.10 b/target/linux/bcm4908/config-5.10 index 762ce49eeb..1564123ca7 100644 --- a/target/linux/bcm4908/config-5.10 +++ b/target/linux/bcm4908/config-5.10 @@ -47,6 +47,7 @@ CONFIG_CMDLINE="earlycon=bcm63xx_uart,0xff800640 console=ttyS0,115200" CONFIG_CMDLINE_FORCE=y CONFIG_COMMON_CLK=y # CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_RMAP=y CONFIG_CRC16=y CONFIG_CRYPTO_AES_ARM64=y diff --git a/target/linux/bmips/config-5.15 b/target/linux/bmips/config-5.15 index 433915a3fc..a66443eaba 100644 --- a/target/linux/bmips/config-5.15 +++ b/target/linux/bmips/config-5.15 @@ -46,7 +46,6 @@ CONFIG_CPU_GENERIC_DUMP_TLB=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_CPU_MIPS32=y CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y CONFIG_CPU_NO_EFFICIENT_FFS=y diff --git a/target/linux/generic/pending-5.15/020-00-mm-x86-arm64-add-arch_has_hw_pte_young.patch b/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-00-mm-x86-arm64-add-arch_has_hw_pte_young.patch rename to target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch diff --git a/target/linux/generic/pending-5.15/020-01-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch b/target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-01-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch rename to target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch diff --git a/target/linux/generic/pending-5.15/020-02-mm-vmscan.c-refactor-shrink_node.patch b/target/linux/generic/backport-5.15/020-v6.1-03-mm-vmscan.c-refactor-shrink_node.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-02-mm-vmscan.c-refactor-shrink_node.patch rename to target/linux/generic/backport-5.15/020-v6.1-03-mm-vmscan.c-refactor-shrink_node.patch diff --git a/target/linux/generic/pending-5.15/020-03-mm-multigenerational-lru-groundwork.patch b/target/linux/generic/backport-5.15/020-v6.1-04-mm-multigenerational-lru-groundwork.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-03-mm-multigenerational-lru-groundwork.patch rename to target/linux/generic/backport-5.15/020-v6.1-04-mm-multigenerational-lru-groundwork.patch diff --git a/target/linux/generic/pending-5.15/020-04-mm-multigenerational-lru-mm_struct-list.patch b/target/linux/generic/backport-5.15/020-v6.1-05-mm-multigenerational-lru-mm_struct-list.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-04-mm-multigenerational-lru-mm_struct-list.patch rename to target/linux/generic/backport-5.15/020-v6.1-05-mm-multigenerational-lru-mm_struct-list.patch diff --git a/target/linux/generic/pending-5.15/020-05-mm-multigenerational-lru-aging.patch b/target/linux/generic/backport-5.15/020-v6.1-06-mm-multigenerational-lru-aging.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-05-mm-multigenerational-lru-aging.patch rename to target/linux/generic/backport-5.15/020-v6.1-06-mm-multigenerational-lru-aging.patch diff --git a/target/linux/generic/pending-5.15/020-06-mm-multigenerational-lru-eviction.patch b/target/linux/generic/backport-5.15/020-v6.1-07-mm-multigenerational-lru-eviction.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-06-mm-multigenerational-lru-eviction.patch rename to target/linux/generic/backport-5.15/020-v6.1-07-mm-multigenerational-lru-eviction.patch diff --git a/target/linux/generic/pending-5.15/020-07-mm-multigenerational-lru-user-interface.patch b/target/linux/generic/backport-5.15/020-v6.1-08-mm-multigenerational-lru-user-interface.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-07-mm-multigenerational-lru-user-interface.patch rename to target/linux/generic/backport-5.15/020-v6.1-08-mm-multigenerational-lru-user-interface.patch diff --git a/target/linux/generic/pending-5.15/020-08-mm-multigenerational-lru-Kconfig.patch b/target/linux/generic/backport-5.15/020-v6.1-09-mm-multigenerational-lru-Kconfig.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-08-mm-multigenerational-lru-Kconfig.patch rename to target/linux/generic/backport-5.15/020-v6.1-09-mm-multigenerational-lru-Kconfig.patch diff --git a/target/linux/generic/pending-5.15/020-09-mm-multigenerational-lru-documentation.patch b/target/linux/generic/backport-5.15/020-v6.1-10-mm-multigenerational-lru-documentation.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-09-mm-multigenerational-lru-documentation.patch rename to target/linux/generic/backport-5.15/020-v6.1-10-mm-multigenerational-lru-documentation.patch diff --git a/target/linux/generic/backport-5.15/021-v6.1-mm-mglru-don-t-sync-disk-for-each-aging-cycle.patch b/target/linux/generic/backport-5.15/021-v6.1-mm-mglru-don-t-sync-disk-for-each-aging-cycle.patch new file mode 100644 index 0000000000..269e5eb204 --- /dev/null +++ b/target/linux/generic/backport-5.15/021-v6.1-mm-mglru-don-t-sync-disk-for-each-aging-cycle.patch @@ -0,0 +1,32 @@ +From 14aa8b2d5c2ebead01b542f62d68029023054774 Mon Sep 17 00:00:00 2001 +From: Yu Zhao +Date: Wed, 28 Sep 2022 13:36:58 -0600 +Subject: [PATCH 1/1] mm/mglru: don't sync disk for each aging cycle + +wakeup_flusher_threads() was added under the assumption that if a system +runs out of clean cold pages, it might want to write back dirty pages more +aggressively so that they can become clean and be dropped. + +However, doing so can breach the rate limit a system wants to impose on +writeback, resulting in early SSD wearout. + +Link: https://lkml.kernel.org/r/YzSiWq9UEER5LKup@google.com +Fixes: bd74fdaea146 ("mm: multi-gen LRU: support page table walks") +Signed-off-by: Yu Zhao +Reported-by: Axel Rasmussen +Signed-off-by: Andrew Morton +--- + mm/vmscan.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/mm/vmscan.c ++++ b/mm/vmscan.c +@@ -4072,8 +4072,6 @@ static bool try_to_inc_max_seq(struct lr + if (wq_has_sleeper(&lruvec->mm_walk.wait)) + wake_up_all(&lruvec->mm_walk.wait); + +- wakeup_flusher_threads(WB_REASON_VMSCAN); +- + return true; + } + diff --git a/target/linux/generic/backport-5.15/201-v5.16-scripts-dtc-Update-to-upstream-version-v1.6.1-19-g0a.patch b/target/linux/generic/backport-5.15/201-v5.16-scripts-dtc-Update-to-upstream-version-v1.6.1-19-g0a.patch new file mode 100644 index 0000000000..d1bef74f32 --- /dev/null +++ b/target/linux/generic/backport-5.15/201-v5.16-scripts-dtc-Update-to-upstream-version-v1.6.1-19-g0a.patch @@ -0,0 +1,997 @@ +From a77725a9a3c5924e2fd4cd5b3557dd92a8e46f87 Mon Sep 17 00:00:00 2001 +From: Rob Herring +Date: Mon, 25 Oct 2021 11:05:45 -0500 +Subject: [PATCH 1/1] scripts/dtc: Update to upstream version + v1.6.1-19-g0a3a9d3449c8 + +This adds the following commits from upstream: + +0a3a9d3449c8 checks: Add an interrupt-map check +8fd24744e361 checks: Ensure '#interrupt-cells' only exists in interrupt providers +d8d1a9a77863 checks: Drop interrupt provider '#address-cells' check +52a16fd72824 checks: Make interrupt_provider check dependent on interrupts_extended_is_cell +37fd700685da treesource: Maintain phandle label/path on output +e33ce1d6a8c7 flattree: Use '\n', not ';' to separate asm pseudo-ops +d24cc189dca6 asm: Use assembler macros instead of cpp macros +ff3a30c115ad asm: Use .asciz and .ascii instead of .string +5eb5927d81ee fdtdump: fix -Werror=int-to-pointer-cast +0869f8269161 libfdt: Add ALIGNMENT error string +69595a167f06 checks: Fix bus-range check +72d09e2682a4 Makefile: add -Wsign-compare to warning options +b587787ef388 checks: Fix signedness comparisons warnings +69bed6c2418f dtc: Wrap phandle validity check +910221185560 fdtget: Fix signedness comparisons warnings +d966f08fcd21 tests: Fix signedness comparisons warnings +ecfb438c07fa dtc: Fix signedness comparisons warnings: pointer diff +5bec74a6d135 dtc: Fix signedness comparisons warnings: reservednum +24e7f511fd4a fdtdump: Fix signedness comparisons warnings +b6910bec1161 Bump version to v1.6.1 +21d61d18f968 Fix CID 1461557 +4c2ef8f4d14c checks: Introduce is_multiple_of() +e59ca36fb70e Make handling of cpp line information more tolerant +0c3fd9b6aceb checks: Drop interrupt_cells_is_cell check +6b3081abc4ac checks: Add check_is_cell() for all phandle+arg properties +2dffc192a77f yamltree: Remove marker ordering dependency +61e513439e40 pylibfdt: Rework "avoid unused variable warning" lines +c8bddd106095 tests: add a positive gpio test case +ad4abfadb687 checks: replace strstr and strrchr with strends +09c6a6e88718 dtc.h: add strends for suffix matching +9bb9b8d0b4a0 checks: tigthen up nr-gpios prop exception +b07b62ee3342 libfdt: Add FDT alignment check to fdt_check_header() +a2def5479950 libfdt: Check that the root-node name is empty +4ca61f84dc21 libfdt: Check that there is only one root node +34d708249a91 dtc: Remove -O dtbo support +8e7ff260f755 libfdt: Fix a possible "unchecked return value" warning +88875268c05c checks: Warn on node-name and property name being the same +9d2279e7e6ee checks: Change node-name check to match devicetree spec +f527c867a8c6 util: limit gnu_printf format attribute to gcc >= 4.4.0 + +Reviewed-by: Frank Rowand +Tested-by: Frank Rowand +Signed-off-by: Rob Herring +--- + scripts/dtc/checks.c | 222 ++++++++++++++++++++++-------- + scripts/dtc/dtc-lexer.l | 2 +- + scripts/dtc/dtc.c | 6 +- + scripts/dtc/dtc.h | 40 +++++- + scripts/dtc/flattree.c | 11 +- + scripts/dtc/libfdt/fdt.c | 4 + + scripts/dtc/libfdt/fdt_rw.c | 18 ++- + scripts/dtc/libfdt/fdt_strerror.c | 1 + + scripts/dtc/libfdt/libfdt.h | 7 + + scripts/dtc/livetree.c | 6 +- + scripts/dtc/treesource.c | 48 +++---- + scripts/dtc/util.h | 6 +- + scripts/dtc/version_gen.h | 2 +- + scripts/dtc/yamltree.c | 16 ++- + 14 files changed, 275 insertions(+), 114 deletions(-) + +--- a/scripts/dtc/checks.c ++++ b/scripts/dtc/checks.c +@@ -143,6 +143,14 @@ static void check_nodes_props(struct che + check_nodes_props(c, dti, child); + } + ++static bool is_multiple_of(int multiple, int divisor) ++{ ++ if (divisor == 0) ++ return multiple == 0; ++ else ++ return (multiple % divisor) == 0; ++} ++ + static bool run_check(struct check *c, struct dt_info *dti) + { + struct node *dt = dti->dt; +@@ -297,19 +305,20 @@ ERROR(duplicate_property_names, check_du + #define LOWERCASE "abcdefghijklmnopqrstuvwxyz" + #define UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ" + #define DIGITS "0123456789" +-#define PROPNODECHARS LOWERCASE UPPERCASE DIGITS ",._+*#?-" ++#define NODECHARS LOWERCASE UPPERCASE DIGITS ",._+-@" ++#define PROPCHARS LOWERCASE UPPERCASE DIGITS ",._+*#?-" + #define PROPNODECHARSSTRICT LOWERCASE UPPERCASE DIGITS ",-" + + static void check_node_name_chars(struct check *c, struct dt_info *dti, + struct node *node) + { +- int n = strspn(node->name, c->data); ++ size_t n = strspn(node->name, c->data); + + if (n < strlen(node->name)) + FAIL(c, dti, node, "Bad character '%c' in node name", + node->name[n]); + } +-ERROR(node_name_chars, check_node_name_chars, PROPNODECHARS "@"); ++ERROR(node_name_chars, check_node_name_chars, NODECHARS); + + static void check_node_name_chars_strict(struct check *c, struct dt_info *dti, + struct node *node) +@@ -330,6 +339,20 @@ static void check_node_name_format(struc + } + ERROR(node_name_format, check_node_name_format, NULL, &node_name_chars); + ++static void check_node_name_vs_property_name(struct check *c, ++ struct dt_info *dti, ++ struct node *node) ++{ ++ if (!node->parent) ++ return; ++ ++ if (get_property(node->parent, node->name)) { ++ FAIL(c, dti, node, "node name and property name conflict"); ++ } ++} ++WARNING(node_name_vs_property_name, check_node_name_vs_property_name, ++ NULL, &node_name_chars); ++ + static void check_unit_address_vs_reg(struct check *c, struct dt_info *dti, + struct node *node) + { +@@ -363,14 +386,14 @@ static void check_property_name_chars(st + struct property *prop; + + for_each_property(node, prop) { +- int n = strspn(prop->name, c->data); ++ size_t n = strspn(prop->name, c->data); + + if (n < strlen(prop->name)) + FAIL_PROP(c, dti, node, prop, "Bad character '%c' in property name", + prop->name[n]); + } + } +-ERROR(property_name_chars, check_property_name_chars, PROPNODECHARS); ++ERROR(property_name_chars, check_property_name_chars, PROPCHARS); + + static void check_property_name_chars_strict(struct check *c, + struct dt_info *dti, +@@ -380,7 +403,7 @@ static void check_property_name_chars_st + + for_each_property(node, prop) { + const char *name = prop->name; +- int n = strspn(name, c->data); ++ size_t n = strspn(name, c->data); + + if (n == strlen(prop->name)) + continue; +@@ -497,7 +520,7 @@ static cell_t check_phandle_prop(struct + + phandle = propval_cell(prop); + +- if ((phandle == 0) || (phandle == -1)) { ++ if (!phandle_is_valid(phandle)) { + FAIL_PROP(c, dti, node, prop, "bad value (0x%x) in %s property", + phandle, prop->name); + return 0; +@@ -556,7 +579,7 @@ static void check_name_properties(struct + if (!prop) + return; /* No name property, that's fine */ + +- if ((prop->val.len != node->basenamelen+1) ++ if ((prop->val.len != node->basenamelen + 1U) + || (memcmp(prop->val.val, node->name, node->basenamelen) != 0)) { + FAIL(c, dti, node, "\"name\" property is incorrect (\"%s\" instead" + " of base node name)", prop->val.val); +@@ -657,7 +680,6 @@ ERROR(omit_unused_nodes, fixup_omit_unus + */ + WARNING_IF_NOT_CELL(address_cells_is_cell, "#address-cells"); + WARNING_IF_NOT_CELL(size_cells_is_cell, "#size-cells"); +-WARNING_IF_NOT_CELL(interrupt_cells_is_cell, "#interrupt-cells"); + + WARNING_IF_NOT_STRING(device_type_is_string, "device_type"); + WARNING_IF_NOT_STRING(model_is_string, "model"); +@@ -672,8 +694,7 @@ static void check_names_is_string_list(s + struct property *prop; + + for_each_property(node, prop) { +- const char *s = strrchr(prop->name, '-'); +- if (!s || !streq(s, "-names")) ++ if (!strends(prop->name, "-names")) + continue; + + c->data = prop->name; +@@ -753,7 +774,7 @@ static void check_reg_format(struct chec + size_cells = node_size_cells(node->parent); + entrylen = (addr_cells + size_cells) * sizeof(cell_t); + +- if (!entrylen || (prop->val.len % entrylen) != 0) ++ if (!is_multiple_of(prop->val.len, entrylen)) + FAIL_PROP(c, dti, node, prop, "property has invalid length (%d bytes) " + "(#address-cells == %d, #size-cells == %d)", + prop->val.len, addr_cells, size_cells); +@@ -794,7 +815,7 @@ static void check_ranges_format(struct c + "#size-cells (%d) differs from %s (%d)", + ranges, c_size_cells, node->parent->fullpath, + p_size_cells); +- } else if ((prop->val.len % entrylen) != 0) { ++ } else if (!is_multiple_of(prop->val.len, entrylen)) { + FAIL_PROP(c, dti, node, prop, "\"%s\" property has invalid length (%d bytes) " + "(parent #address-cells == %d, child #address-cells == %d, " + "#size-cells == %d)", ranges, prop->val.len, +@@ -871,7 +892,7 @@ static void check_pci_device_bus_num(str + } else { + cells = (cell_t *)prop->val.val; + min_bus = fdt32_to_cpu(cells[0]); +- max_bus = fdt32_to_cpu(cells[0]); ++ max_bus = fdt32_to_cpu(cells[1]); + } + if ((bus_num < min_bus) || (bus_num > max_bus)) + FAIL_PROP(c, dti, node, prop, "PCI bus number %d out of range, expected (%d - %d)", +@@ -1367,9 +1388,9 @@ static void check_property_phandle_args( + const struct provider *provider) + { + struct node *root = dti->dt; +- int cell, cellsize = 0; ++ unsigned int cell, cellsize = 0; + +- if (prop->val.len % sizeof(cell_t)) { ++ if (!is_multiple_of(prop->val.len, sizeof(cell_t))) { + FAIL_PROP(c, dti, node, prop, + "property size (%d) is invalid, expected multiple of %zu", + prop->val.len, sizeof(cell_t)); +@@ -1379,14 +1400,14 @@ static void check_property_phandle_args( + for (cell = 0; cell < prop->val.len / sizeof(cell_t); cell += cellsize + 1) { + struct node *provider_node; + struct property *cellprop; +- int phandle; ++ cell_t phandle; + + phandle = propval_cell_n(prop, cell); + /* + * Some bindings use a cell value 0 or -1 to skip over optional + * entries when each index position has a specific definition. + */ +- if (phandle == 0 || phandle == -1) { ++ if (!phandle_is_valid(phandle)) { + /* Give up if this is an overlay with external references */ + if (dti->dtsflags & DTSF_PLUGIN) + break; +@@ -1452,7 +1473,8 @@ static void check_provider_cells_propert + } + #define WARNING_PROPERTY_PHANDLE_CELLS(nm, propname, cells_name, ...) \ + static struct provider nm##_provider = { (propname), (cells_name), __VA_ARGS__ }; \ +- WARNING(nm##_property, check_provider_cells_property, &nm##_provider, &phandle_references); ++ WARNING_IF_NOT_CELL(nm##_is_cell, cells_name); \ ++ WARNING(nm##_property, check_provider_cells_property, &nm##_provider, &nm##_is_cell, &phandle_references); + + WARNING_PROPERTY_PHANDLE_CELLS(clocks, "clocks", "#clock-cells"); + WARNING_PROPERTY_PHANDLE_CELLS(cooling_device, "cooling-device", "#cooling-cells"); +@@ -1473,24 +1495,17 @@ WARNING_PROPERTY_PHANDLE_CELLS(thermal_s + + static bool prop_is_gpio(struct property *prop) + { +- char *str; +- + /* + * *-gpios and *-gpio can appear in property names, + * so skip over any false matches (only one known ATM) + */ +- if (strstr(prop->name, "nr-gpio")) ++ if (strends(prop->name, ",nr-gpios")) + return false; + +- str = strrchr(prop->name, '-'); +- if (str) +- str++; +- else +- str = prop->name; +- if (!(streq(str, "gpios") || streq(str, "gpio"))) +- return false; +- +- return true; ++ return strends(prop->name, "-gpios") || ++ streq(prop->name, "gpios") || ++ strends(prop->name, "-gpio") || ++ streq(prop->name, "gpio"); + } + + static void check_gpios_property(struct check *c, +@@ -1525,13 +1540,10 @@ static void check_deprecated_gpio_proper + struct property *prop; + + for_each_property(node, prop) { +- char *str; +- + if (!prop_is_gpio(prop)) + continue; + +- str = strstr(prop->name, "gpio"); +- if (!streq(str, "gpio")) ++ if (!strends(prop->name, "gpio")) + continue; + + FAIL_PROP(c, dti, node, prop, +@@ -1561,21 +1573,106 @@ static void check_interrupt_provider(str + struct node *node) + { + struct property *prop; ++ bool irq_provider = node_is_interrupt_provider(node); + +- if (!node_is_interrupt_provider(node)) ++ prop = get_property(node, "#interrupt-cells"); ++ if (irq_provider && !prop) { ++ FAIL(c, dti, node, ++ "Missing '#interrupt-cells' in interrupt provider"); + return; ++ } + +- prop = get_property(node, "#interrupt-cells"); +- if (!prop) ++ if (!irq_provider && prop) { + FAIL(c, dti, node, +- "Missing #interrupt-cells in interrupt provider"); ++ "'#interrupt-cells' found, but node is not an interrupt provider"); ++ return; ++ } ++} ++WARNING(interrupt_provider, check_interrupt_provider, NULL, &interrupts_extended_is_cell); + +- prop = get_property(node, "#address-cells"); +- if (!prop) ++static void check_interrupt_map(struct check *c, ++ struct dt_info *dti, ++ struct node *node) ++{ ++ struct node *root = dti->dt; ++ struct property *prop, *irq_map_prop; ++ size_t cellsize, cell, map_cells; ++ ++ irq_map_prop = get_property(node, "interrupt-map"); ++ if (!irq_map_prop) ++ return; ++ ++ if (node->addr_cells < 0) { + FAIL(c, dti, node, +- "Missing #address-cells in interrupt provider"); ++ "Missing '#address-cells' in interrupt-map provider"); ++ return; ++ } ++ cellsize = node_addr_cells(node); ++ cellsize += propval_cell(get_property(node, "#interrupt-cells")); ++ ++ prop = get_property(node, "interrupt-map-mask"); ++ if (prop && (prop->val.len != (cellsize * sizeof(cell_t)))) ++ FAIL_PROP(c, dti, node, prop, ++ "property size (%d) is invalid, expected %zu", ++ prop->val.len, cellsize * sizeof(cell_t)); ++ ++ if (!is_multiple_of(irq_map_prop->val.len, sizeof(cell_t))) { ++ FAIL_PROP(c, dti, node, irq_map_prop, ++ "property size (%d) is invalid, expected multiple of %zu", ++ irq_map_prop->val.len, sizeof(cell_t)); ++ return; ++ } ++ ++ map_cells = irq_map_prop->val.len / sizeof(cell_t); ++ for (cell = 0; cell < map_cells; ) { ++ struct node *provider_node; ++ struct property *cellprop; ++ int phandle; ++ size_t parent_cellsize; ++ ++ if ((cell + cellsize) >= map_cells) { ++ FAIL_PROP(c, dti, node, irq_map_prop, ++ "property size (%d) too small, expected > %zu", ++ irq_map_prop->val.len, (cell + cellsize) * sizeof(cell_t)); ++ break; ++ } ++ cell += cellsize; ++ ++ phandle = propval_cell_n(irq_map_prop, cell); ++ if (!phandle_is_valid(phandle)) { ++ /* Give up if this is an overlay with external references */ ++ if (!(dti->dtsflags & DTSF_PLUGIN)) ++ FAIL_PROP(c, dti, node, irq_map_prop, ++ "Cell %zu is not a phandle(%d)", ++ cell, phandle); ++ break; ++ } ++ ++ provider_node = get_node_by_phandle(root, phandle); ++ if (!provider_node) { ++ FAIL_PROP(c, dti, node, irq_map_prop, ++ "Could not get phandle(%d) node for (cell %zu)", ++ phandle, cell); ++ break; ++ } ++ ++ cellprop = get_property(provider_node, "#interrupt-cells"); ++ if (cellprop) { ++ parent_cellsize = propval_cell(cellprop); ++ } else { ++ FAIL(c, dti, node, "Missing property '#interrupt-cells' in node %s or bad phandle (referred from interrupt-map[%zu])", ++ provider_node->fullpath, cell); ++ break; ++ } ++ ++ cellprop = get_property(provider_node, "#address-cells"); ++ if (cellprop) ++ parent_cellsize += propval_cell(cellprop); ++ ++ cell += 1 + parent_cellsize; ++ } + } +-WARNING(interrupt_provider, check_interrupt_provider, NULL); ++WARNING(interrupt_map, check_interrupt_map, NULL, &phandle_references, &addr_size_cells, &interrupt_provider); + + static void check_interrupts_property(struct check *c, + struct dt_info *dti, +@@ -1584,13 +1681,13 @@ static void check_interrupts_property(st + struct node *root = dti->dt; + struct node *irq_node = NULL, *parent = node; + struct property *irq_prop, *prop = NULL; +- int irq_cells, phandle; ++ cell_t irq_cells, phandle; + + irq_prop = get_property(node, "interrupts"); + if (!irq_prop) + return; + +- if (irq_prop->val.len % sizeof(cell_t)) ++ if (!is_multiple_of(irq_prop->val.len, sizeof(cell_t))) + FAIL_PROP(c, dti, node, irq_prop, "size (%d) is invalid, expected multiple of %zu", + irq_prop->val.len, sizeof(cell_t)); + +@@ -1603,7 +1700,7 @@ static void check_interrupts_property(st + prop = get_property(parent, "interrupt-parent"); + if (prop) { + phandle = propval_cell(prop); +- if ((phandle == 0) || (phandle == -1)) { ++ if (!phandle_is_valid(phandle)) { + /* Give up if this is an overlay with + * external references */ + if (dti->dtsflags & DTSF_PLUGIN) +@@ -1639,7 +1736,7 @@ static void check_interrupts_property(st + } + + irq_cells = propval_cell(prop); +- if (irq_prop->val.len % (irq_cells * sizeof(cell_t))) { ++ if (!is_multiple_of(irq_prop->val.len, irq_cells * sizeof(cell_t))) { + FAIL_PROP(c, dti, node, prop, + "size is (%d), expected multiple of %d", + irq_prop->val.len, (int)(irq_cells * sizeof(cell_t))); +@@ -1750,7 +1847,7 @@ WARNING(graph_port, check_graph_port, NU + static struct node *get_remote_endpoint(struct check *c, struct dt_info *dti, + struct node *endpoint) + { +- int phandle; ++ cell_t phandle; + struct node *node; + struct property *prop; + +@@ -1760,7 +1857,7 @@ static struct node *get_remote_endpoint( + + phandle = propval_cell(prop); + /* Give up if this is an overlay with external references */ +- if (phandle == 0 || phandle == -1) ++ if (!phandle_is_valid(phandle)) + return NULL; + + node = get_node_by_phandle(dti->dt, phandle); +@@ -1796,7 +1893,7 @@ WARNING(graph_endpoint, check_graph_endp + static struct check *check_table[] = { + &duplicate_node_names, &duplicate_property_names, + &node_name_chars, &node_name_format, &property_name_chars, +- &name_is_string, &name_properties, ++ &name_is_string, &name_properties, &node_name_vs_property_name, + + &duplicate_label, + +@@ -1804,7 +1901,7 @@ static struct check *check_table[] = { + &phandle_references, &path_references, + &omit_unused_nodes, + +- &address_cells_is_cell, &size_cells_is_cell, &interrupt_cells_is_cell, ++ &address_cells_is_cell, &size_cells_is_cell, + &device_type_is_string, &model_is_string, &status_is_string, + &label_is_string, + +@@ -1839,26 +1936,43 @@ static struct check *check_table[] = { + &chosen_node_is_root, &chosen_node_bootargs, &chosen_node_stdout_path, + + &clocks_property, ++ &clocks_is_cell, + &cooling_device_property, ++ &cooling_device_is_cell, + &dmas_property, ++ &dmas_is_cell, + &hwlocks_property, ++ &hwlocks_is_cell, + &interrupts_extended_property, ++ &interrupts_extended_is_cell, + &io_channels_property, ++ &io_channels_is_cell, + &iommus_property, ++ &iommus_is_cell, + &mboxes_property, ++ &mboxes_is_cell, + &msi_parent_property, ++ &msi_parent_is_cell, + &mux_controls_property, ++ &mux_controls_is_cell, + &phys_property, ++ &phys_is_cell, + &power_domains_property, ++ &power_domains_is_cell, + &pwms_property, ++ &pwms_is_cell, + &resets_property, ++ &resets_is_cell, + &sound_dai_property, ++ &sound_dai_is_cell, + &thermal_sensors_property, ++ &thermal_sensors_is_cell, + + &deprecated_gpio_property, + &gpios_property, + &interrupts_property, + &interrupt_provider, ++ &interrupt_map, + + &alias_paths, + +@@ -1882,7 +1996,7 @@ static void enable_warning_error(struct + + static void disable_warning_error(struct check *c, bool warn, bool error) + { +- int i; ++ unsigned int i; + + /* Lowering level, also lower it for things this is the prereq + * for */ +@@ -1903,7 +2017,7 @@ static void disable_warning_error(struct + + void parse_checks_option(bool warn, bool error, const char *arg) + { +- int i; ++ unsigned int i; + const char *name = arg; + bool enable = true; + +@@ -1930,7 +2044,7 @@ void parse_checks_option(bool warn, bool + + void process_checks(bool force, struct dt_info *dti) + { +- int i; ++ unsigned int i; + int error = 0; + + for (i = 0; i < ARRAY_SIZE(check_table); i++) { +--- a/scripts/dtc/dtc-lexer.l ++++ b/scripts/dtc/dtc-lexer.l +@@ -57,7 +57,7 @@ static void PRINTF(1, 2) lexical_error(c + push_input_file(name); + } + +-<*>^"#"(line)?[ \t]+[0-9]+[ \t]+{STRING}([ \t]+[0-9]+)? { ++<*>^"#"(line)?[ \t]+[0-9]+[ \t]+{STRING}([ \t]+[0-9]+)* { + char *line, *fnstart, *fnend; + struct data fn; + /* skip text before line # */ +--- a/scripts/dtc/dtc.c ++++ b/scripts/dtc/dtc.c +@@ -12,7 +12,7 @@ + * Command line options + */ + int quiet; /* Level of quietness */ +-int reservenum; /* Number of memory reservation slots */ ++unsigned int reservenum;/* Number of memory reservation slots */ + int minsize; /* Minimum blob size */ + int padsize; /* Additional padding to blob */ + int alignsize; /* Additional padding to blob accroding to the alignsize */ +@@ -197,7 +197,7 @@ int main(int argc, char *argv[]) + depname = optarg; + break; + case 'R': +- reservenum = strtol(optarg, NULL, 0); ++ reservenum = strtoul(optarg, NULL, 0); + break; + case 'S': + minsize = strtol(optarg, NULL, 0); +@@ -359,8 +359,6 @@ int main(int argc, char *argv[]) + #endif + } else if (streq(outform, "dtb")) { + dt_to_blob(outf, dti, outversion); +- } else if (streq(outform, "dtbo")) { +- dt_to_blob(outf, dti, outversion); + } else if (streq(outform, "asm")) { + dt_to_asm(outf, dti, outversion); + } else if (streq(outform, "null")) { +--- a/scripts/dtc/dtc.h ++++ b/scripts/dtc/dtc.h +@@ -35,7 +35,7 @@ + * Command line options + */ + extern int quiet; /* Level of quietness */ +-extern int reservenum; /* Number of memory reservation slots */ ++extern unsigned int reservenum; /* Number of memory reservation slots */ + extern int minsize; /* Minimum blob size */ + extern int padsize; /* Additional padding to blob */ + extern int alignsize; /* Additional padding to blob accroding to the alignsize */ +@@ -51,6 +51,11 @@ extern int annotate; /* annotate .dts w + + typedef uint32_t cell_t; + ++static inline bool phandle_is_valid(cell_t phandle) ++{ ++ return phandle != 0 && phandle != ~0U; ++} ++ + static inline uint16_t dtb_ld16(const void *p) + { + const uint8_t *bp = (const uint8_t *)p; +@@ -86,6 +91,16 @@ static inline uint64_t dtb_ld64(const vo + #define streq(a, b) (strcmp((a), (b)) == 0) + #define strstarts(s, prefix) (strncmp((s), (prefix), strlen(prefix)) == 0) + #define strprefixeq(a, n, b) (strlen(b) == (n) && (memcmp(a, b, n) == 0)) ++static inline bool strends(const char *str, const char *suffix) ++{ ++ unsigned int len, suffix_len; ++ ++ len = strlen(str); ++ suffix_len = strlen(suffix); ++ if (len < suffix_len) ++ return false; ++ return streq(str + len - suffix_len, suffix); ++} + + #define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) + +@@ -101,6 +116,12 @@ enum markertype { + TYPE_UINT64, + TYPE_STRING, + }; ++ ++static inline bool is_type_marker(enum markertype type) ++{ ++ return type >= TYPE_UINT8; ++} ++ + extern const char *markername(enum markertype markertype); + + struct marker { +@@ -125,7 +146,22 @@ struct data { + for_each_marker(m) \ + if ((m)->type == (t)) + +-size_t type_marker_length(struct marker *m); ++static inline struct marker *next_type_marker(struct marker *m) ++{ ++ for_each_marker(m) ++ if (is_type_marker(m->type)) ++ break; ++ return m; ++} ++ ++static inline size_t type_marker_length(struct marker *m) ++{ ++ struct marker *next = next_type_marker(m->next); ++ ++ if (next) ++ return next->offset - m->offset; ++ return 0; ++} + + void data_free(struct data d); + +--- a/scripts/dtc/flattree.c ++++ b/scripts/dtc/flattree.c +@@ -124,7 +124,8 @@ static void asm_emit_cell(void *e, cell_ + { + FILE *f = e; + +- fprintf(f, "\t.byte 0x%02x; .byte 0x%02x; .byte 0x%02x; .byte 0x%02x\n", ++ fprintf(f, "\t.byte\t0x%02x\n" "\t.byte\t0x%02x\n" ++ "\t.byte\t0x%02x\n" "\t.byte\t0x%02x\n", + (val >> 24) & 0xff, (val >> 16) & 0xff, + (val >> 8) & 0xff, val & 0xff); + } +@@ -134,9 +135,9 @@ static void asm_emit_string(void *e, con + FILE *f = e; + + if (len != 0) +- fprintf(f, "\t.string\t\"%.*s\"\n", len, str); ++ fprintf(f, "\t.asciz\t\"%.*s\"\n", len, str); + else +- fprintf(f, "\t.string\t\"%s\"\n", str); ++ fprintf(f, "\t.asciz\t\"%s\"\n", str); + } + + static void asm_emit_align(void *e, int a) +@@ -295,7 +296,7 @@ static struct data flatten_reserve_list( + { + struct reserve_info *re; + struct data d = empty_data; +- int j; ++ unsigned int j; + + for (re = reservelist; re; re = re->next) { + d = data_append_re(d, re->address, re->size); +@@ -438,7 +439,7 @@ static void dump_stringtable_asm(FILE *f + + while (p < (strbuf.val + strbuf.len)) { + len = strlen(p); +- fprintf(f, "\t.string \"%s\"\n", p); ++ fprintf(f, "\t.asciz \"%s\"\n", p); + p += len+1; + } + } +--- a/scripts/dtc/libfdt/fdt.c ++++ b/scripts/dtc/libfdt/fdt.c +@@ -90,6 +90,10 @@ int fdt_check_header(const void *fdt) + { + size_t hdrsize; + ++ /* The device tree must be at an 8-byte aligned address */ ++ if ((uintptr_t)fdt & 7) ++ return -FDT_ERR_ALIGNMENT; ++ + if (fdt_magic(fdt) != FDT_MAGIC) + return -FDT_ERR_BADMAGIC; + if (!can_assume(LATEST)) { +--- a/scripts/dtc/libfdt/fdt_rw.c ++++ b/scripts/dtc/libfdt/fdt_rw.c +@@ -349,7 +349,10 @@ int fdt_add_subnode_namelen(void *fdt, i + return offset; + + /* Try to place the new node after the parent's properties */ +- fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */ ++ tag = fdt_next_tag(fdt, parentoffset, &nextoffset); ++ /* the fdt_subnode_offset_namelen() should ensure this never hits */ ++ if (!can_assume(LIBFDT_FLAWLESS) && (tag != FDT_BEGIN_NODE)) ++ return -FDT_ERR_INTERNAL; + do { + offset = nextoffset; + tag = fdt_next_tag(fdt, offset, &nextoffset); +@@ -391,7 +394,9 @@ int fdt_del_node(void *fdt, int nodeoffs + } + + static void fdt_packblocks_(const char *old, char *new, +- int mem_rsv_size, int struct_size) ++ int mem_rsv_size, ++ int struct_size, ++ int strings_size) + { + int mem_rsv_off, struct_off, strings_off; + +@@ -406,8 +411,7 @@ static void fdt_packblocks_(const char * + fdt_set_off_dt_struct(new, struct_off); + fdt_set_size_dt_struct(new, struct_size); + +- memmove(new + strings_off, old + fdt_off_dt_strings(old), +- fdt_size_dt_strings(old)); ++ memmove(new + strings_off, old + fdt_off_dt_strings(old), strings_size); + fdt_set_off_dt_strings(new, strings_off); + fdt_set_size_dt_strings(new, fdt_size_dt_strings(old)); + } +@@ -467,7 +471,8 @@ int fdt_open_into(const void *fdt, void + return -FDT_ERR_NOSPACE; + } + +- fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size); ++ fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size, ++ fdt_size_dt_strings(fdt)); + memmove(buf, tmp, newsize); + + fdt_set_magic(buf, FDT_MAGIC); +@@ -487,7 +492,8 @@ int fdt_pack(void *fdt) + + mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) + * sizeof(struct fdt_reserve_entry); +- fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt)); ++ fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt), ++ fdt_size_dt_strings(fdt)); + fdt_set_totalsize(fdt, fdt_data_size_(fdt)); + + return 0; +--- a/scripts/dtc/libfdt/fdt_strerror.c ++++ b/scripts/dtc/libfdt/fdt_strerror.c +@@ -39,6 +39,7 @@ static struct fdt_errtabent fdt_errtable + FDT_ERRTABENT(FDT_ERR_BADOVERLAY), + FDT_ERRTABENT(FDT_ERR_NOPHANDLES), + FDT_ERRTABENT(FDT_ERR_BADFLAGS), ++ FDT_ERRTABENT(FDT_ERR_ALIGNMENT), + }; + #define FDT_ERRTABSIZE ((int)(sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))) + +--- a/scripts/dtc/libfdt/libfdt.h ++++ b/scripts/dtc/libfdt/libfdt.h +@@ -131,6 +131,13 @@ uint32_t fdt_next_tag(const void *fdt, i + * to work even with unaligned pointers on platforms (such as ARMv5) that don't + * like unaligned loads and stores. + */ ++static inline uint16_t fdt16_ld(const fdt16_t *p) ++{ ++ const uint8_t *bp = (const uint8_t *)p; ++ ++ return ((uint16_t)bp[0] << 8) | bp[1]; ++} ++ + static inline uint32_t fdt32_ld(const fdt32_t *p) + { + const uint8_t *bp = (const uint8_t *)p; +--- a/scripts/dtc/livetree.c ++++ b/scripts/dtc/livetree.c +@@ -526,7 +526,7 @@ struct node *get_node_by_path(struct nod + p = strchr(path, '/'); + + for_each_child(tree, child) { +- if (p && strprefixeq(path, p - path, child->name)) ++ if (p && strprefixeq(path, (size_t)(p - path), child->name)) + return get_node_by_path(child, p+1); + else if (!p && streq(path, child->name)) + return child; +@@ -559,7 +559,7 @@ struct node *get_node_by_phandle(struct + { + struct node *child, *node; + +- if ((phandle == 0) || (phandle == -1)) { ++ if (!phandle_is_valid(phandle)) { + assert(generate_fixups); + return NULL; + } +@@ -594,7 +594,7 @@ cell_t get_node_phandle(struct node *roo + static cell_t phandle = 1; /* FIXME: ick, static local */ + struct data d = empty_data; + +- if ((node->phandle != 0) && (node->phandle != -1)) ++ if (phandle_is_valid(node->phandle)) + return node->phandle; + + while (get_node_by_phandle(root, phandle)) +--- a/scripts/dtc/treesource.c ++++ b/scripts/dtc/treesource.c +@@ -124,27 +124,6 @@ static void write_propval_int(FILE *f, c + } + } + +-static bool has_data_type_information(struct marker *m) +-{ +- return m->type >= TYPE_UINT8; +-} +- +-static struct marker *next_type_marker(struct marker *m) +-{ +- while (m && !has_data_type_information(m)) +- m = m->next; +- return m; +-} +- +-size_t type_marker_length(struct marker *m) +-{ +- struct marker *next = next_type_marker(m->next); +- +- if (next) +- return next->offset - m->offset; +- return 0; +-} +- + static const char *delim_start[] = { + [TYPE_UINT8] = "[", + [TYPE_UINT16] = "/bits/ 16 <", +@@ -229,26 +208,39 @@ static void write_propval(FILE *f, struc + size_t chunk_len = (m->next ? m->next->offset : len) - m->offset; + size_t data_len = type_marker_length(m) ? : len - m->offset; + const char *p = &prop->val.val[m->offset]; ++ struct marker *m_phandle; + +- if (has_data_type_information(m)) { ++ if (is_type_marker(m->type)) { + emit_type = m->type; + fprintf(f, " %s", delim_start[emit_type]); + } else if (m->type == LABEL) + fprintf(f, " %s:", m->ref); +- else if (m->offset) +- fputc(' ', f); + +- if (emit_type == TYPE_NONE) { +- assert(chunk_len == 0); ++ if (emit_type == TYPE_NONE || chunk_len == 0) + continue; +- } + + switch(emit_type) { + case TYPE_UINT16: + write_propval_int(f, p, chunk_len, 2); + break; + case TYPE_UINT32: +- write_propval_int(f, p, chunk_len, 4); ++ m_phandle = prop->val.markers; ++ for_each_marker_of_type(m_phandle, REF_PHANDLE) ++ if (m->offset == m_phandle->offset) ++ break; ++ ++ if (m_phandle) { ++ if (m_phandle->ref[0] == '/') ++ fprintf(f, "&{%s}", m_phandle->ref); ++ else ++ fprintf(f, "&%s", m_phandle->ref); ++ if (chunk_len > 4) { ++ fputc(' ', f); ++ write_propval_int(f, p + 4, chunk_len - 4, 4); ++ } ++ } else { ++ write_propval_int(f, p, chunk_len, 4); ++ } + break; + case TYPE_UINT64: + write_propval_int(f, p, chunk_len, 8); +--- a/scripts/dtc/util.h ++++ b/scripts/dtc/util.h +@@ -13,10 +13,10 @@ + */ + + #ifdef __GNUC__ +-#ifdef __clang__ +-#define PRINTF(i, j) __attribute__((format (printf, i, j))) +-#else ++#if __GNUC__ >= 5 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4) + #define PRINTF(i, j) __attribute__((format (gnu_printf, i, j))) ++#else ++#define PRINTF(i, j) __attribute__((format (printf, i, j))) + #endif + #define NORETURN __attribute__((noreturn)) + #else +--- a/scripts/dtc/version_gen.h ++++ b/scripts/dtc/version_gen.h +@@ -1 +1 @@ +-#define DTC_VERSION "DTC 1.6.0-g183df9e9" ++#define DTC_VERSION "DTC 1.6.1-g0a3a9d34" +--- a/scripts/dtc/yamltree.c ++++ b/scripts/dtc/yamltree.c +@@ -29,11 +29,12 @@ char *yaml_error_name[] = { + (emitter)->problem, __func__, __LINE__); \ + }) + +-static void yaml_propval_int(yaml_emitter_t *emitter, struct marker *markers, char *data, unsigned int len, int width) ++static void yaml_propval_int(yaml_emitter_t *emitter, struct marker *markers, ++ char *data, unsigned int seq_offset, unsigned int len, int width) + { + yaml_event_t event; + void *tag; +- unsigned int off, start_offset = markers->offset; ++ unsigned int off; + + switch(width) { + case 1: tag = "!u8"; break; +@@ -66,7 +67,7 @@ static void yaml_propval_int(yaml_emitte + m = markers; + is_phandle = false; + for_each_marker_of_type(m, REF_PHANDLE) { +- if (m->offset == (start_offset + off)) { ++ if (m->offset == (seq_offset + off)) { + is_phandle = true; + break; + } +@@ -114,6 +115,7 @@ static void yaml_propval(yaml_emitter_t + yaml_event_t event; + unsigned int len = prop->val.len; + struct marker *m = prop->val.markers; ++ struct marker *markers = prop->val.markers; + + /* Emit the property name */ + yaml_scalar_event_initialize(&event, NULL, +@@ -151,19 +153,19 @@ static void yaml_propval(yaml_emitter_t + + switch(m->type) { + case TYPE_UINT16: +- yaml_propval_int(emitter, m, data, chunk_len, 2); ++ yaml_propval_int(emitter, markers, data, m->offset, chunk_len, 2); + break; + case TYPE_UINT32: +- yaml_propval_int(emitter, m, data, chunk_len, 4); ++ yaml_propval_int(emitter, markers, data, m->offset, chunk_len, 4); + break; + case TYPE_UINT64: +- yaml_propval_int(emitter, m, data, chunk_len, 8); ++ yaml_propval_int(emitter, markers, data, m->offset, chunk_len, 8); + break; + case TYPE_STRING: + yaml_propval_string(emitter, data, chunk_len); + break; + default: +- yaml_propval_int(emitter, m, data, chunk_len, 1); ++ yaml_propval_int(emitter, markers, data, m->offset, chunk_len, 1); + break; + } + } diff --git a/target/linux/generic/backport-5.15/330-v5.16-01-MIPS-kernel-proc-add-CPU-option-reporting.patch b/target/linux/generic/backport-5.15/330-v5.16-01-MIPS-kernel-proc-add-CPU-option-reporting.patch new file mode 100644 index 0000000000..c66a3f11b4 --- /dev/null +++ b/target/linux/generic/backport-5.15/330-v5.16-01-MIPS-kernel-proc-add-CPU-option-reporting.patch @@ -0,0 +1,162 @@ +From 626bfa03729959ea9917181fb3d8ffaa1594d02a Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Wed, 13 Oct 2021 22:40:18 -0700 +Subject: [PATCH 1/1] MIPS: kernel: proc: add CPU option reporting + +Many MIPS CPUs have optional CPU features which are not activated for +all CPU cores. Print the CPU options, which are implemented in the core, +in /proc/cpuinfo. This makes it possible to see which features are +supported and which are not supported. This should cover all standard +MIPS extensions. Before, it only printed information about the main MIPS +ASEs. + +Signed-off-by: Hauke Mehrtens + +Changes from original patch[0]: +- Remove cpu_has_6k_cache and cpu_has_8k_cache due to commit 6ce91ba8589a + ("MIPS: Remove cpu_has_6k_cache and cpu_has_8k_cache in cpu_cache_init()") +- Add new options: mac2008_only, ftlbparex, gsexcex, mmid, mm_sysad, + mm_full +- Use seq_puts instead of seq_printf as suggested by checkpatch +- Minor commit message reword + +[0]: https://lore.kernel.org/linux-mips/20181223225224.23042-1-hauke@hauke-m.de/ + +Signed-off-by: Ilya Lipnitskiy +Acked-by: Hauke Mehrtens +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/kernel/proc.c | 122 ++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 122 insertions(+) + +--- a/arch/mips/kernel/proc.c ++++ b/arch/mips/kernel/proc.c +@@ -138,6 +138,128 @@ static int show_cpuinfo(struct seq_file + seq_printf(m, "micromips kernel\t: %s\n", + (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no"); + } ++ ++ seq_puts(m, "Options implemented\t:"); ++ if (cpu_has_tlb) ++ seq_puts(m, " tlb"); ++ if (cpu_has_ftlb) ++ seq_puts(m, " ftlb"); ++ if (cpu_has_tlbinv) ++ seq_puts(m, " tlbinv"); ++ if (cpu_has_segments) ++ seq_puts(m, " segments"); ++ if (cpu_has_rixiex) ++ seq_puts(m, " rixiex"); ++ if (cpu_has_ldpte) ++ seq_puts(m, " ldpte"); ++ if (cpu_has_maar) ++ seq_puts(m, " maar"); ++ if (cpu_has_rw_llb) ++ seq_puts(m, " rw_llb"); ++ if (cpu_has_4kex) ++ seq_puts(m, " 4kex"); ++ if (cpu_has_3k_cache) ++ seq_puts(m, " 3k_cache"); ++ if (cpu_has_4k_cache) ++ seq_puts(m, " 4k_cache"); ++ if (cpu_has_tx39_cache) ++ seq_puts(m, " tx39_cache"); ++ if (cpu_has_octeon_cache) ++ seq_puts(m, " octeon_cache"); ++ if (cpu_has_fpu) ++ seq_puts(m, " fpu"); ++ if (cpu_has_32fpr) ++ seq_puts(m, " 32fpr"); ++ if (cpu_has_cache_cdex_p) ++ seq_puts(m, " cache_cdex_p"); ++ if (cpu_has_cache_cdex_s) ++ seq_puts(m, " cache_cdex_s"); ++ if (cpu_has_prefetch) ++ seq_puts(m, " prefetch"); ++ if (cpu_has_mcheck) ++ seq_puts(m, " mcheck"); ++ if (cpu_has_ejtag) ++ seq_puts(m, " ejtag"); ++ if (cpu_has_llsc) ++ seq_puts(m, " llsc"); ++ if (cpu_has_guestctl0ext) ++ seq_puts(m, " guestctl0ext"); ++ if (cpu_has_guestctl1) ++ seq_puts(m, " guestctl1"); ++ if (cpu_has_guestctl2) ++ seq_puts(m, " guestctl2"); ++ if (cpu_has_guestid) ++ seq_puts(m, " guestid"); ++ if (cpu_has_drg) ++ seq_puts(m, " drg"); ++ if (cpu_has_rixi) ++ seq_puts(m, " rixi"); ++ if (cpu_has_lpa) ++ seq_puts(m, " lpa"); ++ if (cpu_has_mvh) ++ seq_puts(m, " mvh"); ++ if (cpu_has_vtag_icache) ++ seq_puts(m, " vtag_icache"); ++ if (cpu_has_dc_aliases) ++ seq_puts(m, " dc_aliases"); ++ if (cpu_has_ic_fills_f_dc) ++ seq_puts(m, " ic_fills_f_dc"); ++ if (cpu_has_pindexed_dcache) ++ seq_puts(m, " pindexed_dcache"); ++ if (cpu_has_userlocal) ++ seq_puts(m, " userlocal"); ++ if (cpu_has_nofpuex) ++ seq_puts(m, " nofpuex"); ++ if (cpu_has_vint) ++ seq_puts(m, " vint"); ++ if (cpu_has_veic) ++ seq_puts(m, " veic"); ++ if (cpu_has_inclusive_pcaches) ++ seq_puts(m, " inclusive_pcaches"); ++ if (cpu_has_perf_cntr_intr_bit) ++ seq_puts(m, " perf_cntr_intr_bit"); ++ if (cpu_has_ufr) ++ seq_puts(m, " ufr"); ++ if (cpu_has_fre) ++ seq_puts(m, " fre"); ++ if (cpu_has_cdmm) ++ seq_puts(m, " cdmm"); ++ if (cpu_has_small_pages) ++ seq_puts(m, " small_pages"); ++ if (cpu_has_nan_legacy) ++ seq_puts(m, " nan_legacy"); ++ if (cpu_has_nan_2008) ++ seq_puts(m, " nan_2008"); ++ if (cpu_has_ebase_wg) ++ seq_puts(m, " ebase_wg"); ++ if (cpu_has_badinstr) ++ seq_puts(m, " badinstr"); ++ if (cpu_has_badinstrp) ++ seq_puts(m, " badinstrp"); ++ if (cpu_has_contextconfig) ++ seq_puts(m, " contextconfig"); ++ if (cpu_has_perf) ++ seq_puts(m, " perf"); ++ if (cpu_has_mac2008_only) ++ seq_puts(m, " mac2008_only"); ++ if (cpu_has_ftlbparex) ++ seq_puts(m, " ftlbparex"); ++ if (cpu_has_gsexcex) ++ seq_puts(m, " gsexcex"); ++ if (cpu_has_shared_ftlb_ram) ++ seq_puts(m, " shared_ftlb_ram"); ++ if (cpu_has_shared_ftlb_entries) ++ seq_puts(m, " shared_ftlb_entries"); ++ if (cpu_has_mipsmt_pertccounters) ++ seq_puts(m, " mipsmt_pertccounters"); ++ if (cpu_has_mmid) ++ seq_puts(m, " mmid"); ++ if (cpu_has_mm_sysad) ++ seq_puts(m, " mm_sysad"); ++ if (cpu_has_mm_full) ++ seq_puts(m, " mm_full"); ++ seq_puts(m, "\n"); ++ + seq_printf(m, "shadow register sets\t: %d\n", + cpu_data[n].srsets); + seq_printf(m, "kscratch registers\t: %d\n", diff --git a/target/linux/generic/backport-5.15/330-v5.16-02-MIPS-Fix-using-smp_processor_id-in-preemptible-in-sh.patch b/target/linux/generic/backport-5.15/330-v5.16-02-MIPS-Fix-using-smp_processor_id-in-preemptible-in-sh.patch new file mode 100644 index 0000000000..6caf7d06d4 --- /dev/null +++ b/target/linux/generic/backport-5.15/330-v5.16-02-MIPS-Fix-using-smp_processor_id-in-preemptible-in-sh.patch @@ -0,0 +1,62 @@ +From 1cab5bd69eb1f995ced2d7576cb15f8a8941fd85 Mon Sep 17 00:00:00 2001 +From: Tiezhu Yang +Date: Thu, 25 Nov 2021 19:39:32 +0800 +Subject: [PATCH 1/1] MIPS: Fix using smp_processor_id() in preemptible in + show_cpuinfo() + +There exists the following issue under DEBUG_PREEMPT: + + BUG: using smp_processor_id() in preemptible [00000000] code: systemd/1 + caller is show_cpuinfo+0x460/0xea0 + ... + Call Trace: + [] show_stack+0x94/0x128 + [] dump_stack_lvl+0x94/0xd8 + [] check_preemption_disabled+0x104/0x110 + [] show_cpuinfo+0x460/0xea0 + [] seq_read_iter+0xfc/0x4f8 + [] new_sync_read+0x110/0x1b8 + [] vfs_read+0x1b4/0x1d0 + [] ksys_read+0xd0/0x110 + [] syscall_common+0x34/0x58 + +We can see the following call trace: + show_cpuinfo() + cpu_has_fpu + current_cpu_data + smp_processor_id() + + $ addr2line -f -e vmlinux 0xffffffff802209c8 + show_cpuinfo + arch/mips/kernel/proc.c:188 + + $ head -188 arch/mips/kernel/proc.c | tail -1 + if (cpu_has_fpu) + + arch/mips/include/asm/cpu-features.h + # define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) + + arch/mips/include/asm/cpu-info.h + #define current_cpu_data cpu_data[smp_processor_id()] + +Based on the above analysis, fix the issue by using raw_cpu_has_fpu +which calls raw_smp_processor_id() in show_cpuinfo(). + +Fixes: 626bfa037299 ("MIPS: kernel: proc: add CPU option reporting") +Signed-off-by: Tiezhu Yang +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/kernel/proc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/kernel/proc.c ++++ b/arch/mips/kernel/proc.c +@@ -166,7 +166,7 @@ static int show_cpuinfo(struct seq_file + seq_puts(m, " tx39_cache"); + if (cpu_has_octeon_cache) + seq_puts(m, " octeon_cache"); +- if (cpu_has_fpu) ++ if (raw_cpu_has_fpu) + seq_puts(m, " fpu"); + if (cpu_has_32fpr) + seq_puts(m, " 32fpr"); diff --git a/target/linux/generic/pending-5.15/483-mtd-spinand-add-support-for-xtx-xt26g0xa.patch b/target/linux/generic/backport-5.15/331-v5.19-mtd-spinand-Add-support-for-XTX-XT26G0xA.patch similarity index 85% rename from target/linux/generic/pending-5.15/483-mtd-spinand-add-support-for-xtx-xt26g0xa.patch rename to target/linux/generic/backport-5.15/331-v5.19-mtd-spinand-Add-support-for-XTX-XT26G0xA.patch index a73c9fa97d..541d247542 100644 --- a/target/linux/generic/pending-5.15/483-mtd-spinand-add-support-for-xtx-xt26g0xa.patch +++ b/target/linux/generic/backport-5.15/331-v5.19-mtd-spinand-Add-support-for-XTX-XT26G0xA.patch @@ -1,7 +1,7 @@ -From a07e31adf2753cad2fd9790db5bfc047c81e8152 Mon Sep 17 00:00:00 2001 +From f4c5c7f9d2e5ab005d57826b740b694b042a737c Mon Sep 17 00:00:00 2001 From: Felix Matouschek -Date: Fri, 2 Jul 2021 20:31:23 +0200 -Subject: [PATCH] mtd: spinand: Add support for XTX XT26G0xA +Date: Mon, 18 Apr 2022 15:28:03 +0200 +Subject: [PATCH 1/1] mtd: spinand: Add support for XTX XT26G0xA Add support for XTX Technology XT26G01AXXXXX, XTX26G02AXXXXX and XTX26G04AXXXXX SPI NAND. @@ -11,17 +11,18 @@ These are 3V, 1G/2G/4Gbit serial SLC NAND flash devices with on-die ECC Tested on Teltonika RUTX10 flashed with OpenWrt. -Datasheets available at -http://www.xtxtech.com/download/?AId=225 -https://datasheet.lcsc.com/szlcsc/2005251034_XTX-XT26G01AWSEGA_C558841.pdf - +Links: + - http://www.xtxtech.com/download/?AId=225 + - https://datasheet.lcsc.com/szlcsc/2005251034_XTX-XT26G01AWSEGA_C558841.pdf Signed-off-by: Felix Matouschek +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20220418132803.664103-1-felix@matouschek.org --- drivers/mtd/nand/spi/Makefile | 2 +- drivers/mtd/nand/spi/core.c | 1 + - drivers/mtd/nand/spi/xtx.c | 122 ++++++++++++++++++++++++++++++++++ + drivers/mtd/nand/spi/xtx.c | 129 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + - 4 files changed, 125 insertions(+), 1 deletion(-) + 4 files changed, 132 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/spi/xtx.c --- a/drivers/mtd/nand/spi/Makefile @@ -43,7 +44,7 @@ Signed-off-by: Felix Matouschek static int spinand_manufacturer_match(struct spinand_device *spinand, --- /dev/null +++ b/drivers/mtd/nand/spi/xtx.c -@@ -0,0 +1,122 @@ +@@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Author: @@ -109,18 +110,25 @@ Signed-off-by: Felix Matouschek +static int xt26g0xa_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ -+ switch (status & XT26G0XA_STATUS_ECC_MASK) { ++ status = status & XT26G0XA_STATUS_ECC_MASK; ++ ++ switch (status) { + case XT26G0XA_STATUS_ECC_NO_DETECTED: + return 0; + case XT26G0XA_STATUS_ECC_8_CORRECTED: + return 8; + case XT26G0XA_STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; -+ default: /* (1 << 2) through (7 << 2) are 1-7 corrected errors */ -+ return (status & XT26G0XA_STATUS_ECC_MASK) >> 2; ++ default: ++ break; + } + -+ return -EINVAL; ++ /* At this point values greater than (2 << 4) are invalid */ ++ if (status > XT26G0XA_STATUS_ECC_UNCOR_ERROR) ++ return -EINVAL; ++ ++ /* (1 << 2) through (7 << 2) are 1-7 corrected errors */ ++ return status >> 2; +} + +static const struct spinand_info xtx_spinand_table[] = { diff --git a/target/linux/generic/pending-5.15/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch b/target/linux/generic/backport-5.15/344-v5.18-01-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch similarity index 95% rename from target/linux/generic/pending-5.15/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch rename to target/linux/generic/backport-5.15/344-v5.18-01-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch index 4a963be952..d6c4b4fd1e 100644 --- a/target/linux/generic/pending-5.15/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch +++ b/target/linux/generic/backport-5.15/344-v5.18-01-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch @@ -1,8 +1,8 @@ -From a719f7ba7fcba05d85801c6f0267f389a21627c1 Mon Sep 17 00:00:00 2001 +From 4bf18d5a2dd02db8c5b16a2cfae513510506df5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Fri, 24 Sep 2021 13:03:02 +0200 -Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Remove port from driver - configuration +Date: Thu, 3 Feb 2022 22:44:40 +0100 +Subject: [PATCH 1/2] phy: marvell: phy-mvebu-a3700-comphy: Remove port from + driver configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -25,6 +25,8 @@ driver code which parses it. This also simplifies the driver. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Reviewed-by: Miquel Raynal +Link: https://lore.kernel.org/r/20220203214444.1508-2-kabel@kernel.org +Signed-off-by: Vinod Koul --- drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 62 +++++++++----------- 1 file changed, 29 insertions(+), 33 deletions(-) diff --git a/target/linux/generic/pending-5.15/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch b/target/linux/generic/backport-5.15/344-v5.18-02-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch similarity index 95% rename from target/linux/generic/pending-5.15/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch rename to target/linux/generic/backport-5.15/344-v5.18-02-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch index 73ead1e16c..4593d14bfe 100644 --- a/target/linux/generic/pending-5.15/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch +++ b/target/linux/generic/backport-5.15/344-v5.18-02-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch @@ -1,7 +1,7 @@ -From 9d276da259cce20b2ed7a868b6e6a6a205f7bb04 Mon Sep 17 00:00:00 2001 +From 934337080c6c59b75db76b180b509f218640ad48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:20:13 +0200 -Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Add native kernel +Date: Thu, 3 Feb 2022 22:44:41 +0100 +Subject: [PATCH 2/2] phy: marvell: phy-mvebu-a3700-comphy: Add native kernel implementation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -46,16 +46,19 @@ original code not conforming to kernel standards. Also PCIe mode poweroff support was added here, and PHY reset support. These changes are also going to be sent to ARM Trusted Firmware. -Signed-off-by: Pali Rohár -Acked-by: Miquel Raynal [ Pali did the porting from ATF. I (Marek) then fixed some register names, some various other things, added some comments and refactored the code to kernel standards. Also fixed PHY poweroff and added PHY reset. ] + +Signed-off-by: Pali Rohár +Acked-by: Miquel Raynal Signed-off-by: Marek Behún +Link: https://lore.kernel.org/r/20220203214444.1508-3-kabel@kernel.org +Signed-off-by: Vinod Koul --- - drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 1351 ++++++++++++++++-- - 1 file changed, 1234 insertions(+), 117 deletions(-) + drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 1332 ++++++++++++++++-- + 1 file changed, 1215 insertions(+), 117 deletions(-) --- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c +++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c @@ -78,7 +81,7 @@ Signed-off-by: Marek Behún #include #include #include -@@ -18,103 +22,1147 @@ +@@ -18,103 +22,1118 @@ #include #include #include @@ -480,23 +483,23 @@ Signed-off-by: Marek Behún - struct arm_smccc_res res; - s32 ret; + u32 val; - -- arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res); -- ret = res.a0; ++ + val = readl(addr); + val = (val & ~mask) | (data & mask); + writel(val, addr); +} +- arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res); +- ret = res.a0; ++static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask) ++{ ++ u16 val; + - switch (ret) { - case SMCCC_RET_SUCCESS: - return 0; - case SMCCC_RET_NOT_SUPPORTED: - return -EOPNOTSUPP; -+static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask) -+{ -+ u16 val; -+ + val = readw(addr); + val = (val & ~mask) | (data & mask); + writew(val, addr); @@ -708,12 +711,10 @@ Signed-off-by: Marek Behún + ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN, + PLL_READY_TX_BIT, COMPHY_PLL_SLEEP, + COMPHY_PLL_TIMEOUT); -+ if (ret) { ++ if (ret) + dev_err(lane->dev, "Failed to lock SATA PLL\n"); -+ return ret; -+ } + -+ return 0; ++ return ret; +} + +static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane, @@ -827,7 +828,8 @@ Signed-off-by: Marek Behún + mask = REF_FREF_SEL_MASK; + comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); + -+ /* 10. Program COMPHY register PHY_GEN_MAX[1:0] ++ /* ++ * 10. Program COMPHY register PHY_GEN_MAX[1:0] + * This step is mentioned in the flow received from verification team. + * However the PHY_GEN_MAX value is only meaningful for other interfaces + * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or @@ -846,9 +848,8 @@ Signed-off-by: Marek Behún + * 12. As long as DFE function needs to be enabled in any mode, + * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F + * for real chip during COMPHY power on. -+ * The step 14 exists (and empty) in the original initialization flow -+ * obtained from the verification team. According to the functional -+ * specification DFE_UPDATE_EN already has the default value 0x3F ++ * The value of the DFE_UPDATE_EN already is 0x3F, because it is the ++ * default value after reset of the PHY. + */ + + /* @@ -867,19 +868,7 @@ Signed-off-by: Marek Behún + lane->submode != PHY_INTERFACE_MODE_2500BASEX); + + /* -+ * 14. [Simulation Only] should not be used for real chip. -+ * By pass power up calibration by programming EXT_FORCE_CAL_DONE -+ * (R02h[9]) to 1 to shorten COMPHY simulation time. -+ */ -+ -+ /* -+ * 15. [Simulation Only: should not be used for real chip] -+ * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training -+ * simulation time. -+ */ -+ -+ /* -+ * 16. Check the PHY Polarity invert bit ++ * 14. Check the PHY Polarity invert bit + */ + data = 0x0; + if (lane->invert_tx) @@ -890,7 +879,7 @@ Signed-off-by: Marek Behún + comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); + + /* -+ * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to ++ * 15. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to + * start PHY power up sequence. All the PHY register programming should + * be done before PIN_PU_PLL=1. There should be no register programming + * for normal PHY operation from this point. @@ -900,7 +889,7 @@ Signed-off-by: Marek Behún + comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); + + /* -+ * 18. Wait for PHY power up sequence to finish by checking output ports ++ * 16. Wait for PHY power up sequence to finish by checking output ports + * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. + */ + ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, @@ -914,12 +903,12 @@ Signed-off-by: Marek Behún + } + + /* -+ * 19. Set COMPHY input port PIN_TX_IDLE=0 ++ * 17. Set COMPHY input port PIN_TX_IDLE=0 + */ + comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT); + + /* -+ * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To ++ * 18. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To + * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the + * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to + * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please @@ -941,13 +930,11 @@ Signed-off-by: Marek Behún + ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, + PHY_RX_INIT_DONE_BIT, + COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); -+ if (ret) { ++ if (ret) + dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n", + lane->id); -+ return ret; -+ } + -+ return 0; ++ return ret; } -static int mvebu_a3700_comphy_get_fw_mode(int lane, @@ -1107,12 +1094,10 @@ Signed-off-by: Marek Behún + + ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, + COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); -+ if (ret) { ++ if (ret) + dev_err(lane->dev, "Failed to lock USB3 PLL\n"); -+ return ret; -+ } + -+ return 0; ++ return ret; +} + +static int @@ -1197,21 +1182,10 @@ Signed-off-by: Marek Behún + + ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, + COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); -+ if (ret) { ++ if (ret) + dev_err(lane->dev, "Failed to lock PCIE PLL\n"); -+ return ret; -+ } + -+ return 0; -+} -+ -+static void -+mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane) -+{ -+ /* -+ * Currently the USB3 MAC sets the USB3 PHY to low state, so we do not -+ * need to power off USB3 PHY again. -+ */ ++ return ret; +} + +static void @@ -1285,7 +1259,7 @@ Signed-off-by: Marek Behún enum phy_mode mode, int submode) { -@@ -122,7 +1170,7 @@ static int mvebu_a3700_comphy_get_fw_mod +@@ -122,7 +1141,7 @@ static int mvebu_a3700_comphy_get_fw_mod /* Unused PHY mux value is 0x0 */ if (mode == PHY_MODE_INVALID) @@ -1294,7 +1268,7 @@ Signed-off-by: Marek Behún for (i = 0; i < n; i++) { if (mvebu_a3700_comphy_modes[i].lane == lane && -@@ -132,27 +1180,30 @@ static int mvebu_a3700_comphy_get_fw_mod +@@ -132,27 +1151,30 @@ static int mvebu_a3700_comphy_get_fw_mod } if (i == n) @@ -1310,10 +1284,10 @@ Signed-off-by: Marek Behún { struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); - int fw_mode; -- + - if (submode == PHY_INTERFACE_MODE_1000BASEX) - submode = PHY_INTERFACE_MODE_SGMII; - +- - fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, mode, - submode); - if (fw_mode < 0) { @@ -1335,7 +1309,7 @@ Signed-off-by: Marek Behún /* Just remember the mode, ->power_on() will do the real setup */ lane->mode = mode; lane->submode = submode; -@@ -163,76 +1214,68 @@ static int mvebu_a3700_comphy_set_mode(s +@@ -163,76 +1185,77 @@ static int mvebu_a3700_comphy_set_mode(s static int mvebu_a3700_comphy_power_on(struct phy *phy) { struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); @@ -1423,21 +1397,30 @@ Signed-off-by: Marek Behún - return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0); + switch (lane->mode) { + case PHY_MODE_USB_HOST_SS: -+ mvebu_a3700_comphy_usb3_power_off(lane); -+ return 0; ++ /* ++ * The USB3 MAC sets the USB3 PHY to low state, so we do not ++ * need to power off USB3 PHY again. ++ */ ++ break; ++ + case PHY_MODE_SATA: + mvebu_a3700_comphy_sata_power_off(lane); -+ return 0; ++ break; ++ + case PHY_MODE_ETHERNET: + mvebu_a3700_comphy_ethernet_power_off(lane); -+ return 0; ++ break; ++ + case PHY_MODE_PCIE: + mvebu_a3700_comphy_pcie_power_off(lane); -+ return 0; ++ break; ++ + default: + dev_err(lane->dev, "invalid COMPHY mode\n"); + return -EINVAL; + } ++ ++ return 0; } static const struct phy_ops mvebu_a3700_comphy_ops = { @@ -1447,7 +1430,7 @@ Signed-off-by: Marek Behún .set_mode = mvebu_a3700_comphy_set_mode, .owner = THIS_MODULE, }; -@@ -256,13 +1299,75 @@ static struct phy *mvebu_a3700_comphy_xl +@@ -256,13 +1279,75 @@ static struct phy *mvebu_a3700_comphy_xl return ERR_PTR(-EINVAL); } @@ -1523,7 +1506,7 @@ Signed-off-by: Marek Behún for_each_available_child_of_node(pdev->dev.of_node, child) { struct mvebu_a3700_comphy_lane *lane; -@@ -277,7 +1382,7 @@ static int mvebu_a3700_comphy_probe(stru +@@ -277,7 +1362,7 @@ static int mvebu_a3700_comphy_probe(stru continue; } @@ -1532,7 +1515,7 @@ Signed-off-by: Marek Behún dev_err(&pdev->dev, "invalid 'reg' property\n"); continue; } -@@ -295,11 +1400,21 @@ static int mvebu_a3700_comphy_probe(stru +@@ -295,15 +1380,26 @@ static int mvebu_a3700_comphy_probe(stru return PTR_ERR(phy); } @@ -1554,7 +1537,12 @@ Signed-off-by: Marek Behún } provider = devm_of_phy_provider_register(&pdev->dev, -@@ -323,5 +1438,7 @@ static struct platform_driver mvebu_a370 + mvebu_a3700_comphy_xlate); ++ + return PTR_ERR_OR_ZERO(provider); + } + +@@ -323,5 +1419,7 @@ static struct platform_driver mvebu_a370 module_platform_driver(mvebu_a3700_comphy_driver); MODULE_AUTHOR("Miquèl Raynal "); diff --git a/target/linux/generic/pending-5.15/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch b/target/linux/generic/backport-5.15/345-v5.17-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch similarity index 78% rename from target/linux/generic/pending-5.15/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch rename to target/linux/generic/backport-5.15/345-v5.17-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch index 33203a154d..03b6a5754d 100644 --- a/target/linux/generic/pending-5.15/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch +++ b/target/linux/generic/backport-5.15/345-v5.17-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch @@ -1,8 +1,8 @@ -From 66c51c39fd4bf05e99debf0e71de5704231c57dc Mon Sep 17 00:00:00 2001 +From 73a78b6130d9e13daca22b86ad52f063b9403e03 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:26:26 +0200 -Subject: [PATCH] arm64: dts: marvell: armada-37xx: Add xtal clock to comphy - node +Date: Wed, 8 Dec 2021 03:40:35 +0100 +Subject: [PATCH 1/1] arm64: dts: marvell: armada-37xx: Add xtal clock to + comphy node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -14,6 +14,7 @@ xtal rate (which, as far as we know, is used by all the existing boards). Signed-off-by: Pali Rohár Signed-off-by: Marek Behún +Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/generic/pending-5.15/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch b/target/linux/generic/backport-5.15/346-v5.18-01-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch similarity index 84% rename from target/linux/generic/pending-5.15/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch rename to target/linux/generic/backport-5.15/346-v5.18-01-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch index 3c994d2548..b254e7c0b3 100644 --- a/target/linux/generic/pending-5.15/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch +++ b/target/linux/generic/backport-5.15/346-v5.18-01-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch @@ -1,8 +1,8 @@ -From 750bb44dbbe9dfb4ba3e1f8a746b831b39ba3cd9 Mon Sep 17 00:00:00 2001 +From ee995101fde67f85a3cd4c74f4f92fc4592e726b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:35:57 +0200 -Subject: [PATCH] Revert "ata: ahci: mvebu: Make SATA PHY optional for Armada - 3720" +Date: Thu, 3 Feb 2022 22:44:42 +0100 +Subject: [PATCH 1/3] Revert "ata: ahci: mvebu: Make SATA PHY optional for + Armada 3720" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -20,6 +20,9 @@ remove this flag completely. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Acked-by: Miquel Raynal +Acked-by: Damien Le Moal +Link: https://lore.kernel.org/r/20220203214444.1508-4-kabel@kernel.org +Signed-off-by: Vinod Koul --- drivers/ata/ahci.h | 2 -- drivers/ata/ahci_mvebu.c | 2 +- diff --git a/target/linux/generic/pending-5.15/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch b/target/linux/generic/backport-5.15/346-v5.18-02-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch similarity index 92% rename from target/linux/generic/pending-5.15/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch rename to target/linux/generic/backport-5.15/346-v5.18-02-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch index b8a3e880ce..1e8afb7bbf 100644 --- a/target/linux/generic/pending-5.15/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch +++ b/target/linux/generic/backport-5.15/346-v5.18-02-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch @@ -1,8 +1,8 @@ -From 9f0dfb279b1dd505d5e10b10e4a78a62030978d8 Mon Sep 17 00:00:00 2001 +From 8e10548f7f4814e530857d2049d6af6bc78add53 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:40:06 +0200 -Subject: [PATCH] Revert "usb: host: xhci: mvebu: make USB 3.0 PHY optional for - Armada 3720" +Date: Thu, 3 Feb 2022 22:44:43 +0100 +Subject: [PATCH 2/3] Revert "usb: host: xhci: mvebu: make USB 3.0 PHY optional + for Armada 3720" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -22,6 +22,9 @@ remove this callback completely. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Acked-by: Miquel Raynal +Acked-by: Greg Kroah-Hartman +Link: https://lore.kernel.org/r/20220203214444.1508-5-kabel@kernel.org +Signed-off-by: Vinod Koul --- drivers/usb/host/xhci-mvebu.c | 42 ----------------------------------- drivers/usb/host/xhci-mvebu.h | 6 ----- diff --git a/target/linux/generic/pending-5.15/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch b/target/linux/generic/backport-5.15/346-v5.18-03-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch similarity index 67% rename from target/linux/generic/pending-5.15/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch rename to target/linux/generic/backport-5.15/346-v5.18-03-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch index 76b39452ad..fcfb02d35a 100644 --- a/target/linux/generic/pending-5.15/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch +++ b/target/linux/generic/backport-5.15/346-v5.18-03-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch @@ -1,8 +1,8 @@ -From 9a352062b7e3857742389dff6f64393481dc755e Mon Sep 17 00:00:00 2001 +From 9a4556dad7bd0a6b8339cb72e169f5c76f2af6f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:37:05 +0200 -Subject: [PATCH] Revert "PCI: aardvark: Fix initialization with old Marvell's - Arm Trusted Firmware" +Date: Thu, 3 Feb 2022 22:44:44 +0100 +Subject: [PATCH 3/3] Revert "PCI: aardvark: Fix initialization with old + Marvell's Arm Trusted Firmware" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -17,13 +17,16 @@ So remove dead code which handles -EOPNOTSUPP return value. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Acked-by: Miquel Raynal +Acked-by: Lorenzo Pieralisi +Link: https://lore.kernel.org/r/20220203214444.1508-6-kabel@kernel.org +Signed-off-by: Vinod Koul --- drivers/pci/controller/pci-aardvark.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c -@@ -1631,9 +1631,7 @@ static int advk_pcie_enable_phy(struct a +@@ -1642,9 +1642,7 @@ static int advk_pcie_enable_phy(struct a } ret = phy_power_on(pcie->phy); diff --git a/target/linux/generic/backport-5.15/347-v6.0-phy-marvell-phy-mvebu-a3700-comphy-Remove-broken-res.patch b/target/linux/generic/backport-5.15/347-v6.0-phy-marvell-phy-mvebu-a3700-comphy-Remove-broken-res.patch new file mode 100644 index 0000000000..a2c897b7a9 --- /dev/null +++ b/target/linux/generic/backport-5.15/347-v6.0-phy-marvell-phy-mvebu-a3700-comphy-Remove-broken-res.patch @@ -0,0 +1,194 @@ +From 0a6fc70d76bddf98278af2ac000379c82aec8f11 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Mon, 29 Aug 2022 10:30:46 +0200 +Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Remove broken reset + support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Reset support for SATA PHY is somehow broken and after calling it, kernel +is not able to detect and initialize SATA disk Samsung SSD 850 EMT0 [1]. + +Reset support was introduced in commit 934337080c6c ("phy: marvell: +phy-mvebu-a3700-comphy: Add native kernel implementation") as part of +complete rewrite of this driver. v1 patch series of that commit [2] did +not contain reset support and was tested that is working fine with +Ethernet, SATA and USB PHYs without issues too. + +So for now remove broken reset support and change implementation of +power_off callback to power off all functions on specified lane (and not +only selected function) because during startup kernel does not know which +function was selected and configured by bootloader. Same logic was used +also in v1 patch series of that commit. + +This change fixes issues with initialization of SATA disk Samsung SSD 850 +and disk is working again, like before mentioned commit. + +Once problem with PHY reset callback is solved its functionality could be +re-introduced. But for now it is unknown why it does not work. + +[1] - https://lore.kernel.org/r/20220531124159.3e4lgn2v462irbtz@shindev/ +[2] - https://lore.kernel.org/r/20211028184242.22105-1-kabel@kernel.org/ + +Reported-by: Shinichiro Kawasaki +Fixes: 934337080c6c ("phy: marvell: phy-mvebu-a3700-comphy: Add native kernel implementation") +Cc: stable@vger.kernel.org # v5.18+ +Signed-off-by: Pali Rohár +Tested-by: Shinichiro Kawasaki +Link: https://lore.kernel.org/r/20220829083046.15082-1-pali@kernel.org +Signed-off-by: Vinod Koul +--- + drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 87 ++++---------------- + 1 file changed, 17 insertions(+), 70 deletions(-) + +--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c ++++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c +@@ -274,7 +274,6 @@ struct mvebu_a3700_comphy_lane { + int submode; + bool invert_tx; + bool invert_rx; +- bool needs_reset; + }; + + struct gbe_phy_init_data_fix { +@@ -1097,40 +1096,12 @@ mvebu_a3700_comphy_pcie_power_off(struct + 0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); + } + +-static int mvebu_a3700_comphy_reset(struct phy *phy) ++static void mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane) + { +- struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); +- u16 mask, data; +- +- dev_dbg(lane->dev, "resetting lane %d\n", lane->id); +- +- /* COMPHY reset for internal logic */ +- comphy_lane_reg_set(lane, COMPHY_SFT_RESET, +- SFT_RST_NO_REG, SFT_RST_NO_REG); +- +- /* COMPHY register reset (cleared automatically) */ +- comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST); +- +- /* PIPE soft and register reset */ +- data = PIPE_SOFT_RESET | PIPE_REG_RESET; +- mask = data; +- comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); +- +- /* Release PIPE register reset */ +- comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, +- 0x0, PIPE_REG_RESET); +- +- /* Reset SB configuration register (only for lanes 0 and 1) */ +- if (lane->id == 0 || lane->id == 1) { +- u32 mask, data; +- +- data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | +- PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT; +- mask = data | PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT; +- comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); +- } +- +- return 0; ++ /* ++ * The USB3 MAC sets the USB3 PHY to low state, so we do not ++ * need to power off USB3 PHY again. ++ */ + } + + static bool mvebu_a3700_comphy_check_mode(int lane, +@@ -1171,10 +1142,6 @@ static int mvebu_a3700_comphy_set_mode(s + (lane->mode != mode || lane->submode != submode)) + return -EBUSY; + +- /* If changing mode, ensure reset is called */ +- if (lane->mode != PHY_MODE_INVALID && lane->mode != mode) +- lane->needs_reset = true; +- + /* Just remember the mode, ->power_on() will do the real setup */ + lane->mode = mode; + lane->submode = submode; +@@ -1185,7 +1152,6 @@ static int mvebu_a3700_comphy_set_mode(s + static int mvebu_a3700_comphy_power_on(struct phy *phy) + { + struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); +- int ret; + + if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode, + lane->submode)) { +@@ -1193,14 +1159,6 @@ static int mvebu_a3700_comphy_power_on(s + return -EINVAL; + } + +- if (lane->needs_reset) { +- ret = mvebu_a3700_comphy_reset(phy); +- if (ret) +- return ret; +- +- lane->needs_reset = false; +- } +- + switch (lane->mode) { + case PHY_MODE_USB_HOST_SS: + dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id); +@@ -1224,38 +1182,28 @@ static int mvebu_a3700_comphy_power_off( + { + struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); + +- switch (lane->mode) { +- case PHY_MODE_USB_HOST_SS: +- /* +- * The USB3 MAC sets the USB3 PHY to low state, so we do not +- * need to power off USB3 PHY again. +- */ +- break; +- +- case PHY_MODE_SATA: +- mvebu_a3700_comphy_sata_power_off(lane); +- break; +- +- case PHY_MODE_ETHERNET: ++ switch (lane->id) { ++ case 0: ++ mvebu_a3700_comphy_usb3_power_off(lane); + mvebu_a3700_comphy_ethernet_power_off(lane); +- break; +- +- case PHY_MODE_PCIE: ++ return 0; ++ case 1: + mvebu_a3700_comphy_pcie_power_off(lane); +- break; +- ++ mvebu_a3700_comphy_ethernet_power_off(lane); ++ return 0; ++ case 2: ++ mvebu_a3700_comphy_usb3_power_off(lane); ++ mvebu_a3700_comphy_sata_power_off(lane); ++ return 0; + default: + dev_err(lane->dev, "invalid COMPHY mode\n"); + return -EINVAL; + } +- +- return 0; + } + + static const struct phy_ops mvebu_a3700_comphy_ops = { + .power_on = mvebu_a3700_comphy_power_on, + .power_off = mvebu_a3700_comphy_power_off, +- .reset = mvebu_a3700_comphy_reset, + .set_mode = mvebu_a3700_comphy_set_mode, + .owner = THIS_MODULE, + }; +@@ -1393,8 +1341,7 @@ static int mvebu_a3700_comphy_probe(stru + * To avoid relying on the bootloader/firmware configuration, + * power off all comphys. + */ +- mvebu_a3700_comphy_reset(phy); +- lane->needs_reset = false; ++ mvebu_a3700_comphy_power_off(phy); + } + + provider = devm_of_phy_provider_register(&pdev->dev, diff --git a/target/linux/generic/pending-5.15/731-net-dsa-mt7530-add-support-for-in-band-link-status.patch b/target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch similarity index 63% rename from target/linux/generic/pending-5.15/731-net-dsa-mt7530-add-support-for-in-band-link-status.patch rename to target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch index 8196f19540..7bb6530266 100644 --- a/target/linux/generic/pending-5.15/731-net-dsa-mt7530-add-support-for-in-band-link-status.patch +++ b/target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch @@ -1,37 +1,25 @@ -From 8e18c5fef75debfae3531fbd6901f3bf317d91ed Mon Sep 17 00:00:00 2001 +From e19de30d20809af3221ef8a2648b8a8a52e02d90 Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Fri, 9 Sep 2022 04:28:43 +0100 -Subject: [PATCH] net: dsa: mt7530: add support for in-band link status -To: linux-mediatek@lists.infradead.org, - netdev@vger.kernel.org -Cc: Russell King , - Sean Wang , - Landen Chao , - DENG Qingfang , - Andrew Lunn , - Vivien Didelot , - Florian Fainelli , - Vladimir Oltean , - David S. Miller , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Matthias Brugger , - Philipp Zabel +Date: Wed, 21 Sep 2022 01:23:14 +0100 +Subject: [PATCH 1/1] net: dsa: mt7530: add support for in-band link status Read link status from SGMII PCS for in-band managed 2500Base-X and 1000Base-X connection on a MAC port of the MT7531. This is needed to get the SFP cage working which is connected to SGMII interface of port 5 of the MT7531 switch IC on the Bananapi BPi-R3 board. +While at it also handle an_complete for both the autoneg and the +non-autoneg codepath. Signed-off-by: Daniel Golle +Signed-off-by: David S. Miller --- - drivers/net/dsa/mt7530.c | 48 +++++++++++++++++++++++++++++----------- - 1 file changed, 35 insertions(+), 13 deletions(-) + drivers/net/dsa/mt7530.c | 50 +++++++++++++++++++++++++++++----------- + drivers/net/dsa/mt7530.h | 1 + + 2 files changed, 38 insertions(+), 13 deletions(-) --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2703,9 +2703,6 @@ mt7531_mac_config(struct dsa_switch *ds, +@@ -2699,9 +2699,6 @@ mt7531_mac_config(struct dsa_switch *ds, case PHY_INTERFACE_MODE_NA: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: @@ -41,7 +29,7 @@ Signed-off-by: Daniel Golle return mt7531_sgmii_setup_mode_force(priv, port, interface); default: return -EINVAL; -@@ -2781,13 +2778,6 @@ unsupported: +@@ -2777,13 +2774,6 @@ unsupported: return; } @@ -55,7 +43,7 @@ Signed-off-by: Daniel Golle mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); mcr_new = mcr_cur; mcr_new &= ~PMCR_LINK_SETTINGS_MASK; -@@ -2924,6 +2914,9 @@ static void mt753x_phylink_get_caps(stru +@@ -2920,6 +2910,9 @@ static void mt753x_phylink_get_caps(stru config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; @@ -65,7 +53,15 @@ Signed-off-by: Daniel Golle /* This driver does not make use of the speed, duplex, pause or the * advertisement in its mac_config, so it is safe to mark this driver * as non-legacy. -@@ -3019,16 +3012,43 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 +@@ -2985,6 +2978,7 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 + + status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); + state->link = !!(status & MT7531_SGMII_LINK_STATUS); ++ state->an_complete = !!(status & MT7531_SGMII_AN_COMPLETE); + if (state->interface == PHY_INTERFACE_MODE_SGMII && + (status & MT7531_SGMII_AN_ENABLE)) { + val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); +@@ -3015,16 +3009,44 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 return 0; } @@ -80,13 +76,15 @@ Signed-off-by: Daniel Golle + if (!state->link) + return; + ++ state->an_complete = state->link; ++ + if (state->interface == PHY_INTERFACE_MODE_2500BASEX) + state->speed = SPEED_2500; + else + state->speed = SPEED_1000; + + state->duplex = DUPLEX_FULL; -+ state->pause = 0; ++ state->pause = MLO_PAUSE_NONE; +} + static void mt7531_pcs_get_state(struct phylink_pcs *pcs, @@ -94,7 +92,6 @@ Signed-off-by: Daniel Golle { struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; int port = pcs_to_mt753x_pcs(pcs)->port; -+ unsigned int val; - if (state->interface == PHY_INTERFACE_MODE_SGMII) + if (state->interface == PHY_INTERFACE_MODE_SGMII) { @@ -112,7 +109,7 @@ Signed-off-by: Daniel Golle } static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, -@@ -3069,6 +3089,8 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3065,6 +3087,8 @@ mt753x_setup(struct dsa_switch *ds) priv->pcs[i].pcs.ops = priv->info->pcs_ops; priv->pcs[i].priv = priv; priv->pcs[i].port = i; @@ -121,3 +118,13 @@ Signed-off-by: Daniel Golle } ret = priv->info->sw_setup(ds); +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -373,6 +373,7 @@ enum mt7530_vlan_port_acc_frm { + #define MT7531_SGMII_LINK_STATUS BIT(18) + #define MT7531_SGMII_AN_ENABLE BIT(12) + #define MT7531_SGMII_AN_RESTART BIT(9) ++#define MT7531_SGMII_AN_COMPLETE BIT(21) + + /* Register for SGMII PCS_SPPED_ABILITY */ + #define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08) diff --git a/target/linux/generic/backport-5.15/783-v6.1-net-sfp-re-implement-soft-state-polling-setup.patch b/target/linux/generic/backport-5.15/783-v6.1-net-sfp-re-implement-soft-state-polling-setup.patch new file mode 100644 index 0000000000..6f69b7ddfe --- /dev/null +++ b/target/linux/generic/backport-5.15/783-v6.1-net-sfp-re-implement-soft-state-polling-setup.patch @@ -0,0 +1,98 @@ +From 8475c4b70b040f9d8cbc308100f2c4d865f810b3 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 13 Sep 2022 20:06:27 +0100 +Subject: [PATCH 1/1] net: sfp: re-implement soft state polling setup + +Re-implement the decision making for soft state polling. Instead of +generating the soft state mask in sfp_soft_start_poll() by looking at +which GPIOs are available, record their availability in +sfp_sm_mod_probe() in sfp->state_hw_mask. + +This will then allow us to clear bits in sfp->state_hw_mask in module +specific quirks when the hardware signals should not be used, thereby +allowing us to switch to using the software state polling. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/sfp.c | 38 ++++++++++++++++++++++++++------------ + 1 file changed, 26 insertions(+), 12 deletions(-) + +--- a/drivers/net/phy/sfp.c ++++ b/drivers/net/phy/sfp.c +@@ -234,6 +234,7 @@ struct sfp { + bool need_poll; + + struct mutex st_mutex; /* Protects state */ ++ unsigned int state_hw_mask; + unsigned int state_soft_mask; + unsigned int state; + struct delayed_work poll; +@@ -499,17 +500,18 @@ static void sfp_soft_set_state(struct sf + static void sfp_soft_start_poll(struct sfp *sfp) + { + const struct sfp_eeprom_id *id = &sfp->id; ++ unsigned int mask = 0; + + sfp->state_soft_mask = 0; +- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_DISABLE && +- !sfp->gpio[GPIO_TX_DISABLE]) +- sfp->state_soft_mask |= SFP_F_TX_DISABLE; +- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_FAULT && +- !sfp->gpio[GPIO_TX_FAULT]) +- sfp->state_soft_mask |= SFP_F_TX_FAULT; +- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_RX_LOS && +- !sfp->gpio[GPIO_LOS]) +- sfp->state_soft_mask |= SFP_F_LOS; ++ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_DISABLE) ++ mask |= SFP_F_TX_DISABLE; ++ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_FAULT) ++ mask |= SFP_F_TX_FAULT; ++ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_RX_LOS) ++ mask |= SFP_F_LOS; ++ ++ // Poll the soft state for hardware pins we want to ignore ++ sfp->state_soft_mask = ~sfp->state_hw_mask & mask; + + if (sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT) && + !sfp->need_poll) +@@ -523,10 +525,11 @@ static void sfp_soft_stop_poll(struct sf + + static unsigned int sfp_get_state(struct sfp *sfp) + { +- unsigned int state = sfp->get_state(sfp); ++ unsigned int soft = sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT); ++ unsigned int state; + +- if (state & SFP_F_PRESENT && +- sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT)) ++ state = sfp->get_state(sfp) & sfp->state_hw_mask; ++ if (state & SFP_F_PRESENT && soft) + state |= sfp_soft_get_state(sfp); + + return state; +@@ -1940,6 +1943,15 @@ static int sfp_sm_mod_probe(struct sfp * + if (ret < 0) + return ret; + ++ /* Initialise state bits to use from hardware */ ++ sfp->state_hw_mask = SFP_F_PRESENT; ++ if (sfp->gpio[GPIO_TX_DISABLE]) ++ sfp->state_hw_mask |= SFP_F_TX_DISABLE; ++ if (sfp->gpio[GPIO_TX_FAULT]) ++ sfp->state_hw_mask |= SFP_F_TX_FAULT; ++ if (sfp->gpio[GPIO_LOS]) ++ sfp->state_hw_mask |= SFP_F_LOS; ++ + if (!memcmp(id.base.vendor_name, "ALCATELLUCENT ", 16) && + !memcmp(id.base.vendor_pn, "3FE46541AA ", 16)) + sfp->module_t_start_up = T_START_UP_BAD_GPON; +@@ -2565,6 +2577,8 @@ static int sfp_probe(struct platform_dev + return PTR_ERR(sfp->gpio[i]); + } + ++ sfp->state_hw_mask = SFP_F_PRESENT; ++ + sfp->get_state = sfp_gpio_get_state; + sfp->set_state = sfp_gpio_set_state; + diff --git a/target/linux/generic/pending-5.15/770-net-sfp-move-quirk-handling-into-sfp.c.patch b/target/linux/generic/backport-5.15/784-v6.1-net-sfp-move-quirk-handling-into-sfp.c.patch similarity index 94% rename from target/linux/generic/pending-5.15/770-net-sfp-move-quirk-handling-into-sfp.c.patch rename to target/linux/generic/backport-5.15/784-v6.1-net-sfp-move-quirk-handling-into-sfp.c.patch index 8d43ccb3e9..e5f8031636 100644 --- a/target/linux/generic/pending-5.15/770-net-sfp-move-quirk-handling-into-sfp.c.patch +++ b/target/linux/generic/backport-5.15/784-v6.1-net-sfp-move-quirk-handling-into-sfp.c.patch @@ -1,13 +1,14 @@ -From a4648a1957cd79bc389538aa0472db39a56e3df6 Mon Sep 17 00:00:00 2001 +From 23571c7b96437483d28a990c906cc81f5f66374e Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" -Date: Fri, 26 Aug 2022 08:43:30 +0100 -Subject: [PATCH 1/6] net: sfp: move quirk handling into sfp.c +Date: Tue, 13 Sep 2022 20:06:32 +0100 +Subject: [PATCH 1/1] net: sfp: move quirk handling into sfp.c We need to handle more quirks than just those which affect the link modes of the module. Move the quirk lookup into sfp.c, and pass the quirk to sfp-bus.c Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski --- drivers/net/phy/sfp-bus.c | 98 ++------------------------------------- drivers/net/phy/sfp.c | 94 ++++++++++++++++++++++++++++++++++++- @@ -141,7 +142,7 @@ Signed-off-by: Russell King (Oracle) ret = ops->module_insert(bus->upstream, id); --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c -@@ -252,6 +252,8 @@ struct sfp { +@@ -253,6 +253,8 @@ struct sfp { unsigned int module_t_start_up; bool tx_fault_ignore; @@ -150,7 +151,7 @@ Signed-off-by: Russell King (Oracle) #if IS_ENABLED(CONFIG_HWMON) struct sfp_diag diag; struct delayed_work hwmon_probe; -@@ -308,6 +310,93 @@ static const struct of_device_id sfp_of_ +@@ -309,6 +311,93 @@ static const struct of_device_id sfp_of_ }; MODULE_DEVICE_TABLE(of, sfp_of_match); @@ -244,7 +245,7 @@ Signed-off-by: Russell King (Oracle) static unsigned long poll_jiffies; static unsigned int sfp_gpio_get_state(struct sfp *sfp) -@@ -1952,6 +2041,8 @@ static int sfp_sm_mod_probe(struct sfp * +@@ -1964,6 +2053,8 @@ static int sfp_sm_mod_probe(struct sfp * else sfp->tx_fault_ignore = false; @@ -253,7 +254,7 @@ Signed-off-by: Russell King (Oracle) return 0; } -@@ -2063,7 +2154,8 @@ static void sfp_sm_module(struct sfp *sf +@@ -2075,7 +2166,8 @@ static void sfp_sm_module(struct sfp *sf break; /* Report the module insertion to the upstream device */ diff --git a/target/linux/generic/pending-5.15/771-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch b/target/linux/generic/backport-5.15/785-v6.1-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch similarity index 76% rename from target/linux/generic/pending-5.15/771-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch rename to target/linux/generic/backport-5.15/785-v6.1-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch index f285561ebb..aa3112e585 100644 --- a/target/linux/generic/pending-5.15/771-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch +++ b/target/linux/generic/backport-5.15/785-v6.1-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch @@ -1,12 +1,13 @@ -From 21fdd8281de3022aee35dd5bfccc892bd46529a3 Mon Sep 17 00:00:00 2001 +From 275416754e9a262c97a1ad6f806a4bc6e0464aa2 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" -Date: Fri, 26 Aug 2022 08:43:35 +0100 -Subject: [PATCH 2/6] net: sfp: move Alcatel Lucent 3FE46541AA fixup +Date: Tue, 13 Sep 2022 20:06:37 +0100 +Subject: [PATCH 1/1] net: sfp: move Alcatel Lucent 3FE46541AA fixup Add a new fixup mechanism to the SFP quirks, and use it for this module. Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski --- drivers/net/phy/sfp.c | 14 +++++++++----- drivers/net/phy/sfp.h | 1 + @@ -14,7 +15,7 @@ Signed-off-by: Russell King (Oracle) --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c -@@ -310,6 +310,11 @@ static const struct of_device_id sfp_of_ +@@ -311,6 +311,11 @@ static const struct of_device_id sfp_of_ }; MODULE_DEVICE_TABLE(of, sfp_of_match); @@ -26,7 +27,7 @@ Signed-off-by: Russell King (Oracle) static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, unsigned long *modes) { -@@ -340,6 +345,7 @@ static const struct sfp_quirk sfp_quirks +@@ -341,6 +346,7 @@ static const struct sfp_quirk sfp_quirks .vendor = "ALCATELLUCENT", .part = "3FE46541AA", .modes = sfp_quirk_2500basex, @@ -34,9 +35,9 @@ Signed-off-by: Russell King (Oracle) }, { // Huawei MA5671A can operate at 2500base-X, but report 1.2GBd // NRZ in their EEPROM -@@ -2029,11 +2035,7 @@ static int sfp_sm_mod_probe(struct sfp * - if (ret < 0) - return ret; +@@ -2041,11 +2047,7 @@ static int sfp_sm_mod_probe(struct sfp * + if (sfp->gpio[GPIO_LOS]) + sfp->state_hw_mask |= SFP_F_LOS; - if (!memcmp(id.base.vendor_name, "ALCATELLUCENT ", 16) && - !memcmp(id.base.vendor_pn, "3FE46541AA ", 16)) @@ -47,7 +48,7 @@ Signed-off-by: Russell King (Oracle) if (!memcmp(id.base.vendor_name, "HUAWEI ", 16) && !memcmp(id.base.vendor_pn, "MA5671A ", 16)) -@@ -2042,6 +2044,8 @@ static int sfp_sm_mod_probe(struct sfp * +@@ -2054,6 +2056,8 @@ static int sfp_sm_mod_probe(struct sfp * sfp->tx_fault_ignore = false; sfp->quirk = sfp_lookup_quirk(&id); diff --git a/target/linux/generic/pending-5.15/772-net-sfp-move-Huawei-MA5671A-fixup.patch b/target/linux/generic/backport-5.15/786-v6.1-net-sfp-move-Huawei-MA5671A-fixup.patch similarity index 74% rename from target/linux/generic/pending-5.15/772-net-sfp-move-Huawei-MA5671A-fixup.patch rename to target/linux/generic/backport-5.15/786-v6.1-net-sfp-move-Huawei-MA5671A-fixup.patch index dfd08af671..14b0f9b8c3 100644 --- a/target/linux/generic/pending-5.15/772-net-sfp-move-Huawei-MA5671A-fixup.patch +++ b/target/linux/generic/backport-5.15/786-v6.1-net-sfp-move-Huawei-MA5671A-fixup.patch @@ -1,18 +1,19 @@ -From 4c9d8c654827ef42da702c5b6c3392e8ac0bc60a Mon Sep 17 00:00:00 2001 +From 5029be761161374a3624aa7b4670174c35449bf5 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" -Date: Fri, 26 Aug 2022 08:43:40 +0100 -Subject: [PATCH 3/6] net: sfp: move Huawei MA5671A fixup +Date: Tue, 13 Sep 2022 20:06:42 +0100 +Subject: [PATCH 1/1] net: sfp: move Huawei MA5671A fixup Move this module over to the new fixup mechanism. Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski --- drivers/net/phy/sfp.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c -@@ -315,6 +315,11 @@ static void sfp_fixup_long_startup(struc +@@ -316,6 +316,11 @@ static void sfp_fixup_long_startup(struc sfp->module_t_start_up = T_START_UP_BAD_GPON; } @@ -24,7 +25,7 @@ Signed-off-by: Russell King (Oracle) static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, unsigned long *modes) { -@@ -352,6 +357,7 @@ static const struct sfp_quirk sfp_quirks +@@ -353,6 +358,7 @@ static const struct sfp_quirk sfp_quirks .vendor = "HUAWEI", .part = "MA5671A", .modes = sfp_quirk_2500basex, @@ -32,7 +33,7 @@ Signed-off-by: Russell King (Oracle) }, { // Lantech 8330-262D-E can operate at 2500base-X, but // incorrectly report 2500MBd NRZ in their EEPROM -@@ -2037,11 +2043,7 @@ static int sfp_sm_mod_probe(struct sfp * +@@ -2049,11 +2055,7 @@ static int sfp_sm_mod_probe(struct sfp * sfp->module_t_start_up = T_START_UP; diff --git a/target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch b/target/linux/generic/backport-5.15/787-v6.1-net-sfp-add-support-for-HALNy-GPON-SFP.patch similarity index 60% rename from target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch rename to target/linux/generic/backport-5.15/787-v6.1-net-sfp-add-support-for-HALNy-GPON-SFP.patch index 85c1d5b203..0c65de5ab8 100644 --- a/target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch +++ b/target/linux/generic/backport-5.15/787-v6.1-net-sfp-add-support-for-HALNy-GPON-SFP.patch @@ -1,18 +1,19 @@ -From 43ac680124bc57951a6d0356b41498c2324388bf Mon Sep 17 00:00:00 2001 +From 73472c830eae5fce2107f7f086f1e6827d215caf Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" -Date: Fri, 26 Aug 2022 08:43:45 +0100 -Subject: [PATCH 4/6] net: sfp: add support for HALNy GPON SFP +Date: Tue, 13 Sep 2022 20:06:48 +0100 +Subject: [PATCH 1/1] net: sfp: add support for HALNy GPON SFP Add a quirk for the HALNy HL-GSFP module, which appears to have an -inverted RX_LOS signal, and possibly uses TX_FAULT as an inverted -host-link status signal. As we can't be certain about the modules -use of TX_FAULT, we ignore it. +inverted RX_LOS signal, and maybe uses TX_FAULT as a serial port +transmit pin. Rather than use these hardware signals, switch to +using software polling for these status signals. Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski --- drivers/net/phy/sfp-bus.c | 2 +- - drivers/net/phy/sfp.c | 29 ++++++++++++++++++++++++++--- - 2 files changed, 27 insertions(+), 4 deletions(-) + drivers/net/phy/sfp.c | 21 ++++++++++++++++++--- + 2 files changed, 19 insertions(+), 4 deletions(-) --- a/drivers/net/phy/sfp-bus.c +++ b/drivers/net/phy/sfp-bus.c @@ -27,31 +28,23 @@ Signed-off-by: Russell King (Oracle) linkmode_or(support, support, modes); --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c -@@ -320,6 +320,23 @@ static void sfp_fixup_ignore_tx_fault(st +@@ -321,6 +321,15 @@ static void sfp_fixup_ignore_tx_fault(st sfp->tx_fault_ignore = true; } -+static void sfp_fixup_inverted_los(struct sfp *sfp) -+{ -+ const __be16 los_inverted = cpu_to_be16(SFP_OPTIONS_LOS_INVERTED); -+ const __be16 los_normal = cpu_to_be16(SFP_OPTIONS_LOS_NORMAL); -+ -+ sfp->id.ext.options &= ~los_normal; -+ sfp->id.ext.options |= los_inverted; -+} -+ +static void sfp_fixup_halny_gsfp(struct sfp *sfp) +{ -+ /* LOS is inverted */ -+ sfp_fixup_inverted_los(sfp); -+ /* TX fault might be inverted, but we don't know for certain. */ -+ sfp_fixup_ignore_tx_fault(sfp); ++ /* Ignore the TX_FAULT and LOS signals on this module. ++ * these are possibly used for other purposes on this ++ * module, e.g. a serial port. ++ */ ++ sfp->state_hw_mask &= ~(SFP_F_TX_FAULT | SFP_F_LOS); +} + static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, unsigned long *modes) { -@@ -352,6 +369,10 @@ static const struct sfp_quirk sfp_quirks +@@ -353,6 +362,10 @@ static const struct sfp_quirk sfp_quirks .modes = sfp_quirk_2500basex, .fixup = sfp_fixup_long_startup, }, { @@ -62,7 +55,7 @@ Signed-off-by: Russell King (Oracle) // Huawei MA5671A can operate at 2500base-X, but report 1.2GBd // NRZ in their EEPROM .vendor = "HUAWEI", -@@ -368,16 +389,18 @@ static const struct sfp_quirk sfp_quirks +@@ -369,16 +382,18 @@ static const struct sfp_quirk sfp_quirks .vendor = "UBNT", .part = "UF-INSTANT", .modes = sfp_quirk_ubnt_uf_instant, diff --git a/target/linux/generic/pending-5.15/781-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch b/target/linux/generic/backport-5.15/788-v6.0-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch similarity index 57% rename from target/linux/generic/pending-5.15/781-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch rename to target/linux/generic/backport-5.15/788-v6.0-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch index 65845ea4c6..27c719b663 100644 --- a/target/linux/generic/pending-5.15/781-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch +++ b/target/linux/generic/backport-5.15/788-v6.0-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch @@ -1,23 +1,8 @@ -From 8743af8a77dd909970462ca578358128cce5d027 Mon Sep 17 00:00:00 2001 +From c9da02bfb1112461e048d3b736afb1873f6f4ccf Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Tue, 27 Sep 2022 15:39:39 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: fix mask of +Date: Tue, 27 Sep 2022 16:30:02 +0100 +Subject: [PATCH 1/1] net: ethernet: mtk_eth_soc: fix mask of RX_DMA_GET_SPORT{,_V2} -To: linux-mediatek@lists.infradead.org, - netdev@vger.kernel.org, - Lorenzo Bianconi -Cc: Sujuan Chen , - Bo Jiao , - Felix Fietkau , - John Crispin , - Sean Wang , - Mark Lee , - David S. Miller , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Matthias Brugger , - Chen Minqiang The bitmasks applied in RX_DMA_GET_SPORT and RX_DMA_GET_SPORT_V2 macros were swapped. Fix that. @@ -26,6 +11,8 @@ Reported-by: Chen Minqiang Fixes: 160d3a9b192985 ("net: ethernet: mtk_eth_soc: introduce MTK_NETSYS_V2 support") Acked-by: Lorenzo Bianconi Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/YzMW+mg9UsaCdKRQ@makrotopia.org +Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/generic/pending-5.15/782-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch b/target/linux/generic/backport-5.15/789-v6.1-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch similarity index 58% rename from target/linux/generic/pending-5.15/782-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch rename to target/linux/generic/backport-5.15/789-v6.1-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch index cc71ec60f3..11465c1c5b 100644 --- a/target/linux/generic/pending-5.15/782-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch +++ b/target/linux/generic/backport-5.15/789-v6.1-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch @@ -1,24 +1,8 @@ -From cd8e1f340c3e571b78952d4ca2c128d183a47cc2 Mon Sep 17 00:00:00 2001 +From ae3ed15da5889263de372ff9df2e83e16acca4cb Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Wed, 28 Sep 2022 02:17:02 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: fix state in +Date: Fri, 30 Sep 2022 01:56:53 +0100 +Subject: [PATCH 1/1] net: ethernet: mtk_eth_soc: fix state in __mtk_foe_entry_clear -To: linux-mediatek@lists.infradead.org, - netdev@vger.kernel.org, - Lorenzo Bianconi -Cc: Sujuan Chen , - Bo Jiao , - Felix Fietkau , - John Crispin , - Sean Wang , - Mark Lee , - David S. Miller , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Matthias Brugger , - Chen Minqiang , - Thomas Hühn Setting ib1 state to MTK_FOE_STATE_UNBIND in __mtk_foe_entry_clear routine as done by commit 0e80707d94e4c8 ("net: ethernet: mtk_eth_soc: @@ -32,8 +16,10 @@ Tested on MT7622 (Linksys E8450) and MT7986 (BananaPi BPI-R3). Suggested-by: Felix Fietkau Fixes: 0e80707d94e4c8 ("net: ethernet: mtk_eth_soc: fix typo in __mtk_foe_entry_clear") -Fixes: 33fc42de33278 ("net: ethernet: mtk_eth_soc: support creating mac address based offload entries") +Fixes: 33fc42de33278b ("net: ethernet: mtk_eth_soc: support creating mac address based offload entries") Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/YzY+1Yg0FBXcnrtc@makrotopia.org +Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/mediatek/mtk_ppe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/generic/pending-5.15/842-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch b/target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch similarity index 97% rename from target/linux/generic/pending-5.15/842-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch rename to target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch index 05eadcf764..25802be7e3 100644 --- a/target/linux/generic/pending-5.15/842-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch +++ b/target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch @@ -1,7 +1,7 @@ From 078c6a1cbd4cd7496048786beec2e312577bebbf Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Tue, 11 Jan 2022 23:11:32 +0100 -Subject: [PATCH] net: qmi_wwan: add ZTE MF286D modem 19d2:1485 +Subject: [PATCH 1/1] net: qmi_wwan: add ZTE MF286D modem 19d2:1485 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/target/linux/generic/pending-5.15/825-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch b/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch similarity index 86% rename from target/linux/generic/pending-5.15/825-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch rename to target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch index 4f9dfc2755..8957ff8e22 100644 --- a/target/linux/generic/pending-5.15/825-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch +++ b/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch @@ -1,13 +1,7 @@ -From ced9d535126a81a85b022cff1e2fd8e0da46c7ae Mon Sep 17 00:00:00 2001 +From be55622ce673f9692cc15d26d77a050cda42a3d3 Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Fri, 9 Sep 2022 18:25:21 +0100 -Subject: [PATCH] Bluetooth: btusb: Add a new VID/PID 0e8d/0608 for MT7921 -To: linux-mediatek@lists.infradead.org, - linux-bluetooth@vger.kernel.org -Cc: Matthias Brugger , - Luiz Augusto von Dentz , - Johan Hedberg , - Marcel Holtmann +Date: Fri, 9 Sep 2022 21:00:30 +0100 +Subject: [PATCH 1/1] Bluetooth: btusb: Add a new VID/PID 0e8d/0608 for MT7921 Add a new PID/VID 0e8d/0608 for MT7921K chip found on AMD RZ608 module. @@ -53,6 +47,7 @@ E: Ad=8a(I) Atr=03(Int.) MxPS= 64 Ivl=125us E: Ad=0a(O) Atr=03(Int.) MxPS= 64 Ivl=125us Signed-off-by: Daniel Golle +Signed-off-by: Luiz Augusto von Dentz --- drivers/bluetooth/btusb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/linux/generic/config-5.10 b/target/linux/generic/config-5.10 index fb74fd785e..2eb3634fa2 100644 --- a/target/linux/generic/config-5.10 +++ b/target/linux/generic/config-5.10 @@ -992,7 +992,7 @@ CONFIG_CONSTRUCTORS=y # CONFIG_CPU_IDLE_GOV_TEO is not set # CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set # CONFIG_CPU_ISOLATION is not set -CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set # CONFIG_CPU_NO_EFFICIENT_FFS is not set CONFIG_CPU_SW_DOMAIN_PAN=y # CONFIG_CPU_THERMAL is not set diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15 index d321177dbd..bba53d1228 100644 --- a/target/linux/generic/config-5.15 +++ b/target/linux/generic/config-5.15 @@ -1023,7 +1023,7 @@ CONFIG_CONSTRUCTORS=y # CONFIG_CPU_IDLE_GOV_TEO is not set # CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set # CONFIG_CPU_ISOLATION is not set -CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set # CONFIG_CPU_NO_EFFICIENT_FFS is not set CONFIG_CPU_SW_DOMAIN_PAN=y # CONFIG_CPU_THERMAL is not set @@ -1504,6 +1504,7 @@ CONFIG_DQL=y # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_ARMADA is not set # CONFIG_DRM_AST is not set +# CONFIG_DRM_ATMEL_HLCDC is not set # CONFIG_DRM_BOCHS is not set # CONFIG_DRM_CDNS_DSI is not set # CONFIG_DRM_CDNS_MHDP8546 is not set @@ -1930,6 +1931,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FB_ARK is not set # CONFIG_FB_ARMCLCD is not set # CONFIG_FB_ASILIANT is not set +# CONFIG_FB_ATMEL is not set # CONFIG_FB_ATY is not set # CONFIG_FB_ATY128 is not set # CONFIG_FB_AUO_K190X is not set diff --git a/target/linux/ath79/patches-5.10/600-of_net-add-mac-address-ascii-support.patch b/target/linux/generic/hack-5.10/601-of_net-add-mac-address-ascii-support.patch similarity index 95% rename from target/linux/ath79/patches-5.10/600-of_net-add-mac-address-ascii-support.patch rename to target/linux/generic/hack-5.10/601-of_net-add-mac-address-ascii-support.patch index 7f95852c7e..f73e262bba 100644 --- a/target/linux/ath79/patches-5.10/600-of_net-add-mac-address-ascii-support.patch +++ b/target/linux/generic/hack-5.10/601-of_net-add-mac-address-ascii-support.patch @@ -11,7 +11,7 @@ Submitted-by: Yousong Zhou --- a/net/ethernet/eth.c +++ b/net/ethernet/eth.c -@@ -545,6 +545,63 @@ int eth_platform_get_mac_address(struct +@@ -539,6 +539,63 @@ int eth_platform_get_mac_address(struct } EXPORT_SYMBOL(eth_platform_get_mac_address); @@ -75,7 +75,7 @@ Submitted-by: Yousong Zhou /** * Obtain the MAC address from an nvmem cell named 'mac-address' associated * with given device. -@@ -558,19 +615,23 @@ int nvmem_get_mac_address(struct device +@@ -552,19 +609,23 @@ int nvmem_get_mac_address(struct device { struct nvmem_cell *cell; const void *mac; diff --git a/target/linux/ath79/patches-5.15/600-of_net-add-mac-address-ascii-support.patch b/target/linux/generic/hack-5.15/601-of_net-add-mac-address-ascii-support.patch similarity index 95% rename from target/linux/ath79/patches-5.15/600-of_net-add-mac-address-ascii-support.patch rename to target/linux/generic/hack-5.15/601-of_net-add-mac-address-ascii-support.patch index ff22945eb4..83483751f8 100644 --- a/target/linux/ath79/patches-5.15/600-of_net-add-mac-address-ascii-support.patch +++ b/target/linux/generic/hack-5.15/601-of_net-add-mac-address-ascii-support.patch @@ -11,7 +11,7 @@ Submitted-by: Yousong Zhou --- a/net/ethernet/eth.c +++ b/net/ethernet/eth.c -@@ -544,6 +544,63 @@ int eth_platform_get_mac_address(struct +@@ -538,6 +538,63 @@ int eth_platform_get_mac_address(struct } EXPORT_SYMBOL(eth_platform_get_mac_address); @@ -75,7 +75,7 @@ Submitted-by: Yousong Zhou /** * nvmem_get_mac_address - Obtain the MAC address from an nvmem cell named * 'mac-address' associated with given device. -@@ -557,19 +614,23 @@ int nvmem_get_mac_address(struct device +@@ -551,19 +608,23 @@ int nvmem_get_mac_address(struct device { struct nvmem_cell *cell; const void *mac; diff --git a/target/linux/generic/hack-5.15/790-SFP-GE-T-ignore-TX_FAULT.patch b/target/linux/generic/hack-5.15/790-SFP-GE-T-ignore-TX_FAULT.patch index d9835f8896..83b2c304e2 100644 --- a/target/linux/generic/hack-5.15/790-SFP-GE-T-ignore-TX_FAULT.patch +++ b/target/linux/generic/hack-5.15/790-SFP-GE-T-ignore-TX_FAULT.patch @@ -26,7 +26,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c -@@ -369,6 +369,11 @@ static const struct sfp_quirk sfp_quirks +@@ -373,6 +373,11 @@ static const struct sfp_quirk sfp_quirks .modes = sfp_quirk_2500basex, .fixup = sfp_fixup_ignore_tx_fault, }, { @@ -38,7 +38,7 @@ Signed-off-by: Daniel Golle // Lantech 8330-262D-E can operate at 2500base-X, but // incorrectly report 2500MBd NRZ in their EEPROM .vendor = "Lantech", -@@ -2303,7 +2308,8 @@ static void sfp_sm_main(struct sfp *sfp, +@@ -2306,7 +2311,8 @@ static void sfp_sm_main(struct sfp *sfp, * or t_start_up, so assume there is a fault. */ sfp_sm_fault(sfp, SFP_S_INIT_TX_FAULT, @@ -48,7 +48,7 @@ Signed-off-by: Daniel Golle } else if (event == SFP_E_TIMEOUT || event == SFP_E_TX_CLEAR) { init_done: sfp->sm_phy_retries = R_PHY_RETRY; -@@ -2526,10 +2532,12 @@ static void sfp_check_state(struct sfp * +@@ -2529,10 +2535,12 @@ static void sfp_check_state(struct sfp * mutex_lock(&sfp->st_mutex); state = sfp_get_state(sfp); changed = state ^ sfp->state; diff --git a/target/linux/generic/pending-5.15/050-dtc-checks-Drop-interrupt-provider-address-cells-check.patch b/target/linux/generic/pending-5.15/050-dtc-checks-Drop-interrupt-provider-address-cells-check.patch deleted file mode 100644 index 75f63728ec..0000000000 --- a/target/linux/generic/pending-5.15/050-dtc-checks-Drop-interrupt-provider-address-cells-check.patch +++ /dev/null @@ -1,28 +0,0 @@ -From d8d1a9a77863a8c7031ae82a1d461aa78eb72a7b Mon Sep 17 00:00:00 2001 -From: Rob Herring -Date: Mon, 11 Oct 2021 14:12:43 -0500 -Subject: [PATCH] checks: Drop interrupt provider '#address-cells' check - -'#address-cells' is only needed when parsing 'interrupt-map' properties, so -remove it from the common interrupt-provider test. - -Cc: Andre Przywara -Reviewed-by: David Gibson -Signed-off-by: Rob Herring -Message-Id: <20211011191245.1009682-3-robh@kernel.org> -Signed-off-by: David Gibson ---- ---- a/scripts/dtc/checks.c -+++ b/scripts/dtc/checks.c -@@ -1569,11 +1569,6 @@ static void check_interrupt_provider(str - if (!prop) - FAIL(c, dti, node, - "Missing #interrupt-cells in interrupt provider"); -- -- prop = get_property(node, "#address-cells"); -- if (!prop) -- FAIL(c, dti, node, -- "Missing #address-cells in interrupt provider"); - } - WARNING(interrupt_provider, check_interrupt_provider, NULL); - diff --git a/target/linux/generic/backport-5.15/011-kbuild-export-SUBARCH.patch b/target/linux/generic/pending-5.15/103-kbuild-export-SUBARCH.patch similarity index 100% rename from target/linux/generic/backport-5.15/011-kbuild-export-SUBARCH.patch rename to target/linux/generic/pending-5.15/103-kbuild-export-SUBARCH.patch diff --git a/target/linux/generic/pending-5.15/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch b/target/linux/generic/pending-5.15/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch deleted file mode 100644 index 318c0b1b25..0000000000 --- a/target/linux/generic/pending-5.15/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch +++ /dev/null @@ -1,136 +0,0 @@ -From 87ec87c2ad615c1a177cd08ef5fa29fc739f6e50 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sun, 23 Dec 2018 18:06:53 +0100 -Subject: [PATCH] MIPS: Add CPU option reporting to /proc/cpuinfo - -Many MIPS CPUs have optional CPU features which are not activates for -all CPU cores. Print the CPU options which are implemented in the core -in /proc/cpuinfo. This makes it possible to see what features are -supported and which are not supported. This should cover all standard -MIPS extensions, before it only printed information about the main MIPS -ASEs. - -Signed-off-by: Hauke Mehrtens ---- - arch/mips/kernel/proc.c | 116 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 116 insertions(+) - ---- a/arch/mips/kernel/proc.c -+++ b/arch/mips/kernel/proc.c -@@ -138,6 +138,116 @@ static int show_cpuinfo(struct seq_file - seq_printf(m, "micromips kernel\t: %s\n", - (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no"); - } -+ -+ seq_printf(m, "Options implemented\t:"); -+ if (cpu_has_tlb) -+ seq_printf(m, "%s", " tlb"); -+ if (cpu_has_ftlb) -+ seq_printf(m, "%s", " ftlb"); -+ if (cpu_has_tlbinv) -+ seq_printf(m, "%s", " tlbinv"); -+ if (cpu_has_segments) -+ seq_printf(m, "%s", " segments"); -+ if (cpu_has_rixiex) -+ seq_printf(m, "%s", " rixiex"); -+ if (cpu_has_ldpte) -+ seq_printf(m, "%s", " ldpte"); -+ if (cpu_has_maar) -+ seq_printf(m, "%s", " maar"); -+ if (cpu_has_rw_llb) -+ seq_printf(m, "%s", " rw_llb"); -+ if (cpu_has_4kex) -+ seq_printf(m, "%s", " 4kex"); -+ if (cpu_has_3k_cache) -+ seq_printf(m, "%s", " 3k_cache"); -+ if (cpu_has_4k_cache) -+ seq_printf(m, "%s", " 4k_cache"); -+ if (cpu_has_tx39_cache) -+ seq_printf(m, "%s", " tx39_cache"); -+ if (cpu_has_octeon_cache) -+ seq_printf(m, "%s", " octeon_cache"); -+ if (cpu_has_fpu) -+ seq_printf(m, "%s", " fpu"); -+ if (cpu_has_32fpr) -+ seq_printf(m, "%s", " 32fpr"); -+ if (cpu_has_cache_cdex_p) -+ seq_printf(m, "%s", " cache_cdex_p"); -+ if (cpu_has_cache_cdex_s) -+ seq_printf(m, "%s", " cache_cdex_s"); -+ if (cpu_has_prefetch) -+ seq_printf(m, "%s", " prefetch"); -+ if (cpu_has_mcheck) -+ seq_printf(m, "%s", " mcheck"); -+ if (cpu_has_ejtag) -+ seq_printf(m, "%s", " ejtag"); -+ if (cpu_has_llsc) -+ seq_printf(m, "%s", " llsc"); -+ if (cpu_has_guestctl0ext) -+ seq_printf(m, "%s", " guestctl0ext"); -+ if (cpu_has_guestctl1) -+ seq_printf(m, "%s", " guestctl1"); -+ if (cpu_has_guestctl2) -+ seq_printf(m, "%s", " guestctl2"); -+ if (cpu_has_guestid) -+ seq_printf(m, "%s", " guestid"); -+ if (cpu_has_drg) -+ seq_printf(m, "%s", " drg"); -+ if (cpu_has_rixi) -+ seq_printf(m, "%s", " rixi"); -+ if (cpu_has_lpa) -+ seq_printf(m, "%s", " lpa"); -+ if (cpu_has_mvh) -+ seq_printf(m, "%s", " mvh"); -+ if (cpu_has_vtag_icache) -+ seq_printf(m, "%s", " vtag_icache"); -+ if (cpu_has_dc_aliases) -+ seq_printf(m, "%s", " dc_aliases"); -+ if (cpu_has_ic_fills_f_dc) -+ seq_printf(m, "%s", " ic_fills_f_dc"); -+ if (cpu_has_pindexed_dcache) -+ seq_printf(m, "%s", " pindexed_dcache"); -+ if (cpu_has_userlocal) -+ seq_printf(m, "%s", " userlocal"); -+ if (cpu_has_nofpuex) -+ seq_printf(m, "%s", " nofpuex"); -+ if (cpu_has_vint) -+ seq_printf(m, "%s", " vint"); -+ if (cpu_has_veic) -+ seq_printf(m, "%s", " veic"); -+ if (cpu_has_inclusive_pcaches) -+ seq_printf(m, "%s", " inclusive_pcaches"); -+ if (cpu_has_perf_cntr_intr_bit) -+ seq_printf(m, "%s", " perf_cntr_intr_bit"); -+ if (cpu_has_ufr) -+ seq_printf(m, "%s", " ufr"); -+ if (cpu_has_fre) -+ seq_printf(m, "%s", " fre"); -+ if (cpu_has_cdmm) -+ seq_printf(m, "%s", " cdmm"); -+ if (cpu_has_small_pages) -+ seq_printf(m, "%s", " small_pages"); -+ if (cpu_has_nan_legacy) -+ seq_printf(m, "%s", " nan_legacy"); -+ if (cpu_has_nan_2008) -+ seq_printf(m, "%s", " nan_2008"); -+ if (cpu_has_ebase_wg) -+ seq_printf(m, "%s", " ebase_wg"); -+ if (cpu_has_badinstr) -+ seq_printf(m, "%s", " badinstr"); -+ if (cpu_has_badinstrp) -+ seq_printf(m, "%s", " badinstrp"); -+ if (cpu_has_contextconfig) -+ seq_printf(m, "%s", " contextconfig"); -+ if (cpu_has_perf) -+ seq_printf(m, "%s", " perf"); -+ if (cpu_has_shared_ftlb_ram) -+ seq_printf(m, "%s", " shared_ftlb_ram"); -+ if (cpu_has_shared_ftlb_entries) -+ seq_printf(m, "%s", " shared_ftlb_entries"); -+ if (cpu_has_mipsmt_pertccounters) -+ seq_printf(m, "%s", " mipsmt_pertccounters"); -+ seq_printf(m, "\n"); -+ - seq_printf(m, "shadow register sets\t: %d\n", - cpu_data[n].srsets); - seq_printf(m, "kscratch registers\t: %d\n", diff --git a/target/linux/generic/backport-5.15/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch b/target/linux/generic/pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch similarity index 100% rename from target/linux/generic/backport-5.15/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch rename to target/linux/generic/pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch diff --git a/target/linux/generic/pending-5.15/774--net-sfp-redo-soft-state-polling.patch b/target/linux/generic/pending-5.15/774--net-sfp-redo-soft-state-polling.patch deleted file mode 100644 index 3aa51deb3c..0000000000 --- a/target/linux/generic/pending-5.15/774--net-sfp-redo-soft-state-polling.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 9a84d699ddde0d4e272aa919ad8fd50271a3f932 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Fri, 26 Aug 2022 08:48:20 +0100 -Subject: [PATCH 5/6] net: sfp: redo soft state polling - -Signed-off-by: Russell King (Oracle) ---- - drivers/net/phy/sfp.c | 35 ++++++++++++++++++++++++----------- - 1 file changed, 24 insertions(+), 11 deletions(-) - ---- a/drivers/net/phy/sfp.c -+++ b/drivers/net/phy/sfp.c -@@ -234,6 +234,7 @@ struct sfp { - bool need_poll; - - struct mutex st_mutex; /* Protects state */ -+ unsigned int state_ignore_hw_mask; - unsigned int state_soft_mask; - unsigned int state; - struct delayed_work poll; -@@ -623,17 +624,18 @@ static void sfp_soft_set_state(struct sf - static void sfp_soft_start_poll(struct sfp *sfp) - { - const struct sfp_eeprom_id *id = &sfp->id; -+ unsigned int mask = 0; - - sfp->state_soft_mask = 0; -- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_DISABLE && -- !sfp->gpio[GPIO_TX_DISABLE]) -- sfp->state_soft_mask |= SFP_F_TX_DISABLE; -- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_FAULT && -- !sfp->gpio[GPIO_TX_FAULT]) -- sfp->state_soft_mask |= SFP_F_TX_FAULT; -- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_RX_LOS && -- !sfp->gpio[GPIO_LOS]) -- sfp->state_soft_mask |= SFP_F_LOS; -+ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_DISABLE) -+ mask |= SFP_F_TX_DISABLE; -+ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_FAULT) -+ mask |= SFP_F_TX_FAULT; -+ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_RX_LOS) -+ mask |= SFP_F_LOS; -+ -+ // Poll the soft state for hardware pins we want to ignore -+ sfp->state_soft_mask = sfp->state_ignore_hw_mask & mask; - - if (sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT) && - !sfp->need_poll) -@@ -647,10 +649,12 @@ static void sfp_soft_stop_poll(struct sf - - static unsigned int sfp_get_state(struct sfp *sfp) - { -+ unsigned int soft = sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT); - unsigned int state = sfp->get_state(sfp); - -- if (state & SFP_F_PRESENT && -- sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT)) -+ state &= ~sfp->state_ignore_hw_mask; -+ -+ if (state & SFP_F_PRESENT && soft) - state |= sfp_soft_get_state(sfp); - - return state; -@@ -2064,6 +2068,15 @@ static int sfp_sm_mod_probe(struct sfp * - if (ret < 0) - return ret; - -+ /* Initialise state bits to ignore from hardware */ -+ sfp->state_ignore_hw_mask = 0; -+ if (!sfp->gpio[GPIO_TX_DISABLE]) -+ sfp->state_ignore_hw_mask |= SFP_F_TX_DISABLE; -+ if (!sfp->gpio[GPIO_TX_FAULT]) -+ sfp->state_ignore_hw_mask |= SFP_F_TX_FAULT; -+ if (!sfp->gpio[GPIO_LOS]) -+ sfp->state_ignore_hw_mask |= SFP_F_LOS; -+ - sfp->module_t_start_up = T_START_UP; - - sfp->tx_fault_ignore = false; diff --git a/target/linux/generic/pending-5.15/775-net-sfp-change-HALNy-to-ignore-hardware-pins.patch b/target/linux/generic/pending-5.15/775-net-sfp-change-HALNy-to-ignore-hardware-pins.patch deleted file mode 100644 index 7aa29cd722..0000000000 --- a/target/linux/generic/pending-5.15/775-net-sfp-change-HALNy-to-ignore-hardware-pins.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 32a59a1c5dc8f6fa755bab9a5f9751fdb66bb234 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Fri, 26 Aug 2022 08:48:25 +0100 -Subject: [PATCH 6/6] net: sfp: change HALNy to ignore hardware pins - -Signed-off-by: Russell King (Oracle) ---- - drivers/net/phy/sfp.c | 14 +------------- - 1 file changed, 1 insertion(+), 13 deletions(-) - ---- a/drivers/net/phy/sfp.c -+++ b/drivers/net/phy/sfp.c -@@ -321,21 +321,9 @@ static void sfp_fixup_ignore_tx_fault(st - sfp->tx_fault_ignore = true; - } - --static void sfp_fixup_inverted_los(struct sfp *sfp) --{ -- const __be16 los_inverted = cpu_to_be16(SFP_OPTIONS_LOS_INVERTED); -- const __be16 los_normal = cpu_to_be16(SFP_OPTIONS_LOS_NORMAL); -- -- sfp->id.ext.options &= ~los_normal; -- sfp->id.ext.options |= los_inverted; --} -- - static void sfp_fixup_halny_gsfp(struct sfp *sfp) - { -- /* LOS is inverted */ -- sfp_fixup_inverted_los(sfp); -- /* TX fault might be inverted, but we don't know for certain. */ -- sfp_fixup_ignore_tx_fault(sfp); -+ sfp->state_ignore_hw_mask |= SFP_F_TX_FAULT | SFP_F_LOS; - } - - static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, diff --git a/target/linux/ipq40xx/base-files/etc/board.d/01_leds b/target/linux/ipq40xx/base-files/etc/board.d/01_leds index cd68ed32c0..ac03c3317a 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/01_leds +++ b/target/linux/ipq40xx/base-files/etc/board.d/01_leds @@ -13,10 +13,11 @@ alfa-network,ap120c-ac) ucidef_set_led_netdev "wan" "WAN" "amber:wan" "wan" ;; asus,rt-ac42u) - ucidef_set_led_switch "lan1" "LAN1" "blue:lan-1" "switch0" "0x02" - ucidef_set_led_switch "lan2" "LAN2" "blue:lan-2" "switch0" "0x04" - ucidef_set_led_switch "lan3" "LAN3" "blue:lan-3" "switch0" "0x08" - ucidef_set_led_switch "lan4" "LAN4" "blue:lan-4" "switch0" "0x10" + ucidef_set_led_netdev "lan1" "LAN1" "blue:lan-1" "lan1" + ucidef_set_led_netdev "lan2" "LAN2" "blue:lan-2" "lan2" + ucidef_set_led_netdev "lan3" "LAN3" "blue:lan-3" "lan3" + ucidef_set_led_netdev "lan4" "LAN4" "blue:lan-4" "lan4" + ucidef_set_led_netdev "wan" "WAN" "blue:wan" "wan" ;; asus,rt-ac58u) ucidef_set_led_netdev "wan" "WAN" "blue:wan" "eth1" @@ -80,9 +81,9 @@ mikrotik,sxtsq-5-ac) ucidef_set_led_rssi "rssihigh" "rssihigh" "green:rssihigh" "wlan0" "81" "100" ;; mobipromo,cm520-79f) - ucidef_set_led_netdev "wan" "WAN" "blue:wan" "eth1" - ucidef_set_led_switch "lan1" "LAN1" "blue:lan1" "switch0" "0x10" - ucidef_set_led_switch "lan2" "LAN2" "blue:lan2" "switch0" "0x08" + ucidef_set_led_netdev "wan" "WAN" "blue:wan" "wan" + ucidef_set_led_netdev "lan1" "LAN1" "blue:lan1" "lan1" + ucidef_set_led_netdev "lan2" "LAN2" "blue:lan2" "lan2" ;; netgear,ex6100v2 |\ netgear,ex6150v2) diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network index 36f1f7c24a..57c228e123 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/02_network +++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network @@ -13,6 +13,7 @@ ipq40xx_setup_interfaces() case "$board" in 8dev,habanero-dvk|\ avm,fritzbox-4040|\ + asus,rt-ac42u|\ asus,rt-ac58u|\ linksys,ea6350v3|\ linksys,ea8300|\ @@ -31,6 +32,7 @@ ipq40xx_setup_interfaces() cilab,meshpoint-one|\ edgecore,ecw5211|\ glinet,gl-b2200|\ + google,wifi|\ luma,wrtq-329acn|\ mikrotik,cap-ac|\ netgear,wac510|\ @@ -55,7 +57,8 @@ ipq40xx_setup_interfaces() compex,wpj428) ucidef_set_interface_lan "lan1 lan2" ;; - glinet,gl-b1300) + glinet,gl-b1300|\ + mobipromo,cm520-79f) ucidef_set_interfaces_lan_wan "lan1 lan2" "wan" ;; mikrotik,wap-ac) @@ -81,6 +84,9 @@ ipq40xx_setup_macs() 8dev,habanero-dvk) label_mac=$(mtd_get_mac_binary "ART" 0x1006) ;; + asus,rt-ac42u) + label_mac=$(mtd_get_mac_binary_ubi Factory 0x1006) + ;; asus,rt-ac58u) wan_mac=$(mtd_get_mac_binary_ubi Factory 0x1006) lan_mac=$(mtd_get_mac_binary_ubi Factory 0x5006) @@ -114,6 +120,10 @@ ipq40xx_setup_macs() ezviz,cs-w3-wd1200g-eup) label_mac=$(mtd_get_mac_binary "ART" 0x6) ;; + google,wifi) + wan_mac=$(get_mac_label) + lan_mac=$(macaddr_add "$wan_mac" 1) + ;; linksys,ea6350v3|\ linksys,ea8300 |\ linksys,mr8300) diff --git a/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh b/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh index e4a5eb3e89..ddfef1ab2d 100644 --- a/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh +++ b/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh @@ -8,8 +8,13 @@ preinit_set_mac_address() { ip link set dev eth1 address $(macaddr_add "$base_mac" 3) ;; asus,rt-ac42u) - ip link set dev eth0 address $(mtd_get_mac_binary_ubi Factory 0x1006) - ip link set dev eth1 address $(mtd_get_mac_binary_ubi Factory 0x9006) + base_mac=$(mtd_get_mac_binary_ubi Factory 0x1006) + ip link set dev eth0 address $base_mac + ip link set dev lan1 address $base_mac + ip link set dev lan2 address $base_mac + ip link set dev lan3 address $base_mac + ip link set dev lan4 address $base_mac + ip link set dev wan address $(mtd_get_mac_binary_ubi Factory 0x9006) ;; engenius,eap2200) base_mac=$(cat /sys/class/net/eth0/address) diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts index 93dc8b656a..5be88fcb31 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts @@ -288,6 +288,36 @@ status = "okay"; }; +&gmac { + status = "okay"; + + nvmem-cells = <&macaddr_art_1006>; + nvmem-cell-names = "mac-address"; +}; + +&switch { + status = "okay"; +}; + +&swport3 { + status = "okay"; + + label = "lan2"; +}; + +&swport4 { + status = "okay"; + + label = "lan1"; +}; + +&swport5 { + status = "okay"; + + nvmem-cells = <&macaddr_art_5006>; + nvmem-cell-names = "mac-address"; +}; + &wifi0 { status = "okay"; nvmem-cell-names = "pre-calibration"; diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts index 3d58eac09e..f746acfbb9 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts @@ -31,10 +31,6 @@ status = "okay"; }; - ess-psgmii@98000 { - status = "okay"; - }; - tcsr@1949000 { compatible = "qcom,tcsr"; reg = <0x1949000 0x100>; @@ -85,14 +81,6 @@ watchdog@b017000 { status = "okay"; }; - - ess-switch@c000000 { - status = "okay"; - }; - - edma@c080000 { - status = "okay"; - }; }; keys { @@ -282,6 +270,34 @@ status = "okay"; }; +&gmac { + status = "okay"; +}; + +&switch { + status = "okay"; +}; + +&swport1 { + status = "okay"; +}; + +&swport2 { + status = "okay"; +}; + +&swport3 { + status = "okay"; +}; + +&swport4 { + status = "okay"; +}; + +&swport5 { + status = "okay"; +}; + &wifi0 { status = "okay"; qcom,ath10k-calibration-variant = "ASUS-RT-AC42U"; diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wifi.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wifi.dts index 643449f8e4..65f5933305 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wifi.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wifi.dts @@ -13,6 +13,10 @@ model = "Google WiFi (Gale)"; compatible = "google,wifi", "google,gale-v2", "qcom,ipq4019"; + aliases { + label-mac-device = &gmac0; + }; + chosen { /* * rootwait: in case we're booting from slow/async USB storage. @@ -25,6 +29,26 @@ device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512MB */ }; + + soc { + edma@c080000 { + /* + * Factory bootloader (depthcharge) will fail to boot + * if this exact path (soc/edma@c080000/gmac0) doesn't + * exist. + */ + gmac0: gmac0 { + }; + + /* + * Factory bootloader (depthcharge) will fail to boot + * if this exact path (soc/edma@c080000/gmac1) doesn't + * exist. + */ + gmac1 { + }; + }; + }; }; &tlmm { @@ -325,6 +349,10 @@ status = "okay"; }; +&gmac { + status = "okay"; +}; + &mdio { status = "okay"; pinctrl-0 = <&mdio_pins>; @@ -344,6 +372,20 @@ non-removable; }; +&switch { + status = "okay"; +}; + +&swport4 { + status = "okay"; + + label = "lan"; +}; + +&swport5 { + status = "okay"; +}; + &usb2 { status = "okay"; }; diff --git a/target/linux/ipq40xx/image/chromium.mk b/target/linux/ipq40xx/image/chromium.mk index 7410794fb4..2abd2df02a 100644 --- a/target/linux/ipq40xx/image/chromium.mk +++ b/target/linux/ipq40xx/image/chromium.mk @@ -33,5 +33,4 @@ define Device/google_wifi DEVICE_PACKAGES := partx-utils mkf2fs e2fsprogs \ kmod-fs-ext4 kmod-fs-f2fs kmod-google-firmware endef -# Missing DSA Setup -#TARGET_DEVICES += google_wifi +TARGET_DEVICES += google_wifi diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 68ce31c205..fd3140c2aa 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -228,8 +228,7 @@ define Device/asus_rt-ac42u UIMAGE_NAME:=$(shell echo -e '\03\01\01\01RT-AC82U') DEVICE_PACKAGES := ath10k-firmware-qca9984-ct kmod-usb-ledtrig-usbport endef -# Missing DSA Setup -#TARGET_DEVICES += asus_rt-ac42u +TARGET_DEVICES += asus_rt-ac42u define Device/asus_rt-ac58u $(call Device/FitImageLzma) @@ -762,8 +761,7 @@ define Device/mobipromo_cm520-79f PAGESIZE := 2048 DEVICE_PACKAGES := kmod-usb-ledtrig-usbport endef -# Missing DSA Setup -#TARGET_DEVICES += mobipromo_cm520-79f +TARGET_DEVICES += mobipromo_cm520-79f define Device/netgear_ex61x0v2 $(call Device/DniImage) diff --git a/target/linux/lantiq/Makefile b/target/linux/lantiq/Makefile index 89f457ec5f..08618fa9a3 100644 --- a/target/linux/lantiq/Makefile +++ b/target/linux/lantiq/Makefile @@ -10,7 +10,7 @@ FEATURES:=squashfs SUBTARGETS:=xrx200 xway xway_legacy falcon ase KERNEL_PATCHVER:=5.10 -KERNEL_TESTING_PATCHVER:=5.10 +KERNEL_TESTING_PATCHVER:=5.15 define Target/Description Build firmware images for Lantiq SoC diff --git a/target/linux/lantiq/ase/config-5.15 b/target/linux/lantiq/ase/config-5.15 new file mode 100644 index 0000000000..195e49df69 --- /dev/null +++ b/target/linux/lantiq/ase/config-5.15 @@ -0,0 +1,25 @@ +CONFIG_ADM6996_PHY=y +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +CONFIG_CPU_MIPSR1=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_HW_RANDOM=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_ETOP=y +CONFIG_NLS=y +CONFIG_SGL_ALLOC=y +CONFIG_SOC_AMAZON_SE=y +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SWCONFIG=y +CONFIG_TARGET_ISA_REV=1 +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/config-5.15 b/target/linux/lantiq/config-5.15 new file mode 100644 index 0000000000..c37a543e1e --- /dev/null +++ b/target/linux/lantiq/config-5.15 @@ -0,0 +1,225 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_CEVT_R4K=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_LOAD_STORE_LR=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_BLAKE2S=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_RNG2=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y +CONFIG_DTC=y +# CONFIG_DT_EASY50712 is not set +CONFIG_EARLY_PRINTK=y +CONFIG_EFI_EARLYCON=y +CONFIG_FIXED_PHY=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIO_MM_LANTIQ=y +CONFIG_GPIO_STP_XWAY=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARCH_COMPILER_H=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KVM=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_LANTIQ=y +CONFIG_LANTIQ_DT_NONE=y +# CONFIG_LANTIQ_ETOP is not set +CONFIG_LANTIQ_WDT=y +# CONFIG_LANTIQ_XRX200 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CBPF_JIT=y +CONFIG_MIPS_CLOCK_VSYSCALL=y +# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CMDLINE_FROM_DTB=y +# CONFIG_MIPS_ELF_APPENDED_DTB is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_LD_CAN_LINK_VDSO=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_LANTIQ=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_BRNIMAGE_FW=y +CONFIG_MTD_SPLIT_EVA_FW=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_TPLINK_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NVMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +# CONFIG_PCIE_LANTIQ is not set +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHY_LANTIQ_RCU_USB2=y +# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_LANTIQ=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINCTRL_XWAY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_LANTIQ=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_LANTIQ=y +CONFIG_SERIAL_LANTIQ_CONSOLE=y +# CONFIG_SOC_AMAZON_SE is not set +# CONFIG_SOC_FALCON is not set +# CONFIG_SOC_XWAY is not set +CONFIG_SPI=y +CONFIG_SPI_LANTIQ_SSC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SRCU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_VPE_LOADER=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TINY_SRCU=y +CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/lantiq/falcon/config-5.15 b/target/linux/lantiq/falcon/config-5.15 new file mode 100644 index 0000000000..3041c65dbd --- /dev/null +++ b/target/linux/lantiq/falcon/config-5.15 @@ -0,0 +1,9 @@ +CONFIG_CPU_HAS_DIEI=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux" +CONFIG_PINCTRL_FALCON=y +CONFIG_SOC_FALCON=y +CONFIG_SPI_FALCON=y diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts index 1cd0f2c6b6..be44cb7161 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts @@ -174,13 +174,17 @@ port@0 { reg = <0>; label = "lan3"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; + tx-internal-delay-ps = <1500>; + rx-internal-delay-ps = <1500>; phy-handle = <&phy0>; }; port@1 { reg = <1>; label = "lan4"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; + tx-internal-delay-ps = <1500>; + rx-internal-delay-ps = <1500>; phy-handle = <&phy1>; }; port@2 { @@ -198,7 +202,9 @@ port@5 { reg = <5>; label = "wan"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; + tx-internal-delay-ps = <1500>; + rx-internal-delay-ps = <1500>; phy-handle = <&phy5>; }; }; diff --git a/target/linux/lantiq/patches-5.10/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch b/target/linux/lantiq/patches-5.10/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch similarity index 94% rename from target/linux/lantiq/patches-5.10/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch rename to target/linux/lantiq/patches-5.10/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch index 0ac9adfb96..b7b95d6bfc 100644 --- a/target/linux/lantiq/patches-5.10/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch +++ b/target/linux/lantiq/patches-5.10/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch @@ -1,6 +1,6 @@ -From 2025bc9c3a949b65bfd0601f727678b37962c6c5 Mon Sep 17 00:00:00 2001 +From 730320fd770d4114a2ecb6fb223dcc8c3cecdc5b Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski -Date: Fri, 4 Jun 2021 18:27:58 +0200 +Date: Wed, 21 Sep 2022 22:59:44 +0200 Subject: [PATCH] MIPS: lantiq: enable all hardware interrupts on second VPE This patch is needed to handle interrupts by the second VPE on the Lantiq @@ -32,6 +32,7 @@ Tested on Lantiq xRX200. Suggested-by: Thomas Bogendoerfer Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Thomas Bogendoerfer --- arch/mips/lantiq/prom.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch new file mode 100644 index 0000000000..2276b38c6e --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch @@ -0,0 +1,5505 @@ +From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:12:28 +0200 +Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/Kconfig | 10 + + arch/mips/lantiq/xway/sysctrl.c | 2 + + arch/mips/pci/Makefile | 2 + + arch/mips/pci/fixup-lantiq-pcie.c | 82 +++ + arch/mips/pci/fixup-lantiq.c | 5 +- + arch/mips/pci/ifxmips_pci_common.h | 57 ++ + arch/mips/pci/ifxmips_pcie.c | 1099 ++++++++++++++++++++++++++++++ + arch/mips/pci/ifxmips_pcie.h | 135 ++++ + arch/mips/pci/ifxmips_pcie_ar10.h | 290 ++++++++ + arch/mips/pci/ifxmips_pcie_msi.c | 392 +++++++++++ + arch/mips/pci/ifxmips_pcie_phy.c | 478 +++++++++++++ + arch/mips/pci/ifxmips_pcie_pm.c | 176 +++++ + arch/mips/pci/ifxmips_pcie_pm.h | 36 + + arch/mips/pci/ifxmips_pcie_reg.h | 1001 +++++++++++++++++++++++++++ + arch/mips/pci/ifxmips_pcie_vr9.h | 271 ++++++++ + arch/mips/pci/pci.c | 25 + + arch/mips/pci/pcie-lantiq.h | 1305 ++++++++++++++++++++++++++++++++++++ + drivers/pci/pcie/aer/Kconfig | 2 +- + include/linux/pci.h | 2 + + include/linux/pci_ids.h | 6 + + 20 files changed, 5374 insertions(+), 2 deletions(-) + create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c + create mode 100644 arch/mips/pci/ifxmips_pci_common.h + create mode 100644 arch/mips/pci/ifxmips_pcie.c + create mode 100644 arch/mips/pci/ifxmips_pcie.h + create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h + create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c + create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c + create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c + create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h + create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h + create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h + create mode 100644 arch/mips/pci/pcie-lantiq.h + +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -20,6 +20,7 @@ config SOC_XWAY + bool "XWAY" + select SOC_TYPE_XWAY + select HAVE_PCI ++ select ARCH_SUPPORTS_MSI + select MFD_SYSCON + select MFD_CORE + +@@ -52,4 +53,13 @@ config PCI_LANTIQ + bool "PCI Support" + depends on SOC_XWAY && PCI + ++config PCIE_LANTIQ ++ bool "PCIE Support" ++ depends on SOC_XWAY && PCI ++ ++config PCIE_LANTIQ_MSI ++ bool ++ depends on PCIE_LANTIQ && PCI_MSI ++ default y ++ + endif +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -43,6 +43,8 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o + obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o + obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o ++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o ++obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o + obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o + obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o + obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o +--- /dev/null ++++ b/arch/mips/pci/fixup-lantiq-pcie.c +@@ -0,0 +1,74 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_fixup_pcie.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \file ifxmips_fixup_pcie.c ++ \ingroup IFX_PCIE ++ \brief PCIe Fixup functions source file ++*/ ++#include ++#include ++#include ++ ++#include ++ ++#include "pcie-lantiq.h" ++ ++static void ++ifx_pcie_fixup_resource(struct pci_dev *dev) ++{ ++ u32 reg; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); ++ ++ printk("%s: fixup host controller %s (%04x:%04x)\n", ++ __func__, pci_name(dev), dev->vendor, dev->device); ++ ++ /* Setup COMMAND register */ ++ reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | ++ PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; ++ pci_write_config_word(dev, PCI_COMMAND, reg); ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); ++ ++static void ++ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); ++ ++ if (dev->devfn == PCI_DEVFN(0, 0) && ++ (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { ++ ++ dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); ++ ++ printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); ++ } ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); ++ mdelay(10); ++} ++ ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ++ ifx_pcie_rc_class_early_fixup); ++ ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, ++ ifx_pcie_rc_class_early_fixup); +--- a/arch/mips/pci/fixup-lantiq.c ++++ b/arch/mips/pci/fixup-lantiq.c +@@ -6,12 +6,19 @@ + + #include + #include ++#include ++#include "ifxmips_pci_common.h" + + int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; + int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; + + int pcibios_plat_dev_init(struct pci_dev *dev) + { ++#ifdef CONFIG_PCIE_LANTIQ ++ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) ++ ifx_pcie_bios_plat_dev_init(dev); ++#endif ++ + if (ltq_pci_plat_arch_init) + return ltq_pci_plat_arch_init(dev); + +@@ -23,5 +30,10 @@ int pcibios_plat_dev_init(struct pci_dev + + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) + { ++#ifdef CONFIG_PCIE_LANTIQ ++ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) ++ return ifx_pcie_bios_map_irq(dev, slot, pin); ++#endif ++ + return of_irq_parse_and_map_pci(dev, slot, pin); + } +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pci_common.h +@@ -0,0 +1,53 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pci_common.h ++** PROJECT : IFX UEIP ++** MODULES : PCI subsystem ++** ++** DATE : 30 June 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 30 June,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++ ++#ifndef IFXMIPS_PCI_COMMON_H ++#define IFXMIPS_PCI_COMMON_H ++#include ++/*! ++ \defgroup IFX_PCI_COM IFX PCI/PCIe common parts for OS integration ++ \brief PCI/PCIe common parts ++*/ ++ ++/*! ++ \defgroup IFX_PCI_COM_OS OS APIs ++ \ingroup IFX_PCI_COM ++ \brief PCI/PCIe bus driver OS interface functions ++*/ ++/*! ++ \file ifxmips_pci_common.h ++ \ingroup IFX_PCI_COM ++ \brief PCI/PCIe bus driver common OS header file ++*/ ++#define IFX_PCI_CONST const ++#ifdef CONFIG_IFX_PCI ++extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); ++extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev); ++#endif /* COFNIG_IFX_PCI */ ++ ++#ifdef CONFIG_PCIE_LANTIQ ++extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); ++extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev); ++#endif ++ ++#endif /* IFXMIPS_PCI_COMMON_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie.c +@@ -0,0 +1,1091 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2009 Lei Chuanhua ++ * Copyright (C) 2013 John Crispin ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie.h" ++#include "ifxmips_pcie_reg.h" ++ ++/* Enable 32bit io due to its mem mapped io nature */ ++#define IFX_PCIE_ERROR_INT ++#define IFX_PCIE_IO_32BIT ++ ++#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) ++#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) ++#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) ++#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) ++#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) ++#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) ++#define SM(_v, _f) (((_v) << _f##_S) & (_f)) ++#define IFX_REG_SET_BIT(_f, _r) \ ++ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) ++ ++#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 ++ ++static DEFINE_SPINLOCK(ifx_pcie_lock); ++ ++u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); ++ ++static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { ++ { ++ .ir_irq = { ++ .irq = IFX_PCIE_IR, ++ .name = "ifx_pcie_rc0", ++ }, ++ ++ .legacy_irq = { ++ { ++ .irq_bit = PCIE_IRN_INTA, ++ .irq = IFX_PCIE_INTA, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTB, ++ .irq = IFX_PCIE_INTB, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTC, ++ .irq = IFX_PCIE_INTC, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTD, ++ .irq = IFX_PCIE_INTD, ++ }, ++ }, ++ }, ++ ++}; ++ ++void ifx_pcie_debug(const char *fmt, ...) ++{ ++ static char buf[256] = {0}; /* XXX */ ++ va_list ap; ++ ++ va_start(ap, fmt); ++ vsnprintf(buf, sizeof(buf), fmt, ap); ++ va_end(ap); ++ ++ printk("%s", buf); ++} ++ ++ ++static inline int pcie_ltssm_enable(int pcie_port) ++{ ++ int i; ++ ++ /* Enable LTSSM */ ++ IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); ++ ++ /* Wait for the link to come up */ ++ for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { ++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) ++ return 0; ++ udelay(10); ++ } ++ ++ printk("%s link timeout!!!!!\n", __func__); ++ return -1; ++} ++ ++static inline void pcie_status_register_clear(int pcie_port) ++{ ++ IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); ++ IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_RSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_UES_R(pcie_port)); ++ IFX_REG_W32(0, PCIE_UEMR(pcie_port)); ++ IFX_REG_W32(0, PCIE_UESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_CESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_CEMR(pcie_port)); ++ IFX_REG_W32(0, PCIE_RESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); ++ IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); ++ IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_QSR(pcie_port)); ++ IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); ++} ++ ++static inline int ifx_pcie_link_up(int pcie_port) ++{ ++ return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; ++} ++ ++ ++static inline void pcie_mem_io_setup(int pcie_port) ++{ ++ u32 reg; ++ /* ++ * BAR[0:1] readonly register ++ * RC contains only minimal BARs for packets mapped to this device ++ * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that ++ * reside on the downstream side fo the bridge. ++ */ ++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) ++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); ++ ++ IFX_REG_W32(reg, PCIE_MBML(pcie_port)); ++ ++ ++#ifdef IFX_PCIE_PREFETCH_MEM_64BIT ++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR) ++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT) ++ | PCIE_PMBL_64BIT_ADDR; ++ IFX_REG_W32(reg, PCIE_PMBL(pcie_port)); ++ ++ /* Must configure upper 32bit */ ++ IFX_REG_W32(0, PCIE_PMBU32(pcie_port)); ++ IFX_REG_W32(0, PCIE_PMLU32(pcie_port)); ++#else ++ /* PCIe_PBML, same as MBML */ ++ IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); ++#endif ++ ++ /* IO Address Range */ ++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) ++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); ++#ifdef IFX_PCIE_IO_32BIT ++ reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; ++#endif /* IFX_PCIE_IO_32BIT */ ++ IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); ++ ++#ifdef IFX_PCIE_IO_32BIT ++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) ++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); ++ IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); ++ ++#endif /* IFX_PCIE_IO_32BIT */ ++} ++ ++static inline void ++pcie_device_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Device capability register, set up Maximum payload size */ ++ reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); ++ reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; ++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); ++ ++ /* Only available for EP */ ++ reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); ++ IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); ++ ++ /* Device control and status register */ ++ /* Set Maximum Read Request size for the device as a Requestor */ ++ reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); ++ ++ /* ++ * Request size can be larger than the MPS used, but the completions returned ++ * for the read will be bounded by the MPS size. ++ * In our system, Max request size depends on AHB burst size. It is 64 bytes. ++ * but we set it as 128 as minimum one. ++ */ ++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) ++ | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); ++ ++ /* Enable relaxed ordering, no snoop, and all kinds of errors */ ++ reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; ++ ++ IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); ++} ++ ++static inline void ++pcie_link_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* ++ * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM ++ * L0s is reported during link training via TS1 order set by N_FTS ++ */ ++ reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); ++ reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; ++ reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); ++ IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); ++ ++ /* Link control and status register */ ++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); ++ ++ /* Link Enable, ASPM enabled */ ++ reg &= ~PCIE_LCTLSTS_LINK_DISABLE; ++ ++#ifdef CONFIG_PCIEASPM ++ /* ++ * We use the same physical reference clock that the platform provides on the connector ++ * It paved the way for ASPM to calculate the new exit Latency ++ */ ++ reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; ++ reg |= PCIE_LCTLSTS_COM_CLK_CFG; ++ /* ++ * We should disable ASPM by default except that we have dedicated power management support ++ * Enable ASPM will cause the system hangup/instability, performance degration ++ */ ++ reg |= PCIE_LCTLSTS_ASPM_ENABLE; ++#else ++ reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; ++#endif /* CONFIG_PCIEASPM */ ++ ++ /* ++ * The maximum size of any completion with data packet is bounded by the MPS setting ++ * in device control register ++ */ ++ ++ /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ ++ reg &= ~ PCIE_LCTLSTS_RCB128; ++ ++ IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); ++} ++ ++static inline void pcie_error_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* ++ * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone ++ * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE ++ */ ++ reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); ++ reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; ++ ++ IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); ++ ++ /* Uncorrectable Error Mask Register, Unmask all bits in PCIE_UESR */ ++ reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); ++ reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; ++ IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); ++ ++ /* Uncorrectable Error Severity Register, ALL errors are FATAL */ ++ IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); ++ ++ /* Correctable Error Mask Register, unmask all bits */ ++ reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); ++ reg &= ~PCIE_CORRECTABLE_ERR; ++ IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); ++ ++ /* Advanced Error Capabilities and Control Registr */ ++ reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); ++ reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; ++ IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); ++ ++ /* Root Error Command Register, Report all types of errors */ ++ reg = IFX_REG_R32(PCIE_RECR(pcie_port)); ++ reg |= PCIE_RECR_ERR_REPORT_EN; ++ IFX_REG_W32(reg, PCIE_RECR(pcie_port)); ++ ++ /* Clear the Root status register */ ++ reg = IFX_REG_R32(PCIE_RESR(pcie_port)); ++ IFX_REG_W32(reg, PCIE_RESR(pcie_port)); ++} ++ ++static inline void pcie_port_logic_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ ++ reg = IFX_REG_R32(PCIE_AFR(pcie_port)); ++ reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); ++ reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) ++ | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); ++ /* L0s and L1 entry latency */ ++ reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); ++ reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) ++ | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); ++ IFX_REG_W32(reg, PCIE_AFR(pcie_port)); ++ ++ ++ /* Port Link Control Register */ ++ reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); ++ reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ ++ IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); ++ ++ /* Lane Skew Register */ ++ reg = IFX_REG_R32(PCIE_LSR(pcie_port)); ++ /* Enable ACK/NACK and FC */ ++ reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); ++ IFX_REG_W32(reg, PCIE_LSR(pcie_port)); ++ ++ /* Symbol Timer Register and Filter Mask Register 1 */ ++ reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); ++ ++ /* Default SKP interval is very accurate already, 5us */ ++ /* Enable IO/CFG transaction */ ++ reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; ++ /* Disable FC WDT */ ++ reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; ++ IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); ++ ++ /* Filter Masker Register 2 */ ++ reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); ++ reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; ++ IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); ++ ++ /* VC0 Completion Receive Queue Control Register */ ++ reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); ++ reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; ++ reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); ++ IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); ++} ++ ++static inline void pcie_rc_cfg_reg_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Disable LTSSM */ ++ IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */ ++ ++ pcie_mem_io_setup(pcie_port); ++ ++ /* XXX, MSI stuff should only apply to EP */ ++ /* MSI Capability: Only enable 32-bit addresses */ ++ reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); ++ reg &= ~PCIE_MCAPR_ADDR64_CAP; ++ ++ reg |= PCIE_MCAPR_MSI_ENABLE; ++ ++ /* Disable multiple message */ ++ reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); ++ IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); ++ ++ ++ /* Enable PME, Soft reset enabled */ ++ reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); ++ reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; ++ IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); ++ ++ /* setup the bus */ ++ reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); ++ IFX_REG_W32(reg, PCIE_BNR(pcie_port)); ++ ++ ++ pcie_device_setup(pcie_port); ++ pcie_link_setup(pcie_port); ++ pcie_error_setup(pcie_port); ++ ++ /* Root control and capabilities register */ ++ reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); ++ reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; ++ IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); ++ ++ /* Port VC Capability Register 2 */ ++ reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); ++ reg &= ~PCIE_PVC2_VC_ARB_WRR; ++ reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; ++ IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); ++ ++ /* VC0 Resource Capability Register */ ++ reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); ++ reg &= ~PCIE_VC0_RC_REJECT_SNOOP; ++ IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); ++ ++ pcie_port_logic_setup(pcie_port); ++} ++ ++static int ifx_pcie_wait_phy_link_up(int pcie_port) ++{ ++#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 /* XXX, tunable */ ++ int i; ++ ++ /* Wait for PHY link is up */ ++ for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { ++ if (ifx_pcie_link_up(pcie_port)) { ++ break; ++ } ++ udelay(100); ++ } ++ if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { ++ printk(KERN_ERR "%s timeout\n", __func__); ++ return -1; ++ } ++ ++ /* Check data link up or not */ ++ if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { ++ printk(KERN_ERR "%s DLL link is still down\n", __func__); ++ return -1; ++ } ++ ++ /* Check Data link active or not */ ++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { ++ printk(KERN_ERR "%s DLL is not active\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static inline int pcie_app_loigc_setup(int pcie_port) ++{ ++ /* supress ahb bus errrors */ ++ IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); ++ ++ /* Pull PCIe EP out of reset */ ++ pcie_device_rst_deassert(pcie_port); ++ ++ /* Start LTSSM training between RC and EP */ ++ pcie_ltssm_enable(pcie_port); ++ ++ /* Check PHY status after enabling LTSSM */ ++ if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) ++ return -1; ++ ++ return 0; ++} ++ ++/* ++ * The numbers below are directly from the PCIe spec table 3-4/5. ++ */ ++static inline void pcie_replay_time_update(int pcie_port) ++{ ++ u32 reg; ++ int nlw; ++ int rtl; ++ ++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); ++ ++ nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); ++ switch (nlw) { ++ case PCIE_MAX_LENGTH_WIDTH_X1: ++ rtl = 1677; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X2: ++ rtl = 867; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X4: ++ rtl = 462; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X8: ++ rtl = 258; ++ break; ++ default: ++ rtl = 1677; ++ break; ++ } ++ reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); ++ reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; ++ reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); ++ IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); ++} ++ ++/* ++ * Table 359 Enhanced Configuration Address Mapping1) ++ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 ++ * Memory Address PCI Express Configuration Space ++ * A[(20+n-1):20] Bus Number 1 < n < 8 ++ * A[19:15] Device Number ++ * A[14:12] Function Number ++ * A[11:8] Extended Register Number ++ * A[7:2] Register Number ++ * A[1:0] Along with size of the access, used to generate Byte Enables ++ * For VR9, only the address bits [22:0] are mapped to the configuration space: ++ * . Address bits [22:20] select the target bus (1-of-8)1) ++ * . Address bits [19:15] select the target device (1-of-32) on the bus ++ * . Address bits [14:12] select the target function (1-of-8) within the device. ++ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space ++ * . Address bits [1:0] define the start byte location within the selected dword. ++ */ ++static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where) ++{ ++ u32 addr; ++ u8 bus; ++ ++ if (!bus_num) { ++ /* type 0 */ ++ addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); ++ } else { ++ bus = bus_num; ++ /* type 1, only support 8 buses */ ++ addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | ++ ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); ++ } ++ return addr; ++} ++ ++static int pcie_valid_config(int pcie_port, int bus, int dev) ++{ ++ /* RC itself */ ++ if ((bus == 0) && (dev == 0)) { ++ return 1; ++ } ++ ++ /* No physical link */ ++ if (!ifx_pcie_link_up(pcie_port)) { ++ return 0; ++ } ++ ++ /* Bus zero only has RC itself ++ * XXX, check if EP will be integrated ++ */ ++ if ((bus == 0) && (dev != 0)) { ++ return 0; ++ } ++ ++ /* Maximum 8 buses supported for VRX */ ++ if (bus > 9) { ++ return 0; ++ } ++ ++ /* ++ * PCIe is PtP link, one bus only supports only one device ++ * except bus zero and PCIe switch which is virtual bus device ++ * The following two conditions really depends on the system design ++ * and attached the device. ++ * XXX, how about more new switch ++ */ ++ if ((bus == 1) && (dev != 0)) { ++ return 0; ++ } ++ ++ if ((bus >= 3) && (dev != 0)) { ++ return 0; ++ } ++ return 1; ++} ++ ++static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg) ++{ ++ return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val) ++{ ++ IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg) ++{ ++ return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val) ++{ ++ IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++u32 ifx_pcie_bus_enum_read_hack(int where, u32 value) ++{ ++ u32 tvalue = value; ++ ++ if (where == PCI_PRIMARY_BUS) { ++ u8 primary, secondary, subordinate; ++ ++ primary = tvalue & 0xFF; ++ secondary = (tvalue >> 8) & 0xFF; ++ subordinate = (tvalue >> 16) & 0xFF; ++ primary += pcibios_1st_host_bus_nr(); ++ secondary += pcibios_1st_host_bus_nr(); ++ subordinate += pcibios_1st_host_bus_nr(); ++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); ++ } ++ return tvalue; ++} ++ ++u32 ifx_pcie_bus_enum_write_hack(int where, u32 value) ++{ ++ u32 tvalue = value; ++ ++ if (where == PCI_PRIMARY_BUS) { ++ u8 primary, secondary, subordinate; ++ ++ primary = tvalue & 0xFF; ++ secondary = (tvalue >> 8) & 0xFF; ++ subordinate = (tvalue >> 16) & 0xFF; ++ if (primary > 0 && primary != 0xFF) { ++ primary -= pcibios_1st_host_bus_nr(); ++ } ++ ++ if (secondary > 0 && secondary != 0xFF) { ++ secondary -= pcibios_1st_host_bus_nr(); ++ } ++ if (subordinate > 0 && subordinate != 0xFF) { ++ subordinate -= pcibios_1st_host_bus_nr(); ++ } ++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); ++ } ++ else if (where == PCI_SUBORDINATE_BUS) { ++ u8 subordinate = tvalue & 0xFF; ++ ++ subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; ++ tvalue = subordinate; ++ } ++ return tvalue; ++} ++ ++static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 *value) ++{ ++ u32 data = 0; ++ int bus_number = bus->number; ++ static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; ++ int ret = PCIBIOS_SUCCESSFUL; ++ struct ifx_pci_controller *ctrl = bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ if (unlikely(size != 1 && size != 2 && size != 4)){ ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ ++ /* Make sure the address is aligned to natural boundary */ ++ if (unlikely(((size - 1) & where))) { ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ ++ /* ++ * If we are second controller, we have to cheat OS so that it assume ++ * its bus number starts from 0 in host controller ++ */ ++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); ++ ++ /* ++ * We need to force the bus number to be zero on the root ++ * bus. Linux numbers the 2nd root bus to start after all ++ * busses on root 0. ++ */ ++ if (bus->parent == NULL) { ++ bus_number = 0; ++ } ++ ++ /* ++ * PCIe only has a single device connected to it. It is ++ * always device ID 0. Don't bother doing reads for other ++ * device IDs on the first segment. ++ */ ++ if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { ++ ret = PCIBIOS_FUNC_NOT_SUPPORTED; ++ goto out; ++ } ++ ++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { ++ *value = 0xffffffff; ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ goto out; ++ } ++ ++ PCIE_IRQ_LOCK(ifx_pcie_lock); ++ if (bus_number == 0) { /* RC itself */ ++ u32 t; ++ ++ t = (where & ~3); ++ data = ifx_pcie_rc_cfg_rd(pcie_port, t); ++ } else { ++ u32 addr = pcie_bus_addr(bus_number, devfn, where); ++ ++ data = ifx_pcie_cfg_rd(pcie_port, addr); ++ #ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = le32_to_cpu(data); ++ #endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ } ++ /* To get a correct PCI topology, we have to restore the bus number to OS */ ++ data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); ++ ++ PCIE_IRQ_UNLOCK(ifx_pcie_lock); ++ ++ *value = (data >> (8 * (where & 3))) & mask[size & 7]; ++out: ++ return ret; ++} ++ ++static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value) ++{ ++ u32 shift; ++ u32 tdata = data; ++ ++ switch (size) { ++ case 1: ++ shift = (where & 0x3) << 3; ++ tdata &= ~(0xffU << shift); ++ tdata |= ((value & 0xffU) << shift); ++ break; ++ case 2: ++ shift = (where & 3) << 3; ++ tdata &= ~(0xffffU << shift); ++ tdata |= ((value & 0xffffU) << shift); ++ break; ++ case 4: ++ tdata = value; ++ break; ++ } ++ return tdata; ++} ++ ++static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 value) ++{ ++ int bus_number = bus->number; ++ int ret = PCIBIOS_SUCCESSFUL; ++ struct ifx_pci_controller *ctrl = bus->sysdata; ++ int pcie_port = ctrl->port; ++ u32 tvalue = value; ++ u32 data; ++ ++ /* Make sure the address is aligned to natural boundary */ ++ if (unlikely(((size - 1) & where))) { ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ /* ++ * If we are second controller, we have to cheat OS so that it assume ++ * its bus number starts from 0 in host controller ++ */ ++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); ++ ++ /* ++ * We need to force the bus number to be zero on the root ++ * bus. Linux numbers the 2nd root bus to start after all ++ * busses on root 0. ++ */ ++ if (bus->parent == NULL) { ++ bus_number = 0; ++ } ++ ++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ goto out; ++ } ++ ++ /* XXX, some PCIe device may need some delay */ ++ PCIE_IRQ_LOCK(ifx_pcie_lock); ++ ++ /* ++ * To configure the correct bus topology using native way, we have to cheat Os so that ++ * it can configure the PCIe hardware correctly. ++ */ ++ tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); ++ ++ if (bus_number == 0) { /* RC itself */ ++ u32 t; ++ ++ t = (where & ~3); ++ data = ifx_pcie_rc_cfg_rd(pcie_port, t); ++ ++ data = ifx_pcie_size_to_value(where, size, data, tvalue); ++ ++ ifx_pcie_rc_cfg_wr(pcie_port, t, data); ++ } else { ++ u32 addr = pcie_bus_addr(bus_number, devfn, where); ++ ++ data = ifx_pcie_cfg_rd(pcie_port, addr); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = le32_to_cpu(data); ++#endif ++ ++ data = ifx_pcie_size_to_value(where, size, data, tvalue); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = cpu_to_le32(data); ++#endif ++ ifx_pcie_cfg_wr(pcie_port, addr, data); ++ } ++ PCIE_IRQ_UNLOCK(ifx_pcie_lock); ++out: ++ return ret; ++} ++ ++static struct resource ifx_pcie_io_resource = { ++ .name = "PCIe0 I/O space", ++ .start = PCIE_IO_PHY_BASE, ++ .end = PCIE_IO_PHY_END, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource ifx_pcie_mem_resource = { ++ .name = "PCIe0 Memory space", ++ .start = PCIE_MEM_PHY_BASE, ++ .end = PCIE_MEM_PHY_END, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct pci_ops ifx_pcie_ops = { ++ .read = ifx_pcie_read_config, ++ .write = ifx_pcie_write_config, ++}; ++ ++static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { ++ { ++ .pcic = { ++ .pci_ops = &ifx_pcie_ops, ++ .mem_resource = &ifx_pcie_mem_resource, ++ .io_resource = &ifx_pcie_io_resource, ++ }, ++ .port = IFX_PCIE_PORT0, ++ }, ++}; ++ ++#ifdef IFX_PCIE_ERROR_INT ++ ++static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) ++{ ++ struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; ++ int pcie_port = ctrl->port; ++ u32 reg; ++ ++ pr_debug("PCIe RC error intr %d\n", irq); ++ reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); ++ reg &= PCIE_RC_CORE_COMBINED_INT; ++ IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ++pcie_rc_core_int_init(int pcie_port) ++{ ++ int ret; ++ ++ /* Enable core interrupt */ ++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); ++ ++ /* Clear it first */ ++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); ++ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0, ++ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); ++ if (ret) ++ printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); ++ ++ return ret; ++} ++#endif ++ ++int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ u32 irq_bit = 0; ++ int irq = 0; ++ struct ifx_pci_controller *ctrl = dev->bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); ++ ++ if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { ++ printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); ++ return -1; ++ } ++ ++ /* Pin index so minus one */ ++ irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; ++ irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; ++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); ++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); ++ printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); ++ return irq; ++} ++ ++int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) ++{ ++ u16 config; ++#ifdef IFX_PCIE_ERROR_INT ++ u32 dconfig; ++ int pos; ++#endif ++ ++ /* Enable reporting System errors and parity errors on all devices */ ++ /* Enable parity checking and error reporting */ ++ pci_read_config_word(dev, PCI_COMMAND, &config); ++ config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | ++ PCI_COMMAND_FAST_BACK*/; ++ pci_write_config_word(dev, PCI_COMMAND, config); ++ ++ if (dev->subordinate) { ++ /* Set latency timers on sub bridges */ ++ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ ++ /* More bridge error detection */ ++ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); ++ config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; ++ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); ++ } ++#ifdef IFX_PCIE_ERROR_INT ++ /* Enable the PCIe normal error reporting */ ++ pos = pci_find_capability(dev, PCI_CAP_ID_EXP); ++ if (pos) { ++ ++ /* Disable system error generation in response to error messages */ ++ pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); ++ config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); ++ pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); ++ ++ /* Clear PCIE Capability's Device Status */ ++ pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); ++ pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); ++ ++ /* Update Device Control */ ++ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); ++ /* Correctable Error Reporting */ ++ config |= PCI_EXP_DEVCTL_CERE; ++ /* Non-Fatal Error Reporting */ ++ config |= PCI_EXP_DEVCTL_NFERE; ++ /* Fatal Error Reporting */ ++ config |= PCI_EXP_DEVCTL_FERE; ++ /* Unsupported Request */ ++ config |= PCI_EXP_DEVCTL_URRE; ++ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); ++ } ++ ++ /* Find the Advanced Error Reporting capability */ ++ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); ++ if (pos) { ++ /* Clear Uncorrectable Error Status */ ++ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); ++ /* Enable reporting of all uncorrectable errors */ ++ /* Uncorrectable Error Mask - turned on bits disable errors */ ++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); ++ /* ++ * Leave severity at HW default. This only controls if ++ * errors are reported as uncorrectable or ++ * correctable, not if the error is reported. ++ */ ++ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ ++ /* Clear Correctable Error Status */ ++ pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); ++ /* Enable reporting of all correctable errors */ ++ /* Correctable Error Mask - turned on bits disable errors */ ++ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); ++ /* Advanced Error Capabilities */ ++ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); ++ /* ECRC Generation Enable */ ++ if (dconfig & PCI_ERR_CAP_ECRC_GENC) { ++ dconfig |= PCI_ERR_CAP_ECRC_GENE; ++ } ++ /* ECRC Check Enable */ ++ if (dconfig & PCI_ERR_CAP_ECRC_CHKC) { ++ dconfig |= PCI_ERR_CAP_ECRC_CHKE; ++ } ++ pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); ++ ++ /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ ++ /* Enable Root Port's interrupt in response to error messages */ ++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, ++ PCI_ERR_ROOT_CMD_COR_EN | ++ PCI_ERR_ROOT_CMD_NONFATAL_EN | ++ PCI_ERR_ROOT_CMD_FATAL_EN); ++ /* Clear the Root status register */ ++ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); ++ } ++#endif /* IFX_PCIE_ERROR_INT */ ++ /* WAR, only 128 MRRS is supported, force all EPs to support this value */ ++ pcie_set_readrq(dev, 128); ++ return 0; ++} ++ ++static int ++pcie_rc_initialize(int pcie_port) ++{ ++ int i; ++#define IFX_PCIE_PHY_LOOP_CNT 5 ++ ++ pcie_rcu_endian_setup(pcie_port); ++ ++ pcie_ep_gpio_rst_init(pcie_port); ++ ++ /* ++ * XXX, PCIe elastic buffer bug will cause not to be detected. One more ++ * reset PCIe PHY will solve this issue ++ */ ++ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { ++ /* Disable PCIe PHY Analog part for sanity check */ ++ pcie_phy_pmu_disable(pcie_port); ++ ++ pcie_phy_rst_assert(pcie_port); ++ pcie_phy_rst_deassert(pcie_port); ++ ++ /* Make sure PHY PLL is stable */ ++ udelay(20); ++ ++ /* PCIe Core reset enabled, low active, sw programmed */ ++ pcie_core_rst_assert(pcie_port); ++ ++ /* Put PCIe EP in reset status */ ++ pcie_device_rst_assert(pcie_port); ++ ++ /* PCI PHY & Core reset disabled, high active, sw programmed */ ++ pcie_core_rst_deassert(pcie_port); ++ ++ /* Already in a quiet state, program PLL, enable PHY, check ready bit */ ++ pcie_phy_clock_mode_setup(pcie_port); ++ ++ /* Enable PCIe PHY and Clock */ ++ pcie_core_pmu_setup(pcie_port); ++ ++ /* Clear status registers */ ++ pcie_status_register_clear(pcie_port); ++ ++#ifdef CONFIG_PCI_MSI ++ pcie_msi_init(pcie_port); ++#endif /* CONFIG_PCI_MSI */ ++ pcie_rc_cfg_reg_setup(pcie_port); ++ ++ /* Once link is up, break out */ ++ if (pcie_app_loigc_setup(pcie_port) == 0) ++ break; ++ } ++ if (i >= IFX_PCIE_PHY_LOOP_CNT) { ++ printk(KERN_ERR "%s link up failed!!!!!\n", __func__); ++ return -EIO; ++ } ++ /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ ++ pcie_replay_time_update(pcie_port); ++ return 0; ++} ++ ++static int __init ifx_pcie_bios_init(void) ++{ ++ void __iomem *io_map_base; ++ int pcie_port; ++ int startup_port; ++ ++ /* Enable AHB Master/ Slave */ ++ pcie_ahb_pmu_setup(); ++ ++ startup_port = IFX_PCIE_PORT0; ++ ++ for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ ++ if (pcie_rc_initialize(pcie_port) == 0) { ++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", ++ __func__, PCIE_CFG_PORT_TO_BASE(pcie_port)); ++ /* Otherwise, warning will pop up */ ++ io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); ++ if (io_map_base == NULL) { ++ IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__); ++ return -ENOMEM; ++ } ++ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; ++ ++ register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); ++ /* XXX, clear error status */ ++ ++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n", ++ __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, ++ &ifx_pcie_controller[pcie_port].pcic.io_resource); ++ ++ #ifdef IFX_PCIE_ERROR_INT ++ pcie_rc_core_int_init(pcie_port); ++ #endif /* IFX_PCIE_ERROR_INT */ ++ } ++ } ++ ++ return 0; ++} ++arch_initcall(ifx_pcie_bios_init); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); ++MODULE_DESCRIPTION("Infineon builtin PCIe RC driver"); ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie.h +@@ -0,0 +1,131 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_H ++#define IFXMIPS_PCIE_H ++#include ++#include ++#include ++#include ++#include "ifxmips_pci_common.h" ++#include "ifxmips_pcie_reg.h" ++ ++/*! ++ \defgroup IFX_PCIE PCI Express bus driver module ++ \brief PCI Express IP module support VRX200 ++*/ ++ ++/*! ++ \defgroup IFX_PCIE_OS OS APIs ++ \ingroup IFX_PCIE ++ \brief PCIe bus driver OS interface functions ++*/ ++ ++/*! ++ \file ifxmips_pcie.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module common header file ++*/ ++#define PCIE_IRQ_LOCK(lock) do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(&(lock), flags); ++#define PCIE_IRQ_UNLOCK(lock) \ ++ spin_unlock_irqrestore(&(lock), flags); \ ++} while (0) ++ ++#define PCIE_MSG_MSI 0x00000001 ++#define PCIE_MSG_ISR 0x00000002 ++#define PCIE_MSG_FIXUP 0x00000004 ++#define PCIE_MSG_READ_CFG 0x00000008 ++#define PCIE_MSG_WRITE_CFG 0x00000010 ++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) ++#define PCIE_MSG_REG 0x00000020 ++#define PCIE_MSG_INIT 0x00000040 ++#define PCIE_MSG_ERR 0x00000080 ++#define PCIE_MSG_PHY 0x00000100 ++#define PCIE_MSG_ANY 0x000001ff ++ ++#define IFX_PCIE_PORT0 0 ++#define IFX_PCIE_PORT1 1 ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++#define IFX_PCIE_CORE_NR 2 ++#else ++#define IFX_PCIE_CORE_NR 1 ++#endif ++ ++#define IFX_PCIE_ERROR_INT ++ ++//#define IFX_PCIE_DBG ++ ++#if defined(IFX_PCIE_DBG) ++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ ++ ifx_pcie_debug((_fmt), ##args); \ ++} while (0) ++ ++#define INLINE ++#else ++#define IFX_PCIE_PRINT(_m, _fmt, args...) \ ++ do {} while(0) ++#define INLINE inline ++#endif ++ ++struct ifx_pci_controller { ++ struct pci_controller pcic; ++ ++ /* RC specific, per host bus information */ ++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ ++}; ++ ++typedef struct ifx_pcie_ir_irq { ++ const unsigned int irq; ++ const char name[16]; ++}ifx_pcie_ir_irq_t; ++ ++typedef struct ifx_pcie_legacy_irq{ ++ const u32 irq_bit; ++ const int irq; ++}ifx_pcie_legacy_irq_t; ++ ++typedef struct ifx_pcie_irq { ++ ifx_pcie_ir_irq_t ir_irq; ++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; ++}ifx_pcie_irq_t; ++ ++extern u32 g_pcie_debug_flag; ++extern void ifx_pcie_debug(const char *fmt, ...); ++extern void pcie_phy_clock_mode_setup(int pcie_port); ++extern void pcie_msi_pic_init(int pcie_port); ++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); ++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); ++ ++#define CONFIG_VR9 ++ ++#ifdef CONFIG_VR9 ++#include "ifxmips_pcie_vr9.h" ++#elif defined (CONFIG_AR10) ++#include "ifxmips_pcie_ar10.h" ++#else ++#error "PCIE: platform not defined" ++#endif /* CONFIG_VR9 */ ++ ++#endif /* IFXMIPS_PCIE_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_ar10.h +@@ -0,0 +1,290 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++/*! ++ \file ifxmips_pcie_ar10.h ++ \ingroup IFX_PCIE ++ \brief PCIe RC driver ar10 specific file ++*/ ++ ++#ifndef IFXMIPS_PCIE_AR10_H ++#define IFXMIPS_PCIE_AR10_H ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++ ++/* Project header file */ ++#include ++#include ++#include ++#include ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ ifx_ebu_led_enable(); ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 1); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 1); ++ } ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ /* XXX, moved to CGU to control AHBM */ ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ /* Inbound, big endian */ ++ reg |= IFX_RCU_BE_AHB4S; ++ if (pcie_port == 0) { ++ reg |= IFX_RCU_BE_PCIE0M; ++ ++ #ifdef CONFIG_IFX_PCIE_HW_SWAP ++ /* Outbound, software swap needed */ ++ reg |= IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE0S; ++ #else ++ /* Outbound little endian */ ++ reg &= ~IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE0S; ++ #endif ++ } ++ else { ++ reg |= IFX_RCU_BE_PCIE1M; ++ #ifdef CONFIG_IFX_PCIE1_HW_SWAP ++ /* Outbound, software swap needed */ ++ reg |= IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE1S; ++ #else ++ /* Outbound little endian */ ++ reg &= ~IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE1S; ++ #endif ++ } ++ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ if (pcie_port == 0) { /* XXX, should use macro*/ ++ PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_phy_pmu_disable(int pcie_port) ++{ ++ if (pcie_port == 0) { /* XXX, should use macro*/ ++ PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++ } ++ else { ++ PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++ } ++} ++ ++static inline void pcie_pdi_big_endian(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ if (pcie_port == 0) { ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_BE_PCIE0_PDI; ++ } ++ else { ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_BE_PCIE1_PDI; ++ } ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ /* Enable PDI to access PCIe PHY register */ ++ PDI0_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PDI1_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_core_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ ++ /* Reset Core, bit 22 */ ++ if (pcie_port == 0) { ++ reg |= 0x00400000; ++ } ++ else { ++ reg |= 0x08000000; /* Bit 27 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_core_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg &= ~0x00400000; /* bit 22 */ ++ } ++ else { ++ reg &= ~0x08000000; /* Bit 27 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg |= 0x00001000; /* Bit 12 */ ++ } ++ else { ++ reg |= 0x00002000; /* Bit 13 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg &= ~0x00001000; /* Bit 12 */ ++ } ++ else { ++ reg &= ~0x00002000; /* Bit 13 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 0); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 0); ++ } ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 1); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 1); ++ } ++ ifx_ebu_led_disable(); ++} ++ ++static inline void pcie_core_pmu_setup(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_msi_init(int pcie_port) ++{ ++ pcie_msi_pic_init(pcie_port); ++ if (pcie_port == 0) { ++ MSI0_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ MSI1_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline u32 ++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) ++{ ++ u32 tbus_number = bus_number; ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++ } ++#endif /* CONFIG_IFX_PCI */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ } ++ #endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_AR10_H */ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_msi.c +@@ -0,0 +1,391 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_msi.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCI MSI sub module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe MSI Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Date $Author $Comment ++** 02 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \defgroup IFX_PCIE_MSI MSI OS APIs ++ \ingroup IFX_PCIE ++ \brief PCIe bus driver OS interface functions ++*/ ++ ++/*! ++ \file ifxmips_pcie_msi.c ++ \ingroup IFX_PCIE ++ \brief PCIe MSI OS interface file ++*/ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie_reg.h" ++#include "ifxmips_pcie.h" ++ ++#define IFX_MSI_IRQ_NUM 16 ++ ++enum { ++ IFX_PCIE_MSI_IDX0 = 0, ++ IFX_PCIE_MSI_IDX1, ++ IFX_PCIE_MSI_IDX2, ++ IFX_PCIE_MSI_IDX3, ++}; ++ ++typedef struct ifx_msi_irq_idx { ++ const int irq; ++ const int idx; ++}ifx_msi_irq_idx_t; ++ ++struct ifx_msi_pic { ++ volatile u32 pic_table[IFX_MSI_IRQ_NUM]; ++ volatile u32 pic_endian; /* 0x40 */ ++}; ++typedef struct ifx_msi_pic *ifx_msi_pic_t; ++ ++typedef struct ifx_msi_irq { ++ const volatile ifx_msi_pic_t msi_pic_p; ++ const u32 msi_phy_base; ++ const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; ++ /* ++ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is ++ * in use. ++ */ ++ u16 msi_free_irq_bitmask; ++ ++ /* ++ * Each bit in msi_multiple_irq_bitmask tells that the device using ++ * this bit in msi_free_irq_bitmask is also using the next bit. This ++ * is used so we can disable all of the MSI interrupts when a device ++ * uses multiple. ++ */ ++ u16 msi_multiple_irq_bitmask; ++}ifx_msi_irq_t; ++ ++static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { ++ { ++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, ++ .msi_phy_base = PCIE_MSI_PHY_BASE, ++ .msi_irq_idx = { ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ }, ++ .msi_free_irq_bitmask = 0, ++ .msi_multiple_irq_bitmask= 0, ++ }, ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ { ++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, ++ .msi_phy_base = PCIE1_MSI_PHY_BASE, ++ .msi_irq_idx = { ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ }, ++ .msi_free_irq_bitmask = 0, ++ .msi_multiple_irq_bitmask= 0, ++ ++ }, ++#endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++}; ++ ++/* ++ * This lock controls updates to msi_free_irq_bitmask, ++ * msi_multiple_irq_bitmask and pic register settting ++ */ ++static DEFINE_SPINLOCK(ifx_pcie_msi_lock); ++ ++void pcie_msi_pic_init(int pcie_port) ++{ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; ++ spin_unlock(&ifx_pcie_msi_lock); ++} ++ ++/** ++ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ++ * \brief Called when a driver request MSI interrupts instead of the ++ * legacy INT A-D. This routine will allocate multiple interrupts ++ * for MSI devices that support them. A device can override this by ++ * programming the MSI control bits [6:4] before calling ++ * pci_enable_msi(). ++ * ++ * \param[in] pdev Device requesting MSI interrupts ++ * \param[in] desc MSI descriptor ++ * ++ * \return -EINVAL Invalid pcie root port or invalid msi bit ++ * \return 0 OK ++ * \ingroup IFX_PCIE_MSI ++ */ ++int ++arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ++{ ++ int irq, pos; ++ u16 control; ++ int irq_idx; ++ int irq_step; ++ int configured_private_bits; ++ int request_private_bits; ++ struct msi_msg msg; ++ u16 search_mask; ++ struct ifx_pci_controller *ctrl = pdev->bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); ++ ++ /* XXX, skip RC MSI itself */ ++ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* ++ * Read the MSI config to figure out how many IRQs this device ++ * wants. Most devices only want 1, which will give ++ * configured_private_bits and request_private_bits equal 0. ++ */ ++ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); ++ ++ /* ++ * If the number of private bits has been configured then use ++ * that value instead of the requested number. This gives the ++ * driver the chance to override the number of interrupts ++ * before calling pci_enable_msi(). ++ */ ++ configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; ++ if (configured_private_bits == 0) { ++ /* Nothing is configured, so use the hardware requested size */ ++ request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; ++ } ++ else { ++ /* ++ * Use the number of configured bits, assuming the ++ * driver wanted to override the hardware request ++ * value. ++ */ ++ request_private_bits = configured_private_bits; ++ } ++ ++ /* ++ * The PCI 2.3 spec mandates that there are at most 32 ++ * interrupts. If this device asks for more, only give it one. ++ */ ++ if (request_private_bits > 5) { ++ request_private_bits = 0; ++ } ++again: ++ /* ++ * The IRQs have to be aligned on a power of two based on the ++ * number being requested. ++ */ ++ irq_step = (1 << request_private_bits); ++ ++ /* Mask with one bit for each IRQ */ ++ search_mask = (1 << irq_step) - 1; ++ ++ /* ++ * We're going to search msi_free_irq_bitmask_lock for zero ++ * bits. This represents an MSI interrupt number that isn't in ++ * use. ++ */ ++ spin_lock(&ifx_pcie_msi_lock); ++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { ++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { ++ msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; ++ msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; ++ break; ++ } ++ } ++ spin_unlock(&ifx_pcie_msi_lock); ++ ++ /* Make sure the search for available interrupts didn't fail */ ++ if (pos >= IFX_MSI_IRQ_NUM) { ++ if (request_private_bits) { ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " ++ "interrupts, trying just one", __func__, 1 << request_private_bits); ++ request_private_bits = 0; ++ goto again; ++ } ++ else { ++ printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); ++ return -EINVAL; ++ } ++ } ++ irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; ++ irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); ++ ++ /* ++ * Initialize MSI. This has to match the memory-write endianess from the device ++ * Address bits [23:12] ++ */ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | ++ SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | ++ SM((1 << pos), IFX_MSI_PIC_MSG_DATA); ++ ++ /* Enable this entry */ ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; ++ spin_unlock(&ifx_pcie_msi_lock); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", ++ pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); ++ ++ /* Update the number of IRQs the device has available to it */ ++ control &= ~PCI_MSI_FLAGS_QSIZE; ++ control |= (request_private_bits << 4); ++ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); ++ ++ set_irq_msi(irq, desc); ++ msg.address_hi = 0x0; ++ msg.address_lo = msi_irqs[pcie_port].msi_phy_base; ++ msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); ++ ++ write_msi_msg(irq, &msg); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); ++ return 0; ++} ++ ++static int ++pcie_msi_irq_to_port(unsigned int irq, int *port) ++{ ++ int ret = 0; ++ ++ if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || ++ irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { ++ *port = IFX_PCIE_PORT0; ++ } ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || ++ irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { ++ *port = IFX_PCIE_PORT1; ++ } ++#endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++ else { ++ printk(KERN_ERR "%s: Attempted to teardown illegal " ++ "MSI interrupt (%d)\n", __func__, irq); ++ ret = -EINVAL; ++ } ++ return ret; ++} ++ ++/** ++ * \fn void arch_teardown_msi_irq(unsigned int irq) ++ * \brief Called when a device no longer needs its MSI interrupts. All ++ * MSI interrupts for the device are freed. ++ * ++ * \param irq The devices first irq number. There may be multple in sequence. ++ * \return none ++ * \ingroup IFX_PCIE_MSI ++ */ ++void ++arch_teardown_msi_irq(unsigned int irq) ++{ ++ int pos; ++ int number_irqs; ++ u16 bitmask; ++ int pcie_port; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); ++ ++ BUG_ON(irq > INT_NUM_IM4_IRL31); ++ ++ if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { ++ return; ++ } ++ ++ /* Shift the mask to the correct bit location, not always correct ++ * Probally, the first match will be chosen. ++ */ ++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { ++ if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) ++ && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { ++ break; ++ } ++ } ++ if (pos >= IFX_MSI_IRQ_NUM) { ++ printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); ++ return; ++ } ++ spin_lock(&ifx_pcie_msi_lock); ++ /* Disable this entry */ ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); ++ spin_unlock(&ifx_pcie_msi_lock); ++ /* ++ * Count the number of IRQs we need to free by looking at the ++ * msi_multiple_irq_bitmask. Each bit set means that the next ++ * IRQ is also owned by this device. ++ */ ++ number_irqs = 0; ++ while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && ++ (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { ++ number_irqs++; ++ } ++ number_irqs++; ++ ++ /* Mask with one bit for each IRQ */ ++ bitmask = (1 << number_irqs) - 1; ++ ++ bitmask <<= pos; ++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { ++ printk(KERN_ERR "%s: Attempted to teardown MSI " ++ "interrupt (%d) not in use\n", __func__, irq); ++ return; ++ } ++ /* Checks are done, update the in use bitmask */ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; ++ msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); ++ spin_unlock(&ifx_pcie_msi_lock); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); ++} ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); ++MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_phy.c +@@ -0,0 +1,478 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_phy.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe PHY sub module ++** ++** DATE : 14 May 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 14 May,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \file ifxmips_pcie_phy.c ++ \ingroup IFX_PCIE ++ \brief PCIe PHY PLL register programming source file ++*/ ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie_reg.h" ++#include "ifxmips_pcie.h" ++ ++/* PCIe PDI only supports 16 bit operation */ ++ ++#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ ++ ((*(volatile u16 *) (__addr)) = (__data)) ++ ++#define IFX_PCIE_PHY_REG_READ16(__addr) \ ++ (*(volatile u16 *) (__addr)) ++ ++#define IFX_PCIE_PHY_REG16(__addr) \ ++ (*(volatile u16 *) (__addr)) ++ ++#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ ++ u16 read_data; \ ++ u16 write_data; \ ++ read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ ++ write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ ++ IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ ++} while (0) ++ ++#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ ++ ++//#define IFX_PCI_PHY_REG_DUMP ++ ++#ifdef IFX_PCI_PHY_REG_DUMP ++static void ++pcie_phy_reg_dump(int pcie_port) ++{ ++ printk("PLL REGFILE\n"); ++ printk("PCIE_PHY_PLL_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL4 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL5 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL6 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL7 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port))); ++ printk("PCIE_PHY_PLL_STATUS 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port))); ++ ++ printk("TX1 REGFILE\n"); ++ printk("PCIE_PHY_TX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX1_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port))); ++ printk("PCIE_PHY_TX1_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX1_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port))); ++ ++ printk("TX2 REGFILE\n"); ++ printk("PCIE_PHY_TX2_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX2_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX2_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX2_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port))); ++ ++ printk("RX1 REGFILE\n"); ++ printk("PCIE_PHY_RX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port))); ++ printk("PCIE_PHY_RX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port))); ++ printk("PCIE_PHY_RX1_CDR 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port))); ++ printk("PCIE_PHY_RX1_EI 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port))); ++ printk("PCIE_PHY_RX1_A_CTRL 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port))); ++} ++#endif /* IFX_PCI_PHY_REG_DUMP */ ++ ++static void ++pcie_phy_comm_setup(int pcie_port) ++{ ++ /* PLL Setting */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); ++ ++ /* increase the bias reference voltage */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); ++ ++ /* Endcnt */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); ++ ++ /* force */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); ++ ++ /* ctrl_lim */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); ++ ++ /* ctrl */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); ++ ++ /* RTERM*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); ++ ++ /* Improved 100MHz clock output */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); ++ ++ /* Reduced CDR BW to avoid glitches */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); ++} ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++static void ++pcie_phy_36mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE ++static void ++pcie_phy_36mhz_ssc_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ ++ /* PLL Setting */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); ++ ++ /* Increase the bias reference voltage */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); ++ ++ /* Endcnt */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); ++ ++ /* Force */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); ++ ++ /* Predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); ++ ++ /* ctrl_lim */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); ++ ++ /* ctrl */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); ++ ++ /* RTERM*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); ++ ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); ++ ++ /* improved 100MHz clock output */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); ++ ++ /* reduced CDR BW to avoid glitches */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE ++static void ++pcie_phy_25mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); ++ ++ /* en_ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE ++static void ++pcie_phy_100mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ ++ ++static int ++pcie_phy_wait_startup_ready(int pcie_port) ++{ ++ int i; ++ ++ for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { ++ if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { ++ break; ++ } ++ udelay(10); ++ } ++ if (i >= IFX_PCIE_PLL_TIMEOUT) { ++ printk(KERN_ERR "%s PLL Link timeout\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static void ++pcie_phy_load_enable(int pcie_port, int slice) ++{ ++ /* Set the load_en of tx/rx slice to '1' */ ++ switch (slice) { ++ case 1: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); ++ break; ++ case 2: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); ++ break; ++ case 3: ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); ++ break; ++ } ++} ++ ++static void ++pcie_phy_load_disable(int pcie_port, int slice) ++{ ++ /* set the load_en of tx/rx slice to '0' */ ++ switch (slice) { ++ case 1: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); ++ break; ++ case 2: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); ++ break; ++ case 3: ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); ++ break; ++ } ++} ++ ++static void ++pcie_phy_load_war(int pcie_port) ++{ ++ int slice; ++ ++ for (slice = 1; slice < 4; slice++) { ++ pcie_phy_load_enable(pcie_port, slice); ++ udelay(1); ++ pcie_phy_load_disable(pcie_port, slice); ++ } ++} ++ ++static void ++pcie_phy_tx2_modulation(int pcie_port) ++{ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); ++ mdelay(1); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); ++} ++ ++static void ++pcie_phy_tx1_modulation(int pcie_port) ++{ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); ++ mdelay(1); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); ++} ++ ++static void ++pcie_phy_tx_modulation_war(int pcie_port) ++{ ++ int i; ++ ++#define PCIE_PHY_MODULATION_NUM 5 ++ for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { ++ pcie_phy_tx2_modulation(pcie_port); ++ pcie_phy_tx1_modulation(pcie_port); ++ } ++#undef PCIE_PHY_MODULATION_NUM ++} ++ ++void ++pcie_phy_clock_mode_setup(int pcie_port) ++{ ++ pcie_pdi_big_endian(pcie_port); ++ ++ /* Enable PDI to access PCIe PHY register */ ++ pcie_pdi_pmu_enable(pcie_port); ++ ++ /* Configure PLL and PHY clock */ ++ pcie_phy_comm_setup(pcie_port); ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ pcie_phy_36mhz_mode_setup(pcie_port); ++#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) ++ pcie_phy_36mhz_ssc_mode_setup(pcie_port); ++#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) ++ pcie_phy_25mhz_mode_setup(pcie_port); ++#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) ++ pcie_phy_100mhz_mode_setup(pcie_port); ++#else ++ #error "PCIE PHY Clock Mode must be chosen first!!!!" ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ ++ ++ /* Enable PCIe PHY and make PLL setting take effect */ ++ pcie_phy_pmu_enable(pcie_port); ++ ++ /* Check if we are in startup_ready status */ ++ pcie_phy_wait_startup_ready(pcie_port); ++ ++ pcie_phy_load_war(pcie_port); ++ ++ /* Apply TX modulation workarounds */ ++ pcie_phy_tx_modulation_war(pcie_port); ++ ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++} ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_pm.c +@@ -0,0 +1,176 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_pm.c ++** PROJECT : IFX UEIP ++** MODULES : PCIE Root Complex Driver ++** ++** DATE : 21 Dec 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIE Root Complex Driver Power Managment ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 Dec,2009 Lei Chuanhua First UEIP release ++*******************************************************************************/ ++/*! ++ \defgroup IFX_PCIE_PM Power Management functions ++ \ingroup IFX_PCIE ++ \brief IFX PCIE Root Complex Driver power management functions ++*/ ++ ++/*! ++ \file ifxmips_pcie_pm.c ++ \ingroup IFX_PCIE ++ \brief source file for PCIE Root Complex Driver Power Management ++*/ ++ ++#ifndef EXPORT_SYMTAB ++#define EXPORT_SYMTAB ++#endif ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++ ++/* Project header */ ++#include ++#include ++#include ++#include ++#include "ifxmips_pcie_pm.h" ++ ++/** ++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) ++ * \brief the callback function to request pmcu state in the power management hardware-dependent module ++ * ++ * \param pmcuState This parameter is a PMCU state. ++ * ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) ++{ ++ switch(pmcuState) ++ { ++ case IFX_PMCU_STATE_D0: ++ return IFX_PMCU_RETURN_SUCCESS; ++ case IFX_PMCU_STATE_D1: // Not Applicable ++ return IFX_PMCU_RETURN_DENIED; ++ case IFX_PMCU_STATE_D2: // Not Applicable ++ return IFX_PMCU_RETURN_DENIED; ++ case IFX_PMCU_STATE_D3: // Module clock gating and Power gating ++ return IFX_PMCU_RETURN_SUCCESS; ++ default: ++ return IFX_PMCU_RETURN_DENIED; ++ } ++} ++ ++/** ++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) ++ * \brief the callback function to get pmcu state in the power management hardware-dependent module ++ ++ * \param pmcuState Pointer to return power state. ++ * ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule ++ * ++ * \param pmcuModule Module ++ * \param newState New state ++ * \param oldState Old state ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule ++ * ++ * \param pmcuModule Module ++ * \param newState New state ++ * \param oldState Old state ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn static void ifx_pcie_pmcu_init(void) ++ * \brief Register with central PMCU module ++ * \return none ++ * \ingroup IFX_PCIE_PM ++ */ ++void ++ifx_pcie_pmcu_init(void) ++{ ++ IFX_PMCU_REGISTER_t pmcuRegister; ++ ++ /* XXX, hook driver context */ ++ ++ /* State function register */ ++ memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t)); ++ pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; ++ pmcuRegister.pmcuModuleNr = 0; ++ pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change; ++ pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get; ++ pmcuRegister.pre = ifx_pcie_pmcu_prechange; ++ pmcuRegister.post= ifx_pcie_pmcu_postchange; ++ ifx_pmcu_register(&pmcuRegister); ++} ++ ++/** ++ * \fn static void ifx_pcie_pmcu_exit(void) ++ * \brief Unregister with central PMCU module ++ * ++ * \return none ++ * \ingroup IFX_PCIE_PM ++ */ ++void ++ifx_pcie_pmcu_exit(void) ++{ ++ IFX_PMCU_REGISTER_t pmcuUnRegister; ++ ++ /* XXX, hook driver context */ ++ ++ pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; ++ pmcuUnRegister.pmcuModuleNr = 0; ++ ifx_pmcu_unregister(&pmcuUnRegister); ++} ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_pm.h +@@ -0,0 +1,36 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_pm.h ++** PROJECT : IFX UEIP ++** MODULES : PCIe Root Complex Driver ++** ++** DATE : 21 Dec 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver Power Managment ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 Dec,2009 Lei Chuanhua First UEIP release ++*******************************************************************************/ ++/*! ++ \file ifxmips_pcie_pm.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe Root Complex Driver Power Management ++*/ ++ ++#ifndef IFXMIPS_PCIE_PM_H ++#define IFXMIPS_PCIE_PM_H ++ ++void ifx_pcie_pmcu_init(void); ++void ifx_pcie_pmcu_exit(void); ++ ++#endif /* IFXMIPS_PCIE_PM_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_reg.h +@@ -0,0 +1,1001 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_reg.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_REG_H ++#define IFXMIPS_PCIE_REG_H ++/*! ++ \file ifxmips_pcie_reg.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module register definition ++*/ ++/* PCIe Address Mapping Base */ ++#define PCIE_CFG_PHY_BASE 0x1D000000UL ++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) ++#define PCIE_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE_MEM_PHY_BASE 0x1C000000UL ++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) ++#define PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) ++ ++#define PCIE_IO_PHY_BASE 0x1D800000UL ++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) ++#define PCIE_IO_SIZE (1 * 1024 * 1024) ++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) ++ ++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) ++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) ++#define PCIE_MSI_PHY_BASE 0x1F600000UL ++ ++#define PCIE_PDI_PHY_BASE 0x1F106800UL ++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) ++#define PCIE_PDI_SIZE 0x400 ++ ++#define PCIE1_CFG_PHY_BASE 0x19000000UL ++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) ++#define PCIE1_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE1_MEM_PHY_BASE 0x18000000UL ++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) ++#define PCIE1_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) ++ ++#define PCIE1_IO_PHY_BASE 0x19800000UL ++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) ++#define PCIE1_IO_SIZE (1 * 1024 * 1024) ++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) ++ ++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) ++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) ++#define PCIE1_MSI_PHY_BASE 0x1F400000UL ++ ++#define PCIE1_PDI_PHY_BASE 0x1F700400UL ++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) ++#define PCIE1_PDI_SIZE 0x400 ++ ++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) ++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) ++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) ++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) ++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) ++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) ++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) ++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) ++ ++/* PCIe Application Logic Register */ ++/* RC Core Control Register */ ++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) ++/* This should be enabled after initializing configuratin registers ++ * Also should check link status retraining bit ++ */ ++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ ++ ++/* RC Core Debug Register */ ++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) ++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 ++ ++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ ++#define PCIE_RC_DR_PM_DEV_STATE_S 9 ++ ++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ ++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ ++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ ++ ++/* Current Power State Definition */ ++enum { ++ PCIE_RC_DR_D0 = 0, ++ PCIE_RC_DR_D1, /* Not supported */ ++ PCIE_RC_DR_D2, /* Not supported */ ++ PCIE_RC_DR_D3, ++ PCIE_RC_DR_UN, ++}; ++ ++/* PHY Link Status Register */ ++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) ++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ ++ ++/* Electromechanical Control Register */ ++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) ++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ ++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ ++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ ++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ ++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ ++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ ++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ ++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ ++ ++/* Interrupt Status Register */ ++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) ++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ ++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ ++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ ++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ ++#define PCIE_IR_SR_AHB_LU_ERR_S 4 ++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ ++#define PCIE_IR_SR_INT_MSG_NUM_S 9 ++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 ++ ++/* Message Control Register */ ++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) ++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ ++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ ++ ++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) ++ ++/* Vendor-Defined Message Requester ID Register */ ++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) ++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF ++#define PCIE_VDM_RID_VDMRID_S 0 ++ ++/* ASPM Control Register */ ++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) ++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ ++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ ++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ ++ ++/* Vendor Message DW0 Register */ ++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) ++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ ++#define PCIE_VM_MSG_DW0_TYPE_S 0 ++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ ++#define PCIE_VM_MSG_DW0_FORMAT_S 5 ++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ ++#define PCIE_VM_MSG_DW0_TC_S 12 ++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ ++#define PCIE_VM_MSG_DW0_ATTR_S 18 ++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ ++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ ++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ ++#define PCIE_VM_MSG_DW0_LEN_S 22 ++ ++/* Format Definition */ ++enum { ++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ ++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ ++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ ++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ ++}; ++ ++/* Traffic Class Definition */ ++enum { ++ PCIE_VM_MSG_TC0 = 0, ++ PCIE_VM_MSG_TC1, ++ PCIE_VM_MSG_TC2, ++ PCIE_VM_MSG_TC3, ++ PCIE_VM_MSG_TC4, ++ PCIE_VM_MSG_TC5, ++ PCIE_VM_MSG_TC6, ++ PCIE_VM_MSG_TC7, ++}; ++ ++/* Attributes Definition */ ++enum { ++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ ++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ ++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ ++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ ++}; ++ ++/* Payload Size Definition */ ++#define PCIE_VM_MSG_LEN_MIN 0 ++#define PCIE_VM_MSG_LEN_MAX 1024 ++ ++/* Vendor Message DW1 Register */ ++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) ++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ ++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 ++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ ++#define PCIE_VM_MSG_DW1_CODE_S 16 ++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ ++#define PCIE_VM_MSG_DW1_TAG_S 24 ++ ++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) ++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) ++ ++/* Vendor Message Request Register */ ++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) ++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ ++ ++ ++/* AHB Slave Side Band Control Register */ ++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) ++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ ++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ ++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ ++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ ++#define PCIE_AHB_SSB_REQ_ATTR_S 3 ++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ ++#define PCIE_AHB_SSB_REQ_TC_S 5 ++ ++/* AHB Master SideBand Ctrl Register */ ++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) ++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ ++#define PCIE_AHB_MSB_RESP_ATTR_S 0 ++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ ++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ ++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ ++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 ++ ++/* AHB Control Register, fixed bus enumeration exception */ ++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) ++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 ++ ++/* Interrupt Enalbe Register */ ++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) ++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) ++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) ++ ++/* PCIe interrupt enable/control/capture register definition */ ++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ ++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ ++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ ++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ ++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ ++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ ++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ ++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ ++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ ++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ ++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ ++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ ++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ ++#define PCIE_IRN_INTA 0x00002000 /* INTA */ ++#define PCIE_IRN_INTB 0x00004000 /* INTB */ ++#define PCIE_IRN_INTC 0x00008000 /* INTC */ ++#define PCIE_IRN_INTD 0x00010000 /* INTD */ ++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ ++ ++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ ++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ ++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ ++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ ++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) ++/* PCIe RC Configuration Register */ ++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) ++ ++/* Bit definition from pci_reg.h */ ++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) ++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) ++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ ++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ ++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ ++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ ++ ++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ ++/* Bus Number Register bits */ ++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF ++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 ++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 ++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 ++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 ++#define PCIE_PNR_SUB_BUS_NUM_S 16 ++ ++/* IO Base/Limit Register bits */ ++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ ++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 ++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 ++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 ++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 ++ ++/* Non-prefetchable Memory Base/Limit Register bit */ ++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ ++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 ++#define PCIE_MBML_MEM_BASE_ADDR_S 4 ++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 ++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 ++ ++/* Prefetchable Memory Base/Limit Register bit */ ++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ ++#define PCIE_PMBL_64BIT_ADDR 0x00000001 ++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 ++#define PCIE_PMBL_UPPER_12BIT_S 4 ++#define PCIE_PMBL_E64MA 0x00010000 ++#define PCIE_PMBL_END_ADDR 0xFFF00000 ++#define PCIE_PMBL_END_ADDR_S 20 ++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ ++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ ++ ++/* I/O Base/Limit Upper 16 bits register */ ++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 ++ ++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) ++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) ++ ++/* Interrupt and Secondary Bridge Control Register */ ++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) ++ ++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF ++#define PCIE_INTRBCTRL_INT_LINE_S 0 ++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 ++#define PCIE_INTRBCTRL_INT_PIN_S 8 ++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ ++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ ++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ ++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ ++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ ++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ ++/* Others are read only */ ++enum { ++ PCIE_INTRBCTRL_INT_NON = 0, ++ PCIE_INTRBCTRL_INTA, ++ PCIE_INTRBCTRL_INTB, ++ PCIE_INTRBCTRL_INTC, ++ PCIE_INTRBCTRL_INTD, ++}; ++ ++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) ++ ++/* Power Management Control and Status Register */ ++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) ++ ++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ ++#define PCIE_PM_CSR_POWER_STATE_S 0 ++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ ++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ ++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ ++ ++/* MSI Capability Register for EP */ ++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) ++ ++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ ++#define PCIE_MCAPR_MSI_CAP_ID_S 0 ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 ++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 ++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ ++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 ++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ ++ ++/* MSI Message Address Register */ ++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) ++ ++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ ++ ++/* MSI Message Upper Address Register */ ++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) ++ ++/* MSI Message Data Register */ ++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) ++ ++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ ++#define PCIE_MD_DATA_S 0 ++ ++/* PCI Express Capability Register */ ++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) ++ ++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ ++#define PCIE_XCAP_ID_S 0 ++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_XCAP_NEXT_CAP_S 8 ++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ ++#define PCIE_XCAP_VER_S 16 ++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ ++#define PCIE_XCAP_DEV_PORT_TYPE_S 20 ++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ ++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ ++#define PCIE_XCAP_MSG_INT_NUM_S 25 ++ ++/* Device Capability Register */ ++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) ++ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 ++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ ++#define PCIE_DCAP_PHANTOM_FUNC_S 3 ++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ ++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ ++#define PCIE_DCAP_EP_L0S_LATENCY_S 6 ++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ ++#define PCIE_DCAP_EP_L1_LATENCY_S 9 ++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ ++ ++/* Maximum payload size supported */ ++enum { ++ PCIE_MAX_PAYLOAD_128 = 0, ++ PCIE_MAX_PAYLOAD_256, ++ PCIE_MAX_PAYLOAD_512, ++ PCIE_MAX_PAYLOAD_1024, ++ PCIE_MAX_PAYLOAD_2048, ++ PCIE_MAX_PAYLOAD_4096, ++}; ++ ++/* Device Control and Status Register */ ++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) ++ ++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ ++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ ++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ ++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 ++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ ++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ ++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ ++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 ++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ ++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ ++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ ++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ ++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ ++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ ++ ++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ ++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ ++ PCIE_DCTLSYS_UR_REQ_EN) ++ ++/* Link Capability Register */ ++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) ++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ ++#define PCIE_LCAP_MAX_LINK_SPEED_S 0 ++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ ++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 ++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ ++#define PCIE_LCAP_ASPM_LEVEL_S 10 ++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ ++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 ++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ ++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 ++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ ++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ ++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ ++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ ++#define PCIE_LCAP_PORT_NUM_S 24 ++ ++/* Maximum Length width definition */ ++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 ++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ ++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 ++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 ++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 ++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C ++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 ++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 ++ ++/* Active State Link PM definition */ ++enum { ++ PCIE_ASPM_RES0 = 0, ++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ ++ PCIE_ASPM_RES1, ++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ ++}; ++ ++/* L0s Exit Latency definition */ ++enum { ++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ ++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ ++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ ++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ ++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ ++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ ++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ ++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ ++}; ++ ++/* L1 Exit Latency definition */ ++enum { ++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ ++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ ++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ ++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ ++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ ++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ ++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ ++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ ++}; ++ ++/* Link Control and Status Register */ ++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) ++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ ++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 ++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ ++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ ++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ ++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ ++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ ++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ ++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ ++#define PCIE_LCTLSTS_LINK_SPEED_S 16 ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 ++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ ++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ ++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ ++ ++/* Slot Capabilities Register */ ++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) ++ ++/* Slot Capabilities */ ++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) ++ ++/* Root Control and Capability Register */ ++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) ++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ ++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ ++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ ++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ ++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ ++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) ++/* Root Status Register */ ++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) ++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ ++#define PCIE_RSTS_PME_REQ_ID_S 0 ++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ ++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ ++ ++/* PCI Express Enhanced Capability Header */ ++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) ++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ ++#define PCIE_ENHANCED_CAP_ID_S 0 ++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ ++#define PCIE_ENHANCED_CAP_VER_S 16 ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 ++ ++/* Uncorrectable Error Status Register */ ++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) ++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ ++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ ++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ ++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ ++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ ++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ ++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ ++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ ++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ ++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ ++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ ++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ ++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ ++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ ++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) ++ ++/* Uncorrectable Error Mask Register, Mask means no report */ ++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) ++ ++/* Uncorrectable Error Severity Register */ ++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) ++ ++/* Correctable Error Status Register */ ++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) ++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ ++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ ++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ ++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ ++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ ++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ ++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ ++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) ++ ++/* Correctable Error Mask Register */ ++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) ++ ++/* Advanced Error Capabilities and Control Register */ ++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) ++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ ++#define PCIE_AECCR_FIRST_ERR_PTR_S 0 ++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ ++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ ++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ ++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ ++ ++/* Header Log Register 1 */ ++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) ++ ++/* Header Log Register 2 */ ++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) ++ ++/* Header Log Register 3 */ ++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) ++ ++/* Header Log Register 4 */ ++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) ++ ++/* Root Error Command Register */ ++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) ++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ ++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ ++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ ++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) ++ ++/* Root Error Status Register */ ++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) ++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ ++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ ++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ ++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ ++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ ++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_RESR_AER_INT_MSG_NUM_S 27 ++ ++/* Error Source Indentification Register */ ++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 ++ ++/* VC Enhanced Capability Header */ ++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) ++ ++/* Port VC Capability Register */ ++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) ++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ ++#define PCIE_PVC1_EXT_VC_CNT_S 0 ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 ++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ ++#define PCIE_PVC1_REF_CLK_S 8 ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 ++ ++/* Extended Virtual Channel Count Defintion */ ++#define PCIE_EXT_VC_CNT_MIN 0 ++#define PCIE_EXT_VC_CNT_MAX 7 ++ ++/* Port Arbitration Table Entry Size Definition */ ++enum { ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, ++}; ++ ++/* Port VC Capability Register 2 */ ++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) ++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ ++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 ++ ++/* Port VC Control and Status Register */ ++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) ++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ ++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ ++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 ++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ ++ ++/* VC0 Resource Capability Register */ ++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) ++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ ++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ ++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ ++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) ++ ++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 ++ ++/* VC0 Resource Control Register */ ++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) ++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ ++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ ++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ ++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ ++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ ++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ ++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ ++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ ++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ ++ ++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 ++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ ++#define PCIE_VC0_RC0_VC_ID_S 24 ++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ ++ ++/* VC0 Resource Status Register */ ++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) ++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ ++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ ++ ++/* Ack Latency Timer and Replay Timer Register */ ++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 ++ ++/* Other Message Register */ ++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) ++ ++/* Port Force Link Register */ ++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) ++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ ++#define PCIE_PFLR_LINK_NUM_S 0 ++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ ++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ ++#define PCIE_PFLR_LINK_STATE_S 16 ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 ++ ++/* Ack Frequency Register */ ++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) ++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ ++#define PCIE_AFR_AF_S 0 ++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ ++#define PCIE_AFR_FTS_NUM_S 8 ++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ ++#define PCIE_AFR_COM_FTS_NUM_S 16 ++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ ++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 ++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ ++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 ++#define PCIE_AFR_FTS_NUM_DEFAULT 32 ++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 ++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 ++ ++/* Port Link Control Register */ ++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) ++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ ++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ ++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ ++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ ++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ ++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ ++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ ++#define PCIE_PLCR_LINK_MODE_S 16 ++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ ++ ++/* Lane Skew Register */ ++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) ++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ ++#define PCIE_LSR_LANE_SKEW_NUM_S 0 ++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ ++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ ++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ ++ ++/* Symbol Number Register */ ++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) ++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ ++#define PCIE_SNR_TS_S 0 ++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ ++#define PCIE_SNR_SKP_S 8 ++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ ++#define PCIE_SNR_REPLAY_TIMER_S 14 ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 ++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ ++#define PCIE_SNR_FC_TIMER_S 28 ++ ++/* Symbol Timer Register and Filter Mask Register 1 */ ++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) ++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ ++#define PCIE_STRFMR_SKP_INTERVAL_S 0 ++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ ++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ ++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ ++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ ++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ ++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ ++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ ++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ ++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ ++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ ++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ ++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ ++ ++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ ++ ++/* Filter Masker Register 2 */ ++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) ++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ ++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ ++ ++/* Debug Register 0 */ ++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) ++ ++/* Debug Register 1 */ ++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) ++ ++/* Transmit Posted FC Credit Status Register */ ++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Non-Posted FC Credit Status */ ++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Complete FC Credit Status Register */ ++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 ++ ++/* Queue Status Register */ ++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) ++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ ++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ ++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ ++ ++/* VC Transmit Arbitration Register 1 */ ++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) ++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ ++ ++/* VC Transmit Arbitration Register 2 */ ++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) ++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ ++ ++/* VC0 Posted Receive Queue Control Register */ ++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 ++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ ++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ ++ ++/* VC0 Non-Posted Receive Queue Control */ ++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 ++ ++/* VC0 Completion Receive Queue Control */ ++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 ++ ++/* Applicable to the above three registers */ ++enum { ++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, ++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, ++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, ++}; ++ ++/* VC0 Posted Buffer Depth Register */ ++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Non-Posted Buffer Depth Register */ ++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Completion Buffer Depth Register */ ++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 ++ ++/* PHY Status Register, all zeros in VR9 */ ++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) ++ ++/* PHY Control Register, all zeros in VR9 */ ++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) ++ ++/* ++ * PCIe PDI PHY register definition, suppose all the following ++ * stuff is confidential. ++ * XXX, detailed bit definition ++ */ ++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) ++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) ++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) ++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) ++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) ++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) ++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) ++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) ++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) ++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) ++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) ++ ++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) ++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) ++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) ++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) ++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) ++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) ++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) ++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) ++ ++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) ++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) ++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) ++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) ++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) ++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) ++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) ++ ++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) ++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) ++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) ++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) ++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) ++ ++/* Interrupt related stuff */ ++#define PCIE_LEGACY_DISABLE 0 ++#define PCIE_LEGACY_INTA 1 ++#define PCIE_LEGACY_INTB 2 ++#define PCIE_LEGACY_INTC 3 ++#define PCIE_LEGACY_INTD 4 ++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD ++ ++#endif /* IFXMIPS_PCIE_REG_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_vr9.h +@@ -0,0 +1,269 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++/*! ++ \file ifxmips_pcie_vr9.h ++ \ingroup IFX_PCIE ++ \brief PCIe RC driver vr9 specific file ++*/ ++ ++#ifndef IFXMIPS_PCIE_VR9_H ++#define IFXMIPS_PCIE_VR9_H ++ ++#include ++#include ++ ++#include ++#include ++ ++#define IFX_PCIE_GPIO_RESET 494 ++ ++#define IFX_REG_R32 ltq_r32 ++#define IFX_REG_W32 ltq_w32 ++#define CONFIG_IFX_PCIE_HW_SWAP ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ ++#define IFX_PMU1_MODULE_PCIE_PHY (0) ++#define IFX_PMU1_MODULE_PCIE_CTRL (1) ++#define IFX_PMU1_MODULE_PDI (4) ++#define IFX_PMU1_MODULE_MSI (5) ++ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++ ++#define IFX_GPIO (KSEG1 | 0x1E100B00) ++#define ALT0 ((volatile u32*)(IFX_GPIO + 0x007c)) ++#define ALT1 ((volatile u32*)(IFX_GPIO + 0x0080)) ++#define OD ((volatile u32*)(IFX_GPIO + 0x0084)) ++#define DIR ((volatile u32*)(IFX_GPIO + 0x0078)) ++#define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) ++ ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ ++ gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); ++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); ++ gpio_set_value(IFX_PCIE_GPIO_RESET, 1); ++ ++/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ /* Enable AHB bus master/slave */ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "ahb"); ++ clk_enable(clk); ++ ++ //AHBM_PMU_SETUP(IFX_PMU_ENABLE); ++ //AHBS_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg |= IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#else ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg &= ~IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "phy"); ++ clk_enable(clk); ++ ++ //PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_phy_pmu_disable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "phy"); ++ clk_disable(clk); ++ ++// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++} ++ ++static inline void pcie_pdi_big_endian(int pcie_port) ++{ ++ u32 reg; ++ ++ /* SRAM2PDI endianness control. */ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_AHB_BE_PCIE_PDI; ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ /* Enable PDI to access PCIe PHY register */ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "pdi"); ++ clk_enable(clk); ++ //PDI_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_core_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ ++ /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ ++ reg |= 0x00400000; ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_core_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ /* Reset PCIe PHY & Core, bit 22 */ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg &= ~0x00400000; ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg |= 0x00001000; /* Bit 12 */ ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg &= ~0x00001000; /* Bit 12 */ ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ gpio_set_value(IFX_PCIE_GPIO_RESET, 0); ++// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); ++// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); ++ //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++} ++ ++static inline void pcie_core_pmu_setup(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "ctl"); ++ clk_enable(clk); ++ clk = clk_get_sys("1d900000.pcie", "bus"); ++ clk_enable(clk); ++ ++ /* PCIe Core controller enabled */ ++// PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ ++ /* Enable PCIe L0 Clock */ ++// PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_msi_init(int pcie_port) ++{ ++ struct clk *clk; ++ pcie_msi_pic_init(pcie_port); ++ clk = clk_get_sys("ltq_pcie", "msi"); ++ clk_enable(clk); ++// MSI_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline u32 ++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) ++{ ++ u32 tbus_number = bus_number; ++ ++#ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++#endif /* CONFIG_PCI_LANTIQ */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ #endif /* CONFIG_PCI_LANTIQ */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_VR9_H */ ++ +--- a/arch/mips/pci/pci-legacy.c ++++ b/arch/mips/pci/pci-legacy.c +@@ -305,3 +305,30 @@ char *__init pcibios_setup(char *str) + return pcibios_plat_setup(str); + return str; + } ++ ++int pcibios_host_nr(void) ++{ ++ int count = 0; ++ struct pci_controller *hose; ++ list_for_each_entry(hose, &controllers, list) { ++ count++; ++ } ++ return count; ++} ++EXPORT_SYMBOL(pcibios_host_nr); ++ ++int pcibios_1st_host_bus_nr(void) ++{ ++ int bus_nr = 0; ++ struct pci_controller *hose; ++ ++ hose = list_first_entry_or_null(&controllers, struct pci_controller, list); ++ ++ if (hose != NULL) { ++ if (hose->bus != NULL) { ++ bus_nr = hose->bus->number + 1; ++ } ++ } ++ return bus_nr; ++} ++EXPORT_SYMBOL(pcibios_1st_host_bus_nr); +--- /dev/null ++++ b/arch/mips/pci/pcie-lantiq.h +@@ -0,0 +1,1301 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_reg.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_REG_H ++#define IFXMIPS_PCIE_REG_H ++#include ++#include ++#include ++#include ++/*! ++ \file ifxmips_pcie_reg.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module register definition ++*/ ++/* PCIe Address Mapping Base */ ++#define PCIE_CFG_PHY_BASE 0x1D000000UL ++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) ++#define PCIE_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE_MEM_PHY_BASE 0x1C000000UL ++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) ++#define PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) ++ ++#define PCIE_IO_PHY_BASE 0x1D800000UL ++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) ++#define PCIE_IO_SIZE (1 * 1024 * 1024) ++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) ++ ++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) ++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) ++#define PCIE_MSI_PHY_BASE 0x1F600000UL ++ ++#define PCIE_PDI_PHY_BASE 0x1F106800UL ++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) ++#define PCIE_PDI_SIZE 0x400 ++ ++#define PCIE1_CFG_PHY_BASE 0x19000000UL ++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) ++#define PCIE1_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE1_MEM_PHY_BASE 0x18000000UL ++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) ++#define PCIE1_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) ++ ++#define PCIE1_IO_PHY_BASE 0x19800000UL ++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) ++#define PCIE1_IO_SIZE (1 * 1024 * 1024) ++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) ++ ++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) ++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) ++#define PCIE1_MSI_PHY_BASE 0x1F400000UL ++ ++#define PCIE1_PDI_PHY_BASE 0x1F700400UL ++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) ++#define PCIE1_PDI_SIZE 0x400 ++ ++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) ++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) ++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) ++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) ++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) ++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) ++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) ++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) ++ ++/* PCIe Application Logic Register */ ++/* RC Core Control Register */ ++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) ++/* This should be enabled after initializing configuratin registers ++ * Also should check link status retraining bit ++ */ ++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ ++ ++/* RC Core Debug Register */ ++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) ++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 ++ ++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ ++#define PCIE_RC_DR_PM_DEV_STATE_S 9 ++ ++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ ++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ ++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ ++ ++/* Current Power State Definition */ ++enum { ++ PCIE_RC_DR_D0 = 0, ++ PCIE_RC_DR_D1, /* Not supported */ ++ PCIE_RC_DR_D2, /* Not supported */ ++ PCIE_RC_DR_D3, ++ PCIE_RC_DR_UN, ++}; ++ ++/* PHY Link Status Register */ ++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) ++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ ++ ++/* Electromechanical Control Register */ ++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) ++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ ++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ ++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ ++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ ++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ ++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ ++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ ++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ ++ ++/* Interrupt Status Register */ ++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) ++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ ++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ ++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ ++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ ++#define PCIE_IR_SR_AHB_LU_ERR_S 4 ++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ ++#define PCIE_IR_SR_INT_MSG_NUM_S 9 ++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 ++ ++/* Message Control Register */ ++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) ++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ ++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ ++ ++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) ++ ++/* Vendor-Defined Message Requester ID Register */ ++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) ++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF ++#define PCIE_VDM_RID_VDMRID_S 0 ++ ++/* ASPM Control Register */ ++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) ++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ ++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ ++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ ++ ++/* Vendor Message DW0 Register */ ++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) ++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ ++#define PCIE_VM_MSG_DW0_TYPE_S 0 ++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ ++#define PCIE_VM_MSG_DW0_FORMAT_S 5 ++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ ++#define PCIE_VM_MSG_DW0_TC_S 12 ++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ ++#define PCIE_VM_MSG_DW0_ATTR_S 18 ++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ ++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ ++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ ++#define PCIE_VM_MSG_DW0_LEN_S 22 ++ ++/* Format Definition */ ++enum { ++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ ++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ ++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ ++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ ++}; ++ ++/* Traffic Class Definition */ ++enum { ++ PCIE_VM_MSG_TC0 = 0, ++ PCIE_VM_MSG_TC1, ++ PCIE_VM_MSG_TC2, ++ PCIE_VM_MSG_TC3, ++ PCIE_VM_MSG_TC4, ++ PCIE_VM_MSG_TC5, ++ PCIE_VM_MSG_TC6, ++ PCIE_VM_MSG_TC7, ++}; ++ ++/* Attributes Definition */ ++enum { ++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ ++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ ++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ ++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ ++}; ++ ++/* Payload Size Definition */ ++#define PCIE_VM_MSG_LEN_MIN 0 ++#define PCIE_VM_MSG_LEN_MAX 1024 ++ ++/* Vendor Message DW1 Register */ ++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) ++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ ++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 ++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ ++#define PCIE_VM_MSG_DW1_CODE_S 16 ++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ ++#define PCIE_VM_MSG_DW1_TAG_S 24 ++ ++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) ++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) ++ ++/* Vendor Message Request Register */ ++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) ++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ ++ ++ ++/* AHB Slave Side Band Control Register */ ++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) ++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ ++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ ++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ ++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ ++#define PCIE_AHB_SSB_REQ_ATTR_S 3 ++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ ++#define PCIE_AHB_SSB_REQ_TC_S 5 ++ ++/* AHB Master SideBand Ctrl Register */ ++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) ++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ ++#define PCIE_AHB_MSB_RESP_ATTR_S 0 ++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ ++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ ++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ ++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 ++ ++/* AHB Control Register, fixed bus enumeration exception */ ++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) ++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 ++ ++/* Interrupt Enalbe Register */ ++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) ++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) ++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) ++ ++/* PCIe interrupt enable/control/capture register definition */ ++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ ++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ ++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ ++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ ++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ ++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ ++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ ++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ ++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ ++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ ++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ ++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ ++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ ++#define PCIE_IRN_INTA 0x00002000 /* INTA */ ++#define PCIE_IRN_INTB 0x00004000 /* INTB */ ++#define PCIE_IRN_INTC 0x00008000 /* INTC */ ++#define PCIE_IRN_INTD 0x00010000 /* INTD */ ++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ ++ ++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ ++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ ++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ ++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ ++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) ++/* PCIe RC Configuration Register */ ++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) ++ ++/* Bit definition from pci_reg.h */ ++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) ++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) ++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ ++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ ++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ ++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ ++ ++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ ++/* Bus Number Register bits */ ++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF ++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 ++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 ++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 ++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 ++#define PCIE_PNR_SUB_BUS_NUM_S 16 ++ ++/* IO Base/Limit Register bits */ ++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ ++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 ++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 ++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 ++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 ++ ++/* Non-prefetchable Memory Base/Limit Register bit */ ++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ ++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 ++#define PCIE_MBML_MEM_BASE_ADDR_S 4 ++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 ++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 ++ ++/* Prefetchable Memory Base/Limit Register bit */ ++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ ++#define PCIE_PMBL_64BIT_ADDR 0x00000001 ++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 ++#define PCIE_PMBL_UPPER_12BIT_S 4 ++#define PCIE_PMBL_E64MA 0x00010000 ++#define PCIE_PMBL_END_ADDR 0xFFF00000 ++#define PCIE_PMBL_END_ADDR_S 20 ++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ ++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ ++ ++/* I/O Base/Limit Upper 16 bits register */ ++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 ++ ++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) ++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) ++ ++/* Interrupt and Secondary Bridge Control Register */ ++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) ++ ++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF ++#define PCIE_INTRBCTRL_INT_LINE_S 0 ++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 ++#define PCIE_INTRBCTRL_INT_PIN_S 8 ++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ ++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ ++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ ++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ ++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ ++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ ++/* Others are read only */ ++enum { ++ PCIE_INTRBCTRL_INT_NON = 0, ++ PCIE_INTRBCTRL_INTA, ++ PCIE_INTRBCTRL_INTB, ++ PCIE_INTRBCTRL_INTC, ++ PCIE_INTRBCTRL_INTD, ++}; ++ ++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) ++ ++/* Power Management Control and Status Register */ ++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) ++ ++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ ++#define PCIE_PM_CSR_POWER_STATE_S 0 ++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ ++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ ++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ ++ ++/* MSI Capability Register for EP */ ++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) ++ ++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ ++#define PCIE_MCAPR_MSI_CAP_ID_S 0 ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 ++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 ++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ ++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 ++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ ++ ++/* MSI Message Address Register */ ++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) ++ ++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ ++ ++/* MSI Message Upper Address Register */ ++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) ++ ++/* MSI Message Data Register */ ++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) ++ ++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ ++#define PCIE_MD_DATA_S 0 ++ ++/* PCI Express Capability Register */ ++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) ++ ++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ ++#define PCIE_XCAP_ID_S 0 ++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_XCAP_NEXT_CAP_S 8 ++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ ++#define PCIE_XCAP_VER_S 16 ++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ ++#define PCIE_XCAP_DEV_PORT_TYPE_S 20 ++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ ++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ ++#define PCIE_XCAP_MSG_INT_NUM_S 25 ++ ++/* Device Capability Register */ ++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) ++ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 ++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ ++#define PCIE_DCAP_PHANTOM_FUNC_S 3 ++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ ++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ ++#define PCIE_DCAP_EP_L0S_LATENCY_S 6 ++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ ++#define PCIE_DCAP_EP_L1_LATENCY_S 9 ++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ ++ ++/* Maximum payload size supported */ ++enum { ++ PCIE_MAX_PAYLOAD_128 = 0, ++ PCIE_MAX_PAYLOAD_256, ++ PCIE_MAX_PAYLOAD_512, ++ PCIE_MAX_PAYLOAD_1024, ++ PCIE_MAX_PAYLOAD_2048, ++ PCIE_MAX_PAYLOAD_4096, ++}; ++ ++/* Device Control and Status Register */ ++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) ++ ++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ ++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ ++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ ++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 ++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ ++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ ++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ ++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 ++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ ++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ ++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ ++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ ++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ ++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ ++ ++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ ++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ ++ PCIE_DCTLSYS_UR_REQ_EN) ++ ++/* Link Capability Register */ ++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) ++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ ++#define PCIE_LCAP_MAX_LINK_SPEED_S 0 ++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ ++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 ++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ ++#define PCIE_LCAP_ASPM_LEVEL_S 10 ++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ ++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 ++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ ++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 ++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ ++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ ++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ ++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ ++#define PCIE_LCAP_PORT_NUM_S 24 ++ ++/* Maximum Length width definition */ ++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 ++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ ++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 ++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 ++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 ++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C ++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 ++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 ++ ++/* Active State Link PM definition */ ++enum { ++ PCIE_ASPM_RES0 = 0, ++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ ++ PCIE_ASPM_RES1, ++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ ++}; ++ ++/* L0s Exit Latency definition */ ++enum { ++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ ++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ ++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ ++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ ++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ ++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ ++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ ++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ ++}; ++ ++/* L1 Exit Latency definition */ ++enum { ++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ ++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ ++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ ++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ ++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ ++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ ++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ ++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ ++}; ++ ++/* Link Control and Status Register */ ++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) ++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ ++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 ++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ ++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ ++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ ++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ ++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ ++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ ++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ ++#define PCIE_LCTLSTS_LINK_SPEED_S 16 ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 ++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ ++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ ++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ ++ ++/* Slot Capabilities Register */ ++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) ++ ++/* Slot Capabilities */ ++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) ++ ++/* Root Control and Capability Register */ ++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) ++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ ++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ ++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ ++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ ++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ ++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) ++/* Root Status Register */ ++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) ++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ ++#define PCIE_RSTS_PME_REQ_ID_S 0 ++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ ++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ ++ ++/* PCI Express Enhanced Capability Header */ ++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) ++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ ++#define PCIE_ENHANCED_CAP_ID_S 0 ++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ ++#define PCIE_ENHANCED_CAP_VER_S 16 ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 ++ ++/* Uncorrectable Error Status Register */ ++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) ++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ ++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ ++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ ++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ ++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ ++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ ++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ ++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ ++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ ++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ ++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ ++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ ++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ ++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ ++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) ++ ++/* Uncorrectable Error Mask Register, Mask means no report */ ++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) ++ ++/* Uncorrectable Error Severity Register */ ++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) ++ ++/* Correctable Error Status Register */ ++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) ++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ ++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ ++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ ++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ ++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ ++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ ++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ ++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) ++ ++/* Correctable Error Mask Register */ ++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) ++ ++/* Advanced Error Capabilities and Control Register */ ++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) ++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ ++#define PCIE_AECCR_FIRST_ERR_PTR_S 0 ++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ ++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ ++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ ++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ ++ ++/* Header Log Register 1 */ ++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) ++ ++/* Header Log Register 2 */ ++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) ++ ++/* Header Log Register 3 */ ++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) ++ ++/* Header Log Register 4 */ ++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) ++ ++/* Root Error Command Register */ ++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) ++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ ++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ ++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ ++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) ++ ++/* Root Error Status Register */ ++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) ++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ ++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ ++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ ++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ ++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ ++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_RESR_AER_INT_MSG_NUM_S 27 ++ ++/* Error Source Indentification Register */ ++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 ++ ++/* VC Enhanced Capability Header */ ++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) ++ ++/* Port VC Capability Register */ ++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) ++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ ++#define PCIE_PVC1_EXT_VC_CNT_S 0 ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 ++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ ++#define PCIE_PVC1_REF_CLK_S 8 ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 ++ ++/* Extended Virtual Channel Count Defintion */ ++#define PCIE_EXT_VC_CNT_MIN 0 ++#define PCIE_EXT_VC_CNT_MAX 7 ++ ++/* Port Arbitration Table Entry Size Definition */ ++enum { ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, ++}; ++ ++/* Port VC Capability Register 2 */ ++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) ++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ ++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 ++ ++/* Port VC Control and Status Register */ ++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) ++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ ++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ ++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 ++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ ++ ++/* VC0 Resource Capability Register */ ++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) ++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ ++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ ++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ ++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) ++ ++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 ++ ++/* VC0 Resource Control Register */ ++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) ++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ ++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ ++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ ++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ ++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ ++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ ++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ ++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ ++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ ++ ++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 ++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ ++#define PCIE_VC0_RC0_VC_ID_S 24 ++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ ++ ++/* VC0 Resource Status Register */ ++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) ++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ ++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ ++ ++/* Ack Latency Timer and Replay Timer Register */ ++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 ++ ++/* Other Message Register */ ++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) ++ ++/* Port Force Link Register */ ++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) ++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ ++#define PCIE_PFLR_LINK_NUM_S 0 ++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ ++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ ++#define PCIE_PFLR_LINK_STATE_S 16 ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 ++ ++/* Ack Frequency Register */ ++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) ++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ ++#define PCIE_AFR_AF_S 0 ++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ ++#define PCIE_AFR_FTS_NUM_S 8 ++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ ++#define PCIE_AFR_COM_FTS_NUM_S 16 ++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ ++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 ++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ ++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 ++#define PCIE_AFR_FTS_NUM_DEFAULT 32 ++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 ++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 ++ ++/* Port Link Control Register */ ++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) ++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ ++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ ++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ ++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ ++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ ++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ ++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ ++#define PCIE_PLCR_LINK_MODE_S 16 ++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ ++ ++/* Lane Skew Register */ ++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) ++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ ++#define PCIE_LSR_LANE_SKEW_NUM_S 0 ++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ ++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ ++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ ++ ++/* Symbol Number Register */ ++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) ++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ ++#define PCIE_SNR_TS_S 0 ++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ ++#define PCIE_SNR_SKP_S 8 ++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ ++#define PCIE_SNR_REPLAY_TIMER_S 14 ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 ++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ ++#define PCIE_SNR_FC_TIMER_S 28 ++ ++/* Symbol Timer Register and Filter Mask Register 1 */ ++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) ++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ ++#define PCIE_STRFMR_SKP_INTERVAL_S 0 ++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ ++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ ++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ ++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ ++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ ++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ ++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ ++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ ++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ ++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ ++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ ++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ ++ ++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ ++ ++/* Filter Masker Register 2 */ ++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) ++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ ++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ ++ ++/* Debug Register 0 */ ++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) ++ ++/* Debug Register 1 */ ++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) ++ ++/* Transmit Posted FC Credit Status Register */ ++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Non-Posted FC Credit Status */ ++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Complete FC Credit Status Register */ ++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 ++ ++/* Queue Status Register */ ++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) ++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ ++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ ++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ ++ ++/* VC Transmit Arbitration Register 1 */ ++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) ++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ ++ ++/* VC Transmit Arbitration Register 2 */ ++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) ++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ ++ ++/* VC0 Posted Receive Queue Control Register */ ++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 ++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ ++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ ++ ++/* VC0 Non-Posted Receive Queue Control */ ++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 ++ ++/* VC0 Completion Receive Queue Control */ ++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 ++ ++/* Applicable to the above three registers */ ++enum { ++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, ++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, ++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, ++}; ++ ++/* VC0 Posted Buffer Depth Register */ ++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Non-Posted Buffer Depth Register */ ++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Completion Buffer Depth Register */ ++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 ++ ++/* PHY Status Register, all zeros in VR9 */ ++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) ++ ++/* PHY Control Register, all zeros in VR9 */ ++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) ++ ++/* ++ * PCIe PDI PHY register definition, suppose all the following ++ * stuff is confidential. ++ * XXX, detailed bit definition ++ */ ++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) ++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) ++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) ++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) ++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) ++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) ++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) ++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) ++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) ++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) ++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) ++ ++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) ++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) ++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) ++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) ++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) ++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) ++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) ++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) ++ ++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) ++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) ++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) ++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) ++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) ++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) ++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) ++ ++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) ++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) ++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) ++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) ++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) ++ ++/* Interrupt related stuff */ ++#define PCIE_LEGACY_DISABLE 0 ++#define PCIE_LEGACY_INTA 1 ++#define PCIE_LEGACY_INTB 2 ++#define PCIE_LEGACY_INTC 3 ++#define PCIE_LEGACY_INTD 4 ++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD ++ ++#define PCIE_IRQ_LOCK(lock) do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(&(lock), flags); ++#define PCIE_IRQ_UNLOCK(lock) \ ++ spin_unlock_irqrestore(&(lock), flags); \ ++} while (0) ++ ++#define PCIE_MSG_MSI 0x00000001 ++#define PCIE_MSG_ISR 0x00000002 ++#define PCIE_MSG_FIXUP 0x00000004 ++#define PCIE_MSG_READ_CFG 0x00000008 ++#define PCIE_MSG_WRITE_CFG 0x00000010 ++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) ++#define PCIE_MSG_REG 0x00000020 ++#define PCIE_MSG_INIT 0x00000040 ++#define PCIE_MSG_ERR 0x00000080 ++#define PCIE_MSG_PHY 0x00000100 ++#define PCIE_MSG_ANY 0x000001ff ++ ++#define IFX_PCIE_PORT0 0 ++#define IFX_PCIE_PORT1 1 ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++#define IFX_PCIE_CORE_NR 2 ++#else ++#define IFX_PCIE_CORE_NR 1 ++#endif ++ ++//#define IFX_PCIE_ERROR_INT ++ ++//#define IFX_PCIE_DBG ++ ++#if defined(IFX_PCIE_DBG) ++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ ++ if (g_pcie_debug_flag & (_m)) { \ ++ ifx_pcie_debug((_fmt), ##args); \ ++ } \ ++} while (0) ++ ++#define INLINE ++#else ++#define IFX_PCIE_PRINT(_m, _fmt, args...) \ ++ do {} while(0) ++#define INLINE inline ++#endif ++ ++struct ifx_pci_controller { ++ struct pci_controller pcic; ++ ++ /* RC specific, per host bus information */ ++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ ++}; ++ ++typedef struct ifx_pcie_ir_irq { ++ const unsigned int irq; ++ const char name[16]; ++}ifx_pcie_ir_irq_t; ++ ++typedef struct ifx_pcie_legacy_irq{ ++ const u32 irq_bit; ++ const int irq; ++}ifx_pcie_legacy_irq_t; ++ ++typedef struct ifx_pcie_irq { ++ ifx_pcie_ir_irq_t ir_irq; ++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; ++}ifx_pcie_irq_t; ++ ++extern u32 g_pcie_debug_flag; ++extern void ifx_pcie_debug(const char *fmt, ...); ++extern void pcie_phy_clock_mode_setup(int pcie_port); ++extern void pcie_msi_pic_init(int pcie_port); ++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); ++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); ++ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define IFX_PCIE_GPIO_RESET 38 ++#define IFX_REG_R32 ltq_r32 ++#define IFX_REG_W32 ltq_w32 ++#define CONFIG_IFX_PCIE_HW_SWAP ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ ++#define IFX_PMU1_MODULE_PCIE_PHY (0) ++#define IFX_PMU1_MODULE_PCIE_CTRL (1) ++#define IFX_PMU1_MODULE_PDI (4) ++#define IFX_PMU1_MODULE_MSI (5) ++ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "ahb"); ++ clk_enable(clk); ++ //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg |= IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#else ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg &= ~IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "phy"); ++ clk_enable(clk); ++ //ltq_pmu1_enable(1<PCIe and PDI endianness */ ++ reg |= IFX_RCU_AHB_BE_PCIE_PDI; ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "pdi"); ++ clk_enable(clk); ++ //ltq_pmu1_enable(1< 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++#endif /* CONFIG_PCI_LANTIQ */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ #endif /* CONFIG_PCI_LANTIQ */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_VR9_H */ ++ +--- a/drivers/pci/pcie/Kconfig ++++ b/drivers/pci/pcie/Kconfig +@@ -51,6 +51,7 @@ config PCIEAER_INJECT + config PCIE_ECRC + bool "PCI Express ECRC settings control" + depends on PCIEAER ++ default n + help + Used to override firmware/bios settings for PCI Express ECRC + (transaction layer end-to-end CRC checking). +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -1480,6 +1480,8 @@ void pci_walk_bus(struct pci_bus *top, i + void *userdata); + int pci_cfg_space_size(struct pci_dev *dev); + unsigned char pci_bus_max_busnr(struct pci_bus *bus); ++int pcibios_host_nr(void); ++int pcibios_1st_host_bus_nr(void); + void pci_setup_bridge(struct pci_bus *bus); + resource_size_t pcibios_window_alignment(struct pci_bus *bus, + unsigned long type); +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -1085,6 +1085,12 @@ + #define PCI_DEVICE_ID_SGI_IOC3 0x0003 + #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 + ++#define PCI_VENDOR_ID_INFINEON 0x15D1 ++#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F ++#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 ++#define PCI_VENDOR_ID_LANTIQ 0x1BEF ++#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 ++ + #define PCI_VENDOR_ID_WINBOND 0x10ad + #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 + #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 diff --git a/target/linux/lantiq/patches-5.15/0004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-5.15/0004-MIPS-lantiq-add-atm-hack.patch new file mode 100644 index 0000000000..e32e4e2daa --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0004-MIPS-lantiq-add-atm-hack.patch @@ -0,0 +1,482 @@ +From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:27:25 +0200 +Subject: [PATCH 04/36] MIPS: lantiq: add atm hack + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++ + arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++ + arch/mips/lantiq/irq.c | 2 + + arch/mips/mm/cache.c | 4 + + include/uapi/linux/atm.h | 6 + + net/atm/common.c | 6 + + net/atm/proc.c | 2 +- + 7 files changed, 416 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h +@@ -0,0 +1,196 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_atm.h ++** PROJECT : UEIP ++** MODULES : ATM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global ATM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_ATM_H ++#define IFX_ATM_H ++ ++ ++ ++/*! ++ \defgroup IFX_ATM UEIP Project - ATM driver module ++ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_IOCTL IOCTL Commands ++ \ingroup IFX_ATM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_STRUCT Structures ++ \ingroup IFX_ATM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_atm.h ++ \ingroup IFX_ATM ++ \brief ATM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ATM MIB ++ */ ++ ++/*! ++ \struct atm_cell_ifEntry_t ++ \brief Structure used for Cell Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifInErrors; /*!< counter of error ingress cells */ ++ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ ++ __u32 ifOutErrors; /*!< counter of error egress cells */ ++} atm_cell_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_ifEntry_t ++ \brief Structure used for AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifInUcastPkts; /*!< counter of ingress packets */ ++ __u32 ifOutUcastPkts; /*!< counter of egress packets */ ++ __u32 ifInErrors; /*!< counter of error ingress packets */ ++ __u32 ifInDiscards; /*!< counter of dropped ingress packets */ ++ __u32 ifOutErros; /*!< counter of error egress packets */ ++ __u32 ifOutDiscards; /*!< counter of dropped egress packets */ ++} atm_aal5_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_vcc_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ This structure is a part of structure "atm_aal5_vcc_x_t". ++ */ ++typedef struct { ++ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ ++ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet ++ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ ++} atm_aal5_vcc_t; ++ ++/*! ++ \struct atm_aal5_vcc_x_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". ++ */ ++typedef struct { ++ int vpi; /*!< VPI of the VCC to get MIB counters */ ++ int vci; /*!< VCI of the VCC to get MIB counters */ ++ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ ++} atm_aal5_vcc_x_t; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief ATM IOCTL Magic Number ++ */ ++#define PPE_ATM_IOC_MAGIC 'o' ++/*! ++ \brief ATM IOCTL Command - Get Cell Level MIB Counters ++ ++ This command is obsolete. User can get cell level MIB from DSL API. ++ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters ++ ++ Get AAL5 packet counters. ++ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get Per PVC MIB Counters ++ ++ Get AAL5 packet counters for each PVC. ++ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. ++ */ ++#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) ++/*! ++ \brief Total Number of ATM IOCTL Commands ++ */ ++#define PPE_ATM_IOC_MAXNR 3 ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_ATM_H ++ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h +@@ -0,0 +1,203 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_ptm.h ++** PROJECT : UEIP ++** MODULES : PTM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global PTM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_PTM_H ++#define IFX_PTM_H ++ ++ ++ ++/*! ++ \defgroup IFX_PTM UEIP Project - PTM driver module ++ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_IOCTL IOCTL Commands ++ \ingroup IFX_PTM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_STRUCT Structures ++ \ingroup IFX_PTM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_ptm.h ++ \ingroup IFX_PTM ++ \brief PTM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_PTM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief PTM IOCTL Command - Get codeword MIB counters. ++ ++ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. ++ */ ++#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 ++/*! ++ \brief PTM IOCTL Command - Get packet MIB counters. ++ ++ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. ++ */ ++#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 ++/*! ++ \brief PTM IOCTL Command - Get firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 ++/*! ++ \brief PTM IOCTL Command - Set firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 ++/*! ++ \brief PTM IOCTL Command - Program priority value to TX queue mapping. ++ ++ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. ++ */ ++#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 ++ ++/*@}*/ ++ ++ ++/*! ++ \addtogroup IFX_PTM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Data Type ++ */ ++ ++/*! ++ \typedef PTM_CW_IF_ENTRY_T ++ \brief Wrapping of structure "ptm_cw_ifEntry_t". ++ */ ++/*! ++ \struct ptm_cw_ifEntry_t ++ \brief Structure used for CodeWord level MIB counters. ++ */ ++typedef struct ptm_cw_ifEntry_t { ++ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ ++ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ ++ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ ++ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ ++ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ ++} PTM_CW_IF_ENTRY_T; ++ ++/*! ++ \typedef PTM_FRAME_MIB_T ++ \brief Wrapping of structure "ptm_frame_mib_t". ++ */ ++/*! ++ \struct ptm_frame_mib_t ++ \brief Structure used for packet level MIB counters. ++ */ ++typedef struct ptm_frame_mib_t { ++ uint32_t RxCorrect; /*!< output, number of ingress packet */ ++ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ ++ uint32_t RxDropped; /*!< output, number of dropped ingress packet */ ++ uint32_t TxSend; /*!< output, number of egress packet */ ++} PTM_FRAME_MIB_T; ++ ++/*! ++ \typedef IFX_PTM_CFG_T ++ \brief Wrapping of structure "ptm_cfg_t". ++ */ ++/*! ++ \struct ptm_cfg_t ++ \brief Structure used for ETH/TC CRC configuration. ++ */ ++typedef struct ptm_cfg_t { ++ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ ++ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ ++ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ ++ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ ++ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ ++ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ ++ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ ++} IFX_PTM_CFG_T; ++ ++/*! ++ \typedef IFX_PTM_PRIO_Q_MAP_T ++ \brief Wrapping of structure "ppe_prio_q_map". ++ */ ++/*! ++ \struct ppe_prio_q_map ++ \brief Structure used for Priority Value to TX Queue mapping. ++ */ ++typedef struct ppe_prio_q_map { ++ int pkt_prio; ++ int qid; ++ int vpi; // ignored in eth interface ++ int vci; // ignored in eth interface ++} IFX_PTM_PRIO_Q_MAP_T; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_PTM_H ++ +--- a/arch/mips/lantiq/irq.c ++++ b/arch/mips/lantiq/irq.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -92,6 +93,7 @@ void ltq_disable_irq(struct irq_data *d) + } + raw_spin_unlock_irqrestore(<q_icu_lock, flags); + } ++EXPORT_SYMBOL(ltq_mask_and_ack_irq); + + void ltq_mask_and_ack_irq(struct irq_data *d) + { +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -63,6 +63,10 @@ void (*_dma_cache_wback_inv)(unsigned lo + void (*_dma_cache_wback)(unsigned long start, unsigned long size); + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + ++EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_wback); ++EXPORT_SYMBOL(_dma_cache_inv); ++ + #endif /* CONFIG_DMA_NONCOHERENT */ + + /* +--- a/include/uapi/linux/atm.h ++++ b/include/uapi/linux/atm.h +@@ -131,8 +131,14 @@ + #define ATM_ABR 4 + #define ATM_ANYCLASS 5 /* compatible with everything */ + ++#define ATM_VBR_NRT ATM_VBR ++#define ATM_VBR_RT 6 ++#define ATM_UBR_PLUS 7 ++#define ATM_GFR 8 ++ + #define ATM_MAX_PCR -1 /* maximum available PCR */ + ++ + struct atm_trafprm { + unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ + int max_pcr; /* maximum PCR in cells per second */ +--- a/net/atm/proc.c ++++ b/net/atm/proc.c +@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil + static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) + { + static const char *const class_name[] = { +- "off", "UBR", "CBR", "VBR", "ABR"}; ++ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; + static const char *const aal_name[] = { + "---", "1", "2", "3/4", /* 0- 3 */ + "???", "5", "???", "???", /* 4- 7 */ diff --git a/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch new file mode 100644 index 0000000000..16b87ed0a5 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch @@ -0,0 +1,1041 @@ +From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:30:56 +0200 +Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ + arch/mips/lantiq/xway/Makefile | 2 +- + arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++ + 3 files changed, 1001 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h + create mode 100644 arch/mips/lantiq/xway/timer.c + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h +@@ -0,0 +1,155 @@ ++#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++ ++ ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/* ++ * Available Timer/Counter Index ++ */ ++#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) ++#define TIMER_ANY 0x00 ++#define TIMER1A TIMER(1, 0) ++#define TIMER1B TIMER(1, 1) ++#define TIMER2A TIMER(2, 0) ++#define TIMER2B TIMER(2, 1) ++#define TIMER3A TIMER(3, 0) ++#define TIMER3B TIMER(3, 1) ++ ++/* ++ * Flag of Timer/Counter ++ * These flags specify the way in which timer is configured. ++ */ ++/* Bit size of timer/counter. */ ++#define TIMER_FLAG_16BIT 0x0000 ++#define TIMER_FLAG_32BIT 0x0001 ++/* Switch between timer and counter. */ ++#define TIMER_FLAG_TIMER 0x0000 ++#define TIMER_FLAG_COUNTER 0x0002 ++/* Stop or continue when overflowing/underflowing. */ ++#define TIMER_FLAG_ONCE 0x0000 ++#define TIMER_FLAG_CYCLIC 0x0004 ++/* Count up or counter down. */ ++#define TIMER_FLAG_UP 0x0000 ++#define TIMER_FLAG_DOWN 0x0008 ++/* Count on specific level or edge. */ ++#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 ++#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 ++#define TIMER_FLAG_RISE_EDGE 0x0010 ++#define TIMER_FLAG_FALL_EDGE 0x0020 ++#define TIMER_FLAG_ANY_EDGE 0x0030 ++/* Signal is syncronous to module clock or not. */ ++#define TIMER_FLAG_UNSYNC 0x0000 ++#define TIMER_FLAG_SYNC 0x0080 ++/* Different interrupt handle type. */ ++#define TIMER_FLAG_NO_HANDLE 0x0000 ++#if defined(__KERNEL__) ++ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 ++#endif // defined(__KERNEL__) ++#define TIMER_FLAG_SIGNAL 0x0300 ++/* Internal clock source or external clock source */ ++#define TIMER_FLAG_INT_SRC 0x0000 ++#define TIMER_FLAG_EXT_SRC 0x1000 ++ ++ ++/* ++ * ioctl Command ++ */ ++#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ ++#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ ++#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ ++#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ ++#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ ++#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ ++#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ ++#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ ++ ++/* ++ * Data Type Used to Call ioctl ++ */ ++struct gptu_ioctl_param { ++ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field is ID of expected * ++ * timer/counter. If it's zero, a timer/counter would * ++ * be dynamically allocated and ID would be stored in * ++ * this field. * ++ * In command GPTU_GET_COUNT_VALUE, this field is * ++ * ignored. * ++ * In other command, this field is ID of timer/counter * ++ * allocated. */ ++ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field contains flags to * ++ * specify how to configure timer/counter. * ++ * In command GPTU_START_TIMER, zero indicate start * ++ * and non-zero indicate resume timer/counter. * ++ * In other command, this field is ignored. */ ++ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * ++ * init/reload value. * ++ * In command GPTU_SET_TIMER, this field contains * ++ * frequency (0.001Hz) of timer. * ++ * In command GPTU_GET_COUNT_VALUE, current count * ++ * value would be stored in this field. * ++ * In command GPTU_CALCULATE_DIVIDER, this field * ++ * contains frequency wanted, and after calculation, * ++ * divider would be stored in this field to overwrite * ++ * the frequency. * ++ * In other command, this field is ignored. */ ++ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains process * ++ * ID to which signal would be sent. * ++ * In other command, this field is ignored. */ ++ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains signal * ++ * number which would be sent. * ++ * In other command, this field is ignored. */ ++}; ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++typedef void (*timer_callback)(unsigned long arg); ++ ++extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); ++extern int lq_free_timer(unsigned int); ++extern int lq_start_timer(unsigned int, int); ++extern int lq_stop_timer(unsigned int); ++extern int lq_reset_counter_flags(u32 timer, u32 flags); ++extern int lq_get_count_value(unsigned int, unsigned long *); ++extern u32 lq_cal_divider(unsigned long); ++extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); ++extern int lq_set_counter(unsigned int timer, unsigned int flag, ++ u32 reload, unsigned long arg1, unsigned long arg2); ++ ++#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,4 +1,10 @@ + # SPDX-License-Identifier: GPL-2.0-only +-obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o ++obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o ++ ++ifdef CONFIG_SOC_AMAZON_SE ++obj-y += gptu.o ++else ++obj-y += timer.o ++endif + + obj-y += vmmc.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/timer.c +@@ -0,0 +1,852 @@ ++#ifndef CONFIG_SOC_AMAZON_SE ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "../clk.h" ++ ++#include ++#include ++#include ++ ++#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 ++ ++#ifdef TIMER1A ++#define FIRST_TIMER TIMER1A ++#else ++#define FIRST_TIMER 2 ++#endif ++ ++/* ++ * GPTC divider is set or not. ++ */ ++#define GPTU_CLC_RMC_IS_SET 0 ++ ++/* ++ * Timer Interrupt (IRQ) ++ */ ++/* Must be adjusted when ICU driver is available */ ++#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) ++ ++/* ++ * Bits Operation ++ */ ++#define GET_BITS(x, msb, lsb) \ ++ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) ++#define SET_BITS(x, msb, lsb, value) \ ++ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ ++ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) ++ ++/* ++ * GPTU Register Mapping ++ */ ++#define LQ_GPTU (KSEG1 + 0x1E100A00) ++#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) ++#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) ++#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) ++#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) ++#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) ++ ++/* ++ * Clock Control Register ++ */ ++#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) ++#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) ++#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) ++#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) ++#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) ++#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) ++#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) ++ ++#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) ++#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) ++#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) ++ ++/* ++ * ID Register ++ */ ++#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) ++#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) ++#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) ++ ++/* ++ * Control Register of Timer/Counter nX ++ * n is the index of block (1 based index) ++ * X is either A or B ++ */ ++#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) ++#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) ++#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) ++#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) ++#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) ++#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ ++#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) ++#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) ++#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) ++#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) ++ ++#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) ++#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) ++#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) ++#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) ++#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) ++ ++#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) ++#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) ++ ++#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++ ++#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) ++#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) ++#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) ++#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) ++#define TIMER_FLAG_NONE_EDGE 0x0000 ++#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) ++#define TIMER_FLAG_REAL 0x0000 ++#define TIMER_FLAG_INVERT 0x0040 ++#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) ++#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) ++#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) ++#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 ++#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) ++#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) ++ ++struct timer_dev_timer { ++ unsigned int f_irq_on; ++ unsigned int irq; ++ unsigned int flag; ++ unsigned long arg1; ++ unsigned long arg2; ++}; ++ ++struct timer_dev { ++ struct mutex gptu_mutex; ++ unsigned int number_of_timers; ++ unsigned int occupation; ++ unsigned int f_gptu_on; ++ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; ++}; ++ ++ ++unsigned int ltq_get_fpi_bus_clock(int fpi) { ++ struct clk *clk = clk_get_fpi(); ++ return clk_get_rate(clk); ++} ++ ++ ++static long gptu_ioctl(struct file *, unsigned int, unsigned long); ++static int gptu_open(struct inode *, struct file *); ++static int gptu_release(struct inode *, struct file *); ++ ++static struct file_operations gptu_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = gptu_ioctl, ++ .open = gptu_open, ++ .release = gptu_release ++}; ++ ++static struct miscdevice gptu_miscdev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "gptu", ++ .fops = &gptu_fops, ++}; ++ ++static struct timer_dev timer_dev; ++ ++static irqreturn_t timer_irq_handler(int irq, void *p) ++{ ++ unsigned int timer; ++ unsigned int flag; ++ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; ++ ++ timer = irq - TIMER_INTERRUPT; ++ if (timer < timer_dev.number_of_timers ++ && dev_timer == &timer_dev.timer[timer]) { ++ /* Clear interrupt. */ ++ ltq_w32(1 << timer, LQ_GPTU_IRNCR); ++ ++ /* Call user hanler or signal. */ ++ flag = dev_timer->flag; ++ if (!(timer & 0x01) ++ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ /* 16-bit timer or timer A of 32-bit timer */ ++ switch (TIMER_FLAG_MASK_HANDLE(flag)) { ++ case TIMER_FLAG_CALLBACK_IN_IRQ: ++ case TIMER_FLAG_CALLBACK_IN_HB: ++ if (dev_timer->arg1) ++ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); ++ break; ++ case TIMER_FLAG_SIGNAL: ++ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); ++ break; ++ } ++ } ++ } ++ return IRQ_HANDLED; ++} ++ ++static inline void lq_enable_gptu(void) ++{ ++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); ++ clk_enable(clk); ++ ++ //ltq_pmu_enable(PMU_GPT); ++ ++ /* Set divider as 1, disable write protection for SPEN, enable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x01) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(1) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(0); ++} ++ ++static inline void lq_disable_gptu(void) ++{ ++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); ++ ltq_w32(0x00, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ /* Set divider as 0, enable write protection for SPEN, disable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x00) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(0) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(1); ++ ++ clk_enable(clk); ++} ++ ++int lq_request_timer(unsigned int timer, unsigned int flag, ++ unsigned long value, unsigned long arg1, unsigned long arg2) ++{ ++ int ret = 0; ++ unsigned int con_reg, irnen_reg; ++ int n, X; ++ ++ if (timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", ++ timer, flag, value); ++ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) ++ value &= 0xFFFF; ++ else ++ timer &= ~0x01; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ /* ++ * Allocate timer. ++ */ ++ if (timer < FIRST_TIMER) { ++ unsigned int mask; ++ unsigned int shift; ++ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ ++ unsigned int offset = TIMER2A; ++ ++ /* ++ * Pick up a free timer. ++ */ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ mask = 1 << offset; ++ shift = 1; ++ } else { ++ mask = 3 << offset; ++ shift = 2; ++ } ++ for (timer = offset; ++ timer < offset + timer_dev.number_of_timers; ++ timer += shift, mask <<= shift) ++ if (!(timer_dev.occupation & mask)) { ++ timer_dev.occupation |= mask; ++ break; ++ } ++ if (timer >= offset + timer_dev.number_of_timers) { ++ printk("failed![%d]\n", __LINE__); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } else ++ ret = timer; ++ } else { ++ register unsigned int mask; ++ ++ /* ++ * Check if the requested timer is free. ++ */ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if ((timer_dev.occupation & mask)) { ++ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", ++ __LINE__, mask, timer_dev.occupation); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EBUSY; ++ } else { ++ timer_dev.occupation |= mask; ++ ret = 0; ++ } ++ } ++ ++ /* ++ * Prepare control register value. ++ */ ++ switch (TIMER_FLAG_MASK_EDGE(flag)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : ++ GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : ++ GPTU_CON_SRC_EG_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_SYNC(flag) == ++ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : ++ GPTU_CON_SYNC_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_INVERT(flag) == ++ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : ++ GPTU_CON_EXT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_STOP(flag) == ++ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_TYPE(flag) == ++ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : ++ GPTU_CON_CNT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_DIR(flag) == ++ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ /* ++ * Fill up running data. ++ */ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flag; ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; ++ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; ++ ++ /* ++ * Enable GPTU module. ++ */ ++ if (!timer_dev.f_gptu_on) { ++ lq_enable_gptu(); ++ timer_dev.f_gptu_on = 1; ++ } ++ ++ /* ++ * Enable IRQ. ++ */ ++ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = ++ (unsigned long) find_task_by_vpid((int) arg1); ++ ++ irnen_reg = 1 << (timer - FIRST_TIMER); ++ ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL ++ || (TIMER_FLAG_MASK_HANDLE(flag) == ++ TIMER_FLAG_CALLBACK_IN_IRQ ++ && timer_dev.timer[timer - FIRST_TIMER].arg1)) { ++ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; ++ } ++ } else ++ irnen_reg = 0; ++ ++ /* ++ * Write config register, reload value and enable interrupt. ++ */ ++ n = timer >> 1; ++ X = timer & 0x01; ++ *LQ_GPTU_CON(n, X) = con_reg; ++ *LQ_GPTU_RELOAD(n, X) = value; ++ /* printk("reload value = %d\n", (u32)value); */ ++ *LQ_GPTU_IRNEN |= irnen_reg; ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ printk("successful!\n"); ++ return ret; ++} ++EXPORT_SYMBOL(lq_request_timer); ++ ++int lq_free_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ if (GPTU_CON_EN(n, X)) ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); ++ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); ++ ++ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { ++ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; ++ } ++ ++ timer_dev.occupation &= ~mask; ++ if (!timer_dev.occupation && timer_dev.f_gptu_on) { ++ lq_disable_gptu(); ++ timer_dev.f_gptu_on = 0; ++ } ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_free_timer); ++ ++int lq_start_timer(unsigned int timer, int is_resume) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); ++ ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_start_timer); ++ ++int lq_stop_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_stop_timer); ++ ++int lq_reset_counter_flags(u32 timer, u32 flags) ++{ ++ unsigned int oflag; ++ unsigned int mask, con_reg; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ oflag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ switch (TIMER_FLAG_MASK_EDGE(flags)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); ++ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); ++ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flags; ++ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_CON(n, X) = con_reg; ++ smp_wmb(); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return 0; ++} ++EXPORT_SYMBOL(lq_reset_counter_flags); ++ ++int lq_get_count_value(unsigned int timer, unsigned long *value) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *value = *LQ_GPTU_COUNT(n, X); ++ ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_get_count_value); ++ ++u32 lq_cal_divider(unsigned long freq) ++{ ++ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); ++ u32 clock_divider = 1; ++ module_freq = fpi * 1000; ++ do_div(module_freq, clock_divider * freq); ++ return module_freq; ++} ++EXPORT_SYMBOL(lq_cal_divider); ++ ++int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, ++ int is_ext_src, unsigned int handle_flag, unsigned long arg1, ++ unsigned long arg2) ++{ ++ unsigned long divider; ++ unsigned int flag; ++ ++ divider = lq_cal_divider(freq); ++ if (divider == 0) ++ return -EINVAL; ++ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) ++ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) ++ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) ++ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN ++ | TIMER_FLAG_MASK_HANDLE(handle_flag); ++ ++ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", ++ timer, freq, divider); ++ return lq_request_timer(timer, flag, divider, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_timer); ++ ++int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, ++ unsigned long arg1, unsigned long arg2) ++{ ++ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); ++ return lq_request_timer(timer, flag, reload, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_counter); ++ ++static long gptu_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ int ret; ++ struct gptu_ioctl_param param; ++ ++ if (!access_ok((void __user *)arg, sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ if (copy_from_user(¶m, (void __user *)arg, sizeof(param))) ++ return -EFAULT; ++ ++ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER ++ || GPTU_SET_COUNTER) && param.timer < 2) ++ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) ++ && !access_ok((void __user *)arg, ++ sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ ++ switch (cmd) { ++ case GPTU_REQUEST_TIMER: ++ ret = lq_request_timer(param.timer, param.flag, param.value, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret))) ++ ret = -EFAULT; ++ else ++ ret = 0; ++ } ++ break; ++ case GPTU_FREE_TIMER: ++ ret = lq_free_timer(param.timer); ++ break; ++ case GPTU_START_TIMER: ++ ret = lq_start_timer(param.timer, param.flag); ++ break; ++ case GPTU_STOP_TIMER: ++ ret = lq_stop_timer(param.timer); ++ break; ++ case GPTU_GET_COUNT_VALUE: ++ ret = lq_get_count_value(param.timer, ¶m.value); ++ if (!ret && copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value,sizeof(param.value))) ++ ret = -EFAULT; ++ break; ++ case GPTU_CALCULATE_DIVIDER: ++ param.value = lq_cal_divider(param.value); ++ if (param.value == 0) ++ ret = -EINVAL; ++ else if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value, ++ sizeof(param.value))) ++ ret = -EFAULT; ++ else ++ ret = 0; ++ break; ++ case GPTU_SET_TIMER: ++ ret = lq_set_timer(param.timer, param.value, ++ TIMER_FLAG_MASK_STOP(param.flag) != ++ TIMER_FLAG_ONCE ? 1 : 0, ++ TIMER_FLAG_MASK_SRC(param.flag) == ++ TIMER_FLAG_EXT_SRC ? 1 : 0, ++ TIMER_FLAG_MASK_HANDLE(param.flag) == ++ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : ++ TIMER_FLAG_NO_HANDLE, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret))) ++ ret = -EFAULT; ++ else ++ ret = 0; ++ } ++ break; ++ case GPTU_SET_COUNTER: ++ lq_set_counter(param.timer, param.flag, param.value, 0, 0); ++ if (ret > 0) { ++ if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret))) ++ ret = -EFAULT; ++ else ++ ret = 0; ++ } ++ break; ++ default: ++ ret = -ENOTTY; ++ } ++ ++ return ret; ++} ++ ++static int gptu_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static int gptu_release(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++int __init lq_gptu_init(void) ++{ ++ int ret; ++ unsigned int i; ++ ++ ltq_w32(0, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ memset(&timer_dev, 0, sizeof(timer_dev)); ++ mutex_init(&timer_dev.gptu_mutex); ++ ++ lq_enable_gptu(); ++ timer_dev.number_of_timers = GPTU_ID_CFG * 2; ++ lq_disable_gptu(); ++ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) ++ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; ++ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); ++ ++ ret = misc_register(&gptu_miscdev); ++ if (ret) { ++ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); ++ return ret; ++ } else { ++ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); ++ } ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); ++ if (ret) { ++ for (; i >= 0; i--) ++ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); ++ misc_deregister(&gptu_miscdev); ++ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); ++ return ret; ++ } else { ++ timer_dev.timer[i].irq = TIMER_INTERRUPT + i; ++ disable_irq(timer_dev.timer[i].irq); ++ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); ++ } ++ } ++ ++ return 0; ++} ++ ++void __exit lq_gptu_exit(void) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ if (timer_dev.timer[i].f_irq_on) ++ disable_irq(timer_dev.timer[i].irq); ++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); ++ } ++ lq_disable_gptu(); ++ misc_deregister(&gptu_miscdev); ++} ++ ++module_init(lq_gptu_init); ++module_exit(lq_gptu_exit); ++ ++#endif diff --git a/target/linux/lantiq/patches-5.15/0018-MTD-nand-lots-of-xrx200-fixes.patch b/target/linux/lantiq/patches-5.15/0018-MTD-nand-lots-of-xrx200-fixes.patch new file mode 100644 index 0000000000..35f656da6e --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0018-MTD-nand-lots-of-xrx200-fixes.patch @@ -0,0 +1,121 @@ +From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 9 Sep 2014 23:12:15 +0200 +Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/raw/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 63 insertions(+) + +--- a/drivers/mtd/nand/raw/xway_nand.c ++++ b/drivers/mtd/nand/raw/xway_nand.c +@@ -61,6 +61,24 @@ + #define NAND_CON_CSMUX (1 << 1) + #define NAND_CON_NANDM 1 + ++#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr)) ++#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400) ++#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080) ++ ++/* ++ * req_mask provides a mechanism to prevent interference between ++ * nand and pci (probably only relevant for the BT Home Hub 2B). ++ * Setting it causes the corresponding pci req pins to be masked ++ * during nand access, and also moves ebu locking from the read/write ++ * functions to the chip select function to ensure that the whole ++ * operation runs with interrupts disabled. ++ * In addition it switches on some extra waiting in xway_cmd_ctrl(). ++ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled, ++ * which in turn seems to be necessary for the nor chip to be recognised ++ * reliably, on a board (Home Hub 2B again) which has both nor and nand. ++ */ ++static __be32 req_mask = 0; ++ + struct xway_nand_data { + struct nand_controller controller; + struct nand_chip chip; +@@ -92,10 +110,22 @@ static void xway_select_chip(struct nand + case -1: + ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); ++ ++ if (req_mask) { ++ /* Unmask all external PCI request */ ++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16); ++ } ++ + spin_unlock_irqrestore(&ebu_lock, data->csflags); + break; + case 0: + spin_lock_irqsave(&ebu_lock, data->csflags); ++ ++ if (req_mask) { ++ /* Mask all external PCI request */ ++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16); ++ } ++ + ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); + ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); + break; +@@ -108,6 +138,11 @@ static void xway_cmd_ctrl(struct nand_ch + { + struct mtd_info *mtd = nand_to_mtd(chip); + ++ if (req_mask) { ++ if (cmd != NAND_CMD_STATUS) ++ ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */ ++ } ++ + if (cmd == NAND_CMD_NONE) + return; + +@@ -118,6 +153,24 @@ static void xway_cmd_ctrl(struct nand_ch + + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; ++ ++ if (req_mask) { ++ /* ++ * program and erase have their own busy handlers ++ * status and sequential in needs no delay ++ */ ++ switch (cmd) { ++ case NAND_CMD_ERASE1: ++ case NAND_CMD_SEQIN: ++ case NAND_CMD_STATUS: ++ case NAND_CMD_READID: ++ return; ++ } ++ ++ /* wait until command is processed */ ++ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) ++ ; ++ } + } + + static int xway_dev_ready(struct nand_chip *chip) +@@ -170,6 +223,7 @@ static int xway_nand_probe(struct platfo + int err; + u32 cs; + u32 cs_flag = 0; ++ const __be32 *req_mask_ptr; + + /* Allocate memory for the device structure (and zero it) */ + data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), +@@ -206,6 +260,15 @@ static int xway_nand_probe(struct platfo + if (!err && cs == 1) + cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; + ++ req_mask_ptr = of_get_property(pdev->dev.of_node, ++ "req-mask", NULL); ++ ++ /* ++ * Load the PCI req lines to mask from the device tree. If the ++ * property is not present, setting req_mask to 0 disables masking. ++ */ ++ req_mask = (req_mask_ptr ? *req_mask_ptr : 0); ++ + /* setup the EBU to run in NAND mode on our base addr */ + ltq_ebu_w32(CPHYSADDR(data->nandaddr) + | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); diff --git a/target/linux/lantiq/patches-5.15/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch b/target/linux/lantiq/patches-5.15/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch new file mode 100644 index 0000000000..c1fc59487a --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch @@ -0,0 +1,25 @@ +From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:18:00 +0200 +Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash + +Signed-off-by: John Crispin +--- + drivers/mtd/maps/lantiq-flash.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -129,7 +129,11 @@ ltq_mtd_probe(struct platform_device *pd + if (!ltq_mtd->map) + return -ENOMEM; + +- ltq_mtd->map->phys = ltq_mtd->res->start; ++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) ++ ltq_mtd->map->phys = NO_XIP; ++ else ++ ltq_mtd->map->phys = ltq_mtd->res->start; ++ ltq_mtd->res->start; + ltq_mtd->map->size = resource_size(ltq_mtd->res); + ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); + if (IS_ERR(ltq_mtd->map->virt)) diff --git a/target/linux/lantiq/patches-5.15/0023-NET-PHY-add-led-support-for-intel-xway.patch b/target/linux/lantiq/patches-5.15/0023-NET-PHY-add-led-support-for-intel-xway.patch new file mode 100644 index 0000000000..fcc760b911 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0023-NET-PHY-add-led-support-for-intel-xway.patch @@ -0,0 +1,294 @@ +From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:15:36 +0200 +Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G + +Signed-off-by: John Crispin +--- + drivers/net/phy/Kconfig | 5 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 237 insertions(+) + create mode 100644 drivers/net/phy/lantiq.c + +--- a/drivers/net/phy/intel-xway.c ++++ b/drivers/net/phy/intel-xway.c +@@ -229,6 +229,51 @@ static int xway_gphy_rgmii_init(struct p + XWAY_MDIO_MIICTRL_TXSKEW_MASK, val); + } + ++#if IS_ENABLED(CONFIG_OF_MDIO) ++static int vr9_gphy_of_reg_init(struct phy_device *phydev) ++{ ++ u32 tmp; ++ ++ /* store the led values if one was passed by the devicetree */ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp); ++ ++ return 0; ++} ++#else ++static int vr9_gphy_of_reg_init(struct phy_device *phydev) ++{ ++ return 0; ++} ++#endif /* CONFIG_OF_MDIO */ ++ + static int xway_gphy_config_init(struct phy_device *phydev) + { + int err; +@@ -280,6 +325,7 @@ static int xway_gphy_config_init(struct + if (err) + return err; + ++ vr9_gphy_of_reg_init(phydev); + return 0; + } + +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt +@@ -0,0 +1,216 @@ ++Lanitq PHY binding ++============================================ ++ ++This devicetree binding controls the lantiq ethernet phys led functionality. ++ ++Example: ++ mdio@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "lantiq,xrx200-mdio"; ++ phy5: ethernet-phy@5 { ++ reg = <0x1>; ++ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; ++ }; ++ phy11: ethernet-phy@11 { ++ reg = <0x11>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led2h = <0x00>; ++ lantiq,led2l = <0x03>; ++ }; ++ phy12: ethernet-phy@12 { ++ reg = <0x12>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led1h = <0x00>; ++ lantiq,led1l = <0x03>; ++ }; ++ phy13: ethernet-phy@13 { ++ reg = <0x13>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led2h = <0x00>; ++ lantiq,led2l = <0x03>; ++ }; ++ phy14: ethernet-phy@14 { ++ reg = <0x14>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led1h = <0x00>; ++ lantiq,led1l = <0x03>; ++ }; ++ }; ++ ++Register Description ++============================================ ++ ++LEDCH: ++ ++Name Hardware Reset Value ++LEDCH 0x00C5 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++| FBF | SBF |RES | NACS | ++========================================= ++ ++Field Bits Type Description ++FBF 7:6 RW Fast Blink Frequency ++ --- ++ 0x0 (00b) F02HZ 2 Hz blinking frequency ++ 0x1 (01b) F04HZ 4 Hz blinking frequency ++ 0x2 (10b) F08HZ 8 Hz blinking frequency ++ 0x3 (11b) F16HZ 16 Hz blinking frequency ++ ++SBF 5:4 RW Slow Blink Frequency ++ --- ++ 0x0 (00b) F02HZ 2 Hz blinking frequency ++ 0x1 (01b) F04HZ 4 Hz blinking frequency ++ 0x2 (10b) F08HZ 8 Hz blinking frequency ++ 0x3 (11b) F16HZ 16 Hz blinking frequency ++ ++NACS 2:0 RW Inverse of Scan Function ++ --- ++ 0x0 (000b) NONE No Function ++ 0x1 (001b) LINK Complex function enabled when link is up ++ 0x2 (010b) PDOWN Complex function enabled when device is powered-down ++ 0x3 (011b) EEE Complex function enabled when device is in EEE mode ++ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running ++ 0x5 (101b) ABIST Complex function enabled when analog self-test is running ++ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running ++ 0x7 (111b) TEST Complex function enabled when test mode is running ++ ++LEDCL: ++ ++Name Hardware Reset Value ++LEDCL 0x0067 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++|RES | SCAN |RES | CBLINK | ++========================================= ++ ++Field Bits Type Description ++SCAN 6:4 RW Complex Scan Configuration ++ --- ++ 000 B NONE No Function ++ 001 B LINK Complex function enabled when link is up ++ 010 B PDOWN Complex function enabled when device is powered-down ++ 011 B EEE Complex function enabled when device is in EEE mode ++ 100 B ANEG Complex function enabled when auto-negotiation is running ++ 101 B ABIST Complex function enabled when analog self-test is running ++ 110 B CDIAG Complex function enabled when cable diagnostics are running ++ 111 B TEST Complex function enabled when test mode is running ++ ++CBLINK 2:0 RW Complex Blinking Configuration ++ --- ++ 000 B NONE No Function ++ 001 B LINK Complex function enabled when link is up ++ 010 B PDOWN Complex function enabled when device is powered-down ++ 011 B EEE Complex function enabled when device is in EEE mode ++ 100 B ANEG Complex function enabled when auto-negotiation is running ++ 101 B ABIST Complex function enabled when analog self-test is running ++ 110 B CDIAG Complex function enabled when cable diagnostics are running ++ 111 B TEST Complex function enabled when test mode is running ++ ++LEDxH: ++ ++Name Hardware Reset Value ++LED0H 0x0070 ++LED1H 0x0020 ++LED2H 0x0040 ++LED3H 0x0040 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++| CON | BLINKF | ++========================================= ++ ++Field Bits Type Description ++CON 7:4 RW Constant On Configuration ++ --- ++ 0x0 (0000b) NONE LED does not light up constantly ++ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s ++ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s ++ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s ++ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s ++ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s ++ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s ++ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s ++ 0x8 (1000b) PDOWN LED is on when device is powered-down ++ 0x9 (1001b) EEE LED is on when device is in EEE mode ++ 0xA (1010b) ANEG LED is on when auto-negotiation is running ++ 0xB (1011b) ABIST LED is on when analog self-test is running ++ 0xC (1100b) CDIAG LED is on when cable diagnostics are running ++ ++BLINKF 3:0 RW Fast Blinking Configuration ++ --- ++ 0x0 (0000b) NONE No Blinking ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s ++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s ++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s ++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s ++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s ++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s ++ 0x8 (1000b) PDOWN Blink when device is powered-down ++ 0x9 (1001b) EEE Blink when device is in EEE mode ++ 0xA (1010b) ANEG Blink when auto-negotiation is running ++ 0xB (1011b) ABIST Blink when analog self-test is running ++ 0xC (1100b) CDIAG Blink when cable diagnostics are running ++ ++LEDxL: ++ ++Name Hardware Reset Value ++LED0L 0x0003 ++LED1L 0x0000 ++LED2L 0x0000 ++LED3L 0x0020 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++| BLINKS | PULSE | ++========================================= ++ ++Field Bits Type Description ++BLINKS 7:4 RW Slow Blinkin Configuration ++ --- ++ 0x0 (0000b) NONE No Blinking ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s ++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s ++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s ++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s ++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s ++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s ++ 0x8 (1000b) PDOWN Blink when device is powered-down ++ 0x9 (1001b) EEE Blink when device is in EEE mode ++ 0xA (1010b) ANEG Blink when auto-negotiation is running ++ 0xB (1011b) ABIST Blink when analog self-test is running ++ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning ++ ++PULSE 3:0 RW Pulsing Configuration ++ The pulse field is a mask field by which certain events can be combined ++ --- ++ 0x0 (0000b) NONE No pulsing ++ 0x1 (0001b) TXACT Transmit activity ++ 0x2 (0010b) RXACT Receive activity ++ 0x4 (0100b) COL Collision ++ 0x8 (1000b) RES Reserved diff --git a/target/linux/lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch b/target/linux/lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch new file mode 100644 index 0000000000..eb47010fa0 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch @@ -0,0 +1,865 @@ +From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 9 Sep 2014 22:45:34 +0200 +Subject: [PATCH 28/36] NET: lantiq: various etop fixes + +Signed-off-by: John Crispin +--- + drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- + 1 file changed, 389 insertions(+), 166 deletions(-) + +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* + * +- * Copyright (C) 2011 John Crispin ++ * Copyright (C) 2011-12 John Crispin + */ + + #include +@@ -20,11 +20,16 @@ + #include + #include + #include ++#include + #include + #include + #include + #include + #include ++#include ++#include ++#include ++#include + + #include + +@@ -32,7 +37,7 @@ + #include + #include + +-#define LTQ_ETOP_MDIO 0x11804 ++#define LTQ_ETOP_MDIO_ACC 0x11804 + #define MDIO_REQUEST 0x80000000 + #define MDIO_READ 0x40000000 + #define MDIO_ADDR_MASK 0x1f +@@ -41,44 +46,91 @@ + #define MDIO_REG_OFFSET 0x10 + #define MDIO_VAL_MASK 0xffff + +-#define PPE32_CGEN 0x800 +-#define LQ_PPE32_ENET_MAC_CFG 0x1840 ++#define LTQ_ETOP_MDIO_CFG 0x11800 ++#define MDIO_CFG_MASK 0x6 ++ ++#define LTQ_ETOP_CFG 0x11808 ++#define LTQ_ETOP_IGPLEN 0x11820 ++#define LTQ_ETOP_MAC_CFG 0x11840 + + #define LTQ_ETOP_ENETS0 0x11850 + #define LTQ_ETOP_MAC_DA0 0x1186C + #define LTQ_ETOP_MAC_DA1 0x11870 +-#define LTQ_ETOP_CFG 0x16020 +-#define LTQ_ETOP_IGPLEN 0x16080 ++ ++#define MAC_CFG_MASK 0xfff ++#define MAC_CFG_CGEN (1 << 11) ++#define MAC_CFG_DUPLEX (1 << 2) ++#define MAC_CFG_SPEED (1 << 1) ++#define MAC_CFG_LINK (1 << 0) + + #define MAX_DMA_CHAN 0x8 + #define MAX_DMA_CRC_LEN 0x4 + #define MAX_DMA_DATA_LEN 0x600 + + #define ETOP_FTCU BIT(28) +-#define ETOP_MII_MASK 0xf +-#define ETOP_MII_NORMAL 0xd +-#define ETOP_MII_REVERSE 0xe + #define ETOP_PLEN_UNDER 0x40 +-#define ETOP_CGEN 0x800 ++#define ETOP_CFG_MII0 0x01 + +-/* use 2 static channels for TX/RX */ +-#define LTQ_ETOP_TX_CHANNEL 1 +-#define LTQ_ETOP_RX_CHANNEL 6 +-#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) +-#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) ++#define ETOP_CFG_MASK 0xfff ++#define ETOP_CFG_FEN0 (1 << 8) ++#define ETOP_CFG_SEN0 (1 << 6) ++#define ETOP_CFG_OFF1 (1 << 3) ++#define ETOP_CFG_REMII0 (1 << 1) ++#define ETOP_CFG_OFF0 (1 << 0) ++ ++#define LTQ_GBIT_MDIO_CTL 0xCC ++#define LTQ_GBIT_MDIO_DATA 0xd0 ++#define LTQ_GBIT_GCTL0 0x68 ++#define LTQ_GBIT_PMAC_HD_CTL 0x8c ++#define LTQ_GBIT_P0_CTL 0x4 ++#define LTQ_GBIT_PMAC_RX_IPG 0xa8 ++#define LTQ_GBIT_RGMII_CTL 0x78 ++ ++#define PMAC_HD_CTL_AS (1 << 19) ++#define PMAC_HD_CTL_RXSH (1 << 22) ++ ++/* Switch Enable (0=disable, 1=enable) */ ++#define GCTL0_SE 0x80000000 ++/* Disable MDIO auto polling (0=disable, 1=enable) */ ++#define PX_CTL_DMDIO 0x00400000 ++ ++/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ ++#define MDC_CLOCK_MASK 0xff000000 ++#define MDC_CLOCK_OFFSET 24 ++ ++/* register information for the gbit's MDIO bus */ ++#define MDIO_XR9_REQUEST 0x00008000 ++#define MDIO_XR9_READ 0x00000800 ++#define MDIO_XR9_WRITE 0x00000400 ++#define MDIO_XR9_REG_MASK 0x1f ++#define MDIO_XR9_ADDR_MASK 0x1f ++#define MDIO_XR9_RD_MASK 0xffff ++#define MDIO_XR9_REG_OFFSET 0 ++#define MDIO_XR9_ADDR_OFFSET 5 ++#define MDIO_XR9_WR_OFFSET 16 + ++#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \ ++ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) ++ ++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ + #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) + #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) + #define ltq_etop_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_etop_membase + (z)) + +-#define DRV_VERSION "1.0" ++#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) ++#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) ++#define ltq_gbit_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) ++ ++#define DRV_VERSION "1.2" + + static void __iomem *ltq_etop_membase; ++static void __iomem *ltq_gbit_membase; + + struct ltq_etop_chan { +- int idx; + int tx_free; ++ int irq; + struct net_device *netdev; + struct napi_struct napi; + struct ltq_dma_channel dma; +@@ -88,23 +140,36 @@ struct ltq_etop_chan { + struct ltq_etop_priv { + struct net_device *netdev; + struct platform_device *pdev; +- struct ltq_eth_data *pldata; + struct resource *res; + + struct mii_bus *mii_bus; + +- struct ltq_etop_chan ch[MAX_DMA_CHAN]; +- int tx_free[MAX_DMA_CHAN >> 1]; ++ struct ltq_etop_chan txch; ++ struct ltq_etop_chan rxch; + +- spinlock_t lock; ++ int tx_irq; ++ int rx_irq; ++ ++ unsigned char mac[6]; ++ phy_interface_t mii_mode; ++ ++ spinlock_t lock; ++ ++ struct clk *clk_ppe; ++ struct clk *clk_switch; ++ struct clk *clk_ephy; ++ struct clk *clk_ephycgu; + }; + ++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data); ++ + static int + ltq_etop_alloc_skb(struct ltq_etop_chan *ch) + { + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + +- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); ++ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); + if (!ch->skb[ch->dma.desc]) + return -ENOMEM; + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev, +@@ -139,8 +204,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan + spin_unlock_irqrestore(&priv->lock, flags); + + skb_put(skb, len); ++ skb->dev = ch->netdev; + skb->protocol = eth_type_trans(skb, ch->netdev); + netif_receive_skb(skb); ++ ch->netdev->stats.rx_packets++; ++ ch->netdev->stats.rx_bytes += len; + } + + static int +@@ -148,7 +216,9 @@ ltq_etop_poll_rx(struct napi_struct *nap + { + struct ltq_etop_chan *ch = container_of(napi, + struct ltq_etop_chan, napi); ++ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + int work_done = 0; ++ unsigned long flags; + + while (work_done < budget) { + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +@@ -160,7 +230,9 @@ ltq_etop_poll_rx(struct napi_struct *nap + } + if (work_done < budget) { + napi_complete_done(&ch->napi, work_done); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + } + return work_done; + } +@@ -172,12 +244,14 @@ ltq_etop_poll_tx(struct napi_struct *nap + container_of(napi, struct ltq_etop_chan, napi); + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + struct netdev_queue *txq = +- netdev_get_tx_queue(ch->netdev, ch->idx >> 1); ++ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + while ((ch->dma.desc_base[ch->tx_free].ctl & + (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { ++ ch->netdev->stats.tx_packets++; ++ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len; + dev_kfree_skb_any(ch->skb[ch->tx_free]); + ch->skb[ch->tx_free] = NULL; + memset(&ch->dma.desc_base[ch->tx_free], 0, +@@ -190,7 +264,9 @@ ltq_etop_poll_tx(struct napi_struct *nap + if (netif_tx_queue_stopped(txq)) + netif_tx_start_queue(txq); + napi_complete(&ch->napi); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + return 1; + } + +@@ -198,9 +274,10 @@ static irqreturn_t + ltq_etop_dma_irq(int irq, void *_priv) + { + struct ltq_etop_priv *priv = _priv; +- int ch = irq - LTQ_DMA_CH0_INT; +- +- napi_schedule(&priv->ch[ch].napi); ++ if (irq == priv->txch.dma.irq) ++ napi_schedule(&priv->txch.napi); ++ else ++ napi_schedule(&priv->rxch.napi); + return IRQ_HANDLED; + } + +@@ -212,7 +289,7 @@ ltq_etop_free_channel(struct net_device + ltq_dma_free(&ch->dma); + if (ch->dma.irq) + free_irq(ch->dma.irq, priv); +- if (IS_RX(ch->idx)) { ++ if (ch == &priv->txch) { + int desc; + for (desc = 0; desc < LTQ_DESC_NUM; desc++) + dev_kfree_skb_any(ch->skb[ch->dma.desc]); +@@ -223,66 +300,135 @@ static void + ltq_etop_hw_exit(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; + +- ltq_pmu_disable(PMU_PPE); +- for (i = 0; i < MAX_DMA_CHAN; i++) +- if (IS_TX(i) || IS_RX(i)) +- ltq_etop_free_channel(dev, &priv->ch[i]); ++ clk_disable(priv->clk_ppe); ++ ++ if (of_machine_is_compatible("lantiq,ar9")) ++ clk_disable(priv->clk_switch); ++ ++ if (of_machine_is_compatible("lantiq,ase")) { ++ clk_disable(priv->clk_ephy); ++ clk_disable(priv->clk_ephycgu); ++ } ++ ++ ltq_etop_free_channel(dev, &priv->txch); ++ ltq_etop_free_channel(dev, &priv->rxch); ++} ++ ++static void ++ltq_etop_gbit_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ ++ clk_enable(priv->clk_switch); ++ ++ /* enable gbit port0 on the SoC */ ++ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL); ++ ++ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); ++ /* disable MDIO auto polling mode */ ++ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); ++ /* set 1522 packet size */ ++ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); ++ /* disable pmac & dmac headers */ ++ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, ++ LTQ_GBIT_PMAC_HD_CTL); ++ /* Due to traffic halt when burst length 8, ++ replace default IPG value with 0x3B */ ++ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); ++ /* set mdc clock to 2.5 MHz */ ++ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, ++ LTQ_GBIT_RGMII_CTL); + } + + static int + ltq_etop_hw_init(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ phy_interface_t mii_mode = priv->mii_mode; + +- ltq_pmu_enable(PMU_PPE); ++ clk_enable(priv->clk_ppe); + +- switch (priv->pldata->mii_mode) { ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ ltq_etop_gbit_init(dev); ++ /* force the etops link to the gbit to MII */ ++ mii_mode = PHY_INTERFACE_MODE_MII; ++ } ++ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG); ++ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX | ++ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG); ++ ++ switch (mii_mode) { + case PHY_INTERFACE_MODE_RMII: +- ltq_etop_w32_mask(ETOP_MII_MASK, +- ETOP_MII_REVERSE, LTQ_ETOP_CFG); ++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 | ++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); + break; + + case PHY_INTERFACE_MODE_MII: +- ltq_etop_w32_mask(ETOP_MII_MASK, +- ETOP_MII_NORMAL, LTQ_ETOP_CFG); ++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 | ++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); + break; + + default: ++ if (of_machine_is_compatible("lantiq,ase")) { ++ clk_enable(priv->clk_ephy); ++ /* disable external MII */ ++ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); ++ /* enable clock for internal PHY */ ++ clk_enable(priv->clk_ephycgu); ++ /* we need to write this magic to the internal phy to ++ make it work */ ++ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); ++ pr_info("Selected EPHY mode\n"); ++ break; ++ } + netdev_err(dev, "unknown mii mode %d\n", +- priv->pldata->mii_mode); ++ mii_mode); + return -ENOTSUPP; + } + +- /* enable crc generation */ +- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); ++ return 0; ++} ++ ++static int ++ltq_etop_dma_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ int tx = priv->tx_irq - LTQ_DMA_ETOP; ++ int rx = priv->rx_irq - LTQ_DMA_ETOP; ++ int err; + + ltq_dma_init_port(DMA_PORT_ETOP); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- int irq = LTQ_DMA_CH0_INT + i; +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- ch->idx = ch->dma.nr = i; +- ch->dma.dev = &priv->pdev->dev; +- +- if (IS_TX(i)) { +- ltq_dma_alloc_tx(&ch->dma); +- request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); +- } else if (IS_RX(i)) { +- ltq_dma_alloc_rx(&ch->dma); +- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; +- ch->dma.desc++) +- if (ltq_etop_alloc_skb(ch)) +- return -ENOMEM; +- ch->dma.desc = 0; +- request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); ++ priv->txch.dma.nr = tx; ++ priv->txch.dma.dev = &priv->pdev->dev; ++ ltq_dma_alloc_tx(&priv->txch.dma); ++ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv); ++ if (err) { ++ netdev_err(dev, "failed to allocate tx irq\n"); ++ goto err_out; ++ } ++ priv->txch.dma.irq = priv->tx_irq; ++ ++ priv->rxch.dma.nr = rx; ++ priv->rxch.dma.dev = &priv->pdev->dev; ++ ltq_dma_alloc_rx(&priv->rxch.dma); ++ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; ++ priv->rxch.dma.desc++) { ++ if (ltq_etop_alloc_skb(&priv->rxch)) { ++ netdev_err(dev, "failed to allocate skbs\n"); ++ err = -ENOMEM; ++ goto err_out; + } +- ch->dma.irq = irq; + } +- return 0; ++ priv->rxch.dma.desc = 0; ++ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv); ++ if (err) ++ netdev_err(dev, "failed to allocate rx irq\n"); ++ else ++ priv->rxch.dma.irq = priv->rx_irq; ++err_out: ++ return err; + } + + static void +@@ -301,6 +447,39 @@ static const struct ethtool_ops ltq_etop + }; + + static int ++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | ++ (phy_data << MDIO_XR9_WR_OFFSET) | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ return 0; ++} ++ ++static int ++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; ++ return val; ++} ++ ++static int + ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) + { + u32 val = MDIO_REQUEST | +@@ -308,9 +487,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | + phy_data; + +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- ltq_etop_w32(val, LTQ_ETOP_MDIO); ++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); + return 0; + } + +@@ -321,12 +500,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in + ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); + +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- ltq_etop_w32(val, LTQ_ETOP_MDIO); +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; ++ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK; + return val; + } + +@@ -342,7 +521,10 @@ ltq_etop_mdio_probe(struct net_device *d + struct ltq_etop_priv *priv = netdev_priv(dev); + struct phy_device *phydev; + +- phydev = phy_find_first(priv->mii_bus); ++ if (of_machine_is_compatible("lantiq,ase")) ++ phydev = mdiobus_get_phy(priv->mii_bus, 8); ++ else ++ phydev = mdiobus_get_phy(priv->mii_bus, 0); + + if (!phydev) { + netdev_err(dev, "no PHY found\n"); +@@ -350,14 +532,17 @@ ltq_etop_mdio_probe(struct net_device *d + } + + phydev = phy_connect(dev, phydev_name(phydev), +- <q_etop_mdio_link, priv->pldata->mii_mode); ++ <q_etop_mdio_link, priv->mii_mode); + + if (IS_ERR(phydev)) { + netdev_err(dev, "Could not attach to PHY\n"); + return PTR_ERR(phydev); + } + +- phy_set_max_speed(phydev, SPEED_100); ++ if (of_machine_is_compatible("lantiq,ar9")) ++ phy_set_max_speed(phydev, SPEED_1000); ++ else ++ phy_set_max_speed(phydev, SPEED_100); + + phy_attached_info(phydev); + +@@ -378,8 +563,13 @@ ltq_etop_mdio_init(struct net_device *de + } + + priv->mii_bus->priv = dev; +- priv->mii_bus->read = ltq_etop_mdio_rd; +- priv->mii_bus->write = ltq_etop_mdio_wr; ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; ++ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; ++ } else { ++ priv->mii_bus->read = ltq_etop_mdio_rd; ++ priv->mii_bus->write = ltq_etop_mdio_wr; ++ } + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + priv->pdev->name, priv->pdev->id); +@@ -416,18 +606,21 @@ static int + ltq_etop_open(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; ++ napi_enable(&priv->txch.napi); ++ napi_enable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_open(&priv->txch.dma); ++ ltq_dma_enable_irq(&priv->txch.dma); ++ ltq_dma_open(&priv->rxch.dma); ++ ltq_dma_enable_irq(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ if (dev->phydev) ++ phy_start(dev->phydev); + +- if (!IS_TX(i) && (!IS_RX(i))) +- continue; +- ltq_dma_open(&ch->dma); +- ltq_dma_enable_irq(&ch->dma); +- napi_enable(&ch->napi); +- } +- phy_start(dev->phydev); + netif_tx_start_all_queues(dev); + return 0; + } +@@ -436,18 +629,19 @@ static int + ltq_etop_stop(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + + netif_tx_stop_all_queues(dev); +- phy_stop(dev->phydev); +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- if (!IS_RX(i) && !IS_TX(i)) +- continue; +- napi_disable(&ch->napi); +- ltq_dma_close(&ch->dma); +- } ++ if (dev->phydev) ++ phy_stop(dev->phydev); ++ napi_disable(&priv->txch.napi); ++ napi_disable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_close(&priv->txch.dma); ++ ltq_dma_close(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ + return 0; + } + +@@ -457,16 +651,16 @@ ltq_etop_tx(struct sk_buff *skb, struct + int queue = skb_get_queue_mapping(skb); + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); + struct ltq_etop_priv *priv = netdev_priv(dev); +- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; +- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +- int len; ++ struct ltq_dma_desc *desc = ++ &priv->txch.dma.desc_base[priv->txch.dma.desc]; + unsigned long flags; + u32 byte_offset; ++ int len; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + +- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { +- dev_kfree_skb_any(skb); ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ++ priv->txch.skb[priv->txch.dma.desc]) { + netdev_err(dev, "tx ring full\n"); + netif_tx_stop_queue(txq); + return NETDEV_TX_BUSY; +@@ -474,7 +668,7 @@ ltq_etop_tx(struct sk_buff *skb, struct + + /* dma needs to start on a 16 byte aligned address */ + byte_offset = CPHYSADDR(skb->data) % 16; +- ch->skb[ch->dma.desc] = skb; ++ priv->txch.skb[priv->txch.dma.desc] = skb; + + netif_trans_update(dev); + +@@ -484,11 +678,11 @@ ltq_etop_tx(struct sk_buff *skb, struct + wmb(); + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); +- ch->dma.desc++; +- ch->dma.desc %= LTQ_DESC_NUM; ++ priv->txch.dma.desc++; ++ priv->txch.dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + +- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) ++ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) + netif_tx_stop_queue(txq); + + return NETDEV_TX_OK; +@@ -499,11 +693,14 @@ ltq_etop_change_mtu(struct net_device *d + { + struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned long flags; ++ int max; + + dev->mtu = new_mtu; + ++ max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN; ++ + spin_lock_irqsave(&priv->lock, flags); +- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); ++ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN); + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +@@ -556,6 +753,9 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_hw; + ltq_etop_change_mtu(dev, 1500); ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + + memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); + if (!is_valid_ether_addr(mac.sa_data)) { +@@ -573,9 +773,10 @@ ltq_etop_init(struct net_device *dev) + dev->addr_assign_type = NET_ADDR_RANDOM; + + ltq_etop_set_multicast_list(dev); +- err = ltq_etop_mdio_init(dev); +- if (err) +- goto err_netdev; ++ if (!ltq_etop_mdio_init(dev)) ++ dev->ethtool_ops = <q_etop_ethtool_ops; ++ else ++ pr_warn("etop: mdio probe failed\n");; + return 0; + + err_netdev: +@@ -595,6 +796,9 @@ ltq_etop_tx_timeout(struct net_device *d + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + netif_trans_update(dev); + netif_wake_queue(dev); + return; +@@ -618,14 +822,18 @@ static const struct net_device_ops ltq_e + .ndo_tx_timeout = ltq_etop_tx_timeout, + }; + +-static int __init +-ltq_etop_probe(struct platform_device *pdev) ++static int ltq_etop_probe(struct platform_device *pdev) + { + struct net_device *dev; + struct ltq_etop_priv *priv; +- struct resource *res; ++ struct resource *res, *gbit_res, irqres[2]; + int err; +- int i; ++ ++ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2); ++ if (err != 2) { ++ dev_err(&pdev->dev, "failed to get etop irqs\n"); ++ return -EINVAL; ++ } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { +@@ -651,31 +859,62 @@ ltq_etop_probe(struct platform_device *p + goto err_out; + } + +- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); +- if (!dev) { +- err = -ENOMEM; +- goto err_out; ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!gbit_res) { ++ dev_err(&pdev->dev, "failed to get gbit resource\n"); ++ err = -ENOENT; ++ goto err_out; ++ } ++ ltq_gbit_membase = devm_ioremap(&pdev->dev, ++ gbit_res->start, resource_size(gbit_res)); ++ if (!ltq_gbit_membase) { ++ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", ++ pdev->id); ++ err = -ENOMEM; ++ goto err_out; ++ } + } ++ ++ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = <q_eth_netdev_ops; +- dev->ethtool_ops = <q_etop_ethtool_ops; + priv = netdev_priv(dev); + priv->res = res; + priv->pdev = pdev; +- priv->pldata = dev_get_platdata(&pdev->dev); + priv->netdev = dev; ++ priv->tx_irq = irqres[0].start; ++ priv->rx_irq = irqres[1].start; ++ err = of_get_phy_mode(pdev->dev.of_node, &priv->mii_mode); ++ if (err) ++ pr_err("Can't find phy-mode for port\n"); ++ ++ of_get_mac_address(pdev->dev.of_node, priv->mac); ++ ++ priv->clk_ppe = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_ppe)) ++ return PTR_ERR(priv->clk_ppe); ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ priv->clk_switch = clk_get(&pdev->dev, "switch"); ++ if (IS_ERR(priv->clk_switch)) ++ return PTR_ERR(priv->clk_switch); ++ } ++ if (of_machine_is_compatible("lantiq,ase")) { ++ priv->clk_ephy = clk_get(&pdev->dev, "ephy"); ++ if (IS_ERR(priv->clk_ephy)) ++ return PTR_ERR(priv->clk_ephy); ++ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); ++ if (IS_ERR(priv->clk_ephycgu)) ++ return PTR_ERR(priv->clk_ephycgu); ++ } ++ + spin_lock_init(&priv->lock); + SET_NETDEV_DEV(dev, &pdev->dev); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- if (IS_TX(i)) +- netif_napi_add(dev, &priv->ch[i].napi, +- ltq_etop_poll_tx, 8); +- else if (IS_RX(i)) +- netif_napi_add(dev, &priv->ch[i].napi, +- ltq_etop_poll_rx, 32); +- priv->ch[i].netdev = dev; +- } ++ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); ++ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); ++ priv->txch.netdev = dev; ++ priv->rxch.netdev = dev; + + err = register_netdev(dev); + if (err) +@@ -704,31 +943,22 @@ ltq_etop_remove(struct platform_device * + return 0; + } + ++static const struct of_device_id ltq_etop_match[] = { ++ { .compatible = "lantiq,etop-xway" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_etop_match); ++ + static struct platform_driver ltq_mii_driver = { ++ .probe = ltq_etop_probe, + .remove = ltq_etop_remove, + .driver = { + .name = "ltq_etop", ++ .of_match_table = ltq_etop_match, + }, + }; + +-int __init +-init_ltq_etop(void) +-{ +- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); +- +- if (ret) +- pr_err("ltq_etop: Error registering platform driver!"); +- return ret; +-} +- +-static void __exit +-exit_ltq_etop(void) +-{ +- platform_driver_unregister(<q_mii_driver); +-} +- +-module_init(init_ltq_etop); +-module_exit(exit_ltq_etop); ++module_platform_driver(ltq_mii_driver); + + MODULE_AUTHOR("John Crispin "); + MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/target/linux/lantiq/patches-5.15/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-5.15/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch new file mode 100644 index 0000000000..2d3b4e2996 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch @@ -0,0 +1,1034 @@ +From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:26:42 +0200 +Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master + +This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. + +Signed-off-by: Thomas Langer +Signed-off-by: John Crispin +--- + drivers/i2c/busses/Kconfig | 10 + + drivers/i2c/busses/Makefile | 1 + + drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++ + drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++ + 4 files changed, 992 insertions(+) + create mode 100644 drivers/i2c/busses/i2c-lantiq.c + create mode 100644 drivers/i2c/busses/i2c-lantiq.h + +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -757,6 +757,16 @@ config I2C_MESON + If you say yes to this option, support will be included for the + I2C interface on the Amlogic Meson family of SoCs. + ++config I2C_LANTIQ ++ tristate "Lantiq I2C interface" ++ depends on LANTIQ && SOC_FALCON ++ help ++ If you say yes to this option, support will be included for the ++ Lantiq I2C core. ++ ++ This driver can also be built as a module. If so, the module ++ will be called i2c-lantiq. ++ + config I2C_MPC + tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" + depends on PPC +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -72,6 +72,7 @@ obj-$(CONFIG_I2C_IMX_LPI2C) += i2c-imx-l + obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o + obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o + obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o ++obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o + obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o + obj-$(CONFIG_I2C_MESON) += i2c-meson.o + obj-$(CONFIG_I2C_MPC) += i2c-mpc.o +--- /dev/null ++++ b/drivers/i2c/busses/i2c-lantiq.c +@@ -0,0 +1,747 @@ ++ ++/* ++ * Lantiq I2C bus adapter ++ * ++ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * Copyright (C) 2012 Thomas Langer ++ */ ++ ++#include ++#include ++#include ++#include /* for kzalloc, kfree */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "i2c-lantiq.h" ++ ++/* ++ * CURRENT ISSUES: ++ * - no high speed support ++ * - ten bit mode is not tested (no slave devices) ++ */ ++ ++/* access macros */ ++#define i2c_r32(reg) \ ++ __raw_readl(&(priv->membase)->reg) ++#define i2c_w32(val, reg) \ ++ __raw_writel(val, &(priv->membase)->reg) ++#define i2c_w32_mask(clear, set, reg) \ ++ i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg) ++ ++#define DRV_NAME "i2c-lantiq" ++#define DRV_VERSION "1.00" ++ ++#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */ ++ ++#ifdef DEBUG ++#define LTQ_I2C_XFER_TIMEOUT (25*HZ) ++#else ++#define LTQ_I2C_XFER_TIMEOUT HZ ++#endif ++ ++#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ ++ I2C_IMSC_I2C_ERR_INT_EN) ++ ++#define LTQ_I2C_ARB_LOST (1 << 0) ++#define LTQ_I2C_NACK (1 << 1) ++#define LTQ_I2C_RX_UFL (1 << 2) ++#define LTQ_I2C_RX_OFL (1 << 3) ++#define LTQ_I2C_TX_UFL (1 << 4) ++#define LTQ_I2C_TX_OFL (1 << 5) ++ ++struct ltq_i2c { ++ struct mutex mutex; ++ ++ ++ /* active clock settings */ ++ unsigned int input_clock; /* clock input for i2c hardware block */ ++ unsigned int i2c_clock; /* approximated bus clock in kHz */ ++ ++ struct clk *clk_gate; ++ struct clk *clk_input; ++ ++ ++ /* resources (memory and interrupts) */ ++ int irq_lb; /* last burst irq */ ++ ++ struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */ ++ ++ struct i2c_adapter adap; ++ struct device *dev; ++ ++ struct completion cmd_complete; ++ ++ ++ /* message transfer data */ ++ struct i2c_msg *current_msg; /* current message */ ++ int msgs_num; /* number of messages to handle */ ++ u8 *msg_buf; /* current buffer */ ++ u32 msg_buf_len; /* remaining length of current buffer */ ++ int msg_err; /* error status of the current transfer */ ++ ++ ++ /* master status codes */ ++ enum { ++ STATUS_IDLE, ++ STATUS_ADDR, /* address phase */ ++ STATUS_WRITE, ++ STATUS_READ, ++ STATUS_READ_END, ++ STATUS_STOP ++ } status; ++}; ++ ++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id); ++ ++static inline void enable_burst_irq(struct ltq_i2c *priv) ++{ ++ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); ++} ++static inline void disable_burst_irq(struct ltq_i2c *priv) ++{ ++ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); ++} ++ ++static void prepare_msg_send_addr(struct ltq_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */ ++ u16 addr = msg->addr; ++ ++ /* new i2c_msg */ ++ priv->msg_buf = msg->buf; ++ priv->msg_buf_len = msg->len; ++ if (rd) ++ priv->status = STATUS_READ; ++ else ++ priv->status = STATUS_WRITE; ++ ++ /* send slave address */ ++ if (msg->flags & I2C_M_TEN) { ++ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); ++ i2c_w32(addr & 0xff, txd); ++ } else { ++ i2c_w32((addr & 0x7f) << 1 | rd, txd); ++ } ++} ++ ++static void ltq_i2c_set_tx_len(struct ltq_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int len = (msg->flags & I2C_M_TEN) ? 2 : 1; ++ ++ pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T'); ++ ++ priv->status = STATUS_ADDR; ++ ++ if (!(msg->flags & I2C_M_RD)) ++ len += msg->len; ++ else ++ /* set maximum received packet size (before rx int!) */ ++ i2c_w32(msg->len, mrps_ctrl); ++ i2c_w32(len, tps_ctrl); ++ enable_burst_irq(priv); ++} ++ ++static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap) ++{ ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ unsigned int input_clock = clk_get_rate(priv->clk_input); ++ u32 dec, inc = 1; ++ ++ /* clock changed? */ ++ if (priv->input_clock == input_clock) ++ return 0; ++ ++ /* ++ * this formula is only an approximation, found by the recommended ++ * values in the "I2C Architecture Specification 1.7.1" ++ */ ++ dec = input_clock / (priv->i2c_clock * 2); ++ if (dec <= 6) ++ return -ENXIO; ++ ++ i2c_w32(0, fdiv_high_cfg); ++ i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) | ++ (dec << I2C_FDIV_CFG_DEC_OFFSET), ++ fdiv_cfg); ++ ++ dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n", ++ input_clock, priv->i2c_clock, dec); ++ ++ priv->input_clock = input_clock; ++ return 0; ++} ++ ++static int ltq_i2c_hw_init(struct i2c_adapter *adap) ++{ ++ int ret = 0; ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++#ifndef DEBUG ++ /* set normal operation clock divider */ ++ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); ++#else ++ /* for debugging a higher divider value! */ ++ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); ++#endif ++ ++ /* setup clock */ ++ ret = ltq_i2c_hw_set_clock(adap); ++ if (ret != 0) { ++ dev_warn(priv->dev, "invalid clock settings\n"); ++ return ret; ++ } ++ ++ /* configure fifo */ ++ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ ++ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ ++ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ ++ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ ++ fifo_cfg); ++ ++ /* configure address */ ++ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in ++ the fifo */ ++ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ ++ I2C_ADDR_CFG_MnS_EN | /* we are master device */ ++ 0, /* our slave address (not used!) */ ++ addr_cfg); ++ ++ /* enable bus */ ++ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); ++ ++ return 0; ++} ++ ++static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv) ++{ ++ unsigned long timeout; ++ ++ timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT); ++ ++ do { ++ u32 stat = i2c_r32(bus_stat); ++ ++ if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE) ++ return 0; ++ ++ cond_resched(); ++ } while (!time_after_eq(jiffies, timeout)); ++ ++ dev_err(priv->dev, "timeout waiting for bus ready\n"); ++ return -ETIMEDOUT; ++} ++ ++static void ltq_i2c_tx(struct ltq_i2c *priv, int last) ++{ ++ if (priv->msg_buf_len && priv->msg_buf) { ++ i2c_w32(*priv->msg_buf, txd); ++ ++ if (--priv->msg_buf_len) ++ priv->msg_buf++; ++ else ++ priv->msg_buf = NULL; ++ } else { ++ last = 1; ++ } ++ ++ if (last) ++ disable_burst_irq(priv); ++} ++ ++static void ltq_i2c_rx(struct ltq_i2c *priv, int last) ++{ ++ u32 fifo_stat, timeout; ++ if (priv->msg_buf_len && priv->msg_buf) { ++ timeout = 5000000; ++ do { ++ fifo_stat = i2c_r32(ffs_stat); ++ } while (!fifo_stat && --timeout); ++ if (!timeout) { ++ last = 1; ++ pr_debug("\nrx timeout\n"); ++ goto err; ++ } ++ while (fifo_stat) { ++ *priv->msg_buf = i2c_r32(rxd); ++ if (--priv->msg_buf_len) { ++ priv->msg_buf++; ++ } else { ++ priv->msg_buf = NULL; ++ last = 1; ++ break; ++ } ++ /* ++ * do not read more than burst size, otherwise no "last ++ * burst" is generated and the transaction is blocked! ++ */ ++ fifo_stat = 0; ++ } ++ } else { ++ last = 1; ++ } ++err: ++ if (last) { ++ disable_burst_irq(priv); ++ ++ if (priv->status == STATUS_READ_END) { ++ /* ++ * do the STATUS_STOP and complete() here, as sometimes ++ * the tx_end is already seen before this is finished ++ */ ++ priv->status = STATUS_STOP; ++ complete(&priv->cmd_complete); ++ } else { ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++ priv->status = STATUS_READ_END; ++ } ++ } ++} ++ ++static void ltq_i2c_xfer_init(struct ltq_i2c *priv) ++{ ++ /* enable interrupts */ ++ i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc); ++ ++ /* trigger transfer of first msg */ ++ ltq_i2c_set_tx_len(priv); ++} ++ ++static void dump_msgs(struct i2c_msg msgs[], int num, int rx) ++{ ++#if defined(DEBUG) ++ int i, j; ++ pr_debug("Messages %d %s\n", num, rx ? "out" : "in"); ++ for (i = 0; i < num; i++) { ++ pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i, ++ (msgs[i].flags & I2C_M_RD) ? 'R' : 'T', ++ msgs[i].len, msgs[i].addr); ++ if (!(msgs[i].flags & I2C_M_RD) || rx) { ++ for (j = 0; j < msgs[i].len; j++) ++ pr_debug("%02X ", msgs[i].buf[j]); ++ } ++ pr_debug("\n"); ++ } ++#endif ++} ++ ++static void ltq_i2c_release_bus(struct ltq_i2c *priv) ++{ ++ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++} ++ ++static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], ++ int num) ++{ ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ int ret; ++ ++ dev_dbg(priv->dev, "xfer %u messages\n", num); ++ dump_msgs(msgs, num, 0); ++ ++ mutex_lock(&priv->mutex); ++ ++ init_completion(&priv->cmd_complete); ++ priv->current_msg = msgs; ++ priv->msgs_num = num; ++ priv->msg_err = 0; ++ priv->status = STATUS_IDLE; ++ ++ /* wait for the bus to become ready */ ++ ret = ltq_i2c_wait_bus_not_busy(priv); ++ if (ret) ++ goto done; ++ ++ while (priv->msgs_num) { ++ /* start the transfers */ ++ ltq_i2c_xfer_init(priv); ++ ++ /* wait for transfers to complete */ ++ ret = wait_for_completion_interruptible_timeout( ++ &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT); ++ if (ret == 0) { ++ dev_err(priv->dev, "controller timed out\n"); ++ ltq_i2c_hw_init(adap); ++ ret = -ETIMEDOUT; ++ goto done; ++ } else if (ret < 0) ++ goto done; ++ ++ if (priv->msg_err) { ++ if (priv->msg_err & LTQ_I2C_NACK) ++ ret = -ENXIO; ++ else ++ ret = -EREMOTEIO; ++ goto done; ++ } ++ if (--priv->msgs_num) ++ priv->current_msg++; ++ } ++ /* no error? */ ++ ret = num; ++ ++done: ++ ltq_i2c_release_bus(priv); ++ ++ mutex_unlock(&priv->mutex); ++ ++ if (ret >= 0) ++ dump_msgs(msgs, num, 1); ++ ++ pr_debug("XFER ret %d\n", ret); ++ return ret; ++} ++ ++static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id) ++{ ++ struct ltq_i2c *priv = dev_id; ++ struct i2c_msg *msg = priv->current_msg; ++ int last = (irq == priv->irq_lb); ++ ++ if (last) ++ pr_debug("LB "); ++ else ++ pr_debug("B "); ++ ++ if (msg->flags & I2C_M_RD) { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ pr_debug("X"); ++ prepare_msg_send_addr(priv); ++ disable_burst_irq(priv); ++ break; ++ case STATUS_READ: ++ case STATUS_READ_END: ++ pr_debug("R"); ++ ltq_i2c_rx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ pr_warn("Status R %d\n", priv->status); ++ break; ++ } ++ } else { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ pr_debug("x"); ++ prepare_msg_send_addr(priv); ++ break; ++ case STATUS_WRITE: ++ pr_debug("w"); ++ ltq_i2c_tx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ pr_warn("Status W %d\n", priv->status); ++ break; ++ } ++ } ++ ++ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); ++ return IRQ_HANDLED; ++} ++ ++static void ltq_i2c_isr_prot(struct ltq_i2c *priv) ++{ ++ u32 i_pro = i2c_r32(p_irqss); ++ ++ pr_debug("i2c-p"); ++ ++ /* not acknowledge */ ++ if (i_pro & I2C_P_IRQSS_NACK) { ++ priv->msg_err |= LTQ_I2C_NACK; ++ pr_debug(" nack"); ++ } ++ ++ /* arbitration lost */ ++ if (i_pro & I2C_P_IRQSS_AL) { ++ priv->msg_err |= LTQ_I2C_ARB_LOST; ++ pr_debug(" arb-lost"); ++ } ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) ++ pr_debug(" rx"); ++ ++ /* tx end */ ++ if (i_pro & I2C_P_IRQSS_TX_END) ++ pr_debug(" txend"); ++ pr_debug("\n"); ++ ++ if (!priv->msg_err) { ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) { ++ priv->status = STATUS_READ; ++ enable_burst_irq(priv); ++ } ++ if (i_pro & I2C_P_IRQSS_TX_END) { ++ if (priv->status == STATUS_READ) ++ priv->status = STATUS_READ_END; ++ else { ++ disable_burst_irq(priv); ++ priv->status = STATUS_STOP; ++ } ++ } ++ } ++ ++ i2c_w32(i_pro, p_irqsc); ++} ++ ++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id) ++{ ++ u32 i_raw, i_err = 0; ++ struct ltq_i2c *priv = dev_id; ++ ++ i_raw = i2c_r32(mis); ++ pr_debug("i_raw 0x%08X\n", i_raw); ++ ++ /* error interrupt */ ++ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { ++ i_err = i2c_r32(err_irqss); ++ pr_debug("i_err 0x%08X bus_stat 0x%04X\n", ++ i_err, i2c_r32(bus_stat)); ++ ++ /* tx fifo overflow (8) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_OFL) ++ priv->msg_err |= LTQ_I2C_TX_OFL; ++ ++ /* tx fifo underflow (4) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_UFL) ++ priv->msg_err |= LTQ_I2C_TX_UFL; ++ ++ /* rx fifo overflow (2) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_OFL) ++ priv->msg_err |= LTQ_I2C_RX_OFL; ++ ++ /* rx fifo underflow (1) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_UFL) ++ priv->msg_err |= LTQ_I2C_RX_UFL; ++ ++ i2c_w32(i_err, err_irqsc); ++ } ++ ++ /* protocol interrupt */ ++ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) ++ ltq_i2c_isr_prot(priv); ++ ++ if ((priv->msg_err) || (priv->status == STATUS_STOP)) ++ complete(&priv->cmd_complete); ++ ++ return IRQ_HANDLED; ++} ++ ++static u32 ltq_i2c_functionality(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | ++ I2C_FUNC_10BIT_ADDR | ++ I2C_FUNC_SMBUS_EMUL; ++} ++ ++static struct i2c_algorithm ltq_i2c_algorithm = { ++ .master_xfer = ltq_i2c_xfer, ++ .functionality = ltq_i2c_functionality, ++}; ++ ++static int ltq_i2c_probe(struct platform_device *pdev) ++{ ++ struct device_node *node = pdev->dev.of_node; ++ struct ltq_i2c *priv; ++ struct i2c_adapter *adap; ++ struct resource *mmres, irqres[4]; ++ int ret = 0; ++ ++ dev_dbg(&pdev->dev, "probing\n"); ++ ++ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ret = of_irq_to_resource_table(node, irqres, 4); ++ if (!mmres || (ret != 4)) { ++ dev_err(&pdev->dev, "no resources\n"); ++ return -ENODEV; ++ } ++ ++ /* allocate private data */ ++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) { ++ dev_err(&pdev->dev, "can't allocate private data\n"); ++ return -ENOMEM; ++ } ++ ++ adap = &priv->adap; ++ i2c_set_adapdata(adap, priv); ++ adap->owner = THIS_MODULE; ++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; ++ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); ++ adap->algo = <q_i2c_algorithm; ++ adap->dev.parent = &pdev->dev; ++ adap->dev.of_node = pdev->dev.of_node; ++ ++ if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) { ++ dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n"); ++ priv->i2c_clock = 100000; ++ } ++ ++ init_completion(&priv->cmd_complete); ++ mutex_init(&priv->mutex); ++ ++ priv->membase = devm_ioremap_resource(&pdev->dev, mmres); ++ if (IS_ERR(priv->membase)) ++ return PTR_ERR(priv->membase); ++ ++ priv->dev = &pdev->dev; ++ priv->irq_lb = irqres[0].start; ++ ++ ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst, ++ 0x0, "i2c lb", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", ++ irqres[0].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst, ++ 0x0, "i2c b", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get burst IRQ %d\n", ++ irqres[1].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr, ++ 0x0, "i2c err", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get error IRQ %d\n", ++ irqres[2].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr, ++ 0x0, "i2c p", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", ++ irqres[3].start); ++ return -ENODEV; ++ } ++ ++ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); ++ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start, ++ irqres[1].start, irqres[2].start, irqres[3].start); ++ ++ priv->clk_gate = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_gate)) { ++ dev_err(&pdev->dev, "failed to get i2c clk\n"); ++ return -ENOENT; ++ } ++ ++ /* this is a static clock, which has no refcounting */ ++ priv->clk_input = clk_get_fpi(); ++ if (IS_ERR(priv->clk_input)) { ++ dev_err(&pdev->dev, "failed to get fpi clk\n"); ++ return -ENOENT; ++ } ++ ++ clk_activate(priv->clk_gate); ++ ++ /* add our adapter to the i2c stack */ ++ ret = i2c_add_numbered_adapter(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't register I2C adapter\n"); ++ goto out; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ i2c_set_adapdata(adap, priv); ++ ++ /* print module version information */ ++ dev_dbg(&pdev->dev, "module id=%u revision=%u\n", ++ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, ++ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); ++ ++ /* initialize HW */ ++ ret = ltq_i2c_hw_init(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't configure adapter\n"); ++ i2c_del_adapter(adap); ++ platform_set_drvdata(pdev, NULL); ++ goto out; ++ } else { ++ dev_info(&pdev->dev, "version %s\n", DRV_VERSION); ++ } ++ ++out: ++ /* if init failed, we need to deactivate the clock gate */ ++ if (ret) ++ clk_deactivate(priv->clk_gate); ++ ++ return ret; ++} ++ ++static int ltq_i2c_remove(struct platform_device *pdev) ++{ ++ struct ltq_i2c *priv = platform_get_drvdata(pdev); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++ /* power down the core */ ++ clk_deactivate(priv->clk_gate); ++ ++ /* remove driver */ ++ i2c_del_adapter(&priv->adap); ++ kfree(priv); ++ ++ dev_dbg(&pdev->dev, "removed\n"); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++static const struct of_device_id ltq_i2c_match[] = { ++ { .compatible = "lantiq,lantiq-i2c" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_i2c_match); ++ ++static struct platform_driver ltq_i2c_driver = { ++ .probe = ltq_i2c_probe, ++ .remove = ltq_i2c_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = ltq_i2c_match, ++ }, ++}; ++ ++module_platform_driver(ltq_i2c_driver); ++ ++MODULE_DESCRIPTION("Lantiq I2C bus adapter"); ++MODULE_AUTHOR("Thomas Langer "); ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); +--- /dev/null ++++ b/drivers/i2c/busses/i2c-lantiq.h +@@ -0,0 +1,234 @@ ++#ifndef I2C_LANTIQ_H ++#define I2C_LANTIQ_H ++ ++/* I2C register structure */ ++struct lantiq_reg_i2c { ++ /* I2C Kernel Clock Control Register */ ++ unsigned int clc; /* 0x00000000 */ ++ /* Reserved */ ++ unsigned int res_0; /* 0x00000004 */ ++ /* I2C Identification Register */ ++ unsigned int id; /* 0x00000008 */ ++ /* Reserved */ ++ unsigned int res_1; /* 0x0000000C */ ++ /* ++ * I2C RUN Control Register ++ * This register enables and disables the I2C peripheral. Before ++ * enabling, the I2C has to be configured properly. After enabling ++ * no configuration is possible ++ */ ++ unsigned int run_ctrl; /* 0x00000010 */ ++ /* ++ * I2C End Data Control Register ++ * This register is used to either turn around the data transmission ++ * direction or to address another slave without sending a stop ++ * condition. Also the software can stop the slave-transmitter by ++ * sending a not-accolade when working as master-receiver or even ++ * stop data transmission immediately when operating as ++ * master-transmitter. The writing to the bits of this control ++ * register is only effective when in MASTER RECEIVES BYTES, MASTER ++ * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state ++ */ ++ unsigned int endd_ctrl; /* 0x00000014 */ ++ /* ++ * I2C Fractional Divider Configuration Register ++ * These register is used to program the fractional divider of the I2C ++ * bus. Before the peripheral is switched on by setting the RUN-bit the ++ * two (fixed) values for the two operating frequencies are programmed ++ * into these (configuration) registers. The Register FDIV_HIGH_CFG has ++ * the same layout as I2C_FDIV_CFG. ++ */ ++ unsigned int fdiv_cfg; /* 0x00000018 */ ++ /* ++ * I2C Fractional Divider (highspeed mode) Configuration Register ++ * These register is used to program the fractional divider of the I2C ++ * bus. Before the peripheral is switched on by setting the RUN-bit the ++ * two (fixed) values for the two operating frequencies are programmed ++ * into these (configuration) registers. The Register FDIV_CFG has the ++ * same layout as I2C_FDIV_CFG. ++ */ ++ unsigned int fdiv_high_cfg; /* 0x0000001C */ ++ /* I2C Address Configuration Register */ ++ unsigned int addr_cfg; /* 0x00000020 */ ++ /* I2C Bus Status Register ++ * This register gives a status information of the I2C. This additional ++ * information can be used by the software to start proper actions. ++ */ ++ unsigned int bus_stat; /* 0x00000024 */ ++ /* I2C FIFO Configuration Register */ ++ unsigned int fifo_cfg; /* 0x00000028 */ ++ /* I2C Maximum Received Packet Size Register */ ++ unsigned int mrps_ctrl; /* 0x0000002C */ ++ /* I2C Received Packet Size Status Register */ ++ unsigned int rps_stat; /* 0x00000030 */ ++ /* I2C Transmit Packet Size Register */ ++ unsigned int tps_ctrl; /* 0x00000034 */ ++ /* I2C Filled FIFO Stages Status Register */ ++ unsigned int ffs_stat; /* 0x00000038 */ ++ /* Reserved */ ++ unsigned int res_2; /* 0x0000003C */ ++ /* I2C Timing Configuration Register */ ++ unsigned int tim_cfg; /* 0x00000040 */ ++ /* Reserved */ ++ unsigned int res_3[7]; /* 0x00000044 */ ++ /* I2C Error Interrupt Request Source Mask Register */ ++ unsigned int err_irqsm; /* 0x00000060 */ ++ /* I2C Error Interrupt Request Source Status Register */ ++ unsigned int err_irqss; /* 0x00000064 */ ++ /* I2C Error Interrupt Request Source Clear Register */ ++ unsigned int err_irqsc; /* 0x00000068 */ ++ /* Reserved */ ++ unsigned int res_4; /* 0x0000006C */ ++ /* I2C Protocol Interrupt Request Source Mask Register */ ++ unsigned int p_irqsm; /* 0x00000070 */ ++ /* I2C Protocol Interrupt Request Source Status Register */ ++ unsigned int p_irqss; /* 0x00000074 */ ++ /* I2C Protocol Interrupt Request Source Clear Register */ ++ unsigned int p_irqsc; /* 0x00000078 */ ++ /* Reserved */ ++ unsigned int res_5; /* 0x0000007C */ ++ /* I2C Raw Interrupt Status Register */ ++ unsigned int ris; /* 0x00000080 */ ++ /* I2C Interrupt Mask Control Register */ ++ unsigned int imsc; /* 0x00000084 */ ++ /* I2C Masked Interrupt Status Register */ ++ unsigned int mis; /* 0x00000088 */ ++ /* I2C Interrupt Clear Register */ ++ unsigned int icr; /* 0x0000008C */ ++ /* I2C Interrupt Set Register */ ++ unsigned int isr; /* 0x00000090 */ ++ /* I2C DMA Enable Register */ ++ unsigned int dmae; /* 0x00000094 */ ++ /* Reserved */ ++ unsigned int res_6[8154]; /* 0x00000098 */ ++ /* I2C Transmit Data Register */ ++ unsigned int txd; /* 0x00008000 */ ++ /* Reserved */ ++ unsigned int res_7[4095]; /* 0x00008004 */ ++ /* I2C Receive Data Register */ ++ unsigned int rxd; /* 0x0000C000 */ ++ /* Reserved */ ++ unsigned int res_8[4095]; /* 0x0000C004 */ ++}; ++ ++/* ++ * Clock Divider for Normal Run Mode ++ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long ++ * as the new divider value RMC is not valid, the register returns 0x0000 00xx ++ * on reading. ++ */ ++#define I2C_CLC_RMC_MASK 0x0000FF00 ++/* field offset */ ++#define I2C_CLC_RMC_OFFSET 8 ++ ++/* Fields of "I2C Identification Register" */ ++/* Module ID */ ++#define I2C_ID_ID_MASK 0x0000FF00 ++/* field offset */ ++#define I2C_ID_ID_OFFSET 8 ++/* Revision */ ++#define I2C_ID_REV_MASK 0x000000FF ++/* field offset */ ++#define I2C_ID_REV_OFFSET 0 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/* Enable */ ++#define I2C_IMSC_BREQ_INT_EN 0x00000008 ++/* Enable */ ++#define I2C_IMSC_LBREQ_INT_EN 0x00000004 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/* field offset */ ++#define I2C_FDIV_CFG_INC_OFFSET 16 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/* Enable */ ++#define I2C_IMSC_I2C_P_INT_EN 0x00000020 ++/* Enable */ ++#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 ++ ++/* Fields of "I2C Error Interrupt Request Source Status Register" */ ++/* TXF_OFL */ ++#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 ++/* TXF_UFL */ ++#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 ++/* RXF_OFL */ ++#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 ++/* RXF_UFL */ ++#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 ++ ++/* Fields of "I2C Raw Interrupt Status Register" */ ++/* Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 ++/* Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/* TX FIFO Flow Control */ ++#define I2C_FIFO_CFG_TXFC 0x00020000 ++/* RX FIFO Flow Control */ ++#define I2C_FIFO_CFG_RXFC 0x00010000 ++/* Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 ++/* Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 ++/* 1 word */ ++#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/* 1 word */ ++#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 ++/* Stop on Packet End Enable */ ++#define I2C_ADDR_CFG_SOPE_EN 0x00200000 ++/* Stop on Not Acknowledge Enable */ ++#define I2C_ADDR_CFG_SONA_EN 0x00100000 ++/* Enable */ ++#define I2C_ADDR_CFG_MnS_EN 0x00080000 ++ ++/* Fields of "I2C Interrupt Clear Register" */ ++/* Clear */ ++#define I2C_ICR_BREQ_INT_CLR 0x00000008 ++/* Clear */ ++#define I2C_ICR_LBREQ_INT_CLR 0x00000004 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/* field offset */ ++#define I2C_FDIV_CFG_DEC_OFFSET 0 ++ ++/* Fields of "I2C Bus Status Register" */ ++/* Bus Status */ ++#define I2C_BUS_STAT_BS_MASK 0x00000003 ++/* Read from I2C Bus. */ ++#define I2C_BUS_STAT_RNW_READ 0x00000004 ++/* I2C Bus is free. */ ++#define I2C_BUS_STAT_BS_FREE 0x00000000 ++/* ++ * The device is working as master and has claimed the control on the ++ * I2C-bus (busy master). ++ */ ++#define I2C_BUS_STAT_BS_BM 0x00000002 ++ ++/* Fields of "I2C RUN Control Register" */ ++/* Enable */ ++#define I2C_RUN_CTRL_RUN_EN 0x00000001 ++ ++/* Fields of "I2C End Data Control Register" */ ++/* ++ * Set End of Transmission ++ * Note:Do not write '1' to this bit when bus is free. This will cause an ++ * abort after the first byte when a new transfer is started. ++ */ ++#define I2C_ENDD_CTRL_SETEND 0x00000002 ++ ++/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ ++/* NACK */ ++#define I2C_P_IRQSS_NACK 0x00000010 ++/* AL */ ++#define I2C_P_IRQSS_AL 0x00000008 ++/* RX */ ++#define I2C_P_IRQSS_RX 0x00000040 ++/* TX_END */ ++#define I2C_P_IRQSS_TX_END 0x00000020 ++ ++ ++#endif /* I2C_LANTIQ_H */ diff --git a/target/linux/lantiq/patches-5.15/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-5.15/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch new file mode 100644 index 0000000000..c80045e878 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch @@ -0,0 +1,218 @@ +From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 10 Sep 2014 22:42:14 +0200 +Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling + +Signed-off-by: John Crispin +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + + arch/mips/lantiq/xway/Makefile | 3 + + arch/mips/lantiq/xway/ath5k_eep.c | 136 +++++++++++++++++++++ + arch/mips/lantiq/xway/eth_mac.c | 25 ++++ + drivers/net/ethernet/lantiq_etop.c | 6 +- + 5 files changed, 172 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c + create mode 100644 arch/mips/lantiq/xway/eth_mac.c + +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -102,5 +102,8 @@ int xrx200_gphy_boot(struct device *dev, + extern void ltq_pmu_enable(unsigned int module); + extern void ltq_pmu_disable(unsigned int module); + ++/* allow the ethernet driver to load a flash mapped mac addr */ ++const u8* ltq_get_eth_mac(void); ++ + #endif /* CONFIG_SOC_TYPE_XWAY */ + #endif /* _LTQ_XWAY_H__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -8,3 +8,6 @@ obj-y += timer.o + endif + + obj-y += vmmc.o ++ ++obj-y += eth_mac.o ++obj-$(CONFIG_PCI) += ath5k_eep.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/ath5k_eep.c +@@ -0,0 +1,136 @@ ++/* ++ * Copyright (C) 2011 Luca Olivetti ++ * Copyright (C) 2011 John Crispin ++ * Copyright (C) 2011 Andrej Vlašić ++ * Copyright (C) 2013 Álvaro Fernández Rojas ++ * Copyright (C) 2013 Daniel Gimpelevich ++ * Copyright (C) 2015 Vittorio Gambaletta ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); ++struct ath5k_platform_data ath5k_pdata; ++static u8 athxk_eeprom_mac[6]; ++ ++static int ath5k_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ dev->dev.platform_data = &ath5k_pdata; ++ return 0; ++} ++ ++static int ath5k_eep_load; ++int __init of_ath5k_eeprom_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node, *mtd_np = NULL; ++ int mac_offset; ++ u32 mac_inc = 0; ++ int i; ++ struct mtd_info *the_mtd; ++ size_t flash_readlen; ++ const __be32 *list; ++ const char *part; ++ phandle phandle; ++ ++ list = of_get_property(np, "ath,eep-flash", &i); ++ if (!list || (i != (2 * sizeof(*list)))) ++ return -ENODEV; ++ ++ phandle = be32_to_cpup(list++); ++ if (phandle) ++ mtd_np = of_find_node_by_phandle(phandle); ++ ++ if (!mtd_np) ++ return -ENODEV; ++ ++ part = of_get_property(mtd_np, "label", NULL); ++ if (!part) ++ part = mtd_np->name; ++ ++ the_mtd = get_mtd_device_nm(part); ++ if (IS_ERR(the_mtd)) ++ return -ENODEV; ++ ++ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL); ++ ++ i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1, ++ &flash_readlen, (void *) ath5k_pdata.eeprom_data); ++ ++ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) { ++ size_t mac_readlen; ++ mtd_read(the_mtd, mac_offset, 6, &mac_readlen, ++ (void *) athxk_eeprom_mac); ++ } ++ put_mtd_device(the_mtd); ++ ++ if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) { ++ dev_err(&pdev->dev, "failed to load eeprom from mtd\n"); ++ return -ENODEV; ++ } ++ ++ if (of_find_property(np, "ath,eep-swap", NULL)) ++ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++) ++ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]); ++ ++ if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac()) ++ ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac()); ++ ++ if (!is_valid_ether_addr(athxk_eeprom_mac)) { ++ dev_warn(&pdev->dev, "using random mac\n"); ++ random_ether_addr(athxk_eeprom_mac); ++ } ++ ++ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc)) ++ athxk_eeprom_mac[5] += mac_inc; ++ ++ ath5k_pdata.macaddr = athxk_eeprom_mac; ++ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init; ++ ++ dev_info(&pdev->dev, "loaded ath5k eeprom\n"); ++ ++ return 0; ++} ++ ++static struct of_device_id ath5k_eeprom_ids[] = { ++ { .compatible = "ath5k,eeprom" }, ++ { } ++}; ++ ++static struct platform_driver ath5k_eeprom_driver = { ++ .driver = { ++ .name = "ath5k,eeprom", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ath5k_eeprom_ids), ++ }, ++}; ++ ++static int __init of_ath5k_eeprom_init(void) ++{ ++ int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); ++ ++ if (ret) ++ ath5k_eep_load = 1; ++ ++ return ret; ++} ++ ++static int __init of_ath5k_eeprom_init_late(void) ++{ ++ if (!ath5k_eep_load) ++ return 0; ++ ++ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); ++} ++late_initcall(of_ath5k_eeprom_init_late); ++subsys_initcall(of_ath5k_eeprom_init); +--- /dev/null ++++ b/arch/mips/lantiq/xway/eth_mac.c +@@ -0,0 +1,25 @@ ++/* ++ * Copyright (C) 2012 John Crispin ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++static u8 eth_mac[6]; ++static int eth_mac_set; ++ ++const u8* ltq_get_eth_mac(void) ++{ ++ return eth_mac; ++} ++ ++static int __init setup_ethaddr(char *str) ++{ ++ eth_mac_set = mac_pton(str, eth_mac); ++ return !eth_mac_set; ++} ++early_param("ethaddr", setup_ethaddr); +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -757,7 +757,11 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_hw; + +- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); ++ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN); ++ ++ if (priv->mac && !is_valid_ether_addr(mac.sa_data)) ++ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); ++ + if (!is_valid_ether_addr(mac.sa_data)) { + pr_warn("etop: invalid MAC, using random\n"); + eth_random_addr(mac.sa_data); diff --git a/target/linux/lantiq/patches-5.15/0042-arch-mips-increase-io_space_limit.patch b/target/linux/lantiq/patches-5.15/0042-arch-mips-increase-io_space_limit.patch new file mode 100644 index 0000000000..c81222af57 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0042-arch-mips-increase-io_space_limit.patch @@ -0,0 +1,24 @@ +From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Jun 2016 13:12:20 +0200 +Subject: [PATCH] arch: mips: increase io_space_limit + +this value comes from x86 and breaks some pci devices + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/spaces.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + create mode 100644 arch/mips/include/asm/mach-lantiq/spaces.h + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/spaces.h +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef __ASM_MACH_LANTIQ_SPACES_H_ ++#define __ASM_MACH_LANTIQ_SPACES_H_ ++ ++#define IO_SPACE_LIMIT 0xffffffff ++ ++#include ++#endif diff --git a/target/linux/lantiq/patches-5.15/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch b/target/linux/lantiq/patches-5.15/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch new file mode 100644 index 0000000000..6615a9edbf --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch @@ -0,0 +1,78 @@ +From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Fri, 6 Jan 2017 17:55:24 +0100 +Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs + +The size of the internal RAM of the DesignWare USB controller changed +between the different Lantiq SoCs. We have the following sizes: + +Amazon + Danube: 8 KByte +Amazon SE + arx100: 2 KByte +xrx200 + xrx300: 2.5 KByte + +For Danube SoC we do not provide the params and let the driver decide +to use sane defaults, for the Amazon SE and arx100 we use small fifos +and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo. +The auto detection of max_transfer_size and max_packet_count should +work, so remove it. + +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++------- + 1 file changed, 39 insertions(+), 7 deletions(-) + +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -93,7 +93,14 @@ static void dwc2_set_rk_params(struct dw + p->power_down = DWC2_POWER_DOWN_PARAM_NONE; + } + +-static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) ++static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg) ++{ ++ struct dwc2_core_params *p = &hsotg->params; ++ ++ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; ++} ++ ++static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg) + { + struct dwc2_core_params *p = &hsotg->params; + +@@ -101,12 +108,20 @@ static void dwc2_set_ltq_params(struct d + p->host_rx_fifo_size = 288; + p->host_nperio_tx_fifo_size = 128; + p->host_perio_tx_fifo_size = 96; +- p->max_transfer_size = 65535; +- p->max_packet_count = 511; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << + GAHBCFG_HBSTLEN_SHIFT; + } + ++static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg) ++{ ++ struct dwc2_core_params *p = &hsotg->params; ++ ++ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; ++ p->host_rx_fifo_size = 288; ++ p->host_nperio_tx_fifo_size = 128; ++ p->host_perio_tx_fifo_size = 136; ++} ++ + static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) + { + struct dwc2_core_params *p = &hsotg->params; +@@ -205,8 +220,11 @@ const struct of_device_id dwc2_of_match_ + { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, + { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, + { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, +- { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, +- { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, ++ { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params }, ++ { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params }, ++ { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params }, ++ { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params }, ++ { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params }, + { .compatible = "snps,dwc2" }, + { .compatible = "samsung,s3c6400-hsotg", + .data = dwc2_set_s3c6400_params }, diff --git a/target/linux/lantiq/patches-5.15/0051-MIPS-lantiq-improve-USB-initialization.patch b/target/linux/lantiq/patches-5.15/0051-MIPS-lantiq-improve-USB-initialization.patch new file mode 100644 index 0000000000..9d62892b56 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0051-MIPS-lantiq-improve-USB-initialization.patch @@ -0,0 +1,49 @@ +From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Fri, 6 Jan 2017 17:40:12 +0100 +Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization + +This adds code to initialize the USB controller and PHY also on Danube, +Amazon SE and AR10. This code is based on the Vendor driver from +different UGW versions and compared to the hardware documentation. + +Signed-off-by: Hauke Mehrtens +--- + arch/mips/lantiq/xway/sysctrl.c | 20 +++++++ + 2 files changed, 110 insertions(+), 30 deletions(-) + + +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -248,6 +248,25 @@ static void pmu_disable(struct clk *clk) + pr_warn("deactivating PMU module failed!"); + } + ++static void usb_set_clock(void) ++{ ++ unsigned int val = ltq_cgu_r32(ifccr); ++ ++ if (of_machine_is_compatible("lantiq,ar10") || ++ of_machine_is_compatible("lantiq,grx390")) { ++ val &= ~0x03; /* XTAL divided by 3 */ ++ } else if (of_machine_is_compatible("lantiq,ar9") || ++ of_machine_is_compatible("lantiq,vr9")) { ++ /* TODO: this depends on the XTAL frequency */ ++ val |= 0x03; /* XTAL divided by 3 */ ++ } else if (of_machine_is_compatible("lantiq,ase")) { ++ val |= 0x20; /* from XTAL */ ++ } else if (of_machine_is_compatible("lantiq,danube")) { ++ val |= 0x30; /* 12 MHz, generated from 36 MHz */ ++ } ++ ltq_cgu_w32(val, ifccr); ++} ++ + /* the pci enable helper */ + static int pci_enable(struct clk *clk) + { +@@ -585,4 +604,5 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); + clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); + } ++ usb_set_clock(); + } diff --git a/target/linux/lantiq/patches-5.15/0101-find_active_root.patch b/target/linux/lantiq/patches-5.15/0101-find_active_root.patch new file mode 100644 index 0000000000..925ac9dbba --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0101-find_active_root.patch @@ -0,0 +1,93 @@ +--- a/drivers/mtd/parsers/ofpart_core.c ++++ b/drivers/mtd/parsers/ofpart_core.c +@@ -38,6 +38,38 @@ static bool node_has_compatible(struct d + return of_get_property(pp, "compatible", NULL); + } + ++static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master, ++ loff_t offset) ++{ ++ static uint8_t root_id; ++ int err, len; ++ ++ err = mtd_read(master, offset, 0x01, &len, &root_id); ++ ++ if (mtd_is_bitflip(err) || !err) ++ return &root_id; ++ ++ return NULL; ++} ++ ++static void brnboot_set_active_root_part(struct mtd_partition *pparts, ++ struct device_node **part_nodes, ++ int nr_parts, ++ uint8_t *root_id) ++{ ++ int i; ++ ++ for (i = 0; i < nr_parts; i++) { ++ int part_root_id; ++ ++ if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id) ++ && part_root_id == *root_id) { ++ pparts[i].name = "firmware"; ++ break; ++ } ++ } ++} ++ + static int parse_fixed_partitions(struct mtd_info *master, + const struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +@@ -51,6 +83,8 @@ static int parse_fixed_partitions(struct + struct device_node *pp; + int nr_parts, i, ret = 0; + bool dedicated = true; ++ uint8_t *proot_id = NULL; ++ struct device_node **part_nodes; + + /* Pull of_node from the master device node */ + mtd_node = mtd_get_of_node(master); +@@ -95,7 +129,9 @@ static int parse_fixed_partitions(struct + return 0; + + parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); +- if (!parts) ++ part_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL); ++ ++ if (!parts || !part_nodes) + return -ENOMEM; + + i = 0; +@@ -147,6 +183,11 @@ static int parse_fixed_partitions(struct + if (of_property_read_bool(pp, "slc-mode")) + parts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION; + ++ if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector")) ++ proot_id = brnboot_get_selected_root_part(master, parts[i].offset); ++ ++ part_nodes[i] = pp; ++ + i++; + } + +@@ -156,6 +197,11 @@ static int parse_fixed_partitions(struct + if (quirks && quirks->post_parse) + quirks->post_parse(master, parts, nr_parts); + ++ if (proot_id) ++ brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id); ++ ++ kfree(part_nodes); ++ + *pparts = parts; + return nr_parts; + +@@ -166,6 +212,7 @@ ofpart_fail: + ofpart_none: + of_node_put(pp); + kfree(parts); ++ kfree(part_nodes); + return ret; + } + diff --git a/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch new file mode 100644 index 0000000000..10633199e6 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch @@ -0,0 +1,387 @@ +--- a/arch/mips/pci/ifxmips_pcie.c ++++ b/arch/mips/pci/ifxmips_pcie.c +@@ -16,8 +16,15 @@ + #include + #include + #include ++#include ++#include ++#include ++#include + #include + ++#include ++#include ++ + #include "ifxmips_pcie.h" + #include "ifxmips_pcie_reg.h" + +@@ -40,6 +47,10 @@ + static DEFINE_SPINLOCK(ifx_pcie_lock); + + u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); ++static int pcie_reset_gpio; ++static struct phy *ltq_pcie_phy; ++static struct reset_control *ltq_pcie_reset; ++static struct regmap *ltq_rcu_regmap; + + static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { + { +@@ -82,6 +93,22 @@ void ifx_pcie_debug(const char *fmt, ... + printk("%s", buf); + } + ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ gpio_direction_output(pcie_reset_gpio, 1); ++ gpio_set_value(pcie_reset_gpio, 1); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ gpio_set_value(pcie_reset_gpio, 0); ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ gpio_direction_output(pcie_reset_gpio, 1); ++} + + static inline int pcie_ltssm_enable(int pcie_port) + { +@@ -988,10 +1015,22 @@ int ifx_pcie_bios_plat_dev_init(struct + static int + pcie_rc_initialize(int pcie_port) + { +- int i; ++ int i, ret; + #define IFX_PCIE_PHY_LOOP_CNT 5 + +- pcie_rcu_endian_setup(pcie_port); ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_M, ++ IFX_RCU_AHB_BE_PCIE_M); ++ ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S, ++ IFX_RCU_AHB_BE_PCIE_S); ++#else ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S, ++ 0x0); ++#endif ++ ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_M, ++ 0x0); + + pcie_ep_gpio_rst_init(pcie_port); + +@@ -1000,26 +1039,21 @@ pcie_rc_initialize(int pcie_port) + * reset PCIe PHY will solve this issue + */ + for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { +- /* Disable PCIe PHY Analog part for sanity check */ +- pcie_phy_pmu_disable(pcie_port); +- +- pcie_phy_rst_assert(pcie_port); +- pcie_phy_rst_deassert(pcie_port); +- +- /* Make sure PHY PLL is stable */ +- udelay(20); +- +- /* PCIe Core reset enabled, low active, sw programmed */ +- pcie_core_rst_assert(pcie_port); ++ ret = phy_init(ltq_pcie_phy); ++ if (ret) ++ continue; + + /* Put PCIe EP in reset status */ + pcie_device_rst_assert(pcie_port); + +- /* PCI PHY & Core reset disabled, high active, sw programmed */ +- pcie_core_rst_deassert(pcie_port); ++ udelay(1); ++ reset_control_deassert(ltq_pcie_reset); + +- /* Already in a quiet state, program PLL, enable PHY, check ready bit */ +- pcie_phy_clock_mode_setup(pcie_port); ++ ret = phy_power_on(ltq_pcie_phy); ++ if (ret) { ++ phy_exit(ltq_pcie_phy); ++ continue; ++ } + + /* Enable PCIe PHY and Clock */ + pcie_core_pmu_setup(pcie_port); +@@ -1035,6 +1069,10 @@ pcie_rc_initialize(int pcie_port) + /* Once link is up, break out */ + if (pcie_app_loigc_setup(pcie_port) == 0) + break; ++ ++ phy_power_off(ltq_pcie_phy); ++ reset_control_assert(ltq_pcie_reset); ++ phy_exit(ltq_pcie_phy); + } + if (i >= IFX_PCIE_PHY_LOOP_CNT) { + printk(KERN_ERR "%s link up failed!!!!!\n", __func__); +@@ -1045,17 +1083,67 @@ pcie_rc_initialize(int pcie_port) + return 0; + } + +-static int __init ifx_pcie_bios_init(void) ++static int ifx_pcie_bios_probe(struct platform_device *pdev) + { ++ struct device_node *node = pdev->dev.of_node; + void __iomem *io_map_base; + int pcie_port; + int startup_port; ++ struct device_node *np; ++ struct pci_bus *bus; ++ ++ /* ++ * In case a PCI device is physical present, the Lantiq PCI driver need ++ * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them ++ * will work. ++ * ++ * In case the lantiq PCI driver is enabled in the device tree, check if ++ * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already ++ * registered. ++ * ++ * It will fail if there is another PCI controller, this controller is ++ * registered before the Lantiq PCIe driver is probe and the lantiq PCI ++ */ ++ np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway"); ++ ++ if (of_device_is_available(np)) { ++ bus = pci_find_next_bus(bus); ++ ++ if (!bus) ++ return -EPROBE_DEFER; ++ } + + /* Enable AHB Master/ Slave */ + pcie_ahb_pmu_setup(); + + startup_port = IFX_PCIE_PORT0; +- ++ ++ ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie"); ++ if (IS_ERR(ltq_pcie_phy)) { ++ dev_err(&pdev->dev, "failed to get the PCIe PHY\n"); ++ return PTR_ERR(ltq_pcie_phy); ++ } ++ ++ ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL); ++ if (IS_ERR(ltq_pcie_reset)) { ++ dev_err(&pdev->dev, "failed to get the PCIe reset line\n"); ++ return PTR_ERR(ltq_pcie_reset); ++ } ++ ++ ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu"); ++ if (IS_ERR(ltq_rcu_regmap)) ++ return PTR_ERR(ltq_rcu_regmap); ++ ++ pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); ++ if (gpio_is_valid(pcie_reset_gpio)) { ++ int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset"); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio); ++ return ret; ++ } ++ gpio_direction_output(pcie_reset_gpio, 1); ++ } ++ + for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ + if (pcie_rc_initialize(pcie_port) == 0) { + IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", +@@ -1067,6 +1155,7 @@ static int __init ifx_pcie_bios_init(voi + return -ENOMEM; + } + ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; ++ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node); + + register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); + /* XXX, clear error status */ +@@ -1083,6 +1172,30 @@ static int __init ifx_pcie_bios_init(voi + + return 0; + } ++ ++static const struct of_device_id ifxmips_pcie_match[] = { ++ { .compatible = "lantiq,pcie-xrx200" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ifxmips_pcie_match); ++ ++static struct platform_driver ltq_pci_driver = { ++ .probe = ifx_pcie_bios_probe, ++ .driver = { ++ .name = "pcie-xrx200", ++ .owner = THIS_MODULE, ++ .of_match_table = ifxmips_pcie_match, ++ }, ++}; ++ ++int __init ifx_pcie_bios_init(void) ++{ ++ int ret = platform_driver_register(<q_pci_driver); ++ if (ret) ++ pr_info("pcie-xrx200: Error registering platform driver!"); ++ return ret; ++} ++ + arch_initcall(ifx_pcie_bios_init); + + MODULE_LICENSE("GPL"); +--- a/arch/mips/pci/ifxmips_pcie_vr9.h ++++ b/arch/mips/pci/ifxmips_pcie_vr9.h +@@ -22,8 +22,6 @@ + #include + #include + +-#define IFX_PCIE_GPIO_RESET 494 +- + #define IFX_REG_R32 ltq_r32 + #define IFX_REG_W32 ltq_w32 + #define CONFIG_IFX_PCIE_HW_SWAP +@@ -53,21 +51,6 @@ + #define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) + + +-static inline void pcie_ep_gpio_rst_init(int pcie_port) +-{ +- +- gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); +- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); +- gpio_set_value(IFX_PCIE_GPIO_RESET, 1); +- +-/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ +-} +- + static inline void pcie_ahb_pmu_setup(void) + { + /* Enable AHB bus master/slave */ +@@ -79,24 +62,6 @@ static inline void pcie_ahb_pmu_setup(vo + //AHBS_PMU_SETUP(IFX_PMU_ENABLE); + } + +-static inline void pcie_rcu_endian_setup(int pcie_port) +-{ +- u32 reg; +- +- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); +-#ifdef CONFIG_IFX_PCIE_HW_SWAP +- reg |= IFX_RCU_AHB_BE_PCIE_M; +- reg |= IFX_RCU_AHB_BE_PCIE_S; +- reg &= ~IFX_RCU_AHB_BE_XBAR_M; +-#else +- reg |= IFX_RCU_AHB_BE_PCIE_M; +- reg &= ~IFX_RCU_AHB_BE_PCIE_S; +- reg &= ~IFX_RCU_AHB_BE_XBAR_M; +-#endif /* CONFIG_IFX_PCIE_HW_SWAP */ +- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); +- IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); +-} +- + static inline void pcie_phy_pmu_enable(int pcie_port) + { + struct clk *clk; +@@ -115,17 +80,6 @@ static inline void pcie_phy_pmu_disable( + // PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); + } + +-static inline void pcie_pdi_big_endian(int pcie_port) +-{ +- u32 reg; +- +- /* SRAM2PDI endianness control. */ +- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); +- /* Config AHB->PCIe and PDI endianness */ +- reg |= IFX_RCU_AHB_BE_PCIE_PDI; +- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); +-} +- + static inline void pcie_pdi_pmu_enable(int pcie_port) + { + /* Enable PDI to access PCIe PHY register */ +@@ -135,65 +89,6 @@ static inline void pcie_pdi_pmu_enable(i + //PDI_PMU_SETUP(IFX_PMU_ENABLE); + } + +-static inline void pcie_core_rst_assert(int pcie_port) +-{ +- u32 reg; +- +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- +- /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ +- reg |= 0x00400000; +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_core_rst_deassert(int pcie_port) +-{ +- u32 reg; +- +- /* Make sure one micro-second delay */ +- udelay(1); +- +- /* Reset PCIe PHY & Core, bit 22 */ +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- reg &= ~0x00400000; +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_phy_rst_assert(int pcie_port) +-{ +- u32 reg; +- +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- reg |= 0x00001000; /* Bit 12 */ +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_phy_rst_deassert(int pcie_port) +-{ +- u32 reg; +- +- /* Make sure one micro-second delay */ +- udelay(1); +- +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- reg &= ~0x00001000; /* Bit 12 */ +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_device_rst_assert(int pcie_port) +-{ +- gpio_set_value(IFX_PCIE_GPIO_RESET, 0); +-// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +-} +- +-static inline void pcie_device_rst_deassert(int pcie_port) +-{ +- mdelay(100); +- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); +-// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); +- //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +-} +- + static inline void pcie_core_pmu_setup(int pcie_port) + { + struct clk *clk; +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -43,7 +43,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o + obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o + obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o +-obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o ++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie.o fixup-lantiq-pcie.o + obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o + obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o + obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o diff --git a/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch new file mode 100644 index 0000000000..34fe761d1e --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch @@ -0,0 +1,180 @@ +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -2429,6 +2429,12 @@ config MIPS_VPE_LOADER + Includes a loader for loading an elf relocatable object + onto another VPE and running it. + ++config IFX_VPE_EXT ++ bool "IFX APRP Extensions" ++ depends on MIPS_VPE_LOADER ++ help ++ IFX included extensions in APRP ++ + config MIPS_VPE_LOADER_CMP + bool + default "y" +--- a/arch/mips/include/asm/vpe.h ++++ b/arch/mips/include/asm/vpe.h +@@ -124,4 +124,13 @@ void cleanup_tc(struct tc *tc); + + int __init vpe_module_init(void); + void __exit vpe_module_exit(void); ++ ++/* For the explanation of the APIs please refer the section "MT APRP Kernel ++ * Programming" in AR9 SW Architecture Specification ++ */ ++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags); ++int32_t vpe1_sw_stop(uint32_t flags); ++uint32_t vpe1_get_load_addr(uint32_t flags); ++uint32_t vpe1_get_max_mem(uint32_t flags); ++ + #endif /* _ASM_VPE_H */ +--- a/arch/mips/kernel/vpe-mt.c ++++ b/arch/mips/kernel/vpe-mt.c +@@ -29,6 +29,7 @@ int vpe_run(struct vpe *v) + struct vpe_notifications *notifier; + unsigned int vpeflags; + struct tc *t; ++ unsigned long physical_memsize = 0L; + + /* check we are the Master VPE */ + local_irq_save(flags); +@@ -417,6 +418,8 @@ int __init vpe_module_init(void) + } + + v->ntcs = hw_tcs - aprp_cpu_index(); ++ write_tc_c0_tcbind((read_tc_c0_tcbind() & ++ ~TCBIND_CURVPE) | 1); + + /* add the tc to the list of this vpe's tc's. */ + list_add(&t->tc, &v->tc); +@@ -519,3 +522,47 @@ void __exit vpe_module_exit(void) + release_vpe(v); + } + } ++ ++#ifdef CONFIG_IFX_VPE_EXT ++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags) ++{ ++ enum vpe_state state; ++ struct vpe *v = get_vpe(tclimit); ++ struct vpe_notifications *not; ++ ++ if (tcmask || flags) { ++ pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n"); ++ return -1; ++ } ++ ++ state = xchg(&v->state, VPE_STATE_INUSE); ++ if (state != VPE_STATE_UNUSED) { ++ vpe_stop(v); ++ ++ list_for_each_entry(not, &v->notify, list) { ++ not->stop(tclimit); ++ } ++ } ++ ++ v->__start = (unsigned long)sw_start_addr; ++ ++ if (!vpe_run(v)) { ++ pr_debug("VPE loader: VPE1 running successfully\n"); ++ return 0; ++ } ++ return -1; ++} ++EXPORT_SYMBOL(vpe1_sw_start); ++ ++int32_t vpe1_sw_stop(uint32_t flags) ++{ ++ struct vpe *v = get_vpe(tclimit); ++ ++ if (!vpe_free(v)) { ++ pr_debug("RP Stopped\n"); ++ return 0; ++ } else ++ return -1; ++} ++EXPORT_SYMBOL(vpe1_sw_stop); ++#endif +--- a/arch/mips/kernel/vpe.c ++++ b/arch/mips/kernel/vpe.c +@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = { + .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) + }; + ++#ifdef CONFIG_IFX_VPE_EXT ++unsigned int vpe1_load_addr; ++ ++static int __init load_address(char *str) ++{ ++ get_option(&str, &vpe1_load_addr); ++ return 1; ++} ++__setup("vpe1_load_addr=", load_address); ++ ++static unsigned int vpe1_mem; ++static int __init vpe1mem(char *str) ++{ ++ vpe1_mem = memparse(str, &str); ++ return 1; ++} ++__setup("vpe1_mem=", vpe1mem); ++ ++uint32_t vpe1_get_load_addr(uint32_t flags) ++{ ++ return vpe1_load_addr; ++} ++EXPORT_SYMBOL(vpe1_get_load_addr); ++ ++uint32_t vpe1_get_max_mem(uint32_t flags) ++{ ++ if (!vpe1_mem) ++ return P_SIZE; ++ else ++ return vpe1_mem; ++} ++EXPORT_SYMBOL(vpe1_get_max_mem); ++ ++#endif ++ + /* get the vpe associated with this minor */ + struct vpe *get_vpe(int minor) + { +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -34,10 +34,14 @@ unsigned long physical_memsize = 0L; + */ + static struct ltq_soc_info soc_info; + ++/* for Multithreading (APRP), vpe.c will use it */ ++unsigned long cp0_memsize; ++ + const char *get_system_type(void) + { + return soc_info.sys_type; + } ++EXPORT_SYMBOL(ltq_soc_type); + + int ltq_soc_type(void) + { +--- a/arch/mips/include/asm/mipsmtregs.h ++++ b/arch/mips/include/asm/mipsmtregs.h +@@ -32,6 +32,9 @@ + #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) + #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) + ++#define read_c0_vpeopt() __read_32bit_c0_register($1, 7) ++#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val) ++ + #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) + #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) + +@@ -378,6 +381,8 @@ do { \ + #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) + #define read_vpe_c0_vpeconf1() mftc0(1, 3) + #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) ++#define read_vpe_c0_vpeopt() mftc0(1, 7) ++#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val) + #define read_vpe_c0_count() mftc0(9, 0) + #define write_vpe_c0_count(val) mttc0(9, 0, val) + #define read_vpe_c0_status() mftc0(12, 0) diff --git a/target/linux/lantiq/patches-5.15/0154-lantiq-pci-bar11mask-fix.patch b/target/linux/lantiq/patches-5.15/0154-lantiq-pci-bar11mask-fix.patch new file mode 100644 index 0000000000..d6556d115d --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0154-lantiq-pci-bar11mask-fix.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/pci/pci-lantiq.c ++++ b/arch/mips/pci/pci-lantiq.c +@@ -59,6 +59,8 @@ + #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) + #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) + ++extern u32 max_low_pfn; ++ + __iomem void *ltq_pci_mapped_cfg; + static __iomem void *ltq_pci_membase; + +@@ -84,8 +86,8 @@ static inline u32 ltq_calc_bar11mask(voi + u32 mem, bar11mask; + + /* BAR11MASK value depends on available memory on system. */ +- mem = get_num_physpages() * PAGE_SIZE; +- bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; ++ mem = max_low_pfn << PAGE_SHIFT; ++ bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8; + + return bar11mask; + } diff --git a/target/linux/lantiq/patches-5.15/0155-lantiq-VPE-nosmp.patch b/target/linux/lantiq/patches-5.15/0155-lantiq-VPE-nosmp.patch new file mode 100644 index 0000000000..898c2d4821 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0155-lantiq-VPE-nosmp.patch @@ -0,0 +1,14 @@ +--- a/arch/mips/kernel/vpe-mt.c ++++ b/arch/mips/kernel/vpe-mt.c +@@ -132,7 +132,10 @@ int vpe_run(struct vpe *v) + * kernels need to turn it on, even if that wasn't the pre-dvpe() state. + */ + #ifdef CONFIG_SMP +- evpe(vpeflags); ++ if (!setup_max_cpus) /* nosmp is set */ ++ evpe(EVPE_ENABLE); ++ else ++ evpe(vpeflags); + #else + evpe(EVPE_ENABLE); + #endif diff --git a/target/linux/lantiq/patches-5.15/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-5.15/0160-owrt-lantiq-multiple-flash.patch new file mode 100644 index 0000000000..796220b2bc --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0160-owrt-lantiq-multiple-flash.patch @@ -0,0 +1,220 @@ +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -36,13 +37,16 @@ enum { + LTQ_NOR_NORMAL + }; + ++#define MAX_RESOURCES 4 ++ + struct ltq_mtd { +- struct resource *res; +- struct mtd_info *mtd; +- struct map_info *map; ++ struct mtd_info *mtd[MAX_RESOURCES]; ++ struct mtd_info *cmtd; ++ struct map_info map[MAX_RESOURCES]; + }; + + static const char ltq_map_name[] = "ltq_nor"; ++static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL }; + + static map_word + ltq_read16(struct map_info *map, unsigned long adr) +@@ -106,11 +110,43 @@ ltq_copy_to(struct map_info *map, unsign + } + + static int ++ltq_mtd_remove(struct platform_device *pdev) ++{ ++ struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); ++ int i; ++ ++ if (ltq_mtd == NULL) ++ return 0; ++ ++ if (ltq_mtd->cmtd) { ++ mtd_device_unregister(ltq_mtd->cmtd); ++ if (ltq_mtd->cmtd != ltq_mtd->mtd[0]) ++ mtd_concat_destroy(ltq_mtd->cmtd); ++ } ++ ++ for (i = 0; i < MAX_RESOURCES; i++) { ++ if (ltq_mtd->mtd[i] != NULL) ++ map_destroy(ltq_mtd->mtd[i]); ++ } ++ ++ kfree(ltq_mtd); ++ ++ return 0; ++} ++ ++static int + ltq_mtd_probe(struct platform_device *pdev) + { + struct ltq_mtd *ltq_mtd; + struct cfi_private *cfi; +- int err; ++ int err = 0; ++ int i; ++ int devices_found = 0; ++ ++ static const char *rom_probe_types[] = { ++ "cfi_probe", "jedec_probe", NULL ++ }; ++ const char **type; + + ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL); + if (!ltq_mtd) +@@ -118,75 +154,89 @@ ltq_mtd_probe(struct platform_device *pd + + platform_set_drvdata(pdev, ltq_mtd); + +- ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!ltq_mtd->res) { +- dev_err(&pdev->dev, "failed to get memory resource\n"); +- return -ENOENT; ++ for (i = 0; i < pdev->num_resources; i++) { ++ printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n", ++ (unsigned long long)resource_size(&pdev->resource[i]), ++ (unsigned long long)pdev->resource[i].start); ++ ++ if (!devm_request_mem_region(&pdev->dev, ++ pdev->resource[i].start, ++ resource_size(&pdev->resource[i]), ++ dev_name(&pdev->dev))) { ++ dev_err(&pdev->dev, "Could not reserve memory region\n"); ++ return -ENOMEM; ++ } ++ ++ ltq_mtd->map[i].name = ltq_map_name; ++ ltq_mtd->map[i].bankwidth = 2; ++ ltq_mtd->map[i].read = ltq_read16; ++ ltq_mtd->map[i].write = ltq_write16; ++ ltq_mtd->map[i].copy_from = ltq_copy_from; ++ ltq_mtd->map[i].copy_to = ltq_copy_to; ++ ++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) ++ ltq_mtd->map[i].phys = NO_XIP; ++ else ++ ltq_mtd->map[i].phys = pdev->resource[i].start; ++ ltq_mtd->map[i].size = resource_size(&pdev->resource[i]); ++ ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start, ++ ltq_mtd->map[i].size); ++ if (IS_ERR(ltq_mtd->map[i].virt)) ++ return PTR_ERR(ltq_mtd->map[i].virt); ++ ++ if (ltq_mtd->map[i].virt == NULL) { ++ dev_err(&pdev->dev, "Failed to ioremap flash region\n"); ++ err = PTR_ERR(ltq_mtd->map[i].virt); ++ goto err_out; ++ } ++ ++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING; ++ for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++) ++ ltq_mtd->mtd[i] = do_map_probe(*type, <q_mtd->map[i]); ++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL; ++ ++ if (!ltq_mtd->mtd[i]) { ++ dev_err(&pdev->dev, "probing failed\n"); ++ return -ENXIO; ++ } else { ++ devices_found++; ++ } ++ ++ ltq_mtd->mtd[i]->owner = THIS_MODULE; ++ ltq_mtd->mtd[i]->dev.parent = &pdev->dev; ++ ++ cfi = ltq_mtd->map[i].fldrv_priv; ++ cfi->addr_unlock1 ^= 1; ++ cfi->addr_unlock2 ^= 1; + } + +- ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info), +- GFP_KERNEL); +- if (!ltq_mtd->map) +- return -ENOMEM; +- +- if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) +- ltq_mtd->map->phys = NO_XIP; +- else +- ltq_mtd->map->phys = ltq_mtd->res->start; +- ltq_mtd->res->start; +- ltq_mtd->map->size = resource_size(ltq_mtd->res); +- ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); +- if (IS_ERR(ltq_mtd->map->virt)) +- return PTR_ERR(ltq_mtd->map->virt); +- +- ltq_mtd->map->name = ltq_map_name; +- ltq_mtd->map->bankwidth = 2; +- ltq_mtd->map->read = ltq_read16; +- ltq_mtd->map->write = ltq_write16; +- ltq_mtd->map->copy_from = ltq_copy_from; +- ltq_mtd->map->copy_to = ltq_copy_to; +- +- ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING; +- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map); +- ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL; +- +- if (!ltq_mtd->mtd) { +- dev_err(&pdev->dev, "probing failed\n"); +- return -ENXIO; ++ if (devices_found == 1) { ++ ltq_mtd->cmtd = ltq_mtd->mtd[0]; ++ } else if (devices_found > 1) { ++ /* ++ * We detected multiple devices. Concatenate them together. ++ */ ++ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev)); ++ if (ltq_mtd->cmtd == NULL) ++ err = -ENXIO; + } + +- ltq_mtd->mtd->dev.parent = &pdev->dev; +- mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node); +- +- cfi = ltq_mtd->map->fldrv_priv; +- cfi->addr_unlock1 ^= 1; +- cfi->addr_unlock2 ^= 1; ++ ltq_mtd->cmtd->dev.parent = &pdev->dev; ++ mtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node); + +- err = mtd_device_register(ltq_mtd->mtd, NULL, 0); ++ err = mtd_device_register(ltq_mtd->cmtd, NULL, 0); + if (err) { + dev_err(&pdev->dev, "failed to add partitions\n"); +- goto err_destroy; ++ goto err_out; + } + + return 0; + +-err_destroy: +- map_destroy(ltq_mtd->mtd); ++err_out: ++ ltq_mtd_remove(pdev); + return err; + } + +-static int +-ltq_mtd_remove(struct platform_device *pdev) +-{ +- struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); +- +- if (ltq_mtd && ltq_mtd->mtd) { +- mtd_device_unregister(ltq_mtd->mtd); +- map_destroy(ltq_mtd->mtd); +- } +- return 0; +-} +- + static const struct of_device_id ltq_mtd_match[] = { + { .compatible = "lantiq,nor" }, + {}, diff --git a/target/linux/lantiq/patches-5.15/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-5.15/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch new file mode 100644 index 0000000000..d153c521d3 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0001.c ++++ b/drivers/mtd/chips/cfi_cmdset_0001.c +@@ -39,7 +39,7 @@ + /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ + + // debugging, turns off buffer write mode if set to 1 +-#define FORCE_WORD_WRITE 0 ++#define FORCE_WORD_WRITE 1 + + /* Intel chips */ + #define I82802AB 0x00ad diff --git a/target/linux/lantiq/patches-5.15/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-5.15/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch new file mode 100644 index 0000000000..92c4b56493 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch @@ -0,0 +1,30 @@ +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -440,6 +440,20 @@ static void clkdev_add_clkout(void) + } + } + ++static void set_phy_clock_source(struct device_node *np_cgu) ++{ ++ u32 phy_clk_src, ifcc; ++ ++ if (!np_cgu) ++ return; ++ ++ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) ++ return; ++ ++ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); ++ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); ++} ++ + /* bring up all register ranges that we need for basic system control */ + void __init ltq_soc_init(void) + { +@@ -605,4 +619,6 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); + } + usb_set_clock(); ++ ++ set_phy_clock_source(np_cgu); + } diff --git a/target/linux/lantiq/patches-5.15/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch b/target/linux/lantiq/patches-5.15/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch new file mode 100644 index 0000000000..4f3210a6c3 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch @@ -0,0 +1,86 @@ +From 49293bbc50cb7d44223eb49e0f7cb38e7dac2361 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 14 Sep 2021 23:21:01 +0200 +Subject: [PATCH 4/5] MIPS: lantiq: dma: make the burst length configurable by + the drivers + +Make the burst length configurable by the drivers. + +Signed-off-by: Aleksander Jan Bajkowski +Acked-by: Hauke Mehrtens +Signed-off-by: David S. Miller +--- + .../include/asm/mach-lantiq/xway/xway_dma.h | 2 +- + arch/mips/lantiq/xway/dma.c | 38 ++++++++++++++++--- + 2 files changed, 34 insertions(+), 6 deletions(-) + +--- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h +@@ -45,6 +45,6 @@ extern void ltq_dma_close(struct ltq_dma + extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch); + extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch); + extern void ltq_dma_free(struct ltq_dma_channel *ch); +-extern void ltq_dma_init_port(int p); ++extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst); + + #endif +--- a/arch/mips/lantiq/xway/dma.c ++++ b/arch/mips/lantiq/xway/dma.c +@@ -182,7 +182,7 @@ ltq_dma_free(struct ltq_dma_channel *ch) + EXPORT_SYMBOL_GPL(ltq_dma_free); + + void +-ltq_dma_init_port(int p) ++ltq_dma_init_port(int p, int tx_burst, int rx_burst) + { + ltq_dma_w32(p, LTQ_DMA_PS); + switch (p) { +@@ -191,16 +191,44 @@ ltq_dma_init_port(int p) + * Tell the DMA engine to swap the endianness of data frames and + * drop packets if the channel arbitration fails. + */ +- ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN, ++ ltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN), + LTQ_DMA_PCTRL); + break; + +- case DMA_PORT_DEU: +- ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) | +- (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT), ++ default: ++ break; ++ } ++ ++ switch (rx_burst) { ++ case 8: ++ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT), + LTQ_DMA_PCTRL); + break; ++ case 4: ++ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT), ++ LTQ_DMA_PCTRL); ++ break; ++ case 2: ++ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT), ++ LTQ_DMA_PCTRL); ++ break; ++ default: ++ break; ++ } + ++ switch (tx_burst) { ++ case 8: ++ ltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT), ++ LTQ_DMA_PCTRL); ++ break; ++ case 4: ++ ltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT), ++ LTQ_DMA_PCTRL); ++ break; ++ case 2: ++ ltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT), ++ LTQ_DMA_PCTRL); ++ break; + default: + break; + } diff --git a/target/linux/lantiq/patches-5.15/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch b/target/linux/lantiq/patches-5.15/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch new file mode 100644 index 0000000000..d83a3616b3 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch @@ -0,0 +1,87 @@ +From 730320fd770d4114a2ecb6fb223dcc8c3cecdc5b Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Wed, 21 Sep 2022 22:59:44 +0200 +Subject: [PATCH] MIPS: lantiq: enable all hardware interrupts on second VPE + +This patch is needed to handle interrupts by the second VPE on the Lantiq +ARX100, xRX200, xRX300 and xRX330 SoCs. Switching some ICU interrupts to +the second VPE results in a hang. Currently, the vsmp_init_secondary() +function is responsible for enabling these interrupts. It only enables +Malta-specific interrupts (SW0, SW1, HW4 and HW5). + +The MIPS core has 8 interrupts defined. On Lantiq SoCs, hardware +interrupts are wired to an ICU instance. Each VPE has an independent +instance of the ICU. The mapping of the ICU interrupts is shown below: +SW0(IP0) - IPI call, +SW1(IP1) - IPI resched, +HW0(IP2) - ICU 0-31, +HW1(IP3) - ICU 32-63, +HW2(IP4) - ICU 64-95, +HW3(IP5) - ICU 96-127, +HW4(IP6) - ICU 128-159, +HW5(IP7) - timer. + +This patch enables all interrupt lines on the second VPE. + +This problem affects multithreaded SoCs with a custom interrupt controller. +SOCs with 1004Kc core and newer use the MIPS GIC. At this point, I am aware +that the Realtek RTL839x and RTL930x SoCs may need a similar fix. In the +future, this may be replaced with some generic solution. + +Tested on Lantiq xRX200. + +Suggested-by: Thomas Bogendoerfer +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/lantiq/prom.c | 26 ++++++++++++++++++++++++-- + 1 file changed, 24 insertions(+), 2 deletions(-) + +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -37,6 +37,14 @@ static struct ltq_soc_info soc_info; + /* for Multithreading (APRP), vpe.c will use it */ + unsigned long cp0_memsize; + ++/* ++ * These structs are used to override vsmp_init_secondary() ++ */ ++#if defined(CONFIG_MIPS_MT_SMP) ++extern const struct plat_smp_ops vsmp_smp_ops; ++static struct plat_smp_ops lantiq_smp_ops; ++#endif ++ + const char *get_system_type(void) + { + return soc_info.sys_type; +@@ -93,6 +101,17 @@ void __init device_tree_init(void) + unflatten_and_copy_device_tree(); + } + ++#if defined(CONFIG_MIPS_MT_SMP) ++static void lantiq_init_secondary(void) ++{ ++ /* ++ * MIPS CPU startup function vsmp_init_secondary() will only ++ * enable some of the interrupts for the second CPU/VPE. ++ */ ++ set_c0_status(ST0_IM); ++} ++#endif ++ + void __init prom_init(void) + { + /* call the soc specific detetcion code and get it to fill soc_info */ +@@ -104,7 +123,10 @@ void __init prom_init(void) + prom_init_cmdline(); + + #if defined(CONFIG_MIPS_MT_SMP) +- if (register_vsmp_smp_ops()) +- panic("failed to register_vsmp_smp_ops()"); ++ if (cpu_has_mipsmt) { ++ lantiq_smp_ops = vsmp_smp_ops; ++ lantiq_smp_ops.init_secondary = lantiq_init_secondary; ++ register_smp_ops(&lantiq_smp_ops); ++ } + #endif + } diff --git a/target/linux/lantiq/patches-5.15/0701-NET-lantiq-etop-of-mido.patch b/target/linux/lantiq/patches-5.15/0701-NET-lantiq-etop-of-mido.patch new file mode 100644 index 0000000000..2cc541ae3c --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0701-NET-lantiq-etop-of-mido.patch @@ -0,0 +1,37 @@ +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -30,6 +30,7 @@ + #include + #include + #include ++#include + + #include + +@@ -553,7 +554,8 @@ static int + ltq_etop_mdio_init(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int err; ++ struct device_node *mdio_np = NULL; ++ int err, ret; + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { +@@ -573,7 +575,15 @@ ltq_etop_mdio_init(struct net_device *de + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + priv->pdev->name, priv->pdev->id); +- if (mdiobus_register(priv->mii_bus)) { ++ ++ mdio_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus"); ++ ++ if (mdio_np) ++ ret = of_mdiobus_register(priv->mii_bus, mdio_np); ++ else ++ ret = mdiobus_register(priv->mii_bus); ++ ++ if (ret) { + err = -ENXIO; + goto err_out_free_mdiobus; + } diff --git a/target/linux/lantiq/patches-5.15/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch b/target/linux/lantiq/patches-5.15/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch new file mode 100644 index 0000000000..4a4109c772 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch @@ -0,0 +1,145 @@ +From 998ac358019e491217e752bc6dcbb3afb2a6fa3e Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Sun, 19 Sep 2021 20:24:28 +0200 +Subject: [PATCH] net: lantiq: add support for jumbo frames + +Add support for jumbo frames. Full support for jumbo frames requires +changes in the DSA switch driver (lantiq_gswip.c). + +Tested on BT Hone Hub 5A. + +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/lantiq_xrx200.c | 64 +++++++++++++++++++++++++--- + 1 file changed, 57 insertions(+), 7 deletions(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -14,13 +14,15 @@ + #include + #include + ++#include ++ + #include + #include + + #include + + /* DMA */ +-#define XRX200_DMA_DATA_LEN 0x600 ++#define XRX200_DMA_DATA_LEN (SZ_64K - 1) + #define XRX200_DMA_RX 0 + #define XRX200_DMA_TX 1 + +@@ -106,7 +108,8 @@ static void xrx200_flush_dma(struct xrx2 + break; + + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | +- XRX200_DMA_DATA_LEN; ++ (ch->priv->net_dev->mtu + VLAN_ETH_HLEN + ++ ETH_FCS_LEN); + ch->dma.desc++; + ch->dma.desc %= LTQ_DESC_NUM; + } +@@ -154,19 +157,20 @@ static int xrx200_close(struct net_devic + + static int xrx200_alloc_skb(struct xrx200_chan *ch) + { ++ int len = ch->priv->net_dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; + struct sk_buff *skb = ch->skb[ch->dma.desc]; + dma_addr_t mapping; + int ret = 0; + + ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev, +- XRX200_DMA_DATA_LEN); ++ len); + if (!ch->skb[ch->dma.desc]) { + ret = -ENOMEM; + goto skip; + } + + mapping = dma_map_single(ch->priv->dev, ch->skb[ch->dma.desc]->data, +- XRX200_DMA_DATA_LEN, DMA_FROM_DEVICE); ++ len, DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(ch->priv->dev, mapping))) { + dev_kfree_skb_any(ch->skb[ch->dma.desc]); + ch->skb[ch->dma.desc] = skb; +@@ -179,8 +183,7 @@ static int xrx200_alloc_skb(struct xrx20 + wmb(); + skip: + ch->dma.desc_base[ch->dma.desc].ctl = +- LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | +- XRX200_DMA_DATA_LEN; ++ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | len; + + return ret; + } +@@ -340,10 +343,57 @@ err_drop: + return NETDEV_TX_OK; + } + ++static int ++xrx200_change_mtu(struct net_device *net_dev, int new_mtu) ++{ ++ struct xrx200_priv *priv = netdev_priv(net_dev); ++ struct xrx200_chan *ch_rx = &priv->chan_rx; ++ int old_mtu = net_dev->mtu; ++ bool running = false; ++ struct sk_buff *skb; ++ int curr_desc; ++ int ret = 0; ++ ++ net_dev->mtu = new_mtu; ++ ++ if (new_mtu <= old_mtu) ++ return ret; ++ ++ running = netif_running(net_dev); ++ if (running) { ++ napi_disable(&ch_rx->napi); ++ ltq_dma_close(&ch_rx->dma); ++ } ++ ++ xrx200_poll_rx(&ch_rx->napi, LTQ_DESC_NUM); ++ curr_desc = ch_rx->dma.desc; ++ ++ for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; ++ ch_rx->dma.desc++) { ++ skb = ch_rx->skb[ch_rx->dma.desc]; ++ ret = xrx200_alloc_skb(ch_rx); ++ if (ret) { ++ net_dev->mtu = old_mtu; ++ break; ++ } ++ dev_kfree_skb_any(skb); ++ } ++ ++ ch_rx->dma.desc = curr_desc; ++ if (running) { ++ napi_enable(&ch_rx->napi); ++ ltq_dma_open(&ch_rx->dma); ++ ltq_dma_enable_irq(&ch_rx->dma); ++ } ++ ++ return ret; ++} ++ + static const struct net_device_ops xrx200_netdev_ops = { + .ndo_open = xrx200_open, + .ndo_stop = xrx200_close, + .ndo_start_xmit = xrx200_start_xmit, ++ .ndo_change_mtu = xrx200_change_mtu, + .ndo_set_mac_address = eth_mac_addr, + .ndo_validate_addr = eth_validate_addr, + }; +@@ -453,7 +503,7 @@ static int xrx200_probe(struct platform_ + net_dev->netdev_ops = &xrx200_netdev_ops; + SET_NETDEV_DEV(net_dev, dev); + net_dev->min_mtu = ETH_ZLEN; +- net_dev->max_mtu = XRX200_DMA_DATA_LEN; ++ net_dev->max_mtu = XRX200_DMA_DATA_LEN - VLAN_ETH_HLEN - ETH_FCS_LEN; + + /* load the memory ranges */ + priv->pmac_reg = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); diff --git a/target/linux/lantiq/patches-5.15/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch b/target/linux/lantiq/patches-5.15/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch new file mode 100644 index 0000000000..c197b1a1c9 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch @@ -0,0 +1,122 @@ +From 1488fc204568f707fe2a42a913788c00a95af30e Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Fri, 17 Dec 2021 01:07:40 +0100 +Subject: [PATCH] net: lantiq_xrx200: increase buffer reservation + +If the user sets a lower mtu on the CPU port than on the switch, +then DMA inserts a few more bytes into the buffer than expected. +In the worst case, it may exceed the size of the buffer. The +experiments showed that the buffer should be a multiple of the +burst length value. This patch rounds the length of the rx buffer +upwards and fixes this bug. The reservation of FCS space in the +buffer has been removed as PMAC strips the FCS. + +Fixes: 998ac358019e ("net: lantiq: add support for jumbo frames") +Reported-by: Thomas Nixon +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/lantiq_xrx200.c | 34 ++++++++++++++++++++-------- + 1 file changed, 24 insertions(+), 10 deletions(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -70,6 +70,8 @@ struct xrx200_priv { + struct xrx200_chan chan_tx; + struct xrx200_chan chan_rx; + ++ u16 rx_buf_size; ++ + struct net_device *net_dev; + struct device *dev; + +@@ -96,6 +98,16 @@ static void xrx200_pmac_mask(struct xrx2 + xrx200_pmac_w32(priv, val, offset); + } + ++static int xrx200_max_frame_len(int mtu) ++{ ++ return VLAN_ETH_HLEN + mtu; ++} ++ ++static int xrx200_buffer_size(int mtu) ++{ ++ return round_up(xrx200_max_frame_len(mtu), 4 * XRX200_DMA_BURST_LEN); ++} ++ + /* drop all the packets from the DMA ring */ + static void xrx200_flush_dma(struct xrx200_chan *ch) + { +@@ -108,8 +120,7 @@ static void xrx200_flush_dma(struct xrx2 + break; + + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | +- (ch->priv->net_dev->mtu + VLAN_ETH_HLEN + +- ETH_FCS_LEN); ++ ch->priv->rx_buf_size; + ch->dma.desc++; + ch->dma.desc %= LTQ_DESC_NUM; + } +@@ -157,21 +168,21 @@ static int xrx200_close(struct net_devic + + static int xrx200_alloc_skb(struct xrx200_chan *ch) + { +- int len = ch->priv->net_dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; + struct sk_buff *skb = ch->skb[ch->dma.desc]; ++ struct xrx200_priv *priv = ch->priv; + dma_addr_t mapping; + int ret = 0; + +- ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev, +- len); ++ ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(priv->net_dev, ++ priv->rx_buf_size); + if (!ch->skb[ch->dma.desc]) { + ret = -ENOMEM; + goto skip; + } + +- mapping = dma_map_single(ch->priv->dev, ch->skb[ch->dma.desc]->data, +- len, DMA_FROM_DEVICE); +- if (unlikely(dma_mapping_error(ch->priv->dev, mapping))) { ++ mapping = dma_map_single(priv->dev, ch->skb[ch->dma.desc]->data, ++ priv->rx_buf_size, DMA_FROM_DEVICE); ++ if (unlikely(dma_mapping_error(priv->dev, mapping))) { + dev_kfree_skb_any(ch->skb[ch->dma.desc]); + ch->skb[ch->dma.desc] = skb; + ret = -ENOMEM; +@@ -183,7 +194,7 @@ static int xrx200_alloc_skb(struct xrx20 + wmb(); + skip: + ch->dma.desc_base[ch->dma.desc].ctl = +- LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | len; ++ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | priv->rx_buf_size; + + return ret; + } +@@ -355,6 +366,7 @@ xrx200_change_mtu(struct net_device *net + int ret = 0; + + net_dev->mtu = new_mtu; ++ priv->rx_buf_size = xrx200_buffer_size(new_mtu); + + if (new_mtu <= old_mtu) + return ret; +@@ -374,6 +386,7 @@ xrx200_change_mtu(struct net_device *net + ret = xrx200_alloc_skb(ch_rx); + if (ret) { + net_dev->mtu = old_mtu; ++ priv->rx_buf_size = xrx200_buffer_size(old_mtu); + break; + } + dev_kfree_skb_any(skb); +@@ -503,7 +516,8 @@ static int xrx200_probe(struct platform_ + net_dev->netdev_ops = &xrx200_netdev_ops; + SET_NETDEV_DEV(net_dev, dev); + net_dev->min_mtu = ETH_ZLEN; +- net_dev->max_mtu = XRX200_DMA_DATA_LEN - VLAN_ETH_HLEN - ETH_FCS_LEN; ++ net_dev->max_mtu = XRX200_DMA_DATA_LEN - xrx200_max_frame_len(0); ++ priv->rx_buf_size = xrx200_buffer_size(ETH_DATA_LEN); + + /* load the memory ranges */ + priv->pmac_reg = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); diff --git a/target/linux/lantiq/patches-5.15/0704-v5.17-net-lantiq_xrx200-add-ingress-SG-DMA-support.patch b/target/linux/lantiq/patches-5.15/0704-v5.17-net-lantiq_xrx200-add-ingress-SG-DMA-support.patch new file mode 100644 index 0000000000..f2c36952fc --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0704-v5.17-net-lantiq_xrx200-add-ingress-SG-DMA-support.patch @@ -0,0 +1,104 @@ +From c3e6b2c35b34214c58c1e90d65dab5f5393608e7 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Mon, 3 Jan 2022 20:43:16 +0100 +Subject: [PATCH] net: lantiq_xrx200: add ingress SG DMA support + +This patch adds support for scatter gather DMA. DMA in PMAC splits +the packet into several buffers when the MTU on the CPU port is +less than the MTU of the switch. The first buffer starts at an +offset of NET_IP_ALIGN. In subsequent buffers, dma ignores the +offset. Thanks to this patch, the user can still connect to the +device in such a situation. For normal configurations, the patch +has no effect on performance. + +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/lantiq_xrx200.c | 47 +++++++++++++++++++++++----- + 1 file changed, 40 insertions(+), 7 deletions(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -26,6 +26,9 @@ + #define XRX200_DMA_RX 0 + #define XRX200_DMA_TX 1 + ++#define XRX200_DMA_PACKET_COMPLETE 0 ++#define XRX200_DMA_PACKET_IN_PROGRESS 1 ++ + /* cpu port mac */ + #define PMAC_RX_IPG 0x0024 + #define PMAC_RX_IPG_MASK 0xf +@@ -61,6 +64,9 @@ struct xrx200_chan { + struct ltq_dma_channel dma; + struct sk_buff *skb[LTQ_DESC_NUM]; + ++ struct sk_buff *skb_head; ++ struct sk_buff *skb_tail; ++ + struct xrx200_priv *priv; + }; + +@@ -204,7 +210,8 @@ static int xrx200_hw_receive(struct xrx2 + struct xrx200_priv *priv = ch->priv; + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; + struct sk_buff *skb = ch->skb[ch->dma.desc]; +- int len = (desc->ctl & LTQ_DMA_SIZE_MASK); ++ u32 ctl = desc->ctl; ++ int len = (ctl & LTQ_DMA_SIZE_MASK); + struct net_device *net_dev = priv->net_dev; + int ret; + +@@ -220,12 +227,36 @@ static int xrx200_hw_receive(struct xrx2 + } + + skb_put(skb, len); +- skb->protocol = eth_type_trans(skb, net_dev); +- netif_receive_skb(skb); +- net_dev->stats.rx_packets++; +- net_dev->stats.rx_bytes += len; + +- return 0; ++ /* add buffers to skb via skb->frag_list */ ++ if (ctl & LTQ_DMA_SOP) { ++ ch->skb_head = skb; ++ ch->skb_tail = skb; ++ } else if (ch->skb_head) { ++ if (ch->skb_head == ch->skb_tail) ++ skb_shinfo(ch->skb_tail)->frag_list = skb; ++ else ++ ch->skb_tail->next = skb; ++ ch->skb_tail = skb; ++ skb_reserve(ch->skb_tail, -NET_IP_ALIGN); ++ ch->skb_head->len += skb->len; ++ ch->skb_head->data_len += skb->len; ++ ch->skb_head->truesize += skb->truesize; ++ } ++ ++ if (ctl & LTQ_DMA_EOP) { ++ ch->skb_head->protocol = eth_type_trans(ch->skb_head, net_dev); ++ netif_receive_skb(ch->skb_head); ++ net_dev->stats.rx_packets++; ++ net_dev->stats.rx_bytes += ch->skb_head->len; ++ ch->skb_head = NULL; ++ ch->skb_tail = NULL; ++ ret = XRX200_DMA_PACKET_COMPLETE; ++ } else { ++ ret = XRX200_DMA_PACKET_IN_PROGRESS; ++ } ++ ++ return ret; + } + + static int xrx200_poll_rx(struct napi_struct *napi, int budget) +@@ -240,7 +271,9 @@ static int xrx200_poll_rx(struct napi_st + + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { + ret = xrx200_hw_receive(ch); +- if (ret) ++ if (ret == XRX200_DMA_PACKET_IN_PROGRESS) ++ continue; ++ if (ret != XRX200_DMA_PACKET_COMPLETE) + return ret; + rx++; + } else { diff --git a/target/linux/lantiq/patches-5.15/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch b/target/linux/lantiq/patches-5.15/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch new file mode 100644 index 0000000000..22aa2eea6e --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch @@ -0,0 +1,127 @@ +From c40bb4fedcd6b8b6a714da5dd466eb88ed2652d1 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Wed, 9 Mar 2022 00:04:57 +0100 +Subject: net: dsa: lantiq_gswip: enable jumbo frames on GSWIP + +This enables non-standard MTUs on a per-port basis, with the overall +frame size set based on the CPU port. + +When the MTU is not changed, this should have no effect. + +Long packets crash the switch with MTUs of greater than 2526, so the +maximum is limited for now. Medium packets are sometimes dropped (e.g. +TCP over 2477, UDP over 2516-2519, ICMP over 2526), Hence an MTU value +of 2400 seems safe. + +Signed-off-by: Thomas Nixon +Signed-off-by: Aleksander Jan Bajkowski +Link: https://lore.kernel.org/r/20220308230457.1599237-1-olek2@wp.pl +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/lantiq_gswip.c | 53 ++++++++++++++++++++++++++++++++++++++---- + 1 file changed, 49 insertions(+), 4 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -213,6 +213,7 @@ + #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 + #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 + #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) ++#define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */ + #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ + + /* Ethernet Switch Fetch DMA Port Control Register */ +@@ -239,6 +240,15 @@ + + #define XRX200_GPHY_FW_ALIGN (16 * 1024) + ++/* Maximum packet size supported by the switch. In theory this should be 10240, ++ * but long packets currently cause lock-ups with an MTU of over 2526. Medium ++ * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP ++ * over 2526), hence an MTU value of 2400 seems safe. This issue only affects ++ * packet reception. This is probably caused by the PPA engine, which is on the ++ * RX part of the device. Packet transmission works properly up to 10240. ++ */ ++#define GSWIP_MAX_PACKET_LENGTH 2400 ++ + struct gswip_hw_info { + int max_ports; + int cpu_port; +@@ -846,10 +856,6 @@ static int gswip_setup(struct dsa_switch + gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, + GSWIP_PCE_PCTRL_0p(cpu_port)); + +- gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, +- GSWIP_MAC_CTRL_2p(cpu_port)); +- gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8 + ETH_FCS_LEN, +- GSWIP_MAC_FLEN); + gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, + GSWIP_BM_QUEUE_GCTRL); + +@@ -866,6 +872,8 @@ static int gswip_setup(struct dsa_switch + return err; + } + ++ ds->mtu_enforcement_ingress = true; ++ + gswip_port_enable(ds, cpu_port, NULL); + + ds->configure_vlan_while_not_filtering = false; +@@ -1456,6 +1464,39 @@ static void gswip_phylink_set_capab(unsi + linkmode_and(state->advertising, state->advertising, mask); + } + ++static int gswip_port_max_mtu(struct dsa_switch *ds, int port) ++{ ++ /* Includes 8 bytes for special header. */ ++ return GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN; ++} ++ ++static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) ++{ ++ struct gswip_priv *priv = ds->priv; ++ int cpu_port = priv->hw_info->cpu_port; ++ ++ /* CPU port always has maximum mtu of user ports, so use it to set ++ * switch frame size, including 8 byte special header. ++ */ ++ if (port == cpu_port) { ++ new_mtu += 8; ++ gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN, ++ GSWIP_MAC_FLEN); ++ } ++ ++ /* Enable MLEN for ports with non-standard MTUs, including the special ++ * header on the CPU port added above. ++ */ ++ if (new_mtu != ETH_DATA_LEN) ++ gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, ++ GSWIP_MAC_CTRL_2p(port)); ++ else ++ gswip_switch_mask(priv, GSWIP_MAC_CTRL_2_MLEN, 0, ++ GSWIP_MAC_CTRL_2p(port)); ++ ++ return 0; ++} ++ + static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port, + unsigned long *supported, + struct phylink_link_state *state) +@@ -1812,6 +1853,8 @@ static const struct dsa_switch_ops gswip + .port_fdb_add = gswip_port_fdb_add, + .port_fdb_del = gswip_port_fdb_del, + .port_fdb_dump = gswip_port_fdb_dump, ++ .port_change_mtu = gswip_port_change_mtu, ++ .port_max_mtu = gswip_port_max_mtu, + .phylink_validate = gswip_xrx200_phylink_validate, + .phylink_mac_config = gswip_phylink_mac_config, + .phylink_mac_link_down = gswip_phylink_mac_link_down, +@@ -1836,6 +1879,8 @@ static const struct dsa_switch_ops gswip + .port_fdb_add = gswip_port_fdb_add, + .port_fdb_del = gswip_port_fdb_del, + .port_fdb_dump = gswip_port_fdb_dump, ++ .port_change_mtu = gswip_port_change_mtu, ++ .port_max_mtu = gswip_port_max_mtu, + .phylink_validate = gswip_xrx300_phylink_validate, + .phylink_mac_config = gswip_phylink_mac_config, + .phylink_mac_link_down = gswip_phylink_mac_link_down, diff --git a/target/linux/lantiq/patches-5.15/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch b/target/linux/lantiq/patches-5.15/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch new file mode 100644 index 0000000000..818fa811e9 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch @@ -0,0 +1,126 @@ +From 14d4e308e0aa0b78dc7a059716861a4380de3535 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 14 Sep 2021 23:21:02 +0200 +Subject: [PATCH 5/5] net: lantiq: configure the burst length in ethernet + drivers + +Configure the burst length in Ethernet drivers. This improves +Ethernet performance by 58%. According to the vendor BSP, +8W burst length is supported by ar9 and newer SoCs. + +The NAT benchmark results on xRX200 (Down/Up): +* 2W: 330 Mb/s +* 4W: 432 Mb/s 372 Mb/s +* 8W: 520 Mb/s 389 Mb/s + +Tested on xRX200 and xRX330. + +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/lantiq_etop.c | 21 ++++++++++++++++++--- + drivers/net/ethernet/lantiq_xrx200.c | 21 ++++++++++++++++++--- + 2 files changed, 36 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -148,6 +148,9 @@ struct ltq_etop_priv { + struct ltq_etop_chan txch; + struct ltq_etop_chan rxch; + ++ int tx_burst_len; ++ int rx_burst_len; ++ + int tx_irq; + int rx_irq; + +@@ -399,7 +402,7 @@ ltq_etop_dma_init(struct net_device *dev + int rx = priv->rx_irq - LTQ_DMA_ETOP; + int err; + +- ltq_dma_init_port(DMA_PORT_ETOP); ++ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); + + priv->txch.dma.nr = tx; + priv->txch.dma.dev = &priv->pdev->dev; +@@ -676,8 +679,8 @@ ltq_etop_tx(struct sk_buff *skb, struct + return NETDEV_TX_BUSY; + } + +- /* dma needs to start on a 16 byte aligned address */ +- byte_offset = CPHYSADDR(skb->data) % 16; ++ /* dma needs to start on a burst length value aligned address */ ++ byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4); + priv->txch.skb[priv->txch.dma.desc] = skb; + + netif_trans_update(dev); +@@ -925,6 +928,18 @@ static int ltq_etop_probe(struct platfor + spin_lock_init(&priv->lock); + SET_NETDEV_DEV(dev, &pdev->dev); + ++ err = device_property_read_u32(&pdev->dev, "lantiq,tx-burst-length", &priv->tx_burst_len); ++ if (err < 0) { ++ dev_err(&pdev->dev, "unable to read tx-burst-length property\n"); ++ return err; ++ } ++ ++ err = device_property_read_u32(&pdev->dev, "lantiq,rx-burst-length", &priv->rx_burst_len); ++ if (err < 0) { ++ dev_err(&pdev->dev, "unable to read rx-burst-length property\n"); ++ return err; ++ } ++ + netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); + netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); + priv->txch.netdev = dev; +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -81,6 +81,9 @@ struct xrx200_priv { + struct net_device *net_dev; + struct device *dev; + ++ int tx_burst_len; ++ int rx_burst_len; ++ + __iomem void *pmac_reg; + }; + +@@ -363,8 +366,8 @@ static netdev_tx_t xrx200_start_xmit(str + if (unlikely(dma_mapping_error(priv->dev, mapping))) + goto err_drop; + +- /* dma needs to start on a 16 byte aligned address */ +- byte_offset = mapping % 16; ++ /* dma needs to start on a burst length value aligned address */ ++ byte_offset = mapping % (priv->tx_burst_len * 4); + + desc->addr = mapping - byte_offset; + /* Make sure the address is written before we give it to HW */ +@@ -465,7 +468,7 @@ static int xrx200_dma_init(struct xrx200 + int ret = 0; + int i; + +- ltq_dma_init_port(DMA_PORT_ETOP); ++ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); + + ch_rx->dma.nr = XRX200_DMA_RX; + ch_rx->dma.dev = priv->dev; +@@ -575,6 +578,18 @@ static int xrx200_probe(struct platform_ + if (err) + eth_hw_addr_random(net_dev); + ++ err = device_property_read_u32(dev, "lantiq,tx-burst-length", &priv->tx_burst_len); ++ if (err < 0) { ++ dev_err(dev, "unable to read tx-burst-length property\n"); ++ return err; ++ } ++ ++ err = device_property_read_u32(dev, "lantiq,rx-burst-length", &priv->rx_burst_len); ++ if (err < 0) { ++ dev_err(dev, "unable to read rx-burst-length property\n"); ++ return err; ++ } ++ + /* bring up the dma engine and IP core */ + err = xrx200_dma_init(priv); + if (err) diff --git a/target/linux/lantiq/patches-5.15/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch b/target/linux/lantiq/patches-5.15/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch new file mode 100644 index 0000000000..e002f81d5a --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch @@ -0,0 +1,73 @@ +From 7e553c44f09a8f536090904c6db5b8c9dbafa03b Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 26 Oct 2021 22:59:01 +0200 +Subject: [PATCH] net: lantiq_xrx200: Hardcode the burst length value + +All SoCs with this IP core support 8 burst length. Hauke +suggested to hardcode this value and simplify the driver. + +Link: https://lkml.org/lkml/2021/9/14/1533 +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/lantiq_xrx200.c | 21 ++++----------------- + 1 file changed, 4 insertions(+), 17 deletions(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -25,6 +25,7 @@ + #define XRX200_DMA_DATA_LEN (SZ_64K - 1) + #define XRX200_DMA_RX 0 + #define XRX200_DMA_TX 1 ++#define XRX200_DMA_BURST_LEN 8 + + #define XRX200_DMA_PACKET_COMPLETE 0 + #define XRX200_DMA_PACKET_IN_PROGRESS 1 +@@ -81,9 +82,6 @@ struct xrx200_priv { + struct net_device *net_dev; + struct device *dev; + +- int tx_burst_len; +- int rx_burst_len; +- + __iomem void *pmac_reg; + }; + +@@ -367,7 +365,7 @@ static netdev_tx_t xrx200_start_xmit(str + goto err_drop; + + /* dma needs to start on a burst length value aligned address */ +- byte_offset = mapping % (priv->tx_burst_len * 4); ++ byte_offset = mapping % (XRX200_DMA_BURST_LEN * 4); + + desc->addr = mapping - byte_offset; + /* Make sure the address is written before we give it to HW */ +@@ -468,7 +466,8 @@ static int xrx200_dma_init(struct xrx200 + int ret = 0; + int i; + +- ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); ++ ltq_dma_init_port(DMA_PORT_ETOP, XRX200_DMA_BURST_LEN, ++ XRX200_DMA_BURST_LEN); + + ch_rx->dma.nr = XRX200_DMA_RX; + ch_rx->dma.dev = priv->dev; +@@ -578,18 +577,6 @@ static int xrx200_probe(struct platform_ + if (err) + eth_hw_addr_random(net_dev); + +- err = device_property_read_u32(dev, "lantiq,tx-burst-length", &priv->tx_burst_len); +- if (err < 0) { +- dev_err(dev, "unable to read tx-burst-length property\n"); +- return err; +- } +- +- err = device_property_read_u32(dev, "lantiq,rx-burst-length", &priv->rx_burst_len); +- if (err < 0) { +- dev_err(dev, "unable to read rx-burst-length property\n"); +- return err; +- } +- + /* bring up the dma engine and IP core */ + err = xrx200_dma_init(priv); + if (err) diff --git a/target/linux/lantiq/patches-5.15/0712-v5.16-net-ethernet-lantiq_etop-Fix-compilation-error.patch b/target/linux/lantiq/patches-5.15/0712-v5.16-net-ethernet-lantiq_etop-Fix-compilation-error.patch new file mode 100644 index 0000000000..06f4bc2eee --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0712-v5.16-net-ethernet-lantiq_etop-Fix-compilation-error.patch @@ -0,0 +1,26 @@ +From 68eabc348148ae051631e8dab13c3b1a85c82896 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 9 Nov 2021 23:23:54 +0100 +Subject: [PATCH] net: ethernet: lantiq_etop: Fix compilation error + +This fixes the error detected when compiling the driver. + +Fixes: 14d4e308e0aa ("net: lantiq: configure the burst length in ethernet drivers") +Reported-by: kernel test robot +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/lantiq_etop.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -402,7 +402,7 @@ ltq_etop_dma_init(struct net_device *dev + int rx = priv->rx_irq - LTQ_DMA_ETOP; + int err; + +- ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); ++ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len); + + priv->txch.dma.nr = tx; + priv->txch.dma.dev = &priv->pdev->dev; diff --git a/target/linux/lantiq/patches-5.15/0713-v5.17-MIPS-lantiq-dma-increase-descritor-count.patch b/target/linux/lantiq/patches-5.15/0713-v5.17-MIPS-lantiq-dma-increase-descritor-count.patch new file mode 100644 index 0000000000..37ed1d4f31 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0713-v5.17-MIPS-lantiq-dma-increase-descritor-count.patch @@ -0,0 +1,28 @@ +From 5112e9234bbb89f8dd15c983206bd9107b8436d5 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 4 Jan 2022 16:11:42 +0100 +Subject: [PATCH 713/715] MIPS: lantiq: dma: increase descritor count + +NAT Performance results on BT Home Hub 5A (kernel 5.10.89, mtu 1500): + + Down Up +Before 539 Mbps 599 Mbps +After 545 Mbps 625 Mbps + +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + arch/mips/include/asm/mach-lantiq/xway/xway_dma.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h +@@ -8,7 +8,7 @@ + #define LTQ_DMA_H__ + + #define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */ +-#define LTQ_DESC_NUM 0x40 /* 64 descriptors / channel */ ++#define LTQ_DESC_NUM 0xC0 /* 192 descriptors / channel */ + + #define LTQ_DMA_OWN BIT(31) /* owner bit */ + #define LTQ_DMA_C BIT(30) /* complete bit */ diff --git a/target/linux/lantiq/patches-5.15/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch b/target/linux/lantiq/patches-5.15/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch new file mode 100644 index 0000000000..10791f9d53 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch @@ -0,0 +1,32 @@ +From 768818d772d5d4ddc0c7eb2e62848929270ab7a3 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 4 Jan 2022 16:11:43 +0100 +Subject: [PATCH 714/715] net: lantiq_xrx200: increase napi poll weigth + +NAT Performance results on BT Home Hub 5A (kernel 5.10.89, mtu 1500): + + Down Up +Before 545 Mbps 625 Mbps +After 577 Mbps 648 Mbps + +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/lantiq_xrx200.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -597,8 +597,10 @@ static int xrx200_probe(struct platform_ + PMAC_HD_CTL); + + /* setup NAPI */ +- netif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, 32); +- netif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, 32); ++ netif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, ++ NAPI_POLL_WEIGHT); ++ netif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, ++ NAPI_POLL_WEIGHT); + + platform_set_drvdata(pdev, priv); + diff --git a/target/linux/lantiq/patches-5.15/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch b/target/linux/lantiq/patches-5.15/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch new file mode 100644 index 0000000000..6613d0bbd7 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch @@ -0,0 +1,206 @@ +From e015593573b3e3f74bd8a63c05fa92902194a354 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 4 Jan 2022 16:11:44 +0100 +Subject: [PATCH 715/715] net: lantiq_xrx200: convert to build_skb + +We can increase the efficiency of rx path by using buffers to receive +packets then build SKBs around them just before passing into the network +stack. In contrast, preallocating SKBs too early reduces CPU cache +efficiency. + +NAT Performance results on BT Home Hub 5A (kernel 5.10.89, mtu 1500): + + Down Up +Before 577 Mbps 648 Mbps +After 624 Mbps 695 Mbps + +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/lantiq_xrx200.c | 56 ++++++++++++++++++---------- + 1 file changed, 36 insertions(+), 20 deletions(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -63,7 +63,11 @@ struct xrx200_chan { + + struct napi_struct napi; + struct ltq_dma_channel dma; +- struct sk_buff *skb[LTQ_DESC_NUM]; ++ ++ union { ++ struct sk_buff *skb[LTQ_DESC_NUM]; ++ void *rx_buff[LTQ_DESC_NUM]; ++ }; + + struct sk_buff *skb_head; + struct sk_buff *skb_tail; +@@ -78,6 +82,7 @@ struct xrx200_priv { + struct xrx200_chan chan_rx; + + u16 rx_buf_size; ++ u16 rx_skb_size; + + struct net_device *net_dev; + struct device *dev; +@@ -115,6 +120,12 @@ static int xrx200_buffer_size(int mtu) + return round_up(xrx200_max_frame_len(mtu), 4 * XRX200_DMA_BURST_LEN); + } + ++static int xrx200_skb_size(u16 buf_size) ++{ ++ return SKB_DATA_ALIGN(buf_size + NET_SKB_PAD + NET_IP_ALIGN) + ++ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); ++} ++ + /* drop all the packets from the DMA ring */ + static void xrx200_flush_dma(struct xrx200_chan *ch) + { +@@ -173,30 +184,29 @@ static int xrx200_close(struct net_devic + return 0; + } + +-static int xrx200_alloc_skb(struct xrx200_chan *ch) ++static int xrx200_alloc_buf(struct xrx200_chan *ch, void *(*alloc)(unsigned int size)) + { +- struct sk_buff *skb = ch->skb[ch->dma.desc]; ++ void *buf = ch->rx_buff[ch->dma.desc]; + struct xrx200_priv *priv = ch->priv; + dma_addr_t mapping; + int ret = 0; + +- ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(priv->net_dev, +- priv->rx_buf_size); +- if (!ch->skb[ch->dma.desc]) { ++ ch->rx_buff[ch->dma.desc] = alloc(priv->rx_skb_size); ++ if (!ch->rx_buff[ch->dma.desc]) { + ret = -ENOMEM; + goto skip; + } + +- mapping = dma_map_single(priv->dev, ch->skb[ch->dma.desc]->data, ++ mapping = dma_map_single(priv->dev, ch->rx_buff[ch->dma.desc], + priv->rx_buf_size, DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(priv->dev, mapping))) { +- dev_kfree_skb_any(ch->skb[ch->dma.desc]); +- ch->skb[ch->dma.desc] = skb; ++ skb_free_frag(ch->rx_buff[ch->dma.desc]); ++ ch->rx_buff[ch->dma.desc] = buf; + ret = -ENOMEM; + goto skip; + } + +- ch->dma.desc_base[ch->dma.desc].addr = mapping; ++ ch->dma.desc_base[ch->dma.desc].addr = mapping + NET_SKB_PAD + NET_IP_ALIGN; + /* Make sure the address is written before we give it to HW */ + wmb(); + skip: +@@ -210,13 +220,14 @@ static int xrx200_hw_receive(struct xrx2 + { + struct xrx200_priv *priv = ch->priv; + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +- struct sk_buff *skb = ch->skb[ch->dma.desc]; ++ void *buf = ch->rx_buff[ch->dma.desc]; + u32 ctl = desc->ctl; + int len = (ctl & LTQ_DMA_SIZE_MASK); + struct net_device *net_dev = priv->net_dev; ++ struct sk_buff *skb; + int ret; + +- ret = xrx200_alloc_skb(ch); ++ ret = xrx200_alloc_buf(ch, napi_alloc_frag); + + ch->dma.desc++; + ch->dma.desc %= LTQ_DESC_NUM; +@@ -227,19 +238,21 @@ static int xrx200_hw_receive(struct xrx2 + return ret; + } + ++ skb = build_skb(buf, priv->rx_skb_size); ++ skb_reserve(skb, NET_SKB_PAD); + skb_put(skb, len); + + /* add buffers to skb via skb->frag_list */ + if (ctl & LTQ_DMA_SOP) { + ch->skb_head = skb; + ch->skb_tail = skb; ++ skb_reserve(skb, NET_IP_ALIGN); + } else if (ch->skb_head) { + if (ch->skb_head == ch->skb_tail) + skb_shinfo(ch->skb_tail)->frag_list = skb; + else + ch->skb_tail->next = skb; + ch->skb_tail = skb; +- skb_reserve(ch->skb_tail, -NET_IP_ALIGN); + ch->skb_head->len += skb->len; + ch->skb_head->data_len += skb->len; + ch->skb_head->truesize += skb->truesize; +@@ -395,12 +408,13 @@ xrx200_change_mtu(struct net_device *net + struct xrx200_chan *ch_rx = &priv->chan_rx; + int old_mtu = net_dev->mtu; + bool running = false; +- struct sk_buff *skb; ++ void *buff; + int curr_desc; + int ret = 0; + + net_dev->mtu = new_mtu; + priv->rx_buf_size = xrx200_buffer_size(new_mtu); ++ priv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size); + + if (new_mtu <= old_mtu) + return ret; +@@ -416,14 +430,15 @@ xrx200_change_mtu(struct net_device *net + + for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; + ch_rx->dma.desc++) { +- skb = ch_rx->skb[ch_rx->dma.desc]; +- ret = xrx200_alloc_skb(ch_rx); ++ buff = ch_rx->rx_buff[ch_rx->dma.desc]; ++ ret = xrx200_alloc_buf(ch_rx, netdev_alloc_frag); + if (ret) { + net_dev->mtu = old_mtu; + priv->rx_buf_size = xrx200_buffer_size(old_mtu); ++ priv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size); + break; + } +- dev_kfree_skb_any(skb); ++ skb_free_frag(buff); + } + + ch_rx->dma.desc = curr_desc; +@@ -476,7 +491,7 @@ static int xrx200_dma_init(struct xrx200 + ltq_dma_alloc_rx(&ch_rx->dma); + for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; + ch_rx->dma.desc++) { +- ret = xrx200_alloc_skb(ch_rx); ++ ret = xrx200_alloc_buf(ch_rx, netdev_alloc_frag); + if (ret) + goto rx_free; + } +@@ -511,7 +526,7 @@ rx_ring_free: + /* free the allocated RX ring */ + for (i = 0; i < LTQ_DESC_NUM; i++) { + if (priv->chan_rx.skb[i]) +- dev_kfree_skb_any(priv->chan_rx.skb[i]); ++ skb_free_frag(priv->chan_rx.rx_buff[i]); + } + + rx_free: +@@ -528,7 +543,7 @@ static void xrx200_hw_cleanup(struct xrx + + /* free the allocated RX ring */ + for (i = 0; i < LTQ_DESC_NUM; i++) +- dev_kfree_skb_any(priv->chan_rx.skb[i]); ++ skb_free_frag(priv->chan_rx.rx_buff[i]); + } + + static int xrx200_probe(struct platform_device *pdev) +@@ -553,6 +568,7 @@ static int xrx200_probe(struct platform_ + net_dev->min_mtu = ETH_ZLEN; + net_dev->max_mtu = XRX200_DMA_DATA_LEN - xrx200_max_frame_len(0); + priv->rx_buf_size = xrx200_buffer_size(ETH_DATA_LEN); ++ priv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size); + + /* load the memory ranges */ + priv->pmac_reg = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); diff --git a/target/linux/lantiq/patches-5.15/0716-v5.17-net-lantiq_xrx200-fix-use-after-free-bug.patch b/target/linux/lantiq/patches-5.15/0716-v5.17-net-lantiq_xrx200-fix-use-after-free-bug.patch new file mode 100644 index 0000000000..090b7e3111 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0716-v5.17-net-lantiq_xrx200-fix-use-after-free-bug.patch @@ -0,0 +1,30 @@ +From dd830aed23c6e07cd8e2a163742bf3d63c9add08 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Sat, 5 Mar 2022 12:20:39 +0100 +Subject: net: lantiq_xrx200: fix use after free bug + +The skb->len field is read after the packet is sent to the network +stack. In the meantime, skb can be freed. This patch fixes this bug. + +Fixes: c3e6b2c35b34 ("net: lantiq_xrx200: add ingress SG DMA support") +Reported-by: Eric Dumazet +Signed-off-by: Aleksander Jan Bajkowski +Acked-by: Hauke Mehrtens +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/lantiq_xrx200.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -260,9 +260,9 @@ static int xrx200_hw_receive(struct xrx2 + + if (ctl & LTQ_DMA_EOP) { + ch->skb_head->protocol = eth_type_trans(ch->skb_head, net_dev); +- netif_receive_skb(ch->skb_head); + net_dev->stats.rx_packets++; + net_dev->stats.rx_bytes += ch->skb_head->len; ++ netif_receive_skb(ch->skb_head); + ch->skb_head = NULL; + ch->skb_tail = NULL; + ret = XRX200_DMA_PACKET_COMPLETE; diff --git a/target/linux/lantiq/patches-5.15/0717-v6.0-net-lantiq_xrx200-confirm-skb-is-allocated-before-us.patch b/target/linux/lantiq/patches-5.15/0717-v6.0-net-lantiq_xrx200-confirm-skb-is-allocated-before-us.patch new file mode 100644 index 0000000000..9eaec58033 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0717-v6.0-net-lantiq_xrx200-confirm-skb-is-allocated-before-us.patch @@ -0,0 +1,33 @@ +From c8b043702dc0894c07721c5b019096cebc8c798f Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Wed, 24 Aug 2022 23:54:06 +0200 +Subject: [PATCH] net: lantiq_xrx200: confirm skb is allocated before using + +xrx200_hw_receive() assumes build_skb() always works and goes straight +to skb_reserve(). However, build_skb() can fail under memory pressure. + +Add a check in case build_skb() failed to allocate and return NULL. + +Fixes: e015593573b3 ("net: lantiq_xrx200: convert to build_skb") +Reported-by: Eric Dumazet +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/lantiq_xrx200.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -239,6 +239,12 @@ static int xrx200_hw_receive(struct xrx2 + } + + skb = build_skb(buf, priv->rx_skb_size); ++ if (!skb) { ++ skb_free_frag(buf); ++ net_dev->stats.rx_dropped++; ++ return -ENOMEM; ++ } ++ + skb_reserve(skb, NET_SKB_PAD); + skb_put(skb, len); + diff --git a/target/linux/lantiq/patches-5.15/0718-v6.0-net-lantiq_xrx200-fix-lock-under-memory-pressure.patch b/target/linux/lantiq/patches-5.15/0718-v6.0-net-lantiq_xrx200-fix-lock-under-memory-pressure.patch new file mode 100644 index 0000000000..929ae57ace --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0718-v6.0-net-lantiq_xrx200-fix-lock-under-memory-pressure.patch @@ -0,0 +1,33 @@ +From c4b6e9341f930e4dd089231c0414758f5f1f9dbd Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Wed, 24 Aug 2022 23:54:07 +0200 +Subject: [PATCH] net: lantiq_xrx200: fix lock under memory pressure + +When the xrx200_hw_receive() function returns -ENOMEM, the NAPI poll +function immediately returns an error. +This is incorrect for two reasons: +* the function terminates without enabling interrupts or scheduling NAPI, +* the error code (-ENOMEM) is returned instead of the number of received +packets. + +After the first memory allocation failure occurs, packet reception is +locked due to disabled interrupts from DMA.. + +Fixes: fe1a56420cf2 ("net: lantiq: Add Lantiq / Intel VRX200 Ethernet driver") +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/lantiq_xrx200.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -294,7 +294,7 @@ static int xrx200_poll_rx(struct napi_st + if (ret == XRX200_DMA_PACKET_IN_PROGRESS) + continue; + if (ret != XRX200_DMA_PACKET_COMPLETE) +- return ret; ++ break; + rx++; + } else { + break; diff --git a/target/linux/lantiq/patches-5.15/0719-v6.0-net-lantiq_xrx200-restore-buffer-if-memory-allocatio.patch b/target/linux/lantiq/patches-5.15/0719-v6.0-net-lantiq_xrx200-restore-buffer-if-memory-allocatio.patch new file mode 100644 index 0000000000..182da58ed9 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0719-v6.0-net-lantiq_xrx200-restore-buffer-if-memory-allocatio.patch @@ -0,0 +1,27 @@ +From c9c3b1775f80fa21f5bff874027d2ccb10f5d90c Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Wed, 24 Aug 2022 23:54:08 +0200 +Subject: [PATCH] net: lantiq_xrx200: restore buffer if memory allocation + failed + +In a situation where memory allocation fails, an invalid buffer address +is stored. When this descriptor is used again, the system panics in the +build_skb() function when accessing memory. + +Fixes: 7ea6cd16f159 ("lantiq: net: fix duplicated skb in rx descriptor ring") +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/lantiq_xrx200.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -193,6 +193,7 @@ static int xrx200_alloc_buf(struct xrx20 + + ch->rx_buff[ch->dma.desc] = alloc(priv->rx_skb_size); + if (!ch->rx_buff[ch->dma.desc]) { ++ ch->rx_buff[ch->dma.desc] = buf; + ret = -ENOMEM; + goto skip; + } diff --git a/target/linux/lantiq/xrx200/config-5.15 b/target/linux/lantiq/xrx200/config-5.15 new file mode 100644 index 0000000000..4dfd55274a --- /dev/null +++ b/target/linux/lantiq/xrx200/config-5.15 @@ -0,0 +1,93 @@ +CONFIG_AT803X_PHY=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin" +CONFIG_EXTRA_FIRMWARE_DIR="firmware" +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GRO_CELLS=y +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_ICPLUS_PHY=y +CONFIG_IFX_VPE_EXT=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +CONFIG_INTEL_XWAY_PHY=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_XRX200=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MIPS_MT=y +# CONFIG_MIPS_MT_FPAFF is not set +CONFIG_MIPS_MT_SMP=y +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MIPS_VPE_APSP_API=y +CONFIG_MIPS_VPE_APSP_API_MT=y +CONFIG_MIPS_VPE_LOADER=y +CONFIG_MIPS_VPE_LOADER_MT=y +CONFIG_MIPS_VPE_LOADER_TOM=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MTD_NAND_XWAY=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_LANTIQ_GSWIP=y +CONFIG_NET_DSA_TAG_GSWIP=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NLS=y +CONFIG_NR_CPUS=2 +CONFIG_PADATA=y +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_LANTIQ=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_PHY_LANTIQ_VRX200_PCIE=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_SENSORS_LTQ_CPUTEMP=y +CONFIG_SGL_ALLOC=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SOC_XWAY=y +CONFIG_SYNC_R4K=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/lantiq/xway/config-5.15 b/target/linux/lantiq/xway/config-5.15 new file mode 100644 index 0000000000..8ff706fea9 --- /dev/null +++ b/target/linux/lantiq/xway/config-5.15 @@ -0,0 +1,46 @@ +CONFIG_ADM6996_PHY=y +CONFIG_AR8216_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LZO=y +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HW_RANDOM=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_ETOP=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_XWAY=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NLS=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_PSB6970_PHY=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTL8306_PHY=y +CONFIG_RTL8366RB_PHY=y +CONFIG_RTL8366_SMI=y +CONFIG_SGL_ALLOC=y +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SOC_XWAY=y +CONFIG_SWCONFIG=y +CONFIG_UBIFS_FS=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y diff --git a/target/linux/lantiq/xway_legacy/config-5.15 b/target/linux/lantiq/xway_legacy/config-5.15 new file mode 100644 index 0000000000..c177d2a935 --- /dev/null +++ b/target/linux/lantiq/xway_legacy/config-5.15 @@ -0,0 +1,33 @@ +CONFIG_ADM6996_PHY=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_GENERIC_ALLOCATOR=y +# CONFIG_GPIO_SYSFS is not set +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_ETOP=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_NLS=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTL8306_PHY=y +CONFIG_SGL_ALLOC=y +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SOC_XWAY=y +CONFIG_SWCONFIG=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/layerscape/armv8_64b/config-5.10 b/target/linux/layerscape/armv8_64b/config-5.10 index 0d4afa9809..10aaace99c 100644 --- a/target/linux/layerscape/armv8_64b/config-5.10 +++ b/target/linux/layerscape/armv8_64b/config-5.10 @@ -147,6 +147,7 @@ CONFIG_CPU_FREQ_THERMAL=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y diff --git a/target/linux/malta/be/config-default b/target/linux/malta/be/config-default index 5586be6b7c..0e7faa0877 100644 --- a/target/linux/malta/be/config-default +++ b/target/linux/malta/be/config-default @@ -1,4 +1,3 @@ CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_CPU_MIPS32_R2=y CONFIG_HIGHMEM=y diff --git a/target/linux/malta/be64/config-default b/target/linux/malta/be64/config-default index ef044bb8ca..a7e88feda0 100644 --- a/target/linux/malta/be64/config-default +++ b/target/linux/malta/be64/config-default @@ -2,7 +2,6 @@ CONFIG_64BIT=y CONFIG_ARCH_MMAP_RND_BITS=12 CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_CPU_MIPS64_R2=y # CONFIG_MIPS32_N32 is not set # CONFIG_MIPS32_O32 is not set diff --git a/target/linux/mediatek/filogic/config-5.15 b/target/linux/mediatek/filogic/config-5.15 index 2e21cc3ce5..cabb2b74ae 100644 --- a/target/linux/mediatek/filogic/config-5.15 +++ b/target/linux/mediatek/filogic/config-5.15 @@ -78,6 +78,7 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y CONFIG_CRC16=y diff --git a/target/linux/mediatek/mt7622/config-5.15 b/target/linux/mediatek/mt7622/config-5.15 index 4a753c1b9f..305edc1e9a 100644 --- a/target/linux/mediatek/mt7622/config-5.15 +++ b/target/linux/mediatek/mt7622/config-5.15 @@ -107,6 +107,7 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y CONFIG_CRC16=y diff --git a/target/linux/mvebu/cortexa53/config-5.10 b/target/linux/mvebu/cortexa53/config-5.10 index 9c76159d51..fd58578405 100644 --- a/target/linux/mvebu/cortexa53/config-5.10 +++ b/target/linux/mvebu/cortexa53/config-5.10 @@ -34,6 +34,7 @@ CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_PSCI_FW=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y diff --git a/target/linux/mvebu/cortexa53/config-5.15 b/target/linux/mvebu/cortexa53/config-5.15 index 3c195291d1..27d410f68b 100644 --- a/target/linux/mvebu/cortexa53/config-5.15 +++ b/target/linux/mvebu/cortexa53/config-5.15 @@ -36,6 +36,7 @@ CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_PSCI_FW=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_FRAME_POINTER=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y diff --git a/target/linux/mvebu/cortexa72/config-5.10 b/target/linux/mvebu/cortexa72/config-5.10 index d0eeb4b739..584c3fc9b8 100644 --- a/target/linux/mvebu/cortexa72/config-5.10 +++ b/target/linux/mvebu/cortexa72/config-5.10 @@ -34,6 +34,7 @@ CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_PSCI_FW=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y diff --git a/target/linux/mvebu/cortexa72/config-5.15 b/target/linux/mvebu/cortexa72/config-5.15 index 7e07c28ba6..37379834d3 100644 --- a/target/linux/mvebu/cortexa72/config-5.15 +++ b/target/linux/mvebu/cortexa72/config-5.15 @@ -36,6 +36,7 @@ CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_PSCI_FW=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_FRAME_POINTER=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y diff --git a/target/linux/octeon/config-5.10 b/target/linux/octeon/config-5.10 index 997d22008c..58a02e6e6d 100644 --- a/target/linux/octeon/config-5.10 +++ b/target/linux/octeon/config-5.10 @@ -32,7 +32,6 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_CPU_MIPS64=y CONFIG_CPU_MIPSR2=y CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y diff --git a/target/linux/octeon/config-5.15 b/target/linux/octeon/config-5.15 index f125858636..450b84be44 100644 --- a/target/linux/octeon/config-5.15 +++ b/target/linux/octeon/config-5.15 @@ -34,7 +34,6 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_CPU_MIPS64=y CONFIG_CPU_MIPSR2=y CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y diff --git a/target/linux/octeontx/config-5.10 b/target/linux/octeontx/config-5.10 index fa6fcc3e8a..19a8c258d9 100644 --- a/target/linux/octeontx/config-5.10 +++ b/target/linux/octeontx/config-5.10 @@ -86,6 +86,7 @@ CONFIG_CONTIG_ALLOC=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CRASH_CORE=y diff --git a/target/linux/oxnas/Makefile b/target/linux/oxnas/Makefile index 9dfdb5c86e..2884a66cc7 100644 --- a/target/linux/oxnas/Makefile +++ b/target/linux/oxnas/Makefile @@ -7,8 +7,7 @@ SUBTARGETS:=ox810se ox820 FEATURES:=gpio ramdisk rtc squashfs DEVICE_TYPE:=nas -KERNEL_PATCHVER:=5.10 -KERNEL_TESTING_PATCHVER:=5.15 +KERNEL_PATCHVER:=5.15 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/oxnas/config-5.10 b/target/linux/oxnas/config-5.10 deleted file mode 100644 index dd1706cb13..0000000000 --- a/target/linux/oxnas/config-5.10 +++ /dev/null @@ -1,357 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HAS_BINFMT_FLAT=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_KCOV=y -CONFIG_ARCH_HAS_KEEPINITRD=y -CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_ARCH_HAS_PHYS_TO_DMA=y -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAS_SETUP_DMA_OPS=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_CPU_AUTO=y -# CONFIG_ARCH_MULTI_V4 is not set -# CONFIG_ARCH_MULTI_V4T is not set -CONFIG_ARCH_MULTI_V4_V5=y -CONFIG_ARCH_MULTI_V5=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OXNAS=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_LIBATA_LEDS=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_PMU=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_CMDLINE_PARSER=y -CONFIG_BLK_DEBUG_FS=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_CC_HAS_KASAN_GENERIC=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=64 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -CONFIG_CMDLINE_PARTITION=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_OXNAS=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONTIG_ALLOC=y -CONFIG_COREDUMP=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5TJ=y -CONFIG_CPU_ARM926T=y -# CONFIG_CPU_CACHE_ROUND_ROBIN is not set -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_PM=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_USE_DOMAINS=y -CONFIG_CRASH_CORE=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_RNG2=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEBUG_USER is not set -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_LZ4=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DMA_CMA=y -CONFIG_DMA_REMAP=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -# CONFIG_DWMAC_DWC_QOS_ETH is not set -CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_OXNAS=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ELF_CORE=y -CONFIG_FAT_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FREEZER=y -# CONFIG_FW_CACHE is not set -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_COPY_THREAD_TLS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PCI=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -CONFIG_HWMON=y -CONFIG_HZ_FIXED=0 -CONFIG_ICPLUS_PHY=y -CONFIG_INET_DIAG=y -# CONFIG_INET_DIAG_DESTROY is not set -# CONFIG_INET_RAW_DIAG is not set -CONFIG_INET_TCP_DIAG=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -# CONFIG_ISDN is not set -# CONFIG_JFFS2_FS is not set -CONFIG_KALLSYMS=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_XZ is not set -CONFIG_KEXEC=y -CONFIG_KEXEC_CORE=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_OX810SE is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_KUSER_HELPERS=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NLS=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OXNAS_RPS_TIMER=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHY_OXNAS=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_OXNAS=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PM=y -CONFIG_PM_CLK=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_OXNAS=y -CONFIG_PPS=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RCU_TRACE=y -CONFIG_RD_BZIP2=y -CONFIG_RD_GZIP=y -CONFIG_RD_LZ4=y -CONFIG_RD_LZMA=y -CONFIG_RD_LZO=y -CONFIG_RD_XZ=y -CONFIG_REALTEK_PHY=y -CONFIG_REFCOUNT_FULL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_OXNAS=y -CONFIG_SCHED_DEBUG=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_SERPORT=y -CONFIG_SIMPLE_PM_BUS=y -CONFIG_SLUB_DEBUG=y -CONFIG_SOCK_DIAG=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPLIT_PTLOCK_CPUS=999999 -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -# CONFIG_STMMAC_SELFTESTS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWPHY=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_TRACE_CLOCK=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -# CONFIG_UNWINDER_FRAME_POINTER is not set -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VERSATILE_FPGA_IRQ=y -CONFIG_VERSATILE_FPGA_IRQ_NR=4 -CONFIG_VFAT_FS=y -# CONFIG_VFP is not set -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_WATCHDOG is not set -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_IA64=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_X86=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts index 0bcd2fcf00..2cff439c25 100644 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts +++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts @@ -31,7 +31,7 @@ led-upgrade = &led_warn; }; - thermal_zones { + thermal-zones { chassis-thermal { /* Poll every 20 seconds */ polling-delay = <20000>; @@ -153,6 +153,7 @@ gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; gpio-fan,speed-map = <0 0 3000 1>; + #cooling-cells = <2>; }; gpio-poweroff { diff --git a/target/linux/oxnas/files/drivers/ata/sata_oxnas.c b/target/linux/oxnas/files/drivers/ata/sata_oxnas.c index a5d7b3de72..217c258565 100644 --- a/target/linux/oxnas/files/drivers/ata/sata_oxnas.c +++ b/target/linux/oxnas/files/drivers/ata/sata_oxnas.c @@ -2232,9 +2232,6 @@ static struct scsi_host_template sata_oxnas_sht = { .can_queue = SATA_OXNAS_QUEUE_DEPTH, .sg_tablesize = SATA_OXNAS_MAX_PRD, .dma_boundary = ATA_DMA_BOUNDARY, -#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 13, 0) - .unchecked_isa_dma = 0, -#endif }; diff --git a/target/linux/oxnas/patches-5.10/010-pogoplug-series-3.patch b/target/linux/oxnas/patches-5.10/010-pogoplug-series-3.patch deleted file mode 100644 index 44102352af..0000000000 --- a/target/linux/oxnas/patches-5.10/010-pogoplug-series-3.patch +++ /dev/null @@ -1,82 +0,0 @@ -- add compatible string -- add console to bootargs -- add led aliases -- adjust nand partition table ---- ---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts -+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts -@@ -11,10 +11,10 @@ - / { - model = "Cloud Engines PogoPlug Series 3"; - -- compatible = "cloudengines,pogoplugv3", "oxsemi,ox820"; -+ compatible = "cloudengines,pogoplug-series-3", "cloudengines,pogoplugv3", "oxsemi,ox820"; - - chosen { -- bootargs = "earlyprintk"; -+ bootargs = "earlyprintk console=ttyS0,115200"; - stdout-path = "serial0:115200n8"; - }; - -@@ -27,24 +27,28 @@ - serial0 = &uart0; - gpio0 = &gpio0; - gpio1 = &gpio1; -+ led-boot = &led_status; -+ led-failsafe = &led_warn; -+ led-running = &led_act; -+ led-upgrade = &led_warn; - }; - - leds { - compatible = "gpio-leds"; - -- blue { -+ led_status: blue { - label = "pogoplug:blue"; - gpios = <&gpio0 2 0>; - default-state = "keep"; - }; - -- orange { -+ led_warn: orange { - label = "pogoplug:orange"; - gpios = <&gpio1 16 1>; - default-state = "keep"; - }; - -- green { -+ led_act: green { - label = "pogoplug:green"; - gpios = <&gpio1 17 1>; - default-state = "keep"; -@@ -73,11 +77,27 @@ - nand-ecc-algo = "hamming"; - - partition@0 { -- label = "boot"; -- reg = <0x00000000 0x00e00000>; -+ label = "stage1"; -+ reg = <0x00000000 0x00040000>; - read-only; - }; - -+ partition@40000 { -+ label = "u-boot"; -+ reg = <0x00040000 0x00380000>; -+ read-only; -+ }; -+ -+ partition@3c0000 { -+ label = "u-boot-env"; -+ reg = <0x003c0000 0x00080000>; -+ }; -+ -+ partition@440000 { -+ label = "kernel"; -+ reg = <0x00440000 0x009c0000>; -+ }; -+ - partition@e00000 { - label = "ubi"; - reg = <0x00e00000 0x07200000>; diff --git a/target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch b/target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch deleted file mode 100644 index e30f328792..0000000000 --- a/target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 1 Jun 2018 02:41:15 +0200 -Subject: [PATCH] arm: ox820: remove left-overs - -Signed-off-by: Daniel Golle ---- - drivers/clk/clk-oxnas.c | 2 -- - include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++------------- - 2 files changed, 14 insertions(+), 20 deletions(-) - ---- a/drivers/clk/clk-oxnas.c -+++ b/drivers/clk/clk-oxnas.c -@@ -29,8 +29,6 @@ struct oxnas_stdclk_data { - struct clk_hw_onecell_data *onecell_data; - struct clk_oxnas_gate **gates; - unsigned int ngates; -- struct clk_oxnas_pll **plls; -- unsigned int nplls; - }; - - /* Regmap offsets */ ---- a/include/dt-bindings/clock/oxsemi,ox820.h -+++ b/include/dt-bindings/clock/oxsemi,ox820.h -@@ -6,24 +6,20 @@ - #ifndef DT_CLOCK_OXSEMI_OX820_H - #define DT_CLOCK_OXSEMI_OX820_H - --/* PLLs */ --#define CLK_820_PLLA 0 --#define CLK_820_PLLB 1 -- - /* Gate Clocks */ --#define CLK_820_LEON 2 --#define CLK_820_DMA_SGDMA 3 --#define CLK_820_CIPHER 4 --#define CLK_820_SD 5 --#define CLK_820_SATA 6 --#define CLK_820_AUDIO 7 --#define CLK_820_USBMPH 8 --#define CLK_820_ETHA 9 --#define CLK_820_PCIEA 10 --#define CLK_820_NAND 11 --#define CLK_820_PCIEB 12 --#define CLK_820_ETHB 13 --#define CLK_820_REF600 14 --#define CLK_820_USBDEV 15 -+#define CLK_820_LEON 0 -+#define CLK_820_DMA_SGDMA 1 -+#define CLK_820_CIPHER 2 -+#define CLK_820_SD 3 -+#define CLK_820_SATA 4 -+#define CLK_820_AUDIO 5 -+#define CLK_820_USBMPH 6 -+#define CLK_820_ETHA 7 -+#define CLK_820_PCIEA 8 -+#define CLK_820_NAND 9 -+#define CLK_820_PCIEB 10 -+#define CLK_820_ETHB 11 -+#define CLK_820_REF600 12 -+#define CLK_820_USBDEV 13 - - #endif /* DT_CLOCK_OXSEMI_OX820_H */ diff --git a/target/linux/oxnas/patches-5.10/100-oxnas-clk-plla-pllb.patch b/target/linux/oxnas/patches-5.10/100-oxnas-clk-plla-pllb.patch deleted file mode 100644 index 6c795c1d25..0000000000 --- a/target/linux/oxnas/patches-5.10/100-oxnas-clk-plla-pllb.patch +++ /dev/null @@ -1,273 +0,0 @@ ---- a/drivers/clk/clk-oxnas.c -+++ b/drivers/clk/clk-oxnas.c -@@ -5,19 +5,42 @@ - * Copyright (C) 2016 Neil Armstrong - */ - -+#include -+#include - #include - #include - #include -+#include - #include - #include - #include - #include - #include - #include -+#include - - #include - #include - -+#define REF300_DIV_INT_SHIFT 8 -+#define REF300_DIV_FRAC_SHIFT 0 -+#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT) -+#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT) -+ -+#define PLLB_BYPASS 1 -+#define PLLB_ENSAT 3 -+#define PLLB_OUTDIV 4 -+#define PLLB_REFDIV 8 -+#define PLLB_DIV_INT_SHIFT 8 -+#define PLLB_DIV_FRAC_SHIFT 0 -+#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT) -+#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT) -+ -+#define PLLA_REFDIV_MASK 0x3F -+#define PLLA_REFDIV_SHIFT 8 -+#define PLLA_OUTDIV_MASK 0x7 -+#define PLLA_OUTDIV_SHIFT 4 -+ - /* Standard regmap gate clocks */ - struct clk_oxnas_gate { - struct clk_hw hw; -@@ -36,6 +59,135 @@ struct oxnas_stdclk_data { - #define CLK_SET_REGOFFSET 0x2c - #define CLK_CLR_REGOFFSET 0x30 - -+#define PLLA_CTRL0_REGOFFSET 0x1f0 -+#define PLLA_CTRL1_REGOFFSET 0x1f4 -+#define PLLB_CTRL0_REGOFFSET 0x1001f0 -+#define MHZ (1000 * 1000) -+ -+struct clk_oxnas_pll { -+ struct clk_hw hw; -+ struct device_node *devnode; -+ struct reset_control *rstc; -+ struct regmap *syscon; -+}; -+ -+#define to_clk_oxnas_pll(_hw) container_of(_hw, struct clk_oxnas_pll, hw) -+ -+static unsigned long plla_clk_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct clk_oxnas_pll *plla = to_clk_oxnas_pll(hw); -+ unsigned long fin = parent_rate; -+ unsigned long refdiv, outdiv; -+ unsigned int pll0, fbdiv; -+ -+ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL0_REGOFFSET, &pll0)); -+ -+ refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK; -+ refdiv += 1; -+ outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK; -+ outdiv += 1; -+ -+ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL1_REGOFFSET, &fbdiv)); -+ /* seems we will not be here when pll is bypassed, so ignore this -+ * case */ -+ -+ return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ; -+} -+ -+static const char *pll_clk_parents[] = { -+ "oscillator", -+}; -+ -+static struct clk_ops plla_ops = { -+ .recalc_rate = plla_clk_recalc_rate, -+}; -+ -+static struct clk_init_data clk_plla_init = { -+ .name = "plla", -+ .ops = &plla_ops, -+ .parent_names = pll_clk_parents, -+ .num_parents = ARRAY_SIZE(pll_clk_parents), -+}; -+ -+static int pllb_clk_is_prepared(struct clk_hw *hw) -+{ -+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); -+ -+ return !!pllb->rstc; -+} -+ -+static int pllb_clk_prepare(struct clk_hw *hw) -+{ -+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); -+ -+ pllb->rstc = of_reset_control_get(pllb->devnode, NULL); -+ -+ return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0; -+} -+ -+static void pllb_clk_unprepare(struct clk_hw *hw) -+{ -+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); -+ -+ BUG_ON(IS_ERR(pllb->rstc)); -+ -+ reset_control_put(pllb->rstc); -+ pllb->rstc = NULL; -+} -+ -+static int pllb_clk_enable(struct clk_hw *hw) -+{ -+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); -+ -+ BUG_ON(IS_ERR(pllb->rstc)); -+ -+ /* put PLL into bypass */ -+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS)); -+ wmb(); -+ udelay(10); -+ reset_control_assert(pllb->rstc); -+ udelay(10); -+ /* set PLL B control information */ -+ regmap_write_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, 0xffff, -+ (1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV)); -+ reset_control_deassert(pllb->rstc); -+ udelay(100); -+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), 0); -+ -+ return 0; -+} -+ -+static void pllb_clk_disable(struct clk_hw *hw) -+{ -+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); -+ -+ BUG_ON(IS_ERR(pllb->rstc)); -+ -+ /* put PLL into bypass */ -+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS)); -+ -+ wmb(); -+ udelay(10); -+ -+ reset_control_assert(pllb->rstc); -+} -+ -+static struct clk_ops pllb_ops = { -+ .prepare = pllb_clk_prepare, -+ .unprepare = pllb_clk_unprepare, -+ .is_prepared = pllb_clk_is_prepared, -+ .enable = pllb_clk_enable, -+ .disable = pllb_clk_disable, -+}; -+ -+static struct clk_init_data clk_pllb_init = { -+ .name = "pllb", -+ .ops = &pllb_ops, -+ .parent_names = pll_clk_parents, -+ .num_parents = ARRAY_SIZE(pll_clk_parents), -+}; -+ - static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw) - { - return container_of(hw, struct clk_oxnas_gate, hw); -@@ -249,3 +401,42 @@ static struct platform_driver oxnas_stdc - }, - }; - builtin_platform_driver(oxnas_stdclk_driver); -+ -+void __init oxnas_init_plla(struct device_node *np) -+{ -+ struct clk *clk; -+ struct clk_oxnas_pll *plla; -+ -+ plla = kmalloc(sizeof(*plla), GFP_KERNEL); -+ BUG_ON(!plla); -+ -+ plla->syscon = syscon_node_to_regmap(of_get_parent(np)); -+ plla->hw.init = &clk_plla_init; -+ plla->devnode = np; -+ plla->rstc = NULL; -+ clk = clk_register(NULL, &plla->hw); -+ BUG_ON(IS_ERR(clk)); -+ /* mark it as enabled */ -+ clk_prepare_enable(clk); -+ of_clk_add_provider(np, of_clk_src_simple_get, clk); -+} -+CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla); -+ -+void __init oxnas_init_pllb(struct device_node *np) -+{ -+ struct clk *clk; -+ struct clk_oxnas_pll *pllb; -+ -+ pllb = kmalloc(sizeof(*pllb), GFP_KERNEL); -+ BUG_ON(!pllb); -+ -+ pllb->syscon = syscon_node_to_regmap(of_get_parent(np)); -+ pllb->hw.init = &clk_pllb_init; -+ pllb->devnode = np; -+ pllb->rstc = NULL; -+ -+ clk = clk_register(NULL, &pllb->hw); -+ BUG_ON(IS_ERR(clk)); -+ of_clk_add_provider(np, of_clk_src_simple_get, clk); -+} -+CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb); ---- a/arch/arm/boot/dts/ox820.dtsi -+++ b/arch/arm/boot/dts/ox820.dtsi -@@ -61,12 +61,6 @@ - clocks = <&osc>; - }; - -- plla: plla { -- compatible = "fixed-clock"; -- #clock-cells = <0>; -- clock-frequency = <850000000>; -- }; -- - armclk: armclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; -@@ -266,6 +260,19 @@ - compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk"; - #clock-cells = <1>; - }; -+ -+ plla: plla { -+ compatible = "plxtech,nas782x-plla"; -+ #clock-cells = <0>; -+ clocks = <&osc>; -+ }; -+ -+ pllb: pllb { -+ compatible = "plxtech,nas782x-pllb"; -+ #clock-cells = <0>; -+ clocks = <&osc>; -+ resets = <&reset RESET_PLLB>; -+ }; - }; - }; - -@@ -287,6 +294,13 @@ - clocks = <&armclk>; - }; - -+ watchdog@620 { -+ compatible = "mpcore_wdt"; -+ reg = <0x620 0x20>; -+ interrupts = ; -+ clocks = <&armclk>; -+ }; -+ - gic: interrupt-controller@1000 { - compatible = "arm,arm11mp-gic"; - interrupt-controller; diff --git a/target/linux/oxnas/patches-5.10/150-oxnas-restart.patch b/target/linux/oxnas/patches-5.10/150-oxnas-restart.patch deleted file mode 100644 index c5b07fd5a7..0000000000 --- a/target/linux/oxnas/patches-5.10/150-oxnas-restart.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/power/reset/Kconfig -+++ b/drivers/power/reset/Kconfig -@@ -141,6 +141,12 @@ config POWER_RESET_OXNAS - help - Restart support for OXNAS/PLXTECH OX820 SoC. - -+config POWER_RESET_OXNAS -+ bool "OXNAS SoC restart driver" -+ depends on ARCH_OXNAS -+ help -+ Restart support for OXNAS boards. -+ - config POWER_RESET_PIIX4_POWEROFF - tristate "Intel PIIX4 power-off driver" - depends on PCI ---- a/drivers/power/reset/Makefile -+++ b/drivers/power/reset/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_POWER_RESET_QCOM_PON) += qc - obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o - obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o - obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o -+obj-$(CONFIG_POWER_RESET_OXNAS) += oxnas-restart.o - obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o - obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o - obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o diff --git a/target/linux/oxnas/patches-5.10/320-oxnas-phy-pcie.patch b/target/linux/oxnas/patches-5.10/320-oxnas-phy-pcie.patch deleted file mode 100644 index a590151e5c..0000000000 --- a/target/linux/oxnas/patches-5.10/320-oxnas-phy-pcie.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- a/arch/arm/boot/dts/ox820.dtsi -+++ b/arch/arm/boot/dts/ox820.dtsi -@@ -247,6 +247,15 @@ - }; - }; - -+ pcie_phy: pcie-phy@a00000 { -+ compatible = "oxsemi,ox820-pcie-phy"; -+ reg = <0xa00000 0x10>; -+ #phy-cells = <0>; -+ resets = <&reset RESET_PCIEPHY>; -+ reset-names = "phy"; -+ status = "disabled"; -+ }; -+ - sys: sys-ctrl@e00000 { - compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"; - reg = <0xe00000 0x200000>; ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -35,6 +35,13 @@ config PHY_LPC18XX_USB_OTG - This driver is need for USB0 support on LPC18xx/43xx and takes - care of enabling and clock setup. - -+config PHY_OXNAS -+ tristate "Oxford Semi. OX820 PCI-E PHY support" -+ depends on HAS_IOMEM && OF && (ARM || COMPILE_TEST) -+ select GENERIC_PHY -+ help -+ This option enables support for OXNAS OX820 SoC PCIE PHY. -+ - config PHY_PISTACHIO_USB - tristate "IMG Pistachio USB2.0 PHY driver" - depends on MACH_PISTACHIO ---- a/drivers/phy/Makefile -+++ b/drivers/phy/Makefile -@@ -6,6 +6,7 @@ - obj-$(CONFIG_GENERIC_PHY) += phy-core.o - obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o - obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o -+obj-$(CONFIG_PHY_OXNAS) += phy-oxnas-pcie.o - obj-$(CONFIG_PHY_XGENE) += phy-xgene.o - obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o - obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o diff --git a/target/linux/oxnas/patches-5.10/340-oxnas-pcie.patch b/target/linux/oxnas/patches-5.10/340-oxnas-pcie.patch deleted file mode 100644 index 01b5a188c3..0000000000 --- a/target/linux/oxnas/patches-5.10/340-oxnas-pcie.patch +++ /dev/null @@ -1,122 +0,0 @@ ---- a/drivers/pci/controller/Kconfig -+++ b/drivers/pci/controller/Kconfig -@@ -305,6 +305,11 @@ config PCIE_HISI_ERR - Say Y here if you want error handling support - for the PCIe controller's errors on HiSilicon HIP SoCs - -+config PCIE_OXNAS -+ bool "PLX Oxnas PCIe controller" -+ depends on ARCH_OXNAS -+ select PCIEPORTBUS -+ - source "drivers/pci/controller/dwc/Kconfig" - source "drivers/pci/controller/mobiveil/Kconfig" - source "drivers/pci/controller/cadence/Kconfig" ---- a/drivers/pci/controller/Makefile -+++ b/drivers/pci/controller/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rock - obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o - obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o - obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o -+obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o - obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o - obj-$(CONFIG_VMD) += vmd.o - obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o ---- a/arch/arm/boot/dts/ox820.dtsi -+++ b/arch/arm/boot/dts/ox820.dtsi -@@ -289,7 +289,7 @@ - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; -- ranges = <0 0x47000000 0x1000000>; -+ ranges = <0 0x47000000 0x2000>; - - scu: scu@0 { - compatible = "arm,arm11mp-scu"; -@@ -318,5 +318,86 @@ - <0x100 0x500>; - }; - }; -+ -+ pcie0: pcie-controller@47c00000 { -+ compatible = "plxtech,nas782x-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ /* flag & space bus address host address size */ -+ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000 -+ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000 -+ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000 -+ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>; -+ -+ bus-range = <0x00 0x7f>; -+ -+ /* cfg inbound translator */ -+ reg = <0x47c00000 0x1000>, <0x47d00000 0x100>; -+ -+ phys = <&pcie_phy>; -+ phy-names = "pcie-phy"; -+ -+ #interrupt-cells = <1>; -+ /* wild card mask, match all bus address & interrupt specifier */ -+ /* format: bus address mask, interrupt specifier mask */ -+ /* each bit 1 means need match, 0 means ignored when match */ -+ interrupt-map-mask = <0 0 0 0>; -+ /* format: a list of: bus address, interrupt specifier, -+ * parent interrupt controller & specifier */ -+ interrupt-map = <0 0 0 0 &gic 0 19 0x304>; -+ gpios = <&gpio1 12 0>; -+ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>; -+ clock-names = "pcie", "busclk"; -+ resets = <&reset RESET_PCIEA>; -+ reset-names = "pcie"; -+ -+ plxtech,pcie-hcsl-bit = <2>; -+ plxtech,pcie-ctrl-offset = <0x120>; -+ plxtech,pcie-outbound-offset = <0x138>; -+ status = "disabled"; -+ }; -+ -+ pcie1: pcie-controller@47e00000 { -+ compatible = "plxtech,nas782x-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ /* flag & space bus address host address size */ -+ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000 -+ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000 -+ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000 -+ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>; -+ -+ bus-range = <0x80 0xff>; -+ -+ /* cfg inbound translator */ -+ reg = <0x47e00000 0x1000>, <0x47f00000 0x100>; -+ -+ phys = <&pcie_phy>; -+ phy-names = "pcie-phy"; -+ -+ #interrupt-cells = <1>; -+ /* wild card mask, match all bus address & interrupt specifier */ -+ /* format: bus address mask, interrupt specifier mask */ -+ /* each bit 1 means need match, 0 means ignored when match */ -+ interrupt-map-mask = <0 0 0 0>; -+ /* format: a list of: bus address, interrupt specifier, -+ * parent interrupt controller & specifier */ -+ interrupt-map = <0 0 0 0 &gic 0 20 0x304>; -+ -+ /* gpios = <&gpio1 12 0>; */ -+ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>; -+ clock-names = "pcie", "busclk"; -+ resets = <&reset RESET_PCIEB>; -+ reset-names = "pcie"; -+ -+ plxtech,pcie-hcsl-bit = <3>; -+ plxtech,pcie-ctrl-offset = <0x124>; -+ plxtech,pcie-outbound-offset = <0x174>; -+ status = "disabled"; -+ }; - }; - }; diff --git a/target/linux/oxnas/patches-5.10/500-oxnas-sata.patch b/target/linux/oxnas/patches-5.10/500-oxnas-sata.patch deleted file mode 100644 index d3ec2e2d48..0000000000 --- a/target/linux/oxnas/patches-5.10/500-oxnas-sata.patch +++ /dev/null @@ -1,60 +0,0 @@ ---- a/drivers/ata/Kconfig -+++ b/drivers/ata/Kconfig -@@ -568,6 +568,14 @@ config SATA_VITESSE - - If unsure, say N. - -+config SATA_OXNAS -+ tristate "PLXTECH NAS782X SATA support" -+ select SATA_HOST -+ help -+ This option enables support for Nas782x Serial ATA controller. -+ -+ If unsure, say N. -+ - comment "PATA SFF controllers with BMDMA" - - config PATA_ALI ---- a/drivers/ata/Makefile -+++ b/drivers/ata/Makefile -@@ -46,6 +46,7 @@ obj-$(CONFIG_SATA_SVW) += sata_svw.o - obj-$(CONFIG_SATA_ULI) += sata_uli.o - obj-$(CONFIG_SATA_VIA) += sata_via.o - obj-$(CONFIG_SATA_VITESSE) += sata_vsc.o -+obj-$(CONFIG_SATA_OXNAS) += sata_oxnas.o - - # SFF PATA w/ BMDMA - obj-$(CONFIG_PATA_ALI) += pata_ali.o ---- a/arch/arm/boot/dts/ox820.dtsi -+++ b/arch/arm/boot/dts/ox820.dtsi -@@ -399,5 +399,20 @@ - plxtech,pcie-outbound-offset = <0x174>; - status = "disabled"; - }; -+ -+ sata: sata@45900000 { -+ compatible = "plxtech,nas782x-sata"; -+ /* ports dmactl sgdma */ -+ reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>, -+ /* core phy descriptors (optional) */ -+ <0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>; -+ interrupts = ; -+ clocks = <&stdclk CLK_820_SATA>; -+ resets = <&reset RESET_SATA>, <&reset RESET_SATA_LINK>, <&reset RESET_SATA_PHY>; -+ reset-names = "sata", "link", "phy"; -+ nr-ports = <1>; -+ status = "disabled"; -+ }; -+ - }; - }; ---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts -+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts -@@ -111,3 +111,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etha_mdio>; - }; -+ -+&sata { -+ status = "okay"; -+}; diff --git a/target/linux/oxnas/patches-5.10/510-ox820-libata-leds.patch b/target/linux/oxnas/patches-5.10/510-ox820-libata-leds.patch deleted file mode 100644 index 05ae9ba44b..0000000000 --- a/target/linux/oxnas/patches-5.10/510-ox820-libata-leds.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/mach-oxnas/Kconfig -+++ b/arch/arm/mach-oxnas/Kconfig -@@ -2,6 +2,7 @@ - menuconfig ARCH_OXNAS - bool "Oxford Semiconductor OXNAS Family SoCs" - select ARCH_HAS_RESET_CONTROLLER -+ select ARCH_WANT_LIBATA_LEDS - select COMMON_CLK_OXNAS - select GPIOLIB - select MFD_SYSCON diff --git a/target/linux/oxnas/patches-5.10/800-oxnas-ehci.patch b/target/linux/oxnas/patches-5.10/800-oxnas-ehci.patch deleted file mode 100644 index 8b4d943810..0000000000 --- a/target/linux/oxnas/patches-5.10/800-oxnas-ehci.patch +++ /dev/null @@ -1,73 +0,0 @@ ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -350,6 +350,13 @@ config USB_OCTEON_EHCI - USB 2.0 device support. All CN6XXX based chips with USB are - supported. - -+config USB_EHCI_OXNAS -+ tristate "OXNAS EHCI Module" -+ depends on USB_EHCI_HCD && ARCH_OXNAS -+ select USB_EHCI_ROOT_HUB_TT -+ help -+ Enable support for the OX820 SOC's on-chip EHCI controller. -+ - endif # USB_EHCI_HCD - - config USB_OXU210HP_HCD ---- a/drivers/usb/host/Makefile -+++ b/drivers/usb/host/Makefile -@@ -48,6 +48,7 @@ obj-$(CONFIG_USB_EHCI_HCD_SPEAR) += ehci - obj-$(CONFIG_USB_EHCI_HCD_STI) += ehci-st.o - obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o - obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o -+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o - obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o - obj-$(CONFIG_USB_EHCI_BRCMSTB) += ehci-brcm.o - ---- a/arch/arm/boot/dts/ox820.dtsi -+++ b/arch/arm/boot/dts/ox820.dtsi -@@ -106,6 +106,31 @@ - status = "disabled"; - }; - -+ ehci: ehci@40200100 { -+ compatible = "plxtech,nas782x-ehci"; -+ reg = <0x40200100 0xf00>; -+ interrupts = ; -+ clocks = <&stdclk CLK_820_USBMPH>, <&pllb>, <&stdclk CLK_820_REF600>; -+ clock-names = "usb", "refsrc", "phyref"; -+ resets = <&reset RESET_USBHS>, <&reset RESET_USBPHYA>, <&reset RESET_USBPHYB>; -+ reset-names = "host", "phya", "phyb"; -+ oxsemi,sys-ctrl = <&sys>; -+ /* Otherwise ref300 is used, which is derived from sata phy -+ * in that case, usb depends on sata initialization */ -+ /* FIXME: how to make this dependency explicit ? */ -+ oxsemi,ehci_use_pllb; -+ status = "disabled"; -+ -+ ehci_port1: port@1 { -+ reg = <1>; -+ #trigger-source-cells = <0>; -+ }; -+ ehci_port2: port@2 { -+ reg = <2>; -+ #trigger-source-cells = <0>; -+ }; -+ }; -+ - apb-bridge@44000000 { - #address-cells = <1>; - #size-cells = <1>; ---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts -+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts -@@ -105,6 +105,10 @@ - }; - }; - -+&ehci { -+ status = "okay"; -+}; -+ - ða { - status = "okay"; - diff --git a/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch deleted file mode 100644 index 8f56bdbf9c..0000000000 --- a/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001 -From: Adrian Panella -Date: Thu, 9 Mar 2017 09:37:17 +0100 -Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments - -The command-line arguments provided by the boot loader will be -appended to a new device tree property: bootloader-args. -If there is a property "append-rootblock" in DT under /chosen -and a root= option in bootloaders command line it will be parsed -and added to DT bootargs with the form: XX. -Only command line ATAG will be processed, the rest of the ATAGs -sent by bootloader will be ignored. -This is usefull in dual boot systems, to get the current root partition -without afecting the rest of the system. - -Signed-off-by: Adrian Panella ---- - arch/arm/Kconfig | 11 +++++ - arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++- - init/main.c | 16 ++++++++ - 3 files changed, 98 insertions(+), 1 deletion(-) - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1777,6 +1777,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - The command-line arguments provided by the boot loader will be - appended to the the device tree bootargs property. - -+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ bool "Append rootblock parsing bootloader's kernel arguments" -+ help -+ The command-line arguments provided by the boot loader will be -+ appended to a new device tree property: bootloader-args. -+ If there is a property "append-rootblock" in DT under /chosen -+ and a root= option in bootloaders command line it will be parsed -+ and added to DT bootargs with the form: XX. -+ Only command line ATAG will be processed, the rest of the ATAGs -+ sent by bootloader will be ignored. -+ - endchoice - - config CMDLINE ---- a/arch/arm/boot/compressed/atags_to_fdt.c -+++ b/arch/arm/boot/compressed/atags_to_fdt.c -@@ -5,6 +5,8 @@ - - #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) - #define do_extend_cmdline 1 -+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#define do_extend_cmdline 1 - #else - #define do_extend_cmdline 0 - #endif -@@ -69,6 +71,59 @@ static uint32_t get_cell_size(const void - return cell_size; - } - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ -+static char *append_rootblock(char *dest, const char *str, int len, void *fdt) -+{ -+ char *ptr, *end; -+ char *root="root="; -+ int i, l; -+ const char *rootblock; -+ -+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually -+ ptr = str - 1; -+ -+ do { -+ //first find an 'r' at the begining or after a space -+ do { -+ ptr++; -+ ptr = strchr(ptr, 'r'); -+ if(!ptr) return dest; -+ -+ } while (ptr != str && *(ptr-1) != ' '); -+ -+ //then check for the rest -+ for(i = 1; i <= 4; i++) -+ if(*(ptr+i) != *(root+i)) break; -+ -+ } while (i != 5); -+ -+ end = strchr(ptr, ' '); -+ end = end ? (end - 1) : (strchr(ptr, 0) - 1); -+ -+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX ) -+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++); -+ ptr = end + 1; -+ -+ /* if append-rootblock property is set use it to append to command line */ -+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l); -+ if(rootblock != NULL) { -+ if(*dest != ' ') { -+ *dest = ' '; -+ dest++; -+ len++; -+ } -+ if (len + l + i <= COMMAND_LINE_SIZE) { -+ memcpy(dest, rootblock, l); -+ dest += l - 1; -+ memcpy(dest, ptr, i); -+ dest += i; -+ } -+ } -+ return dest; -+} -+#endif -+ - static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) - { - char cmdline[COMMAND_LINE_SIZE]; -@@ -88,12 +143,21 @@ static void merge_fdt_bootargs(void *fdt - - /* and append the ATAG_CMDLINE */ - if (fdt_cmdline) { -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //save original bootloader args -+ //and append ubi.mtd with root partition number to current cmdline -+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline); -+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt); -+ -+#else - len = strlen(fdt_cmdline); - if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { - *ptr++ = ' '; - memcpy(ptr, fdt_cmdline, len); - ptr += len; - } -+#endif - } - *ptr = '\0'; - -@@ -168,7 +232,9 @@ int atags_to_fdt(void *atag_list, void * - else - setprop_string(fdt, "/chosen", "bootargs", - atag->u.cmdline.cmdline); -- } else if (atag->hdr.tag == ATAG_MEM) { -+ } -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ else if (atag->hdr.tag == ATAG_MEM) { - if (memcount >= sizeof(mem_reg_property)/4) - continue; - if (!atag->u.mem.size) -@@ -212,6 +278,10 @@ int atags_to_fdt(void *atag_list, void * - setprop(fdt, "/memory", "reg", mem_reg_property, - 4 * memcount * memsize); - } -+#else -+ -+ } -+#endif - - return fdt_pack(fdt); - } ---- a/init/main.c -+++ b/init/main.c -@@ -110,6 +110,10 @@ - - #include - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#include -+#endif -+ - static int kernel_init(void *); - - extern void init_IRQ(void); -@@ -904,6 +908,18 @@ asmlinkage __visible void __init __no_sa - page_alloc_init(); - - pr_notice("Kernel command line: %s\n", saved_command_line); -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //Show bootloader's original command line for reference -+ if(of_chosen) { -+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL); -+ if(prop) -+ pr_notice("Bootloader command line (ignored): %s\n", prop); -+ else -+ pr_notice("Bootloader command line not present\n"); -+ } -+#endif -+ - /* parameters may set static keys */ - jump_label_init(); - parse_early_param(); diff --git a/target/linux/oxnas/patches-5.10/999-libata-hacks.patch b/target/linux/oxnas/patches-5.10/999-libata-hacks.patch deleted file mode 100644 index 461a1b87f4..0000000000 --- a/target/linux/oxnas/patches-5.10/999-libata-hacks.patch +++ /dev/null @@ -1,57 +0,0 @@ ---- a/drivers/ata/libata-core.c -+++ b/drivers/ata/libata-core.c -@@ -1528,6 +1528,14 @@ unsigned ata_exec_internal_sg(struct ata - return AC_ERR_SYSTEM; - } - -+ if (ap->ops->acquire_hw && !ap->ops->acquire_hw(ap, 0, 0)) { -+ spin_unlock_irqrestore(ap->lock, flags); -+ if (!ap->ops->acquire_hw(ap, 1, (2*HZ))) { -+ return AC_ERR_TIMEOUT; -+ } -+ spin_lock_irqsave(ap->lock, flags); -+ } -+ - /* initialize internal qc */ - qc = __ata_qc_from_tag(ap, ATA_TAG_INTERNAL); - -@@ -4562,6 +4570,9 @@ struct ata_queued_cmd *ata_qc_new_init(s - if (unlikely(ap->pflags & ATA_PFLAG_FROZEN)) - return NULL; - -+ if (ap->ops->qc_new && ap->ops->qc_new(ap)) -+ return NULL; -+ - /* libsas case */ - if (ap->flags & ATA_FLAG_SAS_HOST) { - tag = ata_sas_allocate_tag(ap); -@@ -4607,6 +4618,8 @@ void ata_qc_free(struct ata_queued_cmd * - qc->tag = ATA_TAG_POISON; - if (ap->flags & ATA_FLAG_SAS_HOST) - ata_sas_free_tag(tag, ap); -+ if (ap->ops->qc_free) -+ ap->ops->qc_free(qc); - } - } - ---- a/include/linux/libata.h -+++ b/include/linux/libata.h -@@ -912,6 +912,8 @@ struct ata_port_operations { - enum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *qc); - unsigned int (*qc_issue)(struct ata_queued_cmd *qc); - bool (*qc_fill_rtf)(struct ata_queued_cmd *qc); -+ int (*qc_new)(struct ata_port *ap); -+ void (*qc_free)(struct ata_queued_cmd *qc); - - /* - * Configuration and exception handling -@@ -1002,6 +1004,9 @@ struct ata_port_operations { - void (*phy_reset)(struct ata_port *ap); - void (*eng_timeout)(struct ata_port *ap); - -+ int (*acquire_hw)(struct ata_port *ap, int may_sleep, -+ int timeout_jiffies); -+ - /* - * ->inherits must be the last field and all the preceding - * fields must be pointers. diff --git a/target/linux/pistachio/config-5.10 b/target/linux/pistachio/config-5.10 index 9ac748c4e9..681607f65c 100644 --- a/target/linux/pistachio/config-5.10 +++ b/target/linux/pistachio/config-5.10 @@ -26,6 +26,7 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y CONFIG_CPU_MIPS32_R2=y CONFIG_CPU_MIPSR2=y diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts b/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts index 6e75d1b930..8780b17b80 100644 --- a/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts +++ b/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts @@ -53,9 +53,8 @@ }; &gmac1 { - nvmem-cells = <&macaddr_factory_e000>; + nvmem-cells = <&macaddr_factory_e006>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; &factory { @@ -66,4 +65,8 @@ macaddr_factory_e000: macaddr@e000 { reg = <0xe000 0x6>; }; + + macaddr_factory_e006: macaddr@e006 { + reg = <0xe006 0x6>; + }; }; diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts b/target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts index d7dd4ccd46..212c000942 100644 --- a/target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts +++ b/target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts @@ -58,9 +58,8 @@ }; &gmac1 { - nvmem-cells = <&macaddr_factory_e000>; + nvmem-cells = <&macaddr_factory_e006>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; &factory { @@ -71,4 +70,8 @@ macaddr_factory_e000: macaddr@e000 { reg = <0xe000 0x6>; }; + + macaddr_factory_e006: macaddr@e006 { + reg = <0xe006 0x6>; + }; }; diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts b/target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts index 669340f194..f196432111 100644 --- a/target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts +++ b/target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts @@ -59,9 +59,8 @@ }; &gmac1 { - nvmem-cells = <&macaddr_factory_e000>; + nvmem-cells = <&macaddr_factory_e006>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; &factory { @@ -72,4 +71,8 @@ macaddr_factory_e000: macaddr@e000 { reg = <0xe000 0x6>; }; + + macaddr_factory_e006: macaddr@e006 { + reg = <0xe006 0x6>; + }; }; diff --git a/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi b/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi index 0a48c06019..ff738a5261 100644 --- a/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi +++ b/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi @@ -30,6 +30,11 @@ label = "yellow:power"; gpios = <&gpio 44 GPIO_ACTIVE_LOW>; }; + + wan { + label = "blue:wan"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + }; }; keys { @@ -93,7 +98,7 @@ &state_default { gpio { - groups = "gpio", "wdt", "wled_an"; + groups = "gpio", "refclk", "wdt", "wled_an"; function = "gpio"; }; }; diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk index a41f61ffae..c942d76ddc 100644 --- a/target/linux/ramips/image/mt7621.mk +++ b/target/linux/ramips/image/mt7621.mk @@ -291,6 +291,7 @@ TARGET_DEVICES += asus_rt-ac85p define Device/asus_rt-n56u-b1 $(Device/dsa-migration) + $(Device/uimage-lzma-loader) DEVICE_VENDOR := ASUS DEVICE_MODEL := RT-N56U DEVICE_VARIANT := B1 @@ -1670,6 +1671,8 @@ define Device/raisecom_msg1500-x-00 DEVICE_VENDOR := RAISECOM DEVICE_MODEL := MSG1500 DEVICE_VARIANT := X.00 + DEVICE_ALT0_VENDOR := Nokia + DEVICE_ALT0_MODEL := A-040W-Q DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3 \ kmod-usb-ledtrig-usbport uboot-envtools endef diff --git a/target/linux/ramips/image/rt3883.mk b/target/linux/ramips/image/rt3883.mk index 65f5c55fc0..057090d85f 100644 --- a/target/linux/ramips/image/rt3883.mk +++ b/target/linux/ramips/image/rt3883.mk @@ -19,6 +19,7 @@ endef TARGET_DEVICES += asus_rt-n56u define Device/belkin_f9k1109v1 + $(Device/uimage-lzma-loader) SOC := rt3883 BLOCKSIZE := 64k DEVICE_VENDOR := Belkin @@ -26,7 +27,6 @@ define Device/belkin_f9k1109v1 DEVICE_VARIANT := Version 1.0 DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport IMAGE_SIZE := 7808k - KERNEL := kernel-bin | append-dtb | lzma -d16 | uImage lzma # Stock firmware checks for this uImage image name during upload. UIMAGE_NAME := N750F9K1103VB endef diff --git a/target/linux/ramips/mt7620/config-5.10 b/target/linux/ramips/mt7620/config-5.10 index fb0fd1d30b..4ee113facd 100644 --- a/target/linux/ramips/mt7620/config-5.10 +++ b/target/linux/ramips/mt7620/config-5.10 @@ -20,6 +20,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/mt7620/config-5.15 b/target/linux/ramips/mt7620/config-5.15 index 0f8aca000c..fdca30fecb 100644 --- a/target/linux/ramips/mt7620/config-5.15 +++ b/target/linux/ramips/mt7620/config-5.15 @@ -21,6 +21,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/mt7621/config-5.10 b/target/linux/ramips/mt7621/config-5.10 index b6c7407484..8c077d211d 100644 --- a/target/linux/ramips/mt7621/config-5.10 +++ b/target/linux/ramips/mt7621/config-5.10 @@ -27,6 +27,7 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_CPU_IDLE=y # CONFIG_CPU_IDLE_GOV_LADDER is not set CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/mt7621/config-5.15 b/target/linux/ramips/mt7621/config-5.15 index adda3fef64..1b8a48100d 100644 --- a/target/linux/ramips/mt7621/config-5.15 +++ b/target/linux/ramips/mt7621/config-5.15 @@ -26,6 +26,7 @@ CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds b/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds index 0af01d4393..8a21756225 100644 --- a/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds +++ b/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds @@ -144,6 +144,13 @@ wavlink,wl-wn578a2) ucidef_set_led_switch "lan" "lan" "green:lan" "switch0" "0x8" ucidef_set_led_switch "wan" "wan" "green:wan" "switch0" "0x10" ;; +xiaomi,mi-router-4a-100m|\ +xiaomi,mi-router-4a-100m-intl) + ucidef_set_led_switch "wan" "WAN" "blue:wan" "switch0" "0x01" + ;; +xiaomi,mi-router-4c) + ucidef_set_led_switch "wan" "WAN" "blue:wan" "switch0" "0x02" + ;; zbtlink,zbt-we1226) ucidef_set_led_netdev "wifi_led" "wifi" "green:wlan" "wlan0" ucidef_set_led_switch "lan1" "LAN1" "green:lan1" "switch0" "0x01" diff --git a/target/linux/ramips/mt76x8/config-5.10 b/target/linux/ramips/mt76x8/config-5.10 index 37f0bb8e3e..36922354a9 100644 --- a/target/linux/ramips/mt76x8/config-5.10 +++ b/target/linux/ramips/mt76x8/config-5.10 @@ -20,6 +20,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/mt76x8/config-5.15 b/target/linux/ramips/mt76x8/config-5.15 index 5e44d613df..0734bee16e 100644 --- a/target/linux/ramips/mt76x8/config-5.15 +++ b/target/linux/ramips/mt76x8/config-5.15 @@ -21,6 +21,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/rt288x/config-5.10 b/target/linux/ramips/rt288x/config-5.10 index 3071f8719f..8aff187cb6 100644 --- a/target/linux/ramips/rt288x/config-5.10 +++ b/target/linux/ramips/rt288x/config-5.10 @@ -16,6 +16,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/rt288x/config-5.15 b/target/linux/ramips/rt288x/config-5.15 index 1cf653163b..19a71d67ea 100644 --- a/target/linux/ramips/rt288x/config-5.15 +++ b/target/linux/ramips/rt288x/config-5.15 @@ -17,6 +17,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/rt305x/config-5.10 b/target/linux/ramips/rt305x/config-5.10 index 771f42ab3b..ba36912718 100644 --- a/target/linux/ramips/rt305x/config-5.10 +++ b/target/linux/ramips/rt305x/config-5.10 @@ -18,6 +18,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/rt305x/config-5.15 b/target/linux/ramips/rt305x/config-5.15 index 69835c8b54..2c2fc37a63 100644 --- a/target/linux/ramips/rt305x/config-5.15 +++ b/target/linux/ramips/rt305x/config-5.15 @@ -19,6 +19,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y` CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/rt3883/config-5.10 b/target/linux/ramips/rt3883/config-5.10 index 6e4ad04d90..aaccbddefd 100644 --- a/target/linux/ramips/rt3883/config-5.10 +++ b/target/linux/ramips/rt3883/config-5.10 @@ -17,6 +17,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/rt3883/config-5.15 b/target/linux/ramips/rt3883/config-5.15 index 4dd839be72..70d8797306 100644 --- a/target/linux/ramips/rt3883/config-5.15 +++ b/target/linux/ramips/rt3883/config-5.15 @@ -18,6 +18,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/realtek/dts-5.10/rtl838x.dtsi b/target/linux/realtek/dts-5.10/rtl838x.dtsi index 256efb1c05..64e13e1ff3 100644 --- a/target/linux/realtek/dts-5.10/rtl838x.dtsi +++ b/target/linux/realtek/dts-5.10/rtl838x.dtsi @@ -152,6 +152,16 @@ #size-cells = <0>; }; + timer0: timer@3100 { + compatible = "realtek,rtl8380-timer", "realtek,otto-timer"; + reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>, + <0x3130 0x10>, <0x3140 0x10>; + + interrupt-parent = <&intc>; + interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>; + clocks = <&ccu CLK_LXB>; + }; + uart0: uart@2000 { compatible = "ns16550a"; reg = <0x2000 0x100>; diff --git a/target/linux/realtek/dts-5.10/rtl839x.dtsi b/target/linux/realtek/dts-5.10/rtl839x.dtsi index 78e2454b7e..91d6e17a9e 100644 --- a/target/linux/realtek/dts-5.10/rtl839x.dtsi +++ b/target/linux/realtek/dts-5.10/rtl839x.dtsi @@ -177,6 +177,16 @@ #size-cells = <0>; }; + timer0: timer@3100 { + compatible = "realtek,rtl8390-timer", "realtek,otto-timer"; + reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>, + <0x3130 0x10>, <0x3140 0x10>; + + interrupt-parent = <&intc>; + interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>; + clocks = <&ccu CLK_LXB>; + }; + uart0: uart@2000 { compatible = "ns16550a"; reg = <0x2000 0x100>; diff --git a/target/linux/realtek/files-5.10/Documentation/devicetree/bindings/realtek,otto-timer.yaml b/target/linux/realtek/files-5.10/Documentation/devicetree/bindings/realtek,otto-timer.yaml new file mode 100644 index 0000000000..b508362a72 --- /dev/null +++ b/target/linux/realtek/files-5.10/Documentation/devicetree/bindings/realtek,otto-timer.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/realtek,rtl8300-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek Timer Device Tree Bindings + +maintainers: + - Markus Stockhausen + +description: | + The Realtek SOCs of the RTL83XX and RTL93XX series have at least 5 known + timers with corresponding interrupt lines . Their speed is derived from the + Lexra Bus (LXB) by dividers. Each timer has a block of 4 control registers in + the address range 0xb800xxxx with following start offsets. + + RTL83XX: 0x3100, 0x3110, 0x3120, 0x3130, 0x3140 + RTL93XX: 0x3200, 0x3210, 0x3220, 0x3230, 0x3240 + +properties: + compatible: + items: + - enum: + - realtek,rtl8380-timer + - realtek,rtl8390-timer + - realtek,rtl9300-timer + - const: realtek,otto-timer + + reg: + minItems: 5 + maxItems: 5 + description: + List of timer register addresses. + + interrupts: + minItems: 5 + maxItems: 5 + description: + List of timer interrupts. + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer0: timer@3100 { + compatible = "realtek,rtl8380-timer", "realtek,otto-timer"; + reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>, + <0x3130 0x10>, <0x3140 0x10>; + + interrupt-parent = <&intc>; + interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>; + clocks = <&ccu CLK_LXB>; + }; + - | + timer0: timer@3100 { + compatible = "realtek,rtl8390-timer", "realtek,otto-timer"; + reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>, + <0x3130 0x10>, <0x3140 0x10>; + + interrupt-parent = <&intc>; + interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>; + clocks = <&ccu CLK_LXB>; + }; + - | + timer0: timer@3200 { + compatible = "realtek,rtl9300-timer", "realtek,otto-timer"; + reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, + <0x3230 0x10>, <0x3240 0x10>; + + interrupt-parent = <&intc>; + interrupts = <7 4>, <8 4>, <9 4>, <10 4>, <11 4>; + clocks = <&ccu CLK_LXB>; + }; + +... diff --git a/target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl-otto.c b/target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl-otto.c new file mode 100644 index 0000000000..12eed78653 --- /dev/null +++ b/target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl-otto.c @@ -0,0 +1,298 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include "timer-of.h" + +#define RTTM_DATA 0x0 +#define RTTM_CNT 0x4 +#define RTTM_CTRL 0x8 +#define RTTM_INT 0xc + +#define RTTM_CTRL_ENABLE BIT(28) +#define RTTM_INT_PENDING BIT(16) +#define RTTM_INT_ENABLE BIT(20) + +/* + * The Otto platform provides multiple 28 bit timers/counters with the following + * operating logic. If enabled the timer counts up. Per timer one can set a + * maximum counter value as an end marker. If end marker is reached the timer + * fires an interrupt. If the timer "overflows" by reaching the end marker or + * by adding 1 to 0x0fffffff the counter is reset to 0. When this happens and + * the timer is in operating mode COUNTER it stops. In mode TIMER it will + * continue to count up. + */ + +#define RTTM_CTRL_COUNTER 0 +#define RTTM_CTRL_TIMER BIT(24) + +#define RTTM_BIT_COUNT 28 +#define RTTM_MIN_DELTA 8 +#define RTTM_MAX_DELTA CLOCKSOURCE_MASK(28) + +/* + * Timers are derived from the LXB clock frequency. Usually this is a fixed + * multiple of the 25 MHz oscillator. The 930X SOC is an exception from that. + * Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its + * base. The only meaningful frequencies we can achieve from that are 175.000 + * MHz and 153.125 MHz. The greatest common divisor of all explained possible + * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency. + */ + +#define RTTM_TICKS_PER_SEC 3125000 + +struct rttm_cs { + struct timer_of to; + struct clocksource cs; +}; + +/* + * Simple internal register functions + */ + +static inline void rttm_set_counter(void __iomem *base, unsigned int counter) +{ + iowrite32(counter, base + RTTM_CNT); +} + +static inline unsigned int rttm_get_counter(void __iomem *base) +{ + return ioread32(base + RTTM_CNT); +} + +static inline void rttm_set_period(void __iomem *base, unsigned int period) +{ + iowrite32(period, base + RTTM_DATA); +} + +static inline void rttm_disable_timer(void __iomem *base) +{ + iowrite32(0, base + RTTM_CTRL); +} + +static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor) +{ + iowrite32(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL); +} + +static inline void rttm_ack_irq(void __iomem *base) +{ + iowrite32(ioread32(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT); +} + +static inline void rttm_enable_irq(void __iomem *base) +{ + iowrite32(RTTM_INT_ENABLE, base + RTTM_INT); +} + +static inline void rttm_disable_irq(void __iomem *base) +{ + iowrite32(0, base + RTTM_INT); +} + +/* + * Aggregated control functions for kernel clock framework + */ + +#define RTTM_DEBUG(base) \ + pr_debug("------------- %s %d %08x\n", __func__, \ + smp_processor_id(), (u32)base) + +static irqreturn_t rttm_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *clkevt = dev_id; + struct timer_of *to = to_timer_of(clkevt); + + rttm_ack_irq(to->of_base.base); + RTTM_DEBUG(to->of_base.base); + clkevt->event_handler(clkevt); + + return IRQ_HANDLED; +} + +static void rttm_stop_timer(void __iomem *base) +{ + rttm_disable_timer(base); + rttm_ack_irq(base); +} + +static void rttm_start_timer(struct timer_of *to, u32 mode) +{ + rttm_set_counter(to->of_base.base, 0); + rttm_enable_timer(to->of_base.base, mode, to->of_clk.rate / RTTM_TICKS_PER_SEC); +} + +static int rttm_next_event(unsigned long delta, struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + RTTM_DEBUG(to->of_base.base); + rttm_stop_timer(to->of_base.base); + rttm_set_period(to->of_base.base, delta); + rttm_start_timer(to, RTTM_CTRL_COUNTER); + + return 0; +} + +static int rttm_state_oneshot(struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + RTTM_DEBUG(to->of_base.base); + rttm_stop_timer(to->of_base.base); + rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ); + rttm_start_timer(to, RTTM_CTRL_COUNTER); + + return 0; +} + +static int rttm_state_periodic(struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + RTTM_DEBUG(to->of_base.base); + rttm_stop_timer(to->of_base.base); + rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ); + rttm_start_timer(to, RTTM_CTRL_TIMER); + + return 0; +} + +static int rttm_state_shutdown(struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + RTTM_DEBUG(to->of_base.base); + rttm_stop_timer(to->of_base.base); + + return 0; +} + +static void rttm_setup_timer(void __iomem *base) +{ + RTTM_DEBUG(base); + rttm_stop_timer(base); + rttm_set_period(base, 0); +} + +static u64 rttm_read_clocksource(struct clocksource *cs) +{ + struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs); + + return (u64)rttm_get_counter(rcs->to.of_base.base); +} + +/* + * Module initialization part. + */ + +static DEFINE_PER_CPU(struct timer_of, rttm_to) = { + .flags = TIMER_OF_BASE | TIMER_OF_CLOCK | TIMER_OF_IRQ, + .of_irq = { + .flags = IRQF_PERCPU | IRQF_TIMER, + .handler = rttm_timer_interrupt, + }, + .clkevt = { + .rating = 400, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_state_periodic = rttm_state_periodic, + .set_state_shutdown = rttm_state_shutdown, + .set_state_oneshot = rttm_state_oneshot, + .set_next_event = rttm_next_event + }, +}; + +static int rttm_enable_clocksource(struct clocksource *cs) +{ + struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs); + + rttm_disable_irq(rcs->to.of_base.base); + rttm_setup_timer(rcs->to.of_base.base); + rttm_enable_timer(rcs->to.of_base.base, RTTM_CTRL_TIMER, + rcs->to.of_clk.rate / RTTM_TICKS_PER_SEC); + + return 0; +} + +struct rttm_cs rttm_cs = { + .to = { + .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, + }, + .cs = { + .name = "realtek_otto_timer", + .rating = 400, + .mask = CLOCKSOURCE_MASK(RTTM_BIT_COUNT), + .read = rttm_read_clocksource, + .enable = rttm_enable_clocksource + } +}; + +static u64 notrace rttm_read_clock(void) +{ + return (u64)rttm_get_counter(rttm_cs.to.of_base.base); +} + +static int rttm_cpu_starting(unsigned int cpu) +{ + struct timer_of *to = per_cpu_ptr(&rttm_to, cpu); + + RTTM_DEBUG(to->of_base.base); + to->clkevt.cpumask = cpumask_of(cpu); + irq_set_affinity(to->of_irq.irq, to->clkevt.cpumask); + clockevents_config_and_register(&to->clkevt, RTTM_TICKS_PER_SEC, + RTTM_MIN_DELTA, RTTM_MAX_DELTA); + rttm_enable_irq(to->of_base.base); + + return 0; +} + +static int __init rttm_probe(struct device_node *np) +{ + int cpu, cpu_rollback; + struct timer_of *to; + int clkidx = num_possible_cpus(); +/* + * Use the first n timers as per CPU clock event generators + */ + for_each_possible_cpu(cpu) { + to = per_cpu_ptr(&rttm_to, cpu); + to->of_irq.index = to->of_base.index = cpu; + if (timer_of_init(np, to)) { + pr_err("%s: setup of timer %d failed\n", __func__, cpu); + goto rollback; + } + rttm_setup_timer(to->of_base.base); + } +/* + * Activate the n'th+1 timer as a stable CPU clocksource. + */ + to = &rttm_cs.to; + to->of_base.index = clkidx; + timer_of_init(np, to); + if (rttm_cs.to.of_base.base && rttm_cs.to.of_clk.rate) { + clocksource_register_hz(&rttm_cs.cs, RTTM_TICKS_PER_SEC); + sched_clock_register(rttm_read_clock, RTTM_BIT_COUNT, RTTM_TICKS_PER_SEC); + } else + pr_err("%s: setup of timer %d as clocksoure failed", __func__, clkidx); + + return cpuhp_setup_state(CPUHP_AP_REALTEK_TIMER_STARTING, + "timer/realtek:online", + rttm_cpu_starting, NULL); +rollback: + pr_err("%s: timer registration failed\n", __func__); + for_each_possible_cpu(cpu_rollback) { + if (cpu_rollback == cpu) + break; + to = per_cpu_ptr(&rttm_to, cpu_rollback); + timer_of_cleanup(to); + } + + return -EINVAL; +} + +TIMER_OF_DECLARE(otto_timer, "realtek,otto-timer", rttm_probe); diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c index 21f00096e5..6dd064c95b 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c @@ -270,6 +270,109 @@ static const struct file_operations drop_counter_fops = { .read = drop_counter_read, }; +static void l2_table_print_entry(struct seq_file *m, struct rtl838x_switch_priv *priv, + struct rtl838x_l2_entry *e) +{ + u64 portmask; + int i; + + if (e->type == L2_UNICAST) { + seq_puts(m, "L2_UNICAST\n"); + + seq_printf(m, " mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n", + e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5], + e->vid, e->rvid); + + seq_printf(m, " port %d age %d", e->port, e->age); + if (e->is_static) + seq_puts(m, " static"); + if (e->block_da) + seq_puts(m, " block_da"); + if (e->block_sa) + seq_puts(m, " block_sa"); + if (e->suspended) + seq_puts(m, " suspended"); + if (e->next_hop) + seq_printf(m, " next_hop route_id %u", e->nh_route_id); + seq_puts(m, "\n"); + + } else { + if (e->type == L2_MULTICAST) { + seq_puts(m, "L2_MULTICAST\n"); + + seq_printf(m, " mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n", + e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5], + e->vid, e->rvid); + } + + if (e->type == IP4_MULTICAST || e->type == IP6_MULTICAST) { + seq_puts(m, (e->type == IP4_MULTICAST) ? + "IP4_MULTICAST\n" : "IP6_MULTICAST\n"); + + seq_printf(m, " gip %08x sip %08x vid %u rvid %u\n", + e->mc_gip, e->mc_sip, e->vid, e->rvid); + } + + portmask = priv->r->read_mcast_pmask(e->mc_portmask_index); + seq_printf(m, " index %u ports", e->mc_portmask_index); + for (i = 0; i < 64; i++) { + if (portmask & BIT_ULL(i)) + seq_printf(m, " %d", i); + } + seq_puts(m, "\n"); + } + + seq_puts(m, "\n"); +} + +static int l2_table_show(struct seq_file *m, void *v) +{ + struct rtl838x_switch_priv *priv = m->private; + struct rtl838x_l2_entry e; + int i, bucket, index; + + mutex_lock(&priv->reg_mutex); + + for (i = 0; i < priv->fib_entries; i++) { + bucket = i >> 2; + index = i & 0x3; + priv->r->read_l2_entry_using_hash(bucket, index, &e); + + if (!e.valid) + continue; + + seq_printf(m, "Hash table bucket %d index %d ", bucket, index); + l2_table_print_entry(m, priv, &e); + } + + for (i = 0; i < 64; i++) { + priv->r->read_cam(i, &e); + + if (!e.valid) + continue; + + seq_printf(m, "CAM index %d ", i); + l2_table_print_entry(m, priv, &e); + } + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int l2_table_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, l2_table_show, inode->i_private); +} + +static const struct file_operations l2_table_fops = { + .owner = THIS_MODULE, + .open = l2_table_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + static ssize_t age_out_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos) { @@ -608,6 +711,8 @@ void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv) debugfs_create_file("drop_counters", 0400, rtl838x_dir, priv, &drop_counter_fops); + debugfs_create_file("l2_table", 0400, rtl838x_dir, priv, &l2_table_fops); + return; err: rtl838x_dbgfs_cleanup(priv); @@ -625,4 +730,6 @@ void rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv) priv->dbgfs_dir = dbg_dir; debugfs_create_file("drop_counters", 0400, dbg_dir, priv, &drop_counter_fops); + + debugfs_create_file("l2_table", 0400, dbg_dir, priv, &l2_table_fops); } diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c index 3ff1a96ed6..10e6103f0d 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c @@ -1535,28 +1535,6 @@ static int rtl83xx_vlan_del(struct dsa_switch *ds, int port, return 0; } -static void dump_l2_entry(struct rtl838x_l2_entry *e) -{ - pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n", - e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5], - e->vid, e->rvid, e->port, e->valid); - - if (e->type != L2_MULTICAST) { - pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n", - e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da); - pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n", - e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk); - } - if (e->type == L2_MULTICAST) - pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index); - if (e->is_ip_mc || e->is_ipv6_mc) - pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n", - e->mc_portmask_index, e->mc_gip, e->mc_sip); - pr_info(" stack_dev: %d\n", e->stack_dev); - if (e->next_hop) - pr_info(" nh_route_id: %d\n", e->nh_route_id); -} - static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac) { e->is_ip_mc = e->is_ipv6_mc = false; @@ -1685,15 +1663,14 @@ static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port, int err = 0, idx; u64 seed = priv->r->l2_hash_seed(mac, vid); - pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid); + pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid); mutex_lock(&priv->reg_mutex); idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e); if (idx >= 0) { - pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3); + pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3); e.valid = false; - dump_l2_entry(&e); priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); goto out; } @@ -1718,8 +1695,6 @@ static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port, struct rtl838x_l2_entry e; struct rtl838x_switch_priv *priv = ds->priv; int i; - u32 fid, pkey; - u64 mac; mutex_lock(&priv->reg_mutex); @@ -1729,30 +1704,8 @@ static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port, if (!e.valid) continue; - if (e.port == port || e.port == RTL930X_PORT_IGNORE) { - u64 seed; - u32 key; - - fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff); - mac = ether_addr_to_u64(&e.mac[0]); - pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid)); - fid = (pkey & 0x3ff) | (fid & ~0x3ff); - pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n", - i, i >> 2, i & 0x3, mac, fid, e.rvid); - dump_l2_entry(&e); - seed = priv->r->l2_hash_seed(mac, e.rvid); - key = priv->r->l2_hash_key(priv, seed); - pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key); + if (e.port == port || e.port == RTL930X_PORT_IGNORE) cb(e.mac, e.vid, e.is_static, data); - } - if (e.type == L2_MULTICAST) { - u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index); - - if (portmask & BIT_ULL(port)) { - dump_l2_entry(&e); - pr_info(" PM: %016llx\n", portmask); - } - } } for (i = 0; i < 64; i++) { @@ -1876,7 +1829,6 @@ int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port, portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port); if (!portmask) { e.valid = false; - // dump_l2_entry(&e); priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); } goto out; @@ -1889,7 +1841,6 @@ int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port, portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port); if (!portmask) { e.valid = false; - // dump_l2_entry(&e); priv->r->write_cam(idx, &e); } goto out; diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c index 199ba347da..29912257e8 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c @@ -630,9 +630,23 @@ int rtl8390_sds_power(int mac, int val) return 0; } +static int rtl839x_smi_wait_op(int timeout) +{ + int ret = 0; + u32 val; + + ret = readx_poll_timeout(sw_r32, RTL839X_PHYREG_ACCESS_CTRL, + val, !(val & 0x1), 20, timeout); + if (ret) + pr_err("%s: timeout\n", __func__); + + return ret; +} + int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val) { u32 v; + int err = 0; if (port > 63 || page > 4095 || reg > 31) return -ENOTSUPP; @@ -652,13 +666,15 @@ int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val) v |= 1; sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - do { - } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1); + err = rtl839x_smi_wait_op(100000); + if (err) + goto errout; *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff; +errout: mutex_unlock(&smi_lock); - return 0; + return err; } int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val) @@ -689,12 +705,14 @@ int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val) v |= BIT(3) | 1; /* Write operation and execute */ sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - do { - } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1); + err = rtl839x_smi_wait_op(100000); + if (err) + goto errout; if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2) err = -EIO; +errout: mutex_unlock(&smi_lock); return err; } @@ -722,15 +740,16 @@ int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) v = BIT(2) | BIT(0); // MMD-access | EXEC sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - do { - v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL); - } while (v & BIT(0)); + err = rtl839x_smi_wait_op(100000); + if (err) + goto errout; + // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly *val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff); pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err); +errout: mutex_unlock(&smi_lock); - return err; } @@ -760,11 +779,13 @@ int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) v = BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - do { - v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL); - } while (v & BIT(0)); + err = rtl839x_smi_wait_op(100000); + if (err) + goto errout; pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err); + +errout: mutex_unlock(&smi_lock); return err; } diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c index cd93e4bc8e..e89d75d4b9 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c @@ -579,22 +579,6 @@ static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e) rtl_table_release(q); } -static void dump_l2_entry(struct rtl838x_l2_entry *e) -{ - pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n", - e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5], - e->vid, e->rvid, e->port, e->valid); - pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n", - e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da); - pr_info(" block_sa: %d, suspended: %d, next_hop: %d, age: %d, is_trunk: %d, trunk: %d\n", - e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk); - if (e->is_ip_mc || e->is_ipv6_mc) - pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n", - e->mc_portmask_index, e->mc_gip, e->mc_sip); - pr_info(" stac_dev: %d, nh_route_id: %d, port: %d, dev_id\n", - e->stack_dev, e->nh_route_id, e->port); -} - static u64 rtl930x_read_mcast_pmask(int idx) { u32 portmask; diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c index d497b4cc8c..f5424bbfa3 100644 --- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c @@ -1030,8 +1030,32 @@ static int rtl838x_eth_stop(struct net_device *ndev) return 0; } +static void rtl838x_eth_set_multicast_list(struct net_device *ndev) +{ + /* + * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + * CTRL_0_FULL = GENMASK(21, 0) = 0x3FFFFF + */ + if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { + sw_w32(0x0, RTL838X_RMA_CTRL_0); + sw_w32(0x0, RTL838X_RMA_CTRL_1); + } + if (ndev->flags & IFF_ALLMULTI) + sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0); + if (ndev->flags & IFF_PROMISC) { + sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0); + sw_w32(0x7fff, RTL838X_RMA_CTRL_1); + } +} + static void rtl839x_eth_set_multicast_list(struct net_device *ndev) { + /* + * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC + * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00 + * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) + */ if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { sw_w32(0x0, RTL839X_RMA_CTRL_0); sw_w32(0x0, RTL839X_RMA_CTRL_1); @@ -1039,73 +1063,54 @@ static void rtl839x_eth_set_multicast_list(struct net_device *ndev) sw_w32(0x0, RTL839X_RMA_CTRL_3); } if (ndev->flags & IFF_ALLMULTI) { - sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0); - sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1); - sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2); + sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0); + sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1); + sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2); } if (ndev->flags & IFF_PROMISC) { - sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0); - sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1); - sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2); + sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0); + sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1); + sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2); sw_w32(0x3ff, RTL839X_RMA_CTRL_3); } } -static void rtl838x_eth_set_multicast_list(struct net_device *ndev) -{ - struct rtl838x_eth_priv *priv = netdev_priv(ndev); - - if (priv->family_id == RTL8390_FAMILY_ID) - return rtl839x_eth_set_multicast_list(ndev); - - if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { - sw_w32(0x0, RTL838X_RMA_CTRL_0); - sw_w32(0x0, RTL838X_RMA_CTRL_1); - } - if (ndev->flags & IFF_ALLMULTI) - sw_w32(0x1fffff, RTL838X_RMA_CTRL_0); - if (ndev->flags & IFF_PROMISC) { - sw_w32(0x1fffff, RTL838X_RMA_CTRL_0); - sw_w32(0x7fff, RTL838X_RMA_CTRL_1); - } -} - static void rtl930x_eth_set_multicast_list(struct net_device *ndev) { - if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { + /* + * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC + * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00 + * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) + */ + if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) { + sw_w32(GENMASK(31, 2), RTL930X_RMA_CTRL_0); + sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_1); + sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_2); + } else { sw_w32(0x0, RTL930X_RMA_CTRL_0); sw_w32(0x0, RTL930X_RMA_CTRL_1); sw_w32(0x0, RTL930X_RMA_CTRL_2); } - if (ndev->flags & IFF_ALLMULTI) { - sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0); - sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1); - sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2); - } - if (ndev->flags & IFF_PROMISC) { - sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0); - sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1); - sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2); - } } static void rtl931x_eth_set_multicast_list(struct net_device *ndev) { - if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { + /* + * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC + * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00. + * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) + */ + if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) { + sw_w32(GENMASK(31, 2), RTL931X_RMA_CTRL_0); + sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_1); + sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_2); + } else { sw_w32(0x0, RTL931X_RMA_CTRL_0); sw_w32(0x0, RTL931X_RMA_CTRL_1); sw_w32(0x0, RTL931X_RMA_CTRL_2); } - if (ndev->flags & IFF_ALLMULTI) { - sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0); - sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1); - sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2); - } - if (ndev->flags & IFF_PROMISC) { - sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0); - sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1); - sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2); - } } static void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue) diff --git a/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch b/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch index 591b157d40..eaf03c74f9 100644 --- a/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch +++ b/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch @@ -25,7 +25,7 @@ Submitted-by: Birger Koblitz platform-$(CONFIG_SGI_IP28) += sgi-ip22/ --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -1037,8 +1037,62 @@ config NLM_XLP_BOARD +@@ -1037,8 +1037,58 @@ config NLM_XLP_BOARD This board is based on Netlogic XLP Processor. Say Y here if you have a XLP based board. @@ -54,16 +54,12 @@ Submitted-by: Birger Koblitz + bool "Realtek RTL838X based platforms" + depends on RTL83XX + select CPU_SUPPORTS_CPUFREQ -+ select CSRC_R4K -+ select CEVT_R4K + select MIPS_EXTERNAL_TIMER + +config RTL839X + bool "Realtek RTL839X based platforms" + depends on RTL83XX + select CPU_SUPPORTS_CPUFREQ -+ select CSRC_R4K -+ select CEVT_R4K + select MIPS_EXTERNAL_TIMER + select SYS_SUPPORTS_MULTITHREADING + diff --git a/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch b/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch new file mode 100644 index 0000000000..8b17ddaef0 --- /dev/null +++ b/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch @@ -0,0 +1,40 @@ +--- a/drivers/clocksource/Kconfig ++++ b/drivers/clocksource/Kconfig +@@ -127,6 +127,17 @@ config RDA_TIMER + help + Enables the support for the RDA Micro timer driver. + ++config REALTEK_OTTO_TIMER ++ bool "Clocksource/timer for the Realtek Otto platform" ++ select COMMON_CLK ++ select TIMER_OF ++ help ++ This driver adds support for the timers found in the Realtek RTL83xx ++ and RTL93xx SoCs series. This includes chips such as RTL8380, RTL8381 ++ and RTL832, as well as chips from the RTL839x series, such as RTL8390 ++ RT8391, RTL8392, RTL8393 and RTL8396 and chips of the RTL930x series ++ such as RTL9301, RTL9302 or RTL9303. ++ + config SUN4I_TIMER + bool "Sun4i timer driver" if COMPILE_TEST + depends on HAS_IOMEM +--- a/drivers/clocksource/Makefile ++++ b/drivers/clocksource/Makefile +@@ -63,6 +63,7 @@ obj-$(CONFIG_MILBEAUT_TIMER) += timer-mi + obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o + obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o + obj-$(CONFIG_RDA_TIMER) += timer-rda.o ++obj-$(CONFIG_REALTEK_OTTO_TIMER) += timer-rtl-otto.o + + obj-$(CONFIG_ARC_TIMERS) += arc_timer.o + obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o +--- a/include/linux/cpuhotplug.h ++++ b/include/linux/cpuhotplug.h +@@ -133,6 +133,7 @@ enum cpuhp_state { + CPUHP_AP_MARCO_TIMER_STARTING, + CPUHP_AP_MIPS_GIC_TIMER_STARTING, + CPUHP_AP_ARC_TIMER_STARTING, ++ CPUHP_AP_REALTEK_TIMER_STARTING, + CPUHP_AP_RISCV_TIMER_STARTING, + CPUHP_AP_CLINT_TIMER_STARTING, + CPUHP_AP_CSKY_TIMER_STARTING, diff --git a/target/linux/realtek/rtl838x/config-5.10 b/target/linux/realtek/rtl838x/config-5.10 index c45f10dee0..d69345e301 100644 --- a/target/linux/realtek/rtl838x/config-5.10 +++ b/target/linux/realtek/rtl838x/config-5.10 @@ -7,8 +7,8 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BMIPS_CPUFREQ is not set -CONFIG_CEVT_R4K=y -CONFIG_CEVT_RTL9300=y +# CONFIG_CEVT_R4K is not set +# CONFIG_CEVT_RTL9300 is not set CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y @@ -51,7 +51,6 @@ CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_DMA_NONCOHERENT=y CONFIG_DTC=y @@ -187,6 +186,7 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_POWER_RESET_SYSCON=y CONFIG_RATIONAL=y +CONFIG_REALTEK_OTTO_TIMER=y CONFIG_REALTEK_OTTO_WDT=y CONFIG_REALTEK_PHY=y CONFIG_REALTEK_SOC_PHY=y diff --git a/target/linux/realtek/rtl839x/config-5.10 b/target/linux/realtek/rtl839x/config-5.10 index c685a3f24b..57eded97fc 100644 --- a/target/linux/realtek/rtl839x/config-5.10 +++ b/target/linux/realtek/rtl839x/config-5.10 @@ -7,10 +7,7 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BMIPS_CPUFREQ is not set -CONFIG_CEVT_R4K=y -CONFIG_CEVT_RTL9300=y CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_BOSTON=y @@ -53,7 +50,6 @@ CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_DMA_NONCOHERENT=y CONFIG_DTC=y @@ -185,6 +181,7 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_POWER_RESET_SYSCON=y CONFIG_RATIONAL=y +CONFIG_REALTEK_OTTO_TIMER=y CONFIG_REALTEK_OTTO_WDT=y CONFIG_REALTEK_PHY=y CONFIG_REALTEK_SOC_PHY=y diff --git a/target/linux/realtek/rtl930x/config-5.10 b/target/linux/realtek/rtl930x/config-5.10 index 9984533c06..3b2b327f08 100644 --- a/target/linux/realtek/rtl930x/config-5.10 +++ b/target/linux/realtek/rtl930x/config-5.10 @@ -171,6 +171,7 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_POWER_RESET_SYSCON=y CONFIG_RATIONAL=y +# CONFIG_REALTEK_OTTO_TIMER is not set CONFIG_REALTEK_OTTO_WDT=y CONFIG_REALTEK_PHY=y CONFIG_REALTEK_SOC_PHY=y diff --git a/target/linux/realtek/rtl931x/config-5.10 b/target/linux/realtek/rtl931x/config-5.10 index cc0fd34b38..567421c8d4 100644 --- a/target/linux/realtek/rtl931x/config-5.10 +++ b/target/linux/realtek/rtl931x/config-5.10 @@ -169,6 +169,7 @@ CONFIG_PINCTRL=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_RATIONAL=y +# CONFIG_REALTEK_OTTO_TIMER is not set # CONFIG_REALTEK_PHY is not set CONFIG_REALTEK_SOC_PHY=y CONFIG_REGMAP=y diff --git a/target/linux/rockchip/armv8/config-5.10 b/target/linux/rockchip/armv8/config-5.10 new file mode 100644 index 0000000000..25e32145d3 --- /dev/null +++ b/target/linux/rockchip/armv8/config-5.10 @@ -0,0 +1,653 @@ +CONFIG_64BIT=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=33 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARC_EMAC_CORE=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_CNP=y +CONFIG_ARM64_CRYPTO=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_845719=y +CONFIG_ARM64_ERRATUM_858921=y +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_MODULE_PLTS=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PAN=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PTR_AUTH=y +CONFIG_ARM64_RAS_EXTN=y +CONFIG_ARM64_SVE=y +# CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_UAO=y +CONFIG_ARM64_VA_BITS=48 +# CONFIG_ARM64_VA_BITS_39 is not set +CONFIG_ARM64_VA_BITS_48=y +CONFIG_ARM64_VHE=y +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +# CONFIG_ARMV8_DEPRECATED is not set +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +CONFIG_ARM_MHU=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set +# CONFIG_ARM_SCMI_PROTOCOL is not set +CONFIG_ARM_SCPI_CPUFREQ=y +CONFIG_ARM_SCPI_POWER_DOMAIN=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y +# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set +CONFIG_ARM_SMMU_V3=y +# CONFIG_ARM_SMMU_V3_SVA is not set +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NVME=y +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLOCK_COMPAT=y +CONFIG_BRCMSTB_GISB_ARB=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_CHARGER_BQ25980 is not set +CONFIG_CHARGER_GPIO=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLK_PX30=y +CONFIG_CLK_RK3036=y +CONFIG_CLK_RK312X=y +CONFIG_CLK_RK3188=y +CONFIG_CLK_RK322X=y +CONFIG_CLK_RK3308=y +CONFIG_CLK_RK3328=y +CONFIG_CLK_RK3368=y +CONFIG_CLK_RK3399=y +CONFIG_CLK_RV110X=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=5 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_ROCKCHIP=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMPAT=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTIG_ALLOC=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRASH_CORE=y +CONFIG_CRASH_DUMP=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC_T10DIF=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_BLAKE2S=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y +CONFIG_CRYPTO_CRYPTD=y +# CONFIG_CRYPTO_DEV_ROCKCHIP is not set +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_SIMD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DEVMEM=y +# CONFIG_DEVPORT is not set +CONFIG_DMADEVICES=y +CONFIG_DMA_CMA=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DNOTIFY=y +# CONFIG_DRM_ROCKCHIP is not set +CONFIG_DTC=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DWMAC_DWC_QOS_ETH=y +CONFIG_DWMAC_GENERIC=y +CONFIG_DWMAC_ROCKCHIP=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_EMAC_ROCKCHIP=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_ENERGY_MODEL=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXTCON=y +CONFIG_F2FS_FS=y +CONFIG_FANOTIFY=y +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +# CONFIG_FLATMEM_MANUAL is not set +# CONFIG_FORTIFY_SOURCE is not set +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_HANDLE_DOMAIN_IRQ=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +# CONFIG_HISI_HIKEY_USB is not set +CONFIG_HOLES_IN_ZONE=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_PCIE is not set +# CONFIG_HOTPLUG_PCI_SHPC is not set +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HWMON=y +CONFIG_HWSPINLOCK=y +CONFIG_HW_CONSOLE=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_RK3X=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INDIRECT_PIO=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_MATRIXKMAP=y +# CONFIG_INPUT_RK805_PWRKEY is not set +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DMA=y +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_IO_PGTABLE=y +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +CONFIG_IOMMU_SUPPORT=y +# CONFIG_IO_STRICT_DEVMEM is not set +CONFIG_IO_URING=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_IOMMU=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS=y +CONFIG_KEXEC_CORE=y +CONFIG_KEXEC_FILE=y +CONFIG_KSM=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_LP50XX is not set +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_LIBCRC32C=y +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +CONFIG_MANDATORY_FILE_LOCKING=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=y +CONFIG_MDIO_BUS_MUX_GPIO=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_MDIO_DEVICE=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_KHADAS_MCU is not set +CONFIG_MFD_RK808=y +# CONFIG_MFD_ROHM_BD71828 is not set +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_CQHCI=y +CONFIG_MMC_DW=y +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_K3 is not set +# CONFIG_MMC_DW_PCI is not set +CONFIG_MMC_DW_PLTFM=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_DWCMSHC=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MQ_IOSCHED_DEADLINE=y +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NLS=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=256 +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_NVME_CORE=y +# CONFIG_NVME_HWMON is not set +# CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_TCP is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_RESOLVE=y +CONFIG_OLD_SIGSUSPEND3=y +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_PME=y +CONFIG_PCIE_ROCKCHIP=y +CONFIG_PCIE_ROCKCHIP_HOST=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_STUB=y +CONFIG_PCS_XPCS=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_ROCKCHIP_DP=y +# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set +CONFIG_PHY_ROCKCHIP_EMMC=y +# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set +# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_PCIE=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PHY_ROCKCHIP_USB=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_RK805 is not set +CONFIG_PINCTRL_ROCKCHIP=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PL330_DMA=y +CONFIG_PLATFORM_MHU=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_DEVFREQ=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_OPP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PREEMPT=y +CONFIG_PREEMPTION=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +CONFIG_PRINTK_TIME=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_VMCORE=y +CONFIG_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_PWM_SYSFS=y +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_RAID_ATTRS=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_MODULE_REGION_FULL=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RAVE_SP_CORE is not set +CONFIG_RCU_TRACE=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK808=y +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RTMV20 is not set +CONFIG_RELOCATABLE=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_ROCKCHIP_GRF=y +CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_ROCKCHIP_IOMMU=y +CONFIG_ROCKCHIP_MBOX=y +# CONFIG_ROCKCHIP_OTP is not set +CONFIG_ROCKCHIP_PHY=y +CONFIG_ROCKCHIP_PM_DOMAINS=y +# CONFIG_ROCKCHIP_SARADC is not set +CONFIG_ROCKCHIP_THERMAL=y +CONFIG_ROCKCHIP_TIMER=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPS=y +CONFIG_RSEQ=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_RK808=y +# CONFIG_RTC_DRV_RV3032 is not set +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_NVMEM=y +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_MC=y +CONFIG_SCSI=y +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_PROC_FS is not set +CONFIG_SCSI_SAS_ATTRS=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SENSORS_ARM_SCPI=y +# CONFIG_SENSORS_MR75203 is not set +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIO=y +CONFIG_SERIO_AMBAKMI=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SG_POOL=y +CONFIG_SIMPLE_PM_BUS=y +CONFIG_SLUB_DEBUG=y +CONFIG_SMP=y +# CONFIG_SND_SOC_ROCKCHIP is not set +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_ROCKCHIP=y +CONFIG_SPI_SPIDEV=y +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SRAM=y +CONFIG_SRCU=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STRICT_DEVMEM=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_SWAP is not set +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYNC_FILE=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +# CONFIG_TEXTSEARCH is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TRACE_CLOCK=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_TYPEC=y +# CONFIG_TYPEC_DP_ALTMODE is not set +CONFIG_TYPEC_FUSB302=y +# CONFIG_TYPEC_HD3SS3220 is not set +# CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_STUSB160X is not set +# CONFIG_TYPEC_TCPCI is not set +CONFIG_TYPEC_TCPM=y +# CONFIG_TYPEC_TPS6598X is not set +# CONFIG_UACCE is not set +# CONFIG_UCLAMP_TASK is not set +# CONFIG_UEVENT_HELPER is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_HOST=y +CONFIG_USB_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_HID=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_PHY=y +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_BUS=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +# CONFIG_VIRTIO_MENU is not set +CONFIG_VMAP_STACK=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_WATCHDOG is not set +CONFIG_XARRAY_MULTI=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/rockchip/armv8/config-5.15 b/target/linux/rockchip/armv8/config-5.15 index 76c54b019a..275fa201a8 100644 --- a/target/linux/rockchip/armv8/config-5.15 +++ b/target/linux/rockchip/armv8/config-5.15 @@ -152,6 +152,7 @@ CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_ISOLATION=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y diff --git a/target/linux/sunxi/cortexa53/config-5.10 b/target/linux/sunxi/cortexa53/config-5.10 index 25dc0ade6b..d58dba543e 100644 --- a/target/linux/sunxi/cortexa53/config-5.10 +++ b/target/linux/sunxi/cortexa53/config-5.10 @@ -29,6 +29,7 @@ CONFIG_ARM_SMMU_V3=y # CONFIG_ARM_SMMU_V3_SVA is not set CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y diff --git a/target/linux/sunxi/cortexa53/config-5.15 b/target/linux/sunxi/cortexa53/config-5.15 index 00a3d971fd..b93abf0765 100644 --- a/target/linux/sunxi/cortexa53/config-5.15 +++ b/target/linux/sunxi/cortexa53/config-5.15 @@ -23,6 +23,7 @@ CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y diff --git a/toolchain/gcc/Config.in b/toolchain/gcc/Config.in index f725ad5785..3c074c99b2 100644 --- a/toolchain/gcc/Config.in +++ b/toolchain/gcc/Config.in @@ -6,12 +6,6 @@ choice help Select the version of gcc you wish to use. - config GCC_USE_VERSION_8 - bool "gcc 8.x" - - config GCC_USE_VERSION_10 - bool "gcc 10.x" - config GCC_USE_VERSION_11 bool "gcc 11.x" diff --git a/toolchain/gcc/Config.version b/toolchain/gcc/Config.version index a909979cf6..65f272746b 100644 --- a/toolchain/gcc/Config.version +++ b/toolchain/gcc/Config.version @@ -1,18 +1,8 @@ -config GCC_VERSION_8 - default y if GCC_USE_VERSION_8 - bool - -config GCC_VERSION_10 - default y if GCC_USE_VERSION_10 - bool - config GCC_VERSION_12 default y if GCC_USE_VERSION_12 bool config GCC_VERSION string - default "8.4.0" if GCC_VERSION_8 - default "10.3.0" if GCC_VERSION_10 default "12.2.0" if GCC_VERSION_12 default "11.3.0" diff --git a/toolchain/gcc/common.mk b/toolchain/gcc/common.mk index 83884dd54c..6661b0aa38 100644 --- a/toolchain/gcc/common.mk +++ b/toolchain/gcc/common.mk @@ -29,14 +29,6 @@ GCC_DIR:=$(PKG_NAME)-$(PKG_VERSION) PKG_SOURCE_URL:=@GNU/gcc/gcc-$(PKG_VERSION) PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz -ifeq ($(PKG_VERSION),8.4.0) - PKG_HASH:=e30a6e52d10e1f27ed55104ad233c30bd1e99cfb5ff98ab022dc941edd1b2dd4 -endif - -ifeq ($(PKG_VERSION),10.3.0) - PKG_HASH:=64f404c1a650f27fc33da242e1f2df54952e3963a49e06e73f6940f3223ac344 -endif - ifeq ($(PKG_VERSION),11.3.0) PKG_HASH:=b47cf2818691f5b1e21df2bb38c795fac2cfbd640ede2d0a5e1c89e338a3ac39 endif diff --git a/toolchain/gcc/patches-10.x/002-case_insensitive.patch b/toolchain/gcc/patches-10.x/002-case_insensitive.patch deleted file mode 100644 index 409497e5a3..0000000000 --- a/toolchain/gcc/patches-10.x/002-case_insensitive.patch +++ /dev/null @@ -1,24 +0,0 @@ -commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e -Author: Felix Fietkau -Date: Sun Oct 19 21:45:51 2014 +0000 - - gcc: do not assume that the Mac OS X filesystem is case insensitive - - Signed-off-by: Felix Fietkau - - SVN-Revision: 42973 - ---- a/include/filenames.h -+++ b/include/filenames.h -@@ -44,11 +44,6 @@ extern "C" { - # define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c) - # define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f) - #else /* not DOSish */ --# if defined(__APPLE__) --# ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM --# define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1 --# endif --# endif /* __APPLE__ */ - # define HAS_DRIVE_SPEC(f) (0) - # define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c) - # define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f) diff --git a/toolchain/gcc/patches-10.x/010-documentation.patch b/toolchain/gcc/patches-10.x/010-documentation.patch deleted file mode 100644 index 85990e5acc..0000000000 --- a/toolchain/gcc/patches-10.x/010-documentation.patch +++ /dev/null @@ -1,35 +0,0 @@ -commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2 -Author: Luka Perkov -Date: Tue Feb 26 16:16:33 2013 +0000 - - gcc: don't build documentation - - This closes #13039. - - Signed-off-by: Luka Perkov - - SVN-Revision: 35807 - ---- a/gcc/Makefile.in -+++ b/gcc/Makefile.in -@@ -3285,18 +3285,10 @@ doc/gcc.info: $(TEXI_GCC_FILES) - doc/gccint.info: $(TEXI_GCCINT_FILES) - doc/cppinternals.info: $(TEXI_CPPINT_FILES) - --doc/%.info: %.texi -- if [ x$(BUILD_INFO) = xinfo ]; then \ -- $(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \ -- -I $(gcc_docdir)/include -o $@ $<; \ -- fi -+doc/%.info: - - # Duplicate entry to handle renaming of gccinstall.info --doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES) -- if [ x$(BUILD_INFO) = xinfo ]; then \ -- $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \ -- -I $(gcc_docdir)/include -o $@ $<; \ -- fi -+doc/gccinstall.info: - - doc/cpp.dvi: $(TEXI_CPP_FILES) - doc/gcc.dvi: $(TEXI_GCC_FILES) diff --git a/toolchain/gcc/patches-10.x/110-Fix-MIPS-PR-84790.patch b/toolchain/gcc/patches-10.x/110-Fix-MIPS-PR-84790.patch deleted file mode 100644 index 82ac013d30..0000000000 --- a/toolchain/gcc/patches-10.x/110-Fix-MIPS-PR-84790.patch +++ /dev/null @@ -1,20 +0,0 @@ -Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790. -MIPS16 functions have a static assembler prologue which clobbers -registers v0 and v1. Add these register clobbers to function call -instructions. - ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -3132,6 +3132,12 @@ mips_emit_call_insn (rtx pattern, rtx or - emit_insn (gen_update_got_version ()); - } - -+ if (TARGET_MIPS16 && TARGET_USE_GOT) -+ { -+ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP); -+ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode)); -+ } -+ - if (TARGET_MIPS16 - && TARGET_EXPLICIT_RELOCS - && TARGET_CALL_CLOBBERED_GP) diff --git a/toolchain/gcc/patches-10.x/230-musl_libssp.patch b/toolchain/gcc/patches-10.x/230-musl_libssp.patch deleted file mode 100644 index 63f37662f4..0000000000 --- a/toolchain/gcc/patches-10.x/230-musl_libssp.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/gcc/gcc.c -+++ b/gcc/gcc.c -@@ -875,7 +875,9 @@ proper position among the other output f - #endif - - #ifndef LINK_SSP_SPEC --#ifdef TARGET_LIBC_PROVIDES_SSP -+#if DEFAULT_LIBC == LIBC_MUSL -+#define LINK_SSP_SPEC "-lssp_nonshared" -+#elif defined(TARGET_LIBC_PROVIDES_SSP) - #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ - "|fstack-protector-strong|fstack-protector-explicit:}" - #else diff --git a/toolchain/gcc/patches-10.x/300-mips_Os_cpu_rtx_cost_model.patch b/toolchain/gcc/patches-10.x/300-mips_Os_cpu_rtx_cost_model.patch deleted file mode 100644 index 8c4a5fce19..0000000000 --- a/toolchain/gcc/patches-10.x/300-mips_Os_cpu_rtx_cost_model.patch +++ /dev/null @@ -1,21 +0,0 @@ -commit ecf7671b769fe96f7b5134be442089f8bdba55d2 -Author: Felix Fietkau -Date: Thu Aug 4 20:29:45 2016 +0200 - -gcc: add a patch to generate better code with Os on mips - -Also happens to reduce compressed code size a bit - -Signed-off-by: Felix Fietkau - ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -20041,7 +20041,7 @@ mips_option_override (void) - flag_pcc_struct_return = 0; - - /* Decide which rtx_costs structure to use. */ -- if (optimize_size) -+ if (0 && optimize_size) - mips_cost = &mips_rtx_cost_optimize_size; - else - mips_cost = &mips_rtx_cost_data[mips_tune]; diff --git a/toolchain/gcc/patches-10.x/810-arm-softfloat-libgcc.patch b/toolchain/gcc/patches-10.x/810-arm-softfloat-libgcc.patch deleted file mode 100644 index 5c9d86aead..0000000000 --- a/toolchain/gcc/patches-10.x/810-arm-softfloat-libgcc.patch +++ /dev/null @@ -1,33 +0,0 @@ -commit 8570c4be394cff7282f332f97da2ff569a927ddb -Author: Imre Kaloz -Date: Wed Feb 2 20:06:12 2011 +0000 - - fixup arm soft-float symbols - - SVN-Revision: 25325 - ---- a/libgcc/config/arm/t-linux -+++ b/libgcc/config/arm/t-linux -@@ -1,6 +1,10 @@ - LIB1ASMSRC = arm/lib1funcs.S - LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \ -- _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 -+ _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \ -+ _arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \ -+ _arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \ -+ _arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \ -+ _arm_fixsfsi _arm_fixunssfsi - - # Just for these, we omit the frame pointer since it makes such a big - # difference. ---- a/gcc/config/arm/linux-elf.h -+++ b/gcc/config/arm/linux-elf.h -@@ -58,8 +58,6 @@ - %{shared:-lc} \ - %{!shared:%{profile:-lc_p}%{!profile:-lc}}" - --#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc" -- - #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" - - #define LINUX_TARGET_LINK_SPEC "%{h*} \ diff --git a/toolchain/gcc/patches-10.x/820-libgcc_pic.patch b/toolchain/gcc/patches-10.x/820-libgcc_pic.patch deleted file mode 100644 index ddd6cf8732..0000000000 --- a/toolchain/gcc/patches-10.x/820-libgcc_pic.patch +++ /dev/null @@ -1,44 +0,0 @@ -commit c96312958c0621e72c9b32da5bc224ffe2161384 -Author: Felix Fietkau -Date: Mon Oct 19 23:26:09 2009 +0000 - - gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow) - - SVN-Revision: 18086 - ---- a/libgcc/Makefile.in -+++ b/libgcc/Makefile.in -@@ -929,11 +929,12 @@ $(libgcov-driver-objects): %$(objext): $ - - # Static libraries. - libgcc.a: $(libgcc-objects) -+libgcc_pic.a: $(libgcc-s-objects) - libgcov.a: $(libgcov-objects) - libunwind.a: $(libunwind-objects) - libgcc_eh.a: $(libgcc-eh-objects) - --libgcc.a libgcov.a libunwind.a libgcc_eh.a: -+libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a: - -rm -f $@ - - objects="$(objects)"; \ -@@ -957,7 +958,7 @@ all: libunwind.a - endif - - ifeq ($(enable_shared),yes) --all: libgcc_eh.a libgcc_s$(SHLIB_EXT) -+all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT) - ifneq ($(LIBUNWIND),) - all: libunwind$(SHLIB_EXT) - libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT) -@@ -1163,6 +1164,10 @@ install-shared: - chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a - $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a - -+ $(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/ -+ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a -+ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a -+ - $(subst @multilib_dir@,$(MULTIDIR),$(subst \ - @shlib_base_name@,libgcc_s,$(subst \ - @shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL)))) diff --git a/toolchain/gcc/patches-10.x/840-armv4_pass_fix-v4bx_to_ld.patch b/toolchain/gcc/patches-10.x/840-armv4_pass_fix-v4bx_to_ld.patch deleted file mode 100644 index e3cb616c4e..0000000000 --- a/toolchain/gcc/patches-10.x/840-armv4_pass_fix-v4bx_to_ld.patch +++ /dev/null @@ -1,28 +0,0 @@ -commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc -Author: Imre Kaloz -Date: Wed Feb 2 19:34:36 2011 +0000 - - add armv4 fixup patches - - SVN-Revision: 25322 - - ---- a/gcc/config/arm/linux-eabi.h -+++ b/gcc/config/arm/linux-eabi.h -@@ -91,10 +91,15 @@ - #define MUSL_DYNAMIC_LINKER \ - "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1" - -+/* For armv4 we pass --fix-v4bx to linker to support EABI */ -+#undef TARGET_FIX_V4BX_SPEC -+#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\ -+ "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}" -+ - /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to - use the GNU/Linux version, not the generic BPABI version. */ - #undef LINK_SPEC --#define LINK_SPEC EABI_LINK_SPEC \ -+#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC \ - LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \ - LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) - diff --git a/toolchain/gcc/patches-10.x/850-use_shared_libgcc.patch b/toolchain/gcc/patches-10.x/850-use_shared_libgcc.patch deleted file mode 100644 index 8b17f1374f..0000000000 --- a/toolchain/gcc/patches-10.x/850-use_shared_libgcc.patch +++ /dev/null @@ -1,54 +0,0 @@ -commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd -Author: Felix Fietkau -Date: Sun Feb 12 20:25:47 2012 +0000 - - gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary - - SVN-Revision: 30486 ---- a/gcc/config/arm/linux-eabi.h -+++ b/gcc/config/arm/linux-eabi.h -@@ -132,10 +132,6 @@ - "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} " \ - LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC) - --/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we -- do not use -lfloat. */ --#undef LIBGCC_SPEC -- - /* Clear the instruction cache from `beg' to `end'. This is - implemented in lib1funcs.S, so ensure an error if this definition - is used. */ ---- a/gcc/config/linux.h -+++ b/gcc/config/linux.h -@@ -66,6 +66,10 @@ see the files COPYING3 and COPYING.RUNTI - builtin_version ("CRuntime_Musl"); \ - } while (0) - -+#ifndef LIBGCC_SPEC -+#define LIBGCC_SPEC "%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}" -+#endif -+ - /* Determine which dynamic linker to use depending on whether GLIBC or - uClibc or Bionic or musl is the default C library and whether - -muclibc or -mglibc or -mbionic or -mmusl has been passed to change ---- a/libgcc/mkmap-symver.awk -+++ b/libgcc/mkmap-symver.awk -@@ -136,5 +136,5 @@ function output(lib) { - else if (inherit[lib]) - printf("} %s;\n", inherit[lib]); - else -- printf ("\n local:\n\t*;\n};\n"); -+ printf ("\n\t*;\n};\n"); - } ---- a/gcc/config/rs6000/linux.h -+++ b/gcc/config/rs6000/linux.h -@@ -62,6 +62,9 @@ - #undef CPP_OS_DEFAULT_SPEC - #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)" - -+#undef LIBGCC_SPEC -+#define LIBGCC_SPEC "%{!static:%{!static-libgcc:-lgcc_s}} -lgcc" -+ - #undef LINK_SHLIB_SPEC - #define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}} \ - %{static-pie:-static -pie --no-dynamic-linker -z text}" diff --git a/toolchain/gcc/patches-10.x/851-libgcc_no_compat.patch b/toolchain/gcc/patches-10.x/851-libgcc_no_compat.patch deleted file mode 100644 index d710e40717..0000000000 --- a/toolchain/gcc/patches-10.x/851-libgcc_no_compat.patch +++ /dev/null @@ -1,22 +0,0 @@ -commit 64661de100da1ec1061ef3e5e400285dce115e6b -Author: Felix Fietkau -Date: Sun May 10 13:16:35 2015 +0000 - - gcc: add some size optimization patches - - Signed-off-by: Felix Fietkau - - SVN-Revision: 45664 - ---- a/libgcc/config/t-libunwind -+++ b/libgcc/config/t-libunwind -@@ -2,8 +2,7 @@ - - HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER - --LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \ -- $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c -+LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c - LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c - - # Override the default value from t-slibgcc-elf-ver and mention -lunwind diff --git a/toolchain/gcc/patches-10.x/870-ppc_no_crtsavres.patch b/toolchain/gcc/patches-10.x/870-ppc_no_crtsavres.patch deleted file mode 100644 index bc182f0cec..0000000000 --- a/toolchain/gcc/patches-10.x/870-ppc_no_crtsavres.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/gcc/config/rs6000/rs6000-logue.c -+++ b/gcc/config/rs6000/rs6000-logue.c -@@ -348,7 +348,7 @@ rs6000_savres_strategy (rs6000_stack_t * - /* Define cutoff for using out-of-line functions to save registers. */ - if (DEFAULT_ABI == ABI_V4 || TARGET_ELF) - { -- if (!optimize_size) -+ if (1) - { - strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS; - strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; diff --git a/toolchain/gcc/patches-10.x/881-no_tm_section.patch b/toolchain/gcc/patches-10.x/881-no_tm_section.patch deleted file mode 100644 index 2029910fd0..0000000000 --- a/toolchain/gcc/patches-10.x/881-no_tm_section.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/libgcc/crtstuff.c -+++ b/libgcc/crtstuff.c -@@ -152,7 +152,7 @@ call_ ## FUNC (void) \ - #endif - - #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF) --# define USE_TM_CLONE_REGISTRY 1 -+# define USE_TM_CLONE_REGISTRY 0 - #elif !defined(USE_TM_CLONE_REGISTRY) - # define USE_TM_CLONE_REGISTRY 0 - #endif diff --git a/toolchain/gcc/patches-10.x/900-bad-mips16-crt.patch b/toolchain/gcc/patches-10.x/900-bad-mips16-crt.patch deleted file mode 100644 index dd6e9dc889..0000000000 --- a/toolchain/gcc/patches-10.x/900-bad-mips16-crt.patch +++ /dev/null @@ -1,9 +0,0 @@ ---- a/libgcc/config/mips/t-mips16 -+++ b/libgcc/config/mips/t-mips16 -@@ -43,3 +43,6 @@ SYNC_CFLAGS = -mno-mips16 - - # Version these symbols if building libgcc.so. - SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver -+ -+CRTSTUFF_T_CFLAGS += -mno-mips16 -+CRTSTUFF_T_CFLAGS_S += -mno-mips16 diff --git a/toolchain/gcc/patches-10.x/910-mbsd_multi.patch b/toolchain/gcc/patches-10.x/910-mbsd_multi.patch deleted file mode 100644 index 3ed6238310..0000000000 --- a/toolchain/gcc/patches-10.x/910-mbsd_multi.patch +++ /dev/null @@ -1,146 +0,0 @@ -commit 99368862e44740ff4fd33760893f04e14f9dbdf1 -Author: Felix Fietkau -Date: Tue Jul 31 00:52:27 2007 +0000 - - Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly - - SVN-Revision: 8256 - - This patch brings over a feature from MirBSD: - * -fhonour-copts - If this option is not given, it's warned (depending - on environment variables). This is to catch errors - of misbuilt packages which override CFLAGS themselves. - - This patch was authored by Thorsten Glaser - with copyright assignment to the FSF in effect. - ---- a/gcc/c-family/c-opts.c -+++ b/gcc/c-family/c-opts.c -@@ -107,6 +107,9 @@ static dump_flags_t original_dump_flags; - /* Whether any standard preincluded header has been preincluded. */ - static bool done_preinclude; - -+/* Check if a port honours COPTS. */ -+static int honour_copts = 0; -+ - static void handle_OPT_d (const char *); - static void set_std_cxx98 (int); - static void set_std_cxx11 (int); -@@ -455,6 +458,12 @@ c_common_handle_option (size_t scode, co - flag_no_builtin = !value; - break; - -+ case OPT_fhonour_copts: -+ if (c_language == clk_c) { -+ honour_copts++; -+ } -+ break; -+ - case OPT_fconstant_string_class_: - constant_string_class_name = arg; - break; -@@ -1168,6 +1177,47 @@ c_common_init (void) - return false; - } - -+ if (c_language == clk_c) { -+ char *ev = getenv ("GCC_HONOUR_COPTS"); -+ int evv; -+ if (ev == NULL) -+ evv = -1; -+ else if ((*ev == '0') || (*ev == '\0')) -+ evv = 0; -+ else if (*ev == '1') -+ evv = 1; -+ else if (*ev == '2') -+ evv = 2; -+ else if (*ev == 's') -+ evv = -1; -+ else { -+ warning (0, "unknown GCC_HONOUR_COPTS value, assuming 1"); -+ evv = 1; /* maybe depend this on something like MIRBSD_NATIVE? */ -+ } -+ if (evv == 1) { -+ if (honour_copts == 0) { -+ error ("someone does not honour COPTS at all in lenient mode"); -+ return false; -+ } else if (honour_copts != 1) { -+ warning (0, "someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ } -+ } else if (evv == 2) { -+ if (honour_copts == 0) { -+ error ("someone does not honour COPTS at all in strict mode"); -+ return false; -+ } else if (honour_copts != 1) { -+ error ("someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ return false; -+ } -+ } else if (evv == 0) { -+ if (honour_copts != 1) -+ inform (UNKNOWN_LOCATION, "someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ } -+ } -+ - return true; - } - ---- a/gcc/c-family/c.opt -+++ b/gcc/c-family/c.opt -@@ -1590,6 +1590,9 @@ C++ ObjC++ Optimization Alias(fexception - fhonor-std - C++ ObjC++ WarnRemoved - -+fhonour-copts -+C ObjC C++ ObjC++ RejectNegative -+ - fhosted - C ObjC - Assume normal C execution environment. ---- a/gcc/common.opt -+++ b/gcc/common.opt -@@ -1660,6 +1660,9 @@ fguess-branch-probability - Common Report Var(flag_guess_branch_prob) Optimization - Enable guessing of branch probabilities. - -+fhonour-copts -+Common RejectNegative -+ - ; Nonzero means ignore `#ident' directives. 0 means handle them. - ; Generate position-independent code for executables if possible - ; On SVR4 targets, it also controls whether or not to emit a ---- a/gcc/doc/invoke.texi -+++ b/gcc/doc/invoke.texi -@@ -8171,6 +8171,17 @@ This option is only supported for C and - @option{-Wall} and by @option{-Wpedantic}, which can be disabled with - @option{-Wno-pointer-sign}. - -+@item -fhonour-copts -+@opindex fhonour-copts -+If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not -+given at least once, and warn if it is given more than once. -+If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not -+given exactly once. -+If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option -+is not given exactly once. -+The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}. -+This flag and environment variable only affect the C language. -+ - @item -Wstack-protector - @opindex Wstack-protector - @opindex Wno-stack-protector ---- a/gcc/opts.c -+++ b/gcc/opts.c -@@ -2318,6 +2318,9 @@ common_handle_option (struct gcc_options - /* Currently handled in a prescan. */ - break; - -+ case OPT_fhonour_copts: -+ break; -+ - case OPT_Werror: - dc->warning_as_error_requested = value; - break; diff --git a/toolchain/gcc/patches-10.x/920-specs_nonfatal_getenv.patch b/toolchain/gcc/patches-10.x/920-specs_nonfatal_getenv.patch deleted file mode 100644 index 487b9e47cb..0000000000 --- a/toolchain/gcc/patches-10.x/920-specs_nonfatal_getenv.patch +++ /dev/null @@ -1,22 +0,0 @@ -Author: Jo-Philipp Wich -Date: Sat Apr 21 03:02:39 2012 +0000 - - gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset - - SVN-Revision: 31390 - ---- a/gcc/gcc.c -+++ b/gcc/gcc.c -@@ -9396,8 +9396,10 @@ getenv_spec_function (int argc, const ch - } - - if (!value) -- fatal_error (input_location, -- "environment variable %qs not defined", varname); -+ { -+ warning (input_location, "environment variable %qs not defined", varname); -+ value = ""; -+ } - - /* We have to escape every character of the environment variable so - they are not interpreted as active spec characters. A diff --git a/toolchain/gcc/patches-10.x/930-fix-mips-noexecstack.patch b/toolchain/gcc/patches-10.x/930-fix-mips-noexecstack.patch deleted file mode 100644 index e795acd1de..0000000000 --- a/toolchain/gcc/patches-10.x/930-fix-mips-noexecstack.patch +++ /dev/null @@ -1,111 +0,0 @@ -From da45b3fde60095756f5f6030f6012c23a3d34429 Mon Sep 17 00:00:00 2001 -From: Andrew McDonnell -Date: Fri, 3 Oct 2014 19:09:00 +0930 -Subject: Add .note.GNU-stack section - -See http://lists.busybox.net/pipermail/uclibc/2014-October/048671.html -Below copied from https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02430.html - -Re: [Patch, MIPS] Add .note.GNU-stack section - - From: Steve Ellcey - -On Wed, 2014-09-10 at 10:15 -0700, Eric Christopher wrote: -> -> -> On Wed, Sep 10, 2014 at 9:27 AM, wrote: - -> This works except you did not update the assembly files in -> libgcc or glibc. We (Cavium) have the same patch in our tree -> for a few released versions. - -> Mind just checking yours in then Andrew? - -> Thanks! -> -eric - -I talked to Andrew about what files he changed in GCC and created and -tested this new patch. Andrew also mentioned changing some assembly -files in glibc but I don't see any use of '.section .note.GNU-stack' in -any assembly files in glibc (for any platform) so I wasn't planning on -creating a glibc to add them to mips glibc assembly language files. - -OK to check in this patch? - -Steve Ellcey -sellcey@mips.com - - - -2014-09-26 Steve Ellcey ---- - gcc/config/mips/mips.c | 3 +++ - libgcc/config/mips/crti.S | 4 ++++ - libgcc/config/mips/crtn.S | 3 +++ - libgcc/config/mips/mips16.S | 4 ++++ - libgcc/config/mips/vr4120-div.S | 4 ++++ - 5 files changed, 18 insertions(+) - ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -22881,6 +22881,9 @@ mips_asm_file_end (void) - #define TARGET_ASM_FILE_END mips_asm_file_end - - -+#undef TARGET_ASM_FILE_END -+#define TARGET_ASM_FILE_END file_end_indicate_exec_stack -+ - struct gcc_target targetm = TARGET_INITIALIZER; - - #include "gt-mips.h" ---- a/libgcc/config/mips/crti.S -+++ b/libgcc/config/mips/crti.S -@@ -24,6 +24,10 @@ see the files COPYING3 and COPYING.RUNTI - /* An executable stack is *not* required for these functions. */ - #include "gnustack.h" - -+ -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ - /* 4 slots for argument spill area. 1 for cpreturn, 1 for stack. - Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */ - ---- a/libgcc/config/mips/crtn.S -+++ b/libgcc/config/mips/crtn.S -@@ -24,6 +24,9 @@ see the files COPYING3 and COPYING.RUNTI - /* An executable stack is *not* required for these functions. */ - #include "gnustack.h" - -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ - /* 4 slots for argument spill area. 1 for cpreturn, 1 for stack. - Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */ - ---- a/libgcc/config/mips/mips16.S -+++ b/libgcc/config/mips/mips16.S -@@ -51,6 +51,10 @@ see the files COPYING3 and COPYING.RUNTI - values using the soft-float calling convention, but do the actual - operation using the hard floating point instructions. */ - -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ .previous -+ - #if defined _MIPS_SIM && (_MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIO64) - - /* This file contains 32-bit assembly code. */ ---- a/libgcc/config/mips/vr4120-div.S -+++ b/libgcc/config/mips/vr4120-div.S -@@ -29,6 +29,10 @@ see the files COPYING3 and COPYING.RUNTI - -mfix-vr4120. div and ddiv do not give the correct result when one - of the operands is negative. */ - -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ .previous -+ - .set nomips16 - - #define DIV \ diff --git a/toolchain/gcc/patches-10.x/931-libffi-fix-MIPS-softfloat-build-issue.patch b/toolchain/gcc/patches-10.x/931-libffi-fix-MIPS-softfloat-build-issue.patch deleted file mode 100644 index fb4cb1533a..0000000000 --- a/toolchain/gcc/patches-10.x/931-libffi-fix-MIPS-softfloat-build-issue.patch +++ /dev/null @@ -1,168 +0,0 @@ -From c0c62fa4256f805389f16ebfc4a60cf789129b50 Mon Sep 17 00:00:00 2001 -From: BangLang Huang -Date: Wed, 9 Nov 2016 10:36:49 +0800 -Subject: [PATCH] libffi: fix MIPS softfloat build issue - -Backported from github.com/libffi/libffi#272 - -Signed-off-by: BangLang Huang -Signed-off-by: Yousong Zhou ---- - libffi/src/mips/n32.S | 17 +++++++++++++++++ - libffi/src/mips/o32.S | 17 +++++++++++++++++ - 2 files changed, 34 insertions(+) - ---- a/libffi/src/mips/n32.S -+++ b/libffi/src/mips/n32.S -@@ -107,6 +107,16 @@ loadregs: - - REG_L t6, 3*FFI_SIZEOF_ARG($fp) # load the flags word into t6. - -+#ifdef __mips_soft_float -+ REG_L a0, 0*FFI_SIZEOF_ARG(t9) -+ REG_L a1, 1*FFI_SIZEOF_ARG(t9) -+ REG_L a2, 2*FFI_SIZEOF_ARG(t9) -+ REG_L a3, 3*FFI_SIZEOF_ARG(t9) -+ REG_L a4, 4*FFI_SIZEOF_ARG(t9) -+ REG_L a5, 5*FFI_SIZEOF_ARG(t9) -+ REG_L a6, 6*FFI_SIZEOF_ARG(t9) -+ REG_L a7, 7*FFI_SIZEOF_ARG(t9) -+#else - and t4, t6, ((1< -Date: Fri, 4 May 2018 18:20:53 +0800 -Subject: [PATCH] gotools: fix compilation when making cross compiler - -libgo is "the runtime support library for the Go programming language. -This library is intended for use with the Go frontend." - -gccgo will link target files with libgo.so which depends on libgcc_s.so.1, but -the linker will complain that it cannot find it. That's because shared libgcc -is not present in the install directory yet. libgo.so was made without problem -because gcc will emit -lgcc_s when compiled with -shared option. When gotools -were being made, it was supplied with -static-libgcc thus no link option was -provided. Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec -for linking with libgo.so - -- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation -- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html - -When 3-pass GCC compilation is used, shared libgcc runtime libraries will be -available after gcc pass2 completed and will meet the gotools link requirement -at gcc pass3 ---- - gotools/Makefile.am | 4 +++- - gotools/Makefile.in | 4 +++- - 2 files changed, 6 insertions(+), 2 deletions(-) - ---- a/gotools/Makefile.am -+++ b/gotools/Makefile.am -@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd} - STAMP = echo timestamp > - - libgodir = ../$(target_noncanonical)/libgo -+libgccdir = ../$(target_noncanonical)/libgcc - LIBGODEP = $(libgodir)/libgo.la - - LIBGOTOOL = $(libgodir)/libgotool.a -@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET) - GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS) - - AM_GOCFLAGS = -I $(libgodir) --AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs -+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \ -+ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s - GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@ - - libgosrcdir = $(srcdir)/../libgo/go ---- a/gotools/Makefile.in -+++ b/gotools/Makefile.in -@@ -337,6 +337,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd - PWD_COMMAND = $${PWDCMD-pwd} - STAMP = echo timestamp > - libgodir = ../$(target_noncanonical)/libgo -+libgccdir = ../$(target_noncanonical)/libgcc - LIBGODEP = $(libgodir)/libgo.la - LIBGOTOOL = $(libgodir)/libgotool.a - @NATIVE_FALSE@GOCOMPILER = $(GOC) -@@ -346,7 +347,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a - GOCFLAGS = $(CFLAGS_FOR_TARGET) - GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS) - AM_GOCFLAGS = -I $(libgodir) --AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs -+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \ -+ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s - GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@ - libgosrcdir = $(srcdir)/../libgo/go - cmdsrcdir = $(libgosrcdir)/cmd diff --git a/toolchain/gcc/patches-8.x/002-case_insensitive.patch b/toolchain/gcc/patches-8.x/002-case_insensitive.patch deleted file mode 100644 index 3442076d7d..0000000000 --- a/toolchain/gcc/patches-8.x/002-case_insensitive.patch +++ /dev/null @@ -1,24 +0,0 @@ -commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e -Author: Felix Fietkau -Date: Sun Oct 19 21:45:51 2014 +0000 - - gcc: do not assume that the Mac OS X filesystem is case insensitive - - Signed-off-by: Felix Fietkau - - SVN-Revision: 42973 - ---- a/include/filenames.h -+++ b/include/filenames.h -@@ -43,11 +43,6 @@ extern "C" { - # define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c) - # define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f) - #else /* not DOSish */ --# if defined(__APPLE__) --# ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM --# define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1 --# endif --# endif /* __APPLE__ */ - # define HAS_DRIVE_SPEC(f) (0) - # define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c) - # define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f) diff --git a/toolchain/gcc/patches-8.x/010-documentation.patch b/toolchain/gcc/patches-8.x/010-documentation.patch deleted file mode 100644 index c7e3d4ad55..0000000000 --- a/toolchain/gcc/patches-8.x/010-documentation.patch +++ /dev/null @@ -1,35 +0,0 @@ -commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2 -Author: Luka Perkov -Date: Tue Feb 26 16:16:33 2013 +0000 - - gcc: don't build documentation - - This closes #13039. - - Signed-off-by: Luka Perkov - - SVN-Revision: 35807 - ---- a/gcc/Makefile.in -+++ b/gcc/Makefile.in -@@ -3204,18 +3204,10 @@ doc/gcc.info: $(TEXI_GCC_FILES) - doc/gccint.info: $(TEXI_GCCINT_FILES) - doc/cppinternals.info: $(TEXI_CPPINT_FILES) - --doc/%.info: %.texi -- if [ x$(BUILD_INFO) = xinfo ]; then \ -- $(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \ -- -I $(gcc_docdir)/include -o $@ $<; \ -- fi -+doc/%.info: - - # Duplicate entry to handle renaming of gccinstall.info --doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES) -- if [ x$(BUILD_INFO) = xinfo ]; then \ -- $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \ -- -I $(gcc_docdir)/include -o $@ $<; \ -- fi -+doc/gccinstall.info: - - doc/cpp.dvi: $(TEXI_CPP_FILES) - doc/gcc.dvi: $(TEXI_GCC_FILES) diff --git a/toolchain/gcc/patches-8.x/110-Fix-MIPS-PR-84790.patch b/toolchain/gcc/patches-8.x/110-Fix-MIPS-PR-84790.patch deleted file mode 100644 index b89eca2faf..0000000000 --- a/toolchain/gcc/patches-8.x/110-Fix-MIPS-PR-84790.patch +++ /dev/null @@ -1,20 +0,0 @@ -Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790. -MIPS16 functions have a static assembler prologue which clobbers -registers v0 and v1. Add these register clobbers to function call -instructions. - ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -3102,6 +3102,12 @@ mips_emit_call_insn (rtx pattern, rtx or - emit_insn (gen_update_got_version ()); - } - -+ if (TARGET_MIPS16 && TARGET_USE_GOT) -+ { -+ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP); -+ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode)); -+ } -+ - if (TARGET_MIPS16 - && TARGET_EXPLICIT_RELOCS - && TARGET_CALL_CLOBBERED_GP) diff --git a/toolchain/gcc/patches-8.x/230-musl_libssp.patch b/toolchain/gcc/patches-8.x/230-musl_libssp.patch deleted file mode 100644 index b3ab79cafb..0000000000 --- a/toolchain/gcc/patches-8.x/230-musl_libssp.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/gcc/gcc.c -+++ b/gcc/gcc.c -@@ -868,7 +868,9 @@ proper position among the other output f - #endif - - #ifndef LINK_SSP_SPEC --#ifdef TARGET_LIBC_PROVIDES_SSP -+#if DEFAULT_LIBC == LIBC_MUSL -+#define LINK_SSP_SPEC "-lssp_nonshared" -+#elif defined(TARGET_LIBC_PROVIDES_SSP) - #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ - "|fstack-protector-strong|fstack-protector-explicit:}" - #else diff --git a/toolchain/gcc/patches-8.x/300-mips_Os_cpu_rtx_cost_model.patch b/toolchain/gcc/patches-8.x/300-mips_Os_cpu_rtx_cost_model.patch deleted file mode 100644 index 2e2c609e48..0000000000 --- a/toolchain/gcc/patches-8.x/300-mips_Os_cpu_rtx_cost_model.patch +++ /dev/null @@ -1,21 +0,0 @@ -commit ecf7671b769fe96f7b5134be442089f8bdba55d2 -Author: Felix Fietkau -Date: Thu Aug 4 20:29:45 2016 +0200 - -gcc: add a patch to generate better code with Os on mips - -Also happens to reduce compressed code size a bit - -Signed-off-by: Felix Fietkau - ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -19847,7 +19847,7 @@ mips_option_override (void) - flag_pcc_struct_return = 0; - - /* Decide which rtx_costs structure to use. */ -- if (optimize_size) -+ if (0 && optimize_size) - mips_cost = &mips_rtx_cost_optimize_size; - else - mips_cost = &mips_rtx_cost_data[mips_tune]; diff --git a/toolchain/gcc/patches-8.x/800-arm_v5te_no_ldrd_strd.patch b/toolchain/gcc/patches-8.x/800-arm_v5te_no_ldrd_strd.patch deleted file mode 100644 index 172295f28b..0000000000 --- a/toolchain/gcc/patches-8.x/800-arm_v5te_no_ldrd_strd.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/gcc/config/arm/arm.h -+++ b/gcc/config/arm/arm.h -@@ -155,7 +155,7 @@ extern tree arm_fp16_type_node; - /* Thumb-1 only. */ - #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) - --#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ -+#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \ - && !TARGET_THUMB1) - - #define TARGET_CRC32 (arm_arch_crc) diff --git a/toolchain/gcc/patches-8.x/810-arm-softfloat-libgcc.patch b/toolchain/gcc/patches-8.x/810-arm-softfloat-libgcc.patch deleted file mode 100644 index 5c9d86aead..0000000000 --- a/toolchain/gcc/patches-8.x/810-arm-softfloat-libgcc.patch +++ /dev/null @@ -1,33 +0,0 @@ -commit 8570c4be394cff7282f332f97da2ff569a927ddb -Author: Imre Kaloz -Date: Wed Feb 2 20:06:12 2011 +0000 - - fixup arm soft-float symbols - - SVN-Revision: 25325 - ---- a/libgcc/config/arm/t-linux -+++ b/libgcc/config/arm/t-linux -@@ -1,6 +1,10 @@ - LIB1ASMSRC = arm/lib1funcs.S - LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \ -- _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 -+ _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \ -+ _arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \ -+ _arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \ -+ _arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \ -+ _arm_fixsfsi _arm_fixunssfsi - - # Just for these, we omit the frame pointer since it makes such a big - # difference. ---- a/gcc/config/arm/linux-elf.h -+++ b/gcc/config/arm/linux-elf.h -@@ -58,8 +58,6 @@ - %{shared:-lc} \ - %{!shared:%{profile:-lc_p}%{!profile:-lc}}" - --#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc" -- - #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" - - #define LINUX_TARGET_LINK_SPEC "%{h*} \ diff --git a/toolchain/gcc/patches-8.x/820-libgcc_pic.patch b/toolchain/gcc/patches-8.x/820-libgcc_pic.patch deleted file mode 100644 index 1a9678d480..0000000000 --- a/toolchain/gcc/patches-8.x/820-libgcc_pic.patch +++ /dev/null @@ -1,44 +0,0 @@ -commit c96312958c0621e72c9b32da5bc224ffe2161384 -Author: Felix Fietkau -Date: Mon Oct 19 23:26:09 2009 +0000 - - gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow) - - SVN-Revision: 18086 - ---- a/libgcc/Makefile.in -+++ b/libgcc/Makefile.in -@@ -923,11 +923,12 @@ $(libgcov-driver-objects): %$(objext): $ - - # Static libraries. - libgcc.a: $(libgcc-objects) -+libgcc_pic.a: $(libgcc-s-objects) - libgcov.a: $(libgcov-objects) - libunwind.a: $(libunwind-objects) - libgcc_eh.a: $(libgcc-eh-objects) - --libgcc.a libgcov.a libunwind.a libgcc_eh.a: -+libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a: - -rm -f $@ - - objects="$(objects)"; \ -@@ -948,7 +949,7 @@ all: libunwind.a - endif - - ifeq ($(enable_shared),yes) --all: libgcc_eh.a libgcc_s$(SHLIB_EXT) -+all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT) - ifneq ($(LIBUNWIND),) - all: libunwind$(SHLIB_EXT) - libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT) -@@ -1154,6 +1155,10 @@ install-shared: - chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a - $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a - -+ $(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/ -+ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a -+ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a -+ - $(subst @multilib_dir@,$(MULTIDIR),$(subst \ - @shlib_base_name@,libgcc_s,$(subst \ - @shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL)))) diff --git a/toolchain/gcc/patches-8.x/840-armv4_pass_fix-v4bx_to_ld.patch b/toolchain/gcc/patches-8.x/840-armv4_pass_fix-v4bx_to_ld.patch deleted file mode 100644 index b9c9b161ad..0000000000 --- a/toolchain/gcc/patches-8.x/840-armv4_pass_fix-v4bx_to_ld.patch +++ /dev/null @@ -1,28 +0,0 @@ -commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc -Author: Imre Kaloz -Date: Wed Feb 2 19:34:36 2011 +0000 - - add armv4 fixup patches - - SVN-Revision: 25322 - - ---- a/gcc/config/arm/linux-eabi.h -+++ b/gcc/config/arm/linux-eabi.h -@@ -88,10 +88,15 @@ - #define MUSL_DYNAMIC_LINKER \ - "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}.so.1" - -+/* For armv4 we pass --fix-v4bx to linker to support EABI */ -+#undef TARGET_FIX_V4BX_SPEC -+#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\ -+ "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}" -+ - /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to - use the GNU/Linux version, not the generic BPABI version. */ - #undef LINK_SPEC --#define LINK_SPEC EABI_LINK_SPEC \ -+#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC \ - LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \ - LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) - diff --git a/toolchain/gcc/patches-8.x/850-use_shared_libgcc.patch b/toolchain/gcc/patches-8.x/850-use_shared_libgcc.patch deleted file mode 100644 index f619f0e6a1..0000000000 --- a/toolchain/gcc/patches-8.x/850-use_shared_libgcc.patch +++ /dev/null @@ -1,54 +0,0 @@ -commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd -Author: Felix Fietkau -Date: Sun Feb 12 20:25:47 2012 +0000 - - gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary - - SVN-Revision: 30486 ---- a/gcc/config/arm/linux-eabi.h -+++ b/gcc/config/arm/linux-eabi.h -@@ -126,10 +126,6 @@ - "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} " \ - LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC) - --/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we -- do not use -lfloat. */ --#undef LIBGCC_SPEC -- - /* Clear the instruction cache from `beg' to `end'. This is - implemented in lib1funcs.S, so ensure an error if this definition - is used. */ ---- a/gcc/config/linux.h -+++ b/gcc/config/linux.h -@@ -53,6 +53,10 @@ see the files COPYING3 and COPYING.RUNTI - builtin_assert ("system=posix"); \ - } while (0) - -+#ifndef LIBGCC_SPEC -+#define LIBGCC_SPEC "%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}" -+#endif -+ - /* Determine which dynamic linker to use depending on whether GLIBC or - uClibc or Bionic or musl is the default C library and whether - -muclibc or -mglibc or -mbionic or -mmusl has been passed to change ---- a/libgcc/mkmap-symver.awk -+++ b/libgcc/mkmap-symver.awk -@@ -136,5 +136,5 @@ function output(lib) { - else if (inherit[lib]) - printf("} %s;\n", inherit[lib]); - else -- printf ("\n local:\n\t*;\n};\n"); -+ printf ("\n\t*;\n};\n"); - } ---- a/gcc/config/rs6000/linux.h -+++ b/gcc/config/rs6000/linux.h -@@ -60,6 +60,9 @@ - #undef CPP_OS_DEFAULT_SPEC - #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)" - -+#undef LIBGCC_SPEC -+#define LIBGCC_SPEC "%{!static:%{!static-libgcc:-lgcc_s}} -lgcc" -+ - #undef LINK_SHLIB_SPEC - #define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}} \ - %{static-pie:-static -pie --no-dynamic-linker -z text}" diff --git a/toolchain/gcc/patches-8.x/851-libgcc_no_compat.patch b/toolchain/gcc/patches-8.x/851-libgcc_no_compat.patch deleted file mode 100644 index d710e40717..0000000000 --- a/toolchain/gcc/patches-8.x/851-libgcc_no_compat.patch +++ /dev/null @@ -1,22 +0,0 @@ -commit 64661de100da1ec1061ef3e5e400285dce115e6b -Author: Felix Fietkau -Date: Sun May 10 13:16:35 2015 +0000 - - gcc: add some size optimization patches - - Signed-off-by: Felix Fietkau - - SVN-Revision: 45664 - ---- a/libgcc/config/t-libunwind -+++ b/libgcc/config/t-libunwind -@@ -2,8 +2,7 @@ - - HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER - --LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \ -- $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c -+LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c - LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c - - # Override the default value from t-slibgcc-elf-ver and mention -lunwind diff --git a/toolchain/gcc/patches-8.x/870-ppc_no_crtsavres.patch b/toolchain/gcc/patches-8.x/870-ppc_no_crtsavres.patch deleted file mode 100644 index 51d11c3d85..0000000000 --- a/toolchain/gcc/patches-8.x/870-ppc_no_crtsavres.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/gcc/config/rs6000/rs6000.c -+++ b/gcc/config/rs6000/rs6000.c -@@ -24780,7 +24780,7 @@ rs6000_savres_strategy (rs6000_stack_t * - /* Define cutoff for using out-of-line functions to save registers. */ - if (DEFAULT_ABI == ABI_V4 || TARGET_ELF) - { -- if (!optimize_size) -+ if (1) - { - strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS; - strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; diff --git a/toolchain/gcc/patches-8.x/881-no_tm_section.patch b/toolchain/gcc/patches-8.x/881-no_tm_section.patch deleted file mode 100644 index fab5db3be5..0000000000 --- a/toolchain/gcc/patches-8.x/881-no_tm_section.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/libgcc/crtstuff.c -+++ b/libgcc/crtstuff.c -@@ -152,7 +152,7 @@ call_ ## FUNC (void) \ - #endif - - #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF) --# define USE_TM_CLONE_REGISTRY 1 -+# define USE_TM_CLONE_REGISTRY 0 - #endif - - /* We do not want to add the weak attribute to the declarations of these diff --git a/toolchain/gcc/patches-8.x/900-bad-mips16-crt.patch b/toolchain/gcc/patches-8.x/900-bad-mips16-crt.patch deleted file mode 100644 index dd6e9dc889..0000000000 --- a/toolchain/gcc/patches-8.x/900-bad-mips16-crt.patch +++ /dev/null @@ -1,9 +0,0 @@ ---- a/libgcc/config/mips/t-mips16 -+++ b/libgcc/config/mips/t-mips16 -@@ -43,3 +43,6 @@ SYNC_CFLAGS = -mno-mips16 - - # Version these symbols if building libgcc.so. - SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver -+ -+CRTSTUFF_T_CFLAGS += -mno-mips16 -+CRTSTUFF_T_CFLAGS_S += -mno-mips16 diff --git a/toolchain/gcc/patches-8.x/910-mbsd_multi.patch b/toolchain/gcc/patches-8.x/910-mbsd_multi.patch deleted file mode 100644 index c566ea35e5..0000000000 --- a/toolchain/gcc/patches-8.x/910-mbsd_multi.patch +++ /dev/null @@ -1,146 +0,0 @@ -commit 99368862e44740ff4fd33760893f04e14f9dbdf1 -Author: Felix Fietkau -Date: Tue Jul 31 00:52:27 2007 +0000 - - Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly - - SVN-Revision: 8256 - - This patch brings over a feature from MirBSD: - * -fhonour-copts - If this option is not given, it's warned (depending - on environment variables). This is to catch errors - of misbuilt packages which override CFLAGS themselves. - - This patch was authored by Thorsten Glaser - with copyright assignment to the FSF in effect. - ---- a/gcc/c-family/c-opts.c -+++ b/gcc/c-family/c-opts.c -@@ -107,6 +107,9 @@ static dump_flags_t original_dump_flags; - /* Whether any standard preincluded header has been preincluded. */ - static bool done_preinclude; - -+/* Check if a port honours COPTS. */ -+static int honour_copts = 0; -+ - static void handle_OPT_d (const char *); - static void set_std_cxx98 (int); - static void set_std_cxx11 (int); -@@ -459,6 +462,12 @@ c_common_handle_option (size_t scode, co - flag_no_builtin = !value; - break; - -+ case OPT_fhonour_copts: -+ if (c_language == clk_c) { -+ honour_copts++; -+ } -+ break; -+ - case OPT_fconstant_string_class_: - constant_string_class_name = arg; - break; -@@ -1125,6 +1134,47 @@ c_common_init (void) - return false; - } - -+ if (c_language == clk_c) { -+ char *ev = getenv ("GCC_HONOUR_COPTS"); -+ int evv; -+ if (ev == NULL) -+ evv = -1; -+ else if ((*ev == '0') || (*ev == '\0')) -+ evv = 0; -+ else if (*ev == '1') -+ evv = 1; -+ else if (*ev == '2') -+ evv = 2; -+ else if (*ev == 's') -+ evv = -1; -+ else { -+ warning (0, "unknown GCC_HONOUR_COPTS value, assuming 1"); -+ evv = 1; /* maybe depend this on something like MIRBSD_NATIVE? */ -+ } -+ if (evv == 1) { -+ if (honour_copts == 0) { -+ error ("someone does not honour COPTS at all in lenient mode"); -+ return false; -+ } else if (honour_copts != 1) { -+ warning (0, "someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ } -+ } else if (evv == 2) { -+ if (honour_copts == 0) { -+ error ("someone does not honour COPTS at all in strict mode"); -+ return false; -+ } else if (honour_copts != 1) { -+ error ("someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ return false; -+ } -+ } else if (evv == 0) { -+ if (honour_copts != 1) -+ inform (UNKNOWN_LOCATION, "someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ } -+ } -+ - return true; - } - ---- a/gcc/c-family/c.opt -+++ b/gcc/c-family/c.opt -@@ -1469,6 +1469,9 @@ C++ ObjC++ Optimization Alias(fexception - fhonor-std - C++ ObjC++ Ignore Warn(switch %qs is no longer supported) - -+fhonour-copts -+C ObjC C++ ObjC++ RejectNegative -+ - fhosted - C ObjC - Assume normal C execution environment. ---- a/gcc/common.opt -+++ b/gcc/common.opt -@@ -1551,6 +1551,9 @@ fguess-branch-probability - Common Report Var(flag_guess_branch_prob) Optimization - Enable guessing of branch probabilities. - -+fhonour-copts -+Common RejectNegative -+ - ; Nonzero means ignore `#ident' directives. 0 means handle them. - ; Generate position-independent code for executables if possible - ; On SVR4 targets, it also controls whether or not to emit a ---- a/gcc/opts.c -+++ b/gcc/opts.c -@@ -2073,6 +2073,9 @@ common_handle_option (struct gcc_options - opts, opts_set, loc, dc); - break; - -+ case OPT_fhonour_copts: -+ break; -+ - case OPT_Wlarger_than_: - opts->x_larger_than_size = value; - opts->x_warn_larger_than = value != -1; ---- a/gcc/doc/invoke.texi -+++ b/gcc/doc/invoke.texi -@@ -7013,6 +7013,17 @@ This option is only supported for C and - @option{-Wall} and by @option{-Wpedantic}, which can be disabled with - @option{-Wno-pointer-sign}. - -+@item -fhonour-copts -+@opindex fhonour-copts -+If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not -+given at least once, and warn if it is given more than once. -+If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not -+given exactly once. -+If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option -+is not given exactly once. -+The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}. -+This flag and environment variable only affect the C language. -+ - @item -Wstack-protector - @opindex Wstack-protector - @opindex Wno-stack-protector diff --git a/toolchain/gcc/patches-8.x/920-specs_nonfatal_getenv.patch b/toolchain/gcc/patches-8.x/920-specs_nonfatal_getenv.patch deleted file mode 100644 index c3836e63af..0000000000 --- a/toolchain/gcc/patches-8.x/920-specs_nonfatal_getenv.patch +++ /dev/null @@ -1,22 +0,0 @@ -Author: Jo-Philipp Wich -Date: Sat Apr 21 03:02:39 2012 +0000 - - gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset - - SVN-Revision: 31390 - ---- a/gcc/gcc.c -+++ b/gcc/gcc.c -@@ -9347,8 +9347,10 @@ getenv_spec_function (int argc, const ch - value = varname; - - if (!value) -- fatal_error (input_location, -- "environment variable %qs not defined", varname); -+ { -+ warning (input_location, "environment variable %qs not defined", varname); -+ value = ""; -+ } - - /* We have to escape every character of the environment variable so - they are not interpreted as active spec characters. A diff --git a/toolchain/gcc/patches-8.x/930-fix-mips-noexecstack.patch b/toolchain/gcc/patches-8.x/930-fix-mips-noexecstack.patch deleted file mode 100644 index ed8ada22a1..0000000000 --- a/toolchain/gcc/patches-8.x/930-fix-mips-noexecstack.patch +++ /dev/null @@ -1,111 +0,0 @@ -From da45b3fde60095756f5f6030f6012c23a3d34429 Mon Sep 17 00:00:00 2001 -From: Andrew McDonnell -Date: Fri, 3 Oct 2014 19:09:00 +0930 -Subject: Add .note.GNU-stack section - -See http://lists.busybox.net/pipermail/uclibc/2014-October/048671.html -Below copied from https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02430.html - -Re: [Patch, MIPS] Add .note.GNU-stack section - - From: Steve Ellcey - -On Wed, 2014-09-10 at 10:15 -0700, Eric Christopher wrote: -> -> -> On Wed, Sep 10, 2014 at 9:27 AM, wrote: - -> This works except you did not update the assembly files in -> libgcc or glibc. We (Cavium) have the same patch in our tree -> for a few released versions. - -> Mind just checking yours in then Andrew? - -> Thanks! -> -eric - -I talked to Andrew about what files he changed in GCC and created and -tested this new patch. Andrew also mentioned changing some assembly -files in glibc but I don't see any use of '.section .note.GNU-stack' in -any assembly files in glibc (for any platform) so I wasn't planning on -creating a glibc to add them to mips glibc assembly language files. - -OK to check in this patch? - -Steve Ellcey -sellcey@mips.com - - - -2014-09-26 Steve Ellcey ---- - gcc/config/mips/mips.c | 3 +++ - libgcc/config/mips/crti.S | 4 ++++ - libgcc/config/mips/crtn.S | 3 +++ - libgcc/config/mips/mips16.S | 4 ++++ - libgcc/config/mips/vr4120-div.S | 4 ++++ - 5 files changed, 18 insertions(+) - ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -22640,6 +22640,9 @@ mips_starting_frame_offset (void) - #undef TARGET_STARTING_FRAME_OFFSET - #define TARGET_STARTING_FRAME_OFFSET mips_starting_frame_offset - -+#undef TARGET_ASM_FILE_END -+#define TARGET_ASM_FILE_END file_end_indicate_exec_stack -+ - struct gcc_target targetm = TARGET_INITIALIZER; - - #include "gt-mips.h" ---- a/libgcc/config/mips/crti.S -+++ b/libgcc/config/mips/crti.S -@@ -21,6 +21,10 @@ a copy of the GCC Runtime Library Except - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - -+ -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ - /* 4 slots for argument spill area. 1 for cpreturn, 1 for stack. - Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */ - ---- a/libgcc/config/mips/crtn.S -+++ b/libgcc/config/mips/crtn.S -@@ -21,6 +21,9 @@ a copy of the GCC Runtime Library Except - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ - /* 4 slots for argument spill area. 1 for cpreturn, 1 for stack. - Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */ - ---- a/libgcc/config/mips/mips16.S -+++ b/libgcc/config/mips/mips16.S -@@ -48,6 +48,10 @@ see the files COPYING3 and COPYING.RUNTI - values using the soft-float calling convention, but do the actual - operation using the hard floating point instructions. */ - -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ .previous -+ - #if defined _MIPS_SIM && (_MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIO64) - - /* This file contains 32-bit assembly code. */ ---- a/libgcc/config/mips/vr4120-div.S -+++ b/libgcc/config/mips/vr4120-div.S -@@ -26,6 +26,10 @@ see the files COPYING3 and COPYING.RUNTI - -mfix-vr4120. div and ddiv do not give the correct result when one - of the operands is negative. */ - -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ .previous -+ - .set nomips16 - - #define DIV \ diff --git a/toolchain/gcc/patches-8.x/931-libffi-fix-MIPS-softfloat-build-issue.patch b/toolchain/gcc/patches-8.x/931-libffi-fix-MIPS-softfloat-build-issue.patch deleted file mode 100644 index fb4cb1533a..0000000000 --- a/toolchain/gcc/patches-8.x/931-libffi-fix-MIPS-softfloat-build-issue.patch +++ /dev/null @@ -1,168 +0,0 @@ -From c0c62fa4256f805389f16ebfc4a60cf789129b50 Mon Sep 17 00:00:00 2001 -From: BangLang Huang -Date: Wed, 9 Nov 2016 10:36:49 +0800 -Subject: [PATCH] libffi: fix MIPS softfloat build issue - -Backported from github.com/libffi/libffi#272 - -Signed-off-by: BangLang Huang -Signed-off-by: Yousong Zhou ---- - libffi/src/mips/n32.S | 17 +++++++++++++++++ - libffi/src/mips/o32.S | 17 +++++++++++++++++ - 2 files changed, 34 insertions(+) - ---- a/libffi/src/mips/n32.S -+++ b/libffi/src/mips/n32.S -@@ -107,6 +107,16 @@ loadregs: - - REG_L t6, 3*FFI_SIZEOF_ARG($fp) # load the flags word into t6. - -+#ifdef __mips_soft_float -+ REG_L a0, 0*FFI_SIZEOF_ARG(t9) -+ REG_L a1, 1*FFI_SIZEOF_ARG(t9) -+ REG_L a2, 2*FFI_SIZEOF_ARG(t9) -+ REG_L a3, 3*FFI_SIZEOF_ARG(t9) -+ REG_L a4, 4*FFI_SIZEOF_ARG(t9) -+ REG_L a5, 5*FFI_SIZEOF_ARG(t9) -+ REG_L a6, 6*FFI_SIZEOF_ARG(t9) -+ REG_L a7, 7*FFI_SIZEOF_ARG(t9) -+#else - and t4, t6, ((1< -Date: Fri, 4 May 2018 18:20:53 +0800 -Subject: [PATCH] gotools: fix compilation when making cross compiler - -libgo is "the runtime support library for the Go programming language. -This library is intended for use with the Go frontend." - -gccgo will link target files with libgo.so which depends on libgcc_s.so.1, but -the linker will complain that it cannot find it. That's because shared libgcc -is not present in the install directory yet. libgo.so was made without problem -because gcc will emit -lgcc_s when compiled with -shared option. When gotools -were being made, it was supplied with -static-libgcc thus no link option was -provided. Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec -for linking with libgo.so - -- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation -- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html - -When 3-pass GCC compilation is used, shared libgcc runtime libraries will be -available after gcc pass2 completed and will meet the gotools link requirement -at gcc pass3 ---- - gotools/Makefile.am | 4 +++- - gotools/Makefile.in | 4 +++- - 2 files changed, 6 insertions(+), 2 deletions(-) - ---- a/gotools/Makefile.am -+++ b/gotools/Makefile.am -@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd} - STAMP = echo timestamp > - - libgodir = ../$(target_noncanonical)/libgo -+libgccdir = ../$(target_noncanonical)/libgcc - LIBGODEP = $(libgodir)/libgo.la - - LIBGOTOOL = $(libgodir)/libgotool.a -@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET) - GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS) - - AM_GOCFLAGS = -I $(libgodir) --AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs -+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \ -+ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s - GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@ - - libgosrcdir = $(srcdir)/../libgo/go ---- a/gotools/Makefile.in -+++ b/gotools/Makefile.in -@@ -263,6 +263,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd - PWD_COMMAND = $${PWDCMD-pwd} - STAMP = echo timestamp > - libgodir = ../$(target_noncanonical)/libgo -+libgccdir = ../$(target_noncanonical)/libgcc - LIBGODEP = $(libgodir)/libgo.la - LIBGOTOOL = $(libgodir)/libgotool.a - @NATIVE_FALSE@GOCOMPILER = $(GOC) -@@ -271,7 +272,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a - @NATIVE_TRUE@GOCOMPILER = $(GOC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) - GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS) - AM_GOCFLAGS = -I $(libgodir) --AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs -+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \ -+ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s - GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@ - libgosrcdir = $(srcdir)/../libgo/go - cmdsrcdir = $(libgosrcdir)/cmd diff --git a/tools/Makefile b/tools/Makefile index 79de499a85..902cb94e0d 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -53,6 +53,7 @@ $(curdir)/fakeroot/compile := $(curdir)/libtool/compile $(curdir)/findutils/compile := $(curdir)/bison/compile $(curdir)/firmware-utils/compile += $(curdir)/cmake/compile $(curdir)/flex/compile := $(curdir)/libtool/compile +$(curdir)/genext2fs/compile := $(curdir)/libtool/compile $(curdir)/gengetopt/compile := $(curdir)/libtool/compile $(curdir)/gmp/compile := $(curdir)/libtool/compile $(curdir)/gptfdisk/compile += $(curdir)/e2fsprogs/compile $(curdir)/popt/compile diff --git a/tools/bash/Makefile b/tools/bash/Makefile index 992933c6bf..e5cf3b5945 100644 --- a/tools/bash/Makefile +++ b/tools/bash/Makefile @@ -8,11 +8,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=bash PKG_CPE_ID:=cpe:/a:gnu:bash -PKG_VERSION:=5.1.16 +PKG_VERSION:=5.2 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@GNU/bash -PKG_HASH:=5bac17218d3911834520dad13cd1f85ab944e1c09ae1aba55906be1f8192f558 +PKG_HASH:=a139c166df7ff4471c5e0733051642ee5556c1cc8a4a78f145583c5c81ab32fb HOST_BUILD_PARALLEL := 1 diff --git a/tools/bc/Makefile b/tools/bc/Makefile index ac6609e008..2c29e094e2 100644 --- a/tools/bc/Makefile +++ b/tools/bc/Makefile @@ -7,11 +7,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=bc -PKG_VERSION:=1.07 +PKG_VERSION:=1.07.1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@GNU/bc -PKG_HASH:=55cf1fc33a728d7c3d386cc7b0cb556eb5bacf8e0cb5a3fcca7f109fc61205ad +PKG_HASH:=62adfca89b0a1c0164c2cdca59ca210c1d44c3ffc46daf9931cf4942664cb02a PKG_FIXUP := autoreconf PKG_CPE_ID:=cpe:/a:gnu:bc diff --git a/tools/bc/patches/003-bc-fix-hang.patch b/tools/bc/patches/003-bc-fix-hang.patch deleted file mode 100644 index ba297051e2..0000000000 --- a/tools/bc/patches/003-bc-fix-hang.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/bc/execute.c -+++ b/bc/execute.c -@@ -595,7 +595,7 @@ input_char (void) - if (in_ch == '.' || in_ch == '+' || in_ch == '-') - return (in_ch); - if (in_ch <= ' ') -- return (' '); -+ return (':'); - - return (':'); - } diff --git a/tools/dwarves/Makefile b/tools/dwarves/Makefile index 41f0532701..d9a121aab1 100644 --- a/tools/dwarves/Makefile +++ b/tools/dwarves/Makefile @@ -3,11 +3,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=dwarves +PKG_VERSION:=1.24 +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz +PKG_SOURCE_URL:=https://fedorapeople.org/~acme/dwarves/ +PKG_HASH:=576bc112b95937dfbcd347c423696ee9e1992a338fdca1acacca736fd95f69c2 -PKG_SOURCE_VERSION:=v1.23 -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://git.kernel.org/pub/scm/devel/pahole/pahole.git -PKG_MIRROR_HASH:=6ab1bb1dbdf6c73ffcf485d909229dc1da1a3d24efd213e92c56489b58d6a4bd PKG_LICENSE:=GPL-2.0-only PKG_LICENSE_FILES:=COPYING diff --git a/tools/genext2fs/Makefile b/tools/genext2fs/Makefile index 3a911df91a..4e7abf8bb6 100644 --- a/tools/genext2fs/Makefile +++ b/tools/genext2fs/Makefile @@ -8,11 +8,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=genext2fs -PKG_VERSION:=1.4.1 +PKG_VERSION:=1.5.0 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz -PKG_SOURCE_URL:=@SF/genext2fs -PKG_HASH:=404dbbfa7a86a6c3de8225c8da254d026b17fd288e05cec4df2cc7e1f4feecfc +PKG_SOURCE_URL:=https://codeload.github.com/bestouff/$(PKG_NAME)/tar.gz/v$(PKG_VERSION)? +PKG_HASH:=d3861e4fe89131bd21fbd25cf0b683b727b5c030c4c336fadcd738ada830aab0 include $(INCLUDE_DIR)/host-build.mk @@ -33,6 +33,13 @@ HOST_CONFIGURE_ARGS = \ --mandir=/usr/man \ --infodir=/usr/info \ +define Host/Configure + (cd $(HOST_BUILD_DIR); \ + ./autogen.sh \ + ); + $(call Host/Configure/Default) +endef + define Host/Compile $(MAKE) -C $(HOST_BUILD_DIR) \ CFLAGS="$(HOST_CFLAGS)" \ diff --git a/tools/genext2fs/patches/100-c99_scanf.patch b/tools/genext2fs/patches/100-c99_scanf.patch deleted file mode 100644 index e7aa17cc6f..0000000000 --- a/tools/genext2fs/patches/100-c99_scanf.patch +++ /dev/null @@ -1,21 +0,0 @@ -commit 3b8ca0ce9a0b58287a780747c90c449bdebfe464 -Author: Xavier Bestel -Date: Mon Jan 14 08:52:44 2008 +0000 - - removed use of %as is scanf (GNU conflicts with C99) by Giacomo Catenazzi - -diff --git a/genext2fs.c b/genext2fs.c -index 070b270..f0d797d 100644 ---- a/genext2fs.c -+++ b/genext2fs.c -@@ -286,7 +286,9 @@ typedef unsigned int uint32; - // older solaris. Note that this is still not very portable, in that - // the return value cannot be trusted. - --#if SCANF_CAN_MALLOC -+#if 0 // SCANF_CAN_MALLOC -+// C99 define "a" for floating point, so you can have runtime surprise -+// according the library versions - # define SCANF_PREFIX "a" - # define SCANF_STRING(s) (&s) - #else diff --git a/tools/genext2fs/patches/200-autoconf.patch b/tools/genext2fs/patches/200-autoconf.patch deleted file mode 100644 index b3317bdd10..0000000000 --- a/tools/genext2fs/patches/200-autoconf.patch +++ /dev/null @@ -1,13 +0,0 @@ -Index: genext2fs/m4/ac_func_scanf_can_malloc.m4 -=================================================================== ---- genext2fs.orig/m4/ac_func_scanf_can_malloc.m4 2011-09-03 21:28:49.000000000 +0200 -+++ genext2fs/m4/ac_func_scanf_can_malloc.m4 2011-09-03 21:29:41.000000000 +0200 -@@ -9,7 +9,7 @@ - # -------------------------------------- - AC_DEFUN([AC_FUNC_SCANF_CAN_MALLOC], - [ AC_CHECK_HEADERS([stdlib.h]) -- AC_CACHE_CHECK([whether scanf can malloc], [ac_scanf_can_malloc], -+ AC_CACHE_CHECK([whether scanf can malloc], [ac_cv_func_scanf_can_malloc], - [ AC_RUN_IFELSE( - [ AC_LANG_PROGRAM( - [ diff --git a/tools/genext2fs/patches/300-blocksize-creator.patch b/tools/genext2fs/patches/300-blocksize-creator.patch deleted file mode 100644 index 97a4836eeb..0000000000 --- a/tools/genext2fs/patches/300-blocksize-creator.patch +++ /dev/null @@ -1,558 +0,0 @@ -Index: genext2fs/genext2fs.c -=================================================================== ---- genext2fs.orig/genext2fs.c 2011-09-03 14:21:17.000000000 +0200 -+++ genext2fs/genext2fs.c 2011-09-03 14:21:17.000000000 +0200 -@@ -151,13 +151,24 @@ - - // block size - --#define BLOCKSIZE 1024 -+static int blocksize = 1024; -+ -+#define BLOCKSIZE blocksize - #define BLOCKS_PER_GROUP 8192 - #define INODES_PER_GROUP 8192 - /* Percentage of blocks that are reserved.*/ - #define RESERVED_BLOCKS 5/100 - #define MAX_RESERVED_BLOCKS 25/100 - -+/* The default value for s_creator_os. */ -+#if defined(__GNU__) -+# define CREATOR_OS 1 /* Hurd */ -+#elif defined(__FreeBSD__) -+# define CREATOR_OS 3 /* FreeBSD */ -+#else -+# define CREATOR_OS 0 /* Linux */ -+#endif -+ - - // inode block size (why is it != BLOCKSIZE ?!?) - /* The field i_blocks in the ext2 inode stores the number of data blocks -@@ -239,10 +250,10 @@ - (fs)->sb.s_blocks_per_group - 1) / (fs)->sb.s_blocks_per_group) - - // Get group block bitmap (bbm) given the group number --#define GRP_GET_GROUP_BBM(fs,grp) ( get_blk((fs),(fs)->gd[(grp)].bg_block_bitmap) ) -+#define GRP_GET_GROUP_BBM(fs,grp) ( get_blk((fs), get_gd((fs),(grp))->bg_block_bitmap) ) - - // Get group inode bitmap (ibm) given the group number --#define GRP_GET_GROUP_IBM(fs,grp) ( get_blk((fs),(fs)->gd[(grp)].bg_inode_bitmap) ) -+#define GRP_GET_GROUP_IBM(fs,grp) ( get_blk((fs), get_gd((fs),(grp))->bg_inode_bitmap) ) - - // Given an inode number find the group it belongs to - #define GRP_GROUP_OF_INODE(fs,nod) ( ((nod)-1) / (fs)->sb.s_inodes_per_group) -@@ -532,7 +543,7 @@ - char d_name[0]; - } directory; - --typedef uint8 block[BLOCKSIZE]; -+typedef uint8 *block; - - /* blockwalker fields: - The blockwalker is used to access all the blocks of a file (including -@@ -571,16 +582,12 @@ - - - /* Filesystem structure that support groups */ --#if BLOCKSIZE == 1024 - typedef struct - { -- block zero; // The famous block 0 -- superblock sb; // The superblock -- groupdescriptor gd[0]; // The group descriptors -+ uint8 zero[1024]; // Room for bootloader stuff -+ superblock sb; // The superblock, always at 1024 -+ // group descriptors come next, see get_gd() below - } filesystem; --#else --#error UNHANDLED BLOCKSIZE --#endif - - // now the endianness swap - -@@ -820,6 +827,14 @@ - return (uint8*)fs + blk*BLOCKSIZE; - } - -+// the group descriptors are aligned on the block size -+static inline groupdescriptor * -+get_gd(filesystem *fs, int no) -+{ -+ int gdblk = (sizeof (filesystem) + BLOCKSIZE - 1) / BLOCKSIZE; -+ return ((groupdescriptor *) get_blk(fs, gdblk)) + no; -+} -+ - // return a given inode from a filesystem - static inline inode * - get_nod(filesystem *fs, uint32 nod) -@@ -829,7 +844,7 @@ - - offset = GRP_IBM_OFFSET(fs,nod); - grp = GRP_GROUP_OF_INODE(fs,nod); -- itab = (inode *)get_blk(fs, fs->gd[grp].bg_inode_table); -+ itab = (inode *)get_blk(fs, get_gd(fs,grp)->bg_inode_table); - return itab+offset-1; - } - -@@ -875,18 +890,18 @@ - - grp = GRP_GROUP_OF_INODE(fs,nod); - nbgroups = GRP_NBGROUPS(fs); -- if(!(bk = allocate(get_blk(fs,fs->gd[grp].bg_block_bitmap), 0))) { -+ if(!(bk = allocate(GRP_GET_GROUP_BBM(fs, grp), 0))) { - for(grp=0;grpgd[grp].bg_block_bitmap),0); -+ bk = allocate(GRP_GET_GROUP_BBM(fs, grp), 0); - grp--; - } - if (!bk) - error_msg_and_die("couldn't allocate a block (no free space)"); -- if(!(fs->gd[grp].bg_free_blocks_count--)) -+ if(!(get_gd(fs, grp)->bg_free_blocks_count--)) - error_msg_and_die("group descr %d. free blocks count == 0 (corrupted fs?)",grp); - if(!(fs->sb.s_free_blocks_count--)) - error_msg_and_die("superblock free blocks count == 0 (corrupted fs?)"); -- return fs->sb.s_blocks_per_group*grp + bk; -+ return fs->sb.s_first_data_block + fs->sb.s_blocks_per_group*grp + (bk-1); - } - - // free a block -@@ -897,8 +912,8 @@ - - grp = bk / fs->sb.s_blocks_per_group; - bk %= fs->sb.s_blocks_per_group; -- deallocate(get_blk(fs,fs->gd[grp].bg_block_bitmap), bk); -- fs->gd[grp].bg_free_blocks_count++; -+ deallocate(GRP_GET_GROUP_BBM(fs, grp), bk); -+ get_gd(fs, grp)->bg_free_blocks_count++; - fs->sb.s_free_blocks_count++; - } - -@@ -918,16 +933,16 @@ - /* We do it for all inodes. */ - avefreei = fs->sb.s_free_inodes_count / nbgroups; - for(grp=0; grpgd[grp].bg_free_inodes_count < avefreei || -- fs->gd[grp].bg_free_inodes_count == 0) -+ if (get_gd(fs, grp)->bg_free_inodes_count < avefreei || -+ get_gd(fs, grp)->bg_free_inodes_count == 0) - continue; - if (!best_group || -- fs->gd[grp].bg_free_blocks_count > fs->gd[best_group].bg_free_blocks_count) -+ get_gd(fs, grp)->bg_free_blocks_count > get_gd(fs, best_group)->bg_free_blocks_count) - best_group = grp; - } -- if (!(nod = allocate(get_blk(fs,fs->gd[best_group].bg_inode_bitmap),0))) -+ if (!(nod = allocate(GRP_GET_GROUP_IBM(fs, best_group), 0))) - error_msg_and_die("couldn't allocate an inode (no free inode)"); -- if(!(fs->gd[best_group].bg_free_inodes_count--)) -+ if(!(get_gd(fs, best_group)->bg_free_inodes_count--)) - error_msg_and_die("group descr. free blocks count == 0 (corrupted fs?)"); - if(!(fs->sb.s_free_inodes_count--)) - error_msg_and_die("superblock free blocks count == 0 (corrupted fs?)"); -@@ -1390,7 +1405,7 @@ - case FM_IFDIR: - add2dir(fs, nod, nod, "."); - add2dir(fs, nod, parent_nod, ".."); -- fs->gd[GRP_GROUP_OF_INODE(fs,nod)].bg_used_dirs_count++; -+ get_gd(fs, GRP_GROUP_OF_INODE(fs,nod))->bg_used_dirs_count++; - break; - } - } -@@ -1860,7 +1875,7 @@ - swap_nod(nod); - } - for(i=0;igd[i])); -+ swap_gd(get_gd(fs, i)); - swap_sb(&fs->sb); - } - -@@ -1870,7 +1885,7 @@ - uint32 i; - swap_sb(&fs->sb); - for(i=0;igd[i])); -+ swap_gd(get_gd(fs, i)); - for(i = 1; i < fs->sb.s_inodes_count; i++) - { - inode *nod = get_nod(fs, i); -@@ -1895,7 +1910,8 @@ - - // initialize an empty filesystem - static filesystem * --init_fs(int nbblocks, int nbinodes, int nbresrvd, int holes, uint32 fs_timestamp) -+init_fs(int nbblocks, int nbinodes, int nbresrvd, int holes, -+ uint32 fs_timestamp, uint32 creator_os) - { - uint32 i; - filesystem *fs; -@@ -1921,10 +1937,14 @@ - */ - min_nbgroups = (nbinodes + INODES_PER_GROUP - 1) / INODES_PER_GROUP; - -+ /* On filesystems with 1k block size, the bootloader area uses a full -+ * block. For 2048 and up, the superblock can be fitted into block 0. -+ */ -+ first_block = (BLOCKSIZE == 1024); -+ - /* nbblocks is the total number of blocks in the filesystem. - * a block group can have no more than 8192 blocks. - */ -- first_block = (BLOCKSIZE == 1024); - nbgroups = (nbblocks - first_block + BLOCKS_PER_GROUP - 1) / BLOCKS_PER_GROUP; - if(nbgroups < min_nbgroups) nbgroups = min_nbgroups; - nbblocks_per_group = rndup((nbblocks - first_block + nbgroups - 1)/nbgroups, 8); -@@ -1936,10 +1956,10 @@ - gdsz = rndup(nbgroups*sizeof(groupdescriptor),BLOCKSIZE)/BLOCKSIZE; - itblsz = nbinodes_per_group * sizeof(inode)/BLOCKSIZE; - overhead_per_group = 3 /*sb,bbm,ibm*/ + gdsz + itblsz; -- if((uint32)nbblocks - 1 < overhead_per_group * nbgroups) -- error_msg_and_die("too much overhead, try fewer inodes or more blocks. Note: options have changed, see --help or the man page."); -- free_blocks = nbblocks - overhead_per_group*nbgroups - 1 /*boot block*/; -+ free_blocks = nbblocks - overhead_per_group*nbgroups - first_block; - free_blocks_per_group = nbblocks_per_group - overhead_per_group; -+ if(free_blocks < 0) -+ error_msg_and_die("too much overhead, try fewer inodes or more blocks. Note: options have changed, see --help or the man page."); - - if(!(fs = (filesystem*)calloc(nbblocks, BLOCKSIZE))) - error_msg_and_die("not enough memory for filesystem"); -@@ -1959,28 +1979,31 @@ - fs->sb.s_wtime = fs_timestamp; - fs->sb.s_magic = EXT2_MAGIC_NUMBER; - fs->sb.s_lastcheck = fs_timestamp; -+ fs->sb.s_creator_os = creator_os; - - // set up groupdescriptors -- for(i=0, bbmpos=gdsz+2, ibmpos=bbmpos+1, itblpos=ibmpos+1; -+ for(i=0, bbmpos=first_block+1+gdsz, ibmpos=bbmpos+1, itblpos=ibmpos+1; - i free_blocks_per_group) { -- fs->gd[i].bg_free_blocks_count = free_blocks_per_group; -+ gd->bg_free_blocks_count = free_blocks_per_group; - free_blocks -= free_blocks_per_group; - } else { -- fs->gd[i].bg_free_blocks_count = free_blocks; -+ gd->bg_free_blocks_count = free_blocks; - free_blocks = 0; // this is the last block group - } - if(i) -- fs->gd[i].bg_free_inodes_count = nbinodes_per_group; -+ gd->bg_free_inodes_count = nbinodes_per_group; - else -- fs->gd[i].bg_free_inodes_count = nbinodes_per_group - -+ gd->bg_free_inodes_count = nbinodes_per_group - - EXT2_FIRST_INO + 2; -- fs->gd[i].bg_used_dirs_count = 0; -- fs->gd[i].bg_block_bitmap = bbmpos; -- fs->gd[i].bg_inode_bitmap = ibmpos; -- fs->gd[i].bg_inode_table = itblpos; -+ gd->bg_used_dirs_count = 0; -+ gd->bg_block_bitmap = bbmpos; -+ gd->bg_inode_bitmap = ibmpos; -+ gd->bg_inode_table = itblpos; - } - - /* Mark non-filesystem blocks and inodes as allocated */ -@@ -1988,9 +2011,9 @@ - for(i = 0; igd[i].bg_block_bitmap); -+ bbm = GRP_GET_GROUP_BBM(fs, i); - //non-filesystem blocks -- for(j = fs->gd[i].bg_free_blocks_count -+ for(j = get_gd(fs, i)->bg_free_blocks_count - + overhead_per_group + 1; j <= BLOCKSIZE * 8; j++) - allocate(bbm, j); - //system blocks -@@ -1998,7 +2021,7 @@ - allocate(bbm, j); - - /* Inode bitmap */ -- ibm = get_blk(fs,fs->gd[i].bg_inode_bitmap); -+ ibm = GRP_GET_GROUP_IBM(fs, i); - //non-filesystem inodes - for(j = fs->sb.s_inodes_per_group+1; j <= BLOCKSIZE * 8; j++) - allocate(ibm, j); -@@ -2012,9 +2035,9 @@ - // make root inode and directory - /* We have groups now. Add the root filesystem in group 0 */ - /* Also increment the directory count for group 0 */ -- fs->gd[0].bg_free_inodes_count--; -- fs->gd[0].bg_used_dirs_count = 1; -- itab0 = (inode *)get_blk(fs,fs->gd[0].bg_inode_table); -+ get_gd(fs, 0)->bg_free_inodes_count--; -+ get_gd(fs, 0)->bg_used_dirs_count = 1; -+ itab0 = (inode *)get_blk(fs, get_gd(fs,0)->bg_inode_table); - itab0[EXT2_ROOT_INO-1].i_mode = FM_IFDIR | FM_IRWXU | FM_IRGRP | FM_IROTH | FM_IXGRP | FM_IXOTH; - itab0[EXT2_ROOT_INO-1].i_ctime = fs_timestamp; - itab0[EXT2_ROOT_INO-1].i_mtime = fs_timestamp; -@@ -2338,8 +2361,9 @@ - for (i = 0; i < GRP_NBGROUPS(fs); i++) { - printf("Group No: %d\n", i+1); - printf("block bitmap: block %d,inode bitmap: block %d, inode table: block %d\n", -- fs->gd[i].bg_block_bitmap, fs->gd[i].bg_inode_bitmap, -- fs->gd[i].bg_inode_table); -+ get_gd(fs, i)->bg_block_bitmap, -+ get_gd(fs, i)->bg_inode_bitmap, -+ get_gd(fs, i)->bg_inode_table); - printf("block bitmap allocation:\n"); - print_bm(GRP_GET_GROUP_BBM(fs, i),fs->sb.s_blocks_per_group); - printf("inode bitmap allocation:\n"); -@@ -2421,10 +2445,12 @@ - " -x, --starting-image \n" - " -d, --root \n" - " -D, --devtable \n" -+ " -B, --block-size \n" - " -b, --size-in-blocks \n" - " -i, --bytes-per-inode \n" - " -N, --number-of-inodes \n" - " -m, --reserved-percentage \n" -+ " -o, --creator-os 'linux', 'hurd', 'freebsd' or a numerical value.\n" - " -g, --block-map Generate a block map file for this path.\n" - " -e, --fill-value Fill unallocated blocks with value.\n" - " -z, --allow-holes Allow files with holes.\n" -@@ -2446,6 +2472,29 @@ - extern char* optarg; - extern int optind, opterr, optopt; - -+// parse the value for -o -+int -+lookup_creator_os(const char *name) -+{ -+ static const char *const creators[] = -+ {"linux", "hurd", "2", "freebsd", NULL}; -+ char *endptr; -+ int i; -+ -+ // numerical value ? -+ i = strtol(name, &endptr, 0); -+ if(name[0] && *endptr == '\0') -+ return i; -+ -+ // symbolic name ? -+ for(i=0; creators[i]; i++) -+ if(strcasecmp(creators[i], name) == 0) -+ return i; -+ -+ // whatever ? -+ return -1; -+} -+ - int - main(int argc, char **argv) - { -@@ -2455,6 +2504,7 @@ - float bytes_per_inode = -1; - float reserved_frac = -1; - int fs_timestamp = -1; -+ int creator_os = CREATOR_OS; - char * fsout = "-"; - char * fsin = 0; - char * dopt[MAX_DOPT]; -@@ -2478,10 +2528,12 @@ - { "starting-image", required_argument, NULL, 'x' }, - { "root", required_argument, NULL, 'd' }, - { "devtable", required_argument, NULL, 'D' }, -+ { "block-size", required_argument, NULL, 'B' }, - { "size-in-blocks", required_argument, NULL, 'b' }, - { "bytes-per-inode", required_argument, NULL, 'i' }, - { "number-of-inodes", required_argument, NULL, 'N' }, - { "reserved-percentage", required_argument, NULL, 'm' }, -+ { "creator-os", required_argument, NULL, 'o' }, - { "block-map", required_argument, NULL, 'g' }, - { "fill-value", required_argument, NULL, 'e' }, - { "allow-holes", no_argument, NULL, 'z' }, -@@ -2497,11 +2549,11 @@ - - app_name = argv[0]; - -- while((c = getopt_long(argc, argv, "x:d:D:b:i:N:m:g:e:zfqUPhVv", longopts, NULL)) != EOF) { -+ while((c = getopt_long(argc, argv, "x:d:D:B:b:i:N:m:o:g:e:zfqUPhVv", longopts, NULL)) != EOF) { - #else - app_name = argv[0]; - -- while((c = getopt(argc, argv, "x:d:D:b:i:N:m:g:e:zfqUPhVv")) != EOF) { -+ while((c = getopt(argc, argv, "x:d:D:B:b:i:N:m:o:g:e:zfqUPhVv")) != EOF) { - #endif /* HAVE_GETOPT_LONG */ - switch(c) - { -@@ -2512,6 +2564,9 @@ - case 'D': - dopt[didx++] = optarg; - break; -+ case 'B': -+ blocksize = SI_atof(optarg); -+ break; - case 'b': - nbblocks = SI_atof(optarg); - break; -@@ -2524,6 +2579,9 @@ - case 'm': - reserved_frac = SI_atof(optarg) / 100; - break; -+ case 'o': -+ creator_os = lookup_creator_os(optarg); -+ break; - case 'g': - gopt[gidx++] = optarg; - break; -@@ -2567,6 +2625,11 @@ - error_msg_and_die("Not enough arguments. Try --help or else see the man page."); - fsout = argv[optind]; - -+ if(blocksize != 1024 && blocksize != 2048 && blocksize != 4096) -+ error_msg_and_die("Valid block sizes: 1024, 2048 or 4096."); -+ if(creator_os < 0) -+ error_msg_and_die("Creator OS unknown."); -+ - hdlinks.hdl = (struct hdlink_s *)malloc(hdlink_cnt * sizeof(struct hdlink_s)); - if (!hdlinks.hdl) - error_msg_and_die("Not enough memory"); -@@ -2611,7 +2674,8 @@ - } - if(fs_timestamp == -1) - fs_timestamp = time(NULL); -- fs = init_fs(nbblocks, nbinodes, nbresrvd, holes, fs_timestamp); -+ fs = init_fs(nbblocks, nbinodes, nbresrvd, holes, -+ fs_timestamp, creator_os); - } - - populate_fs(fs, dopt, didx, squash_uids, squash_perms, fs_timestamp, NULL); -Index: genext2fs/test-gen.lib -=================================================================== ---- genext2fs.orig/test-gen.lib 2011-09-03 13:40:35.000000000 +0200 -+++ genext2fs/test-gen.lib 2011-09-03 14:21:17.000000000 +0200 -@@ -8,7 +8,7 @@ - # Creates an image with a file of given size - # Usage: dgen file-size number-of-blocks - dgen () { -- size=$1; blocks=$2 -+ size=$1; blocks=$2; blocksz=$3; - rm -rf test - mkdir -p test - cd test -@@ -20,7 +20,7 @@ - chmod 777 file.$1 - TZ=UTC-11 touch -t 200502070321.43 file.$1 . - cd .. -- ./genext2fs -N 17 -b $blocks -d test -f -q ext2.img -+ ./genext2fs -B $blocksz -N 17 -b $blocks -d test -f -o Linux -q ext2.img - } - - # fgen - Exercises the -f spec-file option of genext2fs -@@ -31,7 +31,7 @@ - mkdir -p test - cp $fname test - TZ=UTC-11 touch -t 200502070321.43 test/$fname -- ./genext2fs -N 92 -b $blocks -D test/$fname -f ext2.img -+ ./genext2fs -N 92 -b $blocks -D test/$fname -f -o Linux ext2.img - } - - # gen_cleanup - Remove the files generated by the above functions -Index: genext2fs/test-mount.sh -=================================================================== ---- genext2fs.orig/test-mount.sh 2011-09-03 13:40:35.000000000 +0200 -+++ genext2fs/test-mount.sh 2011-09-03 14:21:17.000000000 +0200 -@@ -33,9 +33,9 @@ - # and returns the command line with which to invoke dtest() - # Usage: dtest-mount file-size number-of-blocks - dtest_mount () { -- size=$1; blocks=$2 -- echo Testing with file of size $size -- dgen $size $blocks -+ size=$1; blocks=$2; blocksz=$3; -+ echo Testing $blocks blocks of $blocksz bytes with file of size $size -+ dgen $size $blocks $blocksz - /sbin/e2fsck -fn ext2.img || fail - mkdir -p mnt - mount -t ext2 -o ro,loop ext2.img mnt || fail -@@ -44,7 +44,7 @@ - awk '{print $5}'`" ] ; then - fail - fi -- pass dtest $size $blocks -+ pass dtest $size $blocks $blocksz - } - - # ftest-mount - Exercise the -f spec-file option of genext2fs -@@ -75,13 +75,21 @@ - pass ftest $fname $blocks - } - --dtest_mount 0 4096 --dtest_mount 0 8193 --dtest_mount 0 8194 --dtest_mount 1 4096 --dtest_mount 12288 4096 --dtest_mount 274432 4096 --dtest_mount 8388608 9000 --dtest_mount 16777216 20000 -+dtest_mount 0 4096 1024 -+dtest_mount 0 2048 2048 -+dtest_mount 0 1024 4096 -+dtest_mount 0 8193 1024 -+dtest_mount 0 8194 1024 -+dtest_mount 0 8193 4096 -+dtest_mount 0 8194 2048 -+dtest_mount 1 4096 1024 -+dtest_mount 1 1024 4096 -+dtest_mount 12288 4096 1024 -+dtest_mount 274432 4096 1024 -+dtest_mount 8388608 9000 1024 -+dtest_mount 8388608 4500 2048 -+dtest_mount 8388608 2250 4096 -+dtest_mount 16777216 20000 1024 -+dtest_mount 16777216 10000 2048 - - ftest_mount device_table.txt 4096 -Index: genext2fs/test.sh -=================================================================== ---- genext2fs.orig/test.sh 2011-09-03 13:40:35.000000000 +0200 -+++ genext2fs/test.sh 2011-09-03 14:21:17.000000000 +0200 -@@ -30,9 +30,9 @@ - # Creates an image with a file of given size and verifies it - # Usage: dtest file-size number-of-blocks correct-checksum - dtest () { -- size=$1; blocks=$2; checksum=$3 -+ size=$1; blocks=$2; blocksz=$3; checksum=$4 - echo Testing with file of size $size -- dgen $size $blocks -+ dgen $size $blocks $blocksz - md5cmp $checksum - gen_cleanup - } -@@ -53,12 +53,20 @@ - # replace the following lines with the output of - # sudo sh test-mount.sh|grep test - --dtest 0 4096 3bc6424b8fcd51a0de34ee59d91d5f16 --dtest 0 8193 f174804f6b433b552706cbbfc60c416d --dtest 0 8194 4855a55d0cbdc44584634df49ebd5711 --dtest 1 4096 09c569b6bfb45222c729c42d04d5451f --dtest 12288 4096 61febcbfbf32024ef99103fcdc282c39 --dtest 274432 4096 0c517803552c55c1806e4220b0a0164f --dtest 8388608 9000 e0e5ea15bced10ab486d8135584b5d8e --dtest 16777216 20000 fdf636eb905ab4dc1bf76dce5ac5d209 -+dtest 0 4096 1024 3bc6424b8fcd51a0de34ee59d91d5f16 -+dtest 0 2048 2048 230afa16496df019878cc2370c661cdc -+dtest 0 1024 4096 ebff5eeb38b70f3f1cd081e60eb44561 -+dtest 0 8193 1024 f174804f6b433b552706cbbfc60c416d -+dtest 0 8194 1024 4855a55d0cbdc44584634df49ebd5711 -+dtest 0 8193 4096 c493679698418ec7e6552005e2d2a6d8 -+dtest 0 8194 2048 ec13f328fa7543563f35f494bddc059c -+dtest 1 4096 1024 09c569b6bfb45222c729c42d04d5451f -+dtest 1 1024 4096 d318a326fdc907810ae9e6b0a20e9b06 -+dtest 12288 4096 1024 61febcbfbf32024ef99103fcdc282c39 -+dtest 274432 4096 1024 0c517803552c55c1806e4220b0a0164f -+dtest 8388608 9000 1024 e0e5ea15bced10ab486d8135584b5d8e -+dtest 8388608 4500 2048 39f4d537a72f5053fd6891721c59680d -+dtest 8388608 2250 4096 1d697fa4bc2cfffe02ac91edfadc40bf -+dtest 16777216 20000 1024 fdf636eb905ab4dc1bf76dce5ac5d209 -+dtest 16777216 10000 2048 f9824a81ea5e74fdf469c097927c292b - ftest device_table.txt 4096 a0af06d944b11d2902dfd705484c64cc diff --git a/tools/genext2fs/patches/400-byteswap_fix.patch b/tools/genext2fs/patches/400-byteswap_fix.patch deleted file mode 100644 index 7b3c00b5ee..0000000000 --- a/tools/genext2fs/patches/400-byteswap_fix.patch +++ /dev/null @@ -1,44 +0,0 @@ -Index: genext2fs/genext2fs.c -=================================================================== ---- genext2fs.orig/genext2fs.c 2011-11-29 17:36:06.000000000 +0100 -+++ genext2fs/genext2fs.c 2011-11-29 17:37:37.000000000 +0100 -@@ -1779,7 +1779,8 @@ - assert(nod->i_block[EXT2_DIND_BLOCK] != 0); - for(i = 0; i < BLOCKSIZE/4; i++) - if(nblk > EXT2_IND_BLOCK + BLOCKSIZE/4 + (BLOCKSIZE/4)*i ) -- swap_block(get_blk(fs, ((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i])); -+ if (((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i]) -+ swap_block(get_blk(fs, ((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i])); - swap_block(get_blk(fs, nod->i_block[EXT2_DIND_BLOCK])); - if(nblk <= EXT2_IND_BLOCK + BLOCKSIZE/4 + BLOCKSIZE/4 * BLOCKSIZE/4) - return; -@@ -1792,7 +1793,8 @@ - (BLOCKSIZE/4)*(BLOCKSIZE/4) + - i*(BLOCKSIZE/4)*(BLOCKSIZE/4) + - j*(BLOCKSIZE/4)) ) -- swap_block(get_blk(fs,b2[j])); -+ if (b2[j]) -+ swap_block(get_blk(fs,b2[j])); - else { - done = 1; - break; -@@ -1825,7 +1827,8 @@ - swap_block(get_blk(fs, nod->i_block[EXT2_DIND_BLOCK])); - for(i = 0; i < BLOCKSIZE/4; i++) - if(nblk > EXT2_IND_BLOCK + BLOCKSIZE/4 + (BLOCKSIZE/4)*i ) -- swap_block(get_blk(fs, ((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i])); -+ if (((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i]) -+ swap_block(get_blk(fs, ((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i])); - if(nblk <= EXT2_IND_BLOCK + BLOCKSIZE/4 + BLOCKSIZE/4 * BLOCKSIZE/4) - return; - /* Adding support for triple indirection */ -@@ -1839,7 +1842,8 @@ - (BLOCKSIZE/4)*(BLOCKSIZE/4) + - i*(BLOCKSIZE/4)*(BLOCKSIZE/4) + - j*(BLOCKSIZE/4)) ) -- swap_block(get_blk(fs,b2[j])); -+ if (b2[j]) -+ swap_block(get_blk(fs,b2[j])); - else { - done = 1; - break; diff --git a/tools/mkimage/Makefile b/tools/mkimage/Makefile index a7c98e755e..10fe6eea43 100644 --- a/tools/mkimage/Makefile +++ b/tools/mkimage/Makefile @@ -7,14 +7,14 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mkimage -PKG_VERSION:=2022.07 +PKG_VERSION:=2022.10 PKG_SOURCE:=u-boot-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:= \ https://mirror.cyberbits.eu/u-boot \ https://ftp.denx.de/pub/u-boot \ ftp://ftp.denx.de/pub/u-boot -PKG_HASH:=92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e +PKG_HASH:=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8 HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/u-boot-$(PKG_VERSION) diff --git a/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch b/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch index 62300af266..c8747ae154 100644 --- a/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch +++ b/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao --- a/tools/mtk_image.c +++ b/tools/mtk_image.c -@@ -432,6 +432,25 @@ static int mtk_image_vrec_header(struct +@@ -480,6 +480,25 @@ static int mtk_image_vrec_header(struct return SHA256_SUM_LEN; } @@ -41,7 +41,7 @@ Signed-off-by: Weijie Gao static int mtk_image_verify_gen_header(const uint8_t *ptr, int print) { union gen_boot_header *gbh = (union gen_boot_header *)ptr; -@@ -494,21 +513,7 @@ static int mtk_image_verify_gen_header(c +@@ -542,21 +561,7 @@ static int mtk_image_verify_gen_header(c gfh = (struct gfh_header *)(ptr + gfh_offset); @@ -64,7 +64,7 @@ Signed-off-by: Weijie Gao } static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) -@@ -562,21 +567,7 @@ static int mtk_image_verify_nand_header( +@@ -610,21 +615,7 @@ static int mtk_image_verify_nand_header( gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); @@ -86,4 +86,4 @@ Signed-off-by: Weijie Gao + return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); } - static int mtk_image_verify_header(unsigned char *ptr, int image_size, + static uint32_t crc32be_cal(const void *data, size_t length) diff --git a/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch b/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch index 0b4013864e..9a5332f695 100644 --- a/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch +++ b/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch @@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao $(AES_OBJS-y) --- a/tools/mtk_image.c +++ b/tools/mtk_image.c -@@ -10,216 +10,7 @@ +@@ -12,216 +12,7 @@ #include #include "imagetool.h" #include "mtk_image.h" @@ -252,7 +252,7 @@ Signed-off-by: Weijie Gao static const struct brom_img_type { const char *name; -@@ -258,6 +49,7 @@ static char lk_name[32] = "U-Boot"; +@@ -264,6 +55,7 @@ static uint32_t crc32tbl[256]; /* NAND header selected by user */ static const union nand_boot_header *hdr_nand; @@ -260,7 +260,7 @@ Signed-off-by: Weijie Gao /* GFH header + 2 * 4KB pages of NAND */ static char hdr_tmp[sizeof(struct gfh_header) + 0x2000]; -@@ -361,12 +153,7 @@ static int mtk_brom_parse_imagename(cons +@@ -402,12 +194,7 @@ static int mtk_brom_parse_imagename(cons } /* parse nand header type */ @@ -274,7 +274,7 @@ Signed-off-by: Weijie Gao /* parse device header offset */ if (hdr_offs && hdr_offs[0]) -@@ -391,6 +178,9 @@ static int mtk_brom_parse_imagename(cons +@@ -432,6 +219,9 @@ static int mtk_brom_parse_imagename(cons return -EINVAL; } @@ -284,7 +284,7 @@ Signed-off-by: Weijie Gao return 0; } -@@ -420,7 +210,7 @@ static int mtk_image_vrec_header(struct +@@ -468,7 +258,7 @@ static int mtk_image_vrec_header(struct } if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) @@ -293,7 +293,7 @@ Signed-off-by: Weijie Gao else tparams->header_size = sizeof(struct gen_device_header); -@@ -518,16 +308,17 @@ static int mtk_image_verify_gen_header(c +@@ -566,16 +356,17 @@ static int mtk_image_verify_gen_header(c static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) { @@ -316,7 +316,7 @@ Signed-off-by: Weijie Gao if (strcmp(bh->name, BRLYT_NAME)) return -1; -@@ -538,34 +329,23 @@ static int mtk_image_verify_nand_header( +@@ -586,34 +377,23 @@ static int mtk_image_verify_nand_header( if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) bootmedia = "Parallel NAND"; else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) @@ -358,25 +358,25 @@ Signed-off-by: Weijie Gao return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); } -@@ -581,7 +361,7 @@ static int mtk_image_verify_header(unsig - - img_size = image_size; +@@ -713,7 +493,7 @@ static int mtk_image_verify_header(unsig + if (image_get_magic(hdr) == IH_MAGIC) + return mtk_image_verify_mt7621_header(ptr, 0); - if (!strcmp((char *)ptr, NAND_BOOT_NAME)) + if (is_mtk_nand_header(ptr)) return mtk_image_verify_nand_header(ptr, 0); else return mtk_image_verify_gen_header(ptr, 0); -@@ -601,7 +381,7 @@ static void mtk_image_print_header(const - - printf("Image Type: MediaTek BootROM Loadable Image\n"); +@@ -739,7 +519,7 @@ static void mtk_image_print_header(const + return; + } - if (!strcmp((char *)ptr, NAND_BOOT_NAME)) + if (is_mtk_nand_header(ptr)) mtk_image_verify_nand_header(ptr, 1); else mtk_image_verify_gen_header(ptr, 1); -@@ -732,36 +512,33 @@ static void mtk_image_set_gen_header(voi +@@ -870,36 +650,33 @@ static void mtk_image_set_gen_header(voi static void mtk_image_set_nand_header(void *ptr, off_t filesize, uint32_t loadaddr) { @@ -431,7 +431,7 @@ Signed-off-by: Weijie Gao + put_hash((uint8_t *)gfh, filesize - hdr_nand_size - SHA256_SUM_LEN); } - static void mtk_image_set_header(void *ptr, struct stat *sbuf, int ifd, + static void mtk_image_set_mt7621_header(void *ptr, off_t filesize, --- a/tools/mtk_image.h +++ b/tools/mtk_image.h @@ -26,31 +26,6 @@ union gen_boot_header { diff --git a/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch b/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch index 12ff7f32de..0ce095998f 100644 --- a/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch +++ b/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch @@ -19,7 +19,7 @@ Signed-off-by: Weijie Gao --- a/tools/mtk_image.c +++ b/tools/mtk_image.c -@@ -31,6 +31,9 @@ static const struct brom_img_type { +@@ -33,6 +33,9 @@ static const struct brom_img_type { }, { .name = "snand", .type = BRLYT_TYPE_SNAND @@ -29,8 +29,8 @@ Signed-off-by: Weijie Gao } }; -@@ -48,7 +51,7 @@ static bool is_arm64_image; - static char lk_name[32] = "U-Boot"; +@@ -54,7 +57,7 @@ static char lk_name[32] = "U-Boot"; + static uint32_t crc32tbl[256]; /* NAND header selected by user */ -static const union nand_boot_header *hdr_nand; @@ -38,7 +38,7 @@ Signed-off-by: Weijie Gao static uint32_t hdr_nand_size; /* GFH header + 2 * 4KB pages of NAND */ -@@ -318,20 +321,26 @@ static int mtk_image_verify_nand_header( +@@ -366,20 +369,26 @@ static int mtk_image_verify_nand_header( if (ret < 0) return ret; diff --git a/tools/mkimage/patches/030-allow-to-use-different-magic.patch b/tools/mkimage/patches/030-allow-to-use-different-magic.patch index b97cd819cc..591edf24ea 100644 --- a/tools/mkimage/patches/030-allow-to-use-different-magic.patch +++ b/tools/mkimage/patches/030-allow-to-use-different-magic.patch @@ -2,7 +2,7 @@ This patch makes it possible to set a custom image magic. --- a/tools/mkimage.c +++ b/tools/mkimage.c -@@ -25,6 +25,7 @@ static struct image_tool_params params = +@@ -26,6 +26,7 @@ static struct image_tool_params params = .arch = IH_ARCH_PPC, .type = IH_TYPE_KERNEL, .comp = IH_COMP_GZIP, @@ -10,7 +10,7 @@ This patch makes it possible to set a custom image magic. .dtc = MKIMAGE_DEFAULT_DTC_OPTIONS, .imagename = "", .imagename2 = "", -@@ -88,11 +89,12 @@ static void usage(const char *msg) +@@ -89,11 +90,12 @@ static void usage(const char *msg) " -q ==> quiet\n", params.cmdname); fprintf(stderr, @@ -24,16 +24,16 @@ This patch makes it possible to set a custom image magic. " -a ==> set load address to 'addr' (hex)\n" " -e ==> set entry point to 'ep' (hex)\n" " -n ==> set image name to 'name'\n" -@@ -163,7 +165,7 @@ static void process_args(int argc, char - int opt; +@@ -159,7 +161,7 @@ static int add_content(int type, const c + } - while ((opt = getopt(argc, argv, -- "a:A:b:B:c:C:d:D:e:Ef:FG:k:i:K:ln:N:p:o:O:rR:qstT:vVx")) != -1) { -+ "a:A:b:B:c:C:d:D:e:Ef:FG:k:i:K:lM:n:N:p:o:O:rR:qstT:vVx")) != -1) { - switch (opt) { - case 'a': - params.addr = strtoull(optarg, &ptr, 16); -@@ -254,6 +256,14 @@ static void process_args(int argc, char + static const char optstring[] = +- "a:A:b:B:c:C:d:D:e:Ef:Fg:G:i:k:K:ln:N:o:O:p:qrR:stT:vVx"; ++ "a:A:b:B:c:C:d:D:e:Ef:Fg:G:i:k:K:lM:n:N:o:O:p:qrR:stT:vVx"; + + static const struct option longopts[] = { + { "load-address", required_argument, NULL, 'a' }, +@@ -298,6 +300,14 @@ static void process_args(int argc, char case 'l': params.lflag = 1; break; diff --git a/tools/mtools/Makefile b/tools/mtools/Makefile index 74007a88d0..964ef9db33 100644 --- a/tools/mtools/Makefile +++ b/tools/mtools/Makefile @@ -7,11 +7,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mtools -PKG_VERSION:=4.0.40 +PKG_VERSION:=4.0.41 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:=@GNU/$(PKG_NAME) -PKG_HASH:=a22fca42354011dd2293a7f51f228b46ebbd802e7740b0975912afecb79d5df4 +PKG_HASH:=2542152264fb3eff7ed70662abf4f4eef8133bc37d0b7a686c240df2b5f80a13 HOST_BUILD_PARALLEL:=1 diff --git a/tools/xz/Makefile b/tools/xz/Makefile index 8add2f21df..845fefe9af 100644 --- a/tools/xz/Makefile +++ b/tools/xz/Makefile @@ -7,12 +7,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=xz -PKG_VERSION:=5.2.6 +PKG_VERSION:=5.2.7 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:=@SF/lzmautils \ http://tukaani.org/xz -PKG_HASH:=13e3402e301b6018f6a71ef0e497f714c6d11e214ae82dab156b81c2a64acb25 +PKG_HASH:=b65f1d0c2708e57716f4dd2216989a73847ac6fdb4168ffceb155767e22b834b PKG_CPE_ID:=cpe:/a:tukaani:xz HOST_BUILD_PARALLEL:=1 diff --git a/tools/zlib/Makefile b/tools/zlib/Makefile index 974de38154..17fe9fa233 100644 --- a/tools/zlib/Makefile +++ b/tools/zlib/Makefile @@ -8,13 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=zlib -PKG_VERSION:=1.2.12 +PKG_VERSION:=1.2.13 PKG_RELEASE:=1 -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://github.com/madler/zlib -PKG_MIRROR_HASH:=a162fc219763635f0c1591ec515d4b08684e4b0bfb4b1c8e65e4eab18d597c27 -PKG_SOURCE_VERSION:=21767c654d31d2dccdde4330529775c6c5fd5389 +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz +PKG_SOURCE_URL:=https://github.com/madler/zlib/releases/download/v$(PKG_VERSION) +PKG_HASH:=d14c38e313afc35a9a8760dadf26042f51ea0f5d154b0630a31da0540107fb98 PKG_LICENSE:=Zlib PKG_LICENSE_FILES:=README