From 069bda0adb5cb97c78ad9ea2561512ced487fa59 Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Sun, 16 Oct 2022 20:05:26 +0200 Subject: [PATCH 01/80] lantiq: add rgmii delays on BT Home Hub 5A This comit fixes warnings that occur on kernel 5.15: ... [ 2.269736] Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.5 / v1.6 1e108000.switch-mii:00: PHY has delays (e.g. via pin strapping), but phy-mode = 'rgmii' [ 2.269736] Should be 'rgmii-id' to use internal delays txskew:1500 ps rxskew:1500 ps ... Ref: https://github.com/torvalds/linux/commit/be393dd685d215d44a43f5c5dcb8f7e57668d00e Signed-off-by: Aleksander Jan Bajkowski --- .../arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts index 1cd0f2c6b6..be44cb7161 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts @@ -174,13 +174,17 @@ port@0 { reg = <0>; label = "lan3"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; + tx-internal-delay-ps = <1500>; + rx-internal-delay-ps = <1500>; phy-handle = <&phy0>; }; port@1 { reg = <1>; label = "lan4"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; + tx-internal-delay-ps = <1500>; + rx-internal-delay-ps = <1500>; phy-handle = <&phy1>; }; port@2 { @@ -198,7 +202,9 @@ port@5 { reg = <5>; label = "wan"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; + tx-internal-delay-ps = <1500>; + rx-internal-delay-ps = <1500>; phy-handle = <&phy5>; }; }; From 9226f1e41948e841c1a546a6b58273e6e994539a Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Mon, 22 Feb 2021 19:48:42 +0100 Subject: [PATCH 02/80] kernel: disable CONFIG_CPU_LITTLE_ENDIAN in generic config Endianness depends on CPU architecture. CONFIG_CPU_(BIG/LITTLE)_ENDIAN should be enabled on target or subtarget based on SoC architecture. Fixes warning: $ make kernel_oldconfig CONFIG_TARGET=subtarget ... .config:1008:warning: override: CPU_LITTLE_ENDIAN changes choice state .... Summary: - ARC - only the CONFIG_CPU_BIG_ENDIAN symbol is defined for this architeture. If it is disabled then the processor operates in LITTLE_ENDIAN mode (default), - ARM32 - CONFIG_CPU_LITTLE_ENDIAN symbol available since kernel 5.19. This option should be enabled after OpenWRT moves to kernel 6.x. After refreshing the kernel, the symbol disappears, - ARM64 - enabled CONFIG_CPU_LITTLE_ENDIAN, - MIPS - enabled relevant symbols, - POWERPC - enabled CONFIG_CPU_BIG_ENDIAN, - UML - Symbols are not defined for this architecture, - X86 - always little endian. Symbols are not defined for this architecture. Signed-off-by: Aleksander Jan Bajkowski --- target/linux/armvirt/64/config-5.15 | 1 + target/linux/bcm27xx/bcm2710/config-5.15 | 1 + target/linux/bcm27xx/bcm2711/config-5.15 | 1 + target/linux/bcm4908/config-5.10 | 1 + target/linux/bmips/config-5.15 | 1 - target/linux/generic/config-5.10 | 2 +- target/linux/generic/config-5.15 | 2 +- target/linux/layerscape/armv8_64b/config-5.10 | 1 + target/linux/malta/be/config-default | 1 - target/linux/malta/be64/config-default | 1 - target/linux/mediatek/filogic/config-5.15 | 1 + target/linux/mediatek/mt7622/config-5.15 | 1 + target/linux/mvebu/cortexa53/config-5.10 | 1 + target/linux/mvebu/cortexa53/config-5.15 | 1 + target/linux/mvebu/cortexa72/config-5.10 | 1 + target/linux/mvebu/cortexa72/config-5.15 | 1 + target/linux/octeon/config-5.10 | 1 - target/linux/octeon/config-5.15 | 1 - target/linux/octeontx/config-5.10 | 1 + target/linux/pistachio/config-5.10 | 1 + target/linux/ramips/mt7620/config-5.10 | 1 + target/linux/ramips/mt7620/config-5.15 | 1 + target/linux/ramips/mt7621/config-5.10 | 1 + target/linux/ramips/mt7621/config-5.15 | 1 + target/linux/ramips/mt76x8/config-5.10 | 1 + target/linux/ramips/mt76x8/config-5.15 | 1 + target/linux/ramips/rt288x/config-5.10 | 1 + target/linux/ramips/rt288x/config-5.15 | 1 + target/linux/ramips/rt305x/config-5.10 | 1 + target/linux/ramips/rt305x/config-5.15 | 1 + target/linux/ramips/rt3883/config-5.10 | 1 + target/linux/ramips/rt3883/config-5.15 | 1 + target/linux/rockchip/armv8/config-5.10 | 1 + target/linux/rockchip/armv8/config-5.15 | 1 + target/linux/sunxi/cortexa53/config-5.10 | 1 + target/linux/sunxi/cortexa53/config-5.15 | 1 + 36 files changed, 31 insertions(+), 7 deletions(-) diff --git a/target/linux/armvirt/64/config-5.15 b/target/linux/armvirt/64/config-5.15 index 692619daba..19ae3dc0cf 100644 --- a/target/linux/armvirt/64/config-5.15 +++ b/target/linux/armvirt/64/config-5.15 @@ -50,6 +50,7 @@ CONFIG_CLK_VEXPRESS_OSC=y # CONFIG_COMPAT_32BIT_TIME is not set CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_BS=y diff --git a/target/linux/bcm27xx/bcm2710/config-5.15 b/target/linux/bcm27xx/bcm2710/config-5.15 index 2f1b82484e..2e8b4a4360 100644 --- a/target/linux/bcm27xx/bcm2710/config-5.15 +++ b/target/linux/bcm27xx/bcm2710/config-5.15 @@ -120,6 +120,7 @@ CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CRC16=y diff --git a/target/linux/bcm27xx/bcm2711/config-5.15 b/target/linux/bcm27xx/bcm2711/config-5.15 index 61ced4508a..d98d76c333 100644 --- a/target/linux/bcm27xx/bcm2711/config-5.15 +++ b/target/linux/bcm27xx/bcm2711/config-5.15 @@ -124,6 +124,7 @@ CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CRC16=y diff --git a/target/linux/bcm4908/config-5.10 b/target/linux/bcm4908/config-5.10 index 762ce49eeb..1564123ca7 100644 --- a/target/linux/bcm4908/config-5.10 +++ b/target/linux/bcm4908/config-5.10 @@ -47,6 +47,7 @@ CONFIG_CMDLINE="earlycon=bcm63xx_uart,0xff800640 console=ttyS0,115200" CONFIG_CMDLINE_FORCE=y CONFIG_COMMON_CLK=y # CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_RMAP=y CONFIG_CRC16=y CONFIG_CRYPTO_AES_ARM64=y diff --git a/target/linux/bmips/config-5.15 b/target/linux/bmips/config-5.15 index 433915a3fc..a66443eaba 100644 --- a/target/linux/bmips/config-5.15 +++ b/target/linux/bmips/config-5.15 @@ -46,7 +46,6 @@ CONFIG_CPU_GENERIC_DUMP_TLB=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_CPU_MIPS32=y CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y CONFIG_CPU_NO_EFFICIENT_FFS=y diff --git a/target/linux/generic/config-5.10 b/target/linux/generic/config-5.10 index aa31aba756..30934d2e5f 100644 --- a/target/linux/generic/config-5.10 +++ b/target/linux/generic/config-5.10 @@ -992,7 +992,7 @@ CONFIG_CONSTRUCTORS=y # CONFIG_CPU_IDLE_GOV_TEO is not set # CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set # CONFIG_CPU_ISOLATION is not set -CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set # CONFIG_CPU_NO_EFFICIENT_FFS is not set CONFIG_CPU_SW_DOMAIN_PAN=y # CONFIG_CPU_THERMAL is not set diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15 index 611371b203..6636bd3204 100644 --- a/target/linux/generic/config-5.15 +++ b/target/linux/generic/config-5.15 @@ -1023,7 +1023,7 @@ CONFIG_CONSTRUCTORS=y # CONFIG_CPU_IDLE_GOV_TEO is not set # CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set # CONFIG_CPU_ISOLATION is not set -CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set # CONFIG_CPU_NO_EFFICIENT_FFS is not set CONFIG_CPU_SW_DOMAIN_PAN=y # CONFIG_CPU_THERMAL is not set diff --git a/target/linux/layerscape/armv8_64b/config-5.10 b/target/linux/layerscape/armv8_64b/config-5.10 index 0d4afa9809..10aaace99c 100644 --- a/target/linux/layerscape/armv8_64b/config-5.10 +++ b/target/linux/layerscape/armv8_64b/config-5.10 @@ -147,6 +147,7 @@ CONFIG_CPU_FREQ_THERMAL=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y diff --git a/target/linux/malta/be/config-default b/target/linux/malta/be/config-default index 5586be6b7c..0e7faa0877 100644 --- a/target/linux/malta/be/config-default +++ b/target/linux/malta/be/config-default @@ -1,4 +1,3 @@ CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_CPU_MIPS32_R2=y CONFIG_HIGHMEM=y diff --git a/target/linux/malta/be64/config-default b/target/linux/malta/be64/config-default index ef044bb8ca..a7e88feda0 100644 --- a/target/linux/malta/be64/config-default +++ b/target/linux/malta/be64/config-default @@ -2,7 +2,6 @@ CONFIG_64BIT=y CONFIG_ARCH_MMAP_RND_BITS=12 CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_CPU_MIPS64_R2=y # CONFIG_MIPS32_N32 is not set # CONFIG_MIPS32_O32 is not set diff --git a/target/linux/mediatek/filogic/config-5.15 b/target/linux/mediatek/filogic/config-5.15 index 4d1972e188..2e02d6a7aa 100644 --- a/target/linux/mediatek/filogic/config-5.15 +++ b/target/linux/mediatek/filogic/config-5.15 @@ -78,6 +78,7 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y CONFIG_CRC16=y diff --git a/target/linux/mediatek/mt7622/config-5.15 b/target/linux/mediatek/mt7622/config-5.15 index 8e7734957f..f17876fb05 100644 --- a/target/linux/mediatek/mt7622/config-5.15 +++ b/target/linux/mediatek/mt7622/config-5.15 @@ -107,6 +107,7 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y CONFIG_CRC16=y diff --git a/target/linux/mvebu/cortexa53/config-5.10 b/target/linux/mvebu/cortexa53/config-5.10 index 9c76159d51..fd58578405 100644 --- a/target/linux/mvebu/cortexa53/config-5.10 +++ b/target/linux/mvebu/cortexa53/config-5.10 @@ -34,6 +34,7 @@ CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_PSCI_FW=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y diff --git a/target/linux/mvebu/cortexa53/config-5.15 b/target/linux/mvebu/cortexa53/config-5.15 index 3c195291d1..27d410f68b 100644 --- a/target/linux/mvebu/cortexa53/config-5.15 +++ b/target/linux/mvebu/cortexa53/config-5.15 @@ -36,6 +36,7 @@ CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_PSCI_FW=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_FRAME_POINTER=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y diff --git a/target/linux/mvebu/cortexa72/config-5.10 b/target/linux/mvebu/cortexa72/config-5.10 index d0eeb4b739..584c3fc9b8 100644 --- a/target/linux/mvebu/cortexa72/config-5.10 +++ b/target/linux/mvebu/cortexa72/config-5.10 @@ -34,6 +34,7 @@ CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_PSCI_FW=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y diff --git a/target/linux/mvebu/cortexa72/config-5.15 b/target/linux/mvebu/cortexa72/config-5.15 index 7e07c28ba6..37379834d3 100644 --- a/target/linux/mvebu/cortexa72/config-5.15 +++ b/target/linux/mvebu/cortexa72/config-5.15 @@ -36,6 +36,7 @@ CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_PSCI_FW=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_FRAME_POINTER=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y diff --git a/target/linux/octeon/config-5.10 b/target/linux/octeon/config-5.10 index 997d22008c..58a02e6e6d 100644 --- a/target/linux/octeon/config-5.10 +++ b/target/linux/octeon/config-5.10 @@ -32,7 +32,6 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_CPU_MIPS64=y CONFIG_CPU_MIPSR2=y CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y diff --git a/target/linux/octeon/config-5.15 b/target/linux/octeon/config-5.15 index f125858636..450b84be44 100644 --- a/target/linux/octeon/config-5.15 +++ b/target/linux/octeon/config-5.15 @@ -34,7 +34,6 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_CPU_MIPS64=y CONFIG_CPU_MIPSR2=y CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y diff --git a/target/linux/octeontx/config-5.10 b/target/linux/octeontx/config-5.10 index fa6fcc3e8a..19a8c258d9 100644 --- a/target/linux/octeontx/config-5.10 +++ b/target/linux/octeontx/config-5.10 @@ -86,6 +86,7 @@ CONFIG_CONTIG_ALLOC=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CRASH_CORE=y diff --git a/target/linux/pistachio/config-5.10 b/target/linux/pistachio/config-5.10 index 9ac748c4e9..681607f65c 100644 --- a/target/linux/pistachio/config-5.10 +++ b/target/linux/pistachio/config-5.10 @@ -26,6 +26,7 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y CONFIG_CPU_MIPS32_R2=y CONFIG_CPU_MIPSR2=y diff --git a/target/linux/ramips/mt7620/config-5.10 b/target/linux/ramips/mt7620/config-5.10 index fb0fd1d30b..4ee113facd 100644 --- a/target/linux/ramips/mt7620/config-5.10 +++ b/target/linux/ramips/mt7620/config-5.10 @@ -20,6 +20,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/mt7620/config-5.15 b/target/linux/ramips/mt7620/config-5.15 index 0f8aca000c..fdca30fecb 100644 --- a/target/linux/ramips/mt7620/config-5.15 +++ b/target/linux/ramips/mt7620/config-5.15 @@ -21,6 +21,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/mt7621/config-5.10 b/target/linux/ramips/mt7621/config-5.10 index b6c7407484..8c077d211d 100644 --- a/target/linux/ramips/mt7621/config-5.10 +++ b/target/linux/ramips/mt7621/config-5.10 @@ -27,6 +27,7 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_CPU_IDLE=y # CONFIG_CPU_IDLE_GOV_LADDER is not set CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/mt7621/config-5.15 b/target/linux/ramips/mt7621/config-5.15 index adda3fef64..1b8a48100d 100644 --- a/target/linux/ramips/mt7621/config-5.15 +++ b/target/linux/ramips/mt7621/config-5.15 @@ -26,6 +26,7 @@ CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/mt76x8/config-5.10 b/target/linux/ramips/mt76x8/config-5.10 index 37f0bb8e3e..36922354a9 100644 --- a/target/linux/ramips/mt76x8/config-5.10 +++ b/target/linux/ramips/mt76x8/config-5.10 @@ -20,6 +20,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/mt76x8/config-5.15 b/target/linux/ramips/mt76x8/config-5.15 index 5e44d613df..0734bee16e 100644 --- a/target/linux/ramips/mt76x8/config-5.15 +++ b/target/linux/ramips/mt76x8/config-5.15 @@ -21,6 +21,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/rt288x/config-5.10 b/target/linux/ramips/rt288x/config-5.10 index 3071f8719f..8aff187cb6 100644 --- a/target/linux/ramips/rt288x/config-5.10 +++ b/target/linux/ramips/rt288x/config-5.10 @@ -16,6 +16,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/rt288x/config-5.15 b/target/linux/ramips/rt288x/config-5.15 index 1cf653163b..19a71d67ea 100644 --- a/target/linux/ramips/rt288x/config-5.15 +++ b/target/linux/ramips/rt288x/config-5.15 @@ -17,6 +17,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/rt305x/config-5.10 b/target/linux/ramips/rt305x/config-5.10 index 771f42ab3b..ba36912718 100644 --- a/target/linux/ramips/rt305x/config-5.10 +++ b/target/linux/ramips/rt305x/config-5.10 @@ -18,6 +18,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/rt305x/config-5.15 b/target/linux/ramips/rt305x/config-5.15 index 69835c8b54..2c2fc37a63 100644 --- a/target/linux/ramips/rt305x/config-5.15 +++ b/target/linux/ramips/rt305x/config-5.15 @@ -19,6 +19,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y` CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/rt3883/config-5.10 b/target/linux/ramips/rt3883/config-5.10 index 6e4ad04d90..aaccbddefd 100644 --- a/target/linux/ramips/rt3883/config-5.10 +++ b/target/linux/ramips/rt3883/config-5.10 @@ -17,6 +17,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/ramips/rt3883/config-5.15 b/target/linux/ramips/rt3883/config-5.15 index 4dd839be72..70d8797306 100644 --- a/target/linux/ramips/rt3883/config-5.15 +++ b/target/linux/ramips/rt3883/config-5.15 @@ -18,6 +18,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y diff --git a/target/linux/rockchip/armv8/config-5.10 b/target/linux/rockchip/armv8/config-5.10 index 75a61b8b16..25e32145d3 100644 --- a/target/linux/rockchip/armv8/config-5.10 +++ b/target/linux/rockchip/armv8/config-5.10 @@ -143,6 +143,7 @@ CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_ISOLATION=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y diff --git a/target/linux/rockchip/armv8/config-5.15 b/target/linux/rockchip/armv8/config-5.15 index 3079b09272..e5c8a6ce7f 100644 --- a/target/linux/rockchip/armv8/config-5.15 +++ b/target/linux/rockchip/armv8/config-5.15 @@ -139,6 +139,7 @@ CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_ISOLATION=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y diff --git a/target/linux/sunxi/cortexa53/config-5.10 b/target/linux/sunxi/cortexa53/config-5.10 index 958ad1addb..952b09b6ea 100644 --- a/target/linux/sunxi/cortexa53/config-5.10 +++ b/target/linux/sunxi/cortexa53/config-5.10 @@ -25,6 +25,7 @@ CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y diff --git a/target/linux/sunxi/cortexa53/config-5.15 b/target/linux/sunxi/cortexa53/config-5.15 index 00a3d971fd..b93abf0765 100644 --- a/target/linux/sunxi/cortexa53/config-5.15 +++ b/target/linux/sunxi/cortexa53/config-5.15 @@ -23,6 +23,7 @@ CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y From 6d4bcadaa343cb969f370631a5ed5338306c056e Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 21 Oct 2022 16:09:19 +0200 Subject: [PATCH 03/80] CI: kernel: fix deprecation of set-output From [0], github deprecated set-output with a better approach of appending variables to $GITHUB_OUTPUT [0] https://github.blog/changelog/2022-10-11-github-actions-deprecating-save-state-and-set-output-commands/ Signed-off-by: Christian Marangi --- .github/workflows/kernel.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/kernel.yml b/.github/workflows/kernel.yml index c8d30c0758..773e843bfd 100644 --- a/.github/workflows/kernel.yml +++ b/.github/workflows/kernel.yml @@ -35,14 +35,14 @@ jobs: run: | OWNER_LC=$(echo "${{ github.repository_owner }}" \ | tr '[:upper:]' '[:lower:]') - echo "::set-output name=owner_lc::$OWNER_LC" + echo "owner_lc=$OWNER_LC" >> $GITHUB_OUTPUT - name: Generate ccache hash id: ccache_hash run: | CCACHE_HASH=$(md5sum include/kernel-* | awk '{ print $1 }' \ | md5sum | awk '{ print $1 }') - echo "::set-output name=ccache_hash::$CCACHE_HASH" + echo "ccache_hash=$CCACHE_HASH" >> $GITHUB_OUTPUT - name: Set targets id: find_targets @@ -64,7 +64,7 @@ jobs: echo "$JSON" echo -e "\n---- targets ----\n" - echo "::set-output name=target::$JSON" + echo "target=$JSON" >> $GITHUB_OUTPUT build: name: Build Kernel with external toolchain From 63ff5b783d227bcdfb8db4500b84a3acf68b0f4c Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 21 Oct 2022 18:59:37 +0100 Subject: [PATCH 04/80] oxnas: switch to Linux 5.15 and drop Linux 5.10 Signed-off-by: Daniel Golle --- target/linux/oxnas/Makefile | 3 +- target/linux/oxnas/config-5.10 | 357 ------------------ .../oxnas/files/drivers/ata/sata_oxnas.c | 3 - .../patches-5.10/010-pogoplug-series-3.patch | 82 ---- .../050-ox820-remove-left-overs.patch | 63 ---- .../100-oxnas-clk-plla-pllb.patch | 273 -------------- .../patches-5.10/150-oxnas-restart.patch | 25 -- .../patches-5.10/320-oxnas-phy-pcie.patch | 44 --- .../oxnas/patches-5.10/340-oxnas-pcie.patch | 122 ------ .../oxnas/patches-5.10/500-oxnas-sata.patch | 60 --- .../patches-5.10/510-ox820-libata-leds.patch | 10 - .../oxnas/patches-5.10/800-oxnas-ehci.patch | 73 ---- ...Mangle-bootloader-s-kernel-arguments.patch | 189 ---------- .../oxnas/patches-5.10/999-libata-hacks.patch | 57 --- 14 files changed, 1 insertion(+), 1360 deletions(-) delete mode 100644 target/linux/oxnas/config-5.10 delete mode 100644 target/linux/oxnas/patches-5.10/010-pogoplug-series-3.patch delete mode 100644 target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch delete mode 100644 target/linux/oxnas/patches-5.10/100-oxnas-clk-plla-pllb.patch delete mode 100644 target/linux/oxnas/patches-5.10/150-oxnas-restart.patch delete mode 100644 target/linux/oxnas/patches-5.10/320-oxnas-phy-pcie.patch delete mode 100644 target/linux/oxnas/patches-5.10/340-oxnas-pcie.patch delete mode 100644 target/linux/oxnas/patches-5.10/500-oxnas-sata.patch delete mode 100644 target/linux/oxnas/patches-5.10/510-ox820-libata-leds.patch delete mode 100644 target/linux/oxnas/patches-5.10/800-oxnas-ehci.patch delete mode 100644 target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch delete mode 100644 target/linux/oxnas/patches-5.10/999-libata-hacks.patch diff --git a/target/linux/oxnas/Makefile b/target/linux/oxnas/Makefile index 9dfdb5c86e..2884a66cc7 100644 --- a/target/linux/oxnas/Makefile +++ b/target/linux/oxnas/Makefile @@ -7,8 +7,7 @@ SUBTARGETS:=ox810se ox820 FEATURES:=gpio ramdisk rtc squashfs DEVICE_TYPE:=nas -KERNEL_PATCHVER:=5.10 -KERNEL_TESTING_PATCHVER:=5.15 +KERNEL_PATCHVER:=5.15 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/oxnas/config-5.10 b/target/linux/oxnas/config-5.10 deleted file mode 100644 index dd1706cb13..0000000000 --- a/target/linux/oxnas/config-5.10 +++ /dev/null @@ -1,357 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HAS_BINFMT_FLAT=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_KCOV=y -CONFIG_ARCH_HAS_KEEPINITRD=y -CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_ARCH_HAS_PHYS_TO_DMA=y -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAS_SETUP_DMA_OPS=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_CPU_AUTO=y -# CONFIG_ARCH_MULTI_V4 is not set -# CONFIG_ARCH_MULTI_V4T is not set -CONFIG_ARCH_MULTI_V4_V5=y -CONFIG_ARCH_MULTI_V5=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OXNAS=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_LIBATA_LEDS=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_PMU=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_CMDLINE_PARSER=y -CONFIG_BLK_DEBUG_FS=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_CC_HAS_KASAN_GENERIC=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=64 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -CONFIG_CMDLINE_PARTITION=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_OXNAS=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONTIG_ALLOC=y -CONFIG_COREDUMP=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5TJ=y -CONFIG_CPU_ARM926T=y -# CONFIG_CPU_CACHE_ROUND_ROBIN is not set -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_PM=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_USE_DOMAINS=y -CONFIG_CRASH_CORE=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_RNG2=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEBUG_USER is not set -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_LZ4=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DMA_CMA=y -CONFIG_DMA_REMAP=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -# CONFIG_DWMAC_DWC_QOS_ETH is not set -CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_OXNAS=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ELF_CORE=y -CONFIG_FAT_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FREEZER=y -# CONFIG_FW_CACHE is not set -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_COPY_THREAD_TLS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PCI=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -CONFIG_HWMON=y -CONFIG_HZ_FIXED=0 -CONFIG_ICPLUS_PHY=y -CONFIG_INET_DIAG=y -# CONFIG_INET_DIAG_DESTROY is not set -# CONFIG_INET_RAW_DIAG is not set -CONFIG_INET_TCP_DIAG=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -# CONFIG_ISDN is not set -# CONFIG_JFFS2_FS is not set -CONFIG_KALLSYMS=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_XZ is not set -CONFIG_KEXEC=y -CONFIG_KEXEC_CORE=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_OX810SE is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_KUSER_HELPERS=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NLS=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OXNAS_RPS_TIMER=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHY_OXNAS=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_OXNAS=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PM=y -CONFIG_PM_CLK=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_OXNAS=y -CONFIG_PPS=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RCU_TRACE=y -CONFIG_RD_BZIP2=y -CONFIG_RD_GZIP=y -CONFIG_RD_LZ4=y -CONFIG_RD_LZMA=y -CONFIG_RD_LZO=y -CONFIG_RD_XZ=y -CONFIG_REALTEK_PHY=y -CONFIG_REFCOUNT_FULL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_OXNAS=y -CONFIG_SCHED_DEBUG=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_SERPORT=y -CONFIG_SIMPLE_PM_BUS=y -CONFIG_SLUB_DEBUG=y -CONFIG_SOCK_DIAG=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPLIT_PTLOCK_CPUS=999999 -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -# CONFIG_STMMAC_SELFTESTS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWPHY=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_TRACE_CLOCK=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -# CONFIG_UNWINDER_FRAME_POINTER is not set -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VERSATILE_FPGA_IRQ=y -CONFIG_VERSATILE_FPGA_IRQ_NR=4 -CONFIG_VFAT_FS=y -# CONFIG_VFP is not set -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_WATCHDOG is not set -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_IA64=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_X86=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/oxnas/files/drivers/ata/sata_oxnas.c b/target/linux/oxnas/files/drivers/ata/sata_oxnas.c index a5d7b3de72..217c258565 100644 --- a/target/linux/oxnas/files/drivers/ata/sata_oxnas.c +++ b/target/linux/oxnas/files/drivers/ata/sata_oxnas.c @@ -2232,9 +2232,6 @@ static struct scsi_host_template sata_oxnas_sht = { .can_queue = SATA_OXNAS_QUEUE_DEPTH, .sg_tablesize = SATA_OXNAS_MAX_PRD, .dma_boundary = ATA_DMA_BOUNDARY, -#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 13, 0) - .unchecked_isa_dma = 0, -#endif }; diff --git a/target/linux/oxnas/patches-5.10/010-pogoplug-series-3.patch b/target/linux/oxnas/patches-5.10/010-pogoplug-series-3.patch deleted file mode 100644 index 44102352af..0000000000 --- a/target/linux/oxnas/patches-5.10/010-pogoplug-series-3.patch +++ /dev/null @@ -1,82 +0,0 @@ -- add compatible string -- add console to bootargs -- add led aliases -- adjust nand partition table ---- ---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts -+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts -@@ -11,10 +11,10 @@ - / { - model = "Cloud Engines PogoPlug Series 3"; - -- compatible = "cloudengines,pogoplugv3", "oxsemi,ox820"; -+ compatible = "cloudengines,pogoplug-series-3", "cloudengines,pogoplugv3", "oxsemi,ox820"; - - chosen { -- bootargs = "earlyprintk"; -+ bootargs = "earlyprintk console=ttyS0,115200"; - stdout-path = "serial0:115200n8"; - }; - -@@ -27,24 +27,28 @@ - serial0 = &uart0; - gpio0 = &gpio0; - gpio1 = &gpio1; -+ led-boot = &led_status; -+ led-failsafe = &led_warn; -+ led-running = &led_act; -+ led-upgrade = &led_warn; - }; - - leds { - compatible = "gpio-leds"; - -- blue { -+ led_status: blue { - label = "pogoplug:blue"; - gpios = <&gpio0 2 0>; - default-state = "keep"; - }; - -- orange { -+ led_warn: orange { - label = "pogoplug:orange"; - gpios = <&gpio1 16 1>; - default-state = "keep"; - }; - -- green { -+ led_act: green { - label = "pogoplug:green"; - gpios = <&gpio1 17 1>; - default-state = "keep"; -@@ -73,11 +77,27 @@ - nand-ecc-algo = "hamming"; - - partition@0 { -- label = "boot"; -- reg = <0x00000000 0x00e00000>; -+ label = "stage1"; -+ reg = <0x00000000 0x00040000>; - read-only; - }; - -+ partition@40000 { -+ label = "u-boot"; -+ reg = <0x00040000 0x00380000>; -+ read-only; -+ }; -+ -+ partition@3c0000 { -+ label = "u-boot-env"; -+ reg = <0x003c0000 0x00080000>; -+ }; -+ -+ partition@440000 { -+ label = "kernel"; -+ reg = <0x00440000 0x009c0000>; -+ }; -+ - partition@e00000 { - label = "ubi"; - reg = <0x00e00000 0x07200000>; diff --git a/target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch b/target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch deleted file mode 100644 index e30f328792..0000000000 --- a/target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 1 Jun 2018 02:41:15 +0200 -Subject: [PATCH] arm: ox820: remove left-overs - -Signed-off-by: Daniel Golle ---- - drivers/clk/clk-oxnas.c | 2 -- - include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++------------- - 2 files changed, 14 insertions(+), 20 deletions(-) - ---- a/drivers/clk/clk-oxnas.c -+++ b/drivers/clk/clk-oxnas.c -@@ -29,8 +29,6 @@ struct oxnas_stdclk_data { - struct clk_hw_onecell_data *onecell_data; - struct clk_oxnas_gate **gates; - unsigned int ngates; -- struct clk_oxnas_pll **plls; -- unsigned int nplls; - }; - - /* Regmap offsets */ ---- a/include/dt-bindings/clock/oxsemi,ox820.h -+++ b/include/dt-bindings/clock/oxsemi,ox820.h -@@ -6,24 +6,20 @@ - #ifndef DT_CLOCK_OXSEMI_OX820_H - #define DT_CLOCK_OXSEMI_OX820_H - --/* PLLs */ --#define CLK_820_PLLA 0 --#define CLK_820_PLLB 1 -- - /* Gate Clocks */ --#define CLK_820_LEON 2 --#define CLK_820_DMA_SGDMA 3 --#define CLK_820_CIPHER 4 --#define CLK_820_SD 5 --#define CLK_820_SATA 6 --#define CLK_820_AUDIO 7 --#define CLK_820_USBMPH 8 --#define CLK_820_ETHA 9 --#define CLK_820_PCIEA 10 --#define CLK_820_NAND 11 --#define CLK_820_PCIEB 12 --#define CLK_820_ETHB 13 --#define CLK_820_REF600 14 --#define CLK_820_USBDEV 15 -+#define CLK_820_LEON 0 -+#define CLK_820_DMA_SGDMA 1 -+#define CLK_820_CIPHER 2 -+#define CLK_820_SD 3 -+#define CLK_820_SATA 4 -+#define CLK_820_AUDIO 5 -+#define CLK_820_USBMPH 6 -+#define CLK_820_ETHA 7 -+#define CLK_820_PCIEA 8 -+#define CLK_820_NAND 9 -+#define CLK_820_PCIEB 10 -+#define CLK_820_ETHB 11 -+#define CLK_820_REF600 12 -+#define CLK_820_USBDEV 13 - - #endif /* DT_CLOCK_OXSEMI_OX820_H */ diff --git a/target/linux/oxnas/patches-5.10/100-oxnas-clk-plla-pllb.patch b/target/linux/oxnas/patches-5.10/100-oxnas-clk-plla-pllb.patch deleted file mode 100644 index 6c795c1d25..0000000000 --- a/target/linux/oxnas/patches-5.10/100-oxnas-clk-plla-pllb.patch +++ /dev/null @@ -1,273 +0,0 @@ ---- a/drivers/clk/clk-oxnas.c -+++ b/drivers/clk/clk-oxnas.c -@@ -5,19 +5,42 @@ - * Copyright (C) 2016 Neil Armstrong - */ - -+#include -+#include - #include - #include - #include -+#include - #include - #include - #include - #include - #include - #include -+#include - - #include - #include - -+#define REF300_DIV_INT_SHIFT 8 -+#define REF300_DIV_FRAC_SHIFT 0 -+#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT) -+#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT) -+ -+#define PLLB_BYPASS 1 -+#define PLLB_ENSAT 3 -+#define PLLB_OUTDIV 4 -+#define PLLB_REFDIV 8 -+#define PLLB_DIV_INT_SHIFT 8 -+#define PLLB_DIV_FRAC_SHIFT 0 -+#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT) -+#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT) -+ -+#define PLLA_REFDIV_MASK 0x3F -+#define PLLA_REFDIV_SHIFT 8 -+#define PLLA_OUTDIV_MASK 0x7 -+#define PLLA_OUTDIV_SHIFT 4 -+ - /* Standard regmap gate clocks */ - struct clk_oxnas_gate { - struct clk_hw hw; -@@ -36,6 +59,135 @@ struct oxnas_stdclk_data { - #define CLK_SET_REGOFFSET 0x2c - #define CLK_CLR_REGOFFSET 0x30 - -+#define PLLA_CTRL0_REGOFFSET 0x1f0 -+#define PLLA_CTRL1_REGOFFSET 0x1f4 -+#define PLLB_CTRL0_REGOFFSET 0x1001f0 -+#define MHZ (1000 * 1000) -+ -+struct clk_oxnas_pll { -+ struct clk_hw hw; -+ struct device_node *devnode; -+ struct reset_control *rstc; -+ struct regmap *syscon; -+}; -+ -+#define to_clk_oxnas_pll(_hw) container_of(_hw, struct clk_oxnas_pll, hw) -+ -+static unsigned long plla_clk_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct clk_oxnas_pll *plla = to_clk_oxnas_pll(hw); -+ unsigned long fin = parent_rate; -+ unsigned long refdiv, outdiv; -+ unsigned int pll0, fbdiv; -+ -+ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL0_REGOFFSET, &pll0)); -+ -+ refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK; -+ refdiv += 1; -+ outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK; -+ outdiv += 1; -+ -+ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL1_REGOFFSET, &fbdiv)); -+ /* seems we will not be here when pll is bypassed, so ignore this -+ * case */ -+ -+ return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ; -+} -+ -+static const char *pll_clk_parents[] = { -+ "oscillator", -+}; -+ -+static struct clk_ops plla_ops = { -+ .recalc_rate = plla_clk_recalc_rate, -+}; -+ -+static struct clk_init_data clk_plla_init = { -+ .name = "plla", -+ .ops = &plla_ops, -+ .parent_names = pll_clk_parents, -+ .num_parents = ARRAY_SIZE(pll_clk_parents), -+}; -+ -+static int pllb_clk_is_prepared(struct clk_hw *hw) -+{ -+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); -+ -+ return !!pllb->rstc; -+} -+ -+static int pllb_clk_prepare(struct clk_hw *hw) -+{ -+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); -+ -+ pllb->rstc = of_reset_control_get(pllb->devnode, NULL); -+ -+ return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0; -+} -+ -+static void pllb_clk_unprepare(struct clk_hw *hw) -+{ -+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); -+ -+ BUG_ON(IS_ERR(pllb->rstc)); -+ -+ reset_control_put(pllb->rstc); -+ pllb->rstc = NULL; -+} -+ -+static int pllb_clk_enable(struct clk_hw *hw) -+{ -+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); -+ -+ BUG_ON(IS_ERR(pllb->rstc)); -+ -+ /* put PLL into bypass */ -+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS)); -+ wmb(); -+ udelay(10); -+ reset_control_assert(pllb->rstc); -+ udelay(10); -+ /* set PLL B control information */ -+ regmap_write_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, 0xffff, -+ (1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV)); -+ reset_control_deassert(pllb->rstc); -+ udelay(100); -+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), 0); -+ -+ return 0; -+} -+ -+static void pllb_clk_disable(struct clk_hw *hw) -+{ -+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); -+ -+ BUG_ON(IS_ERR(pllb->rstc)); -+ -+ /* put PLL into bypass */ -+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS)); -+ -+ wmb(); -+ udelay(10); -+ -+ reset_control_assert(pllb->rstc); -+} -+ -+static struct clk_ops pllb_ops = { -+ .prepare = pllb_clk_prepare, -+ .unprepare = pllb_clk_unprepare, -+ .is_prepared = pllb_clk_is_prepared, -+ .enable = pllb_clk_enable, -+ .disable = pllb_clk_disable, -+}; -+ -+static struct clk_init_data clk_pllb_init = { -+ .name = "pllb", -+ .ops = &pllb_ops, -+ .parent_names = pll_clk_parents, -+ .num_parents = ARRAY_SIZE(pll_clk_parents), -+}; -+ - static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw) - { - return container_of(hw, struct clk_oxnas_gate, hw); -@@ -249,3 +401,42 @@ static struct platform_driver oxnas_stdc - }, - }; - builtin_platform_driver(oxnas_stdclk_driver); -+ -+void __init oxnas_init_plla(struct device_node *np) -+{ -+ struct clk *clk; -+ struct clk_oxnas_pll *plla; -+ -+ plla = kmalloc(sizeof(*plla), GFP_KERNEL); -+ BUG_ON(!plla); -+ -+ plla->syscon = syscon_node_to_regmap(of_get_parent(np)); -+ plla->hw.init = &clk_plla_init; -+ plla->devnode = np; -+ plla->rstc = NULL; -+ clk = clk_register(NULL, &plla->hw); -+ BUG_ON(IS_ERR(clk)); -+ /* mark it as enabled */ -+ clk_prepare_enable(clk); -+ of_clk_add_provider(np, of_clk_src_simple_get, clk); -+} -+CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla); -+ -+void __init oxnas_init_pllb(struct device_node *np) -+{ -+ struct clk *clk; -+ struct clk_oxnas_pll *pllb; -+ -+ pllb = kmalloc(sizeof(*pllb), GFP_KERNEL); -+ BUG_ON(!pllb); -+ -+ pllb->syscon = syscon_node_to_regmap(of_get_parent(np)); -+ pllb->hw.init = &clk_pllb_init; -+ pllb->devnode = np; -+ pllb->rstc = NULL; -+ -+ clk = clk_register(NULL, &pllb->hw); -+ BUG_ON(IS_ERR(clk)); -+ of_clk_add_provider(np, of_clk_src_simple_get, clk); -+} -+CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb); ---- a/arch/arm/boot/dts/ox820.dtsi -+++ b/arch/arm/boot/dts/ox820.dtsi -@@ -61,12 +61,6 @@ - clocks = <&osc>; - }; - -- plla: plla { -- compatible = "fixed-clock"; -- #clock-cells = <0>; -- clock-frequency = <850000000>; -- }; -- - armclk: armclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; -@@ -266,6 +260,19 @@ - compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk"; - #clock-cells = <1>; - }; -+ -+ plla: plla { -+ compatible = "plxtech,nas782x-plla"; -+ #clock-cells = <0>; -+ clocks = <&osc>; -+ }; -+ -+ pllb: pllb { -+ compatible = "plxtech,nas782x-pllb"; -+ #clock-cells = <0>; -+ clocks = <&osc>; -+ resets = <&reset RESET_PLLB>; -+ }; - }; - }; - -@@ -287,6 +294,13 @@ - clocks = <&armclk>; - }; - -+ watchdog@620 { -+ compatible = "mpcore_wdt"; -+ reg = <0x620 0x20>; -+ interrupts = ; -+ clocks = <&armclk>; -+ }; -+ - gic: interrupt-controller@1000 { - compatible = "arm,arm11mp-gic"; - interrupt-controller; diff --git a/target/linux/oxnas/patches-5.10/150-oxnas-restart.patch b/target/linux/oxnas/patches-5.10/150-oxnas-restart.patch deleted file mode 100644 index c5b07fd5a7..0000000000 --- a/target/linux/oxnas/patches-5.10/150-oxnas-restart.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/power/reset/Kconfig -+++ b/drivers/power/reset/Kconfig -@@ -141,6 +141,12 @@ config POWER_RESET_OXNAS - help - Restart support for OXNAS/PLXTECH OX820 SoC. - -+config POWER_RESET_OXNAS -+ bool "OXNAS SoC restart driver" -+ depends on ARCH_OXNAS -+ help -+ Restart support for OXNAS boards. -+ - config POWER_RESET_PIIX4_POWEROFF - tristate "Intel PIIX4 power-off driver" - depends on PCI ---- a/drivers/power/reset/Makefile -+++ b/drivers/power/reset/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_POWER_RESET_QCOM_PON) += qc - obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o - obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o - obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o -+obj-$(CONFIG_POWER_RESET_OXNAS) += oxnas-restart.o - obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o - obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o - obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o diff --git a/target/linux/oxnas/patches-5.10/320-oxnas-phy-pcie.patch b/target/linux/oxnas/patches-5.10/320-oxnas-phy-pcie.patch deleted file mode 100644 index a590151e5c..0000000000 --- a/target/linux/oxnas/patches-5.10/320-oxnas-phy-pcie.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- a/arch/arm/boot/dts/ox820.dtsi -+++ b/arch/arm/boot/dts/ox820.dtsi -@@ -247,6 +247,15 @@ - }; - }; - -+ pcie_phy: pcie-phy@a00000 { -+ compatible = "oxsemi,ox820-pcie-phy"; -+ reg = <0xa00000 0x10>; -+ #phy-cells = <0>; -+ resets = <&reset RESET_PCIEPHY>; -+ reset-names = "phy"; -+ status = "disabled"; -+ }; -+ - sys: sys-ctrl@e00000 { - compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"; - reg = <0xe00000 0x200000>; ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -35,6 +35,13 @@ config PHY_LPC18XX_USB_OTG - This driver is need for USB0 support on LPC18xx/43xx and takes - care of enabling and clock setup. - -+config PHY_OXNAS -+ tristate "Oxford Semi. OX820 PCI-E PHY support" -+ depends on HAS_IOMEM && OF && (ARM || COMPILE_TEST) -+ select GENERIC_PHY -+ help -+ This option enables support for OXNAS OX820 SoC PCIE PHY. -+ - config PHY_PISTACHIO_USB - tristate "IMG Pistachio USB2.0 PHY driver" - depends on MACH_PISTACHIO ---- a/drivers/phy/Makefile -+++ b/drivers/phy/Makefile -@@ -6,6 +6,7 @@ - obj-$(CONFIG_GENERIC_PHY) += phy-core.o - obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o - obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o -+obj-$(CONFIG_PHY_OXNAS) += phy-oxnas-pcie.o - obj-$(CONFIG_PHY_XGENE) += phy-xgene.o - obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o - obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o diff --git a/target/linux/oxnas/patches-5.10/340-oxnas-pcie.patch b/target/linux/oxnas/patches-5.10/340-oxnas-pcie.patch deleted file mode 100644 index 01b5a188c3..0000000000 --- a/target/linux/oxnas/patches-5.10/340-oxnas-pcie.patch +++ /dev/null @@ -1,122 +0,0 @@ ---- a/drivers/pci/controller/Kconfig -+++ b/drivers/pci/controller/Kconfig -@@ -305,6 +305,11 @@ config PCIE_HISI_ERR - Say Y here if you want error handling support - for the PCIe controller's errors on HiSilicon HIP SoCs - -+config PCIE_OXNAS -+ bool "PLX Oxnas PCIe controller" -+ depends on ARCH_OXNAS -+ select PCIEPORTBUS -+ - source "drivers/pci/controller/dwc/Kconfig" - source "drivers/pci/controller/mobiveil/Kconfig" - source "drivers/pci/controller/cadence/Kconfig" ---- a/drivers/pci/controller/Makefile -+++ b/drivers/pci/controller/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rock - obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o - obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o - obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o -+obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o - obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o - obj-$(CONFIG_VMD) += vmd.o - obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o ---- a/arch/arm/boot/dts/ox820.dtsi -+++ b/arch/arm/boot/dts/ox820.dtsi -@@ -289,7 +289,7 @@ - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; -- ranges = <0 0x47000000 0x1000000>; -+ ranges = <0 0x47000000 0x2000>; - - scu: scu@0 { - compatible = "arm,arm11mp-scu"; -@@ -318,5 +318,86 @@ - <0x100 0x500>; - }; - }; -+ -+ pcie0: pcie-controller@47c00000 { -+ compatible = "plxtech,nas782x-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ /* flag & space bus address host address size */ -+ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000 -+ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000 -+ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000 -+ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>; -+ -+ bus-range = <0x00 0x7f>; -+ -+ /* cfg inbound translator */ -+ reg = <0x47c00000 0x1000>, <0x47d00000 0x100>; -+ -+ phys = <&pcie_phy>; -+ phy-names = "pcie-phy"; -+ -+ #interrupt-cells = <1>; -+ /* wild card mask, match all bus address & interrupt specifier */ -+ /* format: bus address mask, interrupt specifier mask */ -+ /* each bit 1 means need match, 0 means ignored when match */ -+ interrupt-map-mask = <0 0 0 0>; -+ /* format: a list of: bus address, interrupt specifier, -+ * parent interrupt controller & specifier */ -+ interrupt-map = <0 0 0 0 &gic 0 19 0x304>; -+ gpios = <&gpio1 12 0>; -+ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>; -+ clock-names = "pcie", "busclk"; -+ resets = <&reset RESET_PCIEA>; -+ reset-names = "pcie"; -+ -+ plxtech,pcie-hcsl-bit = <2>; -+ plxtech,pcie-ctrl-offset = <0x120>; -+ plxtech,pcie-outbound-offset = <0x138>; -+ status = "disabled"; -+ }; -+ -+ pcie1: pcie-controller@47e00000 { -+ compatible = "plxtech,nas782x-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ /* flag & space bus address host address size */ -+ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000 -+ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000 -+ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000 -+ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>; -+ -+ bus-range = <0x80 0xff>; -+ -+ /* cfg inbound translator */ -+ reg = <0x47e00000 0x1000>, <0x47f00000 0x100>; -+ -+ phys = <&pcie_phy>; -+ phy-names = "pcie-phy"; -+ -+ #interrupt-cells = <1>; -+ /* wild card mask, match all bus address & interrupt specifier */ -+ /* format: bus address mask, interrupt specifier mask */ -+ /* each bit 1 means need match, 0 means ignored when match */ -+ interrupt-map-mask = <0 0 0 0>; -+ /* format: a list of: bus address, interrupt specifier, -+ * parent interrupt controller & specifier */ -+ interrupt-map = <0 0 0 0 &gic 0 20 0x304>; -+ -+ /* gpios = <&gpio1 12 0>; */ -+ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>; -+ clock-names = "pcie", "busclk"; -+ resets = <&reset RESET_PCIEB>; -+ reset-names = "pcie"; -+ -+ plxtech,pcie-hcsl-bit = <3>; -+ plxtech,pcie-ctrl-offset = <0x124>; -+ plxtech,pcie-outbound-offset = <0x174>; -+ status = "disabled"; -+ }; - }; - }; diff --git a/target/linux/oxnas/patches-5.10/500-oxnas-sata.patch b/target/linux/oxnas/patches-5.10/500-oxnas-sata.patch deleted file mode 100644 index d3ec2e2d48..0000000000 --- a/target/linux/oxnas/patches-5.10/500-oxnas-sata.patch +++ /dev/null @@ -1,60 +0,0 @@ ---- a/drivers/ata/Kconfig -+++ b/drivers/ata/Kconfig -@@ -568,6 +568,14 @@ config SATA_VITESSE - - If unsure, say N. - -+config SATA_OXNAS -+ tristate "PLXTECH NAS782X SATA support" -+ select SATA_HOST -+ help -+ This option enables support for Nas782x Serial ATA controller. -+ -+ If unsure, say N. -+ - comment "PATA SFF controllers with BMDMA" - - config PATA_ALI ---- a/drivers/ata/Makefile -+++ b/drivers/ata/Makefile -@@ -46,6 +46,7 @@ obj-$(CONFIG_SATA_SVW) += sata_svw.o - obj-$(CONFIG_SATA_ULI) += sata_uli.o - obj-$(CONFIG_SATA_VIA) += sata_via.o - obj-$(CONFIG_SATA_VITESSE) += sata_vsc.o -+obj-$(CONFIG_SATA_OXNAS) += sata_oxnas.o - - # SFF PATA w/ BMDMA - obj-$(CONFIG_PATA_ALI) += pata_ali.o ---- a/arch/arm/boot/dts/ox820.dtsi -+++ b/arch/arm/boot/dts/ox820.dtsi -@@ -399,5 +399,20 @@ - plxtech,pcie-outbound-offset = <0x174>; - status = "disabled"; - }; -+ -+ sata: sata@45900000 { -+ compatible = "plxtech,nas782x-sata"; -+ /* ports dmactl sgdma */ -+ reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>, -+ /* core phy descriptors (optional) */ -+ <0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>; -+ interrupts = ; -+ clocks = <&stdclk CLK_820_SATA>; -+ resets = <&reset RESET_SATA>, <&reset RESET_SATA_LINK>, <&reset RESET_SATA_PHY>; -+ reset-names = "sata", "link", "phy"; -+ nr-ports = <1>; -+ status = "disabled"; -+ }; -+ - }; - }; ---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts -+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts -@@ -111,3 +111,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etha_mdio>; - }; -+ -+&sata { -+ status = "okay"; -+}; diff --git a/target/linux/oxnas/patches-5.10/510-ox820-libata-leds.patch b/target/linux/oxnas/patches-5.10/510-ox820-libata-leds.patch deleted file mode 100644 index 05ae9ba44b..0000000000 --- a/target/linux/oxnas/patches-5.10/510-ox820-libata-leds.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/mach-oxnas/Kconfig -+++ b/arch/arm/mach-oxnas/Kconfig -@@ -2,6 +2,7 @@ - menuconfig ARCH_OXNAS - bool "Oxford Semiconductor OXNAS Family SoCs" - select ARCH_HAS_RESET_CONTROLLER -+ select ARCH_WANT_LIBATA_LEDS - select COMMON_CLK_OXNAS - select GPIOLIB - select MFD_SYSCON diff --git a/target/linux/oxnas/patches-5.10/800-oxnas-ehci.patch b/target/linux/oxnas/patches-5.10/800-oxnas-ehci.patch deleted file mode 100644 index 8b4d943810..0000000000 --- a/target/linux/oxnas/patches-5.10/800-oxnas-ehci.patch +++ /dev/null @@ -1,73 +0,0 @@ ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -350,6 +350,13 @@ config USB_OCTEON_EHCI - USB 2.0 device support. All CN6XXX based chips with USB are - supported. - -+config USB_EHCI_OXNAS -+ tristate "OXNAS EHCI Module" -+ depends on USB_EHCI_HCD && ARCH_OXNAS -+ select USB_EHCI_ROOT_HUB_TT -+ help -+ Enable support for the OX820 SOC's on-chip EHCI controller. -+ - endif # USB_EHCI_HCD - - config USB_OXU210HP_HCD ---- a/drivers/usb/host/Makefile -+++ b/drivers/usb/host/Makefile -@@ -48,6 +48,7 @@ obj-$(CONFIG_USB_EHCI_HCD_SPEAR) += ehci - obj-$(CONFIG_USB_EHCI_HCD_STI) += ehci-st.o - obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o - obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o -+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o - obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o - obj-$(CONFIG_USB_EHCI_BRCMSTB) += ehci-brcm.o - ---- a/arch/arm/boot/dts/ox820.dtsi -+++ b/arch/arm/boot/dts/ox820.dtsi -@@ -106,6 +106,31 @@ - status = "disabled"; - }; - -+ ehci: ehci@40200100 { -+ compatible = "plxtech,nas782x-ehci"; -+ reg = <0x40200100 0xf00>; -+ interrupts = ; -+ clocks = <&stdclk CLK_820_USBMPH>, <&pllb>, <&stdclk CLK_820_REF600>; -+ clock-names = "usb", "refsrc", "phyref"; -+ resets = <&reset RESET_USBHS>, <&reset RESET_USBPHYA>, <&reset RESET_USBPHYB>; -+ reset-names = "host", "phya", "phyb"; -+ oxsemi,sys-ctrl = <&sys>; -+ /* Otherwise ref300 is used, which is derived from sata phy -+ * in that case, usb depends on sata initialization */ -+ /* FIXME: how to make this dependency explicit ? */ -+ oxsemi,ehci_use_pllb; -+ status = "disabled"; -+ -+ ehci_port1: port@1 { -+ reg = <1>; -+ #trigger-source-cells = <0>; -+ }; -+ ehci_port2: port@2 { -+ reg = <2>; -+ #trigger-source-cells = <0>; -+ }; -+ }; -+ - apb-bridge@44000000 { - #address-cells = <1>; - #size-cells = <1>; ---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts -+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts -@@ -105,6 +105,10 @@ - }; - }; - -+&ehci { -+ status = "okay"; -+}; -+ - ða { - status = "okay"; - diff --git a/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch deleted file mode 100644 index 8f56bdbf9c..0000000000 --- a/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001 -From: Adrian Panella -Date: Thu, 9 Mar 2017 09:37:17 +0100 -Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments - -The command-line arguments provided by the boot loader will be -appended to a new device tree property: bootloader-args. -If there is a property "append-rootblock" in DT under /chosen -and a root= option in bootloaders command line it will be parsed -and added to DT bootargs with the form: XX. -Only command line ATAG will be processed, the rest of the ATAGs -sent by bootloader will be ignored. -This is usefull in dual boot systems, to get the current root partition -without afecting the rest of the system. - -Signed-off-by: Adrian Panella ---- - arch/arm/Kconfig | 11 +++++ - arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++- - init/main.c | 16 ++++++++ - 3 files changed, 98 insertions(+), 1 deletion(-) - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1777,6 +1777,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - The command-line arguments provided by the boot loader will be - appended to the the device tree bootargs property. - -+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ bool "Append rootblock parsing bootloader's kernel arguments" -+ help -+ The command-line arguments provided by the boot loader will be -+ appended to a new device tree property: bootloader-args. -+ If there is a property "append-rootblock" in DT under /chosen -+ and a root= option in bootloaders command line it will be parsed -+ and added to DT bootargs with the form: XX. -+ Only command line ATAG will be processed, the rest of the ATAGs -+ sent by bootloader will be ignored. -+ - endchoice - - config CMDLINE ---- a/arch/arm/boot/compressed/atags_to_fdt.c -+++ b/arch/arm/boot/compressed/atags_to_fdt.c -@@ -5,6 +5,8 @@ - - #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) - #define do_extend_cmdline 1 -+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#define do_extend_cmdline 1 - #else - #define do_extend_cmdline 0 - #endif -@@ -69,6 +71,59 @@ static uint32_t get_cell_size(const void - return cell_size; - } - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ -+static char *append_rootblock(char *dest, const char *str, int len, void *fdt) -+{ -+ char *ptr, *end; -+ char *root="root="; -+ int i, l; -+ const char *rootblock; -+ -+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually -+ ptr = str - 1; -+ -+ do { -+ //first find an 'r' at the begining or after a space -+ do { -+ ptr++; -+ ptr = strchr(ptr, 'r'); -+ if(!ptr) return dest; -+ -+ } while (ptr != str && *(ptr-1) != ' '); -+ -+ //then check for the rest -+ for(i = 1; i <= 4; i++) -+ if(*(ptr+i) != *(root+i)) break; -+ -+ } while (i != 5); -+ -+ end = strchr(ptr, ' '); -+ end = end ? (end - 1) : (strchr(ptr, 0) - 1); -+ -+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX ) -+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++); -+ ptr = end + 1; -+ -+ /* if append-rootblock property is set use it to append to command line */ -+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l); -+ if(rootblock != NULL) { -+ if(*dest != ' ') { -+ *dest = ' '; -+ dest++; -+ len++; -+ } -+ if (len + l + i <= COMMAND_LINE_SIZE) { -+ memcpy(dest, rootblock, l); -+ dest += l - 1; -+ memcpy(dest, ptr, i); -+ dest += i; -+ } -+ } -+ return dest; -+} -+#endif -+ - static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) - { - char cmdline[COMMAND_LINE_SIZE]; -@@ -88,12 +143,21 @@ static void merge_fdt_bootargs(void *fdt - - /* and append the ATAG_CMDLINE */ - if (fdt_cmdline) { -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //save original bootloader args -+ //and append ubi.mtd with root partition number to current cmdline -+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline); -+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt); -+ -+#else - len = strlen(fdt_cmdline); - if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { - *ptr++ = ' '; - memcpy(ptr, fdt_cmdline, len); - ptr += len; - } -+#endif - } - *ptr = '\0'; - -@@ -168,7 +232,9 @@ int atags_to_fdt(void *atag_list, void * - else - setprop_string(fdt, "/chosen", "bootargs", - atag->u.cmdline.cmdline); -- } else if (atag->hdr.tag == ATAG_MEM) { -+ } -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ else if (atag->hdr.tag == ATAG_MEM) { - if (memcount >= sizeof(mem_reg_property)/4) - continue; - if (!atag->u.mem.size) -@@ -212,6 +278,10 @@ int atags_to_fdt(void *atag_list, void * - setprop(fdt, "/memory", "reg", mem_reg_property, - 4 * memcount * memsize); - } -+#else -+ -+ } -+#endif - - return fdt_pack(fdt); - } ---- a/init/main.c -+++ b/init/main.c -@@ -110,6 +110,10 @@ - - #include - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#include -+#endif -+ - static int kernel_init(void *); - - extern void init_IRQ(void); -@@ -904,6 +908,18 @@ asmlinkage __visible void __init __no_sa - page_alloc_init(); - - pr_notice("Kernel command line: %s\n", saved_command_line); -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //Show bootloader's original command line for reference -+ if(of_chosen) { -+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL); -+ if(prop) -+ pr_notice("Bootloader command line (ignored): %s\n", prop); -+ else -+ pr_notice("Bootloader command line not present\n"); -+ } -+#endif -+ - /* parameters may set static keys */ - jump_label_init(); - parse_early_param(); diff --git a/target/linux/oxnas/patches-5.10/999-libata-hacks.patch b/target/linux/oxnas/patches-5.10/999-libata-hacks.patch deleted file mode 100644 index 461a1b87f4..0000000000 --- a/target/linux/oxnas/patches-5.10/999-libata-hacks.patch +++ /dev/null @@ -1,57 +0,0 @@ ---- a/drivers/ata/libata-core.c -+++ b/drivers/ata/libata-core.c -@@ -1528,6 +1528,14 @@ unsigned ata_exec_internal_sg(struct ata - return AC_ERR_SYSTEM; - } - -+ if (ap->ops->acquire_hw && !ap->ops->acquire_hw(ap, 0, 0)) { -+ spin_unlock_irqrestore(ap->lock, flags); -+ if (!ap->ops->acquire_hw(ap, 1, (2*HZ))) { -+ return AC_ERR_TIMEOUT; -+ } -+ spin_lock_irqsave(ap->lock, flags); -+ } -+ - /* initialize internal qc */ - qc = __ata_qc_from_tag(ap, ATA_TAG_INTERNAL); - -@@ -4562,6 +4570,9 @@ struct ata_queued_cmd *ata_qc_new_init(s - if (unlikely(ap->pflags & ATA_PFLAG_FROZEN)) - return NULL; - -+ if (ap->ops->qc_new && ap->ops->qc_new(ap)) -+ return NULL; -+ - /* libsas case */ - if (ap->flags & ATA_FLAG_SAS_HOST) { - tag = ata_sas_allocate_tag(ap); -@@ -4607,6 +4618,8 @@ void ata_qc_free(struct ata_queued_cmd * - qc->tag = ATA_TAG_POISON; - if (ap->flags & ATA_FLAG_SAS_HOST) - ata_sas_free_tag(tag, ap); -+ if (ap->ops->qc_free) -+ ap->ops->qc_free(qc); - } - } - ---- a/include/linux/libata.h -+++ b/include/linux/libata.h -@@ -912,6 +912,8 @@ struct ata_port_operations { - enum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *qc); - unsigned int (*qc_issue)(struct ata_queued_cmd *qc); - bool (*qc_fill_rtf)(struct ata_queued_cmd *qc); -+ int (*qc_new)(struct ata_port *ap); -+ void (*qc_free)(struct ata_queued_cmd *qc); - - /* - * Configuration and exception handling -@@ -1002,6 +1004,9 @@ struct ata_port_operations { - void (*phy_reset)(struct ata_port *ap); - void (*eng_timeout)(struct ata_port *ap); - -+ int (*acquire_hw)(struct ata_port *ap, int may_sleep, -+ int timeout_jiffies); -+ - /* - * ->inherits must be the last field and all the preceding - * fields must be pointers. From c5c37886cff1705ba9be9b33df3ab121bd27fe6b Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 21 Oct 2022 20:47:26 +0100 Subject: [PATCH 05/80] oxnas: shuttle-kd20: fix thermal zone Fix typo ('_' vs '-') and add #cooling-cells to gpio-fan to get thermal zone into functional state. Signed-off-by: Daniel Golle --- .../linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts index 0bcd2fcf00..2cff439c25 100644 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts +++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts @@ -31,7 +31,7 @@ led-upgrade = &led_warn; }; - thermal_zones { + thermal-zones { chassis-thermal { /* Poll every 20 seconds */ polling-delay = <20000>; @@ -153,6 +153,7 @@ gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; gpio-fan,speed-map = <0 0 3000 1>; + #cooling-cells = <2>; }; gpio-poweroff { From eb758a8fec2cee24e528008052fa2bd58482ca3a Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 15 Sep 2022 17:09:28 +0300 Subject: [PATCH 06/80] at91: kernel v5.15: copy config and patches from 5.10 Copy kernel config and patches from 5.10. Along with it individual targets' config-default from 5.10 has been moved to config-5.10. Signed-off-by: Claudiu Beznea --- .../101-ARM-at91-build-dtb-for-q5xr5.patch | 10 + ...s-clock-at91-add-sama7g5-pll-defines.patch | 65 + ...-allow-SYS-and-CPU-PLLs-to-be-export.patch | 41 + ...aster-add-5th-divisor-for-mck-master.patch | 42 + ...-add-5th-divisor-for-mck0-layout-and.patch | 36 + ...9x60-pll-allow-runtime-changes-for-p.patch | 510 ++++ ...-remove-mck0-from-parent-list-of-oth.patch | 196 ++ ...5-decrease-lower-limit-for-MCK0-rate.patch | 30 + ...-do-not-allow-cpu-pll-to-go-higher-t.patch | 221 ++ ...91-clk-master-re-factor-master-clock.patch | 1230 ++++++++++ ...-clk-at91-sama7g5-register-cpu-clock.patch | 65 + ...91-Fix-the-declaration-of-the-clocks.patch | 181 ++ ...ial-typo-fixes-in-the-file-sama7g5.c.patch | 45 + ...-remove-all-kernel-doc-kernel-doc-wa.patch | 90 + ...serio-bits-as-platform-configuration.patch | 179 ++ ...capability-to-not-set-the-clock-rate.patch | 85 + ...-function-to-disable-all-macb-clocks.patch | 82 + ...-unprepare-clocks-in-case-of-failure.patch | 60 + ...dd-support-for-sama7g5-gem-interface.patch | 54 + ...d-support-for-sama7g5-emac-interface.patch | 39 + ...-ASoC-pcm5102a-Make-codec-selectable.patch | 28 + ...i2s-do-not-warn-if-muxclk-is-missing.patch | 30 + ...egulator-mcp16502-add-linear_min_sel.patch | 25 + ...02-adapt-for-get-set-on-other-regist.patch | 117 + ...-mcp16502-add-support-for-ramp-delay.patch | 141 ++ ...02-remove-void-documentation-of-stru.patch | 27 + ...alidate-selector-against-linear_min_.patch | 64 + ...re-do-not-continue-if-selector-match.patch | 26 + ...eturn-zero-for-selectors-lower-than-.patch | 64 + ...02-lpm-pin-can-be-optional-on-some-p.patch | 30 + ...4-add-support-for-fewer-lines-on-las.patch | 70 + ...ac-adapt-perid-for-mem2mem-operation.patch | 50 + ...ac-add-support-for-sama7g5-based-at_.patch | 280 +++ ...ac-add-AXI-priority-support-and-reco.patch | 113 + ...t-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch | 45 + ...0-SiP-types-added-to-soc-description.patch | 43 + .../137-drivers-soc-atmel-use-GENMASK.patch | 25 + ...l-fix-__initconst-should-be-placed-a.patch | 26 + ...l-add-per-soc-id-and-version-match-m.patch | 348 +++ ...rs-soc-atmel-add-support-for-sama7g5.patch | 87 + ...oc-atmel-add-spdx-license-identifier.patch | 49 + ...drivers-soc-atmel-fix-type-for-same7.patch | 28 + ...ers-timer-microchip-pit64b-Add-clock.patch | 173 ++ ...dc-Use-managed-DMA-buffer-allocation.patch | 135 ++ ...-sama5d2_shdwc-add-support-for-sama7.patch | 141 ++ ...-at91-pio4-add-support-for-slew-rate.patch | 121 + ...4-fix-Prefer-unsigned-int-to-bare-us.patch | 340 +++ ...ault-usrio-config-to-default-gem-con.patch | 58 + ...-prototypes-to-mutually-included-hea.patch | 108 + ...p-i2s-mcc-Add-compatible-for-SAMA7G5.patch | 46 + ...c-Add-multi-channel-support-for-I2S-.patch | 113 + ...s-mcc-Add-support-to-select-TDM-pins.patch | 108 + ...-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch | 187 ++ ...-at91-pio4-Fix-slew-rate-disablement.patch | 49 + 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(100%) create mode 100644 target/linux/at91/sam9x/config-5.15 rename target/linux/at91/sama5/{config-default => config-5.10} (100%) create mode 100644 target/linux/at91/sama5/config-5.15 rename target/linux/at91/sama7/{config-default => config-5.10} (100%) create mode 100644 target/linux/at91/sama7/config-5.15 diff --git a/target/linux/at91/patches-5.15/101-ARM-at91-build-dtb-for-q5xr5.patch b/target/linux/at91/patches-5.15/101-ARM-at91-build-dtb-for-q5xr5.patch new file mode 100644 index 0000000000..2bf8ca52ec --- /dev/null +++ b/target/linux/at91/patches-5.15/101-ARM-at91-build-dtb-for-q5xr5.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -41,6 +41,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ + at91-kizboxmini-mb.dtb \ + at91-kizboxmini-rd.dtb \ + at91-smartkiz.dtb \ ++ at91-q5xr5.dtb \ + at91-wb45n.dtb \ + at91sam9g15ek.dtb \ + at91sam9g25-gardena-smart-gateway.dtb \ diff --git a/target/linux/at91/patches-5.15/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch b/target/linux/at91/patches-5.15/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch new file mode 100644 index 0000000000..e684e5d4db --- /dev/null +++ b/target/linux/at91/patches-5.15/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch @@ -0,0 +1,65 @@ +From 44bb7c72cdd830f54fe18e730205f892d9cbfe39 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Thu, 19 Nov 2020 17:43:08 +0200 +Subject: [PATCH 102/247] dt-bindings: clock: at91: add sama7g5 pll defines + +Add SAMA7G5 specific PLL defines to be referenced in a phandle as a +PMC_TYPE_CORE clock. + +Suggested-by: Claudiu Beznea +Signed-off-by: Eugen Hristev +[claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c] +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605800597-16720-3-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 6 +++--- + include/dt-bindings/clock/at91.h | 10 ++++++++++ + 2 files changed, 13 insertions(+), 3 deletions(-) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -182,13 +182,13 @@ static const struct { + .p = "audiopll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, +- .eid = PMC_I2S0_MUX, }, ++ .eid = PMC_AUDIOPMCPLL, }, + + { .n = "audiopll_diviock", + .p = "audiopll_fracck", + .l = &pll_layout_divio, + .t = PLL_TYPE_DIV, +- .eid = PMC_I2S1_MUX, }, ++ .eid = PMC_AUDIOIOPLL, }, + }, + + [PLL_ID_ETH] = { +@@ -835,7 +835,7 @@ static void __init sama7g5_pmc_setup(str + if (IS_ERR(regmap)) + return; + +- sama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1, ++ sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1, + nck(sama7g5_systemck), + nck(sama7g5_periphck), + nck(sama7g5_gck), 8); +--- a/include/dt-bindings/clock/at91.h ++++ b/include/dt-bindings/clock/at91.h +@@ -25,6 +25,16 @@ + #define PMC_PLLBCK 8 + #define PMC_AUDIOPLLCK 9 + ++/* SAMA7G5 */ ++#define PMC_CPUPLL (PMC_MAIN + 1) ++#define PMC_SYSPLL (PMC_MAIN + 2) ++#define PMC_DDRPLL (PMC_MAIN + 3) ++#define PMC_IMGPLL (PMC_MAIN + 4) ++#define PMC_BAUDPLL (PMC_MAIN + 5) ++#define PMC_AUDIOPMCPLL (PMC_MAIN + 6) ++#define PMC_AUDIOIOPLL (PMC_MAIN + 7) ++#define PMC_ETHPLL (PMC_MAIN + 8) ++ + #ifndef AT91_PMC_MOSCS + #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ + #define AT91_PMC_LOCKA 1 /* PLLA Lock */ diff --git a/target/linux/at91/patches-5.15/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch b/target/linux/at91/patches-5.15/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch new file mode 100644 index 0000000000..cd50dee6e1 --- /dev/null +++ b/target/linux/at91/patches-5.15/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch @@ -0,0 +1,41 @@ +From 55c14526f970805a6bf2ed4b820f062334375abe Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Thu, 19 Nov 2020 17:43:09 +0200 +Subject: [PATCH 103/247] clk: at91: sama7g5: allow SYS and CPU PLLs to be + exported and referenced in DT + +Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock +from phandle in DT. + +Suggested-by: Claudiu Beznea +Signed-off-by: Eugen Hristev +[claudiu.beznea@microchip.com: adapt commit message, add CPU PLL] +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -117,7 +117,8 @@ static const struct { + .p = "cpupll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, +- .c = 1, }, ++ .c = 1, ++ .eid = PMC_CPUPLL, }, + }, + + [PLL_ID_SYS] = { +@@ -131,7 +132,8 @@ static const struct { + .p = "syspll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, +- .c = 1, }, ++ .c = 1, ++ .eid = PMC_SYSPLL, }, + }, + + [PLL_ID_DDR] = { diff --git a/target/linux/at91/patches-5.15/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch b/target/linux/at91/patches-5.15/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch new file mode 100644 index 0000000000..9feea82490 --- /dev/null +++ b/target/linux/at91/patches-5.15/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch @@ -0,0 +1,42 @@ +From b2349278894bb381fa26a8717d3093d53f08fd36 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Thu, 19 Nov 2020 17:43:10 +0200 +Subject: [PATCH 104/247] clk: at91: clk-master: add 5th divisor for mck master + +clk-master can have 5 divisors with a field width of 3 bits +on some products. + +Change the mask and number of divisors accordingly. + +Reported-by: Mihai Sain +Signed-off-by: Eugen Hristev +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605800597-16720-5-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-master.c | 2 +- + drivers/clk/at91/pmc.h | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -15,7 +15,7 @@ + #define MASTER_PRES_MASK 0x7 + #define MASTER_PRES_MAX MASTER_PRES_MASK + #define MASTER_DIV_SHIFT 8 +-#define MASTER_DIV_MASK 0x3 ++#define MASTER_DIV_MASK 0x7 + + #define PMC_MCR 0x30 + #define PMC_MCR_ID_MSK GENMASK(3, 0) +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -48,7 +48,7 @@ extern const struct clk_master_layout at + + struct clk_master_characteristics { + struct clk_range output; +- u32 divisors[4]; ++ u32 divisors[5]; + u8 have_div3_pres; + }; + diff --git a/target/linux/at91/patches-5.15/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch b/target/linux/at91/patches-5.15/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch new file mode 100644 index 0000000000..55e7f913c2 --- /dev/null +++ b/target/linux/at91/patches-5.15/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch @@ -0,0 +1,36 @@ +From c41f013e13962dcc78239d5e4834214d44556cfb Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Thu, 19 Nov 2020 17:43:11 +0200 +Subject: [PATCH 105/247] clk: at91: sama7g5: add 5th divisor for mck0 layout + and characteristics + +This SoC has the 5th divisor for the mck0 master clock. +Adapt the characteristics accordingly. + +Reported-by: Mihai Sain +Signed-off-by: Eugen Hristev +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -775,13 +775,13 @@ static const struct clk_pll_characterist + /* MCK0 characteristics. */ + static const struct clk_master_characteristics mck0_characteristics = { + .output = { .min = 140000000, .max = 200000000 }, +- .divisors = { 1, 2, 4, 3 }, ++ .divisors = { 1, 2, 4, 3, 5 }, + .have_div3_pres = 1, + }; + + /* MCK0 layout. */ + static const struct clk_master_layout mck0_layout = { +- .mask = 0x373, ++ .mask = 0x773, + .pres_shift = 4, + .offset = 0x28, + }; diff --git a/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch b/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch new file mode 100644 index 0000000000..fa76cbb5a3 --- /dev/null +++ b/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch @@ -0,0 +1,510 @@ +From 6fe2927863de96edf35d8357712dbf83a489f556 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 19 Nov 2020 17:43:12 +0200 +Subject: [PATCH 106/247] clk: at91: clk-sam9x60-pll: allow runtime changes for + pll + +Allow runtime frequency changes for PLLs registered with proper flags. +This is necessary for CPU PLL on SAMA7G5 which is used by DVFS. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-sam9x60-pll.c | 145 +++++++++++++++++++++++++---- + drivers/clk/at91/pmc.h | 4 +- + drivers/clk/at91/sam9x60.c | 22 ++++- + drivers/clk/at91/sama7g5.c | 67 +++++++++---- + 4 files changed, 197 insertions(+), 41 deletions(-) + +--- a/drivers/clk/at91/clk-sam9x60-pll.c ++++ b/drivers/clk/at91/clk-sam9x60-pll.c +@@ -229,6 +229,57 @@ static int sam9x60_frac_pll_set_rate(str + return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true); + } + ++static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ struct sam9x60_frac *frac = to_sam9x60_frac(core); ++ struct regmap *regmap = core->regmap; ++ unsigned long irqflags; ++ unsigned int val, cfrac, cmul; ++ long ret; ++ ++ ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true); ++ if (ret <= 0) ++ return ret; ++ ++ spin_lock_irqsave(core->lock, irqflags); ++ ++ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, ++ core->id); ++ regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val); ++ cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; ++ cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift; ++ ++ if (cmul == frac->mul && cfrac == frac->frac) ++ goto unlock; ++ ++ regmap_write(regmap, AT91_PMC_PLL_CTRL1, ++ (frac->mul << core->layout->mul_shift) | ++ (frac->frac << core->layout->frac_shift)); ++ ++ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, ++ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, ++ AT91_PMC_PLL_UPDT_UPDATE | core->id); ++ ++ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, ++ AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL, ++ AT91_PMC_PLL_CTRL0_ENLOCK | ++ AT91_PMC_PLL_CTRL0_ENPLL); ++ ++ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, ++ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, ++ AT91_PMC_PLL_UPDT_UPDATE | core->id); ++ ++ while (!sam9x60_pll_ready(regmap, core->id)) ++ cpu_relax(); ++ ++unlock: ++ spin_unlock_irqrestore(core->lock, irqflags); ++ ++ return ret; ++} ++ + static const struct clk_ops sam9x60_frac_pll_ops = { + .prepare = sam9x60_frac_pll_prepare, + .unprepare = sam9x60_frac_pll_unprepare, +@@ -238,6 +289,15 @@ static const struct clk_ops sam9x60_frac + .set_rate = sam9x60_frac_pll_set_rate, + }; + ++static const struct clk_ops sam9x60_frac_pll_ops_chg = { ++ .prepare = sam9x60_frac_pll_prepare, ++ .unprepare = sam9x60_frac_pll_unprepare, ++ .is_prepared = sam9x60_frac_pll_is_prepared, ++ .recalc_rate = sam9x60_frac_pll_recalc_rate, ++ .round_rate = sam9x60_frac_pll_round_rate, ++ .set_rate = sam9x60_frac_pll_set_rate_chg, ++}; ++ + static int sam9x60_div_pll_prepare(struct clk_hw *hw) + { + struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); +@@ -384,6 +444,44 @@ static int sam9x60_div_pll_set_rate(stru + return 0; + } + ++static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ struct sam9x60_div *div = to_sam9x60_div(core); ++ struct regmap *regmap = core->regmap; ++ unsigned long irqflags; ++ unsigned int val, cdiv; ++ ++ div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; ++ ++ spin_lock_irqsave(core->lock, irqflags); ++ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, ++ core->id); ++ regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); ++ cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; ++ ++ /* Stop if nothing changed. */ ++ if (cdiv == div->div) ++ goto unlock; ++ ++ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, ++ core->layout->div_mask, ++ (div->div << core->layout->div_shift)); ++ ++ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, ++ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, ++ AT91_PMC_PLL_UPDT_UPDATE | core->id); ++ ++ while (!sam9x60_pll_ready(regmap, core->id)) ++ cpu_relax(); ++ ++unlock: ++ spin_unlock_irqrestore(core->lock, irqflags); ++ ++ return 0; ++} ++ + static const struct clk_ops sam9x60_div_pll_ops = { + .prepare = sam9x60_div_pll_prepare, + .unprepare = sam9x60_div_pll_unprepare, +@@ -393,17 +491,26 @@ static const struct clk_ops sam9x60_div_ + .set_rate = sam9x60_div_pll_set_rate, + }; + ++static const struct clk_ops sam9x60_div_pll_ops_chg = { ++ .prepare = sam9x60_div_pll_prepare, ++ .unprepare = sam9x60_div_pll_unprepare, ++ .is_prepared = sam9x60_div_pll_is_prepared, ++ .recalc_rate = sam9x60_div_pll_recalc_rate, ++ .round_rate = sam9x60_div_pll_round_rate, ++ .set_rate = sam9x60_div_pll_set_rate_chg, ++}; ++ + struct clk_hw * __init + sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, + const char *name, const char *parent_name, + struct clk_hw *parent_hw, u8 id, + const struct clk_pll_characteristics *characteristics, +- const struct clk_pll_layout *layout, bool critical) ++ const struct clk_pll_layout *layout, u32 flags) + { + struct sam9x60_frac *frac; + struct clk_hw *hw; + struct clk_init_data init; +- unsigned long parent_rate, flags; ++ unsigned long parent_rate, irqflags; + unsigned int val; + int ret; + +@@ -417,10 +524,12 @@ sam9x60_clk_register_frac_pll(struct reg + init.name = name; + init.parent_names = &parent_name; + init.num_parents = 1; +- init.ops = &sam9x60_frac_pll_ops; +- init.flags = CLK_SET_RATE_GATE; +- if (critical) +- init.flags |= CLK_IS_CRITICAL; ++ if (flags & CLK_SET_RATE_GATE) ++ init.ops = &sam9x60_frac_pll_ops; ++ else ++ init.ops = &sam9x60_frac_pll_ops_chg; ++ ++ init.flags = flags; + + frac->core.id = id; + frac->core.hw.init = &init; +@@ -429,7 +538,7 @@ sam9x60_clk_register_frac_pll(struct reg + frac->core.regmap = regmap; + frac->core.lock = lock; + +- spin_lock_irqsave(frac->core.lock, flags); ++ spin_lock_irqsave(frac->core.lock, irqflags); + if (sam9x60_pll_ready(regmap, id)) { + regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, + AT91_PMC_PLL_UPDT_ID_MSK, id); +@@ -457,7 +566,7 @@ sam9x60_clk_register_frac_pll(struct reg + goto free; + } + } +- spin_unlock_irqrestore(frac->core.lock, flags); ++ spin_unlock_irqrestore(frac->core.lock, irqflags); + + hw = &frac->core.hw; + ret = clk_hw_register(NULL, hw); +@@ -469,7 +578,7 @@ sam9x60_clk_register_frac_pll(struct reg + return hw; + + free: +- spin_unlock_irqrestore(frac->core.lock, flags); ++ spin_unlock_irqrestore(frac->core.lock, irqflags); + kfree(frac); + return hw; + } +@@ -478,12 +587,12 @@ struct clk_hw * __init + sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, + const char *name, const char *parent_name, u8 id, + const struct clk_pll_characteristics *characteristics, +- const struct clk_pll_layout *layout, bool critical) ++ const struct clk_pll_layout *layout, u32 flags) + { + struct sam9x60_div *div; + struct clk_hw *hw; + struct clk_init_data init; +- unsigned long flags; ++ unsigned long irqflags; + unsigned int val; + int ret; + +@@ -497,11 +606,11 @@ sam9x60_clk_register_div_pll(struct regm + init.name = name; + init.parent_names = &parent_name; + init.num_parents = 1; +- init.ops = &sam9x60_div_pll_ops; +- init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | +- CLK_SET_RATE_PARENT; +- if (critical) +- init.flags |= CLK_IS_CRITICAL; ++ if (flags & CLK_SET_RATE_GATE) ++ init.ops = &sam9x60_div_pll_ops; ++ else ++ init.ops = &sam9x60_div_pll_ops_chg; ++ init.flags = flags; + + div->core.id = id; + div->core.hw.init = &init; +@@ -510,14 +619,14 @@ sam9x60_clk_register_div_pll(struct regm + div->core.regmap = regmap; + div->core.lock = lock; + +- spin_lock_irqsave(div->core.lock, flags); ++ spin_lock_irqsave(div->core.lock, irqflags); + + regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, + AT91_PMC_PLL_UPDT_ID_MSK, id); + regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); + div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val); + +- spin_unlock_irqrestore(div->core.lock, flags); ++ spin_unlock_irqrestore(div->core.lock, irqflags); + + hw = &div->core.hw; + ret = clk_hw_register(NULL, hw); +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -190,14 +190,14 @@ struct clk_hw * __init + sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, + const char *name, const char *parent_name, u8 id, + const struct clk_pll_characteristics *characteristics, +- const struct clk_pll_layout *layout, bool critical); ++ const struct clk_pll_layout *layout, u32 flags); + + struct clk_hw * __init + sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, + const char *name, const char *parent_name, + struct clk_hw *parent_hw, u8 id, + const struct clk_pll_characteristics *characteristics, +- const struct clk_pll_layout *layout, bool critical); ++ const struct clk_pll_layout *layout, u32 flags); + + struct clk_hw * __init + at91_clk_register_programmable(struct regmap *regmap, const char *name, +--- a/drivers/clk/at91/sam9x60.c ++++ b/drivers/clk/at91/sam9x60.c +@@ -224,13 +224,24 @@ static void __init sam9x60_pmc_setup(str + hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck", + "mainck", sam9x60_pmc->chws[PMC_MAIN], + 0, &plla_characteristics, +- &pll_frac_layout, true); ++ &pll_frac_layout, ++ /* ++ * This feeds pllack_divck which ++ * feeds CPU. It should not be ++ * disabled. ++ */ ++ CLK_IS_CRITICAL | CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + + hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck", + "pllack_fracck", 0, &plla_characteristics, +- &pll_div_layout, true); ++ &pll_div_layout, ++ /* ++ * This feeds CPU. It should not ++ * be disabled. ++ */ ++ CLK_IS_CRITICAL | CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + +@@ -239,13 +250,16 @@ static void __init sam9x60_pmc_setup(str + hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck", + "main_osc", main_osc_hw, 1, + &upll_characteristics, +- &pll_frac_layout, false); ++ &pll_frac_layout, CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + + hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck", + "upllck_fracck", 1, &upll_characteristics, +- &pll_div_layout, false); ++ &pll_div_layout, ++ CLK_SET_RATE_GATE | ++ CLK_SET_PARENT_GATE | ++ CLK_SET_RATE_PARENT); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -95,15 +95,15 @@ static const struct clk_pll_layout pll_l + * @p: clock parent + * @l: clock layout + * @t: clock type +- * @f: true if clock is critical and cannot be disabled ++ * @f: clock flags + * @eid: export index in sama7g5->chws[] array + */ + static const struct { + const char *n; + const char *p; + const struct clk_pll_layout *l; ++ unsigned long f; + u8 t; +- u8 c; + u8 eid; + } sama7g5_plls[][PLL_ID_MAX] = { + [PLL_ID_CPU] = { +@@ -111,13 +111,18 @@ static const struct { + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, +- .c = 1, }, ++ /* ++ * This feeds cpupll_divpmcck which feeds CPU. It should ++ * not be disabled. ++ */ ++ .f = CLK_IS_CRITICAL, }, + + { .n = "cpupll_divpmcck", + .p = "cpupll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, +- .c = 1, ++ /* This feeds CPU. It should not be disabled. */ ++ .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + .eid = PMC_CPUPLL, }, + }, + +@@ -126,13 +131,22 @@ static const struct { + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, +- .c = 1, }, ++ /* ++ * This feeds syspll_divpmcck which may feed critial parts ++ * of the systems like timers. Therefore it should not be ++ * disabled. ++ */ ++ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, + + { .n = "syspll_divpmcck", + .p = "syspll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, +- .c = 1, ++ /* ++ * This may feed critial parts of the systems like timers. ++ * Therefore it should not be disabled. ++ */ ++ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .eid = PMC_SYSPLL, }, + }, + +@@ -141,55 +155,71 @@ static const struct { + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, +- .c = 1, }, ++ /* ++ * This feeds ddrpll_divpmcck which feeds DDR. It should not ++ * be disabled. ++ */ ++ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, + + { .n = "ddrpll_divpmcck", + .p = "ddrpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, +- .c = 1, }, ++ /* This feeds DDR. It should not be disabled. */ ++ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, + }, + + [PLL_ID_IMG] = { + { .n = "imgpll_fracck", + .p = "mainck", + .l = &pll_layout_frac, +- .t = PLL_TYPE_FRAC, }, ++ .t = PLL_TYPE_FRAC, ++ .f = CLK_SET_RATE_GATE, }, + + { .n = "imgpll_divpmcck", + .p = "imgpll_fracck", + .l = &pll_layout_divpmc, +- .t = PLL_TYPE_DIV, }, ++ .t = PLL_TYPE_DIV, ++ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | ++ CLK_SET_RATE_PARENT, }, + }, + + [PLL_ID_BAUD] = { + { .n = "baudpll_fracck", + .p = "mainck", + .l = &pll_layout_frac, +- .t = PLL_TYPE_FRAC, }, ++ .t = PLL_TYPE_FRAC, ++ .f = CLK_SET_RATE_GATE, }, + + { .n = "baudpll_divpmcck", + .p = "baudpll_fracck", + .l = &pll_layout_divpmc, +- .t = PLL_TYPE_DIV, }, ++ .t = PLL_TYPE_DIV, ++ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | ++ CLK_SET_RATE_PARENT, }, + }, + + [PLL_ID_AUDIO] = { + { .n = "audiopll_fracck", + .p = "main_xtal", + .l = &pll_layout_frac, +- .t = PLL_TYPE_FRAC, }, ++ .t = PLL_TYPE_FRAC, ++ .f = CLK_SET_RATE_GATE, }, + + { .n = "audiopll_divpmcck", + .p = "audiopll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, ++ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | ++ CLK_SET_RATE_PARENT, + .eid = PMC_AUDIOPMCPLL, }, + + { .n = "audiopll_diviock", + .p = "audiopll_fracck", + .l = &pll_layout_divio, + .t = PLL_TYPE_DIV, ++ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | ++ CLK_SET_RATE_PARENT, + .eid = PMC_AUDIOIOPLL, }, + }, + +@@ -197,12 +227,15 @@ static const struct { + { .n = "ethpll_fracck", + .p = "main_xtal", + .l = &pll_layout_frac, +- .t = PLL_TYPE_FRAC, }, ++ .t = PLL_TYPE_FRAC, ++ .f = CLK_SET_RATE_GATE, }, + + { .n = "ethpll_divpmcck", + .p = "ethpll_fracck", + .l = &pll_layout_divpmc, +- .t = PLL_TYPE_DIV, }, ++ .t = PLL_TYPE_DIV, ++ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | ++ CLK_SET_RATE_PARENT, }, + }, + }; + +@@ -890,7 +923,7 @@ static void __init sama7g5_pmc_setup(str + sama7g5_plls[i][j].p, parent_hw, i, + &pll_characteristics, + sama7g5_plls[i][j].l, +- sama7g5_plls[i][j].c); ++ sama7g5_plls[i][j].f); + break; + + case PLL_TYPE_DIV: +@@ -899,7 +932,7 @@ static void __init sama7g5_pmc_setup(str + sama7g5_plls[i][j].p, i, + &pll_characteristics, + sama7g5_plls[i][j].l, +- sama7g5_plls[i][j].c); ++ sama7g5_plls[i][j].f); + break; + + default: diff --git a/target/linux/at91/patches-5.15/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch b/target/linux/at91/patches-5.15/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch new file mode 100644 index 0000000000..209c40cf2f --- /dev/null +++ b/target/linux/at91/patches-5.15/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch @@ -0,0 +1,196 @@ +From 7cfe2dfe5ac7c72b904e4b59b240caa42721ee07 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 19 Nov 2020 17:43:13 +0200 +Subject: [PATCH 107/247] clk: at91: sama7g5: remove mck0 from parent list of + other clocks + +MCK0 is changed at runtime by DVFS. Due to this, since not all IPs +are glitch free aware at MCK0 changes, remove MCK0 from parent list +of other clocks (e.g. generic clock, programmable/system clock, MCKX). + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605800597-16720-8-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 55 ++++++++++++++++++-------------------- + 1 file changed, 26 insertions(+), 29 deletions(-) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -280,7 +280,7 @@ static const struct { + .ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", }, + .ep_mux_table = { 5, 6, 7, }, + .ep_count = 3, +- .ep_chg_id = 6, }, ++ .ep_chg_id = 5, }, + + { .n = "mck4", + .id = 4, +@@ -313,7 +313,7 @@ static const struct { + }; + + /* Mux table for programmable clocks. */ +-static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, }; ++static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, }; + + /** + * Peripheral clock description +@@ -436,7 +436,7 @@ static const struct { + .pp = { "audiopll_divpmcck", }, + .pp_mux_table = { 9, }, + .pp_count = 1, +- .pp_chg_id = 4, }, ++ .pp_chg_id = 3, }, + + { .n = "csi_gclk", + .id = 33, +@@ -548,7 +548,7 @@ static const struct { + .pp = { "ethpll_divpmcck", }, + .pp_mux_table = { 10, }, + .pp_count = 1, +- .pp_chg_id = 4, }, ++ .pp_chg_id = 3, }, + + { .n = "gmac1_gclk", + .id = 52, +@@ -580,7 +580,7 @@ static const struct { + .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, + .pp_mux_table = { 5, 9, }, + .pp_count = 2, +- .pp_chg_id = 5, }, ++ .pp_chg_id = 4, }, + + { .n = "i2smcc1_gclk", + .id = 58, +@@ -588,7 +588,7 @@ static const struct { + .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, + .pp_mux_table = { 5, 9, }, + .pp_count = 2, +- .pp_chg_id = 5, }, ++ .pp_chg_id = 4, }, + + { .n = "mcan0_gclk", + .id = 61, +@@ -730,7 +730,7 @@ static const struct { + .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, + .pp_mux_table = { 5, 8, }, + .pp_count = 2, +- .pp_chg_id = 5, }, ++ .pp_chg_id = 4, }, + + { .n = "sdmmc1_gclk", + .id = 81, +@@ -738,7 +738,7 @@ static const struct { + .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, + .pp_mux_table = { 5, 8, }, + .pp_count = 2, +- .pp_chg_id = 5, }, ++ .pp_chg_id = 4, }, + + { .n = "sdmmc2_gclk", + .id = 82, +@@ -746,7 +746,7 @@ static const struct { + .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, + .pp_mux_table = { 5, 8, }, + .pp_count = 2, +- .pp_chg_id = 5, }, ++ .pp_chg_id = 4, }, + + { .n = "spdifrx_gclk", + .id = 84, +@@ -754,7 +754,7 @@ static const struct { + .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, + .pp_mux_table = { 5, 9, }, + .pp_count = 2, +- .pp_chg_id = 5, }, ++ .pp_chg_id = 4, }, + + { .n = "spdiftx_gclk", + .id = 85, +@@ -762,7 +762,7 @@ static const struct { + .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, + .pp_mux_table = { 5, 9, }, + .pp_count = 2, +- .pp_chg_id = 5, }, ++ .pp_chg_id = 4, }, + + { .n = "tcb0_ch0_gclk", + .id = 88, +@@ -961,9 +961,8 @@ static void __init sama7g5_pmc_setup(str + parent_names[0] = md_slck_name; + parent_names[1] = td_slck_name; + parent_names[2] = "mainck"; +- parent_names[3] = "mck0"; + for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) { +- u8 num_parents = 4 + sama7g5_mckx[i].ep_count; ++ u8 num_parents = 3 + sama7g5_mckx[i].ep_count; + u32 *mux_table; + + mux_table = kmalloc_array(num_parents, sizeof(*mux_table), +@@ -971,10 +970,10 @@ static void __init sama7g5_pmc_setup(str + if (!mux_table) + goto err_free; + +- SAMA7G5_INIT_TABLE(mux_table, 4); +- SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_mckx[i].ep_mux_table, ++ SAMA7G5_INIT_TABLE(mux_table, 3); ++ SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, + sama7g5_mckx[i].ep_count); +- SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_mckx[i].ep, ++ SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep, + sama7g5_mckx[i].ep_count); + + hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, +@@ -997,20 +996,19 @@ static void __init sama7g5_pmc_setup(str + parent_names[0] = md_slck_name; + parent_names[1] = td_slck_name; + parent_names[2] = "mainck"; +- parent_names[3] = "mck0"; +- parent_names[4] = "syspll_divpmcck"; +- parent_names[5] = "ddrpll_divpmcck"; +- parent_names[6] = "imgpll_divpmcck"; +- parent_names[7] = "baudpll_divpmcck"; +- parent_names[8] = "audiopll_divpmcck"; +- parent_names[9] = "ethpll_divpmcck"; ++ parent_names[3] = "syspll_divpmcck"; ++ parent_names[4] = "ddrpll_divpmcck"; ++ parent_names[5] = "imgpll_divpmcck"; ++ parent_names[6] = "baudpll_divpmcck"; ++ parent_names[7] = "audiopll_divpmcck"; ++ parent_names[8] = "ethpll_divpmcck"; + for (i = 0; i < 8; i++) { + char name[6]; + + snprintf(name, sizeof(name), "prog%d", i); + + hw = at91_clk_register_programmable(regmap, name, parent_names, +- 10, i, ++ 9, i, + &programmable_layout, + sama7g5_prog_mux_table); + if (IS_ERR(hw)) +@@ -1047,9 +1045,8 @@ static void __init sama7g5_pmc_setup(str + parent_names[0] = md_slck_name; + parent_names[1] = td_slck_name; + parent_names[2] = "mainck"; +- parent_names[3] = "mck0"; + for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) { +- u8 num_parents = 4 + sama7g5_gck[i].pp_count; ++ u8 num_parents = 3 + sama7g5_gck[i].pp_count; + u32 *mux_table; + + mux_table = kmalloc_array(num_parents, sizeof(*mux_table), +@@ -1057,10 +1054,10 @@ static void __init sama7g5_pmc_setup(str + if (!mux_table) + goto err_free; + +- SAMA7G5_INIT_TABLE(mux_table, 4); +- SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_gck[i].pp_mux_table, ++ SAMA7G5_INIT_TABLE(mux_table, 3); ++ SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, + sama7g5_gck[i].pp_count); +- SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_gck[i].pp, ++ SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp, + sama7g5_gck[i].pp_count); + + hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, diff --git a/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch b/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch new file mode 100644 index 0000000000..2bc1907cfb --- /dev/null +++ b/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch @@ -0,0 +1,30 @@ +From 8b88f1e9918c173b24b43015cdb713cdde9e4d17 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 19 Nov 2020 17:43:14 +0200 +Subject: [PATCH 108/247] clk: at91: sama7g5: decrease lower limit for MCK0 + rate + +On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and +CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is +also changed by DVFS to avoid over/under clocking of MCK0 consumers. +The lower limit is changed to be able to set MCK0 accordingly by +DVFS. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -807,7 +807,7 @@ static const struct clk_pll_characterist + + /* MCK0 characteristics. */ + static const struct clk_master_characteristics mck0_characteristics = { +- .output = { .min = 140000000, .max = 200000000 }, ++ .output = { .min = 50000000, .max = 200000000 }, + .divisors = { 1, 2, 4, 3, 5 }, + .have_div3_pres = 1, + }; diff --git a/target/linux/at91/patches-5.15/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch b/target/linux/at91/patches-5.15/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch new file mode 100644 index 0000000000..b11efc9d4e --- /dev/null +++ b/target/linux/at91/patches-5.15/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch @@ -0,0 +1,221 @@ +From 943ed75a2a5ab08582d3bc8025e8111903698763 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 19 Nov 2020 17:43:15 +0200 +Subject: [PATCH 109/247] clk: at91: sama7g5: do not allow cpu pll to go higher + than 1GHz + +Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher +than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at +1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 61 +++++++++++++++++++++++++++++--------- + 1 file changed, 47 insertions(+), 14 deletions(-) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -89,11 +89,40 @@ static const struct clk_pll_layout pll_l + .endiv_shift = 30, + }; + ++/* ++ * CPU PLL output range. ++ * Notice: The upper limit has been setup to 1000000002 due to hardware ++ * block which cannot output exactly 1GHz. ++ */ ++static const struct clk_range cpu_pll_outputs[] = { ++ { .min = 2343750, .max = 1000000002 }, ++}; ++ ++/* PLL output range. */ ++static const struct clk_range pll_outputs[] = { ++ { .min = 2343750, .max = 1200000000 }, ++}; ++ ++/* CPU PLL characteristics. */ ++static const struct clk_pll_characteristics cpu_pll_characteristics = { ++ .input = { .min = 12000000, .max = 50000000 }, ++ .num_output = ARRAY_SIZE(cpu_pll_outputs), ++ .output = cpu_pll_outputs, ++}; ++ ++/* PLL characteristics. */ ++static const struct clk_pll_characteristics pll_characteristics = { ++ .input = { .min = 12000000, .max = 50000000 }, ++ .num_output = ARRAY_SIZE(pll_outputs), ++ .output = pll_outputs, ++}; ++ + /** + * PLL clocks description + * @n: clock name + * @p: clock parent + * @l: clock layout ++ * @c: clock characteristics + * @t: clock type + * @f: clock flags + * @eid: export index in sama7g5->chws[] array +@@ -102,6 +131,7 @@ static const struct { + const char *n; + const char *p; + const struct clk_pll_layout *l; ++ const struct clk_pll_characteristics *c; + unsigned long f; + u8 t; + u8 eid; +@@ -110,6 +140,7 @@ static const struct { + { .n = "cpupll_fracck", + .p = "mainck", + .l = &pll_layout_frac, ++ .c = &cpu_pll_characteristics, + .t = PLL_TYPE_FRAC, + /* + * This feeds cpupll_divpmcck which feeds CPU. It should +@@ -120,6 +151,7 @@ static const struct { + { .n = "cpupll_divpmcck", + .p = "cpupll_fracck", + .l = &pll_layout_divpmc, ++ .c = &cpu_pll_characteristics, + .t = PLL_TYPE_DIV, + /* This feeds CPU. It should not be disabled. */ + .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, +@@ -130,6 +162,7 @@ static const struct { + { .n = "syspll_fracck", + .p = "mainck", + .l = &pll_layout_frac, ++ .c = &pll_characteristics, + .t = PLL_TYPE_FRAC, + /* + * This feeds syspll_divpmcck which may feed critial parts +@@ -141,6 +174,7 @@ static const struct { + { .n = "syspll_divpmcck", + .p = "syspll_fracck", + .l = &pll_layout_divpmc, ++ .c = &pll_characteristics, + .t = PLL_TYPE_DIV, + /* + * This may feed critial parts of the systems like timers. +@@ -154,6 +188,7 @@ static const struct { + { .n = "ddrpll_fracck", + .p = "mainck", + .l = &pll_layout_frac, ++ .c = &pll_characteristics, + .t = PLL_TYPE_FRAC, + /* + * This feeds ddrpll_divpmcck which feeds DDR. It should not +@@ -164,6 +199,7 @@ static const struct { + { .n = "ddrpll_divpmcck", + .p = "ddrpll_fracck", + .l = &pll_layout_divpmc, ++ .c = &pll_characteristics, + .t = PLL_TYPE_DIV, + /* This feeds DDR. It should not be disabled. */ + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, +@@ -173,12 +209,14 @@ static const struct { + { .n = "imgpll_fracck", + .p = "mainck", + .l = &pll_layout_frac, ++ .c = &pll_characteristics, + .t = PLL_TYPE_FRAC, + .f = CLK_SET_RATE_GATE, }, + + { .n = "imgpll_divpmcck", + .p = "imgpll_fracck", + .l = &pll_layout_divpmc, ++ .c = &pll_characteristics, + .t = PLL_TYPE_DIV, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, }, +@@ -188,12 +226,14 @@ static const struct { + { .n = "baudpll_fracck", + .p = "mainck", + .l = &pll_layout_frac, ++ .c = &pll_characteristics, + .t = PLL_TYPE_FRAC, + .f = CLK_SET_RATE_GATE, }, + + { .n = "baudpll_divpmcck", + .p = "baudpll_fracck", + .l = &pll_layout_divpmc, ++ .c = &pll_characteristics, + .t = PLL_TYPE_DIV, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, }, +@@ -203,12 +243,14 @@ static const struct { + { .n = "audiopll_fracck", + .p = "main_xtal", + .l = &pll_layout_frac, ++ .c = &pll_characteristics, + .t = PLL_TYPE_FRAC, + .f = CLK_SET_RATE_GATE, }, + + { .n = "audiopll_divpmcck", + .p = "audiopll_fracck", + .l = &pll_layout_divpmc, ++ .c = &pll_characteristics, + .t = PLL_TYPE_DIV, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, +@@ -217,6 +259,7 @@ static const struct { + { .n = "audiopll_diviock", + .p = "audiopll_fracck", + .l = &pll_layout_divio, ++ .c = &pll_characteristics, + .t = PLL_TYPE_DIV, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, +@@ -227,12 +270,14 @@ static const struct { + { .n = "ethpll_fracck", + .p = "main_xtal", + .l = &pll_layout_frac, ++ .c = &pll_characteristics, + .t = PLL_TYPE_FRAC, + .f = CLK_SET_RATE_GATE, }, + + { .n = "ethpll_divpmcck", + .p = "ethpll_fracck", + .l = &pll_layout_divpmc, ++ .c = &pll_characteristics, + .t = PLL_TYPE_DIV, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, }, +@@ -793,18 +838,6 @@ static const struct { + .pp_chg_id = INT_MIN, }, + }; + +-/* PLL output range. */ +-static const struct clk_range pll_outputs[] = { +- { .min = 2343750, .max = 1200000000 }, +-}; +- +-/* PLL characteristics. */ +-static const struct clk_pll_characteristics pll_characteristics = { +- .input = { .min = 12000000, .max = 50000000 }, +- .num_output = ARRAY_SIZE(pll_outputs), +- .output = pll_outputs, +-}; +- + /* MCK0 characteristics. */ + static const struct clk_master_characteristics mck0_characteristics = { + .output = { .min = 50000000, .max = 200000000 }, +@@ -921,7 +954,7 @@ static void __init sama7g5_pmc_setup(str + hw = sam9x60_clk_register_frac_pll(regmap, + &pmc_pll_lock, sama7g5_plls[i][j].n, + sama7g5_plls[i][j].p, parent_hw, i, +- &pll_characteristics, ++ sama7g5_plls[i][j].c, + sama7g5_plls[i][j].l, + sama7g5_plls[i][j].f); + break; +@@ -930,7 +963,7 @@ static void __init sama7g5_pmc_setup(str + hw = sam9x60_clk_register_div_pll(regmap, + &pmc_pll_lock, sama7g5_plls[i][j].n, + sama7g5_plls[i][j].p, i, +- &pll_characteristics, ++ sama7g5_plls[i][j].c, + sama7g5_plls[i][j].l, + sama7g5_plls[i][j].f); + break; diff --git a/target/linux/at91/patches-5.15/110-clk-at91-clk-master-re-factor-master-clock.patch b/target/linux/at91/patches-5.15/110-clk-at91-clk-master-re-factor-master-clock.patch new file mode 100644 index 0000000000..a0eadd8886 --- /dev/null +++ b/target/linux/at91/patches-5.15/110-clk-at91-clk-master-re-factor-master-clock.patch @@ -0,0 +1,1230 @@ +From 9109b768fe65994547ef464b13e508b22de3e89b Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 19 Nov 2020 17:43:16 +0200 +Subject: [PATCH 110/247] clk: at91: clk-master: re-factor master clock + +Re-factor master clock driver by splitting it into 2 clocks: prescaller +and divider clocks. Based on registered clock flags the prescaler's rate +could be changed at runtime. This is necessary for platforms supporting +DVFS (e.g. SAMA7G5) where master clock could be changed at run-time. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/at91rm9200.c | 21 ++- + drivers/clk/at91/at91sam9260.c | 26 ++- + drivers/clk/at91/at91sam9g45.c | 32 +++- + drivers/clk/at91/at91sam9n12.c | 36 ++-- + drivers/clk/at91/at91sam9rl.c | 23 ++- + drivers/clk/at91/at91sam9x5.c | 28 ++- + drivers/clk/at91/clk-master.c | 335 ++++++++++++++++++++++++++++----- + drivers/clk/at91/dt-compat.c | 15 +- + drivers/clk/at91/pmc.h | 16 +- + drivers/clk/at91/sam9x60.c | 23 ++- + drivers/clk/at91/sama5d2.c | 42 +++-- + drivers/clk/at91/sama5d3.c | 38 ++-- + drivers/clk/at91/sama5d4.c | 40 ++-- + drivers/clk/at91/sama7g5.c | 13 +- + 14 files changed, 542 insertions(+), 146 deletions(-) + +--- a/drivers/clk/at91/at91rm9200.c ++++ b/drivers/clk/at91/at91rm9200.c +@@ -7,6 +7,8 @@ + + #include "pmc.h" + ++static DEFINE_SPINLOCK(rm9200_mck_lock); ++ + struct sck { + char *n; + char *p; +@@ -137,9 +139,20 @@ static void __init at91rm9200_pmc_setup( + parent_names[1] = "mainck"; + parent_names[2] = "pllack"; + parent_names[3] = "pllbck"; +- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, +- &at91rm9200_master_layout, +- &rm9200_mck_characteristics); ++ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, ++ parent_names, ++ &at91rm9200_master_layout, ++ &rm9200_mck_characteristics, ++ &rm9200_mck_lock, CLK_SET_RATE_GATE, ++ INT_MIN); ++ if (IS_ERR(hw)) ++ goto err_free; ++ ++ hw = at91_clk_register_master_div(regmap, "masterck_div", ++ "masterck_pres", ++ &at91rm9200_master_layout, ++ &rm9200_mck_characteristics, ++ &rm9200_mck_lock, CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + +@@ -181,7 +194,7 @@ static void __init at91rm9200_pmc_setup( + for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) { + hw = at91_clk_register_peripheral(regmap, + at91rm9200_periphck[i].n, +- "masterck", ++ "masterck_div", + at91rm9200_periphck[i].id); + if (IS_ERR(hw)) + goto err_free; +--- a/drivers/clk/at91/at91sam9260.c ++++ b/drivers/clk/at91/at91sam9260.c +@@ -32,6 +32,8 @@ struct at91sam926x_data { + bool has_slck; + }; + ++static DEFINE_SPINLOCK(at91sam9260_mck_lock); ++ + static const struct clk_master_characteristics sam9260_mck_characteristics = { + .output = { .min = 0, .max = 105000000 }, + .divisors = { 1, 2, 4, 0 }, +@@ -218,8 +220,8 @@ static const struct sck at91sam9261_syst + { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "pck2", .p = "prog2", .id = 10 }, + { .n = "pck3", .p = "prog3", .id = 11 }, +- { .n = "hclk0", .p = "masterck", .id = 16 }, +- { .n = "hclk1", .p = "masterck", .id = 17 }, ++ { .n = "hclk0", .p = "masterck_div", .id = 16 }, ++ { .n = "hclk1", .p = "masterck_div", .id = 17 }, + }; + + static const struct pck at91sam9261_periphck[] = { +@@ -413,9 +415,21 @@ static void __init at91sam926x_pmc_setup + parent_names[1] = "mainck"; + parent_names[2] = "pllack"; + parent_names[3] = "pllbck"; +- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, +- &at91rm9200_master_layout, +- data->mck_characteristics); ++ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, ++ parent_names, ++ &at91rm9200_master_layout, ++ data->mck_characteristics, ++ &at91sam9260_mck_lock, ++ CLK_SET_RATE_GATE, INT_MIN); ++ if (IS_ERR(hw)) ++ goto err_free; ++ ++ hw = at91_clk_register_master_div(regmap, "masterck_div", ++ "masterck_pres", ++ &at91rm9200_master_layout, ++ data->mck_characteristics, ++ &at91sam9260_mck_lock, ++ CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + +@@ -457,7 +471,7 @@ static void __init at91sam926x_pmc_setup + for (i = 0; i < data->num_pck; i++) { + hw = at91_clk_register_peripheral(regmap, + data->pck[i].n, +- "masterck", ++ "masterck_div", + data->pck[i].id); + if (IS_ERR(hw)) + goto err_free; +--- a/drivers/clk/at91/at91sam9g45.c ++++ b/drivers/clk/at91/at91sam9g45.c +@@ -7,6 +7,8 @@ + + #include "pmc.h" + ++static DEFINE_SPINLOCK(at91sam9g45_mck_lock); ++ + static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 0, .max = 133333333 }, + .divisors = { 1, 2, 4, 3 }, +@@ -40,10 +42,10 @@ static const struct { + char *p; + u8 id; + } at91sam9g45_systemck[] = { +- { .n = "ddrck", .p = "masterck", .id = 2 }, +- { .n = "uhpck", .p = "usbck", .id = 6 }, +- { .n = "pck0", .p = "prog0", .id = 8 }, +- { .n = "pck1", .p = "prog1", .id = 9 }, ++ { .n = "ddrck", .p = "masterck_div", .id = 2 }, ++ { .n = "uhpck", .p = "usbck", .id = 6 }, ++ { .n = "pck0", .p = "prog0", .id = 8 }, ++ { .n = "pck1", .p = "prog1", .id = 9 }, + }; + + struct pck { +@@ -148,9 +150,21 @@ static void __init at91sam9g45_pmc_setup + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; +- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, +- &at91rm9200_master_layout, +- &mck_characteristics); ++ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, ++ parent_names, ++ &at91rm9200_master_layout, ++ &mck_characteristics, ++ &at91sam9g45_mck_lock, ++ CLK_SET_RATE_GATE, INT_MIN); ++ if (IS_ERR(hw)) ++ goto err_free; ++ ++ hw = at91_clk_register_master_div(regmap, "masterck_div", ++ "masterck_pres", ++ &at91rm9200_master_layout, ++ &mck_characteristics, ++ &at91sam9g45_mck_lock, ++ CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + +@@ -166,7 +180,7 @@ static void __init at91sam9g45_pmc_setup + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; +- parent_names[4] = "masterck"; ++ parent_names[4] = "masterck_div"; + for (i = 0; i < 2; i++) { + char name[6]; + +@@ -195,7 +209,7 @@ static void __init at91sam9g45_pmc_setup + for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) { + hw = at91_clk_register_peripheral(regmap, + at91sam9g45_periphck[i].n, +- "masterck", ++ "masterck_div", + at91sam9g45_periphck[i].id); + if (IS_ERR(hw)) + goto err_free; +--- a/drivers/clk/at91/at91sam9n12.c ++++ b/drivers/clk/at91/at91sam9n12.c +@@ -7,6 +7,8 @@ + + #include "pmc.h" + ++static DEFINE_SPINLOCK(at91sam9n12_mck_lock); ++ + static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 0, .max = 133333333 }, + .divisors = { 1, 2, 4, 3 }, +@@ -54,12 +56,12 @@ static const struct { + char *p; + u8 id; + } at91sam9n12_systemck[] = { +- { .n = "ddrck", .p = "masterck", .id = 2 }, +- { .n = "lcdck", .p = "masterck", .id = 3 }, +- { .n = "uhpck", .p = "usbck", .id = 6 }, +- { .n = "udpck", .p = "usbck", .id = 7 }, +- { .n = "pck0", .p = "prog0", .id = 8 }, +- { .n = "pck1", .p = "prog1", .id = 9 }, ++ { .n = "ddrck", .p = "masterck_div", .id = 2 }, ++ { .n = "lcdck", .p = "masterck_div", .id = 3 }, ++ { .n = "uhpck", .p = "usbck", .id = 6 }, ++ { .n = "udpck", .p = "usbck", .id = 7 }, ++ { .n = "pck0", .p = "prog0", .id = 8 }, ++ { .n = "pck1", .p = "prog1", .id = 9 }, + }; + + static const struct clk_pcr_layout at91sam9n12_pcr_layout = { +@@ -175,9 +177,21 @@ static void __init at91sam9n12_pmc_setup + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "pllbck"; +- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, +- &at91sam9x5_master_layout, +- &mck_characteristics); ++ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, ++ parent_names, ++ &at91sam9x5_master_layout, ++ &mck_characteristics, ++ &at91sam9n12_mck_lock, ++ CLK_SET_RATE_GATE, INT_MIN); ++ if (IS_ERR(hw)) ++ goto err_free; ++ ++ hw = at91_clk_register_master_div(regmap, "masterck_div", ++ "masterck_pres", ++ &at91sam9x5_master_layout, ++ &mck_characteristics, ++ &at91sam9n12_mck_lock, ++ CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + +@@ -191,7 +205,7 @@ static void __init at91sam9n12_pmc_setup + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "pllbck"; +- parent_names[4] = "masterck"; ++ parent_names[4] = "masterck_div"; + for (i = 0; i < 2; i++) { + char name[6]; + +@@ -221,7 +235,7 @@ static void __init at91sam9n12_pmc_setup + hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &at91sam9n12_pcr_layout, + at91sam9n12_periphck[i].n, +- "masterck", ++ "masterck_div", + at91sam9n12_periphck[i].id, + &range, INT_MIN); + if (IS_ERR(hw)) +--- a/drivers/clk/at91/at91sam9rl.c ++++ b/drivers/clk/at91/at91sam9rl.c +@@ -7,6 +7,8 @@ + + #include "pmc.h" + ++static DEFINE_SPINLOCK(sam9rl_mck_lock); ++ + static const struct clk_master_characteristics sam9rl_mck_characteristics = { + .output = { .min = 0, .max = 94000000 }, + .divisors = { 1, 2, 4, 0 }, +@@ -117,9 +119,20 @@ static void __init at91sam9rl_pmc_setup( + parent_names[1] = "mainck"; + parent_names[2] = "pllack"; + parent_names[3] = "utmick"; +- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, +- &at91rm9200_master_layout, +- &sam9rl_mck_characteristics); ++ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, ++ parent_names, ++ &at91rm9200_master_layout, ++ &sam9rl_mck_characteristics, ++ &sam9rl_mck_lock, CLK_SET_RATE_GATE, ++ INT_MIN); ++ if (IS_ERR(hw)) ++ goto err_free; ++ ++ hw = at91_clk_register_master_div(regmap, "masterck_div", ++ "masterck_pres", ++ &at91rm9200_master_layout, ++ &sam9rl_mck_characteristics, ++ &sam9rl_mck_lock, CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + +@@ -129,7 +142,7 @@ static void __init at91sam9rl_pmc_setup( + parent_names[1] = "mainck"; + parent_names[2] = "pllack"; + parent_names[3] = "utmick"; +- parent_names[4] = "masterck"; ++ parent_names[4] = "masterck_div"; + for (i = 0; i < 2; i++) { + char name[6]; + +@@ -158,7 +171,7 @@ static void __init at91sam9rl_pmc_setup( + for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) { + hw = at91_clk_register_peripheral(regmap, + at91sam9rl_periphck[i].n, +- "masterck", ++ "masterck_div", + at91sam9rl_periphck[i].id); + if (IS_ERR(hw)) + goto err_free; +--- a/drivers/clk/at91/at91sam9x5.c ++++ b/drivers/clk/at91/at91sam9x5.c +@@ -7,6 +7,8 @@ + + #include "pmc.h" + ++static DEFINE_SPINLOCK(mck_lock); ++ + static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 0, .max = 133333333 }, + .divisors = { 1, 2, 4, 3 }, +@@ -41,7 +43,7 @@ static const struct { + char *p; + u8 id; + } at91sam9x5_systemck[] = { +- { .n = "ddrck", .p = "masterck", .id = 2 }, ++ { .n = "ddrck", .p = "masterck_div", .id = 2 }, + { .n = "smdck", .p = "smdclk", .id = 4 }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "udpck", .p = "usbck", .id = 7 }, +@@ -196,9 +198,19 @@ static void __init at91sam9x5_pmc_setup( + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; +- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, +- &at91sam9x5_master_layout, +- &mck_characteristics); ++ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, ++ parent_names, ++ &at91sam9x5_master_layout, ++ &mck_characteristics, &mck_lock, ++ CLK_SET_RATE_GATE, INT_MIN); ++ if (IS_ERR(hw)) ++ goto err_free; ++ ++ hw = at91_clk_register_master_div(regmap, "masterck_div", ++ "masterck_pres", ++ &at91sam9x5_master_layout, ++ &mck_characteristics, &mck_lock, ++ CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + +@@ -218,7 +230,7 @@ static void __init at91sam9x5_pmc_setup( + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; +- parent_names[4] = "masterck"; ++ parent_names[4] = "masterck_div"; + for (i = 0; i < 2; i++) { + char name[6]; + +@@ -245,7 +257,7 @@ static void __init at91sam9x5_pmc_setup( + } + + if (has_lcdck) { +- hw = at91_clk_register_system(regmap, "lcdck", "masterck", 3); ++ hw = at91_clk_register_system(regmap, "lcdck", "masterck_div", 3); + if (IS_ERR(hw)) + goto err_free; + +@@ -256,7 +268,7 @@ static void __init at91sam9x5_pmc_setup( + hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &at91sam9x5_pcr_layout, + at91sam9x5_periphck[i].n, +- "masterck", ++ "masterck_div", + at91sam9x5_periphck[i].id, + &range, INT_MIN); + if (IS_ERR(hw)) +@@ -269,7 +281,7 @@ static void __init at91sam9x5_pmc_setup( + hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &at91sam9x5_pcr_layout, + extra_pcks[i].n, +- "masterck", ++ "masterck_div", + extra_pcks[i].id, + &range, INT_MIN); + if (IS_ERR(hw)) +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -58,83 +58,309 @@ static inline bool clk_master_ready(stru + static int clk_master_prepare(struct clk_hw *hw) + { + struct clk_master *master = to_clk_master(hw); ++ unsigned long flags; ++ ++ spin_lock_irqsave(master->lock, flags); + + while (!clk_master_ready(master)) + cpu_relax(); + ++ spin_unlock_irqrestore(master->lock, flags); ++ + return 0; + } + + static int clk_master_is_prepared(struct clk_hw *hw) + { + struct clk_master *master = to_clk_master(hw); ++ unsigned long flags; ++ bool status; ++ ++ spin_lock_irqsave(master->lock, flags); ++ status = clk_master_ready(master); ++ spin_unlock_irqrestore(master->lock, flags); + +- return clk_master_ready(master); ++ return status; + } + +-static unsigned long clk_master_recalc_rate(struct clk_hw *hw, +- unsigned long parent_rate) ++static unsigned long clk_master_div_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) + { +- u8 pres; + u8 div; +- unsigned long rate = parent_rate; ++ unsigned long flags, rate = parent_rate; + struct clk_master *master = to_clk_master(hw); + const struct clk_master_layout *layout = master->layout; + const struct clk_master_characteristics *characteristics = + master->characteristics; + unsigned int mckr; + ++ spin_lock_irqsave(master->lock, flags); + regmap_read(master->regmap, master->layout->offset, &mckr); ++ spin_unlock_irqrestore(master->lock, flags); ++ + mckr &= layout->mask; + +- pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK; + div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + +- if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX) +- rate /= 3; +- else +- rate >>= pres; +- + rate /= characteristics->divisors[div]; + + if (rate < characteristics->output.min) +- pr_warn("master clk is underclocked"); ++ pr_warn("master clk div is underclocked"); + else if (rate > characteristics->output.max) +- pr_warn("master clk is overclocked"); ++ pr_warn("master clk div is overclocked"); + + return rate; + } + +-static u8 clk_master_get_parent(struct clk_hw *hw) ++static const struct clk_ops master_div_ops = { ++ .prepare = clk_master_prepare, ++ .is_prepared = clk_master_is_prepared, ++ .recalc_rate = clk_master_div_recalc_rate, ++}; ++ ++static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ const struct clk_master_characteristics *characteristics = ++ master->characteristics; ++ unsigned long flags; ++ int div, i; ++ ++ div = DIV_ROUND_CLOSEST(parent_rate, rate); ++ if (div > ARRAY_SIZE(characteristics->divisors)) ++ return -EINVAL; ++ ++ for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { ++ if (!characteristics->divisors[i]) ++ break; ++ ++ if (div == characteristics->divisors[i]) { ++ div = i; ++ break; ++ } ++ } ++ ++ if (i == ARRAY_SIZE(characteristics->divisors)) ++ return -EINVAL; ++ ++ spin_lock_irqsave(master->lock, flags); ++ regmap_update_bits(master->regmap, master->layout->offset, ++ (MASTER_DIV_MASK << MASTER_DIV_SHIFT), ++ (div << MASTER_DIV_SHIFT)); ++ while (!clk_master_ready(master)) ++ cpu_relax(); ++ spin_unlock_irqrestore(master->lock, flags); ++ ++ return 0; ++} ++ ++static int clk_master_div_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ const struct clk_master_characteristics *characteristics = ++ master->characteristics; ++ struct clk_hw *parent; ++ unsigned long parent_rate, tmp_rate, best_rate = 0; ++ int i, best_diff = INT_MIN, tmp_diff; ++ ++ parent = clk_hw_get_parent(hw); ++ if (!parent) ++ return -EINVAL; ++ ++ parent_rate = clk_hw_get_rate(parent); ++ if (!parent_rate) ++ return -EINVAL; ++ ++ for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { ++ if (!characteristics->divisors[i]) ++ break; ++ ++ tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate, ++ characteristics->divisors[i]); ++ tmp_diff = abs(tmp_rate - req->rate); ++ ++ if (!best_rate || best_diff > tmp_diff) { ++ best_diff = tmp_diff; ++ best_rate = tmp_rate; ++ } ++ ++ if (!best_diff) ++ break; ++ } ++ ++ req->best_parent_rate = best_rate; ++ req->best_parent_hw = parent; ++ req->rate = best_rate; ++ ++ return 0; ++} ++ ++static const struct clk_ops master_div_ops_chg = { ++ .prepare = clk_master_prepare, ++ .is_prepared = clk_master_is_prepared, ++ .recalc_rate = clk_master_div_recalc_rate, ++ .determine_rate = clk_master_div_determine_rate, ++ .set_rate = clk_master_div_set_rate, ++}; ++ ++static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, ++ struct clk_hw *parent, ++ unsigned long parent_rate, ++ long *best_rate, ++ long *best_diff, ++ u32 div) ++{ ++ unsigned long tmp_rate, tmp_diff; ++ ++ if (div == MASTER_PRES_MAX) ++ tmp_rate = parent_rate / 3; ++ else ++ tmp_rate = parent_rate >> div; ++ ++ tmp_diff = abs(req->rate - tmp_rate); ++ ++ if (*best_diff < 0 || *best_diff >= tmp_diff) { ++ *best_rate = tmp_rate; ++ *best_diff = tmp_diff; ++ req->best_parent_rate = parent_rate; ++ req->best_parent_hw = parent; ++ } ++} ++ ++static int clk_master_pres_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ struct clk_rate_request req_parent = *req; ++ const struct clk_master_characteristics *characteristics = ++ master->characteristics; ++ struct clk_hw *parent; ++ long best_rate = LONG_MIN, best_diff = LONG_MIN; ++ u32 pres; ++ int i; ++ ++ if (master->chg_pid < 0) ++ return -EOPNOTSUPP; ++ ++ parent = clk_hw_get_parent_by_index(hw, master->chg_pid); ++ if (!parent) ++ return -EOPNOTSUPP; ++ ++ for (i = 0; i <= MASTER_PRES_MAX; i++) { ++ if (characteristics->have_div3_pres && i == MASTER_PRES_MAX) ++ pres = 3; ++ else ++ pres = 1 << i; ++ ++ req_parent.rate = req->rate * pres; ++ if (__clk_determine_rate(parent, &req_parent)) ++ continue; ++ ++ clk_sama7g5_master_best_diff(req, parent, req_parent.rate, ++ &best_diff, &best_rate, pres); ++ if (!best_diff) ++ break; ++ } ++ ++ return 0; ++} ++ ++static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ unsigned long flags; ++ unsigned int pres; ++ ++ pres = DIV_ROUND_CLOSEST(parent_rate, rate); ++ if (pres > MASTER_PRES_MAX) ++ return -EINVAL; ++ ++ else if (pres == 3) ++ pres = MASTER_PRES_MAX; ++ else ++ pres = ffs(pres) - 1; ++ ++ spin_lock_irqsave(master->lock, flags); ++ regmap_update_bits(master->regmap, master->layout->offset, ++ (MASTER_PRES_MASK << master->layout->pres_shift), ++ (pres << master->layout->pres_shift)); ++ ++ while (!clk_master_ready(master)) ++ cpu_relax(); ++ spin_unlock_irqrestore(master->lock, flags); ++ ++ return 0; ++} ++ ++static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ const struct clk_master_characteristics *characteristics = ++ master->characteristics; ++ unsigned long flags; ++ unsigned int val, pres; ++ ++ spin_lock_irqsave(master->lock, flags); ++ regmap_read(master->regmap, master->layout->offset, &val); ++ spin_unlock_irqrestore(master->lock, flags); ++ ++ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; ++ if (pres == 3 && characteristics->have_div3_pres) ++ pres = 3; ++ else ++ pres = (1 << pres); ++ ++ return DIV_ROUND_CLOSEST_ULL(parent_rate, pres); ++} ++ ++static u8 clk_master_pres_get_parent(struct clk_hw *hw) + { + struct clk_master *master = to_clk_master(hw); ++ unsigned long flags; + unsigned int mckr; + ++ spin_lock_irqsave(master->lock, flags); + regmap_read(master->regmap, master->layout->offset, &mckr); ++ spin_unlock_irqrestore(master->lock, flags); + + return mckr & AT91_PMC_CSS; + } + +-static const struct clk_ops master_ops = { ++static const struct clk_ops master_pres_ops = { + .prepare = clk_master_prepare, + .is_prepared = clk_master_is_prepared, +- .recalc_rate = clk_master_recalc_rate, +- .get_parent = clk_master_get_parent, ++ .recalc_rate = clk_master_pres_recalc_rate, ++ .get_parent = clk_master_pres_get_parent, + }; + +-struct clk_hw * __init +-at91_clk_register_master(struct regmap *regmap, ++static const struct clk_ops master_pres_ops_chg = { ++ .prepare = clk_master_prepare, ++ .is_prepared = clk_master_is_prepared, ++ .determine_rate = clk_master_pres_determine_rate, ++ .recalc_rate = clk_master_pres_recalc_rate, ++ .get_parent = clk_master_pres_get_parent, ++ .set_rate = clk_master_pres_set_rate, ++}; ++ ++static struct clk_hw * __init ++at91_clk_register_master_internal(struct regmap *regmap, + const char *name, int num_parents, + const char **parent_names, + const struct clk_master_layout *layout, +- const struct clk_master_characteristics *characteristics) ++ const struct clk_master_characteristics *characteristics, ++ const struct clk_ops *ops, spinlock_t *lock, u32 flags, ++ int chg_pid) + { + struct clk_master *master; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + +- if (!name || !num_parents || !parent_names) ++ if (!name || !num_parents || !parent_names || !lock) + return ERR_PTR(-EINVAL); + + master = kzalloc(sizeof(*master), GFP_KERNEL); +@@ -142,15 +368,17 @@ at91_clk_register_master(struct regmap * + return ERR_PTR(-ENOMEM); + + init.name = name; +- init.ops = &master_ops; ++ init.ops = ops; + init.parent_names = parent_names; + init.num_parents = num_parents; +- init.flags = 0; ++ init.flags = flags; + + master->hw.init = &init; + master->layout = layout; + master->characteristics = characteristics; + master->regmap = regmap; ++ master->chg_pid = chg_pid; ++ master->lock = lock; + + hw = &master->hw; + ret = clk_hw_register(NULL, &master->hw); +@@ -162,37 +390,54 @@ at91_clk_register_master(struct regmap * + return hw; + } + +-static unsigned long +-clk_sama7g5_master_recalc_rate(struct clk_hw *hw, +- unsigned long parent_rate) ++struct clk_hw * __init ++at91_clk_register_master_pres(struct regmap *regmap, ++ const char *name, int num_parents, ++ const char **parent_names, ++ const struct clk_master_layout *layout, ++ const struct clk_master_characteristics *characteristics, ++ spinlock_t *lock, u32 flags, int chg_pid) + { +- struct clk_master *master = to_clk_master(hw); ++ const struct clk_ops *ops; + +- return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); ++ if (flags & CLK_SET_RATE_GATE) ++ ops = &master_pres_ops; ++ else ++ ops = &master_pres_ops_chg; ++ ++ return at91_clk_register_master_internal(regmap, name, num_parents, ++ parent_names, layout, ++ characteristics, ops, ++ lock, flags, chg_pid); + } + +-static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, +- struct clk_hw *parent, +- unsigned long parent_rate, +- long *best_rate, +- long *best_diff, +- u32 div) ++struct clk_hw * __init ++at91_clk_register_master_div(struct regmap *regmap, ++ const char *name, const char *parent_name, ++ const struct clk_master_layout *layout, ++ const struct clk_master_characteristics *characteristics, ++ spinlock_t *lock, u32 flags) + { +- unsigned long tmp_rate, tmp_diff; ++ const struct clk_ops *ops; + +- if (div == MASTER_PRES_MAX) +- tmp_rate = parent_rate / 3; ++ if (flags & CLK_SET_RATE_GATE) ++ ops = &master_div_ops; + else +- tmp_rate = parent_rate >> div; ++ ops = &master_div_ops_chg; + +- tmp_diff = abs(req->rate - tmp_rate); ++ return at91_clk_register_master_internal(regmap, name, 1, ++ &parent_name, layout, ++ characteristics, ops, ++ lock, flags, -EINVAL); ++} + +- if (*best_diff < 0 || *best_diff >= tmp_diff) { +- *best_rate = tmp_rate; +- *best_diff = tmp_diff; +- req->best_parent_rate = parent_rate; +- req->best_parent_hw = parent; +- } ++static unsigned long ++clk_sama7g5_master_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ ++ return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); + } + + static int clk_sama7g5_master_determine_rate(struct clk_hw *hw, +--- a/drivers/clk/at91/dt-compat.c ++++ b/drivers/clk/at91/dt-compat.c +@@ -24,6 +24,8 @@ + + #define GCK_INDEX_DT_AUDIO_PLL 5 + ++static DEFINE_SPINLOCK(mck_lock); ++ + #ifdef CONFIG_HAVE_AT91_AUDIO_PLL + static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np) + { +@@ -388,9 +390,16 @@ of_at91_clk_master_setup(struct device_n + if (IS_ERR(regmap)) + return; + +- hw = at91_clk_register_master(regmap, name, num_parents, +- parent_names, layout, +- characteristics); ++ hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents, ++ parent_names, layout, ++ characteristics, &mck_lock, ++ CLK_SET_RATE_GATE, INT_MIN); ++ if (IS_ERR(hw)) ++ goto out_free_characteristics; ++ ++ hw = at91_clk_register_master_div(regmap, name, "masterck_pres", ++ layout, characteristics, ++ &mck_lock, CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto out_free_characteristics; + +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -155,10 +155,18 @@ at91_clk_register_sam9x5_main(struct reg + const char **parent_names, int num_parents); + + struct clk_hw * __init +-at91_clk_register_master(struct regmap *regmap, const char *name, +- int num_parents, const char **parent_names, +- const struct clk_master_layout *layout, +- const struct clk_master_characteristics *characteristics); ++at91_clk_register_master_pres(struct regmap *regmap, const char *name, ++ int num_parents, const char **parent_names, ++ const struct clk_master_layout *layout, ++ const struct clk_master_characteristics *characteristics, ++ spinlock_t *lock, u32 flags, int chg_pid); ++ ++struct clk_hw * __init ++at91_clk_register_master_div(struct regmap *regmap, const char *name, ++ const char *parent_names, ++ const struct clk_master_layout *layout, ++ const struct clk_master_characteristics *characteristics, ++ spinlock_t *lock, u32 flags); + + struct clk_hw * __init + at91_clk_sama7g5_register_master(struct regmap *regmap, +--- a/drivers/clk/at91/sam9x60.c ++++ b/drivers/clk/at91/sam9x60.c +@@ -8,6 +8,7 @@ + #include "pmc.h" + + static DEFINE_SPINLOCK(pmc_pll_lock); ++static DEFINE_SPINLOCK(mck_lock); + + static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 140000000, .max = 200000000 }, +@@ -76,11 +77,11 @@ static const struct { + char *p; + u8 id; + } sam9x60_systemck[] = { +- { .n = "ddrck", .p = "masterck", .id = 2 }, ++ { .n = "ddrck", .p = "masterck_div", .id = 2 }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, +- { .n = "qspick", .p = "masterck", .id = 19 }, ++ { .n = "qspick", .p = "masterck_div", .id = 19 }, + }; + + static const struct { +@@ -268,9 +269,17 @@ static void __init sam9x60_pmc_setup(str + parent_names[0] = md_slck_name; + parent_names[1] = "mainck"; + parent_names[2] = "pllack_divck"; +- hw = at91_clk_register_master(regmap, "masterck", 3, parent_names, +- &sam9x60_master_layout, +- &mck_characteristics); ++ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3, ++ parent_names, &sam9x60_master_layout, ++ &mck_characteristics, &mck_lock, ++ CLK_SET_RATE_GATE, INT_MIN); ++ if (IS_ERR(hw)) ++ goto err_free; ++ ++ hw = at91_clk_register_master_div(regmap, "masterck_div", ++ "masterck_pres", &sam9x60_master_layout, ++ &mck_characteristics, &mck_lock, ++ CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + +@@ -286,7 +295,7 @@ static void __init sam9x60_pmc_setup(str + parent_names[0] = md_slck_name; + parent_names[1] = td_slck_name; + parent_names[2] = "mainck"; +- parent_names[3] = "masterck"; ++ parent_names[3] = "masterck_div"; + parent_names[4] = "pllack_divck"; + parent_names[5] = "upllck_divck"; + for (i = 0; i < 2; i++) { +@@ -318,7 +327,7 @@ static void __init sam9x60_pmc_setup(str + hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &sam9x60_pcr_layout, + sam9x60_periphck[i].n, +- "masterck", ++ "masterck_div", + sam9x60_periphck[i].id, + &range, INT_MIN); + if (IS_ERR(hw)) +--- a/drivers/clk/at91/sama5d2.c ++++ b/drivers/clk/at91/sama5d2.c +@@ -7,6 +7,8 @@ + + #include "pmc.h" + ++static DEFINE_SPINLOCK(mck_lock); ++ + static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 124000000, .max = 166000000 }, + .divisors = { 1, 2, 4, 3 }, +@@ -40,14 +42,14 @@ static const struct { + char *p; + u8 id; + } sama5d2_systemck[] = { +- { .n = "ddrck", .p = "masterck", .id = 2 }, +- { .n = "lcdck", .p = "masterck", .id = 3 }, +- { .n = "uhpck", .p = "usbck", .id = 6 }, +- { .n = "udpck", .p = "usbck", .id = 7 }, +- { .n = "pck0", .p = "prog0", .id = 8 }, +- { .n = "pck1", .p = "prog1", .id = 9 }, +- { .n = "pck2", .p = "prog2", .id = 10 }, +- { .n = "iscck", .p = "masterck", .id = 18 }, ++ { .n = "ddrck", .p = "masterck_div", .id = 2 }, ++ { .n = "lcdck", .p = "masterck_div", .id = 3 }, ++ { .n = "uhpck", .p = "usbck", .id = 6 }, ++ { .n = "udpck", .p = "usbck", .id = 7 }, ++ { .n = "pck0", .p = "prog0", .id = 8 }, ++ { .n = "pck1", .p = "prog1", .id = 9 }, ++ { .n = "pck2", .p = "prog2", .id = 10 }, ++ { .n = "iscck", .p = "masterck_div", .id = 18 }, + }; + + static const struct { +@@ -235,15 +237,25 @@ static void __init sama5d2_pmc_setup(str + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; +- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, +- &at91sam9x5_master_layout, +- &mck_characteristics); ++ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, ++ parent_names, ++ &at91sam9x5_master_layout, ++ &mck_characteristics, &mck_lock, ++ CLK_SET_RATE_GATE, INT_MIN); ++ if (IS_ERR(hw)) ++ goto err_free; ++ ++ hw = at91_clk_register_master_div(regmap, "masterck_div", ++ "masterck_pres", ++ &at91sam9x5_master_layout, ++ &mck_characteristics, &mck_lock, ++ CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + + sama5d2_pmc->chws[PMC_MCK] = hw; + +- hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck"); ++ hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); + if (IS_ERR(hw)) + goto err_free; + +@@ -259,7 +271,7 @@ static void __init sama5d2_pmc_setup(str + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; +- parent_names[4] = "masterck"; ++ parent_names[4] = "masterck_div"; + parent_names[5] = "audiopll_pmcck"; + for (i = 0; i < 3; i++) { + char name[6]; +@@ -290,7 +302,7 @@ static void __init sama5d2_pmc_setup(str + hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &sama5d2_pcr_layout, + sama5d2_periphck[i].n, +- "masterck", ++ "masterck_div", + sama5d2_periphck[i].id, + &range, INT_MIN); + if (IS_ERR(hw)) +@@ -317,7 +329,7 @@ static void __init sama5d2_pmc_setup(str + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; +- parent_names[4] = "masterck"; ++ parent_names[4] = "masterck_div"; + parent_names[5] = "audiopll_pmcck"; + for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) { + hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, +--- a/drivers/clk/at91/sama5d3.c ++++ b/drivers/clk/at91/sama5d3.c +@@ -7,6 +7,8 @@ + + #include "pmc.h" + ++static DEFINE_SPINLOCK(mck_lock); ++ + static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 0, .max = 166000000 }, + .divisors = { 1, 2, 4, 3 }, +@@ -40,14 +42,14 @@ static const struct { + char *p; + u8 id; + } sama5d3_systemck[] = { +- { .n = "ddrck", .p = "masterck", .id = 2 }, +- { .n = "lcdck", .p = "masterck", .id = 3 }, +- { .n = "smdck", .p = "smdclk", .id = 4 }, +- { .n = "uhpck", .p = "usbck", .id = 6 }, +- { .n = "udpck", .p = "usbck", .id = 7 }, +- { .n = "pck0", .p = "prog0", .id = 8 }, +- { .n = "pck1", .p = "prog1", .id = 9 }, +- { .n = "pck2", .p = "prog2", .id = 10 }, ++ { .n = "ddrck", .p = "masterck_div", .id = 2 }, ++ { .n = "lcdck", .p = "masterck_div", .id = 3 }, ++ { .n = "smdck", .p = "smdclk", .id = 4 }, ++ { .n = "uhpck", .p = "usbck", .id = 6 }, ++ { .n = "udpck", .p = "usbck", .id = 7 }, ++ { .n = "pck0", .p = "prog0", .id = 8 }, ++ { .n = "pck1", .p = "prog1", .id = 9 }, ++ { .n = "pck2", .p = "prog2", .id = 10 }, + }; + + static const struct { +@@ -170,9 +172,19 @@ static void __init sama5d3_pmc_setup(str + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; +- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, +- &at91sam9x5_master_layout, +- &mck_characteristics); ++ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, ++ parent_names, ++ &at91sam9x5_master_layout, ++ &mck_characteristics, &mck_lock, ++ CLK_SET_RATE_GATE, INT_MIN); ++ if (IS_ERR(hw)) ++ goto err_free; ++ ++ hw = at91_clk_register_master_div(regmap, "masterck_div", ++ "masterck_pres", ++ &at91sam9x5_master_layout, ++ &mck_characteristics, &mck_lock, ++ CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + +@@ -192,7 +204,7 @@ static void __init sama5d3_pmc_setup(str + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; +- parent_names[4] = "masterck"; ++ parent_names[4] = "masterck_div"; + for (i = 0; i < 3; i++) { + char name[6]; + +@@ -222,7 +234,7 @@ static void __init sama5d3_pmc_setup(str + hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &sama5d3_pcr_layout, + sama5d3_periphck[i].n, +- "masterck", ++ "masterck_div", + sama5d3_periphck[i].id, + &sama5d3_periphck[i].r, + INT_MIN); +--- a/drivers/clk/at91/sama5d4.c ++++ b/drivers/clk/at91/sama5d4.c +@@ -7,6 +7,8 @@ + + #include "pmc.h" + ++static DEFINE_SPINLOCK(mck_lock); ++ + static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 125000000, .max = 200000000 }, + .divisors = { 1, 2, 4, 3 }, +@@ -39,14 +41,14 @@ static const struct { + char *p; + u8 id; + } sama5d4_systemck[] = { +- { .n = "ddrck", .p = "masterck", .id = 2 }, +- { .n = "lcdck", .p = "masterck", .id = 3 }, +- { .n = "smdck", .p = "smdclk", .id = 4 }, +- { .n = "uhpck", .p = "usbck", .id = 6 }, +- { .n = "udpck", .p = "usbck", .id = 7 }, +- { .n = "pck0", .p = "prog0", .id = 8 }, +- { .n = "pck1", .p = "prog1", .id = 9 }, +- { .n = "pck2", .p = "prog2", .id = 10 }, ++ { .n = "ddrck", .p = "masterck_div", .id = 2 }, ++ { .n = "lcdck", .p = "masterck_div", .id = 3 }, ++ { .n = "smdck", .p = "smdclk", .id = 4 }, ++ { .n = "uhpck", .p = "usbck", .id = 6 }, ++ { .n = "udpck", .p = "usbck", .id = 7 }, ++ { .n = "pck0", .p = "prog0", .id = 8 }, ++ { .n = "pck1", .p = "prog1", .id = 9 }, ++ { .n = "pck2", .p = "prog2", .id = 10 }, + }; + + static const struct { +@@ -185,15 +187,25 @@ static void __init sama5d4_pmc_setup(str + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; +- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, +- &at91sam9x5_master_layout, +- &mck_characteristics); ++ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, ++ parent_names, ++ &at91sam9x5_master_layout, ++ &mck_characteristics, &mck_lock, ++ CLK_SET_RATE_GATE, INT_MIN); ++ if (IS_ERR(hw)) ++ goto err_free; ++ ++ hw = at91_clk_register_master_div(regmap, "masterck_div", ++ "masterck_pres", ++ &at91sam9x5_master_layout, ++ &mck_characteristics, &mck_lock, ++ CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err_free; + + sama5d4_pmc->chws[PMC_MCK] = hw; + +- hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck"); ++ hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); + if (IS_ERR(hw)) + goto err_free; + +@@ -215,7 +227,7 @@ static void __init sama5d4_pmc_setup(str + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; +- parent_names[4] = "masterck"; ++ parent_names[4] = "masterck_div"; + for (i = 0; i < 3; i++) { + char name[6]; + +@@ -245,7 +257,7 @@ static void __init sama5d4_pmc_setup(str + hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &sama5d4_pcr_layout, + sama5d4_periphck[i].n, +- "masterck", ++ "masterck_div", + sama5d4_periphck[i].id, + &range, INT_MIN); + if (IS_ERR(hw)) +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -32,6 +32,7 @@ + } while (0) + + static DEFINE_SPINLOCK(pmc_pll_lock); ++static DEFINE_SPINLOCK(pmc_mck0_lock); + static DEFINE_SPINLOCK(pmc_mckX_lock); + + /** +@@ -984,8 +985,16 @@ static void __init sama7g5_pmc_setup(str + parent_names[1] = "mainck"; + parent_names[2] = "cpupll_divpmcck"; + parent_names[3] = "syspll_divpmcck"; +- hw = at91_clk_register_master(regmap, "mck0", 4, parent_names, +- &mck0_layout, &mck0_characteristics); ++ hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names, ++ &mck0_layout, &mck0_characteristics, ++ &pmc_mck0_lock, ++ CLK_SET_RATE_PARENT, 0); ++ if (IS_ERR(hw)) ++ goto err_free; ++ ++ hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres", ++ &mck0_layout, &mck0_characteristics, ++ &pmc_mck0_lock, 0); + if (IS_ERR(hw)) + goto err_free; + diff --git a/target/linux/at91/patches-5.15/111-clk-at91-sama7g5-register-cpu-clock.patch b/target/linux/at91/patches-5.15/111-clk-at91-sama7g5-register-cpu-clock.patch new file mode 100644 index 0000000000..dc55e32027 --- /dev/null +++ b/target/linux/at91/patches-5.15/111-clk-at91-sama7g5-register-cpu-clock.patch @@ -0,0 +1,65 @@ +From 36e97c421dd9f866e31fe14bcb7af01334791890 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 19 Nov 2020 17:43:17 +0200 +Subject: [PATCH 111/247] clk: at91: sama7g5: register cpu clock + +Register CPU clock as being the master clock prescaler. This would +be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider +between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the +frequencies supported by SAMA7G5 could be directly received from +CPUPLL + master clock prescaler and the extra divider would do no work in +case it would be enabled. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 13 ++++++------- + include/dt-bindings/clock/at91.h | 1 + + 2 files changed, 7 insertions(+), 7 deletions(-) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(str + if (IS_ERR(regmap)) + return; + +- sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1, ++ sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1, + nck(sama7g5_systemck), + nck(sama7g5_periphck), + nck(sama7g5_gck), 8); +@@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(str + } + } + +- parent_names[0] = md_slck_name; +- parent_names[1] = "mainck"; +- parent_names[2] = "cpupll_divpmcck"; +- parent_names[3] = "syspll_divpmcck"; +- hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names, ++ parent_names[0] = "cpupll_divpmcck"; ++ hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names, + &mck0_layout, &mck0_characteristics, + &pmc_mck0_lock, + CLK_SET_RATE_PARENT, 0); + if (IS_ERR(hw)) + goto err_free; + +- hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres", ++ sama7g5_pmc->chws[PMC_CPU] = hw; ++ ++ hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", + &mck0_layout, &mck0_characteristics, + &pmc_mck0_lock, 0); + if (IS_ERR(hw)) +--- a/include/dt-bindings/clock/at91.h ++++ b/include/dt-bindings/clock/at91.h +@@ -34,6 +34,7 @@ + #define PMC_AUDIOPMCPLL (PMC_MAIN + 6) + #define PMC_AUDIOIOPLL (PMC_MAIN + 7) + #define PMC_ETHPLL (PMC_MAIN + 8) ++#define PMC_CPU (PMC_MAIN + 9) + + #ifndef AT91_PMC_MOSCS + #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ diff --git a/target/linux/at91/patches-5.15/112-clk-at91-Fix-the-declaration-of-the-clocks.patch b/target/linux/at91/patches-5.15/112-clk-at91-Fix-the-declaration-of-the-clocks.patch new file mode 100644 index 0000000000..e989ed207e --- /dev/null +++ b/target/linux/at91/patches-5.15/112-clk-at91-Fix-the-declaration-of-the-clocks.patch @@ -0,0 +1,181 @@ +From 5a25e2437af0db535b17da352fb16680a8dfdeda Mon Sep 17 00:00:00 2001 +From: Tudor Ambarus +Date: Wed, 3 Feb 2021 17:43:32 +0200 +Subject: [PATCH 112/247] clk: at91: Fix the declaration of the clocks + +These are all "early clocks" that require initialization just at +of_clk_init() time. Use CLK_OF_DECLARE() to declare them. + +This also fixes a problem that was spotted when fw_devlink was +set to 'on' by default: the boards failed to boot. The reason is +that CLK_OF_DECLARE_DRIVER() clears the OF_POPULATED and causes +the consumers of the clock to be postponed by fw_devlink until +the second initialization routine of the clock has been completed. +One of the consumers of the clock is the timer, which is used as a +clocksource, and needs the clock initialized early. Postponing the +timers caused the fail at boot. + +Signed-off-by: Tudor Ambarus +Link: https://lore.kernel.org/r/20210203154332.470587-1-tudor.ambarus@microchip.com +Acked-by: Saravana Kannan +Tested-by: Eugen Hristev +Acked-by: Nicolas Ferre +Reviewed-by: Claudiu Beznea +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/at91rm9200.c | 3 +-- + drivers/clk/at91/at91sam9260.c | 16 ++++++++-------- + drivers/clk/at91/at91sam9g45.c | 3 +-- + drivers/clk/at91/at91sam9n12.c | 3 +-- + drivers/clk/at91/at91sam9rl.c | 3 ++- + drivers/clk/at91/at91sam9x5.c | 20 ++++++++++---------- + drivers/clk/at91/sama5d2.c | 3 ++- + drivers/clk/at91/sama5d3.c | 2 +- + drivers/clk/at91/sama5d4.c | 3 ++- + 9 files changed, 28 insertions(+), 28 deletions(-) + +--- a/drivers/clk/at91/at91rm9200.c ++++ b/drivers/clk/at91/at91rm9200.c +@@ -215,5 +215,4 @@ err_free: + * deferring properly. Once this is fixed, this can be switched to a platform + * driver. + */ +-CLK_OF_DECLARE_DRIVER(at91rm9200_pmc, "atmel,at91rm9200-pmc", +- at91rm9200_pmc_setup); ++CLK_OF_DECLARE(at91rm9200_pmc, "atmel,at91rm9200-pmc", at91rm9200_pmc_setup); +--- a/drivers/clk/at91/at91sam9260.c ++++ b/drivers/clk/at91/at91sam9260.c +@@ -491,26 +491,26 @@ static void __init at91sam9260_pmc_setup + { + at91sam926x_pmc_setup(np, &at91sam9260_data); + } +-CLK_OF_DECLARE_DRIVER(at91sam9260_pmc, "atmel,at91sam9260-pmc", +- at91sam9260_pmc_setup); ++ ++CLK_OF_DECLARE(at91sam9260_pmc, "atmel,at91sam9260-pmc", at91sam9260_pmc_setup); + + static void __init at91sam9261_pmc_setup(struct device_node *np) + { + at91sam926x_pmc_setup(np, &at91sam9261_data); + } +-CLK_OF_DECLARE_DRIVER(at91sam9261_pmc, "atmel,at91sam9261-pmc", +- at91sam9261_pmc_setup); ++ ++CLK_OF_DECLARE(at91sam9261_pmc, "atmel,at91sam9261-pmc", at91sam9261_pmc_setup); + + static void __init at91sam9263_pmc_setup(struct device_node *np) + { + at91sam926x_pmc_setup(np, &at91sam9263_data); + } +-CLK_OF_DECLARE_DRIVER(at91sam9263_pmc, "atmel,at91sam9263-pmc", +- at91sam9263_pmc_setup); ++ ++CLK_OF_DECLARE(at91sam9263_pmc, "atmel,at91sam9263-pmc", at91sam9263_pmc_setup); + + static void __init at91sam9g20_pmc_setup(struct device_node *np) + { + at91sam926x_pmc_setup(np, &at91sam9g20_data); + } +-CLK_OF_DECLARE_DRIVER(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", +- at91sam9g20_pmc_setup); ++ ++CLK_OF_DECLARE(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", at91sam9g20_pmc_setup); +--- a/drivers/clk/at91/at91sam9g45.c ++++ b/drivers/clk/at91/at91sam9g45.c +@@ -228,5 +228,4 @@ err_free: + * The TCB is used as the clocksource so its clock is needed early. This means + * this can't be a platform driver. + */ +-CLK_OF_DECLARE_DRIVER(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", +- at91sam9g45_pmc_setup); ++CLK_OF_DECLARE(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", at91sam9g45_pmc_setup); +--- a/drivers/clk/at91/at91sam9n12.c ++++ b/drivers/clk/at91/at91sam9n12.c +@@ -255,5 +255,4 @@ err_free: + * The TCB is used as the clocksource so its clock is needed early. This means + * this can't be a platform driver. + */ +-CLK_OF_DECLARE_DRIVER(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", +- at91sam9n12_pmc_setup); ++CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup); +--- a/drivers/clk/at91/at91sam9rl.c ++++ b/drivers/clk/at91/at91sam9rl.c +@@ -186,4 +186,5 @@ static void __init at91sam9rl_pmc_setup( + err_free: + kfree(at91sam9rl_pmc); + } +-CLK_OF_DECLARE_DRIVER(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup); ++ ++CLK_OF_DECLARE(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup); +--- a/drivers/clk/at91/at91sam9x5.c ++++ b/drivers/clk/at91/at91sam9x5.c +@@ -302,33 +302,33 @@ static void __init at91sam9g15_pmc_setup + { + at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true); + } +-CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", +- at91sam9g15_pmc_setup); ++ ++CLK_OF_DECLARE(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", at91sam9g15_pmc_setup); + + static void __init at91sam9g25_pmc_setup(struct device_node *np) + { + at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false); + } +-CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", +- at91sam9g25_pmc_setup); ++ ++CLK_OF_DECLARE(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", at91sam9g25_pmc_setup); + + static void __init at91sam9g35_pmc_setup(struct device_node *np) + { + at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true); + } +-CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", +- at91sam9g35_pmc_setup); ++ ++CLK_OF_DECLARE(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", at91sam9g35_pmc_setup); + + static void __init at91sam9x25_pmc_setup(struct device_node *np) + { + at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false); + } +-CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", +- at91sam9x25_pmc_setup); ++ ++CLK_OF_DECLARE(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", at91sam9x25_pmc_setup); + + static void __init at91sam9x35_pmc_setup(struct device_node *np) + { + at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true); + } +-CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", +- at91sam9x35_pmc_setup); ++ ++CLK_OF_DECLARE(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", at91sam9x35_pmc_setup); +--- a/drivers/clk/at91/sama5d2.c ++++ b/drivers/clk/at91/sama5d2.c +@@ -372,4 +372,5 @@ static void __init sama5d2_pmc_setup(str + err_free: + kfree(sama5d2_pmc); + } +-CLK_OF_DECLARE_DRIVER(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup); ++ ++CLK_OF_DECLARE(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup); +--- a/drivers/clk/at91/sama5d3.c ++++ b/drivers/clk/at91/sama5d3.c +@@ -255,4 +255,4 @@ err_free: + * The TCB is used as the clocksource so its clock is needed early. This means + * this can't be a platform driver. + */ +-CLK_OF_DECLARE_DRIVER(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup); ++CLK_OF_DECLARE(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup); +--- a/drivers/clk/at91/sama5d4.c ++++ b/drivers/clk/at91/sama5d4.c +@@ -286,4 +286,5 @@ static void __init sama5d4_pmc_setup(str + err_free: + kfree(sama5d4_pmc); + } +-CLK_OF_DECLARE_DRIVER(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup); ++ ++CLK_OF_DECLARE(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup); diff --git a/target/linux/at91/patches-5.15/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch b/target/linux/at91/patches-5.15/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch new file mode 100644 index 0000000000..f3ebee10fe --- /dev/null +++ b/target/linux/at91/patches-5.15/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch @@ -0,0 +1,45 @@ +From 268b36c42b7d1e480dd56ecfec626a46f4b5975e Mon Sep 17 00:00:00 2001 +From: Bhaskar Chowdhury +Date: Sat, 13 Mar 2021 11:02:22 +0530 +Subject: [PATCH 113/247] clk: at91: Trivial typo fixes in the file sama7g5.c + +s/critial/critical/ ......two different places +s/parrent/parent/ + +Signed-off-by: Bhaskar Chowdhury +Link: https://lore.kernel.org/r/20210313053222.14706-1-unixbhaskar@gmail.com +Acked-by: Randy Dunlap +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -166,7 +166,7 @@ static const struct { + .c = &pll_characteristics, + .t = PLL_TYPE_FRAC, + /* +- * This feeds syspll_divpmcck which may feed critial parts ++ * This feeds syspll_divpmcck which may feed critical parts + * of the systems like timers. Therefore it should not be + * disabled. + */ +@@ -178,7 +178,7 @@ static const struct { + .c = &pll_characteristics, + .t = PLL_TYPE_DIV, + /* +- * This may feed critial parts of the systems like timers. ++ * This may feed critical parts of the systems like timers. + * Therefore it should not be disabled. + */ + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, +@@ -455,7 +455,7 @@ static const struct { + * @pp: PLL parents + * @pp_mux_table: PLL parents mux table + * @r: clock output range +- * @pp_chg_id: id in parrent array of changeable PLL parent ++ * @pp_chg_id: id in parent array of changeable PLL parent + * @pp_count: PLL parents count + * @id: clock id + */ diff --git a/target/linux/at91/patches-5.15/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch b/target/linux/at91/patches-5.15/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch new file mode 100644 index 0000000000..a9ceda533b --- /dev/null +++ b/target/linux/at91/patches-5.15/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch @@ -0,0 +1,90 @@ +From 9997227090cf529675aeb775585ec9f6c2f0f131 Mon Sep 17 00:00:00 2001 +From: Randy Dunlap +Date: Thu, 19 Aug 2021 15:32:37 -0700 +Subject: [PATCH 114/247] clk: at91: sama7g5: remove all kernel-doc & + kernel-doc warnings + +Remove all "/**" kernel-doc markers from sama7g5.c since they are +all internal to this driver source file only. +This eliminates 14 warnings that were reported by the kernel test robot. + +Signed-off-by: Randy Dunlap +Reported-by: kernel test robot +Cc: Claudiu Beznea +Cc: Michael Turquette +Cc: Stephen Boyd +Cc: Eugen Hristev +Cc: linux-clk@vger.kernel.org +Cc: linux-arm-kernel@lists.infradead.org +Link: https://lore.kernel.org/r/20210819223237.20115-1-rdunlap@infradead.org +Reviewed-by: Claudiu Beznea +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -35,7 +35,7 @@ static DEFINE_SPINLOCK(pmc_pll_lock); + static DEFINE_SPINLOCK(pmc_mck0_lock); + static DEFINE_SPINLOCK(pmc_mckX_lock); + +-/** ++/* + * PLL clocks identifiers + * @PLL_ID_CPU: CPU PLL identifier + * @PLL_ID_SYS: System PLL identifier +@@ -56,7 +56,7 @@ enum pll_ids { + PLL_ID_MAX, + }; + +-/** ++/* + * PLL type identifiers + * @PLL_TYPE_FRAC: fractional PLL identifier + * @PLL_TYPE_DIV: divider PLL identifier +@@ -118,7 +118,7 @@ static const struct clk_pll_characterist + .output = pll_outputs, + }; + +-/** ++/* + * PLL clocks description + * @n: clock name + * @p: clock parent +@@ -285,7 +285,7 @@ static const struct { + }, + }; + +-/** ++/* + * Master clock (MCK[1..4]) description + * @n: clock name + * @ep: extra parents names array +@@ -337,7 +337,7 @@ static const struct { + .c = 1, }, + }; + +-/** ++/* + * System clock description + * @n: clock name + * @p: clock parent name +@@ -361,7 +361,7 @@ static const struct { + /* Mux table for programmable clocks. */ + static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, }; + +-/** ++/* + * Peripheral clock description + * @n: clock name + * @p: clock parent name +@@ -449,7 +449,7 @@ static const struct { + { .n = "uhphs_clk", .p = "mck1", .id = 106, }, + }; + +-/** ++/* + * Generic clock description + * @n: clock name + * @pp: PLL parents diff --git a/target/linux/at91/patches-5.15/115-net-macb-add-userio-bits-as-platform-configuration.patch b/target/linux/at91/patches-5.15/115-net-macb-add-userio-bits-as-platform-configuration.patch new file mode 100644 index 0000000000..79e7e62440 --- /dev/null +++ b/target/linux/at91/patches-5.15/115-net-macb-add-userio-bits-as-platform-configuration.patch @@ -0,0 +1,179 @@ +From 89f37ac2780d113d3c17d329726c0e92a1400744 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 9 Dec 2020 15:03:32 +0200 +Subject: [PATCH 115/247] net: macb: add userio bits as platform configuration + +This is necessary for SAMA7G5 as it uses different values for +PHY interface and also introduces hdfctlen bit. + +Signed-off-by: Claudiu Beznea +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/cadence/macb.h | 10 +++++++++ + drivers/net/ethernet/cadence/macb_main.c | 28 ++++++++++++++++++++---- + 2 files changed, 34 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/cadence/macb.h ++++ b/drivers/net/ethernet/cadence/macb.h +@@ -1104,6 +1104,14 @@ struct macb_pm_data { + u32 usrio; + }; + ++struct macb_usrio_config { ++ u32 mii; ++ u32 rmii; ++ u32 rgmii; ++ u32 refclk; ++ u32 hdfctlen; ++}; ++ + struct macb_config { + u32 caps; + unsigned int dma_burst_length; +@@ -1112,6 +1120,7 @@ struct macb_config { + struct clk **rx_clk, struct clk **tsu_clk); + int (*init)(struct platform_device *pdev); + int jumbo_max_len; ++ const struct macb_usrio_config *usrio; + }; + + struct tsu_incr { +@@ -1244,6 +1253,7 @@ struct macb { + u32 rx_intr_mask; + + struct macb_pm_data pm_data; ++ const struct macb_usrio_config *usrio; + }; + + #ifdef CONFIG_MACB_USE_HWSTAMP +--- a/drivers/net/ethernet/cadence/macb_main.c ++++ b/drivers/net/ethernet/cadence/macb_main.c +@@ -3831,15 +3831,15 @@ static int macb_init(struct platform_dev + if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) { + val = 0; + if (phy_interface_mode_is_rgmii(bp->phy_interface)) +- val = GEM_BIT(RGMII); ++ val = bp->usrio->rgmii; + else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII && + (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) +- val = MACB_BIT(RMII); ++ val = bp->usrio->rmii; + else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) +- val = MACB_BIT(MII); ++ val = bp->usrio->mii; + + if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN) +- val |= MACB_BIT(CLKEN); ++ val |= bp->usrio->refclk; + + macb_or_gem_writel(bp, USRIO, val); + } +@@ -4357,6 +4357,13 @@ static int fu540_c000_init(struct platfo + return macb_init(pdev); + } + ++static const struct macb_usrio_config macb_default_usrio = { ++ .mii = MACB_BIT(MII), ++ .rmii = MACB_BIT(RMII), ++ .rgmii = GEM_BIT(RGMII), ++ .refclk = MACB_BIT(CLKEN), ++}; ++ + static const struct macb_config fu540_c000_config = { + .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | + MACB_CAPS_GEM_HAS_PTP, +@@ -4364,12 +4371,14 @@ static const struct macb_config fu540_c0 + .clk_init = fu540_c000_clk_init, + .init = fu540_c000_init, + .jumbo_max_len = 10240, ++ .usrio = &macb_default_usrio, + }; + + static const struct macb_config at91sam9260_config = { + .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, + .clk_init = macb_clk_init, + .init = macb_init, ++ .usrio = &macb_default_usrio, + }; + + static const struct macb_config sama5d3macb_config = { +@@ -4377,6 +4386,7 @@ static const struct macb_config sama5d3m + | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, + .clk_init = macb_clk_init, + .init = macb_init, ++ .usrio = &macb_default_usrio, + }; + + static const struct macb_config pc302gem_config = { +@@ -4384,6 +4394,7 @@ static const struct macb_config pc302gem + .dma_burst_length = 16, + .clk_init = macb_clk_init, + .init = macb_init, ++ .usrio = &macb_default_usrio, + }; + + static const struct macb_config sama5d2_config = { +@@ -4391,6 +4402,7 @@ static const struct macb_config sama5d2_ + .dma_burst_length = 16, + .clk_init = macb_clk_init, + .init = macb_init, ++ .usrio = &macb_default_usrio, + }; + + static const struct macb_config sama5d3_config = { +@@ -4400,6 +4412,7 @@ static const struct macb_config sama5d3_ + .clk_init = macb_clk_init, + .init = macb_init, + .jumbo_max_len = 10240, ++ .usrio = &macb_default_usrio, + }; + + static const struct macb_config sama5d4_config = { +@@ -4407,18 +4420,21 @@ static const struct macb_config sama5d4_ + .dma_burst_length = 4, + .clk_init = macb_clk_init, + .init = macb_init, ++ .usrio = &macb_default_usrio, + }; + + static const struct macb_config emac_config = { + .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC, + .clk_init = at91ether_clk_init, + .init = at91ether_init, ++ .usrio = &macb_default_usrio, + }; + + static const struct macb_config np4_config = { + .caps = MACB_CAPS_USRIO_DISABLED, + .clk_init = macb_clk_init, + .init = macb_init, ++ .usrio = &macb_default_usrio, + }; + + static const struct macb_config zynqmp_config = { +@@ -4429,6 +4445,7 @@ static const struct macb_config zynqmp_c + .clk_init = macb_clk_init, + .init = macb_init, + .jumbo_max_len = 10240, ++ .usrio = &macb_default_usrio, + }; + + static const struct macb_config zynq_config = { +@@ -4437,6 +4454,7 @@ static const struct macb_config zynq_con + .dma_burst_length = 16, + .clk_init = macb_clk_init, + .init = macb_init, ++ .usrio = &macb_default_usrio, + }; + + static const struct of_device_id macb_dt_ids[] = { +@@ -4557,6 +4575,8 @@ static int macb_probe(struct platform_de + bp->wol |= MACB_WOL_HAS_MAGIC_PACKET; + device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET); + ++ bp->usrio = macb_config->usrio; ++ + spin_lock_init(&bp->lock); + + /* setup capabilities */ diff --git a/target/linux/at91/patches-5.15/116-net-macb-add-capability-to-not-set-the-clock-rate.patch b/target/linux/at91/patches-5.15/116-net-macb-add-capability-to-not-set-the-clock-rate.patch new file mode 100644 index 0000000000..87dde7ef60 --- /dev/null +++ b/target/linux/at91/patches-5.15/116-net-macb-add-capability-to-not-set-the-clock-rate.patch @@ -0,0 +1,85 @@ +From 1b15259551b701f416aa024050a2e619860bd0d8 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 9 Dec 2020 15:03:33 +0200 +Subject: [PATCH 116/247] net: macb: add capability to not set the clock rate + +SAMA7G5's ethernet IPs TX clock could be provided by its generic clock or +by the external clock provided by the PHY. The internal IP logic divides +properly this clock depending on the link speed. The patch adds a new +capability so that macb_set_tx_clock() to not be called for IPs having +this capability (the clock rate, in case of generic clock, is set at the +boot time via device tree and the driver only enables it). + +Signed-off-by: Claudiu Beznea +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/cadence/macb.h | 1 + + drivers/net/ethernet/cadence/macb_main.c | 18 +++++++++--------- + 2 files changed, 10 insertions(+), 9 deletions(-) + +--- a/drivers/net/ethernet/cadence/macb.h ++++ b/drivers/net/ethernet/cadence/macb.h +@@ -658,6 +658,7 @@ + #define MACB_CAPS_GEM_HAS_PTP 0x00000040 + #define MACB_CAPS_BD_RD_PREFETCH 0x00000080 + #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 ++#define MACB_CAPS_CLK_HW_CHG 0x04000000 + #define MACB_CAPS_MACB_IS_EMAC 0x08000000 + #define MACB_CAPS_FIFO_MODE 0x10000000 + #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 +--- a/drivers/net/ethernet/cadence/macb_main.c ++++ b/drivers/net/ethernet/cadence/macb_main.c +@@ -457,15 +457,14 @@ static void macb_init_buffers(struct mac + + /** + * macb_set_tx_clk() - Set a clock to a new frequency +- * @clk: Pointer to the clock to change ++ * @bp: pointer to struct macb + * @speed: New frequency in Hz +- * @dev: Pointer to the struct net_device + */ +-static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) ++static void macb_set_tx_clk(struct macb *bp, int speed) + { + long ferr, rate, rate_rounded; + +- if (!clk) ++ if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG)) + return; + + switch (speed) { +@@ -482,7 +481,7 @@ static void macb_set_tx_clk(struct clk * + return; + } + +- rate_rounded = clk_round_rate(clk, rate); ++ rate_rounded = clk_round_rate(bp->tx_clk, rate); + if (rate_rounded < 0) + return; + +@@ -492,11 +491,12 @@ static void macb_set_tx_clk(struct clk * + ferr = abs(rate_rounded - rate); + ferr = DIV_ROUND_UP(ferr, rate / 100000); + if (ferr > 5) +- netdev_warn(dev, "unable to generate target frequency: %ld Hz\n", ++ netdev_warn(bp->dev, ++ "unable to generate target frequency: %ld Hz\n", + rate); + +- if (clk_set_rate(clk, rate_rounded)) +- netdev_err(dev, "adjusting tx_clk failed.\n"); ++ if (clk_set_rate(bp->tx_clk, rate_rounded)) ++ netdev_err(bp->dev, "adjusting tx_clk failed.\n"); + } + + static void macb_validate(struct phylink_config *config, +@@ -649,7 +649,7 @@ static void macb_mac_link_up(struct phyl + if (rx_pause) + ctrl |= MACB_BIT(PAE); + +- macb_set_tx_clk(bp->tx_clk, speed, ndev); ++ macb_set_tx_clk(bp, speed); + + /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down + * cleared the pipeline and control registers. diff --git a/target/linux/at91/patches-5.15/117-net-macb-add-function-to-disable-all-macb-clocks.patch b/target/linux/at91/patches-5.15/117-net-macb-add-function-to-disable-all-macb-clocks.patch new file mode 100644 index 0000000000..a474f2a405 --- /dev/null +++ b/target/linux/at91/patches-5.15/117-net-macb-add-function-to-disable-all-macb-clocks.patch @@ -0,0 +1,82 @@ +From 935d9aae15ee245a1bc6e322cbef02566a8996cc Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 9 Dec 2020 15:03:34 +0200 +Subject: [PATCH 117/247] net: macb: add function to disable all macb clocks + +Add function to disable all macb clocks. + +Signed-off-by: Claudiu Beznea +Suggested-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/cadence/macb_main.c | 38 +++++++++++++----------- + 1 file changed, 21 insertions(+), 17 deletions(-) + +--- a/drivers/net/ethernet/cadence/macb_main.c ++++ b/drivers/net/ethernet/cadence/macb_main.c +@@ -3606,6 +3606,20 @@ static void macb_probe_queues(void __iom + *num_queues = hweight32(*queue_mask); + } + ++static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk, ++ struct clk *rx_clk, struct clk *tsu_clk) ++{ ++ struct clk_bulk_data clks[] = { ++ { .clk = tsu_clk, }, ++ { .clk = rx_clk, }, ++ { .clk = pclk, }, ++ { .clk = hclk, }, ++ { .clk = tx_clk }, ++ }; ++ ++ clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks); ++} ++ + static int macb_clk_init(struct platform_device *pdev, struct clk **pclk, + struct clk **hclk, struct clk **tx_clk, + struct clk **rx_clk, struct clk **tsu_clk) +@@ -4668,11 +4682,7 @@ err_out_free_netdev: + free_netdev(dev); + + err_disable_clocks: +- clk_disable_unprepare(tx_clk); +- clk_disable_unprepare(hclk); +- clk_disable_unprepare(pclk); +- clk_disable_unprepare(rx_clk); +- clk_disable_unprepare(tsu_clk); ++ macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk); + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); +@@ -4697,11 +4707,8 @@ static int macb_remove(struct platform_d + pm_runtime_disable(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); + if (!pm_runtime_suspended(&pdev->dev)) { +- clk_disable_unprepare(bp->tx_clk); +- clk_disable_unprepare(bp->hclk); +- clk_disable_unprepare(bp->pclk); +- clk_disable_unprepare(bp->rx_clk); +- clk_disable_unprepare(bp->tsu_clk); ++ macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, ++ bp->rx_clk, bp->tsu_clk); + pm_runtime_set_suspended(&pdev->dev); + } + phylink_destroy(bp->phylink); +@@ -4880,13 +4887,10 @@ static int __maybe_unused macb_runtime_s + struct net_device *netdev = dev_get_drvdata(dev); + struct macb *bp = netdev_priv(netdev); + +- if (!(device_may_wakeup(dev))) { +- clk_disable_unprepare(bp->tx_clk); +- clk_disable_unprepare(bp->hclk); +- clk_disable_unprepare(bp->pclk); +- clk_disable_unprepare(bp->rx_clk); +- } +- clk_disable_unprepare(bp->tsu_clk); ++ if (!(device_may_wakeup(dev))) ++ macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk); ++ else ++ macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk); + + return 0; + } diff --git a/target/linux/at91/patches-5.15/118-net-macb-unprepare-clocks-in-case-of-failure.patch b/target/linux/at91/patches-5.15/118-net-macb-unprepare-clocks-in-case-of-failure.patch new file mode 100644 index 0000000000..7456cc6c52 --- /dev/null +++ b/target/linux/at91/patches-5.15/118-net-macb-unprepare-clocks-in-case-of-failure.patch @@ -0,0 +1,60 @@ +From 9692c07ee8bf8f68b74d553d861d092e33264781 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 9 Dec 2020 15:03:35 +0200 +Subject: [PATCH 118/247] net: macb: unprepare clocks in case of failure + +Unprepare clocks in case of any failure in fu540_c000_clk_init(). + +Fixes: c218ad559020 ("macb: Add support for SiFive FU540-C000") +Signed-off-by: Claudiu Beznea +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/cadence/macb_main.c | 24 ++++++++++++++++++------ + 1 file changed, 18 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/cadence/macb_main.c ++++ b/drivers/net/ethernet/cadence/macb_main.c +@@ -4338,8 +4338,10 @@ static int fu540_c000_clk_init(struct pl + return err; + + mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL); +- if (!mgmt) +- return -ENOMEM; ++ if (!mgmt) { ++ err = -ENOMEM; ++ goto err_disable_clks; ++ } + + init.name = "sifive-gemgxl-mgmt"; + init.ops = &fu540_c000_ops; +@@ -4350,16 +4352,26 @@ static int fu540_c000_clk_init(struct pl + mgmt->hw.init = &init; + + *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw); +- if (IS_ERR(*tx_clk)) +- return PTR_ERR(*tx_clk); ++ if (IS_ERR(*tx_clk)) { ++ err = PTR_ERR(*tx_clk); ++ goto err_disable_clks; ++ } + + err = clk_prepare_enable(*tx_clk); +- if (err) ++ if (err) { + dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); +- else ++ *tx_clk = NULL; ++ goto err_disable_clks; ++ } else { + dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name); ++ } + + return 0; ++ ++err_disable_clks: ++ macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk); ++ ++ return err; + } + + static int fu540_c000_init(struct platform_device *pdev) diff --git a/target/linux/at91/patches-5.15/119-net-macb-add-support-for-sama7g5-gem-interface.patch b/target/linux/at91/patches-5.15/119-net-macb-add-support-for-sama7g5-gem-interface.patch new file mode 100644 index 0000000000..64abd3d6c0 --- /dev/null +++ b/target/linux/at91/patches-5.15/119-net-macb-add-support-for-sama7g5-gem-interface.patch @@ -0,0 +1,54 @@ +From 0085cd8576ceeaddeedf973b939b41ba96e3f77c Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 9 Dec 2020 15:03:38 +0200 +Subject: [PATCH 119/247] net: macb: add support for sama7g5 gem interface + +Add support for SAMA7G5 gigabit ethernet interface. + +Signed-off-by: Claudiu Beznea +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/cadence/macb_main.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/drivers/net/ethernet/cadence/macb_main.c ++++ b/drivers/net/ethernet/cadence/macb_main.c +@@ -4390,6 +4390,14 @@ static const struct macb_usrio_config ma + .refclk = MACB_BIT(CLKEN), + }; + ++static const struct macb_usrio_config sama7g5_usrio = { ++ .mii = 0, ++ .rmii = 1, ++ .rgmii = 2, ++ .refclk = BIT(2), ++ .hdfctlen = BIT(6), ++}; ++ + static const struct macb_config fu540_c000_config = { + .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | + MACB_CAPS_GEM_HAS_PTP, +@@ -4483,6 +4491,14 @@ static const struct macb_config zynq_con + .usrio = &macb_default_usrio, + }; + ++static const struct macb_config sama7g5_gem_config = { ++ .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG, ++ .dma_burst_length = 16, ++ .clk_init = macb_clk_init, ++ .init = macb_init, ++ .usrio = &sama7g5_usrio, ++}; ++ + static const struct of_device_id macb_dt_ids[] = { + { .compatible = "cdns,at32ap7000-macb" }, + { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, +@@ -4500,6 +4516,7 @@ static const struct of_device_id macb_dt + { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, + { .compatible = "cdns,zynq-gem", .data = &zynq_config }, + { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, ++ { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, macb_dt_ids); diff --git a/target/linux/at91/patches-5.15/120-net-macb-add-support-for-sama7g5-emac-interface.patch b/target/linux/at91/patches-5.15/120-net-macb-add-support-for-sama7g5-emac-interface.patch new file mode 100644 index 0000000000..50d31f736b --- /dev/null +++ b/target/linux/at91/patches-5.15/120-net-macb-add-support-for-sama7g5-emac-interface.patch @@ -0,0 +1,39 @@ +From a42f90357cfcfcf5cdade4594ad79a1eae633a9f Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 9 Dec 2020 15:03:39 +0200 +Subject: [PATCH 120/247] net: macb: add support for sama7g5 emac interface + +Add support for SAMA7G5 10/100Mbps interface. + +Signed-off-by: Claudiu Beznea +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/cadence/macb_main.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/net/ethernet/cadence/macb_main.c ++++ b/drivers/net/ethernet/cadence/macb_main.c +@@ -4499,6 +4499,14 @@ static const struct macb_config sama7g5_ + .usrio = &sama7g5_usrio, + }; + ++static const struct macb_config sama7g5_emac_config = { ++ .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_USRIO_HAS_CLKEN, ++ .dma_burst_length = 16, ++ .clk_init = macb_clk_init, ++ .init = macb_init, ++ .usrio = &sama7g5_usrio, ++}; ++ + static const struct of_device_id macb_dt_ids[] = { + { .compatible = "cdns,at32ap7000-macb" }, + { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, +@@ -4517,6 +4525,7 @@ static const struct of_device_id macb_dt + { .compatible = "cdns,zynq-gem", .data = &zynq_config }, + { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, + { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, ++ { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, macb_dt_ids); diff --git a/target/linux/at91/patches-5.15/121-ASoC-pcm5102a-Make-codec-selectable.patch b/target/linux/at91/patches-5.15/121-ASoC-pcm5102a-Make-codec-selectable.patch new file mode 100644 index 0000000000..8c918fd779 --- /dev/null +++ b/target/linux/at91/patches-5.15/121-ASoC-pcm5102a-Make-codec-selectable.patch @@ -0,0 +1,28 @@ +From 5ac0e1f5577b266543756521b1a749003b0f3686 Mon Sep 17 00:00:00 2001 +From: Codrin Ciubotariu +Date: Mon, 12 Oct 2020 17:19:11 +0300 +Subject: [PATCH 121/247] ASoC: pcm5102a: Make codec selectable + +The TI PCM5102A codec driver can be used with the generic sound card +drivers, so it should be selectable. For example, with the addition +of #sound-dai-cells = <0> property in DT, it can be used with simple/graph +card drivers. + +Signed-off-by: Codrin Ciubotariu +Link: https://lore.kernel.org/r/20201012141911.3150996-1-codrin.ciubotariu@microchip.com +Signed-off-by: Mark Brown +--- + sound/soc/codecs/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -1007,7 +1007,7 @@ config SND_SOC_PCM3168A_SPI + select REGMAP_SPI + + config SND_SOC_PCM5102A +- tristate ++ tristate "Texas Instruments PCM5102A CODEC" + + config SND_SOC_PCM512x + tristate diff --git a/target/linux/at91/patches-5.15/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch b/target/linux/at91/patches-5.15/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch new file mode 100644 index 0000000000..978b68184e --- /dev/null +++ b/target/linux/at91/patches-5.15/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch @@ -0,0 +1,30 @@ +From f4389949bf422fe04775c17b833100fa0e95ea68 Mon Sep 17 00:00:00 2001 +From: Codrin Ciubotariu +Date: Tue, 3 Nov 2020 12:05:54 +0200 +Subject: [PATCH 122/247] ASoC: atmel-i2s: do not warn if muxclk is missing + +Besides the fact that muxclk is optional, muxclk can be set using +assigned-clocks, removing the need to set it in driver. The warning is +thus unneeded, so we can transform it in a debug print, eventually to just +reflect that muxclk was not set by the driver. + +Signed-off-by: Codrin Ciubotariu +Link: https://lore.kernel.org/r/20201103100554.1307190-1-codrin.ciubotariu@microchip.com +Signed-off-by: Mark Brown +--- + sound/soc/atmel/atmel-i2s.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/sound/soc/atmel/atmel-i2s.c ++++ b/sound/soc/atmel/atmel-i2s.c +@@ -581,8 +581,8 @@ static int atmel_i2s_sama5d2_mck_init(st + err = PTR_ERR(muxclk); + if (err == -EPROBE_DEFER) + return -EPROBE_DEFER; +- dev_warn(dev->dev, +- "failed to get the I2S clock control: %d\n", err); ++ dev_dbg(dev->dev, ++ "failed to get the I2S clock control: %d\n", err); + return 0; + } + diff --git a/target/linux/at91/patches-5.15/123-regulator-mcp16502-add-linear_min_sel.patch b/target/linux/at91/patches-5.15/123-regulator-mcp16502-add-linear_min_sel.patch new file mode 100644 index 0000000000..ce97be4b77 --- /dev/null +++ b/target/linux/at91/patches-5.15/123-regulator-mcp16502-add-linear_min_sel.patch @@ -0,0 +1,25 @@ +From f5a73f3bb600b96b6149f2115360e1d0d51fbac4 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Fri, 13 Nov 2020 17:21:07 +0200 +Subject: [PATCH 123/247] regulator: mcp16502: add linear_min_sel + +Selectors b/w zero and VDD_LOW_SEL are not valid. Use linear_min_sel. + +Fixes: 919261c03e7ca ("regulator: mcp16502: add regulator driver for MCP16502") +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605280870-32432-4-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Mark Brown +--- + drivers/regulator/mcp16502.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/regulator/mcp16502.c ++++ b/drivers/regulator/mcp16502.c +@@ -93,6 +93,7 @@ static unsigned int mcp16502_of_map_mode + .owner = THIS_MODULE, \ + .n_voltages = MCP16502_VSEL + 1, \ + .linear_ranges = _ranges, \ ++ .linear_min_sel = VDD_LOW_SEL, \ + .n_linear_ranges = ARRAY_SIZE(_ranges), \ + .of_match = of_match_ptr(_name), \ + .of_map_mode = mcp16502_of_map_mode, \ diff --git a/target/linux/at91/patches-5.15/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch b/target/linux/at91/patches-5.15/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch new file mode 100644 index 0000000000..f371266c78 --- /dev/null +++ b/target/linux/at91/patches-5.15/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch @@ -0,0 +1,117 @@ +From 5295f4c122258a11fb6012b7e043248e681db5a2 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Fri, 13 Nov 2020 17:21:08 +0200 +Subject: [PATCH 124/247] regulator: mcp16502: adapt for get/set on other + registers + +MCP16502 have multiple registers for each regulator (as described +in enum mcp16502_reg). Adapt the code to be able to get/set all these +registers. This is necessary for the following commits. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605280870-32432-5-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Mark Brown +--- + drivers/regulator/mcp16502.c | 43 ++++++++++++++++++++++-------------- + 1 file changed, 27 insertions(+), 16 deletions(-) + +--- a/drivers/regulator/mcp16502.c ++++ b/drivers/regulator/mcp16502.c +@@ -54,13 +54,9 @@ + * This function is useful for iterating over all regulators and accessing their + * registers in a generic way or accessing a regulator device by its id. + */ +-#define MCP16502_BASE(i) (((i) + 1) << 4) ++#define MCP16502_REG_BASE(i, r) ((((i) + 1) << 4) + MCP16502_REG_##r) + #define MCP16502_STAT_BASE(i) ((i) + 5) + +-#define MCP16502_OFFSET_MODE_A 0 +-#define MCP16502_OFFSET_MODE_LPM 1 +-#define MCP16502_OFFSET_MODE_HIB 2 +- + #define MCP16502_OPMODE_ACTIVE REGULATOR_MODE_NORMAL + #define MCP16502_OPMODE_LPM REGULATOR_MODE_IDLE + #define MCP16502_OPMODE_HIB REGULATOR_MODE_STANDBY +@@ -75,6 +71,23 @@ + #define MCP16502_MIN_REG 0x0 + #define MCP16502_MAX_REG 0x65 + ++/** ++ * enum mcp16502_reg - MCP16502 regulators's registers ++ * @MCP16502_REG_A: active state register ++ * @MCP16502_REG_LPM: low power mode state register ++ * @MCP16502_REG_HIB: hibernate state register ++ * @MCP16502_REG_SEQ: startup sequence register ++ * @MCP16502_REG_CFG: configuration register ++ */ ++enum mcp16502_reg { ++ MCP16502_REG_A, ++ MCP16502_REG_LPM, ++ MCP16502_REG_HIB, ++ MCP16502_REG_HPM, ++ MCP16502_REG_SEQ, ++ MCP16502_REG_CFG, ++}; ++ + static unsigned int mcp16502_of_map_mode(unsigned int mode) + { + if (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE) +@@ -144,22 +157,20 @@ static void mcp16502_gpio_set_mode(struc + } + + /* +- * mcp16502_get_reg() - get the PMIC's configuration register for opmode ++ * mcp16502_get_reg() - get the PMIC's state configuration register for opmode + * + * @rdev: the regulator whose register we are searching + * @opmode: the PMIC's operating mode ACTIVE, Low-power, Hibernate + */ +-static int mcp16502_get_reg(struct regulator_dev *rdev, int opmode) ++static int mcp16502_get_state_reg(struct regulator_dev *rdev, int opmode) + { +- int reg = MCP16502_BASE(rdev_get_id(rdev)); +- + switch (opmode) { + case MCP16502_OPMODE_ACTIVE: +- return reg + MCP16502_OFFSET_MODE_A; ++ return MCP16502_REG_BASE(rdev_get_id(rdev), A); + case MCP16502_OPMODE_LPM: +- return reg + MCP16502_OFFSET_MODE_LPM; ++ return MCP16502_REG_BASE(rdev_get_id(rdev), LPM); + case MCP16502_OPMODE_HIB: +- return reg + MCP16502_OFFSET_MODE_HIB; ++ return MCP16502_REG_BASE(rdev_get_id(rdev), HIB); + default: + return -EINVAL; + } +@@ -179,7 +190,7 @@ static unsigned int mcp16502_get_mode(st + unsigned int val; + int ret, reg; + +- reg = mcp16502_get_reg(rdev, MCP16502_OPMODE_ACTIVE); ++ reg = mcp16502_get_state_reg(rdev, MCP16502_OPMODE_ACTIVE); + if (reg < 0) + return reg; + +@@ -210,7 +221,7 @@ static int _mcp16502_set_mode(struct reg + int val; + int reg; + +- reg = mcp16502_get_reg(rdev, op_mode); ++ reg = mcp16502_get_state_reg(rdev, op_mode); + if (reg < 0) + return reg; + +@@ -269,10 +280,10 @@ static int mcp16502_suspend_get_target_r + { + switch (pm_suspend_target_state) { + case PM_SUSPEND_STANDBY: +- return mcp16502_get_reg(rdev, MCP16502_OPMODE_LPM); ++ return mcp16502_get_state_reg(rdev, MCP16502_OPMODE_LPM); + case PM_SUSPEND_ON: + case PM_SUSPEND_MEM: +- return mcp16502_get_reg(rdev, MCP16502_OPMODE_HIB); ++ return mcp16502_get_state_reg(rdev, MCP16502_OPMODE_HIB); + default: + dev_err(&rdev->dev, "invalid suspend target: %d\n", + pm_suspend_target_state); diff --git a/target/linux/at91/patches-5.15/125-regulator-mcp16502-add-support-for-ramp-delay.patch b/target/linux/at91/patches-5.15/125-regulator-mcp16502-add-support-for-ramp-delay.patch new file mode 100644 index 0000000000..c91dd4a18b --- /dev/null +++ b/target/linux/at91/patches-5.15/125-regulator-mcp16502-add-support-for-ramp-delay.patch @@ -0,0 +1,141 @@ +From 7f13433e11a3c88f1fd6417c4c5e5a6c98370b9a Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Fri, 13 Nov 2020 17:21:09 +0200 +Subject: [PATCH 125/247] regulator: mcp16502: add support for ramp delay + +MCP16502 have configurable ramp delay support (via DVSR bits in +regulators' CFG register). + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605280870-32432-6-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Mark Brown +--- + drivers/regulator/mcp16502.c | 89 +++++++++++++++++++++++++++++++++++- + 1 file changed, 87 insertions(+), 2 deletions(-) + +--- a/drivers/regulator/mcp16502.c ++++ b/drivers/regulator/mcp16502.c +@@ -22,8 +22,9 @@ + #define VDD_LOW_SEL 0x0D + #define VDD_HIGH_SEL 0x3F + +-#define MCP16502_FLT BIT(7) +-#define MCP16502_ENS BIT(0) ++#define MCP16502_FLT BIT(7) ++#define MCP16502_DVSR GENMASK(3, 2) ++#define MCP16502_ENS BIT(0) + + /* + * The PMIC has four sets of registers corresponding to four power modes: +@@ -88,6 +89,12 @@ enum mcp16502_reg { + MCP16502_REG_CFG, + }; + ++/* Ramp delay (uV/us) for buck1, ldo1, ldo2. */ ++static const int mcp16502_ramp_b1l12[] = { 6250, 3125, 2083, 1563 }; ++ ++/* Ramp delay (uV/us) for buck2, buck3, buck4. */ ++static const int mcp16502_ramp_b234[] = { 3125, 1563, 1042, 781 }; ++ + static unsigned int mcp16502_of_map_mode(unsigned int mode) + { + if (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE) +@@ -271,6 +278,80 @@ static int mcp16502_get_status(struct re + return REGULATOR_STATUS_UNDEFINED; + } + ++static int mcp16502_set_voltage_time_sel(struct regulator_dev *rdev, ++ unsigned int old_sel, ++ unsigned int new_sel) ++{ ++ static const u8 us_ramp[] = { 8, 16, 24, 32 }; ++ int id = rdev_get_id(rdev); ++ unsigned int uV_delta, val; ++ int ret; ++ ++ ret = regmap_read(rdev->regmap, MCP16502_REG_BASE(id, CFG), &val); ++ if (ret) ++ return ret; ++ ++ val = (val & MCP16502_DVSR) >> 2; ++ uV_delta = abs(new_sel * rdev->desc->linear_ranges->step - ++ old_sel * rdev->desc->linear_ranges->step); ++ switch (id) { ++ case BUCK1: ++ case LDO1: ++ case LDO2: ++ ret = DIV_ROUND_CLOSEST(uV_delta * us_ramp[val], ++ mcp16502_ramp_b1l12[val]); ++ break; ++ ++ case BUCK2: ++ case BUCK3: ++ case BUCK4: ++ ret = DIV_ROUND_CLOSEST(uV_delta * us_ramp[val], ++ mcp16502_ramp_b234[val]); ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++static int mcp16502_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay) ++{ ++ const int *ramp; ++ int id = rdev_get_id(rdev); ++ unsigned int i, size; ++ ++ switch (id) { ++ case BUCK1: ++ case LDO1: ++ case LDO2: ++ ramp = mcp16502_ramp_b1l12; ++ size = ARRAY_SIZE(mcp16502_ramp_b1l12); ++ break; ++ ++ case BUCK2: ++ case BUCK3: ++ case BUCK4: ++ ramp = mcp16502_ramp_b234; ++ size = ARRAY_SIZE(mcp16502_ramp_b234); ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < size; i++) { ++ if (ramp[i] == ramp_delay) ++ break; ++ } ++ if (i == size) ++ return -EINVAL; ++ ++ return regmap_update_bits(rdev->regmap, MCP16502_REG_BASE(id, CFG), ++ MCP16502_DVSR, (i << 2)); ++} ++ + #ifdef CONFIG_SUSPEND + /* + * mcp16502_suspend_get_target_reg() - get the reg of the target suspend PMIC +@@ -365,6 +446,8 @@ static const struct regulator_ops mcp165 + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = mcp16502_get_status, ++ .set_voltage_time_sel = mcp16502_set_voltage_time_sel, ++ .set_ramp_delay = mcp16502_set_ramp_delay, + + .set_mode = mcp16502_set_mode, + .get_mode = mcp16502_get_mode, +@@ -389,6 +472,8 @@ static const struct regulator_ops mcp165 + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = mcp16502_get_status, ++ .set_voltage_time_sel = mcp16502_set_voltage_time_sel, ++ .set_ramp_delay = mcp16502_set_ramp_delay, + + #ifdef CONFIG_SUSPEND + .set_suspend_voltage = mcp16502_set_suspend_voltage, diff --git a/target/linux/at91/patches-5.15/126-regulator-mcp16502-remove-void-documentation-of-stru.patch b/target/linux/at91/patches-5.15/126-regulator-mcp16502-remove-void-documentation-of-stru.patch new file mode 100644 index 0000000000..f570e2805f --- /dev/null +++ b/target/linux/at91/patches-5.15/126-regulator-mcp16502-remove-void-documentation-of-stru.patch @@ -0,0 +1,27 @@ +From 8dcbcb052f682478dcbfa7fc9abdd909e1deab87 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Fri, 13 Nov 2020 17:21:10 +0200 +Subject: [PATCH 126/247] regulator: mcp16502: remove void documentation of + struct mcp16502 + +struct mcp16502 has no members called rdev or rmap. Remove the +documentation. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605280870-32432-7-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Mark Brown +--- + drivers/regulator/mcp16502.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/regulator/mcp16502.c ++++ b/drivers/regulator/mcp16502.c +@@ -135,8 +135,6 @@ enum { + + /* + * struct mcp16502 - PMIC representation +- * @rdev: the regulators belonging to this chip +- * @rmap: regmap to be used for I2C communication + * @lpm: LPM GPIO descriptor + */ + struct mcp16502 { diff --git a/target/linux/at91/patches-5.15/127-regulator-core-validate-selector-against-linear_min_.patch b/target/linux/at91/patches-5.15/127-regulator-core-validate-selector-against-linear_min_.patch new file mode 100644 index 0000000000..14eedb094c --- /dev/null +++ b/target/linux/at91/patches-5.15/127-regulator-core-validate-selector-against-linear_min_.patch @@ -0,0 +1,64 @@ +From 3aee4f22ed0a22d3d6d22fc49812c03d876c7637 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Fri, 13 Nov 2020 17:21:05 +0200 +Subject: [PATCH 127/247] regulator: core: validate selector against + linear_min_sel + +There are regulators who's min selector is not zero. Selectors loops +(looping b/w zero and regulator::desc::n_voltages) might throw errors +because invalid selectors are used (lower than +regulator::desc::linear_min_sel). For this situations validate selectors +against regulator::desc::linear_min_sel. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605280870-32432-2-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Mark Brown +--- + drivers/regulator/core.c | 9 +++++++-- + drivers/regulator/helpers.c | 3 ++- + 2 files changed, 9 insertions(+), 3 deletions(-) + +--- a/drivers/regulator/core.c ++++ b/drivers/regulator/core.c +@@ -2992,7 +2992,8 @@ static int _regulator_list_voltage(struc + return rdev->desc->fixed_uV; + + if (ops->list_voltage) { +- if (selector >= rdev->desc->n_voltages) ++ if (selector >= rdev->desc->n_voltages || ++ selector < rdev->desc->linear_min_sel) + return -EINVAL; + if (lock) + regulator_lock(rdev); +@@ -3143,7 +3144,8 @@ int regulator_list_hardware_vsel(struct + struct regulator_dev *rdev = regulator->rdev; + const struct regulator_ops *ops = rdev->desc->ops; + +- if (selector >= rdev->desc->n_voltages) ++ if (selector >= rdev->desc->n_voltages || ++ selector < rdev->desc->linear_min_sel) + return -EINVAL; + if (ops->set_voltage_sel != regulator_set_voltage_sel_regmap) + return -EOPNOTSUPP; +@@ -4066,6 +4068,9 @@ int regulator_set_voltage_time(struct re + + for (i = 0; i < rdev->desc->n_voltages; i++) { + /* We only look for exact voltage matches here */ ++ if (i < rdev->desc->linear_min_sel) ++ continue; ++ + voltage = regulator_list_voltage(regulator, i); + if (voltage < 0) + return -EINVAL; +--- a/drivers/regulator/helpers.c ++++ b/drivers/regulator/helpers.c +@@ -647,7 +647,8 @@ int regulator_list_voltage_table(struct + return -EINVAL; + } + +- if (selector >= rdev->desc->n_voltages) ++ if (selector >= rdev->desc->n_voltages || ++ selector < rdev->desc->linear_min_sel) + return -EINVAL; + + return rdev->desc->volt_table[selector]; diff --git a/target/linux/at91/patches-5.15/128-regulator-core-do-not-continue-if-selector-match.patch b/target/linux/at91/patches-5.15/128-regulator-core-do-not-continue-if-selector-match.patch new file mode 100644 index 0000000000..2eed3a0aee --- /dev/null +++ b/target/linux/at91/patches-5.15/128-regulator-core-do-not-continue-if-selector-match.patch @@ -0,0 +1,26 @@ +From 42b56e8bd343f34d5f2a601d8a8a05d8c861c08c Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Fri, 13 Nov 2020 19:56:04 +0200 +Subject: [PATCH 128/247] regulator: core: do not continue if selector match + +Do not continue if selector has already been located. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1605290164-11556-1-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Mark Brown +--- + drivers/regulator/core.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/regulator/core.c ++++ b/drivers/regulator/core.c +@@ -4071,6 +4071,9 @@ int regulator_set_voltage_time(struct re + if (i < rdev->desc->linear_min_sel) + continue; + ++ if (old_sel >= 0 && new_sel >= 0) ++ break; ++ + voltage = regulator_list_voltage(regulator, i); + if (voltage < 0) + return -EINVAL; diff --git a/target/linux/at91/patches-5.15/129-regulator-core-return-zero-for-selectors-lower-than-.patch b/target/linux/at91/patches-5.15/129-regulator-core-return-zero-for-selectors-lower-than-.patch new file mode 100644 index 0000000000..9af0e0f53c --- /dev/null +++ b/target/linux/at91/patches-5.15/129-regulator-core-return-zero-for-selectors-lower-than-.patch @@ -0,0 +1,64 @@ +From 0e933ffc049a0e181b5a6c3af1933976d6959ba9 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 25 Nov 2020 19:25:47 +0200 +Subject: [PATCH 129/247] regulator: core: return zero for selectors lower than + linear_min_sel + +Selectors lower than linear_min_sel should not be considered invalid. +Thus return zero in case _regulator_list_voltage(), +regulator_list_hardware_vsel() or regulator_list_voltage_table() +receives such selectors as argument. + +Fixes: bdcd1177578c ("regulator: core: validate selector against linear_min_sel") +Reported-by: Jon Hunter +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1606325147-606-1-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Mark Brown +--- + drivers/regulator/core.c | 10 ++++++---- + drivers/regulator/helpers.c | 5 +++-- + 2 files changed, 9 insertions(+), 6 deletions(-) + +--- a/drivers/regulator/core.c ++++ b/drivers/regulator/core.c +@@ -2992,9 +2992,10 @@ static int _regulator_list_voltage(struc + return rdev->desc->fixed_uV; + + if (ops->list_voltage) { +- if (selector >= rdev->desc->n_voltages || +- selector < rdev->desc->linear_min_sel) ++ if (selector >= rdev->desc->n_voltages) + return -EINVAL; ++ if (selector < rdev->desc->linear_min_sel) ++ return 0; + if (lock) + regulator_lock(rdev); + ret = ops->list_voltage(rdev, selector); +@@ -3144,9 +3145,10 @@ int regulator_list_hardware_vsel(struct + struct regulator_dev *rdev = regulator->rdev; + const struct regulator_ops *ops = rdev->desc->ops; + +- if (selector >= rdev->desc->n_voltages || +- selector < rdev->desc->linear_min_sel) ++ if (selector >= rdev->desc->n_voltages) + return -EINVAL; ++ if (selector < rdev->desc->linear_min_sel) ++ return 0; + if (ops->set_voltage_sel != regulator_set_voltage_sel_regmap) + return -EOPNOTSUPP; + +--- a/drivers/regulator/helpers.c ++++ b/drivers/regulator/helpers.c +@@ -647,9 +647,10 @@ int regulator_list_voltage_table(struct + return -EINVAL; + } + +- if (selector >= rdev->desc->n_voltages || +- selector < rdev->desc->linear_min_sel) ++ if (selector >= rdev->desc->n_voltages) + return -EINVAL; ++ if (selector < rdev->desc->linear_min_sel) ++ return 0; + + return rdev->desc->volt_table[selector]; + } diff --git a/target/linux/at91/patches-5.15/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch b/target/linux/at91/patches-5.15/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch new file mode 100644 index 0000000000..12679a20bd --- /dev/null +++ b/target/linux/at91/patches-5.15/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch @@ -0,0 +1,30 @@ +From 763fe72f607d4e929d2c710c88e5c6978dd6ad97 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 7 Jan 2021 16:15:26 +0200 +Subject: [PATCH 130/247] regulator: mcp16502: lpm pin can be optional on some + platforms + +On some platform (e.g. SAMA7G5) LPM pin should be optional as it can +be controlled explicitly (via shutdown controller registers) in the +platform specific power saving code to decrease the power consumption +while suspended as this SoC pin may be connected to other devices that +could take power saving actions based on its value. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/1610028927-9842-3-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Mark Brown +--- + drivers/regulator/mcp16502.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/regulator/mcp16502.c ++++ b/drivers/regulator/mcp16502.c +@@ -550,7 +550,7 @@ static int mcp16502_probe(struct i2c_cli + config.regmap = rmap; + config.driver_data = mcp; + +- mcp->lpm = devm_gpiod_get(dev, "lpm", GPIOD_OUT_LOW); ++ mcp->lpm = devm_gpiod_get_optional(dev, "lpm", GPIOD_OUT_LOW); + if (IS_ERR(mcp->lpm)) { + dev_err(dev, "failed to get lpm pin: %ld\n", PTR_ERR(mcp->lpm)); + return PTR_ERR(mcp->lpm); diff --git a/target/linux/at91/patches-5.15/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch b/target/linux/at91/patches-5.15/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch new file mode 100644 index 0000000000..78db5a0d32 --- /dev/null +++ b/target/linux/at91/patches-5.15/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch @@ -0,0 +1,70 @@ +From 7cb1dad7a7dfe4cfe55ebe86930dd6aef0de66b4 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Fri, 13 Nov 2020 15:24:29 +0200 +Subject: [PATCH 131/247] pinctrl: at91-pio4: add support for fewer lines on + last PIO bank + +Some products, like sama7g5, do not have a full last bank of PIO lines. +In this case for example, sama7g5 only has 8 lines for the PE bank. +PA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines. +To cope with this situation, added a data attribute that is product dependent, +to specify the number of lines of the last bank. +In case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK, +adjust the total number of lines accordingly. +This will avoid advertising 160 lines instead of the actual 136, as this +product supports, and to avoid reading/writing to invalid register addresses. + +Signed-off-by: Eugen Hristev +Acked-by: Ludovic Desroches +Link: https://lore.kernel.org/r/20201113132429.420940-1-eugen.hristev@microchip.com +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/pinctrl-at91-pio4.c | 18 ++++++++++++++++-- + 1 file changed, 16 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/pinctrl-at91-pio4.c ++++ b/drivers/pinctrl/pinctrl-at91-pio4.c +@@ -71,8 +71,15 @@ + /* Custom pinconf parameters */ + #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1) + ++/** ++ * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct ++ * @nbanks: number of PIO banks ++ * @last_bank_count: number of lines in the last bank (can be less than ++ * the rest of the banks). ++ */ + struct atmel_pioctrl_data { + unsigned nbanks; ++ unsigned last_bank_count; + }; + + struct atmel_group { +@@ -980,11 +987,13 @@ static const struct dev_pm_ops atmel_pct + * We can have up to 16 banks. + */ + static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { +- .nbanks = 4, ++ .nbanks = 4, ++ .last_bank_count = ATMEL_PIO_NPINS_PER_BANK, + }; + + static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = { +- .nbanks = 5, ++ .nbanks = 5, ++ .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */ + }; + + static const struct of_device_id atmel_pctrl_of_match[] = { +@@ -1025,6 +1034,11 @@ static int atmel_pinctrl_probe(struct pl + atmel_pioctrl_data = match->data; + atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; + atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; ++ /* if last bank has limited number of pins, adjust accordingly */ ++ if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) { ++ atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK; ++ atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count; ++ } + + atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(atmel_pioctrl->reg_base)) diff --git a/target/linux/at91/patches-5.15/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch b/target/linux/at91/patches-5.15/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch new file mode 100644 index 0000000000..ca1fa8cee5 --- /dev/null +++ b/target/linux/at91/patches-5.15/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch @@ -0,0 +1,50 @@ +From 1dccaa4c1e99cd8bd27684a2c87ec806d426c088 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Fri, 16 Oct 2020 12:37:25 +0300 +Subject: [PATCH 132/247] dmaengine: at_xdmac: adapt perid for mem2mem + operations + +The PERID in the CC register for mem2mem operations must match an unused +PERID. +The PERID field is 7 bits, but the selected value is 0x3f. +On later products we can have more reserved PERIDs for actual peripherals, +thus this needs to be increased to maximum size. +Changing the value to 0x7f, which is the maximum for 7 bits field. + +Signed-off-by: Eugen Hristev +Reviewed-by: Tudor Ambarus +Link: https://lore.kernel.org/r/20201016093725.289880-1-eugen.hristev@microchip.com +Signed-off-by: Vinod Koul +--- + drivers/dma/at_xdmac.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/dma/at_xdmac.c ++++ b/drivers/dma/at_xdmac.c +@@ -865,7 +865,7 @@ at_xdmac_interleaved_queue_desc(struct d + * match the one of another channel. If not, it could lead to spurious + * flag status. + */ +- u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) ++ u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) + | AT_XDMAC_CC_DIF(0) + | AT_XDMAC_CC_SIF(0) + | AT_XDMAC_CC_MBSIZE_SIXTEEN +@@ -1047,7 +1047,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan + * match the one of another channel. If not, it could lead to spurious + * flag status. + */ +- u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) ++ u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) + | AT_XDMAC_CC_DAM_INCREMENTED_AM + | AT_XDMAC_CC_SAM_INCREMENTED_AM + | AT_XDMAC_CC_DIF(0) +@@ -1153,7 +1153,7 @@ static struct at_xdmac_desc *at_xdmac_me + * match the one of another channel. If not, it could lead to spurious + * flag status. + */ +- u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) ++ u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) + | AT_XDMAC_CC_DAM_UBS_AM + | AT_XDMAC_CC_SAM_INCREMENTED_AM + | AT_XDMAC_CC_DIF(0) diff --git a/target/linux/at91/patches-5.15/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch b/target/linux/at91/patches-5.15/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch new file mode 100644 index 0000000000..6d338490fb --- /dev/null +++ b/target/linux/at91/patches-5.15/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch @@ -0,0 +1,280 @@ +From 613af756b93fe005d9db11ea26fd0318f239d5a2 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Fri, 16 Oct 2020 12:38:50 +0300 +Subject: [PATCH 133/247] dmaengine: at_xdmac: add support for sama7g5 based + at_xdmac + +SAMA7G5 SoC uses a slightly different variant of the AT_XDMAC. +Added support by a new compatible and a layout struct that copes +to the specific version considering the compatible string. +Only the differences in register map are present in the layout struct. +I reworked the register access for this part that has the differences. +Also the Source/Destination Interface bits are no longer valid for this +variant of the XDMAC. Thus, the layout also has a bool for specifying +whether these bits are required or not. + +Signed-off-by: Eugen Hristev +Link: https://lore.kernel.org/r/20201016093850.290053-1-eugen.hristev@microchip.com +Signed-off-by: Vinod Koul +--- + drivers/dma/at_xdmac.c | 110 +++++++++++++++++++++++++++++++---------- + 1 file changed, 84 insertions(+), 26 deletions(-) + +--- a/drivers/dma/at_xdmac.c ++++ b/drivers/dma/at_xdmac.c +@@ -38,13 +38,6 @@ + #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */ + #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */ + #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */ +-#define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */ +-#define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */ +-#define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */ +-#define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */ +-#define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */ +-#define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */ +-#define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */ + #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */ + + /* Channel relative registers offsets */ +@@ -151,8 +144,6 @@ + #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */ + #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */ + +-#define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */ +- + /* Microblock control members */ + #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */ + #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */ +@@ -180,6 +171,27 @@ enum atc_status { + AT_XDMAC_CHAN_IS_PAUSED, + }; + ++struct at_xdmac_layout { ++ /* Global Channel Read Suspend Register */ ++ u8 grs; ++ /* Global Write Suspend Register */ ++ u8 gws; ++ /* Global Channel Read Write Suspend Register */ ++ u8 grws; ++ /* Global Channel Read Write Resume Register */ ++ u8 grwr; ++ /* Global Channel Software Request Register */ ++ u8 gswr; ++ /* Global channel Software Request Status Register */ ++ u8 gsws; ++ /* Global Channel Software Flush Request Register */ ++ u8 gswf; ++ /* Channel reg base */ ++ u8 chan_cc_reg_base; ++ /* Source/Destination Interface must be specified or not */ ++ bool sdif; ++}; ++ + /* ----- Channels ----- */ + struct at_xdmac_chan { + struct dma_chan chan; +@@ -213,6 +225,7 @@ struct at_xdmac { + struct clk *clk; + u32 save_gim; + struct dma_pool *at_xdmac_desc_pool; ++ const struct at_xdmac_layout *layout; + struct at_xdmac_chan chan[]; + }; + +@@ -245,9 +258,33 @@ struct at_xdmac_desc { + struct list_head xfer_node; + } __aligned(sizeof(u64)); + ++static const struct at_xdmac_layout at_xdmac_sama5d4_layout = { ++ .grs = 0x28, ++ .gws = 0x2C, ++ .grws = 0x30, ++ .grwr = 0x34, ++ .gswr = 0x38, ++ .gsws = 0x3C, ++ .gswf = 0x40, ++ .chan_cc_reg_base = 0x50, ++ .sdif = true, ++}; ++ ++static const struct at_xdmac_layout at_xdmac_sama7g5_layout = { ++ .grs = 0x30, ++ .gws = 0x38, ++ .grws = 0x40, ++ .grwr = 0x44, ++ .gswr = 0x48, ++ .gsws = 0x4C, ++ .gswf = 0x50, ++ .chan_cc_reg_base = 0x60, ++ .sdif = false, ++}; ++ + static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb) + { +- return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40); ++ return atxdmac->regs + (atxdmac->layout->chan_cc_reg_base + chan_nb * 0x40); + } + + #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg)) +@@ -343,8 +380,10 @@ static void at_xdmac_start_xfer(struct a + first->active_xfer = true; + + /* Tell xdmac where to get the first descriptor. */ +- reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys) +- | AT_XDMAC_CNDA_NDAIF(atchan->memif); ++ reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys); ++ if (atxdmac->layout->sdif) ++ reg |= AT_XDMAC_CNDA_NDAIF(atchan->memif); ++ + at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg); + + /* +@@ -539,6 +578,7 @@ static int at_xdmac_compute_chan_conf(st + enum dma_transfer_direction direction) + { + struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); ++ struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); + int csize, dwidth; + + if (direction == DMA_DEV_TO_MEM) { +@@ -546,12 +586,14 @@ static int at_xdmac_compute_chan_conf(st + AT91_XDMAC_DT_PERID(atchan->perid) + | AT_XDMAC_CC_DAM_INCREMENTED_AM + | AT_XDMAC_CC_SAM_FIXED_AM +- | AT_XDMAC_CC_DIF(atchan->memif) +- | AT_XDMAC_CC_SIF(atchan->perif) + | AT_XDMAC_CC_SWREQ_HWR_CONNECTED + | AT_XDMAC_CC_DSYNC_PER2MEM + | AT_XDMAC_CC_MBSIZE_SIXTEEN + | AT_XDMAC_CC_TYPE_PER_TRAN; ++ if (atxdmac->layout->sdif) ++ atchan->cfg |= AT_XDMAC_CC_DIF(atchan->memif) | ++ AT_XDMAC_CC_SIF(atchan->perif); ++ + csize = ffs(atchan->sconfig.src_maxburst) - 1; + if (csize < 0) { + dev_err(chan2dev(chan), "invalid src maxburst value\n"); +@@ -569,12 +611,14 @@ static int at_xdmac_compute_chan_conf(st + AT91_XDMAC_DT_PERID(atchan->perid) + | AT_XDMAC_CC_DAM_FIXED_AM + | AT_XDMAC_CC_SAM_INCREMENTED_AM +- | AT_XDMAC_CC_DIF(atchan->perif) +- | AT_XDMAC_CC_SIF(atchan->memif) + | AT_XDMAC_CC_SWREQ_HWR_CONNECTED + | AT_XDMAC_CC_DSYNC_MEM2PER + | AT_XDMAC_CC_MBSIZE_SIXTEEN + | AT_XDMAC_CC_TYPE_PER_TRAN; ++ if (atxdmac->layout->sdif) ++ atchan->cfg |= AT_XDMAC_CC_DIF(atchan->perif) | ++ AT_XDMAC_CC_SIF(atchan->memif); ++ + csize = ffs(atchan->sconfig.dst_maxburst) - 1; + if (csize < 0) { + dev_err(chan2dev(chan), "invalid src maxburst value\n"); +@@ -864,10 +908,12 @@ at_xdmac_interleaved_queue_desc(struct d + * ERRATA: Even if useless for memory transfers, the PERID has to not + * match the one of another channel. If not, it could lead to spurious + * flag status. ++ * For SAMA7G5x case, the SIF and DIF fields are no longer used. ++ * Thus, no need to have the SIF/DIF interfaces here. ++ * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as ++ * zero. + */ + u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) +- | AT_XDMAC_CC_DIF(0) +- | AT_XDMAC_CC_SIF(0) + | AT_XDMAC_CC_MBSIZE_SIXTEEN + | AT_XDMAC_CC_TYPE_MEM_TRAN; + +@@ -1046,12 +1092,14 @@ at_xdmac_prep_dma_memcpy(struct dma_chan + * ERRATA: Even if useless for memory transfers, the PERID has to not + * match the one of another channel. If not, it could lead to spurious + * flag status. ++ * For SAMA7G5x case, the SIF and DIF fields are no longer used. ++ * Thus, no need to have the SIF/DIF interfaces here. ++ * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as ++ * zero. + */ + u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) + | AT_XDMAC_CC_DAM_INCREMENTED_AM + | AT_XDMAC_CC_SAM_INCREMENTED_AM +- | AT_XDMAC_CC_DIF(0) +- | AT_XDMAC_CC_SIF(0) + | AT_XDMAC_CC_MBSIZE_SIXTEEN + | AT_XDMAC_CC_TYPE_MEM_TRAN; + unsigned long irqflags; +@@ -1152,12 +1200,14 @@ static struct at_xdmac_desc *at_xdmac_me + * ERRATA: Even if useless for memory transfers, the PERID has to not + * match the one of another channel. If not, it could lead to spurious + * flag status. ++ * For SAMA7G5x case, the SIF and DIF fields are no longer used. ++ * Thus, no need to have the SIF/DIF interfaces here. ++ * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as ++ * zero. + */ + u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) + | AT_XDMAC_CC_DAM_UBS_AM + | AT_XDMAC_CC_SAM_INCREMENTED_AM +- | AT_XDMAC_CC_DIF(0) +- | AT_XDMAC_CC_SIF(0) + | AT_XDMAC_CC_MBSIZE_SIXTEEN + | AT_XDMAC_CC_MEMSET_HW_MODE + | AT_XDMAC_CC_TYPE_MEM_TRAN; +@@ -1436,7 +1486,7 @@ at_xdmac_tx_status(struct dma_chan *chan + mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC; + value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM; + if ((desc->lld.mbr_cfg & mask) == value) { +- at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); ++ at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask); + while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) + cpu_relax(); + } +@@ -1494,7 +1544,7 @@ at_xdmac_tx_status(struct dma_chan *chan + * FIFO flush ensures that data are really written. + */ + if ((desc->lld.mbr_cfg & mask) == value) { +- at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); ++ at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask); + while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) + cpu_relax(); + } +@@ -1762,7 +1812,7 @@ static int at_xdmac_device_pause(struct + return 0; + + spin_lock_irqsave(&atchan->lock, flags); +- at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask); ++ at_xdmac_write(atxdmac, atxdmac->layout->grws, atchan->mask); + while (at_xdmac_chan_read(atchan, AT_XDMAC_CC) + & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP)) + cpu_relax(); +@@ -1785,7 +1835,7 @@ static int at_xdmac_device_resume(struct + return 0; + } + +- at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask); ++ at_xdmac_write(atxdmac, atxdmac->layout->grwr, atchan->mask); + clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); + spin_unlock_irqrestore(&atchan->lock, flags); + +@@ -1992,6 +2042,10 @@ static int at_xdmac_probe(struct platfor + atxdmac->regs = base; + atxdmac->irq = irq; + ++ atxdmac->layout = of_device_get_match_data(&pdev->dev); ++ if (!atxdmac->layout) ++ return -ENODEV; ++ + atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk"); + if (IS_ERR(atxdmac->clk)) { + dev_err(&pdev->dev, "can't get dma_clk\n"); +@@ -2134,6 +2188,10 @@ static const struct dev_pm_ops atmel_xdm + static const struct of_device_id atmel_xdmac_dt_ids[] = { + { + .compatible = "atmel,sama5d4-dma", ++ .data = &at_xdmac_sama5d4_layout, ++ }, { ++ .compatible = "microchip,sama7g5-dma", ++ .data = &at_xdmac_sama7g5_layout, + }, { + /* sentinel */ + } diff --git a/target/linux/at91/patches-5.15/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch b/target/linux/at91/patches-5.15/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch new file mode 100644 index 0000000000..463d03a35e --- /dev/null +++ b/target/linux/at91/patches-5.15/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch @@ -0,0 +1,113 @@ +From 4833d6ea13a6d2c44a91247991a82c3eb6c1613e Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Fri, 16 Oct 2020 12:39:18 +0300 +Subject: [PATCH 134/247] dmaengine: at_xdmac: add AXI priority support and + recommended settings + +The sama7g5 version of the XDMAC supports priority configuration and +outstanding capabilities. +Add defines for the specific registers for this configuration, together +with recommended settings. +However the settings are very different if the XDMAC is a mem2mem or a +per2mem controller. +Thus, we need to differentiate according to device tree property. + +Signed-off-by: Eugen Hristev +Link: https://lore.kernel.org/r/20201016093918.290137-1-eugen.hristev@microchip.com +Signed-off-by: Vinod Koul +--- + drivers/dma/at_xdmac.c | 47 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 47 insertions(+) + +--- a/drivers/dma/at_xdmac.c ++++ b/drivers/dma/at_xdmac.c +@@ -30,7 +30,24 @@ + #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */ + #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */ + #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */ ++#define AT_XDMAC_WRHP(i) (((i) & 0xF) << 4) ++#define AT_XDMAC_WRMP(i) (((i) & 0xF) << 8) ++#define AT_XDMAC_WRLP(i) (((i) & 0xF) << 12) ++#define AT_XDMAC_RDHP(i) (((i) & 0xF) << 16) ++#define AT_XDMAC_RDMP(i) (((i) & 0xF) << 20) ++#define AT_XDMAC_RDLP(i) (((i) & 0xF) << 24) ++#define AT_XDMAC_RDSG(i) (((i) & 0xF) << 28) ++#define AT_XDMAC_GCFG_M2M (AT_XDMAC_RDLP(0xF) | AT_XDMAC_WRLP(0xF)) ++#define AT_XDMAC_GCFG_P2M (AT_XDMAC_RDSG(0x1) | AT_XDMAC_RDHP(0x3) | \ ++ AT_XDMAC_WRHP(0x5)) + #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */ ++#define AT_XDMAC_PW0(i) (((i) & 0xF) << 0) ++#define AT_XDMAC_PW1(i) (((i) & 0xF) << 4) ++#define AT_XDMAC_PW2(i) (((i) & 0xF) << 8) ++#define AT_XDMAC_PW3(i) (((i) & 0xF) << 12) ++#define AT_XDMAC_GWAC_M2M 0 ++#define AT_XDMAC_GWAC_P2M (AT_XDMAC_PW0(0xF) | AT_XDMAC_PW2(0xF)) ++ + #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */ + #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */ + #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */ +@@ -190,6 +207,8 @@ struct at_xdmac_layout { + u8 chan_cc_reg_base; + /* Source/Destination Interface must be specified or not */ + bool sdif; ++ /* AXI queue priority configuration supported */ ++ bool axi_config; + }; + + /* ----- Channels ----- */ +@@ -268,6 +287,7 @@ static const struct at_xdmac_layout at_x + .gswf = 0x40, + .chan_cc_reg_base = 0x50, + .sdif = true, ++ .axi_config = false, + }; + + static const struct at_xdmac_layout at_xdmac_sama7g5_layout = { +@@ -280,6 +300,7 @@ static const struct at_xdmac_layout at_x + .gswf = 0x50, + .chan_cc_reg_base = 0x60, + .sdif = false, ++ .axi_config = true, + }; + + static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb) +@@ -2003,6 +2024,30 @@ static int atmel_xdmac_resume(struct dev + } + #endif /* CONFIG_PM_SLEEP */ + ++static void at_xdmac_axi_config(struct platform_device *pdev) ++{ ++ struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev); ++ bool dev_m2m = false; ++ u32 dma_requests; ++ ++ if (!atxdmac->layout->axi_config) ++ return; /* Not supported */ ++ ++ if (!of_property_read_u32(pdev->dev.of_node, "dma-requests", ++ &dma_requests)) { ++ dev_info(&pdev->dev, "controller in mem2mem mode.\n"); ++ dev_m2m = true; ++ } ++ ++ if (dev_m2m) { ++ at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M); ++ at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M); ++ } else { ++ at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M); ++ at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M); ++ } ++} ++ + static int at_xdmac_probe(struct platform_device *pdev) + { + struct at_xdmac *atxdmac; +@@ -2147,6 +2192,8 @@ static int at_xdmac_probe(struct platfor + dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n", + nr_channels, atxdmac->regs); + ++ at_xdmac_axi_config(pdev); ++ + return 0; + + err_dma_unregister: diff --git a/target/linux/at91/patches-5.15/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch b/target/linux/at91/patches-5.15/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch new file mode 100644 index 0000000000..210d1bd2de --- /dev/null +++ b/target/linux/at91/patches-5.15/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch @@ -0,0 +1,45 @@ +From 982347f757b85ef526afaf243867ddd515475e1b Mon Sep 17 00:00:00 2001 +From: Charles Keepax +Date: Mon, 4 Jan 2021 10:38:02 +0000 +Subject: [PATCH 135/247] net: macb: Correct usage of MACB_CAPS_CLK_HW_CHG flag + +A new flag MACB_CAPS_CLK_HW_CHG was added and all callers of +macb_set_tx_clk were gated on the presence of this flag. + +- if (!clk) ++ if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG)) + +However the flag was not added to anything other than the new +sama7g5_gem, turning that function call into a no op for all other +systems. This breaks the networking on Zynq. + +The commit message adding this states: a new capability so that +macb_set_tx_clock() to not be called for IPs having this +capability + +This strongly implies that present of the flag was intended to skip +the function not absence of the flag. Update the if statement to +this effect, which repairs the existing users. + +Fixes: daafa1d33cc9 ("net: macb: add capability to not set the clock rate") +Suggested-by: Andrew Lunn +Signed-off-by: Charles Keepax +Reviewed-by: Claudiu Beznea +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20210104103802.13091-1-ckeepax@opensource.cirrus.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/cadence/macb_main.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/cadence/macb_main.c ++++ b/drivers/net/ethernet/cadence/macb_main.c +@@ -464,7 +464,7 @@ static void macb_set_tx_clk(struct macb + { + long ferr, rate, rate_rounded; + +- if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG)) ++ if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG)) + return; + + switch (speed) { diff --git a/target/linux/at91/patches-5.15/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch b/target/linux/at91/patches-5.15/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch new file mode 100644 index 0000000000..7c36d0f93a --- /dev/null +++ b/target/linux/at91/patches-5.15/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch @@ -0,0 +1,43 @@ +From a2eda4ef1e3d617cdd669e256e45e969fab62398 Mon Sep 17 00:00:00 2001 +From: Kai Stuhlemmer +Date: Thu, 8 Oct 2020 14:50:28 +0200 +Subject: [PATCH 136/247] ARM: at91: sam9x60 SiP types added to soc description + +Adding SAM9X60 SIP variants to the soc description list. + +Signed-off-by: Kai Stuhlemmer +Signed-off-by: Nicolas Ferre +Signed-off-by: Alexandre Belloni +Link: https://lore.kernel.org/r/20201008125028.21071-1-nicolas.ferre@microchip.com +--- + drivers/soc/atmel/soc.c | 6 ++++++ + drivers/soc/atmel/soc.h | 3 +++ + 2 files changed, 9 insertions(+) + +--- a/drivers/soc/atmel/soc.c ++++ b/drivers/soc/atmel/soc.c +@@ -69,6 +69,12 @@ static const struct at91_soc __initconst + #endif + #ifdef CONFIG_SOC_SAM9X60 + AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"), ++ AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH, ++ "sam9x60 64MiB DDR2 SiP", "sam9x60"), ++ AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH, ++ "sam9x60 128MiB DDR2 SiP", "sam9x60"), ++ AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH, ++ "sam9x60 8MiB SDRAM SiP", "sam9x60"), + #endif + #ifdef CONFIG_SOC_SAMA5 + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH, +--- a/drivers/soc/atmel/soc.h ++++ b/drivers/soc/atmel/soc.h +@@ -60,6 +60,9 @@ at91_soc_init(const struct at91_soc *soc + #define AT91SAM9CN11_EXID_MATCH 0x00000009 + + #define SAM9X60_EXID_MATCH 0x00000000 ++#define SAM9X60_D5M_EXID_MATCH 0x00000001 ++#define SAM9X60_D1G_EXID_MATCH 0x00000010 ++#define SAM9X60_D6K_EXID_MATCH 0x00000011 + + #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 + #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 diff --git a/target/linux/at91/patches-5.15/137-drivers-soc-atmel-use-GENMASK.patch b/target/linux/at91/patches-5.15/137-drivers-soc-atmel-use-GENMASK.patch new file mode 100644 index 0000000000..de99d562f4 --- /dev/null +++ b/target/linux/at91/patches-5.15/137-drivers-soc-atmel-use-GENMASK.patch @@ -0,0 +1,25 @@ +From 8d858d9c57a0210ca1ce9e5ba76fab8bdb4d7b39 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Fri, 22 Jan 2021 14:21:32 +0200 +Subject: [PATCH 137/247] drivers: soc: atmel: use GENMASK + +Use GENMASK() to define CIDR match mask. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/1611318097-8970-3-git-send-email-claudiu.beznea@microchip.com +--- + drivers/soc/atmel/soc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/soc/atmel/soc.c ++++ b/drivers/soc/atmel/soc.c +@@ -27,7 +27,7 @@ + #define AT91_CHIPID_EXID 0x04 + #define AT91_CIDR_VERSION(x) ((x) & 0x1f) + #define AT91_CIDR_EXT BIT(31) +-#define AT91_CIDR_MATCH_MASK 0x7fffffe0 ++#define AT91_CIDR_MATCH_MASK GENMASK(30, 5) + + static const struct at91_soc __initconst socs[] = { + #ifdef CONFIG_SOC_AT91RM9200 diff --git a/target/linux/at91/patches-5.15/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch b/target/linux/at91/patches-5.15/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch new file mode 100644 index 0000000000..885528a28e --- /dev/null +++ b/target/linux/at91/patches-5.15/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch @@ -0,0 +1,26 @@ +From ed871f95827e9b6d4ee9f9eafec4e18b87fb1a56 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Fri, 22 Jan 2021 14:21:33 +0200 +Subject: [PATCH 138/247] drivers: soc: atmel: fix "__initconst should be + placed after socs[]" warning + +Fix checkpatch.pl warning: "__initconst should be placed after socs[]". + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/1611318097-8970-4-git-send-email-claudiu.beznea@microchip.com +--- + drivers/soc/atmel/soc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/soc/atmel/soc.c ++++ b/drivers/soc/atmel/soc.c +@@ -29,7 +29,7 @@ + #define AT91_CIDR_EXT BIT(31) + #define AT91_CIDR_MATCH_MASK GENMASK(30, 5) + +-static const struct at91_soc __initconst socs[] = { ++static const struct at91_soc socs[] __initconst = { + #ifdef CONFIG_SOC_AT91RM9200 + AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"), + #endif diff --git a/target/linux/at91/patches-5.15/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch b/target/linux/at91/patches-5.15/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch new file mode 100644 index 0000000000..72cdb46f11 --- /dev/null +++ b/target/linux/at91/patches-5.15/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch @@ -0,0 +1,348 @@ +From 8f6f7ef363268f417f1729bb0b234326dd1e8e2a Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Fri, 22 Jan 2021 14:21:35 +0200 +Subject: [PATCH 139/247] drivers: soc: atmel: add per soc id and version match + masks + +SAMA7G5 has different masks for chip ID and chip version on CIDR +register compared to previous AT91 SoCs. For this the commit adapts +the code for SAMA7G5 addition by introducing 2 new members in +struct at91_soc and fill them properly and also preparing the +parsing of proper DT binding. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/1611318097-8970-6-git-send-email-claudiu.beznea@microchip.com +--- + drivers/soc/atmel/soc.c | 199 +++++++++++++++++++++++++++------------- + drivers/soc/atmel/soc.h | 7 +- + 2 files changed, 140 insertions(+), 66 deletions(-) + +--- a/drivers/soc/atmel/soc.c ++++ b/drivers/soc/atmel/soc.c +@@ -25,135 +25,200 @@ + #define AT91_DBGU_EXID 0x44 + #define AT91_CHIPID_CIDR 0x00 + #define AT91_CHIPID_EXID 0x04 +-#define AT91_CIDR_VERSION(x) ((x) & 0x1f) ++#define AT91_CIDR_VERSION(x, m) ((x) & (m)) ++#define AT91_CIDR_VERSION_MASK GENMASK(4, 0) + #define AT91_CIDR_EXT BIT(31) + #define AT91_CIDR_MATCH_MASK GENMASK(30, 5) + + static const struct at91_soc socs[] __initconst = { + #ifdef CONFIG_SOC_AT91RM9200 +- AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"), ++ AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"), + #endif + #ifdef CONFIG_SOC_AT91SAM9 +- AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL), +- AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL), +- AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL), +- AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL), +- AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL), +- AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH, ++ AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL), ++ AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL), ++ AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL), ++ AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL), ++ AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL), ++ AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH, + "at91sam9m11", "at91sam9g45"), +- AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH, ++ AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH, + "at91sam9m10", "at91sam9g45"), +- AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH, ++ AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH, + "at91sam9g46", "at91sam9g45"), +- AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH, ++ AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH, + "at91sam9g45", "at91sam9g45"), +- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH, ++ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH, + "at91sam9g15", "at91sam9x5"), +- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH, ++ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH, + "at91sam9g35", "at91sam9x5"), +- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH, ++ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH, + "at91sam9x35", "at91sam9x5"), +- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH, ++ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH, + "at91sam9g25", "at91sam9x5"), +- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH, ++ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH, + "at91sam9x25", "at91sam9x5"), +- AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH, ++ AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH, + "at91sam9cn12", "at91sam9n12"), +- AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH, ++ AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH, + "at91sam9n12", "at91sam9n12"), +- AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH, ++ AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH, + "at91sam9cn11", "at91sam9n12"), +- AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"), +- AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"), +- AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"), ++ AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"), ++ AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"), ++ AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"), + #endif + #ifdef CONFIG_SOC_SAM9X60 +- AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"), ++ AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, ++ "sam9x60", "sam9x60"), + AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH, ++ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, + "sam9x60 64MiB DDR2 SiP", "sam9x60"), + AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH, ++ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, + "sam9x60 128MiB DDR2 SiP", "sam9x60"), + AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH, ++ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, + "sam9x60 8MiB SDRAM SiP", "sam9x60"), + #endif + #ifdef CONFIG_SOC_SAMA5 +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH, + "sama5d21", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH, + "sama5d22", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D225C_D1M_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH, + "sama5d225c 16MiB SiP", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH, + "sama5d23", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH, + "sama5d24", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH, + "sama5d24", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH, + "sama5d26", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH, + "sama5d27", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH, + "sama5d27", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D1G_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH, + "sama5d27c 128MiB SiP", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D5M_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH, + "sama5d27c 64MiB SiP", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD1G_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH, + "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD2G_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH, + "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH, + "sama5d28", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH, + "sama5d28", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_D1G_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH, + "sama5d28c 128MiB SiP", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD1G_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH, + "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"), +- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD2G_EXID_MATCH, ++ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH, + "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"), +- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH, ++ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH, + "sama5d31", "sama5d3"), +- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH, ++ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH, + "sama5d33", "sama5d3"), +- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH, ++ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH, + "sama5d34", "sama5d3"), +- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH, ++ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH, + "sama5d35", "sama5d3"), +- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH, ++ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH, + "sama5d36", "sama5d3"), +- AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH, ++ AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH, + "sama5d41", "sama5d4"), +- AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH, ++ AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH, + "sama5d42", "sama5d4"), +- AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH, ++ AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH, + "sama5d43", "sama5d4"), +- AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH, ++ AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH, + "sama5d44", "sama5d4"), + #endif + #ifdef CONFIG_SOC_SAMV7 +- AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH, ++ AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH, + "same70q21", "same7"), +- AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH, ++ AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH, + "same70q20", "same7"), +- AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH, ++ AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK ++ AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH, + "same70q19", "same7"), +- AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH, ++ AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH, + "sams70q21", "sams7"), +- AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH, ++ AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH, + "sams70q20", "sams7"), +- AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH, ++ AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH, + "sams70q19", "sams7"), +- AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH, ++ AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH, + "samv71q21", "samv7"), +- AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH, ++ AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH, + "samv71q20", "samv7"), +- AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH, ++ AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH, + "samv71q19", "samv7"), +- AT91_SOC(SAMV70Q20_CIDR_MATCH, SAMV70Q20_EXID_MATCH, ++ AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH, + "samv70q20", "samv7"), +- AT91_SOC(SAMV70Q19_CIDR_MATCH, SAMV70Q19_EXID_MATCH, ++ AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH, + "samv70q19", "samv7"), + #endif + { /* sentinel */ }, +@@ -191,8 +256,12 @@ static int __init at91_get_cidr_exid_fro + { + struct device_node *np; + void __iomem *regs; ++ static const struct of_device_id chipids[] = { ++ { .compatible = "atmel,sama5d2-chipid" }, ++ { }, ++ }; + +- np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid"); ++ np = of_find_matching_node(NULL, chipids); + if (!np) + return -ENODEV; + +@@ -235,7 +304,7 @@ struct soc_device * __init at91_soc_init + } + + for (soc = socs; soc->name; soc++) { +- if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK)) ++ if (soc->cidr_match != (cidr & soc->cidr_mask)) + continue; + + if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid) +@@ -254,7 +323,7 @@ struct soc_device * __init at91_soc_init + soc_dev_attr->family = soc->family; + soc_dev_attr->soc_id = soc->name; + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X", +- AT91_CIDR_VERSION(cidr)); ++ AT91_CIDR_VERSION(cidr, soc->version_mask)); + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr->revision); +@@ -266,7 +335,7 @@ struct soc_device * __init at91_soc_init + if (soc->family) + pr_info("Detected SoC family: %s\n", soc->family); + pr_info("Detected SoC: %s, revision %X\n", soc->name, +- AT91_CIDR_VERSION(cidr)); ++ AT91_CIDR_VERSION(cidr, soc->version_mask)); + + return soc_dev; + } +--- a/drivers/soc/atmel/soc.h ++++ b/drivers/soc/atmel/soc.h +@@ -16,14 +16,19 @@ + + struct at91_soc { + u32 cidr_match; ++ u32 cidr_mask; ++ u32 version_mask; + u32 exid_match; + const char *name; + const char *family; + }; + +-#define AT91_SOC(__cidr, __exid, __name, __family) \ ++#define AT91_SOC(__cidr, __cidr_mask, __version_mask, __exid, \ ++ __name, __family) \ + { \ + .cidr_match = (__cidr), \ ++ .cidr_mask = (__cidr_mask), \ ++ .version_mask = (__version_mask), \ + .exid_match = (__exid), \ + .name = (__name), \ + .family = (__family), \ diff --git a/target/linux/at91/patches-5.15/140-drivers-soc-atmel-add-support-for-sama7g5.patch b/target/linux/at91/patches-5.15/140-drivers-soc-atmel-add-support-for-sama7g5.patch new file mode 100644 index 0000000000..3b21017673 --- /dev/null +++ b/target/linux/at91/patches-5.15/140-drivers-soc-atmel-add-support-for-sama7g5.patch @@ -0,0 +1,87 @@ +From e20bb57fc51741677a6fcae04e564797fd18921b Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Fri, 22 Jan 2021 14:21:37 +0200 +Subject: [PATCH 140/247] drivers: soc: atmel: add support for sama7g5 + +Add support for SAMA7G5 SoCs. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/1611318097-8970-8-git-send-email-claudiu.beznea@microchip.com +--- + drivers/soc/atmel/soc.c | 18 ++++++++++++++++++ + drivers/soc/atmel/soc.h | 6 ++++++ + 2 files changed, 24 insertions(+) + +--- a/drivers/soc/atmel/soc.c ++++ b/drivers/soc/atmel/soc.c +@@ -27,8 +27,10 @@ + #define AT91_CHIPID_EXID 0x04 + #define AT91_CIDR_VERSION(x, m) ((x) & (m)) + #define AT91_CIDR_VERSION_MASK GENMASK(4, 0) ++#define AT91_CIDR_VERSION_MASK_SAMA7G5 GENMASK(3, 0) + #define AT91_CIDR_EXT BIT(31) + #define AT91_CIDR_MATCH_MASK GENMASK(30, 5) ++#define AT91_CIDR_MASK_SAMA7G5 GENMASK(27, 5) + + static const struct at91_soc socs[] __initconst = { + #ifdef CONFIG_SOC_AT91RM9200 +@@ -221,6 +223,20 @@ static const struct at91_soc socs[] __in + AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH, + "samv70q19", "samv7"), + #endif ++#ifdef CONFIG_SOC_SAMA7 ++ AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH, ++ "sama7g51", "sama7g5"), ++ AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH, ++ "sama7g52", "sama7g5"), ++ AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH, ++ "sama7g53", "sama7g5"), ++ AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH, ++ "sama7g54", "sama7g5"), ++#endif + { /* sentinel */ }, + }; + +@@ -258,6 +274,7 @@ static int __init at91_get_cidr_exid_fro + void __iomem *regs; + static const struct of_device_id chipids[] = { + { .compatible = "atmel,sama5d2-chipid" }, ++ { .compatible = "microchip,sama7g5-chipid" }, + { }, + }; + +@@ -345,6 +362,7 @@ static const struct of_device_id at91_so + { .compatible = "atmel,at91sam9", }, + { .compatible = "atmel,sama5", }, + { .compatible = "atmel,samv7", }, ++ { .compatible = "microchip,sama7g5", }, + { } + }; + +--- a/drivers/soc/atmel/soc.h ++++ b/drivers/soc/atmel/soc.h +@@ -48,6 +48,7 @@ at91_soc_init(const struct at91_soc *soc + #define AT91SAM9X5_CIDR_MATCH 0x019a05a0 + #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 + #define SAM9X60_CIDR_MATCH 0x019b35a0 ++#define SAMA7G5_CIDR_MATCH 0x00162100 + + #define AT91SAM9M11_EXID_MATCH 0x00000001 + #define AT91SAM9M10_EXID_MATCH 0x00000002 +@@ -69,6 +70,11 @@ at91_soc_init(const struct at91_soc *soc + #define SAM9X60_D1G_EXID_MATCH 0x00000010 + #define SAM9X60_D6K_EXID_MATCH 0x00000011 + ++#define SAMA7G51_EXID_MATCH 0x3 ++#define SAMA7G52_EXID_MATCH 0x2 ++#define SAMA7G53_EXID_MATCH 0x1 ++#define SAMA7G54_EXID_MATCH 0x0 ++ + #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 + #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 + #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 diff --git a/target/linux/at91/patches-5.15/141-drivers-soc-atmel-add-spdx-license-identifier.patch b/target/linux/at91/patches-5.15/141-drivers-soc-atmel-add-spdx-license-identifier.patch new file mode 100644 index 0000000000..be238147d6 --- /dev/null +++ b/target/linux/at91/patches-5.15/141-drivers-soc-atmel-add-spdx-license-identifier.patch @@ -0,0 +1,49 @@ +From acd4816cfa7811b13ca2864645f2de41031ccf4d Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Tue, 26 Jan 2021 11:29:30 +0200 +Subject: [PATCH 141/247] drivers: soc: atmel: add spdx license identifier + +Add SPDX-License-Identifier. + +Signed-off-by: Claudiu Beznea +[nicolas.ferre@microhcip.com: remove license boilerplate now it's useless] +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/1611653376-24168-2-git-send-email-claudiu.beznea@microchip.com +--- + drivers/soc/atmel/soc.c | 6 +----- + drivers/soc/atmel/soc.h | 6 +----- + 2 files changed, 2 insertions(+), 10 deletions(-) + +--- a/drivers/soc/atmel/soc.c ++++ b/drivers/soc/atmel/soc.c +@@ -1,13 +1,9 @@ ++// SPDX-License-Identifier: GPL-2.0-only + /* + * Copyright (C) 2015 Atmel + * + * Alexandre Belloni +Date: Thu, 4 Feb 2021 16:49:25 +0100 +Subject: [PATCH 142/247] drivers: soc: atmel: fix type for same7 + +A missing comma caused a build failure: + +drivers/soc/atmel/soc.c:196:24: error: too few arguments provided to function-like macro invocation + +Fixes: af3a10513cd6 ("drivers: soc: atmel: add per soc id and version match masks") +Signed-off-by: Arnd Bergmann +Acked-by: Alexandre Belloni +Signed-off-by: Arnd Bergmann +--- + drivers/soc/atmel/soc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/soc/atmel/soc.c ++++ b/drivers/soc/atmel/soc.c +@@ -191,7 +191,7 @@ static const struct at91_soc socs[] __in + AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH, + "same70q20", "same7"), +- AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK ++ AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH, + "same70q19", "same7"), + AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, diff --git a/target/linux/at91/patches-5.15/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch b/target/linux/at91/patches-5.15/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch new file mode 100644 index 0000000000..7b2462cd00 --- /dev/null +++ b/target/linux/at91/patches-5.15/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch @@ -0,0 +1,173 @@ +From 5f090a664d62ceeaf9a0f482426e35cab18d65a9 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Tue, 19 Jan 2021 14:59:25 +0200 +Subject: [PATCH 143/247] clocksource/drivers/timer-microchip-pit64b: Add + clocksource suspend/resume + +Add suspend/resume support for clocksource timer. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/1611061165-30180-1-git-send-email-claudiu.beznea@microchip.com +--- + drivers/clocksource/timer-microchip-pit64b.c | 86 ++++++++++++++++---- + 1 file changed, 71 insertions(+), 15 deletions(-) + +--- a/drivers/clocksource/timer-microchip-pit64b.c ++++ b/drivers/clocksource/timer-microchip-pit64b.c +@@ -71,10 +71,24 @@ struct mchp_pit64b_clkevt { + struct clock_event_device clkevt; + }; + +-#define to_mchp_pit64b_timer(x) \ ++#define clkevt_to_mchp_pit64b_timer(x) \ + ((struct mchp_pit64b_timer *)container_of(x,\ + struct mchp_pit64b_clkevt, clkevt)) + ++/** ++ * mchp_pit64b_clksrc - PIT64B clocksource data structure ++ * @timer: PIT64B timer ++ * @clksrc: clocksource ++ */ ++struct mchp_pit64b_clksrc { ++ struct mchp_pit64b_timer timer; ++ struct clocksource clksrc; ++}; ++ ++#define clksrc_to_mchp_pit64b_timer(x) \ ++ ((struct mchp_pit64b_timer *)container_of(x,\ ++ struct mchp_pit64b_clksrc, clksrc)) ++ + /* Base address for clocksource timer. */ + static void __iomem *mchp_pit64b_cs_base; + /* Default cycles for clockevent timer. */ +@@ -116,6 +130,36 @@ static inline void mchp_pit64b_reset(str + writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR); + } + ++static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer) ++{ ++ writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); ++ if (timer->mode & MCHP_PIT64B_MR_SGCLK) ++ clk_disable_unprepare(timer->gclk); ++ clk_disable_unprepare(timer->pclk); ++} ++ ++static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer) ++{ ++ clk_prepare_enable(timer->pclk); ++ if (timer->mode & MCHP_PIT64B_MR_SGCLK) ++ clk_prepare_enable(timer->gclk); ++} ++ ++static void mchp_pit64b_clksrc_suspend(struct clocksource *cs) ++{ ++ struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs); ++ ++ mchp_pit64b_suspend(timer); ++} ++ ++static void mchp_pit64b_clksrc_resume(struct clocksource *cs) ++{ ++ struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs); ++ ++ mchp_pit64b_resume(timer); ++ mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); ++} ++ + static u64 mchp_pit64b_clksrc_read(struct clocksource *cs) + { + return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); +@@ -128,7 +172,7 @@ static u64 notrace mchp_pit64b_sched_rea + + static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev) + { +- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); ++ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); + + writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); + +@@ -137,7 +181,7 @@ static int mchp_pit64b_clkevt_shutdown(s + + static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev) + { +- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); ++ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); + + mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT, + MCHP_PIT64B_IER_PERIOD); +@@ -148,7 +192,7 @@ static int mchp_pit64b_clkevt_set_period + static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, + struct clock_event_device *cedev) + { +- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); ++ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); + + mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, + MCHP_PIT64B_IER_PERIOD); +@@ -158,21 +202,16 @@ static int mchp_pit64b_clkevt_set_next_e + + static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev) + { +- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); ++ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); + +- writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); +- if (timer->mode & MCHP_PIT64B_MR_SGCLK) +- clk_disable_unprepare(timer->gclk); +- clk_disable_unprepare(timer->pclk); ++ mchp_pit64b_suspend(timer); + } + + static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev) + { +- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); ++ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); + +- clk_prepare_enable(timer->pclk); +- if (timer->mode & MCHP_PIT64B_MR_SGCLK) +- clk_prepare_enable(timer->gclk); ++ mchp_pit64b_resume(timer); + } + + static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id) +@@ -296,20 +335,37 @@ done: + static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer, + u32 clk_rate) + { ++ struct mchp_pit64b_clksrc *cs; + int ret; + ++ cs = kzalloc(sizeof(*cs), GFP_KERNEL); ++ if (!cs) ++ return -ENOMEM; ++ + mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); + + mchp_pit64b_cs_base = timer->base; + +- ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate, +- 210, 64, mchp_pit64b_clksrc_read); ++ cs->timer.base = timer->base; ++ cs->timer.pclk = timer->pclk; ++ cs->timer.gclk = timer->gclk; ++ cs->timer.mode = timer->mode; ++ cs->clksrc.name = MCHP_PIT64B_NAME; ++ cs->clksrc.mask = CLOCKSOURCE_MASK(64); ++ cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; ++ cs->clksrc.rating = 210; ++ cs->clksrc.read = mchp_pit64b_clksrc_read; ++ cs->clksrc.suspend = mchp_pit64b_clksrc_suspend; ++ cs->clksrc.resume = mchp_pit64b_clksrc_resume; ++ ++ ret = clocksource_register_hz(&cs->clksrc, clk_rate); + if (ret) { + pr_debug("clksrc: Failed to register PIT64B clocksource!\n"); + + /* Stop timer. */ + writel_relaxed(MCHP_PIT64B_CR_SWRST, + timer->base + MCHP_PIT64B_CR); ++ kfree(cs); + + return ret; + } diff --git a/target/linux/at91/patches-5.15/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch b/target/linux/at91/patches-5.15/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch new file mode 100644 index 0000000000..072e13bcc6 --- /dev/null +++ b/target/linux/at91/patches-5.15/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch @@ -0,0 +1,135 @@ +From 0b20c174a17dcfa805ddac1301a5af7298877ec3 Mon Sep 17 00:00:00 2001 +From: Lars-Peter Clausen +Date: Wed, 6 Jan 2021 14:36:48 +0100 +Subject: [PATCH 144/247] ASoC: atmel-pdc: Use managed DMA buffer allocation + +Instead of manually managing its DMA buffers using +dma_{alloc,free}_coherent() lets the sound core take care of this using +managed buffers. + +On one hand this reduces the amount of boiler plate code, but the main +motivation for the change is to use the shared code where possible. This +makes it easier to argue about correctness and that the code does not +contain subtle bugs like data leakage or similar. + +Signed-off-by: Lars-Peter Clausen +Reviewed-by: Codrin Ciubotariu +Link: https://lore.kernel.org/r/20210106133650.13509-1-lars@metafoo.de +Signed-off-by: Mark Brown +--- + sound/soc/atmel/atmel-pcm-pdc.c | 78 ++------------------------------- + 1 file changed, 4 insertions(+), 74 deletions(-) + +--- a/sound/soc/atmel/atmel-pcm-pdc.c ++++ b/sound/soc/atmel/atmel-pcm-pdc.c +@@ -34,86 +34,21 @@ + #include "atmel-pcm.h" + + +-static int atmel_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, +- int stream) +-{ +- struct snd_pcm_substream *substream = pcm->streams[stream].substream; +- struct snd_dma_buffer *buf = &substream->dma_buffer; +- size_t size = ATMEL_SSC_DMABUF_SIZE; +- +- buf->dev.type = SNDRV_DMA_TYPE_DEV; +- buf->dev.dev = pcm->card->dev; +- buf->private_data = NULL; +- buf->area = dma_alloc_coherent(pcm->card->dev, size, +- &buf->addr, GFP_KERNEL); +- pr_debug("atmel-pcm: alloc dma buffer: area=%p, addr=%p, size=%zu\n", +- (void *)buf->area, (void *)(long)buf->addr, size); +- +- if (!buf->area) +- return -ENOMEM; +- +- buf->bytes = size; +- return 0; +-} +- +-static int atmel_pcm_mmap(struct snd_soc_component *component, +- struct snd_pcm_substream *substream, +- struct vm_area_struct *vma) +-{ +- return remap_pfn_range(vma, vma->vm_start, +- substream->dma_buffer.addr >> PAGE_SHIFT, +- vma->vm_end - vma->vm_start, vma->vm_page_prot); +-} +- + static int atmel_pcm_new(struct snd_soc_component *component, + struct snd_soc_pcm_runtime *rtd) + { + struct snd_card *card = rtd->card->snd_card; +- struct snd_pcm *pcm = rtd->pcm; + int ret; + + ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32)); + if (ret) + return ret; + +- if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) { +- pr_debug("atmel-pcm: allocating PCM playback DMA buffer\n"); +- ret = atmel_pcm_preallocate_dma_buffer(pcm, +- SNDRV_PCM_STREAM_PLAYBACK); +- if (ret) +- goto out; +- } ++ snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, ++ card->dev, ATMEL_SSC_DMABUF_SIZE, ++ ATMEL_SSC_DMABUF_SIZE); + +- if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { +- pr_debug("atmel-pcm: allocating PCM capture DMA buffer\n"); +- ret = atmel_pcm_preallocate_dma_buffer(pcm, +- SNDRV_PCM_STREAM_CAPTURE); +- if (ret) +- goto out; +- } +- out: +- return ret; +-} +- +-static void atmel_pcm_free(struct snd_soc_component *component, +- struct snd_pcm *pcm) +-{ +- struct snd_pcm_substream *substream; +- struct snd_dma_buffer *buf; +- int stream; +- +- for (stream = 0; stream < 2; stream++) { +- substream = pcm->streams[stream].substream; +- if (!substream) +- continue; +- +- buf = &substream->dma_buffer; +- if (!buf->area) +- continue; +- dma_free_coherent(pcm->card->dev, buf->bytes, +- buf->area, buf->addr); +- buf->area = NULL; +- } ++ return 0; + } + + /*--------------------------------------------------------------------------*\ +@@ -210,9 +145,6 @@ static int atmel_pcm_hw_params(struct sn + /* this may get called several times by oss emulation + * with different params */ + +- snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); +- runtime->dma_bytes = params_buffer_bytes(params); +- + prtd->params = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream); + prtd->params->dma_intr_handler = atmel_pcm_dma_irq; + +@@ -384,9 +316,7 @@ static const struct snd_soc_component_dr + .prepare = atmel_pcm_prepare, + .trigger = atmel_pcm_trigger, + .pointer = atmel_pcm_pointer, +- .mmap = atmel_pcm_mmap, + .pcm_construct = atmel_pcm_new, +- .pcm_destruct = atmel_pcm_free, + }; + + int atmel_pcm_pdc_platform_register(struct device *dev) diff --git a/target/linux/at91/patches-5.15/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch b/target/linux/at91/patches-5.15/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch new file mode 100644 index 0000000000..af1c01bf90 --- /dev/null +++ b/target/linux/at91/patches-5.15/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch @@ -0,0 +1,141 @@ +From f39f2312a68ec0843adba08f9c9182ffa5624190 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 16 Dec 2020 14:57:33 +0200 +Subject: [PATCH 145/247] power: reset: at91-sama5d2_shdwc: add support for + sama7g5 + +Add support for SAMA7G5 by adding proper struct reg_config structure +and since SAMA7G5 is not currently on LPDDR setups the commit also +avoid the mapping of DDR controller. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Sebastian Reichel +--- + drivers/power/reset/at91-sama5d2_shdwc.c | 72 ++++++++++++++++++------ + 1 file changed, 54 insertions(+), 18 deletions(-) + +--- a/drivers/power/reset/at91-sama5d2_shdwc.c ++++ b/drivers/power/reset/at91-sama5d2_shdwc.c +@@ -78,9 +78,15 @@ struct pmc_reg_config { + u8 mckr; + }; + ++struct ddrc_reg_config { ++ u32 type_offset; ++ u32 type_mask; ++}; ++ + struct reg_config { + struct shdwc_reg_config shdwc; + struct pmc_reg_config pmc; ++ struct ddrc_reg_config ddrc; + }; + + struct shdwc { +@@ -262,6 +268,10 @@ static const struct reg_config sama5d2_r + .pmc = { + .mckr = 0x30, + }, ++ .ddrc = { ++ .type_offset = AT91_DDRSDRC_MDR, ++ .type_mask = AT91_DDRSDRC_MD ++ }, + }; + + static const struct reg_config sam9x60_reg_config = { +@@ -275,6 +285,23 @@ static const struct reg_config sam9x60_r + .pmc = { + .mckr = 0x28, + }, ++ .ddrc = { ++ .type_offset = AT91_DDRSDRC_MDR, ++ .type_mask = AT91_DDRSDRC_MD ++ }, ++}; ++ ++static const struct reg_config sama7g5_reg_config = { ++ .shdwc = { ++ .wkup_pin_input = 0, ++ .mr_rtcwk_shift = 17, ++ .mr_rttwk_shift = 16, ++ .sr_rtcwk_shift = 5, ++ .sr_rttwk_shift = 4, ++ }, ++ .pmc = { ++ .mckr = 0x28, ++ }, + }; + + static const struct of_device_id at91_shdwc_of_match[] = { +@@ -285,6 +312,10 @@ static const struct of_device_id at91_sh + { + .compatible = "microchip,sam9x60-shdwc", + .data = &sam9x60_reg_config, ++ }, ++ { ++ .compatible = "microchip,sama7g5-shdwc", ++ .data = &sama7g5_reg_config, + }, { + /*sentinel*/ + } +@@ -294,6 +325,7 @@ MODULE_DEVICE_TABLE(of, at91_shdwc_of_ma + static const struct of_device_id at91_pmc_ids[] = { + { .compatible = "atmel,sama5d2-pmc" }, + { .compatible = "microchip,sam9x60-pmc" }, ++ { .compatible = "microchip,sama7g5-pmc" }, + { /* Sentinel. */ } + }; + +@@ -355,30 +387,34 @@ static int __init at91_shdwc_probe(struc + goto clk_disable; + } + +- np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc"); +- if (!np) { +- ret = -ENODEV; +- goto unmap; +- } ++ if (at91_shdwc->rcfg->ddrc.type_mask) { ++ np = of_find_compatible_node(NULL, NULL, ++ "atmel,sama5d3-ddramc"); ++ if (!np) { ++ ret = -ENODEV; ++ goto unmap; ++ } + +- at91_shdwc->mpddrc_base = of_iomap(np, 0); +- of_node_put(np); ++ at91_shdwc->mpddrc_base = of_iomap(np, 0); ++ of_node_put(np); + +- if (!at91_shdwc->mpddrc_base) { +- ret = -ENOMEM; +- goto unmap; ++ if (!at91_shdwc->mpddrc_base) { ++ ret = -ENOMEM; ++ goto unmap; ++ } ++ ++ ddr_type = readl(at91_shdwc->mpddrc_base + ++ at91_shdwc->rcfg->ddrc.type_offset) & ++ at91_shdwc->rcfg->ddrc.type_mask; ++ if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && ++ ddr_type != AT91_DDRSDRC_MD_LPDDR3) { ++ iounmap(at91_shdwc->mpddrc_base); ++ at91_shdwc->mpddrc_base = NULL; ++ } + } + + pm_power_off = at91_poweroff; + +- ddr_type = readl(at91_shdwc->mpddrc_base + AT91_DDRSDRC_MDR) & +- AT91_DDRSDRC_MD; +- if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && +- ddr_type != AT91_DDRSDRC_MD_LPDDR3) { +- iounmap(at91_shdwc->mpddrc_base); +- at91_shdwc->mpddrc_base = NULL; +- } +- + return 0; + + unmap: diff --git a/target/linux/at91/patches-5.15/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch b/target/linux/at91/patches-5.15/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch new file mode 100644 index 0000000000..84dea5a48a --- /dev/null +++ b/target/linux/at91/patches-5.15/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch @@ -0,0 +1,121 @@ +From bd819c78346012ae0627b1cd4f6ceb1b51162c71 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 27 Jan 2021 13:45:44 +0200 +Subject: [PATCH 146/247] pinctrl: at91-pio4: add support for slew-rate + +SAMA7G5 supports slew rate configuration. Adapt the driver for this. +For output switching frequencies lower than 50MHz the slew rate needs to +be enabled. Since most of the pins on SAMA7G5 fall into this category +enabled the slew rate by default. + +Signed-off-by: Claudiu Beznea +Acked-by: Ludovic Desroches +Link: https://lore.kernel.org/r/1611747945-29960-3-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/pinctrl-at91-pio4.c | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +--- a/drivers/pinctrl/pinctrl-at91-pio4.c ++++ b/drivers/pinctrl/pinctrl-at91-pio4.c +@@ -36,6 +36,7 @@ + #define ATMEL_PIO_DIR_MASK BIT(8) + #define ATMEL_PIO_PUEN_MASK BIT(9) + #define ATMEL_PIO_PDEN_MASK BIT(10) ++#define ATMEL_PIO_SR_MASK BIT(11) + #define ATMEL_PIO_IFEN_MASK BIT(12) + #define ATMEL_PIO_IFSCEN_MASK BIT(13) + #define ATMEL_PIO_OPD_MASK BIT(14) +@@ -76,10 +77,12 @@ + * @nbanks: number of PIO banks + * @last_bank_count: number of lines in the last bank (can be less than + * the rest of the banks). ++ * @slew_rate_support: slew rate support + */ + struct atmel_pioctrl_data { + unsigned nbanks; + unsigned last_bank_count; ++ unsigned int slew_rate_support; + }; + + struct atmel_group { +@@ -117,6 +120,7 @@ struct atmel_pin { + * @pm_suspend_backup: backup/restore register values on suspend/resume + * @dev: device entry for the Atmel PIO controller. + * @node: node of the Atmel PIO controller. ++ * @slew_rate_support: slew rate support + */ + struct atmel_pioctrl { + void __iomem *reg_base; +@@ -138,6 +142,7 @@ struct atmel_pioctrl { + } *pm_suspend_backup; + struct device *dev; + struct device_node *node; ++ unsigned int slew_rate_support; + }; + + static const char * const atmel_functions[] = { +@@ -760,6 +765,13 @@ static int atmel_conf_pin_config_group_g + return -EINVAL; + arg = 1; + break; ++ case PIN_CONFIG_SLEW_RATE: ++ if (!atmel_pioctrl->slew_rate_support) ++ return -EOPNOTSUPP; ++ if (!(res & ATMEL_PIO_SR_MASK)) ++ return -EINVAL; ++ arg = 1; ++ break; + case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: + if (!(res & ATMEL_PIO_DRVSTR_MASK)) + return -EINVAL; +@@ -793,6 +805,10 @@ static int atmel_conf_pin_config_group_s + dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", + __func__, pin_id, configs[i]); + ++ /* Keep slew rate enabled by default. */ ++ if (atmel_pioctrl->slew_rate_support) ++ conf |= ATMEL_PIO_SR_MASK; ++ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + conf &= (~ATMEL_PIO_PUEN_MASK); +@@ -850,6 +866,13 @@ static int atmel_conf_pin_config_group_s + ATMEL_PIO_SODR); + } + break; ++ case PIN_CONFIG_SLEW_RATE: ++ if (!atmel_pioctrl->slew_rate_support) ++ break; ++ /* And remove it if explicitly requested. */ ++ if (arg == 0) ++ conf &= ~ATMEL_PIO_SR_MASK; ++ break; + case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: + switch (arg) { + case ATMEL_PIO_DRVSTR_LO: +@@ -901,6 +924,8 @@ static void atmel_conf_pin_config_dbg_sh + seq_printf(s, "%s ", "open-drain"); + if (conf & ATMEL_PIO_SCHMITT_MASK) + seq_printf(s, "%s ", "schmitt"); ++ if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK)) ++ seq_printf(s, "%s ", "slew-rate"); + if (conf & ATMEL_PIO_DRVSTR_MASK) { + switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) { + case ATMEL_PIO_DRVSTR_ME: +@@ -994,6 +1019,7 @@ static const struct atmel_pioctrl_data a + static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = { + .nbanks = 5, + .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */ ++ .slew_rate_support = 1, + }; + + static const struct of_device_id atmel_pctrl_of_match[] = { +@@ -1039,6 +1065,7 @@ static int atmel_pinctrl_probe(struct pl + atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK; + atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count; + } ++ atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support; + + atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(atmel_pioctrl->reg_base)) diff --git a/target/linux/at91/patches-5.15/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch b/target/linux/at91/patches-5.15/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch new file mode 100644 index 0000000000..0be811cc97 --- /dev/null +++ b/target/linux/at91/patches-5.15/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch @@ -0,0 +1,340 @@ +From 99629d1ad7e4e03ac3324d36b703220555b65566 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 27 Jan 2021 13:45:45 +0200 +Subject: [PATCH 147/247] pinctrl: at91-pio4: fix "Prefer 'unsigned int' to + bare use of 'unsigned'" + +Fix "Prefer 'unsigned int' to bare use of 'unsigned'" checkpatch.pl +warning. + +Signed-off-by: Claudiu Beznea +Acked-by: Ludovic Desroches +Link: https://lore.kernel.org/r/1611747945-29960-4-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/pinctrl-at91-pio4.c | 110 ++++++++++++++-------------- + 1 file changed, 57 insertions(+), 53 deletions(-) + +--- a/drivers/pinctrl/pinctrl-at91-pio4.c ++++ b/drivers/pinctrl/pinctrl-at91-pio4.c +@@ -80,8 +80,8 @@ + * @slew_rate_support: slew rate support + */ + struct atmel_pioctrl_data { +- unsigned nbanks; +- unsigned last_bank_count; ++ unsigned int nbanks; ++ unsigned int last_bank_count; + unsigned int slew_rate_support; + }; + +@@ -91,11 +91,11 @@ struct atmel_group { + }; + + struct atmel_pin { +- unsigned pin_id; +- unsigned mux; +- unsigned ioset; +- unsigned bank; +- unsigned line; ++ unsigned int pin_id; ++ unsigned int mux; ++ unsigned int ioset; ++ unsigned int bank; ++ unsigned int line; + const char *device; + }; + +@@ -125,16 +125,16 @@ struct atmel_pin { + struct atmel_pioctrl { + void __iomem *reg_base; + struct clk *clk; +- unsigned nbanks; ++ unsigned int nbanks; + struct pinctrl_dev *pinctrl_dev; + struct atmel_group *groups; + const char * const *group_names; + struct atmel_pin **pins; +- unsigned npins; ++ unsigned int npins; + struct gpio_chip *gpio_chip; + struct irq_domain *irq_domain; + int *irqs; +- unsigned *pm_wakeup_sources; ++ unsigned int *pm_wakeup_sources; + struct { + u32 imr; + u32 odsr; +@@ -177,11 +177,11 @@ static void atmel_gpio_irq_ack(struct ir + */ + } + +-static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type) ++static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type) + { + struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); + struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; +- unsigned reg; ++ unsigned int reg; + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, + BIT(pin->line)); +@@ -268,7 +268,7 @@ static struct irq_chip atmel_gpio_irq_ch + .irq_set_wake = atmel_gpio_irq_set_wake, + }; + +-static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) ++static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) + { + struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); + +@@ -316,11 +316,12 @@ static void atmel_gpio_irq_handler(struc + chained_irq_exit(chip, desc); + } + +-static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) ++static int atmel_gpio_direction_input(struct gpio_chip *chip, ++ unsigned int offset) + { + struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); + struct atmel_pin *pin = atmel_pioctrl->pins[offset]; +- unsigned reg; ++ unsigned int reg; + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, + BIT(pin->line)); +@@ -331,11 +332,11 @@ static int atmel_gpio_direction_input(st + return 0; + } + +-static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) ++static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset) + { + struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); + struct atmel_pin *pin = atmel_pioctrl->pins[offset]; +- unsigned reg; ++ unsigned int reg; + + reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); + +@@ -369,12 +370,13 @@ static int atmel_gpio_get_multiple(struc + return 0; + } + +-static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, ++static int atmel_gpio_direction_output(struct gpio_chip *chip, ++ unsigned int offset, + int value) + { + struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); + struct atmel_pin *pin = atmel_pioctrl->pins[offset]; +- unsigned reg; ++ unsigned int reg; + + atmel_gpio_write(atmel_pioctrl, pin->bank, + value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, +@@ -389,7 +391,7 @@ static int atmel_gpio_direction_output(s + return 0; + } + +-static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) ++static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) + { + struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); + struct atmel_pin *pin = atmel_pioctrl->pins[offset]; +@@ -445,11 +447,11 @@ static struct gpio_chip atmel_gpio_chip + + /* --- PINCTRL --- */ + static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, +- unsigned pin_id) ++ unsigned int pin_id) + { + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); +- unsigned bank = atmel_pioctrl->pins[pin_id]->bank; +- unsigned line = atmel_pioctrl->pins[pin_id]->line; ++ unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; ++ unsigned int line = atmel_pioctrl->pins[pin_id]->line; + void __iomem *addr = atmel_pioctrl->reg_base + + bank * ATMEL_PIO_BANK_OFFSET; + +@@ -461,11 +463,11 @@ static unsigned int atmel_pin_config_rea + } + + static void atmel_pin_config_write(struct pinctrl_dev *pctldev, +- unsigned pin_id, u32 conf) ++ unsigned int pin_id, u32 conf) + { + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); +- unsigned bank = atmel_pioctrl->pins[pin_id]->bank; +- unsigned line = atmel_pioctrl->pins[pin_id]->line; ++ unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; ++ unsigned int line = atmel_pioctrl->pins[pin_id]->line; + void __iomem *addr = atmel_pioctrl->reg_base + + bank * ATMEL_PIO_BANK_OFFSET; + +@@ -483,7 +485,7 @@ static int atmel_pctl_get_groups_count(s + } + + static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, +- unsigned selector) ++ unsigned int selector) + { + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + +@@ -491,19 +493,20 @@ static const char *atmel_pctl_get_group_ + } + + static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, +- unsigned selector, const unsigned **pins, +- unsigned *num_pins) ++ unsigned int selector, ++ const unsigned int **pins, ++ unsigned int *num_pins) + { + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + +- *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin; ++ *pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin; + *num_pins = 1; + + return 0; + } + + static struct atmel_group * +-atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin) ++atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin) + { + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + int i; +@@ -524,7 +527,7 @@ static int atmel_pctl_xlate_pinfunc(stru + const char **func_name) + { + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); +- unsigned pin_id, func_id; ++ unsigned int pin_id, func_id; + struct atmel_group *grp; + + pin_id = ATMEL_GET_PIN_NO(pinfunc); +@@ -554,10 +557,10 @@ static int atmel_pctl_xlate_pinfunc(stru + static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, +- unsigned *reserved_maps, +- unsigned *num_maps) ++ unsigned int *reserved_maps, ++ unsigned int *num_maps) + { +- unsigned num_pins, num_configs, reserve; ++ unsigned int num_pins, num_configs, reserve; + unsigned long *configs; + struct property *pins; + u32 pinfunc; +@@ -628,10 +631,10 @@ exit: + static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, +- unsigned *num_maps) ++ unsigned int *num_maps) + { + struct device_node *np; +- unsigned reserved_maps; ++ unsigned int reserved_maps; + int ret; + + *map = NULL; +@@ -679,13 +682,13 @@ static int atmel_pmx_get_functions_count + } + + static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, +- unsigned selector) ++ unsigned int selector) + { + return atmel_functions[selector]; + } + + static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, +- unsigned selector, ++ unsigned int selector, + const char * const **groups, + unsigned * const num_groups) + { +@@ -698,11 +701,11 @@ static int atmel_pmx_get_function_groups + } + + static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, +- unsigned function, +- unsigned group) ++ unsigned int function, ++ unsigned int group) + { + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); +- unsigned pin; ++ unsigned int pin; + u32 conf; + + dev_dbg(pctldev->dev, "enable function %s group %s\n", +@@ -726,13 +729,13 @@ static const struct pinmux_ops atmel_pmx + }; + + static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, +- unsigned group, ++ unsigned int group, + unsigned long *config) + { + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); +- unsigned param = pinconf_to_config_param(*config), arg = 0; ++ unsigned int param = pinconf_to_config_param(*config), arg = 0; + struct atmel_group *grp = atmel_pioctrl->groups + group; +- unsigned pin_id = grp->pin; ++ unsigned int pin_id = grp->pin; + u32 res; + + res = atmel_pin_config_read(pctldev, pin_id); +@@ -786,21 +789,21 @@ static int atmel_conf_pin_config_group_g + } + + static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, +- unsigned group, ++ unsigned int group, + unsigned long *configs, +- unsigned num_configs) ++ unsigned int num_configs) + { + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + struct atmel_group *grp = atmel_pioctrl->groups + group; +- unsigned bank, pin, pin_id = grp->pin; ++ unsigned int bank, pin, pin_id = grp->pin; + u32 mask, conf = 0; + int i; + + conf = atmel_pin_config_read(pctldev, pin_id); + + for (i = 0; i < num_configs; i++) { +- unsigned param = pinconf_to_config_param(configs[i]); +- unsigned arg = pinconf_to_config_argument(configs[i]); ++ unsigned int param = pinconf_to_config_param(configs[i]); ++ unsigned int arg = pinconf_to_config_argument(configs[i]); + + dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", + __func__, pin_id, configs[i]); +@@ -900,7 +903,8 @@ static int atmel_conf_pin_config_group_s + } + + static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, +- struct seq_file *s, unsigned pin_id) ++ struct seq_file *s, ++ unsigned int pin_id) + { + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + u32 conf; +@@ -1108,8 +1112,8 @@ static int atmel_pinctrl_probe(struct pl + return -ENOMEM; + for (i = 0 ; i < atmel_pioctrl->npins; i++) { + struct atmel_group *group = atmel_pioctrl->groups + i; +- unsigned bank = ATMEL_PIO_BANK(i); +- unsigned line = ATMEL_PIO_LINE(i); ++ unsigned int bank = ATMEL_PIO_BANK(i); ++ unsigned int line = ATMEL_PIO_LINE(i); + + atmel_pioctrl->pins[i] = devm_kzalloc(dev, + sizeof(**atmel_pioctrl->pins), GFP_KERNEL); diff --git a/target/linux/at91/patches-5.15/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch b/target/linux/at91/patches-5.15/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch new file mode 100644 index 0000000000..721ddaea00 --- /dev/null +++ b/target/linux/at91/patches-5.15/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch @@ -0,0 +1,58 @@ +From 096f58e564aed56936ef6de42a44c3101e9b8ed1 Mon Sep 17 00:00:00 2001 +From: Atish Patra +Date: Wed, 3 Mar 2021 11:55:49 -0800 +Subject: [PATCH 148/247] net: macb: Add default usrio config to default gem + config + +There is no usrio config defined for default gem config leading to +a kernel panic devices that don't define a data. This issue can be +reprdouced with microchip polar fire soc where compatible string +is defined as "cdns,macb". + +Fixes: edac63861db7 ("add userio bits as platform configuration") + +Signed-off-by: Atish Patra +Acked-by: Nicolas Ferre +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/cadence/macb_main.c | 15 ++++++++------- + 1 file changed, 8 insertions(+), 7 deletions(-) + +--- a/drivers/net/ethernet/cadence/macb_main.c ++++ b/drivers/net/ethernet/cadence/macb_main.c +@@ -3868,6 +3868,13 @@ static int macb_init(struct platform_dev + return 0; + } + ++static const struct macb_usrio_config macb_default_usrio = { ++ .mii = MACB_BIT(MII), ++ .rmii = MACB_BIT(RMII), ++ .rgmii = GEM_BIT(RGMII), ++ .refclk = MACB_BIT(CLKEN), ++}; ++ + #if defined(CONFIG_OF) + /* 1518 rounded up */ + #define AT91ETHER_MAX_RBUFF_SZ 0x600 +@@ -4383,13 +4390,6 @@ static int fu540_c000_init(struct platfo + return macb_init(pdev); + } + +-static const struct macb_usrio_config macb_default_usrio = { +- .mii = MACB_BIT(MII), +- .rmii = MACB_BIT(RMII), +- .rgmii = GEM_BIT(RGMII), +- .refclk = MACB_BIT(CLKEN), +-}; +- + static const struct macb_usrio_config sama7g5_usrio = { + .mii = 0, + .rmii = 1, +@@ -4538,6 +4538,7 @@ static const struct macb_config default_ + .dma_burst_length = 16, + .clk_init = macb_clk_init, + .init = macb_init, ++ .usrio = &macb_default_usrio, + .jumbo_max_len = 10240, + }; + diff --git a/target/linux/at91/patches-5.15/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch b/target/linux/at91/patches-5.15/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch new file mode 100644 index 0000000000..cc7f6583aa --- /dev/null +++ b/target/linux/at91/patches-5.15/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch @@ -0,0 +1,108 @@ +From 746aba88c64e409cbc3757a5f81fad5b5c74bbcc Mon Sep 17 00:00:00 2001 +From: Lee Jones +Date: Wed, 3 Mar 2021 12:41:49 +0000 +Subject: [PATCH 149/247] ARM: at91: pm: Move prototypes to mutually included + header +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Both the caller and the supplier's source file should have access to +the include file containing the prototypes. + +Fixes the following W=1 kernel build warning(s): + + drivers/pinctrl/pinctrl-at91.c:1637:6: warning: no previous prototype for ‘at91_pinctrl_gpio_suspend’ [-Wmissing-prototypes] + 1637 | void at91_pinctrl_gpio_suspend(void) + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + drivers/pinctrl/pinctrl-at91.c:1661:6: warning: no previous prototype for ‘at91_pinctrl_gpio_resume’ [-Wmissing-prototypes] + 1661 | void at91_pinctrl_gpio_resume(void) + | ^~~~~~~~~~~~~~~~~~~~~~~~ + +Cc: Russell King +Cc: Nicolas Ferre +Cc: Alexandre Belloni +Cc: Ludovic Desroches +Signed-off-by: Lee Jones +Acked-by: Linus Walleij +Signed-off-by: Alexandre Belloni +Link: https://lore.kernel.org/r/20210303124149.3149511-1-lee.jones@linaro.org +--- + arch/arm/mach-at91/pm.c | 19 ++++++++----------- + drivers/pinctrl/pinctrl-at91.c | 2 ++ + include/soc/at91/pm.h | 16 ++++++++++++++++ + 3 files changed, 26 insertions(+), 11 deletions(-) + create mode 100644 include/soc/at91/pm.h + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -17,6 +17,8 @@ + #include + #include + ++#include ++ + #include + #include + #include +@@ -25,17 +27,6 @@ + #include "generic.h" + #include "pm.h" + +-/* +- * FIXME: this is needed to communicate between the pinctrl driver and +- * the PM implementation in the machine. Possibly part of the PM +- * implementation should be moved down into the pinctrl driver and get +- * called as part of the generic suspend/resume path. +- */ +-#ifdef CONFIG_PINCTRL_AT91 +-extern void at91_pinctrl_gpio_suspend(void); +-extern void at91_pinctrl_gpio_resume(void); +-#endif +- + struct at91_soc_pm { + int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); + int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); +@@ -326,6 +317,12 @@ static void at91_pm_suspend(suspend_stat + static int at91_pm_enter(suspend_state_t state) + { + #ifdef CONFIG_PINCTRL_AT91 ++ /* ++ * FIXME: this is needed to communicate between the pinctrl driver and ++ * the PM implementation in the machine. Possibly part of the PM ++ * implementation should be moved down into the pinctrl driver and get ++ * called as part of the generic suspend/resume path. ++ */ + at91_pinctrl_gpio_suspend(); + #endif + +--- a/drivers/pinctrl/pinctrl-at91.c ++++ b/drivers/pinctrl/pinctrl-at91.c +@@ -23,6 +23,8 @@ + /* Since we request GPIOs from ourself */ + #include + ++#include ++ + #include "pinctrl-at91.h" + #include "core.h" + +--- /dev/null ++++ b/include/soc/at91/pm.h +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Atmel Power Management ++ * ++ * Copyright (C) 2020 Atmel ++ * ++ * Author: Lee Jones ++ */ ++ ++#ifndef __SOC_ATMEL_PM_H ++#define __SOC_ATMEL_PM_H ++ ++void at91_pinctrl_gpio_suspend(void); ++void at91_pinctrl_gpio_resume(void); ++ ++#endif /* __SOC_ATMEL_PM_H */ diff --git a/target/linux/at91/patches-5.15/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch b/target/linux/at91/patches-5.15/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch new file mode 100644 index 0000000000..174d0b3ced --- /dev/null +++ b/target/linux/at91/patches-5.15/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch @@ -0,0 +1,46 @@ +From d6493e6f1c42f7ad350ea25e11f0e71fc32e6116 Mon Sep 17 00:00:00 2001 +From: Codrin Ciubotariu +Date: Mon, 1 Mar 2021 19:09:00 +0200 +Subject: [PATCH 150/247] ASoC: mchp-i2s-mcc: Add compatible for SAMA7G5 + +Microchip's new SAMA7G5 includes an updated I2S-MCC compatible with the +previous version found on SAM9X60. The new controller includes 8 (4 * 2) +input and output data pins for up to 8 channels for I2S and Left-Justified +formats. + +Signed-off-by: Codrin Ciubotariu +Link: https://lore.kernel.org/r/20210301170905.835091-3-codrin.ciubotariu@microchip.com +Signed-off-by: Mark Brown +--- + sound/soc/atmel/Kconfig | 3 +++ + sound/soc/atmel/mchp-i2s-mcc.c | 3 +++ + 2 files changed, 6 insertions(+) + +--- a/sound/soc/atmel/Kconfig ++++ b/sound/soc/atmel/Kconfig +@@ -126,10 +126,13 @@ config SND_MCHP_SOC_I2S_MCC + Say Y or M if you want to add support for I2S Multi-Channel ASoC + driver on the following Microchip platforms: + - sam9x60 ++ - sama7g5 + + The I2SMCC complies with the Inter-IC Sound (I2S) bus specification + and supports a Time Division Multiplexed (TDM) interface with + external multi-channel audio codecs. ++ Starting with sama7g5, I2S and Left-Justified multi-channel is ++ supported by using multiple data pins, output and input, without TDM. + + config SND_MCHP_SOC_SPDIFTX + tristate "Microchip ASoC driver for boards using S/PDIF TX" +--- a/sound/soc/atmel/mchp-i2s-mcc.c ++++ b/sound/soc/atmel/mchp-i2s-mcc.c +@@ -873,6 +873,9 @@ static const struct of_device_id mchp_i2 + { + .compatible = "microchip,sam9x60-i2smcc", + }, ++ { ++ .compatible = "microchip,sama7g5-i2smcc", ++ }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids); diff --git a/target/linux/at91/patches-5.15/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch b/target/linux/at91/patches-5.15/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch new file mode 100644 index 0000000000..5047e04d5b --- /dev/null +++ b/target/linux/at91/patches-5.15/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch @@ -0,0 +1,113 @@ +From 5bef4e8125d09443b5486971d5550ed285cde4b1 Mon Sep 17 00:00:00 2001 +From: Codrin Ciubotariu +Date: Mon, 1 Mar 2021 19:09:01 +0200 +Subject: [PATCH 151/247] ASoC: mchp-i2s-mcc: Add multi-channel support for I2S + and LEFT_J formats + +The latest I2S-MCC available in SAMA7G5 supports multi-channel for I2S and +Left-Justified formats. For this, the new version uses 8 (4 * 2) input and +output pins, with each pin being responsible for 2 channels. This sums up +to a total of 8 channels for synchronous capture and playback. + +Signed-off-by: Codrin Ciubotariu +Link: https://lore.kernel.org/r/20210301170905.835091-4-codrin.ciubotariu@microchip.com +Signed-off-by: Mark Brown +--- + sound/soc/atmel/mchp-i2s-mcc.c | 38 ++++++++++++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +--- a/sound/soc/atmel/mchp-i2s-mcc.c ++++ b/sound/soc/atmel/mchp-i2s-mcc.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -225,6 +226,10 @@ static const struct regmap_config mchp_i + .max_register = MCHP_I2SMCC_VERSION, + }; + ++struct mchp_i2s_mcc_soc_data { ++ unsigned int data_pin_pair_num; ++}; ++ + struct mchp_i2s_mcc_dev { + struct wait_queue_head wq_txrdy; + struct wait_queue_head wq_rxrdy; +@@ -232,6 +237,7 @@ struct mchp_i2s_mcc_dev { + struct regmap *regmap; + struct clk *pclk; + struct clk *gclk; ++ const struct mchp_i2s_mcc_soc_data *soc; + struct snd_dmaengine_dai_dma_data playback; + struct snd_dmaengine_dai_dma_data capture; + unsigned int fmt; +@@ -549,6 +555,17 @@ static int mchp_i2s_mcc_hw_params(struct + } + + if (dev->fmt & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) { ++ /* for I2S and LEFT_J one pin is needed for every 2 channels */ ++ if (channels > dev->soc->data_pin_pair_num * 2) { ++ dev_err(dev->dev, ++ "unsupported number of audio channels: %d\n", ++ channels); ++ return -EINVAL; ++ } ++ ++ /* enable for interleaved format */ ++ mrb |= MCHP_I2SMCC_MRB_CRAMODE_REGULAR; ++ + switch (channels) { + case 1: + if (is_playback) +@@ -558,6 +575,12 @@ static int mchp_i2s_mcc_hw_params(struct + break; + case 2: + break; ++ case 4: ++ mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1; ++ break; ++ case 8: ++ mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2; ++ break; + default: + dev_err(dev->dev, "unsupported number of audio channels\n"); + return -EINVAL; +@@ -869,12 +892,22 @@ static const struct snd_soc_component_dr + }; + + #ifdef CONFIG_OF ++static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sam9x60 = { ++ .data_pin_pair_num = 1, ++}; ++ ++static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = { ++ .data_pin_pair_num = 4, ++}; ++ + static const struct of_device_id mchp_i2s_mcc_dt_ids[] = { + { + .compatible = "microchip,sam9x60-i2smcc", ++ .data = &mchp_i2s_mcc_sam9x60, + }, + { + .compatible = "microchip,sama7g5-i2smcc", ++ .data = &mchp_i2s_mcc_sama7g5, + }, + { /* sentinel */ } + }; +@@ -932,6 +965,11 @@ static int mchp_i2s_mcc_probe(struct pla + dev->gclk = NULL; + } + ++ dev->soc = of_device_get_match_data(&pdev->dev); ++ if (!dev->soc) { ++ dev_err(&pdev->dev, "failed to get soc data\n"); ++ return -ENODEV; ++ } + dev->dev = &pdev->dev; + dev->regmap = regmap; + platform_set_drvdata(pdev, dev); diff --git a/target/linux/at91/patches-5.15/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch b/target/linux/at91/patches-5.15/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch new file mode 100644 index 0000000000..6d5a15d36b --- /dev/null +++ b/target/linux/at91/patches-5.15/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch @@ -0,0 +1,108 @@ +From 2bbdc5b38603384996271a8817b0578a2360af2f Mon Sep 17 00:00:00 2001 +From: Codrin Ciubotariu +Date: Mon, 1 Mar 2021 19:09:03 +0200 +Subject: [PATCH 152/247] ASoC: mchp-i2s-mcc: Add support to select TDM pins + +SAMA7G5's I2S-MCC has 4 pairs of DIN/DOUT pins. Since TDM only uses a +single pair of pins for synchronous capture and playback, the controller +needs to be told which of the pair is connected. This can be mentioned +using the "microchip,tdm-data-pair" property from DT. The property is +optional, useful only if TDM is used. If it's missing, DIN/DOUT 0 pins +will be used by default. + +Signed-off-by: Codrin Ciubotariu +Link: https://lore.kernel.org/r/20210301170905.835091-6-codrin.ciubotariu@microchip.com +Signed-off-by: Mark Brown +--- + sound/soc/atmel/mchp-i2s-mcc.c | 52 +++++++++++++++++++++++++++++++--- + 1 file changed, 48 insertions(+), 4 deletions(-) + +--- a/sound/soc/atmel/mchp-i2s-mcc.c ++++ b/sound/soc/atmel/mchp-i2s-mcc.c +@@ -100,6 +100,8 @@ + #define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS_COMPACT (7 << 1) + + #define MCHP_I2SMCC_MRA_WIRECFG_MASK GENMASK(5, 4) ++#define MCHP_I2SMCC_MRA_WIRECFG_TDM(pin) (((pin) << 4) & \ ++ MCHP_I2SMCC_MRA_WIRECFG_MASK) + #define MCHP_I2SMCC_MRA_WIRECFG_I2S_1_TDM_0 (0 << 4) + #define MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1 (1 << 4) + #define MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2 (2 << 4) +@@ -245,6 +247,7 @@ struct mchp_i2s_mcc_dev { + unsigned int frame_length; + int tdm_slots; + int channels; ++ u8 tdm_data_pair; + unsigned int gclk_use:1; + unsigned int gclk_running:1; + unsigned int tx_rdy:1; +@@ -589,6 +592,8 @@ static int mchp_i2s_mcc_hw_params(struct + if (!frame_length) + frame_length = 2 * params_physical_width(params); + } else if (dev->fmt & SND_SOC_DAIFMT_DSP_A) { ++ mra |= MCHP_I2SMCC_MRA_WIRECFG_TDM(dev->tdm_data_pair); ++ + if (dev->tdm_slots) { + if (channels % 2 && channels * 2 <= dev->tdm_slots) { + /* +@@ -914,6 +919,45 @@ static const struct of_device_id mchp_i2 + MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids); + #endif + ++static int mchp_i2s_mcc_soc_data_parse(struct platform_device *pdev, ++ struct mchp_i2s_mcc_dev *dev) ++{ ++ int err; ++ ++ if (!dev->soc) { ++ dev_err(&pdev->dev, "failed to get soc data\n"); ++ return -ENODEV; ++ } ++ ++ if (dev->soc->data_pin_pair_num == 1) ++ return 0; ++ ++ err = of_property_read_u8(pdev->dev.of_node, "microchip,tdm-data-pair", ++ &dev->tdm_data_pair); ++ if (err < 0 && err != -EINVAL) { ++ dev_err(&pdev->dev, ++ "bad property data for 'microchip,tdm-data-pair': %d", ++ err); ++ return err; ++ } ++ if (err == -EINVAL) { ++ dev_info(&pdev->dev, ++ "'microchip,tdm-data-pair' not found; assuming DIN/DOUT 0 for TDM\n"); ++ dev->tdm_data_pair = 0; ++ } else { ++ if (dev->tdm_data_pair > dev->soc->data_pin_pair_num - 1) { ++ dev_err(&pdev->dev, ++ "invalid value for 'microchip,tdm-data-pair': %d\n", ++ dev->tdm_data_pair); ++ return -EINVAL; ++ } ++ dev_dbg(&pdev->dev, "TMD format on DIN/DOUT %d pins\n", ++ dev->tdm_data_pair); ++ } ++ ++ return 0; ++} ++ + static int mchp_i2s_mcc_probe(struct platform_device *pdev) + { + struct mchp_i2s_mcc_dev *dev; +@@ -966,10 +1010,10 @@ static int mchp_i2s_mcc_probe(struct pla + } + + dev->soc = of_device_get_match_data(&pdev->dev); +- if (!dev->soc) { +- dev_err(&pdev->dev, "failed to get soc data\n"); +- return -ENODEV; +- } ++ err = mchp_i2s_mcc_soc_data_parse(pdev, dev); ++ if (err < 0) ++ return err; ++ + dev->dev = &pdev->dev; + dev->regmap = regmap; + platform_set_drvdata(pdev, dev); diff --git a/target/linux/at91/patches-5.15/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch b/target/linux/at91/patches-5.15/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch new file mode 100644 index 0000000000..24e0e4de4c --- /dev/null +++ b/target/linux/at91/patches-5.15/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch @@ -0,0 +1,187 @@ +From 36bb4f0ab8e7ef69cc11d4d888aa898223b0e901 Mon Sep 17 00:00:00 2001 +From: Codrin Ciubotariu +Date: Mon, 1 Mar 2021 19:09:04 +0200 +Subject: [PATCH 153/247] ASoC: mchp-i2s-mcc: Add FIFOs support + +I2S-MCC found on SAMA7G5 includes 2 FIFOs (capture and playback). When +FIFOs are enabled, bits I2SMCC_ISRA.TXLRDYx and I2SMCC_ISRA.TXRRDYx must +not be used. Bits I2SMCC_ISRB.TXFFRDY and I2SMCC_ISRB.RXFFRDY must be used +instead. + +Signed-off-by: Codrin Ciubotariu +Link: https://lore.kernel.org/r/20210301170905.835091-7-codrin.ciubotariu@microchip.com +Signed-off-by: Mark Brown +--- + sound/soc/atmel/mchp-i2s-mcc.c | 76 +++++++++++++++++++++++++--------- + 1 file changed, 56 insertions(+), 20 deletions(-) + +--- a/sound/soc/atmel/mchp-i2s-mcc.c ++++ b/sound/soc/atmel/mchp-i2s-mcc.c +@@ -176,7 +176,7 @@ + */ + #define MCHP_I2SMCC_MRB_CRAMODE_REGULAR (1 << 0) + +-#define MCHP_I2SMCC_MRB_FIFOEN BIT(1) ++#define MCHP_I2SMCC_MRB_FIFOEN BIT(4) + + #define MCHP_I2SMCC_MRB_DMACHUNK_MASK GENMASK(9, 8) + #define MCHP_I2SMCC_MRB_DMACHUNK(no_words) \ +@@ -230,6 +230,7 @@ static const struct regmap_config mchp_i + + struct mchp_i2s_mcc_soc_data { + unsigned int data_pin_pair_num; ++ bool has_fifo; + }; + + struct mchp_i2s_mcc_dev { +@@ -257,7 +258,7 @@ struct mchp_i2s_mcc_dev { + static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id) + { + struct mchp_i2s_mcc_dev *dev = dev_id; +- u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0; ++ u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0, idrb = 0; + irqreturn_t ret = IRQ_NONE; + + regmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra); +@@ -275,24 +276,36 @@ static irqreturn_t mchp_i2s_mcc_interrup + * Tx/Rx ready interrupts are enabled when stopping only, to assure + * availability and to disable clocks if necessary + */ +- idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) | +- MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); +- if (idra) ++ if (dev->soc->has_fifo) { ++ idrb |= pendingb & (MCHP_I2SMCC_INT_TXFFRDY | ++ MCHP_I2SMCC_INT_RXFFRDY); ++ } else { ++ idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) | ++ MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); ++ } ++ if (idra || idrb) + ret = IRQ_HANDLED; + +- if ((imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) && +- (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) == +- (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) { ++ if ((!dev->soc->has_fifo && ++ (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) && ++ (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) == ++ (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) || ++ (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_TXFFRDY)) { + dev->tx_rdy = 1; + wake_up_interruptible(&dev->wq_txrdy); + } +- if ((imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) && +- (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) == +- (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) { ++ if ((!dev->soc->has_fifo && ++ (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) && ++ (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) == ++ (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) || ++ (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_RXFFRDY)) { + dev->rx_rdy = 1; + wake_up_interruptible(&dev->wq_rxrdy); + } +- regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra); ++ if (dev->soc->has_fifo) ++ regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, idrb); ++ else ++ regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra); + + return ret; + } +@@ -664,6 +677,10 @@ static int mchp_i2s_mcc_hw_params(struct + } + } + ++ /* enable FIFO if available */ ++ if (dev->soc->has_fifo) ++ mrb |= MCHP_I2SMCC_MRB_FIFOEN; ++ + /* + * If we are already running, the wanted setup must be + * the same with the one that's currently ongoing +@@ -726,8 +743,13 @@ static int mchp_i2s_mcc_hw_free(struct s + if (err == 0) { + dev_warn_once(dev->dev, + "Timeout waiting for Tx ready\n"); +- regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, +- MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)); ++ if (dev->soc->has_fifo) ++ regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, ++ MCHP_I2SMCC_INT_TXFFRDY); ++ else ++ regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, ++ MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)); ++ + dev->tx_rdy = 1; + } + } else { +@@ -737,8 +759,12 @@ static int mchp_i2s_mcc_hw_free(struct s + if (err == 0) { + dev_warn_once(dev->dev, + "Timeout waiting for Rx ready\n"); +- regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, +- MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); ++ if (dev->soc->has_fifo) ++ regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, ++ MCHP_I2SMCC_INT_RXFFRDY); ++ else ++ regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, ++ MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); + dev->rx_rdy = 1; + } + } +@@ -765,7 +791,7 @@ static int mchp_i2s_mcc_trigger(struct s + struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai); + bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); + u32 cr = 0; +- u32 iera = 0; ++ u32 iera = 0, ierb = 0; + u32 sr; + int err; + +@@ -789,7 +815,10 @@ static int mchp_i2s_mcc_trigger(struct s + * Enable Tx Ready interrupts on all channels + * to assure all data is sent + */ +- iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels); ++ if (dev->soc->has_fifo) ++ ierb = MCHP_I2SMCC_INT_TXFFRDY; ++ else ++ iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels); + } else if (!is_playback && (sr & MCHP_I2SMCC_SR_RXEN)) { + cr = MCHP_I2SMCC_CR_RXDIS; + dev->rx_rdy = 0; +@@ -797,7 +826,10 @@ static int mchp_i2s_mcc_trigger(struct s + * Enable Rx Ready interrupts on all channels + * to assure all data is received + */ +- iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels); ++ if (dev->soc->has_fifo) ++ ierb = MCHP_I2SMCC_INT_RXFFRDY; ++ else ++ iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels); + } + break; + default: +@@ -815,7 +847,10 @@ static int mchp_i2s_mcc_trigger(struct s + } + } + +- regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera); ++ if (dev->soc->has_fifo) ++ regmap_write(dev->regmap, MCHP_I2SMCC_IERB, ierb); ++ else ++ regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera); + regmap_write(dev->regmap, MCHP_I2SMCC_CR, cr); + + return 0; +@@ -903,6 +938,7 @@ static struct mchp_i2s_mcc_soc_data mchp + + static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = { + .data_pin_pair_num = 4, ++ .has_fifo = true, + }; + + static const struct of_device_id mchp_i2s_mcc_dt_ids[] = { diff --git a/target/linux/at91/patches-5.15/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch b/target/linux/at91/patches-5.15/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch new file mode 100644 index 0000000000..c61e6b1c90 --- /dev/null +++ b/target/linux/at91/patches-5.15/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch @@ -0,0 +1,49 @@ +From dc07cbae6e96843d26e8f10b16e901620bd16462 Mon Sep 17 00:00:00 2001 +From: Tudor Ambarus +Date: Fri, 9 Apr 2021 11:25:22 +0300 +Subject: [PATCH 154/247] pinctrl: at91-pio4: Fix slew rate disablement + +The slew rate was enabled by default for each configuration of the +pin. In case the pin had more than one configuration, even if +we set the slew rate as disabled in the device tree, the next pin +configuration would set again the slew rate enabled by default, +overwriting the slew rate disablement. +Instead of enabling the slew rate by default for each pin configuration, +enable the slew rate by default just once per pin, regardless of the +number of configurations. This way the slew rate disablement will also +work for cases where pins have multiple configurations. + +Fixes: c709135e576b ("pinctrl: at91-pio4: add support for slew-rate") +Signed-off-by: Tudor Ambarus +Reviewed-by: Claudiu Beznea +Acked-by: Ludovic Desroches +Link: https://lore.kernel.org/r/20210409082522.625168-1-tudor.ambarus@microchip.com +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/pinctrl-at91-pio4.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/pinctrl/pinctrl-at91-pio4.c ++++ b/drivers/pinctrl/pinctrl-at91-pio4.c +@@ -801,6 +801,10 @@ static int atmel_conf_pin_config_group_s + + conf = atmel_pin_config_read(pctldev, pin_id); + ++ /* Keep slew rate enabled by default. */ ++ if (atmel_pioctrl->slew_rate_support) ++ conf |= ATMEL_PIO_SR_MASK; ++ + for (i = 0; i < num_configs; i++) { + unsigned int param = pinconf_to_config_param(configs[i]); + unsigned int arg = pinconf_to_config_argument(configs[i]); +@@ -808,10 +812,6 @@ static int atmel_conf_pin_config_group_s + dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", + __func__, pin_id, configs[i]); + +- /* Keep slew rate enabled by default. */ +- if (atmel_pioctrl->slew_rate_support) +- conf |= ATMEL_PIO_SR_MASK; +- + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + conf &= (~ATMEL_PIO_PUEN_MASK); diff --git a/target/linux/at91/patches-5.15/155-media-atmel-properly-get-pm_runtime.patch b/target/linux/at91/patches-5.15/155-media-atmel-properly-get-pm_runtime.patch new file mode 100644 index 0000000000..58f90db46d --- /dev/null +++ b/target/linux/at91/patches-5.15/155-media-atmel-properly-get-pm_runtime.patch @@ -0,0 +1,159 @@ +From c7660cc977621c4a14d870d523918df067f0db39 Mon Sep 17 00:00:00 2001 +From: Mauro Carvalho Chehab +Date: Fri, 23 Apr 2021 16:47:42 +0200 +Subject: [PATCH 155/247] media: atmel: properly get pm_runtime + +There are several issues in the way the atmel driver handles +pm_runtime_get_sync(): + +- it doesn't check return codes; +- it doesn't properly decrement the usage_count on all places; +- it starts streaming even if pm_runtime_get_sync() fails. +- while it tries to get pm_runtime at the clock enable logic, + it doesn't check if the operation was suceeded. + +Replace all occurrences of it to use the new kAPI: +pm_runtime_resume_and_get(), which ensures that, if the +return code is not negative, the usage_count was incremented. + +With that, add additional checks when this is called, in order +to ensure that errors will be properly addressed. + +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 30 ++++++++++++++----- + drivers/media/platform/atmel/atmel-isi.c | 19 +++++++++--- + 2 files changed, 38 insertions(+), 11 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -294,9 +294,13 @@ static int isc_wait_clk_stable(struct cl + static int isc_clk_prepare(struct clk_hw *hw) + { + struct isc_clk *isc_clk = to_isc_clk(hw); ++ int ret; + +- if (isc_clk->id == ISC_ISPCK) +- pm_runtime_get_sync(isc_clk->dev); ++ if (isc_clk->id == ISC_ISPCK) { ++ ret = pm_runtime_resume_and_get(isc_clk->dev); ++ if (ret < 0) ++ return ret; ++ } + + return isc_wait_clk_stable(hw); + } +@@ -353,9 +357,13 @@ static int isc_clk_is_enabled(struct clk + { + struct isc_clk *isc_clk = to_isc_clk(hw); + u32 status; ++ int ret; + +- if (isc_clk->id == ISC_ISPCK) +- pm_runtime_get_sync(isc_clk->dev); ++ if (isc_clk->id == ISC_ISPCK) { ++ ret = pm_runtime_resume_and_get(isc_clk->dev); ++ if (ret < 0) ++ return 0; ++ } + + regmap_read(isc_clk->regmap, ISC_CLKSR, &status); + +@@ -807,7 +815,12 @@ static int isc_start_streaming(struct vb + goto err_start_stream; + } + +- pm_runtime_get_sync(isc->dev); ++ ret = pm_runtime_resume_and_get(isc->dev); ++ if (ret < 0) { ++ v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n", ++ ret); ++ goto err_pm_get; ++ } + + ret = isc_configure(isc); + if (unlikely(ret)) +@@ -838,7 +851,7 @@ static int isc_start_streaming(struct vb + + err_configure: + pm_runtime_put_sync(isc->dev); +- ++err_pm_get: + v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); + + err_start_stream: +@@ -1809,6 +1822,7 @@ static void isc_awb_work(struct work_str + u32 baysel; + unsigned long flags; + u32 min, max; ++ int ret; + + /* streaming is not active anymore */ + if (isc->stop) +@@ -1831,7 +1845,9 @@ static void isc_awb_work(struct work_str + ctrls->hist_id = hist_id; + baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT; + +- pm_runtime_get_sync(isc->dev); ++ ret = pm_runtime_resume_and_get(isc->dev); ++ if (ret < 0) ++ return; + + /* + * only update if we have all the required histograms and controls +--- a/drivers/media/platform/atmel/atmel-isi.c ++++ b/drivers/media/platform/atmel/atmel-isi.c +@@ -423,7 +423,9 @@ static int start_streaming(struct vb2_qu + struct frame_buffer *buf, *node; + int ret; + +- pm_runtime_get_sync(isi->dev); ++ ret = pm_runtime_resume_and_get(isi->dev); ++ if (ret < 0) ++ return ret; + + /* Enable stream on the sub device */ + ret = v4l2_subdev_call(isi->entity.subdev, video, s_stream, 1); +@@ -783,9 +785,10 @@ static int isi_enum_frameintervals(struc + return 0; + } + +-static void isi_camera_set_bus_param(struct atmel_isi *isi) ++static int isi_camera_set_bus_param(struct atmel_isi *isi) + { + u32 cfg1 = 0; ++ int ret; + + /* set bus param for ISI */ + if (isi->pdata.hsync_act_low) +@@ -802,12 +805,16 @@ static void isi_camera_set_bus_param(str + cfg1 |= ISI_CFG1_THMASK_BEATS_16; + + /* Enable PM and peripheral clock before operate isi registers */ +- pm_runtime_get_sync(isi->dev); ++ ret = pm_runtime_resume_and_get(isi->dev); ++ if (ret < 0) ++ return ret; + + isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS); + isi_writel(isi, ISI_CFG1, cfg1); + + pm_runtime_put(isi->dev); ++ ++ return 0; + } + + /* -----------------------------------------------------------------------*/ +@@ -1086,7 +1093,11 @@ static int isi_graph_notify_complete(str + dev_err(isi->dev, "No supported mediabus format found\n"); + return ret; + } +- isi_camera_set_bus_param(isi); ++ ret = isi_camera_set_bus_param(isi); ++ if (ret) { ++ dev_err(isi->dev, "Can't wake up device\n"); ++ return ret; ++ } + + ret = isi_set_default_fmt(isi); + if (ret) { diff --git a/target/linux/at91/patches-5.15/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch b/target/linux/at91/patches-5.15/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch new file mode 100644 index 0000000000..f8bdcbef23 --- /dev/null +++ b/target/linux/at91/patches-5.15/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch @@ -0,0 +1,32 @@ +From b074b4695004b793a9199716295cb76da6c41686 Mon Sep 17 00:00:00 2001 +From: Jiapeng Chong +Date: Mon, 17 May 2021 12:07:48 +0200 +Subject: [PATCH 156/247] media: atmel: atmel-isc: Remove redundant assignment + to i + +Variable i is being assigned a value however the assignment is +never read, so this redundant assignment can be removed. + +Clean up the following clang-analyzer warning: + +drivers/media/platform/atmel/atmel-isc-base.c:975:2: warning: Value +stored to 'i' is never read [clang-analyzer-deadcode.DeadStores]. + +Reported-by: Abaci Robot +Signed-off-by: Jiapeng Chong +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -972,7 +972,6 @@ static int isc_enum_fmt_vid_cap(struct f + + index -= ARRAY_SIZE(controller_formats); + +- i = 0; + supported_index = 0; + + for (i = 0; i < ARRAY_SIZE(formats_list); i++) { diff --git a/target/linux/at91/patches-5.15/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch b/target/linux/at91/patches-5.15/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch new file mode 100644 index 0000000000..6f2d5879c7 --- /dev/null +++ b/target/linux/at91/patches-5.15/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch @@ -0,0 +1,187 @@ +From c3f54d192dc7344c5216a3628b67c4bbccbf8c3c Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:56:59 +0200 +Subject: [PATCH 157/247] media: atmel: atmel-isc: specialize gamma table into + product specific + +Separate the gamma table from the isc base file into the specific sama5d2 +product file. +Add a pointer to the gamma table and entries count inside the platform +driver specific struct. + +[hverkuil: made isc_sama5d2_gamma_table static] + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 47 ++----------------- + drivers/media/platform/atmel/atmel-isc.h | 11 +++-- + .../media/platform/atmel/atmel-sama5d2-isc.c | 45 ++++++++++++++++++ + 3 files changed, 56 insertions(+), 47 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -176,48 +176,6 @@ struct isc_format formats_list[] = { + + }; + +-/* Gamma table with gamma 1/2.2 */ +-const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES] = { +- /* 0 --> gamma 1/1.8 */ +- { 0x65, 0x66002F, 0x950025, 0xBB0020, 0xDB001D, 0xF8001A, +- 0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012, +- 0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F, +- 0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E, +- 0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C, +- 0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B, +- 0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A, +- 0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A, +- 0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A, +- 0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009, +- 0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 }, +- +- /* 1 --> gamma 1/2 */ +- { 0x7F, 0x800034, 0xB50028, 0xDE0021, 0x100001E, 0x11E001B, +- 0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013, +- 0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F, +- 0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D, +- 0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B, +- 0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A, +- 0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A, +- 0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009, +- 0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009, +- 0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009, +- 0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 }, +- +- /* 2 --> gamma 1/2.2 */ +- { 0x99, 0x9B0038, 0xD4002A, 0xFF0023, 0x122001F, 0x141001B, +- 0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012, +- 0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F, +- 0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C, +- 0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B, +- 0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A, +- 0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009, +- 0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009, +- 0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008, +- 0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007, +- 0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 }, +-}; +- + #define ISC_IS_FORMAT_RAW(mbus_code) \ + (((mbus_code) & 0xf000) == 0x3000) + +@@ -691,7 +649,7 @@ static void isc_set_pipeline(struct isc_ + + regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL); + +- gamma = &isc_gamma_table[ctrls->gamma_index][0]; ++ gamma = &isc->gamma_table[ctrls->gamma_index][0]; + regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES); + regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); + regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); +@@ -2085,7 +2043,8 @@ static int isc_ctrl_init(struct isc_devi + + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); +- v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, GAMMA_MAX, 1, 2); ++ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, ++ isc->gamma_max); + isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, + V4L2_CID_AUTO_WHITE_BALANCE, + 0, 1, 1, 1); +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -186,6 +186,10 @@ struct isc_ctrls { + * + * @current_subdev: current subdevice: the sensor + * @subdev_entities: list of subdevice entitites ++ * ++ * @gamma_table: pointer to the table with gamma values, has ++ * gamma_max sets of GAMMA_ENTRIES entries each ++ * @gamma_max: maximum number of sets of inside the gamma_table + */ + struct isc_device { + struct regmap *regmap; +@@ -244,16 +248,17 @@ struct isc_device { + struct v4l2_ctrl *gr_off_ctrl; + struct v4l2_ctrl *gb_off_ctrl; + }; +-}; + +-#define GAMMA_MAX 2 + #define GAMMA_ENTRIES 64 ++ /* pointer to the defined gamma table */ ++ const u32 (*gamma_table)[GAMMA_ENTRIES]; ++ u32 gamma_max; ++}; + + #define ATMEL_ISC_NAME "atmel-isc" + + extern struct isc_format formats_list[]; + extern const struct isc_format controller_formats[]; +-extern const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES]; + extern const struct regmap_config isc_regmap_config; + extern const struct v4l2_async_notifier_operations isc_async_ops; + +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -54,6 +54,48 @@ + + #define ISC_CLK_MAX_DIV 255 + ++/* Gamma table with gamma 1/2.2 */ ++static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { ++ /* 0 --> gamma 1/1.8 */ ++ { 0x65, 0x66002F, 0x950025, 0xBB0020, 0xDB001D, 0xF8001A, ++ 0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012, ++ 0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F, ++ 0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E, ++ 0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C, ++ 0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B, ++ 0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A, ++ 0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A, ++ 0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A, ++ 0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009, ++ 0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 }, ++ ++ /* 1 --> gamma 1/2 */ ++ { 0x7F, 0x800034, 0xB50028, 0xDE0021, 0x100001E, 0x11E001B, ++ 0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013, ++ 0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F, ++ 0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D, ++ 0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B, ++ 0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A, ++ 0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A, ++ 0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009, ++ 0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009, ++ 0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009, ++ 0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 }, ++ ++ /* 2 --> gamma 1/2.2 */ ++ { 0x99, 0x9B0038, 0xD4002A, 0xFF0023, 0x122001F, 0x141001B, ++ 0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012, ++ 0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F, ++ 0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C, ++ 0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B, ++ 0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A, ++ 0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009, ++ 0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009, ++ 0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008, ++ 0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007, ++ 0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 }, ++}; ++ + static int isc_parse_dt(struct device *dev, struct isc_device *isc) + { + struct device_node *np = dev->of_node; +@@ -171,6 +213,9 @@ static int atmel_isc_probe(struct platfo + return ret; + } + ++ isc->gamma_table = isc_sama5d2_gamma_table; ++ isc->gamma_max = 2; ++ + ret = isc_pipeline_init(isc); + if (ret) + return ret; diff --git a/target/linux/at91/patches-5.15/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch b/target/linux/at91/patches-5.15/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch new file mode 100644 index 0000000000..5fd7be8098 --- /dev/null +++ b/target/linux/at91/patches-5.15/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch @@ -0,0 +1,70 @@ +From 0576e163d93d08a1ed112bd23f40478ef3fd323d Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:00 +0200 +Subject: [PATCH 158/247] media: atmel: atmel-isc: specialize driver name + constant + +The driver name constant must defined based on product driver, thus moving +the constant directly where it's required. This will allow each ISC based +product to define it's own name. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- + drivers/media/platform/atmel/atmel-isc.h | 2 -- + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 4 ++-- + 3 files changed, 4 insertions(+), 6 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -909,7 +909,7 @@ static int isc_querycap(struct file *fil + { + struct isc_device *isc = video_drvdata(file); + +- strscpy(cap->driver, ATMEL_ISC_NAME, sizeof(cap->driver)); ++ strscpy(cap->driver, "microchip-isc", sizeof(cap->driver)); + strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card)); + snprintf(cap->bus_info, sizeof(cap->bus_info), + "platform:%s", isc->v4l2_dev.name); +@@ -2261,7 +2261,7 @@ static int isc_async_complete(struct v4l + } + + /* Register video device */ +- strscpy(vdev->name, ATMEL_ISC_NAME, sizeof(vdev->name)); ++ strscpy(vdev->name, "microchip-isc", sizeof(vdev->name)); + vdev->release = video_device_release_empty; + vdev->fops = &isc_fops; + vdev->ioctl_ops = &isc_ioctl_ops; +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -255,8 +255,6 @@ struct isc_device { + u32 gamma_max; + }; + +-#define ATMEL_ISC_NAME "atmel-isc" +- + extern struct isc_format formats_list[]; + extern const struct isc_format controller_formats[]; + extern const struct regmap_config isc_regmap_config; +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -206,7 +206,7 @@ static int atmel_isc_probe(struct platfo + return irq; + + ret = devm_request_irq(dev, irq, isc_interrupt, 0, +- ATMEL_ISC_NAME, isc); ++ "atmel-sama5d2-isc", isc); + if (ret < 0) { + dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", + irq, ret); +@@ -378,7 +378,7 @@ static struct platform_driver atmel_isc_ + .probe = atmel_isc_probe, + .remove = atmel_isc_remove, + .driver = { +- .name = ATMEL_ISC_NAME, ++ .name = "atmel-sama5d2-isc", + .pm = &atmel_isc_dev_pm_ops, + .of_match_table = of_match_ptr(atmel_isc_of_match), + }, diff --git a/target/linux/at91/patches-5.15/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch b/target/linux/at91/patches-5.15/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch new file mode 100644 index 0000000000..c6ca456a56 --- /dev/null +++ b/target/linux/at91/patches-5.15/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch @@ -0,0 +1,45 @@ +From de8fa25cdf3726c83ac0d7b3b1e28bcb6334aadd Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:01 +0200 +Subject: [PATCH 159/247] media: atmel: atmel-isc: add checks for limiting + frame sizes + +When calling the subdev, certain subdev drivers will overwrite the +frame size and adding sizes which are beyond the ISC's capabilities. +Thus we need to ensure the frame size is cropped to the maximum caps. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -1338,6 +1338,12 @@ static int isc_try_fmt(struct isc_device + + v4l2_fill_pix_format(pixfmt, &format.format); + ++ /* Limit to Atmel ISC hardware capabilities */ ++ if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) ++ pixfmt->width = ISC_MAX_SUPPORT_WIDTH; ++ if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) ++ pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; ++ + pixfmt->field = V4L2_FIELD_NONE; + pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3; + pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height; +@@ -1373,6 +1379,12 @@ static int isc_set_fmt(struct isc_device + if (ret < 0) + return ret; + ++ /* Limit to Atmel ISC hardware capabilities */ ++ if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) ++ pixfmt->width = ISC_MAX_SUPPORT_WIDTH; ++ if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) ++ pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; ++ + isc->fmt = *f; + + if (isc->try_config.sd_format && isc->config.sd_format && diff --git a/target/linux/at91/patches-5.15/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch b/target/linux/at91/patches-5.15/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch new file mode 100644 index 0000000000..afa89ed916 --- /dev/null +++ b/target/linux/at91/patches-5.15/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch @@ -0,0 +1,131 @@ +From b51819e17260af2ecc152b7dcd61e63bcaa35edf Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:02 +0200 +Subject: [PATCH 160/247] media: atmel: atmel-isc: specialize max width and max + height + +Move the max width and max height constants to the product specific driver +and have them in the device struct. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 28 +++++++++---------- + drivers/media/platform/atmel/atmel-isc.h | 9 ++++-- + .../media/platform/atmel/atmel-sama5d2-isc.c | 7 +++-- + 3 files changed, 25 insertions(+), 19 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -1216,8 +1216,8 @@ static void isc_try_fse(struct isc_devic + * just use the maximum ISC can receive. + */ + if (ret) { +- pad_cfg->try_crop.width = ISC_MAX_SUPPORT_WIDTH; +- pad_cfg->try_crop.height = ISC_MAX_SUPPORT_HEIGHT; ++ pad_cfg->try_crop.width = isc->max_width; ++ pad_cfg->try_crop.height = isc->max_height; + } else { + pad_cfg->try_crop.width = fse.max_width; + pad_cfg->try_crop.height = fse.max_height; +@@ -1294,10 +1294,10 @@ static int isc_try_fmt(struct isc_device + isc->try_config.sd_format = sd_fmt; + + /* Limit to Atmel ISC hardware capabilities */ +- if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) +- pixfmt->width = ISC_MAX_SUPPORT_WIDTH; +- if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) +- pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; ++ if (pixfmt->width > isc->max_width) ++ pixfmt->width = isc->max_width; ++ if (pixfmt->height > isc->max_height) ++ pixfmt->height = isc->max_height; + + /* + * The mbus format is the one the subdev outputs. +@@ -1339,10 +1339,10 @@ static int isc_try_fmt(struct isc_device + v4l2_fill_pix_format(pixfmt, &format.format); + + /* Limit to Atmel ISC hardware capabilities */ +- if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) +- pixfmt->width = ISC_MAX_SUPPORT_WIDTH; +- if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) +- pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; ++ if (pixfmt->width > isc->max_width) ++ pixfmt->width = isc->max_width; ++ if (pixfmt->height > isc->max_height) ++ pixfmt->height = isc->max_height; + + pixfmt->field = V4L2_FIELD_NONE; + pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3; +@@ -1380,10 +1380,10 @@ static int isc_set_fmt(struct isc_device + return ret; + + /* Limit to Atmel ISC hardware capabilities */ +- if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) +- pixfmt->width = ISC_MAX_SUPPORT_WIDTH; +- if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) +- pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; ++ if (f->fmt.pix.width > isc->max_width) ++ f->fmt.pix.width = isc->max_width; ++ if (f->fmt.pix.height > isc->max_height) ++ f->fmt.pix.height = isc->max_height; + + isc->fmt = *f; + +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -10,9 +10,6 @@ + */ + #ifndef _ATMEL_ISC_H_ + +-#define ISC_MAX_SUPPORT_WIDTH 2592 +-#define ISC_MAX_SUPPORT_HEIGHT 1944 +- + #define ISC_CLK_MAX_DIV 255 + + enum isc_clk_id { +@@ -190,6 +187,9 @@ struct isc_ctrls { + * @gamma_table: pointer to the table with gamma values, has + * gamma_max sets of GAMMA_ENTRIES entries each + * @gamma_max: maximum number of sets of inside the gamma_table ++ * ++ * @max_width: maximum frame width, dependent on the internal RAM ++ * @max_height: maximum frame height, dependent on the internal RAM + */ + struct isc_device { + struct regmap *regmap; +@@ -253,6 +253,9 @@ struct isc_device { + /* pointer to the defined gamma table */ + const u32 (*gamma_table)[GAMMA_ENTRIES]; + u32 gamma_max; ++ ++ u32 max_width; ++ u32 max_height; + }; + + extern struct isc_format formats_list[]; +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -49,8 +49,8 @@ + #include "atmel-isc-regs.h" + #include "atmel-isc.h" + +-#define ISC_MAX_SUPPORT_WIDTH 2592 +-#define ISC_MAX_SUPPORT_HEIGHT 1944 ++#define ISC_SAMA5D2_MAX_SUPPORT_WIDTH 2592 ++#define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT 1944 + + #define ISC_CLK_MAX_DIV 255 + +@@ -216,6 +216,9 @@ static int atmel_isc_probe(struct platfo + isc->gamma_table = isc_sama5d2_gamma_table; + isc->gamma_max = 2; + ++ isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; ++ isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; ++ + ret = isc_pipeline_init(isc); + if (ret) + return ret; diff --git a/target/linux/at91/patches-5.15/161-media-atmel-atmel-isc-specialize-dma-cfg.patch b/target/linux/at91/patches-5.15/161-media-atmel-atmel-isc-specialize-dma-cfg.patch new file mode 100644 index 0000000000..410831771e --- /dev/null +++ b/target/linux/at91/patches-5.15/161-media-atmel-atmel-isc-specialize-dma-cfg.patch @@ -0,0 +1,60 @@ +From c42305f52560a1be6fc25a2f23579c7b323de654 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:03 +0200 +Subject: [PATCH 161/247] media: atmel: atmel-isc: specialize dma cfg + +The dma configuration (DCFG) is specific to the product. +Move this configuration in the product specific driver, and add the +field inside the driver struct. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 3 +-- + drivers/media/platform/atmel/atmel-isc.h | 2 ++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 3 +++ + 3 files changed, 6 insertions(+), 2 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -724,8 +724,7 @@ static int isc_configure(struct isc_devi + rlp_mode = isc->config.rlp_cfg_mode; + pipeline = isc->config.bits_pipeline; + +- dcfg = isc->config.dcfg_imode | +- ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; ++ dcfg = isc->config.dcfg_imode | isc->dcfg; + + pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE; + mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW | +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -149,6 +149,7 @@ struct isc_ctrls { + * @hclock: Hclock clock input (refer datasheet) + * @ispck: iscpck clock (refer datasheet) + * @isc_clks: ISC clocks ++ * @dcfg: DMA master configuration, architecture dependent + * + * @dev: Registered device driver + * @v4l2_dev: v4l2 registered device +@@ -196,6 +197,7 @@ struct isc_device { + struct clk *hclock; + struct clk *ispck; + struct isc_clk isc_clks[2]; ++ u32 dcfg; + + struct device *dev; + struct v4l2_device v4l2_dev; +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -219,6 +219,9 @@ static int atmel_isc_probe(struct platfo + isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; + isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; + ++ /* sama5d2-isc - 8 bits per beat */ ++ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; ++ + ret = isc_pipeline_init(isc); + if (ret) + return ret; diff --git a/target/linux/at91/patches-5.15/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch b/target/linux/at91/patches-5.15/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch new file mode 100644 index 0000000000..7b8e8ed697 --- /dev/null +++ b/target/linux/at91/patches-5.15/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch @@ -0,0 +1,94 @@ +From 6ccda3cf6a102ac4f6e21386d0dd0fedfb066525 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:04 +0200 +Subject: [PATCH 162/247] media: atmel: atmel-isc: extract CSC submodule config + into separate function + +The CSC submodule is a part of the atmel-isc pipeline, and stands for +Color Space Conversion. It is used to apply a matrix transformation to +RGB pixels to convert them to the YUV components. +The CSC submodule should be initialized in the product specific driver +as it's product specific. Other products can implement it differently. + +[hverkuil: made isc_sama5d2_config_csc static] + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 8 +------- + drivers/media/platform/atmel/atmel-isc.h | 7 +++++++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 15 +++++++++++++++ + 3 files changed, 23 insertions(+), 7 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -654,13 +654,7 @@ static void isc_set_pipeline(struct isc_ + regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); + regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); + +- /* Convert RGB to YUV */ +- regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16)); +- regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16)); +- regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16)); +- regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16)); +- regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16)); +- regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16)); ++ isc->config_csc(isc); + + regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness); + regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast); +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -191,6 +191,9 @@ struct isc_ctrls { + * + * @max_width: maximum frame width, dependent on the internal RAM + * @max_height: maximum frame height, dependent on the internal RAM ++ * ++ * @config_csc: pointer to a function that initializes product ++ * specific CSC module + */ + struct isc_device { + struct regmap *regmap; +@@ -258,6 +261,10 @@ struct isc_device { + + u32 max_width; + u32 max_height; ++ ++ struct { ++ void (*config_csc)(struct isc_device *isc); ++ }; + }; + + extern struct isc_format formats_list[]; +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -54,6 +54,19 @@ + + #define ISC_CLK_MAX_DIV 255 + ++static void isc_sama5d2_config_csc(struct isc_device *isc) ++{ ++ struct regmap *regmap = isc->regmap; ++ ++ /* Convert RGB to YUV */ ++ regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16)); ++ regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16)); ++ regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16)); ++ regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16)); ++ regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16)); ++ regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16)); ++} ++ + /* Gamma table with gamma 1/2.2 */ + static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { + /* 0 --> gamma 1/1.8 */ +@@ -219,6 +232,8 @@ static int atmel_isc_probe(struct platfo + isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; + isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; + ++ isc->config_csc = isc_sama5d2_config_csc; ++ + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; + diff --git a/target/linux/at91/patches-5.15/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch b/target/linux/at91/patches-5.15/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch new file mode 100644 index 0000000000..832465363b --- /dev/null +++ b/target/linux/at91/patches-5.15/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch @@ -0,0 +1,28 @@ +From 19dd7c72c6c457c147133a7dad8ab28d35538f99 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:05 +0200 +Subject: [PATCH 163/247] media: atmel: atmel-isc-base: add id to clock debug + message + +Add the clock id to the debug message regarding clock setup + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -281,8 +281,8 @@ static int isc_clk_enable(struct clk_hw + unsigned long flags; + unsigned int status; + +- dev_dbg(isc_clk->dev, "ISC CLK: %s, div = %d, parent id = %d\n", +- __func__, isc_clk->div, isc_clk->parent_id); ++ dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n", ++ __func__, id, isc_clk->div, isc_clk->parent_id); + + spin_lock_irqsave(&isc_clk->lock, flags); + regmap_update_bits(regmap, ISC_CLKCFG, diff --git a/target/linux/at91/patches-5.15/164-media-atmel-atmel-isc-create-register-offsets-struct.patch b/target/linux/at91/patches-5.15/164-media-atmel-atmel-isc-create-register-offsets-struct.patch new file mode 100644 index 0000000000..bb599618d1 --- /dev/null +++ b/target/linux/at91/patches-5.15/164-media-atmel-atmel-isc-create-register-offsets-struct.patch @@ -0,0 +1,115 @@ +From 7a1b082cd81a2496e2687cee7ea1ef04a3020f48 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:06 +0200 +Subject: [PATCH 164/247] media: atmel: atmel-isc: create register offsets + struct + +Create a struct that holds register offsets that are product specific. +Add initially the CSC register. +This allows each product that contains a variant of the ISC to add their +own register offset. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 2 +- + drivers/media/platform/atmel/atmel-isc-regs.h | 3 +++ + drivers/media/platform/atmel/atmel-isc.h | 12 +++++++++++ + .../media/platform/atmel/atmel-sama5d2-isc.c | 20 +++++++++++++------ + 4 files changed, 30 insertions(+), 7 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -2326,7 +2326,7 @@ int isc_pipeline_init(struct isc_device + REG_FIELD(ISC_GAM_CTRL, 1, 1), + REG_FIELD(ISC_GAM_CTRL, 2, 2), + REG_FIELD(ISC_GAM_CTRL, 3, 3), +- REG_FIELD(ISC_CSC_CTRL, 0, 0), ++ REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), + REG_FIELD(ISC_CBC_CTRL, 0, 0), + REG_FIELD(ISC_SUB422_CTRL, 0, 0), + REG_FIELD(ISC_SUB420_CTRL, 0, 0), +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -153,6 +153,9 @@ + /* ISC_Gamma Correction Green Entry Register */ + #define ISC_GAM_RENTRY 0x00000298 + ++/* Offset for CSC register specific to sama5d2 product */ ++#define ISC_SAMA5D2_CSC_OFFSET 0 ++ + /* Color Space Conversion Control Register */ + #define ISC_CSC_CTRL 0x00000398 + +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -144,6 +144,14 @@ struct isc_ctrls { + #define ISC_PIPE_LINE_NODE_NUM 11 + + /* ++ * struct isc_reg_offsets - ISC device register offsets ++ * @csc: Offset for the CSC register ++ */ ++struct isc_reg_offsets { ++ u32 csc; ++}; ++ ++/* + * struct isc_device - ISC device driver data/config struct + * @regmap: Register map + * @hclock: Hclock clock input (refer datasheet) +@@ -194,6 +202,8 @@ struct isc_ctrls { + * + * @config_csc: pointer to a function that initializes product + * specific CSC module ++ * ++ * @offsets: struct holding the product specific register offsets + */ + struct isc_device { + struct regmap *regmap; +@@ -265,6 +275,8 @@ struct isc_device { + struct { + void (*config_csc)(struct isc_device *isc); + }; ++ ++ struct isc_reg_offsets offsets; + }; + + extern struct isc_format formats_list[]; +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -59,12 +59,18 @@ static void isc_sama5d2_config_csc(struc + struct regmap *regmap = isc->regmap; + + /* Convert RGB to YUV */ +- regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16)); +- regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16)); +- regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16)); +- regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16)); +- regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16)); +- regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16)); ++ regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, ++ 0x42 | (0x81 << 16)); ++ regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, ++ 0x19 | (0x10 << 16)); ++ regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, ++ 0xFDA | (0xFB6 << 16)); ++ regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, ++ 0x70 | (0x80 << 16)); ++ regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, ++ 0x70 | (0xFA2 << 16)); ++ regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, ++ 0xFEE | (0x80 << 16)); + } + + /* Gamma table with gamma 1/2.2 */ +@@ -234,6 +240,8 @@ static int atmel_isc_probe(struct platfo + + isc->config_csc = isc_sama5d2_config_csc; + ++ isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; ++ + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; + diff --git a/target/linux/at91/patches-5.15/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch b/target/linux/at91/patches-5.15/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch new file mode 100644 index 0000000000..fd7ed1e94d --- /dev/null +++ b/target/linux/at91/patches-5.15/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch @@ -0,0 +1,80 @@ +From aa31e58d80d233385fa3b972e6b85f293e2a9093 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:07 +0200 +Subject: [PATCH 165/247] media: atmel: atmel-isc: extract CBC submodule config + into separate function + +The CBC submodule is a part of the atmel-isc pipeline, and stands for +Contrast Brightness Control. It is used to apply gains and offsets to the +luma (Y) and chroma (U, V) components of the YUV elements. +The CBC submodule should be initialized in the product specific driver +as it's product specific. Other products can implement it differently + +[hverkuil: made isc_sama5d2_config_cbc static] + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 4 +--- + drivers/media/platform/atmel/atmel-isc.h | 3 +++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 9 +++++++++ + 3 files changed, 13 insertions(+), 3 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -655,9 +655,7 @@ static void isc_set_pipeline(struct isc_ + regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); + + isc->config_csc(isc); +- +- regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness); +- regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast); ++ isc->config_cbc(isc); + } + + static int isc_update_profile(struct isc_device *isc) +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -202,6 +202,8 @@ struct isc_reg_offsets { + * + * @config_csc: pointer to a function that initializes product + * specific CSC module ++ * @config_cbc: pointer to a function that initializes product ++ * specific CBC module + * + * @offsets: struct holding the product specific register offsets + */ +@@ -274,6 +276,7 @@ struct isc_device { + + struct { + void (*config_csc)(struct isc_device *isc); ++ void (*config_cbc)(struct isc_device *isc); + }; + + struct isc_reg_offsets offsets; +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -73,6 +73,14 @@ static void isc_sama5d2_config_csc(struc + 0xFEE | (0x80 << 16)); + } + ++static void isc_sama5d2_config_cbc(struct isc_device *isc) ++{ ++ struct regmap *regmap = isc->regmap; ++ ++ regmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness); ++ regmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast); ++} ++ + /* Gamma table with gamma 1/2.2 */ + static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { + /* 0 --> gamma 1/1.8 */ +@@ -239,6 +247,7 @@ static int atmel_isc_probe(struct platfo + isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; + + isc->config_csc = isc_sama5d2_config_csc; ++ isc->config_cbc = isc_sama5d2_config_cbc; + + isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; + diff --git a/target/linux/at91/patches-5.15/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch b/target/linux/at91/patches-5.15/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch new file mode 100644 index 0000000000..51659f54a4 --- /dev/null +++ b/target/linux/at91/patches-5.15/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch @@ -0,0 +1,82 @@ +From 52e4b779ae1af3e322d0c673375dcd51315739d4 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:08 +0200 +Subject: [PATCH 166/247] media: atmel: atmel-isc: add CBC to the reg offsets + struct + +The CBC submodule is a part of the atmel-isc pipeline, and stands for +Contrast Brightness Control. It is used to apply gains and offsets to the +luma (Y) and chroma (U, V) components of the YUV elements. +Add cbc to the reg offsets struct. This will allow different products +to have a different reg offset for this particular module. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 2 +- + drivers/media/platform/atmel/atmel-isc-regs.h | 3 +++ + drivers/media/platform/atmel/atmel-isc.h | 2 ++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 7 +++++-- + 4 files changed, 11 insertions(+), 3 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -2325,7 +2325,7 @@ int isc_pipeline_init(struct isc_device + REG_FIELD(ISC_GAM_CTRL, 2, 2), + REG_FIELD(ISC_GAM_CTRL, 3, 3), + REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), +- REG_FIELD(ISC_CBC_CTRL, 0, 0), ++ REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), + REG_FIELD(ISC_SUB422_CTRL, 0, 0), + REG_FIELD(ISC_SUB420_CTRL, 0, 0), + }; +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -177,6 +177,9 @@ + /* Color Space Conversion CRB OCR Register */ + #define ISC_CSC_CRB_OCR 0x000003b0 + ++/* Offset for CBC register specific to sama5d2 product */ ++#define ISC_SAMA5D2_CBC_OFFSET 0 ++ + /* Contrast And Brightness Control Register */ + #define ISC_CBC_CTRL 0x000003b4 + +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -146,9 +146,11 @@ struct isc_ctrls { + /* + * struct isc_reg_offsets - ISC device register offsets + * @csc: Offset for the CSC register ++ * @cbc: Offset for the CBC register + */ + struct isc_reg_offsets { + u32 csc; ++ u32 cbc; + }; + + /* +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -77,8 +77,10 @@ static void isc_sama5d2_config_cbc(struc + { + struct regmap *regmap = isc->regmap; + +- regmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness); +- regmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast); ++ regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, ++ isc->ctrls.brightness); ++ regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, ++ isc->ctrls.contrast); + } + + /* Gamma table with gamma 1/2.2 */ +@@ -250,6 +252,7 @@ static int atmel_isc_probe(struct platfo + isc->config_cbc = isc_sama5d2_config_cbc; + + isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; ++ isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; + + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.15/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch b/target/linux/at91/patches-5.15/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch new file mode 100644 index 0000000000..6d937fdeb7 --- /dev/null +++ b/target/linux/at91/patches-5.15/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch @@ -0,0 +1,80 @@ +From aebb741058a63c3493f4139d11d6f290d5691e9b Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:09 +0200 +Subject: [PATCH 167/247] media: atmel: atmel-isc: add SUB422 and SUB420 to + register offsets + +The SUB submodules are a part of the atmel-isc pipeline, and stand for +Subsampling. They are used to subsample the original YUV 4:4:4 pixel ratio +aspect to either 4:2:2 or 4:2:0. +Add sub420 and sub422 to the reg offsets struct. +This will allow different products to have a different reg offset for these +particular modules. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- + drivers/media/platform/atmel/atmel-isc-regs.h | 4 ++++ + drivers/media/platform/atmel/atmel-isc.h | 4 ++++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 ++ + 4 files changed, 12 insertions(+), 2 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -2326,8 +2326,8 @@ int isc_pipeline_init(struct isc_device + REG_FIELD(ISC_GAM_CTRL, 3, 3), + REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), + REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), +- REG_FIELD(ISC_SUB422_CTRL, 0, 0), +- REG_FIELD(ISC_SUB420_CTRL, 0, 0), ++ REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0), ++ REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0), + }; + + for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) { +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -194,9 +194,13 @@ + #define ISC_CBC_CONTRAST 0x000003c0 + #define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) + ++/* Offset for SUB422 register specific to sama5d2 product */ ++#define ISC_SAMA5D2_SUB422_OFFSET 0 + /* Subsampling 4:4:4 to 4:2:2 Control Register */ + #define ISC_SUB422_CTRL 0x000003c4 + ++/* Offset for SUB420 register specific to sama5d2 product */ ++#define ISC_SAMA5D2_SUB420_OFFSET 0 + /* Subsampling 4:2:2 to 4:2:0 Control Register */ + #define ISC_SUB420_CTRL 0x000003cc + +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -147,10 +147,14 @@ struct isc_ctrls { + * struct isc_reg_offsets - ISC device register offsets + * @csc: Offset for the CSC register + * @cbc: Offset for the CBC register ++ * @sub422: Offset for the SUB422 register ++ * @sub420: Offset for the SUB420 register + */ + struct isc_reg_offsets { + u32 csc; + u32 cbc; ++ u32 sub422; ++ u32 sub420; + }; + + /* +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -253,6 +253,8 @@ static int atmel_isc_probe(struct platfo + + isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; + isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; ++ isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; ++ isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; + + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.15/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch b/target/linux/at91/patches-5.15/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch new file mode 100644 index 0000000000..050e2816c0 --- /dev/null +++ b/target/linux/at91/patches-5.15/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch @@ -0,0 +1,74 @@ +From b432a8b0fc88de5b49236482053d8d372c68ee55 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:10 +0200 +Subject: [PATCH 168/247] media: atmel: atmel-isc: add RLP to register offsets + +The RLP submodule is a part of the atmel-isc pipeline, and stands for +Rounding,Limiting and Packaging. It used to extract specific data from the +ISC pipeline. For example if we want to output greyscale 8 bit, we would +use limiting to 8 bits, and packaging to Luma component only. +Add rlp to the reg offsets struct. +This will allow different products to have a different reg offset for this +particular module. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- + drivers/media/platform/atmel/atmel-isc-regs.h | 2 ++ + drivers/media/platform/atmel/atmel-isc.h | 2 ++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 + + 4 files changed, 7 insertions(+), 2 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -726,8 +726,8 @@ static int isc_configure(struct isc_devi + + regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); + +- regmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK, +- rlp_mode); ++ regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, ++ ISC_RLP_CFG_MODE_MASK, rlp_mode); + + regmap_write(regmap, ISC_DCFG, dcfg); + +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -204,6 +204,8 @@ + /* Subsampling 4:2:2 to 4:2:0 Control Register */ + #define ISC_SUB420_CTRL 0x000003cc + ++/* Offset for RLP register specific to sama5d2 product */ ++#define ISC_SAMA5D2_RLP_OFFSET 0 + /* Rounding, Limiting and Packing Configuration Register */ + #define ISC_RLP_CFG 0x000003d0 + +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -149,12 +149,14 @@ struct isc_ctrls { + * @cbc: Offset for the CBC register + * @sub422: Offset for the SUB422 register + * @sub420: Offset for the SUB420 register ++ * @rlp: Offset for the RLP register + */ + struct isc_reg_offsets { + u32 csc; + u32 cbc; + u32 sub422; + u32 sub420; ++ u32 rlp; + }; + + /* +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -255,6 +255,7 @@ static int atmel_isc_probe(struct platfo + isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; + isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; + isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; ++ isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; + + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.15/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch b/target/linux/at91/patches-5.15/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch new file mode 100644 index 0000000000..6ce49e67ff --- /dev/null +++ b/target/linux/at91/patches-5.15/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch @@ -0,0 +1,99 @@ +From 8c19aa14b8303a0e7c4bae42f3f00f9a2a65b0db Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:11 +0200 +Subject: [PATCH 169/247] media: atmel: atmel-isc: add HIS to register offsets + +The HIS submodule is a part of the atmel-isc pipeline, and stands for +Histogram. This module performs a color histogram that can be read and used +by the main processor. +Add his to the reg offsets struct. +This will allow different products to have a different reg offset for this +particular module. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 11 +++++++---- + drivers/media/platform/atmel/atmel-isc-regs.h | 2 ++ + drivers/media/platform/atmel/atmel-isc.h | 2 ++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 + + 4 files changed, 12 insertions(+), 4 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -686,12 +686,13 @@ static void isc_set_histogram(struct isc + struct isc_ctrls *ctrls = &isc->ctrls; + + if (enable) { +- regmap_write(regmap, ISC_HIS_CFG, ++ regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, + ISC_HIS_CFG_MODE_GR | + (isc->config.sd_format->cfa_baycfg + << ISC_HIS_CFG_BAYSEL_SHIFT) | + ISC_HIS_CFG_RAR); +- regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN); ++ regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, ++ ISC_HIS_CTRL_EN); + regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE); + ctrls->hist_id = ISC_HIS_CFG_MODE_GR; + isc_update_profile(isc); +@@ -700,7 +701,8 @@ static void isc_set_histogram(struct isc + ctrls->hist_stat = HIST_ENABLED; + } else { + regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE); +- regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_DIS); ++ regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, ++ ISC_HIS_CTRL_DIS); + + ctrls->hist_stat = HIST_DISABLED; + } +@@ -1836,7 +1838,8 @@ static void isc_awb_work(struct work_str + ctrls->awb = ISC_WB_NONE; + } + } +- regmap_write(regmap, ISC_HIS_CFG, hist_id | baysel | ISC_HIS_CFG_RAR); ++ regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, ++ hist_id | baysel | ISC_HIS_CFG_RAR); + isc_update_profile(isc); + /* if awb has been disabled, we don't need to start another histogram */ + if (ctrls->awb) +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -224,6 +224,8 @@ + #define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc + #define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) + ++/* Offset for HIS register specific to sama5d2 product */ ++#define ISC_SAMA5D2_HIS_OFFSET 0 + /* Histogram Control Register */ + #define ISC_HIS_CTRL 0x000003d4 + +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -150,6 +150,7 @@ struct isc_ctrls { + * @sub422: Offset for the SUB422 register + * @sub420: Offset for the SUB420 register + * @rlp: Offset for the RLP register ++ * @his: Offset for the HIS related registers + */ + struct isc_reg_offsets { + u32 csc; +@@ -157,6 +158,7 @@ struct isc_reg_offsets { + u32 sub422; + u32 sub420; + u32 rlp; ++ u32 his; + }; + + /* +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -256,6 +256,7 @@ static int atmel_isc_probe(struct platfo + isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; + isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; + isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; ++ isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; + + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.15/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch b/target/linux/at91/patches-5.15/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch new file mode 100644 index 0000000000..ef7104e587 --- /dev/null +++ b/target/linux/at91/patches-5.15/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch @@ -0,0 +1,110 @@ +From 7173e54070a9b530c8c16e0a507be71385133abd Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:12 +0200 +Subject: [PATCH 170/247] media: atmel: atmel-isc: add DMA to register offsets + +The DMA submodule is a part of the atmel-isc pipeline, and stands for +Direct Memory Access. It acts like a master on the AXI bus of the SoC, and +can directly write the RAM area with the pixel data from the ISC internal +sram. +Add dma to the reg offsets struct. +This will allow different products to have a different reg offset for this +particular module. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 19 ++++++++++++------- + drivers/media/platform/atmel/atmel-isc-regs.h | 3 +++ + drivers/media/platform/atmel/atmel-isc.h | 2 ++ + .../media/platform/atmel/atmel-sama5d2-isc.c | 1 + + 4 files changed, 18 insertions(+), 7 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -601,16 +601,20 @@ static void isc_start_dma(struct isc_dev + ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN); + + addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0); +- regmap_write(regmap, ISC_DAD0, addr0); ++ regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0); + + switch (isc->config.fourcc) { + case V4L2_PIX_FMT_YUV420: +- regmap_write(regmap, ISC_DAD1, addr0 + (sizeimage * 2) / 3); +- regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 5) / 6); ++ regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, ++ addr0 + (sizeimage * 2) / 3); ++ regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, ++ addr0 + (sizeimage * 5) / 6); + break; + case V4L2_PIX_FMT_YUV422P: +- regmap_write(regmap, ISC_DAD1, addr0 + sizeimage / 2); +- regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 3) / 4); ++ regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, ++ addr0 + sizeimage / 2); ++ regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, ++ addr0 + (sizeimage * 3) / 4); + break; + default: + break; +@@ -618,7 +622,8 @@ static void isc_start_dma(struct isc_dev + + dctrl_dview = isc->config.dctrl_dview; + +- regmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS); ++ regmap_write(regmap, ISC_DCTRL + isc->offsets.dma, ++ dctrl_dview | ISC_DCTRL_IE_IS); + spin_lock(&isc->awb_lock); + regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE); + spin_unlock(&isc->awb_lock); +@@ -731,7 +736,7 @@ static int isc_configure(struct isc_devi + regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, + ISC_RLP_CFG_MODE_MASK, rlp_mode); + +- regmap_write(regmap, ISC_DCFG, dcfg); ++ regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); + + /* Set the pipeline */ + isc_set_pipeline(isc, pipeline); +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -247,6 +247,9 @@ + + #define ISC_HIS_CFG_RAR BIT(8) + ++/* Offset for DMA register specific to sama5d2 product */ ++#define ISC_SAMA5D2_DMA_OFFSET 0 ++ + /* DMA Configuration Register */ + #define ISC_DCFG 0x000003e0 + #define ISC_DCFG_IMODE_PACKED8 0x0 +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -151,6 +151,7 @@ struct isc_ctrls { + * @sub420: Offset for the SUB420 register + * @rlp: Offset for the RLP register + * @his: Offset for the HIS related registers ++ * @dma: Offset for the DMA related registers + */ + struct isc_reg_offsets { + u32 csc; +@@ -159,6 +160,7 @@ struct isc_reg_offsets { + u32 sub420; + u32 rlp; + u32 his; ++ u32 dma; + }; + + /* +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -257,6 +257,7 @@ static int atmel_isc_probe(struct platfo + isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; + isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; + isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; ++ isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; + + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.15/171-media-atmel-atmel-isc-add-support-for-version-regist.patch b/target/linux/at91/patches-5.15/171-media-atmel-atmel-isc-add-support-for-version-regist.patch new file mode 100644 index 0000000000..b582945b99 --- /dev/null +++ b/target/linux/at91/patches-5.15/171-media-atmel-atmel-isc-add-support-for-version-regist.patch @@ -0,0 +1,77 @@ +From 0939b0a92acca11a5a3b0de5dd70434e17e40ed3 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:13 +0200 +Subject: [PATCH 171/247] media: atmel: atmel-isc: add support for version + register + +Add support for version register and print it at probe time. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-regs.h | 5 +++++ + drivers/media/platform/atmel/atmel-isc.h | 2 ++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 5 +++++ + 3 files changed, 12 insertions(+) + +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -295,6 +295,11 @@ + /* DMA Address 2 Register */ + #define ISC_DAD2 0x000003fc + ++/* Offset for version register specific to sama5d2 product */ ++#define ISC_SAMA5D2_VERSION_OFFSET 0 ++/* Version Register */ ++#define ISC_VERSION 0x0000040c ++ + /* Histogram Entry */ + #define ISC_HIS_ENTRY 0x00000410 + +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -152,6 +152,7 @@ struct isc_ctrls { + * @rlp: Offset for the RLP register + * @his: Offset for the HIS related registers + * @dma: Offset for the DMA related registers ++ * @version: Offset for the version register + */ + struct isc_reg_offsets { + u32 csc; +@@ -161,6 +162,7 @@ struct isc_reg_offsets { + u32 rlp; + u32 his; + u32 dma; ++ u32 version; + }; + + /* +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -210,6 +210,7 @@ static int atmel_isc_probe(struct platfo + struct isc_subdev_entity *subdev_entity; + int irq; + int ret; ++ u32 ver; + + isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL); + if (!isc) +@@ -258,6 +259,7 @@ static int atmel_isc_probe(struct platfo + isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; + isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; + isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; ++ isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; + + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; +@@ -346,6 +348,9 @@ static int atmel_isc_probe(struct platfo + pm_runtime_enable(dev); + pm_request_idle(dev); + ++ regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); ++ dev_info(dev, "Microchip ISC version %x\n", ver); ++ + return 0; + + cleanup_subdev: diff --git a/target/linux/at91/patches-5.15/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch b/target/linux/at91/patches-5.15/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch new file mode 100644 index 0000000000..c48301cf25 --- /dev/null +++ b/target/linux/at91/patches-5.15/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch @@ -0,0 +1,71 @@ +From bce46a8a620a796ca3cfe5bff61baf6744074986 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:14 +0200 +Subject: [PATCH 172/247] media: atmel: atmel-isc: add his_entry to register + offsets + +Add his_entry to the reg offsets struct. +This will allow different products to have a different reg offset for this +particular module. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 3 ++- + drivers/media/platform/atmel/atmel-isc-regs.h | 2 ++ + drivers/media/platform/atmel/atmel-isc.h | 2 ++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 + + 4 files changed, 7 insertions(+), 1 deletion(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -1684,7 +1684,8 @@ static void isc_hist_count(struct isc_de + *min = 0; + *max = HIST_ENTRIES; + +- regmap_bulk_read(regmap, ISC_HIS_ENTRY, hist_entry, HIST_ENTRIES); ++ regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry, ++ hist_entry, HIST_ENTRIES); + + *hist_count = 0; + /* +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -300,6 +300,8 @@ + /* Version Register */ + #define ISC_VERSION 0x0000040c + ++/* Offset for version register specific to sama5d2 product */ ++#define ISC_SAMA5D2_HIS_ENTRY_OFFSET 0 + /* Histogram Entry */ + #define ISC_HIS_ENTRY 0x00000410 + +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -153,6 +153,7 @@ struct isc_ctrls { + * @his: Offset for the HIS related registers + * @dma: Offset for the DMA related registers + * @version: Offset for the version register ++ * @his_entry: Offset for the HIS entries registers + */ + struct isc_reg_offsets { + u32 csc; +@@ -163,6 +164,7 @@ struct isc_reg_offsets { + u32 his; + u32 dma; + u32 version; ++ u32 his_entry; + }; + + /* +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -260,6 +260,7 @@ static int atmel_isc_probe(struct platfo + isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; + isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; + isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; ++ isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET; + + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.15/173-media-atmel-atmel-isc-add-register-description-for-a.patch b/target/linux/at91/patches-5.15/173-media-atmel-atmel-isc-add-register-description-for-a.patch new file mode 100644 index 0000000000..f701ede09c --- /dev/null +++ b/target/linux/at91/patches-5.15/173-media-atmel-atmel-isc-add-register-description-for-a.patch @@ -0,0 +1,99 @@ +From 87b581b1197df5f77bd65819d0428f2404c6b764 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:15 +0200 +Subject: [PATCH 173/247] media: atmel: atmel-isc: add register description for + additional modules + +Add register description for additional pipeline modules: the +Defective Pixel Correction (DPC) and the Vertical and Horizontal Scaler(VHXS) + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-regs.h | 67 +++++++++++++++++++ + 1 file changed, 67 insertions(+) + +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -90,6 +90,46 @@ + #define ISC_INT_DDONE BIT(8) + #define ISC_INT_HISDONE BIT(12) + ++/* ISC DPC Control Register */ ++#define ISC_DPC_CTRL 0x40 ++ ++#define ISC_DPC_CTRL_DPCEN BIT(0) ++#define ISC_DPC_CTRL_GDCEN BIT(1) ++#define ISC_DPC_CTRL_BLCEN BIT(2) ++ ++/* ISC DPC Config Register */ ++#define ISC_DPC_CFG 0x44 ++ ++#define ISC_DPC_CFG_BAYSEL_SHIFT 0 ++ ++#define ISC_DPC_CFG_EITPOL BIT(4) ++ ++#define ISC_DPC_CFG_TA_ENABLE BIT(14) ++#define ISC_DPC_CFG_TC_ENABLE BIT(13) ++#define ISC_DPC_CFG_TM_ENABLE BIT(12) ++ ++#define ISC_DPC_CFG_RE_MODE BIT(17) ++ ++#define ISC_DPC_CFG_GDCCLP_SHIFT 20 ++#define ISC_DPC_CFG_GDCCLP_MASK GENMASK(22, 20) ++ ++#define ISC_DPC_CFG_BLOFF_SHIFT 24 ++#define ISC_DPC_CFG_BLOFF_MASK GENMASK(31, 24) ++ ++#define ISC_DPC_CFG_BAYCFG_SHIFT 0 ++#define ISC_DPC_CFG_BAYCFG_MASK GENMASK(1, 0) ++/* ISC DPC Threshold Median Register */ ++#define ISC_DPC_THRESHM 0x48 ++ ++/* ISC DPC Threshold Closest Register */ ++#define ISC_DPC_THRESHC 0x4C ++ ++/* ISC DPC Threshold Average Register */ ++#define ISC_DPC_THRESHA 0x50 ++ ++/* ISC DPC STatus Register */ ++#define ISC_DPC_SR 0x54 ++ + /* ISC White Balance Control Register */ + #define ISC_WB_CTRL 0x00000058 + +@@ -153,6 +193,33 @@ + /* ISC_Gamma Correction Green Entry Register */ + #define ISC_GAM_RENTRY 0x00000298 + ++/* ISC VHXS Control Register */ ++#define ISC_VHXS_CTRL 0x398 ++ ++/* ISC VHXS Source Size Register */ ++#define ISC_VHXS_SS 0x39C ++ ++/* ISC VHXS Destination Size Register */ ++#define ISC_VHXS_DS 0x3A0 ++ ++/* ISC Vertical Factor Register */ ++#define ISC_VXS_FACT 0x3a4 ++ ++/* ISC Horizontal Factor Register */ ++#define ISC_HXS_FACT 0x3a8 ++ ++/* ISC Vertical Config Register */ ++#define ISC_VXS_CFG 0x3ac ++ ++/* ISC Horizontal Config Register */ ++#define ISC_HXS_CFG 0x3b0 ++ ++/* ISC Vertical Tap Register */ ++#define ISC_VXS_TAP 0x3b4 ++ ++/* ISC Horizontal Tap Register */ ++#define ISC_HXS_TAP 0x434 ++ + /* Offset for CSC register specific to sama5d2 product */ + #define ISC_SAMA5D2_CSC_OFFSET 0 + diff --git a/target/linux/at91/patches-5.15/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch b/target/linux/at91/patches-5.15/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch new file mode 100644 index 0000000000..7cb5233c2e --- /dev/null +++ b/target/linux/at91/patches-5.15/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch @@ -0,0 +1,104 @@ +From 58a6cc3c7eecd16208cd16b92b4eaf8385e69696 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:16 +0200 +Subject: [PATCH 174/247] media: atmel: atmel-isc: extend pipeline with extra + modules + +Newer ISC pipelines have the additional modules of +Defective Pixel Correction -> DPC itself, +Defective Pixel Correction -> Green Disparity Correction (DPC_GDC) +Defective Pixel Correction -> Black Level Correction (DPC_BLC) +Vertical and Horizontal Scaler -> VHXS + +Some products have this full pipeline (sama7g5), other products do not (sama5d2) + +Add the modules to the isc base, and also extend the register range to include +the modules. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 11 ++++++-- + drivers/media/platform/atmel/atmel-isc.h | 28 +++++++++++-------- + 2 files changed, 25 insertions(+), 14 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -2324,8 +2324,14 @@ int isc_pipeline_init(struct isc_device + struct regmap_field *regs; + unsigned int i; + +- /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */ ++ /* ++ * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC--> ++ * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420 ++ */ + const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = { ++ REG_FIELD(ISC_DPC_CTRL, 0, 0), ++ REG_FIELD(ISC_DPC_CTRL, 1, 1), ++ REG_FIELD(ISC_DPC_CTRL, 2, 2), + REG_FIELD(ISC_WB_CTRL, 0, 0), + REG_FIELD(ISC_CFA_CTRL, 0, 0), + REG_FIELD(ISC_CC_CTRL, 0, 0), +@@ -2333,6 +2339,7 @@ int isc_pipeline_init(struct isc_device + REG_FIELD(ISC_GAM_CTRL, 1, 1), + REG_FIELD(ISC_GAM_CTRL, 2, 2), + REG_FIELD(ISC_GAM_CTRL, 3, 3), ++ REG_FIELD(ISC_VHXS_CTRL, 0, 0), + REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), + REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), + REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0), +@@ -2351,7 +2358,7 @@ int isc_pipeline_init(struct isc_device + } + + /* regmap configuration */ +-#define ATMEL_ISC_REG_MAX 0xbfc ++#define ATMEL_ISC_REG_MAX 0xd5c + const struct regmap_config isc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -67,17 +67,21 @@ struct isc_format { + }; + + /* Pipeline bitmap */ +-#define WB_ENABLE BIT(0) +-#define CFA_ENABLE BIT(1) +-#define CC_ENABLE BIT(2) +-#define GAM_ENABLE BIT(3) +-#define GAM_BENABLE BIT(4) +-#define GAM_GENABLE BIT(5) +-#define GAM_RENABLE BIT(6) +-#define CSC_ENABLE BIT(7) +-#define CBC_ENABLE BIT(8) +-#define SUB422_ENABLE BIT(9) +-#define SUB420_ENABLE BIT(10) ++#define DPC_DPCENABLE BIT(0) ++#define DPC_GDCENABLE BIT(1) ++#define DPC_BLCENABLE BIT(2) ++#define WB_ENABLE BIT(3) ++#define CFA_ENABLE BIT(4) ++#define CC_ENABLE BIT(5) ++#define GAM_ENABLE BIT(6) ++#define GAM_BENABLE BIT(7) ++#define GAM_GENABLE BIT(8) ++#define GAM_RENABLE BIT(9) ++#define VHXS_ENABLE BIT(10) ++#define CSC_ENABLE BIT(11) ++#define CBC_ENABLE BIT(12) ++#define SUB422_ENABLE BIT(13) ++#define SUB420_ENABLE BIT(14) + + #define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE) + +@@ -141,7 +145,7 @@ struct isc_ctrls { + u32 hist_minmax[HIST_BAYER][2]; + }; + +-#define ISC_PIPE_LINE_NODE_NUM 11 ++#define ISC_PIPE_LINE_NODE_NUM 15 + + /* + * struct isc_reg_offsets - ISC device register offsets diff --git a/target/linux/at91/patches-5.15/175-media-atmel-atmel-isc-add-CC-initialization-function.patch b/target/linux/at91/patches-5.15/175-media-atmel-atmel-isc-add-CC-initialization-function.patch new file mode 100644 index 0000000000..69491d7d13 --- /dev/null +++ b/target/linux/at91/patches-5.15/175-media-atmel-atmel-isc-add-CC-initialization-function.patch @@ -0,0 +1,83 @@ +From 0db91d2a803221c313c9f2cd1d71050d7c5a7b5b Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:17 +0200 +Subject: [PATCH 175/247] media: atmel: atmel-isc: add CC initialization + function + +The CC submodule is a part of the atmel-isc pipeline, and stands for +Color Correction. It is used to apply gains and offsets to the +chroma (U, V) components of the YUV elements. +Implement the CC submodule initialization, as a product +specific function, which currently configures the neutral point in color +correction. + +[hverkuil: made isc_sama5d2_config_cc static] + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 1 + + drivers/media/platform/atmel/atmel-isc.h | 3 +++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 14 ++++++++++++++ + 3 files changed, 18 insertions(+) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -661,6 +661,7 @@ static void isc_set_pipeline(struct isc_ + + isc->config_csc(isc); + isc->config_cbc(isc); ++ isc->config_cc(isc); + } + + static int isc_update_profile(struct isc_device *isc) +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -224,6 +224,8 @@ struct isc_reg_offsets { + * specific CSC module + * @config_cbc: pointer to a function that initializes product + * specific CBC module ++ * @config_cc: pointer to a function that initializes product ++ * specific CC module + * + * @offsets: struct holding the product specific register offsets + */ +@@ -297,6 +299,7 @@ struct isc_device { + struct { + void (*config_csc)(struct isc_device *isc); + void (*config_cbc)(struct isc_device *isc); ++ void (*config_cc)(struct isc_device *isc); + }; + + struct isc_reg_offsets offsets; +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -83,6 +83,19 @@ static void isc_sama5d2_config_cbc(struc + isc->ctrls.contrast); + } + ++static void isc_sama5d2_config_cc(struct isc_device *isc) ++{ ++ struct regmap *regmap = isc->regmap; ++ ++ /* Configure each register at the neutral fixed point 1.0 or 0.0 */ ++ regmap_write(regmap, ISC_CC_RR_RG, (1 << 8)); ++ regmap_write(regmap, ISC_CC_RB_OR, 0); ++ regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16); ++ regmap_write(regmap, ISC_CC_GB_OG, 0); ++ regmap_write(regmap, ISC_CC_BR_BG, 0); ++ regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); ++} ++ + /* Gamma table with gamma 1/2.2 */ + static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { + /* 0 --> gamma 1/1.8 */ +@@ -251,6 +264,7 @@ static int atmel_isc_probe(struct platfo + + isc->config_csc = isc_sama5d2_config_csc; + isc->config_cbc = isc_sama5d2_config_cbc; ++ isc->config_cc = isc_sama5d2_config_cc; + + isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; + isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; diff --git a/target/linux/at91/patches-5.15/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch b/target/linux/at91/patches-5.15/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch new file mode 100644 index 0000000000..35c839692c --- /dev/null +++ b/target/linux/at91/patches-5.15/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch @@ -0,0 +1,86 @@ +From 0a75c502eac4f2ef71b6c3e0b3a01db1b3c37ba9 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:18 +0200 +Subject: [PATCH 176/247] media: atmel: atmel-isc: create product specific v4l2 + controls config + +Create product specific callback for initializing v4l2 controls. +Call this from v4l2 controls init function. + +[hverkuil: made isc_sama5d2_config_ctrls static] + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 5 +++-- + drivers/media/platform/atmel/atmel-isc.h | 5 +++++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 12 ++++++++++++ + 3 files changed, 20 insertions(+), 2 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -2051,11 +2051,12 @@ static int isc_ctrl_init(struct isc_devi + if (ret < 0) + return ret; + ++ /* Initialize product specific controls. For example, contrast */ ++ isc->config_ctrls(isc, ops); ++ + ctrls->brightness = 0; +- ctrls->contrast = 256; + + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); +- v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, + isc->gamma_max); + isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -226,6 +226,8 @@ struct isc_reg_offsets { + * specific CBC module + * @config_cc: pointer to a function that initializes product + * specific CC module ++ * @config_ctrls: pointer to a functoin that initializes product ++ * specific v4l2 controls. + * + * @offsets: struct holding the product specific register offsets + */ +@@ -300,6 +302,9 @@ struct isc_device { + void (*config_csc)(struct isc_device *isc); + void (*config_cbc)(struct isc_device *isc); + void (*config_cc)(struct isc_device *isc); ++ ++ void (*config_ctrls)(struct isc_device *isc, ++ const struct v4l2_ctrl_ops *ops); + }; + + struct isc_reg_offsets offsets; +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -96,6 +96,17 @@ static void isc_sama5d2_config_cc(struct + regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); + } + ++static void isc_sama5d2_config_ctrls(struct isc_device *isc, ++ const struct v4l2_ctrl_ops *ops) ++{ ++ struct isc_ctrls *ctrls = &isc->ctrls; ++ struct v4l2_ctrl_handler *hdl = &ctrls->handler; ++ ++ ctrls->contrast = 256; ++ ++ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); ++} ++ + /* Gamma table with gamma 1/2.2 */ + static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { + /* 0 --> gamma 1/1.8 */ +@@ -265,6 +276,7 @@ static int atmel_isc_probe(struct platfo + isc->config_csc = isc_sama5d2_config_csc; + isc->config_cbc = isc_sama5d2_config_cbc; + isc->config_cc = isc_sama5d2_config_cc; ++ isc->config_ctrls = isc_sama5d2_config_ctrls; + + isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; + isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; diff --git a/target/linux/at91/patches-5.15/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch b/target/linux/at91/patches-5.15/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch new file mode 100644 index 0000000000..ef396f84cf --- /dev/null +++ b/target/linux/at91/patches-5.15/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch @@ -0,0 +1,75 @@ +From d53eb90044c19ba22b51978fcb007d9b5200b83a Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:19 +0200 +Subject: [PATCH 177/247] media: atmel: atmel-isc: create callback for DPC + submodule product specific + +The DPC submodule is a part of the atmel-isc pipeline, and stands for +Defective Pixel Correction. Its purpose is to detect defective pixels and +correct them if possible with the help of adjacent pixels. +Create a product specific callback for initializing the DPC submodule +of the pipeline. +For sama5d2 product, this module does not exist, thus this function is a noop. + +[hverkuil: made isc_sama5d2_config_dpc static] + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 1 + + drivers/media/platform/atmel/atmel-isc.h | 3 +++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++ + 3 files changed, 10 insertions(+) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -659,6 +659,7 @@ static void isc_set_pipeline(struct isc_ + regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); + regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); + ++ isc->config_dpc(isc); + isc->config_csc(isc); + isc->config_cbc(isc); + isc->config_cc(isc); +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -220,6 +220,8 @@ struct isc_reg_offsets { + * @max_width: maximum frame width, dependent on the internal RAM + * @max_height: maximum frame height, dependent on the internal RAM + * ++ * @config_dpc: pointer to a function that initializes product ++ * specific DPC module + * @config_csc: pointer to a function that initializes product + * specific CSC module + * @config_cbc: pointer to a function that initializes product +@@ -299,6 +301,7 @@ struct isc_device { + u32 max_height; + + struct { ++ void (*config_dpc)(struct isc_device *isc); + void (*config_csc)(struct isc_device *isc); + void (*config_cbc)(struct isc_device *isc); + void (*config_cc)(struct isc_device *isc); +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -107,6 +107,11 @@ static void isc_sama5d2_config_ctrls(str + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); + } + ++static void isc_sama5d2_config_dpc(struct isc_device *isc) ++{ ++ /* This module is not present on sama5d2 pipeline */ ++} ++ + /* Gamma table with gamma 1/2.2 */ + static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { + /* 0 --> gamma 1/1.8 */ +@@ -273,6 +278,7 @@ static int atmel_isc_probe(struct platfo + isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; + isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; + ++ isc->config_dpc = isc_sama5d2_config_dpc; + isc->config_csc = isc_sama5d2_config_csc; + isc->config_cbc = isc_sama5d2_config_cbc; + isc->config_cc = isc_sama5d2_config_cc; diff --git a/target/linux/at91/patches-5.15/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch b/target/linux/at91/patches-5.15/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch new file mode 100644 index 0000000000..a219704b31 --- /dev/null +++ b/target/linux/at91/patches-5.15/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch @@ -0,0 +1,75 @@ +From 96936a6753a13dea5a8f66de949e6594dd82ce22 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:20 +0200 +Subject: [PATCH 178/247] media: atmel: atmel-isc: create callback for GAM + submodule product specific + +The GAM submodule is a part of the atmel-isc pipeline, and stands for +Gamma Correction. It is used to apply the gamma curve to the incoming pixels. +Create a product specific callback for initializing the GAM submodule +of the pipeline. +For sama5d2 product, there is no special configuration at this moment, +thus this function is a noop. + +[hverkuil: made isc_sama5d2_config_gam static] + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 1 + + drivers/media/platform/atmel/atmel-isc.h | 3 +++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++ + 3 files changed, 10 insertions(+) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -663,6 +663,7 @@ static void isc_set_pipeline(struct isc_ + isc->config_csc(isc); + isc->config_cbc(isc); + isc->config_cc(isc); ++ isc->config_gam(isc); + } + + static int isc_update_profile(struct isc_device *isc) +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -228,6 +228,8 @@ struct isc_reg_offsets { + * specific CBC module + * @config_cc: pointer to a function that initializes product + * specific CC module ++ * @config_gam: pointer to a function that initializes product ++ * specific GAMMA module + * @config_ctrls: pointer to a functoin that initializes product + * specific v4l2 controls. + * +@@ -305,6 +307,7 @@ struct isc_device { + void (*config_csc)(struct isc_device *isc); + void (*config_cbc)(struct isc_device *isc); + void (*config_cc)(struct isc_device *isc); ++ void (*config_gam)(struct isc_device *isc); + + void (*config_ctrls)(struct isc_device *isc, + const struct v4l2_ctrl_ops *ops); +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -112,6 +112,11 @@ static void isc_sama5d2_config_dpc(struc + /* This module is not present on sama5d2 pipeline */ + } + ++static void isc_sama5d2_config_gam(struct isc_device *isc) ++{ ++ /* No specific gamma configuration */ ++} ++ + /* Gamma table with gamma 1/2.2 */ + static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { + /* 0 --> gamma 1/1.8 */ +@@ -282,6 +287,7 @@ static int atmel_isc_probe(struct platfo + isc->config_csc = isc_sama5d2_config_csc; + isc->config_cbc = isc_sama5d2_config_cbc; + isc->config_cc = isc_sama5d2_config_cc; ++ isc->config_gam = isc_sama5d2_config_gam; + isc->config_ctrls = isc_sama5d2_config_ctrls; + + isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; diff --git a/target/linux/at91/patches-5.15/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch b/target/linux/at91/patches-5.15/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch new file mode 100644 index 0000000000..8442925a7e --- /dev/null +++ b/target/linux/at91/patches-5.15/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch @@ -0,0 +1,95 @@ +From ece1d7059731e31875e6eb464da4fb4a16465305 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:21 +0200 +Subject: [PATCH 179/247] media: atmel: atmel-isc: create callback for RLP + submodule product specific + +The RLP submodule is a part of the atmel-isc pipeline, and stands for +Rounding,Limiting and Packaging. It used to extract specific data from the +ISC pipeline. For example if we want to output greyscale 8 bit, we would +use limiting to 8 bits, and packaging to Luma component only. + +Create a product specific callback for initializing the RLP submodule +of the pipeline + +[hverkuil: made isc_sama5d2_config_rlp static] + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 6 ++---- + drivers/media/platform/atmel/atmel-isc.h | 3 +++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 10 ++++++++++ + 3 files changed, 15 insertions(+), 4 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -719,11 +719,10 @@ static void isc_set_histogram(struct isc + static int isc_configure(struct isc_device *isc) + { + struct regmap *regmap = isc->regmap; +- u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline; ++ u32 pfe_cfg0, dcfg, mask, pipeline; + struct isc_subdev_entity *subdev = isc->current_subdev; + + pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps; +- rlp_mode = isc->config.rlp_cfg_mode; + pipeline = isc->config.bits_pipeline; + + dcfg = isc->config.dcfg_imode | isc->dcfg; +@@ -736,8 +735,7 @@ static int isc_configure(struct isc_devi + + regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); + +- regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, +- ISC_RLP_CFG_MODE_MASK, rlp_mode); ++ isc->config_rlp(isc); + + regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); + +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -230,6 +230,8 @@ struct isc_reg_offsets { + * specific CC module + * @config_gam: pointer to a function that initializes product + * specific GAMMA module ++ * @config_rlp: pointer to a function that initializes product ++ * specific RLP module + * @config_ctrls: pointer to a functoin that initializes product + * specific v4l2 controls. + * +@@ -308,6 +310,7 @@ struct isc_device { + void (*config_cbc)(struct isc_device *isc); + void (*config_cc)(struct isc_device *isc); + void (*config_gam)(struct isc_device *isc); ++ void (*config_rlp)(struct isc_device *isc); + + void (*config_ctrls)(struct isc_device *isc, + const struct v4l2_ctrl_ops *ops); +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -117,6 +117,15 @@ static void isc_sama5d2_config_gam(struc + /* No specific gamma configuration */ + } + ++static void isc_sama5d2_config_rlp(struct isc_device *isc) ++{ ++ struct regmap *regmap = isc->regmap; ++ u32 rlp_mode = isc->config.rlp_cfg_mode; ++ ++ regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, ++ ISC_RLP_CFG_MODE_MASK, rlp_mode); ++} ++ + /* Gamma table with gamma 1/2.2 */ + static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { + /* 0 --> gamma 1/1.8 */ +@@ -288,6 +297,7 @@ static int atmel_isc_probe(struct platfo + isc->config_cbc = isc_sama5d2_config_cbc; + isc->config_cc = isc_sama5d2_config_cc; + isc->config_gam = isc_sama5d2_config_gam; ++ isc->config_rlp = isc_sama5d2_config_rlp; + isc->config_ctrls = isc_sama5d2_config_ctrls; + + isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; diff --git a/target/linux/at91/patches-5.15/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch b/target/linux/at91/patches-5.15/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch new file mode 100644 index 0000000000..1c64cfca2e --- /dev/null +++ b/target/linux/at91/patches-5.15/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch @@ -0,0 +1,440 @@ +From dda51aa2e4524914d25022864466fa9d8713a5e9 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:22 +0200 +Subject: [PATCH 180/247] media: atmel: atmel-isc: move the formats list into + product specific code + +The list of input and output formats has to be product specific. +Move this list into the product specific code. +Have pointers to these arrays inside the device struct. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 167 ++---------------- + drivers/media/platform/atmel/atmel-isc.h | 12 +- + .../media/platform/atmel/atmel-sama5d2-isc.c | 136 ++++++++++++++ + 3 files changed, 165 insertions(+), 150 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -45,137 +45,6 @@ module_param(sensor_preferred, uint, 064 + MODULE_PARM_DESC(sensor_preferred, + "Sensor is preferred to output the specified format (1-on 0-off), default 1"); + +-/* This is a list of the formats that the ISC can *output* */ +-const struct isc_format controller_formats[] = { +- { +- .fourcc = V4L2_PIX_FMT_ARGB444, +- }, +- { +- .fourcc = V4L2_PIX_FMT_ARGB555, +- }, +- { +- .fourcc = V4L2_PIX_FMT_RGB565, +- }, +- { +- .fourcc = V4L2_PIX_FMT_ABGR32, +- }, +- { +- .fourcc = V4L2_PIX_FMT_XBGR32, +- }, +- { +- .fourcc = V4L2_PIX_FMT_YUV420, +- }, +- { +- .fourcc = V4L2_PIX_FMT_YUYV, +- }, +- { +- .fourcc = V4L2_PIX_FMT_YUV422P, +- }, +- { +- .fourcc = V4L2_PIX_FMT_GREY, +- }, +- { +- .fourcc = V4L2_PIX_FMT_Y10, +- }, +-}; +- +-/* This is a list of formats that the ISC can receive as *input* */ +-struct isc_format formats_list[] = { +- { +- .fourcc = V4L2_PIX_FMT_SBGGR8, +- .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- .cfa_baycfg = ISC_BAY_CFG_BGBG, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SGBRG8, +- .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- .cfa_baycfg = ISC_BAY_CFG_GBGB, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SGRBG8, +- .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- .cfa_baycfg = ISC_BAY_CFG_GRGR, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SRGGB8, +- .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- .cfa_baycfg = ISC_BAY_CFG_RGRG, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SBGGR10, +- .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, +- .cfa_baycfg = ISC_BAY_CFG_RGRG, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SGBRG10, +- .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, +- .cfa_baycfg = ISC_BAY_CFG_GBGB, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SGRBG10, +- .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, +- .cfa_baycfg = ISC_BAY_CFG_GRGR, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SRGGB10, +- .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, +- .cfa_baycfg = ISC_BAY_CFG_RGRG, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SBGGR12, +- .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, +- .cfa_baycfg = ISC_BAY_CFG_BGBG, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SGBRG12, +- .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, +- .cfa_baycfg = ISC_BAY_CFG_GBGB, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SGRBG12, +- .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, +- .cfa_baycfg = ISC_BAY_CFG_GRGR, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SRGGB12, +- .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, +- .cfa_baycfg = ISC_BAY_CFG_RGRG, +- }, +- { +- .fourcc = V4L2_PIX_FMT_GREY, +- .mbus_code = MEDIA_BUS_FMT_Y8_1X8, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- }, +- { +- .fourcc = V4L2_PIX_FMT_YUYV, +- .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- }, +- { +- .fourcc = V4L2_PIX_FMT_RGB565, +- .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- }, +- { +- .fourcc = V4L2_PIX_FMT_Y10, +- .mbus_code = MEDIA_BUS_FMT_Y10_1X10, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, +- }, +- +-}; +- + #define ISC_IS_FORMAT_RAW(mbus_code) \ + (((mbus_code) & 0xf000) == 0x3000) + +@@ -919,24 +788,25 @@ static int isc_querycap(struct file *fil + static int isc_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) + { ++ struct isc_device *isc = video_drvdata(file); + u32 index = f->index; + u32 i, supported_index; + +- if (index < ARRAY_SIZE(controller_formats)) { +- f->pixelformat = controller_formats[index].fourcc; ++ if (index < isc->controller_formats_size) { ++ f->pixelformat = isc->controller_formats[index].fourcc; + return 0; + } + +- index -= ARRAY_SIZE(controller_formats); ++ index -= isc->controller_formats_size; + + supported_index = 0; + +- for (i = 0; i < ARRAY_SIZE(formats_list); i++) { +- if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) || +- !formats_list[i].sd_support) ++ for (i = 0; i < isc->formats_list_size; i++) { ++ if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) || ++ !isc->formats_list[i].sd_support) + continue; + if (supported_index == index) { +- f->pixelformat = formats_list[i].fourcc; ++ f->pixelformat = isc->formats_list[i].fourcc; + return 0; + } + supported_index++; +@@ -1477,8 +1347,8 @@ static int isc_enum_framesizes(struct fi + if (isc->user_formats[i]->fourcc == fsize->pixel_format) + ret = 0; + +- for (i = 0; i < ARRAY_SIZE(controller_formats); i++) +- if (controller_formats[i].fourcc == fsize->pixel_format) ++ for (i = 0; i < isc->controller_formats_size; i++) ++ if (isc->controller_formats[i].fourcc == fsize->pixel_format) + ret = 0; + + if (ret) +@@ -1514,8 +1384,8 @@ static int isc_enum_frameintervals(struc + if (isc->user_formats[i]->fourcc == fival->pixel_format) + ret = 0; + +- for (i = 0; i < ARRAY_SIZE(controller_formats); i++) +- if (controller_formats[i].fourcc == fival->pixel_format) ++ for (i = 0; i < isc->controller_formats_size; i++) ++ if (isc->controller_formats[i].fourcc == fival->pixel_format) + ret = 0; + + if (ret) +@@ -2126,12 +1996,13 @@ static void isc_async_unbind(struct v4l2 + v4l2_ctrl_handler_free(&isc->ctrls.handler); + } + +-static struct isc_format *find_format_by_code(unsigned int code, int *index) ++static struct isc_format *find_format_by_code(struct isc_device *isc, ++ unsigned int code, int *index) + { +- struct isc_format *fmt = &formats_list[0]; ++ struct isc_format *fmt = &isc->formats_list[0]; + unsigned int i; + +- for (i = 0; i < ARRAY_SIZE(formats_list); i++) { ++ for (i = 0; i < isc->formats_list_size; i++) { + if (fmt->mbus_code == code) { + *index = i; + return fmt; +@@ -2148,7 +2019,7 @@ static int isc_formats_init(struct isc_d + struct isc_format *fmt; + struct v4l2_subdev *subdev = isc->current_subdev->sd; + unsigned int num_fmts, i, j; +- u32 list_size = ARRAY_SIZE(formats_list); ++ u32 list_size = isc->formats_list_size; + struct v4l2_subdev_mbus_code_enum mbus_code = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; +@@ -2158,7 +2029,7 @@ static int isc_formats_init(struct isc_d + NULL, &mbus_code)) { + mbus_code.index++; + +- fmt = find_format_by_code(mbus_code.code, &i); ++ fmt = find_format_by_code(isc, mbus_code.code, &i); + if (!fmt) { + v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n", + mbus_code.code); +@@ -2179,7 +2050,7 @@ static int isc_formats_init(struct isc_d + if (!isc->user_formats) + return -ENOMEM; + +- fmt = &formats_list[0]; ++ fmt = &isc->formats_list[0]; + for (i = 0, j = 0; i < list_size; i++) { + if (fmt->sd_support) + isc->user_formats[j++] = fmt; +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -236,6 +236,12 @@ struct isc_reg_offsets { + * specific v4l2 controls. + * + * @offsets: struct holding the product specific register offsets ++ * @controller_formats: pointer to the array of possible formats that the ++ * controller can output ++ * @formats_list: pointer to the array of possible formats that can ++ * be used as an input to the controller ++ * @controller_formats_size: size of controller_formats array ++ * @formats_list_size: size of formats_list array + */ + struct isc_device { + struct regmap *regmap; +@@ -317,10 +323,12 @@ struct isc_device { + }; + + struct isc_reg_offsets offsets; ++ const struct isc_format *controller_formats; ++ struct isc_format *formats_list; ++ u32 controller_formats_size; ++ u32 formats_list_size; + }; + +-extern struct isc_format formats_list[]; +-extern const struct isc_format controller_formats[]; + extern const struct regmap_config isc_regmap_config; + extern const struct v4l2_async_notifier_operations isc_async_ops; + +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -54,6 +54,137 @@ + + #define ISC_CLK_MAX_DIV 255 + ++/* This is a list of the formats that the ISC can *output* */ ++static const struct isc_format sama5d2_controller_formats[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_ARGB444, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_ARGB555, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_RGB565, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_ABGR32, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_XBGR32, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV420, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUYV, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV422P, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_GREY, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_Y10, ++ }, ++}; ++ ++/* This is a list of formats that the ISC can receive as *input* */ ++static struct isc_format sama5d2_formats_list[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_SBGGR8, ++ .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ .cfa_baycfg = ISC_BAY_CFG_BGBG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGBRG8, ++ .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ .cfa_baycfg = ISC_BAY_CFG_GBGB, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGRBG8, ++ .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ .cfa_baycfg = ISC_BAY_CFG_GRGR, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SRGGB8, ++ .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ .cfa_baycfg = ISC_BAY_CFG_RGRG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SBGGR10, ++ .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ .cfa_baycfg = ISC_BAY_CFG_RGRG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGBRG10, ++ .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ .cfa_baycfg = ISC_BAY_CFG_GBGB, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGRBG10, ++ .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ .cfa_baycfg = ISC_BAY_CFG_GRGR, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SRGGB10, ++ .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ .cfa_baycfg = ISC_BAY_CFG_RGRG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SBGGR12, ++ .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, ++ .cfa_baycfg = ISC_BAY_CFG_BGBG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGBRG12, ++ .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, ++ .cfa_baycfg = ISC_BAY_CFG_GBGB, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGRBG12, ++ .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, ++ .cfa_baycfg = ISC_BAY_CFG_GRGR, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SRGGB12, ++ .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, ++ .cfa_baycfg = ISC_BAY_CFG_RGRG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_GREY, ++ .mbus_code = MEDIA_BUS_FMT_Y8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUYV, ++ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_RGB565, ++ .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_Y10, ++ .mbus_code = MEDIA_BUS_FMT_Y10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ }, ++ ++}; ++ + static void isc_sama5d2_config_csc(struct isc_device *isc) + { + struct regmap *regmap = isc->regmap; +@@ -310,6 +441,11 @@ static int atmel_isc_probe(struct platfo + isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; + isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET; + ++ isc->controller_formats = sama5d2_controller_formats; ++ isc->controller_formats_size = ARRAY_SIZE(sama5d2_controller_formats); ++ isc->formats_list = sama5d2_formats_list; ++ isc->formats_list_size = ARRAY_SIZE(sama5d2_formats_list); ++ + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; + diff --git a/target/linux/at91/patches-5.15/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch b/target/linux/at91/patches-5.15/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch new file mode 100644 index 0000000000..042fc609fe --- /dev/null +++ b/target/linux/at91/patches-5.15/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch @@ -0,0 +1,89 @@ +From 8601f1fc0a9a22788bfa6369fbbf83b3828a5b42 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:23 +0200 +Subject: [PATCH 181/247] media: atmel: atmel-isc: create an adapt pipeline + callback for product specific + +Once the pipeline is set in the base code, create a callback that will adapt +the ISC pipeline to each product. +Create the adapt_pipeline callback that will be used in this fashion. + +[hverkuil: made isc_sama5d2_adapt_pipeline static] + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 4 ++++ + drivers/media/platform/atmel/atmel-isc.h | 5 +++++ + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 11 +++++++++++ + 3 files changed, 20 insertions(+) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -1059,6 +1059,10 @@ static int isc_try_configure_pipeline(st + default: + isc->try_config.bits_pipeline = 0x0; + } ++ ++ /* Tune the pipeline to product specific */ ++ isc->adapt_pipeline(isc); ++ + return 0; + } + +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -235,6 +235,9 @@ struct isc_reg_offsets { + * @config_ctrls: pointer to a functoin that initializes product + * specific v4l2 controls. + * ++ * @adapt_pipeline: pointer to a function that adapts the pipeline bits ++ * to the product specific pipeline ++ * + * @offsets: struct holding the product specific register offsets + * @controller_formats: pointer to the array of possible formats that the + * controller can output +@@ -320,6 +323,8 @@ struct isc_device { + + void (*config_ctrls)(struct isc_device *isc, + const struct v4l2_ctrl_ops *ops); ++ ++ void (*adapt_pipeline)(struct isc_device *isc); + }; + + struct isc_reg_offsets offsets; +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -54,6 +54,10 @@ + + #define ISC_CLK_MAX_DIV 255 + ++#define ISC_SAMA5D2_PIPELINE \ ++ (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ ++ CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) ++ + /* This is a list of the formats that the ISC can *output* */ + static const struct isc_format sama5d2_controller_formats[] = { + { +@@ -257,6 +261,11 @@ static void isc_sama5d2_config_rlp(struc + ISC_RLP_CFG_MODE_MASK, rlp_mode); + } + ++static void isc_sama5d2_adapt_pipeline(struct isc_device *isc) ++{ ++ isc->try_config.bits_pipeline &= ISC_SAMA5D2_PIPELINE; ++} ++ + /* Gamma table with gamma 1/2.2 */ + static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { + /* 0 --> gamma 1/1.8 */ +@@ -431,6 +440,8 @@ static int atmel_isc_probe(struct platfo + isc->config_rlp = isc_sama5d2_config_rlp; + isc->config_ctrls = isc_sama5d2_config_ctrls; + ++ isc->adapt_pipeline = isc_sama5d2_adapt_pipeline; ++ + isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; + isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; + isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; diff --git a/target/linux/at91/patches-5.15/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch b/target/linux/at91/patches-5.15/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch new file mode 100644 index 0000000000..00849c7d12 --- /dev/null +++ b/target/linux/at91/patches-5.15/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch @@ -0,0 +1,55 @@ +From bf032d1a0105939b90072914d88181fbe6187f43 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:24 +0200 +Subject: [PATCH 182/247] media: atmel: atmel-isc-regs: add additional fields + for sama7g5 type pipeline + +Add additional fields for registers present in sama7g5 type pipeline. +Extend register masks for additional bits in sama7g5 type pipeline registers. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-regs.h | 16 ++++++++++++++-- + 1 file changed, 14 insertions(+), 2 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -289,8 +289,18 @@ + #define ISC_RLP_CFG_MODE_ARGB32 0xa + #define ISC_RLP_CFG_MODE_YYCC 0xb + #define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc ++#define ISC_RLP_CFG_MODE_YCYC 0xd + #define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) + ++#define ISC_RLP_CFG_LSH BIT(5) ++ ++#define ISC_RLP_CFG_YMODE_YUYV (3 << 6) ++#define ISC_RLP_CFG_YMODE_YVYU (2 << 6) ++#define ISC_RLP_CFG_YMODE_VYUY (0 << 6) ++#define ISC_RLP_CFG_YMODE_UYVY (1 << 6) ++ ++#define ISC_RLP_CFG_YMODE_MASK GENMASK(7, 6) ++ + /* Offset for HIS register specific to sama5d2 product */ + #define ISC_SAMA5D2_HIS_OFFSET 0 + /* Histogram Control Register */ +@@ -332,13 +342,15 @@ + #define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4) + #define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4) + #define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4) +-#define ISC_DCFG_YMBSIZE_MASK GENMASK(5, 4) ++#define ISC_DCFG_YMBSIZE_BEATS32 (0x4 << 4) ++#define ISC_DCFG_YMBSIZE_MASK GENMASK(6, 4) + + #define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8) + #define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8) + #define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8) + #define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8) +-#define ISC_DCFG_CMBSIZE_MASK GENMASK(9, 8) ++#define ISC_DCFG_CMBSIZE_BEATS32 (0x4 << 8) ++#define ISC_DCFG_CMBSIZE_MASK GENMASK(10, 8) + + /* DMA Control Register */ + #define ISC_DCTRL 0x000003e4 diff --git a/target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch b/target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch new file mode 100644 index 0000000000..247c901558 --- /dev/null +++ b/target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch @@ -0,0 +1,145 @@ +From fa9e6cd8f3ba4a277c06e4c1fb01cd69b3a57234 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:25 +0200 +Subject: [PATCH 183/247] media: atmel: atmel-isc-base: add support for more + formats and additional pipeline modules + +Add support for additional formats supported by newer pipelines, and for +additional pipeline modules. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 48 +++++++++++++++---- + 1 file changed, 38 insertions(+), 10 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -855,6 +855,8 @@ static int isc_try_validate_formats(stru + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YUV422P: + case V4L2_PIX_FMT_YUYV: ++ case V4L2_PIX_FMT_UYVY: ++ case V4L2_PIX_FMT_VYUY: + ret = 0; + yuv = true; + break; +@@ -869,6 +871,7 @@ static int isc_try_validate_formats(stru + break; + case V4L2_PIX_FMT_GREY: + case V4L2_PIX_FMT_Y10: ++ case V4L2_PIX_FMT_Y16: + ret = 0; + grey = true; + break; +@@ -899,6 +902,8 @@ static int isc_try_validate_formats(stru + */ + static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) + { ++ isc->try_config.rlp_cfg_mode = 0; ++ + switch (isc->try_config.fourcc) { + case V4L2_PIX_FMT_SBGGR8: + case V4L2_PIX_FMT_SGBRG8: +@@ -965,7 +970,19 @@ static int isc_try_configure_rlp_dma(str + isc->try_config.bpp = 16; + break; + case V4L2_PIX_FMT_YUYV: +- isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; ++ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV; ++ isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; ++ isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; ++ isc->try_config.bpp = 16; ++ break; ++ case V4L2_PIX_FMT_UYVY: ++ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY; ++ isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; ++ isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; ++ isc->try_config.bpp = 16; ++ break; ++ case V4L2_PIX_FMT_VYUY: ++ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; +@@ -976,8 +993,11 @@ static int isc_try_configure_rlp_dma(str + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 8; + break; ++ case V4L2_PIX_FMT_Y16: ++ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH; ++ fallthrough; + case V4L2_PIX_FMT_Y10: +- isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10; ++ isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; +@@ -1011,7 +1031,8 @@ static int isc_try_configure_pipeline(st + /* if sensor format is RAW, we convert inside ISC */ + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | +- WB_ENABLE | GAM_ENABLES; ++ WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE | ++ CC_ENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } +@@ -1020,8 +1041,9 @@ static int isc_try_configure_pipeline(st + /* if sensor format is RAW, we convert inside ISC */ + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | +- CSC_ENABLE | WB_ENABLE | GAM_ENABLES | +- SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE; ++ CSC_ENABLE | GAM_ENABLES | WB_ENABLE | ++ SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE | ++ DPC_BLCENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } +@@ -1031,33 +1053,39 @@ static int isc_try_configure_pipeline(st + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | + CSC_ENABLE | WB_ENABLE | GAM_ENABLES | +- SUB422_ENABLE | CBC_ENABLE; ++ SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } + break; + case V4L2_PIX_FMT_YUYV: ++ case V4L2_PIX_FMT_UYVY: ++ case V4L2_PIX_FMT_VYUY: + /* if sensor format is RAW, we convert inside ISC */ + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | + CSC_ENABLE | WB_ENABLE | GAM_ENABLES | +- SUB422_ENABLE | CBC_ENABLE; ++ SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } + break; + case V4L2_PIX_FMT_GREY: +- if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { ++ case V4L2_PIX_FMT_Y16: + /* if sensor format is RAW, we convert inside ISC */ ++ if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | + CSC_ENABLE | WB_ENABLE | GAM_ENABLES | +- CBC_ENABLE; ++ CBC_ENABLE | DPC_BLCENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } + break; + default: +- isc->try_config.bits_pipeline = 0x0; ++ if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) ++ isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE; ++ else ++ isc->try_config.bits_pipeline = 0x0; + } + + /* Tune the pipeline to product specific */ diff --git a/target/linux/at91/patches-5.15/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch b/target/linux/at91/patches-5.15/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch new file mode 100644 index 0000000000..587f4862f2 --- /dev/null +++ b/target/linux/at91/patches-5.15/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch @@ -0,0 +1,26 @@ +From b36d11efc134f9f1e2804270d08b9dbefdee4a0d Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:26 +0200 +Subject: [PATCH 184/247] media: atmel: atmel-isc-sama5d2: remove duplicate + define + +Remove a duplicate definition of clock max divider + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -52,8 +52,6 @@ + #define ISC_SAMA5D2_MAX_SUPPORT_WIDTH 2592 + #define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT 1944 + +-#define ISC_CLK_MAX_DIV 255 +- + #define ISC_SAMA5D2_PIPELINE \ + (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ + CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) diff --git a/target/linux/at91/patches-5.15/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch b/target/linux/at91/patches-5.15/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch new file mode 100644 index 0000000000..a21ac2a7c0 --- /dev/null +++ b/target/linux/at91/patches-5.15/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch @@ -0,0 +1,810 @@ +From 74fd7ea680cb1a3a43b51a7279aea45efdf9ec42 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:29 +0200 +Subject: [PATCH 185/247] media: atmel: atmel-isc: add microchip-xisc driver + +Add driver for the extended variant of the isc, the microchip XISC +present on sama7g5 product. + +[hverkuil: drop MODULE_SUPPORTED_DEVICE, no longer exists] +[hverkuil: made isc_sama7g5_config_csc et al static] +[hverkuil: made sama7g5_controller_formats et al static] + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/Makefile | 1 + + drivers/media/platform/atmel/Kconfig | 11 + + drivers/media/platform/atmel/Makefile | 2 + + drivers/media/platform/atmel/atmel-isc-base.c | 2 +- + drivers/media/platform/atmel/atmel-isc-regs.h | 26 + + .../media/platform/atmel/atmel-sama7g5-isc.c | 630 ++++++++++++++++++ + 6 files changed, 671 insertions(+), 1 deletion(-) + create mode 100644 drivers/media/platform/atmel/atmel-sama7g5-isc.c + +--- a/drivers/media/platform/Makefile ++++ b/drivers/media/platform/Makefile +@@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_RCAR_VIN) += rcar-vi + + obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel/ + obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel/ ++obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel/ + + obj-$(CONFIG_VIDEO_STM32_DCMI) += stm32/ + +--- a/drivers/media/platform/atmel/Kconfig ++++ b/drivers/media/platform/atmel/Kconfig +@@ -12,6 +12,17 @@ config VIDEO_ATMEL_ISC + This module makes the ATMEL Image Sensor Controller available + as a v4l2 device. + ++config VIDEO_ATMEL_XISC ++ tristate "ATMEL eXtended Image Sensor Controller (XISC) support" ++ depends on VIDEO_V4L2 && COMMON_CLK && VIDEO_V4L2_SUBDEV_API ++ depends on ARCH_AT91 || COMPILE_TEST ++ select VIDEOBUF2_DMA_CONTIG ++ select REGMAP_MMIO ++ select V4L2_FWNODE ++ help ++ This module makes the ATMEL eXtended Image Sensor Controller ++ available as a v4l2 device. ++ + config VIDEO_ATMEL_ISI + tristate "ATMEL Image Sensor Interface (ISI) support" + depends on VIDEO_V4L2 && OF +--- a/drivers/media/platform/atmel/Makefile ++++ b/drivers/media/platform/atmel/Makefile +@@ -1,5 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0-only + atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o ++atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o + + obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o + obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o ++obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -600,7 +600,7 @@ static int isc_configure(struct isc_devi + mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW | + ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW | + ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC | +- ISC_PFE_CFG0_CCIR656; ++ ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI; + + regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); + +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -26,6 +26,7 @@ + #define ISC_PFE_CFG0_PPOL_LOW BIT(2) + #define ISC_PFE_CFG0_CCIR656 BIT(9) + #define ISC_PFE_CFG0_CCIR_CRC BIT(10) ++#define ISC_PFE_CFG0_MIPI BIT(14) + + #define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4) + #define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4) +@@ -184,6 +185,8 @@ + /* ISC Gamma Correction Control Register */ + #define ISC_GAM_CTRL 0x00000094 + ++#define ISC_GAM_CTRL_BIPART BIT(4) ++ + /* ISC_Gamma Correction Blue Entry Register */ + #define ISC_GAM_BENTRY 0x00000098 + +@@ -222,6 +225,8 @@ + + /* Offset for CSC register specific to sama5d2 product */ + #define ISC_SAMA5D2_CSC_OFFSET 0 ++/* Offset for CSC register specific to sama7g5 product */ ++#define ISC_SAMA7G5_CSC_OFFSET 0x11c + + /* Color Space Conversion Control Register */ + #define ISC_CSC_CTRL 0x00000398 +@@ -246,6 +251,8 @@ + + /* Offset for CBC register specific to sama5d2 product */ + #define ISC_SAMA5D2_CBC_OFFSET 0 ++/* Offset for CBC register specific to sama7g5 product */ ++#define ISC_SAMA7G5_CBC_OFFSET 0x11c + + /* Contrast And Brightness Control Register */ + #define ISC_CBC_CTRL 0x000003b4 +@@ -261,18 +268,30 @@ + #define ISC_CBC_CONTRAST 0x000003c0 + #define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) + ++/* Hue Register */ ++#define ISC_CBCHS_HUE 0x4e0 ++/* Saturation Register */ ++#define ISC_CBCHS_SAT 0x4e4 ++ + /* Offset for SUB422 register specific to sama5d2 product */ + #define ISC_SAMA5D2_SUB422_OFFSET 0 ++/* Offset for SUB422 register specific to sama7g5 product */ ++#define ISC_SAMA7G5_SUB422_OFFSET 0x124 ++ + /* Subsampling 4:4:4 to 4:2:2 Control Register */ + #define ISC_SUB422_CTRL 0x000003c4 + + /* Offset for SUB420 register specific to sama5d2 product */ + #define ISC_SAMA5D2_SUB420_OFFSET 0 ++/* Offset for SUB420 register specific to sama7g5 product */ ++#define ISC_SAMA7G5_SUB420_OFFSET 0x124 + /* Subsampling 4:2:2 to 4:2:0 Control Register */ + #define ISC_SUB420_CTRL 0x000003cc + + /* Offset for RLP register specific to sama5d2 product */ + #define ISC_SAMA5D2_RLP_OFFSET 0 ++/* Offset for RLP register specific to sama7g5 product */ ++#define ISC_SAMA7G5_RLP_OFFSET 0x124 + /* Rounding, Limiting and Packing Configuration Register */ + #define ISC_RLP_CFG 0x000003d0 + +@@ -303,6 +322,8 @@ + + /* Offset for HIS register specific to sama5d2 product */ + #define ISC_SAMA5D2_HIS_OFFSET 0 ++/* Offset for HIS register specific to sama7g5 product */ ++#define ISC_SAMA7G5_HIS_OFFSET 0x124 + /* Histogram Control Register */ + #define ISC_HIS_CTRL 0x000003d4 + +@@ -326,6 +347,8 @@ + + /* Offset for DMA register specific to sama5d2 product */ + #define ISC_SAMA5D2_DMA_OFFSET 0 ++/* Offset for DMA register specific to sama7g5 product */ ++#define ISC_SAMA7G5_DMA_OFFSET 0x13c + + /* DMA Configuration Register */ + #define ISC_DCFG 0x000003e0 +@@ -376,11 +399,14 @@ + + /* Offset for version register specific to sama5d2 product */ + #define ISC_SAMA5D2_VERSION_OFFSET 0 ++#define ISC_SAMA7G5_VERSION_OFFSET 0x13c + /* Version Register */ + #define ISC_VERSION 0x0000040c + + /* Offset for version register specific to sama5d2 product */ + #define ISC_SAMA5D2_HIS_ENTRY_OFFSET 0 ++/* Offset for version register specific to sama7g5 product */ ++#define ISC_SAMA7G5_HIS_ENTRY_OFFSET 0x14c + /* Histogram Entry */ + #define ISC_HIS_ENTRY 0x00000410 + +--- /dev/null ++++ b/drivers/media/platform/atmel/atmel-sama7g5-isc.c +@@ -0,0 +1,630 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Microchip eXtended Image Sensor Controller (XISC) driver ++ * ++ * Copyright (C) 2019-2021 Microchip Technology, Inc. and its subsidiaries ++ * ++ * Author: Eugen Hristev ++ * ++ * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS ++ * ++ * ISC video pipeline integrates the following submodules: ++ * PFE: Parallel Front End to sample the camera sensor input stream ++ * DPC: Defective Pixel Correction with black offset correction, green disparity ++ * correction and defective pixel correction (3 modules total) ++ * WB: Programmable white balance in the Bayer domain ++ * CFA: Color filter array interpolation module ++ * CC: Programmable color correction ++ * GAM: Gamma correction ++ *VHXS: Vertical and Horizontal Scaler ++ * CSC: Programmable color space conversion ++ *CBHS: Contrast Brightness Hue and Saturation control ++ * SUB: This module performs YCbCr444 to YCbCr420 chrominance subsampling ++ * RLP: This module performs rounding, range limiting ++ * and packing of the incoming data ++ * DMA: This module performs DMA master accesses to write frames to external RAM ++ * HIS: Histogram module performs statistic counters on the frames ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "atmel-isc-regs.h" ++#include "atmel-isc.h" ++ ++#define ISC_SAMA7G5_MAX_SUPPORT_WIDTH 3264 ++#define ISC_SAMA7G5_MAX_SUPPORT_HEIGHT 2464 ++ ++#define ISC_SAMA7G5_PIPELINE \ ++ (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ ++ CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) ++ ++/* This is a list of the formats that the ISC can *output* */ ++static const struct isc_format sama7g5_controller_formats[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_ARGB444, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_ARGB555, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_RGB565, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_ABGR32, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_XBGR32, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV420, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_UYVY, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_VYUY, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUYV, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV422P, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_GREY, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_Y10, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_Y16, ++ }, ++}; ++ ++/* This is a list of formats that the ISC can receive as *input* */ ++static struct isc_format sama7g5_formats_list[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_SBGGR8, ++ .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ .cfa_baycfg = ISC_BAY_CFG_BGBG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGBRG8, ++ .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ .cfa_baycfg = ISC_BAY_CFG_GBGB, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGRBG8, ++ .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ .cfa_baycfg = ISC_BAY_CFG_GRGR, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SRGGB8, ++ .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ .cfa_baycfg = ISC_BAY_CFG_RGRG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SBGGR10, ++ .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ .cfa_baycfg = ISC_BAY_CFG_RGRG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGBRG10, ++ .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ .cfa_baycfg = ISC_BAY_CFG_GBGB, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGRBG10, ++ .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ .cfa_baycfg = ISC_BAY_CFG_GRGR, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SRGGB10, ++ .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ .cfa_baycfg = ISC_BAY_CFG_RGRG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SBGGR12, ++ .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, ++ .cfa_baycfg = ISC_BAY_CFG_BGBG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGBRG12, ++ .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, ++ .cfa_baycfg = ISC_BAY_CFG_GBGB, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGRBG12, ++ .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, ++ .cfa_baycfg = ISC_BAY_CFG_GRGR, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SRGGB12, ++ .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, ++ .cfa_baycfg = ISC_BAY_CFG_RGRG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_GREY, ++ .mbus_code = MEDIA_BUS_FMT_Y8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUYV, ++ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_UYVY, ++ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_RGB565, ++ .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_Y10, ++ .mbus_code = MEDIA_BUS_FMT_Y10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ }, ++ ++}; ++ ++static void isc_sama7g5_config_csc(struct isc_device *isc) ++{ ++ struct regmap *regmap = isc->regmap; ++ ++ /* Convert RGB to YUV */ ++ regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, ++ 0x42 | (0x81 << 16)); ++ regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, ++ 0x19 | (0x10 << 16)); ++ regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, ++ 0xFDA | (0xFB6 << 16)); ++ regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, ++ 0x70 | (0x80 << 16)); ++ regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, ++ 0x70 | (0xFA2 << 16)); ++ regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, ++ 0xFEE | (0x80 << 16)); ++} ++ ++static void isc_sama7g5_config_cbc(struct isc_device *isc) ++{ ++ struct regmap *regmap = isc->regmap; ++ ++ /* Configure what is set via v4l2 ctrls */ ++ regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness); ++ regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast); ++ /* Configure Hue and Saturation as neutral midpoint */ ++ regmap_write(regmap, ISC_CBCHS_HUE, 0); ++ regmap_write(regmap, ISC_CBCHS_SAT, (1 << 4)); ++} ++ ++static void isc_sama7g5_config_cc(struct isc_device *isc) ++{ ++ struct regmap *regmap = isc->regmap; ++ ++ /* Configure each register at the neutral fixed point 1.0 or 0.0 */ ++ regmap_write(regmap, ISC_CC_RR_RG, (1 << 8)); ++ regmap_write(regmap, ISC_CC_RB_OR, 0); ++ regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16); ++ regmap_write(regmap, ISC_CC_GB_OG, 0); ++ regmap_write(regmap, ISC_CC_BR_BG, 0); ++ regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); ++} ++ ++static void isc_sama7g5_config_ctrls(struct isc_device *isc, ++ const struct v4l2_ctrl_ops *ops) ++{ ++ struct isc_ctrls *ctrls = &isc->ctrls; ++ struct v4l2_ctrl_handler *hdl = &ctrls->handler; ++ ++ ctrls->contrast = 16; ++ ++ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 16); ++} ++ ++static void isc_sama7g5_config_dpc(struct isc_device *isc) ++{ ++ u32 bay_cfg = isc->config.sd_format->cfa_baycfg; ++ struct regmap *regmap = isc->regmap; ++ ++ regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK, ++ (64 << ISC_DPC_CFG_BLOFF_SHIFT)); ++ regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK, ++ (bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT)); ++} ++ ++static void isc_sama7g5_config_gam(struct isc_device *isc) ++{ ++ struct regmap *regmap = isc->regmap; ++ ++ regmap_update_bits(regmap, ISC_GAM_CTRL, ISC_GAM_CTRL_BIPART, ++ ISC_GAM_CTRL_BIPART); ++} ++ ++static void isc_sama7g5_config_rlp(struct isc_device *isc) ++{ ++ struct regmap *regmap = isc->regmap; ++ u32 rlp_mode = isc->config.rlp_cfg_mode; ++ ++ regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, ++ ISC_RLP_CFG_MODE_MASK | ISC_RLP_CFG_LSH | ++ ISC_RLP_CFG_YMODE_MASK, rlp_mode); ++} ++ ++static void isc_sama7g5_adapt_pipeline(struct isc_device *isc) ++{ ++ isc->try_config.bits_pipeline &= ISC_SAMA7G5_PIPELINE; ++} ++ ++/* Gamma table with gamma 1/2.2 */ ++static const u32 isc_sama7g5_gamma_table[][GAMMA_ENTRIES] = { ++ /* index 0 --> gamma bipartite */ ++ { ++ 0x980, 0x4c0320, 0x650260, 0x7801e0, 0x8701a0, 0x940180, ++ 0xa00160, 0xab0120, 0xb40120, 0xbd0120, 0xc60100, 0xce0100, ++ 0xd600e0, 0xdd00e0, 0xe400e0, 0xeb00c0, 0xf100c0, 0xf700c0, ++ 0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0, ++ 0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080, ++ 0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a, ++ 0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030, ++ 0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026, ++ 0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020, ++ 0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c, ++ 0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a }, ++}; ++ ++static int xisc_parse_dt(struct device *dev, struct isc_device *isc) ++{ ++ struct device_node *np = dev->of_node; ++ struct device_node *epn = NULL; ++ struct isc_subdev_entity *subdev_entity; ++ unsigned int flags; ++ int ret; ++ bool mipi_mode; ++ ++ INIT_LIST_HEAD(&isc->subdev_entities); ++ ++ mipi_mode = of_property_read_bool(np, "microchip,mipi-mode"); ++ ++ while (1) { ++ struct v4l2_fwnode_endpoint v4l2_epn = { .bus_type = 0 }; ++ ++ epn = of_graph_get_next_endpoint(np, epn); ++ if (!epn) ++ return 0; ++ ++ ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn), ++ &v4l2_epn); ++ if (ret) { ++ ret = -EINVAL; ++ dev_err(dev, "Could not parse the endpoint\n"); ++ break; ++ } ++ ++ subdev_entity = devm_kzalloc(dev, sizeof(*subdev_entity), ++ GFP_KERNEL); ++ if (!subdev_entity) { ++ ret = -ENOMEM; ++ break; ++ } ++ subdev_entity->epn = epn; ++ ++ flags = v4l2_epn.bus.parallel.flags; ++ ++ if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) ++ subdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW; ++ ++ if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) ++ subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW; ++ ++ if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) ++ subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW; ++ ++ if (v4l2_epn.bus_type == V4L2_MBUS_BT656) ++ subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC | ++ ISC_PFE_CFG0_CCIR656; ++ ++ if (mipi_mode) ++ subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_MIPI; ++ ++ list_add_tail(&subdev_entity->list, &isc->subdev_entities); ++ } ++ of_node_put(epn); ++ ++ return ret; ++} ++ ++static int microchip_xisc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct isc_device *isc; ++ struct resource *res; ++ void __iomem *io_base; ++ struct isc_subdev_entity *subdev_entity; ++ int irq; ++ int ret; ++ u32 ver; ++ ++ isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL); ++ if (!isc) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, isc); ++ isc->dev = dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ io_base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(io_base)) ++ return PTR_ERR(io_base); ++ ++ isc->regmap = devm_regmap_init_mmio(dev, io_base, &isc_regmap_config); ++ if (IS_ERR(isc->regmap)) { ++ ret = PTR_ERR(isc->regmap); ++ dev_err(dev, "failed to init register map: %d\n", ret); ++ return ret; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return irq; ++ ++ ret = devm_request_irq(dev, irq, isc_interrupt, 0, ++ "microchip-sama7g5-xisc", isc); ++ if (ret < 0) { ++ dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", ++ irq, ret); ++ return ret; ++ } ++ ++ isc->gamma_table = isc_sama7g5_gamma_table; ++ isc->gamma_max = 0; ++ ++ isc->max_width = ISC_SAMA7G5_MAX_SUPPORT_WIDTH; ++ isc->max_height = ISC_SAMA7G5_MAX_SUPPORT_HEIGHT; ++ ++ isc->config_dpc = isc_sama7g5_config_dpc; ++ isc->config_csc = isc_sama7g5_config_csc; ++ isc->config_cbc = isc_sama7g5_config_cbc; ++ isc->config_cc = isc_sama7g5_config_cc; ++ isc->config_gam = isc_sama7g5_config_gam; ++ isc->config_rlp = isc_sama7g5_config_rlp; ++ isc->config_ctrls = isc_sama7g5_config_ctrls; ++ ++ isc->adapt_pipeline = isc_sama7g5_adapt_pipeline; ++ ++ isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; ++ isc->offsets.cbc = ISC_SAMA7G5_CBC_OFFSET; ++ isc->offsets.sub422 = ISC_SAMA7G5_SUB422_OFFSET; ++ isc->offsets.sub420 = ISC_SAMA7G5_SUB420_OFFSET; ++ isc->offsets.rlp = ISC_SAMA7G5_RLP_OFFSET; ++ isc->offsets.his = ISC_SAMA7G5_HIS_OFFSET; ++ isc->offsets.dma = ISC_SAMA7G5_DMA_OFFSET; ++ isc->offsets.version = ISC_SAMA7G5_VERSION_OFFSET; ++ isc->offsets.his_entry = ISC_SAMA7G5_HIS_ENTRY_OFFSET; ++ ++ isc->controller_formats = sama7g5_controller_formats; ++ isc->controller_formats_size = ARRAY_SIZE(sama7g5_controller_formats); ++ isc->formats_list = sama7g5_formats_list; ++ isc->formats_list_size = ARRAY_SIZE(sama7g5_formats_list); ++ ++ /* sama7g5-isc RAM access port is full AXI4 - 32 bits per beat */ ++ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32; ++ ++ ret = isc_pipeline_init(isc); ++ if (ret) ++ return ret; ++ ++ isc->hclock = devm_clk_get(dev, "hclock"); ++ if (IS_ERR(isc->hclock)) { ++ ret = PTR_ERR(isc->hclock); ++ dev_err(dev, "failed to get hclock: %d\n", ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(isc->hclock); ++ if (ret) { ++ dev_err(dev, "failed to enable hclock: %d\n", ret); ++ return ret; ++ } ++ ++ ret = isc_clk_init(isc); ++ if (ret) { ++ dev_err(dev, "failed to init isc clock: %d\n", ret); ++ goto unprepare_hclk; ++ } ++ ++ isc->ispck = isc->isc_clks[ISC_ISPCK].clk; ++ ++ ret = clk_prepare_enable(isc->ispck); ++ if (ret) { ++ dev_err(dev, "failed to enable ispck: %d\n", ret); ++ goto unprepare_hclk; ++ } ++ ++ /* ispck should be greater or equal to hclock */ ++ ret = clk_set_rate(isc->ispck, clk_get_rate(isc->hclock)); ++ if (ret) { ++ dev_err(dev, "failed to set ispck rate: %d\n", ret); ++ goto unprepare_clk; ++ } ++ ++ ret = v4l2_device_register(dev, &isc->v4l2_dev); ++ if (ret) { ++ dev_err(dev, "unable to register v4l2 device.\n"); ++ goto unprepare_clk; ++ } ++ ++ ret = xisc_parse_dt(dev, isc); ++ if (ret) { ++ dev_err(dev, "fail to parse device tree\n"); ++ goto unregister_v4l2_device; ++ } ++ ++ if (list_empty(&isc->subdev_entities)) { ++ dev_err(dev, "no subdev found\n"); ++ ret = -ENODEV; ++ goto unregister_v4l2_device; ++ } ++ ++ list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { ++ struct v4l2_async_subdev *asd; ++ ++ v4l2_async_notifier_init(&subdev_entity->notifier); ++ ++ asd = v4l2_async_notifier_add_fwnode_remote_subdev( ++ &subdev_entity->notifier, ++ of_fwnode_handle(subdev_entity->epn), ++ struct v4l2_async_subdev); ++ ++ of_node_put(subdev_entity->epn); ++ subdev_entity->epn = NULL; ++ ++ if (IS_ERR(asd)) { ++ ret = PTR_ERR(asd); ++ goto cleanup_subdev; ++ } ++ ++ subdev_entity->notifier.ops = &isc_async_ops; ++ ++ ret = v4l2_async_notifier_register(&isc->v4l2_dev, ++ &subdev_entity->notifier); ++ if (ret) { ++ dev_err(dev, "fail to register async notifier\n"); ++ goto cleanup_subdev; ++ } ++ ++ if (video_is_registered(&isc->video_dev)) ++ break; ++ } ++ ++ pm_runtime_set_active(dev); ++ pm_runtime_enable(dev); ++ pm_request_idle(dev); ++ ++ regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); ++ dev_info(dev, "Microchip XISC version %x\n", ver); ++ ++ return 0; ++ ++cleanup_subdev: ++ isc_subdev_cleanup(isc); ++ ++unregister_v4l2_device: ++ v4l2_device_unregister(&isc->v4l2_dev); ++ ++unprepare_clk: ++ clk_disable_unprepare(isc->ispck); ++unprepare_hclk: ++ clk_disable_unprepare(isc->hclock); ++ ++ isc_clk_cleanup(isc); ++ ++ return ret; ++} ++ ++static int microchip_xisc_remove(struct platform_device *pdev) ++{ ++ struct isc_device *isc = platform_get_drvdata(pdev); ++ ++ pm_runtime_disable(&pdev->dev); ++ ++ isc_subdev_cleanup(isc); ++ ++ v4l2_device_unregister(&isc->v4l2_dev); ++ ++ clk_disable_unprepare(isc->ispck); ++ clk_disable_unprepare(isc->hclock); ++ ++ isc_clk_cleanup(isc); ++ ++ return 0; ++} ++ ++static int __maybe_unused xisc_runtime_suspend(struct device *dev) ++{ ++ struct isc_device *isc = dev_get_drvdata(dev); ++ ++ clk_disable_unprepare(isc->ispck); ++ clk_disable_unprepare(isc->hclock); ++ ++ return 0; ++} ++ ++static int __maybe_unused xisc_runtime_resume(struct device *dev) ++{ ++ struct isc_device *isc = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = clk_prepare_enable(isc->hclock); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(isc->ispck); ++ if (ret) ++ clk_disable_unprepare(isc->hclock); ++ ++ return ret; ++} ++ ++static const struct dev_pm_ops microchip_xisc_dev_pm_ops = { ++ SET_RUNTIME_PM_OPS(xisc_runtime_suspend, xisc_runtime_resume, NULL) ++}; ++ ++static const struct of_device_id microchip_xisc_of_match[] = { ++ { .compatible = "microchip,sama7g5-isc" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, microchip_xisc_of_match); ++ ++static struct platform_driver microchip_xisc_driver = { ++ .probe = microchip_xisc_probe, ++ .remove = microchip_xisc_remove, ++ .driver = { ++ .name = "microchip-sama7g5-xisc", ++ .pm = µchip_xisc_dev_pm_ops, ++ .of_match_table = of_match_ptr(microchip_xisc_of_match), ++ }, ++}; ++ ++module_platform_driver(microchip_xisc_driver); ++ ++MODULE_AUTHOR("Eugen Hristev "); ++MODULE_DESCRIPTION("The V4L2 driver for Microchip-XISC"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/at91/patches-5.15/186-ASoC-atmel-fix-shadowed-variable.patch b/target/linux/at91/patches-5.15/186-ASoC-atmel-fix-shadowed-variable.patch new file mode 100644 index 0000000000..7e88bb39ce --- /dev/null +++ b/target/linux/at91/patches-5.15/186-ASoC-atmel-fix-shadowed-variable.patch @@ -0,0 +1,48 @@ +From 1b41c69264d7233a3e9a0aa36333ee22a5a049e9 Mon Sep 17 00:00:00 2001 +From: Pierre-Louis Bossart +Date: Fri, 26 Mar 2021 16:59:12 -0500 +Subject: [PATCH 186/247] ASoC: atmel: fix shadowed variable + +Fix cppcheck warning: + +sound/soc/atmel/atmel-classd.c:51:14: style: Local variable 'pwm_type' +shadows outer variable [shadowVariable] + const char *pwm_type; + ^ +sound/soc/atmel/atmel-classd.c:226:27: note: Shadowed declaration +static const char * const pwm_type[] = { + ^ +sound/soc/atmel/atmel-classd.c:51:14: note: Shadow variable + const char *pwm_type; + ^ + +Signed-off-by: Pierre-Louis Bossart +Reviewed-by: Codrin Ciubotariu +Link: https://lore.kernel.org/r/20210326215927.936377-3-pierre-louis.bossart@linux.intel.com +Signed-off-by: Mark Brown +--- + sound/soc/atmel/atmel-classd.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/sound/soc/atmel/atmel-classd.c ++++ b/sound/soc/atmel/atmel-classd.c +@@ -48,7 +48,7 @@ static struct atmel_classd_pdata *atmel_ + { + struct device_node *np = dev->of_node; + struct atmel_classd_pdata *pdata; +- const char *pwm_type; ++ const char *pwm_type_s; + int ret; + + if (!np) { +@@ -60,8 +60,8 @@ static struct atmel_classd_pdata *atmel_ + if (!pdata) + return ERR_PTR(-ENOMEM); + +- ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type); +- if ((ret == 0) && (strcmp(pwm_type, "diff") == 0)) ++ ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type_s); ++ if ((ret == 0) && (strcmp(pwm_type_s, "diff") == 0)) + pdata->pwm_type = CLASSD_MR_PWMTYP_DIFF; + else + pdata->pwm_type = CLASSD_MR_PWMTYP_SINGLE; diff --git a/target/linux/at91/patches-5.15/187-ASoC-atmel-atmel-i2s-remove-useless-initialization.patch b/target/linux/at91/patches-5.15/187-ASoC-atmel-atmel-i2s-remove-useless-initialization.patch new file mode 100644 index 0000000000..ed2ae1a979 --- /dev/null +++ b/target/linux/at91/patches-5.15/187-ASoC-atmel-atmel-i2s-remove-useless-initialization.patch @@ -0,0 +1,36 @@ +From e53725fe0c7e6b52927280272f49fe5f4b4ef317 Mon Sep 17 00:00:00 2001 +From: Pierre-Louis Bossart +Date: Fri, 26 Mar 2021 16:59:13 -0500 +Subject: [PATCH 187/247] ASoC: atmel: atmel-i2s: remove useless initialization + +Cppcheck complains: + +sound/soc/atmel/atmel-i2s.c:628:6: style: Redundant initialization for 'err'. The initialized value is overwritten before it is read. [redundantInitialization] + err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0, + ^ +sound/soc/atmel/atmel-i2s.c:598:10: note: err is initialized + int err = -ENXIO; + ^ +sound/soc/atmel/atmel-i2s.c:628:6: note: err is overwritten + err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0, + ^ + +Signed-off-by: Pierre-Louis Bossart +Reviewed-by: Codrin Ciubotariu +Link: https://lore.kernel.org/r/20210326215927.936377-4-pierre-louis.bossart@linux.intel.com +Signed-off-by: Mark Brown +--- + sound/soc/atmel/atmel-i2s.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/sound/soc/atmel/atmel-i2s.c ++++ b/sound/soc/atmel/atmel-i2s.c +@@ -613,7 +613,7 @@ static int atmel_i2s_probe(struct platfo + struct regmap *regmap; + void __iomem *base; + int irq; +- int err = -ENXIO; ++ int err; + unsigned int pcm_flags = 0; + unsigned int version; + diff --git a/target/linux/at91/patches-5.15/188-ASoC-atmel-i2s-Set-symmetric-sample-bits.patch b/target/linux/at91/patches-5.15/188-ASoC-atmel-i2s-Set-symmetric-sample-bits.patch new file mode 100644 index 0000000000..bc8c7fa2b1 --- /dev/null +++ b/target/linux/at91/patches-5.15/188-ASoC-atmel-i2s-Set-symmetric-sample-bits.patch @@ -0,0 +1,26 @@ +From a6f337fdf68294cfae233724567cbeea0ae5148f Mon Sep 17 00:00:00 2001 +From: Codrin Ciubotariu +Date: Fri, 18 Jun 2021 18:07:40 +0300 +Subject: [PATCH 188/247] ASoC: atmel-i2s: Set symmetric sample bits + +The I2S needs to have the same sample bits for both capture and playback +streams. + +Fixes: b543e467d1a9 ("ASoC: atmel-i2s: add driver for the new Atmel I2S controller") +Signed-off-by: Codrin Ciubotariu +Link: https://lore.kernel.org/r/20210618150741.401739-1-codrin.ciubotariu@microchip.com +Signed-off-by: Mark Brown +--- + sound/soc/atmel/atmel-i2s.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/sound/soc/atmel/atmel-i2s.c ++++ b/sound/soc/atmel/atmel-i2s.c +@@ -560,6 +560,7 @@ static struct snd_soc_dai_driver atmel_i + }, + .ops = &atmel_i2s_dai_ops, + .symmetric_rates = 1, ++ .symmetric_samplebits = 1, + }; + + static const struct snd_soc_component_driver atmel_i2s_component = { diff --git a/target/linux/at91/patches-5.15/189-watchdog-sama5d4_wdt-add-support-for-sama7g5-wdt.patch b/target/linux/at91/patches-5.15/189-watchdog-sama5d4_wdt-add-support-for-sama7g5-wdt.patch new file mode 100644 index 0000000000..b79ccadf92 --- /dev/null +++ b/target/linux/at91/patches-5.15/189-watchdog-sama5d4_wdt-add-support-for-sama7g5-wdt.patch @@ -0,0 +1,46 @@ +From ff83cc9f95aaba75991210312061b7fe52aaa400 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Thu, 27 May 2021 13:01:19 +0300 +Subject: [PATCH 189/247] watchdog: sama5d4_wdt: add support for sama7g5-wdt + +Add support for compatible sama7g5-wdt. +The sama7g5 wdt is the same hardware block as on sam9x60. +Adapt the driver to use the sam9x60/sama7g5 variant if either +of the two compatibles are selected (sam9x60-wdt/sama7g5-wdt). + +Signed-off-by: Eugen Hristev +Acked-by: Nicolas Ferre +Reviewed-by: Guenter Roeck +Link: https://lore.kernel.org/r/20210527100120.266796-2-eugen.hristev@microchip.com +Signed-off-by: Guenter Roeck +Signed-off-by: Wim Van Sebroeck +--- + drivers/watchdog/sama5d4_wdt.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/watchdog/sama5d4_wdt.c ++++ b/drivers/watchdog/sama5d4_wdt.c +@@ -268,8 +268,10 @@ static int sama5d4_wdt_probe(struct plat + wdd->min_timeout = MIN_WDT_TIMEOUT; + wdd->max_timeout = MAX_WDT_TIMEOUT; + wdt->last_ping = jiffies; +- wdt->sam9x60_support = of_device_is_compatible(dev->of_node, +- "microchip,sam9x60-wdt"); ++ ++ if (of_device_is_compatible(dev->of_node, "microchip,sam9x60-wdt") || ++ of_device_is_compatible(dev->of_node, "microchip,sama7g5-wdt")) ++ wdt->sam9x60_support = true; + + watchdog_set_drvdata(wdd, wdt); + +@@ -329,6 +331,10 @@ static const struct of_device_id sama5d4 + { + .compatible = "microchip,sam9x60-wdt", + }, ++ { ++ .compatible = "microchip,sama7g5-wdt", ++ }, ++ + { } + }; + MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match); diff --git a/target/linux/at91/patches-5.15/190-media-atmel-fix-build-when-ISC-m-and-XISC-y.patch b/target/linux/at91/patches-5.15/190-media-atmel-fix-build-when-ISC-m-and-XISC-y.patch new file mode 100644 index 0000000000..60b4104442 --- /dev/null +++ b/target/linux/at91/patches-5.15/190-media-atmel-fix-build-when-ISC-m-and-XISC-y.patch @@ -0,0 +1,135 @@ +From dfcc0395f5e838c0b5c3fb93c9335b6a8892178a Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Mon, 5 Jul 2021 14:57:08 +0200 +Subject: [PATCH 190/247] media: atmel: fix build when ISC=m and XISC=y + +Building VIDEO_ATMEL_ISC as module and VIDEO_ATMEL_XISC as built-in +(or viceversa) causes build errors: + + or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o: in function `isc_async_complete': + atmel-isc-base.c:(.text+0x40d0): undefined reference to `__this_module' + or1k-linux-ld: atmel-isc-base.c:(.text+0x40f0): undefined reference to `__this_module' + or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(.rodata+0x390): undefined reference to `__this_module' + or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(__param+0x4): undefined reference to `__this_module' + or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(__param+0x18): undefined reference to `__this_module' + +This is caused by the file atmel-isc-base.c which is common code between +the two drivers. + +The solution is to create another Kconfig symbol that is automatically +selected and generates the module atmel-isc-base.ko. This module can be +loaded when both drivers are modules, or built-in when at least one of them +is built-in. + +Reported-by: kernel test robot +Fixes: c9aa973884a1 ("media: atmel: atmel-isc: add microchip-xisc driver") +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/Kconfig | 8 ++++++++ + drivers/media/platform/atmel/Makefile | 5 +++-- + drivers/media/platform/atmel/atmel-isc-base.c | 11 +++++++++++ + 3 files changed, 22 insertions(+), 2 deletions(-) + +--- a/drivers/media/platform/atmel/Kconfig ++++ b/drivers/media/platform/atmel/Kconfig +@@ -8,6 +8,7 @@ config VIDEO_ATMEL_ISC + select VIDEOBUF2_DMA_CONTIG + select REGMAP_MMIO + select V4L2_FWNODE ++ select VIDEO_ATMEL_ISC_BASE + help + This module makes the ATMEL Image Sensor Controller available + as a v4l2 device. +@@ -19,10 +20,17 @@ config VIDEO_ATMEL_XISC + select VIDEOBUF2_DMA_CONTIG + select REGMAP_MMIO + select V4L2_FWNODE ++ select VIDEO_ATMEL_ISC_BASE + help + This module makes the ATMEL eXtended Image Sensor Controller + available as a v4l2 device. + ++config VIDEO_ATMEL_ISC_BASE ++ tristate ++ default n ++ help ++ ATMEL ISC and XISC common code base. ++ + config VIDEO_ATMEL_ISI + tristate "ATMEL Image Sensor Interface (ISI) support" + depends on VIDEO_V4L2 && OF +--- a/drivers/media/platform/atmel/Makefile ++++ b/drivers/media/platform/atmel/Makefile +@@ -1,7 +1,8 @@ + # SPDX-License-Identifier: GPL-2.0-only +-atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o +-atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o ++atmel-isc-objs = atmel-sama5d2-isc.o ++atmel-xisc-objs = atmel-sama7g5-isc.o + + obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o ++obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += atmel-isc-base.o + obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o + obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -378,6 +378,7 @@ int isc_clk_init(struct isc_device *isc) + + return 0; + } ++EXPORT_SYMBOL_GPL(isc_clk_init); + + void isc_clk_cleanup(struct isc_device *isc) + { +@@ -392,6 +393,7 @@ void isc_clk_cleanup(struct isc_device * + clk_unregister(isc_clk->clk); + } + } ++EXPORT_SYMBOL_GPL(isc_clk_cleanup); + + static int isc_queue_setup(struct vb2_queue *vq, + unsigned int *nbuffers, unsigned int *nplanes, +@@ -1575,6 +1577,7 @@ irqreturn_t isc_interrupt(int irq, void + + return ret; + } ++EXPORT_SYMBOL_GPL(isc_interrupt); + + static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max) + { +@@ -2209,6 +2212,7 @@ const struct v4l2_async_notifier_operati + .unbind = isc_async_unbind, + .complete = isc_async_complete, + }; ++EXPORT_SYMBOL_GPL(isc_async_ops); + + void isc_subdev_cleanup(struct isc_device *isc) + { +@@ -2221,6 +2225,7 @@ void isc_subdev_cleanup(struct isc_devic + + INIT_LIST_HEAD(&isc->subdev_entities); + } ++EXPORT_SYMBOL_GPL(isc_subdev_cleanup); + + int isc_pipeline_init(struct isc_device *isc) + { +@@ -2261,6 +2266,7 @@ int isc_pipeline_init(struct isc_device + + return 0; + } ++EXPORT_SYMBOL_GPL(isc_pipeline_init); + + /* regmap configuration */ + #define ATMEL_ISC_REG_MAX 0xd5c +@@ -2270,4 +2276,9 @@ const struct regmap_config isc_regmap_co + .val_bits = 32, + .max_register = ATMEL_ISC_REG_MAX, + }; ++EXPORT_SYMBOL_GPL(isc_regmap_config); + ++MODULE_AUTHOR("Songjun Wu"); ++MODULE_AUTHOR("Eugen Hristev"); ++MODULE_DESCRIPTION("Atmel ISC common code base"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/at91/patches-5.15/191-i2c-at91-remove-define-CONFIG_PM.patch b/target/linux/at91/patches-5.15/191-i2c-at91-remove-define-CONFIG_PM.patch new file mode 100644 index 0000000000..27ee1b6d19 --- /dev/null +++ b/target/linux/at91/patches-5.15/191-i2c-at91-remove-define-CONFIG_PM.patch @@ -0,0 +1,76 @@ +From 023a6b46536dce41f2c5a7425826fc4da4509b8f Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 5 Jul 2021 15:15:16 +0300 +Subject: [PATCH 191/247] i2c: at91: remove #define CONFIG_PM + +Remove #define CONFIG_PM and use __maybe_unused for PM functions and +pm_ptr() for PM ops. + +Signed-off-by: Claudiu Beznea +Reviewed-by: Codrin Ciubotariu +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-at91-core.c | 17 +++++------------ + 1 file changed, 5 insertions(+), 12 deletions(-) + +--- a/drivers/i2c/busses/i2c-at91-core.c ++++ b/drivers/i2c/busses/i2c-at91-core.c +@@ -286,9 +286,7 @@ static int at91_twi_remove(struct platfo + return 0; + } + +-#ifdef CONFIG_PM +- +-static int at91_twi_runtime_suspend(struct device *dev) ++static int __maybe_unused at91_twi_runtime_suspend(struct device *dev) + { + struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); + +@@ -299,7 +297,7 @@ static int at91_twi_runtime_suspend(stru + return 0; + } + +-static int at91_twi_runtime_resume(struct device *dev) ++static int __maybe_unused at91_twi_runtime_resume(struct device *dev) + { + struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); + +@@ -308,7 +306,7 @@ static int at91_twi_runtime_resume(struc + return clk_prepare_enable(twi_dev->clk); + } + +-static int at91_twi_suspend_noirq(struct device *dev) ++static int __maybe_unused at91_twi_suspend_noirq(struct device *dev) + { + if (!pm_runtime_status_suspended(dev)) + at91_twi_runtime_suspend(dev); +@@ -316,7 +314,7 @@ static int at91_twi_suspend_noirq(struct + return 0; + } + +-static int at91_twi_resume_noirq(struct device *dev) ++static int __maybe_unused at91_twi_resume_noirq(struct device *dev) + { + struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); + int ret; +@@ -342,11 +340,6 @@ static const struct dev_pm_ops at91_twi_ + .runtime_resume = at91_twi_runtime_resume, + }; + +-#define at91_twi_pm_ops (&at91_twi_pm) +-#else +-#define at91_twi_pm_ops NULL +-#endif +- + static struct platform_driver at91_twi_driver = { + .probe = at91_twi_probe, + .remove = at91_twi_remove, +@@ -354,7 +347,7 @@ static struct platform_driver at91_twi_d + .driver = { + .name = "at91_i2c", + .of_match_table = of_match_ptr(atmel_twi_dt_ids), +- .pm = at91_twi_pm_ops, ++ .pm = pm_ptr(&at91_twi_pm), + }, + }; + diff --git a/target/linux/at91/patches-5.15/192-ASoC-codecs-ad193x-add-support-for-96kHz-and-192kHz-.patch b/target/linux/at91/patches-5.15/192-ASoC-codecs-ad193x-add-support-for-96kHz-and-192kHz-.patch new file mode 100644 index 0000000000..6220c1dab2 --- /dev/null +++ b/target/linux/at91/patches-5.15/192-ASoC-codecs-ad193x-add-support-for-96kHz-and-192kHz-.patch @@ -0,0 +1,91 @@ +From 1c906a59a60887e1b997ebab63f19f33a1c69a3e Mon Sep 17 00:00:00 2001 +From: Codrin Ciubotariu +Date: Tue, 3 Aug 2021 13:48:25 +0300 +Subject: [PATCH 192/247] ASoC: codecs: ad193x: add support for 96kHz and + 192kHz playback rates + +ad193x devices support 96KHz and 192KHz sampling rates, when PLL/MCLK is +referenced to 48kHz. +Tested on ad1934. + +Signed-off-by: Codrin Ciubotariu +Link: https://lore.kernel.org/r/20210803104825.2198335-1-codrin.ciubotariu@microchip.com +Signed-off-by: Mark Brown +--- + sound/soc/codecs/ad193x.c | 30 ++++++++++++++++++++++++++++-- + sound/soc/codecs/ad193x.h | 4 ++++ + 2 files changed, 32 insertions(+), 2 deletions(-) + +--- a/sound/soc/codecs/ad193x.c ++++ b/sound/soc/codecs/ad193x.c +@@ -316,6 +316,13 @@ static int ad193x_hw_params(struct snd_p + int word_len = 0, master_rate = 0; + struct snd_soc_component *component = dai->component; + struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(component); ++ bool is_playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; ++ u8 dacc0; ++ ++ dev_dbg(dai->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", ++ __func__, params_rate(params), params_format(params), ++ params_width(params), params_channels(params)); ++ + + /* bit size */ + switch (params_width(params)) { +@@ -346,6 +353,25 @@ static int ad193x_hw_params(struct snd_p + break; + } + ++ if (is_playback) { ++ switch (params_rate(params)) { ++ case 48000: ++ dacc0 = AD193X_DAC_SR_48; ++ break; ++ case 96000: ++ dacc0 = AD193X_DAC_SR_96; ++ break; ++ case 192000: ++ dacc0 = AD193X_DAC_SR_192; ++ break; ++ default: ++ dev_err(dai->dev, "invalid sampling rate: %d\n", params_rate(params)); ++ return -EINVAL; ++ } ++ ++ regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL0, AD193X_DAC_SR_MASK, dacc0); ++ } ++ + regmap_update_bits(ad193x->regmap, AD193X_PLL_CLK_CTRL0, + AD193X_PLL_INPUT_MASK, master_rate); + +@@ -385,7 +411,7 @@ static struct snd_soc_dai_driver ad193x_ + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 8, +- .rates = SNDRV_PCM_RATE_48000, ++ .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE, + }, +@@ -407,7 +433,7 @@ static struct snd_soc_dai_driver ad193x_ + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 8, +- .rates = SNDRV_PCM_RATE_48000, ++ .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE, + }, +--- a/sound/soc/codecs/ad193x.h ++++ b/sound/soc/codecs/ad193x.h +@@ -37,6 +37,10 @@ int ad193x_probe(struct device *dev, str + #define AD193X_PLL_CLK_SRC_MCLK (1 << 1) + #define AD193X_DAC_CTRL0 0x02 + #define AD193X_DAC_POWERDOWN 0x01 ++#define AD193X_DAC_SR_MASK 0x06 ++#define AD193X_DAC_SR_48 (0 << 1) ++#define AD193X_DAC_SR_96 (1 << 1) ++#define AD193X_DAC_SR_192 (2 << 1) + #define AD193X_DAC_SERFMT_MASK 0xC0 + #define AD193X_DAC_SERFMT_STEREO (0 << 6) + #define AD193X_DAC_SERFMT_TDM (1 << 6) diff --git a/target/linux/at91/patches-5.15/193-media-atmel-atmel-sama5d2-isc-fix-YUYV-format.patch b/target/linux/at91/patches-5.15/193-media-atmel-atmel-sama5d2-isc-fix-YUYV-format.patch new file mode 100644 index 0000000000..a554a288a5 --- /dev/null +++ b/target/linux/at91/patches-5.15/193-media-atmel-atmel-sama5d2-isc-fix-YUYV-format.patch @@ -0,0 +1,48 @@ +From 21261e30679118b96ed537d1cdf9e12682fc1b29 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Wed, 9 Jun 2021 15:00:28 +0200 +Subject: [PATCH 193/247] media: atmel: atmel-sama5d2-isc: fix YUYV format + +SAMA5D2 does not have the YCYC field for the RLP (rounding, limiting, +packaging) module. +The YCYC field is supposed to work with interleaved YUV formats like YUYV. +In SAMA5D2, we have to use YYCC field, which is used for both planar +formats like YUV420 and interleaved formats like YUYV. +Fix the according rlp callback to replace the generic YCYC field (which +makes more sense from a logical point of view) with the required YYCC +field. + +Fixes: debfa496871c ("media: atmel: atmel-isc-base: add support for more formats and additional pipeline modules") +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + .../media/platform/atmel/atmel-sama5d2-isc.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -255,6 +255,23 @@ static void isc_sama5d2_config_rlp(struc + struct regmap *regmap = isc->regmap; + u32 rlp_mode = isc->config.rlp_cfg_mode; + ++ /* ++ * In sama5d2, the YUV planar modes and the YUYV modes are treated ++ * in the same way in RLP register. ++ * Normally, YYCC mode should be Luma(n) - Color B(n) - Color R (n) ++ * and YCYC should be Luma(n + 1) - Color B (n) - Luma (n) - Color R (n) ++ * but in sama5d2, the YCYC mode does not exist, and YYCC must be ++ * selected for both planar and interleaved modes, as in fact ++ * both modes are supported. ++ * ++ * Thus, if the YCYC mode is selected, replace it with the ++ * sama5d2-compliant mode which is YYCC . ++ */ ++ if ((rlp_mode & ISC_RLP_CFG_MODE_YCYC) == ISC_RLP_CFG_MODE_YCYC) { ++ rlp_mode &= ~ISC_RLP_CFG_MODE_MASK; ++ rlp_mode |= ISC_RLP_CFG_MODE_YYCC; ++ } ++ + regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, + ISC_RLP_CFG_MODE_MASK, rlp_mode); + } diff --git a/target/linux/at91/patches-5.15/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch b/target/linux/at91/patches-5.15/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch new file mode 100644 index 0000000000..dd221f5be9 --- /dev/null +++ b/target/linux/at91/patches-5.15/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch @@ -0,0 +1,51 @@ +From 602f85ff15d45bd313f8f6600d72202a50fd83a9 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 19 Jul 2021 11:03:17 +0300 +Subject: [PATCH 194/247] clk: at91: add register definition for sama7g5's + master clock + +Add register definitions for SAMA7G5's master clock. These would be +also used by architecture specific power saving code. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210719080317.1045832-3-claudiu.beznea@microchip.com +--- + include/linux/clk/at91_pmc.h | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +--- a/include/linux/clk/at91_pmc.h ++++ b/include/linux/clk/at91_pmc.h +@@ -137,6 +137,32 @@ + #define AT91_PMC_PLLADIV2_ON (1 << 12) + #define AT91_PMC_H32MXDIV BIT(24) + ++#define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */ ++#define AT91_PMC_MCR_V2_ID_MSK (0xF) ++#define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MSK) ++#define AT91_PMC_MCR_V2_CMD (1 << 7) ++#define AT91_PMC_MCR_V2_DIV (7 << 8) ++#define AT91_PMC_MCR_V2_DIV1 (0 << 8) ++#define AT91_PMC_MCR_V2_DIV2 (1 << 8) ++#define AT91_PMC_MCR_V2_DIV4 (2 << 8) ++#define AT91_PMC_MCR_V2_DIV8 (3 << 8) ++#define AT91_PMC_MCR_V2_DIV16 (4 << 8) ++#define AT91_PMC_MCR_V2_DIV32 (5 << 8) ++#define AT91_PMC_MCR_V2_DIV64 (6 << 8) ++#define AT91_PMC_MCR_V2_DIV3 (7 << 8) ++#define AT91_PMC_MCR_V2_CSS (0x1F << 16) ++#define AT91_PMC_MCR_V2_CSS_MD_SLCK (0 << 16) ++#define AT91_PMC_MCR_V2_CSS_TD_SLCK (1 << 16) ++#define AT91_PMC_MCR_V2_CSS_MAINCK (2 << 16) ++#define AT91_PMC_MCR_V2_CSS_MCK0 (3 << 16) ++#define AT91_PMC_MCR_V2_CSS_SYSPLL (5 << 16) ++#define AT91_PMC_MCR_V2_CSS_DDRPLL (6 << 16) ++#define AT91_PMC_MCR_V2_CSS_IMGPLL (7 << 16) ++#define AT91_PMC_MCR_V2_CSS_BAUDPLL (8 << 16) ++#define AT91_PMC_MCR_V2_CSS_AUDIOPLL (9 << 16) ++#define AT91_PMC_MCR_V2_CSS_ETHPLL (10 << 16) ++#define AT91_PMC_MCR_V2_EN (1 << 28) ++ + #define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */ + + #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ diff --git a/target/linux/at91/patches-5.15/195-ARM-at91-add-new-SoC-sama7g5.patch b/target/linux/at91/patches-5.15/195-ARM-at91-add-new-SoC-sama7g5.patch new file mode 100644 index 0000000000..1d6b45ac94 --- /dev/null +++ b/target/linux/at91/patches-5.15/195-ARM-at91-add-new-SoC-sama7g5.patch @@ -0,0 +1,49 @@ +From 32bac6971d0572f67758f9a8c8af7bf4592f1675 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Fri, 9 Apr 2021 14:31:15 +0300 +Subject: [PATCH 195/247] ARM: at91: add new SoC sama7g5 + +Add new SoC from at91 family : sama7g5 + +Signed-off-by: Eugen Hristev +[claudiu.beznea@microchip.com: Select PLL, generic clock and UTMI support, add PM configs] +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210409113116.482199-1-eugen.hristev@microchip.com +Link: https://lore.kernel.org/r/20210719080317.1045832-2-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/Kconfig | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -57,6 +57,16 @@ config SOC_SAMA5D4 + help + Select this if you are using one of Microchip's SAMA5D4 family SoC. + ++config SOC_SAMA7G5 ++ bool "SAMA7G5 family" ++ depends on ARCH_MULTI_V7 ++ select HAVE_AT91_GENERATED_CLK ++ select HAVE_AT91_SAM9X60_PLL ++ select HAVE_AT91_UTMI ++ select SOC_SAMA7 ++ help ++ Select this if you are using one of Microchip's SAMA7G5 family SoC. ++ + config SOC_AT91RM9200 + bool "AT91RM9200" + depends on ARCH_MULTI_V4T +@@ -191,4 +201,12 @@ config SOC_SAMA5 + config ATMEL_PM + bool + ++config SOC_SAMA7 ++ bool ++ select ARM_GIC ++ select ATMEL_PM if PM ++ select ATMEL_SDRAMC ++ select MEMORY ++ select SOC_SAM_V7 ++ select SRAM if PM + endif diff --git a/target/linux/at91/patches-5.15/196-ARM-at91-debug-add-sama7g5-low-level-debug-uart.patch b/target/linux/at91/patches-5.15/196-ARM-at91-debug-add-sama7g5-low-level-debug-uart.patch new file mode 100644 index 0000000000..c99a2d5219 --- /dev/null +++ b/target/linux/at91/patches-5.15/196-ARM-at91-debug-add-sama7g5-low-level-debug-uart.patch @@ -0,0 +1,50 @@ +From 3de4879bf59b46a966ea226a67df70b88f43a23e Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Fri, 9 Apr 2021 14:31:16 +0300 +Subject: [PATCH 196/247] ARM: at91: debug: add sama7g5 low level debug uart + +Add sama7g5 SoC debug uart on Flexcom3. This is the UART that the +ROM bootloader uses. + +Signed-off-by: Eugen Hristev +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210409113116.482199-2-eugen.hristev@microchip.com +[claudiu.beznea: adapt to v5.10.27] +Signed-off-by: Claudiu Beznea +--- + arch/arm/Kconfig.debug | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm/Kconfig.debug ++++ b/arch/arm/Kconfig.debug +@@ -191,6 +191,14 @@ choice + their output to the USART1 port on SAMV7 based + machines. + ++ config DEBUG_AT91_SAMA7G5_FLEXCOM3 ++ bool "Kernel low-level debugging on SAMA7G5 FLEXCOM3" ++ select DEBUG_AT91_UART ++ depends on SOC_SAMA7G5 ++ help ++ Say Y here if you want kernel low-level debugging support ++ on the FLEXCOM3 port of SAMA7G5. ++ + config DEBUG_BCM2835 + bool "Kernel low-level debugging on BCM2835 PL011 UART" + depends on ARCH_BCM2835 && ARCH_MULTI_V6 +@@ -1731,6 +1739,7 @@ config DEBUG_UART_PHYS + default 0xd4017000 if DEBUG_MMP_UART2 + default 0xd4018000 if DEBUG_MMP_UART3 + default 0xe0000000 if DEBUG_SPEAR13XX ++ default 0xe1824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3 + default 0xe4007000 if DEBUG_HIP04_UART + default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0 + default 0xe6c50000 if DEBUG_RMOBILE_SCIFA1 +@@ -1791,6 +1800,7 @@ config DEBUG_UART_VIRT + default 0xc8912000 if DEBUG_RV1108_UART0 + default 0xe0010fe0 if ARCH_RPC + default 0xf0000be0 if ARCH_EBSA110 ++ default 0xe0824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3 + default 0xf0010000 if DEBUG_ASM9260_UART + default 0xf0100000 if DEBUG_DIGICOLOR_UA0 + default 0xf01fb000 if DEBUG_NOMADIK_UART diff --git a/target/linux/at91/patches-5.15/197-ARM-at91-pm-move-pm_bu-to-soc_pm-data-structure.patch b/target/linux/at91/patches-5.15/197-ARM-at91-pm-move-pm_bu-to-soc_pm-data-structure.patch new file mode 100644 index 0000000000..dfd47d55d2 --- /dev/null +++ b/target/linux/at91/patches-5.15/197-ARM-at91-pm-move-pm_bu-to-soc_pm-data-structure.patch @@ -0,0 +1,87 @@ +From e41d00bdaa31b36fd314e927104082615aa4643a Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:47 +0300 +Subject: [PATCH 197/247] ARM: at91: pm: move pm_bu to soc_pm data structure + +Move pm_bu to soc_pm data structure. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-2-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 34 +++++++++++++++++++++------------- + 1 file changed, 21 insertions(+), 13 deletions(-) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -27,10 +27,25 @@ + #include "generic.h" + #include "pm.h" + ++/** ++ * struct at91_pm_bu - AT91 power management backup unit data structure ++ * @suspended: true if suspended to backup mode ++ * @reserved: reserved ++ * @canary: canary data for memory checking after exit from backup mode ++ * @resume: resume API ++ */ ++struct at91_pm_bu { ++ int suspended; ++ unsigned long reserved; ++ phys_addr_t canary; ++ phys_addr_t resume; ++}; ++ + struct at91_soc_pm { + int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); + int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); + const struct of_device_id *ws_ids; ++ struct at91_pm_bu *bu; + struct at91_pm_data data; + }; + +@@ -71,13 +86,6 @@ static int at91_pm_valid_state(suspend_s + + static int canary = 0xA5A5A5A5; + +-static struct at91_pm_bu { +- int suspended; +- unsigned long reserved; +- phys_addr_t canary; +- phys_addr_t resume; +-} *pm_bu; +- + struct wakeup_source_info { + unsigned int pmc_fsmr_bit; + unsigned int shdwc_mr_bit; +@@ -288,7 +296,7 @@ static int at91_suspend_finish(unsigned + static void at91_pm_suspend(suspend_state_t state) + { + if (soc_pm.data.mode == AT91_PM_BACKUP) { +- pm_bu->suspended = 1; ++ soc_pm.bu->suspended = 1; + + cpu_suspend(0, at91_suspend_finish); + +@@ -672,16 +680,16 @@ static int __init at91_pm_backup_init(vo + goto securam_fail; + } + +- pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); +- if (!pm_bu) { ++ soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); ++ if (!soc_pm.bu) { + pr_warn("%s: unable to alloc securam!\n", __func__); + ret = -ENOMEM; + goto securam_fail; + } + +- pm_bu->suspended = 0; +- pm_bu->canary = __pa_symbol(&canary); +- pm_bu->resume = __pa_symbol(cpu_resume); ++ soc_pm.bu->suspended = 0; ++ soc_pm.bu->canary = __pa_symbol(&canary); ++ soc_pm.bu->resume = __pa_symbol(cpu_resume); + + return 0; + diff --git a/target/linux/at91/patches-5.15/198-ARM-at91-pm-move-the-setup-of-soc_pm.bu-suspended.patch b/target/linux/at91/patches-5.15/198-ARM-at91-pm-move-the-setup-of-soc_pm.bu-suspended.patch new file mode 100644 index 0000000000..5b484b7343 --- /dev/null +++ b/target/linux/at91/patches-5.15/198-ARM-at91-pm-move-the-setup-of-soc_pm.bu-suspended.patch @@ -0,0 +1,55 @@ +From c8f2a8aaae41fa0a40ad88855ae82696098230d7 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:48 +0300 +Subject: [PATCH 198/247] ARM: at91: pm: move the setup of soc_pm.bu->suspended + +Move the setup of soc_pm.bu->suspended in platform_suspend::begin +function so that the PMC code in charge with clocks suspend/resume +to differentiate b/w standard PM mode and backup mode. + +Signed-off-by: Claudiu Beznea +Reviewed-by: Alexandre Belloni +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-3-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 15 ++++++++++++--- + 1 file changed, 12 insertions(+), 3 deletions(-) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -214,6 +214,8 @@ static int at91_sam9x60_config_pmc_ws(vo + */ + static int at91_pm_begin(suspend_state_t state) + { ++ int ret; ++ + switch (state) { + case PM_SUSPEND_MEM: + soc_pm.data.mode = soc_pm.data.suspend_mode; +@@ -227,7 +229,16 @@ static int at91_pm_begin(suspend_state_t + soc_pm.data.mode = -1; + } + +- return at91_pm_config_ws(soc_pm.data.mode, true); ++ ret = at91_pm_config_ws(soc_pm.data.mode, true); ++ if (ret) ++ return ret; ++ ++ if (soc_pm.data.mode == AT91_PM_BACKUP) ++ soc_pm.bu->suspended = 1; ++ else if (soc_pm.bu) ++ soc_pm.bu->suspended = 0; ++ ++ return 0; + } + + /* +@@ -296,8 +307,6 @@ static int at91_suspend_finish(unsigned + static void at91_pm_suspend(suspend_state_t state) + { + if (soc_pm.data.mode == AT91_PM_BACKUP) { +- soc_pm.bu->suspended = 1; +- + cpu_suspend(0, at91_suspend_finish); + + /* The SRAM is lost between suspend cycles */ diff --git a/target/linux/at91/patches-5.15/199-ARM-at91-pm-document-at91_soc_pm-structure.patch b/target/linux/at91/patches-5.15/199-ARM-at91-pm-document-at91_soc_pm-structure.patch new file mode 100644 index 0000000000..965555a11d --- /dev/null +++ b/target/linux/at91/patches-5.15/199-ARM-at91-pm-document-at91_soc_pm-structure.patch @@ -0,0 +1,31 @@ +From 59a4b3b9381b727f416d9cc52e60d0bc7d93ecae Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:49 +0300 +Subject: [PATCH 199/247] ARM: at91: pm: document at91_soc_pm structure + +Document at91_soc_pm structure. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-4-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -41,6 +41,14 @@ struct at91_pm_bu { + phys_addr_t resume; + }; + ++/** ++ * struct at91_soc_pm - AT91 SoC power management data structure ++ * @config_shdwc_ws: wakeup sources configuration function for SHDWC ++ * @config_pmc_ws: wakeup srouces configuration function for PMC ++ * @ws_ids: wakup sources of_device_id array ++ * @data: PM data to be used on last phase of suspend ++ * @bu: backup unit mapped data (for backup mode) ++ */ + struct at91_soc_pm { + int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); + int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); diff --git a/target/linux/at91/patches-5.15/200-ARM-at91-pm-check-for-different-controllers-in-at91_.patch b/target/linux/at91/patches-5.15/200-ARM-at91-pm-check-for-different-controllers-in-at91_.patch new file mode 100644 index 0000000000..f15095aafd --- /dev/null +++ b/target/linux/at91/patches-5.15/200-ARM-at91-pm-check-for-different-controllers-in-at91_.patch @@ -0,0 +1,238 @@ +From 0c4cbd38a705bdeab11de4c84ad0ce8c3de8a81d Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:50 +0300 +Subject: [PATCH 200/247] ARM: at91: pm: check for different controllers in + at91_pm_modes_init() + +at91_pm_modes_init() checks for proper nodes in device tree and maps +them accordingly. Up to SAMA7G5 all AT91 SoCs had the same mapping +b/w power saving modes and different controllers needed in the +final/first steps of suspend/resume. SAMA7G5 is not aligned with the +old SoCs thus the code is adapted for this. This patch prepares +the field for next commits. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-5-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 143 +++++++++++++++++++++++++--------------- + 1 file changed, 91 insertions(+), 52 deletions(-) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -57,6 +57,18 @@ struct at91_soc_pm { + struct at91_pm_data data; + }; + ++/** ++ * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes ++ * @AT91_PM_IOMAP_SHDWC: SHDWC controller ++ * @AT91_PM_IOMAP_SFRBU: SFRBU controller ++ */ ++enum at91_pm_iomaps { ++ AT91_PM_IOMAP_SHDWC, ++ AT91_PM_IOMAP_SFRBU, ++}; ++ ++#define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name) ++ + static struct at91_soc_pm soc_pm = { + .data = { + .standby_mode = AT91_PM_STANDBY, +@@ -671,24 +683,15 @@ static int __init at91_pm_backup_init(vo + if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) + return 0; + +- np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); +- if (!np) { +- pr_warn("%s: failed to find sfrbu!\n", __func__); +- return ret; +- } +- +- soc_pm.data.sfrbu = of_iomap(np, 0); +- of_node_put(np); +- + np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); + if (!np) +- goto securam_fail_no_ref_dev; ++ return ret; + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev) { + pr_warn("%s: failed to find securam device!\n", __func__); +- goto securam_fail_no_ref_dev; ++ return ret; + } + + sram_pool = gen_pool_get(&pdev->dev, NULL); +@@ -712,64 +715,92 @@ static int __init at91_pm_backup_init(vo + + securam_fail: + put_device(&pdev->dev); +-securam_fail_no_ref_dev: +- iounmap(soc_pm.data.sfrbu); +- soc_pm.data.sfrbu = NULL; + return ret; + } + +-static void __init at91_pm_use_default_mode(int pm_mode) +-{ +- if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP) +- return; +- +- if (soc_pm.data.standby_mode == pm_mode) +- soc_pm.data.standby_mode = AT91_PM_ULP0; +- if (soc_pm.data.suspend_mode == pm_mode) +- soc_pm.data.suspend_mode = AT91_PM_ULP0; +-} +- + static const struct of_device_id atmel_shdwc_ids[] = { + { .compatible = "atmel,sama5d2-shdwc" }, + { .compatible = "microchip,sam9x60-shdwc" }, + { /* sentinel. */ } + }; + +-static void __init at91_pm_modes_init(void) ++static void __init at91_pm_modes_init(const u32 *maps, int len) + { + struct device_node *np; +- int ret; ++ int ret, mode; + +- if (!at91_is_pm_mode_active(AT91_PM_BACKUP) && +- !at91_is_pm_mode_active(AT91_PM_ULP1)) +- return; ++ ret = at91_pm_backup_init(); ++ if (ret) { ++ if (soc_pm.data.standby_mode == AT91_PM_BACKUP) ++ soc_pm.data.standby_mode = AT91_PM_ULP0; ++ if (soc_pm.data.suspend_mode == AT91_PM_BACKUP) ++ soc_pm.data.suspend_mode = AT91_PM_ULP0; ++ } ++ ++ if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || ++ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) { ++ np = of_find_matching_node(NULL, atmel_shdwc_ids); ++ if (!np) { ++ pr_warn("%s: failed to find shdwc!\n", __func__); ++ ++ /* Use ULP0 if it doesn't needs SHDWC.*/ ++ if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC))) ++ mode = AT91_PM_ULP0; ++ else ++ mode = AT91_PM_STANDBY; ++ ++ if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC)) ++ soc_pm.data.standby_mode = mode; ++ if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) ++ soc_pm.data.suspend_mode = mode; ++ } else { ++ soc_pm.data.shdwc = of_iomap(np, 0); ++ of_node_put(np); ++ } ++ } + +- np = of_find_matching_node(NULL, atmel_shdwc_ids); +- if (!np) { +- pr_warn("%s: failed to find shdwc!\n", __func__); +- goto ulp1_default; ++ if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || ++ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) { ++ np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); ++ if (!np) { ++ pr_warn("%s: failed to find sfrbu!\n", __func__); ++ ++ /* ++ * Use ULP0 if it doesn't need SHDWC or if SHDWC ++ * was already located. ++ */ ++ if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) || ++ soc_pm.data.shdwc) ++ mode = AT91_PM_ULP0; ++ else ++ mode = AT91_PM_STANDBY; ++ ++ if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU)) ++ soc_pm.data.standby_mode = mode; ++ if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) ++ soc_pm.data.suspend_mode = mode; ++ } else { ++ soc_pm.data.sfrbu = of_iomap(np, 0); ++ of_node_put(np); ++ } + } + +- soc_pm.data.shdwc = of_iomap(np, 0); +- of_node_put(np); ++ /* Unmap all unnecessary. */ ++ if (soc_pm.data.shdwc && ++ !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || ++ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) { ++ iounmap(soc_pm.data.shdwc); ++ soc_pm.data.shdwc = NULL; ++ } + +- ret = at91_pm_backup_init(); +- if (ret) { +- if (!at91_is_pm_mode_active(AT91_PM_ULP1)) +- goto unmap; +- else +- goto backup_default; ++ if (soc_pm.data.sfrbu && ++ !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || ++ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) { ++ iounmap(soc_pm.data.sfrbu); ++ soc_pm.data.sfrbu = NULL; + } + + return; +- +-unmap: +- iounmap(soc_pm.data.shdwc); +- soc_pm.data.shdwc = NULL; +-ulp1_default: +- at91_pm_use_default_mode(AT91_PM_ULP1); +-backup_default: +- at91_pm_use_default_mode(AT91_PM_BACKUP); + } + + struct pmc_info { +@@ -936,13 +967,16 @@ void __init sam9x60_pm_init(void) + static const int modes[] __initconst = { + AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, + }; ++ static const int iomaps[] __initconst = { ++ [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), ++ }; + int ret; + + if (!IS_ENABLED(CONFIG_SOC_SAM9X60)) + return; + + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); +- at91_pm_modes_init(); ++ at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); + ret = at91_dt_ramc(); + if (ret) + return; +@@ -999,13 +1033,18 @@ void __init sama5d2_pm_init(void) + AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, + AT91_PM_BACKUP, + }; ++ static const u32 iomaps[] __initconst = { ++ [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), ++ [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) | ++ AT91_PM_IOMAP(SFRBU), ++ }; + int ret; + + if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) + return; + + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); +- at91_pm_modes_init(); ++ at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); + ret = at91_dt_ramc(); + if (ret) + return; diff --git a/target/linux/at91/patches-5.15/201-ARM-at91-pm-do-not-initialize-pdev.patch b/target/linux/at91/patches-5.15/201-ARM-at91-pm-do-not-initialize-pdev.patch new file mode 100644 index 0000000000..413a95a968 --- /dev/null +++ b/target/linux/at91/patches-5.15/201-ARM-at91-pm-do-not-initialize-pdev.patch @@ -0,0 +1,25 @@ +From 31e25503bbad1fffd29fd074a46bd4858b65304f Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:51 +0300 +Subject: [PATCH 201/247] ARM: at91: pm: do not initialize pdev + +There is no need to initialize pdev. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-6-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -674,7 +674,7 @@ static int __init at91_pm_backup_init(vo + { + struct gen_pool *sram_pool; + struct device_node *np; +- struct platform_device *pdev = NULL; ++ struct platform_device *pdev; + int ret = -ENODEV; + + if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) diff --git a/target/linux/at91/patches-5.15/202-ARM-at91-pm-use-r7-instead-of-tmp1.patch b/target/linux/at91/patches-5.15/202-ARM-at91-pm-use-r7-instead-of-tmp1.patch new file mode 100644 index 0000000000..a313ab029a --- /dev/null +++ b/target/linux/at91/patches-5.15/202-ARM-at91-pm-use-r7-instead-of-tmp1.patch @@ -0,0 +1,60 @@ +From 8a7a4cf3860910e460e2c3ca467b1dabf7ce9827 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:52 +0300 +Subject: [PATCH 202/247] ARM: at91: pm: use r7 instead of tmp1 + +Use r7 instead of tmp1 in macros. This prepares the filed for +next commits. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-7-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm_suspend.S | 18 ++++++++++++------ + 1 file changed, 12 insertions(+), 6 deletions(-) + +--- a/arch/arm/mach-at91/pm_suspend.S ++++ b/arch/arm/mach-at91/pm_suspend.S +@@ -31,30 +31,36 @@ tmp3 .req r6 + + /* + * Wait until master oscillator has stabilized. ++ * ++ * Side effects: overwrites r7 + */ + .macro wait_moscrdy +-1: ldr tmp1, [pmc, #AT91_PMC_SR] +- tst tmp1, #AT91_PMC_MOSCS ++1: ldr r7, [pmc, #AT91_PMC_SR] ++ tst r7, #AT91_PMC_MOSCS + beq 1b + .endm + + /* + * Wait for main oscillator selection is done ++ * ++ * Side effects: overwrites r7 + */ + .macro wait_moscsels +-1: ldr tmp1, [pmc, #AT91_PMC_SR] +- tst tmp1, #AT91_PMC_MOSCSELS ++1: ldr r7, [pmc, #AT91_PMC_SR] ++ tst r7, #AT91_PMC_MOSCSELS + beq 1b + .endm + + /* + * Put the processor to enter the idle state ++ * ++ * Side effects: overwrites r7 + */ + .macro at91_cpu_idle + + #if defined(CONFIG_CPU_V7) +- mov tmp1, #AT91_PMC_PCK +- str tmp1, [pmc, #AT91_PMC_SCDR] ++ mov r7, #AT91_PMC_PCK ++ str r7, [pmc, #AT91_PMC_SCDR] + + dsb + diff --git a/target/linux/at91/patches-5.15/203-ARM-at91-pm-avoid-push-and-pop-on-stack-while-memory.patch b/target/linux/at91/patches-5.15/203-ARM-at91-pm-avoid-push-and-pop-on-stack-while-memory.patch new file mode 100644 index 0000000000..a2edec371d --- /dev/null +++ b/target/linux/at91/patches-5.15/203-ARM-at91-pm-avoid-push-and-pop-on-stack-while-memory.patch @@ -0,0 +1,467 @@ +From 892f6d2fb9c42d4ac451236639599f533c37b507 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:53 +0300 +Subject: [PATCH 203/247] ARM: at91: pm: avoid push and pop on stack while + memory is in self-refersh + +For the previous AT91 RAM controller and self-refresh procedure this +had no side effects. However, for SAMA7G5 the self-refresh procedure +doesn't allow this anymore as the RAM controller ports are closed +before switching it to self-refresh. This commits prepares the code +for the following ones adding self-refresh and PM support for SAMA7G5. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-8-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm_suspend.S | 397 +++++++++++++++++--------------- + 1 file changed, 205 insertions(+), 192 deletions(-) + +--- a/arch/arm/mach-at91/pm_suspend.S ++++ b/arch/arm/mach-at91/pm_suspend.S +@@ -75,98 +75,147 @@ tmp3 .req r6 + + .arm + +-/* +- * void at91_suspend_sram_fn(struct at91_pm_data*) +- * @input param: +- * @r0: base address of struct at91_pm_data ++/** ++ * Enable self-refresh ++ * ++ * register usage: ++ * @r1: memory type ++ * @r2: base address of the sram controller ++ * @r3: temporary + */ +-/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ +- .align 3 +-ENTRY(at91_pm_suspend_in_sram) +- /* Save registers on stack */ +- stmfd sp!, {r4 - r12, lr} ++.macro at91_sramc_self_refresh_ena ++ ldr r1, .memtype ++ ldr r2, .sramc_base + +- /* Drain write buffer */ +- mov tmp1, #0 +- mcr p15, 0, tmp1, c7, c10, 4 ++ cmp r1, #AT91_MEMCTRL_MC ++ bne sr_ena_ddrc_sf + +- ldr tmp1, [r0, #PM_DATA_PMC] +- str tmp1, .pmc_base +- ldr tmp1, [r0, #PM_DATA_RAMC0] +- str tmp1, .sramc_base +- ldr tmp1, [r0, #PM_DATA_RAMC1] +- str tmp1, .sramc1_base +- ldr tmp1, [r0, #PM_DATA_MEMCTRL] +- str tmp1, .memtype +- ldr tmp1, [r0, #PM_DATA_MODE] +- str tmp1, .pm_mode +- ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] +- str tmp1, .mckr_offset +- ldr tmp1, [r0, #PM_DATA_PMC_VERSION] +- str tmp1, .pmc_version +- /* Both ldrne below are here to preload their address in the TLB */ +- ldr tmp1, [r0, #PM_DATA_SHDWC] +- str tmp1, .shdwc +- cmp tmp1, #0 +- ldrne tmp2, [tmp1, #0] +- ldr tmp1, [r0, #PM_DATA_SFRBU] +- str tmp1, .sfrbu +- cmp tmp1, #0 +- ldrne tmp2, [tmp1, #0x10] ++ /* Active SDRAM self-refresh mode */ ++ mov r3, #1 ++ str r3, [r2, #AT91_MC_SDRAMC_SRR] ++ b sr_ena_exit + +- /* Active the self-refresh mode */ +- mov r0, #SRAMC_SELF_FRESH_ACTIVE +- bl at91_sramc_self_refresh ++sr_ena_ddrc_sf: ++ cmp r1, #AT91_MEMCTRL_DDRSDR ++ bne sr_ena_sdramc_sf + +- ldr r0, .pm_mode +- cmp r0, #AT91_PM_STANDBY +- beq standby +- cmp r0, #AT91_PM_BACKUP +- beq backup_mode ++ /* ++ * DDR Memory controller ++ */ + +- bl at91_ulp_mode +- b exit_suspend ++ /* LPDDR1 --> force DDR2 mode during self-refresh */ ++ ldr r3, [r2, #AT91_DDRSDRC_MDR] ++ str r3, .saved_sam9_mdr ++ bic r3, r3, #~AT91_DDRSDRC_MD ++ cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR ++ ldreq r3, [r2, #AT91_DDRSDRC_MDR] ++ biceq r3, r3, #AT91_DDRSDRC_MD ++ orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 ++ streq r3, [r2, #AT91_DDRSDRC_MDR] + +-standby: +- /* Wait for interrupt */ +- ldr pmc, .pmc_base +- at91_cpu_idle +- b exit_suspend ++ /* Active DDRC self-refresh mode */ ++ ldr r3, [r2, #AT91_DDRSDRC_LPR] ++ str r3, .saved_sam9_lpr ++ bic r3, r3, #AT91_DDRSDRC_LPCB ++ orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH ++ str r3, [r2, #AT91_DDRSDRC_LPR] + +-backup_mode: +- bl at91_backup_mode +- b exit_suspend ++ /* If using the 2nd ddr controller */ ++ ldr r2, .sramc1_base ++ cmp r2, #0 ++ beq sr_ena_no_2nd_ddrc + +-exit_suspend: +- /* Exit the self-refresh mode */ +- mov r0, #SRAMC_SELF_FRESH_EXIT +- bl at91_sramc_self_refresh ++ ldr r3, [r2, #AT91_DDRSDRC_MDR] ++ str r3, .saved_sam9_mdr1 ++ bic r3, r3, #~AT91_DDRSDRC_MD ++ cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR ++ ldreq r3, [r2, #AT91_DDRSDRC_MDR] ++ biceq r3, r3, #AT91_DDRSDRC_MD ++ orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 ++ streq r3, [r2, #AT91_DDRSDRC_MDR] + +- /* Restore registers, and return */ +- ldmfd sp!, {r4 - r12, pc} +-ENDPROC(at91_pm_suspend_in_sram) ++ /* Active DDRC self-refresh mode */ ++ ldr r3, [r2, #AT91_DDRSDRC_LPR] ++ str r3, .saved_sam9_lpr1 ++ bic r3, r3, #AT91_DDRSDRC_LPCB ++ orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH ++ str r3, [r2, #AT91_DDRSDRC_LPR] + +-ENTRY(at91_backup_mode) +- /* Switch the master clock source to slow clock. */ +- ldr pmc, .pmc_base +- ldr tmp2, .mckr_offset +- ldr tmp1, [pmc, tmp2] +- bic tmp1, tmp1, #AT91_PMC_CSS +- str tmp1, [pmc, tmp2] ++sr_ena_no_2nd_ddrc: ++ b sr_ena_exit + +- wait_mckrdy ++ /* ++ * SDRAMC Memory controller ++ */ ++sr_ena_sdramc_sf: ++ /* Active SDRAMC self-refresh mode */ ++ ldr r3, [r2, #AT91_SDRAMC_LPR] ++ str r3, .saved_sam9_lpr ++ bic r3, r3, #AT91_SDRAMC_LPCB ++ orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH ++ str r3, [r2, #AT91_SDRAMC_LPR] + +- /*BUMEN*/ +- ldr r0, .sfrbu +- mov tmp1, #0x1 +- str tmp1, [r0, #0x10] ++ ldr r3, .saved_sam9_lpr ++ str r3, [r2, #AT91_SDRAMC_LPR] + +- /* Shutdown */ +- ldr r0, .shdwc +- mov tmp1, #0xA5000000 +- add tmp1, tmp1, #0x1 +- str tmp1, [r0, #0] +-ENDPROC(at91_backup_mode) ++sr_ena_exit: ++.endm ++ ++/** ++ * Disable self-refresh ++ * ++ * register usage: ++ * @r1: memory type ++ * @r2: base address of the sram controller ++ * @r3: temporary ++ */ ++.macro at91_sramc_self_refresh_dis ++ ldr r1, .memtype ++ ldr r2, .sramc_base ++ ++ cmp r1, #AT91_MEMCTRL_MC ++ bne sr_dis_ddrc_exit_sf ++ ++ /* ++ * at91rm9200 Memory controller ++ */ ++ ++ /* ++ * For exiting the self-refresh mode, do nothing, ++ * automatically exit the self-refresh mode. ++ */ ++ b sr_dis_exit ++ ++sr_dis_ddrc_exit_sf: ++ cmp r1, #AT91_MEMCTRL_DDRSDR ++ bne sdramc_exit_sf ++ ++ /* DDR Memory controller */ ++ ++ /* Restore MDR in case of LPDDR1 */ ++ ldr r3, .saved_sam9_mdr ++ str r3, [r2, #AT91_DDRSDRC_MDR] ++ /* Restore LPR on AT91 with DDRAM */ ++ ldr r3, .saved_sam9_lpr ++ str r3, [r2, #AT91_DDRSDRC_LPR] ++ ++ /* If using the 2nd ddr controller */ ++ ldr r2, .sramc1_base ++ cmp r2, #0 ++ ldrne r3, .saved_sam9_mdr1 ++ strne r3, [r2, #AT91_DDRSDRC_MDR] ++ ldrne r3, .saved_sam9_lpr1 ++ strne r3, [r2, #AT91_DDRSDRC_LPR] ++ ++ b sr_dis_exit ++ ++sdramc_exit_sf: ++ /* SDRAMC Memory controller */ ++ ldr r3, .saved_sam9_lpr ++ str r3, [r2, #AT91_SDRAMC_LPR] ++ ++sr_dis_exit: ++.endm + + .macro at91_pm_ulp0_mode + ldr pmc, .pmc_base +@@ -503,7 +552,7 @@ ENDPROC(at91_backup_mode) + 2: + .endm + +-ENTRY(at91_ulp_mode) ++.macro at91_ulp_mode + ldr pmc, .pmc_base + ldr tmp2, .mckr_offset + ldr tmp3, .pm_mode +@@ -552,133 +601,97 @@ ulp_exit: + + wait_mckrdy + +- mov pc, lr +-ENDPROC(at91_ulp_mode) +- +-/* +- * void at91_sramc_self_refresh(unsigned int is_active) +- * +- * @input param: +- * @r0: 1 - active self-refresh mode +- * 0 - exit self-refresh mode +- * register usage: +- * @r1: memory type +- * @r2: base address of the sram controller +- */ +- +-ENTRY(at91_sramc_self_refresh) +- ldr r1, .memtype +- ldr r2, .sramc_base +- +- cmp r1, #AT91_MEMCTRL_MC +- bne ddrc_sf +- +- /* +- * at91rm9200 Memory controller +- */ +- +- /* +- * For exiting the self-refresh mode, do nothing, +- * automatically exit the self-refresh mode. +- */ +- tst r0, #SRAMC_SELF_FRESH_ACTIVE +- beq exit_sramc_sf +- +- /* Active SDRAM self-refresh mode */ +- mov r3, #1 +- str r3, [r2, #AT91_MC_SDRAMC_SRR] +- b exit_sramc_sf +- +-ddrc_sf: +- cmp r1, #AT91_MEMCTRL_DDRSDR +- bne sdramc_sf ++.endm + +- /* +- * DDR Memory controller +- */ +- tst r0, #SRAMC_SELF_FRESH_ACTIVE +- beq ddrc_exit_sf ++.macro at91_backup_mode ++ /* Switch the master clock source to slow clock. */ ++ ldr pmc, .pmc_base ++ ldr tmp2, .mckr_offset ++ ldr tmp1, [pmc, tmp2] ++ bic tmp1, tmp1, #AT91_PMC_CSS ++ str tmp1, [pmc, tmp2] + +- /* LPDDR1 --> force DDR2 mode during self-refresh */ +- ldr r3, [r2, #AT91_DDRSDRC_MDR] +- str r3, .saved_sam9_mdr +- bic r3, r3, #~AT91_DDRSDRC_MD +- cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR +- ldreq r3, [r2, #AT91_DDRSDRC_MDR] +- biceq r3, r3, #AT91_DDRSDRC_MD +- orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 +- streq r3, [r2, #AT91_DDRSDRC_MDR] ++ wait_mckrdy + +- /* Active DDRC self-refresh mode */ +- ldr r3, [r2, #AT91_DDRSDRC_LPR] +- str r3, .saved_sam9_lpr +- bic r3, r3, #AT91_DDRSDRC_LPCB +- orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH +- str r3, [r2, #AT91_DDRSDRC_LPR] ++ /*BUMEN*/ ++ ldr r0, .sfrbu ++ mov tmp1, #0x1 ++ str tmp1, [r0, #0x10] + +- /* If using the 2nd ddr controller */ +- ldr r2, .sramc1_base +- cmp r2, #0 +- beq no_2nd_ddrc ++ /* Shutdown */ ++ ldr r0, .shdwc ++ mov tmp1, #0xA5000000 ++ add tmp1, tmp1, #0x1 ++ str tmp1, [r0, #0] ++.endm + +- ldr r3, [r2, #AT91_DDRSDRC_MDR] +- str r3, .saved_sam9_mdr1 +- bic r3, r3, #~AT91_DDRSDRC_MD +- cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR +- ldreq r3, [r2, #AT91_DDRSDRC_MDR] +- biceq r3, r3, #AT91_DDRSDRC_MD +- orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 +- streq r3, [r2, #AT91_DDRSDRC_MDR] ++/* ++ * void at91_suspend_sram_fn(struct at91_pm_data*) ++ * @input param: ++ * @r0: base address of struct at91_pm_data ++ */ ++/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ ++ .align 3 ++ENTRY(at91_pm_suspend_in_sram) ++ /* Save registers on stack */ ++ stmfd sp!, {r4 - r12, lr} + +- /* Active DDRC self-refresh mode */ +- ldr r3, [r2, #AT91_DDRSDRC_LPR] +- str r3, .saved_sam9_lpr1 +- bic r3, r3, #AT91_DDRSDRC_LPCB +- orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH +- str r3, [r2, #AT91_DDRSDRC_LPR] ++ /* Drain write buffer */ ++ mov tmp1, #0 ++ mcr p15, 0, tmp1, c7, c10, 4 + +-no_2nd_ddrc: +- b exit_sramc_sf ++ ldr tmp1, [r0, #PM_DATA_PMC] ++ str tmp1, .pmc_base ++ ldr tmp1, [r0, #PM_DATA_RAMC0] ++ str tmp1, .sramc_base ++ ldr tmp1, [r0, #PM_DATA_RAMC1] ++ str tmp1, .sramc1_base ++ ldr tmp1, [r0, #PM_DATA_MEMCTRL] ++ str tmp1, .memtype ++ ldr tmp1, [r0, #PM_DATA_MODE] ++ str tmp1, .pm_mode ++ ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] ++ str tmp1, .mckr_offset ++ ldr tmp1, [r0, #PM_DATA_PMC_VERSION] ++ str tmp1, .pmc_version ++ /* Both ldrne below are here to preload their address in the TLB */ ++ ldr tmp1, [r0, #PM_DATA_SHDWC] ++ str tmp1, .shdwc ++ cmp tmp1, #0 ++ ldrne tmp2, [tmp1, #0] ++ ldr tmp1, [r0, #PM_DATA_SFRBU] ++ str tmp1, .sfrbu ++ cmp tmp1, #0 ++ ldrne tmp2, [tmp1, #0x10] + +-ddrc_exit_sf: +- /* Restore MDR in case of LPDDR1 */ +- ldr r3, .saved_sam9_mdr +- str r3, [r2, #AT91_DDRSDRC_MDR] +- /* Restore LPR on AT91 with DDRAM */ +- ldr r3, .saved_sam9_lpr +- str r3, [r2, #AT91_DDRSDRC_LPR] ++ /* Active the self-refresh mode */ ++ at91_sramc_self_refresh_ena + +- /* If using the 2nd ddr controller */ +- ldr r2, .sramc1_base +- cmp r2, #0 +- ldrne r3, .saved_sam9_mdr1 +- strne r3, [r2, #AT91_DDRSDRC_MDR] +- ldrne r3, .saved_sam9_lpr1 +- strne r3, [r2, #AT91_DDRSDRC_LPR] ++ ldr r0, .pm_mode ++ cmp r0, #AT91_PM_STANDBY ++ beq standby ++ cmp r0, #AT91_PM_BACKUP ++ beq backup_mode + +- b exit_sramc_sf ++ at91_ulp_mode ++ b exit_suspend + +- /* +- * SDRAMC Memory controller +- */ +-sdramc_sf: +- tst r0, #SRAMC_SELF_FRESH_ACTIVE +- beq sdramc_exit_sf ++standby: ++ /* Wait for interrupt */ ++ ldr pmc, .pmc_base ++ at91_cpu_idle ++ b exit_suspend + +- /* Active SDRAMC self-refresh mode */ +- ldr r3, [r2, #AT91_SDRAMC_LPR] +- str r3, .saved_sam9_lpr +- bic r3, r3, #AT91_SDRAMC_LPCB +- orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH +- str r3, [r2, #AT91_SDRAMC_LPR] ++backup_mode: ++ at91_backup_mode + +-sdramc_exit_sf: +- ldr r3, .saved_sam9_lpr +- str r3, [r2, #AT91_SDRAMC_LPR] ++exit_suspend: ++ /* Exit the self-refresh mode */ ++ at91_sramc_self_refresh_dis + +-exit_sramc_sf: +- mov pc, lr +-ENDPROC(at91_sramc_self_refresh) ++ /* Restore registers, and return */ ++ ldmfd sp!, {r4 - r12, pc} ++ENDPROC(at91_pm_suspend_in_sram) + + .pmc_base: + .word 0 diff --git a/target/linux/at91/patches-5.15/204-ARM-at91-pm-s-CONFIG_SOC_SAM9X60-CONFIG_HAVE_AT91_SA.patch b/target/linux/at91/patches-5.15/204-ARM-at91-pm-s-CONFIG_SOC_SAM9X60-CONFIG_HAVE_AT91_SA.patch new file mode 100644 index 0000000000..4601d922d6 --- /dev/null +++ b/target/linux/at91/patches-5.15/204-ARM-at91-pm-s-CONFIG_SOC_SAM9X60-CONFIG_HAVE_AT91_SA.patch @@ -0,0 +1,36 @@ +From 673d2519e9028dafb678fac29a990740958bed3c Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:54 +0300 +Subject: [PATCH 204/247] ARM: at91: pm: + s/CONFIG_SOC_SAM9X60/CONFIG_HAVE_AT91_SAM9X60_PLL/g + +Replace CONFIG_SOC_SAM9X60 with CONFIG_HAVE_AT91_SAM9X60_PLL as the +SAM9X60's PLL is also present on SAMA7G5. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-9-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm_suspend.S | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/mach-at91/pm_suspend.S ++++ b/arch/arm/mach-at91/pm_suspend.S +@@ -422,7 +422,7 @@ sr_dis_exit: + cmp tmp1, #AT91_PMC_V1 + beq 1f + +-#ifdef CONFIG_SOC_SAM9X60 ++#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL + /* Save PLLA settings. */ + ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT] + bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID +@@ -489,7 +489,7 @@ sr_dis_exit: + cmp tmp3, #AT91_PMC_V1 + beq 4f + +-#ifdef CONFIG_SOC_SAM9X60 ++#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL + /* step 1. */ + ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] + bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID diff --git a/target/linux/at91/patches-5.15/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch b/target/linux/at91/patches-5.15/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch new file mode 100644 index 0000000000..16e733727f --- /dev/null +++ b/target/linux/at91/patches-5.15/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch @@ -0,0 +1,150 @@ +From 67face049c62cb37cf93da26b7fea037228d1d3d Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:55 +0300 +Subject: [PATCH 205/247] ARM: at91: pm: add support for waiting MCK1..4 + +SAMA7G5 has 5 master clocks 0..4. MCK0 is controlled differently than +MCK 1..4. MCK 1..4 should also be saved/restored in the last phase of +suspend/resume. Thus, adapt wait_mckrdy to support also MCK1..4. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-10-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm_suspend.S | 48 ++++++++++++++++++++++++--------- + 1 file changed, 35 insertions(+), 13 deletions(-) + +--- a/arch/arm/mach-at91/pm_suspend.S ++++ b/arch/arm/mach-at91/pm_suspend.S +@@ -22,11 +22,23 @@ tmp3 .req r6 + + /* + * Wait until master clock is ready (after switching master clock source) ++ * ++ * @r_mckid: register holding master clock identifier ++ * ++ * Side effects: overwrites r7, r8 + */ +- .macro wait_mckrdy +-1: ldr tmp1, [pmc, #AT91_PMC_SR] +- tst tmp1, #AT91_PMC_MCKRDY +- beq 1b ++ .macro wait_mckrdy r_mckid ++#ifdef CONFIG_SOC_SAMA7 ++ cmp \r_mckid, #0 ++ beq 1f ++ mov r7, #AT91_PMC_MCKXRDY ++ b 2f ++#endif ++1: mov r7, #AT91_PMC_MCKRDY ++2: ldr r8, [pmc, #AT91_PMC_SR] ++ and r8, r7 ++ cmp r8, r7 ++ bne 2b + .endm + + /* +@@ -231,7 +243,9 @@ sr_dis_exit: + bic tmp1, tmp1, #AT91_PMC_PRES + orr tmp1, tmp1, #AT91_PMC_PRES_64 + str tmp1, [pmc, tmp3] +- wait_mckrdy ++ ++ mov tmp3, #0 ++ wait_mckrdy tmp3 + b 1f + + 0: +@@ -267,10 +281,13 @@ sr_dis_exit: + bne 5f + + /* Set lowest prescaler for fast resume. */ ++ ldr tmp3, .mckr_offset + ldr tmp1, [pmc, tmp3] + bic tmp1, tmp1, #AT91_PMC_PRES + str tmp1, [pmc, tmp3] +- wait_mckrdy ++ ++ mov tmp3, #0 ++ wait_mckrdy tmp3 + b 6f + + 5: /* Restore RC oscillator state */ +@@ -307,6 +324,7 @@ sr_dis_exit: + .macro at91_pm_ulp1_mode + ldr pmc, .pmc_base + ldr tmp2, .mckr_offset ++ mov tmp3, #0 + + /* Save RC oscillator state and check if it is enabled. */ + ldr tmp1, [pmc, #AT91_PMC_SR] +@@ -348,7 +366,7 @@ sr_dis_exit: + orr tmp1, tmp1, #AT91_PMC_CSS_MAIN + str tmp1, [pmc, tmp2] + +- wait_mckrdy ++ wait_mckrdy tmp3 + + /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] +@@ -361,7 +379,7 @@ sr_dis_exit: + nop + nop + +- wait_mckrdy ++ wait_mckrdy tmp3 + + /* Enable the crystal oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] +@@ -377,7 +395,7 @@ sr_dis_exit: + bic tmp1, tmp1, #AT91_PMC_CSS + str tmp1, [pmc, tmp2] + +- wait_mckrdy ++ wait_mckrdy tmp3 + + /* Switch main clock source to crystal oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] +@@ -394,7 +412,7 @@ sr_dis_exit: + orr tmp1, tmp1, #AT91_PMC_CSS_MAIN + str tmp1, [pmc, tmp2] + +- wait_mckrdy ++ wait_mckrdy tmp3 + + /* Restore RC oscillator state */ + ldr tmp1, .saved_osc_status +@@ -573,10 +591,12 @@ sr_dis_exit: + save_mck: + str tmp1, [pmc, tmp2] + +- wait_mckrdy ++ mov tmp3, #0 ++ wait_mckrdy tmp3 + + at91_plla_disable + ++ ldr tmp3, .pm_mode + cmp tmp3, #AT91_PM_ULP1 + beq ulp1_mode + +@@ -599,7 +619,8 @@ ulp_exit: + ldr tmp2, .saved_mckr + str tmp2, [pmc, tmp1] + +- wait_mckrdy ++ mov tmp3, #0 ++ wait_mckrdy tmp3 + + .endm + +@@ -611,7 +632,8 @@ ulp_exit: + bic tmp1, tmp1, #AT91_PMC_CSS + str tmp1, [pmc, tmp2] + +- wait_mckrdy ++ mov tmp3, #0 ++ wait_mckrdy tmp3 + + /*BUMEN*/ + ldr r0, .sfrbu diff --git a/target/linux/at91/patches-5.15/206-ARM-at91-sfrbu-add-sfrbu-registers-definitions-for-s.patch b/target/linux/at91/patches-5.15/206-ARM-at91-sfrbu-add-sfrbu-registers-definitions-for-s.patch new file mode 100644 index 0000000000..37a22885d7 --- /dev/null +++ b/target/linux/at91/patches-5.15/206-ARM-at91-sfrbu-add-sfrbu-registers-definitions-for-s.patch @@ -0,0 +1,53 @@ +From c6b435625975d9a6daeffd81509a9877ddfb93b5 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:56 +0300 +Subject: [PATCH 206/247] ARM: at91: sfrbu: add sfrbu registers definitions for + sama7g5 + +Add SFRBU registers definitions for SAMA7G5. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-11-claudiu.beznea@microchip.com +--- + include/soc/at91/sama7-sfrbu.h | 34 ++++++++++++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) + create mode 100644 include/soc/at91/sama7-sfrbu.h + +--- /dev/null ++++ b/include/soc/at91/sama7-sfrbu.h +@@ -0,0 +1,34 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Microchip SAMA7 SFRBU registers offsets and bit definitions. ++ * ++ * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries ++ * ++ * Author: Claudu Beznea ++ */ ++ ++#ifndef __SAMA7_SFRBU_H__ ++#define __SAMA7_SFRBU_H__ ++ ++#ifdef CONFIG_SOC_SAMA7 ++ ++#define AT91_SFRBU_PSWBU (0x00) /* SFRBU Power Switch BU Control Register */ ++#define AT91_SFRBU_PSWBU_PSWKEY (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */ ++#define AT91_SFRBU_PSWBU_STATE (1 << 2) /* Power switch BU state */ ++#define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */ ++#define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */ ++ ++#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */ ++#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */ ++#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */ ++#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */ ++#define AT91_SFRBU_PD_VALUE_MSK (0x3) ++#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */ ++ ++#define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */ ++#define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */ ++ ++#endif /* CONFIG_SOC_SAMA7 */ ++ ++#endif /* __SAMA7_SFRBU_H__ */ ++ diff --git a/target/linux/at91/patches-5.15/207-ARM-at91-ddr-add-registers-definitions-for-sama7g5-s.patch b/target/linux/at91/patches-5.15/207-ARM-at91-ddr-add-registers-definitions-for-sama7g5-s.patch new file mode 100644 index 0000000000..1df310f216 --- /dev/null +++ b/target/linux/at91/patches-5.15/207-ARM-at91-ddr-add-registers-definitions-for-sama7g5-s.patch @@ -0,0 +1,99 @@ +From 0005be9abfcddf9a29c6d07afe06caa41560d424 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:57 +0300 +Subject: [PATCH 207/247] ARM: at91: ddr: add registers definitions for + sama7g5's ddr + +Add registers and bits definitions for SAMA7G5's UDDRC and DDR3PHY. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-12-claudiu.beznea@microchip.com +--- + include/soc/at91/sama7-ddr.h | 80 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 80 insertions(+) + create mode 100644 include/soc/at91/sama7-ddr.h + +--- /dev/null ++++ b/include/soc/at91/sama7-ddr.h +@@ -0,0 +1,80 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Microchip SAMA7 UDDR Controller and DDR3 PHY Controller registers offsets ++ * and bit definitions. ++ * ++ * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries ++ * ++ * Author: Claudu Beznea ++ */ ++ ++#ifndef __SAMA7_DDR_H__ ++#define __SAMA7_DDR_H__ ++ ++#ifdef CONFIG_SOC_SAMA7 ++ ++/* DDR3PHY */ ++#define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */ ++#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */ ++#define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */ ++#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */ ++#define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */ ++#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */ ++ ++#define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */ ++#define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */ ++#define DDR3PHY_PGCR_CKDV0 (1 << 12) /* CK Disable Value */ ++ ++#define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */ ++#define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */ ++ ++#define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */ ++#define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */ ++#define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */ ++#define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */ ++ ++#define DDR3PHY_DXCCR (0x28) /* DDR3PHY DATX8 Common Configuration Register */ ++#define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */ ++ ++#define DDR3PHY_DSGCR (0x2C) /* DDR3PHY DDR System General Configuration Register */ ++#define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */ ++ ++#define DDR3PHY_ZQ0SR0 (0x188) /* ZQ status register 0 */ ++ ++/* UDDRC */ ++#define UDDRC_STAT (0x04) /* UDDRC Operating Mode Status Register */ ++#define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */ ++#define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PHY Master Request */ ++#define UDDRC_STAT_SELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automatic Self-refresh control */ ++#define UDDRC_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self-refresh only */ ++#define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */ ++#define UDDRC_STAT_OPMODE_INIT (0x0 << 0) /* Init */ ++#define UDDRC_STAT_OPMODE_NORMAL (0x1 << 0) /* Normal */ ++#define UDDRC_STAT_OPMODE_PWRDOWN (0x2 << 0) /* Power-down */ ++#define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */ ++#define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */ ++ ++#define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */ ++#define UDDRC_PWRCTRL_SELFREF_SW (1 << 5) /* Software self-refresh */ ++ ++#define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */ ++#define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */ ++ ++#define UDDRC_SWCTRL (0x320) /* UDDRC Software Register Programming Control Enable */ ++#define UDDRC_SWCTRL_SW_DONE (1 << 0) /* Enable quasi-dynamic register programming outside reset */ ++ ++#define UDDRC_SWSTAT (0x324) /* UDDRC Software Register Programming Control Status */ ++#define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */ ++ ++#define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */ ++#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */ ++ ++#define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */ ++#define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */ ++#define UDDRC_PCTRL_2 (0x5F0) /* UDDRC Port 2 Control Register */ ++#define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */ ++#define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */ ++ ++#endif /* CONFIG_SOC_SAMA7 */ ++ ++#endif /* __SAMA7_DDR_H__ */ diff --git a/target/linux/at91/patches-5.15/208-ARM-at91-pm-add-self-refresh-support-for-sama7g5.patch b/target/linux/at91/patches-5.15/208-ARM-at91-pm-add-self-refresh-support-for-sama7g5.patch new file mode 100644 index 0000000000..f8321e5042 --- /dev/null +++ b/target/linux/at91/patches-5.15/208-ARM-at91-pm-add-self-refresh-support-for-sama7g5.patch @@ -0,0 +1,274 @@ +From 1bfd85d71703f80392a71043caf74f159bec97b8 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:58 +0300 +Subject: [PATCH 208/247] ARM: at91: pm: add self-refresh support for sama7g5 + +Add self-refresh support for SAMA7G5. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-13-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.h | 2 + + arch/arm/mach-at91/pm_data-offsets.c | 2 + + arch/arm/mach-at91/pm_suspend.S | 199 +++++++++++++++++++++++++++ + 3 files changed, 203 insertions(+) + +--- a/arch/arm/mach-at91/pm.h ++++ b/arch/arm/mach-at91/pm.h +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + + #define AT91_MEMCTRL_MC 0 + #define AT91_MEMCTRL_SDRAMC 1 +@@ -27,6 +28,7 @@ + struct at91_pm_data { + void __iomem *pmc; + void __iomem *ramc[2]; ++ void __iomem *ramc_phy; + unsigned long uhp_udp_mask; + unsigned int memctrl; + unsigned int mode; +--- a/arch/arm/mach-at91/pm_data-offsets.c ++++ b/arch/arm/mach-at91/pm_data-offsets.c +@@ -8,6 +8,8 @@ int main(void) + DEFINE(PM_DATA_PMC, offsetof(struct at91_pm_data, pmc)); + DEFINE(PM_DATA_RAMC0, offsetof(struct at91_pm_data, ramc[0])); + DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1])); ++ DEFINE(PM_DATA_RAMC_PHY, offsetof(struct at91_pm_data, ++ ramc_phy)); + DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl)); + DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode)); + DEFINE(PM_DATA_SHDWC, offsetof(struct at91_pm_data, shdwc)); +--- a/arch/arm/mach-at91/pm_suspend.S ++++ b/arch/arm/mach-at91/pm_suspend.S +@@ -87,6 +87,200 @@ tmp3 .req r6 + + .arm + ++#ifdef CONFIG_SOC_SAMA7 ++/** ++ * Enable self-refresh ++ * ++ * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3, r7 ++ */ ++.macro at91_sramc_self_refresh_ena ++ ldr r2, .sramc_base ++ ldr r3, .sramc_phy_base ++ ldr r7, .pm_mode ++ ++ dsb ++ ++ /* Disable all AXI ports. */ ++ ldr tmp1, [r2, #UDDRC_PCTRL_0] ++ bic tmp1, tmp1, #0x1 ++ str tmp1, [r2, #UDDRC_PCTRL_0] ++ ++ ldr tmp1, [r2, #UDDRC_PCTRL_1] ++ bic tmp1, tmp1, #0x1 ++ str tmp1, [r2, #UDDRC_PCTRL_1] ++ ++ ldr tmp1, [r2, #UDDRC_PCTRL_2] ++ bic tmp1, tmp1, #0x1 ++ str tmp1, [r2, #UDDRC_PCTRL_2] ++ ++ ldr tmp1, [r2, #UDDRC_PCTRL_3] ++ bic tmp1, tmp1, #0x1 ++ str tmp1, [r2, #UDDRC_PCTRL_3] ++ ++ ldr tmp1, [r2, #UDDRC_PCTRL_4] ++ bic tmp1, tmp1, #0x1 ++ str tmp1, [r2, #UDDRC_PCTRL_4] ++ ++sr_ena_1: ++ /* Wait for all ports to disable. */ ++ ldr tmp1, [r2, #UDDRC_PSTAT] ++ ldr tmp2, =UDDRC_PSTAT_ALL_PORTS ++ tst tmp1, tmp2 ++ bne sr_ena_1 ++ ++ /* Switch to self-refresh. */ ++ ldr tmp1, [r2, #UDDRC_PWRCTL] ++ orr tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW ++ str tmp1, [r2, #UDDRC_PWRCTL] ++ ++sr_ena_2: ++ /* Wait for self-refresh enter. */ ++ ldr tmp1, [r2, #UDDRC_STAT] ++ bic tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK ++ cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW ++ bne sr_ena_2 ++ ++ /* Put DDR PHY's DLL in bypass mode for non-backup modes. */ ++ cmp r7, #AT91_PM_BACKUP ++ beq sr_ena_3 ++ ldr tmp1, [r3, #DDR3PHY_PIR] ++ orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP ++ str tmp1, [r3, #DDR3PHY_PIR] ++ ++sr_ena_3: ++ /* Power down DDR PHY data receivers. */ ++ ldr tmp1, [r3, #DDR3PHY_DXCCR] ++ orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR ++ str tmp1, [r3, #DDR3PHY_DXCCR] ++ ++ /* Power down ADDR/CMD IO. */ ++ ldr tmp1, [r3, #DDR3PHY_ACIOCR] ++ orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD ++ orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0 ++ orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0 ++ str tmp1, [r3, #DDR3PHY_ACIOCR] ++ ++ /* Power down ODT. */ ++ ldr tmp1, [r3, #DDR3PHY_DSGCR] ++ orr tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0 ++ str tmp1, [r3, #DDR3PHY_DSGCR] ++.endm ++ ++/** ++ * Disable self-refresh ++ * ++ * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3 ++ */ ++.macro at91_sramc_self_refresh_dis ++ ldr r2, .sramc_base ++ ldr r3, .sramc_phy_base ++ ++ /* Power up DDR PHY data receivers. */ ++ ldr tmp1, [r3, #DDR3PHY_DXCCR] ++ bic tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR ++ str tmp1, [r3, #DDR3PHY_DXCCR] ++ ++ /* Power up the output of CK and CS pins. */ ++ ldr tmp1, [r3, #DDR3PHY_ACIOCR] ++ bic tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD ++ bic tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0 ++ bic tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0 ++ str tmp1, [r3, #DDR3PHY_ACIOCR] ++ ++ /* Power up ODT. */ ++ ldr tmp1, [r3, #DDR3PHY_DSGCR] ++ bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0 ++ str tmp1, [r3, #DDR3PHY_DSGCR] ++ ++ /* Take DDR PHY's DLL out of bypass mode. */ ++ ldr tmp1, [r3, #DDR3PHY_PIR] ++ bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP ++ str tmp1, [r3, #DDR3PHY_PIR] ++ ++ /* Enable quasi-dynamic programming. */ ++ mov tmp1, #0 ++ str tmp1, [r2, #UDDRC_SWCTRL] ++ ++ /* De-assert SDRAM initialization. */ ++ ldr tmp1, [r2, #UDDRC_DFIMISC] ++ bic tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN ++ str tmp1, [r2, #UDDRC_DFIMISC] ++ ++ /* Quasi-dynamic programming done. */ ++ mov tmp1, #UDDRC_SWCTRL_SW_DONE ++ str tmp1, [r2, #UDDRC_SWCTRL] ++ ++sr_dis_1: ++ ldr tmp1, [r2, #UDDRC_SWSTAT] ++ tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK ++ beq sr_dis_1 ++ ++ /* DLL soft-reset + DLL lock wait + ITM reset */ ++ mov tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \ ++ DDR3PHY_PIR_DLLLOCK | DDR3PHY_PIR_ITMSRST) ++ str tmp1, [r3, #DDR3PHY_PIR] ++ ++sr_dis_4: ++ /* Wait for it. */ ++ ldr tmp1, [r3, #DDR3PHY_PGSR] ++ tst tmp1, #DDR3PHY_PGSR_IDONE ++ beq sr_dis_4 ++ ++ /* Enable quasi-dynamic programming. */ ++ mov tmp1, #0 ++ str tmp1, [r2, #UDDRC_SWCTRL] ++ ++ /* Assert PHY init complete enable signal. */ ++ ldr tmp1, [r2, #UDDRC_DFIMISC] ++ orr tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN ++ str tmp1, [r2, #UDDRC_DFIMISC] ++ ++ /* Programming is done. Set sw_done. */ ++ mov tmp1, #UDDRC_SWCTRL_SW_DONE ++ str tmp1, [r2, #UDDRC_SWCTRL] ++ ++sr_dis_5: ++ /* Wait for it. */ ++ ldr tmp1, [r2, #UDDRC_SWSTAT] ++ tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK ++ beq sr_dis_5 ++ ++ /* Trigger self-refresh exit. */ ++ ldr tmp1, [r2, #UDDRC_PWRCTL] ++ bic tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW ++ str tmp1, [r2, #UDDRC_PWRCTL] ++ ++sr_dis_6: ++ /* Wait for self-refresh exit done. */ ++ ldr tmp1, [r2, #UDDRC_STAT] ++ bic tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK ++ cmp tmp1, #UDDRC_STAT_OPMODE_NORMAL ++ bne sr_dis_6 ++ ++ /* Enable all AXI ports. */ ++ ldr tmp1, [r2, #UDDRC_PCTRL_0] ++ orr tmp1, tmp1, #0x1 ++ str tmp1, [r2, #UDDRC_PCTRL_0] ++ ++ ldr tmp1, [r2, #UDDRC_PCTRL_1] ++ orr tmp1, tmp1, #0x1 ++ str tmp1, [r2, #UDDRC_PCTRL_1] ++ ++ ldr tmp1, [r2, #UDDRC_PCTRL_2] ++ orr tmp1, tmp1, #0x1 ++ str tmp1, [r2, #UDDRC_PCTRL_2] ++ ++ ldr tmp1, [r2, #UDDRC_PCTRL_3] ++ orr tmp1, tmp1, #0x1 ++ str tmp1, [r2, #UDDRC_PCTRL_3] ++ ++ ldr tmp1, [r2, #UDDRC_PCTRL_4] ++ orr tmp1, tmp1, #0x1 ++ str tmp1, [r2, #UDDRC_PCTRL_4] ++ ++ dsb ++.endm ++#else + /** + * Enable self-refresh + * +@@ -228,6 +422,7 @@ sdramc_exit_sf: + + sr_dis_exit: + .endm ++#endif + + .macro at91_pm_ulp0_mode + ldr pmc, .pmc_base +@@ -668,6 +863,8 @@ ENTRY(at91_pm_suspend_in_sram) + str tmp1, .sramc_base + ldr tmp1, [r0, #PM_DATA_RAMC1] + str tmp1, .sramc1_base ++ ldr tmp1, [r0, #PM_DATA_RAMC_PHY] ++ str tmp1, .sramc_phy_base + ldr tmp1, [r0, #PM_DATA_MEMCTRL] + str tmp1, .memtype + ldr tmp1, [r0, #PM_DATA_MODE] +@@ -721,6 +918,8 @@ ENDPROC(at91_pm_suspend_in_sram) + .word 0 + .sramc1_base: + .word 0 ++.sramc_phy_base: ++ .word 0 + .shdwc: + .word 0 + .sfrbu: diff --git a/target/linux/at91/patches-5.15/209-ARM-at91-pm-add-support-for-MCK1.4-save-restore-for-.patch b/target/linux/at91/patches-5.15/209-ARM-at91-pm-add-support-for-MCK1.4-save-restore-for-.patch new file mode 100644 index 0000000000..7c8614125c --- /dev/null +++ b/target/linux/at91/patches-5.15/209-ARM-at91-pm-add-support-for-MCK1.4-save-restore-for-.patch @@ -0,0 +1,165 @@ +From 9ee7fd7aa956671727752dac6bd131cf511c1137 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:49:59 +0300 +Subject: [PATCH 209/247] ARM: at91: pm: add support for MCK1..4 save/restore + for ulp modes + +Add support for MCK1..4 save restore for ULP modes. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-14-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm_suspend.S | 126 ++++++++++++++++++++++++++++++++ + 1 file changed, 126 insertions(+) + +--- a/arch/arm/mach-at91/pm_suspend.S ++++ b/arch/arm/mach-at91/pm_suspend.S +@@ -765,7 +765,122 @@ sr_dis_exit: + 2: + .endm + ++/** ++ * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock ++ * ++ * Side effects: overwrites tmp1, tmp2 ++ */ ++.macro at91_mckx_ps_enable ++#ifdef CONFIG_SOC_SAMA7 ++ ldr pmc, .pmc_base ++ ++ /* There are 4 MCKs we need to handle: MCK1..4 */ ++ mov tmp1, #1 ++e_loop: cmp tmp1, #5 ++ beq e_done ++ ++ /* Write MCK ID to retrieve the settings. */ ++ str tmp1, [pmc, #AT91_PMC_MCR_V2] ++ ldr tmp2, [pmc, #AT91_PMC_MCR_V2] ++ ++e_save_mck1: ++ cmp tmp1, #1 ++ bne e_save_mck2 ++ str tmp2, .saved_mck1 ++ b e_ps ++ ++e_save_mck2: ++ cmp tmp1, #2 ++ bne e_save_mck3 ++ str tmp2, .saved_mck2 ++ b e_ps ++ ++e_save_mck3: ++ cmp tmp1, #3 ++ bne e_save_mck4 ++ str tmp2, .saved_mck3 ++ b e_ps ++ ++e_save_mck4: ++ str tmp2, .saved_mck4 ++ ++e_ps: ++ /* Use CSS=MAINCK and DIV=1. */ ++ bic tmp2, tmp2, #AT91_PMC_MCR_V2_CSS ++ bic tmp2, tmp2, #AT91_PMC_MCR_V2_DIV ++ orr tmp2, tmp2, #AT91_PMC_MCR_V2_CSS_MAINCK ++ orr tmp2, tmp2, #AT91_PMC_MCR_V2_DIV1 ++ str tmp2, [pmc, #AT91_PMC_MCR_V2] ++ ++ wait_mckrdy tmp1 ++ ++ add tmp1, tmp1, #1 ++ b e_loop ++ ++e_done: ++#endif ++.endm ++ ++/** ++ * at91_mckx_ps_restore: restore MCK1..4 settings ++ * ++ * Side effects: overwrites tmp1, tmp2 ++ */ ++.macro at91_mckx_ps_restore ++#ifdef CONFIG_SOC_SAMA7 ++ ldr pmc, .pmc_base ++ ++ /* There are 4 MCKs we need to handle: MCK1..4 */ ++ mov tmp1, #1 ++r_loop: cmp tmp1, #5 ++ beq r_done ++ ++r_save_mck1: ++ cmp tmp1, #1 ++ bne r_save_mck2 ++ ldr tmp2, .saved_mck1 ++ b r_ps ++ ++r_save_mck2: ++ cmp tmp1, #2 ++ bne r_save_mck3 ++ ldr tmp2, .saved_mck2 ++ b r_ps ++ ++r_save_mck3: ++ cmp tmp1, #3 ++ bne r_save_mck4 ++ ldr tmp2, .saved_mck3 ++ b r_ps ++ ++r_save_mck4: ++ ldr tmp2, .saved_mck4 ++ ++r_ps: ++ /* Write MCK ID to retrieve the settings. */ ++ str tmp1, [pmc, #AT91_PMC_MCR_V2] ++ ldr tmp3, [pmc, #AT91_PMC_MCR_V2] ++ ++ /* We need to restore CSS and DIV. */ ++ bic tmp3, tmp3, #AT91_PMC_MCR_V2_CSS ++ bic tmp3, tmp3, #AT91_PMC_MCR_V2_DIV ++ orr tmp3, tmp3, tmp2 ++ bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK ++ orr tmp3, tmp3, tmp1 ++ orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD ++ str tmp2, [pmc, #AT91_PMC_MCR_V2] ++ ++ wait_mckrdy tmp1 ++ ++ add tmp1, tmp1, #1 ++ b r_loop ++r_done: ++#endif ++.endm ++ + .macro at91_ulp_mode ++ at91_mckx_ps_enable ++ + ldr pmc, .pmc_base + ldr tmp2, .mckr_offset + ldr tmp3, .pm_mode +@@ -817,6 +932,7 @@ ulp_exit: + mov tmp3, #0 + wait_mckrdy tmp3 + ++ at91_mckx_ps_restore + .endm + + .macro at91_backup_mode +@@ -946,6 +1062,16 @@ ENDPROC(at91_pm_suspend_in_sram) + .word 0 + .saved_osc_status: + .word 0 ++#ifdef CONFIG_SOC_SAMA7 ++.saved_mck1: ++ .word 0 ++.saved_mck2: ++ .word 0 ++.saved_mck3: ++ .word 0 ++.saved_mck4: ++ .word 0 ++#endif + + ENTRY(at91_pm_suspend_in_sram_sz) + .word .-at91_pm_suspend_in_sram diff --git a/target/linux/at91/patches-5.15/210-ARM-at91-pm-add-support-for-2.5V-LDO-regulator-contr.patch b/target/linux/at91/patches-5.15/210-ARM-at91-pm-add-support-for-2.5V-LDO-regulator-contr.patch new file mode 100644 index 0000000000..ede839bf70 --- /dev/null +++ b/target/linux/at91/patches-5.15/210-ARM-at91-pm-add-support-for-2.5V-LDO-regulator-contr.patch @@ -0,0 +1,79 @@ +From b2073cc043612bf95b115bd94103cfb2936f05bf Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:50:00 +0300 +Subject: [PATCH 210/247] ARM: at91: pm: add support for 2.5V LDO regulator + control + +Add support to disable/enable 2.5V LDO regulator when entering/exiting +any ULP mode. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-15-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.h | 1 + + arch/arm/mach-at91/pm_suspend.S | 29 +++++++++++++++++++++++++++++ + 2 files changed, 30 insertions(+) + +--- a/arch/arm/mach-at91/pm.h ++++ b/arch/arm/mach-at91/pm.h +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + + #define AT91_MEMCTRL_MC 0 + #define AT91_MEMCTRL_SDRAMC 1 +--- a/arch/arm/mach-at91/pm_suspend.S ++++ b/arch/arm/mach-at91/pm_suspend.S +@@ -83,6 +83,29 @@ tmp3 .req r6 + + .endm + ++/** ++ * Set state for 2.5V low power regulator ++ * @ena: 0 - disable regulator ++ * 1 - enable regulator ++ * ++ * Side effects: overwrites r7, r8, r9, r10 ++ */ ++ .macro at91_2_5V_reg_set_low_power ena ++#ifdef CONFIG_SOC_SAMA7 ++ ldr r7, .sfrbu ++ mov r8, #\ena ++ ldr r9, [r7, #AT91_SFRBU_25LDOCR] ++ orr r9, r9, #AT91_SFRBU_25LDOCR_LP ++ cmp r8, #1 ++ beq lp_done_\ena ++ bic r9, r9, #AT91_SFRBU_25LDOCR_LP ++lp_done_\ena: ++ ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY ++ orr r9, r9, r10 ++ str r9, [r7, #AT91_SFRBU_25LDOCR] ++#endif ++ .endm ++ + .text + + .arm +@@ -906,6 +929,9 @@ save_mck: + + at91_plla_disable + ++ /* Enable low power mode for 2.5V regulator. */ ++ at91_2_5V_reg_set_low_power 1 ++ + ldr tmp3, .pm_mode + cmp tmp3, #AT91_PM_ULP1 + beq ulp1_mode +@@ -918,6 +944,9 @@ ulp1_mode: + b ulp_exit + + ulp_exit: ++ /* Disable low power mode for 2.5V regulator. */ ++ at91_2_5V_reg_set_low_power 0 ++ + ldr pmc, .pmc_base + + at91_plla_enable diff --git a/target/linux/at91/patches-5.15/211-ARM-at91-pm-wait-for-ddr-power-mode-off.patch b/target/linux/at91/patches-5.15/211-ARM-at91-pm-wait-for-ddr-power-mode-off.patch new file mode 100644 index 0000000000..886f81e7ad --- /dev/null +++ b/target/linux/at91/patches-5.15/211-ARM-at91-pm-wait-for-ddr-power-mode-off.patch @@ -0,0 +1,28 @@ +From 2b522a22243938dd7613e09c954172b1fa6217f5 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:50:01 +0300 +Subject: [PATCH 211/247] ARM: at91: pm: wait for ddr power mode off + +Wait for DDR power mode off before shutting down the core. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-16-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm_suspend.S | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm/mach-at91/pm_suspend.S ++++ b/arch/arm/mach-at91/pm_suspend.S +@@ -980,6 +980,11 @@ ulp_exit: + mov tmp1, #0x1 + str tmp1, [r0, #0x10] + ++ /* Wait for it. */ ++1: ldr tmp1, [r0, #0x10] ++ tst tmp1, #0x1 ++ beq 1b ++ + /* Shutdown */ + ldr r0, .shdwc + mov tmp1, #0xA5000000 diff --git a/target/linux/at91/patches-5.15/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch b/target/linux/at91/patches-5.15/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch new file mode 100644 index 0000000000..e496245061 --- /dev/null +++ b/target/linux/at91/patches-5.15/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch @@ -0,0 +1,40 @@ +From 3f55310c00b8c478da1458704027036c1a414973 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:50:03 +0300 +Subject: [PATCH 212/247] ARM: at91: pm: add sama7g5 ddr controller + +Add SAMA7G5 DDR controller to the list of DDR controller compatibles. +At the moment there is no standby support. Adapt the code for this. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -548,6 +548,7 @@ static const struct of_device_id ramc_id + { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, + { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, + { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, ++ { .compatible = "microchip,sama7g5-uddrc", }, + { /*sentinel*/ } + }; + +@@ -569,9 +570,11 @@ static __init int at91_dt_ramc(void) + } + + ramc = of_id->data; +- if (!standby) +- standby = ramc->idle; +- soc_pm.data.memctrl = ramc->memctrl; ++ if (ramc) { ++ if (!standby) ++ standby = ramc->idle; ++ soc_pm.data.memctrl = ramc->memctrl; ++ } + + idx++; + } diff --git a/target/linux/at91/patches-5.15/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch b/target/linux/at91/patches-5.15/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch new file mode 100644 index 0000000000..89dcacec92 --- /dev/null +++ b/target/linux/at91/patches-5.15/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch @@ -0,0 +1,94 @@ +From bbbbf16c44f34a2d563fa7d71de64ffe3b4b82dc Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:50:04 +0300 +Subject: [PATCH 213/247] ARM: at91: pm: add sama7g5 ddr phy controller + +SAMA7G5 self-refresh procedure accesses also the DDR PHY registers. +Adapt the code so that the at91_dt_ramc() to look also for DDR PHYs, +in case it is mandatory. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-19-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 27 +++++++++++++++++++++------ + 1 file changed, 21 insertions(+), 6 deletions(-) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -552,7 +552,12 @@ static const struct of_device_id ramc_id + { /*sentinel*/ } + }; + +-static __init int at91_dt_ramc(void) ++static const struct of_device_id ramc_phy_ids[] __initconst = { ++ { .compatible = "microchip,sama7g5-ddr3phy", }, ++ { /* Sentinel. */ }, ++}; ++ ++static __init void at91_dt_ramc(bool phy_mandatory) + { + struct device_node *np; + const struct of_device_id *of_id; +@@ -585,6 +590,16 @@ static __init int at91_dt_ramc(void) + goto unmap_ramc; + } + ++ /* Lookup for DDR PHY node, if any. */ ++ for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) { ++ soc_pm.data.ramc_phy = of_iomap(np, 0); ++ if (!soc_pm.data.ramc_phy) ++ panic(pr_fmt("unable to map ramc phy cpu registers\n")); ++ } ++ ++ if (phy_mandatory && !soc_pm.data.ramc_phy) ++ panic(pr_fmt("DDR PHY is mandatory!\n")); ++ + if (!standby) { + pr_warn("ramc no standby function available\n"); + return 0; +@@ -953,7 +968,7 @@ void __init at91rm9200_pm_init(void) + soc_pm.data.standby_mode = AT91_PM_STANDBY; + soc_pm.data.suspend_mode = AT91_PM_ULP0; + +- ret = at91_dt_ramc(); ++ ret = at91_dt_ramc(false); + if (ret) + return; + +@@ -980,7 +995,7 @@ void __init sam9x60_pm_init(void) + + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); + at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); +- ret = at91_dt_ramc(); ++ ret = at91_dt_ramc(false); + if (ret) + return; + +@@ -1005,7 +1020,7 @@ void __init at91sam9_pm_init(void) + soc_pm.data.standby_mode = AT91_PM_STANDBY; + soc_pm.data.suspend_mode = AT91_PM_ULP0; + +- ret = at91_dt_ramc(); ++ ret = at91_dt_ramc(false); + if (ret) + return; + +@@ -1023,7 +1038,7 @@ void __init sama5_pm_init(void) + return; + + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); +- ret = at91_dt_ramc(); ++ ret = at91_dt_ramc(false); + if (ret) + return; + +@@ -1048,7 +1063,7 @@ void __init sama5d2_pm_init(void) + + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); + at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); +- ret = at91_dt_ramc(); ++ ret = at91_dt_ramc(false); + if (ret) + return; + diff --git a/target/linux/at91/patches-5.15/214-ARM-at91-pm-save-ddr-phy-calibration-data-to-securam.patch b/target/linux/at91/patches-5.15/214-ARM-at91-pm-save-ddr-phy-calibration-data-to-securam.patch new file mode 100644 index 0000000000..a46b5acb22 --- /dev/null +++ b/target/linux/at91/patches-5.15/214-ARM-at91-pm-save-ddr-phy-calibration-data-to-securam.patch @@ -0,0 +1,151 @@ +From b355bb98eae3e343969fc5a0203e0dab472a6acd Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:50:05 +0300 +Subject: [PATCH 214/247] ARM: at91: pm: save ddr phy calibration data to + securam + +The resuming from backup mode is done with the help of bootloader. +The bootloader reconfigure the DDR controller and DDR PHY controller. +To speed-up the resuming process save the PHY calibration data into +SECURAM before suspending (securam is powered on backup mode). +This data will be later used by bootloader in DDR PHY reconfiguration +process. Also, in the process or recalibration the first 8 words of +the memory may get corrupted. To solve this, these 8 words are saved +in the securam and restored by bootloader in the process of PHY +configuration. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-20-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 60 ++++++++++++++++++++++++++++++++++++++++- + 1 file changed, 59 insertions(+), 1 deletion(-) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -27,18 +28,23 @@ + #include "generic.h" + #include "pm.h" + ++#define BACKUP_DDR_PHY_CALIBRATION (9) ++ + /** + * struct at91_pm_bu - AT91 power management backup unit data structure + * @suspended: true if suspended to backup mode + * @reserved: reserved + * @canary: canary data for memory checking after exit from backup mode + * @resume: resume API ++ * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words ++ * of the memory + */ + struct at91_pm_bu { + int suspended; + unsigned long reserved; + phys_addr_t canary; + phys_addr_t resume; ++ unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; + }; + + /** +@@ -48,6 +54,7 @@ struct at91_pm_bu { + * @ws_ids: wakup sources of_device_id array + * @data: PM data to be used on last phase of suspend + * @bu: backup unit mapped data (for backup mode) ++ * @memcs: memory chip select + */ + struct at91_soc_pm { + int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); +@@ -55,6 +62,7 @@ struct at91_soc_pm { + const struct of_device_id *ws_ids; + struct at91_pm_bu *bu; + struct at91_pm_data data; ++ void *memcs; + }; + + /** +@@ -316,6 +324,19 @@ extern u32 at91_pm_suspend_in_sram_sz; + + static int at91_suspend_finish(unsigned long val) + { ++ int i; ++ ++ if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) { ++ /* ++ * The 1st 8 words of memory might get corrupted in the process ++ * of DDR PHY recalibration; it is saved here in securam and it ++ * will be restored later, after recalibration, by bootloader ++ */ ++ for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++) ++ soc_pm.bu->ddr_phy_calibration[i] = ++ *((unsigned int *)soc_pm.memcs + (i - 1)); ++ } ++ + flush_cache_all(); + outer_disable(); + +@@ -688,12 +709,40 @@ static bool __init at91_is_pm_mode_activ + soc_pm.data.suspend_mode == pm_mode); + } + ++static int __init at91_pm_backup_scan_memcs(unsigned long node, ++ const char *uname, int depth, ++ void *data) ++{ ++ const char *type; ++ const __be32 *reg; ++ int *located = data; ++ int size; ++ ++ /* Memory node already located. */ ++ if (*located) ++ return 0; ++ ++ type = of_get_flat_dt_prop(node, "device_type", NULL); ++ ++ /* We are scanning "memory" nodes only. */ ++ if (!type || strcmp(type, "memory")) ++ return 0; ++ ++ reg = of_get_flat_dt_prop(node, "reg", &size); ++ if (reg) { ++ soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg)); ++ *located = 1; ++ } ++ ++ return 0; ++} ++ + static int __init at91_pm_backup_init(void) + { + struct gen_pool *sram_pool; + struct device_node *np; + struct platform_device *pdev; +- int ret = -ENODEV; ++ int ret = -ENODEV, located = 0; + + if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) + return -EPERM; +@@ -728,6 +777,15 @@ static int __init at91_pm_backup_init(vo + soc_pm.bu->suspended = 0; + soc_pm.bu->canary = __pa_symbol(&canary); + soc_pm.bu->resume = __pa_symbol(cpu_resume); ++ if (soc_pm.data.ramc_phy) { ++ of_scan_flat_dt(at91_pm_backup_scan_memcs, &located); ++ if (!located) ++ goto securam_fail; ++ ++ /* DDR3PHY_ZQ0SR0 */ ++ soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy + ++ 0x188); ++ } + + return 0; + diff --git a/target/linux/at91/patches-5.15/215-ARM-at91-pm-add-backup-mode-support-for-SAMA7G5.patch b/target/linux/at91/patches-5.15/215-ARM-at91-pm-add-backup-mode-support-for-SAMA7G5.patch new file mode 100644 index 0000000000..cc5f4aec0a --- /dev/null +++ b/target/linux/at91/patches-5.15/215-ARM-at91-pm-add-backup-mode-support-for-SAMA7G5.patch @@ -0,0 +1,52 @@ +From 62be32b56ff31b2cd048a53fac40a165c5bc66cd Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:50:06 +0300 +Subject: [PATCH 215/247] ARM: at91: pm: add backup mode support for SAMA7G5 + +Adapt at91_pm_backup_init() to work for SAMA7G5. Also, set the LPM pin +to shutdown controller. This will signal to PMIC that it needs to switch +to the state corresponding to backup mode. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-21-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 3 ++- + arch/arm/mach-at91/pm_suspend.S | 7 +++++++ + 2 files changed, 9 insertions(+), 1 deletion(-) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -744,7 +744,8 @@ static int __init at91_pm_backup_init(vo + struct platform_device *pdev; + int ret = -ENODEV, located = 0; + +- if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) ++ if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && ++ !IS_ENABLED(CONFIG_SOC_SAMA7G5)) + return -EPERM; + + if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) +--- a/arch/arm/mach-at91/pm_suspend.S ++++ b/arch/arm/mach-at91/pm_suspend.S +@@ -106,6 +106,12 @@ lp_done_\ena: + #endif + .endm + ++ .macro at91_backup_set_lpm reg ++#ifdef CONFIG_SOC_SAMA7 ++ orr \reg, \reg, #0x200000 ++#endif ++ .endm ++ + .text + + .arm +@@ -989,6 +995,7 @@ ulp_exit: + ldr r0, .shdwc + mov tmp1, #0xA5000000 + add tmp1, tmp1, #0x1 ++ at91_backup_set_lpm tmp1 + str tmp1, [r0, #0] + .endm + diff --git a/target/linux/at91/patches-5.15/216-ARM-at91-pm-add-sama7g5-s-pmc.patch b/target/linux/at91/patches-5.15/216-ARM-at91-pm-add-sama7g5-s-pmc.patch new file mode 100644 index 0000000000..a471195fbc --- /dev/null +++ b/target/linux/at91/patches-5.15/216-ARM-at91-pm-add-sama7g5-s-pmc.patch @@ -0,0 +1,36 @@ +From e9855ac00e8d9a2c41cea42b4f38a2b0b010bef3 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:50:07 +0300 +Subject: [PATCH 216/247] ARM: at91: pm: add sama7g5's pmc + +Add SAMA7G5's PMC to compatible list. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-22-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -912,6 +912,11 @@ static const struct pmc_info pmc_infos[] + .mckr = 0x28, + .version = AT91_PMC_V2, + }, ++ { ++ .mckr = 0x28, ++ .version = AT91_PMC_V2, ++ }, ++ + }; + + static const struct of_device_id atmel_pmc_ids[] __initconst = { +@@ -927,6 +932,7 @@ static const struct of_device_id atmel_p + { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, + { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, + { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, ++ { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, + { /* sentinel */ }, + }; + diff --git a/target/linux/at91/patches-5.15/217-ARM-at91-sama7-introduce-sama7-SoC-family.patch b/target/linux/at91/patches-5.15/217-ARM-at91-sama7-introduce-sama7-SoC-family.patch new file mode 100644 index 0000000000..dca065971b --- /dev/null +++ b/target/linux/at91/patches-5.15/217-ARM-at91-sama7-introduce-sama7-SoC-family.patch @@ -0,0 +1,63 @@ +From dea645bce478cc72a2bf2413ec873927d1471442 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Thu, 15 Apr 2021 13:50:08 +0300 +Subject: [PATCH 217/247] ARM: at91: sama7: introduce sama7 SoC family + +Introduce new family of SoCs, sama7, and first SoC, sama7g5. + +Signed-off-by: Eugen Hristev +[claudiu.beznea@microchip.com: keep only the sama7_dt] +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-23-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/Makefile | 1 + + arch/arm/mach-at91/sama7.c | 32 ++++++++++++++++++++++++++++++++ + 2 files changed, 33 insertions(+) + create mode 100644 arch/arm/mach-at91/sama7.c + +--- a/arch/arm/mach-at91/Makefile ++++ b/arch/arm/mach-at91/Makefile +@@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_AT91RM9200) += at91rm92 + obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o + obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o + obj-$(CONFIG_SOC_SAMA5) += sama5.o ++obj-$(CONFIG_SOC_SAMA7) += sama7.o + obj-$(CONFIG_SOC_SAMV7) += samv7.o + + # Power Management +--- /dev/null ++++ b/arch/arm/mach-at91/sama7.c +@@ -0,0 +1,32 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Setup code for SAMA7 ++ * ++ * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries ++ * ++ */ ++ ++#include ++#include ++ ++#include ++#include ++ ++#include "generic.h" ++ ++static void __init sama7_dt_device_init(void) ++{ ++ of_platform_default_populate(NULL, NULL, NULL); ++} ++ ++static const char *const sama7_dt_board_compat[] __initconst = { ++ "microchip,sama7", ++ NULL ++}; ++ ++DT_MACHINE_START(sama7_dt, "Microchip SAMA7") ++ /* Maintainer: Microchip */ ++ .init_machine = sama7_dt_device_init, ++ .dt_compat = sama7_dt_board_compat, ++MACHINE_END ++ diff --git a/target/linux/at91/patches-5.15/218-ARM-at91-pm-add-pm-support-for-SAMA7G5.patch b/target/linux/at91/patches-5.15/218-ARM-at91-pm-add-pm-support-for-SAMA7G5.patch new file mode 100644 index 0000000000..aada9c9679 --- /dev/null +++ b/target/linux/at91/patches-5.15/218-ARM-at91-pm-add-pm-support-for-SAMA7G5.patch @@ -0,0 +1,96 @@ +From aba3984dc7a405d20b83bff603d23719d0e26bc7 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:50:09 +0300 +Subject: [PATCH 218/247] ARM: at91: pm: add pm support for SAMA7G5 + +Add support for SAMA7G5 power management modes: standby, ulp0, ulp1, backup. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-24-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/generic.h | 2 ++ + arch/arm/mach-at91/pm.c | 37 ++++++++++++++++++++++++++++++++++++ + arch/arm/mach-at91/sama7.c | 1 + + 3 files changed, 40 insertions(+) + +--- a/arch/arm/mach-at91/generic.h ++++ b/arch/arm/mach-at91/generic.h +@@ -14,12 +14,14 @@ extern void __init at91sam9_pm_init(void + extern void __init sam9x60_pm_init(void); + extern void __init sama5_pm_init(void); + extern void __init sama5d2_pm_init(void); ++extern void __init sama7_pm_init(void); + #else + static inline void __init at91rm9200_pm_init(void) { } + static inline void __init at91sam9_pm_init(void) { } + static inline void __init sam9x60_pm_init(void) { } + static inline void __init sama5_pm_init(void) { } + static inline void __init sama5d2_pm_init(void) { } ++static inline void __init sama7_pm_init(void) { } + #endif + + #endif /* _AT91_GENERIC_H */ +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -152,6 +152,17 @@ static const struct of_device_id sam9x60 + { /* sentinel */ } + }; + ++static const struct of_device_id sama7g5_ws_ids[] = { ++ { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, ++ { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, ++ { .compatible = "usb-ohci", .data = &ws_info[2] }, ++ { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, ++ { .compatible = "usb-ehci", .data = &ws_info[2] }, ++ { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, ++ { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, ++ { /* sentinel */ } ++}; ++ + static int at91_pm_config_ws(unsigned int pm_mode, bool set) + { + const struct wakeup_source_info *wsi; +@@ -1139,6 +1150,32 @@ void __init sama5d2_pm_init(void) + soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; + } + ++void __init sama7_pm_init(void) ++{ ++ static const int modes[] __initconst = { ++ AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, ++ }; ++ static const u32 iomaps[] __initconst = { ++ [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU), ++ [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) | ++ AT91_PM_IOMAP(SHDWC), ++ [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | ++ AT91_PM_IOMAP(SHDWC), ++ }; ++ ++ if (!IS_ENABLED(CONFIG_SOC_SAMA7)) ++ return; ++ ++ at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); ++ ++ at91_dt_ramc(true); ++ at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); ++ at91_pm_init(NULL); ++ ++ soc_pm.ws_ids = sama7g5_ws_ids; ++ soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; ++} ++ + static int __init at91_pm_modes_select(char *str) + { + char *s; +--- a/arch/arm/mach-at91/sama7.c ++++ b/arch/arm/mach-at91/sama7.c +@@ -17,6 +17,7 @@ + static void __init sama7_dt_device_init(void) + { + of_platform_default_populate(NULL, NULL, NULL); ++ sama7_pm_init(); + } + + static const char *const sama7_dt_board_compat[] __initconst = { diff --git a/target/linux/at91/patches-5.15/219-ARM-at91-pm-add-sama7g5-shdwc.patch b/target/linux/at91/patches-5.15/219-ARM-at91-pm-add-sama7g5-shdwc.patch new file mode 100644 index 0000000000..062274c18f --- /dev/null +++ b/target/linux/at91/patches-5.15/219-ARM-at91-pm-add-sama7g5-shdwc.patch @@ -0,0 +1,24 @@ +From 84ff37cc98e6aaefe27d6edd5e3ced2be99d9833 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 15 Apr 2021 13:50:10 +0300 +Subject: [PATCH 219/247] ARM: at91: pm: add sama7g5 shdwc + +Add SAMA7G5 SHDWC. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210415105010.569620-25-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -809,6 +809,7 @@ securam_fail: + static const struct of_device_id atmel_shdwc_ids[] = { + { .compatible = "atmel,sama5d2-shdwc" }, + { .compatible = "microchip,sam9x60-shdwc" }, ++ { .compatible = "microchip,sama7g5-shdwc" }, + { /* sentinel. */ } + }; + diff --git a/target/linux/at91/patches-5.15/220-ARM-configs-at91-add-defconfig-for-sama7-family-of-S.patch b/target/linux/at91/patches-5.15/220-ARM-configs-at91-add-defconfig-for-sama7-family-of-S.patch new file mode 100644 index 0000000000..fdb45afa7d --- /dev/null +++ b/target/linux/at91/patches-5.15/220-ARM-configs-at91-add-defconfig-for-sama7-family-of-S.patch @@ -0,0 +1,233 @@ +From 2223a85aed2d892bd7c13053f27e777c743e5332 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Mon, 28 Jun 2021 15:04:51 +0300 +Subject: [PATCH 220/247] ARM: configs: at91: add defconfig for sama7 family of + SoCs + +Add defconfig for sama7 SoC family. + +Signed-off-by: Eugen Hristev +[claudiu.beznea@microchip.com: add clocks, ethernet, timers, power] +Signed-off-by: Claudiu Beznea +[codrin.ciubotariu@microchip.com: add audio] +Signed-off-by: Codrin Ciubotariu +[nicolas.ferre@microchip.com: atags not set, mtd tests, spi gpio] +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210628120452.74408-3-eugen.hristev@microchip.com +--- + arch/arm/configs/sama7_defconfig | 209 +++++++++++++++++++++++++++++++ + 1 file changed, 209 insertions(+) + create mode 100644 arch/arm/configs/sama7_defconfig + +--- /dev/null ++++ b/arch/arm/configs/sama7_defconfig +@@ -0,0 +1,209 @@ ++# CONFIG_LOCALVERSION_AUTO is not set ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_NO_HZ_IDLE=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_LOG_BUF_SHIFT=16 ++CONFIG_CGROUPS=y ++CONFIG_CGROUP_DEBUG=y ++CONFIG_NAMESPACES=y ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++CONFIG_BLK_DEV_INITRD=y ++# CONFIG_FHANDLE is not set ++# CONFIG_IO_URING is not set ++CONFIG_KALLSYMS_ALL=y ++CONFIG_EMBEDDED=y ++# CONFIG_VM_EVENT_COUNTERS is not set ++CONFIG_SLAB=y ++CONFIG_ARCH_AT91=y ++CONFIG_SOC_SAMA7G5=y ++CONFIG_ATMEL_CLOCKSOURCE_TCB=y ++# CONFIG_CACHE_L2X0 is not set ++# CONFIG_ARM_PATCH_IDIV is not set ++# CONFIG_CPU_SW_DOMAIN_PAN is not set ++CONFIG_FORCE_MAX_ZONEORDER=15 ++CONFIG_UACCESS_WITH_MEMCPY=y ++# CONFIG_ATAGS is not set ++CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk ignore_loglevel" ++CONFIG_VFP=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_BLK_DEV_BSG is not set ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_COREDUMP is not set ++# CONFIG_COMPACTION is not set ++CONFIG_CMA=y ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++# CONFIG_INET_DIAG is not set ++CONFIG_IPV6_SIT_6RD=y ++CONFIG_BRIDGE=m ++CONFIG_BRIDGE_VLAN_FILTERING=y ++CONFIG_NET_DSA=m ++CONFIG_VLAN_8021Q=m ++CONFIG_CAN=y ++CONFIG_CAN_M_CAN=y ++CONFIG_CAN_M_CAN_PLATFORM=y ++CONFIG_BT=y ++CONFIG_BT_RFCOMM=y ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=y ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=y ++CONFIG_BT_HCIBTUSB=y ++CONFIG_BT_HCIUART=y ++CONFIG_BT_HCIUART_H4=y ++CONFIG_BT_HCIVHCI=y ++CONFIG_CFG80211=m ++# CONFIG_CFG80211_DEFAULT_PS is not set ++CONFIG_CFG80211_DEBUGFS=y ++CONFIG_CFG80211_WEXT=y ++CONFIG_MAC80211=m ++CONFIG_MAC80211_LEDS=y ++CONFIG_RFKILL=y ++CONFIG_RFKILL_INPUT=y ++CONFIG_PCCARD=y ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++CONFIG_MTD_CMDLINE_PARTS=y ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=1 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++CONFIG_EEPROM_AT24=y ++CONFIG_SCSI=y ++CONFIG_BLK_DEV_SD=y ++CONFIG_NETDEVICES=y ++CONFIG_MACB=y ++CONFIG_MICREL_PHY=y ++CONFIG_INPUT_EVDEV=y ++CONFIG_KEYBOARD_GPIO=y ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_LEGACY_PTY_COUNT=4 ++CONFIG_SERIAL_ATMEL=y ++CONFIG_SERIAL_ATMEL_CONSOLE=y ++CONFIG_HW_RANDOM=y ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_AT91=y ++CONFIG_SPI=y ++CONFIG_SPI_MEM=y ++CONFIG_SPI_ATMEL=y ++CONFIG_SPI_GPIO=y ++CONFIG_PINCTRL_AT91=y ++CONFIG_PINCTRL_AT91PIO4=y ++CONFIG_GPIO_SYSFS=y ++CONFIG_POWER_RESET=y ++CONFIG_POWER_RESET_AT91_RESET=y ++CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y ++# CONFIG_HWMON is not set ++CONFIG_WATCHDOG=y ++CONFIG_SAMA5D4_WATCHDOG=y ++CONFIG_MFD_ATMEL_FLEXCOM=y ++CONFIG_REGULATOR=y ++CONFIG_REGULATOR_FIXED_VOLTAGE=y ++CONFIG_REGULATOR_MCP16502=y ++CONFIG_MEDIA_SUPPORT=y ++CONFIG_MEDIA_SUPPORT_FILTER=y ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++CONFIG_MEDIA_PLATFORM_SUPPORT=y ++CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_IMX219=m ++CONFIG_VIDEO_IMX274=m ++CONFIG_VIDEO_OV5647=m ++CONFIG_SOUND=y ++CONFIG_SND=y ++CONFIG_SND_SOC=y ++CONFIG_SND_ATMEL_SOC=y ++CONFIG_SND_SOC_MIKROE_PROTO=m ++CONFIG_SND_MCHP_SOC_I2S_MCC=y ++CONFIG_SND_MCHP_SOC_SPDIFTX=y ++CONFIG_SND_MCHP_SOC_SPDIFRX=y ++CONFIG_SND_SOC_PCM5102A=y ++CONFIG_SND_SOC_SPDIF=y ++CONFIG_SND_SIMPLE_CARD=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_DYNAMIC_MINORS=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_STORAGE=y ++CONFIG_USB_UAS=y ++CONFIG_USB_GADGET=y ++CONFIG_U_SERIAL_CONSOLE=y ++CONFIG_USB_ATMEL_USBA=m ++CONFIG_USB_CONFIGFS=y ++CONFIG_USB_CONFIGFS_ACM=y ++CONFIG_USB_CONFIGFS_MASS_STORAGE=y ++CONFIG_USB_CONFIGFS_F_UVC=y ++CONFIG_USB_G_SERIAL=m ++CONFIG_MMC=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_SDHCI_OF_AT91=y ++CONFIG_NEW_LEDS=y ++CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_GPIO=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_RTC_CLASS=y ++# CONFIG_RTC_NVMEM is not set ++CONFIG_RTC_DRV_AT91RM9200=y ++CONFIG_RTC_DRV_AT91SAM9=y ++CONFIG_DMADEVICES=y ++CONFIG_AT_XDMAC=y ++CONFIG_DMATEST=y ++CONFIG_STAGING=y ++CONFIG_MICROCHIP_PIT64B=y ++# CONFIG_IOMMU_SUPPORT is not set ++# CONFIG_ATMEL_EBI is not set ++CONFIG_IIO=y ++CONFIG_IIO_SW_TRIGGER=y ++CONFIG_AT91_SAMA5D2_ADC=y ++CONFIG_PWM=y ++CONFIG_PWM_ATMEL=y ++CONFIG_EXT2_FS=y ++CONFIG_EXT3_FS=y ++CONFIG_FANOTIFY=y ++CONFIG_VFAT_FS=y ++CONFIG_TMPFS=y ++CONFIG_NFS_FS=y ++CONFIG_ROOT_NFS=y ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_850=y ++CONFIG_NLS_ISO8859_1=y ++CONFIG_NLS_UTF8=y ++CONFIG_LSM="N" ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_HW is not set ++CONFIG_CRC_CCITT=y ++CONFIG_CRC_ITU_T=y ++CONFIG_DMA_CMA=y ++CONFIG_CMA_SIZE_MBYTES=32 ++CONFIG_CMA_ALIGNMENT=9 ++# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_DEBUG_MISC is not set ++# CONFIG_SCHED_DEBUG is not set ++CONFIG_STACKTRACE=y ++# CONFIG_FTRACE is not set ++CONFIG_DEBUG_USER=y ++# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/target/linux/at91/patches-5.15/221-ARM-multi_v7_defconfig-add-sama7g5-SoC.patch b/target/linux/at91/patches-5.15/221-ARM-multi_v7_defconfig-add-sama7g5-SoC.patch new file mode 100644 index 0000000000..6c95d4a0f5 --- /dev/null +++ b/target/linux/at91/patches-5.15/221-ARM-multi_v7_defconfig-add-sama7g5-SoC.patch @@ -0,0 +1,33 @@ +From a62536054548e85da84ed835dc87baa8e5e99b41 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Mon, 28 Jun 2021 15:04:52 +0300 +Subject: [PATCH 221/247] ARM: multi_v7_defconfig: add sama7g5 SoC + +Add the Microchip SAMA7G5 ARM v7 Cortex-A7 based SoC to multi_v7_defconfig. +Also add it's clock timer, the PIT64B. + +Signed-off-by: Eugen Hristev +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210628120452.74408-4-eugen.hristev@microchip.com +--- + arch/arm/configs/multi_v7_defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm/configs/multi_v7_defconfig ++++ b/arch/arm/configs/multi_v7_defconfig +@@ -15,6 +15,7 @@ CONFIG_ARCH_AT91=y + CONFIG_SOC_SAMA5D2=y + CONFIG_SOC_SAMA5D3=y + CONFIG_SOC_SAMA5D4=y ++CONFIG_SOC_SAMA7G5=y + CONFIG_ARCH_BCM=y + CONFIG_ARCH_BCM_CYGNUS=y + CONFIG_ARCH_BCM_HR2=y +@@ -967,6 +968,7 @@ CONFIG_APQ_MMCC_8084=y + CONFIG_MSM_GCC_8660=y + CONFIG_MSM_MMCC_8960=y + CONFIG_MSM_MMCC_8974=y ++CONFIG_MICROCHIP_PIT64B=y + CONFIG_BCM2835_MBOX=y + CONFIG_ROCKCHIP_IOMMU=y + CONFIG_TEGRA_IOMMU_GART=y diff --git a/target/linux/at91/patches-5.15/222-ARM-dts-at91-add-sama7g5-SoC-DT-and-sama7g5-ek.patch b/target/linux/at91/patches-5.15/222-ARM-dts-at91-add-sama7g5-SoC-DT-and-sama7g5-ek.patch new file mode 100644 index 0000000000..b79ce5ab2e --- /dev/null +++ b/target/linux/at91/patches-5.15/222-ARM-dts-at91-add-sama7g5-SoC-DT-and-sama7g5-ek.patch @@ -0,0 +1,2154 @@ +From 969b39d51b7df0869cca9983b06cefb59dae72b0 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Mon, 28 Jun 2021 15:04:50 +0300 +Subject: [PATCH 222/247] ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek + +Add Device Tree for sama7g5 SoC and associated board sama7g5-ek + +Signed-off-by: Eugen Hristev +[claudiu.beznea@microchip.com: add clocks, ethernet, timers, power] +Signed-off-by: Claudiu Beznea +[codrin.ciubotariu@microchip.com: add audio] +Signed-off-by: Codrin Ciubotariu +[nicolas.ferre@microchip.com: removed eeproms, reorder i2s dma chans] +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210628120452.74408-2-eugen.hristev@microchip.com +[claudiu.beznea: adapt to kernel v5.10] +Signed-off-by: Claudiu Beznea +--- + arch/arm/boot/dts/Makefile | 2 + + arch/arm/boot/dts/at91-sama7g5ek.dts | 656 +++++++++++++++++++ + arch/arm/boot/dts/sama7g5-pinfunc.h | 923 +++++++++++++++++++++++++++ + arch/arm/boot/dts/sama7g5.dtsi | 528 +++++++++++++++ + 4 files changed, 2109 insertions(+) + create mode 100644 arch/arm/boot/dts/at91-sama7g5ek.dts + create mode 100644 arch/arm/boot/dts/sama7g5-pinfunc.h + create mode 100644 arch/arm/boot/dts/sama7g5.dtsi + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -79,6 +79,8 @@ dtb-$(CONFIG_ARCH_ATLAS6) += \ + atlas6-evb.dtb + dtb-$(CONFIG_ARCH_ATLAS7) += \ + atlas7-evb.dtb ++dtb-$(CONFIG_SOC_SAMA7G5) += \ ++ at91-sama7g5ek.dtb + dtb-$(CONFIG_ARCH_AXXIA) += \ + axm5516-amarillo.dtb + dtb-$(CONFIG_ARCH_BCM2835) += \ +--- /dev/null ++++ b/arch/arm/boot/dts/at91-sama7g5ek.dts +@@ -0,0 +1,656 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * at91-sama7g5ek.dts - Device Tree file for SAMA7G5-EK board ++ * ++ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries ++ * ++ * Author: Eugen Hristev ++ * Author: Claudiu Beznea ++ * ++ */ ++/dts-v1/; ++#include "sama7g5-pinfunc.h" ++#include "sama7g5.dtsi" ++#include ++#include ++ ++/ { ++ model = "Microchip SAMA7G5-EK"; ++ compatible = "microchip,sama7g5ek", "microchip,sama7g5", "microchip,sama7"; ++ ++ chosen { ++ bootargs = "rw root=/dev/mmcblk1p2 rootfstype=ext4 rootwait"; ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ aliases { ++ serial0 = &uart3; ++ serial1 = &uart4; ++ serial2 = &uart7; ++ serial3 = &uart0; ++ i2c0 = &i2c1; ++ i2c1 = &i2c8; ++ i2c2 = &i2c9; ++ }; ++ ++ clocks { ++ slow_xtal { ++ clock-frequency = <32768>; ++ }; ++ ++ main_xtal { ++ clock-frequency = <24000000>; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_key_gpio_default>; ++ ++ bp1 { ++ label = "PB_USER"; ++ gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ wakeup-source; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_led_gpio_default>; ++ status = "okay"; /* Conflict with pwm. */ ++ ++ red_led { ++ label = "red"; ++ gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ green_led { ++ label = "green"; ++ gpios = <&pioA PIN_PA13 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ blue_led { ++ label = "blue"; ++ gpios = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ /* 512 M */ ++ memory@60000000 { ++ device_type = "memory"; ++ reg = <0x60000000 0x20000000>; ++ }; ++ ++ sound: sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "sama7g5ek audio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ simple-audio-card,dai-link@0 { ++ reg = <0>; ++ cpu { ++ sound-dai = <&spdiftx>; ++ }; ++ codec { ++ sound-dai = <&spdif_out>; ++ }; ++ }; ++ simple-audio-card,dai-link@1 { ++ reg = <1>; ++ cpu { ++ sound-dai = <&spdifrx>; ++ }; ++ codec { ++ sound-dai = <&spdif_in>; ++ }; ++ }; ++ }; ++ ++ spdif_in: spdif-in { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dir"; ++ }; ++ ++ spdif_out: spdif-out { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vddcpu>; ++}; ++ ++&dma0 { ++ status = "okay"; ++}; ++ ++&dma1 { ++ status = "okay"; ++}; ++ ++&dma2 { ++ status = "okay"; ++}; ++ ++&flx0 { ++ atmel,flexcom-mode = ; ++ status = "disabled"; ++ ++ uart0: serial@200 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flx0_default>; ++ status = "disabled"; ++ }; ++}; ++ ++&flx1 { ++ atmel,flexcom-mode = ; ++ status = "okay"; ++ ++ i2c1: i2c@600 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1_default>; ++ i2c-analog-filter; ++ i2c-digital-filter; ++ i2c-digital-filter-width-ns = <35>; ++ status = "okay"; ++ ++ mcp16502@5b { ++ compatible = "microchip,mcp16502"; ++ reg = <0x5b>; ++ status = "okay"; ++ ++ regulators { ++ vdd_3v3: VDD_IO { ++ regulator-name = "VDD_IO"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <3700000>; ++ regulator-initial-mode = <2>; ++ regulator-allowed-modes = <2>, <4>; ++ regulator-always-on; ++ ++ regulator-state-standby { ++ regulator-on-in-suspend; ++ regulator-mode = <4>; ++ }; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-mode = <4>; ++ }; ++ }; ++ ++ vddioddr: VDD_DDR { ++ regulator-name = "VDD_DDR"; ++ regulator-min-microvolt = <1300000>; ++ regulator-max-microvolt = <1450000>; ++ regulator-initial-mode = <2>; ++ regulator-allowed-modes = <2>, <4>; ++ regulator-always-on; ++ ++ regulator-state-standby { ++ regulator-on-in-suspend; ++ regulator-mode = <4>; ++ }; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-mode = <4>; ++ }; ++ }; ++ ++ vddcore: VDD_CORE { ++ regulator-name = "VDD_CORE"; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1850000>; ++ regulator-initial-mode = <2>; ++ regulator-allowed-modes = <2>, <4>; ++ regulator-always-on; ++ ++ regulator-state-standby { ++ regulator-on-in-suspend; ++ regulator-mode = <4>; ++ }; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-mode = <4>; ++ }; ++ }; ++ ++ vddcpu: VDD_OTHER { ++ regulator-name = "VDD_OTHER"; ++ regulator-min-microvolt = <1125000>; ++ regulator-max-microvolt = <1850000>; ++ regulator-initial-mode = <2>; ++ regulator-allowed-modes = <2>, <4>; ++ regulator-ramp-delay = <3125>; ++ regulator-always-on; ++ ++ regulator-state-standby { ++ regulator-on-in-suspend; ++ regulator-mode = <4>; ++ }; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-mode = <4>; ++ }; ++ }; ++ ++ vldo1: LDO1 { ++ regulator-name = "LDO1"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <3700000>; ++ regulator-always-on; ++ ++ regulator-state-standby { ++ regulator-on-in-suspend; ++ }; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vldo2: LDO2 { ++ regulator-name = "LDO2"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <3700000>; ++ ++ regulator-state-standby { ++ regulator-on-in-suspend; ++ }; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&flx3 { ++ atmel,flexcom-mode = ; ++ status = "okay"; ++ ++ uart3: serial@200 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flx3_default>; ++ status = "okay"; ++ }; ++}; ++ ++&flx4 { ++ atmel,flexcom-mode = ; ++ status = "okay"; ++ ++ uart4: serial@200 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flx4_default>; ++ status = "okay"; ++ }; ++}; ++ ++&flx7 { ++ atmel,flexcom-mode = ; ++ status = "okay"; ++ ++ uart7: serial@200 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flx7_default>; ++ status = "okay"; ++ }; ++}; ++ ++&flx8 { ++ atmel,flexcom-mode = ; ++ status = "okay"; ++ ++ i2c8: i2c@600 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c8_default>; ++ i2c-analog-filter; ++ i2c-digital-filter; ++ i2c-digital-filter-width-ns = <35>; ++ status = "okay"; ++ }; ++}; ++ ++&flx9 { ++ atmel,flexcom-mode = ; ++ status = "okay"; ++ ++ i2c9: i2c@600 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c9_default>; ++ i2c-analog-filter; ++ i2c-digital-filter; ++ i2c-digital-filter-width-ns = <35>; ++ status = "okay"; ++ }; ++}; ++ ++&flx11 { ++ atmel,flexcom-mode = ; ++ status = "okay"; ++ ++ spi11: spi@400 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; ++ status = "okay"; ++ }; ++}; ++ ++&gmac0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>; ++ phy-mode = "rgmii-id"; ++ status = "okay"; ++ ++ ethernet-phy@7 { ++ reg = <0x7>; ++ interrupt-parent = <&pioA>; ++ interrupts = ; ++ }; ++}; ++ ++&gmac1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>; ++ phy-mode = "rmii"; ++ status = "okay"; ++ ++ ethernet-phy@0 { ++ reg = <0x0>; ++ interrupt-parent = <&pioA>; ++ interrupts = ; ++ }; ++}; ++ ++&i2s0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2s0_default>; ++}; ++ ++&pioA { ++ pinctrl_flx0_default: flx0_default { ++ pinmux = , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_flx3_default: flx3_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_flx4_default: flx4_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_flx7_default: flx7_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_gmac0_default: gmac0_default { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_gmac0_txck_default: gmac0_txck_default { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ ++ pinctrl_gmac0_phy_irq: gmac0_phy_irq { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_gmac1_default: gmac1_default { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_gmac1_phy_irq: gmac1_phy_irq { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_i2c1_default: i2c1_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_i2c8_default: i2c8_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_i2c9_default: i2c9_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_i2s0_default: i2s0_default { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_key_gpio_default: key_gpio_default { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ ++ pinctrl_led_gpio_default: led_gpio_default { ++ pinmux = , ++ , ++ ; ++ bias-pull-up; ++ }; ++ ++ pinctrl_mikrobus1_an_default: mikrobus1_an_default { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus2_an_default: mikrobus2_an_default { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus1_pwm2_default: mikrobus1_pwm2_default { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus2_pwm3_default: mikrobus2_pwm3_default { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus1_spi: mikrobus1_spi { ++ pinmux = , ++ , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_sdmmc0_default: sdmmc0_default { ++ cmd_data { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ bias-pull-up; ++ }; ++ ++ ck_cd_rstn_vddsel { ++ pinmux = , ++ , ++ ; ++ bias-pull-up; ++ }; ++ }; ++ ++ pinctrl_sdmmc1_default: sdmmc1_default { ++ cmd_data { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ bias-pull-up; ++ }; ++ ++ ck_cd_rstn_vddsel { ++ pinmux = , ++ , ++ , ++ ; ++ bias-pull-up; ++ }; ++ }; ++ ++ pinctrl_sdmmc2_default: sdmmc2_default { ++ cmd_data { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ bias-pull-up; ++ }; ++ ++ ck { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ }; ++ ++ pinctrl_spdifrx_default: spdifrx_default { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_spdiftx_default: spdiftx_default { ++ pinmux = ; ++ bias-disable; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_mikrobus1_pwm2_default &pinctrl_mikrobus2_pwm3_default>; ++ status = "disabled"; /* Conflict with leds. */ ++}; ++ ++&rtt { ++ atmel,rtt-rtc-time-reg = <&gpbr 0x0>; ++}; ++ ++&sdmmc0 { ++ bus-width = <8>; ++ non-removable; ++ no-1-8-v; ++ sdhci-caps-mask = <0x0 0x00200000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_sdmmc0_default>; ++ status = "okay"; ++}; ++ ++&sdmmc1 { ++ bus-width = <4>; ++ no-1-8-v; ++ sdhci-caps-mask = <0x0 0x00200000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_sdmmc1_default>; ++ status = "okay"; ++}; ++ ++&sdmmc2 { ++ bus-width = <4>; ++ no-1-8-v; ++ sdhci-caps-mask = <0x0 0x00200000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_sdmmc2_default>; ++}; ++ ++&spdifrx { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_spdifrx_default>; ++ status = "okay"; ++}; ++ ++&spdiftx { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_spdiftx_default>; ++ status = "okay"; ++}; ++ ++&trng { ++ status = "okay"; ++}; ++ ++&vddout25 { ++ vin-supply = <&vdd_3v3>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/sama7g5-pinfunc.h +@@ -0,0 +1,923 @@ ++/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ ++#define PINMUX_PIN(no, func, ioset) \ ++(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) ++ ++#define PIN_PA0 0 ++#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) ++#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) ++#define PIN_PA0__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA0, 2, 1) ++#define PIN_PA0__CANTX3 PINMUX_PIN(PIN_PA0, 3, 1) ++#define PIN_PA0__PWML0 PINMUX_PIN(PIN_PA0, 5, 2) ++#define PIN_PA1 1 ++#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) ++#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) ++#define PIN_PA1__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA1, 2, 1) ++#define PIN_PA1__CANRX3 PINMUX_PIN(PIN_PA1, 3, 1) ++#define PIN_PA1__D14 PINMUX_PIN(PIN_PA1, 4, 1) ++#define PIN_PA1__PWMH0 PINMUX_PIN(PIN_PA1, 5, 3) ++#define PIN_PA2 2 ++#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) ++#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1) ++#define PIN_PA2__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA2, 2, 1) ++#define PIN_PA2__PDMC1_CLK PINMUX_PIN(PIN_PA2, 3, 1) ++#define PIN_PA2__D15 PINMUX_PIN(PIN_PA2, 4, 1) ++#define PIN_PA2__PWMH1 PINMUX_PIN(PIN_PA2, 5, 3) ++#define PIN_PA2__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA2, 6, 3) ++#define PIN_PA3 3 ++#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) ++#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1) ++#define PIN_PA3__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA3, 2, 1) ++#define PIN_PA3__PDMC1_DS0 PINMUX_PIN(PIN_PA3, 3, 1) ++#define PIN_PA3__NWR1_NBS1 PINMUX_PIN(PIN_PA3, 4, 1) ++#define PIN_PA3__PWML3 PINMUX_PIN(PIN_PA3, 5, 3) ++#define PIN_PA3__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA3, 6, 3) ++#define PIN_PA4 4 ++#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) ++#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1) ++#define PIN_PA4__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA4, 2, 1) ++#define PIN_PA4__PDMC1_DS1 PINMUX_PIN(PIN_PA4, 3, 1) ++#define PIN_PA4__NCS2 PINMUX_PIN(PIN_PA4, 4, 1) ++#define PIN_PA4__PWMH3 PINMUX_PIN(PIN_PA4, 5, 3) ++#define PIN_PA4__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA4, 6, 3) ++#define PIN_PA5 5 ++#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) ++#define PIN_PA5__SDMMC0_DAT2 PINMUX_PIN(PIN_PA5, 1, 1) ++#define PIN_PA5__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA5, 2, 1) ++#define PIN_PA5__CANTX2 PINMUX_PIN(PIN_PA5, 3, 1) ++#define PIN_PA5__A23 PINMUX_PIN(PIN_PA5, 4, 1) ++#define PIN_PA5__PWMEXTRG0 PINMUX_PIN(PIN_PA5, 5, 3) ++#define PIN_PA5__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA5, 6, 3) ++#define PIN_PA6 6 ++#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) ++#define PIN_PA6__SDMMC0_DAT3 PINMUX_PIN(PIN_PA6, 1, 1) ++#define PIN_PA6__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA6, 2, 1) ++#define PIN_PA6__CANRX2 PINMUX_PIN(PIN_PA6, 3, 1) ++#define PIN_PA6__A24 PINMUX_PIN(PIN_PA6, 4, 1) ++#define PIN_PA6__PWMEXTRG1 PINMUX_PIN(PIN_PA6, 5, 3) ++#define PIN_PA6__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA6, 6, 3) ++#define PIN_PA7 7 ++#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) ++#define PIN_PA7__SDMMC0_DAT4 PINMUX_PIN(PIN_PA7, 1, 1) ++#define PIN_PA7__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA7, 2, 1) ++#define PIN_PA7__CANTX1 PINMUX_PIN(PIN_PA7, 3, 1) ++#define PIN_PA7__NWAIT PINMUX_PIN(PIN_PA7, 4, 1) ++#define PIN_PA7__PWMFI0 PINMUX_PIN(PIN_PA7, 5, 3) ++#define PIN_PA7__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA7, 6, 3) ++#define PIN_PA8 8 ++#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) ++#define PIN_PA8__SDMMC0_DAT5 PINMUX_PIN(PIN_PA8, 1, 1) ++#define PIN_PA8__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA8, 2, 1) ++#define PIN_PA8__CANRX1 PINMUX_PIN(PIN_PA8, 3, 1) ++#define PIN_PA8__NCS0 PINMUX_PIN(PIN_PA8, 4, 1) ++#define PIN_PA8__PWMIF1 PINMUX_PIN(PIN_PA8, 5, 3) ++#define PIN_PA8__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA8, 6, 3) ++#define PIN_PA9 9 ++#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) ++#define PIN_PA9__SDMMC0_DAT6 PINMUX_PIN(PIN_PA9, 1, 1) ++#define PIN_PA9__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA9, 2, 1) ++#define PIN_PA9__CANTX0 PINMUX_PIN(PIN_PA9, 3, 1) ++#define PIN_PA9__SMCK PINMUX_PIN(PIN_PA9, 4, 1) ++#define PIN_PA9__SPDIF_RX PINMUX_PIN(PIN_PA9, 5, 1) ++#define PIN_PA9__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA9, 6, 3) ++#define PIN_PA10 10 ++#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) ++#define PIN_PA10__SDMMC0_DAT7 PINMUX_PIN(PIN_PA10, 1, 1) ++#define PIN_PA10__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA10, 2, 1) ++#define PIN_PA10__CANRX0 PINMUX_PIN(PIN_PA10, 3, 1) ++#define PIN_PA10__NCS1 PINMUX_PIN(PIN_PA10, 4, 1) ++#define PIN_PA10__SPDIF_TX PINMUX_PIN(PIN_PA10, 5, 1) ++#define PIN_PA10__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA10, 6, 3) ++#define PIN_PA11 11 ++#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) ++#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1) ++#define PIN_PA11__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA11, 2, 1) ++#define PIN_PA11__A0_NBS0 PINMUX_PIN(PIN_PA11, 4, 1) ++#define PIN_PA11__TIOA0 PINMUX_PIN(PIN_PA11, 5, 1) ++#define PIN_PA11__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA11, 6, 3) ++#define PIN_PA12 12 ++#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) ++#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) ++#define PIN_PA12__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA12, 2, 1) ++#define PIN_PA12__FLEXCOM3_IO5 PINMUX_PIN(PIN_PA12, 4, 1) ++#define PIN_PA12__PWML2 PINMUX_PIN(PIN_PA12, 5, 3) ++#define PIN_PA12__FLEXCOM6_IO0 PINMUX_PIN(PIN_PA12, 6, 3) ++#define PIN_PA13 13 ++#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) ++#define PIN_PA13__SDMMC0_1V8SEL PINMUX_PIN(PIN_PA13, 1, 1) ++#define PIN_PA13__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA13, 2, 1) ++#define PIN_PA13__FLEXCOM3_IO6 PINMUX_PIN(PIN_PA13, 4, 1) ++#define PIN_PA13__PWMH2 PINMUX_PIN(PIN_PA13, 5, 3) ++#define PIN_PA13__FLEXCOM6_IO1 PINMUX_PIN(PIN_PA13, 6, 3) ++#define PIN_PA14 14 ++#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) ++#define PIN_PA14__SDMMC0_CD PINMUX_PIN(PIN_PA14, 1, 1) ++#define PIN_PA14__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA14, 2, 1) ++#define PIN_PA14__A25 PINMUX_PIN(PIN_PA14, 4, 1) ++#define PIN_PA14__PWML1 PINMUX_PIN(PIN_PA14, 5, 3) ++#define PIN_PA15 15 ++#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) ++#define PIN_PA15__G0_TXEN PINMUX_PIN(PIN_PA15, 1, 1) ++#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 2, 1) ++#define PIN_PA15__ISC_MCK PINMUX_PIN(PIN_PA15, 3, 1) ++#define PIN_PA15__A1 PINMUX_PIN(PIN_PA15, 4, 1) ++#define PIN_PA15__TIOB0 PINMUX_PIN(PIN_PA15, 5, 1) ++#define PIN_PA16 16 ++#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) ++#define PIN_PA16__G0_TX0 PINMUX_PIN(PIN_PA16, 1, 1) ++#define PIN_PA16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA16, 2, 1) ++#define PIN_PA16__ISC_D0 PINMUX_PIN(PIN_PA16, 3, 1) ++#define PIN_PA16__A2 PINMUX_PIN(PIN_PA16, 4, 1) ++#define PIN_PA16__TCLK0 PINMUX_PIN(PIN_PA16, 5, 1) ++#define PIN_PA17 17 ++#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) ++#define PIN_PA17__G0_TX1 PINMUX_PIN(PIN_PA17, 1, 1) ++#define PIN_PA17__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA17, 2, 1) ++#define PIN_PA17__ISC_D1 PINMUX_PIN(PIN_PA17, 3, 1) ++#define PIN_PA17__A3 PINMUX_PIN(PIN_PA17, 4, 1) ++#define PIN_PA17__TIOA1 PINMUX_PIN(PIN_PA17, 5, 1) ++#define PIN_PA18 18 ++#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) ++#define PIN_PA18__G0_RXDV PINMUX_PIN(PIN_PA18, 1, 1) ++#define PIN_PA18__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA18, 2, 1) ++#define PIN_PA18__ISC_D2 PINMUX_PIN(PIN_PA18, 3, 1) ++#define PIN_PA18__A4 PINMUX_PIN(PIN_PA18, 4, 1) ++#define PIN_PA18__TIOB1 PINMUX_PIN(PIN_PA18, 5, 1) ++#define PIN_PA19 19 ++#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) ++#define PIN_PA19__G0_RX0 PINMUX_PIN(PIN_PA19, 1, 1) ++#define PIN_PA19__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA19, 2, 1) ++#define PIN_PA19__ISC_D3 PINMUX_PIN(PIN_PA19, 3, 1) ++#define PIN_PA19__A5 PINMUX_PIN(PIN_PA19, 4, 1) ++#define PIN_PA19__TCLK1 PINMUX_PIN(PIN_PA19, 5, 1) ++#define PIN_PA20 20 ++#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) ++#define PIN_PA20__G0_RX1 PINMUX_PIN(PIN_PA20, 1, 1) ++#define PIN_PA20__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA20, 2, 1) ++#define PIN_PA20__ISC_D4 PINMUX_PIN(PIN_PA20, 3, 1) ++#define PIN_PA20__A6 PINMUX_PIN(PIN_PA20, 4, 1) ++#define PIN_PA20__TIOA2 PINMUX_PIN(PIN_PA20, 5, 1) ++#define PIN_PA21 21 ++#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) ++#define PIN_PA21__G0_RXER PINMUX_PIN(PIN_PA21, 1, 1) ++#define PIN_PA21__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA21, 2, 1) ++#define PIN_PA21__ISC_D5 PINMUX_PIN(PIN_PA21, 3, 1) ++#define PIN_PA21__A7 PINMUX_PIN(PIN_PA21, 4, 1) ++#define PIN_PA21__TIOB2 PINMUX_PIN(PIN_PA21, 5, 1) ++#define PIN_PA22 22 ++#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) ++#define PIN_PA22__G0_MDC PINMUX_PIN(PIN_PA22, 1, 1) ++#define PIN_PA22__FLEXCOM4_IO2 PINMUX_PIN(PIN_PA22, 2, 1) ++#define PIN_PA22__ISC_D6 PINMUX_PIN(PIN_PA22, 3, 1) ++#define PIN_PA22__A8 PINMUX_PIN(PIN_PA22, 4, 1) ++#define PIN_PA22__TCLK2 PINMUX_PIN(PIN_PA22, 5, 1) ++#define PIN_PA23 23 ++#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) ++#define PIN_PA23__G0_MDIO PINMUX_PIN(PIN_PA23, 1, 1) ++#define PIN_PA23__FLEXCOM4_IO3 PINMUX_PIN(PIN_PA23, 2, 1) ++#define PIN_PA23__ISC_D7 PINMUX_PIN(PIN_PA23, 3, 1) ++#define PIN_PA23__A9 PINMUX_PIN(PIN_PA23, 4, 1) ++#define PIN_PA24 24 ++#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) ++#define PIN_PA24__G0_TXCK PINMUX_PIN(PIN_PA24, 1, 1) ++#define PIN_PA24__FLEXCOM4_IO4 PINMUX_PIN(PIN_PA24, 2, 1) ++#define PIN_PA24__ISC_HSYNC PINMUX_PIN(PIN_PA24, 3, 1) ++#define PIN_PA24__A10 PINMUX_PIN(PIN_PA24, 4, 1) ++#define PIN_PA24__FLEXCOM0_IO5 PINMUX_PIN(PIN_PA24, 5, 1) ++#define PIN_PA25 25 ++#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) ++#define PIN_PA25__G0_125CK PINMUX_PIN(PIN_PA25, 1, 1) ++#define PIN_PA25__FLEXCOM5_IO4 PINMUX_PIN(PIN_PA25, 2, 1) ++#define PIN_PA25__ISC_VSYNC PINMUX_PIN(PIN_PA25, 3, 1) ++#define PIN_PA25__A11 PINMUX_PIN(PIN_PA25, 4, 1) ++#define PIN_PA25__FLEXCOM0_IO6 PINMUX_PIN(PIN_PA25, 5, 1) ++#define PIN_PA25__FLEXCOM7_IO0 PINMUX_PIN(PIN_PA25, 6, 3) ++#define PIN_PA26 26 ++#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) ++#define PIN_PA26__G0_TX2 PINMUX_PIN(PIN_PA26, 1, 1) ++#define PIN_PA26__FLEXCOM5_IO2 PINMUX_PIN(PIN_PA26, 2, 1) ++#define PIN_PA26__ISC_FIELD PINMUX_PIN(PIN_PA26, 3, 1) ++#define PIN_PA26__A12 PINMUX_PIN(PIN_PA26, 4, 1) ++#define PIN_PA26__TF0 PINMUX_PIN(PIN_PA26, 5, 1) ++#define PIN_PA26__FLEXCOM7_IO1 PINMUX_PIN(PIN_PA26, 6, 3) ++#define PIN_PA27 27 ++#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) ++#define PIN_PA27__G0_TX3 PINMUX_PIN(PIN_PA27, 1, 1) ++#define PIN_PA27__FLEXCOM5_IO3 PINMUX_PIN(PIN_PA27, 2, 1) ++#define PIN_PA27__ISC_PCK PINMUX_PIN(PIN_PA27, 3, 1) ++#define PIN_PA27__A13 PINMUX_PIN(PIN_PA27, 4, 1) ++#define PIN_PA27__TK0 PINMUX_PIN(PIN_PA27, 5, 1) ++#define PIN_PA27__FLEXCOM8_IO0 PINMUX_PIN(PIN_PA27, 6, 3) ++#define PIN_PA28 28 ++#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) ++#define PIN_PA28__G0_RX2 PINMUX_PIN(PIN_PA28, 1, 1) ++#define PIN_PA28__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA28, 2, 1) ++#define PIN_PA28__ISC_D8 PINMUX_PIN(PIN_PA28, 3, 1) ++#define PIN_PA28__A14 PINMUX_PIN(PIN_PA28, 4, 1) ++#define PIN_PA28__RD0 PINMUX_PIN(PIN_PA28, 5, 1) ++#define PIN_PA28__FLEXCOM8_IO1 PINMUX_PIN(PIN_PA28, 6, 3) ++#define PIN_PA29 29 ++#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) ++#define PIN_PA29__G0_RX3 PINMUX_PIN(PIN_PA29, 1, 1) ++#define PIN_PA29__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA29, 2, 1) ++#define PIN_PA29__ISC_D9 PINMUX_PIN(PIN_PA29, 3, 1) ++#define PIN_PA29__A15 PINMUX_PIN(PIN_PA29, 4, 1) ++#define PIN_PA29__RF0 PINMUX_PIN(PIN_PA29, 5, 1) ++#define PIN_PA29__FLEXCOM9_IO0 PINMUX_PIN(PIN_PA29, 6, 3) ++#define PIN_PA30 30 ++#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) ++#define PIN_PA30__G0_RXCK PINMUX_PIN(PIN_PA30, 1, 1) ++#define PIN_PA30__FLEXCOM6_IO4 PINMUX_PIN(PIN_PA30, 2, 1) ++#define PIN_PA30__ISC_D10 PINMUX_PIN(PIN_PA30, 3, 1) ++#define PIN_PA30__A16 PINMUX_PIN(PIN_PA30, 4, 1) ++#define PIN_PA30__RK0 PINMUX_PIN(PIN_PA30, 5, 1) ++#define PIN_PA30__FLEXCOM9_IO1 PINMUX_PIN(PIN_PA30, 6, 3) ++#define PIN_PA31 31 ++#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) ++#define PIN_PA31__G0_TXER PINMUX_PIN(PIN_PA31, 1, 1) ++#define PIN_PA31__FLEXCOM6_IO2 PINMUX_PIN(PIN_PA31, 2, 1) ++#define PIN_PA31__ISC_D11 PINMUX_PIN(PIN_PA31, 3, 1) ++#define PIN_PA31__A17 PINMUX_PIN(PIN_PA31, 4, 1) ++#define PIN_PA31__TD0 PINMUX_PIN(PIN_PA31, 5, 1) ++#define PIN_PA31__FLEXCOM10_IO0 PINMUX_PIN(PIN_PA31, 6, 3) ++#define PIN_PB0 32 ++#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) ++#define PIN_PB0__G0_COL PINMUX_PIN(PIN_PB0, 1, 1) ++#define PIN_PB0__FLEXCOM6_IO3 PINMUX_PIN(PIN_PB0, 2, 2) ++#define PIN_PB0__EXT_IRQ0 PINMUX_PIN(PIN_PB0, 3, 1) ++#define PIN_PB0__A18 PINMUX_PIN(PIN_PB0, 4, 1) ++#define PIN_PB0__SPDIF_RX PINMUX_PIN(PIN_PB0, 5, 2) ++#define PIN_PB0__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB0, 6, 3) ++#define PIN_PB1 33 ++#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) ++#define PIN_PB1__G0_CRS PINMUX_PIN(PIN_PB1, 1, 1) ++#define PIN_PB1__FLEXCOM6_IO1 PINMUX_PIN(PIN_PB1, 2, 2) ++#define PIN_PB1__EXT_IRQ1 PINMUX_PIN(PIN_PB1, 3, 1) ++#define PIN_PB1__A19 PINMUX_PIN(PIN_PB1, 4, 1) ++#define PIN_PB1__SPDIF_TX PINMUX_PIN(PIN_PB1, 5, 2) ++#define PIN_PB1__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB1, 6, 3) ++#define PIN_PB2 34 ++#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) ++#define PIN_PB2__G0_TSUCOMP PINMUX_PIN(PIN_PB2, 1, 1) ++#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1) ++#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1) ++#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1) ++#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3) ++#define PIN_PB3 35 ++#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) ++#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1) ++#define PIN_PB3__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB3, 2, 1) ++#define PIN_PB3__PCK2 PINMUX_PIN(PIN_PB3, 3, 2) ++#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 4, 1) ++#define PIN_PB4 36 ++#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) ++#define PIN_PB4__TF1 PINMUX_PIN(PIN_PB4, 1, 1) ++#define PIN_PB4__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB4, 2, 1) ++#define PIN_PB4__PCK3 PINMUX_PIN(PIN_PB4, 3, 2) ++#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 4, 1) ++#define PIN_PB5 37 ++#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) ++#define PIN_PB5__TK1 PINMUX_PIN(PIN_PB5, 1, 1) ++#define PIN_PB5__FLEXCOM11_IO2 PINMUX_PIN(PIN_PB5, 2, 1) ++#define PIN_PB5__PCK4 PINMUX_PIN(PIN_PB5, 3, 2) ++#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 4, 1) ++#define PIN_PB6 38 ++#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) ++#define PIN_PB6__RK1 PINMUX_PIN(PIN_PB6, 1, 1) ++#define PIN_PB6__FLEXCOM11_IO3 PINMUX_PIN(PIN_PB6, 2, 1) ++#define PIN_PB6__PCK5 PINMUX_PIN(PIN_PB6, 3, 2) ++#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 4, 1) ++#define PIN_PB7 39 ++#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) ++#define PIN_PB7__TD1 PINMUX_PIN(PIN_PB7, 1, 1) ++#define PIN_PB7__FLEXCOM11_IO4 PINMUX_PIN(PIN_PB7, 2, 1) ++#define PIN_PB7__FLEXCOM3_IO5 PINMUX_PIN(PIN_PB7, 3, 2) ++#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 4, 1) ++#define PIN_PB8 40 ++#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) ++#define PIN_PB8__RD1 PINMUX_PIN(PIN_PB8, 1, 1) ++#define PIN_PB8__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB8, 2, 1) ++#define PIN_PB8__FLEXCOM3_IO6 PINMUX_PIN(PIN_PB8, 3, 2) ++#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 4, 1) ++#define PIN_PB9 41 ++#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) ++#define PIN_PB9__QSPI0_IO3 PINMUX_PIN(PIN_PB9, 1, 1) ++#define PIN_PB9__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB9, 2, 1) ++#define PIN_PB9__PDMC0_CLK PINMUX_PIN(PIN_PB9, 3, 1) ++#define PIN_PB9__NCS3_NANDCS PINMUX_PIN(PIN_PB9, 4, 1) ++#define PIN_PB9__PWML0 PINMUX_PIN(PIN_PB9, 5, 2) ++#define PIN_PB10 42 ++#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) ++#define PIN_PB10__QSPI0_IO2 PINMUX_PIN(PIN_PB10, 1, 1) ++#define PIN_PB10__FLEXCOM8_IO2 PINMUX_PIN(PIN_PB10, 2, 1) ++#define PIN_PB10__PDMC0_DS0 PINMUX_PIN(PIN_PB10, 3, 1) ++#define PIN_PB10__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PB10, 4, 1) ++#define PIN_PB10__PWMH0 PINMUX_PIN(PIN_PB10, 5, 2) ++#define PIN_PB11 43 ++#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) ++#define PIN_PB11__QSPI0_IO1 PINMUX_PIN(PIN_PB11, 1, 1) ++#define PIN_PB11__FLEXCOM8_IO3 PINMUX_PIN(PIN_PB11, 2, 1) ++#define PIN_PB11__PDMC0_DS1 PINMUX_PIN(PIN_PB11, 3, 1) ++#define PIN_PB11__NRD_NANDOE PINMUX_PIN(PIN_PB11, 4, 1) ++#define PIN_PB11__PWML1 PINMUX_PIN(PIN_PB11, 5, 2) ++#define PIN_PB12 44 ++#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) ++#define PIN_PB12__QSPI0_IO0 PINMUX_PIN(PIN_PB12, 1, 1) ++#define PIN_PB12__FLEXCOM8_IO4 PINMUX_PIN(PIN_PB12, 2, 1) ++#define PIN_PB12__FLEXCOM6_IO5 PINMUX_PIN(PIN_PB12, 3, 1) ++#define PIN_PB12__A21_NANDALE PINMUX_PIN(PIN_PB12, 4, 1) ++#define PIN_PB12__PWMH1 PINMUX_PIN(PIN_PB12, 5, 2) ++#define PIN_PB13 45 ++#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) ++#define PIN_PB13__QSPI0_CS PINMUX_PIN(PIN_PB13, 1, 1) ++#define PIN_PB13__FLEXCOM9_IO0 PINMUX_PIN(PIN_PB13, 2, 1) ++#define PIN_PB13__FLEXCOM6_IO6 PINMUX_PIN(PIN_PB13, 3, 1) ++#define PIN_PB13__A22_NANDCLE PINMUX_PIN(PIN_PB13, 4, 1) ++#define PIN_PB13__PWML2 PINMUX_PIN(PIN_PB13, 5, 2) ++#define PIN_PB14 46 ++#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) ++#define PIN_PB14__QSPI0_SCK PINMUX_PIN(PIN_PB14, 1, 1) ++#define PIN_PB14__FLEXCOM9_IO1 PINMUX_PIN(PIN_PB14, 2, 1) ++#define PIN_PB14__D0 PINMUX_PIN(PIN_PB14, 4, 1) ++#define PIN_PB14__PWMH2 PINMUX_PIN(PIN_PB14, 5, 2) ++#define PIN_PB15 47 ++#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) ++#define PIN_PB15__QSPI0_SCKN PINMUX_PIN(PIN_PB15, 1, 1) ++#define PIN_PB15__FLEXCOM9_IO2 PINMUX_PIN(PIN_PB15, 2, 1) ++#define PIN_PB15__D1 PINMUX_PIN(PIN_PB15, 4, 1) ++#define PIN_PB15__PWML3 PINMUX_PIN(PIN_PB15, 5, 2) ++#define PIN_PB16 48 ++#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) ++#define PIN_PB16__QSPI0_IO4 PINMUX_PIN(PIN_PB16, 1, 1) ++#define PIN_PB16__FLEXCOM9_IO3 PINMUX_PIN(PIN_PB16, 2, 1) ++#define PIN_PB16__PCK0 PINMUX_PIN(PIN_PB16, 3, 1) ++#define PIN_PB16__D2 PINMUX_PIN(PIN_PB16, 4, 1) ++#define PIN_PB16__PWMH3 PINMUX_PIN(PIN_PB16, 5, 2) ++#define PIN_PB16__EXT_IRQ0 PINMUX_PIN(PIN_PB16, 6, 2) ++#define PIN_PB17 49 ++#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) ++#define PIN_PB17__QSPI0_IO5 PINMUX_PIN(PIN_PB17, 1, 1) ++#define PIN_PB17__FLEXCOM9_IO4 PINMUX_PIN(PIN_PB17, 2, 1) ++#define PIN_PB17__PCK1 PINMUX_PIN(PIN_PB17, 3, 1) ++#define PIN_PB17__D3 PINMUX_PIN(PIN_PB17, 4, 1) ++#define PIN_PB17__PWMEXTRG0 PINMUX_PIN(PIN_PB17, 5, 2) ++#define PIN_PB17__EXT_IRQ1 PINMUX_PIN(PIN_PB17, 6, 2) ++#define PIN_PB18 50 ++#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) ++#define PIN_PB18__QSPI0_IO6 PINMUX_PIN(PIN_PB18, 1, 1) ++#define PIN_PB18__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB18, 2, 1) ++#define PIN_PB18__PCK2 PINMUX_PIN(PIN_PB18, 3, 1) ++#define PIN_PB18__D4 PINMUX_PIN(PIN_PB18, 4, 1) ++#define PIN_PB18__PWMEXTRG1 PINMUX_PIN(PIN_PB18, 5, 2) ++#define PIN_PB19 51 ++#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) ++#define PIN_PB19__QSPI0_IO7 PINMUX_PIN(PIN_PB19, 1, 1) ++#define PIN_PB19__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB19, 2, 1) ++#define PIN_PB19__PCK3 PINMUX_PIN(PIN_PB19, 3, 1) ++#define PIN_PB19__D5 PINMUX_PIN(PIN_PB19, 4, 1) ++#define PIN_PB19__PWMFI0 PINMUX_PIN(PIN_PB19, 5, 2) ++#define PIN_PB20 52 ++#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) ++#define PIN_PB20__QSPI0_DQS PINMUX_PIN(PIN_PB20, 1, 1) ++#define PIN_PB20__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB20, 2, 1) ++#define PIN_PB20__D6 PINMUX_PIN(PIN_PB20, 4, 1) ++#define PIN_PB20__PWMFI1 PINMUX_PIN(PIN_PB20, 5, 2) ++#define PIN_PB21 53 ++#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) ++#define PIN_PB21__QSPI0_INT PINMUX_PIN(PIN_PB21, 1, 1) ++#define PIN_PB21__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB21, 2, 1) ++#define PIN_PB21__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB21, 3, 1) ++#define PIN_PB21__D7 PINMUX_PIN(PIN_PB21, 4, 1) ++#define PIN_PB22 54 ++#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) ++#define PIN_PB22__QSPI1_IO3 PINMUX_PIN(PIN_PB22, 1, 1) ++#define PIN_PB22__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB22, 2, 1) ++#define PIN_PB22__FLEXCOM9_IO6 PINMUX_PIN(PIN_PB22, 3, 1) ++#define PIN_PB22__NANDRDY PINMUX_PIN(PIN_PB22, 4, 1) ++#define PIN_PB23 55 ++#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) ++#define PIN_PB23__QSPI1_IO2 PINMUX_PIN(PIN_PB23, 1, 1) ++#define PIN_PB23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB23, 2, 1) ++#define PIN_PB23__I2SMCC0_CK PINMUX_PIN(PIN_PB23, 3, 1) ++#define PIN_PB23__PCK4 PINMUX_PIN(PIN_PB23, 6, 1) ++#define PIN_PB24 56 ++#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) ++#define PIN_PB24__QSPI1_IO1 PINMUX_PIN(PIN_PB24, 1, 1) ++#define PIN_PB24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB24, 2, 1) ++#define PIN_PB24__I2SMCC0_WS PINMUX_PIN(PIN_PB24, 3, 1) ++#define PIN_PB24__PCK5 PINMUX_PIN(PIN_PB24, 6, 1) ++#define PIN_PB25 57 ++#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) ++#define PIN_PB25__QSPI1_IO0 PINMUX_PIN(PIN_PB25, 1, 1) ++#define PIN_PB25__FLEXCOM7_IO2 PINMUX_PIN(PIN_PB25, 2, 1) ++#define PIN_PB25__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PB25, 3, 1) ++#define PIN_PB25__PCK6 PINMUX_PIN(PIN_PB25, 6, 1) ++#define PIN_PB26 58 ++#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) ++#define PIN_PB26__QSPI1_CS PINMUX_PIN(PIN_PB26, 1, 1) ++#define PIN_PB26__FLEXCOM7_IO3 PINMUX_PIN(PIN_PB26, 2, 1) ++#define PIN_PB26__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PB26, 3, 1) ++#define PIN_PB26__PWMEXTRG0 PINMUX_PIN(PIN_PB26, 5, 1) ++#define PIN_PB26__PCK7 PINMUX_PIN(PIN_PB26, 6, 1) ++#define PIN_PB27 59 ++#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) ++#define PIN_PB27__QSPI1_SCK PINMUX_PIN(PIN_PB27, 1, 1) ++#define PIN_PB27__FLEXCOM7_IO4 PINMUX_PIN(PIN_PB27, 2, 1) ++#define PIN_PB27__I2SMCC0_MCK PINMUX_PIN(PIN_PB27, 3, 1) ++#define PIN_PB27__PWMEXTRG1 PINMUX_PIN(PIN_PB27, 5, 1) ++#define PIN_PB28 60 ++#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) ++#define PIN_PB28__SDMMC1_RSTN PINMUX_PIN(PIN_PB28, 1, 1) ++#define PIN_PB28__ADTRG PINMUX_PIN(PIN_PB28, 2, 2) ++#define PIN_PB28__PWMFI0 PINMUX_PIN(PIN_PB28, 5, 1) ++#define PIN_PB28__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB28, 6, 4) ++#define PIN_PB29 61 ++#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) ++#define PIN_PB29__SDMMC1_CMD PINMUX_PIN(PIN_PB29, 1, 1) ++#define PIN_PB29__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB29, 2, 2) ++#define PIN_PB29__FLEXCOM0_IO5 PINMUX_PIN(PIN_PB29, 3, 2) ++#define PIN_PB29__TIOA3 PINMUX_PIN(PIN_PB29, 4, 2) ++#define PIN_PB29__PWMFI1 PINMUX_PIN(PIN_PB29, 5, 1) ++#define PIN_PB29__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB29, 6, 4) ++#define PIN_PB30 62 ++#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) ++#define PIN_PB30__SDMMC1_CK PINMUX_PIN(PIN_PB30, 1, 1) ++#define PIN_PB30__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB30, 2, 2) ++#define PIN_PB30__FLEXCOM0_IO6 PINMUX_PIN(PIN_PB30, 3, 2) ++#define PIN_PB30__TIOB3 PINMUX_PIN(PIN_PB30, 4, 1) ++#define PIN_PB30__PWMH0 PINMUX_PIN(PIN_PB30, 5, 1) ++#define PIN_PB30__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB30, 6, 4) ++#define PIN_PB31 63 ++#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) ++#define PIN_PB31__SDMMC1_DAT0 PINMUX_PIN(PIN_PB31, 1, 1) ++#define PIN_PB31__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB31, 2, 2) ++#define PIN_PB31__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB31, 3, 2) ++#define PIN_PB31__TCLK3 PINMUX_PIN(PIN_PB31, 4, 1) ++#define PIN_PB31__PWML0 PINMUX_PIN(PIN_PB31, 5, 1) ++#define PIN_PB31__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB31, 6, 4) ++#define PIN_PC0 64 ++#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) ++#define PIN_PC0__SDMMC1_DAT1 PINMUX_PIN(PIN_PC0, 1, 1) ++#define PIN_PC0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC0, 2, 2) ++#define PIN_PC0__TIOA4 PINMUX_PIN(PIN_PC0, 4, 1) ++#define PIN_PC0__PWML1 PINMUX_PIN(PIN_PC0, 5, 1) ++#define PIN_PC0__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC0, 6, 4) ++#define PIN_PC1 65 ++#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) ++#define PIN_PC1__SDMMC1_DAT2 PINMUX_PIN(PIN_PC1, 1, 1) ++#define PIN_PC1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC1, 2, 2) ++#define PIN_PC1__TIOB4 PINMUX_PIN(PIN_PC1, 4, 1) ++#define PIN_PC1__PWMH1 PINMUX_PIN(PIN_PC1, 5, 1) ++#define PIN_PC1__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC1, 6, 4) ++#define PIN_PC2 66 ++#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) ++#define PIN_PC2__SDMMC1_DAT3 PINMUX_PIN(PIN_PC2, 1, 1) ++#define PIN_PC2__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC2, 2, 2) ++#define PIN_PC2__TCLK4 PINMUX_PIN(PIN_PC2, 4, 1) ++#define PIN_PC2__PWML2 PINMUX_PIN(PIN_PC2, 5, 1) ++#define PIN_PC2__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC2, 6, 4) ++#define PIN_PC3 67 ++#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) ++#define PIN_PC3__SDMMC1_WP PINMUX_PIN(PIN_PC3, 1, 1) ++#define PIN_PC3__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC3, 2, 2) ++#define PIN_PC3__TIOA5 PINMUX_PIN(PIN_PC3, 4, 1) ++#define PIN_PC3__PWMH2 PINMUX_PIN(PIN_PC3, 5, 1) ++#define PIN_PC3__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC3, 6, 4) ++#define PIN_PC4 68 ++#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) ++#define PIN_PC4__SDMMC1_CD PINMUX_PIN(PIN_PC4, 1, 1) ++#define PIN_PC4__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC4, 2, 2) ++#define PIN_PC4__FLEXCOM9_IO6 PINMUX_PIN(PIN_PC4, 3, 2) ++#define PIN_PC4__TIOB5 PINMUX_PIN(PIN_PC4, 4, 1) ++#define PIN_PC4__PWML3 PINMUX_PIN(PIN_PC4, 5, 1) ++#define PIN_PC4__FLEXCOM11_IO0 PINMUX_PIN(PIN_PC4, 6, 4) ++#define PIN_PC5 69 ++#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) ++#define PIN_PC5__SDMMC1_1V8SEL PINMUX_PIN(PIN_PC5, 1, 1) ++#define PIN_PC5__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC5, 2, 2) ++#define PIN_PC5__FLEXCOM6_IO5 PINMUX_PIN(PIN_PC5, 3, 2) ++#define PIN_PC5__TCLK5 PINMUX_PIN(PIN_PC5, 4, 1) ++#define PIN_PC5__PWMH3 PINMUX_PIN(PIN_PC5, 5, 1) ++#define PIN_PC5__FLEXCOM11_IO1 PINMUX_PIN(PIN_PC5, 6, 4) ++#define PIN_PC6 70 ++#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) ++#define PIN_PC6__FLEXCOM4_IO4 PINMUX_PIN(PIN_PC6, 2, 2) ++#define PIN_PC6__FLEXCOM6_IO6 PINMUX_PIN(PIN_PC6, 3, 2) ++#define PIN_PC7 71 ++#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) ++#define PIN_PC7__I2SMCC0_DIN0 PINMUX_PIN(PIN_PC7, 1, 1) ++#define PIN_PC7__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC7, 2, 2) ++#define PIN_PC8 72 ++#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) ++#define PIN_PC8__I2SMCC0_DIN1 PINMUX_PIN(PIN_PC8, 1, 1) ++#define PIN_PC8__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC8, 2, 2) ++#define PIN_PC9 73 ++#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) ++#define PIN_PC9__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PC9, 1, 1) ++#define PIN_PC9__FLEXCOM7_IO2 PINMUX_PIN(PIN_PC9, 2, 2) ++#define PIN_PC9__FLEXCOM1_IO0 PINMUX_PIN(PIN_PC9, 6, 4) ++#define PIN_PC10 74 ++#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) ++#define PIN_PC10__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PC10, 1, 1) ++#define PIN_PC10__FLEXCOM7_IO3 PINMUX_PIN(PIN_PC10, 2, 2) ++#define PIN_PC10__FLEXCOM1_IO1 PINMUX_PIN(PIN_PC10, 6, 4) ++#define PIN_PC11 75 ++#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) ++#define PIN_PC11__I2SMCC1_CK PINMUX_PIN(PIN_PC11, 1, 1) ++#define PIN_PC11__FLEXCOM7_IO4 PINMUX_PIN(PIN_PC11, 2, 2) ++#define PIN_PC11__FLEXCOM2_IO0 PINMUX_PIN(PIN_PC11, 6, 4) ++#define PIN_PC12 76 ++#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) ++#define PIN_PC12__I2SMCC1_WS PINMUX_PIN(PIN_PC12, 1, 1) ++#define PIN_PC12__FLEXCOM8_IO2 PINMUX_PIN(PIN_PC12, 2, 2) ++#define PIN_PC12__FLEXCOM2_IO1 PINMUX_PIN(PIN_PC12, 6, 4) ++#define PIN_PC13 77 ++#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) ++#define PIN_PC13__I2SMCC1_MCK PINMUX_PIN(PIN_PC13, 1, 1) ++#define PIN_PC13__FLEXCOM8_IO1 PINMUX_PIN(PIN_PC13, 2, 2) ++#define PIN_PC13__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC13, 6, 4) ++#define PIN_PC14 78 ++#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) ++#define PIN_PC14__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PC14, 1, 1) ++#define PIN_PC14__FLEXCOM8_IO0 PINMUX_PIN(PIN_PC14, 2, 2) ++#define PIN_PC14__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC14, 6, 4) ++#define PIN_PC15 79 ++#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) ++#define PIN_PC15__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PC15, 1, 1) ++#define PIN_PC15__FLEXCOM8_IO3 PINMUX_PIN(PIN_PC15, 2, 2) ++#define PIN_PC15__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC15, 6, 4) ++#define PIN_PC16 80 ++#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) ++#define PIN_PC16__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PC16, 1, 1) ++#define PIN_PC16__FLEXCOM8_IO4 PINMUX_PIN(PIN_PC16, 2, 2) ++#define PIN_PC16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC16, 6, 4) ++#define PIN_PC17 81 ++#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) ++#define PIN_PC17__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PC17, 1, 1) ++#define PIN_PC17__EXT_IRQ0 PINMUX_PIN(PIN_PC17, 2, 3) ++#define PIN_PC17__FLEXCOM5_IO0 PINMUX_PIN(PIN_PC17, 6, 4) ++#define PIN_PC18 82 ++#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) ++#define PIN_PC18__I2SMCC1_DIN0 PINMUX_PIN(PIN_PC18, 1, 1) ++#define PIN_PC18__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC18, 2, 2) ++#define PIN_PC18__FLEXCOM5_IO1 PINMUX_PIN(PIN_PC18, 6, 4) ++#define PIN_PC19 83 ++#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) ++#define PIN_PC19__I2SMCC1_DIN1 PINMUX_PIN(PIN_PC19, 1, 1) ++#define PIN_PC19__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC19, 2, 2) ++#define PIN_PC19__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC19, 6, 4) ++#define PIN_PC20 84 ++#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) ++#define PIN_PC20__I2SMCC1_DIN2 PINMUX_PIN(PIN_PC20, 1, 1) ++#define PIN_PC20__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC20, 2, 2) ++#define PIN_PC20__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC20, 6, 4) ++#define PIN_PC21 85 ++#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) ++#define PIN_PC21__I2SMCC1_DIN3 PINMUX_PIN(PIN_PC21, 1, 1) ++#define PIN_PC21__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC21, 2, 2) ++#define PIN_PC21__D3 PINMUX_PIN(PIN_PC21, 4, 2) ++#define PIN_PC21__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC21, 6, 5) ++#define PIN_PC22 86 ++#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) ++#define PIN_PC22__I2SMCC0_DIN2 PINMUX_PIN(PIN_PC22, 1, 1) ++#define PIN_PC22__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC22, 2, 2) ++#define PIN_PC22__D4 PINMUX_PIN(PIN_PC22, 4, 2) ++#define PIN_PC22__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC22, 6, 5) ++#define PIN_PC23 87 ++#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) ++#define PIN_PC23__I2SMCC0_DIN3 PINMUX_PIN(PIN_PC23, 1, 1) ++#define PIN_PC23__FLEXCOM0_IO5 PINMUX_PIN(PIN_PC23, 2, 3) ++#define PIN_PC23__D5 PINMUX_PIN(PIN_PC23, 4, 2) ++#define PIN_PC23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC23, 6, 5) ++#define PIN_PC24 88 ++#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) ++#define PIN_PC24__FLEXCOM0_IO6 PINMUX_PIN(PIN_PC24, 2, 3) ++#define PIN_PC24__EXT_IRQ1 PINMUX_PIN(PIN_PC24, 3, 3) ++#define PIN_PC24__D6 PINMUX_PIN(PIN_PC24, 4, 2) ++#define PIN_PC24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC24, 6, 5) ++#define PIN_PC25 89 ++#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) ++#define PIN_PC25__NTRST PINMUX_PIN(PIN_PC25, 1, 1) ++#define PIN_PC26 90 ++#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) ++#define PIN_PC26__TCK_SWCLK PINMUX_PIN(PIN_PC26, 1, 1) ++#define PIN_PC27 91 ++#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) ++#define PIN_PC27__TMS_SWDIO PINMUX_PIN(PIN_PC27, 1, 1) ++#define PIN_PC28 92 ++#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) ++#define PIN_PC28__TDI PINMUX_PIN(PIN_PC28, 1, 1) ++#define PIN_PC29 93 ++#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) ++#define PIN_PC29__TDO PINMUX_PIN(PIN_PC29, 1, 1) ++#define PIN_PC30 94 ++#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) ++#define PIN_PC30__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC30, 2, 2) ++#define PIN_PC31 95 ++#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) ++#define PIN_PC31__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC31, 2, 2) ++#define PIN_PD0 96 ++#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) ++#define PIN_PD0__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD0, 2, 2) ++#define PIN_PD1 97 ++#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) ++#define PIN_PD1__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD1, 2, 2) ++#define PIN_PD2 98 ++#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) ++#define PIN_PD2__SDMMC2_RSTN PINMUX_PIN(PIN_PD2, 1, 1) ++#define PIN_PD2__PCK0 PINMUX_PIN(PIN_PD2, 2, 2) ++#define PIN_PD2__CANTX4 PINMUX_PIN(PIN_PD2, 3, 1) ++#define PIN_PD2__D7 PINMUX_PIN(PIN_PD2, 4, 2) ++#define PIN_PD2__TIOA0 PINMUX_PIN(PIN_PD2, 5, 2) ++#define PIN_PD2__FLEXCOM8_IO0 PINMUX_PIN(PIN_PD2, 6, 5) ++#define PIN_PD3 99 ++#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) ++#define PIN_PD3__SDMMC2_CMD PINMUX_PIN(PIN_PD3, 1, 1) ++#define PIN_PD3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD3, 2, 2) ++#define PIN_PD3__CANRX4 PINMUX_PIN(PIN_PD3, 3, 1) ++#define PIN_PD3__NANDRDY PINMUX_PIN(PIN_PD3, 4, 2) ++#define PIN_PD3__TIOB0 PINMUX_PIN(PIN_PD3, 5, 2) ++#define PIN_PD3__FLEXCOM8_IO1 PINMUX_PIN(PIN_PD3, 6, 5) ++#define PIN_PD4 100 ++#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) ++#define PIN_PD4__SDMMC2_CK PINMUX_PIN(PIN_PD4, 1, 1) ++#define PIN_PD4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD4, 2, 2) ++#define PIN_PD4__CANTX5 PINMUX_PIN(PIN_PD4, 3, 1) ++#define PIN_PD4__NCS3_NANDCS PINMUX_PIN(PIN_PD4, 4, 2) ++#define PIN_PD4__TCLK0 PINMUX_PIN(PIN_PD4, 5, 2) ++#define PIN_PD4__FLEXCOM9_IO0 PINMUX_PIN(PIN_PD4, 6, 5) ++#define PIN_PD5 101 ++#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) ++#define PIN_PD5__SDMMC2_DAT0 PINMUX_PIN(PIN_PD5, 1, 1) ++#define PIN_PD5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PD5, 2, 2) ++#define PIN_PD5__CANRX5 PINMUX_PIN(PIN_PD5, 3, 1) ++#define PIN_PD5__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PD5, 4, 2) ++#define PIN_PD5__TIOA1 PINMUX_PIN(PIN_PD5, 5, 2) ++#define PIN_PD5__FLEXCOM9_IO1 PINMUX_PIN(PIN_PD5, 6, 5) ++#define PIN_PD6 102 ++#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) ++#define PIN_PD6__SDMMC2_DAT1 PINMUX_PIN(PIN_PD6, 1, 1) ++#define PIN_PD6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PD6, 2, 2) ++#define PIN_PD6__SPDIF_RX PINMUX_PIN(PIN_PD6, 3, 3) ++#define PIN_PD6__NRD_NANDOE PINMUX_PIN(PIN_PD6, 4, 2) ++#define PIN_PD6__TIOB1 PINMUX_PIN(PIN_PD6, 5, 2) ++#define PIN_PD6__FLEXCOM10_IO0 PINMUX_PIN(PIN_PD6, 6, 5) ++#define PIN_PD7 103 ++#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) ++#define PIN_PD7__SDMMC2_DAT2 PINMUX_PIN(PIN_PD7, 1, 1) ++#define PIN_PD7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PD7, 2, 2) ++#define PIN_PD7__SPDIF_TX PINMUX_PIN(PIN_PD7, 2, 2) ++#define PIN_PD7__A21_NANDALE PINMUX_PIN(PIN_PD7, 4, 2) ++#define PIN_PD7__TCLK1 PINMUX_PIN(PIN_PD7, 5, 2) ++#define PIN_PD7__FLEXCOM10_IO1 PINMUX_PIN(PIN_PD7, 6, 5) ++#define PIN_PD8 104 ++#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) ++#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1) ++#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1) ++#define PIN_PD8__A11_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) ++#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2) ++#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5) ++#define PIN_PD9 105 ++#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) ++#define PIN_PD9__SDMMC2_WP PINMUX_PIN(PIN_PD9, 1, 1) ++#define PIN_PD9__I2SMCC0_DIN1 PINMUX_PIN(PIN_PD9, 3, 2) ++#define PIN_PD9__D0 PINMUX_PIN(PIN_PD9, 4, 2) ++#define PIN_PD9__TIOB2 PINMUX_PIN(PIN_PD9, 5, 2) ++#define PIN_PD9__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD9, 6, 5) ++#define PIN_PD10 106 ++#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) ++#define PIN_PD10__SDMMC2_CD PINMUX_PIN(PIN_PD10, 1, 1) ++#define PIN_PD10__PCK6 PINMUX_PIN(PIN_PD10, 2, 2) ++#define PIN_PD10__I2SMCC0_DIN2 PINMUX_PIN(PIN_PD10, 3, 2) ++#define PIN_PD10__D1 PINMUX_PIN(PIN_PD10, 4, 2) ++#define PIN_PD10__TCLK2 PINMUX_PIN(PIN_PD10, 5, 2) ++#define PIN_PD10__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD10, 6, 3) ++#define PIN_PD11 107 ++#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) ++#define PIN_PD11__SDMMC2_1V8SEL PINMUX_PIN(PIN_PD11, 1, 1) ++#define PIN_PD11__PCK7 PINMUX_PIN(PIN_PD11, 2, 2) ++#define PIN_PD11__I2SMCC0_DIN3 PINMUX_PIN(PIN_PD11, 3, 2) ++#define PIN_PD11__D2 PINMUX_PIN(PIN_PD11, 4, 2) ++#define PIN_PD11__TIOA3 PINMUX_PIN(PIN_PD11, 5, 2) ++#define PIN_PD11__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD11, 6, 3) ++#define PIN_PD12 108 ++#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) ++#define PIN_PD12__PCK1 PINMUX_PIN(PIN_PD12, 1, 2) ++#define PIN_PD12__FLEXCOM1_IO0 PINMUX_PIN(PIN_PD12, 2, 2) ++#define PIN_PD12__CANTX0 PINMUX_PIN(PIN_PD12, 4, 2) ++#define PIN_PD12__TIOB3 PINMUX_PIN(PIN_PD12, 5, 2) ++#define PIN_PD13 109 ++#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) ++#define PIN_PD13__I2SMCC0_CK PINMUX_PIN(PIN_PD13, 1, 2) ++#define PIN_PD13__FLEXCOM1_IO1 PINMUX_PIN(PIN_PD13, 2, 2) ++#define PIN_PD13__PWML0 PINMUX_PIN(PIN_PD13, 3, 4) ++#define PIN_PD13__CANRX0 PINMUX_PIN(PIN_PD13, 4, 2) ++#define PIN_PD13__TCLK3 PINMUX_PIN(PIN_PD13, 5, 2) ++#define PIN_PD14 110 ++#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) ++#define PIN_PD14__I2SMCC0_MCK PINMUX_PIN(PIN_PD14, 1, 2) ++#define PIN_PD14__FLEXCOM1_IO2 PINMUX_PIN(PIN_PD14, 2, 2) ++#define PIN_PD14__PWMH0 PINMUX_PIN(PIN_PD14, 3, 4) ++#define PIN_PD14__CANTX1 PINMUX_PIN(PIN_PD14, 4, 2) ++#define PIN_PD14__TIOA4 PINMUX_PIN(PIN_PD14, 5, 2) ++#define PIN_PD14__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD14, 6, 5) ++#define PIN_PD15 111 ++#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) ++#define PIN_PD15__I2SMCC0_WS PINMUX_PIN(PIN_PD15, 1, 2) ++#define PIN_PD15__FLEXCOM1_IO3 PINMUX_PIN(PIN_PD15, 2, 2) ++#define PIN_PD15__PWML1 PINMUX_PIN(PIN_PD15, 3, 4) ++#define PIN_PD15__CANRX1 PINMUX_PIN(PIN_PD15, 4, 2) ++#define PIN_PD15__TIOB4 PINMUX_PIN(PIN_PD15, 5, 2) ++#define PIN_PD15__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD15, 6, 5) ++#define PIN_PD16 112 ++#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) ++#define PIN_PD16__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PD16, 1, 2) ++#define PIN_PD16__FLEXCOM1_IO4 PINMUX_PIN(PIN_PD16, 2, 2) ++#define PIN_PD16__PWMH1 PINMUX_PIN(PIN_PD16, 3, 4) ++#define PIN_PD16__CANTX2 PINMUX_PIN(PIN_PD16, 4, 2) ++#define PIN_PD16__TCLK4 PINMUX_PIN(PIN_PD16, 5, 2) ++#define PIN_PD16__FLEXCOM3_IO0 PINMUX_PIN(PIN_PD16, 6, 5) ++#define PIN_PD17 113 ++#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) ++#define PIN_PD17__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PD17, 1, 2) ++#define PIN_PD17__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD17, 2, 2) ++#define PIN_PD17__PWML2 PINMUX_PIN(PIN_PD17, 3, 4) ++#define PIN_PD17__CANRX2 PINMUX_PIN(PIN_PD17, 4, 2) ++#define PIN_PD17__TIOA5 PINMUX_PIN(PIN_PD17, 5, 2) ++#define PIN_PD17__FLEXCOM3_IO1 PINMUX_PIN(PIN_PD17, 6, 5) ++#define PIN_PD18 114 ++#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) ++#define PIN_PD18__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PD18, 1, 2) ++#define PIN_PD18__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD18, 2, 2) ++#define PIN_PD18__PWMH2 PINMUX_PIN(PIN_PD18, 3, 4) ++#define PIN_PD18__CANTX3 PINMUX_PIN(PIN_PD18, 4, 2) ++#define PIN_PD18__TIOB5 PINMUX_PIN(PIN_PD18, 5, 2) ++#define PIN_PD18__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD18, 6, 5) ++#define PIN_PD19 115 ++#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) ++#define PIN_PD19__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PD19, 1, 2) ++#define PIN_PD19__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD19, 2, 2) ++#define PIN_PD19__PWML3 PINMUX_PIN(PIN_PD19, 3, 4) ++#define PIN_PD19__CANRX3 PINMUX_PIN(PIN_PD19, 4, 2) ++#define PIN_PD19__TCLK5 PINMUX_PIN(PIN_PD19, 5, 2) ++#define PIN_PD19__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD19, 6, 5) ++#define PIN_PD20 116 ++#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) ++#define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) ++#define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) ++#define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) ++#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 5, 2) ++#define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) ++#define PIN_PD21 117 ++#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) ++#define PIN_PD21__PCK1 PINMUX_PIN(PIN_PD21, 1, 3) ++#define PIN_PD21__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD21, 2, 2) ++#define PIN_PD21__CANRX4 PINMUX_PIN(PIN_PD21, 4, 2) ++#define PIN_PD21__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD21, 6, 5) ++#define PIN_PD21__G1_TXEN PINMUX_PIN(PIN_PD21, 7, 1) ++#define PIN_PD22 118 ++#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) ++#define PIN_PD22__PDMC0_CLK PINMUX_PIN(PIN_PD22, 1, 2) ++#define PIN_PD22__PWMEXTRG0 PINMUX_PIN(PIN_PD22, 3, 4) ++#define PIN_PD22__RD1 PINMUX_PIN(PIN_PD22, 4, 2) ++#define PIN_PD22__CANTX5 PINMUX_PIN(PIN_PD22, 6, 2) ++#define PIN_PD22__G1_TX0 PINMUX_PIN(PIN_PD22, 7, 1) ++#define PIN_PD23 119 ++#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) ++#define PIN_PD23__PDMC0_DS0 PINMUX_PIN(PIN_PD23, 1, 2) ++#define PIN_PD23__PWMEXTRG1 PINMUX_PIN(PIN_PD23, 3, 4) ++#define PIN_PD23__RF1 PINMUX_PIN(PIN_PD23, 4, 2) ++#define PIN_PD23__ISC_MCK PINMUX_PIN(PIN_PD23, 5, 2) ++#define PIN_PD23__CANRX5 PINMUX_PIN(PIN_PD23, 6, 2) ++#define PIN_PD23__G1_TX1 PINMUX_PIN(PIN_PD23, 7, 1) ++#define PIN_PD24 120 ++#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) ++#define PIN_PD24__PDMC0_DS1 PINMUX_PIN(PIN_PD24, 1, 2) ++#define PIN_PD24__PWMFI0 PINMUX_PIN(PIN_PD24, 3, 4) ++#define PIN_PD24__RK1 PINMUX_PIN(PIN_PD24, 4, 2) ++#define PIN_PD24__ISC_D0 PINMUX_PIN(PIN_PD24, 5, 2) ++#define PIN_PD24__G1_RXDV PINMUX_PIN(PIN_PD24, 7, 1) ++#define PIN_PD25 121 ++#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) ++#define PIN_PD25__PDMC1_CLK PINMUX_PIN(PIN_PD25, 1, 2) ++#define PIN_PD25__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD25, 2, 2) ++#define PIN_PD25__PWMFI1 PINMUX_PIN(PIN_PD25, 3, 4) ++#define PIN_PD25__TD1 PINMUX_PIN(PIN_PD25, 4, 2) ++#define PIN_PD25__ISC_D1 PINMUX_PIN(PIN_PD25, 5, 2) ++#define PIN_PD25__G1_RX0 PINMUX_PIN(PIN_PD25, 7, 1) ++#define PIN_PD26 122 ++#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) ++#define PIN_PD26__PDMC1_DS0 PINMUX_PIN(PIN_PD26, 1, 2) ++#define PIN_PD26__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD26, 2, 2) ++#define PIN_PD26__ADTRG PINMUX_PIN(PIN_PD26, 3, 3) ++#define PIN_PD26__TF1 PINMUX_PIN(PIN_PD26, 4, 2) ++#define PIN_PD26__ISC_D2 PINMUX_PIN(PIN_PD26, 5, 2) ++#define PIN_PD26__G1_RX1 PINMUX_PIN(PIN_PD26, 7, 1) ++#define PIN_PD27 123 ++#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) ++#define PIN_PD27__PDMC1_DS1 PINMUX_PIN(PIN_PD27, 1, 2) ++#define PIN_PD27__FLEXCOM5_IO2 PINMUX_PIN(PIN_PD27, 2, 2) ++#define PIN_PD27__TIOA0 PINMUX_PIN(PIN_PD27, 3, 3) ++#define PIN_PD27__TK1 PINMUX_PIN(PIN_PD27, 4, 2) ++#define PIN_PD27__ISC_D3 PINMUX_PIN(PIN_PD27, 5, 2) ++#define PIN_PD27__G1_RXER PINMUX_PIN(PIN_PD27, 7, 1) ++#define PIN_PD28 124 ++#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) ++#define PIN_PD28__RD0 PINMUX_PIN(PIN_PD28, 1, 2) ++#define PIN_PD28__FLEXCOM5_IO3 PINMUX_PIN(PIN_PD28, 2, 2) ++#define PIN_PD28__TIOB0 PINMUX_PIN(PIN_PD28, 3, 3) ++#define PIN_PD28__I2SMCC1_CK PINMUX_PIN(PIN_PD28, 4, 2) ++#define PIN_PD28__ISC_D4 PINMUX_PIN(PIN_PD28, 5, 2) ++#define PIN_PD28__PWML3 PINMUX_PIN(PIN_PD28, 6, 5) ++#define PIN_PD28__G1_MDC PINMUX_PIN(PIN_PD28, 7, 1) ++#define PIN_PD29 125 ++#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) ++#define PIN_PD29__RF0 PINMUX_PIN(PIN_PD29, 1, 2) ++#define PIN_PD29__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD29, 2, 2) ++#define PIN_PD29__TCLK0 PINMUX_PIN(PIN_PD29, 3, 3) ++#define PIN_PD29__I2SMCC1_WS PINMUX_PIN(PIN_PD29, 4, 2) ++#define PIN_PD29__ISC_D5 PINMUX_PIN(PIN_PD29, 5, 2) ++#define PIN_PD29__PWMH3 PINMUX_PIN(PIN_PD29, 6, 5) ++#define PIN_PD29__G1_MDIO PINMUX_PIN(PIN_PD29, 7, 1) ++#define PIN_PD30 126 ++#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) ++#define PIN_PD30__RK0 PINMUX_PIN(PIN_PD30, 1, 2) ++#define PIN_PD30__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD30, 2, 2) ++#define PIN_PD30__TIOA1 PINMUX_PIN(PIN_PD30, 3, 3) ++#define PIN_PD30__I2SMCC1_MCK PINMUX_PIN(PIN_PD30, 4, 2) ++#define PIN_PD30__ISC_D6 PINMUX_PIN(PIN_PD30, 5, 2) ++#define PIN_PD30__PWMEXTRG0 PINMUX_PIN(PIN_PD30, 6, 5) ++#define PIN_PD30__G1_TXCK PINMUX_PIN(PIN_PD30, 7, 1) ++#define PIN_PD31 127 ++#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) ++#define PIN_PD31__TD0 PINMUX_PIN(PIN_PD31, 1, 2) ++#define PIN_PD31__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD31, 2, 2) ++#define PIN_PD31__TIOB1 PINMUX_PIN(PIN_PD31, 3, 3) ++#define PIN_PD31__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PD31, 4, 2) ++#define PIN_PD31__ISC_D7 PINMUX_PIN(PIN_PD31, 5, 2) ++#define PIN_PD31__PWM_EXTRG1 PINMUX_PIN(PIN_PD31, 6, 5) ++#define PIN_PD31__G1_TX2 PINMUX_PIN(PIN_PD31, 7, 1) ++#define PIN_PE0 128 ++#define PIN_PE0__GPIO PINMUX_PIN(PIN_PE0, 0, 0) ++#define PIN_PE0__TF0 PINMUX_PIN(PIN_PE0, 1, 2) ++#define PIN_PE0__FLEXCOM6_IO2 PINMUX_PIN(PIN_PE0, 2, 2) ++#define PIN_PE0__TCLK1 PINMUX_PIN(PIN_PE0, 3, 3) ++#define PIN_PE0__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PE0, 4, 2) ++#define PIN_PE0__ISC_HSYNC PINMUX_PIN(PIN_PE0, 5, 2) ++#define PIN_PE0__PWMFI0 PINMUX_PIN(PIN_PE0, 6, 5) ++#define PIN_PE0__G1_TX3 PINMUX_PIN(PIN_PE0, 7, 1) ++#define PIN_PE1 129 ++#define PIN_PE1__GPIO PINMUX_PIN(PIN_PE1, 0, 0) ++#define PIN_PE1__TK0 PINMUX_PIN(PIN_PE1, 1, 2) ++#define PIN_PE1__FLEXCOM6_IO3 PINMUX_PIN(PIN_PE1, 2, 2) ++#define PIN_PE1__TIOA2 PINMUX_PIN(PIN_PE1, 3, 3) ++#define PIN_PE1__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PE1, 4, 2) ++#define PIN_PE1__ISC_VSYNC PINMUX_PIN(PIN_PE1, 5, 2) ++#define PIN_PE1__PWMFI1 PINMUX_PIN(PIN_PE1, 6, 5) ++#define PIN_PE1__G1_RX2 PINMUX_PIN(PIN_PE1, 7, 1) ++#define PIN_PE2 130 ++#define PIN_PE2__GPIO PINMUX_PIN(PIN_PE2, 0, 0) ++#define PIN_PE2__PWML0 PINMUX_PIN(PIN_PE2, 1, 5) ++#define PIN_PE2__FLEXCOM6_IO4 PINMUX_PIN(PIN_PE2, 2, 2) ++#define PIN_PE2__TIOB2 PINMUX_PIN(PIN_PE2, 3, 3) ++#define PIN_PE2__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PE2, 4, 2) ++#define PIN_PE2__ISC_FIELD PINMUX_PIN(PIN_PE2, 5, 2) ++#define PIN_PE2__G1_RX3 PINMUX_PIN(PIN_PE2, 7, 1) ++#define PIN_PE3 131 ++#define PIN_PE3__GPIO PINMUX_PIN(PIN_PE3, 0, 0) ++#define PIN_PE3__PWMH0 PINMUX_PIN(PIN_PE3, 1, 5) ++#define PIN_PE3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PE3, 2, 4) ++#define PIN_PE3__TCLK2 PINMUX_PIN(PIN_PE3, 3, 3) ++#define PIN_PE3__I2SMCC1_DIN0 PINMUX_PIN(PIN_PE3, 4, 2) ++#define PIN_PE3__ISC_PCK PINMUX_PIN(PIN_PE3, 5, 2) ++#define PIN_PE3__G1_RXCK PINMUX_PIN(PIN_PE3, 7, 1) ++#define PIN_PE4 132 ++#define PIN_PE4__GPIO PINMUX_PIN(PIN_PE4, 0, 0) ++#define PIN_PE4__PWML1 PINMUX_PIN(PIN_PE4, 1, 5) ++#define PIN_PE4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PE4, 2, 4) ++#define PIN_PE4__TIOA3 PINMUX_PIN(PIN_PE4, 3, 3) ++#define PIN_PE4__I2SMCC1_DIN1 PINMUX_PIN(PIN_PE4, 4, 2) ++#define PIN_PE4__ISC_D8 PINMUX_PIN(PIN_PE4, 5, 2) ++#define PIN_PE4__G1_TXER PINMUX_PIN(PIN_PE4, 7, 1) ++#define PIN_PE5 133 ++#define PIN_PE5__GPIO PINMUX_PIN(PIN_PE5, 0, 0) ++#define PIN_PE5__PWMH1 PINMUX_PIN(PIN_PE5, 1, 5) ++#define PIN_PE5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PE5, 2, 4) ++#define PIN_PE5__TIOB3 PINMUX_PIN(PIN_PE5, 3, 3) ++#define PIN_PE5__I2SMCC1_DIN2 PINMUX_PIN(PIN_PE5, 4, 2) ++#define PIN_PE5__ISC_D9 PINMUX_PIN(PIN_PE5, 5, 2) ++#define PIN_PE5__G1_COL PINMUX_PIN(PIN_PE5, 7, 1) ++#define PIN_PE6 134 ++#define PIN_PE6__GPIO PINMUX_PIN(PIN_PE6, 0, 0) ++#define PIN_PE6__PWML2 PINMUX_PIN(PIN_PE6, 1, 5) ++#define PIN_PE6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PE6, 2, 4) ++#define PIN_PE6__TCLK3 PINMUX_PIN(PIN_PE6, 3, 3) ++#define PIN_PE6__I2SMCC1_DIN3 PINMUX_PIN(PIN_PE6, 4, 2) ++#define PIN_PE6__ISC_D10 PINMUX_PIN(PIN_PE6, 5, 2) ++#define PIN_PE6__G1_CRS PINMUX_PIN(PIN_PE6, 7, 1) ++#define PIN_PE7 135 ++#define PIN_PE7__GPIO PINMUX_PIN(PIN_PE7, 0, 0) ++#define PIN_PE7__PWMH2 PINMUX_PIN(PIN_PE7, 1, 5) ++#define PIN_PE7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PE7, 2, 4) ++#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3) ++#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2) ++#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1) +--- /dev/null ++++ b/arch/arm/boot/dts/sama7g5.dtsi +@@ -0,0 +1,528 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC ++ * ++ * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries ++ * ++ * Author: Eugen Hristev ++ * Author: Claudiu Beznea ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++/ { ++ model = "Microchip SAMA7G5 family SoC"; ++ compatible = "microchip,sama7g5"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent = <&gic>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x0>; ++ }; ++ }; ++ ++ clocks { ++ slow_xtal: slow_xtal { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ }; ++ ++ main_xtal: main_xtal { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ }; ++ ++ usb_clk: usb_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <48000000>; ++ }; ++ }; ++ ++ vddout25: fixed-regulator-vddout25 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "VDDOUT25"; ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ regulator-boot-on; ++ status = "disabled"; ++ }; ++ ++ ns_sram: sram@100000 { ++ compatible = "mmio-sram"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0x100000 0x20000>; ++ ranges; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ secumod: secumod@e0004000 { ++ compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; ++ reg = <0xe0004000 0x4000>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ sfrbu: sfr@e0008000 { ++ compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; ++ reg = <0xe0008000 0x20>; ++ }; ++ ++ pioA: pinctrl@e0014000 { ++ compatible = "microchip,sama7g5-pinctrl"; ++ reg = <0xe0014000 0x800>; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; ++ }; ++ ++ pmc: pmc@e0018000 { ++ compatible = "microchip,sama7g5-pmc", "syscon"; ++ reg = <0xe0018000 0x200>; ++ interrupts = ; ++ #clock-cells = <2>; ++ clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; ++ clock-names = "td_slck", "md_slck", "main_xtal"; ++ }; ++ ++ rtt: rtt@e001d020 { ++ compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; ++ reg = <0xe001d020 0x30>; ++ interrupts = ; ++ clocks = <&clk32k 0>; ++ }; ++ ++ clk32k: clock-controller@e001d050 { ++ compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; ++ reg = <0xe001d050 0x4>; ++ clocks = <&slow_xtal>; ++ #clock-cells = <1>; ++ }; ++ ++ gpbr: gpbr@e001d060 { ++ compatible = "microchip,sama7g5-gpbr", "syscon"; ++ reg = <0xe001d060 0x48>; ++ }; ++ ++ ps_wdt: watchdog@e001d180 { ++ compatible = "microchip,sama7g5-wdt"; ++ reg = <0xe001d180 0x24>; ++ interrupts = ; ++ clocks = <&clk32k 0>; ++ }; ++ ++ sdmmc0: mmc@e1204000 { ++ compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; ++ reg = <0xe1204000 0x4000>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; ++ clock-names = "hclock", "multclk"; ++ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; ++ assigned-clocks = <&pmc PMC_TYPE_GCK 80>; ++ assigned-clock-rates = <200000000>; ++ microchip,sdcal-inverted; ++ status = "disabled"; ++ }; ++ ++ sdmmc1: mmc@e1208000 { ++ compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; ++ reg = <0xe1208000 0x4000>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; ++ clock-names = "hclock", "multclk"; ++ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; ++ assigned-clocks = <&pmc PMC_TYPE_GCK 81>; ++ assigned-clock-rates = <200000000>; ++ microchip,sdcal-inverted; ++ status = "disabled"; ++ }; ++ ++ sdmmc2: mmc@e120c000 { ++ compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; ++ reg = <0xe120c000 0x4000>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; ++ clock-names = "hclock", "multclk"; ++ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; ++ assigned-clocks = <&pmc PMC_TYPE_GCK 82>; ++ assigned-clock-rates = <200000000>; ++ microchip,sdcal-inverted; ++ status = "disabled"; ++ }; ++ ++ pwm: pwm@e1604000 { ++ compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; ++ reg = <0xe1604000 0x4000>; ++ interrupts = ; ++ #pwm-cells = <3>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; ++ status = "disabled"; ++ }; ++ ++ spdifrx: spdifrx@e1614000 { ++ #sound-dai-cells = <0>; ++ compatible = "microchip,sama7g5-spdifrx"; ++ reg = <0xe1614000 0x4000>; ++ interrupts = ; ++ dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; ++ dma-names = "rx"; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; ++ clock-names = "pclk", "gclk"; ++ status = "disabled"; ++ }; ++ ++ spdiftx: spdiftx@e1618000 { ++ #sound-dai-cells = <0>; ++ compatible = "microchip,sama7g5-spdiftx"; ++ reg = <0xe1618000 0x4000>; ++ interrupts = ; ++ dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; ++ dma-names = "tx"; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; ++ clock-names = "pclk", "gclk"; ++ }; ++ ++ i2s0: i2s@e161c000 { ++ compatible = "microchip,sama7g5-i2smcc"; ++ #sound-dai-cells = <0>; ++ reg = <0xe161c000 0x4000>; ++ interrupts = ; ++ dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; ++ dma-names = "tx", "rx"; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; ++ clock-names = "pclk", "gclk"; ++ status = "disabled"; ++ }; ++ ++ i2s1: i2s@e1620000 { ++ compatible = "microchip,sama7g5-i2smcc"; ++ #sound-dai-cells = <0>; ++ reg = <0xe1620000 0x4000>; ++ interrupts = ; ++ dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; ++ dma-names = "tx", "rx"; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; ++ clock-names = "pclk", "gclk"; ++ status = "disabled"; ++ }; ++ ++ pit64b0: timer@e1800000 { ++ compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; ++ reg = <0xe1800000 0x4000>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; ++ clock-names = "pclk", "gclk"; ++ }; ++ ++ pit64b1: timer@e1804000 { ++ compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; ++ reg = <0xe1804000 0x4000>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; ++ clock-names = "pclk", "gclk"; ++ }; ++ ++ flx0: flexcom@e1818000 { ++ compatible = "atmel,sama5d2-flexcom"; ++ reg = <0xe1818000 0x200>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0xe1818000 0x800>; ++ status = "disabled"; ++ ++ uart0: serial@200 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0x200 0x200>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; ++ clock-names = "usart"; ++ dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, ++ <&dma1 AT91_XDMAC_DT_PERID(5)>; ++ dma-names = "tx", "rx"; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ }; ++ ++ flx1: flexcom@e181c000 { ++ compatible = "atmel,sama5d2-flexcom"; ++ reg = <0xe181c000 0x200>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0xe181c000 0x800>; ++ status = "disabled"; ++ ++ i2c1: i2c@600 { ++ compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; ++ reg = <0x600 0x200>; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; ++ atmel,fifo-size = <32>; ++ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, ++ <&dma0 AT91_XDMAC_DT_PERID(8)>; ++ dma-names = "rx", "tx"; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ }; ++ ++ flx3: flexcom@e1824000 { ++ compatible = "atmel,sama5d2-flexcom"; ++ reg = <0xe1824000 0x200>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0xe1824000 0x800>; ++ status = "disabled"; ++ ++ uart3: serial@200 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0x200 0x200>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; ++ clock-names = "usart"; ++ dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, ++ <&dma1 AT91_XDMAC_DT_PERID(11)>; ++ dma-names = "tx", "rx"; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ }; ++ ++ trng: rng@e2010000 { ++ compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; ++ reg = <0xe2010000 0x100>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; ++ status = "disabled"; ++ }; ++ ++ flx4: flexcom@e2018000 { ++ compatible = "atmel,sama5d2-flexcom"; ++ reg = <0xe2018000 0x200>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0xe2018000 0x800>; ++ status = "disabled"; ++ ++ uart4: serial@200 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0x200 0x200>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; ++ clock-names = "usart"; ++ dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, ++ <&dma1 AT91_XDMAC_DT_PERID(13)>; ++ dma-names = "tx", "rx"; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ atmel,fifo-size = <16>; ++ status = "disabled"; ++ }; ++ }; ++ ++ flx7: flexcom@e2024000 { ++ compatible = "atmel,sama5d2-flexcom"; ++ reg = <0xe2024000 0x200>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0xe2024000 0x800>; ++ status = "disabled"; ++ ++ uart7: serial@200 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0x200 0x200>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; ++ clock-names = "usart"; ++ dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, ++ <&dma1 AT91_XDMAC_DT_PERID(19)>; ++ dma-names = "tx", "rx"; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ atmel,fifo-size = <16>; ++ status = "disabled"; ++ }; ++ }; ++ ++ gmac0: ethernet@e2800000 { ++ compatible = "microchip,sama7g5-gem"; ++ reg = <0xe2800000 0x1000>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; ++ clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; ++ assigned-clocks = <&pmc PMC_TYPE_GCK 51>; ++ assigned-clock-rates = <125000000>; ++ status = "disabled"; ++ }; ++ ++ gmac1: ethernet@e2804000 { ++ compatible = "microchip,sama7g5-emac"; ++ reg = <0xe2804000 0x1000>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; ++ clock-names = "pclk", "hclk"; ++ status = "disabled"; ++ }; ++ ++ dma0: dma-controller@e2808000 { ++ compatible = "microchip,sama7g5-dma"; ++ reg = <0xe2808000 0x1000>; ++ interrupts = ; ++ #dma-cells = <1>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; ++ clock-names = "dma_clk"; ++ status = "disabled"; ++ }; ++ ++ dma1: dma-controller@e280c000 { ++ compatible = "microchip,sama7g5-dma"; ++ reg = <0xe280c000 0x1000>; ++ interrupts = ; ++ #dma-cells = <1>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; ++ clock-names = "dma_clk"; ++ status = "disabled"; ++ }; ++ ++ /* Place dma2 here despite it's address */ ++ dma2: dma-controller@e1200000 { ++ compatible = "microchip,sama7g5-dma"; ++ reg = <0xe1200000 0x1000>; ++ interrupts = ; ++ #dma-cells = <1>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; ++ clock-names = "dma_clk"; ++ dma-requests = <0>; ++ status = "disabled"; ++ }; ++ ++ flx8: flexcom@e2818000 { ++ compatible = "atmel,sama5d2-flexcom"; ++ reg = <0xe2818000 0x200>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0xe2818000 0x800>; ++ status = "disabled"; ++ ++ i2c8: i2c@600 { ++ compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; ++ reg = <0x600 0x200>; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; ++ atmel,fifo-size = <32>; ++ dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>, ++ <&dma0 AT91_XDMAC_DT_PERID(22)>; ++ dma-names = "rx", "tx"; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ }; ++ ++ flx9: flexcom@e281c000 { ++ compatible = "atmel,sama5d2-flexcom"; ++ reg = <0xe281c000 0x200>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0xe281c000 0x800>; ++ status = "disabled"; ++ ++ i2c9: i2c@600 { ++ compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; ++ reg = <0x600 0x200>; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; ++ atmel,fifo-size = <32>; ++ dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>, ++ <&dma0 AT91_XDMAC_DT_PERID(24)>; ++ dma-names = "rx", "tx"; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ }; ++ ++ flx11: flexcom@e2824000 { ++ compatible = "atmel,sama5d2-flexcom"; ++ reg = <0xe2824000 0x200>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0xe2824000 0x800>; ++ status = "disabled"; ++ ++ spi11: spi@400 { ++ compatible = "atmel,at91rm9200-spi"; ++ reg = <0x400 0x200>; ++ interrupts = ; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; ++ clock-names = "spi_clk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ atmel,fifo-size = <32>; ++ dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, ++ <&dma0 AT91_XDMAC_DT_PERID(28)>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ }; ++ ++ gic: interrupt-controller@e8c11000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <0>; ++ interrupt-controller; ++ interrupt-parent; ++ reg = <0xe8c11000 0x1000>, ++ <0xe8c12000 0x2000>; ++ }; ++ }; ++}; diff --git a/target/linux/at91/patches-5.15/223-ARM-at91-pm-do-not-panic-if-ram-controllers-are-not-.patch b/target/linux/at91/patches-5.15/223-ARM-at91-pm-do-not-panic-if-ram-controllers-are-not-.patch new file mode 100644 index 0000000000..68bf447a03 --- /dev/null +++ b/target/linux/at91/patches-5.15/223-ARM-at91-pm-do-not-panic-if-ram-controllers-are-not-.patch @@ -0,0 +1,74 @@ +From 76dbc56ad65350d78d12bd9b36b00c36fb27addf Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 23 Aug 2021 16:19:12 +0300 +Subject: [PATCH 223/247] ARM: at91: pm: do not panic if ram controllers are + not enabled + +In case PM is enabled but there is no RAM controller information +in DT the code will panic. Avoid such scenarios by not initializing +platform specific PM code in case RAM controller is not provided +via DT. + +Reported-by: Eugen Hristev +Fixes: 827de1f123ba0 ("ARM: at91: remove at91_dt_initialize and machine init_early()") +Fixes: 892e1f4a3ae58 ("ARM: at91: pm: add sama7g5 ddr phy controller") +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210823131915.23857-2-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 22 ++++++++++++++++------ + 1 file changed, 16 insertions(+), 6 deletions(-) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -589,7 +589,7 @@ static const struct of_device_id ramc_ph + { /* Sentinel. */ }, + }; + +-static __init void at91_dt_ramc(bool phy_mandatory) ++static __init int at91_dt_ramc(bool phy_mandatory) + { + struct device_node *np; + const struct of_device_id *of_id; +@@ -625,12 +625,18 @@ static __init void at91_dt_ramc(bool phy + /* Lookup for DDR PHY node, if any. */ + for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) { + soc_pm.data.ramc_phy = of_iomap(np, 0); +- if (!soc_pm.data.ramc_phy) +- panic(pr_fmt("unable to map ramc phy cpu registers\n")); ++ if (!soc_pm.data.ramc_phy) { ++ pr_err("unable to map ramc phy cpu registers\n"); ++ ret = -ENOMEM; ++ goto unmap_ramc; ++ } + } + +- if (phy_mandatory && !soc_pm.data.ramc_phy) +- panic(pr_fmt("DDR PHY is mandatory!\n")); ++ if (phy_mandatory && !soc_pm.data.ramc_phy) { ++ pr_err("DDR PHY is mandatory!\n"); ++ ret = -ENODEV; ++ goto unmap_ramc; ++ } + + if (!standby) { + pr_warn("ramc no standby function available\n"); +@@ -1163,13 +1169,17 @@ void __init sama7_pm_init(void) + [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | + AT91_PM_IOMAP(SHDWC), + }; ++ int ret; + + if (!IS_ENABLED(CONFIG_SOC_SAMA7)) + return; + + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); + +- at91_dt_ramc(true); ++ ret = at91_dt_ramc(true); ++ if (ret) ++ return; ++ + at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); + at91_pm_init(NULL); + diff --git a/target/linux/at91/patches-5.15/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch b/target/linux/at91/patches-5.15/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch new file mode 100644 index 0000000000..11c0f2c1e3 --- /dev/null +++ b/target/linux/at91/patches-5.15/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch @@ -0,0 +1,36 @@ +From cf96a88e44f1fde9f1a30ab335329ff9e895e6f8 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 23 Aug 2021 16:19:13 +0300 +Subject: [PATCH 224/247] ARM: dts: at91: sama7g5: add ram controllers + +Add RAM and RAMC PHY controllers. These are necessary for platform +specific power management code. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210823131915.23857-3-claudiu.beznea@microchip.com +--- + arch/arm/boot/dts/sama7g5.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm/boot/dts/sama7g5.dtsi ++++ b/arch/arm/boot/dts/sama7g5.dtsi +@@ -515,6 +515,18 @@ + }; + }; + ++ uddrc: uddrc@e3800000 { ++ compatible = "microchip,sama7g5-uddrc"; ++ reg = <0xe3800000 0x4000>; ++ status = "okay"; ++ }; ++ ++ ddr3phy: ddr3phy@e3804000 { ++ compatible = "microchip,sama7g5-ddr3phy"; ++ reg = <0xe3804000 0x1000>; ++ status = "okay"; ++ }; ++ + gic: interrupt-controller@e8c11000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; diff --git a/target/linux/at91/patches-5.15/225-ARM-dts-at91-sama7g5-add-securam-node.patch b/target/linux/at91/patches-5.15/225-ARM-dts-at91-sama7g5-add-securam-node.patch new file mode 100644 index 0000000000..f264f5c129 --- /dev/null +++ b/target/linux/at91/patches-5.15/225-ARM-dts-at91-sama7g5-add-securam-node.patch @@ -0,0 +1,34 @@ +From 1da1aae0b207d6a5ac7c3070b8d7c6ef61a32d71 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 23 Aug 2021 16:19:14 +0300 +Subject: [PATCH 225/247] ARM: dts: at91: sama7g5: add securam node + +Add securam node. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210823131915.23857-4-claudiu.beznea@microchip.com +--- + arch/arm/boot/dts/sama7g5.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/arm/boot/dts/sama7g5.dtsi ++++ b/arch/arm/boot/dts/sama7g5.dtsi +@@ -75,6 +75,17 @@ + #size-cells = <1>; + ranges; + ++ securam: securam@e0000000 { ++ compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; ++ reg = <0xe0000000 0x4000>; ++ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0xe0000000 0x4000>; ++ no-memory-wc; ++ status = "okay"; ++ }; ++ + secumod: secumod@e0004000 { + compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; + reg = <0xe0004000 0x4000>; diff --git a/target/linux/at91/patches-5.15/226-ARM-dts-at91-sama7g5-add-shdwc-node.patch b/target/linux/at91/patches-5.15/226-ARM-dts-at91-sama7g5-add-shdwc-node.patch new file mode 100644 index 0000000000..da941918a1 --- /dev/null +++ b/target/linux/at91/patches-5.15/226-ARM-dts-at91-sama7g5-add-shdwc-node.patch @@ -0,0 +1,53 @@ +From 372fa27d07f66f97a4bf45621c1b840ce8417a85 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 23 Aug 2021 16:19:15 +0300 +Subject: [PATCH 226/247] ARM: dts: at91: sama7g5: add shdwc node + +Add shutdown controller node and enable it. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210823131915.23857-5-claudiu.beznea@microchip.com +--- + arch/arm/boot/dts/at91-sama7g5ek.dts | 9 +++++++++ + arch/arm/boot/dts/sama7g5.dtsi | 11 +++++++++++ + 2 files changed, 20 insertions(+) + +--- a/arch/arm/boot/dts/at91-sama7g5ek.dts ++++ b/arch/arm/boot/dts/at91-sama7g5ek.dts +@@ -634,6 +634,15 @@ + pinctrl-0 = <&pinctrl_sdmmc2_default>; + }; + ++&shdwc { ++ atmel,shdwc-debouncer = <976>; ++ status = "okay"; ++ ++ input@0 { ++ reg = <0>; ++ }; ++}; ++ + &spdifrx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdifrx_default>; +--- a/arch/arm/boot/dts/sama7g5.dtsi ++++ b/arch/arm/boot/dts/sama7g5.dtsi +@@ -122,6 +122,17 @@ + clock-names = "td_slck", "md_slck", "main_xtal"; + }; + ++ shdwc: shdwc@e001d010 { ++ compatible = "microchip,sama7g5-shdwc", "syscon"; ++ reg = <0xe001d010 0x10>; ++ clocks = <&clk32k 0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ atmel,wakeup-rtc-timer; ++ atmel,wakeup-rtt-timer; ++ status = "disabled"; ++ }; ++ + rtt: rtt@e001d020 { + compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; + reg = <0xe001d020 0x30>; diff --git a/target/linux/at91/patches-5.15/227-ARM-dts-at91-sama7g5-add-chipid.patch b/target/linux/at91/patches-5.15/227-ARM-dts-at91-sama7g5-add-chipid.patch new file mode 100644 index 0000000000..3e307e418e --- /dev/null +++ b/target/linux/at91/patches-5.15/227-ARM-dts-at91-sama7g5-add-chipid.patch @@ -0,0 +1,28 @@ +From d216c1ecf978574216ece8140146c8dc0ea400e3 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 8 Sep 2021 12:43:29 +0300 +Subject: [PATCH 227/247] ARM: dts: at91: sama7g5: add chipid + +Add chipid node for sama7g5. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210908094329.182477-1-claudiu.beznea@microchip.com +--- + arch/arm/boot/dts/sama7g5.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm/boot/dts/sama7g5.dtsi ++++ b/arch/arm/boot/dts/sama7g5.dtsi +@@ -159,6 +159,11 @@ + clocks = <&clk32k 0>; + }; + ++ chipid@e0020000 { ++ compatible = "microchip,sama7g5-chipid"; ++ reg = <0xe0020000 0x8>; ++ }; ++ + sdmmc0: mmc@e1204000 { + compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; + reg = <0xe1204000 0x4000>; diff --git a/target/linux/at91/patches-5.15/228-ARM-at91-pm-switch-backup-area-to-vbat-in-backup-mod.patch b/target/linux/at91/patches-5.15/228-ARM-at91-pm-switch-backup-area-to-vbat-in-backup-mod.patch new file mode 100644 index 0000000000..02532b4722 --- /dev/null +++ b/target/linux/at91/patches-5.15/228-ARM-at91-pm-switch-backup-area-to-vbat-in-backup-mod.patch @@ -0,0 +1,117 @@ +From 2cd84ddf0e9623c6bc723b1df368cd8b16a3a8e2 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 30 Aug 2021 13:09:27 +0300 +Subject: [PATCH 228/247] ARM: at91: pm: switch backup area to vbat in backup + mode + +Backup area is now switched to VDDIN33 at boot (with the help of +bootloader). When switching to backup mode we need to switch backup area +to VBAT as all the other power sources are cut off. The resuming from +backup mode is done with the help of bootloader, so there is no need to +do something particular in Linux to restore backup area power source. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210830100927.22711-1-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 52 +++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 52 insertions(+) + +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -47,12 +47,26 @@ struct at91_pm_bu { + unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; + }; + ++/* ++ * struct at91_pm_sfrbu_offsets: registers mapping for SFRBU ++ * @pswbu: power switch BU control registers ++ */ ++struct at91_pm_sfrbu_regs { ++ struct { ++ u32 key; ++ u32 ctrl; ++ u32 state; ++ u32 softsw; ++ } pswbu; ++}; ++ + /** + * struct at91_soc_pm - AT91 SoC power management data structure + * @config_shdwc_ws: wakeup sources configuration function for SHDWC + * @config_pmc_ws: wakeup srouces configuration function for PMC + * @ws_ids: wakup sources of_device_id array + * @data: PM data to be used on last phase of suspend ++ * @sfrbu_regs: SFRBU registers mapping + * @bu: backup unit mapped data (for backup mode) + * @memcs: memory chip select + */ +@@ -62,6 +76,7 @@ struct at91_soc_pm { + const struct of_device_id *ws_ids; + struct at91_pm_bu *bu; + struct at91_pm_data data; ++ struct at91_pm_sfrbu_regs sfrbu_regs; + void *memcs; + }; + +@@ -356,9 +371,36 @@ static int at91_suspend_finish(unsigned + return 0; + } + ++static void at91_pm_switch_ba_to_vbat(void) ++{ ++ unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu); ++ unsigned int val; ++ ++ /* Just for safety. */ ++ if (!soc_pm.data.sfrbu) ++ return; ++ ++ val = readl(soc_pm.data.sfrbu + offset); ++ ++ /* Already on VBAT. */ ++ if (!(val & soc_pm.sfrbu_regs.pswbu.state)) ++ return; ++ ++ val &= ~soc_pm.sfrbu_regs.pswbu.softsw; ++ val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl; ++ writel(val, soc_pm.data.sfrbu + offset); ++ ++ /* Wait for update. */ ++ val = readl(soc_pm.data.sfrbu + offset); ++ while (val & soc_pm.sfrbu_regs.pswbu.state) ++ val = readl(soc_pm.data.sfrbu + offset); ++} ++ + static void at91_pm_suspend(suspend_state_t state) + { + if (soc_pm.data.mode == AT91_PM_BACKUP) { ++ at91_pm_switch_ba_to_vbat(); ++ + cpu_suspend(0, at91_suspend_finish); + + /* The SRAM is lost between suspend cycles */ +@@ -1155,6 +1197,11 @@ void __init sama5d2_pm_init(void) + soc_pm.ws_ids = sama5d2_ws_ids; + soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws; + soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; ++ ++ soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); ++ soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); ++ soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); ++ soc_pm.sfrbu_regs.pswbu.state = BIT(3); + } + + void __init sama7_pm_init(void) +@@ -1185,6 +1232,11 @@ void __init sama7_pm_init(void) + + soc_pm.ws_ids = sama7g5_ws_ids; + soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; ++ ++ soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); ++ soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); ++ soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); ++ soc_pm.sfrbu_regs.pswbu.state = BIT(2); + } + + static int __init at91_pm_modes_select(char *str) diff --git a/target/linux/at91/patches-5.15/229-ARM-dts-at91-sama7g5ek-add-suspend-voltage-for-ddr3l.patch b/target/linux/at91/patches-5.15/229-ARM-dts-at91-sama7g5ek-add-suspend-voltage-for-ddr3l.patch new file mode 100644 index 0000000000..b5074b58a0 --- /dev/null +++ b/target/linux/at91/patches-5.15/229-ARM-dts-at91-sama7g5ek-add-suspend-voltage-for-ddr3l.patch @@ -0,0 +1,42 @@ +From e5f87471392b344b1261d1eaf93fd44710587ea9 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 30 Sep 2021 18:42:17 +0300 +Subject: [PATCH 229/247] ARM: dts: at91: sama7g5ek: add suspend voltage for + ddr3l rail + +SAMA7G5-EK board has DDR3L type of memory soldered. This needs 1.35V. The +1.35V for DDR3L rail at run-time is selected by the proper configuration +on SELV2 pin (for 1.35V it needs to be in high-z state). When suspended +the MCP16502 PMIC soldered on SAMA7G5-EK will use different sets of +configuration registers to provide proper voltages on its rail. Run-time +configuration registers could be configured differently than suspend +configuration register for MCP16502 (VSEL2 affects only run-time +configuration). In suspend states the DDR3L memory soldered on SAMA7G5-EK +switches to self-refresh. Even on self-refresh it needs to be powered by +a 1.35V rail. Thus, make sure the PMIC is configured properly when system +is suspended. + +Fixes: 7540629e2fc7 (ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210930154219.2214051-2-claudiu.beznea@microchip.com +--- + arch/arm/boot/dts/at91-sama7g5ek.dts | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm/boot/dts/at91-sama7g5ek.dts ++++ b/arch/arm/boot/dts/at91-sama7g5ek.dts +@@ -196,11 +196,13 @@ + + regulator-state-standby { + regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + }; diff --git a/target/linux/at91/patches-5.15/230-ARM-at91-pm-group-constants-and-addresses-loading.patch b/target/linux/at91/patches-5.15/230-ARM-at91-pm-group-constants-and-addresses-loading.patch new file mode 100644 index 0000000000..e952f6c377 --- /dev/null +++ b/target/linux/at91/patches-5.15/230-ARM-at91-pm-group-constants-and-addresses-loading.patch @@ -0,0 +1,48 @@ +From 12330a9f6b99622e3c21ddcc720b02431b8a6e2d Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 30 Sep 2021 18:42:18 +0300 +Subject: [PATCH 230/247] ARM: at91: pm: group constants and addresses loading + +Group constants and addresses loading. This commit prepares the field for +the next one. + +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210930154219.2214051-3-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm_suspend.S | 17 +++++++++-------- + 1 file changed, 9 insertions(+), 8 deletions(-) + +--- a/arch/arm/mach-at91/pm_suspend.S ++++ b/arch/arm/mach-at91/pm_suspend.S +@@ -1014,6 +1014,15 @@ ENTRY(at91_pm_suspend_in_sram) + mov tmp1, #0 + mcr p15, 0, tmp1, c7, c10, 4 + ++ ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] ++ str tmp1, .mckr_offset ++ ldr tmp1, [r0, #PM_DATA_PMC_VERSION] ++ str tmp1, .pmc_version ++ ldr tmp1, [r0, #PM_DATA_MEMCTRL] ++ str tmp1, .memtype ++ ldr tmp1, [r0, #PM_DATA_MODE] ++ str tmp1, .pm_mode ++ + ldr tmp1, [r0, #PM_DATA_PMC] + str tmp1, .pmc_base + ldr tmp1, [r0, #PM_DATA_RAMC0] +@@ -1022,14 +1031,6 @@ ENTRY(at91_pm_suspend_in_sram) + str tmp1, .sramc1_base + ldr tmp1, [r0, #PM_DATA_RAMC_PHY] + str tmp1, .sramc_phy_base +- ldr tmp1, [r0, #PM_DATA_MEMCTRL] +- str tmp1, .memtype +- ldr tmp1, [r0, #PM_DATA_MODE] +- str tmp1, .pm_mode +- ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] +- str tmp1, .mckr_offset +- ldr tmp1, [r0, #PM_DATA_PMC_VERSION] +- str tmp1, .pmc_version + /* Both ldrne below are here to preload their address in the TLB */ + ldr tmp1, [r0, #PM_DATA_SHDWC] + str tmp1, .shdwc diff --git a/target/linux/at91/patches-5.15/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch b/target/linux/at91/patches-5.15/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch new file mode 100644 index 0000000000..bd7fb4e39e --- /dev/null +++ b/target/linux/at91/patches-5.15/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch @@ -0,0 +1,93 @@ +From 6075bbc75e55258a762d618cd459dbe0dd38aff9 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 30 Sep 2021 18:42:19 +0300 +Subject: [PATCH 231/247] ARM: at91: pm: preload base address of controllers in + tlb + +In suspend/resume procedure for AT91 architecture different controllers +(PMC, SHDWC, RAM, RAM PHY, SFRBU) are accessed to do the proper settings +for power saving. Commit f0bbf17958e8 ("ARM: at91: pm: add self-refresh +support for sama7g5") introduced the access to RAMC PHY controller for +SAMA7G5. The access to this controller is done after RAMC ports are +closed, thus any TLB walk necessary for RAMC PHY virtual address will +fail. In the development branch this was not encountered. However, on +current kernel the issue is reproducible. + +To solve the issue the previous mechanism of pre-loading the TLB with +the RAMC PHY virtual address has been used. However, only the addition +of this new pre-load breaks the functionality for ARMv5 based +devices (SAM9X60). This behavior has been encountered previously +while debugging this code and using the same mechanism for pre-loading +address for different controllers (e.g. pin controller, the assumption +being that other requested translations are replaced from TLB). + +To solve this new issue the TLB flush + the extension of pre-loading +the rest of controllers to TLB (e.g. PMC, RAMC) has been added. The +rest of the controllers should have been pre-loaded previously, anyway. + +Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5") +Depends-on: e42cbbe5c9a2 ("ARM: at91: pm: group constants and addresses loading") +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210930154219.2214051-4-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm_suspend.S | 25 ++++++++++++++++++++++++- + 1 file changed, 24 insertions(+), 1 deletion(-) + +--- a/arch/arm/mach-at91/pm_suspend.S ++++ b/arch/arm/mach-at91/pm_suspend.S +@@ -1014,6 +1014,10 @@ ENTRY(at91_pm_suspend_in_sram) + mov tmp1, #0 + mcr p15, 0, tmp1, c7, c10, 4 + ++ /* Flush tlb. */ ++ mov r4, #0 ++ mcr p15, 0, r4, c8, c7, 0 ++ + ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] + str tmp1, .mckr_offset + ldr tmp1, [r0, #PM_DATA_PMC_VERSION] +@@ -1023,23 +1027,42 @@ ENTRY(at91_pm_suspend_in_sram) + ldr tmp1, [r0, #PM_DATA_MODE] + str tmp1, .pm_mode + ++ /* ++ * ldrne below are here to preload their address in the TLB as access ++ * to RAM may be limited while in self-refresh. ++ */ + ldr tmp1, [r0, #PM_DATA_PMC] + str tmp1, .pmc_base ++ cmp tmp1, #0 ++ ldrne tmp2, [tmp1, #0] ++ + ldr tmp1, [r0, #PM_DATA_RAMC0] + str tmp1, .sramc_base ++ cmp tmp1, #0 ++ ldrne tmp2, [tmp1, #0] ++ + ldr tmp1, [r0, #PM_DATA_RAMC1] + str tmp1, .sramc1_base ++ cmp tmp1, #0 ++ ldrne tmp2, [tmp1, #0] ++ ++#ifndef CONFIG_SOC_SAM_V4_V5 ++ /* ldrne below are here to preload their address in the TLB */ + ldr tmp1, [r0, #PM_DATA_RAMC_PHY] + str tmp1, .sramc_phy_base +- /* Both ldrne below are here to preload their address in the TLB */ ++ cmp tmp1, #0 ++ ldrne tmp2, [tmp1, #0] ++ + ldr tmp1, [r0, #PM_DATA_SHDWC] + str tmp1, .shdwc + cmp tmp1, #0 + ldrne tmp2, [tmp1, #0] ++ + ldr tmp1, [r0, #PM_DATA_SFRBU] + str tmp1, .sfrbu + cmp tmp1, #0 + ldrne tmp2, [tmp1, #0x10] ++#endif + + /* Active the self-refresh mode */ + at91_sramc_self_refresh_ena diff --git a/target/linux/at91/patches-5.15/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch b/target/linux/at91/patches-5.15/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch new file mode 100644 index 0000000000..9b59d9521f --- /dev/null +++ b/target/linux/at91/patches-5.15/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch @@ -0,0 +1,85 @@ +From 98d2c4ca97dde30616fa78ad5677825b1966cec6 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 15 Sep 2021 10:48:35 +0300 +Subject: [PATCH 232/247] ARM: dts: at91: sama7g5ek: use proper slew-rate + settings for GMACs + +Datasheet chapter "EMAC Timings" specifies that while in 3.3V domain +GMAC's MDIO pins should be configured with slew-rate enabled, while the +data + signaling pins should be configured with slew-rate disabled when +GMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets +the slew-rate as enabled for all pins. Adapt the device tree to comply +with these. + +Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210915074836.6574-2-claudiu.beznea@microchip.com +--- + arch/arm/boot/dts/at91-sama7g5ek.dts | 28 ++++++++++++++++++++++------ + 1 file changed, 22 insertions(+), 6 deletions(-) + +--- a/arch/arm/boot/dts/at91-sama7g5ek.dts ++++ b/arch/arm/boot/dts/at91-sama7g5ek.dts +@@ -355,7 +355,10 @@ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>; ++ pinctrl-0 = <&pinctrl_gmac0_default ++ &pinctrl_gmac0_mdio_default ++ &pinctrl_gmac0_txck_default ++ &pinctrl_gmac0_phy_irq>; + phy-mode = "rgmii-id"; + status = "okay"; + +@@ -370,7 +373,9 @@ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>; ++ pinctrl-0 = <&pinctrl_gmac1_default ++ &pinctrl_gmac1_mdio_default ++ &pinctrl_gmac1_phy_irq>; + phy-mode = "rmii"; + status = "okay"; + +@@ -425,14 +430,20 @@ + , + , + , +- , +- , + ; ++ slew-rate = <0>; ++ bias-disable; ++ }; ++ ++ pinctrl_gmac0_mdio_default: gmac0_mdio_default { ++ pinmux = , ++ ; + bias-disable; + }; + + pinctrl_gmac0_txck_default: gmac0_txck_default { + pinmux = ; ++ slew-rate = <0>; + bias-pull-up; + }; + +@@ -449,8 +460,13 @@ + , + , + , +- , +- , ++ ; ++ slew-rate = <0>; ++ bias-disable; ++ }; ++ ++ pinctrl_gmac1_mdio_default: gmac1_mdio_default { ++ pinmux = , + ; + bias-disable; + }; diff --git a/target/linux/at91/patches-5.15/233-ARM-dts-at91-sama7g5ek-to-not-touch-slew-rate-for-SD.patch b/target/linux/at91/patches-5.15/233-ARM-dts-at91-sama7g5ek-to-not-touch-slew-rate-for-SD.patch new file mode 100644 index 0000000000..61ed933f02 --- /dev/null +++ b/target/linux/at91/patches-5.15/233-ARM-dts-at91-sama7g5ek-to-not-touch-slew-rate-for-SD.patch @@ -0,0 +1,73 @@ +From 4c0b77276307d2cba8ae2595cbae4cc916c84c36 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 15 Sep 2021 10:48:36 +0300 +Subject: [PATCH 233/247] ARM: dts: at91: sama7g5ek: to not touch slew-rate for + SDMMC pins + +With commit c709135e576b ("pinctrl: at91-pio4: add support for slew-rate") +and commit cbde6c823bfa ("pinctrl: at91-pio4: Fix slew rate disablement") +the slew-rate is enabled by default for each configured pin. The datasheet +specifies at chapter "Output Driver AC Characteristics" that HSIO +drivers (use in SDMMCx and QSPI0 peripherals), don't have a slewrate +setting but are rather calibrated against an external 1% resistor mounted +on the SDMMCx_CAL or QSPI0_CAL pins. Depending on the target signal +frequency and the external load, it is possible to adjust their target +output impedance. Thus set slew-rate = <0> for SDMMC (QSPI is not enabled +at the moment in device tree). + +Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") +Signed-off-by: Claudiu Beznea +Signed-off-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20210915074836.6574-3-claudiu.beznea@microchip.com +--- + arch/arm/boot/dts/at91-sama7g5ek.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm/boot/dts/at91-sama7g5ek.dts ++++ b/arch/arm/boot/dts/at91-sama7g5ek.dts +@@ -558,6 +558,7 @@ + , + , + ; ++ slew-rate = <0>; + bias-pull-up; + }; + +@@ -565,6 +566,7 @@ + pinmux = , + , + ; ++ slew-rate = <0>; + bias-pull-up; + }; + }; +@@ -576,6 +578,7 @@ + , + , + ; ++ slew-rate = <0>; + bias-pull-up; + }; + +@@ -584,6 +587,7 @@ + , + , + ; ++ slew-rate = <0>; + bias-pull-up; + }; + }; +@@ -595,11 +599,13 @@ + , + , + ; ++ slew-rate = <0>; + bias-pull-up; + }; + + ck { + pinmux = ; ++ slew-rate = <0>; + bias-pull-up; + }; + }; diff --git a/target/linux/at91/patches-5.15/234-clk-at91-re-factor-clocks-suspend-resume.patch b/target/linux/at91/patches-5.15/234-clk-at91-re-factor-clocks-suspend-resume.patch new file mode 100644 index 0000000000..5d399f6535 --- /dev/null +++ b/target/linux/at91/patches-5.15/234-clk-at91-re-factor-clocks-suspend-resume.patch @@ -0,0 +1,1342 @@ +From 65bb4687b2a5c6f02f44345540c3389d6e7523e7 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:05 +0300 +Subject: [PATCH 234/247] clk: at91: re-factor clocks suspend/resume + +SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where +most of the SoC's components are powered off (including PMC). Resuming +from this mode is done with the help of bootloader. Peripherals are not +aware of the power saving mode thus most of them are disabling clocks in +proper suspend API and re-enable them in resume API without taking into +account the previously setup rate. Moreover some of the peripherals are +acting as wakeup sources and are not disabling the clocks in this +scenario, when suspending. Since backup mode cuts the power for +peripherals, in resume part these clocks needs to be re-configured. + +The initial PMC suspend/resume code was designed only for SAMA5D2's PMC +(as it was the only one supporting backup mode). SAMA7G supports also +backup mode and its PMC is different (few new functionalities, different +registers offsets, different offsets in registers for each +functionalities). To address both SAMA5D2 and SAMA7G5 PMC add +.save_context()/.resume_context() support to each clocks driver and call +this from PMC driver. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-generated.c | 46 +++++-- + drivers/clk/at91/clk-main.c | 66 ++++++++++ + drivers/clk/at91/clk-master.c | 194 ++++++++++++++++++++++++++-- + drivers/clk/at91/clk-peripheral.c | 40 +++++- + drivers/clk/at91/clk-pll.c | 39 ++++++ + drivers/clk/at91/clk-programmable.c | 29 ++++- + drivers/clk/at91/clk-sam9x60-pll.c | 68 +++++++++- + drivers/clk/at91/clk-system.c | 20 +++ + drivers/clk/at91/clk-usb.c | 27 ++++ + drivers/clk/at91/clk-utmi.c | 39 ++++++ + drivers/clk/at91/pmc.c | 147 +-------------------- + drivers/clk/at91/pmc.h | 24 ++-- + 12 files changed, 558 insertions(+), 181 deletions(-) + +--- a/drivers/clk/at91/clk-generated.c ++++ b/drivers/clk/at91/clk-generated.c +@@ -27,6 +27,7 @@ struct clk_generated { + u32 id; + u32 gckdiv; + const struct clk_pcr_layout *layout; ++ struct at91_clk_pms pms; + u8 parent_id; + int chg_pid; + }; +@@ -34,25 +35,35 @@ struct clk_generated { + #define to_clk_generated(hw) \ + container_of(hw, struct clk_generated, hw) + +-static int clk_generated_enable(struct clk_hw *hw) ++static int clk_generated_set(struct clk_generated *gck, int status) + { +- struct clk_generated *gck = to_clk_generated(hw); + unsigned long flags; +- +- pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", +- __func__, gck->gckdiv, gck->parent_id); ++ unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0; + + spin_lock_irqsave(gck->lock, flags); + regmap_write(gck->regmap, gck->layout->offset, + (gck->id & gck->layout->pid_mask)); + regmap_update_bits(gck->regmap, gck->layout->offset, + AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | +- gck->layout->cmd | AT91_PMC_PCR_GCKEN, ++ gck->layout->cmd | enable, + field_prep(gck->layout->gckcss_mask, gck->parent_id) | + gck->layout->cmd | + FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) | +- AT91_PMC_PCR_GCKEN); ++ enable); + spin_unlock_irqrestore(gck->lock, flags); ++ ++ return 0; ++} ++ ++static int clk_generated_enable(struct clk_hw *hw) ++{ ++ struct clk_generated *gck = to_clk_generated(hw); ++ ++ pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", ++ __func__, gck->gckdiv, gck->parent_id); ++ ++ clk_generated_set(gck, 1); ++ + return 0; + } + +@@ -249,6 +260,23 @@ static int clk_generated_set_rate(struct + return 0; + } + ++static int clk_generated_save_context(struct clk_hw *hw) ++{ ++ struct clk_generated *gck = to_clk_generated(hw); ++ ++ gck->pms.status = clk_generated_is_enabled(&gck->hw); ++ ++ return 0; ++} ++ ++static void clk_generated_restore_context(struct clk_hw *hw) ++{ ++ struct clk_generated *gck = to_clk_generated(hw); ++ ++ if (gck->pms.status) ++ clk_generated_set(gck, gck->pms.status); ++} ++ + static const struct clk_ops generated_ops = { + .enable = clk_generated_enable, + .disable = clk_generated_disable, +@@ -258,6 +286,8 @@ static const struct clk_ops generated_op + .get_parent = clk_generated_get_parent, + .set_parent = clk_generated_set_parent, + .set_rate = clk_generated_set_rate, ++ .save_context = clk_generated_save_context, ++ .restore_context = clk_generated_restore_context, + }; + + /** +@@ -324,8 +354,6 @@ at91_clk_register_generated(struct regma + if (ret) { + kfree(gck); + hw = ERR_PTR(ret); +- } else { +- pmc_register_id(id); + } + + return hw; +--- a/drivers/clk/at91/clk-main.c ++++ b/drivers/clk/at91/clk-main.c +@@ -28,6 +28,7 @@ + struct clk_main_osc { + struct clk_hw hw; + struct regmap *regmap; ++ struct at91_clk_pms pms; + }; + + #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw) +@@ -37,6 +38,7 @@ struct clk_main_rc_osc { + struct regmap *regmap; + unsigned long frequency; + unsigned long accuracy; ++ struct at91_clk_pms pms; + }; + + #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw) +@@ -51,6 +53,7 @@ struct clk_rm9200_main { + struct clk_sam9x5_main { + struct clk_hw hw; + struct regmap *regmap; ++ struct at91_clk_pms pms; + u8 parent; + }; + +@@ -120,10 +123,29 @@ static int clk_main_osc_is_prepared(stru + return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp); + } + ++static int clk_main_osc_save_context(struct clk_hw *hw) ++{ ++ struct clk_main_osc *osc = to_clk_main_osc(hw); ++ ++ osc->pms.status = clk_main_osc_is_prepared(hw); ++ ++ return 0; ++} ++ ++static void clk_main_osc_restore_context(struct clk_hw *hw) ++{ ++ struct clk_main_osc *osc = to_clk_main_osc(hw); ++ ++ if (osc->pms.status) ++ clk_main_osc_prepare(hw); ++} ++ + static const struct clk_ops main_osc_ops = { + .prepare = clk_main_osc_prepare, + .unprepare = clk_main_osc_unprepare, + .is_prepared = clk_main_osc_is_prepared, ++ .save_context = clk_main_osc_save_context, ++ .restore_context = clk_main_osc_restore_context, + }; + + struct clk_hw * __init +@@ -240,12 +262,31 @@ static unsigned long clk_main_rc_osc_rec + return osc->accuracy; + } + ++static int clk_main_rc_osc_save_context(struct clk_hw *hw) ++{ ++ struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); ++ ++ osc->pms.status = clk_main_rc_osc_is_prepared(hw); ++ ++ return 0; ++} ++ ++static void clk_main_rc_osc_restore_context(struct clk_hw *hw) ++{ ++ struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); ++ ++ if (osc->pms.status) ++ clk_main_rc_osc_prepare(hw); ++} ++ + static const struct clk_ops main_rc_osc_ops = { + .prepare = clk_main_rc_osc_prepare, + .unprepare = clk_main_rc_osc_unprepare, + .is_prepared = clk_main_rc_osc_is_prepared, + .recalc_rate = clk_main_rc_osc_recalc_rate, + .recalc_accuracy = clk_main_rc_osc_recalc_accuracy, ++ .save_context = clk_main_rc_osc_save_context, ++ .restore_context = clk_main_rc_osc_restore_context, + }; + + struct clk_hw * __init +@@ -465,12 +506,37 @@ static u8 clk_sam9x5_main_get_parent(str + return clk_main_parent_select(status); + } + ++static int clk_sam9x5_main_save_context(struct clk_hw *hw) ++{ ++ struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); ++ ++ clkmain->pms.status = clk_main_rc_osc_is_prepared(&clkmain->hw); ++ clkmain->pms.parent = clk_sam9x5_main_get_parent(&clkmain->hw); ++ ++ return 0; ++} ++ ++static void clk_sam9x5_main_restore_context(struct clk_hw *hw) ++{ ++ struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); ++ int ret; ++ ++ ret = clk_sam9x5_main_set_parent(hw, clkmain->pms.parent); ++ if (ret) ++ return; ++ ++ if (clkmain->pms.status) ++ clk_sam9x5_main_prepare(hw); ++} ++ + static const struct clk_ops sam9x5_main_ops = { + .prepare = clk_sam9x5_main_prepare, + .is_prepared = clk_sam9x5_main_is_prepared, + .recalc_rate = clk_sam9x5_main_recalc_rate, + .set_parent = clk_sam9x5_main_set_parent, + .get_parent = clk_sam9x5_main_get_parent, ++ .save_context = clk_sam9x5_main_save_context, ++ .restore_context = clk_sam9x5_main_restore_context, + }; + + struct clk_hw * __init +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -37,6 +37,7 @@ struct clk_master { + spinlock_t *lock; + const struct clk_master_layout *layout; + const struct clk_master_characteristics *characteristics; ++ struct at91_clk_pms pms; + u32 *mux_table; + u32 mckr; + int chg_pid; +@@ -112,10 +113,52 @@ static unsigned long clk_master_div_reca + return rate; + } + ++static int clk_master_div_save_context(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ struct clk_hw *parent_hw = clk_hw_get_parent(hw); ++ unsigned long flags; ++ unsigned int mckr, div; ++ ++ spin_lock_irqsave(master->lock, flags); ++ regmap_read(master->regmap, master->layout->offset, &mckr); ++ spin_unlock_irqrestore(master->lock, flags); ++ ++ mckr &= master->layout->mask; ++ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ div = master->characteristics->divisors[div]; ++ ++ master->pms.parent_rate = clk_hw_get_rate(parent_hw); ++ master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div); ++ ++ return 0; ++} ++ ++static void clk_master_div_restore_context(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ unsigned long flags; ++ unsigned int mckr; ++ u8 div; ++ ++ spin_lock_irqsave(master->lock, flags); ++ regmap_read(master->regmap, master->layout->offset, &mckr); ++ spin_unlock_irqrestore(master->lock, flags); ++ ++ mckr &= master->layout->mask; ++ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ div = master->characteristics->divisors[div]; ++ ++ if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate)) ++ pr_warn("MCKR DIV not configured properly by firmware!\n"); ++} ++ + static const struct clk_ops master_div_ops = { + .prepare = clk_master_prepare, + .is_prepared = clk_master_is_prepared, + .recalc_rate = clk_master_div_recalc_rate, ++ .save_context = clk_master_div_save_context, ++ .restore_context = clk_master_div_restore_context, + }; + + static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, +@@ -125,7 +168,9 @@ static int clk_master_div_set_rate(struc + const struct clk_master_characteristics *characteristics = + master->characteristics; + unsigned long flags; ++ unsigned int mckr, tmp; + int div, i; ++ int ret; + + div = DIV_ROUND_CLOSEST(parent_rate, rate); + if (div > ARRAY_SIZE(characteristics->divisors)) +@@ -145,11 +190,24 @@ static int clk_master_div_set_rate(struc + return -EINVAL; + + spin_lock_irqsave(master->lock, flags); +- regmap_update_bits(master->regmap, master->layout->offset, +- (MASTER_DIV_MASK << MASTER_DIV_SHIFT), +- (div << MASTER_DIV_SHIFT)); ++ ret = regmap_read(master->regmap, master->layout->offset, &mckr); ++ if (ret) ++ goto unlock; ++ ++ tmp = mckr & master->layout->mask; ++ tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ if (tmp == div) ++ goto unlock; ++ ++ mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT); ++ mckr |= (div << MASTER_DIV_SHIFT); ++ ret = regmap_write(master->regmap, master->layout->offset, mckr); ++ if (ret) ++ goto unlock; ++ + while (!clk_master_ready(master)) + cpu_relax(); ++unlock: + spin_unlock_irqrestore(master->lock, flags); + + return 0; +@@ -197,12 +255,25 @@ static int clk_master_div_determine_rate + return 0; + } + ++static void clk_master_div_restore_context_chg(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ int ret; ++ ++ ret = clk_master_div_set_rate(hw, master->pms.rate, ++ master->pms.parent_rate); ++ if (ret) ++ pr_warn("Failed to restore MCK DIV clock\n"); ++} ++ + static const struct clk_ops master_div_ops_chg = { + .prepare = clk_master_prepare, + .is_prepared = clk_master_is_prepared, + .recalc_rate = clk_master_div_recalc_rate, + .determine_rate = clk_master_div_determine_rate, + .set_rate = clk_master_div_set_rate, ++ .save_context = clk_master_div_save_context, ++ .restore_context = clk_master_div_restore_context_chg, + }; + + static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, +@@ -272,7 +343,8 @@ static int clk_master_pres_set_rate(stru + { + struct clk_master *master = to_clk_master(hw); + unsigned long flags; +- unsigned int pres; ++ unsigned int pres, mckr, tmp; ++ int ret; + + pres = DIV_ROUND_CLOSEST(parent_rate, rate); + if (pres > MASTER_PRES_MAX) +@@ -284,15 +356,27 @@ static int clk_master_pres_set_rate(stru + pres = ffs(pres) - 1; + + spin_lock_irqsave(master->lock, flags); +- regmap_update_bits(master->regmap, master->layout->offset, +- (MASTER_PRES_MASK << master->layout->pres_shift), +- (pres << master->layout->pres_shift)); ++ ret = regmap_read(master->regmap, master->layout->offset, &mckr); ++ if (ret) ++ goto unlock; ++ ++ mckr &= master->layout->mask; ++ tmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK; ++ if (pres == tmp) ++ goto unlock; ++ ++ mckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift); ++ mckr |= (pres << master->layout->pres_shift); ++ ret = regmap_write(master->regmap, master->layout->offset, mckr); ++ if (ret) ++ goto unlock; + + while (!clk_master_ready(master)) + cpu_relax(); ++unlock: + spin_unlock_irqrestore(master->lock, flags); + +- return 0; ++ return ret; + } + + static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, +@@ -330,11 +414,68 @@ static u8 clk_master_pres_get_parent(str + return mckr & AT91_PMC_CSS; + } + ++static int clk_master_pres_save_context(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ struct clk_hw *parent_hw = clk_hw_get_parent(hw); ++ unsigned long flags; ++ unsigned int val, pres; ++ ++ spin_lock_irqsave(master->lock, flags); ++ regmap_read(master->regmap, master->layout->offset, &val); ++ spin_unlock_irqrestore(master->lock, flags); ++ ++ val &= master->layout->mask; ++ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; ++ if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres) ++ pres = 3; ++ else ++ pres = (1 << pres); ++ ++ master->pms.parent = val & AT91_PMC_CSS; ++ master->pms.parent_rate = clk_hw_get_rate(parent_hw); ++ master->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres); ++ ++ return 0; ++} ++ ++static void clk_master_pres_restore_context(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ unsigned long flags; ++ unsigned int val, pres; ++ ++ spin_lock_irqsave(master->lock, flags); ++ regmap_read(master->regmap, master->layout->offset, &val); ++ spin_unlock_irqrestore(master->lock, flags); ++ ++ val &= master->layout->mask; ++ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; ++ if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres) ++ pres = 3; ++ else ++ pres = (1 << pres); ++ ++ if (master->pms.rate != ++ DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) || ++ (master->pms.parent != (val & AT91_PMC_CSS))) ++ pr_warn("MCKR PRES was not configured properly by firmware!\n"); ++} ++ ++static void clk_master_pres_restore_context_chg(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ ++ clk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate); ++} ++ + static const struct clk_ops master_pres_ops = { + .prepare = clk_master_prepare, + .is_prepared = clk_master_is_prepared, + .recalc_rate = clk_master_pres_recalc_rate, + .get_parent = clk_master_pres_get_parent, ++ .save_context = clk_master_pres_save_context, ++ .restore_context = clk_master_pres_restore_context, + }; + + static const struct clk_ops master_pres_ops_chg = { +@@ -344,6 +485,8 @@ static const struct clk_ops master_pres_ + .recalc_rate = clk_master_pres_recalc_rate, + .get_parent = clk_master_pres_get_parent, + .set_rate = clk_master_pres_set_rate, ++ .save_context = clk_master_pres_save_context, ++ .restore_context = clk_master_pres_restore_context_chg, + }; + + static struct clk_hw * __init +@@ -539,20 +682,21 @@ static int clk_sama7g5_master_set_parent + return 0; + } + +-static int clk_sama7g5_master_enable(struct clk_hw *hw) ++static void clk_sama7g5_master_set(struct clk_master *master, ++ unsigned int status) + { +- struct clk_master *master = to_clk_master(hw); + unsigned long flags; + unsigned int val, cparent; ++ unsigned int enable = status ? PMC_MCR_EN : 0; + + spin_lock_irqsave(master->lock, flags); + + regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id)); + regmap_read(master->regmap, PMC_MCR, &val); + regmap_update_bits(master->regmap, PMC_MCR, +- PMC_MCR_EN | PMC_MCR_CSS | PMC_MCR_DIV | ++ enable | PMC_MCR_CSS | PMC_MCR_DIV | + PMC_MCR_CMD | PMC_MCR_ID_MSK, +- PMC_MCR_EN | (master->parent << PMC_MCR_CSS_SHIFT) | ++ enable | (master->parent << PMC_MCR_CSS_SHIFT) | + (master->div << MASTER_DIV_SHIFT) | + PMC_MCR_CMD | PMC_MCR_ID(master->id)); + +@@ -563,6 +707,13 @@ static int clk_sama7g5_master_enable(str + cpu_relax(); + + spin_unlock_irqrestore(master->lock, flags); ++} ++ ++static int clk_sama7g5_master_enable(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ ++ clk_sama7g5_master_set(master, 1); + + return 0; + } +@@ -620,6 +771,23 @@ static int clk_sama7g5_master_set_rate(s + return 0; + } + ++static int clk_sama7g5_master_save_context(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ ++ master->pms.status = clk_sama7g5_master_is_enabled(hw); ++ ++ return 0; ++} ++ ++static void clk_sama7g5_master_restore_context(struct clk_hw *hw) ++{ ++ struct clk_master *master = to_clk_master(hw); ++ ++ if (master->pms.status) ++ clk_sama7g5_master_set(master, master->pms.status); ++} ++ + static const struct clk_ops sama7g5_master_ops = { + .enable = clk_sama7g5_master_enable, + .disable = clk_sama7g5_master_disable, +@@ -629,6 +797,8 @@ static const struct clk_ops sama7g5_mast + .set_rate = clk_sama7g5_master_set_rate, + .get_parent = clk_sama7g5_master_get_parent, + .set_parent = clk_sama7g5_master_set_parent, ++ .save_context = clk_sama7g5_master_save_context, ++ .restore_context = clk_sama7g5_master_restore_context, + }; + + struct clk_hw * __init +--- a/drivers/clk/at91/clk-peripheral.c ++++ b/drivers/clk/at91/clk-peripheral.c +@@ -37,6 +37,7 @@ struct clk_sam9x5_peripheral { + u32 id; + u32 div; + const struct clk_pcr_layout *layout; ++ struct at91_clk_pms pms; + bool auto_div; + int chg_pid; + }; +@@ -155,10 +156,11 @@ static void clk_sam9x5_peripheral_autodi + periph->div = shift; + } + +-static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) ++static int clk_sam9x5_peripheral_set(struct clk_sam9x5_peripheral *periph, ++ unsigned int status) + { +- struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); + unsigned long flags; ++ unsigned int enable = status ? AT91_PMC_PCR_EN : 0; + + if (periph->id < PERIPHERAL_ID_MIN) + return 0; +@@ -168,15 +170,21 @@ static int clk_sam9x5_peripheral_enable( + (periph->id & periph->layout->pid_mask)); + regmap_update_bits(periph->regmap, periph->layout->offset, + periph->layout->div_mask | periph->layout->cmd | +- AT91_PMC_PCR_EN, ++ enable, + field_prep(periph->layout->div_mask, periph->div) | +- periph->layout->cmd | +- AT91_PMC_PCR_EN); ++ periph->layout->cmd | enable); + spin_unlock_irqrestore(periph->lock, flags); + + return 0; + } + ++static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) ++{ ++ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); ++ ++ return clk_sam9x5_peripheral_set(periph, 1); ++} ++ + static void clk_sam9x5_peripheral_disable(struct clk_hw *hw) + { + struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); +@@ -393,6 +401,23 @@ static int clk_sam9x5_peripheral_set_rat + return -EINVAL; + } + ++static int clk_sam9x5_peripheral_save_context(struct clk_hw *hw) ++{ ++ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); ++ ++ periph->pms.status = clk_sam9x5_peripheral_is_enabled(hw); ++ ++ return 0; ++} ++ ++static void clk_sam9x5_peripheral_restore_context(struct clk_hw *hw) ++{ ++ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); ++ ++ if (periph->pms.status) ++ clk_sam9x5_peripheral_set(periph, periph->pms.status); ++} ++ + static const struct clk_ops sam9x5_peripheral_ops = { + .enable = clk_sam9x5_peripheral_enable, + .disable = clk_sam9x5_peripheral_disable, +@@ -400,6 +425,8 @@ static const struct clk_ops sam9x5_perip + .recalc_rate = clk_sam9x5_peripheral_recalc_rate, + .round_rate = clk_sam9x5_peripheral_round_rate, + .set_rate = clk_sam9x5_peripheral_set_rate, ++ .save_context = clk_sam9x5_peripheral_save_context, ++ .restore_context = clk_sam9x5_peripheral_restore_context, + }; + + static const struct clk_ops sam9x5_peripheral_chg_ops = { +@@ -409,6 +436,8 @@ static const struct clk_ops sam9x5_perip + .recalc_rate = clk_sam9x5_peripheral_recalc_rate, + .determine_rate = clk_sam9x5_peripheral_determine_rate, + .set_rate = clk_sam9x5_peripheral_set_rate, ++ .save_context = clk_sam9x5_peripheral_save_context, ++ .restore_context = clk_sam9x5_peripheral_restore_context, + }; + + struct clk_hw * __init +@@ -460,7 +489,6 @@ at91_clk_register_sam9x5_peripheral(stru + hw = ERR_PTR(ret); + } else { + clk_sam9x5_peripheral_autodiv(periph); +- pmc_register_id(id); + } + + return hw; +--- a/drivers/clk/at91/clk-pll.c ++++ b/drivers/clk/at91/clk-pll.c +@@ -40,6 +40,7 @@ struct clk_pll { + u16 mul; + const struct clk_pll_layout *layout; + const struct clk_pll_characteristics *characteristics; ++ struct at91_clk_pms pms; + }; + + static inline bool clk_pll_ready(struct regmap *regmap, int id) +@@ -260,6 +261,42 @@ static int clk_pll_set_rate(struct clk_h + return 0; + } + ++static int clk_pll_save_context(struct clk_hw *hw) ++{ ++ struct clk_pll *pll = to_clk_pll(hw); ++ struct clk_hw *parent_hw = clk_hw_get_parent(hw); ++ ++ pll->pms.parent_rate = clk_hw_get_rate(parent_hw); ++ pll->pms.rate = clk_pll_recalc_rate(&pll->hw, pll->pms.parent_rate); ++ pll->pms.status = clk_pll_ready(pll->regmap, PLL_REG(pll->id)); ++ ++ return 0; ++} ++ ++static void clk_pll_restore_context(struct clk_hw *hw) ++{ ++ struct clk_pll *pll = to_clk_pll(hw); ++ unsigned long calc_rate; ++ unsigned int pllr, pllr_out, pllr_count; ++ u8 out = 0; ++ ++ if (pll->characteristics->out) ++ out = pll->characteristics->out[pll->range]; ++ ++ regmap_read(pll->regmap, PLL_REG(pll->id), &pllr); ++ ++ calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) * ++ (PLL_MUL(pllr, pll->layout) + 1); ++ pllr_count = (pllr >> PLL_COUNT_SHIFT) & PLL_MAX_COUNT; ++ pllr_out = (pllr >> PLL_OUT_SHIFT) & out; ++ ++ if (pll->pms.rate != calc_rate || ++ pll->pms.status != clk_pll_ready(pll->regmap, PLL_REG(pll->id)) || ++ pllr_count != PLL_MAX_COUNT || ++ (out && pllr_out != out)) ++ pr_warn("PLLAR was not configured properly by firmware\n"); ++} ++ + static const struct clk_ops pll_ops = { + .prepare = clk_pll_prepare, + .unprepare = clk_pll_unprepare, +@@ -267,6 +304,8 @@ static const struct clk_ops pll_ops = { + .recalc_rate = clk_pll_recalc_rate, + .round_rate = clk_pll_round_rate, + .set_rate = clk_pll_set_rate, ++ .save_context = clk_pll_save_context, ++ .restore_context = clk_pll_restore_context, + }; + + struct clk_hw * __init +--- a/drivers/clk/at91/clk-programmable.c ++++ b/drivers/clk/at91/clk-programmable.c +@@ -24,6 +24,7 @@ struct clk_programmable { + u32 *mux_table; + u8 id; + const struct clk_programmable_layout *layout; ++ struct at91_clk_pms pms; + }; + + #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw) +@@ -177,12 +178,38 @@ static int clk_programmable_set_rate(str + return 0; + } + ++static int clk_programmable_save_context(struct clk_hw *hw) ++{ ++ struct clk_programmable *prog = to_clk_programmable(hw); ++ struct clk_hw *parent_hw = clk_hw_get_parent(hw); ++ ++ prog->pms.parent = clk_programmable_get_parent(hw); ++ prog->pms.parent_rate = clk_hw_get_rate(parent_hw); ++ prog->pms.rate = clk_programmable_recalc_rate(hw, prog->pms.parent_rate); ++ ++ return 0; ++} ++ ++static void clk_programmable_restore_context(struct clk_hw *hw) ++{ ++ struct clk_programmable *prog = to_clk_programmable(hw); ++ int ret; ++ ++ ret = clk_programmable_set_parent(hw, prog->pms.parent); ++ if (ret) ++ return; ++ ++ clk_programmable_set_rate(hw, prog->pms.rate, prog->pms.parent_rate); ++} ++ + static const struct clk_ops programmable_ops = { + .recalc_rate = clk_programmable_recalc_rate, + .determine_rate = clk_programmable_determine_rate, + .get_parent = clk_programmable_get_parent, + .set_parent = clk_programmable_set_parent, + .set_rate = clk_programmable_set_rate, ++ .save_context = clk_programmable_save_context, ++ .restore_context = clk_programmable_restore_context, + }; + + struct clk_hw * __init +@@ -221,8 +248,6 @@ at91_clk_register_programmable(struct re + if (ret) { + kfree(prog); + hw = ERR_PTR(ret); +- } else { +- pmc_register_pck(id); + } + + return hw; +--- a/drivers/clk/at91/clk-sam9x60-pll.c ++++ b/drivers/clk/at91/clk-sam9x60-pll.c +@@ -38,12 +38,14 @@ struct sam9x60_pll_core { + + struct sam9x60_frac { + struct sam9x60_pll_core core; ++ struct at91_clk_pms pms; + u32 frac; + u16 mul; + }; + + struct sam9x60_div { + struct sam9x60_pll_core core; ++ struct at91_clk_pms pms; + u8 div; + }; + +@@ -75,9 +77,8 @@ static unsigned long sam9x60_frac_pll_re + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); + } + +-static int sam9x60_frac_pll_prepare(struct clk_hw *hw) ++static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) + { +- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); + struct sam9x60_frac *frac = to_sam9x60_frac(core); + struct regmap *regmap = core->regmap; + unsigned int val, cfrac, cmul; +@@ -141,6 +142,13 @@ unlock: + return 0; + } + ++static int sam9x60_frac_pll_prepare(struct clk_hw *hw) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ ++ return sam9x60_frac_pll_set(core); ++} ++ + static void sam9x60_frac_pll_unprepare(struct clk_hw *hw) + { + struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); +@@ -280,6 +288,25 @@ unlock: + return ret; + } + ++static int sam9x60_frac_pll_save_context(struct clk_hw *hw) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ struct sam9x60_frac *frac = to_sam9x60_frac(core); ++ ++ frac->pms.status = sam9x60_pll_ready(core->regmap, core->id); ++ ++ return 0; ++} ++ ++static void sam9x60_frac_pll_restore_context(struct clk_hw *hw) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ struct sam9x60_frac *frac = to_sam9x60_frac(core); ++ ++ if (frac->pms.status) ++ sam9x60_frac_pll_set(core); ++} ++ + static const struct clk_ops sam9x60_frac_pll_ops = { + .prepare = sam9x60_frac_pll_prepare, + .unprepare = sam9x60_frac_pll_unprepare, +@@ -287,6 +314,8 @@ static const struct clk_ops sam9x60_frac + .recalc_rate = sam9x60_frac_pll_recalc_rate, + .round_rate = sam9x60_frac_pll_round_rate, + .set_rate = sam9x60_frac_pll_set_rate, ++ .save_context = sam9x60_frac_pll_save_context, ++ .restore_context = sam9x60_frac_pll_restore_context, + }; + + static const struct clk_ops sam9x60_frac_pll_ops_chg = { +@@ -296,11 +325,12 @@ static const struct clk_ops sam9x60_frac + .recalc_rate = sam9x60_frac_pll_recalc_rate, + .round_rate = sam9x60_frac_pll_round_rate, + .set_rate = sam9x60_frac_pll_set_rate_chg, ++ .save_context = sam9x60_frac_pll_save_context, ++ .restore_context = sam9x60_frac_pll_restore_context, + }; + +-static int sam9x60_div_pll_prepare(struct clk_hw *hw) ++static int sam9x60_div_pll_set(struct sam9x60_pll_core *core) + { +- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); + struct sam9x60_div *div = to_sam9x60_div(core); + struct regmap *regmap = core->regmap; + unsigned long flags; +@@ -334,6 +364,13 @@ unlock: + return 0; + } + ++static int sam9x60_div_pll_prepare(struct clk_hw *hw) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ ++ return sam9x60_div_pll_set(core); ++} ++ + static void sam9x60_div_pll_unprepare(struct clk_hw *hw) + { + struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); +@@ -482,6 +519,25 @@ unlock: + return 0; + } + ++static int sam9x60_div_pll_save_context(struct clk_hw *hw) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ struct sam9x60_div *div = to_sam9x60_div(core); ++ ++ div->pms.status = sam9x60_div_pll_is_prepared(hw); ++ ++ return 0; ++} ++ ++static void sam9x60_div_pll_restore_context(struct clk_hw *hw) ++{ ++ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); ++ struct sam9x60_div *div = to_sam9x60_div(core); ++ ++ if (div->pms.status) ++ sam9x60_div_pll_set(core); ++} ++ + static const struct clk_ops sam9x60_div_pll_ops = { + .prepare = sam9x60_div_pll_prepare, + .unprepare = sam9x60_div_pll_unprepare, +@@ -489,6 +545,8 @@ static const struct clk_ops sam9x60_div_ + .recalc_rate = sam9x60_div_pll_recalc_rate, + .round_rate = sam9x60_div_pll_round_rate, + .set_rate = sam9x60_div_pll_set_rate, ++ .save_context = sam9x60_div_pll_save_context, ++ .restore_context = sam9x60_div_pll_restore_context, + }; + + static const struct clk_ops sam9x60_div_pll_ops_chg = { +@@ -498,6 +556,8 @@ static const struct clk_ops sam9x60_div_ + .recalc_rate = sam9x60_div_pll_recalc_rate, + .round_rate = sam9x60_div_pll_round_rate, + .set_rate = sam9x60_div_pll_set_rate_chg, ++ .save_context = sam9x60_div_pll_save_context, ++ .restore_context = sam9x60_div_pll_restore_context, + }; + + struct clk_hw * __init +--- a/drivers/clk/at91/clk-system.c ++++ b/drivers/clk/at91/clk-system.c +@@ -20,6 +20,7 @@ + struct clk_system { + struct clk_hw hw; + struct regmap *regmap; ++ struct at91_clk_pms pms; + u8 id; + }; + +@@ -77,10 +78,29 @@ static int clk_system_is_prepared(struct + return !!(status & (1 << sys->id)); + } + ++static int clk_system_save_context(struct clk_hw *hw) ++{ ++ struct clk_system *sys = to_clk_system(hw); ++ ++ sys->pms.status = clk_system_is_prepared(hw); ++ ++ return 0; ++} ++ ++static void clk_system_restore_context(struct clk_hw *hw) ++{ ++ struct clk_system *sys = to_clk_system(hw); ++ ++ if (sys->pms.status) ++ clk_system_prepare(&sys->hw); ++} ++ + static const struct clk_ops system_ops = { + .prepare = clk_system_prepare, + .unprepare = clk_system_unprepare, + .is_prepared = clk_system_is_prepared, ++ .save_context = clk_system_save_context, ++ .restore_context = clk_system_restore_context, + }; + + struct clk_hw * __init +--- a/drivers/clk/at91/clk-usb.c ++++ b/drivers/clk/at91/clk-usb.c +@@ -24,6 +24,7 @@ + struct at91sam9x5_clk_usb { + struct clk_hw hw; + struct regmap *regmap; ++ struct at91_clk_pms pms; + u32 usbs_mask; + u8 num_parents; + }; +@@ -148,12 +149,38 @@ static int at91sam9x5_clk_usb_set_rate(s + return 0; + } + ++static int at91sam9x5_usb_save_context(struct clk_hw *hw) ++{ ++ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); ++ struct clk_hw *parent_hw = clk_hw_get_parent(hw); ++ ++ usb->pms.parent = at91sam9x5_clk_usb_get_parent(hw); ++ usb->pms.parent_rate = clk_hw_get_rate(parent_hw); ++ usb->pms.rate = at91sam9x5_clk_usb_recalc_rate(hw, usb->pms.parent_rate); ++ ++ return 0; ++} ++ ++static void at91sam9x5_usb_restore_context(struct clk_hw *hw) ++{ ++ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); ++ int ret; ++ ++ ret = at91sam9x5_clk_usb_set_parent(hw, usb->pms.parent); ++ if (ret) ++ return; ++ ++ at91sam9x5_clk_usb_set_rate(hw, usb->pms.rate, usb->pms.parent_rate); ++} ++ + static const struct clk_ops at91sam9x5_usb_ops = { + .recalc_rate = at91sam9x5_clk_usb_recalc_rate, + .determine_rate = at91sam9x5_clk_usb_determine_rate, + .get_parent = at91sam9x5_clk_usb_get_parent, + .set_parent = at91sam9x5_clk_usb_set_parent, + .set_rate = at91sam9x5_clk_usb_set_rate, ++ .save_context = at91sam9x5_usb_save_context, ++ .restore_context = at91sam9x5_usb_restore_context, + }; + + static int at91sam9n12_clk_usb_enable(struct clk_hw *hw) +--- a/drivers/clk/at91/clk-utmi.c ++++ b/drivers/clk/at91/clk-utmi.c +@@ -23,6 +23,7 @@ struct clk_utmi { + struct clk_hw hw; + struct regmap *regmap_pmc; + struct regmap *regmap_sfr; ++ struct at91_clk_pms pms; + }; + + #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw) +@@ -113,11 +114,30 @@ static unsigned long clk_utmi_recalc_rat + return UTMI_RATE; + } + ++static int clk_utmi_save_context(struct clk_hw *hw) ++{ ++ struct clk_utmi *utmi = to_clk_utmi(hw); ++ ++ utmi->pms.status = clk_utmi_is_prepared(hw); ++ ++ return 0; ++} ++ ++static void clk_utmi_restore_context(struct clk_hw *hw) ++{ ++ struct clk_utmi *utmi = to_clk_utmi(hw); ++ ++ if (utmi->pms.status) ++ clk_utmi_prepare(hw); ++} ++ + static const struct clk_ops utmi_ops = { + .prepare = clk_utmi_prepare, + .unprepare = clk_utmi_unprepare, + .is_prepared = clk_utmi_is_prepared, + .recalc_rate = clk_utmi_recalc_rate, ++ .save_context = clk_utmi_save_context, ++ .restore_context = clk_utmi_restore_context, + }; + + static struct clk_hw * __init +@@ -232,10 +252,29 @@ static int clk_utmi_sama7g5_is_prepared( + return 0; + } + ++static int clk_utmi_sama7g5_save_context(struct clk_hw *hw) ++{ ++ struct clk_utmi *utmi = to_clk_utmi(hw); ++ ++ utmi->pms.status = clk_utmi_sama7g5_is_prepared(hw); ++ ++ return 0; ++} ++ ++static void clk_utmi_sama7g5_restore_context(struct clk_hw *hw) ++{ ++ struct clk_utmi *utmi = to_clk_utmi(hw); ++ ++ if (utmi->pms.status) ++ clk_utmi_sama7g5_prepare(hw); ++} ++ + static const struct clk_ops sama7g5_utmi_ops = { + .prepare = clk_utmi_sama7g5_prepare, + .is_prepared = clk_utmi_sama7g5_is_prepared, + .recalc_rate = clk_utmi_recalc_rate, ++ .save_context = clk_utmi_sama7g5_save_context, ++ .restore_context = clk_utmi_sama7g5_restore_context, + }; + + struct clk_hw * __init +--- a/drivers/clk/at91/pmc.c ++++ b/drivers/clk/at91/pmc.c +@@ -3,6 +3,7 @@ + * Copyright (C) 2013 Boris BREZILLON + */ + ++#include + #include + #include + #include +@@ -14,8 +15,6 @@ + + #include + +-#include +- + #include "pmc.h" + + #define PMC_MAX_IDS 128 +@@ -111,147 +110,19 @@ struct pmc_data *pmc_data_allocate(unsig + } + + #ifdef CONFIG_PM +-static struct regmap *pmcreg; +- +-static u8 registered_ids[PMC_MAX_IDS]; +-static u8 registered_pcks[PMC_MAX_PCKS]; +- +-static struct +-{ +- u32 scsr; +- u32 pcsr0; +- u32 uckr; +- u32 mor; +- u32 mcfr; +- u32 pllar; +- u32 mckr; +- u32 usb; +- u32 imr; +- u32 pcsr1; +- u32 pcr[PMC_MAX_IDS]; +- u32 audio_pll0; +- u32 audio_pll1; +- u32 pckr[PMC_MAX_PCKS]; +-} pmc_cache; +- +-/* +- * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored +- * without alteration in the table, and 0 is for unused clocks. +- */ +-void pmc_register_id(u8 id) ++static int at91_pmc_suspend(void) + { +- int i; +- +- for (i = 0; i < PMC_MAX_IDS; i++) { +- if (registered_ids[i] == 0) { +- registered_ids[i] = id; +- break; +- } +- if (registered_ids[i] == id) +- break; +- } ++ return clk_save_context(); + } + +-/* +- * As Programmable Clock 0 is valid on AT91 chips, there is an offset +- * of 1 between the stored value and the real clock ID. +- */ +-void pmc_register_pck(u8 pck) ++static void at91_pmc_resume(void) + { +- int i; +- +- for (i = 0; i < PMC_MAX_PCKS; i++) { +- if (registered_pcks[i] == 0) { +- registered_pcks[i] = pck + 1; +- break; +- } +- if (registered_pcks[i] == (pck + 1)) +- break; +- } +-} +- +-static int pmc_suspend(void) +-{ +- int i; +- u8 num; +- +- regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr); +- regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0); +- regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr); +- regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor); +- regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr); +- regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar); +- regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr); +- regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb); +- regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr); +- regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1); +- +- for (i = 0; registered_ids[i]; i++) { +- regmap_write(pmcreg, AT91_PMC_PCR, +- (registered_ids[i] & AT91_PMC_PCR_PID_MASK)); +- regmap_read(pmcreg, AT91_PMC_PCR, +- &pmc_cache.pcr[registered_ids[i]]); +- } +- for (i = 0; registered_pcks[i]; i++) { +- num = registered_pcks[i] - 1; +- regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]); +- } +- +- return 0; +-} +- +-static bool pmc_ready(unsigned int mask) +-{ +- unsigned int status; +- +- regmap_read(pmcreg, AT91_PMC_SR, &status); +- +- return ((status & mask) == mask) ? 1 : 0; +-} +- +-static void pmc_resume(void) +-{ +- int i; +- u8 num; +- u32 tmp; +- u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA; +- +- regmap_read(pmcreg, AT91_PMC_MCKR, &tmp); +- if (pmc_cache.mckr != tmp) +- pr_warn("MCKR was not configured properly by the firmware\n"); +- regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp); +- if (pmc_cache.pllar != tmp) +- pr_warn("PLLAR was not configured properly by the firmware\n"); +- +- regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr); +- regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0); +- regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr); +- regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor); +- regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr); +- regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb); +- regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr); +- regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1); +- +- for (i = 0; registered_ids[i]; i++) { +- regmap_write(pmcreg, AT91_PMC_PCR, +- pmc_cache.pcr[registered_ids[i]] | +- AT91_PMC_PCR_CMD); +- } +- for (i = 0; registered_pcks[i]; i++) { +- num = registered_pcks[i] - 1; +- regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]); +- } +- +- if (pmc_cache.uckr & AT91_PMC_UPLLEN) +- mask |= AT91_PMC_LOCKU; +- +- while (!pmc_ready(mask)) +- cpu_relax(); ++ clk_restore_context(); + } + + static struct syscore_ops pmc_syscore_ops = { +- .suspend = pmc_suspend, +- .resume = pmc_resume, ++ .suspend = at91_pmc_suspend, ++ .resume = at91_pmc_resume, + }; + + static const struct of_device_id sama5d2_pmc_dt_ids[] = { +@@ -271,11 +142,7 @@ static int __init pmc_register_ops(void) + of_node_put(np); + return -ENODEV; + } +- +- pmcreg = device_node_to_regmap(np); + of_node_put(np); +- if (IS_ERR(pmcreg)) +- return PTR_ERR(pmcreg); + + register_syscore_ops(&pmc_syscore_ops); + +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -13,6 +13,8 @@ + #include + #include + ++#include ++ + extern spinlock_t pmc_pcr_lock; + + struct pmc_data { +@@ -98,6 +100,20 @@ struct clk_pcr_layout { + u32 pid_mask; + }; + ++/** ++ * struct at91_clk_pms - Power management state for AT91 clock ++ * @rate: clock rate ++ * @parent_rate: clock parent rate ++ * @status: clock status (enabled or disabled) ++ * @parent: clock parent index ++ */ ++struct at91_clk_pms { ++ unsigned long rate; ++ unsigned long parent_rate; ++ unsigned int status; ++ unsigned int parent; ++}; ++ + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +@@ -248,12 +264,4 @@ struct clk_hw * __init + at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name, + const char *parent_name); + +-#ifdef CONFIG_PM +-void pmc_register_id(u8 id); +-void pmc_register_pck(u8 pck); +-#else +-static inline void pmc_register_id(u8 id) {} +-static inline void pmc_register_pck(u8 pck) {} +-#endif +- + #endif /* __PMC_H_ */ diff --git a/target/linux/at91/patches-5.15/235-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch b/target/linux/at91/patches-5.15/235-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch new file mode 100644 index 0000000000..19f1f6fdf2 --- /dev/null +++ b/target/linux/at91/patches-5.15/235-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch @@ -0,0 +1,89 @@ +From 63a0c32028148e91ea91cfbf95841c4ecd69d21b Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:06 +0300 +Subject: [PATCH 235/247] clk: at91: pmc: execute suspend/resume only for + backup mode + +Before going to backup mode architecture specific PM code sets the first +word in securam (file arch/arm/mach-at91/pm.c, function at91_pm_begin()). +Thus take this into account when suspending/resuming clocks. This will +avoid executing unnecessary instructions when suspending to non backup +modes. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-3-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/pmc.c | 39 +++++++++++++++++++++++++++++++++++++++ + 1 file changed, 39 insertions(+) + +--- a/drivers/clk/at91/pmc.c ++++ b/drivers/clk/at91/pmc.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -110,13 +111,35 @@ struct pmc_data *pmc_data_allocate(unsig + } + + #ifdef CONFIG_PM ++ ++/* Address in SECURAM that say if we suspend to backup mode. */ ++static void __iomem *at91_pmc_backup_suspend; ++ + static int at91_pmc_suspend(void) + { ++ unsigned int backup; ++ ++ if (!at91_pmc_backup_suspend) ++ return 0; ++ ++ backup = readl_relaxed(at91_pmc_backup_suspend); ++ if (!backup) ++ return 0; ++ + return clk_save_context(); + } + + static void at91_pmc_resume(void) + { ++ unsigned int backup; ++ ++ if (!at91_pmc_backup_suspend) ++ return; ++ ++ backup = readl_relaxed(at91_pmc_backup_suspend); ++ if (!backup) ++ return; ++ + clk_restore_context(); + } + +@@ -144,6 +167,22 @@ static int __init pmc_register_ops(void) + } + of_node_put(np); + ++ np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); ++ if (!np) ++ return -ENODEV; ++ ++ if (!of_device_is_available(np)) { ++ of_node_put(np); ++ return -ENODEV; ++ } ++ of_node_put(np); ++ ++ at91_pmc_backup_suspend = of_iomap(np, 0); ++ if (!at91_pmc_backup_suspend) { ++ pr_warn("%s(): unable to map securam\n", __func__); ++ return -ENOMEM; ++ } ++ + register_syscore_ops(&pmc_syscore_ops); + + return 0; diff --git a/target/linux/at91/patches-5.15/236-clk-at91-sama7g5-add-securam-s-peripheral-clock.patch b/target/linux/at91/patches-5.15/236-clk-at91-sama7g5-add-securam-s-peripheral-clock.patch new file mode 100644 index 0000000000..046acec453 --- /dev/null +++ b/target/linux/at91/patches-5.15/236-clk-at91-sama7g5-add-securam-s-peripheral-clock.patch @@ -0,0 +1,25 @@ +From 50edd53c26177e95995533b7d649801086a52f6c Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:07 +0300 +Subject: [PATCH 236/247] clk: at91: sama7g5: add securam's peripheral clock + +Add SECURAM's peripheral clock. + +Signed-off-by: Claudiu Beznea +Acked-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20211011112719.3951784-4-claudiu.beznea@microchip.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -377,6 +377,7 @@ static const struct { + u8 id; + } sama7g5_periphck[] = { + { .n = "pioA_clk", .p = "mck0", .id = 11, }, ++ { .n = "securam_clk", .p = "mck0", .id = 18, }, + { .n = "sfr_clk", .p = "mck1", .id = 19, }, + { .n = "hsmc_clk", .p = "mck1", .id = 21, }, + { .n = "xdmac0_clk", .p = "mck1", .id = 22, }, diff --git a/target/linux/at91/patches-5.15/237-clk-at91-clk-master-add-register-definition-for-sama.patch b/target/linux/at91/patches-5.15/237-clk-at91-clk-master-add-register-definition-for-sama.patch new file mode 100644 index 0000000000..726d9b33e4 --- /dev/null +++ b/target/linux/at91/patches-5.15/237-clk-at91-clk-master-add-register-definition-for-sama.patch @@ -0,0 +1,124 @@ +From c716562753d1e51a1c53647aa77a332f97187d15 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:08 +0300 +Subject: [PATCH 237/247] clk: at91: clk-master: add register definition for + sama7g5's master clock + +SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the +register at offset 0x30 (relative to PMC). In the last/first phase of +suspend/resume procedure (which is architecture specific) the parent +of master clocks are changed (via assembly code) for more power saving +(see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable +and at91_mckx_ps_restore). Thus the macros corresponding to register +at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S. +commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's +master clock") introduced the proper macros but didn't adapted the +clk-master.c as well. Thus, this commit adapt the clk-master.c to use +the macros introduced in commit ec03f18cc222 ("clk: at91: add register +definition for sama7g5's master clock"). + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-master.c | 50 ++++++++++++++++------------------- + 1 file changed, 23 insertions(+), 27 deletions(-) + +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -17,15 +17,7 @@ + #define MASTER_DIV_SHIFT 8 + #define MASTER_DIV_MASK 0x7 + +-#define PMC_MCR 0x30 +-#define PMC_MCR_ID_MSK GENMASK(3, 0) +-#define PMC_MCR_CMD BIT(7) +-#define PMC_MCR_DIV GENMASK(10, 8) +-#define PMC_MCR_CSS GENMASK(20, 16) + #define PMC_MCR_CSS_SHIFT (16) +-#define PMC_MCR_EN BIT(28) +- +-#define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK) + + #define MASTER_MAX_ID 4 + +@@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struc + { + unsigned long flags; + unsigned int val, cparent; +- unsigned int enable = status ? PMC_MCR_EN : 0; ++ unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0; + + spin_lock_irqsave(master->lock, flags); + +- regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id)); +- regmap_read(master->regmap, PMC_MCR, &val); +- regmap_update_bits(master->regmap, PMC_MCR, +- enable | PMC_MCR_CSS | PMC_MCR_DIV | +- PMC_MCR_CMD | PMC_MCR_ID_MSK, ++ regmap_write(master->regmap, AT91_PMC_MCR_V2, ++ AT91_PMC_MCR_V2_ID(master->id)); ++ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); ++ regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, ++ enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV | ++ AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK, + enable | (master->parent << PMC_MCR_CSS_SHIFT) | + (master->div << MASTER_DIV_SHIFT) | +- PMC_MCR_CMD | PMC_MCR_ID(master->id)); ++ AT91_PMC_MCR_V2_CMD | ++ AT91_PMC_MCR_V2_ID(master->id)); + +- cparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT; ++ cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; + + /* Wait here only if parent is being changed. */ + while ((cparent != master->parent) && !clk_master_ready(master)) +@@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(s + + spin_lock_irqsave(master->lock, flags); + +- regmap_write(master->regmap, PMC_MCR, master->id); +- regmap_update_bits(master->regmap, PMC_MCR, +- PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK, +- PMC_MCR_CMD | PMC_MCR_ID(master->id)); ++ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); ++ regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, ++ AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD | ++ AT91_PMC_MCR_V2_ID_MSK, ++ AT91_PMC_MCR_V2_CMD | ++ AT91_PMC_MCR_V2_ID(master->id)); + + spin_unlock_irqrestore(master->lock, flags); + } +@@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled + + spin_lock_irqsave(master->lock, flags); + +- regmap_write(master->regmap, PMC_MCR, master->id); +- regmap_read(master->regmap, PMC_MCR, &val); ++ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); ++ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); + + spin_unlock_irqrestore(master->lock, flags); + +- return !!(val & PMC_MCR_EN); ++ return !!(val & AT91_PMC_MCR_V2_EN); + } + + static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate, +@@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct + master->mux_table = mux_table; + + spin_lock_irqsave(master->lock, flags); +- regmap_write(master->regmap, PMC_MCR, master->id); +- regmap_read(master->regmap, PMC_MCR, &val); +- master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT; +- master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT; ++ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); ++ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); ++ master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; ++ master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT; + spin_unlock_irqrestore(master->lock, flags); + + hw = &master->hw; diff --git a/target/linux/at91/patches-5.15/238-clk-at91-clk-master-improve-readability-by-using-loc.patch b/target/linux/at91/patches-5.15/238-clk-at91-clk-master-improve-readability-by-using-loc.patch new file mode 100644 index 0000000000..a5b57a67ad --- /dev/null +++ b/target/linux/at91/patches-5.15/238-clk-at91-clk-master-improve-readability-by-using-loc.patch @@ -0,0 +1,40 @@ +From 17b53ad1574cb5f41789993289d3d94f7a50f0ce Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:09 +0300 +Subject: [PATCH 238/247] clk: at91: clk-master: improve readability by using + local variables + +Improve readability in clk_sama7g5_master_set() by using local +variables. + +Suggested-by: Nicolas Ferre +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-6-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-master.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -680,6 +680,8 @@ static void clk_sama7g5_master_set(struc + unsigned long flags; + unsigned int val, cparent; + unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0; ++ unsigned int parent = master->parent << PMC_MCR_CSS_SHIFT; ++ unsigned int div = master->div << MASTER_DIV_SHIFT; + + spin_lock_irqsave(master->lock, flags); + +@@ -689,9 +691,7 @@ static void clk_sama7g5_master_set(struc + regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, + enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV | + AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK, +- enable | (master->parent << PMC_MCR_CSS_SHIFT) | +- (master->div << MASTER_DIV_SHIFT) | +- AT91_PMC_MCR_V2_CMD | ++ enable | parent | div | AT91_PMC_MCR_V2_CMD | + AT91_PMC_MCR_V2_ID(master->id)); + + cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; diff --git a/target/linux/at91/patches-5.15/239-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch b/target/linux/at91/patches-5.15/239-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch new file mode 100644 index 0000000000..2918de1700 --- /dev/null +++ b/target/linux/at91/patches-5.15/239-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch @@ -0,0 +1,39 @@ +From 8a38e0dda46c9d941a61d8b2e6c14704531b7871 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:10 +0300 +Subject: [PATCH 239/247] clk: at91: pmc: add sama7g5 to the list of available + pmcs + +Add SAMA7G5 to the list of available PMCs such that the suspend/resume +code for clocks to be used on backup mode. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-7-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/pmc.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/clk/at91/pmc.c ++++ b/drivers/clk/at91/pmc.c +@@ -148,8 +148,9 @@ static struct syscore_ops pmc_syscore_op + .resume = at91_pmc_resume, + }; + +-static const struct of_device_id sama5d2_pmc_dt_ids[] = { ++static const struct of_device_id pmc_dt_ids[] = { + { .compatible = "atmel,sama5d2-pmc" }, ++ { .compatible = "microchip,sama7g5-pmc", }, + { /* sentinel */ } + }; + +@@ -157,7 +158,7 @@ static int __init pmc_register_ops(void) + { + struct device_node *np; + +- np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids); ++ np = of_find_matching_node(NULL, pmc_dt_ids); + if (!np) + return -ENODEV; + diff --git a/target/linux/at91/patches-5.15/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch b/target/linux/at91/patches-5.15/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch new file mode 100644 index 0000000000..c78883c8d6 --- /dev/null +++ b/target/linux/at91/patches-5.15/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch @@ -0,0 +1,39 @@ +From bb8e6ca274763fa98613dbe8b0833348a1d8fe4d Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:12 +0300 +Subject: [PATCH 240/247] clk: at91: clk-master: check if div or pres is zero + +Check if div or pres is zero before using it as argument for ffs(). +In case div is zero ffs() will return 0 and thus substracting from +zero will lead to invalid values to be setup in registers. + +Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") +Fixes: 75c88143f3b87 ("clk: at91: clk-master: add master clock support for SAMA7G5") +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-9-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-master.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -344,7 +344,7 @@ static int clk_master_pres_set_rate(stru + + else if (pres == 3) + pres = MASTER_PRES_MAX; +- else ++ else if (pres) + pres = ffs(pres) - 1; + + spin_lock_irqsave(master->lock, flags); +@@ -757,7 +757,7 @@ static int clk_sama7g5_master_set_rate(s + + if (div == 3) + div = MASTER_PRES_MAX; +- else ++ else if (div) + div = ffs(div) - 1; + + spin_lock_irqsave(master->lock, flags); diff --git a/target/linux/at91/patches-5.15/241-clk-at91-clk-master-mask-mckr-against-layout-mask.patch b/target/linux/at91/patches-5.15/241-clk-at91-clk-master-mask-mckr-against-layout-mask.patch new file mode 100644 index 0000000000..14fa690769 --- /dev/null +++ b/target/linux/at91/patches-5.15/241-clk-at91-clk-master-mask-mckr-against-layout-mask.patch @@ -0,0 +1,46 @@ +From 27c11c09346b7b9f67eeb39db1b943f4a9742ff3 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:13 +0300 +Subject: [PATCH 241/247] clk: at91: clk-master: mask mckr against layout->mask + +Mask values read/written from/to MCKR against layout->mask as this +mask may be different b/w PMC versions. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-10-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-master.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -186,8 +186,8 @@ static int clk_master_div_set_rate(struc + if (ret) + goto unlock; + +- tmp = mckr & master->layout->mask; +- tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ mckr &= master->layout->mask; ++ tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + if (tmp == div) + goto unlock; + +@@ -384,6 +384,7 @@ static unsigned long clk_master_pres_rec + regmap_read(master->regmap, master->layout->offset, &val); + spin_unlock_irqrestore(master->lock, flags); + ++ val &= master->layout->mask; + pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; + if (pres == 3 && characteristics->have_div3_pres) + pres = 3; +@@ -403,6 +404,8 @@ static u8 clk_master_pres_get_parent(str + regmap_read(master->regmap, master->layout->offset, &mckr); + spin_unlock_irqrestore(master->lock, flags); + ++ mckr &= master->layout->mask; ++ + return mckr & AT91_PMC_CSS; + } + diff --git a/target/linux/at91/patches-5.15/242-clk-at91-clk-master-fix-prescaler-logic.patch b/target/linux/at91/patches-5.15/242-clk-at91-clk-master-fix-prescaler-logic.patch new file mode 100644 index 0000000000..950ca26afd --- /dev/null +++ b/target/linux/at91/patches-5.15/242-clk-at91-clk-master-fix-prescaler-logic.patch @@ -0,0 +1,29 @@ +From 4375cd63b55860f5e82618dc5f50846b3129842a Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:14 +0300 +Subject: [PATCH 242/247] clk: at91: clk-master: fix prescaler logic + +When prescaler value read from register is MASTER_PRES_MAX it means +that the input clock will be divided by 3. Fix the code to reflect +this. + +Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-master.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -386,7 +386,7 @@ static unsigned long clk_master_pres_rec + + val &= master->layout->mask; + pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; +- if (pres == 3 && characteristics->have_div3_pres) ++ if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres) + pres = 3; + else + pres = (1 << pres); diff --git a/target/linux/at91/patches-5.15/243-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch b/target/linux/at91/patches-5.15/243-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch new file mode 100644 index 0000000000..678303da37 --- /dev/null +++ b/target/linux/at91/patches-5.15/243-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch @@ -0,0 +1,312 @@ +From e76d2af5009f52aa02d3db7ae32d150ad66398f9 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:15 +0300 +Subject: [PATCH 243/247] clk: at91: clk-sam9x60-pll: add notifier for div part + of PLL + +SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts: +one fractional part and one divider. On SAMA7G5 the CPU PLL could be +changed at run-time to implement DVFS. The hardware clock tree on +SAMA7G5 for CPU PLL is as follows: + + +---- div1 ----------------> cpuck + | +FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0 + +The div1 block is not implemented in Linux; on prescaler block it has +been discovered a bug on some scenarios and will be removed from Linux +in next commits. Thus, the final clock tree that will be used in Linux +will be as follows: + + +-----------> cpuck + | +FRAC PLL ---> DIV PLL -+-> div0 ---> mck0 + +It has been proposed in [1] to not introduce a new CPUFreq driver but +to overload the proper clock drivers with proper operation such that +cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement +clock notifiers which applies safe dividers before FRAC PLL is changed. +The current commit treats only the DIV PLL by adding a notifier that +sets a safe divider on PRE_RATE_CHANGE events. The safe divider is +provided by initialization clock code (sama7g5.c). The div0 is treated +in next commits (to keep the changes as clean as possible). + +[1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/ + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-12-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/clk-sam9x60-pll.c | 102 ++++++++++++++++++++++------- + drivers/clk/at91/pmc.h | 3 +- + drivers/clk/at91/sam9x60.c | 6 +- + drivers/clk/at91/sama7g5.c | 13 +++- + 4 files changed, 95 insertions(+), 29 deletions(-) + +--- a/drivers/clk/at91/clk-sam9x60-pll.c ++++ b/drivers/clk/at91/clk-sam9x60-pll.c +@@ -5,6 +5,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -47,12 +48,15 @@ struct sam9x60_div { + struct sam9x60_pll_core core; + struct at91_clk_pms pms; + u8 div; ++ u8 safe_div; + }; + + #define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw) + #define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core) + #define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core) + ++static struct sam9x60_div *notifier_div; ++ + static inline bool sam9x60_pll_ready(struct regmap *regmap, int id) + { + unsigned int status; +@@ -329,6 +333,26 @@ static const struct clk_ops sam9x60_frac + .restore_context = sam9x60_frac_pll_restore_context, + }; + ++/* This function should be called with spinlock acquired. */ ++static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div, ++ bool enable) ++{ ++ struct regmap *regmap = core->regmap; ++ u32 ena_msk = enable ? core->layout->endiv_mask : 0; ++ u32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0; ++ ++ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, ++ core->layout->div_mask | ena_msk, ++ (div << core->layout->div_shift) | ena_val); ++ ++ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, ++ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, ++ AT91_PMC_PLL_UPDT_UPDATE | core->id); ++ ++ while (!sam9x60_pll_ready(regmap, core->id)) ++ cpu_relax(); ++} ++ + static int sam9x60_div_pll_set(struct sam9x60_pll_core *core) + { + struct sam9x60_div *div = to_sam9x60_div(core); +@@ -346,17 +370,7 @@ static int sam9x60_div_pll_set(struct sa + if (!!(val & core->layout->endiv_mask) && cdiv == div->div) + goto unlock; + +- regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, +- core->layout->div_mask | core->layout->endiv_mask, +- (div->div << core->layout->div_shift) | +- (1 << core->layout->endiv_shift)); +- +- regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, +- AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, +- AT91_PMC_PLL_UPDT_UPDATE | core->id); +- +- while (!sam9x60_pll_ready(regmap, core->id)) +- cpu_relax(); ++ sam9x60_div_pll_set_div(core, div->div, 1); + + unlock: + spin_unlock_irqrestore(core->lock, flags); +@@ -502,16 +516,7 @@ static int sam9x60_div_pll_set_rate_chg( + if (cdiv == div->div) + goto unlock; + +- regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, +- core->layout->div_mask, +- (div->div << core->layout->div_shift)); +- +- regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, +- AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, +- AT91_PMC_PLL_UPDT_UPDATE | core->id); +- +- while (!sam9x60_pll_ready(regmap, core->id)) +- cpu_relax(); ++ sam9x60_div_pll_set_div(core, div->div, 0); + + unlock: + spin_unlock_irqrestore(core->lock, irqflags); +@@ -538,6 +543,48 @@ static void sam9x60_div_pll_restore_cont + sam9x60_div_pll_set(core); + } + ++static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier, ++ unsigned long code, void *data) ++{ ++ struct sam9x60_div *div = notifier_div; ++ struct sam9x60_pll_core core = div->core; ++ struct regmap *regmap = core.regmap; ++ unsigned long irqflags; ++ u32 val, cdiv; ++ int ret = NOTIFY_DONE; ++ ++ if (code != PRE_RATE_CHANGE) ++ return ret; ++ ++ /* ++ * We switch to safe divider to avoid overclocking of other domains ++ * feed by us while the frac PLL (our parent) is changed. ++ */ ++ div->div = div->safe_div; ++ ++ spin_lock_irqsave(core.lock, irqflags); ++ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, ++ core.id); ++ regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); ++ cdiv = (val & core.layout->div_mask) >> core.layout->div_shift; ++ ++ /* Stop if nothing changed. */ ++ if (cdiv == div->safe_div) ++ goto unlock; ++ ++ sam9x60_div_pll_set_div(&core, div->div, 0); ++ ret = NOTIFY_OK; ++ ++unlock: ++ spin_unlock_irqrestore(core.lock, irqflags); ++ ++ return ret; ++} ++ ++static struct notifier_block sam9x60_div_pll_notifier = { ++ .notifier_call = sam9x60_div_pll_notifier_fn, ++}; ++ + static const struct clk_ops sam9x60_div_pll_ops = { + .prepare = sam9x60_div_pll_prepare, + .unprepare = sam9x60_div_pll_unprepare, +@@ -647,7 +694,8 @@ struct clk_hw * __init + sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, + const char *name, const char *parent_name, u8 id, + const struct clk_pll_characteristics *characteristics, +- const struct clk_pll_layout *layout, u32 flags) ++ const struct clk_pll_layout *layout, u32 flags, ++ u32 safe_div) + { + struct sam9x60_div *div; + struct clk_hw *hw; +@@ -656,9 +704,13 @@ sam9x60_clk_register_div_pll(struct regm + unsigned int val; + int ret; + +- if (id > PLL_MAX_ID || !lock) ++ /* We only support one changeable PLL. */ ++ if (id > PLL_MAX_ID || !lock || (safe_div && notifier_div)) + return ERR_PTR(-EINVAL); + ++ if (safe_div >= PLL_DIV_MAX) ++ safe_div = PLL_DIV_MAX - 1; ++ + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); +@@ -678,6 +730,7 @@ sam9x60_clk_register_div_pll(struct regm + div->core.layout = layout; + div->core.regmap = regmap; + div->core.lock = lock; ++ div->safe_div = safe_div; + + spin_lock_irqsave(div->core.lock, irqflags); + +@@ -693,6 +746,9 @@ sam9x60_clk_register_div_pll(struct regm + if (ret) { + kfree(div); + hw = ERR_PTR(ret); ++ } else if (div->safe_div) { ++ notifier_div = div; ++ clk_notifier_register(hw->clk, &sam9x60_div_pll_notifier); + } + + return hw; +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -214,7 +214,8 @@ struct clk_hw * __init + sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, + const char *name, const char *parent_name, u8 id, + const struct clk_pll_characteristics *characteristics, +- const struct clk_pll_layout *layout, u32 flags); ++ const struct clk_pll_layout *layout, u32 flags, ++ u32 safe_div); + + struct clk_hw * __init + sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, +--- a/drivers/clk/at91/sam9x60.c ++++ b/drivers/clk/at91/sam9x60.c +@@ -242,7 +242,7 @@ static void __init sam9x60_pmc_setup(str + * This feeds CPU. It should not + * be disabled. + */ +- CLK_IS_CRITICAL | CLK_SET_RATE_GATE); ++ CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +@@ -260,7 +260,7 @@ static void __init sam9x60_pmc_setup(str + &pll_div_layout, + CLK_SET_RATE_GATE | + CLK_SET_PARENT_GATE | +- CLK_SET_RATE_PARENT); ++ CLK_SET_RATE_PARENT, 0); + if (IS_ERR(hw)) + goto err_free; + +@@ -279,7 +279,7 @@ static void __init sam9x60_pmc_setup(str + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", &sam9x60_master_layout, + &mck_characteristics, &mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -127,6 +127,8 @@ static const struct clk_pll_characterist + * @t: clock type + * @f: clock flags + * @eid: export index in sama7g5->chws[] array ++ * @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE ++ * notification + */ + static const struct { + const char *n; +@@ -136,6 +138,7 @@ static const struct { + unsigned long f; + u8 t; + u8 eid; ++ u8 safe_div; + } sama7g5_plls[][PLL_ID_MAX] = { + [PLL_ID_CPU] = { + { .n = "cpupll_fracck", +@@ -156,7 +159,12 @@ static const struct { + .t = PLL_TYPE_DIV, + /* This feeds CPU. It should not be disabled. */ + .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, +- .eid = PMC_CPUPLL, }, ++ .eid = PMC_CPUPLL, ++ /* ++ * Safe div=15 should be safe even for switching b/w 1GHz and ++ * 90MHz (frac pll might go up to 1.2GHz). ++ */ ++ .safe_div = 15, }, + }, + + [PLL_ID_SYS] = { +@@ -967,7 +975,8 @@ static void __init sama7g5_pmc_setup(str + sama7g5_plls[i][j].p, i, + sama7g5_plls[i][j].c, + sama7g5_plls[i][j].l, +- sama7g5_plls[i][j].f); ++ sama7g5_plls[i][j].f, ++ sama7g5_plls[i][j].safe_div); + break; + + default: diff --git a/target/linux/at91/patches-5.15/244-clk-at91-clk-master-add-notifier-for-divider.patch b/target/linux/at91/patches-5.15/244-clk-at91-clk-master-add-notifier-for-divider.patch new file mode 100644 index 0000000000..35262db6cb --- /dev/null +++ b/target/linux/at91/patches-5.15/244-clk-at91-clk-master-add-notifier-for-divider.patch @@ -0,0 +1,519 @@ +From 75d5d1d584ae73ba0c36d1d7255db6153ca4d3f3 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:16 +0300 +Subject: [PATCH 244/247] clk: at91: clk-master: add notifier for divider + +SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same +parent with cpuck as seen in the following clock tree: + + +----------> cpuck + | +FRAC PLL ---> DIV PLL -+-> DIV ---> mck0 + +mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking +while changing FRAC PLL or DIV PLL the commit implements a notifier for +mck0 which applies a safe divider to register (maximum value of the divider +which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not +overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE +events. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/at91rm9200.c | 2 +- + drivers/clk/at91/at91sam9260.c | 2 +- + drivers/clk/at91/at91sam9g45.c | 2 +- + drivers/clk/at91/at91sam9n12.c | 2 +- + drivers/clk/at91/at91sam9rl.c | 2 +- + drivers/clk/at91/at91sam9x5.c | 2 +- + drivers/clk/at91/clk-master.c | 244 +++++++++++++++++++++++---------- + drivers/clk/at91/dt-compat.c | 2 +- + drivers/clk/at91/pmc.h | 2 +- + drivers/clk/at91/sama5d2.c | 2 +- + drivers/clk/at91/sama5d3.c | 2 +- + drivers/clk/at91/sama5d4.c | 2 +- + drivers/clk/at91/sama7g5.c | 2 +- + 13 files changed, 186 insertions(+), 82 deletions(-) + +--- a/drivers/clk/at91/at91rm9200.c ++++ b/drivers/clk/at91/at91rm9200.c +@@ -152,7 +152,7 @@ static void __init at91rm9200_pmc_setup( + "masterck_pres", + &at91rm9200_master_layout, + &rm9200_mck_characteristics, +- &rm9200_mck_lock, CLK_SET_RATE_GATE); ++ &rm9200_mck_lock, CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/at91sam9260.c ++++ b/drivers/clk/at91/at91sam9260.c +@@ -429,7 +429,7 @@ static void __init at91sam926x_pmc_setup + &at91rm9200_master_layout, + data->mck_characteristics, + &at91sam9260_mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/at91sam9g45.c ++++ b/drivers/clk/at91/at91sam9g45.c +@@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup + &at91rm9200_master_layout, + &mck_characteristics, + &at91sam9g45_mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/at91sam9n12.c ++++ b/drivers/clk/at91/at91sam9n12.c +@@ -191,7 +191,7 @@ static void __init at91sam9n12_pmc_setup + &at91sam9x5_master_layout, + &mck_characteristics, + &at91sam9n12_mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/at91sam9rl.c ++++ b/drivers/clk/at91/at91sam9rl.c +@@ -132,7 +132,7 @@ static void __init at91sam9rl_pmc_setup( + "masterck_pres", + &at91rm9200_master_layout, + &sam9rl_mck_characteristics, +- &sam9rl_mck_lock, CLK_SET_RATE_GATE); ++ &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/at91sam9x5.c ++++ b/drivers/clk/at91/at91sam9x5.c +@@ -210,7 +210,7 @@ static void __init at91sam9x5_pmc_setup( + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -5,6 +5,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -36,8 +37,12 @@ struct clk_master { + u8 id; + u8 parent; + u8 div; ++ u32 safe_div; + }; + ++/* MCK div reference to be used by notifier. */ ++static struct clk_master *master_div; ++ + static inline bool clk_master_ready(struct clk_master *master) + { + unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY; +@@ -153,107 +158,81 @@ static const struct clk_ops master_div_o + .restore_context = clk_master_div_restore_context, + }; + +-static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, +- unsigned long parent_rate) ++/* This function must be called with lock acquired. */ ++static int clk_master_div_set(struct clk_master *master, ++ unsigned long parent_rate, int div) + { +- struct clk_master *master = to_clk_master(hw); + const struct clk_master_characteristics *characteristics = + master->characteristics; +- unsigned long flags; +- unsigned int mckr, tmp; +- int div, i; ++ unsigned long rate = parent_rate; ++ unsigned int max_div = 0, div_index = 0, max_div_index = 0; ++ unsigned int i, mckr, tmp; + int ret; + +- div = DIV_ROUND_CLOSEST(parent_rate, rate); +- if (div > ARRAY_SIZE(characteristics->divisors)) +- return -EINVAL; +- + for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { + if (!characteristics->divisors[i]) + break; + +- if (div == characteristics->divisors[i]) { +- div = i; +- break; ++ if (div == characteristics->divisors[i]) ++ div_index = i; ++ ++ if (max_div < characteristics->divisors[i]) { ++ max_div = characteristics->divisors[i]; ++ max_div_index = i; + } + } + +- if (i == ARRAY_SIZE(characteristics->divisors)) +- return -EINVAL; ++ if (div > max_div) ++ div_index = max_div_index; + +- spin_lock_irqsave(master->lock, flags); + ret = regmap_read(master->regmap, master->layout->offset, &mckr); + if (ret) +- goto unlock; ++ return ret; + + mckr &= master->layout->mask; + tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; +- if (tmp == div) +- goto unlock; ++ if (tmp == div_index) ++ return 0; ++ ++ rate /= characteristics->divisors[div_index]; ++ if (rate < characteristics->output.min) ++ pr_warn("master clk div is underclocked"); ++ else if (rate > characteristics->output.max) ++ pr_warn("master clk div is overclocked"); + + mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT); +- mckr |= (div << MASTER_DIV_SHIFT); ++ mckr |= (div_index << MASTER_DIV_SHIFT); + ret = regmap_write(master->regmap, master->layout->offset, mckr); + if (ret) +- goto unlock; ++ return ret; + + while (!clk_master_ready(master)) + cpu_relax(); +-unlock: +- spin_unlock_irqrestore(master->lock, flags); ++ ++ master->div = characteristics->divisors[div_index]; + + return 0; + } + +-static int clk_master_div_determine_rate(struct clk_hw *hw, +- struct clk_rate_request *req) ++static unsigned long clk_master_div_recalc_rate_chg(struct clk_hw *hw, ++ unsigned long parent_rate) + { + struct clk_master *master = to_clk_master(hw); +- const struct clk_master_characteristics *characteristics = +- master->characteristics; +- struct clk_hw *parent; +- unsigned long parent_rate, tmp_rate, best_rate = 0; +- int i, best_diff = INT_MIN, tmp_diff; +- +- parent = clk_hw_get_parent(hw); +- if (!parent) +- return -EINVAL; +- +- parent_rate = clk_hw_get_rate(parent); +- if (!parent_rate) +- return -EINVAL; + +- for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { +- if (!characteristics->divisors[i]) +- break; +- +- tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate, +- characteristics->divisors[i]); +- tmp_diff = abs(tmp_rate - req->rate); +- +- if (!best_rate || best_diff > tmp_diff) { +- best_diff = tmp_diff; +- best_rate = tmp_rate; +- } +- +- if (!best_diff) +- break; +- } +- +- req->best_parent_rate = best_rate; +- req->best_parent_hw = parent; +- req->rate = best_rate; +- +- return 0; ++ return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div); + } + + static void clk_master_div_restore_context_chg(struct clk_hw *hw) + { + struct clk_master *master = to_clk_master(hw); ++ unsigned long flags; + int ret; + +- ret = clk_master_div_set_rate(hw, master->pms.rate, +- master->pms.parent_rate); ++ spin_lock_irqsave(master->lock, flags); ++ ret = clk_master_div_set(master, master->pms.parent_rate, ++ DIV_ROUND_CLOSEST(master->pms.parent_rate, ++ master->pms.rate)); ++ spin_unlock_irqrestore(master->lock, flags); + if (ret) + pr_warn("Failed to restore MCK DIV clock\n"); + } +@@ -261,13 +240,116 @@ static void clk_master_div_restore_conte + static const struct clk_ops master_div_ops_chg = { + .prepare = clk_master_prepare, + .is_prepared = clk_master_is_prepared, +- .recalc_rate = clk_master_div_recalc_rate, +- .determine_rate = clk_master_div_determine_rate, +- .set_rate = clk_master_div_set_rate, ++ .recalc_rate = clk_master_div_recalc_rate_chg, + .save_context = clk_master_div_save_context, + .restore_context = clk_master_div_restore_context_chg, + }; + ++static int clk_master_div_notifier_fn(struct notifier_block *notifier, ++ unsigned long code, void *data) ++{ ++ const struct clk_master_characteristics *characteristics = ++ master_div->characteristics; ++ struct clk_notifier_data *cnd = data; ++ unsigned long flags, new_parent_rate, new_rate; ++ unsigned int mckr, div, new_div = 0; ++ int ret, i; ++ long tmp_diff; ++ long best_diff = -1; ++ ++ spin_lock_irqsave(master_div->lock, flags); ++ switch (code) { ++ case PRE_RATE_CHANGE: ++ /* ++ * We want to avoid any overclocking of MCK DIV domain. To do ++ * this we set a safe divider (the underclocking is not of ++ * interest as we can go as low as 32KHz). The relation ++ * b/w this clock and its parents are as follows: ++ * ++ * FRAC PLL -> DIV PLL -> MCK DIV ++ * ++ * With the proper safe divider we should be good even with FRAC ++ * PLL at its maximum value. ++ */ ++ ret = regmap_read(master_div->regmap, master_div->layout->offset, ++ &mckr); ++ if (ret) { ++ ret = NOTIFY_STOP_MASK; ++ goto unlock; ++ } ++ ++ mckr &= master_div->layout->mask; ++ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ ++ /* Switch to safe divider. */ ++ clk_master_div_set(master_div, ++ cnd->old_rate * characteristics->divisors[div], ++ master_div->safe_div); ++ break; ++ ++ case POST_RATE_CHANGE: ++ /* ++ * At this point we want to restore MCK DIV domain to its maximum ++ * allowed rate. ++ */ ++ ret = regmap_read(master_div->regmap, master_div->layout->offset, ++ &mckr); ++ if (ret) { ++ ret = NOTIFY_STOP_MASK; ++ goto unlock; ++ } ++ ++ mckr &= master_div->layout->mask; ++ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ new_parent_rate = cnd->new_rate * characteristics->divisors[div]; ++ ++ for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { ++ if (!characteristics->divisors[i]) ++ break; ++ ++ new_rate = DIV_ROUND_CLOSEST_ULL(new_parent_rate, ++ characteristics->divisors[i]); ++ ++ tmp_diff = characteristics->output.max - new_rate; ++ if (tmp_diff < 0) ++ continue; ++ ++ if (best_diff < 0 || best_diff > tmp_diff) { ++ new_div = characteristics->divisors[i]; ++ best_diff = tmp_diff; ++ } ++ ++ if (!tmp_diff) ++ break; ++ } ++ ++ if (!new_div) { ++ ret = NOTIFY_STOP_MASK; ++ goto unlock; ++ } ++ ++ /* Update the div to preserve MCK DIV clock rate. */ ++ clk_master_div_set(master_div, new_parent_rate, ++ new_div); ++ ++ ret = NOTIFY_OK; ++ break; ++ ++ default: ++ ret = NOTIFY_DONE; ++ break; ++ } ++ ++unlock: ++ spin_unlock_irqrestore(master_div->lock, flags); ++ ++ return ret; ++} ++ ++static struct notifier_block clk_master_div_notifier = { ++ .notifier_call = clk_master_div_notifier_fn, ++}; ++ + static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, + struct clk_hw *parent, + unsigned long parent_rate, +@@ -496,6 +578,8 @@ at91_clk_register_master_internal(struct + struct clk_master *master; + struct clk_init_data init; + struct clk_hw *hw; ++ unsigned int mckr; ++ unsigned long irqflags; + int ret; + + if (!name || !num_parents || !parent_names || !lock) +@@ -518,6 +602,16 @@ at91_clk_register_master_internal(struct + master->chg_pid = chg_pid; + master->lock = lock; + ++ if (ops == &master_div_ops_chg) { ++ spin_lock_irqsave(master->lock, irqflags); ++ regmap_read(master->regmap, master->layout->offset, &mckr); ++ spin_unlock_irqrestore(master->lock, irqflags); ++ ++ mckr &= layout->mask; ++ mckr = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ master->div = characteristics->divisors[mckr]; ++ } ++ + hw = &master->hw; + ret = clk_hw_register(NULL, &master->hw); + if (ret) { +@@ -554,19 +648,29 @@ at91_clk_register_master_div(struct regm + const char *name, const char *parent_name, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics, +- spinlock_t *lock, u32 flags) ++ spinlock_t *lock, u32 flags, u32 safe_div) + { + const struct clk_ops *ops; ++ struct clk_hw *hw; + + if (flags & CLK_SET_RATE_GATE) + ops = &master_div_ops; + else + ops = &master_div_ops_chg; + +- return at91_clk_register_master_internal(regmap, name, 1, +- &parent_name, layout, +- characteristics, ops, +- lock, flags, -EINVAL); ++ hw = at91_clk_register_master_internal(regmap, name, 1, ++ &parent_name, layout, ++ characteristics, ops, ++ lock, flags, -EINVAL); ++ ++ if (!IS_ERR(hw) && safe_div) { ++ master_div = to_clk_master(hw); ++ master_div->safe_div = safe_div; ++ clk_notifier_register(hw->clk, ++ &clk_master_div_notifier); ++ } ++ ++ return hw; + } + + static unsigned long +--- a/drivers/clk/at91/dt-compat.c ++++ b/drivers/clk/at91/dt-compat.c +@@ -399,7 +399,7 @@ of_at91_clk_master_setup(struct device_n + + hw = at91_clk_register_master_div(regmap, name, "masterck_pres", + layout, characteristics, +- &mck_lock, CLK_SET_RATE_GATE); ++ &mck_lock, CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto out_free_characteristics; + +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -182,7 +182,7 @@ at91_clk_register_master_div(struct regm + const char *parent_names, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics, +- spinlock_t *lock, u32 flags); ++ spinlock_t *lock, u32 flags, u32 safe_div); + + struct clk_hw * __init + at91_clk_sama7g5_register_master(struct regmap *regmap, +--- a/drivers/clk/at91/sama5d2.c ++++ b/drivers/clk/at91/sama5d2.c +@@ -249,7 +249,7 @@ static void __init sama5d2_pmc_setup(str + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/sama5d3.c ++++ b/drivers/clk/at91/sama5d3.c +@@ -184,7 +184,7 @@ static void __init sama5d3_pmc_setup(str + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/sama5d4.c ++++ b/drivers/clk/at91/sama5d4.c +@@ -199,7 +199,7 @@ static void __init sama5d4_pmc_setup(str + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, +- CLK_SET_RATE_GATE); ++ CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -1003,7 +1003,7 @@ static void __init sama7g5_pmc_setup(str + + hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", + &mck0_layout, &mck0_characteristics, +- &pmc_mck0_lock, 0); ++ &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); + if (IS_ERR(hw)) + goto err_free; + diff --git a/target/linux/at91/patches-5.15/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch b/target/linux/at91/patches-5.15/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch new file mode 100644 index 0000000000..1ae5076da9 --- /dev/null +++ b/target/linux/at91/patches-5.15/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch @@ -0,0 +1,45 @@ +From 91a49481af7332853c4c921d46aded8210572210 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:17 +0300 +Subject: [PATCH 245/247] clk: at91: sama7g5: remove prescaler part of master + clock + +On SAMA7G5 the prescaler part of master clock has been implemented as a +changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit +must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is +done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has +been discovered that in some conditions the PMC_SR.MCKRDY is not rising +but the rate it provides it's stable. The workaround is to add a timeout +when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler +will be removed from Linux clock tree as all the frequencies for CPU could +be obtained from PLL and also there will be less overhead when changing +frequency via DVFS. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-14-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 11 +---------- + 1 file changed, 1 insertion(+), 10 deletions(-) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -992,16 +992,7 @@ static void __init sama7g5_pmc_setup(str + } + + parent_names[0] = "cpupll_divpmcck"; +- hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names, +- &mck0_layout, &mck0_characteristics, +- &pmc_mck0_lock, +- CLK_SET_RATE_PARENT, 0); +- if (IS_ERR(hw)) +- goto err_free; +- +- sama7g5_pmc->chws[PMC_CPU] = hw; +- +- hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", ++ hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck", + &mck0_layout, &mck0_characteristics, + &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); + if (IS_ERR(hw)) diff --git a/target/linux/at91/patches-5.15/246-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch b/target/linux/at91/patches-5.15/246-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch new file mode 100644 index 0000000000..922cf0b69c --- /dev/null +++ b/target/linux/at91/patches-5.15/246-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch @@ -0,0 +1,26 @@ +From 9fd5a49f6da9de5da83f4a53eccefad647ab15ed Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:18 +0300 +Subject: [PATCH 246/247] clk: at91: sama7g5: set low limit for mck0 at 32KHz + +MCK0 could go as low as 32KHz. Set this limit. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-15-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +Signed-off-by: Stephen Boyd +--- + drivers/clk/at91/sama7g5.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -850,7 +850,7 @@ static const struct { + + /* MCK0 characteristics. */ + static const struct clk_master_characteristics mck0_characteristics = { +- .output = { .min = 50000000, .max = 200000000 }, ++ .output = { .min = 32768, .max = 200000000 }, + .divisors = { 1, 2, 4, 3, 5 }, + .have_div3_pres = 1, + }; diff --git a/target/linux/at91/patches-5.15/247-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch b/target/linux/at91/patches-5.15/247-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch new file mode 100644 index 0000000000..6751edec5c --- /dev/null +++ b/target/linux/at91/patches-5.15/247-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch @@ -0,0 +1,32 @@ +From fe07791494a78d5a4be1363385e6ba7940740644 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Mon, 11 Oct 2021 14:27:19 +0300 +Subject: [PATCH 247/247] clk: use clk_core_get_rate_recalc() in clk_rate_get() + +In case clock flags contains CLK_GET_RATE_NOCACHE the clk_rate_get() +will return the cached rate. Thus, use clk_core_get_rate_recalc() which +takes proper action when clock flags contains CLK_GET_RATE_NOCACHE. + +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20211011112719.3951784-16-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre +[sboyd@kernel.org: Grab prepare lock around operation] +Signed-off-by: Stephen Boyd +--- + drivers/clk/clk.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -3105,7 +3105,10 @@ static int clk_rate_get(void *data, u64 + { + struct clk_core *core = data; + +- *val = core->rate; ++ clk_prepare_lock(); ++ *val = clk_core_get_rate_recalc(core); ++ clk_prepare_unlock(); ++ + return 0; + } + diff --git a/target/linux/at91/patches-5.15/99-scripts-fix-compilation-error.patch b/target/linux/at91/patches-5.15/99-scripts-fix-compilation-error.patch new file mode 100644 index 0000000000..711c7dfbcc --- /dev/null +++ b/target/linux/at91/patches-5.15/99-scripts-fix-compilation-error.patch @@ -0,0 +1,21 @@ +From 6d18eaaaff92f928eab6fad2708b6d28785b4872 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Wed, 13 Oct 2021 08:32:07 +0300 +Subject: [PATCH] scripts: fix compilation error + +Signed-off-by: Claudiu Beznea +--- + scripts/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/scripts/Makefile ++++ b/scripts/Makefile +@@ -21,7 +21,7 @@ HOSTCFLAGS_asn1_compiler.o = -I$(srctree + HOSTCFLAGS_sign-file.o = $(CRYPTO_CFLAGS) + HOSTLDLIBS_sign-file = $(CRYPTO_LIBS) + HOSTCFLAGS_extract-cert.o = $(CRYPTO_CFLAGS) +-HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS) ++HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS) -lpthread + + ifdef CONFIG_UNWINDER_ORC + ifeq ($(ARCH),x86_64) diff --git a/target/linux/at91/sam9x/config-default b/target/linux/at91/sam9x/config-5.10 similarity index 100% rename from target/linux/at91/sam9x/config-default rename to target/linux/at91/sam9x/config-5.10 diff --git a/target/linux/at91/sam9x/config-5.15 b/target/linux/at91/sam9x/config-5.15 new file mode 100644 index 0000000000..609e182905 --- /dev/null +++ b/target/linux/at91/sam9x/config-5.15 @@ -0,0 +1,315 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_AT91=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_V4 is not set +CONFIG_ARCH_MULTI_V4T=y +CONFIG_ARCH_MULTI_V4_V5=y +CONFIG_ARCH_MULTI_V5=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +# CONFIG_ASN1 is not set +# CONFIG_AT91RM9200_WATCHDOG is not set +CONFIG_AT91SAM9X_WATCHDOG=y +# CONFIG_AT91_ADC is not set +CONFIG_AT91_SAMA5D2_ADC=y +CONFIG_AT91_SOC_ID=y +# CONFIG_AT91_SOC_SFR is not set +CONFIG_ATMEL_AIC5_IRQ=y +CONFIG_ATMEL_AIC_IRQ=y +CONFIG_ATMEL_CLOCKSOURCE_PIT=y +CONFIG_ATMEL_CLOCKSOURCE_TCB=y +CONFIG_ATMEL_EBI=y +CONFIG_ATMEL_PIT=y +CONFIG_ATMEL_PM=y +CONFIG_ATMEL_SDRAMC=y +CONFIG_ATMEL_SSC=y +CONFIG_ATMEL_ST=y +CONFIG_ATMEL_TCB_CLKSRC=y +CONFIG_ATMEL_TCLIB=y +CONFIG_AT_HDMAC=y +CONFIG_AT_XDMAC=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_PM=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_AT91=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CPU_32v4T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_ARM920T=y +CONFIG_CPU_ARM926T=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_CPU_CACHE_V4WT=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +CONFIG_CPU_NO_EFFICIENT_FFS=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_PM=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CRC16=y +CONFIG_CRC7=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_BLAKE2S=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DTC=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_EXT4_FS=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ATMEL=y +CONFIG_HZ=128 +CONFIG_HZ_FIXED=128 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_AT91=y +# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_GPIO=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACB=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MFD_AT91_USART=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_MFD_ATMEL_HLCDC=y +CONFIG_MFD_ATMEL_SMC=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MICROCHIP_PIT64B=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_AT91=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_OTP is not set +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_GLUEBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NLS=y +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +# CONFIG_PINCTRL_AT91PIO4 is not set +CONFIG_PINCTRL_MCP23S08=y +CONFIG_PINCTRL_MCP23S08_I2C=y +CONFIG_PINCTRL_MCP23S08_SPI=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_SLEEP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_AT91_POWEROFF=y +CONFIG_POWER_RESET_AT91_RESET=y +CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y +CONFIG_POWER_SUPPLY=y +CONFIG_PWM=y +CONFIG_PWM_ATMEL=y +CONFIG_PWM_ATMEL_HLCDC_PWM=y +CONFIG_PWM_ATMEL_TCB=y +CONFIG_PWM_SYSFS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +CONFIG_RTC_DRV_AT91SAM9=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_SAMA5D4_WATCHDOG=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SGL_ALLOC=y +CONFIG_SOC_AT91RM9200=y +CONFIG_SOC_AT91SAM9=y +CONFIG_SOC_BUS=y +CONFIG_SOC_SAM9X60=y +CONFIG_SOC_SAM_V4_V5=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_AT91_USART is not set +CONFIG_SPI_ATMEL=y +CONFIG_SPI_ATMEL_QUADSPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +CONFIG_SRCU=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWPHY=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_ACM=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +# CONFIG_USB_AT91 is not set +# CONFIG_USB_ATMEL_USBA is not set +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_AT91=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_GADGET=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_AT91=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +# CONFIG_VFP is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_XXHASH=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/at91/sama5/config-default b/target/linux/at91/sama5/config-5.10 similarity index 100% rename from target/linux/at91/sama5/config-default rename to target/linux/at91/sama5/config-5.10 diff --git a/target/linux/at91/sama5/config-5.15 b/target/linux/at91/sama5/config-5.15 new file mode 100644 index 0000000000..e7478cf5c7 --- /dev/null +++ b/target/linux/at91/sama5/config-5.15 @@ -0,0 +1,487 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_AT91=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_AT91_CPUIDLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +# CONFIG_ASN1 is not set +CONFIG_AT91SAM9X_WATCHDOG=y +CONFIG_AT91_ADC=y +CONFIG_AT91_SAMA5D2_ADC=y +CONFIG_AT91_SOC_ID=y +# CONFIG_AT91_SOC_SFR is not set +CONFIG_ATMEL_AIC5_IRQ=y +# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set +CONFIG_ATMEL_CLOCKSOURCE_TCB=y +CONFIG_ATMEL_EBI=y +CONFIG_ATMEL_PM=y +CONFIG_ATMEL_SDRAMC=y +CONFIG_ATMEL_SSC=y +CONFIG_ATMEL_TCB_CLKSRC=y +CONFIG_ATMEL_TCLIB=y +CONFIG_AT_HDMAC=y +CONFIG_AT_XDMAC=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BATTERY_ACT8945A=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_PM=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_CACHE_L2X0=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_AT91=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONTIG_ALLOC=y +CONFIG_COREDUMP=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRASH_CORE=y +CONFIG_CRASH_DUMP=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_BLAKE2S=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_USER=y +CONFIG_DMADEVICES=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DNOTIFY=y +CONFIG_DRM=y +CONFIG_DRM_ATMEL_HLCDC=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_KMS_CMA_HELPER=y +CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_BRIDGE=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DTC=y +CONFIG_DVB_CORE=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_ELF_CORE=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_EXT4_FS=y +CONFIG_FAT_FS=y +CONFIG_FB=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FORCE_MAX_ZONEORDER=15 +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HDMI=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ATMEL=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_AT91=y +# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +# CONFIG_JFFS2_FS is not set +CONFIG_KCMP=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_QT1070=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACB=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MANDATORY_FILE_LOCKING=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +CONFIG_MEDIA_TUNER=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MFD_ACT8945A=y +CONFIG_MFD_AT91_USART=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_MFD_ATMEL_HLCDC=y +CONFIG_MFD_ATMEL_SMC=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_AT91=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_NEON is not set +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_PINCTRL_AT91PIO4=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_SLEEP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_AT91_POWEROFF=y +CONFIG_POWER_RESET_AT91_RESET=y +CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y +CONFIG_POWER_SUPPLY=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_PRINTK_TIME=y +CONFIG_PROC_VMCORE=y +CONFIG_PWM=y +CONFIG_PWM_ATMEL=y +CONFIG_PWM_ATMEL_HLCDC_PWM=y +CONFIG_PWM_ATMEL_TCB=y +CONFIG_PWM_SYSFS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_ACT8865=y +CONFIG_REGULATOR_ACT8945A=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +# CONFIG_RTC_DRV_AT91SAM9 is not set +# CONFIG_RTC_DRV_CMOS is not set +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_SAMA5D4_WATCHDOG=y +CONFIG_SCSI=y +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SND=y +CONFIG_SND_ARM=y +# CONFIG_SND_AT73C213 is not set +# CONFIG_SND_AT91_SOC_SAM9G20_WM8731 is not set +# CONFIG_SND_AT91_SOC_SAM9X5_WM8731 is not set +CONFIG_SND_ATMEL_SOC=y +CONFIG_SND_ATMEL_SOC_CLASSD=y +CONFIG_SND_ATMEL_SOC_DMA=y +CONFIG_SND_ATMEL_SOC_I2S=y +CONFIG_SND_ATMEL_SOC_PDC=y +# CONFIG_SND_ATMEL_SOC_PDMIC is not set +CONFIG_SND_ATMEL_SOC_SSC=y +CONFIG_SND_ATMEL_SOC_SSC_DMA=y +# CONFIG_SND_ATMEL_SOC_SSC_PDC is not set +# CONFIG_SND_ATMEL_SOC_TSE850_PCM5142 is not set +CONFIG_SND_ATMEL_SOC_WM8904=y +# CONFIG_SND_COMPRESS_OFFLOAD is not set +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_MCHP_SOC_I2S_MCC is not set +# CONFIG_SND_MCHP_SOC_SPDIFRX is not set +# CONFIG_SND_MCHP_SOC_SPDIFTX is not set +CONFIG_SND_PCM=y +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_I2C_AND_SPI=y +CONFIG_SND_SOC_MIKROE_PROTO=y +# CONFIG_SND_SOC_PCM5102A is not set +CONFIG_SND_SOC_WM8731=y +CONFIG_SND_SOC_WM8904=y +CONFIG_SND_SPI=y +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_TIMER=y +CONFIG_SOC_BUS=y +CONFIG_SOC_SAMA5=y +CONFIG_SOC_SAMA5D2=y +CONFIG_SOC_SAMA5D3=y +CONFIG_SOC_SAMA5D4=y +# CONFIG_SOC_SAMA7G5 is not set +CONFIG_SOC_SAM_V7=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_AT91_USART is not set +CONFIG_SPI_ATMEL=y +CONFIG_SPI_ATMEL_QUADSPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SQUASHFS is not set +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +CONFIG_SRCU=y +# CONFIG_STANDALONE is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWPHY=y +# CONFIG_SWP_EMULATE is not set +CONFIG_SYNC_FILE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=y +CONFIG_TOUCHSCREEN_PROPERTIES=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_UBIFS_FS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_ACM=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +# CONFIG_USB_AT91 is not set +# CONFIG_USB_ATMEL_USBA is not set +# CONFIG_USB_AUDIO is not set +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_AT91=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_GADGET=y +CONFIG_USB_HID=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_AT91=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +# CONFIG_USB_PWC is not set +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VFAT_FS=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VIDEOMODE_HELPERS=y +# CONFIG_VIDEO_CPIA2 is not set +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XXHASH=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/at91/sama7/config-default b/target/linux/at91/sama7/config-5.10 similarity index 100% rename from target/linux/at91/sama7/config-default rename to target/linux/at91/sama7/config-5.10 diff --git a/target/linux/at91/sama7/config-5.15 b/target/linux/at91/sama7/config-5.15 new file mode 100644 index 0000000000..45568112e4 --- /dev/null +++ b/target/linux/at91/sama7/config-5.15 @@ -0,0 +1,395 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_AT91=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_PATCH_IDIV is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +# CONFIG_AT91SAM9X_WATCHDOG is not set +# CONFIG_AT91_ADC is not set +CONFIG_AT91_SAMA5D2_ADC=y +CONFIG_AT91_SOC_ID=y +# CONFIG_AT91_SOC_SFR is not set +CONFIG_ATMEL_CLOCKSOURCE_TCB=y +# CONFIG_ATMEL_EBI is not set +CONFIG_ATMEL_SDRAMC=y +CONFIG_ATMEL_TCB_CLKSRC=y +# CONFIG_ATMEL_TCLIB is not set +# CONFIG_AT_HDMAC is not set +CONFIG_AT_XDMAC=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_SCSI_REQUEST=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CAN=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=9 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=256 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk nocache ignore_loglevel" +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_AT91=y +# CONFIG_COMPACTION is not set +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTIG_ALLOC=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_SPECTRE=y +# CONFIG_CPU_SW_DOMAIN_PAN is not set +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_BLAKE2S=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SHA256=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_AT91_SAMA7G5_FLEXCOM3=y +CONFIG_DEBUG_AT91_UART=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/at91.S" +CONFIG_DEBUG_UART_PHYS=0xe1824200 +CONFIG_DEBUG_UART_VIRT=0xe0824200 +# CONFIG_DEBUG_UNCOMPRESS is not set +CONFIG_DEBUG_USER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMADEVICES=y +CONFIG_DMATEST=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EARLY_PRINTK=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +# CONFIG_EFI_PARTITION is not set +CONFIG_EXT4_FS=y +CONFIG_FANOTIFY=y +CONFIG_FAT_FS=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FORCE_MAX_ZONEORDER=15 +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GRACE_PERIOD=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_AT91=y +# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_CONFIGFS=y +# CONFIG_IIO_HRTIMER_TRIGGER is not set +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_SW_TRIGGER=y +# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_BOOTP is not set +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCKD=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_LSM="N" +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACB=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_MFD_AT91_USART=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MICROCHIP_PIT64B=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +# CONFIG_MMC_ATMELMCI is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_AT91=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NEON=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NFS_FS=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCCARD=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_PM_OPP=y +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_AT91_POWEROFF is not set +CONFIG_POWER_RESET_AT91_RESET=y +CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_PRINTK_TIME=y +CONFIG_PWM=y +CONFIG_PWM_ATMEL=y +CONFIG_PWM_SYSFS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MCP16502=y +CONFIG_ROOT_NFS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +CONFIG_RTC_DRV_AT91SAM9=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_SAMA5D4_WATCHDOG=y +CONFIG_SCSI=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SND=y +CONFIG_SND_ATMEL_SOC=y +# CONFIG_SND_ATMEL_SOC_CLASSD is not set +# CONFIG_SND_ATMEL_SOC_I2S is not set +# CONFIG_SND_ATMEL_SOC_PDMIC is not set +# CONFIG_SND_COMPRESS_OFFLOAD is not set +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_MCHP_SOC_I2S_MCC=y +CONFIG_SND_MCHP_SOC_SPDIFRX=y +CONFIG_SND_MCHP_SOC_SPDIFTX=y +CONFIG_SND_PCM=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_SIMPLE_CARD_UTILS=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_MIKROE_PROTO is not set +CONFIG_SND_SOC_PCM5102A=y +CONFIG_SND_SOC_SPDIF=y +CONFIG_SOC_BUS=y +# CONFIG_SOC_SAMA5D2 is not set +# CONFIG_SOC_SAMA5D3 is not set +# CONFIG_SOC_SAMA5D4 is not set +CONFIG_SOC_SAMA7=y +CONFIG_SOC_SAMA7G5=y +CONFIG_SOC_SAM_V7=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_AT91_USART is not set +CONFIG_SPI_ATMEL=y +# CONFIG_SPI_ATMEL_QUADSPI is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SRCU=y +CONFIG_STACKTRACE=y +# CONFIG_STANDALONE is not set +CONFIG_SUNRPC=y +# CONFIG_SWAP is not set +CONFIG_SWPHY=y +# CONFIG_SWP_EMULATE is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USE_OF=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VFAT_FS=y +CONFIG_VFP=y +CONFIG_VFPv3=y +# CONFIG_VIDEO_ATMEL_XISC is not set +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y From d0d7771262843bd72bc9ea5441ce73750fd872ff Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 15 Sep 2022 17:37:27 +0300 Subject: [PATCH 07/80] at91: kernel v5.15: remove upstreamed patches Remove patches that are now integrated in kernel v5.15. Signed-off-by: Claudiu Beznea --- ...t91-re-factor-clocks-suspend-resume.patch} | 0 .../101-ARM-at91-build-dtb-for-q5xr5.patch | 10 - ...ute-suspend-resume-only-for-backup-.patch} | 0 ...er-add-register-definition-for-sama.patch} | 0 ...s-clock-at91-add-sama7g5-pll-defines.patch | 65 - ...er-improve-readability-by-using-loc.patch} | 0 ...-allow-SYS-and-CPU-PLLs-to-be-export.patch | 41 - ...aster-add-5th-divisor-for-mck-master.patch | 42 - ...sama7g5-to-the-list-of-available-pm.patch} | 0 ...aster-mask-mckr-against-layout-mask.patch} | 2 +- ...-add-5th-divisor-for-mck0-layout-and.patch | 36 - ...x60-pll-add-notifier-for-div-part-o.patch} | 2 +- ...9x60-pll-allow-runtime-changes-for-p.patch | 510 ---- ...clk-master-add-notifier-for-divider.patch} | 6 +- ...-remove-mck0-from-parent-list-of-oth.patch | 196 -- ...5-decrease-lower-limit-for-MCK0-rate.patch | 30 - ...7g5-set-low-limit-for-mck0-at-32KHz.patch} | 2 +- ...-do-not-allow-cpu-pll-to-go-higher-t.patch | 221 -- ...ore_get_rate_recalc-in-clk_rate_get.patch} | 2 +- ...91-clk-master-re-factor-master-clock.patch | 1230 ---------- ...-clk-at91-sama7g5-register-cpu-clock.patch | 65 - ...91-Fix-the-declaration-of-the-clocks.patch | 181 -- ...ial-typo-fixes-in-the-file-sama7g5.c.patch | 45 - ...-remove-all-kernel-doc-kernel-doc-wa.patch | 90 - ...serio-bits-as-platform-configuration.patch | 179 -- ...capability-to-not-set-the-clock-rate.patch | 85 - ...-function-to-disable-all-macb-clocks.patch | 82 - ...-unprepare-clocks-in-case-of-failure.patch | 60 - ...dd-support-for-sama7g5-gem-interface.patch | 54 - ...d-support-for-sama7g5-emac-interface.patch | 39 - ...-ASoC-pcm5102a-Make-codec-selectable.patch | 28 - ...i2s-do-not-warn-if-muxclk-is-missing.patch | 30 - ...egulator-mcp16502-add-linear_min_sel.patch | 25 - ...02-adapt-for-get-set-on-other-regist.patch | 117 - ...-mcp16502-add-support-for-ramp-delay.patch | 141 -- ...02-remove-void-documentation-of-stru.patch | 27 - ...alidate-selector-against-linear_min_.patch | 64 - ...re-do-not-continue-if-selector-match.patch | 26 - ...eturn-zero-for-selectors-lower-than-.patch | 64 - ...02-lpm-pin-can-be-optional-on-some-p.patch | 30 - ...4-add-support-for-fewer-lines-on-las.patch | 70 - ...ac-adapt-perid-for-mem2mem-operation.patch | 50 - ...ac-add-support-for-sama7g5-based-at_.patch | 280 --- ...ac-add-AXI-priority-support-and-reco.patch | 113 - ...t-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch | 45 - ...0-SiP-types-added-to-soc-description.patch | 43 - .../137-drivers-soc-atmel-use-GENMASK.patch | 25 - ...l-fix-__initconst-should-be-placed-a.patch | 26 - ...l-add-per-soc-id-and-version-match-m.patch | 348 --- ...rs-soc-atmel-add-support-for-sama7g5.patch | 87 - ...oc-atmel-add-spdx-license-identifier.patch | 49 - ...drivers-soc-atmel-fix-type-for-same7.patch | 28 - ...ers-timer-microchip-pit64b-Add-clock.patch | 173 -- ...dc-Use-managed-DMA-buffer-allocation.patch | 135 -- ...-sama5d2_shdwc-add-support-for-sama7.patch | 141 -- ...-at91-pio4-add-support-for-slew-rate.patch | 121 - ...4-fix-Prefer-unsigned-int-to-bare-us.patch | 340 --- ...ault-usrio-config-to-default-gem-con.patch | 58 - ...-prototypes-to-mutually-included-hea.patch | 108 - ...p-i2s-mcc-Add-compatible-for-SAMA7G5.patch | 46 - ...c-Add-multi-channel-support-for-I2S-.patch | 113 - ...s-mcc-Add-support-to-select-TDM-pins.patch | 108 - ...-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch | 187 -- ...-at91-pio4-Fix-slew-rate-disablement.patch | 49 - ...-media-atmel-properly-get-pm_runtime.patch | 159 -- ...l-isc-Remove-redundant-assignment-to.patch | 32 - ...l-isc-specialize-gamma-table-into-pr.patch | 187 -- ...l-isc-specialize-driver-name-constan.patch | 70 - ...l-isc-add-checks-for-limiting-frame-.patch | 45 - ...l-isc-specialize-max-width-and-max-h.patch | 131 - ...a-atmel-atmel-isc-specialize-dma-cfg.patch | 60 - ...l-isc-extract-CSC-submodule-config-i.patch | 94 - ...l-isc-base-add-id-to-clock-debug-mes.patch | 28 - ...l-isc-create-register-offsets-struct.patch | 115 - ...l-isc-extract-CBC-submodule-config-i.patch | 80 - ...l-isc-add-CBC-to-the-reg-offsets-str.patch | 82 - ...l-isc-add-SUB422-and-SUB420-to-regis.patch | 80 - ...tmel-isc-add-RLP-to-register-offsets.patch | 74 - ...tmel-isc-add-HIS-to-register-offsets.patch | 99 - ...tmel-isc-add-DMA-to-register-offsets.patch | 110 - ...l-isc-add-support-for-version-regist.patch | 77 - ...l-isc-add-his_entry-to-register-offs.patch | 71 - ...l-isc-add-register-description-for-a.patch | 99 - ...l-isc-extend-pipeline-with-extra-mod.patch | 104 - ...l-isc-add-CC-initialization-function.patch | 83 - ...l-isc-create-product-specific-v4l2-c.patch | 86 - ...l-isc-create-callback-for-DPC-submod.patch | 75 - ...l-isc-create-callback-for-GAM-submod.patch | 75 - ...l-isc-create-callback-for-RLP-submod.patch | 95 - ...l-isc-move-the-formats-list-into-pro.patch | 440 ---- ...l-isc-create-an-adapt-pipeline-callb.patch | 89 - ...l-isc-regs-add-additional-fields-for.patch | 55 - ...l-isc-base-add-support-for-more-form.patch | 145 -- ...l-isc-sama5d2-remove-duplicate-defin.patch | 26 - ...-atmel-isc-add-microchip-xisc-driver.patch | 810 ------- ...186-ASoC-atmel-fix-shadowed-variable.patch | 48 - ...el-i2s-remove-useless-initialization.patch | 36 - ...-atmel-i2s-Set-symmetric-sample-bits.patch | 26 - ...a5d4_wdt-add-support-for-sama7g5-wdt.patch | 46 - ...tmel-fix-build-when-ISC-m-and-XISC-y.patch | 135 -- ...191-i2c-at91-remove-define-CONFIG_PM.patch | 76 - ...3x-add-support-for-96kHz-and-192kHz-.patch | 91 - ...el-atmel-sama5d2-isc-fix-YUYV-format.patch | 48 - ...ister-definition-for-sama7g5-s-maste.patch | 51 - .../195-ARM-at91-add-new-SoC-sama7g5.patch | 49 - ...bug-add-sama7g5-low-level-debug-uart.patch | 50 - ...-move-pm_bu-to-soc_pm-data-structure.patch | 87 - ...ove-the-setup-of-soc_pm.bu-suspended.patch | 55 - ...91-pm-document-at91_soc_pm-structure.patch | 31 - ...k-for-different-controllers-in-at91_.patch | 238 -- ...1-ARM-at91-pm-do-not-initialize-pdev.patch | 25 - ...2-ARM-at91-pm-use-r7-instead-of-tmp1.patch | 60 - ...d-push-and-pop-on-stack-while-memory.patch | 467 ---- ...NFIG_SOC_SAM9X60-CONFIG_HAVE_AT91_SA.patch | 36 - ...91-pm-add-support-for-waiting-MCK1.4.patch | 150 -- ...dd-sfrbu-registers-definitions-for-s.patch | 53 - ...-registers-definitions-for-sama7g5-s.patch | 99 - ...add-self-refresh-support-for-sama7g5.patch | 274 --- ...support-for-MCK1.4-save-restore-for-.patch | 165 -- ...support-for-2.5V-LDO-regulator-contr.patch | 79 - ...-at91-pm-wait-for-ddr-power-mode-off.patch | 28 - ...M-at91-pm-add-sama7g5-ddr-controller.patch | 40 - ...91-pm-add-sama7g5-ddr-phy-controller.patch | 94 - ...-ddr-phy-calibration-data-to-securam.patch | 151 -- ...-add-backup-mode-support-for-SAMA7G5.patch | 52 - .../216-ARM-at91-pm-add-sama7g5-s-pmc.patch | 36 - ...t91-sama7-introduce-sama7-SoC-family.patch | 63 - ...M-at91-pm-add-pm-support-for-SAMA7G5.patch | 96 - .../219-ARM-at91-pm-add-sama7g5-shdwc.patch | 24 - ...-add-defconfig-for-sama7-family-of-S.patch | 233 -- ...M-multi_v7_defconfig-add-sama7g5-SoC.patch | 33 - ...91-add-sama7g5-SoC-DT-and-sama7g5-ek.patch | 2154 ----------------- ...ot-panic-if-ram-controllers-are-not-.patch | 74 - ...dts-at91-sama7g5-add-ram-controllers.patch | 36 - ...RM-dts-at91-sama7g5-add-securam-node.patch | 34 - ...-ARM-dts-at91-sama7g5-add-shdwc-node.patch | 53 - .../227-ARM-dts-at91-sama7g5-add-chipid.patch | 28 - ...ch-backup-area-to-vbat-in-backup-mod.patch | 117 - ...a7g5ek-add-suspend-voltage-for-ddr3l.patch | 42 - ...roup-constants-and-addresses-loading.patch | 48 - ...oad-base-address-of-controllers-in-t.patch | 93 - ...a7g5ek-use-proper-slew-rate-settings.patch | 85 - ...a7g5ek-to-not-touch-slew-rate-for-SD.patch | 73 - ...ma7g5-add-securam-s-peripheral-clock.patch | 25 - ...-master-check-if-div-or-pres-is-zero.patch | 39 - ...-at91-clk-master-fix-prescaler-logic.patch | 29 - ...-remove-prescaler-part-of-master-clo.patch | 45 - .../99-scripts-fix-compilation-error.patch | 21 - 148 files changed, 7 insertions(+), 16660 deletions(-) rename target/linux/at91/patches-5.15/{234-clk-at91-re-factor-clocks-suspend-resume.patch => 100-clk-at91-re-factor-clocks-suspend-resume.patch} (100%) delete mode 100644 target/linux/at91/patches-5.15/101-ARM-at91-build-dtb-for-q5xr5.patch rename target/linux/at91/patches-5.15/{235-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch => 101-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch} (100%) rename target/linux/at91/patches-5.15/{237-clk-at91-clk-master-add-register-definition-for-sama.patch => 102-clk-at91-clk-master-add-register-definition-for-sama.patch} (100%) delete mode 100644 target/linux/at91/patches-5.15/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch rename target/linux/at91/patches-5.15/{238-clk-at91-clk-master-improve-readability-by-using-loc.patch => 103-clk-at91-clk-master-improve-readability-by-using-loc.patch} (100%) delete mode 100644 target/linux/at91/patches-5.15/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch delete mode 100644 target/linux/at91/patches-5.15/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch rename target/linux/at91/patches-5.15/{239-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch => 104-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch} (100%) rename target/linux/at91/patches-5.15/{241-clk-at91-clk-master-mask-mckr-against-layout-mask.patch => 105-clk-at91-clk-master-mask-mckr-against-layout-mask.patch} (96%) delete mode 100644 target/linux/at91/patches-5.15/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch rename target/linux/at91/patches-5.15/{243-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch => 106-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch} (99%) delete mode 100644 target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch rename target/linux/at91/patches-5.15/{244-clk-at91-clk-master-add-notifier-for-divider.patch => 107-clk-at91-clk-master-add-notifier-for-divider.patch} (98%) delete mode 100644 target/linux/at91/patches-5.15/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch delete mode 100644 target/linux/at91/patches-5.15/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch rename target/linux/at91/patches-5.15/{246-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch => 108-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch} (95%) delete mode 100644 target/linux/at91/patches-5.15/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch rename target/linux/at91/patches-5.15/{247-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch => 109-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch} (94%) delete mode 100644 target/linux/at91/patches-5.15/110-clk-at91-clk-master-re-factor-master-clock.patch delete mode 100644 target/linux/at91/patches-5.15/111-clk-at91-sama7g5-register-cpu-clock.patch delete mode 100644 target/linux/at91/patches-5.15/112-clk-at91-Fix-the-declaration-of-the-clocks.patch delete mode 100644 target/linux/at91/patches-5.15/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch delete mode 100644 target/linux/at91/patches-5.15/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch delete mode 100644 target/linux/at91/patches-5.15/115-net-macb-add-userio-bits-as-platform-configuration.patch delete mode 100644 target/linux/at91/patches-5.15/116-net-macb-add-capability-to-not-set-the-clock-rate.patch delete mode 100644 target/linux/at91/patches-5.15/117-net-macb-add-function-to-disable-all-macb-clocks.patch delete mode 100644 target/linux/at91/patches-5.15/118-net-macb-unprepare-clocks-in-case-of-failure.patch delete mode 100644 target/linux/at91/patches-5.15/119-net-macb-add-support-for-sama7g5-gem-interface.patch delete mode 100644 target/linux/at91/patches-5.15/120-net-macb-add-support-for-sama7g5-emac-interface.patch delete mode 100644 target/linux/at91/patches-5.15/121-ASoC-pcm5102a-Make-codec-selectable.patch delete mode 100644 target/linux/at91/patches-5.15/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch delete mode 100644 target/linux/at91/patches-5.15/123-regulator-mcp16502-add-linear_min_sel.patch delete mode 100644 target/linux/at91/patches-5.15/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch delete mode 100644 target/linux/at91/patches-5.15/125-regulator-mcp16502-add-support-for-ramp-delay.patch delete mode 100644 target/linux/at91/patches-5.15/126-regulator-mcp16502-remove-void-documentation-of-stru.patch delete mode 100644 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a/target/linux/at91/patches-5.15/101-ARM-at91-build-dtb-for-q5xr5.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -41,6 +41,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ - at91-kizboxmini-mb.dtb \ - at91-kizboxmini-rd.dtb \ - at91-smartkiz.dtb \ -+ at91-q5xr5.dtb \ - at91-wb45n.dtb \ - at91sam9g15ek.dtb \ - at91sam9g25-gardena-smart-gateway.dtb \ diff --git a/target/linux/at91/patches-5.15/235-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch b/target/linux/at91/patches-5.15/101-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch similarity index 100% rename from target/linux/at91/patches-5.15/235-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch rename to target/linux/at91/patches-5.15/101-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch diff --git a/target/linux/at91/patches-5.15/237-clk-at91-clk-master-add-register-definition-for-sama.patch b/target/linux/at91/patches-5.15/102-clk-at91-clk-master-add-register-definition-for-sama.patch similarity index 100% rename from target/linux/at91/patches-5.15/237-clk-at91-clk-master-add-register-definition-for-sama.patch rename to target/linux/at91/patches-5.15/102-clk-at91-clk-master-add-register-definition-for-sama.patch diff --git a/target/linux/at91/patches-5.15/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch b/target/linux/at91/patches-5.15/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch deleted file mode 100644 index e684e5d4db..0000000000 --- a/target/linux/at91/patches-5.15/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 44bb7c72cdd830f54fe18e730205f892d9cbfe39 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Thu, 19 Nov 2020 17:43:08 +0200 -Subject: [PATCH 102/247] dt-bindings: clock: at91: add sama7g5 pll defines - -Add SAMA7G5 specific PLL defines to be referenced in a phandle as a -PMC_TYPE_CORE clock. - -Suggested-by: Claudiu Beznea -Signed-off-by: Eugen Hristev -[claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c] -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-3-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 6 +++--- - include/dt-bindings/clock/at91.h | 10 ++++++++++ - 2 files changed, 13 insertions(+), 3 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -182,13 +182,13 @@ static const struct { - .p = "audiopll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -- .eid = PMC_I2S0_MUX, }, -+ .eid = PMC_AUDIOPMCPLL, }, - - { .n = "audiopll_diviock", - .p = "audiopll_fracck", - .l = &pll_layout_divio, - .t = PLL_TYPE_DIV, -- .eid = PMC_I2S1_MUX, }, -+ .eid = PMC_AUDIOIOPLL, }, - }, - - [PLL_ID_ETH] = { -@@ -835,7 +835,7 @@ static void __init sama7g5_pmc_setup(str - if (IS_ERR(regmap)) - return; - -- sama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1, -+ sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1, - nck(sama7g5_systemck), - nck(sama7g5_periphck), - nck(sama7g5_gck), 8); ---- a/include/dt-bindings/clock/at91.h -+++ b/include/dt-bindings/clock/at91.h -@@ -25,6 +25,16 @@ - #define PMC_PLLBCK 8 - #define PMC_AUDIOPLLCK 9 - -+/* SAMA7G5 */ -+#define PMC_CPUPLL (PMC_MAIN + 1) -+#define PMC_SYSPLL (PMC_MAIN + 2) -+#define PMC_DDRPLL (PMC_MAIN + 3) -+#define PMC_IMGPLL (PMC_MAIN + 4) -+#define PMC_BAUDPLL (PMC_MAIN + 5) -+#define PMC_AUDIOPMCPLL (PMC_MAIN + 6) -+#define PMC_AUDIOIOPLL (PMC_MAIN + 7) -+#define PMC_ETHPLL (PMC_MAIN + 8) -+ - #ifndef AT91_PMC_MOSCS - #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ - #define AT91_PMC_LOCKA 1 /* PLLA Lock */ diff --git a/target/linux/at91/patches-5.15/238-clk-at91-clk-master-improve-readability-by-using-loc.patch b/target/linux/at91/patches-5.15/103-clk-at91-clk-master-improve-readability-by-using-loc.patch similarity index 100% rename from target/linux/at91/patches-5.15/238-clk-at91-clk-master-improve-readability-by-using-loc.patch rename to target/linux/at91/patches-5.15/103-clk-at91-clk-master-improve-readability-by-using-loc.patch diff --git a/target/linux/at91/patches-5.15/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch b/target/linux/at91/patches-5.15/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch deleted file mode 100644 index cd50dee6e1..0000000000 --- a/target/linux/at91/patches-5.15/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 55c14526f970805a6bf2ed4b820f062334375abe Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Thu, 19 Nov 2020 17:43:09 +0200 -Subject: [PATCH 103/247] clk: at91: sama7g5: allow SYS and CPU PLLs to be - exported and referenced in DT - -Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock -from phandle in DT. - -Suggested-by: Claudiu Beznea -Signed-off-by: Eugen Hristev -[claudiu.beznea@microchip.com: adapt commit message, add CPU PLL] -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -117,7 +117,8 @@ static const struct { - .p = "cpupll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -- .c = 1, }, -+ .c = 1, -+ .eid = PMC_CPUPLL, }, - }, - - [PLL_ID_SYS] = { -@@ -131,7 +132,8 @@ static const struct { - .p = "syspll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -- .c = 1, }, -+ .c = 1, -+ .eid = PMC_SYSPLL, }, - }, - - [PLL_ID_DDR] = { diff --git a/target/linux/at91/patches-5.15/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch b/target/linux/at91/patches-5.15/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch deleted file mode 100644 index 9feea82490..0000000000 --- a/target/linux/at91/patches-5.15/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch +++ /dev/null @@ -1,42 +0,0 @@ -From b2349278894bb381fa26a8717d3093d53f08fd36 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Thu, 19 Nov 2020 17:43:10 +0200 -Subject: [PATCH 104/247] clk: at91: clk-master: add 5th divisor for mck master - -clk-master can have 5 divisors with a field width of 3 bits -on some products. - -Change the mask and number of divisors accordingly. - -Reported-by: Mihai Sain -Signed-off-by: Eugen Hristev -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-5-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-master.c | 2 +- - drivers/clk/at91/pmc.h | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -15,7 +15,7 @@ - #define MASTER_PRES_MASK 0x7 - #define MASTER_PRES_MAX MASTER_PRES_MASK - #define MASTER_DIV_SHIFT 8 --#define MASTER_DIV_MASK 0x3 -+#define MASTER_DIV_MASK 0x7 - - #define PMC_MCR 0x30 - #define PMC_MCR_ID_MSK GENMASK(3, 0) ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -48,7 +48,7 @@ extern const struct clk_master_layout at - - struct clk_master_characteristics { - struct clk_range output; -- u32 divisors[4]; -+ u32 divisors[5]; - u8 have_div3_pres; - }; - diff --git a/target/linux/at91/patches-5.15/239-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch b/target/linux/at91/patches-5.15/104-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch similarity index 100% rename from target/linux/at91/patches-5.15/239-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch rename to target/linux/at91/patches-5.15/104-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch diff --git a/target/linux/at91/patches-5.15/241-clk-at91-clk-master-mask-mckr-against-layout-mask.patch b/target/linux/at91/patches-5.15/105-clk-at91-clk-master-mask-mckr-against-layout-mask.patch similarity index 96% rename from target/linux/at91/patches-5.15/241-clk-at91-clk-master-mask-mckr-against-layout-mask.patch rename to target/linux/at91/patches-5.15/105-clk-at91-clk-master-mask-mckr-against-layout-mask.patch index 14fa690769..ea869c9485 100644 --- a/target/linux/at91/patches-5.15/241-clk-at91-clk-master-mask-mckr-against-layout-mask.patch +++ b/target/linux/at91/patches-5.15/105-clk-at91-clk-master-mask-mckr-against-layout-mask.patch @@ -33,7 +33,7 @@ Signed-off-by: Stephen Boyd + val &= master->layout->mask; pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; - if (pres == 3 && characteristics->have_div3_pres) + if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres) pres = 3; @@ -403,6 +404,8 @@ static u8 clk_master_pres_get_parent(str regmap_read(master->regmap, master->layout->offset, &mckr); diff --git a/target/linux/at91/patches-5.15/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch b/target/linux/at91/patches-5.15/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch deleted file mode 100644 index 55e7f913c2..0000000000 --- a/target/linux/at91/patches-5.15/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch +++ /dev/null @@ -1,36 +0,0 @@ -From c41f013e13962dcc78239d5e4834214d44556cfb Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Thu, 19 Nov 2020 17:43:11 +0200 -Subject: [PATCH 105/247] clk: at91: sama7g5: add 5th divisor for mck0 layout - and characteristics - -This SoC has the 5th divisor for the mck0 master clock. -Adapt the characteristics accordingly. - -Reported-by: Mihai Sain -Signed-off-by: Eugen Hristev -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -775,13 +775,13 @@ static const struct clk_pll_characterist - /* MCK0 characteristics. */ - static const struct clk_master_characteristics mck0_characteristics = { - .output = { .min = 140000000, .max = 200000000 }, -- .divisors = { 1, 2, 4, 3 }, -+ .divisors = { 1, 2, 4, 3, 5 }, - .have_div3_pres = 1, - }; - - /* MCK0 layout. */ - static const struct clk_master_layout mck0_layout = { -- .mask = 0x373, -+ .mask = 0x773, - .pres_shift = 4, - .offset = 0x28, - }; diff --git a/target/linux/at91/patches-5.15/243-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch b/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch similarity index 99% rename from target/linux/at91/patches-5.15/243-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch rename to target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch index 678303da37..e5ebdc4ea4 100644 --- a/target/linux/at91/patches-5.15/243-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch +++ b/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch @@ -300,7 +300,7 @@ Signed-off-by: Stephen Boyd }, [PLL_ID_SYS] = { -@@ -967,7 +975,8 @@ static void __init sama7g5_pmc_setup(str +@@ -966,7 +974,8 @@ static void __init sama7g5_pmc_setup(str sama7g5_plls[i][j].p, i, sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, diff --git a/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch b/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch deleted file mode 100644 index fa76cbb5a3..0000000000 --- a/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch +++ /dev/null @@ -1,510 +0,0 @@ -From 6fe2927863de96edf35d8357712dbf83a489f556 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 19 Nov 2020 17:43:12 +0200 -Subject: [PATCH 106/247] clk: at91: clk-sam9x60-pll: allow runtime changes for - pll - -Allow runtime frequency changes for PLLs registered with proper flags. -This is necessary for CPU PLL on SAMA7G5 which is used by DVFS. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-sam9x60-pll.c | 145 +++++++++++++++++++++++++---- - drivers/clk/at91/pmc.h | 4 +- - drivers/clk/at91/sam9x60.c | 22 ++++- - drivers/clk/at91/sama7g5.c | 67 +++++++++---- - 4 files changed, 197 insertions(+), 41 deletions(-) - ---- a/drivers/clk/at91/clk-sam9x60-pll.c -+++ b/drivers/clk/at91/clk-sam9x60-pll.c -@@ -229,6 +229,57 @@ static int sam9x60_frac_pll_set_rate(str - return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true); - } - -+static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -+ struct sam9x60_frac *frac = to_sam9x60_frac(core); -+ struct regmap *regmap = core->regmap; -+ unsigned long irqflags; -+ unsigned int val, cfrac, cmul; -+ long ret; -+ -+ ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true); -+ if (ret <= 0) -+ return ret; -+ -+ spin_lock_irqsave(core->lock, irqflags); -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, -+ core->id); -+ regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val); -+ cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; -+ cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift; -+ -+ if (cmul == frac->mul && cfrac == frac->frac) -+ goto unlock; -+ -+ regmap_write(regmap, AT91_PMC_PLL_CTRL1, -+ (frac->mul << core->layout->mul_shift) | -+ (frac->frac << core->layout->frac_shift)); -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, -+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, -+ AT91_PMC_PLL_UPDT_UPDATE | core->id); -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, -+ AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL, -+ AT91_PMC_PLL_CTRL0_ENLOCK | -+ AT91_PMC_PLL_CTRL0_ENPLL); -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, -+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, -+ AT91_PMC_PLL_UPDT_UPDATE | core->id); -+ -+ while (!sam9x60_pll_ready(regmap, core->id)) -+ cpu_relax(); -+ -+unlock: -+ spin_unlock_irqrestore(core->lock, irqflags); -+ -+ return ret; -+} -+ - static const struct clk_ops sam9x60_frac_pll_ops = { - .prepare = sam9x60_frac_pll_prepare, - .unprepare = sam9x60_frac_pll_unprepare, -@@ -238,6 +289,15 @@ static const struct clk_ops sam9x60_frac - .set_rate = sam9x60_frac_pll_set_rate, - }; - -+static const struct clk_ops sam9x60_frac_pll_ops_chg = { -+ .prepare = sam9x60_frac_pll_prepare, -+ .unprepare = sam9x60_frac_pll_unprepare, -+ .is_prepared = sam9x60_frac_pll_is_prepared, -+ .recalc_rate = sam9x60_frac_pll_recalc_rate, -+ .round_rate = sam9x60_frac_pll_round_rate, -+ .set_rate = sam9x60_frac_pll_set_rate_chg, -+}; -+ - static int sam9x60_div_pll_prepare(struct clk_hw *hw) - { - struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -@@ -384,6 +444,44 @@ static int sam9x60_div_pll_set_rate(stru - return 0; - } - -+static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -+ struct sam9x60_div *div = to_sam9x60_div(core); -+ struct regmap *regmap = core->regmap; -+ unsigned long irqflags; -+ unsigned int val, cdiv; -+ -+ div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; -+ -+ spin_lock_irqsave(core->lock, irqflags); -+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, -+ core->id); -+ regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); -+ cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; -+ -+ /* Stop if nothing changed. */ -+ if (cdiv == div->div) -+ goto unlock; -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, -+ core->layout->div_mask, -+ (div->div << core->layout->div_shift)); -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, -+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, -+ AT91_PMC_PLL_UPDT_UPDATE | core->id); -+ -+ while (!sam9x60_pll_ready(regmap, core->id)) -+ cpu_relax(); -+ -+unlock: -+ spin_unlock_irqrestore(core->lock, irqflags); -+ -+ return 0; -+} -+ - static const struct clk_ops sam9x60_div_pll_ops = { - .prepare = sam9x60_div_pll_prepare, - .unprepare = sam9x60_div_pll_unprepare, -@@ -393,17 +491,26 @@ static const struct clk_ops sam9x60_div_ - .set_rate = sam9x60_div_pll_set_rate, - }; - -+static const struct clk_ops sam9x60_div_pll_ops_chg = { -+ .prepare = sam9x60_div_pll_prepare, -+ .unprepare = sam9x60_div_pll_unprepare, -+ .is_prepared = sam9x60_div_pll_is_prepared, -+ .recalc_rate = sam9x60_div_pll_recalc_rate, -+ .round_rate = sam9x60_div_pll_round_rate, -+ .set_rate = sam9x60_div_pll_set_rate_chg, -+}; -+ - struct clk_hw * __init - sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, - struct clk_hw *parent_hw, u8 id, - const struct clk_pll_characteristics *characteristics, -- const struct clk_pll_layout *layout, bool critical) -+ const struct clk_pll_layout *layout, u32 flags) - { - struct sam9x60_frac *frac; - struct clk_hw *hw; - struct clk_init_data init; -- unsigned long parent_rate, flags; -+ unsigned long parent_rate, irqflags; - unsigned int val; - int ret; - -@@ -417,10 +524,12 @@ sam9x60_clk_register_frac_pll(struct reg - init.name = name; - init.parent_names = &parent_name; - init.num_parents = 1; -- init.ops = &sam9x60_frac_pll_ops; -- init.flags = CLK_SET_RATE_GATE; -- if (critical) -- init.flags |= CLK_IS_CRITICAL; -+ if (flags & CLK_SET_RATE_GATE) -+ init.ops = &sam9x60_frac_pll_ops; -+ else -+ init.ops = &sam9x60_frac_pll_ops_chg; -+ -+ init.flags = flags; - - frac->core.id = id; - frac->core.hw.init = &init; -@@ -429,7 +538,7 @@ sam9x60_clk_register_frac_pll(struct reg - frac->core.regmap = regmap; - frac->core.lock = lock; - -- spin_lock_irqsave(frac->core.lock, flags); -+ spin_lock_irqsave(frac->core.lock, irqflags); - if (sam9x60_pll_ready(regmap, id)) { - regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, - AT91_PMC_PLL_UPDT_ID_MSK, id); -@@ -457,7 +566,7 @@ sam9x60_clk_register_frac_pll(struct reg - goto free; - } - } -- spin_unlock_irqrestore(frac->core.lock, flags); -+ spin_unlock_irqrestore(frac->core.lock, irqflags); - - hw = &frac->core.hw; - ret = clk_hw_register(NULL, hw); -@@ -469,7 +578,7 @@ sam9x60_clk_register_frac_pll(struct reg - return hw; - - free: -- spin_unlock_irqrestore(frac->core.lock, flags); -+ spin_unlock_irqrestore(frac->core.lock, irqflags); - kfree(frac); - return hw; - } -@@ -478,12 +587,12 @@ struct clk_hw * __init - sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, u8 id, - const struct clk_pll_characteristics *characteristics, -- const struct clk_pll_layout *layout, bool critical) -+ const struct clk_pll_layout *layout, u32 flags) - { - struct sam9x60_div *div; - struct clk_hw *hw; - struct clk_init_data init; -- unsigned long flags; -+ unsigned long irqflags; - unsigned int val; - int ret; - -@@ -497,11 +606,11 @@ sam9x60_clk_register_div_pll(struct regm - init.name = name; - init.parent_names = &parent_name; - init.num_parents = 1; -- init.ops = &sam9x60_div_pll_ops; -- init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | -- CLK_SET_RATE_PARENT; -- if (critical) -- init.flags |= CLK_IS_CRITICAL; -+ if (flags & CLK_SET_RATE_GATE) -+ init.ops = &sam9x60_div_pll_ops; -+ else -+ init.ops = &sam9x60_div_pll_ops_chg; -+ init.flags = flags; - - div->core.id = id; - div->core.hw.init = &init; -@@ -510,14 +619,14 @@ sam9x60_clk_register_div_pll(struct regm - div->core.regmap = regmap; - div->core.lock = lock; - -- spin_lock_irqsave(div->core.lock, flags); -+ spin_lock_irqsave(div->core.lock, irqflags); - - regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, - AT91_PMC_PLL_UPDT_ID_MSK, id); - regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); - div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val); - -- spin_unlock_irqrestore(div->core.lock, flags); -+ spin_unlock_irqrestore(div->core.lock, irqflags); - - hw = &div->core.hw; - ret = clk_hw_register(NULL, hw); ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -190,14 +190,14 @@ struct clk_hw * __init - sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, u8 id, - const struct clk_pll_characteristics *characteristics, -- const struct clk_pll_layout *layout, bool critical); -+ const struct clk_pll_layout *layout, u32 flags); - - struct clk_hw * __init - sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, - struct clk_hw *parent_hw, u8 id, - const struct clk_pll_characteristics *characteristics, -- const struct clk_pll_layout *layout, bool critical); -+ const struct clk_pll_layout *layout, u32 flags); - - struct clk_hw * __init - at91_clk_register_programmable(struct regmap *regmap, const char *name, ---- a/drivers/clk/at91/sam9x60.c -+++ b/drivers/clk/at91/sam9x60.c -@@ -224,13 +224,24 @@ static void __init sam9x60_pmc_setup(str - hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck", - "mainck", sam9x60_pmc->chws[PMC_MAIN], - 0, &plla_characteristics, -- &pll_frac_layout, true); -+ &pll_frac_layout, -+ /* -+ * This feeds pllack_divck which -+ * feeds CPU. It should not be -+ * disabled. -+ */ -+ CLK_IS_CRITICAL | CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - - hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck", - "pllack_fracck", 0, &plla_characteristics, -- &pll_div_layout, true); -+ &pll_div_layout, -+ /* -+ * This feeds CPU. It should not -+ * be disabled. -+ */ -+ CLK_IS_CRITICAL | CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -239,13 +250,16 @@ static void __init sam9x60_pmc_setup(str - hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck", - "main_osc", main_osc_hw, 1, - &upll_characteristics, -- &pll_frac_layout, false); -+ &pll_frac_layout, CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - - hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck", - "upllck_fracck", 1, &upll_characteristics, -- &pll_div_layout, false); -+ &pll_div_layout, -+ CLK_SET_RATE_GATE | -+ CLK_SET_PARENT_GATE | -+ CLK_SET_RATE_PARENT); - if (IS_ERR(hw)) - goto err_free; - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -95,15 +95,15 @@ static const struct clk_pll_layout pll_l - * @p: clock parent - * @l: clock layout - * @t: clock type -- * @f: true if clock is critical and cannot be disabled -+ * @f: clock flags - * @eid: export index in sama7g5->chws[] array - */ - static const struct { - const char *n; - const char *p; - const struct clk_pll_layout *l; -+ unsigned long f; - u8 t; -- u8 c; - u8 eid; - } sama7g5_plls[][PLL_ID_MAX] = { - [PLL_ID_CPU] = { -@@ -111,13 +111,18 @@ static const struct { - .p = "mainck", - .l = &pll_layout_frac, - .t = PLL_TYPE_FRAC, -- .c = 1, }, -+ /* -+ * This feeds cpupll_divpmcck which feeds CPU. It should -+ * not be disabled. -+ */ -+ .f = CLK_IS_CRITICAL, }, - - { .n = "cpupll_divpmcck", - .p = "cpupll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -- .c = 1, -+ /* This feeds CPU. It should not be disabled. */ -+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .eid = PMC_CPUPLL, }, - }, - -@@ -126,13 +131,22 @@ static const struct { - .p = "mainck", - .l = &pll_layout_frac, - .t = PLL_TYPE_FRAC, -- .c = 1, }, -+ /* -+ * This feeds syspll_divpmcck which may feed critial parts -+ * of the systems like timers. Therefore it should not be -+ * disabled. -+ */ -+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, - - { .n = "syspll_divpmcck", - .p = "syspll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -- .c = 1, -+ /* -+ * This may feed critial parts of the systems like timers. -+ * Therefore it should not be disabled. -+ */ -+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, - .eid = PMC_SYSPLL, }, - }, - -@@ -141,55 +155,71 @@ static const struct { - .p = "mainck", - .l = &pll_layout_frac, - .t = PLL_TYPE_FRAC, -- .c = 1, }, -+ /* -+ * This feeds ddrpll_divpmcck which feeds DDR. It should not -+ * be disabled. -+ */ -+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, - - { .n = "ddrpll_divpmcck", - .p = "ddrpll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -- .c = 1, }, -+ /* This feeds DDR. It should not be disabled. */ -+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, - }, - - [PLL_ID_IMG] = { - { .n = "imgpll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -- .t = PLL_TYPE_FRAC, }, -+ .t = PLL_TYPE_FRAC, -+ .f = CLK_SET_RATE_GATE, }, - - { .n = "imgpll_divpmcck", - .p = "imgpll_fracck", - .l = &pll_layout_divpmc, -- .t = PLL_TYPE_DIV, }, -+ .t = PLL_TYPE_DIV, -+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | -+ CLK_SET_RATE_PARENT, }, - }, - - [PLL_ID_BAUD] = { - { .n = "baudpll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -- .t = PLL_TYPE_FRAC, }, -+ .t = PLL_TYPE_FRAC, -+ .f = CLK_SET_RATE_GATE, }, - - { .n = "baudpll_divpmcck", - .p = "baudpll_fracck", - .l = &pll_layout_divpmc, -- .t = PLL_TYPE_DIV, }, -+ .t = PLL_TYPE_DIV, -+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | -+ CLK_SET_RATE_PARENT, }, - }, - - [PLL_ID_AUDIO] = { - { .n = "audiopll_fracck", - .p = "main_xtal", - .l = &pll_layout_frac, -- .t = PLL_TYPE_FRAC, }, -+ .t = PLL_TYPE_FRAC, -+ .f = CLK_SET_RATE_GATE, }, - - { .n = "audiopll_divpmcck", - .p = "audiopll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | -+ CLK_SET_RATE_PARENT, - .eid = PMC_AUDIOPMCPLL, }, - - { .n = "audiopll_diviock", - .p = "audiopll_fracck", - .l = &pll_layout_divio, - .t = PLL_TYPE_DIV, -+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | -+ CLK_SET_RATE_PARENT, - .eid = PMC_AUDIOIOPLL, }, - }, - -@@ -197,12 +227,15 @@ static const struct { - { .n = "ethpll_fracck", - .p = "main_xtal", - .l = &pll_layout_frac, -- .t = PLL_TYPE_FRAC, }, -+ .t = PLL_TYPE_FRAC, -+ .f = CLK_SET_RATE_GATE, }, - - { .n = "ethpll_divpmcck", - .p = "ethpll_fracck", - .l = &pll_layout_divpmc, -- .t = PLL_TYPE_DIV, }, -+ .t = PLL_TYPE_DIV, -+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | -+ CLK_SET_RATE_PARENT, }, - }, - }; - -@@ -890,7 +923,7 @@ static void __init sama7g5_pmc_setup(str - sama7g5_plls[i][j].p, parent_hw, i, - &pll_characteristics, - sama7g5_plls[i][j].l, -- sama7g5_plls[i][j].c); -+ sama7g5_plls[i][j].f); - break; - - case PLL_TYPE_DIV: -@@ -899,7 +932,7 @@ static void __init sama7g5_pmc_setup(str - sama7g5_plls[i][j].p, i, - &pll_characteristics, - sama7g5_plls[i][j].l, -- sama7g5_plls[i][j].c); -+ sama7g5_plls[i][j].f); - break; - - default: diff --git a/target/linux/at91/patches-5.15/244-clk-at91-clk-master-add-notifier-for-divider.patch b/target/linux/at91/patches-5.15/107-clk-at91-clk-master-add-notifier-for-divider.patch similarity index 98% rename from target/linux/at91/patches-5.15/244-clk-at91-clk-master-add-notifier-for-divider.patch rename to target/linux/at91/patches-5.15/107-clk-at91-clk-master-add-notifier-for-divider.patch index 35262db6cb..83839e6a74 100644 --- a/target/linux/at91/patches-5.15/244-clk-at91-clk-master-add-notifier-for-divider.patch +++ b/target/linux/at91/patches-5.15/107-clk-at91-clk-master-add-notifier-for-divider.patch @@ -508,9 +508,9 @@ Signed-off-by: Stephen Boyd --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c -@@ -1003,7 +1003,7 @@ static void __init sama7g5_pmc_setup(str - - hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", +@@ -993,7 +993,7 @@ static void __init sama7g5_pmc_setup(str + parent_names[0] = "cpupll_divpmcck"; + hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck", &mck0_layout, &mck0_characteristics, - &pmc_mck0_lock, 0); + &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); diff --git a/target/linux/at91/patches-5.15/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch b/target/linux/at91/patches-5.15/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch deleted file mode 100644 index 209c40cf2f..0000000000 --- a/target/linux/at91/patches-5.15/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch +++ /dev/null @@ -1,196 +0,0 @@ -From 7cfe2dfe5ac7c72b904e4b59b240caa42721ee07 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 19 Nov 2020 17:43:13 +0200 -Subject: [PATCH 107/247] clk: at91: sama7g5: remove mck0 from parent list of - other clocks - -MCK0 is changed at runtime by DVFS. Due to this, since not all IPs -are glitch free aware at MCK0 changes, remove MCK0 from parent list -of other clocks (e.g. generic clock, programmable/system clock, MCKX). - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-8-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 55 ++++++++++++++++++-------------------- - 1 file changed, 26 insertions(+), 29 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -280,7 +280,7 @@ static const struct { - .ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", }, - .ep_mux_table = { 5, 6, 7, }, - .ep_count = 3, -- .ep_chg_id = 6, }, -+ .ep_chg_id = 5, }, - - { .n = "mck4", - .id = 4, -@@ -313,7 +313,7 @@ static const struct { - }; - - /* Mux table for programmable clocks. */ --static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, }; -+static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, }; - - /** - * Peripheral clock description -@@ -436,7 +436,7 @@ static const struct { - .pp = { "audiopll_divpmcck", }, - .pp_mux_table = { 9, }, - .pp_count = 1, -- .pp_chg_id = 4, }, -+ .pp_chg_id = 3, }, - - { .n = "csi_gclk", - .id = 33, -@@ -548,7 +548,7 @@ static const struct { - .pp = { "ethpll_divpmcck", }, - .pp_mux_table = { 10, }, - .pp_count = 1, -- .pp_chg_id = 4, }, -+ .pp_chg_id = 3, }, - - { .n = "gmac1_gclk", - .id = 52, -@@ -580,7 +580,7 @@ static const struct { - .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, - .pp_mux_table = { 5, 9, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "i2smcc1_gclk", - .id = 58, -@@ -588,7 +588,7 @@ static const struct { - .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, - .pp_mux_table = { 5, 9, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "mcan0_gclk", - .id = 61, -@@ -730,7 +730,7 @@ static const struct { - .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, - .pp_mux_table = { 5, 8, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "sdmmc1_gclk", - .id = 81, -@@ -738,7 +738,7 @@ static const struct { - .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, - .pp_mux_table = { 5, 8, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "sdmmc2_gclk", - .id = 82, -@@ -746,7 +746,7 @@ static const struct { - .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, - .pp_mux_table = { 5, 8, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "spdifrx_gclk", - .id = 84, -@@ -754,7 +754,7 @@ static const struct { - .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, - .pp_mux_table = { 5, 9, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "spdiftx_gclk", - .id = 85, -@@ -762,7 +762,7 @@ static const struct { - .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, - .pp_mux_table = { 5, 9, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "tcb0_ch0_gclk", - .id = 88, -@@ -961,9 +961,8 @@ static void __init sama7g5_pmc_setup(str - parent_names[0] = md_slck_name; - parent_names[1] = td_slck_name; - parent_names[2] = "mainck"; -- parent_names[3] = "mck0"; - for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) { -- u8 num_parents = 4 + sama7g5_mckx[i].ep_count; -+ u8 num_parents = 3 + sama7g5_mckx[i].ep_count; - u32 *mux_table; - - mux_table = kmalloc_array(num_parents, sizeof(*mux_table), -@@ -971,10 +970,10 @@ static void __init sama7g5_pmc_setup(str - if (!mux_table) - goto err_free; - -- SAMA7G5_INIT_TABLE(mux_table, 4); -- SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_mckx[i].ep_mux_table, -+ SAMA7G5_INIT_TABLE(mux_table, 3); -+ SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, - sama7g5_mckx[i].ep_count); -- SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_mckx[i].ep, -+ SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep, - sama7g5_mckx[i].ep_count); - - hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, -@@ -997,20 +996,19 @@ static void __init sama7g5_pmc_setup(str - parent_names[0] = md_slck_name; - parent_names[1] = td_slck_name; - parent_names[2] = "mainck"; -- parent_names[3] = "mck0"; -- parent_names[4] = "syspll_divpmcck"; -- parent_names[5] = "ddrpll_divpmcck"; -- parent_names[6] = "imgpll_divpmcck"; -- parent_names[7] = "baudpll_divpmcck"; -- parent_names[8] = "audiopll_divpmcck"; -- parent_names[9] = "ethpll_divpmcck"; -+ parent_names[3] = "syspll_divpmcck"; -+ parent_names[4] = "ddrpll_divpmcck"; -+ parent_names[5] = "imgpll_divpmcck"; -+ parent_names[6] = "baudpll_divpmcck"; -+ parent_names[7] = "audiopll_divpmcck"; -+ parent_names[8] = "ethpll_divpmcck"; - for (i = 0; i < 8; i++) { - char name[6]; - - snprintf(name, sizeof(name), "prog%d", i); - - hw = at91_clk_register_programmable(regmap, name, parent_names, -- 10, i, -+ 9, i, - &programmable_layout, - sama7g5_prog_mux_table); - if (IS_ERR(hw)) -@@ -1047,9 +1045,8 @@ static void __init sama7g5_pmc_setup(str - parent_names[0] = md_slck_name; - parent_names[1] = td_slck_name; - parent_names[2] = "mainck"; -- parent_names[3] = "mck0"; - for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) { -- u8 num_parents = 4 + sama7g5_gck[i].pp_count; -+ u8 num_parents = 3 + sama7g5_gck[i].pp_count; - u32 *mux_table; - - mux_table = kmalloc_array(num_parents, sizeof(*mux_table), -@@ -1057,10 +1054,10 @@ static void __init sama7g5_pmc_setup(str - if (!mux_table) - goto err_free; - -- SAMA7G5_INIT_TABLE(mux_table, 4); -- SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_gck[i].pp_mux_table, -+ SAMA7G5_INIT_TABLE(mux_table, 3); -+ SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, - sama7g5_gck[i].pp_count); -- SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_gck[i].pp, -+ SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp, - sama7g5_gck[i].pp_count); - - hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, diff --git a/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch b/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch deleted file mode 100644 index 2bc1907cfb..0000000000 --- a/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 8b88f1e9918c173b24b43015cdb713cdde9e4d17 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 19 Nov 2020 17:43:14 +0200 -Subject: [PATCH 108/247] clk: at91: sama7g5: decrease lower limit for MCK0 - rate - -On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and -CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is -also changed by DVFS to avoid over/under clocking of MCK0 consumers. -The lower limit is changed to be able to set MCK0 accordingly by -DVFS. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -807,7 +807,7 @@ static const struct clk_pll_characterist - - /* MCK0 characteristics. */ - static const struct clk_master_characteristics mck0_characteristics = { -- .output = { .min = 140000000, .max = 200000000 }, -+ .output = { .min = 50000000, .max = 200000000 }, - .divisors = { 1, 2, 4, 3, 5 }, - .have_div3_pres = 1, - }; diff --git a/target/linux/at91/patches-5.15/246-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch b/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch similarity index 95% rename from target/linux/at91/patches-5.15/246-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch rename to target/linux/at91/patches-5.15/108-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch index 922cf0b69c..6cdec0add7 100644 --- a/target/linux/at91/patches-5.15/246-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch +++ b/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch @@ -15,7 +15,7 @@ Signed-off-by: Stephen Boyd --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c -@@ -850,7 +850,7 @@ static const struct { +@@ -849,7 +849,7 @@ static const struct { /* MCK0 characteristics. */ static const struct clk_master_characteristics mck0_characteristics = { diff --git a/target/linux/at91/patches-5.15/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch b/target/linux/at91/patches-5.15/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch deleted file mode 100644 index b11efc9d4e..0000000000 --- a/target/linux/at91/patches-5.15/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch +++ /dev/null @@ -1,221 +0,0 @@ -From 943ed75a2a5ab08582d3bc8025e8111903698763 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 19 Nov 2020 17:43:15 +0200 -Subject: [PATCH 109/247] clk: at91: sama7g5: do not allow cpu pll to go higher - than 1GHz - -Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher -than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at -1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 61 +++++++++++++++++++++++++++++--------- - 1 file changed, 47 insertions(+), 14 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -89,11 +89,40 @@ static const struct clk_pll_layout pll_l - .endiv_shift = 30, - }; - -+/* -+ * CPU PLL output range. -+ * Notice: The upper limit has been setup to 1000000002 due to hardware -+ * block which cannot output exactly 1GHz. -+ */ -+static const struct clk_range cpu_pll_outputs[] = { -+ { .min = 2343750, .max = 1000000002 }, -+}; -+ -+/* PLL output range. */ -+static const struct clk_range pll_outputs[] = { -+ { .min = 2343750, .max = 1200000000 }, -+}; -+ -+/* CPU PLL characteristics. */ -+static const struct clk_pll_characteristics cpu_pll_characteristics = { -+ .input = { .min = 12000000, .max = 50000000 }, -+ .num_output = ARRAY_SIZE(cpu_pll_outputs), -+ .output = cpu_pll_outputs, -+}; -+ -+/* PLL characteristics. */ -+static const struct clk_pll_characteristics pll_characteristics = { -+ .input = { .min = 12000000, .max = 50000000 }, -+ .num_output = ARRAY_SIZE(pll_outputs), -+ .output = pll_outputs, -+}; -+ - /** - * PLL clocks description - * @n: clock name - * @p: clock parent - * @l: clock layout -+ * @c: clock characteristics - * @t: clock type - * @f: clock flags - * @eid: export index in sama7g5->chws[] array -@@ -102,6 +131,7 @@ static const struct { - const char *n; - const char *p; - const struct clk_pll_layout *l; -+ const struct clk_pll_characteristics *c; - unsigned long f; - u8 t; - u8 eid; -@@ -110,6 +140,7 @@ static const struct { - { .n = "cpupll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -+ .c = &cpu_pll_characteristics, - .t = PLL_TYPE_FRAC, - /* - * This feeds cpupll_divpmcck which feeds CPU. It should -@@ -120,6 +151,7 @@ static const struct { - { .n = "cpupll_divpmcck", - .p = "cpupll_fracck", - .l = &pll_layout_divpmc, -+ .c = &cpu_pll_characteristics, - .t = PLL_TYPE_DIV, - /* This feeds CPU. It should not be disabled. */ - .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, -@@ -130,6 +162,7 @@ static const struct { - { .n = "syspll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -+ .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - /* - * This feeds syspll_divpmcck which may feed critial parts -@@ -141,6 +174,7 @@ static const struct { - { .n = "syspll_divpmcck", - .p = "syspll_fracck", - .l = &pll_layout_divpmc, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - /* - * This may feed critial parts of the systems like timers. -@@ -154,6 +188,7 @@ static const struct { - { .n = "ddrpll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -+ .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - /* - * This feeds ddrpll_divpmcck which feeds DDR. It should not -@@ -164,6 +199,7 @@ static const struct { - { .n = "ddrpll_divpmcck", - .p = "ddrpll_fracck", - .l = &pll_layout_divpmc, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - /* This feeds DDR. It should not be disabled. */ - .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, -@@ -173,12 +209,14 @@ static const struct { - { .n = "imgpll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -+ .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - .f = CLK_SET_RATE_GATE, }, - - { .n = "imgpll_divpmcck", - .p = "imgpll_fracck", - .l = &pll_layout_divpmc, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | - CLK_SET_RATE_PARENT, }, -@@ -188,12 +226,14 @@ static const struct { - { .n = "baudpll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -+ .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - .f = CLK_SET_RATE_GATE, }, - - { .n = "baudpll_divpmcck", - .p = "baudpll_fracck", - .l = &pll_layout_divpmc, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | - CLK_SET_RATE_PARENT, }, -@@ -203,12 +243,14 @@ static const struct { - { .n = "audiopll_fracck", - .p = "main_xtal", - .l = &pll_layout_frac, -+ .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - .f = CLK_SET_RATE_GATE, }, - - { .n = "audiopll_divpmcck", - .p = "audiopll_fracck", - .l = &pll_layout_divpmc, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | - CLK_SET_RATE_PARENT, -@@ -217,6 +259,7 @@ static const struct { - { .n = "audiopll_diviock", - .p = "audiopll_fracck", - .l = &pll_layout_divio, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | - CLK_SET_RATE_PARENT, -@@ -227,12 +270,14 @@ static const struct { - { .n = "ethpll_fracck", - .p = "main_xtal", - .l = &pll_layout_frac, -+ .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - .f = CLK_SET_RATE_GATE, }, - - { .n = "ethpll_divpmcck", - .p = "ethpll_fracck", - .l = &pll_layout_divpmc, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | - CLK_SET_RATE_PARENT, }, -@@ -793,18 +838,6 @@ static const struct { - .pp_chg_id = INT_MIN, }, - }; - --/* PLL output range. */ --static const struct clk_range pll_outputs[] = { -- { .min = 2343750, .max = 1200000000 }, --}; -- --/* PLL characteristics. */ --static const struct clk_pll_characteristics pll_characteristics = { -- .input = { .min = 12000000, .max = 50000000 }, -- .num_output = ARRAY_SIZE(pll_outputs), -- .output = pll_outputs, --}; -- - /* MCK0 characteristics. */ - static const struct clk_master_characteristics mck0_characteristics = { - .output = { .min = 50000000, .max = 200000000 }, -@@ -921,7 +954,7 @@ static void __init sama7g5_pmc_setup(str - hw = sam9x60_clk_register_frac_pll(regmap, - &pmc_pll_lock, sama7g5_plls[i][j].n, - sama7g5_plls[i][j].p, parent_hw, i, -- &pll_characteristics, -+ sama7g5_plls[i][j].c, - sama7g5_plls[i][j].l, - sama7g5_plls[i][j].f); - break; -@@ -930,7 +963,7 @@ static void __init sama7g5_pmc_setup(str - hw = sam9x60_clk_register_div_pll(regmap, - &pmc_pll_lock, sama7g5_plls[i][j].n, - sama7g5_plls[i][j].p, i, -- &pll_characteristics, -+ sama7g5_plls[i][j].c, - sama7g5_plls[i][j].l, - sama7g5_plls[i][j].f); - break; diff --git a/target/linux/at91/patches-5.15/247-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch b/target/linux/at91/patches-5.15/109-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch similarity index 94% rename from target/linux/at91/patches-5.15/247-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch rename to target/linux/at91/patches-5.15/109-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch index 6751edec5c..32e760ac17 100644 --- a/target/linux/at91/patches-5.15/247-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch +++ b/target/linux/at91/patches-5.15/109-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch @@ -18,7 +18,7 @@ Signed-off-by: Stephen Boyd --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c -@@ -3105,7 +3105,10 @@ static int clk_rate_get(void *data, u64 +@@ -3131,7 +3131,10 @@ static int clk_rate_get(void *data, u64 { struct clk_core *core = data; diff --git a/target/linux/at91/patches-5.15/110-clk-at91-clk-master-re-factor-master-clock.patch b/target/linux/at91/patches-5.15/110-clk-at91-clk-master-re-factor-master-clock.patch deleted file mode 100644 index a0eadd8886..0000000000 --- a/target/linux/at91/patches-5.15/110-clk-at91-clk-master-re-factor-master-clock.patch +++ /dev/null @@ -1,1230 +0,0 @@ -From 9109b768fe65994547ef464b13e508b22de3e89b Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 19 Nov 2020 17:43:16 +0200 -Subject: [PATCH 110/247] clk: at91: clk-master: re-factor master clock - -Re-factor master clock driver by splitting it into 2 clocks: prescaller -and divider clocks. Based on registered clock flags the prescaler's rate -could be changed at runtime. This is necessary for platforms supporting -DVFS (e.g. SAMA7G5) where master clock could be changed at run-time. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/at91rm9200.c | 21 ++- - drivers/clk/at91/at91sam9260.c | 26 ++- - drivers/clk/at91/at91sam9g45.c | 32 +++- - drivers/clk/at91/at91sam9n12.c | 36 ++-- - drivers/clk/at91/at91sam9rl.c | 23 ++- - drivers/clk/at91/at91sam9x5.c | 28 ++- - drivers/clk/at91/clk-master.c | 335 ++++++++++++++++++++++++++++----- - drivers/clk/at91/dt-compat.c | 15 +- - drivers/clk/at91/pmc.h | 16 +- - drivers/clk/at91/sam9x60.c | 23 ++- - drivers/clk/at91/sama5d2.c | 42 +++-- - drivers/clk/at91/sama5d3.c | 38 ++-- - drivers/clk/at91/sama5d4.c | 40 ++-- - drivers/clk/at91/sama7g5.c | 13 +- - 14 files changed, 542 insertions(+), 146 deletions(-) - ---- a/drivers/clk/at91/at91rm9200.c -+++ b/drivers/clk/at91/at91rm9200.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(rm9200_mck_lock); -+ - struct sck { - char *n; - char *p; -@@ -137,9 +139,20 @@ static void __init at91rm9200_pmc_setup( - parent_names[1] = "mainck"; - parent_names[2] = "pllack"; - parent_names[3] = "pllbck"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91rm9200_master_layout, -- &rm9200_mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91rm9200_master_layout, -+ &rm9200_mck_characteristics, -+ &rm9200_mck_lock, CLK_SET_RATE_GATE, -+ INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91rm9200_master_layout, -+ &rm9200_mck_characteristics, -+ &rm9200_mck_lock, CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -181,7 +194,7 @@ static void __init at91rm9200_pmc_setup( - for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) { - hw = at91_clk_register_peripheral(regmap, - at91rm9200_periphck[i].n, -- "masterck", -+ "masterck_div", - at91rm9200_periphck[i].id); - if (IS_ERR(hw)) - goto err_free; ---- a/drivers/clk/at91/at91sam9260.c -+++ b/drivers/clk/at91/at91sam9260.c -@@ -32,6 +32,8 @@ struct at91sam926x_data { - bool has_slck; - }; - -+static DEFINE_SPINLOCK(at91sam9260_mck_lock); -+ - static const struct clk_master_characteristics sam9260_mck_characteristics = { - .output = { .min = 0, .max = 105000000 }, - .divisors = { 1, 2, 4, 0 }, -@@ -218,8 +220,8 @@ static const struct sck at91sam9261_syst - { .n = "pck1", .p = "prog1", .id = 9 }, - { .n = "pck2", .p = "prog2", .id = 10 }, - { .n = "pck3", .p = "prog3", .id = 11 }, -- { .n = "hclk0", .p = "masterck", .id = 16 }, -- { .n = "hclk1", .p = "masterck", .id = 17 }, -+ { .n = "hclk0", .p = "masterck_div", .id = 16 }, -+ { .n = "hclk1", .p = "masterck_div", .id = 17 }, - }; - - static const struct pck at91sam9261_periphck[] = { -@@ -413,9 +415,21 @@ static void __init at91sam926x_pmc_setup - parent_names[1] = "mainck"; - parent_names[2] = "pllack"; - parent_names[3] = "pllbck"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91rm9200_master_layout, -- data->mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91rm9200_master_layout, -+ data->mck_characteristics, -+ &at91sam9260_mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91rm9200_master_layout, -+ data->mck_characteristics, -+ &at91sam9260_mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -457,7 +471,7 @@ static void __init at91sam926x_pmc_setup - for (i = 0; i < data->num_pck; i++) { - hw = at91_clk_register_peripheral(regmap, - data->pck[i].n, -- "masterck", -+ "masterck_div", - data->pck[i].id); - if (IS_ERR(hw)) - goto err_free; ---- a/drivers/clk/at91/at91sam9g45.c -+++ b/drivers/clk/at91/at91sam9g45.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(at91sam9g45_mck_lock); -+ - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 0, .max = 133333333 }, - .divisors = { 1, 2, 4, 3 }, -@@ -40,10 +42,10 @@ static const struct { - char *p; - u8 id; - } at91sam9g45_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -- { .n = "uhpck", .p = "usbck", .id = 6 }, -- { .n = "pck0", .p = "prog0", .id = 8 }, -- { .n = "pck1", .p = "prog1", .id = 9 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, -+ { .n = "uhpck", .p = "usbck", .id = 6 }, -+ { .n = "pck0", .p = "prog0", .id = 8 }, -+ { .n = "pck1", .p = "prog1", .id = 9 }, - }; - - struct pck { -@@ -148,9 +150,21 @@ static void __init at91sam9g45_pmc_setup - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91rm9200_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91rm9200_master_layout, -+ &mck_characteristics, -+ &at91sam9g45_mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91rm9200_master_layout, -+ &mck_characteristics, -+ &at91sam9g45_mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -166,7 +180,7 @@ static void __init at91sam9g45_pmc_setup - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - for (i = 0; i < 2; i++) { - char name[6]; - -@@ -195,7 +209,7 @@ static void __init at91sam9g45_pmc_setup - for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) { - hw = at91_clk_register_peripheral(regmap, - at91sam9g45_periphck[i].n, -- "masterck", -+ "masterck_div", - at91sam9g45_periphck[i].id); - if (IS_ERR(hw)) - goto err_free; ---- a/drivers/clk/at91/at91sam9n12.c -+++ b/drivers/clk/at91/at91sam9n12.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(at91sam9n12_mck_lock); -+ - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 0, .max = 133333333 }, - .divisors = { 1, 2, 4, 3 }, -@@ -54,12 +56,12 @@ static const struct { - char *p; - u8 id; - } at91sam9n12_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -- { .n = "lcdck", .p = "masterck", .id = 3 }, -- { .n = "uhpck", .p = "usbck", .id = 6 }, -- { .n = "udpck", .p = "usbck", .id = 7 }, -- { .n = "pck0", .p = "prog0", .id = 8 }, -- { .n = "pck1", .p = "prog1", .id = 9 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, -+ { .n = "lcdck", .p = "masterck_div", .id = 3 }, -+ { .n = "uhpck", .p = "usbck", .id = 6 }, -+ { .n = "udpck", .p = "usbck", .id = 7 }, -+ { .n = "pck0", .p = "prog0", .id = 8 }, -+ { .n = "pck1", .p = "prog1", .id = 9 }, - }; - - static const struct clk_pcr_layout at91sam9n12_pcr_layout = { -@@ -175,9 +177,21 @@ static void __init at91sam9n12_pmc_setup - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "pllbck"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91sam9x5_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91sam9x5_master_layout, -+ &mck_characteristics, -+ &at91sam9n12_mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91sam9x5_master_layout, -+ &mck_characteristics, -+ &at91sam9n12_mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -191,7 +205,7 @@ static void __init at91sam9n12_pmc_setup - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "pllbck"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - for (i = 0; i < 2; i++) { - char name[6]; - -@@ -221,7 +235,7 @@ static void __init at91sam9n12_pmc_setup - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &at91sam9n12_pcr_layout, - at91sam9n12_periphck[i].n, -- "masterck", -+ "masterck_div", - at91sam9n12_periphck[i].id, - &range, INT_MIN); - if (IS_ERR(hw)) ---- a/drivers/clk/at91/at91sam9rl.c -+++ b/drivers/clk/at91/at91sam9rl.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(sam9rl_mck_lock); -+ - static const struct clk_master_characteristics sam9rl_mck_characteristics = { - .output = { .min = 0, .max = 94000000 }, - .divisors = { 1, 2, 4, 0 }, -@@ -117,9 +119,20 @@ static void __init at91sam9rl_pmc_setup( - parent_names[1] = "mainck"; - parent_names[2] = "pllack"; - parent_names[3] = "utmick"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91rm9200_master_layout, -- &sam9rl_mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91rm9200_master_layout, -+ &sam9rl_mck_characteristics, -+ &sam9rl_mck_lock, CLK_SET_RATE_GATE, -+ INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91rm9200_master_layout, -+ &sam9rl_mck_characteristics, -+ &sam9rl_mck_lock, CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -129,7 +142,7 @@ static void __init at91sam9rl_pmc_setup( - parent_names[1] = "mainck"; - parent_names[2] = "pllack"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - for (i = 0; i < 2; i++) { - char name[6]; - -@@ -158,7 +171,7 @@ static void __init at91sam9rl_pmc_setup( - for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) { - hw = at91_clk_register_peripheral(regmap, - at91sam9rl_periphck[i].n, -- "masterck", -+ "masterck_div", - at91sam9rl_periphck[i].id); - if (IS_ERR(hw)) - goto err_free; ---- a/drivers/clk/at91/at91sam9x5.c -+++ b/drivers/clk/at91/at91sam9x5.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(mck_lock); -+ - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 0, .max = 133333333 }, - .divisors = { 1, 2, 4, 3 }, -@@ -41,7 +43,7 @@ static const struct { - char *p; - u8 id; - } at91sam9x5_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, - { .n = "smdck", .p = "smdclk", .id = 4 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "udpck", .p = "usbck", .id = 7 }, -@@ -196,9 +198,19 @@ static void __init at91sam9x5_pmc_setup( - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91sam9x5_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -218,7 +230,7 @@ static void __init at91sam9x5_pmc_setup( - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - for (i = 0; i < 2; i++) { - char name[6]; - -@@ -245,7 +257,7 @@ static void __init at91sam9x5_pmc_setup( - } - - if (has_lcdck) { -- hw = at91_clk_register_system(regmap, "lcdck", "masterck", 3); -+ hw = at91_clk_register_system(regmap, "lcdck", "masterck_div", 3); - if (IS_ERR(hw)) - goto err_free; - -@@ -256,7 +268,7 @@ static void __init at91sam9x5_pmc_setup( - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &at91sam9x5_pcr_layout, - at91sam9x5_periphck[i].n, -- "masterck", -+ "masterck_div", - at91sam9x5_periphck[i].id, - &range, INT_MIN); - if (IS_ERR(hw)) -@@ -269,7 +281,7 @@ static void __init at91sam9x5_pmc_setup( - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &at91sam9x5_pcr_layout, - extra_pcks[i].n, -- "masterck", -+ "masterck_div", - extra_pcks[i].id, - &range, INT_MIN); - if (IS_ERR(hw)) ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -58,83 +58,309 @@ static inline bool clk_master_ready(stru - static int clk_master_prepare(struct clk_hw *hw) - { - struct clk_master *master = to_clk_master(hw); -+ unsigned long flags; -+ -+ spin_lock_irqsave(master->lock, flags); - - while (!clk_master_ready(master)) - cpu_relax(); - -+ spin_unlock_irqrestore(master->lock, flags); -+ - return 0; - } - - static int clk_master_is_prepared(struct clk_hw *hw) - { - struct clk_master *master = to_clk_master(hw); -+ unsigned long flags; -+ bool status; -+ -+ spin_lock_irqsave(master->lock, flags); -+ status = clk_master_ready(master); -+ spin_unlock_irqrestore(master->lock, flags); - -- return clk_master_ready(master); -+ return status; - } - --static unsigned long clk_master_recalc_rate(struct clk_hw *hw, -- unsigned long parent_rate) -+static unsigned long clk_master_div_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) - { -- u8 pres; - u8 div; -- unsigned long rate = parent_rate; -+ unsigned long flags, rate = parent_rate; - struct clk_master *master = to_clk_master(hw); - const struct clk_master_layout *layout = master->layout; - const struct clk_master_characteristics *characteristics = - master->characteristics; - unsigned int mckr; - -+ spin_lock_irqsave(master->lock, flags); - regmap_read(master->regmap, master->layout->offset, &mckr); -+ spin_unlock_irqrestore(master->lock, flags); -+ - mckr &= layout->mask; - -- pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK; - div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; - -- if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX) -- rate /= 3; -- else -- rate >>= pres; -- - rate /= characteristics->divisors[div]; - - if (rate < characteristics->output.min) -- pr_warn("master clk is underclocked"); -+ pr_warn("master clk div is underclocked"); - else if (rate > characteristics->output.max) -- pr_warn("master clk is overclocked"); -+ pr_warn("master clk div is overclocked"); - - return rate; - } - --static u8 clk_master_get_parent(struct clk_hw *hw) -+static const struct clk_ops master_div_ops = { -+ .prepare = clk_master_prepare, -+ .is_prepared = clk_master_is_prepared, -+ .recalc_rate = clk_master_div_recalc_rate, -+}; -+ -+static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ const struct clk_master_characteristics *characteristics = -+ master->characteristics; -+ unsigned long flags; -+ int div, i; -+ -+ div = DIV_ROUND_CLOSEST(parent_rate, rate); -+ if (div > ARRAY_SIZE(characteristics->divisors)) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { -+ if (!characteristics->divisors[i]) -+ break; -+ -+ if (div == characteristics->divisors[i]) { -+ div = i; -+ break; -+ } -+ } -+ -+ if (i == ARRAY_SIZE(characteristics->divisors)) -+ return -EINVAL; -+ -+ spin_lock_irqsave(master->lock, flags); -+ regmap_update_bits(master->regmap, master->layout->offset, -+ (MASTER_DIV_MASK << MASTER_DIV_SHIFT), -+ (div << MASTER_DIV_SHIFT)); -+ while (!clk_master_ready(master)) -+ cpu_relax(); -+ spin_unlock_irqrestore(master->lock, flags); -+ -+ return 0; -+} -+ -+static int clk_master_div_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ const struct clk_master_characteristics *characteristics = -+ master->characteristics; -+ struct clk_hw *parent; -+ unsigned long parent_rate, tmp_rate, best_rate = 0; -+ int i, best_diff = INT_MIN, tmp_diff; -+ -+ parent = clk_hw_get_parent(hw); -+ if (!parent) -+ return -EINVAL; -+ -+ parent_rate = clk_hw_get_rate(parent); -+ if (!parent_rate) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { -+ if (!characteristics->divisors[i]) -+ break; -+ -+ tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate, -+ characteristics->divisors[i]); -+ tmp_diff = abs(tmp_rate - req->rate); -+ -+ if (!best_rate || best_diff > tmp_diff) { -+ best_diff = tmp_diff; -+ best_rate = tmp_rate; -+ } -+ -+ if (!best_diff) -+ break; -+ } -+ -+ req->best_parent_rate = best_rate; -+ req->best_parent_hw = parent; -+ req->rate = best_rate; -+ -+ return 0; -+} -+ -+static const struct clk_ops master_div_ops_chg = { -+ .prepare = clk_master_prepare, -+ .is_prepared = clk_master_is_prepared, -+ .recalc_rate = clk_master_div_recalc_rate, -+ .determine_rate = clk_master_div_determine_rate, -+ .set_rate = clk_master_div_set_rate, -+}; -+ -+static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, -+ struct clk_hw *parent, -+ unsigned long parent_rate, -+ long *best_rate, -+ long *best_diff, -+ u32 div) -+{ -+ unsigned long tmp_rate, tmp_diff; -+ -+ if (div == MASTER_PRES_MAX) -+ tmp_rate = parent_rate / 3; -+ else -+ tmp_rate = parent_rate >> div; -+ -+ tmp_diff = abs(req->rate - tmp_rate); -+ -+ if (*best_diff < 0 || *best_diff >= tmp_diff) { -+ *best_rate = tmp_rate; -+ *best_diff = tmp_diff; -+ req->best_parent_rate = parent_rate; -+ req->best_parent_hw = parent; -+ } -+} -+ -+static int clk_master_pres_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ struct clk_rate_request req_parent = *req; -+ const struct clk_master_characteristics *characteristics = -+ master->characteristics; -+ struct clk_hw *parent; -+ long best_rate = LONG_MIN, best_diff = LONG_MIN; -+ u32 pres; -+ int i; -+ -+ if (master->chg_pid < 0) -+ return -EOPNOTSUPP; -+ -+ parent = clk_hw_get_parent_by_index(hw, master->chg_pid); -+ if (!parent) -+ return -EOPNOTSUPP; -+ -+ for (i = 0; i <= MASTER_PRES_MAX; i++) { -+ if (characteristics->have_div3_pres && i == MASTER_PRES_MAX) -+ pres = 3; -+ else -+ pres = 1 << i; -+ -+ req_parent.rate = req->rate * pres; -+ if (__clk_determine_rate(parent, &req_parent)) -+ continue; -+ -+ clk_sama7g5_master_best_diff(req, parent, req_parent.rate, -+ &best_diff, &best_rate, pres); -+ if (!best_diff) -+ break; -+ } -+ -+ return 0; -+} -+ -+static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ unsigned long flags; -+ unsigned int pres; -+ -+ pres = DIV_ROUND_CLOSEST(parent_rate, rate); -+ if (pres > MASTER_PRES_MAX) -+ return -EINVAL; -+ -+ else if (pres == 3) -+ pres = MASTER_PRES_MAX; -+ else -+ pres = ffs(pres) - 1; -+ -+ spin_lock_irqsave(master->lock, flags); -+ regmap_update_bits(master->regmap, master->layout->offset, -+ (MASTER_PRES_MASK << master->layout->pres_shift), -+ (pres << master->layout->pres_shift)); -+ -+ while (!clk_master_ready(master)) -+ cpu_relax(); -+ spin_unlock_irqrestore(master->lock, flags); -+ -+ return 0; -+} -+ -+static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ const struct clk_master_characteristics *characteristics = -+ master->characteristics; -+ unsigned long flags; -+ unsigned int val, pres; -+ -+ spin_lock_irqsave(master->lock, flags); -+ regmap_read(master->regmap, master->layout->offset, &val); -+ spin_unlock_irqrestore(master->lock, flags); -+ -+ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; -+ if (pres == 3 && characteristics->have_div3_pres) -+ pres = 3; -+ else -+ pres = (1 << pres); -+ -+ return DIV_ROUND_CLOSEST_ULL(parent_rate, pres); -+} -+ -+static u8 clk_master_pres_get_parent(struct clk_hw *hw) - { - struct clk_master *master = to_clk_master(hw); -+ unsigned long flags; - unsigned int mckr; - -+ spin_lock_irqsave(master->lock, flags); - regmap_read(master->regmap, master->layout->offset, &mckr); -+ spin_unlock_irqrestore(master->lock, flags); - - return mckr & AT91_PMC_CSS; - } - --static const struct clk_ops master_ops = { -+static const struct clk_ops master_pres_ops = { - .prepare = clk_master_prepare, - .is_prepared = clk_master_is_prepared, -- .recalc_rate = clk_master_recalc_rate, -- .get_parent = clk_master_get_parent, -+ .recalc_rate = clk_master_pres_recalc_rate, -+ .get_parent = clk_master_pres_get_parent, - }; - --struct clk_hw * __init --at91_clk_register_master(struct regmap *regmap, -+static const struct clk_ops master_pres_ops_chg = { -+ .prepare = clk_master_prepare, -+ .is_prepared = clk_master_is_prepared, -+ .determine_rate = clk_master_pres_determine_rate, -+ .recalc_rate = clk_master_pres_recalc_rate, -+ .get_parent = clk_master_pres_get_parent, -+ .set_rate = clk_master_pres_set_rate, -+}; -+ -+static struct clk_hw * __init -+at91_clk_register_master_internal(struct regmap *regmap, - const char *name, int num_parents, - const char **parent_names, - const struct clk_master_layout *layout, -- const struct clk_master_characteristics *characteristics) -+ const struct clk_master_characteristics *characteristics, -+ const struct clk_ops *ops, spinlock_t *lock, u32 flags, -+ int chg_pid) - { - struct clk_master *master; - struct clk_init_data init; - struct clk_hw *hw; - int ret; - -- if (!name || !num_parents || !parent_names) -+ if (!name || !num_parents || !parent_names || !lock) - return ERR_PTR(-EINVAL); - - master = kzalloc(sizeof(*master), GFP_KERNEL); -@@ -142,15 +368,17 @@ at91_clk_register_master(struct regmap * - return ERR_PTR(-ENOMEM); - - init.name = name; -- init.ops = &master_ops; -+ init.ops = ops; - init.parent_names = parent_names; - init.num_parents = num_parents; -- init.flags = 0; -+ init.flags = flags; - - master->hw.init = &init; - master->layout = layout; - master->characteristics = characteristics; - master->regmap = regmap; -+ master->chg_pid = chg_pid; -+ master->lock = lock; - - hw = &master->hw; - ret = clk_hw_register(NULL, &master->hw); -@@ -162,37 +390,54 @@ at91_clk_register_master(struct regmap * - return hw; - } - --static unsigned long --clk_sama7g5_master_recalc_rate(struct clk_hw *hw, -- unsigned long parent_rate) -+struct clk_hw * __init -+at91_clk_register_master_pres(struct regmap *regmap, -+ const char *name, int num_parents, -+ const char **parent_names, -+ const struct clk_master_layout *layout, -+ const struct clk_master_characteristics *characteristics, -+ spinlock_t *lock, u32 flags, int chg_pid) - { -- struct clk_master *master = to_clk_master(hw); -+ const struct clk_ops *ops; - -- return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); -+ if (flags & CLK_SET_RATE_GATE) -+ ops = &master_pres_ops; -+ else -+ ops = &master_pres_ops_chg; -+ -+ return at91_clk_register_master_internal(regmap, name, num_parents, -+ parent_names, layout, -+ characteristics, ops, -+ lock, flags, chg_pid); - } - --static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, -- struct clk_hw *parent, -- unsigned long parent_rate, -- long *best_rate, -- long *best_diff, -- u32 div) -+struct clk_hw * __init -+at91_clk_register_master_div(struct regmap *regmap, -+ const char *name, const char *parent_name, -+ const struct clk_master_layout *layout, -+ const struct clk_master_characteristics *characteristics, -+ spinlock_t *lock, u32 flags) - { -- unsigned long tmp_rate, tmp_diff; -+ const struct clk_ops *ops; - -- if (div == MASTER_PRES_MAX) -- tmp_rate = parent_rate / 3; -+ if (flags & CLK_SET_RATE_GATE) -+ ops = &master_div_ops; - else -- tmp_rate = parent_rate >> div; -+ ops = &master_div_ops_chg; - -- tmp_diff = abs(req->rate - tmp_rate); -+ return at91_clk_register_master_internal(regmap, name, 1, -+ &parent_name, layout, -+ characteristics, ops, -+ lock, flags, -EINVAL); -+} - -- if (*best_diff < 0 || *best_diff >= tmp_diff) { -- *best_rate = tmp_rate; -- *best_diff = tmp_diff; -- req->best_parent_rate = parent_rate; -- req->best_parent_hw = parent; -- } -+static unsigned long -+clk_sama7g5_master_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ -+ return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); - } - - static int clk_sama7g5_master_determine_rate(struct clk_hw *hw, ---- a/drivers/clk/at91/dt-compat.c -+++ b/drivers/clk/at91/dt-compat.c -@@ -24,6 +24,8 @@ - - #define GCK_INDEX_DT_AUDIO_PLL 5 - -+static DEFINE_SPINLOCK(mck_lock); -+ - #ifdef CONFIG_HAVE_AT91_AUDIO_PLL - static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np) - { -@@ -388,9 +390,16 @@ of_at91_clk_master_setup(struct device_n - if (IS_ERR(regmap)) - return; - -- hw = at91_clk_register_master(regmap, name, num_parents, -- parent_names, layout, -- characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents, -+ parent_names, layout, -+ characteristics, &mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto out_free_characteristics; -+ -+ hw = at91_clk_register_master_div(regmap, name, "masterck_pres", -+ layout, characteristics, -+ &mck_lock, CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto out_free_characteristics; - ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -155,10 +155,18 @@ at91_clk_register_sam9x5_main(struct reg - const char **parent_names, int num_parents); - - struct clk_hw * __init --at91_clk_register_master(struct regmap *regmap, const char *name, -- int num_parents, const char **parent_names, -- const struct clk_master_layout *layout, -- const struct clk_master_characteristics *characteristics); -+at91_clk_register_master_pres(struct regmap *regmap, const char *name, -+ int num_parents, const char **parent_names, -+ const struct clk_master_layout *layout, -+ const struct clk_master_characteristics *characteristics, -+ spinlock_t *lock, u32 flags, int chg_pid); -+ -+struct clk_hw * __init -+at91_clk_register_master_div(struct regmap *regmap, const char *name, -+ const char *parent_names, -+ const struct clk_master_layout *layout, -+ const struct clk_master_characteristics *characteristics, -+ spinlock_t *lock, u32 flags); - - struct clk_hw * __init - at91_clk_sama7g5_register_master(struct regmap *regmap, ---- a/drivers/clk/at91/sam9x60.c -+++ b/drivers/clk/at91/sam9x60.c -@@ -8,6 +8,7 @@ - #include "pmc.h" - - static DEFINE_SPINLOCK(pmc_pll_lock); -+static DEFINE_SPINLOCK(mck_lock); - - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 140000000, .max = 200000000 }, -@@ -76,11 +77,11 @@ static const struct { - char *p; - u8 id; - } sam9x60_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, -- { .n = "qspick", .p = "masterck", .id = 19 }, -+ { .n = "qspick", .p = "masterck_div", .id = 19 }, - }; - - static const struct { -@@ -268,9 +269,17 @@ static void __init sam9x60_pmc_setup(str - parent_names[0] = md_slck_name; - parent_names[1] = "mainck"; - parent_names[2] = "pllack_divck"; -- hw = at91_clk_register_master(regmap, "masterck", 3, parent_names, -- &sam9x60_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3, -+ parent_names, &sam9x60_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", &sam9x60_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -286,7 +295,7 @@ static void __init sam9x60_pmc_setup(str - parent_names[0] = md_slck_name; - parent_names[1] = td_slck_name; - parent_names[2] = "mainck"; -- parent_names[3] = "masterck"; -+ parent_names[3] = "masterck_div"; - parent_names[4] = "pllack_divck"; - parent_names[5] = "upllck_divck"; - for (i = 0; i < 2; i++) { -@@ -318,7 +327,7 @@ static void __init sam9x60_pmc_setup(str - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &sam9x60_pcr_layout, - sam9x60_periphck[i].n, -- "masterck", -+ "masterck_div", - sam9x60_periphck[i].id, - &range, INT_MIN); - if (IS_ERR(hw)) ---- a/drivers/clk/at91/sama5d2.c -+++ b/drivers/clk/at91/sama5d2.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(mck_lock); -+ - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 124000000, .max = 166000000 }, - .divisors = { 1, 2, 4, 3 }, -@@ -40,14 +42,14 @@ static const struct { - char *p; - u8 id; - } sama5d2_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -- { .n = "lcdck", .p = "masterck", .id = 3 }, -- { .n = "uhpck", .p = "usbck", .id = 6 }, -- { .n = "udpck", .p = "usbck", .id = 7 }, -- { .n = "pck0", .p = "prog0", .id = 8 }, -- { .n = "pck1", .p = "prog1", .id = 9 }, -- { .n = "pck2", .p = "prog2", .id = 10 }, -- { .n = "iscck", .p = "masterck", .id = 18 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, -+ { .n = "lcdck", .p = "masterck_div", .id = 3 }, -+ { .n = "uhpck", .p = "usbck", .id = 6 }, -+ { .n = "udpck", .p = "usbck", .id = 7 }, -+ { .n = "pck0", .p = "prog0", .id = 8 }, -+ { .n = "pck1", .p = "prog1", .id = 9 }, -+ { .n = "pck2", .p = "prog2", .id = 10 }, -+ { .n = "iscck", .p = "masterck_div", .id = 18 }, - }; - - static const struct { -@@ -235,15 +237,25 @@ static void __init sama5d2_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91sam9x5_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - - sama5d2_pmc->chws[PMC_MCK] = hw; - -- hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck"); -+ hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); - if (IS_ERR(hw)) - goto err_free; - -@@ -259,7 +271,7 @@ static void __init sama5d2_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - parent_names[5] = "audiopll_pmcck"; - for (i = 0; i < 3; i++) { - char name[6]; -@@ -290,7 +302,7 @@ static void __init sama5d2_pmc_setup(str - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &sama5d2_pcr_layout, - sama5d2_periphck[i].n, -- "masterck", -+ "masterck_div", - sama5d2_periphck[i].id, - &range, INT_MIN); - if (IS_ERR(hw)) -@@ -317,7 +329,7 @@ static void __init sama5d2_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - parent_names[5] = "audiopll_pmcck"; - for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) { - hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, ---- a/drivers/clk/at91/sama5d3.c -+++ b/drivers/clk/at91/sama5d3.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(mck_lock); -+ - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 0, .max = 166000000 }, - .divisors = { 1, 2, 4, 3 }, -@@ -40,14 +42,14 @@ static const struct { - char *p; - u8 id; - } sama5d3_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -- { .n = "lcdck", .p = "masterck", .id = 3 }, -- { .n = "smdck", .p = "smdclk", .id = 4 }, -- { .n = "uhpck", .p = "usbck", .id = 6 }, -- { .n = "udpck", .p = "usbck", .id = 7 }, -- { .n = "pck0", .p = "prog0", .id = 8 }, -- { .n = "pck1", .p = "prog1", .id = 9 }, -- { .n = "pck2", .p = "prog2", .id = 10 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, -+ { .n = "lcdck", .p = "masterck_div", .id = 3 }, -+ { .n = "smdck", .p = "smdclk", .id = 4 }, -+ { .n = "uhpck", .p = "usbck", .id = 6 }, -+ { .n = "udpck", .p = "usbck", .id = 7 }, -+ { .n = "pck0", .p = "prog0", .id = 8 }, -+ { .n = "pck1", .p = "prog1", .id = 9 }, -+ { .n = "pck2", .p = "prog2", .id = 10 }, - }; - - static const struct { -@@ -170,9 +172,19 @@ static void __init sama5d3_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91sam9x5_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -192,7 +204,7 @@ static void __init sama5d3_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - for (i = 0; i < 3; i++) { - char name[6]; - -@@ -222,7 +234,7 @@ static void __init sama5d3_pmc_setup(str - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &sama5d3_pcr_layout, - sama5d3_periphck[i].n, -- "masterck", -+ "masterck_div", - sama5d3_periphck[i].id, - &sama5d3_periphck[i].r, - INT_MIN); ---- a/drivers/clk/at91/sama5d4.c -+++ b/drivers/clk/at91/sama5d4.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(mck_lock); -+ - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 125000000, .max = 200000000 }, - .divisors = { 1, 2, 4, 3 }, -@@ -39,14 +41,14 @@ static const struct { - char *p; - u8 id; - } sama5d4_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -- { .n = "lcdck", .p = "masterck", .id = 3 }, -- { .n = "smdck", .p = "smdclk", .id = 4 }, -- { .n = "uhpck", .p = "usbck", .id = 6 }, -- { .n = "udpck", .p = "usbck", .id = 7 }, -- { .n = "pck0", .p = "prog0", .id = 8 }, -- { .n = "pck1", .p = "prog1", .id = 9 }, -- { .n = "pck2", .p = "prog2", .id = 10 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, -+ { .n = "lcdck", .p = "masterck_div", .id = 3 }, -+ { .n = "smdck", .p = "smdclk", .id = 4 }, -+ { .n = "uhpck", .p = "usbck", .id = 6 }, -+ { .n = "udpck", .p = "usbck", .id = 7 }, -+ { .n = "pck0", .p = "prog0", .id = 8 }, -+ { .n = "pck1", .p = "prog1", .id = 9 }, -+ { .n = "pck2", .p = "prog2", .id = 10 }, - }; - - static const struct { -@@ -185,15 +187,25 @@ static void __init sama5d4_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91sam9x5_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - - sama5d4_pmc->chws[PMC_MCK] = hw; - -- hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck"); -+ hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); - if (IS_ERR(hw)) - goto err_free; - -@@ -215,7 +227,7 @@ static void __init sama5d4_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - for (i = 0; i < 3; i++) { - char name[6]; - -@@ -245,7 +257,7 @@ static void __init sama5d4_pmc_setup(str - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &sama5d4_pcr_layout, - sama5d4_periphck[i].n, -- "masterck", -+ "masterck_div", - sama5d4_periphck[i].id, - &range, INT_MIN); - if (IS_ERR(hw)) ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -32,6 +32,7 @@ - } while (0) - - static DEFINE_SPINLOCK(pmc_pll_lock); -+static DEFINE_SPINLOCK(pmc_mck0_lock); - static DEFINE_SPINLOCK(pmc_mckX_lock); - - /** -@@ -984,8 +985,16 @@ static void __init sama7g5_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "cpupll_divpmcck"; - parent_names[3] = "syspll_divpmcck"; -- hw = at91_clk_register_master(regmap, "mck0", 4, parent_names, -- &mck0_layout, &mck0_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names, -+ &mck0_layout, &mck0_characteristics, -+ &pmc_mck0_lock, -+ CLK_SET_RATE_PARENT, 0); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres", -+ &mck0_layout, &mck0_characteristics, -+ &pmc_mck0_lock, 0); - if (IS_ERR(hw)) - goto err_free; - diff --git a/target/linux/at91/patches-5.15/111-clk-at91-sama7g5-register-cpu-clock.patch b/target/linux/at91/patches-5.15/111-clk-at91-sama7g5-register-cpu-clock.patch deleted file mode 100644 index dc55e32027..0000000000 --- a/target/linux/at91/patches-5.15/111-clk-at91-sama7g5-register-cpu-clock.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 36e97c421dd9f866e31fe14bcb7af01334791890 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 19 Nov 2020 17:43:17 +0200 -Subject: [PATCH 111/247] clk: at91: sama7g5: register cpu clock - -Register CPU clock as being the master clock prescaler. This would -be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider -between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the -frequencies supported by SAMA7G5 could be directly received from -CPUPLL + master clock prescaler and the extra divider would do no work in -case it would be enabled. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 13 ++++++------- - include/dt-bindings/clock/at91.h | 1 + - 2 files changed, 7 insertions(+), 7 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(str - if (IS_ERR(regmap)) - return; - -- sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1, -+ sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1, - nck(sama7g5_systemck), - nck(sama7g5_periphck), - nck(sama7g5_gck), 8); -@@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(str - } - } - -- parent_names[0] = md_slck_name; -- parent_names[1] = "mainck"; -- parent_names[2] = "cpupll_divpmcck"; -- parent_names[3] = "syspll_divpmcck"; -- hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names, -+ parent_names[0] = "cpupll_divpmcck"; -+ hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names, - &mck0_layout, &mck0_characteristics, - &pmc_mck0_lock, - CLK_SET_RATE_PARENT, 0); - if (IS_ERR(hw)) - goto err_free; - -- hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres", -+ sama7g5_pmc->chws[PMC_CPU] = hw; -+ -+ hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", - &mck0_layout, &mck0_characteristics, - &pmc_mck0_lock, 0); - if (IS_ERR(hw)) ---- a/include/dt-bindings/clock/at91.h -+++ b/include/dt-bindings/clock/at91.h -@@ -34,6 +34,7 @@ - #define PMC_AUDIOPMCPLL (PMC_MAIN + 6) - #define PMC_AUDIOIOPLL (PMC_MAIN + 7) - #define PMC_ETHPLL (PMC_MAIN + 8) -+#define PMC_CPU (PMC_MAIN + 9) - - #ifndef AT91_PMC_MOSCS - #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ diff --git a/target/linux/at91/patches-5.15/112-clk-at91-Fix-the-declaration-of-the-clocks.patch b/target/linux/at91/patches-5.15/112-clk-at91-Fix-the-declaration-of-the-clocks.patch deleted file mode 100644 index e989ed207e..0000000000 --- a/target/linux/at91/patches-5.15/112-clk-at91-Fix-the-declaration-of-the-clocks.patch +++ /dev/null @@ -1,181 +0,0 @@ -From 5a25e2437af0db535b17da352fb16680a8dfdeda Mon Sep 17 00:00:00 2001 -From: Tudor Ambarus -Date: Wed, 3 Feb 2021 17:43:32 +0200 -Subject: [PATCH 112/247] clk: at91: Fix the declaration of the clocks - -These are all "early clocks" that require initialization just at -of_clk_init() time. Use CLK_OF_DECLARE() to declare them. - -This also fixes a problem that was spotted when fw_devlink was -set to 'on' by default: the boards failed to boot. The reason is -that CLK_OF_DECLARE_DRIVER() clears the OF_POPULATED and causes -the consumers of the clock to be postponed by fw_devlink until -the second initialization routine of the clock has been completed. -One of the consumers of the clock is the timer, which is used as a -clocksource, and needs the clock initialized early. Postponing the -timers caused the fail at boot. - -Signed-off-by: Tudor Ambarus -Link: https://lore.kernel.org/r/20210203154332.470587-1-tudor.ambarus@microchip.com -Acked-by: Saravana Kannan -Tested-by: Eugen Hristev -Acked-by: Nicolas Ferre -Reviewed-by: Claudiu Beznea -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/at91rm9200.c | 3 +-- - drivers/clk/at91/at91sam9260.c | 16 ++++++++-------- - drivers/clk/at91/at91sam9g45.c | 3 +-- - drivers/clk/at91/at91sam9n12.c | 3 +-- - drivers/clk/at91/at91sam9rl.c | 3 ++- - drivers/clk/at91/at91sam9x5.c | 20 ++++++++++---------- - drivers/clk/at91/sama5d2.c | 3 ++- - drivers/clk/at91/sama5d3.c | 2 +- - drivers/clk/at91/sama5d4.c | 3 ++- - 9 files changed, 28 insertions(+), 28 deletions(-) - ---- a/drivers/clk/at91/at91rm9200.c -+++ b/drivers/clk/at91/at91rm9200.c -@@ -215,5 +215,4 @@ err_free: - * deferring properly. Once this is fixed, this can be switched to a platform - * driver. - */ --CLK_OF_DECLARE_DRIVER(at91rm9200_pmc, "atmel,at91rm9200-pmc", -- at91rm9200_pmc_setup); -+CLK_OF_DECLARE(at91rm9200_pmc, "atmel,at91rm9200-pmc", at91rm9200_pmc_setup); ---- a/drivers/clk/at91/at91sam9260.c -+++ b/drivers/clk/at91/at91sam9260.c -@@ -491,26 +491,26 @@ static void __init at91sam9260_pmc_setup - { - at91sam926x_pmc_setup(np, &at91sam9260_data); - } --CLK_OF_DECLARE_DRIVER(at91sam9260_pmc, "atmel,at91sam9260-pmc", -- at91sam9260_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9260_pmc, "atmel,at91sam9260-pmc", at91sam9260_pmc_setup); - - static void __init at91sam9261_pmc_setup(struct device_node *np) - { - at91sam926x_pmc_setup(np, &at91sam9261_data); - } --CLK_OF_DECLARE_DRIVER(at91sam9261_pmc, "atmel,at91sam9261-pmc", -- at91sam9261_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9261_pmc, "atmel,at91sam9261-pmc", at91sam9261_pmc_setup); - - static void __init at91sam9263_pmc_setup(struct device_node *np) - { - at91sam926x_pmc_setup(np, &at91sam9263_data); - } --CLK_OF_DECLARE_DRIVER(at91sam9263_pmc, "atmel,at91sam9263-pmc", -- at91sam9263_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9263_pmc, "atmel,at91sam9263-pmc", at91sam9263_pmc_setup); - - static void __init at91sam9g20_pmc_setup(struct device_node *np) - { - at91sam926x_pmc_setup(np, &at91sam9g20_data); - } --CLK_OF_DECLARE_DRIVER(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", -- at91sam9g20_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", at91sam9g20_pmc_setup); ---- a/drivers/clk/at91/at91sam9g45.c -+++ b/drivers/clk/at91/at91sam9g45.c -@@ -228,5 +228,4 @@ err_free: - * The TCB is used as the clocksource so its clock is needed early. This means - * this can't be a platform driver. - */ --CLK_OF_DECLARE_DRIVER(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", -- at91sam9g45_pmc_setup); -+CLK_OF_DECLARE(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", at91sam9g45_pmc_setup); ---- a/drivers/clk/at91/at91sam9n12.c -+++ b/drivers/clk/at91/at91sam9n12.c -@@ -255,5 +255,4 @@ err_free: - * The TCB is used as the clocksource so its clock is needed early. This means - * this can't be a platform driver. - */ --CLK_OF_DECLARE_DRIVER(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", -- at91sam9n12_pmc_setup); -+CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup); ---- a/drivers/clk/at91/at91sam9rl.c -+++ b/drivers/clk/at91/at91sam9rl.c -@@ -186,4 +186,5 @@ static void __init at91sam9rl_pmc_setup( - err_free: - kfree(at91sam9rl_pmc); - } --CLK_OF_DECLARE_DRIVER(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup); ---- a/drivers/clk/at91/at91sam9x5.c -+++ b/drivers/clk/at91/at91sam9x5.c -@@ -302,33 +302,33 @@ static void __init at91sam9g15_pmc_setup - { - at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true); - } --CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", -- at91sam9g15_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", at91sam9g15_pmc_setup); - - static void __init at91sam9g25_pmc_setup(struct device_node *np) - { - at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false); - } --CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", -- at91sam9g25_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", at91sam9g25_pmc_setup); - - static void __init at91sam9g35_pmc_setup(struct device_node *np) - { - at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true); - } --CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", -- at91sam9g35_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", at91sam9g35_pmc_setup); - - static void __init at91sam9x25_pmc_setup(struct device_node *np) - { - at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false); - } --CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", -- at91sam9x25_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", at91sam9x25_pmc_setup); - - static void __init at91sam9x35_pmc_setup(struct device_node *np) - { - at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true); - } --CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", -- at91sam9x35_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", at91sam9x35_pmc_setup); ---- a/drivers/clk/at91/sama5d2.c -+++ b/drivers/clk/at91/sama5d2.c -@@ -372,4 +372,5 @@ static void __init sama5d2_pmc_setup(str - err_free: - kfree(sama5d2_pmc); - } --CLK_OF_DECLARE_DRIVER(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup); -+ -+CLK_OF_DECLARE(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup); ---- a/drivers/clk/at91/sama5d3.c -+++ b/drivers/clk/at91/sama5d3.c -@@ -255,4 +255,4 @@ err_free: - * The TCB is used as the clocksource so its clock is needed early. This means - * this can't be a platform driver. - */ --CLK_OF_DECLARE_DRIVER(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup); -+CLK_OF_DECLARE(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup); ---- a/drivers/clk/at91/sama5d4.c -+++ b/drivers/clk/at91/sama5d4.c -@@ -286,4 +286,5 @@ static void __init sama5d4_pmc_setup(str - err_free: - kfree(sama5d4_pmc); - } --CLK_OF_DECLARE_DRIVER(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup); -+ -+CLK_OF_DECLARE(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup); diff --git a/target/linux/at91/patches-5.15/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch b/target/linux/at91/patches-5.15/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch deleted file mode 100644 index f3ebee10fe..0000000000 --- a/target/linux/at91/patches-5.15/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 268b36c42b7d1e480dd56ecfec626a46f4b5975e Mon Sep 17 00:00:00 2001 -From: Bhaskar Chowdhury -Date: Sat, 13 Mar 2021 11:02:22 +0530 -Subject: [PATCH 113/247] clk: at91: Trivial typo fixes in the file sama7g5.c - -s/critial/critical/ ......two different places -s/parrent/parent/ - -Signed-off-by: Bhaskar Chowdhury -Link: https://lore.kernel.org/r/20210313053222.14706-1-unixbhaskar@gmail.com -Acked-by: Randy Dunlap -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -166,7 +166,7 @@ static const struct { - .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - /* -- * This feeds syspll_divpmcck which may feed critial parts -+ * This feeds syspll_divpmcck which may feed critical parts - * of the systems like timers. Therefore it should not be - * disabled. - */ -@@ -178,7 +178,7 @@ static const struct { - .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - /* -- * This may feed critial parts of the systems like timers. -+ * This may feed critical parts of the systems like timers. - * Therefore it should not be disabled. - */ - .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, -@@ -455,7 +455,7 @@ static const struct { - * @pp: PLL parents - * @pp_mux_table: PLL parents mux table - * @r: clock output range -- * @pp_chg_id: id in parrent array of changeable PLL parent -+ * @pp_chg_id: id in parent array of changeable PLL parent - * @pp_count: PLL parents count - * @id: clock id - */ diff --git a/target/linux/at91/patches-5.15/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch b/target/linux/at91/patches-5.15/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch deleted file mode 100644 index a9ceda533b..0000000000 --- a/target/linux/at91/patches-5.15/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 9997227090cf529675aeb775585ec9f6c2f0f131 Mon Sep 17 00:00:00 2001 -From: Randy Dunlap -Date: Thu, 19 Aug 2021 15:32:37 -0700 -Subject: [PATCH 114/247] clk: at91: sama7g5: remove all kernel-doc & - kernel-doc warnings - -Remove all "/**" kernel-doc markers from sama7g5.c since they are -all internal to this driver source file only. -This eliminates 14 warnings that were reported by the kernel test robot. - -Signed-off-by: Randy Dunlap -Reported-by: kernel test robot -Cc: Claudiu Beznea -Cc: Michael Turquette -Cc: Stephen Boyd -Cc: Eugen Hristev -Cc: linux-clk@vger.kernel.org -Cc: linux-arm-kernel@lists.infradead.org -Link: https://lore.kernel.org/r/20210819223237.20115-1-rdunlap@infradead.org -Reviewed-by: Claudiu Beznea -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 14 +++++++------- - 1 file changed, 7 insertions(+), 7 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -35,7 +35,7 @@ static DEFINE_SPINLOCK(pmc_pll_lock); - static DEFINE_SPINLOCK(pmc_mck0_lock); - static DEFINE_SPINLOCK(pmc_mckX_lock); - --/** -+/* - * PLL clocks identifiers - * @PLL_ID_CPU: CPU PLL identifier - * @PLL_ID_SYS: System PLL identifier -@@ -56,7 +56,7 @@ enum pll_ids { - PLL_ID_MAX, - }; - --/** -+/* - * PLL type identifiers - * @PLL_TYPE_FRAC: fractional PLL identifier - * @PLL_TYPE_DIV: divider PLL identifier -@@ -118,7 +118,7 @@ static const struct clk_pll_characterist - .output = pll_outputs, - }; - --/** -+/* - * PLL clocks description - * @n: clock name - * @p: clock parent -@@ -285,7 +285,7 @@ static const struct { - }, - }; - --/** -+/* - * Master clock (MCK[1..4]) description - * @n: clock name - * @ep: extra parents names array -@@ -337,7 +337,7 @@ static const struct { - .c = 1, }, - }; - --/** -+/* - * System clock description - * @n: clock name - * @p: clock parent name -@@ -361,7 +361,7 @@ static const struct { - /* Mux table for programmable clocks. */ - static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, }; - --/** -+/* - * Peripheral clock description - * @n: clock name - * @p: clock parent name -@@ -449,7 +449,7 @@ static const struct { - { .n = "uhphs_clk", .p = "mck1", .id = 106, }, - }; - --/** -+/* - * Generic clock description - * @n: clock name - * @pp: PLL parents diff --git a/target/linux/at91/patches-5.15/115-net-macb-add-userio-bits-as-platform-configuration.patch b/target/linux/at91/patches-5.15/115-net-macb-add-userio-bits-as-platform-configuration.patch deleted file mode 100644 index 79e7e62440..0000000000 --- a/target/linux/at91/patches-5.15/115-net-macb-add-userio-bits-as-platform-configuration.patch +++ /dev/null @@ -1,179 +0,0 @@ -From 89f37ac2780d113d3c17d329726c0e92a1400744 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 9 Dec 2020 15:03:32 +0200 -Subject: [PATCH 115/247] net: macb: add userio bits as platform configuration - -This is necessary for SAMA7G5 as it uses different values for -PHY interface and also introduces hdfctlen bit. - -Signed-off-by: Claudiu Beznea -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb.h | 10 +++++++++ - drivers/net/ethernet/cadence/macb_main.c | 28 ++++++++++++++++++++---- - 2 files changed, 34 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/cadence/macb.h -+++ b/drivers/net/ethernet/cadence/macb.h -@@ -1104,6 +1104,14 @@ struct macb_pm_data { - u32 usrio; - }; - -+struct macb_usrio_config { -+ u32 mii; -+ u32 rmii; -+ u32 rgmii; -+ u32 refclk; -+ u32 hdfctlen; -+}; -+ - struct macb_config { - u32 caps; - unsigned int dma_burst_length; -@@ -1112,6 +1120,7 @@ struct macb_config { - struct clk **rx_clk, struct clk **tsu_clk); - int (*init)(struct platform_device *pdev); - int jumbo_max_len; -+ const struct macb_usrio_config *usrio; - }; - - struct tsu_incr { -@@ -1244,6 +1253,7 @@ struct macb { - u32 rx_intr_mask; - - struct macb_pm_data pm_data; -+ const struct macb_usrio_config *usrio; - }; - - #ifdef CONFIG_MACB_USE_HWSTAMP ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -3831,15 +3831,15 @@ static int macb_init(struct platform_dev - if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) { - val = 0; - if (phy_interface_mode_is_rgmii(bp->phy_interface)) -- val = GEM_BIT(RGMII); -+ val = bp->usrio->rgmii; - else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII && - (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) -- val = MACB_BIT(RMII); -+ val = bp->usrio->rmii; - else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) -- val = MACB_BIT(MII); -+ val = bp->usrio->mii; - - if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN) -- val |= MACB_BIT(CLKEN); -+ val |= bp->usrio->refclk; - - macb_or_gem_writel(bp, USRIO, val); - } -@@ -4357,6 +4357,13 @@ static int fu540_c000_init(struct platfo - return macb_init(pdev); - } - -+static const struct macb_usrio_config macb_default_usrio = { -+ .mii = MACB_BIT(MII), -+ .rmii = MACB_BIT(RMII), -+ .rgmii = GEM_BIT(RGMII), -+ .refclk = MACB_BIT(CLKEN), -+}; -+ - static const struct macb_config fu540_c000_config = { - .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | - MACB_CAPS_GEM_HAS_PTP, -@@ -4364,12 +4371,14 @@ static const struct macb_config fu540_c0 - .clk_init = fu540_c000_clk_init, - .init = fu540_c000_init, - .jumbo_max_len = 10240, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config at91sam9260_config = { - .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config sama5d3macb_config = { -@@ -4377,6 +4386,7 @@ static const struct macb_config sama5d3m - | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config pc302gem_config = { -@@ -4384,6 +4394,7 @@ static const struct macb_config pc302gem - .dma_burst_length = 16, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config sama5d2_config = { -@@ -4391,6 +4402,7 @@ static const struct macb_config sama5d2_ - .dma_burst_length = 16, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config sama5d3_config = { -@@ -4400,6 +4412,7 @@ static const struct macb_config sama5d3_ - .clk_init = macb_clk_init, - .init = macb_init, - .jumbo_max_len = 10240, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config sama5d4_config = { -@@ -4407,18 +4420,21 @@ static const struct macb_config sama5d4_ - .dma_burst_length = 4, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config emac_config = { - .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC, - .clk_init = at91ether_clk_init, - .init = at91ether_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config np4_config = { - .caps = MACB_CAPS_USRIO_DISABLED, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config zynqmp_config = { -@@ -4429,6 +4445,7 @@ static const struct macb_config zynqmp_c - .clk_init = macb_clk_init, - .init = macb_init, - .jumbo_max_len = 10240, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config zynq_config = { -@@ -4437,6 +4454,7 @@ static const struct macb_config zynq_con - .dma_burst_length = 16, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct of_device_id macb_dt_ids[] = { -@@ -4557,6 +4575,8 @@ static int macb_probe(struct platform_de - bp->wol |= MACB_WOL_HAS_MAGIC_PACKET; - device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET); - -+ bp->usrio = macb_config->usrio; -+ - spin_lock_init(&bp->lock); - - /* setup capabilities */ diff --git a/target/linux/at91/patches-5.15/116-net-macb-add-capability-to-not-set-the-clock-rate.patch b/target/linux/at91/patches-5.15/116-net-macb-add-capability-to-not-set-the-clock-rate.patch deleted file mode 100644 index 87dde7ef60..0000000000 --- a/target/linux/at91/patches-5.15/116-net-macb-add-capability-to-not-set-the-clock-rate.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 1b15259551b701f416aa024050a2e619860bd0d8 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 9 Dec 2020 15:03:33 +0200 -Subject: [PATCH 116/247] net: macb: add capability to not set the clock rate - -SAMA7G5's ethernet IPs TX clock could be provided by its generic clock or -by the external clock provided by the PHY. The internal IP logic divides -properly this clock depending on the link speed. The patch adds a new -capability so that macb_set_tx_clock() to not be called for IPs having -this capability (the clock rate, in case of generic clock, is set at the -boot time via device tree and the driver only enables it). - -Signed-off-by: Claudiu Beznea -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb.h | 1 + - drivers/net/ethernet/cadence/macb_main.c | 18 +++++++++--------- - 2 files changed, 10 insertions(+), 9 deletions(-) - ---- a/drivers/net/ethernet/cadence/macb.h -+++ b/drivers/net/ethernet/cadence/macb.h -@@ -658,6 +658,7 @@ - #define MACB_CAPS_GEM_HAS_PTP 0x00000040 - #define MACB_CAPS_BD_RD_PREFETCH 0x00000080 - #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 -+#define MACB_CAPS_CLK_HW_CHG 0x04000000 - #define MACB_CAPS_MACB_IS_EMAC 0x08000000 - #define MACB_CAPS_FIFO_MODE 0x10000000 - #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -457,15 +457,14 @@ static void macb_init_buffers(struct mac - - /** - * macb_set_tx_clk() - Set a clock to a new frequency -- * @clk: Pointer to the clock to change -+ * @bp: pointer to struct macb - * @speed: New frequency in Hz -- * @dev: Pointer to the struct net_device - */ --static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) -+static void macb_set_tx_clk(struct macb *bp, int speed) - { - long ferr, rate, rate_rounded; - -- if (!clk) -+ if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG)) - return; - - switch (speed) { -@@ -482,7 +481,7 @@ static void macb_set_tx_clk(struct clk * - return; - } - -- rate_rounded = clk_round_rate(clk, rate); -+ rate_rounded = clk_round_rate(bp->tx_clk, rate); - if (rate_rounded < 0) - return; - -@@ -492,11 +491,12 @@ static void macb_set_tx_clk(struct clk * - ferr = abs(rate_rounded - rate); - ferr = DIV_ROUND_UP(ferr, rate / 100000); - if (ferr > 5) -- netdev_warn(dev, "unable to generate target frequency: %ld Hz\n", -+ netdev_warn(bp->dev, -+ "unable to generate target frequency: %ld Hz\n", - rate); - -- if (clk_set_rate(clk, rate_rounded)) -- netdev_err(dev, "adjusting tx_clk failed.\n"); -+ if (clk_set_rate(bp->tx_clk, rate_rounded)) -+ netdev_err(bp->dev, "adjusting tx_clk failed.\n"); - } - - static void macb_validate(struct phylink_config *config, -@@ -649,7 +649,7 @@ static void macb_mac_link_up(struct phyl - if (rx_pause) - ctrl |= MACB_BIT(PAE); - -- macb_set_tx_clk(bp->tx_clk, speed, ndev); -+ macb_set_tx_clk(bp, speed); - - /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down - * cleared the pipeline and control registers. diff --git a/target/linux/at91/patches-5.15/117-net-macb-add-function-to-disable-all-macb-clocks.patch b/target/linux/at91/patches-5.15/117-net-macb-add-function-to-disable-all-macb-clocks.patch deleted file mode 100644 index a474f2a405..0000000000 --- a/target/linux/at91/patches-5.15/117-net-macb-add-function-to-disable-all-macb-clocks.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 935d9aae15ee245a1bc6e322cbef02566a8996cc Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 9 Dec 2020 15:03:34 +0200 -Subject: [PATCH 117/247] net: macb: add function to disable all macb clocks - -Add function to disable all macb clocks. - -Signed-off-by: Claudiu Beznea -Suggested-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb_main.c | 38 +++++++++++++----------- - 1 file changed, 21 insertions(+), 17 deletions(-) - ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -3606,6 +3606,20 @@ static void macb_probe_queues(void __iom - *num_queues = hweight32(*queue_mask); - } - -+static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk, -+ struct clk *rx_clk, struct clk *tsu_clk) -+{ -+ struct clk_bulk_data clks[] = { -+ { .clk = tsu_clk, }, -+ { .clk = rx_clk, }, -+ { .clk = pclk, }, -+ { .clk = hclk, }, -+ { .clk = tx_clk }, -+ }; -+ -+ clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks); -+} -+ - static int macb_clk_init(struct platform_device *pdev, struct clk **pclk, - struct clk **hclk, struct clk **tx_clk, - struct clk **rx_clk, struct clk **tsu_clk) -@@ -4668,11 +4682,7 @@ err_out_free_netdev: - free_netdev(dev); - - err_disable_clocks: -- clk_disable_unprepare(tx_clk); -- clk_disable_unprepare(hclk); -- clk_disable_unprepare(pclk); -- clk_disable_unprepare(rx_clk); -- clk_disable_unprepare(tsu_clk); -+ macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk); - pm_runtime_disable(&pdev->dev); - pm_runtime_set_suspended(&pdev->dev); - pm_runtime_dont_use_autosuspend(&pdev->dev); -@@ -4697,11 +4707,8 @@ static int macb_remove(struct platform_d - pm_runtime_disable(&pdev->dev); - pm_runtime_dont_use_autosuspend(&pdev->dev); - if (!pm_runtime_suspended(&pdev->dev)) { -- clk_disable_unprepare(bp->tx_clk); -- clk_disable_unprepare(bp->hclk); -- clk_disable_unprepare(bp->pclk); -- clk_disable_unprepare(bp->rx_clk); -- clk_disable_unprepare(bp->tsu_clk); -+ macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, -+ bp->rx_clk, bp->tsu_clk); - pm_runtime_set_suspended(&pdev->dev); - } - phylink_destroy(bp->phylink); -@@ -4880,13 +4887,10 @@ static int __maybe_unused macb_runtime_s - struct net_device *netdev = dev_get_drvdata(dev); - struct macb *bp = netdev_priv(netdev); - -- if (!(device_may_wakeup(dev))) { -- clk_disable_unprepare(bp->tx_clk); -- clk_disable_unprepare(bp->hclk); -- clk_disable_unprepare(bp->pclk); -- clk_disable_unprepare(bp->rx_clk); -- } -- clk_disable_unprepare(bp->tsu_clk); -+ if (!(device_may_wakeup(dev))) -+ macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk); -+ else -+ macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk); - - return 0; - } diff --git a/target/linux/at91/patches-5.15/118-net-macb-unprepare-clocks-in-case-of-failure.patch b/target/linux/at91/patches-5.15/118-net-macb-unprepare-clocks-in-case-of-failure.patch deleted file mode 100644 index 7456cc6c52..0000000000 --- a/target/linux/at91/patches-5.15/118-net-macb-unprepare-clocks-in-case-of-failure.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 9692c07ee8bf8f68b74d553d861d092e33264781 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 9 Dec 2020 15:03:35 +0200 -Subject: [PATCH 118/247] net: macb: unprepare clocks in case of failure - -Unprepare clocks in case of any failure in fu540_c000_clk_init(). - -Fixes: c218ad559020 ("macb: Add support for SiFive FU540-C000") -Signed-off-by: Claudiu Beznea -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb_main.c | 24 ++++++++++++++++++------ - 1 file changed, 18 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -4338,8 +4338,10 @@ static int fu540_c000_clk_init(struct pl - return err; - - mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL); -- if (!mgmt) -- return -ENOMEM; -+ if (!mgmt) { -+ err = -ENOMEM; -+ goto err_disable_clks; -+ } - - init.name = "sifive-gemgxl-mgmt"; - init.ops = &fu540_c000_ops; -@@ -4350,16 +4352,26 @@ static int fu540_c000_clk_init(struct pl - mgmt->hw.init = &init; - - *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw); -- if (IS_ERR(*tx_clk)) -- return PTR_ERR(*tx_clk); -+ if (IS_ERR(*tx_clk)) { -+ err = PTR_ERR(*tx_clk); -+ goto err_disable_clks; -+ } - - err = clk_prepare_enable(*tx_clk); -- if (err) -+ if (err) { - dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); -- else -+ *tx_clk = NULL; -+ goto err_disable_clks; -+ } else { - dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name); -+ } - - return 0; -+ -+err_disable_clks: -+ macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk); -+ -+ return err; - } - - static int fu540_c000_init(struct platform_device *pdev) diff --git a/target/linux/at91/patches-5.15/119-net-macb-add-support-for-sama7g5-gem-interface.patch b/target/linux/at91/patches-5.15/119-net-macb-add-support-for-sama7g5-gem-interface.patch deleted file mode 100644 index 64abd3d6c0..0000000000 --- a/target/linux/at91/patches-5.15/119-net-macb-add-support-for-sama7g5-gem-interface.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 0085cd8576ceeaddeedf973b939b41ba96e3f77c Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 9 Dec 2020 15:03:38 +0200 -Subject: [PATCH 119/247] net: macb: add support for sama7g5 gem interface - -Add support for SAMA7G5 gigabit ethernet interface. - -Signed-off-by: Claudiu Beznea -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb_main.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -4390,6 +4390,14 @@ static const struct macb_usrio_config ma - .refclk = MACB_BIT(CLKEN), - }; - -+static const struct macb_usrio_config sama7g5_usrio = { -+ .mii = 0, -+ .rmii = 1, -+ .rgmii = 2, -+ .refclk = BIT(2), -+ .hdfctlen = BIT(6), -+}; -+ - static const struct macb_config fu540_c000_config = { - .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | - MACB_CAPS_GEM_HAS_PTP, -@@ -4483,6 +4491,14 @@ static const struct macb_config zynq_con - .usrio = &macb_default_usrio, - }; - -+static const struct macb_config sama7g5_gem_config = { -+ .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG, -+ .dma_burst_length = 16, -+ .clk_init = macb_clk_init, -+ .init = macb_init, -+ .usrio = &sama7g5_usrio, -+}; -+ - static const struct of_device_id macb_dt_ids[] = { - { .compatible = "cdns,at32ap7000-macb" }, - { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, -@@ -4500,6 +4516,7 @@ static const struct of_device_id macb_dt - { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, - { .compatible = "cdns,zynq-gem", .data = &zynq_config }, - { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, -+ { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, macb_dt_ids); diff --git a/target/linux/at91/patches-5.15/120-net-macb-add-support-for-sama7g5-emac-interface.patch b/target/linux/at91/patches-5.15/120-net-macb-add-support-for-sama7g5-emac-interface.patch deleted file mode 100644 index 50d31f736b..0000000000 --- a/target/linux/at91/patches-5.15/120-net-macb-add-support-for-sama7g5-emac-interface.patch +++ /dev/null @@ -1,39 +0,0 @@ -From a42f90357cfcfcf5cdade4594ad79a1eae633a9f Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 9 Dec 2020 15:03:39 +0200 -Subject: [PATCH 120/247] net: macb: add support for sama7g5 emac interface - -Add support for SAMA7G5 10/100Mbps interface. - -Signed-off-by: Claudiu Beznea -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb_main.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -4499,6 +4499,14 @@ static const struct macb_config sama7g5_ - .usrio = &sama7g5_usrio, - }; - -+static const struct macb_config sama7g5_emac_config = { -+ .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_USRIO_HAS_CLKEN, -+ .dma_burst_length = 16, -+ .clk_init = macb_clk_init, -+ .init = macb_init, -+ .usrio = &sama7g5_usrio, -+}; -+ - static const struct of_device_id macb_dt_ids[] = { - { .compatible = "cdns,at32ap7000-macb" }, - { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, -@@ -4517,6 +4525,7 @@ static const struct of_device_id macb_dt - { .compatible = "cdns,zynq-gem", .data = &zynq_config }, - { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, - { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, -+ { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, macb_dt_ids); diff --git a/target/linux/at91/patches-5.15/121-ASoC-pcm5102a-Make-codec-selectable.patch b/target/linux/at91/patches-5.15/121-ASoC-pcm5102a-Make-codec-selectable.patch deleted file mode 100644 index 8c918fd779..0000000000 --- a/target/linux/at91/patches-5.15/121-ASoC-pcm5102a-Make-codec-selectable.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 5ac0e1f5577b266543756521b1a749003b0f3686 Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Mon, 12 Oct 2020 17:19:11 +0300 -Subject: [PATCH 121/247] ASoC: pcm5102a: Make codec selectable - -The TI PCM5102A codec driver can be used with the generic sound card -drivers, so it should be selectable. For example, with the addition -of #sound-dai-cells = <0> property in DT, it can be used with simple/graph -card drivers. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20201012141911.3150996-1-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/codecs/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/sound/soc/codecs/Kconfig -+++ b/sound/soc/codecs/Kconfig -@@ -1007,7 +1007,7 @@ config SND_SOC_PCM3168A_SPI - select REGMAP_SPI - - config SND_SOC_PCM5102A -- tristate -+ tristate "Texas Instruments PCM5102A CODEC" - - config SND_SOC_PCM512x - tristate diff --git a/target/linux/at91/patches-5.15/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch b/target/linux/at91/patches-5.15/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch deleted file mode 100644 index 978b68184e..0000000000 --- a/target/linux/at91/patches-5.15/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch +++ /dev/null @@ -1,30 +0,0 @@ -From f4389949bf422fe04775c17b833100fa0e95ea68 Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Tue, 3 Nov 2020 12:05:54 +0200 -Subject: [PATCH 122/247] ASoC: atmel-i2s: do not warn if muxclk is missing - -Besides the fact that muxclk is optional, muxclk can be set using -assigned-clocks, removing the need to set it in driver. The warning is -thus unneeded, so we can transform it in a debug print, eventually to just -reflect that muxclk was not set by the driver. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20201103100554.1307190-1-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/atmel-i2s.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/sound/soc/atmel/atmel-i2s.c -+++ b/sound/soc/atmel/atmel-i2s.c -@@ -581,8 +581,8 @@ static int atmel_i2s_sama5d2_mck_init(st - err = PTR_ERR(muxclk); - if (err == -EPROBE_DEFER) - return -EPROBE_DEFER; -- dev_warn(dev->dev, -- "failed to get the I2S clock control: %d\n", err); -+ dev_dbg(dev->dev, -+ "failed to get the I2S clock control: %d\n", err); - return 0; - } - diff --git a/target/linux/at91/patches-5.15/123-regulator-mcp16502-add-linear_min_sel.patch b/target/linux/at91/patches-5.15/123-regulator-mcp16502-add-linear_min_sel.patch deleted file mode 100644 index ce97be4b77..0000000000 --- a/target/linux/at91/patches-5.15/123-regulator-mcp16502-add-linear_min_sel.patch +++ /dev/null @@ -1,25 +0,0 @@ -From f5a73f3bb600b96b6149f2115360e1d0d51fbac4 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 13 Nov 2020 17:21:07 +0200 -Subject: [PATCH 123/247] regulator: mcp16502: add linear_min_sel - -Selectors b/w zero and VDD_LOW_SEL are not valid. Use linear_min_sel. - -Fixes: 919261c03e7ca ("regulator: mcp16502: add regulator driver for MCP16502") -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605280870-32432-4-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/mcp16502.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/regulator/mcp16502.c -+++ b/drivers/regulator/mcp16502.c -@@ -93,6 +93,7 @@ static unsigned int mcp16502_of_map_mode - .owner = THIS_MODULE, \ - .n_voltages = MCP16502_VSEL + 1, \ - .linear_ranges = _ranges, \ -+ .linear_min_sel = VDD_LOW_SEL, \ - .n_linear_ranges = ARRAY_SIZE(_ranges), \ - .of_match = of_match_ptr(_name), \ - .of_map_mode = mcp16502_of_map_mode, \ diff --git a/target/linux/at91/patches-5.15/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch b/target/linux/at91/patches-5.15/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch deleted file mode 100644 index f371266c78..0000000000 --- a/target/linux/at91/patches-5.15/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 5295f4c122258a11fb6012b7e043248e681db5a2 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 13 Nov 2020 17:21:08 +0200 -Subject: [PATCH 124/247] regulator: mcp16502: adapt for get/set on other - registers - -MCP16502 have multiple registers for each regulator (as described -in enum mcp16502_reg). Adapt the code to be able to get/set all these -registers. This is necessary for the following commits. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605280870-32432-5-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/mcp16502.c | 43 ++++++++++++++++++++++-------------- - 1 file changed, 27 insertions(+), 16 deletions(-) - ---- a/drivers/regulator/mcp16502.c -+++ b/drivers/regulator/mcp16502.c -@@ -54,13 +54,9 @@ - * This function is useful for iterating over all regulators and accessing their - * registers in a generic way or accessing a regulator device by its id. - */ --#define MCP16502_BASE(i) (((i) + 1) << 4) -+#define MCP16502_REG_BASE(i, r) ((((i) + 1) << 4) + MCP16502_REG_##r) - #define MCP16502_STAT_BASE(i) ((i) + 5) - --#define MCP16502_OFFSET_MODE_A 0 --#define MCP16502_OFFSET_MODE_LPM 1 --#define MCP16502_OFFSET_MODE_HIB 2 -- - #define MCP16502_OPMODE_ACTIVE REGULATOR_MODE_NORMAL - #define MCP16502_OPMODE_LPM REGULATOR_MODE_IDLE - #define MCP16502_OPMODE_HIB REGULATOR_MODE_STANDBY -@@ -75,6 +71,23 @@ - #define MCP16502_MIN_REG 0x0 - #define MCP16502_MAX_REG 0x65 - -+/** -+ * enum mcp16502_reg - MCP16502 regulators's registers -+ * @MCP16502_REG_A: active state register -+ * @MCP16502_REG_LPM: low power mode state register -+ * @MCP16502_REG_HIB: hibernate state register -+ * @MCP16502_REG_SEQ: startup sequence register -+ * @MCP16502_REG_CFG: configuration register -+ */ -+enum mcp16502_reg { -+ MCP16502_REG_A, -+ MCP16502_REG_LPM, -+ MCP16502_REG_HIB, -+ MCP16502_REG_HPM, -+ MCP16502_REG_SEQ, -+ MCP16502_REG_CFG, -+}; -+ - static unsigned int mcp16502_of_map_mode(unsigned int mode) - { - if (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE) -@@ -144,22 +157,20 @@ static void mcp16502_gpio_set_mode(struc - } - - /* -- * mcp16502_get_reg() - get the PMIC's configuration register for opmode -+ * mcp16502_get_reg() - get the PMIC's state configuration register for opmode - * - * @rdev: the regulator whose register we are searching - * @opmode: the PMIC's operating mode ACTIVE, Low-power, Hibernate - */ --static int mcp16502_get_reg(struct regulator_dev *rdev, int opmode) -+static int mcp16502_get_state_reg(struct regulator_dev *rdev, int opmode) - { -- int reg = MCP16502_BASE(rdev_get_id(rdev)); -- - switch (opmode) { - case MCP16502_OPMODE_ACTIVE: -- return reg + MCP16502_OFFSET_MODE_A; -+ return MCP16502_REG_BASE(rdev_get_id(rdev), A); - case MCP16502_OPMODE_LPM: -- return reg + MCP16502_OFFSET_MODE_LPM; -+ return MCP16502_REG_BASE(rdev_get_id(rdev), LPM); - case MCP16502_OPMODE_HIB: -- return reg + MCP16502_OFFSET_MODE_HIB; -+ return MCP16502_REG_BASE(rdev_get_id(rdev), HIB); - default: - return -EINVAL; - } -@@ -179,7 +190,7 @@ static unsigned int mcp16502_get_mode(st - unsigned int val; - int ret, reg; - -- reg = mcp16502_get_reg(rdev, MCP16502_OPMODE_ACTIVE); -+ reg = mcp16502_get_state_reg(rdev, MCP16502_OPMODE_ACTIVE); - if (reg < 0) - return reg; - -@@ -210,7 +221,7 @@ static int _mcp16502_set_mode(struct reg - int val; - int reg; - -- reg = mcp16502_get_reg(rdev, op_mode); -+ reg = mcp16502_get_state_reg(rdev, op_mode); - if (reg < 0) - return reg; - -@@ -269,10 +280,10 @@ static int mcp16502_suspend_get_target_r - { - switch (pm_suspend_target_state) { - case PM_SUSPEND_STANDBY: -- return mcp16502_get_reg(rdev, MCP16502_OPMODE_LPM); -+ return mcp16502_get_state_reg(rdev, MCP16502_OPMODE_LPM); - case PM_SUSPEND_ON: - case PM_SUSPEND_MEM: -- return mcp16502_get_reg(rdev, MCP16502_OPMODE_HIB); -+ return mcp16502_get_state_reg(rdev, MCP16502_OPMODE_HIB); - default: - dev_err(&rdev->dev, "invalid suspend target: %d\n", - pm_suspend_target_state); diff --git a/target/linux/at91/patches-5.15/125-regulator-mcp16502-add-support-for-ramp-delay.patch b/target/linux/at91/patches-5.15/125-regulator-mcp16502-add-support-for-ramp-delay.patch deleted file mode 100644 index c91dd4a18b..0000000000 --- a/target/linux/at91/patches-5.15/125-regulator-mcp16502-add-support-for-ramp-delay.patch +++ /dev/null @@ -1,141 +0,0 @@ -From 7f13433e11a3c88f1fd6417c4c5e5a6c98370b9a Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 13 Nov 2020 17:21:09 +0200 -Subject: [PATCH 125/247] regulator: mcp16502: add support for ramp delay - -MCP16502 have configurable ramp delay support (via DVSR bits in -regulators' CFG register). - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605280870-32432-6-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/mcp16502.c | 89 +++++++++++++++++++++++++++++++++++- - 1 file changed, 87 insertions(+), 2 deletions(-) - ---- a/drivers/regulator/mcp16502.c -+++ b/drivers/regulator/mcp16502.c -@@ -22,8 +22,9 @@ - #define VDD_LOW_SEL 0x0D - #define VDD_HIGH_SEL 0x3F - --#define MCP16502_FLT BIT(7) --#define MCP16502_ENS BIT(0) -+#define MCP16502_FLT BIT(7) -+#define MCP16502_DVSR GENMASK(3, 2) -+#define MCP16502_ENS BIT(0) - - /* - * The PMIC has four sets of registers corresponding to four power modes: -@@ -88,6 +89,12 @@ enum mcp16502_reg { - MCP16502_REG_CFG, - }; - -+/* Ramp delay (uV/us) for buck1, ldo1, ldo2. */ -+static const int mcp16502_ramp_b1l12[] = { 6250, 3125, 2083, 1563 }; -+ -+/* Ramp delay (uV/us) for buck2, buck3, buck4. */ -+static const int mcp16502_ramp_b234[] = { 3125, 1563, 1042, 781 }; -+ - static unsigned int mcp16502_of_map_mode(unsigned int mode) - { - if (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE) -@@ -271,6 +278,80 @@ static int mcp16502_get_status(struct re - return REGULATOR_STATUS_UNDEFINED; - } - -+static int mcp16502_set_voltage_time_sel(struct regulator_dev *rdev, -+ unsigned int old_sel, -+ unsigned int new_sel) -+{ -+ static const u8 us_ramp[] = { 8, 16, 24, 32 }; -+ int id = rdev_get_id(rdev); -+ unsigned int uV_delta, val; -+ int ret; -+ -+ ret = regmap_read(rdev->regmap, MCP16502_REG_BASE(id, CFG), &val); -+ if (ret) -+ return ret; -+ -+ val = (val & MCP16502_DVSR) >> 2; -+ uV_delta = abs(new_sel * rdev->desc->linear_ranges->step - -+ old_sel * rdev->desc->linear_ranges->step); -+ switch (id) { -+ case BUCK1: -+ case LDO1: -+ case LDO2: -+ ret = DIV_ROUND_CLOSEST(uV_delta * us_ramp[val], -+ mcp16502_ramp_b1l12[val]); -+ break; -+ -+ case BUCK2: -+ case BUCK3: -+ case BUCK4: -+ ret = DIV_ROUND_CLOSEST(uV_delta * us_ramp[val], -+ mcp16502_ramp_b234[val]); -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ return ret; -+} -+ -+static int mcp16502_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay) -+{ -+ const int *ramp; -+ int id = rdev_get_id(rdev); -+ unsigned int i, size; -+ -+ switch (id) { -+ case BUCK1: -+ case LDO1: -+ case LDO2: -+ ramp = mcp16502_ramp_b1l12; -+ size = ARRAY_SIZE(mcp16502_ramp_b1l12); -+ break; -+ -+ case BUCK2: -+ case BUCK3: -+ case BUCK4: -+ ramp = mcp16502_ramp_b234; -+ size = ARRAY_SIZE(mcp16502_ramp_b234); -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < size; i++) { -+ if (ramp[i] == ramp_delay) -+ break; -+ } -+ if (i == size) -+ return -EINVAL; -+ -+ return regmap_update_bits(rdev->regmap, MCP16502_REG_BASE(id, CFG), -+ MCP16502_DVSR, (i << 2)); -+} -+ - #ifdef CONFIG_SUSPEND - /* - * mcp16502_suspend_get_target_reg() - get the reg of the target suspend PMIC -@@ -365,6 +446,8 @@ static const struct regulator_ops mcp165 - .disable = regulator_disable_regmap, - .is_enabled = regulator_is_enabled_regmap, - .get_status = mcp16502_get_status, -+ .set_voltage_time_sel = mcp16502_set_voltage_time_sel, -+ .set_ramp_delay = mcp16502_set_ramp_delay, - - .set_mode = mcp16502_set_mode, - .get_mode = mcp16502_get_mode, -@@ -389,6 +472,8 @@ static const struct regulator_ops mcp165 - .disable = regulator_disable_regmap, - .is_enabled = regulator_is_enabled_regmap, - .get_status = mcp16502_get_status, -+ .set_voltage_time_sel = mcp16502_set_voltage_time_sel, -+ .set_ramp_delay = mcp16502_set_ramp_delay, - - #ifdef CONFIG_SUSPEND - .set_suspend_voltage = mcp16502_set_suspend_voltage, diff --git a/target/linux/at91/patches-5.15/126-regulator-mcp16502-remove-void-documentation-of-stru.patch b/target/linux/at91/patches-5.15/126-regulator-mcp16502-remove-void-documentation-of-stru.patch deleted file mode 100644 index f570e2805f..0000000000 --- a/target/linux/at91/patches-5.15/126-regulator-mcp16502-remove-void-documentation-of-stru.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 8dcbcb052f682478dcbfa7fc9abdd909e1deab87 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 13 Nov 2020 17:21:10 +0200 -Subject: [PATCH 126/247] regulator: mcp16502: remove void documentation of - struct mcp16502 - -struct mcp16502 has no members called rdev or rmap. Remove the -documentation. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605280870-32432-7-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/mcp16502.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/regulator/mcp16502.c -+++ b/drivers/regulator/mcp16502.c -@@ -135,8 +135,6 @@ enum { - - /* - * struct mcp16502 - PMIC representation -- * @rdev: the regulators belonging to this chip -- * @rmap: regmap to be used for I2C communication - * @lpm: LPM GPIO descriptor - */ - struct mcp16502 { diff --git a/target/linux/at91/patches-5.15/127-regulator-core-validate-selector-against-linear_min_.patch b/target/linux/at91/patches-5.15/127-regulator-core-validate-selector-against-linear_min_.patch deleted file mode 100644 index 14eedb094c..0000000000 --- a/target/linux/at91/patches-5.15/127-regulator-core-validate-selector-against-linear_min_.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 3aee4f22ed0a22d3d6d22fc49812c03d876c7637 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 13 Nov 2020 17:21:05 +0200 -Subject: [PATCH 127/247] regulator: core: validate selector against - linear_min_sel - -There are regulators who's min selector is not zero. Selectors loops -(looping b/w zero and regulator::desc::n_voltages) might throw errors -because invalid selectors are used (lower than -regulator::desc::linear_min_sel). For this situations validate selectors -against regulator::desc::linear_min_sel. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605280870-32432-2-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/core.c | 9 +++++++-- - drivers/regulator/helpers.c | 3 ++- - 2 files changed, 9 insertions(+), 3 deletions(-) - ---- a/drivers/regulator/core.c -+++ b/drivers/regulator/core.c -@@ -2992,7 +2992,8 @@ static int _regulator_list_voltage(struc - return rdev->desc->fixed_uV; - - if (ops->list_voltage) { -- if (selector >= rdev->desc->n_voltages) -+ if (selector >= rdev->desc->n_voltages || -+ selector < rdev->desc->linear_min_sel) - return -EINVAL; - if (lock) - regulator_lock(rdev); -@@ -3143,7 +3144,8 @@ int regulator_list_hardware_vsel(struct - struct regulator_dev *rdev = regulator->rdev; - const struct regulator_ops *ops = rdev->desc->ops; - -- if (selector >= rdev->desc->n_voltages) -+ if (selector >= rdev->desc->n_voltages || -+ selector < rdev->desc->linear_min_sel) - return -EINVAL; - if (ops->set_voltage_sel != regulator_set_voltage_sel_regmap) - return -EOPNOTSUPP; -@@ -4066,6 +4068,9 @@ int regulator_set_voltage_time(struct re - - for (i = 0; i < rdev->desc->n_voltages; i++) { - /* We only look for exact voltage matches here */ -+ if (i < rdev->desc->linear_min_sel) -+ continue; -+ - voltage = regulator_list_voltage(regulator, i); - if (voltage < 0) - return -EINVAL; ---- a/drivers/regulator/helpers.c -+++ b/drivers/regulator/helpers.c -@@ -647,7 +647,8 @@ int regulator_list_voltage_table(struct - return -EINVAL; - } - -- if (selector >= rdev->desc->n_voltages) -+ if (selector >= rdev->desc->n_voltages || -+ selector < rdev->desc->linear_min_sel) - return -EINVAL; - - return rdev->desc->volt_table[selector]; diff --git a/target/linux/at91/patches-5.15/128-regulator-core-do-not-continue-if-selector-match.patch b/target/linux/at91/patches-5.15/128-regulator-core-do-not-continue-if-selector-match.patch deleted file mode 100644 index 2eed3a0aee..0000000000 --- a/target/linux/at91/patches-5.15/128-regulator-core-do-not-continue-if-selector-match.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 42b56e8bd343f34d5f2a601d8a8a05d8c861c08c Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 13 Nov 2020 19:56:04 +0200 -Subject: [PATCH 128/247] regulator: core: do not continue if selector match - -Do not continue if selector has already been located. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605290164-11556-1-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/core.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/regulator/core.c -+++ b/drivers/regulator/core.c -@@ -4071,6 +4071,9 @@ int regulator_set_voltage_time(struct re - if (i < rdev->desc->linear_min_sel) - continue; - -+ if (old_sel >= 0 && new_sel >= 0) -+ break; -+ - voltage = regulator_list_voltage(regulator, i); - if (voltage < 0) - return -EINVAL; diff --git a/target/linux/at91/patches-5.15/129-regulator-core-return-zero-for-selectors-lower-than-.patch b/target/linux/at91/patches-5.15/129-regulator-core-return-zero-for-selectors-lower-than-.patch deleted file mode 100644 index 9af0e0f53c..0000000000 --- a/target/linux/at91/patches-5.15/129-regulator-core-return-zero-for-selectors-lower-than-.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 0e933ffc049a0e181b5a6c3af1933976d6959ba9 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 25 Nov 2020 19:25:47 +0200 -Subject: [PATCH 129/247] regulator: core: return zero for selectors lower than - linear_min_sel - -Selectors lower than linear_min_sel should not be considered invalid. -Thus return zero in case _regulator_list_voltage(), -regulator_list_hardware_vsel() or regulator_list_voltage_table() -receives such selectors as argument. - -Fixes: bdcd1177578c ("regulator: core: validate selector against linear_min_sel") -Reported-by: Jon Hunter -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1606325147-606-1-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/core.c | 10 ++++++---- - drivers/regulator/helpers.c | 5 +++-- - 2 files changed, 9 insertions(+), 6 deletions(-) - ---- a/drivers/regulator/core.c -+++ b/drivers/regulator/core.c -@@ -2992,9 +2992,10 @@ static int _regulator_list_voltage(struc - return rdev->desc->fixed_uV; - - if (ops->list_voltage) { -- if (selector >= rdev->desc->n_voltages || -- selector < rdev->desc->linear_min_sel) -+ if (selector >= rdev->desc->n_voltages) - return -EINVAL; -+ if (selector < rdev->desc->linear_min_sel) -+ return 0; - if (lock) - regulator_lock(rdev); - ret = ops->list_voltage(rdev, selector); -@@ -3144,9 +3145,10 @@ int regulator_list_hardware_vsel(struct - struct regulator_dev *rdev = regulator->rdev; - const struct regulator_ops *ops = rdev->desc->ops; - -- if (selector >= rdev->desc->n_voltages || -- selector < rdev->desc->linear_min_sel) -+ if (selector >= rdev->desc->n_voltages) - return -EINVAL; -+ if (selector < rdev->desc->linear_min_sel) -+ return 0; - if (ops->set_voltage_sel != regulator_set_voltage_sel_regmap) - return -EOPNOTSUPP; - ---- a/drivers/regulator/helpers.c -+++ b/drivers/regulator/helpers.c -@@ -647,9 +647,10 @@ int regulator_list_voltage_table(struct - return -EINVAL; - } - -- if (selector >= rdev->desc->n_voltages || -- selector < rdev->desc->linear_min_sel) -+ if (selector >= rdev->desc->n_voltages) - return -EINVAL; -+ if (selector < rdev->desc->linear_min_sel) -+ return 0; - - return rdev->desc->volt_table[selector]; - } diff --git a/target/linux/at91/patches-5.15/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch b/target/linux/at91/patches-5.15/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch deleted file mode 100644 index 12679a20bd..0000000000 --- a/target/linux/at91/patches-5.15/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 763fe72f607d4e929d2c710c88e5c6978dd6ad97 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 7 Jan 2021 16:15:26 +0200 -Subject: [PATCH 130/247] regulator: mcp16502: lpm pin can be optional on some - platforms - -On some platform (e.g. SAMA7G5) LPM pin should be optional as it can -be controlled explicitly (via shutdown controller registers) in the -platform specific power saving code to decrease the power consumption -while suspended as this SoC pin may be connected to other devices that -could take power saving actions based on its value. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1610028927-9842-3-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/mcp16502.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/regulator/mcp16502.c -+++ b/drivers/regulator/mcp16502.c -@@ -550,7 +550,7 @@ static int mcp16502_probe(struct i2c_cli - config.regmap = rmap; - config.driver_data = mcp; - -- mcp->lpm = devm_gpiod_get(dev, "lpm", GPIOD_OUT_LOW); -+ mcp->lpm = devm_gpiod_get_optional(dev, "lpm", GPIOD_OUT_LOW); - if (IS_ERR(mcp->lpm)) { - dev_err(dev, "failed to get lpm pin: %ld\n", PTR_ERR(mcp->lpm)); - return PTR_ERR(mcp->lpm); diff --git a/target/linux/at91/patches-5.15/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch b/target/linux/at91/patches-5.15/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch deleted file mode 100644 index 78db5a0d32..0000000000 --- a/target/linux/at91/patches-5.15/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 7cb1dad7a7dfe4cfe55ebe86930dd6aef0de66b4 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 13 Nov 2020 15:24:29 +0200 -Subject: [PATCH 131/247] pinctrl: at91-pio4: add support for fewer lines on - last PIO bank - -Some products, like sama7g5, do not have a full last bank of PIO lines. -In this case for example, sama7g5 only has 8 lines for the PE bank. -PA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines. -To cope with this situation, added a data attribute that is product dependent, -to specify the number of lines of the last bank. -In case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK, -adjust the total number of lines accordingly. -This will avoid advertising 160 lines instead of the actual 136, as this -product supports, and to avoid reading/writing to invalid register addresses. - -Signed-off-by: Eugen Hristev -Acked-by: Ludovic Desroches -Link: https://lore.kernel.org/r/20201113132429.420940-1-eugen.hristev@microchip.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-at91-pio4.c | 18 ++++++++++++++++-- - 1 file changed, 16 insertions(+), 2 deletions(-) - ---- a/drivers/pinctrl/pinctrl-at91-pio4.c -+++ b/drivers/pinctrl/pinctrl-at91-pio4.c -@@ -71,8 +71,15 @@ - /* Custom pinconf parameters */ - #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1) - -+/** -+ * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct -+ * @nbanks: number of PIO banks -+ * @last_bank_count: number of lines in the last bank (can be less than -+ * the rest of the banks). -+ */ - struct atmel_pioctrl_data { - unsigned nbanks; -+ unsigned last_bank_count; - }; - - struct atmel_group { -@@ -980,11 +987,13 @@ static const struct dev_pm_ops atmel_pct - * We can have up to 16 banks. - */ - static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { -- .nbanks = 4, -+ .nbanks = 4, -+ .last_bank_count = ATMEL_PIO_NPINS_PER_BANK, - }; - - static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = { -- .nbanks = 5, -+ .nbanks = 5, -+ .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */ - }; - - static const struct of_device_id atmel_pctrl_of_match[] = { -@@ -1025,6 +1034,11 @@ static int atmel_pinctrl_probe(struct pl - atmel_pioctrl_data = match->data; - atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; - atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; -+ /* if last bank has limited number of pins, adjust accordingly */ -+ if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) { -+ atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK; -+ atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count; -+ } - - atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(atmel_pioctrl->reg_base)) diff --git a/target/linux/at91/patches-5.15/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch b/target/linux/at91/patches-5.15/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch deleted file mode 100644 index ca1fa8cee5..0000000000 --- a/target/linux/at91/patches-5.15/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 1dccaa4c1e99cd8bd27684a2c87ec806d426c088 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 16 Oct 2020 12:37:25 +0300 -Subject: [PATCH 132/247] dmaengine: at_xdmac: adapt perid for mem2mem - operations - -The PERID in the CC register for mem2mem operations must match an unused -PERID. -The PERID field is 7 bits, but the selected value is 0x3f. -On later products we can have more reserved PERIDs for actual peripherals, -thus this needs to be increased to maximum size. -Changing the value to 0x7f, which is the maximum for 7 bits field. - -Signed-off-by: Eugen Hristev -Reviewed-by: Tudor Ambarus -Link: https://lore.kernel.org/r/20201016093725.289880-1-eugen.hristev@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/dma/at_xdmac.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/dma/at_xdmac.c -+++ b/drivers/dma/at_xdmac.c -@@ -865,7 +865,7 @@ at_xdmac_interleaved_queue_desc(struct d - * match the one of another channel. If not, it could lead to spurious - * flag status. - */ -- u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) -+ u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) - | AT_XDMAC_CC_DIF(0) - | AT_XDMAC_CC_SIF(0) - | AT_XDMAC_CC_MBSIZE_SIXTEEN -@@ -1047,7 +1047,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan - * match the one of another channel. If not, it could lead to spurious - * flag status. - */ -- u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) -+ u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) - | AT_XDMAC_CC_DAM_INCREMENTED_AM - | AT_XDMAC_CC_SAM_INCREMENTED_AM - | AT_XDMAC_CC_DIF(0) -@@ -1153,7 +1153,7 @@ static struct at_xdmac_desc *at_xdmac_me - * match the one of another channel. If not, it could lead to spurious - * flag status. - */ -- u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) -+ u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) - | AT_XDMAC_CC_DAM_UBS_AM - | AT_XDMAC_CC_SAM_INCREMENTED_AM - | AT_XDMAC_CC_DIF(0) diff --git a/target/linux/at91/patches-5.15/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch b/target/linux/at91/patches-5.15/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch deleted file mode 100644 index 6d338490fb..0000000000 --- a/target/linux/at91/patches-5.15/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch +++ /dev/null @@ -1,280 +0,0 @@ -From 613af756b93fe005d9db11ea26fd0318f239d5a2 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 16 Oct 2020 12:38:50 +0300 -Subject: [PATCH 133/247] dmaengine: at_xdmac: add support for sama7g5 based - at_xdmac - -SAMA7G5 SoC uses a slightly different variant of the AT_XDMAC. -Added support by a new compatible and a layout struct that copes -to the specific version considering the compatible string. -Only the differences in register map are present in the layout struct. -I reworked the register access for this part that has the differences. -Also the Source/Destination Interface bits are no longer valid for this -variant of the XDMAC. Thus, the layout also has a bool for specifying -whether these bits are required or not. - -Signed-off-by: Eugen Hristev -Link: https://lore.kernel.org/r/20201016093850.290053-1-eugen.hristev@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/dma/at_xdmac.c | 110 +++++++++++++++++++++++++++++++---------- - 1 file changed, 84 insertions(+), 26 deletions(-) - ---- a/drivers/dma/at_xdmac.c -+++ b/drivers/dma/at_xdmac.c -@@ -38,13 +38,6 @@ - #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */ - #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */ - #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */ --#define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */ --#define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */ --#define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */ --#define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */ --#define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */ --#define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */ --#define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */ - #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */ - - /* Channel relative registers offsets */ -@@ -151,8 +144,6 @@ - #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */ - #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */ - --#define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */ -- - /* Microblock control members */ - #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */ - #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */ -@@ -180,6 +171,27 @@ enum atc_status { - AT_XDMAC_CHAN_IS_PAUSED, - }; - -+struct at_xdmac_layout { -+ /* Global Channel Read Suspend Register */ -+ u8 grs; -+ /* Global Write Suspend Register */ -+ u8 gws; -+ /* Global Channel Read Write Suspend Register */ -+ u8 grws; -+ /* Global Channel Read Write Resume Register */ -+ u8 grwr; -+ /* Global Channel Software Request Register */ -+ u8 gswr; -+ /* Global channel Software Request Status Register */ -+ u8 gsws; -+ /* Global Channel Software Flush Request Register */ -+ u8 gswf; -+ /* Channel reg base */ -+ u8 chan_cc_reg_base; -+ /* Source/Destination Interface must be specified or not */ -+ bool sdif; -+}; -+ - /* ----- Channels ----- */ - struct at_xdmac_chan { - struct dma_chan chan; -@@ -213,6 +225,7 @@ struct at_xdmac { - struct clk *clk; - u32 save_gim; - struct dma_pool *at_xdmac_desc_pool; -+ const struct at_xdmac_layout *layout; - struct at_xdmac_chan chan[]; - }; - -@@ -245,9 +258,33 @@ struct at_xdmac_desc { - struct list_head xfer_node; - } __aligned(sizeof(u64)); - -+static const struct at_xdmac_layout at_xdmac_sama5d4_layout = { -+ .grs = 0x28, -+ .gws = 0x2C, -+ .grws = 0x30, -+ .grwr = 0x34, -+ .gswr = 0x38, -+ .gsws = 0x3C, -+ .gswf = 0x40, -+ .chan_cc_reg_base = 0x50, -+ .sdif = true, -+}; -+ -+static const struct at_xdmac_layout at_xdmac_sama7g5_layout = { -+ .grs = 0x30, -+ .gws = 0x38, -+ .grws = 0x40, -+ .grwr = 0x44, -+ .gswr = 0x48, -+ .gsws = 0x4C, -+ .gswf = 0x50, -+ .chan_cc_reg_base = 0x60, -+ .sdif = false, -+}; -+ - static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb) - { -- return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40); -+ return atxdmac->regs + (atxdmac->layout->chan_cc_reg_base + chan_nb * 0x40); - } - - #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg)) -@@ -343,8 +380,10 @@ static void at_xdmac_start_xfer(struct a - first->active_xfer = true; - - /* Tell xdmac where to get the first descriptor. */ -- reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys) -- | AT_XDMAC_CNDA_NDAIF(atchan->memif); -+ reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys); -+ if (atxdmac->layout->sdif) -+ reg |= AT_XDMAC_CNDA_NDAIF(atchan->memif); -+ - at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg); - - /* -@@ -539,6 +578,7 @@ static int at_xdmac_compute_chan_conf(st - enum dma_transfer_direction direction) - { - struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); -+ struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); - int csize, dwidth; - - if (direction == DMA_DEV_TO_MEM) { -@@ -546,12 +586,14 @@ static int at_xdmac_compute_chan_conf(st - AT91_XDMAC_DT_PERID(atchan->perid) - | AT_XDMAC_CC_DAM_INCREMENTED_AM - | AT_XDMAC_CC_SAM_FIXED_AM -- | AT_XDMAC_CC_DIF(atchan->memif) -- | AT_XDMAC_CC_SIF(atchan->perif) - | AT_XDMAC_CC_SWREQ_HWR_CONNECTED - | AT_XDMAC_CC_DSYNC_PER2MEM - | AT_XDMAC_CC_MBSIZE_SIXTEEN - | AT_XDMAC_CC_TYPE_PER_TRAN; -+ if (atxdmac->layout->sdif) -+ atchan->cfg |= AT_XDMAC_CC_DIF(atchan->memif) | -+ AT_XDMAC_CC_SIF(atchan->perif); -+ - csize = ffs(atchan->sconfig.src_maxburst) - 1; - if (csize < 0) { - dev_err(chan2dev(chan), "invalid src maxburst value\n"); -@@ -569,12 +611,14 @@ static int at_xdmac_compute_chan_conf(st - AT91_XDMAC_DT_PERID(atchan->perid) - | AT_XDMAC_CC_DAM_FIXED_AM - | AT_XDMAC_CC_SAM_INCREMENTED_AM -- | AT_XDMAC_CC_DIF(atchan->perif) -- | AT_XDMAC_CC_SIF(atchan->memif) - | AT_XDMAC_CC_SWREQ_HWR_CONNECTED - | AT_XDMAC_CC_DSYNC_MEM2PER - | AT_XDMAC_CC_MBSIZE_SIXTEEN - | AT_XDMAC_CC_TYPE_PER_TRAN; -+ if (atxdmac->layout->sdif) -+ atchan->cfg |= AT_XDMAC_CC_DIF(atchan->perif) | -+ AT_XDMAC_CC_SIF(atchan->memif); -+ - csize = ffs(atchan->sconfig.dst_maxburst) - 1; - if (csize < 0) { - dev_err(chan2dev(chan), "invalid src maxburst value\n"); -@@ -864,10 +908,12 @@ at_xdmac_interleaved_queue_desc(struct d - * ERRATA: Even if useless for memory transfers, the PERID has to not - * match the one of another channel. If not, it could lead to spurious - * flag status. -+ * For SAMA7G5x case, the SIF and DIF fields are no longer used. -+ * Thus, no need to have the SIF/DIF interfaces here. -+ * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as -+ * zero. - */ - u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) -- | AT_XDMAC_CC_DIF(0) -- | AT_XDMAC_CC_SIF(0) - | AT_XDMAC_CC_MBSIZE_SIXTEEN - | AT_XDMAC_CC_TYPE_MEM_TRAN; - -@@ -1046,12 +1092,14 @@ at_xdmac_prep_dma_memcpy(struct dma_chan - * ERRATA: Even if useless for memory transfers, the PERID has to not - * match the one of another channel. If not, it could lead to spurious - * flag status. -+ * For SAMA7G5x case, the SIF and DIF fields are no longer used. -+ * Thus, no need to have the SIF/DIF interfaces here. -+ * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as -+ * zero. - */ - u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) - | AT_XDMAC_CC_DAM_INCREMENTED_AM - | AT_XDMAC_CC_SAM_INCREMENTED_AM -- | AT_XDMAC_CC_DIF(0) -- | AT_XDMAC_CC_SIF(0) - | AT_XDMAC_CC_MBSIZE_SIXTEEN - | AT_XDMAC_CC_TYPE_MEM_TRAN; - unsigned long irqflags; -@@ -1152,12 +1200,14 @@ static struct at_xdmac_desc *at_xdmac_me - * ERRATA: Even if useless for memory transfers, the PERID has to not - * match the one of another channel. If not, it could lead to spurious - * flag status. -+ * For SAMA7G5x case, the SIF and DIF fields are no longer used. -+ * Thus, no need to have the SIF/DIF interfaces here. -+ * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as -+ * zero. - */ - u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) - | AT_XDMAC_CC_DAM_UBS_AM - | AT_XDMAC_CC_SAM_INCREMENTED_AM -- | AT_XDMAC_CC_DIF(0) -- | AT_XDMAC_CC_SIF(0) - | AT_XDMAC_CC_MBSIZE_SIXTEEN - | AT_XDMAC_CC_MEMSET_HW_MODE - | AT_XDMAC_CC_TYPE_MEM_TRAN; -@@ -1436,7 +1486,7 @@ at_xdmac_tx_status(struct dma_chan *chan - mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC; - value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM; - if ((desc->lld.mbr_cfg & mask) == value) { -- at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); -+ at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask); - while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) - cpu_relax(); - } -@@ -1494,7 +1544,7 @@ at_xdmac_tx_status(struct dma_chan *chan - * FIFO flush ensures that data are really written. - */ - if ((desc->lld.mbr_cfg & mask) == value) { -- at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); -+ at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask); - while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) - cpu_relax(); - } -@@ -1762,7 +1812,7 @@ static int at_xdmac_device_pause(struct - return 0; - - spin_lock_irqsave(&atchan->lock, flags); -- at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask); -+ at_xdmac_write(atxdmac, atxdmac->layout->grws, atchan->mask); - while (at_xdmac_chan_read(atchan, AT_XDMAC_CC) - & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP)) - cpu_relax(); -@@ -1785,7 +1835,7 @@ static int at_xdmac_device_resume(struct - return 0; - } - -- at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask); -+ at_xdmac_write(atxdmac, atxdmac->layout->grwr, atchan->mask); - clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); - spin_unlock_irqrestore(&atchan->lock, flags); - -@@ -1992,6 +2042,10 @@ static int at_xdmac_probe(struct platfor - atxdmac->regs = base; - atxdmac->irq = irq; - -+ atxdmac->layout = of_device_get_match_data(&pdev->dev); -+ if (!atxdmac->layout) -+ return -ENODEV; -+ - atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk"); - if (IS_ERR(atxdmac->clk)) { - dev_err(&pdev->dev, "can't get dma_clk\n"); -@@ -2134,6 +2188,10 @@ static const struct dev_pm_ops atmel_xdm - static const struct of_device_id atmel_xdmac_dt_ids[] = { - { - .compatible = "atmel,sama5d4-dma", -+ .data = &at_xdmac_sama5d4_layout, -+ }, { -+ .compatible = "microchip,sama7g5-dma", -+ .data = &at_xdmac_sama7g5_layout, - }, { - /* sentinel */ - } diff --git a/target/linux/at91/patches-5.15/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch b/target/linux/at91/patches-5.15/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch deleted file mode 100644 index 463d03a35e..0000000000 --- a/target/linux/at91/patches-5.15/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 4833d6ea13a6d2c44a91247991a82c3eb6c1613e Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 16 Oct 2020 12:39:18 +0300 -Subject: [PATCH 134/247] dmaengine: at_xdmac: add AXI priority support and - recommended settings - -The sama7g5 version of the XDMAC supports priority configuration and -outstanding capabilities. -Add defines for the specific registers for this configuration, together -with recommended settings. -However the settings are very different if the XDMAC is a mem2mem or a -per2mem controller. -Thus, we need to differentiate according to device tree property. - -Signed-off-by: Eugen Hristev -Link: https://lore.kernel.org/r/20201016093918.290137-1-eugen.hristev@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/dma/at_xdmac.c | 47 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 47 insertions(+) - ---- a/drivers/dma/at_xdmac.c -+++ b/drivers/dma/at_xdmac.c -@@ -30,7 +30,24 @@ - #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */ - #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */ - #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */ -+#define AT_XDMAC_WRHP(i) (((i) & 0xF) << 4) -+#define AT_XDMAC_WRMP(i) (((i) & 0xF) << 8) -+#define AT_XDMAC_WRLP(i) (((i) & 0xF) << 12) -+#define AT_XDMAC_RDHP(i) (((i) & 0xF) << 16) -+#define AT_XDMAC_RDMP(i) (((i) & 0xF) << 20) -+#define AT_XDMAC_RDLP(i) (((i) & 0xF) << 24) -+#define AT_XDMAC_RDSG(i) (((i) & 0xF) << 28) -+#define AT_XDMAC_GCFG_M2M (AT_XDMAC_RDLP(0xF) | AT_XDMAC_WRLP(0xF)) -+#define AT_XDMAC_GCFG_P2M (AT_XDMAC_RDSG(0x1) | AT_XDMAC_RDHP(0x3) | \ -+ AT_XDMAC_WRHP(0x5)) - #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */ -+#define AT_XDMAC_PW0(i) (((i) & 0xF) << 0) -+#define AT_XDMAC_PW1(i) (((i) & 0xF) << 4) -+#define AT_XDMAC_PW2(i) (((i) & 0xF) << 8) -+#define AT_XDMAC_PW3(i) (((i) & 0xF) << 12) -+#define AT_XDMAC_GWAC_M2M 0 -+#define AT_XDMAC_GWAC_P2M (AT_XDMAC_PW0(0xF) | AT_XDMAC_PW2(0xF)) -+ - #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */ - #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */ - #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */ -@@ -190,6 +207,8 @@ struct at_xdmac_layout { - u8 chan_cc_reg_base; - /* Source/Destination Interface must be specified or not */ - bool sdif; -+ /* AXI queue priority configuration supported */ -+ bool axi_config; - }; - - /* ----- Channels ----- */ -@@ -268,6 +287,7 @@ static const struct at_xdmac_layout at_x - .gswf = 0x40, - .chan_cc_reg_base = 0x50, - .sdif = true, -+ .axi_config = false, - }; - - static const struct at_xdmac_layout at_xdmac_sama7g5_layout = { -@@ -280,6 +300,7 @@ static const struct at_xdmac_layout at_x - .gswf = 0x50, - .chan_cc_reg_base = 0x60, - .sdif = false, -+ .axi_config = true, - }; - - static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb) -@@ -2003,6 +2024,30 @@ static int atmel_xdmac_resume(struct dev - } - #endif /* CONFIG_PM_SLEEP */ - -+static void at_xdmac_axi_config(struct platform_device *pdev) -+{ -+ struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev); -+ bool dev_m2m = false; -+ u32 dma_requests; -+ -+ if (!atxdmac->layout->axi_config) -+ return; /* Not supported */ -+ -+ if (!of_property_read_u32(pdev->dev.of_node, "dma-requests", -+ &dma_requests)) { -+ dev_info(&pdev->dev, "controller in mem2mem mode.\n"); -+ dev_m2m = true; -+ } -+ -+ if (dev_m2m) { -+ at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M); -+ at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M); -+ } else { -+ at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M); -+ at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M); -+ } -+} -+ - static int at_xdmac_probe(struct platform_device *pdev) - { - struct at_xdmac *atxdmac; -@@ -2147,6 +2192,8 @@ static int at_xdmac_probe(struct platfor - dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n", - nr_channels, atxdmac->regs); - -+ at_xdmac_axi_config(pdev); -+ - return 0; - - err_dma_unregister: diff --git a/target/linux/at91/patches-5.15/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch b/target/linux/at91/patches-5.15/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch deleted file mode 100644 index 210d1bd2de..0000000000 --- a/target/linux/at91/patches-5.15/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 982347f757b85ef526afaf243867ddd515475e1b Mon Sep 17 00:00:00 2001 -From: Charles Keepax -Date: Mon, 4 Jan 2021 10:38:02 +0000 -Subject: [PATCH 135/247] net: macb: Correct usage of MACB_CAPS_CLK_HW_CHG flag - -A new flag MACB_CAPS_CLK_HW_CHG was added and all callers of -macb_set_tx_clk were gated on the presence of this flag. - -- if (!clk) -+ if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG)) - -However the flag was not added to anything other than the new -sama7g5_gem, turning that function call into a no op for all other -systems. This breaks the networking on Zynq. - -The commit message adding this states: a new capability so that -macb_set_tx_clock() to not be called for IPs having this -capability - -This strongly implies that present of the flag was intended to skip -the function not absence of the flag. Update the if statement to -this effect, which repairs the existing users. - -Fixes: daafa1d33cc9 ("net: macb: add capability to not set the clock rate") -Suggested-by: Andrew Lunn -Signed-off-by: Charles Keepax -Reviewed-by: Claudiu Beznea -Reviewed-by: Andrew Lunn -Link: https://lore.kernel.org/r/20210104103802.13091-1-ckeepax@opensource.cirrus.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/cadence/macb_main.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -464,7 +464,7 @@ static void macb_set_tx_clk(struct macb - { - long ferr, rate, rate_rounded; - -- if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG)) -+ if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG)) - return; - - switch (speed) { diff --git a/target/linux/at91/patches-5.15/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch b/target/linux/at91/patches-5.15/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch deleted file mode 100644 index 7c36d0f93a..0000000000 --- a/target/linux/at91/patches-5.15/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch +++ /dev/null @@ -1,43 +0,0 @@ -From a2eda4ef1e3d617cdd669e256e45e969fab62398 Mon Sep 17 00:00:00 2001 -From: Kai Stuhlemmer -Date: Thu, 8 Oct 2020 14:50:28 +0200 -Subject: [PATCH 136/247] ARM: at91: sam9x60 SiP types added to soc description - -Adding SAM9X60 SIP variants to the soc description list. - -Signed-off-by: Kai Stuhlemmer -Signed-off-by: Nicolas Ferre -Signed-off-by: Alexandre Belloni -Link: https://lore.kernel.org/r/20201008125028.21071-1-nicolas.ferre@microchip.com ---- - drivers/soc/atmel/soc.c | 6 ++++++ - drivers/soc/atmel/soc.h | 3 +++ - 2 files changed, 9 insertions(+) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -69,6 +69,12 @@ static const struct at91_soc __initconst - #endif - #ifdef CONFIG_SOC_SAM9X60 - AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"), -+ AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH, -+ "sam9x60 64MiB DDR2 SiP", "sam9x60"), -+ AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH, -+ "sam9x60 128MiB DDR2 SiP", "sam9x60"), -+ AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH, -+ "sam9x60 8MiB SDRAM SiP", "sam9x60"), - #endif - #ifdef CONFIG_SOC_SAMA5 - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH, ---- a/drivers/soc/atmel/soc.h -+++ b/drivers/soc/atmel/soc.h -@@ -60,6 +60,9 @@ at91_soc_init(const struct at91_soc *soc - #define AT91SAM9CN11_EXID_MATCH 0x00000009 - - #define SAM9X60_EXID_MATCH 0x00000000 -+#define SAM9X60_D5M_EXID_MATCH 0x00000001 -+#define SAM9X60_D1G_EXID_MATCH 0x00000010 -+#define SAM9X60_D6K_EXID_MATCH 0x00000011 - - #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 - #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 diff --git a/target/linux/at91/patches-5.15/137-drivers-soc-atmel-use-GENMASK.patch b/target/linux/at91/patches-5.15/137-drivers-soc-atmel-use-GENMASK.patch deleted file mode 100644 index de99d562f4..0000000000 --- a/target/linux/at91/patches-5.15/137-drivers-soc-atmel-use-GENMASK.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 8d858d9c57a0210ca1ce9e5ba76fab8bdb4d7b39 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 22 Jan 2021 14:21:32 +0200 -Subject: [PATCH 137/247] drivers: soc: atmel: use GENMASK - -Use GENMASK() to define CIDR match mask. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/1611318097-8970-3-git-send-email-claudiu.beznea@microchip.com ---- - drivers/soc/atmel/soc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -27,7 +27,7 @@ - #define AT91_CHIPID_EXID 0x04 - #define AT91_CIDR_VERSION(x) ((x) & 0x1f) - #define AT91_CIDR_EXT BIT(31) --#define AT91_CIDR_MATCH_MASK 0x7fffffe0 -+#define AT91_CIDR_MATCH_MASK GENMASK(30, 5) - - static const struct at91_soc __initconst socs[] = { - #ifdef CONFIG_SOC_AT91RM9200 diff --git a/target/linux/at91/patches-5.15/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch b/target/linux/at91/patches-5.15/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch deleted file mode 100644 index 885528a28e..0000000000 --- a/target/linux/at91/patches-5.15/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch +++ /dev/null @@ -1,26 +0,0 @@ -From ed871f95827e9b6d4ee9f9eafec4e18b87fb1a56 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 22 Jan 2021 14:21:33 +0200 -Subject: [PATCH 138/247] drivers: soc: atmel: fix "__initconst should be - placed after socs[]" warning - -Fix checkpatch.pl warning: "__initconst should be placed after socs[]". - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/1611318097-8970-4-git-send-email-claudiu.beznea@microchip.com ---- - drivers/soc/atmel/soc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -29,7 +29,7 @@ - #define AT91_CIDR_EXT BIT(31) - #define AT91_CIDR_MATCH_MASK GENMASK(30, 5) - --static const struct at91_soc __initconst socs[] = { -+static const struct at91_soc socs[] __initconst = { - #ifdef CONFIG_SOC_AT91RM9200 - AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"), - #endif diff --git a/target/linux/at91/patches-5.15/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch b/target/linux/at91/patches-5.15/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch deleted file mode 100644 index 72cdb46f11..0000000000 --- a/target/linux/at91/patches-5.15/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch +++ /dev/null @@ -1,348 +0,0 @@ -From 8f6f7ef363268f417f1729bb0b234326dd1e8e2a Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 22 Jan 2021 14:21:35 +0200 -Subject: [PATCH 139/247] drivers: soc: atmel: add per soc id and version match - masks - -SAMA7G5 has different masks for chip ID and chip version on CIDR -register compared to previous AT91 SoCs. For this the commit adapts -the code for SAMA7G5 addition by introducing 2 new members in -struct at91_soc and fill them properly and also preparing the -parsing of proper DT binding. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/1611318097-8970-6-git-send-email-claudiu.beznea@microchip.com ---- - drivers/soc/atmel/soc.c | 199 +++++++++++++++++++++++++++------------- - drivers/soc/atmel/soc.h | 7 +- - 2 files changed, 140 insertions(+), 66 deletions(-) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -25,135 +25,200 @@ - #define AT91_DBGU_EXID 0x44 - #define AT91_CHIPID_CIDR 0x00 - #define AT91_CHIPID_EXID 0x04 --#define AT91_CIDR_VERSION(x) ((x) & 0x1f) -+#define AT91_CIDR_VERSION(x, m) ((x) & (m)) -+#define AT91_CIDR_VERSION_MASK GENMASK(4, 0) - #define AT91_CIDR_EXT BIT(31) - #define AT91_CIDR_MATCH_MASK GENMASK(30, 5) - - static const struct at91_soc socs[] __initconst = { - #ifdef CONFIG_SOC_AT91RM9200 -- AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"), -+ AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"), - #endif - #ifdef CONFIG_SOC_AT91SAM9 -- AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL), -- AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL), -- AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL), -- AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL), -- AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL), -- AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH, -+ AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL), -+ AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL), -+ AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL), -+ AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL), -+ AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL), -+ AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH, - "at91sam9m11", "at91sam9g45"), -- AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH, -+ AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH, - "at91sam9m10", "at91sam9g45"), -- AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH, -+ AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH, - "at91sam9g46", "at91sam9g45"), -- AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH, -+ AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH, - "at91sam9g45", "at91sam9g45"), -- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH, -+ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH, - "at91sam9g15", "at91sam9x5"), -- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH, -+ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH, - "at91sam9g35", "at91sam9x5"), -- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH, -+ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH, - "at91sam9x35", "at91sam9x5"), -- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH, -+ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH, - "at91sam9g25", "at91sam9x5"), -- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH, -+ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH, - "at91sam9x25", "at91sam9x5"), -- AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH, -+ AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH, - "at91sam9cn12", "at91sam9n12"), -- AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH, -+ AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH, - "at91sam9n12", "at91sam9n12"), -- AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH, -+ AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH, - "at91sam9cn11", "at91sam9n12"), -- AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"), -- AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"), -- AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"), -+ AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"), -+ AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"), -+ AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"), - #endif - #ifdef CONFIG_SOC_SAM9X60 -- AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"), -+ AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, -+ "sam9x60", "sam9x60"), - AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH, -+ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, - "sam9x60 64MiB DDR2 SiP", "sam9x60"), - AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH, -+ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, - "sam9x60 128MiB DDR2 SiP", "sam9x60"), - AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH, -+ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, - "sam9x60 8MiB SDRAM SiP", "sam9x60"), - #endif - #ifdef CONFIG_SOC_SAMA5 -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH, - "sama5d21", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH, - "sama5d22", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D225C_D1M_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH, - "sama5d225c 16MiB SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH, - "sama5d23", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH, - "sama5d24", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH, - "sama5d24", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH, - "sama5d26", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH, - "sama5d27", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH, - "sama5d27", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D1G_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH, - "sama5d27c 128MiB SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D5M_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH, - "sama5d27c 64MiB SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD1G_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH, - "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD2G_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH, - "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH, - "sama5d28", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH, - "sama5d28", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_D1G_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH, - "sama5d28c 128MiB SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD1G_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH, - "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD2G_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH, - "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"), -- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH, -+ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH, - "sama5d31", "sama5d3"), -- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH, -+ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH, - "sama5d33", "sama5d3"), -- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH, -+ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH, - "sama5d34", "sama5d3"), -- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH, -+ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH, - "sama5d35", "sama5d3"), -- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH, -+ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH, - "sama5d36", "sama5d3"), -- AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH, -+ AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH, - "sama5d41", "sama5d4"), -- AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH, -+ AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH, - "sama5d42", "sama5d4"), -- AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH, -+ AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH, - "sama5d43", "sama5d4"), -- AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH, -+ AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH, - "sama5d44", "sama5d4"), - #endif - #ifdef CONFIG_SOC_SAMV7 -- AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH, -+ AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH, - "same70q21", "same7"), -- AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH, -+ AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH, - "same70q20", "same7"), -- AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH, -+ AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK -+ AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH, - "same70q19", "same7"), -- AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH, -+ AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH, - "sams70q21", "sams7"), -- AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH, -+ AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH, - "sams70q20", "sams7"), -- AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH, -+ AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH, - "sams70q19", "sams7"), -- AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH, -+ AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH, - "samv71q21", "samv7"), -- AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH, -+ AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH, - "samv71q20", "samv7"), -- AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH, -+ AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH, - "samv71q19", "samv7"), -- AT91_SOC(SAMV70Q20_CIDR_MATCH, SAMV70Q20_EXID_MATCH, -+ AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH, - "samv70q20", "samv7"), -- AT91_SOC(SAMV70Q19_CIDR_MATCH, SAMV70Q19_EXID_MATCH, -+ AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH, - "samv70q19", "samv7"), - #endif - { /* sentinel */ }, -@@ -191,8 +256,12 @@ static int __init at91_get_cidr_exid_fro - { - struct device_node *np; - void __iomem *regs; -+ static const struct of_device_id chipids[] = { -+ { .compatible = "atmel,sama5d2-chipid" }, -+ { }, -+ }; - -- np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid"); -+ np = of_find_matching_node(NULL, chipids); - if (!np) - return -ENODEV; - -@@ -235,7 +304,7 @@ struct soc_device * __init at91_soc_init - } - - for (soc = socs; soc->name; soc++) { -- if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK)) -+ if (soc->cidr_match != (cidr & soc->cidr_mask)) - continue; - - if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid) -@@ -254,7 +323,7 @@ struct soc_device * __init at91_soc_init - soc_dev_attr->family = soc->family; - soc_dev_attr->soc_id = soc->name; - soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X", -- AT91_CIDR_VERSION(cidr)); -+ AT91_CIDR_VERSION(cidr, soc->version_mask)); - soc_dev = soc_device_register(soc_dev_attr); - if (IS_ERR(soc_dev)) { - kfree(soc_dev_attr->revision); -@@ -266,7 +335,7 @@ struct soc_device * __init at91_soc_init - if (soc->family) - pr_info("Detected SoC family: %s\n", soc->family); - pr_info("Detected SoC: %s, revision %X\n", soc->name, -- AT91_CIDR_VERSION(cidr)); -+ AT91_CIDR_VERSION(cidr, soc->version_mask)); - - return soc_dev; - } ---- a/drivers/soc/atmel/soc.h -+++ b/drivers/soc/atmel/soc.h -@@ -16,14 +16,19 @@ - - struct at91_soc { - u32 cidr_match; -+ u32 cidr_mask; -+ u32 version_mask; - u32 exid_match; - const char *name; - const char *family; - }; - --#define AT91_SOC(__cidr, __exid, __name, __family) \ -+#define AT91_SOC(__cidr, __cidr_mask, __version_mask, __exid, \ -+ __name, __family) \ - { \ - .cidr_match = (__cidr), \ -+ .cidr_mask = (__cidr_mask), \ -+ .version_mask = (__version_mask), \ - .exid_match = (__exid), \ - .name = (__name), \ - .family = (__family), \ diff --git a/target/linux/at91/patches-5.15/140-drivers-soc-atmel-add-support-for-sama7g5.patch b/target/linux/at91/patches-5.15/140-drivers-soc-atmel-add-support-for-sama7g5.patch deleted file mode 100644 index 3b21017673..0000000000 --- a/target/linux/at91/patches-5.15/140-drivers-soc-atmel-add-support-for-sama7g5.patch +++ /dev/null @@ -1,87 +0,0 @@ -From e20bb57fc51741677a6fcae04e564797fd18921b Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 22 Jan 2021 14:21:37 +0200 -Subject: [PATCH 140/247] drivers: soc: atmel: add support for sama7g5 - -Add support for SAMA7G5 SoCs. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/1611318097-8970-8-git-send-email-claudiu.beznea@microchip.com ---- - drivers/soc/atmel/soc.c | 18 ++++++++++++++++++ - drivers/soc/atmel/soc.h | 6 ++++++ - 2 files changed, 24 insertions(+) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -27,8 +27,10 @@ - #define AT91_CHIPID_EXID 0x04 - #define AT91_CIDR_VERSION(x, m) ((x) & (m)) - #define AT91_CIDR_VERSION_MASK GENMASK(4, 0) -+#define AT91_CIDR_VERSION_MASK_SAMA7G5 GENMASK(3, 0) - #define AT91_CIDR_EXT BIT(31) - #define AT91_CIDR_MATCH_MASK GENMASK(30, 5) -+#define AT91_CIDR_MASK_SAMA7G5 GENMASK(27, 5) - - static const struct at91_soc socs[] __initconst = { - #ifdef CONFIG_SOC_AT91RM9200 -@@ -221,6 +223,20 @@ static const struct at91_soc socs[] __in - AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH, - "samv70q19", "samv7"), - #endif -+#ifdef CONFIG_SOC_SAMA7 -+ AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH, -+ "sama7g51", "sama7g5"), -+ AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH, -+ "sama7g52", "sama7g5"), -+ AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH, -+ "sama7g53", "sama7g5"), -+ AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH, -+ "sama7g54", "sama7g5"), -+#endif - { /* sentinel */ }, - }; - -@@ -258,6 +274,7 @@ static int __init at91_get_cidr_exid_fro - void __iomem *regs; - static const struct of_device_id chipids[] = { - { .compatible = "atmel,sama5d2-chipid" }, -+ { .compatible = "microchip,sama7g5-chipid" }, - { }, - }; - -@@ -345,6 +362,7 @@ static const struct of_device_id at91_so - { .compatible = "atmel,at91sam9", }, - { .compatible = "atmel,sama5", }, - { .compatible = "atmel,samv7", }, -+ { .compatible = "microchip,sama7g5", }, - { } - }; - ---- a/drivers/soc/atmel/soc.h -+++ b/drivers/soc/atmel/soc.h -@@ -48,6 +48,7 @@ at91_soc_init(const struct at91_soc *soc - #define AT91SAM9X5_CIDR_MATCH 0x019a05a0 - #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 - #define SAM9X60_CIDR_MATCH 0x019b35a0 -+#define SAMA7G5_CIDR_MATCH 0x00162100 - - #define AT91SAM9M11_EXID_MATCH 0x00000001 - #define AT91SAM9M10_EXID_MATCH 0x00000002 -@@ -69,6 +70,11 @@ at91_soc_init(const struct at91_soc *soc - #define SAM9X60_D1G_EXID_MATCH 0x00000010 - #define SAM9X60_D6K_EXID_MATCH 0x00000011 - -+#define SAMA7G51_EXID_MATCH 0x3 -+#define SAMA7G52_EXID_MATCH 0x2 -+#define SAMA7G53_EXID_MATCH 0x1 -+#define SAMA7G54_EXID_MATCH 0x0 -+ - #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 - #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 - #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 diff --git a/target/linux/at91/patches-5.15/141-drivers-soc-atmel-add-spdx-license-identifier.patch b/target/linux/at91/patches-5.15/141-drivers-soc-atmel-add-spdx-license-identifier.patch deleted file mode 100644 index be238147d6..0000000000 --- a/target/linux/at91/patches-5.15/141-drivers-soc-atmel-add-spdx-license-identifier.patch +++ /dev/null @@ -1,49 +0,0 @@ -From acd4816cfa7811b13ca2864645f2de41031ccf4d Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Tue, 26 Jan 2021 11:29:30 +0200 -Subject: [PATCH 141/247] drivers: soc: atmel: add spdx license identifier - -Add SPDX-License-Identifier. - -Signed-off-by: Claudiu Beznea -[nicolas.ferre@microhcip.com: remove license boilerplate now it's useless] -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/1611653376-24168-2-git-send-email-claudiu.beznea@microchip.com ---- - drivers/soc/atmel/soc.c | 6 +----- - drivers/soc/atmel/soc.h | 6 +----- - 2 files changed, 2 insertions(+), 10 deletions(-) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -1,13 +1,9 @@ -+// SPDX-License-Identifier: GPL-2.0-only - /* - * Copyright (C) 2015 Atmel - * - * Alexandre Belloni -Date: Thu, 4 Feb 2021 16:49:25 +0100 -Subject: [PATCH 142/247] drivers: soc: atmel: fix type for same7 - -A missing comma caused a build failure: - -drivers/soc/atmel/soc.c:196:24: error: too few arguments provided to function-like macro invocation - -Fixes: af3a10513cd6 ("drivers: soc: atmel: add per soc id and version match masks") -Signed-off-by: Arnd Bergmann -Acked-by: Alexandre Belloni -Signed-off-by: Arnd Bergmann ---- - drivers/soc/atmel/soc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -191,7 +191,7 @@ static const struct at91_soc socs[] __in - AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, - AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH, - "same70q20", "same7"), -- AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK -+ AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, - AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH, - "same70q19", "same7"), - AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, diff --git a/target/linux/at91/patches-5.15/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch b/target/linux/at91/patches-5.15/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch deleted file mode 100644 index 7b2462cd00..0000000000 --- a/target/linux/at91/patches-5.15/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch +++ /dev/null @@ -1,173 +0,0 @@ -From 5f090a664d62ceeaf9a0f482426e35cab18d65a9 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Tue, 19 Jan 2021 14:59:25 +0200 -Subject: [PATCH 143/247] clocksource/drivers/timer-microchip-pit64b: Add - clocksource suspend/resume - -Add suspend/resume support for clocksource timer. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/1611061165-30180-1-git-send-email-claudiu.beznea@microchip.com ---- - drivers/clocksource/timer-microchip-pit64b.c | 86 ++++++++++++++++---- - 1 file changed, 71 insertions(+), 15 deletions(-) - ---- a/drivers/clocksource/timer-microchip-pit64b.c -+++ b/drivers/clocksource/timer-microchip-pit64b.c -@@ -71,10 +71,24 @@ struct mchp_pit64b_clkevt { - struct clock_event_device clkevt; - }; - --#define to_mchp_pit64b_timer(x) \ -+#define clkevt_to_mchp_pit64b_timer(x) \ - ((struct mchp_pit64b_timer *)container_of(x,\ - struct mchp_pit64b_clkevt, clkevt)) - -+/** -+ * mchp_pit64b_clksrc - PIT64B clocksource data structure -+ * @timer: PIT64B timer -+ * @clksrc: clocksource -+ */ -+struct mchp_pit64b_clksrc { -+ struct mchp_pit64b_timer timer; -+ struct clocksource clksrc; -+}; -+ -+#define clksrc_to_mchp_pit64b_timer(x) \ -+ ((struct mchp_pit64b_timer *)container_of(x,\ -+ struct mchp_pit64b_clksrc, clksrc)) -+ - /* Base address for clocksource timer. */ - static void __iomem *mchp_pit64b_cs_base; - /* Default cycles for clockevent timer. */ -@@ -116,6 +130,36 @@ static inline void mchp_pit64b_reset(str - writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR); - } - -+static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer) -+{ -+ writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); -+ if (timer->mode & MCHP_PIT64B_MR_SGCLK) -+ clk_disable_unprepare(timer->gclk); -+ clk_disable_unprepare(timer->pclk); -+} -+ -+static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer) -+{ -+ clk_prepare_enable(timer->pclk); -+ if (timer->mode & MCHP_PIT64B_MR_SGCLK) -+ clk_prepare_enable(timer->gclk); -+} -+ -+static void mchp_pit64b_clksrc_suspend(struct clocksource *cs) -+{ -+ struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs); -+ -+ mchp_pit64b_suspend(timer); -+} -+ -+static void mchp_pit64b_clksrc_resume(struct clocksource *cs) -+{ -+ struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs); -+ -+ mchp_pit64b_resume(timer); -+ mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); -+} -+ - static u64 mchp_pit64b_clksrc_read(struct clocksource *cs) - { - return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); -@@ -128,7 +172,7 @@ static u64 notrace mchp_pit64b_sched_rea - - static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev) - { -- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); -+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - - writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); - -@@ -137,7 +181,7 @@ static int mchp_pit64b_clkevt_shutdown(s - - static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev) - { -- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); -+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - - mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT, - MCHP_PIT64B_IER_PERIOD); -@@ -148,7 +192,7 @@ static int mchp_pit64b_clkevt_set_period - static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, - struct clock_event_device *cedev) - { -- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); -+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - - mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, - MCHP_PIT64B_IER_PERIOD); -@@ -158,21 +202,16 @@ static int mchp_pit64b_clkevt_set_next_e - - static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev) - { -- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); -+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - -- writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); -- if (timer->mode & MCHP_PIT64B_MR_SGCLK) -- clk_disable_unprepare(timer->gclk); -- clk_disable_unprepare(timer->pclk); -+ mchp_pit64b_suspend(timer); - } - - static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev) - { -- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); -+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - -- clk_prepare_enable(timer->pclk); -- if (timer->mode & MCHP_PIT64B_MR_SGCLK) -- clk_prepare_enable(timer->gclk); -+ mchp_pit64b_resume(timer); - } - - static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id) -@@ -296,20 +335,37 @@ done: - static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer, - u32 clk_rate) - { -+ struct mchp_pit64b_clksrc *cs; - int ret; - -+ cs = kzalloc(sizeof(*cs), GFP_KERNEL); -+ if (!cs) -+ return -ENOMEM; -+ - mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); - - mchp_pit64b_cs_base = timer->base; - -- ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate, -- 210, 64, mchp_pit64b_clksrc_read); -+ cs->timer.base = timer->base; -+ cs->timer.pclk = timer->pclk; -+ cs->timer.gclk = timer->gclk; -+ cs->timer.mode = timer->mode; -+ cs->clksrc.name = MCHP_PIT64B_NAME; -+ cs->clksrc.mask = CLOCKSOURCE_MASK(64); -+ cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; -+ cs->clksrc.rating = 210; -+ cs->clksrc.read = mchp_pit64b_clksrc_read; -+ cs->clksrc.suspend = mchp_pit64b_clksrc_suspend; -+ cs->clksrc.resume = mchp_pit64b_clksrc_resume; -+ -+ ret = clocksource_register_hz(&cs->clksrc, clk_rate); - if (ret) { - pr_debug("clksrc: Failed to register PIT64B clocksource!\n"); - - /* Stop timer. */ - writel_relaxed(MCHP_PIT64B_CR_SWRST, - timer->base + MCHP_PIT64B_CR); -+ kfree(cs); - - return ret; - } diff --git a/target/linux/at91/patches-5.15/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch b/target/linux/at91/patches-5.15/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch deleted file mode 100644 index 072e13bcc6..0000000000 --- a/target/linux/at91/patches-5.15/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch +++ /dev/null @@ -1,135 +0,0 @@ -From 0b20c174a17dcfa805ddac1301a5af7298877ec3 Mon Sep 17 00:00:00 2001 -From: Lars-Peter Clausen -Date: Wed, 6 Jan 2021 14:36:48 +0100 -Subject: [PATCH 144/247] ASoC: atmel-pdc: Use managed DMA buffer allocation - -Instead of manually managing its DMA buffers using -dma_{alloc,free}_coherent() lets the sound core take care of this using -managed buffers. - -On one hand this reduces the amount of boiler plate code, but the main -motivation for the change is to use the shared code where possible. This -makes it easier to argue about correctness and that the code does not -contain subtle bugs like data leakage or similar. - -Signed-off-by: Lars-Peter Clausen -Reviewed-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210106133650.13509-1-lars@metafoo.de -Signed-off-by: Mark Brown ---- - sound/soc/atmel/atmel-pcm-pdc.c | 78 ++------------------------------- - 1 file changed, 4 insertions(+), 74 deletions(-) - ---- a/sound/soc/atmel/atmel-pcm-pdc.c -+++ b/sound/soc/atmel/atmel-pcm-pdc.c -@@ -34,86 +34,21 @@ - #include "atmel-pcm.h" - - --static int atmel_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, -- int stream) --{ -- struct snd_pcm_substream *substream = pcm->streams[stream].substream; -- struct snd_dma_buffer *buf = &substream->dma_buffer; -- size_t size = ATMEL_SSC_DMABUF_SIZE; -- -- buf->dev.type = SNDRV_DMA_TYPE_DEV; -- buf->dev.dev = pcm->card->dev; -- buf->private_data = NULL; -- buf->area = dma_alloc_coherent(pcm->card->dev, size, -- &buf->addr, GFP_KERNEL); -- pr_debug("atmel-pcm: alloc dma buffer: area=%p, addr=%p, size=%zu\n", -- (void *)buf->area, (void *)(long)buf->addr, size); -- -- if (!buf->area) -- return -ENOMEM; -- -- buf->bytes = size; -- return 0; --} -- --static int atmel_pcm_mmap(struct snd_soc_component *component, -- struct snd_pcm_substream *substream, -- struct vm_area_struct *vma) --{ -- return remap_pfn_range(vma, vma->vm_start, -- substream->dma_buffer.addr >> PAGE_SHIFT, -- vma->vm_end - vma->vm_start, vma->vm_page_prot); --} -- - static int atmel_pcm_new(struct snd_soc_component *component, - struct snd_soc_pcm_runtime *rtd) - { - struct snd_card *card = rtd->card->snd_card; -- struct snd_pcm *pcm = rtd->pcm; - int ret; - - ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32)); - if (ret) - return ret; - -- if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) { -- pr_debug("atmel-pcm: allocating PCM playback DMA buffer\n"); -- ret = atmel_pcm_preallocate_dma_buffer(pcm, -- SNDRV_PCM_STREAM_PLAYBACK); -- if (ret) -- goto out; -- } -+ snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, -+ card->dev, ATMEL_SSC_DMABUF_SIZE, -+ ATMEL_SSC_DMABUF_SIZE); - -- if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { -- pr_debug("atmel-pcm: allocating PCM capture DMA buffer\n"); -- ret = atmel_pcm_preallocate_dma_buffer(pcm, -- SNDRV_PCM_STREAM_CAPTURE); -- if (ret) -- goto out; -- } -- out: -- return ret; --} -- --static void atmel_pcm_free(struct snd_soc_component *component, -- struct snd_pcm *pcm) --{ -- struct snd_pcm_substream *substream; -- struct snd_dma_buffer *buf; -- int stream; -- -- for (stream = 0; stream < 2; stream++) { -- substream = pcm->streams[stream].substream; -- if (!substream) -- continue; -- -- buf = &substream->dma_buffer; -- if (!buf->area) -- continue; -- dma_free_coherent(pcm->card->dev, buf->bytes, -- buf->area, buf->addr); -- buf->area = NULL; -- } -+ return 0; - } - - /*--------------------------------------------------------------------------*\ -@@ -210,9 +145,6 @@ static int atmel_pcm_hw_params(struct sn - /* this may get called several times by oss emulation - * with different params */ - -- snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); -- runtime->dma_bytes = params_buffer_bytes(params); -- - prtd->params = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream); - prtd->params->dma_intr_handler = atmel_pcm_dma_irq; - -@@ -384,9 +316,7 @@ static const struct snd_soc_component_dr - .prepare = atmel_pcm_prepare, - .trigger = atmel_pcm_trigger, - .pointer = atmel_pcm_pointer, -- .mmap = atmel_pcm_mmap, - .pcm_construct = atmel_pcm_new, -- .pcm_destruct = atmel_pcm_free, - }; - - int atmel_pcm_pdc_platform_register(struct device *dev) diff --git a/target/linux/at91/patches-5.15/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch b/target/linux/at91/patches-5.15/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch deleted file mode 100644 index af1c01bf90..0000000000 --- a/target/linux/at91/patches-5.15/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch +++ /dev/null @@ -1,141 +0,0 @@ -From f39f2312a68ec0843adba08f9c9182ffa5624190 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 16 Dec 2020 14:57:33 +0200 -Subject: [PATCH 145/247] power: reset: at91-sama5d2_shdwc: add support for - sama7g5 - -Add support for SAMA7G5 by adding proper struct reg_config structure -and since SAMA7G5 is not currently on LPDDR setups the commit also -avoid the mapping of DDR controller. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Sebastian Reichel ---- - drivers/power/reset/at91-sama5d2_shdwc.c | 72 ++++++++++++++++++------ - 1 file changed, 54 insertions(+), 18 deletions(-) - ---- a/drivers/power/reset/at91-sama5d2_shdwc.c -+++ b/drivers/power/reset/at91-sama5d2_shdwc.c -@@ -78,9 +78,15 @@ struct pmc_reg_config { - u8 mckr; - }; - -+struct ddrc_reg_config { -+ u32 type_offset; -+ u32 type_mask; -+}; -+ - struct reg_config { - struct shdwc_reg_config shdwc; - struct pmc_reg_config pmc; -+ struct ddrc_reg_config ddrc; - }; - - struct shdwc { -@@ -262,6 +268,10 @@ static const struct reg_config sama5d2_r - .pmc = { - .mckr = 0x30, - }, -+ .ddrc = { -+ .type_offset = AT91_DDRSDRC_MDR, -+ .type_mask = AT91_DDRSDRC_MD -+ }, - }; - - static const struct reg_config sam9x60_reg_config = { -@@ -275,6 +285,23 @@ static const struct reg_config sam9x60_r - .pmc = { - .mckr = 0x28, - }, -+ .ddrc = { -+ .type_offset = AT91_DDRSDRC_MDR, -+ .type_mask = AT91_DDRSDRC_MD -+ }, -+}; -+ -+static const struct reg_config sama7g5_reg_config = { -+ .shdwc = { -+ .wkup_pin_input = 0, -+ .mr_rtcwk_shift = 17, -+ .mr_rttwk_shift = 16, -+ .sr_rtcwk_shift = 5, -+ .sr_rttwk_shift = 4, -+ }, -+ .pmc = { -+ .mckr = 0x28, -+ }, - }; - - static const struct of_device_id at91_shdwc_of_match[] = { -@@ -285,6 +312,10 @@ static const struct of_device_id at91_sh - { - .compatible = "microchip,sam9x60-shdwc", - .data = &sam9x60_reg_config, -+ }, -+ { -+ .compatible = "microchip,sama7g5-shdwc", -+ .data = &sama7g5_reg_config, - }, { - /*sentinel*/ - } -@@ -294,6 +325,7 @@ MODULE_DEVICE_TABLE(of, at91_shdwc_of_ma - static const struct of_device_id at91_pmc_ids[] = { - { .compatible = "atmel,sama5d2-pmc" }, - { .compatible = "microchip,sam9x60-pmc" }, -+ { .compatible = "microchip,sama7g5-pmc" }, - { /* Sentinel. */ } - }; - -@@ -355,30 +387,34 @@ static int __init at91_shdwc_probe(struc - goto clk_disable; - } - -- np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc"); -- if (!np) { -- ret = -ENODEV; -- goto unmap; -- } -+ if (at91_shdwc->rcfg->ddrc.type_mask) { -+ np = of_find_compatible_node(NULL, NULL, -+ "atmel,sama5d3-ddramc"); -+ if (!np) { -+ ret = -ENODEV; -+ goto unmap; -+ } - -- at91_shdwc->mpddrc_base = of_iomap(np, 0); -- of_node_put(np); -+ at91_shdwc->mpddrc_base = of_iomap(np, 0); -+ of_node_put(np); - -- if (!at91_shdwc->mpddrc_base) { -- ret = -ENOMEM; -- goto unmap; -+ if (!at91_shdwc->mpddrc_base) { -+ ret = -ENOMEM; -+ goto unmap; -+ } -+ -+ ddr_type = readl(at91_shdwc->mpddrc_base + -+ at91_shdwc->rcfg->ddrc.type_offset) & -+ at91_shdwc->rcfg->ddrc.type_mask; -+ if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && -+ ddr_type != AT91_DDRSDRC_MD_LPDDR3) { -+ iounmap(at91_shdwc->mpddrc_base); -+ at91_shdwc->mpddrc_base = NULL; -+ } - } - - pm_power_off = at91_poweroff; - -- ddr_type = readl(at91_shdwc->mpddrc_base + AT91_DDRSDRC_MDR) & -- AT91_DDRSDRC_MD; -- if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && -- ddr_type != AT91_DDRSDRC_MD_LPDDR3) { -- iounmap(at91_shdwc->mpddrc_base); -- at91_shdwc->mpddrc_base = NULL; -- } -- - return 0; - - unmap: diff --git a/target/linux/at91/patches-5.15/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch b/target/linux/at91/patches-5.15/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch deleted file mode 100644 index 84dea5a48a..0000000000 --- a/target/linux/at91/patches-5.15/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch +++ /dev/null @@ -1,121 +0,0 @@ -From bd819c78346012ae0627b1cd4f6ceb1b51162c71 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 27 Jan 2021 13:45:44 +0200 -Subject: [PATCH 146/247] pinctrl: at91-pio4: add support for slew-rate - -SAMA7G5 supports slew rate configuration. Adapt the driver for this. -For output switching frequencies lower than 50MHz the slew rate needs to -be enabled. Since most of the pins on SAMA7G5 fall into this category -enabled the slew rate by default. - -Signed-off-by: Claudiu Beznea -Acked-by: Ludovic Desroches -Link: https://lore.kernel.org/r/1611747945-29960-3-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-at91-pio4.c | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - ---- a/drivers/pinctrl/pinctrl-at91-pio4.c -+++ b/drivers/pinctrl/pinctrl-at91-pio4.c -@@ -36,6 +36,7 @@ - #define ATMEL_PIO_DIR_MASK BIT(8) - #define ATMEL_PIO_PUEN_MASK BIT(9) - #define ATMEL_PIO_PDEN_MASK BIT(10) -+#define ATMEL_PIO_SR_MASK BIT(11) - #define ATMEL_PIO_IFEN_MASK BIT(12) - #define ATMEL_PIO_IFSCEN_MASK BIT(13) - #define ATMEL_PIO_OPD_MASK BIT(14) -@@ -76,10 +77,12 @@ - * @nbanks: number of PIO banks - * @last_bank_count: number of lines in the last bank (can be less than - * the rest of the banks). -+ * @slew_rate_support: slew rate support - */ - struct atmel_pioctrl_data { - unsigned nbanks; - unsigned last_bank_count; -+ unsigned int slew_rate_support; - }; - - struct atmel_group { -@@ -117,6 +120,7 @@ struct atmel_pin { - * @pm_suspend_backup: backup/restore register values on suspend/resume - * @dev: device entry for the Atmel PIO controller. - * @node: node of the Atmel PIO controller. -+ * @slew_rate_support: slew rate support - */ - struct atmel_pioctrl { - void __iomem *reg_base; -@@ -138,6 +142,7 @@ struct atmel_pioctrl { - } *pm_suspend_backup; - struct device *dev; - struct device_node *node; -+ unsigned int slew_rate_support; - }; - - static const char * const atmel_functions[] = { -@@ -760,6 +765,13 @@ static int atmel_conf_pin_config_group_g - return -EINVAL; - arg = 1; - break; -+ case PIN_CONFIG_SLEW_RATE: -+ if (!atmel_pioctrl->slew_rate_support) -+ return -EOPNOTSUPP; -+ if (!(res & ATMEL_PIO_SR_MASK)) -+ return -EINVAL; -+ arg = 1; -+ break; - case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: - if (!(res & ATMEL_PIO_DRVSTR_MASK)) - return -EINVAL; -@@ -793,6 +805,10 @@ static int atmel_conf_pin_config_group_s - dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", - __func__, pin_id, configs[i]); - -+ /* Keep slew rate enabled by default. */ -+ if (atmel_pioctrl->slew_rate_support) -+ conf |= ATMEL_PIO_SR_MASK; -+ - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - conf &= (~ATMEL_PIO_PUEN_MASK); -@@ -850,6 +866,13 @@ static int atmel_conf_pin_config_group_s - ATMEL_PIO_SODR); - } - break; -+ case PIN_CONFIG_SLEW_RATE: -+ if (!atmel_pioctrl->slew_rate_support) -+ break; -+ /* And remove it if explicitly requested. */ -+ if (arg == 0) -+ conf &= ~ATMEL_PIO_SR_MASK; -+ break; - case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: - switch (arg) { - case ATMEL_PIO_DRVSTR_LO: -@@ -901,6 +924,8 @@ static void atmel_conf_pin_config_dbg_sh - seq_printf(s, "%s ", "open-drain"); - if (conf & ATMEL_PIO_SCHMITT_MASK) - seq_printf(s, "%s ", "schmitt"); -+ if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK)) -+ seq_printf(s, "%s ", "slew-rate"); - if (conf & ATMEL_PIO_DRVSTR_MASK) { - switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) { - case ATMEL_PIO_DRVSTR_ME: -@@ -994,6 +1019,7 @@ static const struct atmel_pioctrl_data a - static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = { - .nbanks = 5, - .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */ -+ .slew_rate_support = 1, - }; - - static const struct of_device_id atmel_pctrl_of_match[] = { -@@ -1039,6 +1065,7 @@ static int atmel_pinctrl_probe(struct pl - atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK; - atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count; - } -+ atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support; - - atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(atmel_pioctrl->reg_base)) diff --git a/target/linux/at91/patches-5.15/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch b/target/linux/at91/patches-5.15/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch deleted file mode 100644 index 0be811cc97..0000000000 --- a/target/linux/at91/patches-5.15/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch +++ /dev/null @@ -1,340 +0,0 @@ -From 99629d1ad7e4e03ac3324d36b703220555b65566 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 27 Jan 2021 13:45:45 +0200 -Subject: [PATCH 147/247] pinctrl: at91-pio4: fix "Prefer 'unsigned int' to - bare use of 'unsigned'" - -Fix "Prefer 'unsigned int' to bare use of 'unsigned'" checkpatch.pl -warning. - -Signed-off-by: Claudiu Beznea -Acked-by: Ludovic Desroches -Link: https://lore.kernel.org/r/1611747945-29960-4-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-at91-pio4.c | 110 ++++++++++++++-------------- - 1 file changed, 57 insertions(+), 53 deletions(-) - ---- a/drivers/pinctrl/pinctrl-at91-pio4.c -+++ b/drivers/pinctrl/pinctrl-at91-pio4.c -@@ -80,8 +80,8 @@ - * @slew_rate_support: slew rate support - */ - struct atmel_pioctrl_data { -- unsigned nbanks; -- unsigned last_bank_count; -+ unsigned int nbanks; -+ unsigned int last_bank_count; - unsigned int slew_rate_support; - }; - -@@ -91,11 +91,11 @@ struct atmel_group { - }; - - struct atmel_pin { -- unsigned pin_id; -- unsigned mux; -- unsigned ioset; -- unsigned bank; -- unsigned line; -+ unsigned int pin_id; -+ unsigned int mux; -+ unsigned int ioset; -+ unsigned int bank; -+ unsigned int line; - const char *device; - }; - -@@ -125,16 +125,16 @@ struct atmel_pin { - struct atmel_pioctrl { - void __iomem *reg_base; - struct clk *clk; -- unsigned nbanks; -+ unsigned int nbanks; - struct pinctrl_dev *pinctrl_dev; - struct atmel_group *groups; - const char * const *group_names; - struct atmel_pin **pins; -- unsigned npins; -+ unsigned int npins; - struct gpio_chip *gpio_chip; - struct irq_domain *irq_domain; - int *irqs; -- unsigned *pm_wakeup_sources; -+ unsigned int *pm_wakeup_sources; - struct { - u32 imr; - u32 odsr; -@@ -177,11 +177,11 @@ static void atmel_gpio_irq_ack(struct ir - */ - } - --static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type) -+static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type) - { - struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); - struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; -- unsigned reg; -+ unsigned int reg; - - atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, - BIT(pin->line)); -@@ -268,7 +268,7 @@ static struct irq_chip atmel_gpio_irq_ch - .irq_set_wake = atmel_gpio_irq_set_wake, - }; - --static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -+static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) - { - struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); - -@@ -316,11 +316,12 @@ static void atmel_gpio_irq_handler(struc - chained_irq_exit(chip, desc); - } - --static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -+static int atmel_gpio_direction_input(struct gpio_chip *chip, -+ unsigned int offset) - { - struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); - struct atmel_pin *pin = atmel_pioctrl->pins[offset]; -- unsigned reg; -+ unsigned int reg; - - atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, - BIT(pin->line)); -@@ -331,11 +332,11 @@ static int atmel_gpio_direction_input(st - return 0; - } - --static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) -+static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset) - { - struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); - struct atmel_pin *pin = atmel_pioctrl->pins[offset]; -- unsigned reg; -+ unsigned int reg; - - reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); - -@@ -369,12 +370,13 @@ static int atmel_gpio_get_multiple(struc - return 0; - } - --static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, -+static int atmel_gpio_direction_output(struct gpio_chip *chip, -+ unsigned int offset, - int value) - { - struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); - struct atmel_pin *pin = atmel_pioctrl->pins[offset]; -- unsigned reg; -+ unsigned int reg; - - atmel_gpio_write(atmel_pioctrl, pin->bank, - value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, -@@ -389,7 +391,7 @@ static int atmel_gpio_direction_output(s - return 0; - } - --static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) -+static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) - { - struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); - struct atmel_pin *pin = atmel_pioctrl->pins[offset]; -@@ -445,11 +447,11 @@ static struct gpio_chip atmel_gpio_chip - - /* --- PINCTRL --- */ - static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, -- unsigned pin_id) -+ unsigned int pin_id) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); -- unsigned bank = atmel_pioctrl->pins[pin_id]->bank; -- unsigned line = atmel_pioctrl->pins[pin_id]->line; -+ unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; -+ unsigned int line = atmel_pioctrl->pins[pin_id]->line; - void __iomem *addr = atmel_pioctrl->reg_base - + bank * ATMEL_PIO_BANK_OFFSET; - -@@ -461,11 +463,11 @@ static unsigned int atmel_pin_config_rea - } - - static void atmel_pin_config_write(struct pinctrl_dev *pctldev, -- unsigned pin_id, u32 conf) -+ unsigned int pin_id, u32 conf) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); -- unsigned bank = atmel_pioctrl->pins[pin_id]->bank; -- unsigned line = atmel_pioctrl->pins[pin_id]->line; -+ unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; -+ unsigned int line = atmel_pioctrl->pins[pin_id]->line; - void __iomem *addr = atmel_pioctrl->reg_base - + bank * ATMEL_PIO_BANK_OFFSET; - -@@ -483,7 +485,7 @@ static int atmel_pctl_get_groups_count(s - } - - static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, -- unsigned selector) -+ unsigned int selector) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - -@@ -491,19 +493,20 @@ static const char *atmel_pctl_get_group_ - } - - static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, -- unsigned selector, const unsigned **pins, -- unsigned *num_pins) -+ unsigned int selector, -+ const unsigned int **pins, -+ unsigned int *num_pins) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - -- *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin; -+ *pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin; - *num_pins = 1; - - return 0; - } - - static struct atmel_group * --atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin) -+atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - int i; -@@ -524,7 +527,7 @@ static int atmel_pctl_xlate_pinfunc(stru - const char **func_name) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); -- unsigned pin_id, func_id; -+ unsigned int pin_id, func_id; - struct atmel_group *grp; - - pin_id = ATMEL_GET_PIN_NO(pinfunc); -@@ -554,10 +557,10 @@ static int atmel_pctl_xlate_pinfunc(stru - static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, -- unsigned *reserved_maps, -- unsigned *num_maps) -+ unsigned int *reserved_maps, -+ unsigned int *num_maps) - { -- unsigned num_pins, num_configs, reserve; -+ unsigned int num_pins, num_configs, reserve; - unsigned long *configs; - struct property *pins; - u32 pinfunc; -@@ -628,10 +631,10 @@ exit: - static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, -- unsigned *num_maps) -+ unsigned int *num_maps) - { - struct device_node *np; -- unsigned reserved_maps; -+ unsigned int reserved_maps; - int ret; - - *map = NULL; -@@ -679,13 +682,13 @@ static int atmel_pmx_get_functions_count - } - - static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, -- unsigned selector) -+ unsigned int selector) - { - return atmel_functions[selector]; - } - - static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, -- unsigned selector, -+ unsigned int selector, - const char * const **groups, - unsigned * const num_groups) - { -@@ -698,11 +701,11 @@ static int atmel_pmx_get_function_groups - } - - static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, -- unsigned function, -- unsigned group) -+ unsigned int function, -+ unsigned int group) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); -- unsigned pin; -+ unsigned int pin; - u32 conf; - - dev_dbg(pctldev->dev, "enable function %s group %s\n", -@@ -726,13 +729,13 @@ static const struct pinmux_ops atmel_pmx - }; - - static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, -- unsigned group, -+ unsigned int group, - unsigned long *config) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); -- unsigned param = pinconf_to_config_param(*config), arg = 0; -+ unsigned int param = pinconf_to_config_param(*config), arg = 0; - struct atmel_group *grp = atmel_pioctrl->groups + group; -- unsigned pin_id = grp->pin; -+ unsigned int pin_id = grp->pin; - u32 res; - - res = atmel_pin_config_read(pctldev, pin_id); -@@ -786,21 +789,21 @@ static int atmel_conf_pin_config_group_g - } - - static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, -- unsigned group, -+ unsigned int group, - unsigned long *configs, -- unsigned num_configs) -+ unsigned int num_configs) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - struct atmel_group *grp = atmel_pioctrl->groups + group; -- unsigned bank, pin, pin_id = grp->pin; -+ unsigned int bank, pin, pin_id = grp->pin; - u32 mask, conf = 0; - int i; - - conf = atmel_pin_config_read(pctldev, pin_id); - - for (i = 0; i < num_configs; i++) { -- unsigned param = pinconf_to_config_param(configs[i]); -- unsigned arg = pinconf_to_config_argument(configs[i]); -+ unsigned int param = pinconf_to_config_param(configs[i]); -+ unsigned int arg = pinconf_to_config_argument(configs[i]); - - dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", - __func__, pin_id, configs[i]); -@@ -900,7 +903,8 @@ static int atmel_conf_pin_config_group_s - } - - static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, -- struct seq_file *s, unsigned pin_id) -+ struct seq_file *s, -+ unsigned int pin_id) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - u32 conf; -@@ -1108,8 +1112,8 @@ static int atmel_pinctrl_probe(struct pl - return -ENOMEM; - for (i = 0 ; i < atmel_pioctrl->npins; i++) { - struct atmel_group *group = atmel_pioctrl->groups + i; -- unsigned bank = ATMEL_PIO_BANK(i); -- unsigned line = ATMEL_PIO_LINE(i); -+ unsigned int bank = ATMEL_PIO_BANK(i); -+ unsigned int line = ATMEL_PIO_LINE(i); - - atmel_pioctrl->pins[i] = devm_kzalloc(dev, - sizeof(**atmel_pioctrl->pins), GFP_KERNEL); diff --git a/target/linux/at91/patches-5.15/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch b/target/linux/at91/patches-5.15/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch deleted file mode 100644 index 721ddaea00..0000000000 --- a/target/linux/at91/patches-5.15/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 096f58e564aed56936ef6de42a44c3101e9b8ed1 Mon Sep 17 00:00:00 2001 -From: Atish Patra -Date: Wed, 3 Mar 2021 11:55:49 -0800 -Subject: [PATCH 148/247] net: macb: Add default usrio config to default gem - config - -There is no usrio config defined for default gem config leading to -a kernel panic devices that don't define a data. This issue can be -reprdouced with microchip polar fire soc where compatible string -is defined as "cdns,macb". - -Fixes: edac63861db7 ("add userio bits as platform configuration") - -Signed-off-by: Atish Patra -Acked-by: Nicolas Ferre -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb_main.c | 15 ++++++++------- - 1 file changed, 8 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -3868,6 +3868,13 @@ static int macb_init(struct platform_dev - return 0; - } - -+static const struct macb_usrio_config macb_default_usrio = { -+ .mii = MACB_BIT(MII), -+ .rmii = MACB_BIT(RMII), -+ .rgmii = GEM_BIT(RGMII), -+ .refclk = MACB_BIT(CLKEN), -+}; -+ - #if defined(CONFIG_OF) - /* 1518 rounded up */ - #define AT91ETHER_MAX_RBUFF_SZ 0x600 -@@ -4383,13 +4390,6 @@ static int fu540_c000_init(struct platfo - return macb_init(pdev); - } - --static const struct macb_usrio_config macb_default_usrio = { -- .mii = MACB_BIT(MII), -- .rmii = MACB_BIT(RMII), -- .rgmii = GEM_BIT(RGMII), -- .refclk = MACB_BIT(CLKEN), --}; -- - static const struct macb_usrio_config sama7g5_usrio = { - .mii = 0, - .rmii = 1, -@@ -4538,6 +4538,7 @@ static const struct macb_config default_ - .dma_burst_length = 16, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - .jumbo_max_len = 10240, - }; - diff --git a/target/linux/at91/patches-5.15/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch b/target/linux/at91/patches-5.15/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch deleted file mode 100644 index cc7f6583aa..0000000000 --- a/target/linux/at91/patches-5.15/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch +++ /dev/null @@ -1,108 +0,0 @@ -From 746aba88c64e409cbc3757a5f81fad5b5c74bbcc Mon Sep 17 00:00:00 2001 -From: Lee Jones -Date: Wed, 3 Mar 2021 12:41:49 +0000 -Subject: [PATCH 149/247] ARM: at91: pm: Move prototypes to mutually included - header -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Both the caller and the supplier's source file should have access to -the include file containing the prototypes. - -Fixes the following W=1 kernel build warning(s): - - drivers/pinctrl/pinctrl-at91.c:1637:6: warning: no previous prototype for ‘at91_pinctrl_gpio_suspend’ [-Wmissing-prototypes] - 1637 | void at91_pinctrl_gpio_suspend(void) - | ^~~~~~~~~~~~~~~~~~~~~~~~~ - drivers/pinctrl/pinctrl-at91.c:1661:6: warning: no previous prototype for ‘at91_pinctrl_gpio_resume’ [-Wmissing-prototypes] - 1661 | void at91_pinctrl_gpio_resume(void) - | ^~~~~~~~~~~~~~~~~~~~~~~~ - -Cc: Russell King -Cc: Nicolas Ferre -Cc: Alexandre Belloni -Cc: Ludovic Desroches -Signed-off-by: Lee Jones -Acked-by: Linus Walleij -Signed-off-by: Alexandre Belloni -Link: https://lore.kernel.org/r/20210303124149.3149511-1-lee.jones@linaro.org ---- - arch/arm/mach-at91/pm.c | 19 ++++++++----------- - drivers/pinctrl/pinctrl-at91.c | 2 ++ - include/soc/at91/pm.h | 16 ++++++++++++++++ - 3 files changed, 26 insertions(+), 11 deletions(-) - create mode 100644 include/soc/at91/pm.h - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -17,6 +17,8 @@ - #include - #include - -+#include -+ - #include - #include - #include -@@ -25,17 +27,6 @@ - #include "generic.h" - #include "pm.h" - --/* -- * FIXME: this is needed to communicate between the pinctrl driver and -- * the PM implementation in the machine. Possibly part of the PM -- * implementation should be moved down into the pinctrl driver and get -- * called as part of the generic suspend/resume path. -- */ --#ifdef CONFIG_PINCTRL_AT91 --extern void at91_pinctrl_gpio_suspend(void); --extern void at91_pinctrl_gpio_resume(void); --#endif -- - struct at91_soc_pm { - int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); - int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); -@@ -326,6 +317,12 @@ static void at91_pm_suspend(suspend_stat - static int at91_pm_enter(suspend_state_t state) - { - #ifdef CONFIG_PINCTRL_AT91 -+ /* -+ * FIXME: this is needed to communicate between the pinctrl driver and -+ * the PM implementation in the machine. Possibly part of the PM -+ * implementation should be moved down into the pinctrl driver and get -+ * called as part of the generic suspend/resume path. -+ */ - at91_pinctrl_gpio_suspend(); - #endif - ---- a/drivers/pinctrl/pinctrl-at91.c -+++ b/drivers/pinctrl/pinctrl-at91.c -@@ -23,6 +23,8 @@ - /* Since we request GPIOs from ourself */ - #include - -+#include -+ - #include "pinctrl-at91.h" - #include "core.h" - ---- /dev/null -+++ b/include/soc/at91/pm.h -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Atmel Power Management -+ * -+ * Copyright (C) 2020 Atmel -+ * -+ * Author: Lee Jones -+ */ -+ -+#ifndef __SOC_ATMEL_PM_H -+#define __SOC_ATMEL_PM_H -+ -+void at91_pinctrl_gpio_suspend(void); -+void at91_pinctrl_gpio_resume(void); -+ -+#endif /* __SOC_ATMEL_PM_H */ diff --git a/target/linux/at91/patches-5.15/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch b/target/linux/at91/patches-5.15/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch deleted file mode 100644 index 174d0b3ced..0000000000 --- a/target/linux/at91/patches-5.15/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch +++ /dev/null @@ -1,46 +0,0 @@ -From d6493e6f1c42f7ad350ea25e11f0e71fc32e6116 Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Mon, 1 Mar 2021 19:09:00 +0200 -Subject: [PATCH 150/247] ASoC: mchp-i2s-mcc: Add compatible for SAMA7G5 - -Microchip's new SAMA7G5 includes an updated I2S-MCC compatible with the -previous version found on SAM9X60. The new controller includes 8 (4 * 2) -input and output data pins for up to 8 channels for I2S and Left-Justified -formats. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210301170905.835091-3-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/Kconfig | 3 +++ - sound/soc/atmel/mchp-i2s-mcc.c | 3 +++ - 2 files changed, 6 insertions(+) - ---- a/sound/soc/atmel/Kconfig -+++ b/sound/soc/atmel/Kconfig -@@ -126,10 +126,13 @@ config SND_MCHP_SOC_I2S_MCC - Say Y or M if you want to add support for I2S Multi-Channel ASoC - driver on the following Microchip platforms: - - sam9x60 -+ - sama7g5 - - The I2SMCC complies with the Inter-IC Sound (I2S) bus specification - and supports a Time Division Multiplexed (TDM) interface with - external multi-channel audio codecs. -+ Starting with sama7g5, I2S and Left-Justified multi-channel is -+ supported by using multiple data pins, output and input, without TDM. - - config SND_MCHP_SOC_SPDIFTX - tristate "Microchip ASoC driver for boards using S/PDIF TX" ---- a/sound/soc/atmel/mchp-i2s-mcc.c -+++ b/sound/soc/atmel/mchp-i2s-mcc.c -@@ -873,6 +873,9 @@ static const struct of_device_id mchp_i2 - { - .compatible = "microchip,sam9x60-i2smcc", - }, -+ { -+ .compatible = "microchip,sama7g5-i2smcc", -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids); diff --git a/target/linux/at91/patches-5.15/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch b/target/linux/at91/patches-5.15/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch deleted file mode 100644 index 5047e04d5b..0000000000 --- a/target/linux/at91/patches-5.15/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 5bef4e8125d09443b5486971d5550ed285cde4b1 Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Mon, 1 Mar 2021 19:09:01 +0200 -Subject: [PATCH 151/247] ASoC: mchp-i2s-mcc: Add multi-channel support for I2S - and LEFT_J formats - -The latest I2S-MCC available in SAMA7G5 supports multi-channel for I2S and -Left-Justified formats. For this, the new version uses 8 (4 * 2) input and -output pins, with each pin being responsible for 2 channels. This sums up -to a total of 8 channels for synchronous capture and playback. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210301170905.835091-4-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/mchp-i2s-mcc.c | 38 ++++++++++++++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - ---- a/sound/soc/atmel/mchp-i2s-mcc.c -+++ b/sound/soc/atmel/mchp-i2s-mcc.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -225,6 +226,10 @@ static const struct regmap_config mchp_i - .max_register = MCHP_I2SMCC_VERSION, - }; - -+struct mchp_i2s_mcc_soc_data { -+ unsigned int data_pin_pair_num; -+}; -+ - struct mchp_i2s_mcc_dev { - struct wait_queue_head wq_txrdy; - struct wait_queue_head wq_rxrdy; -@@ -232,6 +237,7 @@ struct mchp_i2s_mcc_dev { - struct regmap *regmap; - struct clk *pclk; - struct clk *gclk; -+ const struct mchp_i2s_mcc_soc_data *soc; - struct snd_dmaengine_dai_dma_data playback; - struct snd_dmaengine_dai_dma_data capture; - unsigned int fmt; -@@ -549,6 +555,17 @@ static int mchp_i2s_mcc_hw_params(struct - } - - if (dev->fmt & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) { -+ /* for I2S and LEFT_J one pin is needed for every 2 channels */ -+ if (channels > dev->soc->data_pin_pair_num * 2) { -+ dev_err(dev->dev, -+ "unsupported number of audio channels: %d\n", -+ channels); -+ return -EINVAL; -+ } -+ -+ /* enable for interleaved format */ -+ mrb |= MCHP_I2SMCC_MRB_CRAMODE_REGULAR; -+ - switch (channels) { - case 1: - if (is_playback) -@@ -558,6 +575,12 @@ static int mchp_i2s_mcc_hw_params(struct - break; - case 2: - break; -+ case 4: -+ mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1; -+ break; -+ case 8: -+ mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2; -+ break; - default: - dev_err(dev->dev, "unsupported number of audio channels\n"); - return -EINVAL; -@@ -869,12 +892,22 @@ static const struct snd_soc_component_dr - }; - - #ifdef CONFIG_OF -+static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sam9x60 = { -+ .data_pin_pair_num = 1, -+}; -+ -+static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = { -+ .data_pin_pair_num = 4, -+}; -+ - static const struct of_device_id mchp_i2s_mcc_dt_ids[] = { - { - .compatible = "microchip,sam9x60-i2smcc", -+ .data = &mchp_i2s_mcc_sam9x60, - }, - { - .compatible = "microchip,sama7g5-i2smcc", -+ .data = &mchp_i2s_mcc_sama7g5, - }, - { /* sentinel */ } - }; -@@ -932,6 +965,11 @@ static int mchp_i2s_mcc_probe(struct pla - dev->gclk = NULL; - } - -+ dev->soc = of_device_get_match_data(&pdev->dev); -+ if (!dev->soc) { -+ dev_err(&pdev->dev, "failed to get soc data\n"); -+ return -ENODEV; -+ } - dev->dev = &pdev->dev; - dev->regmap = regmap; - platform_set_drvdata(pdev, dev); diff --git a/target/linux/at91/patches-5.15/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch b/target/linux/at91/patches-5.15/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch deleted file mode 100644 index 6d5a15d36b..0000000000 --- a/target/linux/at91/patches-5.15/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch +++ /dev/null @@ -1,108 +0,0 @@ -From 2bbdc5b38603384996271a8817b0578a2360af2f Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Mon, 1 Mar 2021 19:09:03 +0200 -Subject: [PATCH 152/247] ASoC: mchp-i2s-mcc: Add support to select TDM pins - -SAMA7G5's I2S-MCC has 4 pairs of DIN/DOUT pins. Since TDM only uses a -single pair of pins for synchronous capture and playback, the controller -needs to be told which of the pair is connected. This can be mentioned -using the "microchip,tdm-data-pair" property from DT. The property is -optional, useful only if TDM is used. If it's missing, DIN/DOUT 0 pins -will be used by default. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210301170905.835091-6-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/mchp-i2s-mcc.c | 52 +++++++++++++++++++++++++++++++--- - 1 file changed, 48 insertions(+), 4 deletions(-) - ---- a/sound/soc/atmel/mchp-i2s-mcc.c -+++ b/sound/soc/atmel/mchp-i2s-mcc.c -@@ -100,6 +100,8 @@ - #define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS_COMPACT (7 << 1) - - #define MCHP_I2SMCC_MRA_WIRECFG_MASK GENMASK(5, 4) -+#define MCHP_I2SMCC_MRA_WIRECFG_TDM(pin) (((pin) << 4) & \ -+ MCHP_I2SMCC_MRA_WIRECFG_MASK) - #define MCHP_I2SMCC_MRA_WIRECFG_I2S_1_TDM_0 (0 << 4) - #define MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1 (1 << 4) - #define MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2 (2 << 4) -@@ -245,6 +247,7 @@ struct mchp_i2s_mcc_dev { - unsigned int frame_length; - int tdm_slots; - int channels; -+ u8 tdm_data_pair; - unsigned int gclk_use:1; - unsigned int gclk_running:1; - unsigned int tx_rdy:1; -@@ -589,6 +592,8 @@ static int mchp_i2s_mcc_hw_params(struct - if (!frame_length) - frame_length = 2 * params_physical_width(params); - } else if (dev->fmt & SND_SOC_DAIFMT_DSP_A) { -+ mra |= MCHP_I2SMCC_MRA_WIRECFG_TDM(dev->tdm_data_pair); -+ - if (dev->tdm_slots) { - if (channels % 2 && channels * 2 <= dev->tdm_slots) { - /* -@@ -914,6 +919,45 @@ static const struct of_device_id mchp_i2 - MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids); - #endif - -+static int mchp_i2s_mcc_soc_data_parse(struct platform_device *pdev, -+ struct mchp_i2s_mcc_dev *dev) -+{ -+ int err; -+ -+ if (!dev->soc) { -+ dev_err(&pdev->dev, "failed to get soc data\n"); -+ return -ENODEV; -+ } -+ -+ if (dev->soc->data_pin_pair_num == 1) -+ return 0; -+ -+ err = of_property_read_u8(pdev->dev.of_node, "microchip,tdm-data-pair", -+ &dev->tdm_data_pair); -+ if (err < 0 && err != -EINVAL) { -+ dev_err(&pdev->dev, -+ "bad property data for 'microchip,tdm-data-pair': %d", -+ err); -+ return err; -+ } -+ if (err == -EINVAL) { -+ dev_info(&pdev->dev, -+ "'microchip,tdm-data-pair' not found; assuming DIN/DOUT 0 for TDM\n"); -+ dev->tdm_data_pair = 0; -+ } else { -+ if (dev->tdm_data_pair > dev->soc->data_pin_pair_num - 1) { -+ dev_err(&pdev->dev, -+ "invalid value for 'microchip,tdm-data-pair': %d\n", -+ dev->tdm_data_pair); -+ return -EINVAL; -+ } -+ dev_dbg(&pdev->dev, "TMD format on DIN/DOUT %d pins\n", -+ dev->tdm_data_pair); -+ } -+ -+ return 0; -+} -+ - static int mchp_i2s_mcc_probe(struct platform_device *pdev) - { - struct mchp_i2s_mcc_dev *dev; -@@ -966,10 +1010,10 @@ static int mchp_i2s_mcc_probe(struct pla - } - - dev->soc = of_device_get_match_data(&pdev->dev); -- if (!dev->soc) { -- dev_err(&pdev->dev, "failed to get soc data\n"); -- return -ENODEV; -- } -+ err = mchp_i2s_mcc_soc_data_parse(pdev, dev); -+ if (err < 0) -+ return err; -+ - dev->dev = &pdev->dev; - dev->regmap = regmap; - platform_set_drvdata(pdev, dev); diff --git a/target/linux/at91/patches-5.15/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch b/target/linux/at91/patches-5.15/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch deleted file mode 100644 index 24e0e4de4c..0000000000 --- a/target/linux/at91/patches-5.15/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch +++ /dev/null @@ -1,187 +0,0 @@ -From 36bb4f0ab8e7ef69cc11d4d888aa898223b0e901 Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Mon, 1 Mar 2021 19:09:04 +0200 -Subject: [PATCH 153/247] ASoC: mchp-i2s-mcc: Add FIFOs support - -I2S-MCC found on SAMA7G5 includes 2 FIFOs (capture and playback). When -FIFOs are enabled, bits I2SMCC_ISRA.TXLRDYx and I2SMCC_ISRA.TXRRDYx must -not be used. Bits I2SMCC_ISRB.TXFFRDY and I2SMCC_ISRB.RXFFRDY must be used -instead. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210301170905.835091-7-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/mchp-i2s-mcc.c | 76 +++++++++++++++++++++++++--------- - 1 file changed, 56 insertions(+), 20 deletions(-) - ---- a/sound/soc/atmel/mchp-i2s-mcc.c -+++ b/sound/soc/atmel/mchp-i2s-mcc.c -@@ -176,7 +176,7 @@ - */ - #define MCHP_I2SMCC_MRB_CRAMODE_REGULAR (1 << 0) - --#define MCHP_I2SMCC_MRB_FIFOEN BIT(1) -+#define MCHP_I2SMCC_MRB_FIFOEN BIT(4) - - #define MCHP_I2SMCC_MRB_DMACHUNK_MASK GENMASK(9, 8) - #define MCHP_I2SMCC_MRB_DMACHUNK(no_words) \ -@@ -230,6 +230,7 @@ static const struct regmap_config mchp_i - - struct mchp_i2s_mcc_soc_data { - unsigned int data_pin_pair_num; -+ bool has_fifo; - }; - - struct mchp_i2s_mcc_dev { -@@ -257,7 +258,7 @@ struct mchp_i2s_mcc_dev { - static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id) - { - struct mchp_i2s_mcc_dev *dev = dev_id; -- u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0; -+ u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0, idrb = 0; - irqreturn_t ret = IRQ_NONE; - - regmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra); -@@ -275,24 +276,36 @@ static irqreturn_t mchp_i2s_mcc_interrup - * Tx/Rx ready interrupts are enabled when stopping only, to assure - * availability and to disable clocks if necessary - */ -- idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) | -- MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); -- if (idra) -+ if (dev->soc->has_fifo) { -+ idrb |= pendingb & (MCHP_I2SMCC_INT_TXFFRDY | -+ MCHP_I2SMCC_INT_RXFFRDY); -+ } else { -+ idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) | -+ MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); -+ } -+ if (idra || idrb) - ret = IRQ_HANDLED; - -- if ((imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) && -- (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) == -- (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) { -+ if ((!dev->soc->has_fifo && -+ (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) && -+ (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) == -+ (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) || -+ (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_TXFFRDY)) { - dev->tx_rdy = 1; - wake_up_interruptible(&dev->wq_txrdy); - } -- if ((imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) && -- (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) == -- (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) { -+ if ((!dev->soc->has_fifo && -+ (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) && -+ (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) == -+ (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) || -+ (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_RXFFRDY)) { - dev->rx_rdy = 1; - wake_up_interruptible(&dev->wq_rxrdy); - } -- regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra); -+ if (dev->soc->has_fifo) -+ regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, idrb); -+ else -+ regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra); - - return ret; - } -@@ -664,6 +677,10 @@ static int mchp_i2s_mcc_hw_params(struct - } - } - -+ /* enable FIFO if available */ -+ if (dev->soc->has_fifo) -+ mrb |= MCHP_I2SMCC_MRB_FIFOEN; -+ - /* - * If we are already running, the wanted setup must be - * the same with the one that's currently ongoing -@@ -726,8 +743,13 @@ static int mchp_i2s_mcc_hw_free(struct s - if (err == 0) { - dev_warn_once(dev->dev, - "Timeout waiting for Tx ready\n"); -- regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, -- MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)); -+ if (dev->soc->has_fifo) -+ regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, -+ MCHP_I2SMCC_INT_TXFFRDY); -+ else -+ regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, -+ MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)); -+ - dev->tx_rdy = 1; - } - } else { -@@ -737,8 +759,12 @@ static int mchp_i2s_mcc_hw_free(struct s - if (err == 0) { - dev_warn_once(dev->dev, - "Timeout waiting for Rx ready\n"); -- regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, -- MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); -+ if (dev->soc->has_fifo) -+ regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, -+ MCHP_I2SMCC_INT_RXFFRDY); -+ else -+ regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, -+ MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); - dev->rx_rdy = 1; - } - } -@@ -765,7 +791,7 @@ static int mchp_i2s_mcc_trigger(struct s - struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai); - bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); - u32 cr = 0; -- u32 iera = 0; -+ u32 iera = 0, ierb = 0; - u32 sr; - int err; - -@@ -789,7 +815,10 @@ static int mchp_i2s_mcc_trigger(struct s - * Enable Tx Ready interrupts on all channels - * to assure all data is sent - */ -- iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels); -+ if (dev->soc->has_fifo) -+ ierb = MCHP_I2SMCC_INT_TXFFRDY; -+ else -+ iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels); - } else if (!is_playback && (sr & MCHP_I2SMCC_SR_RXEN)) { - cr = MCHP_I2SMCC_CR_RXDIS; - dev->rx_rdy = 0; -@@ -797,7 +826,10 @@ static int mchp_i2s_mcc_trigger(struct s - * Enable Rx Ready interrupts on all channels - * to assure all data is received - */ -- iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels); -+ if (dev->soc->has_fifo) -+ ierb = MCHP_I2SMCC_INT_RXFFRDY; -+ else -+ iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels); - } - break; - default: -@@ -815,7 +847,10 @@ static int mchp_i2s_mcc_trigger(struct s - } - } - -- regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera); -+ if (dev->soc->has_fifo) -+ regmap_write(dev->regmap, MCHP_I2SMCC_IERB, ierb); -+ else -+ regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera); - regmap_write(dev->regmap, MCHP_I2SMCC_CR, cr); - - return 0; -@@ -903,6 +938,7 @@ static struct mchp_i2s_mcc_soc_data mchp - - static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = { - .data_pin_pair_num = 4, -+ .has_fifo = true, - }; - - static const struct of_device_id mchp_i2s_mcc_dt_ids[] = { diff --git a/target/linux/at91/patches-5.15/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch b/target/linux/at91/patches-5.15/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch deleted file mode 100644 index c61e6b1c90..0000000000 --- a/target/linux/at91/patches-5.15/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch +++ /dev/null @@ -1,49 +0,0 @@ -From dc07cbae6e96843d26e8f10b16e901620bd16462 Mon Sep 17 00:00:00 2001 -From: Tudor Ambarus -Date: Fri, 9 Apr 2021 11:25:22 +0300 -Subject: [PATCH 154/247] pinctrl: at91-pio4: Fix slew rate disablement - -The slew rate was enabled by default for each configuration of the -pin. In case the pin had more than one configuration, even if -we set the slew rate as disabled in the device tree, the next pin -configuration would set again the slew rate enabled by default, -overwriting the slew rate disablement. -Instead of enabling the slew rate by default for each pin configuration, -enable the slew rate by default just once per pin, regardless of the -number of configurations. This way the slew rate disablement will also -work for cases where pins have multiple configurations. - -Fixes: c709135e576b ("pinctrl: at91-pio4: add support for slew-rate") -Signed-off-by: Tudor Ambarus -Reviewed-by: Claudiu Beznea -Acked-by: Ludovic Desroches -Link: https://lore.kernel.org/r/20210409082522.625168-1-tudor.ambarus@microchip.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-at91-pio4.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/pinctrl/pinctrl-at91-pio4.c -+++ b/drivers/pinctrl/pinctrl-at91-pio4.c -@@ -801,6 +801,10 @@ static int atmel_conf_pin_config_group_s - - conf = atmel_pin_config_read(pctldev, pin_id); - -+ /* Keep slew rate enabled by default. */ -+ if (atmel_pioctrl->slew_rate_support) -+ conf |= ATMEL_PIO_SR_MASK; -+ - for (i = 0; i < num_configs; i++) { - unsigned int param = pinconf_to_config_param(configs[i]); - unsigned int arg = pinconf_to_config_argument(configs[i]); -@@ -808,10 +812,6 @@ static int atmel_conf_pin_config_group_s - dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", - __func__, pin_id, configs[i]); - -- /* Keep slew rate enabled by default. */ -- if (atmel_pioctrl->slew_rate_support) -- conf |= ATMEL_PIO_SR_MASK; -- - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - conf &= (~ATMEL_PIO_PUEN_MASK); diff --git a/target/linux/at91/patches-5.15/155-media-atmel-properly-get-pm_runtime.patch b/target/linux/at91/patches-5.15/155-media-atmel-properly-get-pm_runtime.patch deleted file mode 100644 index 58f90db46d..0000000000 --- a/target/linux/at91/patches-5.15/155-media-atmel-properly-get-pm_runtime.patch +++ /dev/null @@ -1,159 +0,0 @@ -From c7660cc977621c4a14d870d523918df067f0db39 Mon Sep 17 00:00:00 2001 -From: Mauro Carvalho Chehab -Date: Fri, 23 Apr 2021 16:47:42 +0200 -Subject: [PATCH 155/247] media: atmel: properly get pm_runtime - -There are several issues in the way the atmel driver handles -pm_runtime_get_sync(): - -- it doesn't check return codes; -- it doesn't properly decrement the usage_count on all places; -- it starts streaming even if pm_runtime_get_sync() fails. -- while it tries to get pm_runtime at the clock enable logic, - it doesn't check if the operation was suceeded. - -Replace all occurrences of it to use the new kAPI: -pm_runtime_resume_and_get(), which ensures that, if the -return code is not negative, the usage_count was incremented. - -With that, add additional checks when this is called, in order -to ensure that errors will be properly addressed. - -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 30 ++++++++++++++----- - drivers/media/platform/atmel/atmel-isi.c | 19 +++++++++--- - 2 files changed, 38 insertions(+), 11 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -294,9 +294,13 @@ static int isc_wait_clk_stable(struct cl - static int isc_clk_prepare(struct clk_hw *hw) - { - struct isc_clk *isc_clk = to_isc_clk(hw); -+ int ret; - -- if (isc_clk->id == ISC_ISPCK) -- pm_runtime_get_sync(isc_clk->dev); -+ if (isc_clk->id == ISC_ISPCK) { -+ ret = pm_runtime_resume_and_get(isc_clk->dev); -+ if (ret < 0) -+ return ret; -+ } - - return isc_wait_clk_stable(hw); - } -@@ -353,9 +357,13 @@ static int isc_clk_is_enabled(struct clk - { - struct isc_clk *isc_clk = to_isc_clk(hw); - u32 status; -+ int ret; - -- if (isc_clk->id == ISC_ISPCK) -- pm_runtime_get_sync(isc_clk->dev); -+ if (isc_clk->id == ISC_ISPCK) { -+ ret = pm_runtime_resume_and_get(isc_clk->dev); -+ if (ret < 0) -+ return 0; -+ } - - regmap_read(isc_clk->regmap, ISC_CLKSR, &status); - -@@ -807,7 +815,12 @@ static int isc_start_streaming(struct vb - goto err_start_stream; - } - -- pm_runtime_get_sync(isc->dev); -+ ret = pm_runtime_resume_and_get(isc->dev); -+ if (ret < 0) { -+ v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n", -+ ret); -+ goto err_pm_get; -+ } - - ret = isc_configure(isc); - if (unlikely(ret)) -@@ -838,7 +851,7 @@ static int isc_start_streaming(struct vb - - err_configure: - pm_runtime_put_sync(isc->dev); -- -+err_pm_get: - v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); - - err_start_stream: -@@ -1809,6 +1822,7 @@ static void isc_awb_work(struct work_str - u32 baysel; - unsigned long flags; - u32 min, max; -+ int ret; - - /* streaming is not active anymore */ - if (isc->stop) -@@ -1831,7 +1845,9 @@ static void isc_awb_work(struct work_str - ctrls->hist_id = hist_id; - baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT; - -- pm_runtime_get_sync(isc->dev); -+ ret = pm_runtime_resume_and_get(isc->dev); -+ if (ret < 0) -+ return; - - /* - * only update if we have all the required histograms and controls ---- a/drivers/media/platform/atmel/atmel-isi.c -+++ b/drivers/media/platform/atmel/atmel-isi.c -@@ -423,7 +423,9 @@ static int start_streaming(struct vb2_qu - struct frame_buffer *buf, *node; - int ret; - -- pm_runtime_get_sync(isi->dev); -+ ret = pm_runtime_resume_and_get(isi->dev); -+ if (ret < 0) -+ return ret; - - /* Enable stream on the sub device */ - ret = v4l2_subdev_call(isi->entity.subdev, video, s_stream, 1); -@@ -783,9 +785,10 @@ static int isi_enum_frameintervals(struc - return 0; - } - --static void isi_camera_set_bus_param(struct atmel_isi *isi) -+static int isi_camera_set_bus_param(struct atmel_isi *isi) - { - u32 cfg1 = 0; -+ int ret; - - /* set bus param for ISI */ - if (isi->pdata.hsync_act_low) -@@ -802,12 +805,16 @@ static void isi_camera_set_bus_param(str - cfg1 |= ISI_CFG1_THMASK_BEATS_16; - - /* Enable PM and peripheral clock before operate isi registers */ -- pm_runtime_get_sync(isi->dev); -+ ret = pm_runtime_resume_and_get(isi->dev); -+ if (ret < 0) -+ return ret; - - isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS); - isi_writel(isi, ISI_CFG1, cfg1); - - pm_runtime_put(isi->dev); -+ -+ return 0; - } - - /* -----------------------------------------------------------------------*/ -@@ -1086,7 +1093,11 @@ static int isi_graph_notify_complete(str - dev_err(isi->dev, "No supported mediabus format found\n"); - return ret; - } -- isi_camera_set_bus_param(isi); -+ ret = isi_camera_set_bus_param(isi); -+ if (ret) { -+ dev_err(isi->dev, "Can't wake up device\n"); -+ return ret; -+ } - - ret = isi_set_default_fmt(isi); - if (ret) { diff --git a/target/linux/at91/patches-5.15/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch b/target/linux/at91/patches-5.15/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch deleted file mode 100644 index f8bdcbef23..0000000000 --- a/target/linux/at91/patches-5.15/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch +++ /dev/null @@ -1,32 +0,0 @@ -From b074b4695004b793a9199716295cb76da6c41686 Mon Sep 17 00:00:00 2001 -From: Jiapeng Chong -Date: Mon, 17 May 2021 12:07:48 +0200 -Subject: [PATCH 156/247] media: atmel: atmel-isc: Remove redundant assignment - to i - -Variable i is being assigned a value however the assignment is -never read, so this redundant assignment can be removed. - -Clean up the following clang-analyzer warning: - -drivers/media/platform/atmel/atmel-isc-base.c:975:2: warning: Value -stored to 'i' is never read [clang-analyzer-deadcode.DeadStores]. - -Reported-by: Abaci Robot -Signed-off-by: Jiapeng Chong -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 1 - - 1 file changed, 1 deletion(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -972,7 +972,6 @@ static int isc_enum_fmt_vid_cap(struct f - - index -= ARRAY_SIZE(controller_formats); - -- i = 0; - supported_index = 0; - - for (i = 0; i < ARRAY_SIZE(formats_list); i++) { diff --git a/target/linux/at91/patches-5.15/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch b/target/linux/at91/patches-5.15/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch deleted file mode 100644 index 6f2d5879c7..0000000000 --- a/target/linux/at91/patches-5.15/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch +++ /dev/null @@ -1,187 +0,0 @@ -From c3f54d192dc7344c5216a3628b67c4bbccbf8c3c Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:56:59 +0200 -Subject: [PATCH 157/247] media: atmel: atmel-isc: specialize gamma table into - product specific - -Separate the gamma table from the isc base file into the specific sama5d2 -product file. -Add a pointer to the gamma table and entries count inside the platform -driver specific struct. - -[hverkuil: made isc_sama5d2_gamma_table static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 47 ++----------------- - drivers/media/platform/atmel/atmel-isc.h | 11 +++-- - .../media/platform/atmel/atmel-sama5d2-isc.c | 45 ++++++++++++++++++ - 3 files changed, 56 insertions(+), 47 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -176,48 +176,6 @@ struct isc_format formats_list[] = { - - }; - --/* Gamma table with gamma 1/2.2 */ --const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES] = { -- /* 0 --> gamma 1/1.8 */ -- { 0x65, 0x66002F, 0x950025, 0xBB0020, 0xDB001D, 0xF8001A, -- 0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012, -- 0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F, -- 0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E, -- 0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C, -- 0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B, -- 0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A, -- 0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A, -- 0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A, -- 0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009, -- 0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 }, -- -- /* 1 --> gamma 1/2 */ -- { 0x7F, 0x800034, 0xB50028, 0xDE0021, 0x100001E, 0x11E001B, -- 0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013, -- 0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F, -- 0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D, -- 0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B, -- 0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A, -- 0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A, -- 0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009, -- 0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009, -- 0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009, -- 0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 }, -- -- /* 2 --> gamma 1/2.2 */ -- { 0x99, 0x9B0038, 0xD4002A, 0xFF0023, 0x122001F, 0x141001B, -- 0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012, -- 0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F, -- 0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C, -- 0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B, -- 0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A, -- 0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009, -- 0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009, -- 0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008, -- 0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007, -- 0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 }, --}; -- - #define ISC_IS_FORMAT_RAW(mbus_code) \ - (((mbus_code) & 0xf000) == 0x3000) - -@@ -691,7 +649,7 @@ static void isc_set_pipeline(struct isc_ - - regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL); - -- gamma = &isc_gamma_table[ctrls->gamma_index][0]; -+ gamma = &isc->gamma_table[ctrls->gamma_index][0]; - regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES); - regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); - regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); -@@ -2085,7 +2043,8 @@ static int isc_ctrl_init(struct isc_devi - - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); -- v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, GAMMA_MAX, 1, 2); -+ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, -+ isc->gamma_max); - isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, - V4L2_CID_AUTO_WHITE_BALANCE, - 0, 1, 1, 1); ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -186,6 +186,10 @@ struct isc_ctrls { - * - * @current_subdev: current subdevice: the sensor - * @subdev_entities: list of subdevice entitites -+ * -+ * @gamma_table: pointer to the table with gamma values, has -+ * gamma_max sets of GAMMA_ENTRIES entries each -+ * @gamma_max: maximum number of sets of inside the gamma_table - */ - struct isc_device { - struct regmap *regmap; -@@ -244,16 +248,17 @@ struct isc_device { - struct v4l2_ctrl *gr_off_ctrl; - struct v4l2_ctrl *gb_off_ctrl; - }; --}; - --#define GAMMA_MAX 2 - #define GAMMA_ENTRIES 64 -+ /* pointer to the defined gamma table */ -+ const u32 (*gamma_table)[GAMMA_ENTRIES]; -+ u32 gamma_max; -+}; - - #define ATMEL_ISC_NAME "atmel-isc" - - extern struct isc_format formats_list[]; - extern const struct isc_format controller_formats[]; --extern const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES]; - extern const struct regmap_config isc_regmap_config; - extern const struct v4l2_async_notifier_operations isc_async_ops; - ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -54,6 +54,48 @@ - - #define ISC_CLK_MAX_DIV 255 - -+/* Gamma table with gamma 1/2.2 */ -+static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { -+ /* 0 --> gamma 1/1.8 */ -+ { 0x65, 0x66002F, 0x950025, 0xBB0020, 0xDB001D, 0xF8001A, -+ 0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012, -+ 0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F, -+ 0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E, -+ 0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C, -+ 0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B, -+ 0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A, -+ 0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A, -+ 0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A, -+ 0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009, -+ 0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 }, -+ -+ /* 1 --> gamma 1/2 */ -+ { 0x7F, 0x800034, 0xB50028, 0xDE0021, 0x100001E, 0x11E001B, -+ 0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013, -+ 0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F, -+ 0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D, -+ 0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B, -+ 0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A, -+ 0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A, -+ 0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009, -+ 0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009, -+ 0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009, -+ 0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 }, -+ -+ /* 2 --> gamma 1/2.2 */ -+ { 0x99, 0x9B0038, 0xD4002A, 0xFF0023, 0x122001F, 0x141001B, -+ 0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012, -+ 0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F, -+ 0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C, -+ 0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B, -+ 0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A, -+ 0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009, -+ 0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009, -+ 0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008, -+ 0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007, -+ 0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 }, -+}; -+ - static int isc_parse_dt(struct device *dev, struct isc_device *isc) - { - struct device_node *np = dev->of_node; -@@ -171,6 +213,9 @@ static int atmel_isc_probe(struct platfo - return ret; - } - -+ isc->gamma_table = isc_sama5d2_gamma_table; -+ isc->gamma_max = 2; -+ - ret = isc_pipeline_init(isc); - if (ret) - return ret; diff --git a/target/linux/at91/patches-5.15/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch b/target/linux/at91/patches-5.15/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch deleted file mode 100644 index 5fd7be8098..0000000000 --- a/target/linux/at91/patches-5.15/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 0576e163d93d08a1ed112bd23f40478ef3fd323d Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:00 +0200 -Subject: [PATCH 158/247] media: atmel: atmel-isc: specialize driver name - constant - -The driver name constant must defined based on product driver, thus moving -the constant directly where it's required. This will allow each ISC based -product to define it's own name. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- - drivers/media/platform/atmel/atmel-isc.h | 2 -- - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 4 ++-- - 3 files changed, 4 insertions(+), 6 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -909,7 +909,7 @@ static int isc_querycap(struct file *fil - { - struct isc_device *isc = video_drvdata(file); - -- strscpy(cap->driver, ATMEL_ISC_NAME, sizeof(cap->driver)); -+ strscpy(cap->driver, "microchip-isc", sizeof(cap->driver)); - strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card)); - snprintf(cap->bus_info, sizeof(cap->bus_info), - "platform:%s", isc->v4l2_dev.name); -@@ -2261,7 +2261,7 @@ static int isc_async_complete(struct v4l - } - - /* Register video device */ -- strscpy(vdev->name, ATMEL_ISC_NAME, sizeof(vdev->name)); -+ strscpy(vdev->name, "microchip-isc", sizeof(vdev->name)); - vdev->release = video_device_release_empty; - vdev->fops = &isc_fops; - vdev->ioctl_ops = &isc_ioctl_ops; ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -255,8 +255,6 @@ struct isc_device { - u32 gamma_max; - }; - --#define ATMEL_ISC_NAME "atmel-isc" -- - extern struct isc_format formats_list[]; - extern const struct isc_format controller_formats[]; - extern const struct regmap_config isc_regmap_config; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -206,7 +206,7 @@ static int atmel_isc_probe(struct platfo - return irq; - - ret = devm_request_irq(dev, irq, isc_interrupt, 0, -- ATMEL_ISC_NAME, isc); -+ "atmel-sama5d2-isc", isc); - if (ret < 0) { - dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", - irq, ret); -@@ -378,7 +378,7 @@ static struct platform_driver atmel_isc_ - .probe = atmel_isc_probe, - .remove = atmel_isc_remove, - .driver = { -- .name = ATMEL_ISC_NAME, -+ .name = "atmel-sama5d2-isc", - .pm = &atmel_isc_dev_pm_ops, - .of_match_table = of_match_ptr(atmel_isc_of_match), - }, diff --git a/target/linux/at91/patches-5.15/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch b/target/linux/at91/patches-5.15/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch deleted file mode 100644 index c6ca456a56..0000000000 --- a/target/linux/at91/patches-5.15/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch +++ /dev/null @@ -1,45 +0,0 @@ -From de8fa25cdf3726c83ac0d7b3b1e28bcb6334aadd Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:01 +0200 -Subject: [PATCH 159/247] media: atmel: atmel-isc: add checks for limiting - frame sizes - -When calling the subdev, certain subdev drivers will overwrite the -frame size and adding sizes which are beyond the ISC's capabilities. -Thus we need to ensure the frame size is cropped to the maximum caps. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -1338,6 +1338,12 @@ static int isc_try_fmt(struct isc_device - - v4l2_fill_pix_format(pixfmt, &format.format); - -+ /* Limit to Atmel ISC hardware capabilities */ -+ if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) -+ pixfmt->width = ISC_MAX_SUPPORT_WIDTH; -+ if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) -+ pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; -+ - pixfmt->field = V4L2_FIELD_NONE; - pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3; - pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height; -@@ -1373,6 +1379,12 @@ static int isc_set_fmt(struct isc_device - if (ret < 0) - return ret; - -+ /* Limit to Atmel ISC hardware capabilities */ -+ if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) -+ pixfmt->width = ISC_MAX_SUPPORT_WIDTH; -+ if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) -+ pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; -+ - isc->fmt = *f; - - if (isc->try_config.sd_format && isc->config.sd_format && diff --git a/target/linux/at91/patches-5.15/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch b/target/linux/at91/patches-5.15/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch deleted file mode 100644 index afa89ed916..0000000000 --- a/target/linux/at91/patches-5.15/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch +++ /dev/null @@ -1,131 +0,0 @@ -From b51819e17260af2ecc152b7dcd61e63bcaa35edf Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:02 +0200 -Subject: [PATCH 160/247] media: atmel: atmel-isc: specialize max width and max - height - -Move the max width and max height constants to the product specific driver -and have them in the device struct. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 28 +++++++++---------- - drivers/media/platform/atmel/atmel-isc.h | 9 ++++-- - .../media/platform/atmel/atmel-sama5d2-isc.c | 7 +++-- - 3 files changed, 25 insertions(+), 19 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -1216,8 +1216,8 @@ static void isc_try_fse(struct isc_devic - * just use the maximum ISC can receive. - */ - if (ret) { -- pad_cfg->try_crop.width = ISC_MAX_SUPPORT_WIDTH; -- pad_cfg->try_crop.height = ISC_MAX_SUPPORT_HEIGHT; -+ pad_cfg->try_crop.width = isc->max_width; -+ pad_cfg->try_crop.height = isc->max_height; - } else { - pad_cfg->try_crop.width = fse.max_width; - pad_cfg->try_crop.height = fse.max_height; -@@ -1294,10 +1294,10 @@ static int isc_try_fmt(struct isc_device - isc->try_config.sd_format = sd_fmt; - - /* Limit to Atmel ISC hardware capabilities */ -- if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) -- pixfmt->width = ISC_MAX_SUPPORT_WIDTH; -- if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) -- pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; -+ if (pixfmt->width > isc->max_width) -+ pixfmt->width = isc->max_width; -+ if (pixfmt->height > isc->max_height) -+ pixfmt->height = isc->max_height; - - /* - * The mbus format is the one the subdev outputs. -@@ -1339,10 +1339,10 @@ static int isc_try_fmt(struct isc_device - v4l2_fill_pix_format(pixfmt, &format.format); - - /* Limit to Atmel ISC hardware capabilities */ -- if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) -- pixfmt->width = ISC_MAX_SUPPORT_WIDTH; -- if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) -- pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; -+ if (pixfmt->width > isc->max_width) -+ pixfmt->width = isc->max_width; -+ if (pixfmt->height > isc->max_height) -+ pixfmt->height = isc->max_height; - - pixfmt->field = V4L2_FIELD_NONE; - pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3; -@@ -1380,10 +1380,10 @@ static int isc_set_fmt(struct isc_device - return ret; - - /* Limit to Atmel ISC hardware capabilities */ -- if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) -- pixfmt->width = ISC_MAX_SUPPORT_WIDTH; -- if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) -- pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; -+ if (f->fmt.pix.width > isc->max_width) -+ f->fmt.pix.width = isc->max_width; -+ if (f->fmt.pix.height > isc->max_height) -+ f->fmt.pix.height = isc->max_height; - - isc->fmt = *f; - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -10,9 +10,6 @@ - */ - #ifndef _ATMEL_ISC_H_ - --#define ISC_MAX_SUPPORT_WIDTH 2592 --#define ISC_MAX_SUPPORT_HEIGHT 1944 -- - #define ISC_CLK_MAX_DIV 255 - - enum isc_clk_id { -@@ -190,6 +187,9 @@ struct isc_ctrls { - * @gamma_table: pointer to the table with gamma values, has - * gamma_max sets of GAMMA_ENTRIES entries each - * @gamma_max: maximum number of sets of inside the gamma_table -+ * -+ * @max_width: maximum frame width, dependent on the internal RAM -+ * @max_height: maximum frame height, dependent on the internal RAM - */ - struct isc_device { - struct regmap *regmap; -@@ -253,6 +253,9 @@ struct isc_device { - /* pointer to the defined gamma table */ - const u32 (*gamma_table)[GAMMA_ENTRIES]; - u32 gamma_max; -+ -+ u32 max_width; -+ u32 max_height; - }; - - extern struct isc_format formats_list[]; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -49,8 +49,8 @@ - #include "atmel-isc-regs.h" - #include "atmel-isc.h" - --#define ISC_MAX_SUPPORT_WIDTH 2592 --#define ISC_MAX_SUPPORT_HEIGHT 1944 -+#define ISC_SAMA5D2_MAX_SUPPORT_WIDTH 2592 -+#define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT 1944 - - #define ISC_CLK_MAX_DIV 255 - -@@ -216,6 +216,9 @@ static int atmel_isc_probe(struct platfo - isc->gamma_table = isc_sama5d2_gamma_table; - isc->gamma_max = 2; - -+ isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; -+ isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; -+ - ret = isc_pipeline_init(isc); - if (ret) - return ret; diff --git a/target/linux/at91/patches-5.15/161-media-atmel-atmel-isc-specialize-dma-cfg.patch b/target/linux/at91/patches-5.15/161-media-atmel-atmel-isc-specialize-dma-cfg.patch deleted file mode 100644 index 410831771e..0000000000 --- a/target/linux/at91/patches-5.15/161-media-atmel-atmel-isc-specialize-dma-cfg.patch +++ /dev/null @@ -1,60 +0,0 @@ -From c42305f52560a1be6fc25a2f23579c7b323de654 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:03 +0200 -Subject: [PATCH 161/247] media: atmel: atmel-isc: specialize dma cfg - -The dma configuration (DCFG) is specific to the product. -Move this configuration in the product specific driver, and add the -field inside the driver struct. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 3 +-- - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 3 +++ - 3 files changed, 6 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -724,8 +724,7 @@ static int isc_configure(struct isc_devi - rlp_mode = isc->config.rlp_cfg_mode; - pipeline = isc->config.bits_pipeline; - -- dcfg = isc->config.dcfg_imode | -- ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; -+ dcfg = isc->config.dcfg_imode | isc->dcfg; - - pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE; - mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW | ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -149,6 +149,7 @@ struct isc_ctrls { - * @hclock: Hclock clock input (refer datasheet) - * @ispck: iscpck clock (refer datasheet) - * @isc_clks: ISC clocks -+ * @dcfg: DMA master configuration, architecture dependent - * - * @dev: Registered device driver - * @v4l2_dev: v4l2 registered device -@@ -196,6 +197,7 @@ struct isc_device { - struct clk *hclock; - struct clk *ispck; - struct isc_clk isc_clks[2]; -+ u32 dcfg; - - struct device *dev; - struct v4l2_device v4l2_dev; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -219,6 +219,9 @@ static int atmel_isc_probe(struct platfo - isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; - isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; - -+ /* sama5d2-isc - 8 bits per beat */ -+ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; -+ - ret = isc_pipeline_init(isc); - if (ret) - return ret; diff --git a/target/linux/at91/patches-5.15/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch b/target/linux/at91/patches-5.15/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch deleted file mode 100644 index 7b8e8ed697..0000000000 --- a/target/linux/at91/patches-5.15/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch +++ /dev/null @@ -1,94 +0,0 @@ -From 6ccda3cf6a102ac4f6e21386d0dd0fedfb066525 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:04 +0200 -Subject: [PATCH 162/247] media: atmel: atmel-isc: extract CSC submodule config - into separate function - -The CSC submodule is a part of the atmel-isc pipeline, and stands for -Color Space Conversion. It is used to apply a matrix transformation to -RGB pixels to convert them to the YUV components. -The CSC submodule should be initialized in the product specific driver -as it's product specific. Other products can implement it differently. - -[hverkuil: made isc_sama5d2_config_csc static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 8 +------- - drivers/media/platform/atmel/atmel-isc.h | 7 +++++++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 15 +++++++++++++++ - 3 files changed, 23 insertions(+), 7 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -654,13 +654,7 @@ static void isc_set_pipeline(struct isc_ - regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); - regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); - -- /* Convert RGB to YUV */ -- regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16)); -- regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16)); -- regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16)); -- regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16)); -- regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16)); -- regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16)); -+ isc->config_csc(isc); - - regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness); - regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast); ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -191,6 +191,9 @@ struct isc_ctrls { - * - * @max_width: maximum frame width, dependent on the internal RAM - * @max_height: maximum frame height, dependent on the internal RAM -+ * -+ * @config_csc: pointer to a function that initializes product -+ * specific CSC module - */ - struct isc_device { - struct regmap *regmap; -@@ -258,6 +261,10 @@ struct isc_device { - - u32 max_width; - u32 max_height; -+ -+ struct { -+ void (*config_csc)(struct isc_device *isc); -+ }; - }; - - extern struct isc_format formats_list[]; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -54,6 +54,19 @@ - - #define ISC_CLK_MAX_DIV 255 - -+static void isc_sama5d2_config_csc(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ /* Convert RGB to YUV */ -+ regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16)); -+ regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16)); -+ regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16)); -+ regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16)); -+ regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16)); -+ regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16)); -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -219,6 +232,8 @@ static int atmel_isc_probe(struct platfo - isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; - isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; - -+ isc->config_csc = isc_sama5d2_config_csc; -+ - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; - diff --git a/target/linux/at91/patches-5.15/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch b/target/linux/at91/patches-5.15/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch deleted file mode 100644 index 832465363b..0000000000 --- a/target/linux/at91/patches-5.15/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 19dd7c72c6c457c147133a7dad8ab28d35538f99 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:05 +0200 -Subject: [PATCH 163/247] media: atmel: atmel-isc-base: add id to clock debug - message - -Add the clock id to the debug message regarding clock setup - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -281,8 +281,8 @@ static int isc_clk_enable(struct clk_hw - unsigned long flags; - unsigned int status; - -- dev_dbg(isc_clk->dev, "ISC CLK: %s, div = %d, parent id = %d\n", -- __func__, isc_clk->div, isc_clk->parent_id); -+ dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n", -+ __func__, id, isc_clk->div, isc_clk->parent_id); - - spin_lock_irqsave(&isc_clk->lock, flags); - regmap_update_bits(regmap, ISC_CLKCFG, diff --git a/target/linux/at91/patches-5.15/164-media-atmel-atmel-isc-create-register-offsets-struct.patch b/target/linux/at91/patches-5.15/164-media-atmel-atmel-isc-create-register-offsets-struct.patch deleted file mode 100644 index bb599618d1..0000000000 --- a/target/linux/at91/patches-5.15/164-media-atmel-atmel-isc-create-register-offsets-struct.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 7a1b082cd81a2496e2687cee7ea1ef04a3020f48 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:06 +0200 -Subject: [PATCH 164/247] media: atmel: atmel-isc: create register offsets - struct - -Create a struct that holds register offsets that are product specific. -Add initially the CSC register. -This allows each product that contains a variant of the ISC to add their -own register offset. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 2 +- - drivers/media/platform/atmel/atmel-isc-regs.h | 3 +++ - drivers/media/platform/atmel/atmel-isc.h | 12 +++++++++++ - .../media/platform/atmel/atmel-sama5d2-isc.c | 20 +++++++++++++------ - 4 files changed, 30 insertions(+), 7 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -2326,7 +2326,7 @@ int isc_pipeline_init(struct isc_device - REG_FIELD(ISC_GAM_CTRL, 1, 1), - REG_FIELD(ISC_GAM_CTRL, 2, 2), - REG_FIELD(ISC_GAM_CTRL, 3, 3), -- REG_FIELD(ISC_CSC_CTRL, 0, 0), -+ REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), - REG_FIELD(ISC_CBC_CTRL, 0, 0), - REG_FIELD(ISC_SUB422_CTRL, 0, 0), - REG_FIELD(ISC_SUB420_CTRL, 0, 0), ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -153,6 +153,9 @@ - /* ISC_Gamma Correction Green Entry Register */ - #define ISC_GAM_RENTRY 0x00000298 - -+/* Offset for CSC register specific to sama5d2 product */ -+#define ISC_SAMA5D2_CSC_OFFSET 0 -+ - /* Color Space Conversion Control Register */ - #define ISC_CSC_CTRL 0x00000398 - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -144,6 +144,14 @@ struct isc_ctrls { - #define ISC_PIPE_LINE_NODE_NUM 11 - - /* -+ * struct isc_reg_offsets - ISC device register offsets -+ * @csc: Offset for the CSC register -+ */ -+struct isc_reg_offsets { -+ u32 csc; -+}; -+ -+/* - * struct isc_device - ISC device driver data/config struct - * @regmap: Register map - * @hclock: Hclock clock input (refer datasheet) -@@ -194,6 +202,8 @@ struct isc_ctrls { - * - * @config_csc: pointer to a function that initializes product - * specific CSC module -+ * -+ * @offsets: struct holding the product specific register offsets - */ - struct isc_device { - struct regmap *regmap; -@@ -265,6 +275,8 @@ struct isc_device { - struct { - void (*config_csc)(struct isc_device *isc); - }; -+ -+ struct isc_reg_offsets offsets; - }; - - extern struct isc_format formats_list[]; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -59,12 +59,18 @@ static void isc_sama5d2_config_csc(struc - struct regmap *regmap = isc->regmap; - - /* Convert RGB to YUV */ -- regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16)); -- regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16)); -- regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16)); -- regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16)); -- regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16)); -- regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16)); -+ regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, -+ 0x42 | (0x81 << 16)); -+ regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, -+ 0x19 | (0x10 << 16)); -+ regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, -+ 0xFDA | (0xFB6 << 16)); -+ regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, -+ 0x70 | (0x80 << 16)); -+ regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, -+ 0x70 | (0xFA2 << 16)); -+ regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, -+ 0xFEE | (0x80 << 16)); - } - - /* Gamma table with gamma 1/2.2 */ -@@ -234,6 +240,8 @@ static int atmel_isc_probe(struct platfo - - isc->config_csc = isc_sama5d2_config_csc; - -+ isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; -+ - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; - diff --git a/target/linux/at91/patches-5.15/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch b/target/linux/at91/patches-5.15/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch deleted file mode 100644 index fd7ed1e94d..0000000000 --- a/target/linux/at91/patches-5.15/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch +++ /dev/null @@ -1,80 +0,0 @@ -From aa31e58d80d233385fa3b972e6b85f293e2a9093 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:07 +0200 -Subject: [PATCH 165/247] media: atmel: atmel-isc: extract CBC submodule config - into separate function - -The CBC submodule is a part of the atmel-isc pipeline, and stands for -Contrast Brightness Control. It is used to apply gains and offsets to the -luma (Y) and chroma (U, V) components of the YUV elements. -The CBC submodule should be initialized in the product specific driver -as it's product specific. Other products can implement it differently - -[hverkuil: made isc_sama5d2_config_cbc static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 4 +--- - drivers/media/platform/atmel/atmel-isc.h | 3 +++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 9 +++++++++ - 3 files changed, 13 insertions(+), 3 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -655,9 +655,7 @@ static void isc_set_pipeline(struct isc_ - regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); - - isc->config_csc(isc); -- -- regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness); -- regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast); -+ isc->config_cbc(isc); - } - - static int isc_update_profile(struct isc_device *isc) ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -202,6 +202,8 @@ struct isc_reg_offsets { - * - * @config_csc: pointer to a function that initializes product - * specific CSC module -+ * @config_cbc: pointer to a function that initializes product -+ * specific CBC module - * - * @offsets: struct holding the product specific register offsets - */ -@@ -274,6 +276,7 @@ struct isc_device { - - struct { - void (*config_csc)(struct isc_device *isc); -+ void (*config_cbc)(struct isc_device *isc); - }; - - struct isc_reg_offsets offsets; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -73,6 +73,14 @@ static void isc_sama5d2_config_csc(struc - 0xFEE | (0x80 << 16)); - } - -+static void isc_sama5d2_config_cbc(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ regmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness); -+ regmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast); -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -239,6 +247,7 @@ static int atmel_isc_probe(struct platfo - isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; - - isc->config_csc = isc_sama5d2_config_csc; -+ isc->config_cbc = isc_sama5d2_config_cbc; - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; - diff --git a/target/linux/at91/patches-5.15/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch b/target/linux/at91/patches-5.15/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch deleted file mode 100644 index 51659f54a4..0000000000 --- a/target/linux/at91/patches-5.15/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 52e4b779ae1af3e322d0c673375dcd51315739d4 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:08 +0200 -Subject: [PATCH 166/247] media: atmel: atmel-isc: add CBC to the reg offsets - struct - -The CBC submodule is a part of the atmel-isc pipeline, and stands for -Contrast Brightness Control. It is used to apply gains and offsets to the -luma (Y) and chroma (U, V) components of the YUV elements. -Add cbc to the reg offsets struct. This will allow different products -to have a different reg offset for this particular module. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 2 +- - drivers/media/platform/atmel/atmel-isc-regs.h | 3 +++ - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 7 +++++-- - 4 files changed, 11 insertions(+), 3 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -2325,7 +2325,7 @@ int isc_pipeline_init(struct isc_device - REG_FIELD(ISC_GAM_CTRL, 2, 2), - REG_FIELD(ISC_GAM_CTRL, 3, 3), - REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), -- REG_FIELD(ISC_CBC_CTRL, 0, 0), -+ REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), - REG_FIELD(ISC_SUB422_CTRL, 0, 0), - REG_FIELD(ISC_SUB420_CTRL, 0, 0), - }; ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -177,6 +177,9 @@ - /* Color Space Conversion CRB OCR Register */ - #define ISC_CSC_CRB_OCR 0x000003b0 - -+/* Offset for CBC register specific to sama5d2 product */ -+#define ISC_SAMA5D2_CBC_OFFSET 0 -+ - /* Contrast And Brightness Control Register */ - #define ISC_CBC_CTRL 0x000003b4 - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -146,9 +146,11 @@ struct isc_ctrls { - /* - * struct isc_reg_offsets - ISC device register offsets - * @csc: Offset for the CSC register -+ * @cbc: Offset for the CBC register - */ - struct isc_reg_offsets { - u32 csc; -+ u32 cbc; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -77,8 +77,10 @@ static void isc_sama5d2_config_cbc(struc - { - struct regmap *regmap = isc->regmap; - -- regmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness); -- regmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast); -+ regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, -+ isc->ctrls.brightness); -+ regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, -+ isc->ctrls.contrast); - } - - /* Gamma table with gamma 1/2.2 */ -@@ -250,6 +252,7 @@ static int atmel_isc_probe(struct platfo - isc->config_cbc = isc_sama5d2_config_cbc; - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; -+ isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.15/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch b/target/linux/at91/patches-5.15/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch deleted file mode 100644 index 6d937fdeb7..0000000000 --- a/target/linux/at91/patches-5.15/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch +++ /dev/null @@ -1,80 +0,0 @@ -From aebb741058a63c3493f4139d11d6f290d5691e9b Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:09 +0200 -Subject: [PATCH 167/247] media: atmel: atmel-isc: add SUB422 and SUB420 to - register offsets - -The SUB submodules are a part of the atmel-isc pipeline, and stand for -Subsampling. They are used to subsample the original YUV 4:4:4 pixel ratio -aspect to either 4:2:2 or 4:2:0. -Add sub420 and sub422 to the reg offsets struct. -This will allow different products to have a different reg offset for these -particular modules. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- - drivers/media/platform/atmel/atmel-isc-regs.h | 4 ++++ - drivers/media/platform/atmel/atmel-isc.h | 4 ++++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 ++ - 4 files changed, 12 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -2326,8 +2326,8 @@ int isc_pipeline_init(struct isc_device - REG_FIELD(ISC_GAM_CTRL, 3, 3), - REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), - REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), -- REG_FIELD(ISC_SUB422_CTRL, 0, 0), -- REG_FIELD(ISC_SUB420_CTRL, 0, 0), -+ REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0), -+ REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0), - }; - - for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) { ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -194,9 +194,13 @@ - #define ISC_CBC_CONTRAST 0x000003c0 - #define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) - -+/* Offset for SUB422 register specific to sama5d2 product */ -+#define ISC_SAMA5D2_SUB422_OFFSET 0 - /* Subsampling 4:4:4 to 4:2:2 Control Register */ - #define ISC_SUB422_CTRL 0x000003c4 - -+/* Offset for SUB420 register specific to sama5d2 product */ -+#define ISC_SAMA5D2_SUB420_OFFSET 0 - /* Subsampling 4:2:2 to 4:2:0 Control Register */ - #define ISC_SUB420_CTRL 0x000003cc - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -147,10 +147,14 @@ struct isc_ctrls { - * struct isc_reg_offsets - ISC device register offsets - * @csc: Offset for the CSC register - * @cbc: Offset for the CBC register -+ * @sub422: Offset for the SUB422 register -+ * @sub420: Offset for the SUB420 register - */ - struct isc_reg_offsets { - u32 csc; - u32 cbc; -+ u32 sub422; -+ u32 sub420; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -253,6 +253,8 @@ static int atmel_isc_probe(struct platfo - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; - isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; -+ isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; -+ isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.15/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch b/target/linux/at91/patches-5.15/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch deleted file mode 100644 index 050e2816c0..0000000000 --- a/target/linux/at91/patches-5.15/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch +++ /dev/null @@ -1,74 +0,0 @@ -From b432a8b0fc88de5b49236482053d8d372c68ee55 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:10 +0200 -Subject: [PATCH 168/247] media: atmel: atmel-isc: add RLP to register offsets - -The RLP submodule is a part of the atmel-isc pipeline, and stands for -Rounding,Limiting and Packaging. It used to extract specific data from the -ISC pipeline. For example if we want to output greyscale 8 bit, we would -use limiting to 8 bits, and packaging to Luma component only. -Add rlp to the reg offsets struct. -This will allow different products to have a different reg offset for this -particular module. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- - drivers/media/platform/atmel/atmel-isc-regs.h | 2 ++ - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 + - 4 files changed, 7 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -726,8 +726,8 @@ static int isc_configure(struct isc_devi - - regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); - -- regmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK, -- rlp_mode); -+ regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, -+ ISC_RLP_CFG_MODE_MASK, rlp_mode); - - regmap_write(regmap, ISC_DCFG, dcfg); - ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -204,6 +204,8 @@ - /* Subsampling 4:2:2 to 4:2:0 Control Register */ - #define ISC_SUB420_CTRL 0x000003cc - -+/* Offset for RLP register specific to sama5d2 product */ -+#define ISC_SAMA5D2_RLP_OFFSET 0 - /* Rounding, Limiting and Packing Configuration Register */ - #define ISC_RLP_CFG 0x000003d0 - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -149,12 +149,14 @@ struct isc_ctrls { - * @cbc: Offset for the CBC register - * @sub422: Offset for the SUB422 register - * @sub420: Offset for the SUB420 register -+ * @rlp: Offset for the RLP register - */ - struct isc_reg_offsets { - u32 csc; - u32 cbc; - u32 sub422; - u32 sub420; -+ u32 rlp; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -255,6 +255,7 @@ static int atmel_isc_probe(struct platfo - isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; - isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; - isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; -+ isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.15/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch b/target/linux/at91/patches-5.15/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch deleted file mode 100644 index 6ce49e67ff..0000000000 --- a/target/linux/at91/patches-5.15/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 8c19aa14b8303a0e7c4bae42f3f00f9a2a65b0db Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:11 +0200 -Subject: [PATCH 169/247] media: atmel: atmel-isc: add HIS to register offsets - -The HIS submodule is a part of the atmel-isc pipeline, and stands for -Histogram. This module performs a color histogram that can be read and used -by the main processor. -Add his to the reg offsets struct. -This will allow different products to have a different reg offset for this -particular module. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 11 +++++++---- - drivers/media/platform/atmel/atmel-isc-regs.h | 2 ++ - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 + - 4 files changed, 12 insertions(+), 4 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -686,12 +686,13 @@ static void isc_set_histogram(struct isc - struct isc_ctrls *ctrls = &isc->ctrls; - - if (enable) { -- regmap_write(regmap, ISC_HIS_CFG, -+ regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, - ISC_HIS_CFG_MODE_GR | - (isc->config.sd_format->cfa_baycfg - << ISC_HIS_CFG_BAYSEL_SHIFT) | - ISC_HIS_CFG_RAR); -- regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN); -+ regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, -+ ISC_HIS_CTRL_EN); - regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE); - ctrls->hist_id = ISC_HIS_CFG_MODE_GR; - isc_update_profile(isc); -@@ -700,7 +701,8 @@ static void isc_set_histogram(struct isc - ctrls->hist_stat = HIST_ENABLED; - } else { - regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE); -- regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_DIS); -+ regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, -+ ISC_HIS_CTRL_DIS); - - ctrls->hist_stat = HIST_DISABLED; - } -@@ -1836,7 +1838,8 @@ static void isc_awb_work(struct work_str - ctrls->awb = ISC_WB_NONE; - } - } -- regmap_write(regmap, ISC_HIS_CFG, hist_id | baysel | ISC_HIS_CFG_RAR); -+ regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, -+ hist_id | baysel | ISC_HIS_CFG_RAR); - isc_update_profile(isc); - /* if awb has been disabled, we don't need to start another histogram */ - if (ctrls->awb) ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -224,6 +224,8 @@ - #define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc - #define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) - -+/* Offset for HIS register specific to sama5d2 product */ -+#define ISC_SAMA5D2_HIS_OFFSET 0 - /* Histogram Control Register */ - #define ISC_HIS_CTRL 0x000003d4 - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -150,6 +150,7 @@ struct isc_ctrls { - * @sub422: Offset for the SUB422 register - * @sub420: Offset for the SUB420 register - * @rlp: Offset for the RLP register -+ * @his: Offset for the HIS related registers - */ - struct isc_reg_offsets { - u32 csc; -@@ -157,6 +158,7 @@ struct isc_reg_offsets { - u32 sub422; - u32 sub420; - u32 rlp; -+ u32 his; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -256,6 +256,7 @@ static int atmel_isc_probe(struct platfo - isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; - isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; - isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; -+ isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.15/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch b/target/linux/at91/patches-5.15/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch deleted file mode 100644 index ef7104e587..0000000000 --- a/target/linux/at91/patches-5.15/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 7173e54070a9b530c8c16e0a507be71385133abd Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:12 +0200 -Subject: [PATCH 170/247] media: atmel: atmel-isc: add DMA to register offsets - -The DMA submodule is a part of the atmel-isc pipeline, and stands for -Direct Memory Access. It acts like a master on the AXI bus of the SoC, and -can directly write the RAM area with the pixel data from the ISC internal -sram. -Add dma to the reg offsets struct. -This will allow different products to have a different reg offset for this -particular module. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 19 ++++++++++++------- - drivers/media/platform/atmel/atmel-isc-regs.h | 3 +++ - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - .../media/platform/atmel/atmel-sama5d2-isc.c | 1 + - 4 files changed, 18 insertions(+), 7 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -601,16 +601,20 @@ static void isc_start_dma(struct isc_dev - ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN); - - addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0); -- regmap_write(regmap, ISC_DAD0, addr0); -+ regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0); - - switch (isc->config.fourcc) { - case V4L2_PIX_FMT_YUV420: -- regmap_write(regmap, ISC_DAD1, addr0 + (sizeimage * 2) / 3); -- regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 5) / 6); -+ regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, -+ addr0 + (sizeimage * 2) / 3); -+ regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, -+ addr0 + (sizeimage * 5) / 6); - break; - case V4L2_PIX_FMT_YUV422P: -- regmap_write(regmap, ISC_DAD1, addr0 + sizeimage / 2); -- regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 3) / 4); -+ regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, -+ addr0 + sizeimage / 2); -+ regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, -+ addr0 + (sizeimage * 3) / 4); - break; - default: - break; -@@ -618,7 +622,8 @@ static void isc_start_dma(struct isc_dev - - dctrl_dview = isc->config.dctrl_dview; - -- regmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS); -+ regmap_write(regmap, ISC_DCTRL + isc->offsets.dma, -+ dctrl_dview | ISC_DCTRL_IE_IS); - spin_lock(&isc->awb_lock); - regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE); - spin_unlock(&isc->awb_lock); -@@ -731,7 +736,7 @@ static int isc_configure(struct isc_devi - regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, - ISC_RLP_CFG_MODE_MASK, rlp_mode); - -- regmap_write(regmap, ISC_DCFG, dcfg); -+ regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); - - /* Set the pipeline */ - isc_set_pipeline(isc, pipeline); ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -247,6 +247,9 @@ - - #define ISC_HIS_CFG_RAR BIT(8) - -+/* Offset for DMA register specific to sama5d2 product */ -+#define ISC_SAMA5D2_DMA_OFFSET 0 -+ - /* DMA Configuration Register */ - #define ISC_DCFG 0x000003e0 - #define ISC_DCFG_IMODE_PACKED8 0x0 ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -151,6 +151,7 @@ struct isc_ctrls { - * @sub420: Offset for the SUB420 register - * @rlp: Offset for the RLP register - * @his: Offset for the HIS related registers -+ * @dma: Offset for the DMA related registers - */ - struct isc_reg_offsets { - u32 csc; -@@ -159,6 +160,7 @@ struct isc_reg_offsets { - u32 sub420; - u32 rlp; - u32 his; -+ u32 dma; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -257,6 +257,7 @@ static int atmel_isc_probe(struct platfo - isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; - isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; - isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; -+ isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.15/171-media-atmel-atmel-isc-add-support-for-version-regist.patch b/target/linux/at91/patches-5.15/171-media-atmel-atmel-isc-add-support-for-version-regist.patch deleted file mode 100644 index b582945b99..0000000000 --- a/target/linux/at91/patches-5.15/171-media-atmel-atmel-isc-add-support-for-version-regist.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 0939b0a92acca11a5a3b0de5dd70434e17e40ed3 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:13 +0200 -Subject: [PATCH 171/247] media: atmel: atmel-isc: add support for version - register - -Add support for version register and print it at probe time. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-regs.h | 5 +++++ - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 5 +++++ - 3 files changed, 12 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -295,6 +295,11 @@ - /* DMA Address 2 Register */ - #define ISC_DAD2 0x000003fc - -+/* Offset for version register specific to sama5d2 product */ -+#define ISC_SAMA5D2_VERSION_OFFSET 0 -+/* Version Register */ -+#define ISC_VERSION 0x0000040c -+ - /* Histogram Entry */ - #define ISC_HIS_ENTRY 0x00000410 - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -152,6 +152,7 @@ struct isc_ctrls { - * @rlp: Offset for the RLP register - * @his: Offset for the HIS related registers - * @dma: Offset for the DMA related registers -+ * @version: Offset for the version register - */ - struct isc_reg_offsets { - u32 csc; -@@ -161,6 +162,7 @@ struct isc_reg_offsets { - u32 rlp; - u32 his; - u32 dma; -+ u32 version; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -210,6 +210,7 @@ static int atmel_isc_probe(struct platfo - struct isc_subdev_entity *subdev_entity; - int irq; - int ret; -+ u32 ver; - - isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL); - if (!isc) -@@ -258,6 +259,7 @@ static int atmel_isc_probe(struct platfo - isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; - isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; - isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; -+ isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; -@@ -346,6 +348,9 @@ static int atmel_isc_probe(struct platfo - pm_runtime_enable(dev); - pm_request_idle(dev); - -+ regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); -+ dev_info(dev, "Microchip ISC version %x\n", ver); -+ - return 0; - - cleanup_subdev: diff --git a/target/linux/at91/patches-5.15/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch b/target/linux/at91/patches-5.15/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch deleted file mode 100644 index c48301cf25..0000000000 --- a/target/linux/at91/patches-5.15/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch +++ /dev/null @@ -1,71 +0,0 @@ -From bce46a8a620a796ca3cfe5bff61baf6744074986 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:14 +0200 -Subject: [PATCH 172/247] media: atmel: atmel-isc: add his_entry to register - offsets - -Add his_entry to the reg offsets struct. -This will allow different products to have a different reg offset for this -particular module. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 3 ++- - drivers/media/platform/atmel/atmel-isc-regs.h | 2 ++ - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 + - 4 files changed, 7 insertions(+), 1 deletion(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -1684,7 +1684,8 @@ static void isc_hist_count(struct isc_de - *min = 0; - *max = HIST_ENTRIES; - -- regmap_bulk_read(regmap, ISC_HIS_ENTRY, hist_entry, HIST_ENTRIES); -+ regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry, -+ hist_entry, HIST_ENTRIES); - - *hist_count = 0; - /* ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -300,6 +300,8 @@ - /* Version Register */ - #define ISC_VERSION 0x0000040c - -+/* Offset for version register specific to sama5d2 product */ -+#define ISC_SAMA5D2_HIS_ENTRY_OFFSET 0 - /* Histogram Entry */ - #define ISC_HIS_ENTRY 0x00000410 - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -153,6 +153,7 @@ struct isc_ctrls { - * @his: Offset for the HIS related registers - * @dma: Offset for the DMA related registers - * @version: Offset for the version register -+ * @his_entry: Offset for the HIS entries registers - */ - struct isc_reg_offsets { - u32 csc; -@@ -163,6 +164,7 @@ struct isc_reg_offsets { - u32 his; - u32 dma; - u32 version; -+ u32 his_entry; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -260,6 +260,7 @@ static int atmel_isc_probe(struct platfo - isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; - isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; - isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; -+ isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.15/173-media-atmel-atmel-isc-add-register-description-for-a.patch b/target/linux/at91/patches-5.15/173-media-atmel-atmel-isc-add-register-description-for-a.patch deleted file mode 100644 index f701ede09c..0000000000 --- a/target/linux/at91/patches-5.15/173-media-atmel-atmel-isc-add-register-description-for-a.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 87b581b1197df5f77bd65819d0428f2404c6b764 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:15 +0200 -Subject: [PATCH 173/247] media: atmel: atmel-isc: add register description for - additional modules - -Add register description for additional pipeline modules: the -Defective Pixel Correction (DPC) and the Vertical and Horizontal Scaler(VHXS) - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-regs.h | 67 +++++++++++++++++++ - 1 file changed, 67 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -90,6 +90,46 @@ - #define ISC_INT_DDONE BIT(8) - #define ISC_INT_HISDONE BIT(12) - -+/* ISC DPC Control Register */ -+#define ISC_DPC_CTRL 0x40 -+ -+#define ISC_DPC_CTRL_DPCEN BIT(0) -+#define ISC_DPC_CTRL_GDCEN BIT(1) -+#define ISC_DPC_CTRL_BLCEN BIT(2) -+ -+/* ISC DPC Config Register */ -+#define ISC_DPC_CFG 0x44 -+ -+#define ISC_DPC_CFG_BAYSEL_SHIFT 0 -+ -+#define ISC_DPC_CFG_EITPOL BIT(4) -+ -+#define ISC_DPC_CFG_TA_ENABLE BIT(14) -+#define ISC_DPC_CFG_TC_ENABLE BIT(13) -+#define ISC_DPC_CFG_TM_ENABLE BIT(12) -+ -+#define ISC_DPC_CFG_RE_MODE BIT(17) -+ -+#define ISC_DPC_CFG_GDCCLP_SHIFT 20 -+#define ISC_DPC_CFG_GDCCLP_MASK GENMASK(22, 20) -+ -+#define ISC_DPC_CFG_BLOFF_SHIFT 24 -+#define ISC_DPC_CFG_BLOFF_MASK GENMASK(31, 24) -+ -+#define ISC_DPC_CFG_BAYCFG_SHIFT 0 -+#define ISC_DPC_CFG_BAYCFG_MASK GENMASK(1, 0) -+/* ISC DPC Threshold Median Register */ -+#define ISC_DPC_THRESHM 0x48 -+ -+/* ISC DPC Threshold Closest Register */ -+#define ISC_DPC_THRESHC 0x4C -+ -+/* ISC DPC Threshold Average Register */ -+#define ISC_DPC_THRESHA 0x50 -+ -+/* ISC DPC STatus Register */ -+#define ISC_DPC_SR 0x54 -+ - /* ISC White Balance Control Register */ - #define ISC_WB_CTRL 0x00000058 - -@@ -153,6 +193,33 @@ - /* ISC_Gamma Correction Green Entry Register */ - #define ISC_GAM_RENTRY 0x00000298 - -+/* ISC VHXS Control Register */ -+#define ISC_VHXS_CTRL 0x398 -+ -+/* ISC VHXS Source Size Register */ -+#define ISC_VHXS_SS 0x39C -+ -+/* ISC VHXS Destination Size Register */ -+#define ISC_VHXS_DS 0x3A0 -+ -+/* ISC Vertical Factor Register */ -+#define ISC_VXS_FACT 0x3a4 -+ -+/* ISC Horizontal Factor Register */ -+#define ISC_HXS_FACT 0x3a8 -+ -+/* ISC Vertical Config Register */ -+#define ISC_VXS_CFG 0x3ac -+ -+/* ISC Horizontal Config Register */ -+#define ISC_HXS_CFG 0x3b0 -+ -+/* ISC Vertical Tap Register */ -+#define ISC_VXS_TAP 0x3b4 -+ -+/* ISC Horizontal Tap Register */ -+#define ISC_HXS_TAP 0x434 -+ - /* Offset for CSC register specific to sama5d2 product */ - #define ISC_SAMA5D2_CSC_OFFSET 0 - diff --git a/target/linux/at91/patches-5.15/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch b/target/linux/at91/patches-5.15/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch deleted file mode 100644 index 7cb5233c2e..0000000000 --- a/target/linux/at91/patches-5.15/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 58a6cc3c7eecd16208cd16b92b4eaf8385e69696 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:16 +0200 -Subject: [PATCH 174/247] media: atmel: atmel-isc: extend pipeline with extra - modules - -Newer ISC pipelines have the additional modules of -Defective Pixel Correction -> DPC itself, -Defective Pixel Correction -> Green Disparity Correction (DPC_GDC) -Defective Pixel Correction -> Black Level Correction (DPC_BLC) -Vertical and Horizontal Scaler -> VHXS - -Some products have this full pipeline (sama7g5), other products do not (sama5d2) - -Add the modules to the isc base, and also extend the register range to include -the modules. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 11 ++++++-- - drivers/media/platform/atmel/atmel-isc.h | 28 +++++++++++-------- - 2 files changed, 25 insertions(+), 14 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -2324,8 +2324,14 @@ int isc_pipeline_init(struct isc_device - struct regmap_field *regs; - unsigned int i; - -- /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */ -+ /* -+ * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC--> -+ * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420 -+ */ - const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = { -+ REG_FIELD(ISC_DPC_CTRL, 0, 0), -+ REG_FIELD(ISC_DPC_CTRL, 1, 1), -+ REG_FIELD(ISC_DPC_CTRL, 2, 2), - REG_FIELD(ISC_WB_CTRL, 0, 0), - REG_FIELD(ISC_CFA_CTRL, 0, 0), - REG_FIELD(ISC_CC_CTRL, 0, 0), -@@ -2333,6 +2339,7 @@ int isc_pipeline_init(struct isc_device - REG_FIELD(ISC_GAM_CTRL, 1, 1), - REG_FIELD(ISC_GAM_CTRL, 2, 2), - REG_FIELD(ISC_GAM_CTRL, 3, 3), -+ REG_FIELD(ISC_VHXS_CTRL, 0, 0), - REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), - REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), - REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0), -@@ -2351,7 +2358,7 @@ int isc_pipeline_init(struct isc_device - } - - /* regmap configuration */ --#define ATMEL_ISC_REG_MAX 0xbfc -+#define ATMEL_ISC_REG_MAX 0xd5c - const struct regmap_config isc_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -67,17 +67,21 @@ struct isc_format { - }; - - /* Pipeline bitmap */ --#define WB_ENABLE BIT(0) --#define CFA_ENABLE BIT(1) --#define CC_ENABLE BIT(2) --#define GAM_ENABLE BIT(3) --#define GAM_BENABLE BIT(4) --#define GAM_GENABLE BIT(5) --#define GAM_RENABLE BIT(6) --#define CSC_ENABLE BIT(7) --#define CBC_ENABLE BIT(8) --#define SUB422_ENABLE BIT(9) --#define SUB420_ENABLE BIT(10) -+#define DPC_DPCENABLE BIT(0) -+#define DPC_GDCENABLE BIT(1) -+#define DPC_BLCENABLE BIT(2) -+#define WB_ENABLE BIT(3) -+#define CFA_ENABLE BIT(4) -+#define CC_ENABLE BIT(5) -+#define GAM_ENABLE BIT(6) -+#define GAM_BENABLE BIT(7) -+#define GAM_GENABLE BIT(8) -+#define GAM_RENABLE BIT(9) -+#define VHXS_ENABLE BIT(10) -+#define CSC_ENABLE BIT(11) -+#define CBC_ENABLE BIT(12) -+#define SUB422_ENABLE BIT(13) -+#define SUB420_ENABLE BIT(14) - - #define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE) - -@@ -141,7 +145,7 @@ struct isc_ctrls { - u32 hist_minmax[HIST_BAYER][2]; - }; - --#define ISC_PIPE_LINE_NODE_NUM 11 -+#define ISC_PIPE_LINE_NODE_NUM 15 - - /* - * struct isc_reg_offsets - ISC device register offsets diff --git a/target/linux/at91/patches-5.15/175-media-atmel-atmel-isc-add-CC-initialization-function.patch b/target/linux/at91/patches-5.15/175-media-atmel-atmel-isc-add-CC-initialization-function.patch deleted file mode 100644 index 69491d7d13..0000000000 --- a/target/linux/at91/patches-5.15/175-media-atmel-atmel-isc-add-CC-initialization-function.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 0db91d2a803221c313c9f2cd1d71050d7c5a7b5b Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:17 +0200 -Subject: [PATCH 175/247] media: atmel: atmel-isc: add CC initialization - function - -The CC submodule is a part of the atmel-isc pipeline, and stands for -Color Correction. It is used to apply gains and offsets to the -chroma (U, V) components of the YUV elements. -Implement the CC submodule initialization, as a product -specific function, which currently configures the neutral point in color -correction. - -[hverkuil: made isc_sama5d2_config_cc static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 1 + - drivers/media/platform/atmel/atmel-isc.h | 3 +++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 14 ++++++++++++++ - 3 files changed, 18 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -661,6 +661,7 @@ static void isc_set_pipeline(struct isc_ - - isc->config_csc(isc); - isc->config_cbc(isc); -+ isc->config_cc(isc); - } - - static int isc_update_profile(struct isc_device *isc) ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -224,6 +224,8 @@ struct isc_reg_offsets { - * specific CSC module - * @config_cbc: pointer to a function that initializes product - * specific CBC module -+ * @config_cc: pointer to a function that initializes product -+ * specific CC module - * - * @offsets: struct holding the product specific register offsets - */ -@@ -297,6 +299,7 @@ struct isc_device { - struct { - void (*config_csc)(struct isc_device *isc); - void (*config_cbc)(struct isc_device *isc); -+ void (*config_cc)(struct isc_device *isc); - }; - - struct isc_reg_offsets offsets; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -83,6 +83,19 @@ static void isc_sama5d2_config_cbc(struc - isc->ctrls.contrast); - } - -+static void isc_sama5d2_config_cc(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ /* Configure each register at the neutral fixed point 1.0 or 0.0 */ -+ regmap_write(regmap, ISC_CC_RR_RG, (1 << 8)); -+ regmap_write(regmap, ISC_CC_RB_OR, 0); -+ regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16); -+ regmap_write(regmap, ISC_CC_GB_OG, 0); -+ regmap_write(regmap, ISC_CC_BR_BG, 0); -+ regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -251,6 +264,7 @@ static int atmel_isc_probe(struct platfo - - isc->config_csc = isc_sama5d2_config_csc; - isc->config_cbc = isc_sama5d2_config_cbc; -+ isc->config_cc = isc_sama5d2_config_cc; - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; - isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; diff --git a/target/linux/at91/patches-5.15/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch b/target/linux/at91/patches-5.15/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch deleted file mode 100644 index 35c839692c..0000000000 --- a/target/linux/at91/patches-5.15/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 0a75c502eac4f2ef71b6c3e0b3a01db1b3c37ba9 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:18 +0200 -Subject: [PATCH 176/247] media: atmel: atmel-isc: create product specific v4l2 - controls config - -Create product specific callback for initializing v4l2 controls. -Call this from v4l2 controls init function. - -[hverkuil: made isc_sama5d2_config_ctrls static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 5 +++-- - drivers/media/platform/atmel/atmel-isc.h | 5 +++++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 12 ++++++++++++ - 3 files changed, 20 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -2051,11 +2051,12 @@ static int isc_ctrl_init(struct isc_devi - if (ret < 0) - return ret; - -+ /* Initialize product specific controls. For example, contrast */ -+ isc->config_ctrls(isc, ops); -+ - ctrls->brightness = 0; -- ctrls->contrast = 256; - - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); -- v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, - isc->gamma_max); - isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -226,6 +226,8 @@ struct isc_reg_offsets { - * specific CBC module - * @config_cc: pointer to a function that initializes product - * specific CC module -+ * @config_ctrls: pointer to a functoin that initializes product -+ * specific v4l2 controls. - * - * @offsets: struct holding the product specific register offsets - */ -@@ -300,6 +302,9 @@ struct isc_device { - void (*config_csc)(struct isc_device *isc); - void (*config_cbc)(struct isc_device *isc); - void (*config_cc)(struct isc_device *isc); -+ -+ void (*config_ctrls)(struct isc_device *isc, -+ const struct v4l2_ctrl_ops *ops); - }; - - struct isc_reg_offsets offsets; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -96,6 +96,17 @@ static void isc_sama5d2_config_cc(struct - regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); - } - -+static void isc_sama5d2_config_ctrls(struct isc_device *isc, -+ const struct v4l2_ctrl_ops *ops) -+{ -+ struct isc_ctrls *ctrls = &isc->ctrls; -+ struct v4l2_ctrl_handler *hdl = &ctrls->handler; -+ -+ ctrls->contrast = 256; -+ -+ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -265,6 +276,7 @@ static int atmel_isc_probe(struct platfo - isc->config_csc = isc_sama5d2_config_csc; - isc->config_cbc = isc_sama5d2_config_cbc; - isc->config_cc = isc_sama5d2_config_cc; -+ isc->config_ctrls = isc_sama5d2_config_ctrls; - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; - isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; diff --git a/target/linux/at91/patches-5.15/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch b/target/linux/at91/patches-5.15/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch deleted file mode 100644 index ef396f84cf..0000000000 --- a/target/linux/at91/patches-5.15/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch +++ /dev/null @@ -1,75 +0,0 @@ -From d53eb90044c19ba22b51978fcb007d9b5200b83a Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:19 +0200 -Subject: [PATCH 177/247] media: atmel: atmel-isc: create callback for DPC - submodule product specific - -The DPC submodule is a part of the atmel-isc pipeline, and stands for -Defective Pixel Correction. Its purpose is to detect defective pixels and -correct them if possible with the help of adjacent pixels. -Create a product specific callback for initializing the DPC submodule -of the pipeline. -For sama5d2 product, this module does not exist, thus this function is a noop. - -[hverkuil: made isc_sama5d2_config_dpc static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 1 + - drivers/media/platform/atmel/atmel-isc.h | 3 +++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++ - 3 files changed, 10 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -659,6 +659,7 @@ static void isc_set_pipeline(struct isc_ - regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); - regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); - -+ isc->config_dpc(isc); - isc->config_csc(isc); - isc->config_cbc(isc); - isc->config_cc(isc); ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -220,6 +220,8 @@ struct isc_reg_offsets { - * @max_width: maximum frame width, dependent on the internal RAM - * @max_height: maximum frame height, dependent on the internal RAM - * -+ * @config_dpc: pointer to a function that initializes product -+ * specific DPC module - * @config_csc: pointer to a function that initializes product - * specific CSC module - * @config_cbc: pointer to a function that initializes product -@@ -299,6 +301,7 @@ struct isc_device { - u32 max_height; - - struct { -+ void (*config_dpc)(struct isc_device *isc); - void (*config_csc)(struct isc_device *isc); - void (*config_cbc)(struct isc_device *isc); - void (*config_cc)(struct isc_device *isc); ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -107,6 +107,11 @@ static void isc_sama5d2_config_ctrls(str - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); - } - -+static void isc_sama5d2_config_dpc(struct isc_device *isc) -+{ -+ /* This module is not present on sama5d2 pipeline */ -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -273,6 +278,7 @@ static int atmel_isc_probe(struct platfo - isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; - isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; - -+ isc->config_dpc = isc_sama5d2_config_dpc; - isc->config_csc = isc_sama5d2_config_csc; - isc->config_cbc = isc_sama5d2_config_cbc; - isc->config_cc = isc_sama5d2_config_cc; diff --git a/target/linux/at91/patches-5.15/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch b/target/linux/at91/patches-5.15/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch deleted file mode 100644 index a219704b31..0000000000 --- a/target/linux/at91/patches-5.15/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 96936a6753a13dea5a8f66de949e6594dd82ce22 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:20 +0200 -Subject: [PATCH 178/247] media: atmel: atmel-isc: create callback for GAM - submodule product specific - -The GAM submodule is a part of the atmel-isc pipeline, and stands for -Gamma Correction. It is used to apply the gamma curve to the incoming pixels. -Create a product specific callback for initializing the GAM submodule -of the pipeline. -For sama5d2 product, there is no special configuration at this moment, -thus this function is a noop. - -[hverkuil: made isc_sama5d2_config_gam static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 1 + - drivers/media/platform/atmel/atmel-isc.h | 3 +++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++ - 3 files changed, 10 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -663,6 +663,7 @@ static void isc_set_pipeline(struct isc_ - isc->config_csc(isc); - isc->config_cbc(isc); - isc->config_cc(isc); -+ isc->config_gam(isc); - } - - static int isc_update_profile(struct isc_device *isc) ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -228,6 +228,8 @@ struct isc_reg_offsets { - * specific CBC module - * @config_cc: pointer to a function that initializes product - * specific CC module -+ * @config_gam: pointer to a function that initializes product -+ * specific GAMMA module - * @config_ctrls: pointer to a functoin that initializes product - * specific v4l2 controls. - * -@@ -305,6 +307,7 @@ struct isc_device { - void (*config_csc)(struct isc_device *isc); - void (*config_cbc)(struct isc_device *isc); - void (*config_cc)(struct isc_device *isc); -+ void (*config_gam)(struct isc_device *isc); - - void (*config_ctrls)(struct isc_device *isc, - const struct v4l2_ctrl_ops *ops); ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -112,6 +112,11 @@ static void isc_sama5d2_config_dpc(struc - /* This module is not present on sama5d2 pipeline */ - } - -+static void isc_sama5d2_config_gam(struct isc_device *isc) -+{ -+ /* No specific gamma configuration */ -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -282,6 +287,7 @@ static int atmel_isc_probe(struct platfo - isc->config_csc = isc_sama5d2_config_csc; - isc->config_cbc = isc_sama5d2_config_cbc; - isc->config_cc = isc_sama5d2_config_cc; -+ isc->config_gam = isc_sama5d2_config_gam; - isc->config_ctrls = isc_sama5d2_config_ctrls; - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; diff --git a/target/linux/at91/patches-5.15/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch b/target/linux/at91/patches-5.15/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch deleted file mode 100644 index 8442925a7e..0000000000 --- a/target/linux/at91/patches-5.15/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch +++ /dev/null @@ -1,95 +0,0 @@ -From ece1d7059731e31875e6eb464da4fb4a16465305 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:21 +0200 -Subject: [PATCH 179/247] media: atmel: atmel-isc: create callback for RLP - submodule product specific - -The RLP submodule is a part of the atmel-isc pipeline, and stands for -Rounding,Limiting and Packaging. It used to extract specific data from the -ISC pipeline. For example if we want to output greyscale 8 bit, we would -use limiting to 8 bits, and packaging to Luma component only. - -Create a product specific callback for initializing the RLP submodule -of the pipeline - -[hverkuil: made isc_sama5d2_config_rlp static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 6 ++---- - drivers/media/platform/atmel/atmel-isc.h | 3 +++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 10 ++++++++++ - 3 files changed, 15 insertions(+), 4 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -719,11 +719,10 @@ static void isc_set_histogram(struct isc - static int isc_configure(struct isc_device *isc) - { - struct regmap *regmap = isc->regmap; -- u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline; -+ u32 pfe_cfg0, dcfg, mask, pipeline; - struct isc_subdev_entity *subdev = isc->current_subdev; - - pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps; -- rlp_mode = isc->config.rlp_cfg_mode; - pipeline = isc->config.bits_pipeline; - - dcfg = isc->config.dcfg_imode | isc->dcfg; -@@ -736,8 +735,7 @@ static int isc_configure(struct isc_devi - - regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); - -- regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, -- ISC_RLP_CFG_MODE_MASK, rlp_mode); -+ isc->config_rlp(isc); - - regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -230,6 +230,8 @@ struct isc_reg_offsets { - * specific CC module - * @config_gam: pointer to a function that initializes product - * specific GAMMA module -+ * @config_rlp: pointer to a function that initializes product -+ * specific RLP module - * @config_ctrls: pointer to a functoin that initializes product - * specific v4l2 controls. - * -@@ -308,6 +310,7 @@ struct isc_device { - void (*config_cbc)(struct isc_device *isc); - void (*config_cc)(struct isc_device *isc); - void (*config_gam)(struct isc_device *isc); -+ void (*config_rlp)(struct isc_device *isc); - - void (*config_ctrls)(struct isc_device *isc, - const struct v4l2_ctrl_ops *ops); ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -117,6 +117,15 @@ static void isc_sama5d2_config_gam(struc - /* No specific gamma configuration */ - } - -+static void isc_sama5d2_config_rlp(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ u32 rlp_mode = isc->config.rlp_cfg_mode; -+ -+ regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, -+ ISC_RLP_CFG_MODE_MASK, rlp_mode); -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -288,6 +297,7 @@ static int atmel_isc_probe(struct platfo - isc->config_cbc = isc_sama5d2_config_cbc; - isc->config_cc = isc_sama5d2_config_cc; - isc->config_gam = isc_sama5d2_config_gam; -+ isc->config_rlp = isc_sama5d2_config_rlp; - isc->config_ctrls = isc_sama5d2_config_ctrls; - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; diff --git a/target/linux/at91/patches-5.15/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch b/target/linux/at91/patches-5.15/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch deleted file mode 100644 index 1c64cfca2e..0000000000 --- a/target/linux/at91/patches-5.15/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch +++ /dev/null @@ -1,440 +0,0 @@ -From dda51aa2e4524914d25022864466fa9d8713a5e9 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:22 +0200 -Subject: [PATCH 180/247] media: atmel: atmel-isc: move the formats list into - product specific code - -The list of input and output formats has to be product specific. -Move this list into the product specific code. -Have pointers to these arrays inside the device struct. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 167 ++---------------- - drivers/media/platform/atmel/atmel-isc.h | 12 +- - .../media/platform/atmel/atmel-sama5d2-isc.c | 136 ++++++++++++++ - 3 files changed, 165 insertions(+), 150 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -45,137 +45,6 @@ module_param(sensor_preferred, uint, 064 - MODULE_PARM_DESC(sensor_preferred, - "Sensor is preferred to output the specified format (1-on 0-off), default 1"); - --/* This is a list of the formats that the ISC can *output* */ --const struct isc_format controller_formats[] = { -- { -- .fourcc = V4L2_PIX_FMT_ARGB444, -- }, -- { -- .fourcc = V4L2_PIX_FMT_ARGB555, -- }, -- { -- .fourcc = V4L2_PIX_FMT_RGB565, -- }, -- { -- .fourcc = V4L2_PIX_FMT_ABGR32, -- }, -- { -- .fourcc = V4L2_PIX_FMT_XBGR32, -- }, -- { -- .fourcc = V4L2_PIX_FMT_YUV420, -- }, -- { -- .fourcc = V4L2_PIX_FMT_YUYV, -- }, -- { -- .fourcc = V4L2_PIX_FMT_YUV422P, -- }, -- { -- .fourcc = V4L2_PIX_FMT_GREY, -- }, -- { -- .fourcc = V4L2_PIX_FMT_Y10, -- }, --}; -- --/* This is a list of formats that the ISC can receive as *input* */ --struct isc_format formats_list[] = { -- { -- .fourcc = V4L2_PIX_FMT_SBGGR8, -- .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- .cfa_baycfg = ISC_BAY_CFG_BGBG, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SGBRG8, -- .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- .cfa_baycfg = ISC_BAY_CFG_GBGB, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SGRBG8, -- .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- .cfa_baycfg = ISC_BAY_CFG_GRGR, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SRGGB8, -- .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- .cfa_baycfg = ISC_BAY_CFG_RGRG, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SBGGR10, -- .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -- .cfa_baycfg = ISC_BAY_CFG_RGRG, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SGBRG10, -- .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -- .cfa_baycfg = ISC_BAY_CFG_GBGB, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SGRBG10, -- .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -- .cfa_baycfg = ISC_BAY_CFG_GRGR, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SRGGB10, -- .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -- .cfa_baycfg = ISC_BAY_CFG_RGRG, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SBGGR12, -- .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -- .cfa_baycfg = ISC_BAY_CFG_BGBG, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SGBRG12, -- .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -- .cfa_baycfg = ISC_BAY_CFG_GBGB, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SGRBG12, -- .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -- .cfa_baycfg = ISC_BAY_CFG_GRGR, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SRGGB12, -- .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -- .cfa_baycfg = ISC_BAY_CFG_RGRG, -- }, -- { -- .fourcc = V4L2_PIX_FMT_GREY, -- .mbus_code = MEDIA_BUS_FMT_Y8_1X8, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- }, -- { -- .fourcc = V4L2_PIX_FMT_YUYV, -- .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- }, -- { -- .fourcc = V4L2_PIX_FMT_RGB565, -- .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- }, -- { -- .fourcc = V4L2_PIX_FMT_Y10, -- .mbus_code = MEDIA_BUS_FMT_Y10_1X10, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -- }, -- --}; -- - #define ISC_IS_FORMAT_RAW(mbus_code) \ - (((mbus_code) & 0xf000) == 0x3000) - -@@ -919,24 +788,25 @@ static int isc_querycap(struct file *fil - static int isc_enum_fmt_vid_cap(struct file *file, void *priv, - struct v4l2_fmtdesc *f) - { -+ struct isc_device *isc = video_drvdata(file); - u32 index = f->index; - u32 i, supported_index; - -- if (index < ARRAY_SIZE(controller_formats)) { -- f->pixelformat = controller_formats[index].fourcc; -+ if (index < isc->controller_formats_size) { -+ f->pixelformat = isc->controller_formats[index].fourcc; - return 0; - } - -- index -= ARRAY_SIZE(controller_formats); -+ index -= isc->controller_formats_size; - - supported_index = 0; - -- for (i = 0; i < ARRAY_SIZE(formats_list); i++) { -- if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) || -- !formats_list[i].sd_support) -+ for (i = 0; i < isc->formats_list_size; i++) { -+ if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) || -+ !isc->formats_list[i].sd_support) - continue; - if (supported_index == index) { -- f->pixelformat = formats_list[i].fourcc; -+ f->pixelformat = isc->formats_list[i].fourcc; - return 0; - } - supported_index++; -@@ -1477,8 +1347,8 @@ static int isc_enum_framesizes(struct fi - if (isc->user_formats[i]->fourcc == fsize->pixel_format) - ret = 0; - -- for (i = 0; i < ARRAY_SIZE(controller_formats); i++) -- if (controller_formats[i].fourcc == fsize->pixel_format) -+ for (i = 0; i < isc->controller_formats_size; i++) -+ if (isc->controller_formats[i].fourcc == fsize->pixel_format) - ret = 0; - - if (ret) -@@ -1514,8 +1384,8 @@ static int isc_enum_frameintervals(struc - if (isc->user_formats[i]->fourcc == fival->pixel_format) - ret = 0; - -- for (i = 0; i < ARRAY_SIZE(controller_formats); i++) -- if (controller_formats[i].fourcc == fival->pixel_format) -+ for (i = 0; i < isc->controller_formats_size; i++) -+ if (isc->controller_formats[i].fourcc == fival->pixel_format) - ret = 0; - - if (ret) -@@ -2126,12 +1996,13 @@ static void isc_async_unbind(struct v4l2 - v4l2_ctrl_handler_free(&isc->ctrls.handler); - } - --static struct isc_format *find_format_by_code(unsigned int code, int *index) -+static struct isc_format *find_format_by_code(struct isc_device *isc, -+ unsigned int code, int *index) - { -- struct isc_format *fmt = &formats_list[0]; -+ struct isc_format *fmt = &isc->formats_list[0]; - unsigned int i; - -- for (i = 0; i < ARRAY_SIZE(formats_list); i++) { -+ for (i = 0; i < isc->formats_list_size; i++) { - if (fmt->mbus_code == code) { - *index = i; - return fmt; -@@ -2148,7 +2019,7 @@ static int isc_formats_init(struct isc_d - struct isc_format *fmt; - struct v4l2_subdev *subdev = isc->current_subdev->sd; - unsigned int num_fmts, i, j; -- u32 list_size = ARRAY_SIZE(formats_list); -+ u32 list_size = isc->formats_list_size; - struct v4l2_subdev_mbus_code_enum mbus_code = { - .which = V4L2_SUBDEV_FORMAT_ACTIVE, - }; -@@ -2158,7 +2029,7 @@ static int isc_formats_init(struct isc_d - NULL, &mbus_code)) { - mbus_code.index++; - -- fmt = find_format_by_code(mbus_code.code, &i); -+ fmt = find_format_by_code(isc, mbus_code.code, &i); - if (!fmt) { - v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n", - mbus_code.code); -@@ -2179,7 +2050,7 @@ static int isc_formats_init(struct isc_d - if (!isc->user_formats) - return -ENOMEM; - -- fmt = &formats_list[0]; -+ fmt = &isc->formats_list[0]; - for (i = 0, j = 0; i < list_size; i++) { - if (fmt->sd_support) - isc->user_formats[j++] = fmt; ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -236,6 +236,12 @@ struct isc_reg_offsets { - * specific v4l2 controls. - * - * @offsets: struct holding the product specific register offsets -+ * @controller_formats: pointer to the array of possible formats that the -+ * controller can output -+ * @formats_list: pointer to the array of possible formats that can -+ * be used as an input to the controller -+ * @controller_formats_size: size of controller_formats array -+ * @formats_list_size: size of formats_list array - */ - struct isc_device { - struct regmap *regmap; -@@ -317,10 +323,12 @@ struct isc_device { - }; - - struct isc_reg_offsets offsets; -+ const struct isc_format *controller_formats; -+ struct isc_format *formats_list; -+ u32 controller_formats_size; -+ u32 formats_list_size; - }; - --extern struct isc_format formats_list[]; --extern const struct isc_format controller_formats[]; - extern const struct regmap_config isc_regmap_config; - extern const struct v4l2_async_notifier_operations isc_async_ops; - ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -54,6 +54,137 @@ - - #define ISC_CLK_MAX_DIV 255 - -+/* This is a list of the formats that the ISC can *output* */ -+static const struct isc_format sama5d2_controller_formats[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_ARGB444, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_ARGB555, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_RGB565, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_ABGR32, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_XBGR32, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUV420, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUYV, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUV422P, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_GREY, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_Y10, -+ }, -+}; -+ -+/* This is a list of formats that the ISC can receive as *input* */ -+static struct isc_format sama5d2_formats_list[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_SBGGR8, -+ .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_BGBG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGBRG8, -+ .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_GBGB, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGRBG8, -+ .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_GRGR, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SRGGB8, -+ .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SBGGR10, -+ .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGBRG10, -+ .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_GBGB, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGRBG10, -+ .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_GRGR, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SRGGB10, -+ .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SBGGR12, -+ .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_BGBG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGBRG12, -+ .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_GBGB, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGRBG12, -+ .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_GRGR, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SRGGB12, -+ .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_GREY, -+ .mbus_code = MEDIA_BUS_FMT_Y8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUYV, -+ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_RGB565, -+ .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_Y10, -+ .mbus_code = MEDIA_BUS_FMT_Y10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ }, -+ -+}; -+ - static void isc_sama5d2_config_csc(struct isc_device *isc) - { - struct regmap *regmap = isc->regmap; -@@ -310,6 +441,11 @@ static int atmel_isc_probe(struct platfo - isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; - isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET; - -+ isc->controller_formats = sama5d2_controller_formats; -+ isc->controller_formats_size = ARRAY_SIZE(sama5d2_controller_formats); -+ isc->formats_list = sama5d2_formats_list; -+ isc->formats_list_size = ARRAY_SIZE(sama5d2_formats_list); -+ - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; - diff --git a/target/linux/at91/patches-5.15/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch b/target/linux/at91/patches-5.15/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch deleted file mode 100644 index 042fc609fe..0000000000 --- a/target/linux/at91/patches-5.15/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 8601f1fc0a9a22788bfa6369fbbf83b3828a5b42 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:23 +0200 -Subject: [PATCH 181/247] media: atmel: atmel-isc: create an adapt pipeline - callback for product specific - -Once the pipeline is set in the base code, create a callback that will adapt -the ISC pipeline to each product. -Create the adapt_pipeline callback that will be used in this fashion. - -[hverkuil: made isc_sama5d2_adapt_pipeline static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 4 ++++ - drivers/media/platform/atmel/atmel-isc.h | 5 +++++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 11 +++++++++++ - 3 files changed, 20 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -1059,6 +1059,10 @@ static int isc_try_configure_pipeline(st - default: - isc->try_config.bits_pipeline = 0x0; - } -+ -+ /* Tune the pipeline to product specific */ -+ isc->adapt_pipeline(isc); -+ - return 0; - } - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -235,6 +235,9 @@ struct isc_reg_offsets { - * @config_ctrls: pointer to a functoin that initializes product - * specific v4l2 controls. - * -+ * @adapt_pipeline: pointer to a function that adapts the pipeline bits -+ * to the product specific pipeline -+ * - * @offsets: struct holding the product specific register offsets - * @controller_formats: pointer to the array of possible formats that the - * controller can output -@@ -320,6 +323,8 @@ struct isc_device { - - void (*config_ctrls)(struct isc_device *isc, - const struct v4l2_ctrl_ops *ops); -+ -+ void (*adapt_pipeline)(struct isc_device *isc); - }; - - struct isc_reg_offsets offsets; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -54,6 +54,10 @@ - - #define ISC_CLK_MAX_DIV 255 - -+#define ISC_SAMA5D2_PIPELINE \ -+ (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ -+ CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) -+ - /* This is a list of the formats that the ISC can *output* */ - static const struct isc_format sama5d2_controller_formats[] = { - { -@@ -257,6 +261,11 @@ static void isc_sama5d2_config_rlp(struc - ISC_RLP_CFG_MODE_MASK, rlp_mode); - } - -+static void isc_sama5d2_adapt_pipeline(struct isc_device *isc) -+{ -+ isc->try_config.bits_pipeline &= ISC_SAMA5D2_PIPELINE; -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -431,6 +440,8 @@ static int atmel_isc_probe(struct platfo - isc->config_rlp = isc_sama5d2_config_rlp; - isc->config_ctrls = isc_sama5d2_config_ctrls; - -+ isc->adapt_pipeline = isc_sama5d2_adapt_pipeline; -+ - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; - isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; - isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; diff --git a/target/linux/at91/patches-5.15/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch b/target/linux/at91/patches-5.15/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch deleted file mode 100644 index 00849c7d12..0000000000 --- a/target/linux/at91/patches-5.15/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch +++ /dev/null @@ -1,55 +0,0 @@ -From bf032d1a0105939b90072914d88181fbe6187f43 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:24 +0200 -Subject: [PATCH 182/247] media: atmel: atmel-isc-regs: add additional fields - for sama7g5 type pipeline - -Add additional fields for registers present in sama7g5 type pipeline. -Extend register masks for additional bits in sama7g5 type pipeline registers. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-regs.h | 16 ++++++++++++++-- - 1 file changed, 14 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -289,8 +289,18 @@ - #define ISC_RLP_CFG_MODE_ARGB32 0xa - #define ISC_RLP_CFG_MODE_YYCC 0xb - #define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc -+#define ISC_RLP_CFG_MODE_YCYC 0xd - #define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) - -+#define ISC_RLP_CFG_LSH BIT(5) -+ -+#define ISC_RLP_CFG_YMODE_YUYV (3 << 6) -+#define ISC_RLP_CFG_YMODE_YVYU (2 << 6) -+#define ISC_RLP_CFG_YMODE_VYUY (0 << 6) -+#define ISC_RLP_CFG_YMODE_UYVY (1 << 6) -+ -+#define ISC_RLP_CFG_YMODE_MASK GENMASK(7, 6) -+ - /* Offset for HIS register specific to sama5d2 product */ - #define ISC_SAMA5D2_HIS_OFFSET 0 - /* Histogram Control Register */ -@@ -332,13 +342,15 @@ - #define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4) - #define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4) - #define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4) --#define ISC_DCFG_YMBSIZE_MASK GENMASK(5, 4) -+#define ISC_DCFG_YMBSIZE_BEATS32 (0x4 << 4) -+#define ISC_DCFG_YMBSIZE_MASK GENMASK(6, 4) - - #define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8) - #define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8) - #define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8) - #define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8) --#define ISC_DCFG_CMBSIZE_MASK GENMASK(9, 8) -+#define ISC_DCFG_CMBSIZE_BEATS32 (0x4 << 8) -+#define ISC_DCFG_CMBSIZE_MASK GENMASK(10, 8) - - /* DMA Control Register */ - #define ISC_DCTRL 0x000003e4 diff --git a/target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch b/target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch deleted file mode 100644 index 247c901558..0000000000 --- a/target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch +++ /dev/null @@ -1,145 +0,0 @@ -From fa9e6cd8f3ba4a277c06e4c1fb01cd69b3a57234 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:25 +0200 -Subject: [PATCH 183/247] media: atmel: atmel-isc-base: add support for more - formats and additional pipeline modules - -Add support for additional formats supported by newer pipelines, and for -additional pipeline modules. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 48 +++++++++++++++---- - 1 file changed, 38 insertions(+), 10 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -855,6 +855,8 @@ static int isc_try_validate_formats(stru - case V4L2_PIX_FMT_YUV420: - case V4L2_PIX_FMT_YUV422P: - case V4L2_PIX_FMT_YUYV: -+ case V4L2_PIX_FMT_UYVY: -+ case V4L2_PIX_FMT_VYUY: - ret = 0; - yuv = true; - break; -@@ -869,6 +871,7 @@ static int isc_try_validate_formats(stru - break; - case V4L2_PIX_FMT_GREY: - case V4L2_PIX_FMT_Y10: -+ case V4L2_PIX_FMT_Y16: - ret = 0; - grey = true; - break; -@@ -899,6 +902,8 @@ static int isc_try_validate_formats(stru - */ - static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) - { -+ isc->try_config.rlp_cfg_mode = 0; -+ - switch (isc->try_config.fourcc) { - case V4L2_PIX_FMT_SBGGR8: - case V4L2_PIX_FMT_SGBRG8: -@@ -965,7 +970,19 @@ static int isc_try_configure_rlp_dma(str - isc->try_config.bpp = 16; - break; - case V4L2_PIX_FMT_YUYV: -- isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; -+ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV; -+ isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; -+ isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; -+ isc->try_config.bpp = 16; -+ break; -+ case V4L2_PIX_FMT_UYVY: -+ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY; -+ isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; -+ isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; -+ isc->try_config.bpp = 16; -+ break; -+ case V4L2_PIX_FMT_VYUY: -+ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY; - isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; - isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; - isc->try_config.bpp = 16; -@@ -976,8 +993,11 @@ static int isc_try_configure_rlp_dma(str - isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; - isc->try_config.bpp = 8; - break; -+ case V4L2_PIX_FMT_Y16: -+ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH; -+ fallthrough; - case V4L2_PIX_FMT_Y10: -- isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10; -+ isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10; - isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; - isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; - isc->try_config.bpp = 16; -@@ -1011,7 +1031,8 @@ static int isc_try_configure_pipeline(st - /* if sensor format is RAW, we convert inside ISC */ - if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { - isc->try_config.bits_pipeline = CFA_ENABLE | -- WB_ENABLE | GAM_ENABLES; -+ WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE | -+ CC_ENABLE; - } else { - isc->try_config.bits_pipeline = 0x0; - } -@@ -1020,8 +1041,9 @@ static int isc_try_configure_pipeline(st - /* if sensor format is RAW, we convert inside ISC */ - if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { - isc->try_config.bits_pipeline = CFA_ENABLE | -- CSC_ENABLE | WB_ENABLE | GAM_ENABLES | -- SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE; -+ CSC_ENABLE | GAM_ENABLES | WB_ENABLE | -+ SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE | -+ DPC_BLCENABLE; - } else { - isc->try_config.bits_pipeline = 0x0; - } -@@ -1031,33 +1053,39 @@ static int isc_try_configure_pipeline(st - if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { - isc->try_config.bits_pipeline = CFA_ENABLE | - CSC_ENABLE | WB_ENABLE | GAM_ENABLES | -- SUB422_ENABLE | CBC_ENABLE; -+ SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; - } else { - isc->try_config.bits_pipeline = 0x0; - } - break; - case V4L2_PIX_FMT_YUYV: -+ case V4L2_PIX_FMT_UYVY: -+ case V4L2_PIX_FMT_VYUY: - /* if sensor format is RAW, we convert inside ISC */ - if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { - isc->try_config.bits_pipeline = CFA_ENABLE | - CSC_ENABLE | WB_ENABLE | GAM_ENABLES | -- SUB422_ENABLE | CBC_ENABLE; -+ SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; - } else { - isc->try_config.bits_pipeline = 0x0; - } - break; - case V4L2_PIX_FMT_GREY: -- if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { -+ case V4L2_PIX_FMT_Y16: - /* if sensor format is RAW, we convert inside ISC */ -+ if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { - isc->try_config.bits_pipeline = CFA_ENABLE | - CSC_ENABLE | WB_ENABLE | GAM_ENABLES | -- CBC_ENABLE; -+ CBC_ENABLE | DPC_BLCENABLE; - } else { - isc->try_config.bits_pipeline = 0x0; - } - break; - default: -- isc->try_config.bits_pipeline = 0x0; -+ if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) -+ isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE; -+ else -+ isc->try_config.bits_pipeline = 0x0; - } - - /* Tune the pipeline to product specific */ diff --git a/target/linux/at91/patches-5.15/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch b/target/linux/at91/patches-5.15/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch deleted file mode 100644 index 587f4862f2..0000000000 --- a/target/linux/at91/patches-5.15/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch +++ /dev/null @@ -1,26 +0,0 @@ -From b36d11efc134f9f1e2804270d08b9dbefdee4a0d Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:26 +0200 -Subject: [PATCH 184/247] media: atmel: atmel-isc-sama5d2: remove duplicate - define - -Remove a duplicate definition of clock max divider - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -52,8 +52,6 @@ - #define ISC_SAMA5D2_MAX_SUPPORT_WIDTH 2592 - #define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT 1944 - --#define ISC_CLK_MAX_DIV 255 -- - #define ISC_SAMA5D2_PIPELINE \ - (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ - CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) diff --git a/target/linux/at91/patches-5.15/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch b/target/linux/at91/patches-5.15/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch deleted file mode 100644 index a21ac2a7c0..0000000000 --- a/target/linux/at91/patches-5.15/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch +++ /dev/null @@ -1,810 +0,0 @@ -From 74fd7ea680cb1a3a43b51a7279aea45efdf9ec42 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:29 +0200 -Subject: [PATCH 185/247] media: atmel: atmel-isc: add microchip-xisc driver - -Add driver for the extended variant of the isc, the microchip XISC -present on sama7g5 product. - -[hverkuil: drop MODULE_SUPPORTED_DEVICE, no longer exists] -[hverkuil: made isc_sama7g5_config_csc et al static] -[hverkuil: made sama7g5_controller_formats et al static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/Makefile | 1 + - drivers/media/platform/atmel/Kconfig | 11 + - drivers/media/platform/atmel/Makefile | 2 + - drivers/media/platform/atmel/atmel-isc-base.c | 2 +- - drivers/media/platform/atmel/atmel-isc-regs.h | 26 + - .../media/platform/atmel/atmel-sama7g5-isc.c | 630 ++++++++++++++++++ - 6 files changed, 671 insertions(+), 1 deletion(-) - create mode 100644 drivers/media/platform/atmel/atmel-sama7g5-isc.c - ---- a/drivers/media/platform/Makefile -+++ b/drivers/media/platform/Makefile -@@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_RCAR_VIN) += rcar-vi - - obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel/ - obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel/ -+obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel/ - - obj-$(CONFIG_VIDEO_STM32_DCMI) += stm32/ - ---- a/drivers/media/platform/atmel/Kconfig -+++ b/drivers/media/platform/atmel/Kconfig -@@ -12,6 +12,17 @@ config VIDEO_ATMEL_ISC - This module makes the ATMEL Image Sensor Controller available - as a v4l2 device. - -+config VIDEO_ATMEL_XISC -+ tristate "ATMEL eXtended Image Sensor Controller (XISC) support" -+ depends on VIDEO_V4L2 && COMMON_CLK && VIDEO_V4L2_SUBDEV_API -+ depends on ARCH_AT91 || COMPILE_TEST -+ select VIDEOBUF2_DMA_CONTIG -+ select REGMAP_MMIO -+ select V4L2_FWNODE -+ help -+ This module makes the ATMEL eXtended Image Sensor Controller -+ available as a v4l2 device. -+ - config VIDEO_ATMEL_ISI - tristate "ATMEL Image Sensor Interface (ISI) support" - depends on VIDEO_V4L2 && OF ---- a/drivers/media/platform/atmel/Makefile -+++ b/drivers/media/platform/atmel/Makefile -@@ -1,5 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0-only - atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o -+atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o - - obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o - obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o -+obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -600,7 +600,7 @@ static int isc_configure(struct isc_devi - mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW | - ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW | - ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC | -- ISC_PFE_CFG0_CCIR656; -+ ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI; - - regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); - ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -26,6 +26,7 @@ - #define ISC_PFE_CFG0_PPOL_LOW BIT(2) - #define ISC_PFE_CFG0_CCIR656 BIT(9) - #define ISC_PFE_CFG0_CCIR_CRC BIT(10) -+#define ISC_PFE_CFG0_MIPI BIT(14) - - #define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4) - #define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4) -@@ -184,6 +185,8 @@ - /* ISC Gamma Correction Control Register */ - #define ISC_GAM_CTRL 0x00000094 - -+#define ISC_GAM_CTRL_BIPART BIT(4) -+ - /* ISC_Gamma Correction Blue Entry Register */ - #define ISC_GAM_BENTRY 0x00000098 - -@@ -222,6 +225,8 @@ - - /* Offset for CSC register specific to sama5d2 product */ - #define ISC_SAMA5D2_CSC_OFFSET 0 -+/* Offset for CSC register specific to sama7g5 product */ -+#define ISC_SAMA7G5_CSC_OFFSET 0x11c - - /* Color Space Conversion Control Register */ - #define ISC_CSC_CTRL 0x00000398 -@@ -246,6 +251,8 @@ - - /* Offset for CBC register specific to sama5d2 product */ - #define ISC_SAMA5D2_CBC_OFFSET 0 -+/* Offset for CBC register specific to sama7g5 product */ -+#define ISC_SAMA7G5_CBC_OFFSET 0x11c - - /* Contrast And Brightness Control Register */ - #define ISC_CBC_CTRL 0x000003b4 -@@ -261,18 +268,30 @@ - #define ISC_CBC_CONTRAST 0x000003c0 - #define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) - -+/* Hue Register */ -+#define ISC_CBCHS_HUE 0x4e0 -+/* Saturation Register */ -+#define ISC_CBCHS_SAT 0x4e4 -+ - /* Offset for SUB422 register specific to sama5d2 product */ - #define ISC_SAMA5D2_SUB422_OFFSET 0 -+/* Offset for SUB422 register specific to sama7g5 product */ -+#define ISC_SAMA7G5_SUB422_OFFSET 0x124 -+ - /* Subsampling 4:4:4 to 4:2:2 Control Register */ - #define ISC_SUB422_CTRL 0x000003c4 - - /* Offset for SUB420 register specific to sama5d2 product */ - #define ISC_SAMA5D2_SUB420_OFFSET 0 -+/* Offset for SUB420 register specific to sama7g5 product */ -+#define ISC_SAMA7G5_SUB420_OFFSET 0x124 - /* Subsampling 4:2:2 to 4:2:0 Control Register */ - #define ISC_SUB420_CTRL 0x000003cc - - /* Offset for RLP register specific to sama5d2 product */ - #define ISC_SAMA5D2_RLP_OFFSET 0 -+/* Offset for RLP register specific to sama7g5 product */ -+#define ISC_SAMA7G5_RLP_OFFSET 0x124 - /* Rounding, Limiting and Packing Configuration Register */ - #define ISC_RLP_CFG 0x000003d0 - -@@ -303,6 +322,8 @@ - - /* Offset for HIS register specific to sama5d2 product */ - #define ISC_SAMA5D2_HIS_OFFSET 0 -+/* Offset for HIS register specific to sama7g5 product */ -+#define ISC_SAMA7G5_HIS_OFFSET 0x124 - /* Histogram Control Register */ - #define ISC_HIS_CTRL 0x000003d4 - -@@ -326,6 +347,8 @@ - - /* Offset for DMA register specific to sama5d2 product */ - #define ISC_SAMA5D2_DMA_OFFSET 0 -+/* Offset for DMA register specific to sama7g5 product */ -+#define ISC_SAMA7G5_DMA_OFFSET 0x13c - - /* DMA Configuration Register */ - #define ISC_DCFG 0x000003e0 -@@ -376,11 +399,14 @@ - - /* Offset for version register specific to sama5d2 product */ - #define ISC_SAMA5D2_VERSION_OFFSET 0 -+#define ISC_SAMA7G5_VERSION_OFFSET 0x13c - /* Version Register */ - #define ISC_VERSION 0x0000040c - - /* Offset for version register specific to sama5d2 product */ - #define ISC_SAMA5D2_HIS_ENTRY_OFFSET 0 -+/* Offset for version register specific to sama7g5 product */ -+#define ISC_SAMA7G5_HIS_ENTRY_OFFSET 0x14c - /* Histogram Entry */ - #define ISC_HIS_ENTRY 0x00000410 - ---- /dev/null -+++ b/drivers/media/platform/atmel/atmel-sama7g5-isc.c -@@ -0,0 +1,630 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Microchip eXtended Image Sensor Controller (XISC) driver -+ * -+ * Copyright (C) 2019-2021 Microchip Technology, Inc. and its subsidiaries -+ * -+ * Author: Eugen Hristev -+ * -+ * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS -+ * -+ * ISC video pipeline integrates the following submodules: -+ * PFE: Parallel Front End to sample the camera sensor input stream -+ * DPC: Defective Pixel Correction with black offset correction, green disparity -+ * correction and defective pixel correction (3 modules total) -+ * WB: Programmable white balance in the Bayer domain -+ * CFA: Color filter array interpolation module -+ * CC: Programmable color correction -+ * GAM: Gamma correction -+ *VHXS: Vertical and Horizontal Scaler -+ * CSC: Programmable color space conversion -+ *CBHS: Contrast Brightness Hue and Saturation control -+ * SUB: This module performs YCbCr444 to YCbCr420 chrominance subsampling -+ * RLP: This module performs rounding, range limiting -+ * and packing of the incoming data -+ * DMA: This module performs DMA master accesses to write frames to external RAM -+ * HIS: Histogram module performs statistic counters on the frames -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "atmel-isc-regs.h" -+#include "atmel-isc.h" -+ -+#define ISC_SAMA7G5_MAX_SUPPORT_WIDTH 3264 -+#define ISC_SAMA7G5_MAX_SUPPORT_HEIGHT 2464 -+ -+#define ISC_SAMA7G5_PIPELINE \ -+ (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ -+ CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) -+ -+/* This is a list of the formats that the ISC can *output* */ -+static const struct isc_format sama7g5_controller_formats[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_ARGB444, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_ARGB555, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_RGB565, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_ABGR32, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_XBGR32, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUV420, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_UYVY, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_VYUY, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUYV, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUV422P, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_GREY, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_Y10, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_Y16, -+ }, -+}; -+ -+/* This is a list of formats that the ISC can receive as *input* */ -+static struct isc_format sama7g5_formats_list[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_SBGGR8, -+ .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_BGBG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGBRG8, -+ .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_GBGB, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGRBG8, -+ .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_GRGR, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SRGGB8, -+ .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SBGGR10, -+ .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGBRG10, -+ .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_GBGB, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGRBG10, -+ .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_GRGR, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SRGGB10, -+ .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SBGGR12, -+ .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_BGBG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGBRG12, -+ .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_GBGB, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGRBG12, -+ .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_GRGR, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SRGGB12, -+ .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_GREY, -+ .mbus_code = MEDIA_BUS_FMT_Y8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUYV, -+ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_UYVY, -+ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_RGB565, -+ .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_Y10, -+ .mbus_code = MEDIA_BUS_FMT_Y10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ }, -+ -+}; -+ -+static void isc_sama7g5_config_csc(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ /* Convert RGB to YUV */ -+ regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, -+ 0x42 | (0x81 << 16)); -+ regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, -+ 0x19 | (0x10 << 16)); -+ regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, -+ 0xFDA | (0xFB6 << 16)); -+ regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, -+ 0x70 | (0x80 << 16)); -+ regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, -+ 0x70 | (0xFA2 << 16)); -+ regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, -+ 0xFEE | (0x80 << 16)); -+} -+ -+static void isc_sama7g5_config_cbc(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ /* Configure what is set via v4l2 ctrls */ -+ regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness); -+ regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast); -+ /* Configure Hue and Saturation as neutral midpoint */ -+ regmap_write(regmap, ISC_CBCHS_HUE, 0); -+ regmap_write(regmap, ISC_CBCHS_SAT, (1 << 4)); -+} -+ -+static void isc_sama7g5_config_cc(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ /* Configure each register at the neutral fixed point 1.0 or 0.0 */ -+ regmap_write(regmap, ISC_CC_RR_RG, (1 << 8)); -+ regmap_write(regmap, ISC_CC_RB_OR, 0); -+ regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16); -+ regmap_write(regmap, ISC_CC_GB_OG, 0); -+ regmap_write(regmap, ISC_CC_BR_BG, 0); -+ regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); -+} -+ -+static void isc_sama7g5_config_ctrls(struct isc_device *isc, -+ const struct v4l2_ctrl_ops *ops) -+{ -+ struct isc_ctrls *ctrls = &isc->ctrls; -+ struct v4l2_ctrl_handler *hdl = &ctrls->handler; -+ -+ ctrls->contrast = 16; -+ -+ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 16); -+} -+ -+static void isc_sama7g5_config_dpc(struct isc_device *isc) -+{ -+ u32 bay_cfg = isc->config.sd_format->cfa_baycfg; -+ struct regmap *regmap = isc->regmap; -+ -+ regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK, -+ (64 << ISC_DPC_CFG_BLOFF_SHIFT)); -+ regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK, -+ (bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT)); -+} -+ -+static void isc_sama7g5_config_gam(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ regmap_update_bits(regmap, ISC_GAM_CTRL, ISC_GAM_CTRL_BIPART, -+ ISC_GAM_CTRL_BIPART); -+} -+ -+static void isc_sama7g5_config_rlp(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ u32 rlp_mode = isc->config.rlp_cfg_mode; -+ -+ regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, -+ ISC_RLP_CFG_MODE_MASK | ISC_RLP_CFG_LSH | -+ ISC_RLP_CFG_YMODE_MASK, rlp_mode); -+} -+ -+static void isc_sama7g5_adapt_pipeline(struct isc_device *isc) -+{ -+ isc->try_config.bits_pipeline &= ISC_SAMA7G5_PIPELINE; -+} -+ -+/* Gamma table with gamma 1/2.2 */ -+static const u32 isc_sama7g5_gamma_table[][GAMMA_ENTRIES] = { -+ /* index 0 --> gamma bipartite */ -+ { -+ 0x980, 0x4c0320, 0x650260, 0x7801e0, 0x8701a0, 0x940180, -+ 0xa00160, 0xab0120, 0xb40120, 0xbd0120, 0xc60100, 0xce0100, -+ 0xd600e0, 0xdd00e0, 0xe400e0, 0xeb00c0, 0xf100c0, 0xf700c0, -+ 0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0, -+ 0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080, -+ 0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a, -+ 0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030, -+ 0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026, -+ 0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020, -+ 0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c, -+ 0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a }, -+}; -+ -+static int xisc_parse_dt(struct device *dev, struct isc_device *isc) -+{ -+ struct device_node *np = dev->of_node; -+ struct device_node *epn = NULL; -+ struct isc_subdev_entity *subdev_entity; -+ unsigned int flags; -+ int ret; -+ bool mipi_mode; -+ -+ INIT_LIST_HEAD(&isc->subdev_entities); -+ -+ mipi_mode = of_property_read_bool(np, "microchip,mipi-mode"); -+ -+ while (1) { -+ struct v4l2_fwnode_endpoint v4l2_epn = { .bus_type = 0 }; -+ -+ epn = of_graph_get_next_endpoint(np, epn); -+ if (!epn) -+ return 0; -+ -+ ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn), -+ &v4l2_epn); -+ if (ret) { -+ ret = -EINVAL; -+ dev_err(dev, "Could not parse the endpoint\n"); -+ break; -+ } -+ -+ subdev_entity = devm_kzalloc(dev, sizeof(*subdev_entity), -+ GFP_KERNEL); -+ if (!subdev_entity) { -+ ret = -ENOMEM; -+ break; -+ } -+ subdev_entity->epn = epn; -+ -+ flags = v4l2_epn.bus.parallel.flags; -+ -+ if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) -+ subdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW; -+ -+ if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) -+ subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW; -+ -+ if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) -+ subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW; -+ -+ if (v4l2_epn.bus_type == V4L2_MBUS_BT656) -+ subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC | -+ ISC_PFE_CFG0_CCIR656; -+ -+ if (mipi_mode) -+ subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_MIPI; -+ -+ list_add_tail(&subdev_entity->list, &isc->subdev_entities); -+ } -+ of_node_put(epn); -+ -+ return ret; -+} -+ -+static int microchip_xisc_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct isc_device *isc; -+ struct resource *res; -+ void __iomem *io_base; -+ struct isc_subdev_entity *subdev_entity; -+ int irq; -+ int ret; -+ u32 ver; -+ -+ isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL); -+ if (!isc) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, isc); -+ isc->dev = dev; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ io_base = devm_ioremap_resource(dev, res); -+ if (IS_ERR(io_base)) -+ return PTR_ERR(io_base); -+ -+ isc->regmap = devm_regmap_init_mmio(dev, io_base, &isc_regmap_config); -+ if (IS_ERR(isc->regmap)) { -+ ret = PTR_ERR(isc->regmap); -+ dev_err(dev, "failed to init register map: %d\n", ret); -+ return ret; -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) -+ return irq; -+ -+ ret = devm_request_irq(dev, irq, isc_interrupt, 0, -+ "microchip-sama7g5-xisc", isc); -+ if (ret < 0) { -+ dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", -+ irq, ret); -+ return ret; -+ } -+ -+ isc->gamma_table = isc_sama7g5_gamma_table; -+ isc->gamma_max = 0; -+ -+ isc->max_width = ISC_SAMA7G5_MAX_SUPPORT_WIDTH; -+ isc->max_height = ISC_SAMA7G5_MAX_SUPPORT_HEIGHT; -+ -+ isc->config_dpc = isc_sama7g5_config_dpc; -+ isc->config_csc = isc_sama7g5_config_csc; -+ isc->config_cbc = isc_sama7g5_config_cbc; -+ isc->config_cc = isc_sama7g5_config_cc; -+ isc->config_gam = isc_sama7g5_config_gam; -+ isc->config_rlp = isc_sama7g5_config_rlp; -+ isc->config_ctrls = isc_sama7g5_config_ctrls; -+ -+ isc->adapt_pipeline = isc_sama7g5_adapt_pipeline; -+ -+ isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; -+ isc->offsets.cbc = ISC_SAMA7G5_CBC_OFFSET; -+ isc->offsets.sub422 = ISC_SAMA7G5_SUB422_OFFSET; -+ isc->offsets.sub420 = ISC_SAMA7G5_SUB420_OFFSET; -+ isc->offsets.rlp = ISC_SAMA7G5_RLP_OFFSET; -+ isc->offsets.his = ISC_SAMA7G5_HIS_OFFSET; -+ isc->offsets.dma = ISC_SAMA7G5_DMA_OFFSET; -+ isc->offsets.version = ISC_SAMA7G5_VERSION_OFFSET; -+ isc->offsets.his_entry = ISC_SAMA7G5_HIS_ENTRY_OFFSET; -+ -+ isc->controller_formats = sama7g5_controller_formats; -+ isc->controller_formats_size = ARRAY_SIZE(sama7g5_controller_formats); -+ isc->formats_list = sama7g5_formats_list; -+ isc->formats_list_size = ARRAY_SIZE(sama7g5_formats_list); -+ -+ /* sama7g5-isc RAM access port is full AXI4 - 32 bits per beat */ -+ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32; -+ -+ ret = isc_pipeline_init(isc); -+ if (ret) -+ return ret; -+ -+ isc->hclock = devm_clk_get(dev, "hclock"); -+ if (IS_ERR(isc->hclock)) { -+ ret = PTR_ERR(isc->hclock); -+ dev_err(dev, "failed to get hclock: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(isc->hclock); -+ if (ret) { -+ dev_err(dev, "failed to enable hclock: %d\n", ret); -+ return ret; -+ } -+ -+ ret = isc_clk_init(isc); -+ if (ret) { -+ dev_err(dev, "failed to init isc clock: %d\n", ret); -+ goto unprepare_hclk; -+ } -+ -+ isc->ispck = isc->isc_clks[ISC_ISPCK].clk; -+ -+ ret = clk_prepare_enable(isc->ispck); -+ if (ret) { -+ dev_err(dev, "failed to enable ispck: %d\n", ret); -+ goto unprepare_hclk; -+ } -+ -+ /* ispck should be greater or equal to hclock */ -+ ret = clk_set_rate(isc->ispck, clk_get_rate(isc->hclock)); -+ if (ret) { -+ dev_err(dev, "failed to set ispck rate: %d\n", ret); -+ goto unprepare_clk; -+ } -+ -+ ret = v4l2_device_register(dev, &isc->v4l2_dev); -+ if (ret) { -+ dev_err(dev, "unable to register v4l2 device.\n"); -+ goto unprepare_clk; -+ } -+ -+ ret = xisc_parse_dt(dev, isc); -+ if (ret) { -+ dev_err(dev, "fail to parse device tree\n"); -+ goto unregister_v4l2_device; -+ } -+ -+ if (list_empty(&isc->subdev_entities)) { -+ dev_err(dev, "no subdev found\n"); -+ ret = -ENODEV; -+ goto unregister_v4l2_device; -+ } -+ -+ list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { -+ struct v4l2_async_subdev *asd; -+ -+ v4l2_async_notifier_init(&subdev_entity->notifier); -+ -+ asd = v4l2_async_notifier_add_fwnode_remote_subdev( -+ &subdev_entity->notifier, -+ of_fwnode_handle(subdev_entity->epn), -+ struct v4l2_async_subdev); -+ -+ of_node_put(subdev_entity->epn); -+ subdev_entity->epn = NULL; -+ -+ if (IS_ERR(asd)) { -+ ret = PTR_ERR(asd); -+ goto cleanup_subdev; -+ } -+ -+ subdev_entity->notifier.ops = &isc_async_ops; -+ -+ ret = v4l2_async_notifier_register(&isc->v4l2_dev, -+ &subdev_entity->notifier); -+ if (ret) { -+ dev_err(dev, "fail to register async notifier\n"); -+ goto cleanup_subdev; -+ } -+ -+ if (video_is_registered(&isc->video_dev)) -+ break; -+ } -+ -+ pm_runtime_set_active(dev); -+ pm_runtime_enable(dev); -+ pm_request_idle(dev); -+ -+ regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); -+ dev_info(dev, "Microchip XISC version %x\n", ver); -+ -+ return 0; -+ -+cleanup_subdev: -+ isc_subdev_cleanup(isc); -+ -+unregister_v4l2_device: -+ v4l2_device_unregister(&isc->v4l2_dev); -+ -+unprepare_clk: -+ clk_disable_unprepare(isc->ispck); -+unprepare_hclk: -+ clk_disable_unprepare(isc->hclock); -+ -+ isc_clk_cleanup(isc); -+ -+ return ret; -+} -+ -+static int microchip_xisc_remove(struct platform_device *pdev) -+{ -+ struct isc_device *isc = platform_get_drvdata(pdev); -+ -+ pm_runtime_disable(&pdev->dev); -+ -+ isc_subdev_cleanup(isc); -+ -+ v4l2_device_unregister(&isc->v4l2_dev); -+ -+ clk_disable_unprepare(isc->ispck); -+ clk_disable_unprepare(isc->hclock); -+ -+ isc_clk_cleanup(isc); -+ -+ return 0; -+} -+ -+static int __maybe_unused xisc_runtime_suspend(struct device *dev) -+{ -+ struct isc_device *isc = dev_get_drvdata(dev); -+ -+ clk_disable_unprepare(isc->ispck); -+ clk_disable_unprepare(isc->hclock); -+ -+ return 0; -+} -+ -+static int __maybe_unused xisc_runtime_resume(struct device *dev) -+{ -+ struct isc_device *isc = dev_get_drvdata(dev); -+ int ret; -+ -+ ret = clk_prepare_enable(isc->hclock); -+ if (ret) -+ return ret; -+ -+ ret = clk_prepare_enable(isc->ispck); -+ if (ret) -+ clk_disable_unprepare(isc->hclock); -+ -+ return ret; -+} -+ -+static const struct dev_pm_ops microchip_xisc_dev_pm_ops = { -+ SET_RUNTIME_PM_OPS(xisc_runtime_suspend, xisc_runtime_resume, NULL) -+}; -+ -+static const struct of_device_id microchip_xisc_of_match[] = { -+ { .compatible = "microchip,sama7g5-isc" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, microchip_xisc_of_match); -+ -+static struct platform_driver microchip_xisc_driver = { -+ .probe = microchip_xisc_probe, -+ .remove = microchip_xisc_remove, -+ .driver = { -+ .name = "microchip-sama7g5-xisc", -+ .pm = µchip_xisc_dev_pm_ops, -+ .of_match_table = of_match_ptr(microchip_xisc_of_match), -+ }, -+}; -+ -+module_platform_driver(microchip_xisc_driver); -+ -+MODULE_AUTHOR("Eugen Hristev "); -+MODULE_DESCRIPTION("The V4L2 driver for Microchip-XISC"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/at91/patches-5.15/186-ASoC-atmel-fix-shadowed-variable.patch b/target/linux/at91/patches-5.15/186-ASoC-atmel-fix-shadowed-variable.patch deleted file mode 100644 index 7e88bb39ce..0000000000 --- a/target/linux/at91/patches-5.15/186-ASoC-atmel-fix-shadowed-variable.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 1b41c69264d7233a3e9a0aa36333ee22a5a049e9 Mon Sep 17 00:00:00 2001 -From: Pierre-Louis Bossart -Date: Fri, 26 Mar 2021 16:59:12 -0500 -Subject: [PATCH 186/247] ASoC: atmel: fix shadowed variable - -Fix cppcheck warning: - -sound/soc/atmel/atmel-classd.c:51:14: style: Local variable 'pwm_type' -shadows outer variable [shadowVariable] - const char *pwm_type; - ^ -sound/soc/atmel/atmel-classd.c:226:27: note: Shadowed declaration -static const char * const pwm_type[] = { - ^ -sound/soc/atmel/atmel-classd.c:51:14: note: Shadow variable - const char *pwm_type; - ^ - -Signed-off-by: Pierre-Louis Bossart -Reviewed-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210326215927.936377-3-pierre-louis.bossart@linux.intel.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/atmel-classd.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/sound/soc/atmel/atmel-classd.c -+++ b/sound/soc/atmel/atmel-classd.c -@@ -48,7 +48,7 @@ static struct atmel_classd_pdata *atmel_ - { - struct device_node *np = dev->of_node; - struct atmel_classd_pdata *pdata; -- const char *pwm_type; -+ const char *pwm_type_s; - int ret; - - if (!np) { -@@ -60,8 +60,8 @@ static struct atmel_classd_pdata *atmel_ - if (!pdata) - return ERR_PTR(-ENOMEM); - -- ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type); -- if ((ret == 0) && (strcmp(pwm_type, "diff") == 0)) -+ ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type_s); -+ if ((ret == 0) && (strcmp(pwm_type_s, "diff") == 0)) - pdata->pwm_type = CLASSD_MR_PWMTYP_DIFF; - else - pdata->pwm_type = CLASSD_MR_PWMTYP_SINGLE; diff --git a/target/linux/at91/patches-5.15/187-ASoC-atmel-atmel-i2s-remove-useless-initialization.patch b/target/linux/at91/patches-5.15/187-ASoC-atmel-atmel-i2s-remove-useless-initialization.patch deleted file mode 100644 index ed2ae1a979..0000000000 --- a/target/linux/at91/patches-5.15/187-ASoC-atmel-atmel-i2s-remove-useless-initialization.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e53725fe0c7e6b52927280272f49fe5f4b4ef317 Mon Sep 17 00:00:00 2001 -From: Pierre-Louis Bossart -Date: Fri, 26 Mar 2021 16:59:13 -0500 -Subject: [PATCH 187/247] ASoC: atmel: atmel-i2s: remove useless initialization - -Cppcheck complains: - -sound/soc/atmel/atmel-i2s.c:628:6: style: Redundant initialization for 'err'. The initialized value is overwritten before it is read. [redundantInitialization] - err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0, - ^ -sound/soc/atmel/atmel-i2s.c:598:10: note: err is initialized - int err = -ENXIO; - ^ -sound/soc/atmel/atmel-i2s.c:628:6: note: err is overwritten - err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0, - ^ - -Signed-off-by: Pierre-Louis Bossart -Reviewed-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210326215927.936377-4-pierre-louis.bossart@linux.intel.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/atmel-i2s.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/sound/soc/atmel/atmel-i2s.c -+++ b/sound/soc/atmel/atmel-i2s.c -@@ -613,7 +613,7 @@ static int atmel_i2s_probe(struct platfo - struct regmap *regmap; - void __iomem *base; - int irq; -- int err = -ENXIO; -+ int err; - unsigned int pcm_flags = 0; - unsigned int version; - diff --git a/target/linux/at91/patches-5.15/188-ASoC-atmel-i2s-Set-symmetric-sample-bits.patch b/target/linux/at91/patches-5.15/188-ASoC-atmel-i2s-Set-symmetric-sample-bits.patch deleted file mode 100644 index bc8c7fa2b1..0000000000 --- a/target/linux/at91/patches-5.15/188-ASoC-atmel-i2s-Set-symmetric-sample-bits.patch +++ /dev/null @@ -1,26 +0,0 @@ -From a6f337fdf68294cfae233724567cbeea0ae5148f Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Fri, 18 Jun 2021 18:07:40 +0300 -Subject: [PATCH 188/247] ASoC: atmel-i2s: Set symmetric sample bits - -The I2S needs to have the same sample bits for both capture and playback -streams. - -Fixes: b543e467d1a9 ("ASoC: atmel-i2s: add driver for the new Atmel I2S controller") -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210618150741.401739-1-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/atmel-i2s.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/sound/soc/atmel/atmel-i2s.c -+++ b/sound/soc/atmel/atmel-i2s.c -@@ -560,6 +560,7 @@ static struct snd_soc_dai_driver atmel_i - }, - .ops = &atmel_i2s_dai_ops, - .symmetric_rates = 1, -+ .symmetric_samplebits = 1, - }; - - static const struct snd_soc_component_driver atmel_i2s_component = { diff --git a/target/linux/at91/patches-5.15/189-watchdog-sama5d4_wdt-add-support-for-sama7g5-wdt.patch b/target/linux/at91/patches-5.15/189-watchdog-sama5d4_wdt-add-support-for-sama7g5-wdt.patch deleted file mode 100644 index b79ccadf92..0000000000 --- a/target/linux/at91/patches-5.15/189-watchdog-sama5d4_wdt-add-support-for-sama7g5-wdt.patch +++ /dev/null @@ -1,46 +0,0 @@ -From ff83cc9f95aaba75991210312061b7fe52aaa400 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Thu, 27 May 2021 13:01:19 +0300 -Subject: [PATCH 189/247] watchdog: sama5d4_wdt: add support for sama7g5-wdt - -Add support for compatible sama7g5-wdt. -The sama7g5 wdt is the same hardware block as on sam9x60. -Adapt the driver to use the sam9x60/sama7g5 variant if either -of the two compatibles are selected (sam9x60-wdt/sama7g5-wdt). - -Signed-off-by: Eugen Hristev -Acked-by: Nicolas Ferre -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/20210527100120.266796-2-eugen.hristev@microchip.com -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/sama5d4_wdt.c | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - ---- a/drivers/watchdog/sama5d4_wdt.c -+++ b/drivers/watchdog/sama5d4_wdt.c -@@ -268,8 +268,10 @@ static int sama5d4_wdt_probe(struct plat - wdd->min_timeout = MIN_WDT_TIMEOUT; - wdd->max_timeout = MAX_WDT_TIMEOUT; - wdt->last_ping = jiffies; -- wdt->sam9x60_support = of_device_is_compatible(dev->of_node, -- "microchip,sam9x60-wdt"); -+ -+ if (of_device_is_compatible(dev->of_node, "microchip,sam9x60-wdt") || -+ of_device_is_compatible(dev->of_node, "microchip,sama7g5-wdt")) -+ wdt->sam9x60_support = true; - - watchdog_set_drvdata(wdd, wdt); - -@@ -329,6 +331,10 @@ static const struct of_device_id sama5d4 - { - .compatible = "microchip,sam9x60-wdt", - }, -+ { -+ .compatible = "microchip,sama7g5-wdt", -+ }, -+ - { } - }; - MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match); diff --git a/target/linux/at91/patches-5.15/190-media-atmel-fix-build-when-ISC-m-and-XISC-y.patch b/target/linux/at91/patches-5.15/190-media-atmel-fix-build-when-ISC-m-and-XISC-y.patch deleted file mode 100644 index 60b4104442..0000000000 --- a/target/linux/at91/patches-5.15/190-media-atmel-fix-build-when-ISC-m-and-XISC-y.patch +++ /dev/null @@ -1,135 +0,0 @@ -From dfcc0395f5e838c0b5c3fb93c9335b6a8892178a Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 5 Jul 2021 14:57:08 +0200 -Subject: [PATCH 190/247] media: atmel: fix build when ISC=m and XISC=y - -Building VIDEO_ATMEL_ISC as module and VIDEO_ATMEL_XISC as built-in -(or viceversa) causes build errors: - - or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o: in function `isc_async_complete': - atmel-isc-base.c:(.text+0x40d0): undefined reference to `__this_module' - or1k-linux-ld: atmel-isc-base.c:(.text+0x40f0): undefined reference to `__this_module' - or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(.rodata+0x390): undefined reference to `__this_module' - or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(__param+0x4): undefined reference to `__this_module' - or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(__param+0x18): undefined reference to `__this_module' - -This is caused by the file atmel-isc-base.c which is common code between -the two drivers. - -The solution is to create another Kconfig symbol that is automatically -selected and generates the module atmel-isc-base.ko. This module can be -loaded when both drivers are modules, or built-in when at least one of them -is built-in. - -Reported-by: kernel test robot -Fixes: c9aa973884a1 ("media: atmel: atmel-isc: add microchip-xisc driver") -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/Kconfig | 8 ++++++++ - drivers/media/platform/atmel/Makefile | 5 +++-- - drivers/media/platform/atmel/atmel-isc-base.c | 11 +++++++++++ - 3 files changed, 22 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/Kconfig -+++ b/drivers/media/platform/atmel/Kconfig -@@ -8,6 +8,7 @@ config VIDEO_ATMEL_ISC - select VIDEOBUF2_DMA_CONTIG - select REGMAP_MMIO - select V4L2_FWNODE -+ select VIDEO_ATMEL_ISC_BASE - help - This module makes the ATMEL Image Sensor Controller available - as a v4l2 device. -@@ -19,10 +20,17 @@ config VIDEO_ATMEL_XISC - select VIDEOBUF2_DMA_CONTIG - select REGMAP_MMIO - select V4L2_FWNODE -+ select VIDEO_ATMEL_ISC_BASE - help - This module makes the ATMEL eXtended Image Sensor Controller - available as a v4l2 device. - -+config VIDEO_ATMEL_ISC_BASE -+ tristate -+ default n -+ help -+ ATMEL ISC and XISC common code base. -+ - config VIDEO_ATMEL_ISI - tristate "ATMEL Image Sensor Interface (ISI) support" - depends on VIDEO_V4L2 && OF ---- a/drivers/media/platform/atmel/Makefile -+++ b/drivers/media/platform/atmel/Makefile -@@ -1,7 +1,8 @@ - # SPDX-License-Identifier: GPL-2.0-only --atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o --atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o -+atmel-isc-objs = atmel-sama5d2-isc.o -+atmel-xisc-objs = atmel-sama7g5-isc.o - - obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o -+obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += atmel-isc-base.o - obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o - obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -378,6 +378,7 @@ int isc_clk_init(struct isc_device *isc) - - return 0; - } -+EXPORT_SYMBOL_GPL(isc_clk_init); - - void isc_clk_cleanup(struct isc_device *isc) - { -@@ -392,6 +393,7 @@ void isc_clk_cleanup(struct isc_device * - clk_unregister(isc_clk->clk); - } - } -+EXPORT_SYMBOL_GPL(isc_clk_cleanup); - - static int isc_queue_setup(struct vb2_queue *vq, - unsigned int *nbuffers, unsigned int *nplanes, -@@ -1575,6 +1577,7 @@ irqreturn_t isc_interrupt(int irq, void - - return ret; - } -+EXPORT_SYMBOL_GPL(isc_interrupt); - - static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max) - { -@@ -2209,6 +2212,7 @@ const struct v4l2_async_notifier_operati - .unbind = isc_async_unbind, - .complete = isc_async_complete, - }; -+EXPORT_SYMBOL_GPL(isc_async_ops); - - void isc_subdev_cleanup(struct isc_device *isc) - { -@@ -2221,6 +2225,7 @@ void isc_subdev_cleanup(struct isc_devic - - INIT_LIST_HEAD(&isc->subdev_entities); - } -+EXPORT_SYMBOL_GPL(isc_subdev_cleanup); - - int isc_pipeline_init(struct isc_device *isc) - { -@@ -2261,6 +2266,7 @@ int isc_pipeline_init(struct isc_device - - return 0; - } -+EXPORT_SYMBOL_GPL(isc_pipeline_init); - - /* regmap configuration */ - #define ATMEL_ISC_REG_MAX 0xd5c -@@ -2270,4 +2276,9 @@ const struct regmap_config isc_regmap_co - .val_bits = 32, - .max_register = ATMEL_ISC_REG_MAX, - }; -+EXPORT_SYMBOL_GPL(isc_regmap_config); - -+MODULE_AUTHOR("Songjun Wu"); -+MODULE_AUTHOR("Eugen Hristev"); -+MODULE_DESCRIPTION("Atmel ISC common code base"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/at91/patches-5.15/191-i2c-at91-remove-define-CONFIG_PM.patch b/target/linux/at91/patches-5.15/191-i2c-at91-remove-define-CONFIG_PM.patch deleted file mode 100644 index 27ee1b6d19..0000000000 --- a/target/linux/at91/patches-5.15/191-i2c-at91-remove-define-CONFIG_PM.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 023a6b46536dce41f2c5a7425826fc4da4509b8f Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 5 Jul 2021 15:15:16 +0300 -Subject: [PATCH 191/247] i2c: at91: remove #define CONFIG_PM - -Remove #define CONFIG_PM and use __maybe_unused for PM functions and -pm_ptr() for PM ops. - -Signed-off-by: Claudiu Beznea -Reviewed-by: Codrin Ciubotariu -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-at91-core.c | 17 +++++------------ - 1 file changed, 5 insertions(+), 12 deletions(-) - ---- a/drivers/i2c/busses/i2c-at91-core.c -+++ b/drivers/i2c/busses/i2c-at91-core.c -@@ -286,9 +286,7 @@ static int at91_twi_remove(struct platfo - return 0; - } - --#ifdef CONFIG_PM -- --static int at91_twi_runtime_suspend(struct device *dev) -+static int __maybe_unused at91_twi_runtime_suspend(struct device *dev) - { - struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); - -@@ -299,7 +297,7 @@ static int at91_twi_runtime_suspend(stru - return 0; - } - --static int at91_twi_runtime_resume(struct device *dev) -+static int __maybe_unused at91_twi_runtime_resume(struct device *dev) - { - struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); - -@@ -308,7 +306,7 @@ static int at91_twi_runtime_resume(struc - return clk_prepare_enable(twi_dev->clk); - } - --static int at91_twi_suspend_noirq(struct device *dev) -+static int __maybe_unused at91_twi_suspend_noirq(struct device *dev) - { - if (!pm_runtime_status_suspended(dev)) - at91_twi_runtime_suspend(dev); -@@ -316,7 +314,7 @@ static int at91_twi_suspend_noirq(struct - return 0; - } - --static int at91_twi_resume_noirq(struct device *dev) -+static int __maybe_unused at91_twi_resume_noirq(struct device *dev) - { - struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); - int ret; -@@ -342,11 +340,6 @@ static const struct dev_pm_ops at91_twi_ - .runtime_resume = at91_twi_runtime_resume, - }; - --#define at91_twi_pm_ops (&at91_twi_pm) --#else --#define at91_twi_pm_ops NULL --#endif -- - static struct platform_driver at91_twi_driver = { - .probe = at91_twi_probe, - .remove = at91_twi_remove, -@@ -354,7 +347,7 @@ static struct platform_driver at91_twi_d - .driver = { - .name = "at91_i2c", - .of_match_table = of_match_ptr(atmel_twi_dt_ids), -- .pm = at91_twi_pm_ops, -+ .pm = pm_ptr(&at91_twi_pm), - }, - }; - diff --git a/target/linux/at91/patches-5.15/192-ASoC-codecs-ad193x-add-support-for-96kHz-and-192kHz-.patch b/target/linux/at91/patches-5.15/192-ASoC-codecs-ad193x-add-support-for-96kHz-and-192kHz-.patch deleted file mode 100644 index 6220c1dab2..0000000000 --- a/target/linux/at91/patches-5.15/192-ASoC-codecs-ad193x-add-support-for-96kHz-and-192kHz-.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 1c906a59a60887e1b997ebab63f19f33a1c69a3e Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Tue, 3 Aug 2021 13:48:25 +0300 -Subject: [PATCH 192/247] ASoC: codecs: ad193x: add support for 96kHz and - 192kHz playback rates - -ad193x devices support 96KHz and 192KHz sampling rates, when PLL/MCLK is -referenced to 48kHz. -Tested on ad1934. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210803104825.2198335-1-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/codecs/ad193x.c | 30 ++++++++++++++++++++++++++++-- - sound/soc/codecs/ad193x.h | 4 ++++ - 2 files changed, 32 insertions(+), 2 deletions(-) - ---- a/sound/soc/codecs/ad193x.c -+++ b/sound/soc/codecs/ad193x.c -@@ -316,6 +316,13 @@ static int ad193x_hw_params(struct snd_p - int word_len = 0, master_rate = 0; - struct snd_soc_component *component = dai->component; - struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(component); -+ bool is_playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; -+ u8 dacc0; -+ -+ dev_dbg(dai->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", -+ __func__, params_rate(params), params_format(params), -+ params_width(params), params_channels(params)); -+ - - /* bit size */ - switch (params_width(params)) { -@@ -346,6 +353,25 @@ static int ad193x_hw_params(struct snd_p - break; - } - -+ if (is_playback) { -+ switch (params_rate(params)) { -+ case 48000: -+ dacc0 = AD193X_DAC_SR_48; -+ break; -+ case 96000: -+ dacc0 = AD193X_DAC_SR_96; -+ break; -+ case 192000: -+ dacc0 = AD193X_DAC_SR_192; -+ break; -+ default: -+ dev_err(dai->dev, "invalid sampling rate: %d\n", params_rate(params)); -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL0, AD193X_DAC_SR_MASK, dacc0); -+ } -+ - regmap_update_bits(ad193x->regmap, AD193X_PLL_CLK_CTRL0, - AD193X_PLL_INPUT_MASK, master_rate); - -@@ -385,7 +411,7 @@ static struct snd_soc_dai_driver ad193x_ - .stream_name = "Playback", - .channels_min = 2, - .channels_max = 8, -- .rates = SNDRV_PCM_RATE_48000, -+ .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE, - }, -@@ -407,7 +433,7 @@ static struct snd_soc_dai_driver ad193x_ - .stream_name = "Playback", - .channels_min = 2, - .channels_max = 8, -- .rates = SNDRV_PCM_RATE_48000, -+ .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE, - }, ---- a/sound/soc/codecs/ad193x.h -+++ b/sound/soc/codecs/ad193x.h -@@ -37,6 +37,10 @@ int ad193x_probe(struct device *dev, str - #define AD193X_PLL_CLK_SRC_MCLK (1 << 1) - #define AD193X_DAC_CTRL0 0x02 - #define AD193X_DAC_POWERDOWN 0x01 -+#define AD193X_DAC_SR_MASK 0x06 -+#define AD193X_DAC_SR_48 (0 << 1) -+#define AD193X_DAC_SR_96 (1 << 1) -+#define AD193X_DAC_SR_192 (2 << 1) - #define AD193X_DAC_SERFMT_MASK 0xC0 - #define AD193X_DAC_SERFMT_STEREO (0 << 6) - #define AD193X_DAC_SERFMT_TDM (1 << 6) diff --git a/target/linux/at91/patches-5.15/193-media-atmel-atmel-sama5d2-isc-fix-YUYV-format.patch b/target/linux/at91/patches-5.15/193-media-atmel-atmel-sama5d2-isc-fix-YUYV-format.patch deleted file mode 100644 index a554a288a5..0000000000 --- a/target/linux/at91/patches-5.15/193-media-atmel-atmel-sama5d2-isc-fix-YUYV-format.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 21261e30679118b96ed537d1cdf9e12682fc1b29 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Wed, 9 Jun 2021 15:00:28 +0200 -Subject: [PATCH 193/247] media: atmel: atmel-sama5d2-isc: fix YUYV format - -SAMA5D2 does not have the YCYC field for the RLP (rounding, limiting, -packaging) module. -The YCYC field is supposed to work with interleaved YUV formats like YUYV. -In SAMA5D2, we have to use YYCC field, which is used for both planar -formats like YUV420 and interleaved formats like YUYV. -Fix the according rlp callback to replace the generic YCYC field (which -makes more sense from a logical point of view) with the required YYCC -field. - -Fixes: debfa496871c ("media: atmel: atmel-isc-base: add support for more formats and additional pipeline modules") -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../media/platform/atmel/atmel-sama5d2-isc.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -255,6 +255,23 @@ static void isc_sama5d2_config_rlp(struc - struct regmap *regmap = isc->regmap; - u32 rlp_mode = isc->config.rlp_cfg_mode; - -+ /* -+ * In sama5d2, the YUV planar modes and the YUYV modes are treated -+ * in the same way in RLP register. -+ * Normally, YYCC mode should be Luma(n) - Color B(n) - Color R (n) -+ * and YCYC should be Luma(n + 1) - Color B (n) - Luma (n) - Color R (n) -+ * but in sama5d2, the YCYC mode does not exist, and YYCC must be -+ * selected for both planar and interleaved modes, as in fact -+ * both modes are supported. -+ * -+ * Thus, if the YCYC mode is selected, replace it with the -+ * sama5d2-compliant mode which is YYCC . -+ */ -+ if ((rlp_mode & ISC_RLP_CFG_MODE_YCYC) == ISC_RLP_CFG_MODE_YCYC) { -+ rlp_mode &= ~ISC_RLP_CFG_MODE_MASK; -+ rlp_mode |= ISC_RLP_CFG_MODE_YYCC; -+ } -+ - regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, - ISC_RLP_CFG_MODE_MASK, rlp_mode); - } diff --git a/target/linux/at91/patches-5.15/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch b/target/linux/at91/patches-5.15/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch deleted file mode 100644 index dd221f5be9..0000000000 --- a/target/linux/at91/patches-5.15/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 602f85ff15d45bd313f8f6600d72202a50fd83a9 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 19 Jul 2021 11:03:17 +0300 -Subject: [PATCH 194/247] clk: at91: add register definition for sama7g5's - master clock - -Add register definitions for SAMA7G5's master clock. These would be -also used by architecture specific power saving code. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210719080317.1045832-3-claudiu.beznea@microchip.com ---- - include/linux/clk/at91_pmc.h | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - ---- a/include/linux/clk/at91_pmc.h -+++ b/include/linux/clk/at91_pmc.h -@@ -137,6 +137,32 @@ - #define AT91_PMC_PLLADIV2_ON (1 << 12) - #define AT91_PMC_H32MXDIV BIT(24) - -+#define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */ -+#define AT91_PMC_MCR_V2_ID_MSK (0xF) -+#define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MSK) -+#define AT91_PMC_MCR_V2_CMD (1 << 7) -+#define AT91_PMC_MCR_V2_DIV (7 << 8) -+#define AT91_PMC_MCR_V2_DIV1 (0 << 8) -+#define AT91_PMC_MCR_V2_DIV2 (1 << 8) -+#define AT91_PMC_MCR_V2_DIV4 (2 << 8) -+#define AT91_PMC_MCR_V2_DIV8 (3 << 8) -+#define AT91_PMC_MCR_V2_DIV16 (4 << 8) -+#define AT91_PMC_MCR_V2_DIV32 (5 << 8) -+#define AT91_PMC_MCR_V2_DIV64 (6 << 8) -+#define AT91_PMC_MCR_V2_DIV3 (7 << 8) -+#define AT91_PMC_MCR_V2_CSS (0x1F << 16) -+#define AT91_PMC_MCR_V2_CSS_MD_SLCK (0 << 16) -+#define AT91_PMC_MCR_V2_CSS_TD_SLCK (1 << 16) -+#define AT91_PMC_MCR_V2_CSS_MAINCK (2 << 16) -+#define AT91_PMC_MCR_V2_CSS_MCK0 (3 << 16) -+#define AT91_PMC_MCR_V2_CSS_SYSPLL (5 << 16) -+#define AT91_PMC_MCR_V2_CSS_DDRPLL (6 << 16) -+#define AT91_PMC_MCR_V2_CSS_IMGPLL (7 << 16) -+#define AT91_PMC_MCR_V2_CSS_BAUDPLL (8 << 16) -+#define AT91_PMC_MCR_V2_CSS_AUDIOPLL (9 << 16) -+#define AT91_PMC_MCR_V2_CSS_ETHPLL (10 << 16) -+#define AT91_PMC_MCR_V2_EN (1 << 28) -+ - #define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */ - - #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ diff --git a/target/linux/at91/patches-5.15/195-ARM-at91-add-new-SoC-sama7g5.patch b/target/linux/at91/patches-5.15/195-ARM-at91-add-new-SoC-sama7g5.patch deleted file mode 100644 index 1d6b45ac94..0000000000 --- a/target/linux/at91/patches-5.15/195-ARM-at91-add-new-SoC-sama7g5.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 32bac6971d0572f67758f9a8c8af7bf4592f1675 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 9 Apr 2021 14:31:15 +0300 -Subject: [PATCH 195/247] ARM: at91: add new SoC sama7g5 - -Add new SoC from at91 family : sama7g5 - -Signed-off-by: Eugen Hristev -[claudiu.beznea@microchip.com: Select PLL, generic clock and UTMI support, add PM configs] -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210409113116.482199-1-eugen.hristev@microchip.com -Link: https://lore.kernel.org/r/20210719080317.1045832-2-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/Kconfig | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/arch/arm/mach-at91/Kconfig -+++ b/arch/arm/mach-at91/Kconfig -@@ -57,6 +57,16 @@ config SOC_SAMA5D4 - help - Select this if you are using one of Microchip's SAMA5D4 family SoC. - -+config SOC_SAMA7G5 -+ bool "SAMA7G5 family" -+ depends on ARCH_MULTI_V7 -+ select HAVE_AT91_GENERATED_CLK -+ select HAVE_AT91_SAM9X60_PLL -+ select HAVE_AT91_UTMI -+ select SOC_SAMA7 -+ help -+ Select this if you are using one of Microchip's SAMA7G5 family SoC. -+ - config SOC_AT91RM9200 - bool "AT91RM9200" - depends on ARCH_MULTI_V4T -@@ -191,4 +201,12 @@ config SOC_SAMA5 - config ATMEL_PM - bool - -+config SOC_SAMA7 -+ bool -+ select ARM_GIC -+ select ATMEL_PM if PM -+ select ATMEL_SDRAMC -+ select MEMORY -+ select SOC_SAM_V7 -+ select SRAM if PM - endif diff --git a/target/linux/at91/patches-5.15/196-ARM-at91-debug-add-sama7g5-low-level-debug-uart.patch b/target/linux/at91/patches-5.15/196-ARM-at91-debug-add-sama7g5-low-level-debug-uart.patch deleted file mode 100644 index c99a2d5219..0000000000 --- a/target/linux/at91/patches-5.15/196-ARM-at91-debug-add-sama7g5-low-level-debug-uart.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 3de4879bf59b46a966ea226a67df70b88f43a23e Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 9 Apr 2021 14:31:16 +0300 -Subject: [PATCH 196/247] ARM: at91: debug: add sama7g5 low level debug uart - -Add sama7g5 SoC debug uart on Flexcom3. This is the UART that the -ROM bootloader uses. - -Signed-off-by: Eugen Hristev -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210409113116.482199-2-eugen.hristev@microchip.com -[claudiu.beznea: adapt to v5.10.27] -Signed-off-by: Claudiu Beznea ---- - arch/arm/Kconfig.debug | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm/Kconfig.debug -+++ b/arch/arm/Kconfig.debug -@@ -191,6 +191,14 @@ choice - their output to the USART1 port on SAMV7 based - machines. - -+ config DEBUG_AT91_SAMA7G5_FLEXCOM3 -+ bool "Kernel low-level debugging on SAMA7G5 FLEXCOM3" -+ select DEBUG_AT91_UART -+ depends on SOC_SAMA7G5 -+ help -+ Say Y here if you want kernel low-level debugging support -+ on the FLEXCOM3 port of SAMA7G5. -+ - config DEBUG_BCM2835 - bool "Kernel low-level debugging on BCM2835 PL011 UART" - depends on ARCH_BCM2835 && ARCH_MULTI_V6 -@@ -1731,6 +1739,7 @@ config DEBUG_UART_PHYS - default 0xd4017000 if DEBUG_MMP_UART2 - default 0xd4018000 if DEBUG_MMP_UART3 - default 0xe0000000 if DEBUG_SPEAR13XX -+ default 0xe1824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3 - default 0xe4007000 if DEBUG_HIP04_UART - default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0 - default 0xe6c50000 if DEBUG_RMOBILE_SCIFA1 -@@ -1791,6 +1800,7 @@ config DEBUG_UART_VIRT - default 0xc8912000 if DEBUG_RV1108_UART0 - default 0xe0010fe0 if ARCH_RPC - default 0xf0000be0 if ARCH_EBSA110 -+ default 0xe0824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3 - default 0xf0010000 if DEBUG_ASM9260_UART - default 0xf0100000 if DEBUG_DIGICOLOR_UA0 - default 0xf01fb000 if DEBUG_NOMADIK_UART diff --git a/target/linux/at91/patches-5.15/197-ARM-at91-pm-move-pm_bu-to-soc_pm-data-structure.patch b/target/linux/at91/patches-5.15/197-ARM-at91-pm-move-pm_bu-to-soc_pm-data-structure.patch deleted file mode 100644 index dfd47d55d2..0000000000 --- a/target/linux/at91/patches-5.15/197-ARM-at91-pm-move-pm_bu-to-soc_pm-data-structure.patch +++ /dev/null @@ -1,87 +0,0 @@ -From e41d00bdaa31b36fd314e927104082615aa4643a Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:47 +0300 -Subject: [PATCH 197/247] ARM: at91: pm: move pm_bu to soc_pm data structure - -Move pm_bu to soc_pm data structure. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-2-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 34 +++++++++++++++++++++------------- - 1 file changed, 21 insertions(+), 13 deletions(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -27,10 +27,25 @@ - #include "generic.h" - #include "pm.h" - -+/** -+ * struct at91_pm_bu - AT91 power management backup unit data structure -+ * @suspended: true if suspended to backup mode -+ * @reserved: reserved -+ * @canary: canary data for memory checking after exit from backup mode -+ * @resume: resume API -+ */ -+struct at91_pm_bu { -+ int suspended; -+ unsigned long reserved; -+ phys_addr_t canary; -+ phys_addr_t resume; -+}; -+ - struct at91_soc_pm { - int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); - int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); - const struct of_device_id *ws_ids; -+ struct at91_pm_bu *bu; - struct at91_pm_data data; - }; - -@@ -71,13 +86,6 @@ static int at91_pm_valid_state(suspend_s - - static int canary = 0xA5A5A5A5; - --static struct at91_pm_bu { -- int suspended; -- unsigned long reserved; -- phys_addr_t canary; -- phys_addr_t resume; --} *pm_bu; -- - struct wakeup_source_info { - unsigned int pmc_fsmr_bit; - unsigned int shdwc_mr_bit; -@@ -288,7 +296,7 @@ static int at91_suspend_finish(unsigned - static void at91_pm_suspend(suspend_state_t state) - { - if (soc_pm.data.mode == AT91_PM_BACKUP) { -- pm_bu->suspended = 1; -+ soc_pm.bu->suspended = 1; - - cpu_suspend(0, at91_suspend_finish); - -@@ -672,16 +680,16 @@ static int __init at91_pm_backup_init(vo - goto securam_fail; - } - -- pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); -- if (!pm_bu) { -+ soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); -+ if (!soc_pm.bu) { - pr_warn("%s: unable to alloc securam!\n", __func__); - ret = -ENOMEM; - goto securam_fail; - } - -- pm_bu->suspended = 0; -- pm_bu->canary = __pa_symbol(&canary); -- pm_bu->resume = __pa_symbol(cpu_resume); -+ soc_pm.bu->suspended = 0; -+ soc_pm.bu->canary = __pa_symbol(&canary); -+ soc_pm.bu->resume = __pa_symbol(cpu_resume); - - return 0; - diff --git a/target/linux/at91/patches-5.15/198-ARM-at91-pm-move-the-setup-of-soc_pm.bu-suspended.patch b/target/linux/at91/patches-5.15/198-ARM-at91-pm-move-the-setup-of-soc_pm.bu-suspended.patch deleted file mode 100644 index 5b484b7343..0000000000 --- a/target/linux/at91/patches-5.15/198-ARM-at91-pm-move-the-setup-of-soc_pm.bu-suspended.patch +++ /dev/null @@ -1,55 +0,0 @@ -From c8f2a8aaae41fa0a40ad88855ae82696098230d7 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:48 +0300 -Subject: [PATCH 198/247] ARM: at91: pm: move the setup of soc_pm.bu->suspended - -Move the setup of soc_pm.bu->suspended in platform_suspend::begin -function so that the PMC code in charge with clocks suspend/resume -to differentiate b/w standard PM mode and backup mode. - -Signed-off-by: Claudiu Beznea -Reviewed-by: Alexandre Belloni -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-3-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 15 ++++++++++++--- - 1 file changed, 12 insertions(+), 3 deletions(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -214,6 +214,8 @@ static int at91_sam9x60_config_pmc_ws(vo - */ - static int at91_pm_begin(suspend_state_t state) - { -+ int ret; -+ - switch (state) { - case PM_SUSPEND_MEM: - soc_pm.data.mode = soc_pm.data.suspend_mode; -@@ -227,7 +229,16 @@ static int at91_pm_begin(suspend_state_t - soc_pm.data.mode = -1; - } - -- return at91_pm_config_ws(soc_pm.data.mode, true); -+ ret = at91_pm_config_ws(soc_pm.data.mode, true); -+ if (ret) -+ return ret; -+ -+ if (soc_pm.data.mode == AT91_PM_BACKUP) -+ soc_pm.bu->suspended = 1; -+ else if (soc_pm.bu) -+ soc_pm.bu->suspended = 0; -+ -+ return 0; - } - - /* -@@ -296,8 +307,6 @@ static int at91_suspend_finish(unsigned - static void at91_pm_suspend(suspend_state_t state) - { - if (soc_pm.data.mode == AT91_PM_BACKUP) { -- soc_pm.bu->suspended = 1; -- - cpu_suspend(0, at91_suspend_finish); - - /* The SRAM is lost between suspend cycles */ diff --git a/target/linux/at91/patches-5.15/199-ARM-at91-pm-document-at91_soc_pm-structure.patch b/target/linux/at91/patches-5.15/199-ARM-at91-pm-document-at91_soc_pm-structure.patch deleted file mode 100644 index 965555a11d..0000000000 --- a/target/linux/at91/patches-5.15/199-ARM-at91-pm-document-at91_soc_pm-structure.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 59a4b3b9381b727f416d9cc52e60d0bc7d93ecae Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:49 +0300 -Subject: [PATCH 199/247] ARM: at91: pm: document at91_soc_pm structure - -Document at91_soc_pm structure. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-4-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -41,6 +41,14 @@ struct at91_pm_bu { - phys_addr_t resume; - }; - -+/** -+ * struct at91_soc_pm - AT91 SoC power management data structure -+ * @config_shdwc_ws: wakeup sources configuration function for SHDWC -+ * @config_pmc_ws: wakeup srouces configuration function for PMC -+ * @ws_ids: wakup sources of_device_id array -+ * @data: PM data to be used on last phase of suspend -+ * @bu: backup unit mapped data (for backup mode) -+ */ - struct at91_soc_pm { - int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); - int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); diff --git a/target/linux/at91/patches-5.15/200-ARM-at91-pm-check-for-different-controllers-in-at91_.patch b/target/linux/at91/patches-5.15/200-ARM-at91-pm-check-for-different-controllers-in-at91_.patch deleted file mode 100644 index f15095aafd..0000000000 --- a/target/linux/at91/patches-5.15/200-ARM-at91-pm-check-for-different-controllers-in-at91_.patch +++ /dev/null @@ -1,238 +0,0 @@ -From 0c4cbd38a705bdeab11de4c84ad0ce8c3de8a81d Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:50 +0300 -Subject: [PATCH 200/247] ARM: at91: pm: check for different controllers in - at91_pm_modes_init() - -at91_pm_modes_init() checks for proper nodes in device tree and maps -them accordingly. Up to SAMA7G5 all AT91 SoCs had the same mapping -b/w power saving modes and different controllers needed in the -final/first steps of suspend/resume. SAMA7G5 is not aligned with the -old SoCs thus the code is adapted for this. This patch prepares -the field for next commits. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-5-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 143 +++++++++++++++++++++++++--------------- - 1 file changed, 91 insertions(+), 52 deletions(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -57,6 +57,18 @@ struct at91_soc_pm { - struct at91_pm_data data; - }; - -+/** -+ * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes -+ * @AT91_PM_IOMAP_SHDWC: SHDWC controller -+ * @AT91_PM_IOMAP_SFRBU: SFRBU controller -+ */ -+enum at91_pm_iomaps { -+ AT91_PM_IOMAP_SHDWC, -+ AT91_PM_IOMAP_SFRBU, -+}; -+ -+#define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name) -+ - static struct at91_soc_pm soc_pm = { - .data = { - .standby_mode = AT91_PM_STANDBY, -@@ -671,24 +683,15 @@ static int __init at91_pm_backup_init(vo - if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) - return 0; - -- np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); -- if (!np) { -- pr_warn("%s: failed to find sfrbu!\n", __func__); -- return ret; -- } -- -- soc_pm.data.sfrbu = of_iomap(np, 0); -- of_node_put(np); -- - np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); - if (!np) -- goto securam_fail_no_ref_dev; -+ return ret; - - pdev = of_find_device_by_node(np); - of_node_put(np); - if (!pdev) { - pr_warn("%s: failed to find securam device!\n", __func__); -- goto securam_fail_no_ref_dev; -+ return ret; - } - - sram_pool = gen_pool_get(&pdev->dev, NULL); -@@ -712,64 +715,92 @@ static int __init at91_pm_backup_init(vo - - securam_fail: - put_device(&pdev->dev); --securam_fail_no_ref_dev: -- iounmap(soc_pm.data.sfrbu); -- soc_pm.data.sfrbu = NULL; - return ret; - } - --static void __init at91_pm_use_default_mode(int pm_mode) --{ -- if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP) -- return; -- -- if (soc_pm.data.standby_mode == pm_mode) -- soc_pm.data.standby_mode = AT91_PM_ULP0; -- if (soc_pm.data.suspend_mode == pm_mode) -- soc_pm.data.suspend_mode = AT91_PM_ULP0; --} -- - static const struct of_device_id atmel_shdwc_ids[] = { - { .compatible = "atmel,sama5d2-shdwc" }, - { .compatible = "microchip,sam9x60-shdwc" }, - { /* sentinel. */ } - }; - --static void __init at91_pm_modes_init(void) -+static void __init at91_pm_modes_init(const u32 *maps, int len) - { - struct device_node *np; -- int ret; -+ int ret, mode; - -- if (!at91_is_pm_mode_active(AT91_PM_BACKUP) && -- !at91_is_pm_mode_active(AT91_PM_ULP1)) -- return; -+ ret = at91_pm_backup_init(); -+ if (ret) { -+ if (soc_pm.data.standby_mode == AT91_PM_BACKUP) -+ soc_pm.data.standby_mode = AT91_PM_ULP0; -+ if (soc_pm.data.suspend_mode == AT91_PM_BACKUP) -+ soc_pm.data.suspend_mode = AT91_PM_ULP0; -+ } -+ -+ if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || -+ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) { -+ np = of_find_matching_node(NULL, atmel_shdwc_ids); -+ if (!np) { -+ pr_warn("%s: failed to find shdwc!\n", __func__); -+ -+ /* Use ULP0 if it doesn't needs SHDWC.*/ -+ if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC))) -+ mode = AT91_PM_ULP0; -+ else -+ mode = AT91_PM_STANDBY; -+ -+ if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC)) -+ soc_pm.data.standby_mode = mode; -+ if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) -+ soc_pm.data.suspend_mode = mode; -+ } else { -+ soc_pm.data.shdwc = of_iomap(np, 0); -+ of_node_put(np); -+ } -+ } - -- np = of_find_matching_node(NULL, atmel_shdwc_ids); -- if (!np) { -- pr_warn("%s: failed to find shdwc!\n", __func__); -- goto ulp1_default; -+ if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || -+ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) { -+ np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); -+ if (!np) { -+ pr_warn("%s: failed to find sfrbu!\n", __func__); -+ -+ /* -+ * Use ULP0 if it doesn't need SHDWC or if SHDWC -+ * was already located. -+ */ -+ if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) || -+ soc_pm.data.shdwc) -+ mode = AT91_PM_ULP0; -+ else -+ mode = AT91_PM_STANDBY; -+ -+ if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU)) -+ soc_pm.data.standby_mode = mode; -+ if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) -+ soc_pm.data.suspend_mode = mode; -+ } else { -+ soc_pm.data.sfrbu = of_iomap(np, 0); -+ of_node_put(np); -+ } - } - -- soc_pm.data.shdwc = of_iomap(np, 0); -- of_node_put(np); -+ /* Unmap all unnecessary. */ -+ if (soc_pm.data.shdwc && -+ !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || -+ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) { -+ iounmap(soc_pm.data.shdwc); -+ soc_pm.data.shdwc = NULL; -+ } - -- ret = at91_pm_backup_init(); -- if (ret) { -- if (!at91_is_pm_mode_active(AT91_PM_ULP1)) -- goto unmap; -- else -- goto backup_default; -+ if (soc_pm.data.sfrbu && -+ !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || -+ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) { -+ iounmap(soc_pm.data.sfrbu); -+ soc_pm.data.sfrbu = NULL; - } - - return; -- --unmap: -- iounmap(soc_pm.data.shdwc); -- soc_pm.data.shdwc = NULL; --ulp1_default: -- at91_pm_use_default_mode(AT91_PM_ULP1); --backup_default: -- at91_pm_use_default_mode(AT91_PM_BACKUP); - } - - struct pmc_info { -@@ -936,13 +967,16 @@ void __init sam9x60_pm_init(void) - static const int modes[] __initconst = { - AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, - }; -+ static const int iomaps[] __initconst = { -+ [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), -+ }; - int ret; - - if (!IS_ENABLED(CONFIG_SOC_SAM9X60)) - return; - - at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); -- at91_pm_modes_init(); -+ at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); - ret = at91_dt_ramc(); - if (ret) - return; -@@ -999,13 +1033,18 @@ void __init sama5d2_pm_init(void) - AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, - AT91_PM_BACKUP, - }; -+ static const u32 iomaps[] __initconst = { -+ [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), -+ [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) | -+ AT91_PM_IOMAP(SFRBU), -+ }; - int ret; - - if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) - return; - - at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); -- at91_pm_modes_init(); -+ at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); - ret = at91_dt_ramc(); - if (ret) - return; diff --git a/target/linux/at91/patches-5.15/201-ARM-at91-pm-do-not-initialize-pdev.patch b/target/linux/at91/patches-5.15/201-ARM-at91-pm-do-not-initialize-pdev.patch deleted file mode 100644 index 413a95a968..0000000000 --- a/target/linux/at91/patches-5.15/201-ARM-at91-pm-do-not-initialize-pdev.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 31e25503bbad1fffd29fd074a46bd4858b65304f Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:51 +0300 -Subject: [PATCH 201/247] ARM: at91: pm: do not initialize pdev - -There is no need to initialize pdev. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-6-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -674,7 +674,7 @@ static int __init at91_pm_backup_init(vo - { - struct gen_pool *sram_pool; - struct device_node *np; -- struct platform_device *pdev = NULL; -+ struct platform_device *pdev; - int ret = -ENODEV; - - if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) diff --git a/target/linux/at91/patches-5.15/202-ARM-at91-pm-use-r7-instead-of-tmp1.patch b/target/linux/at91/patches-5.15/202-ARM-at91-pm-use-r7-instead-of-tmp1.patch deleted file mode 100644 index a313ab029a..0000000000 --- a/target/linux/at91/patches-5.15/202-ARM-at91-pm-use-r7-instead-of-tmp1.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 8a7a4cf3860910e460e2c3ca467b1dabf7ce9827 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:52 +0300 -Subject: [PATCH 202/247] ARM: at91: pm: use r7 instead of tmp1 - -Use r7 instead of tmp1 in macros. This prepares the filed for -next commits. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-7-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 18 ++++++++++++------ - 1 file changed, 12 insertions(+), 6 deletions(-) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -31,30 +31,36 @@ tmp3 .req r6 - - /* - * Wait until master oscillator has stabilized. -+ * -+ * Side effects: overwrites r7 - */ - .macro wait_moscrdy --1: ldr tmp1, [pmc, #AT91_PMC_SR] -- tst tmp1, #AT91_PMC_MOSCS -+1: ldr r7, [pmc, #AT91_PMC_SR] -+ tst r7, #AT91_PMC_MOSCS - beq 1b - .endm - - /* - * Wait for main oscillator selection is done -+ * -+ * Side effects: overwrites r7 - */ - .macro wait_moscsels --1: ldr tmp1, [pmc, #AT91_PMC_SR] -- tst tmp1, #AT91_PMC_MOSCSELS -+1: ldr r7, [pmc, #AT91_PMC_SR] -+ tst r7, #AT91_PMC_MOSCSELS - beq 1b - .endm - - /* - * Put the processor to enter the idle state -+ * -+ * Side effects: overwrites r7 - */ - .macro at91_cpu_idle - - #if defined(CONFIG_CPU_V7) -- mov tmp1, #AT91_PMC_PCK -- str tmp1, [pmc, #AT91_PMC_SCDR] -+ mov r7, #AT91_PMC_PCK -+ str r7, [pmc, #AT91_PMC_SCDR] - - dsb - diff --git a/target/linux/at91/patches-5.15/203-ARM-at91-pm-avoid-push-and-pop-on-stack-while-memory.patch b/target/linux/at91/patches-5.15/203-ARM-at91-pm-avoid-push-and-pop-on-stack-while-memory.patch deleted file mode 100644 index a2edec371d..0000000000 --- a/target/linux/at91/patches-5.15/203-ARM-at91-pm-avoid-push-and-pop-on-stack-while-memory.patch +++ /dev/null @@ -1,467 +0,0 @@ -From 892f6d2fb9c42d4ac451236639599f533c37b507 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:53 +0300 -Subject: [PATCH 203/247] ARM: at91: pm: avoid push and pop on stack while - memory is in self-refersh - -For the previous AT91 RAM controller and self-refresh procedure this -had no side effects. However, for SAMA7G5 the self-refresh procedure -doesn't allow this anymore as the RAM controller ports are closed -before switching it to self-refresh. This commits prepares the code -for the following ones adding self-refresh and PM support for SAMA7G5. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-8-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 397 +++++++++++++++++--------------- - 1 file changed, 205 insertions(+), 192 deletions(-) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -75,98 +75,147 @@ tmp3 .req r6 - - .arm - --/* -- * void at91_suspend_sram_fn(struct at91_pm_data*) -- * @input param: -- * @r0: base address of struct at91_pm_data -+/** -+ * Enable self-refresh -+ * -+ * register usage: -+ * @r1: memory type -+ * @r2: base address of the sram controller -+ * @r3: temporary - */ --/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ -- .align 3 --ENTRY(at91_pm_suspend_in_sram) -- /* Save registers on stack */ -- stmfd sp!, {r4 - r12, lr} -+.macro at91_sramc_self_refresh_ena -+ ldr r1, .memtype -+ ldr r2, .sramc_base - -- /* Drain write buffer */ -- mov tmp1, #0 -- mcr p15, 0, tmp1, c7, c10, 4 -+ cmp r1, #AT91_MEMCTRL_MC -+ bne sr_ena_ddrc_sf - -- ldr tmp1, [r0, #PM_DATA_PMC] -- str tmp1, .pmc_base -- ldr tmp1, [r0, #PM_DATA_RAMC0] -- str tmp1, .sramc_base -- ldr tmp1, [r0, #PM_DATA_RAMC1] -- str tmp1, .sramc1_base -- ldr tmp1, [r0, #PM_DATA_MEMCTRL] -- str tmp1, .memtype -- ldr tmp1, [r0, #PM_DATA_MODE] -- str tmp1, .pm_mode -- ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] -- str tmp1, .mckr_offset -- ldr tmp1, [r0, #PM_DATA_PMC_VERSION] -- str tmp1, .pmc_version -- /* Both ldrne below are here to preload their address in the TLB */ -- ldr tmp1, [r0, #PM_DATA_SHDWC] -- str tmp1, .shdwc -- cmp tmp1, #0 -- ldrne tmp2, [tmp1, #0] -- ldr tmp1, [r0, #PM_DATA_SFRBU] -- str tmp1, .sfrbu -- cmp tmp1, #0 -- ldrne tmp2, [tmp1, #0x10] -+ /* Active SDRAM self-refresh mode */ -+ mov r3, #1 -+ str r3, [r2, #AT91_MC_SDRAMC_SRR] -+ b sr_ena_exit - -- /* Active the self-refresh mode */ -- mov r0, #SRAMC_SELF_FRESH_ACTIVE -- bl at91_sramc_self_refresh -+sr_ena_ddrc_sf: -+ cmp r1, #AT91_MEMCTRL_DDRSDR -+ bne sr_ena_sdramc_sf - -- ldr r0, .pm_mode -- cmp r0, #AT91_PM_STANDBY -- beq standby -- cmp r0, #AT91_PM_BACKUP -- beq backup_mode -+ /* -+ * DDR Memory controller -+ */ - -- bl at91_ulp_mode -- b exit_suspend -+ /* LPDDR1 --> force DDR2 mode during self-refresh */ -+ ldr r3, [r2, #AT91_DDRSDRC_MDR] -+ str r3, .saved_sam9_mdr -+ bic r3, r3, #~AT91_DDRSDRC_MD -+ cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR -+ ldreq r3, [r2, #AT91_DDRSDRC_MDR] -+ biceq r3, r3, #AT91_DDRSDRC_MD -+ orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 -+ streq r3, [r2, #AT91_DDRSDRC_MDR] - --standby: -- /* Wait for interrupt */ -- ldr pmc, .pmc_base -- at91_cpu_idle -- b exit_suspend -+ /* Active DDRC self-refresh mode */ -+ ldr r3, [r2, #AT91_DDRSDRC_LPR] -+ str r3, .saved_sam9_lpr -+ bic r3, r3, #AT91_DDRSDRC_LPCB -+ orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH -+ str r3, [r2, #AT91_DDRSDRC_LPR] - --backup_mode: -- bl at91_backup_mode -- b exit_suspend -+ /* If using the 2nd ddr controller */ -+ ldr r2, .sramc1_base -+ cmp r2, #0 -+ beq sr_ena_no_2nd_ddrc - --exit_suspend: -- /* Exit the self-refresh mode */ -- mov r0, #SRAMC_SELF_FRESH_EXIT -- bl at91_sramc_self_refresh -+ ldr r3, [r2, #AT91_DDRSDRC_MDR] -+ str r3, .saved_sam9_mdr1 -+ bic r3, r3, #~AT91_DDRSDRC_MD -+ cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR -+ ldreq r3, [r2, #AT91_DDRSDRC_MDR] -+ biceq r3, r3, #AT91_DDRSDRC_MD -+ orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 -+ streq r3, [r2, #AT91_DDRSDRC_MDR] - -- /* Restore registers, and return */ -- ldmfd sp!, {r4 - r12, pc} --ENDPROC(at91_pm_suspend_in_sram) -+ /* Active DDRC self-refresh mode */ -+ ldr r3, [r2, #AT91_DDRSDRC_LPR] -+ str r3, .saved_sam9_lpr1 -+ bic r3, r3, #AT91_DDRSDRC_LPCB -+ orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH -+ str r3, [r2, #AT91_DDRSDRC_LPR] - --ENTRY(at91_backup_mode) -- /* Switch the master clock source to slow clock. */ -- ldr pmc, .pmc_base -- ldr tmp2, .mckr_offset -- ldr tmp1, [pmc, tmp2] -- bic tmp1, tmp1, #AT91_PMC_CSS -- str tmp1, [pmc, tmp2] -+sr_ena_no_2nd_ddrc: -+ b sr_ena_exit - -- wait_mckrdy -+ /* -+ * SDRAMC Memory controller -+ */ -+sr_ena_sdramc_sf: -+ /* Active SDRAMC self-refresh mode */ -+ ldr r3, [r2, #AT91_SDRAMC_LPR] -+ str r3, .saved_sam9_lpr -+ bic r3, r3, #AT91_SDRAMC_LPCB -+ orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH -+ str r3, [r2, #AT91_SDRAMC_LPR] - -- /*BUMEN*/ -- ldr r0, .sfrbu -- mov tmp1, #0x1 -- str tmp1, [r0, #0x10] -+ ldr r3, .saved_sam9_lpr -+ str r3, [r2, #AT91_SDRAMC_LPR] - -- /* Shutdown */ -- ldr r0, .shdwc -- mov tmp1, #0xA5000000 -- add tmp1, tmp1, #0x1 -- str tmp1, [r0, #0] --ENDPROC(at91_backup_mode) -+sr_ena_exit: -+.endm -+ -+/** -+ * Disable self-refresh -+ * -+ * register usage: -+ * @r1: memory type -+ * @r2: base address of the sram controller -+ * @r3: temporary -+ */ -+.macro at91_sramc_self_refresh_dis -+ ldr r1, .memtype -+ ldr r2, .sramc_base -+ -+ cmp r1, #AT91_MEMCTRL_MC -+ bne sr_dis_ddrc_exit_sf -+ -+ /* -+ * at91rm9200 Memory controller -+ */ -+ -+ /* -+ * For exiting the self-refresh mode, do nothing, -+ * automatically exit the self-refresh mode. -+ */ -+ b sr_dis_exit -+ -+sr_dis_ddrc_exit_sf: -+ cmp r1, #AT91_MEMCTRL_DDRSDR -+ bne sdramc_exit_sf -+ -+ /* DDR Memory controller */ -+ -+ /* Restore MDR in case of LPDDR1 */ -+ ldr r3, .saved_sam9_mdr -+ str r3, [r2, #AT91_DDRSDRC_MDR] -+ /* Restore LPR on AT91 with DDRAM */ -+ ldr r3, .saved_sam9_lpr -+ str r3, [r2, #AT91_DDRSDRC_LPR] -+ -+ /* If using the 2nd ddr controller */ -+ ldr r2, .sramc1_base -+ cmp r2, #0 -+ ldrne r3, .saved_sam9_mdr1 -+ strne r3, [r2, #AT91_DDRSDRC_MDR] -+ ldrne r3, .saved_sam9_lpr1 -+ strne r3, [r2, #AT91_DDRSDRC_LPR] -+ -+ b sr_dis_exit -+ -+sdramc_exit_sf: -+ /* SDRAMC Memory controller */ -+ ldr r3, .saved_sam9_lpr -+ str r3, [r2, #AT91_SDRAMC_LPR] -+ -+sr_dis_exit: -+.endm - - .macro at91_pm_ulp0_mode - ldr pmc, .pmc_base -@@ -503,7 +552,7 @@ ENDPROC(at91_backup_mode) - 2: - .endm - --ENTRY(at91_ulp_mode) -+.macro at91_ulp_mode - ldr pmc, .pmc_base - ldr tmp2, .mckr_offset - ldr tmp3, .pm_mode -@@ -552,133 +601,97 @@ ulp_exit: - - wait_mckrdy - -- mov pc, lr --ENDPROC(at91_ulp_mode) -- --/* -- * void at91_sramc_self_refresh(unsigned int is_active) -- * -- * @input param: -- * @r0: 1 - active self-refresh mode -- * 0 - exit self-refresh mode -- * register usage: -- * @r1: memory type -- * @r2: base address of the sram controller -- */ -- --ENTRY(at91_sramc_self_refresh) -- ldr r1, .memtype -- ldr r2, .sramc_base -- -- cmp r1, #AT91_MEMCTRL_MC -- bne ddrc_sf -- -- /* -- * at91rm9200 Memory controller -- */ -- -- /* -- * For exiting the self-refresh mode, do nothing, -- * automatically exit the self-refresh mode. -- */ -- tst r0, #SRAMC_SELF_FRESH_ACTIVE -- beq exit_sramc_sf -- -- /* Active SDRAM self-refresh mode */ -- mov r3, #1 -- str r3, [r2, #AT91_MC_SDRAMC_SRR] -- b exit_sramc_sf -- --ddrc_sf: -- cmp r1, #AT91_MEMCTRL_DDRSDR -- bne sdramc_sf -+.endm - -- /* -- * DDR Memory controller -- */ -- tst r0, #SRAMC_SELF_FRESH_ACTIVE -- beq ddrc_exit_sf -+.macro at91_backup_mode -+ /* Switch the master clock source to slow clock. */ -+ ldr pmc, .pmc_base -+ ldr tmp2, .mckr_offset -+ ldr tmp1, [pmc, tmp2] -+ bic tmp1, tmp1, #AT91_PMC_CSS -+ str tmp1, [pmc, tmp2] - -- /* LPDDR1 --> force DDR2 mode during self-refresh */ -- ldr r3, [r2, #AT91_DDRSDRC_MDR] -- str r3, .saved_sam9_mdr -- bic r3, r3, #~AT91_DDRSDRC_MD -- cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR -- ldreq r3, [r2, #AT91_DDRSDRC_MDR] -- biceq r3, r3, #AT91_DDRSDRC_MD -- orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 -- streq r3, [r2, #AT91_DDRSDRC_MDR] -+ wait_mckrdy - -- /* Active DDRC self-refresh mode */ -- ldr r3, [r2, #AT91_DDRSDRC_LPR] -- str r3, .saved_sam9_lpr -- bic r3, r3, #AT91_DDRSDRC_LPCB -- orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH -- str r3, [r2, #AT91_DDRSDRC_LPR] -+ /*BUMEN*/ -+ ldr r0, .sfrbu -+ mov tmp1, #0x1 -+ str tmp1, [r0, #0x10] - -- /* If using the 2nd ddr controller */ -- ldr r2, .sramc1_base -- cmp r2, #0 -- beq no_2nd_ddrc -+ /* Shutdown */ -+ ldr r0, .shdwc -+ mov tmp1, #0xA5000000 -+ add tmp1, tmp1, #0x1 -+ str tmp1, [r0, #0] -+.endm - -- ldr r3, [r2, #AT91_DDRSDRC_MDR] -- str r3, .saved_sam9_mdr1 -- bic r3, r3, #~AT91_DDRSDRC_MD -- cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR -- ldreq r3, [r2, #AT91_DDRSDRC_MDR] -- biceq r3, r3, #AT91_DDRSDRC_MD -- orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 -- streq r3, [r2, #AT91_DDRSDRC_MDR] -+/* -+ * void at91_suspend_sram_fn(struct at91_pm_data*) -+ * @input param: -+ * @r0: base address of struct at91_pm_data -+ */ -+/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ -+ .align 3 -+ENTRY(at91_pm_suspend_in_sram) -+ /* Save registers on stack */ -+ stmfd sp!, {r4 - r12, lr} - -- /* Active DDRC self-refresh mode */ -- ldr r3, [r2, #AT91_DDRSDRC_LPR] -- str r3, .saved_sam9_lpr1 -- bic r3, r3, #AT91_DDRSDRC_LPCB -- orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH -- str r3, [r2, #AT91_DDRSDRC_LPR] -+ /* Drain write buffer */ -+ mov tmp1, #0 -+ mcr p15, 0, tmp1, c7, c10, 4 - --no_2nd_ddrc: -- b exit_sramc_sf -+ ldr tmp1, [r0, #PM_DATA_PMC] -+ str tmp1, .pmc_base -+ ldr tmp1, [r0, #PM_DATA_RAMC0] -+ str tmp1, .sramc_base -+ ldr tmp1, [r0, #PM_DATA_RAMC1] -+ str tmp1, .sramc1_base -+ ldr tmp1, [r0, #PM_DATA_MEMCTRL] -+ str tmp1, .memtype -+ ldr tmp1, [r0, #PM_DATA_MODE] -+ str tmp1, .pm_mode -+ ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] -+ str tmp1, .mckr_offset -+ ldr tmp1, [r0, #PM_DATA_PMC_VERSION] -+ str tmp1, .pmc_version -+ /* Both ldrne below are here to preload their address in the TLB */ -+ ldr tmp1, [r0, #PM_DATA_SHDWC] -+ str tmp1, .shdwc -+ cmp tmp1, #0 -+ ldrne tmp2, [tmp1, #0] -+ ldr tmp1, [r0, #PM_DATA_SFRBU] -+ str tmp1, .sfrbu -+ cmp tmp1, #0 -+ ldrne tmp2, [tmp1, #0x10] - --ddrc_exit_sf: -- /* Restore MDR in case of LPDDR1 */ -- ldr r3, .saved_sam9_mdr -- str r3, [r2, #AT91_DDRSDRC_MDR] -- /* Restore LPR on AT91 with DDRAM */ -- ldr r3, .saved_sam9_lpr -- str r3, [r2, #AT91_DDRSDRC_LPR] -+ /* Active the self-refresh mode */ -+ at91_sramc_self_refresh_ena - -- /* If using the 2nd ddr controller */ -- ldr r2, .sramc1_base -- cmp r2, #0 -- ldrne r3, .saved_sam9_mdr1 -- strne r3, [r2, #AT91_DDRSDRC_MDR] -- ldrne r3, .saved_sam9_lpr1 -- strne r3, [r2, #AT91_DDRSDRC_LPR] -+ ldr r0, .pm_mode -+ cmp r0, #AT91_PM_STANDBY -+ beq standby -+ cmp r0, #AT91_PM_BACKUP -+ beq backup_mode - -- b exit_sramc_sf -+ at91_ulp_mode -+ b exit_suspend - -- /* -- * SDRAMC Memory controller -- */ --sdramc_sf: -- tst r0, #SRAMC_SELF_FRESH_ACTIVE -- beq sdramc_exit_sf -+standby: -+ /* Wait for interrupt */ -+ ldr pmc, .pmc_base -+ at91_cpu_idle -+ b exit_suspend - -- /* Active SDRAMC self-refresh mode */ -- ldr r3, [r2, #AT91_SDRAMC_LPR] -- str r3, .saved_sam9_lpr -- bic r3, r3, #AT91_SDRAMC_LPCB -- orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH -- str r3, [r2, #AT91_SDRAMC_LPR] -+backup_mode: -+ at91_backup_mode - --sdramc_exit_sf: -- ldr r3, .saved_sam9_lpr -- str r3, [r2, #AT91_SDRAMC_LPR] -+exit_suspend: -+ /* Exit the self-refresh mode */ -+ at91_sramc_self_refresh_dis - --exit_sramc_sf: -- mov pc, lr --ENDPROC(at91_sramc_self_refresh) -+ /* Restore registers, and return */ -+ ldmfd sp!, {r4 - r12, pc} -+ENDPROC(at91_pm_suspend_in_sram) - - .pmc_base: - .word 0 diff --git a/target/linux/at91/patches-5.15/204-ARM-at91-pm-s-CONFIG_SOC_SAM9X60-CONFIG_HAVE_AT91_SA.patch b/target/linux/at91/patches-5.15/204-ARM-at91-pm-s-CONFIG_SOC_SAM9X60-CONFIG_HAVE_AT91_SA.patch deleted file mode 100644 index 4601d922d6..0000000000 --- a/target/linux/at91/patches-5.15/204-ARM-at91-pm-s-CONFIG_SOC_SAM9X60-CONFIG_HAVE_AT91_SA.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 673d2519e9028dafb678fac29a990740958bed3c Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:54 +0300 -Subject: [PATCH 204/247] ARM: at91: pm: - s/CONFIG_SOC_SAM9X60/CONFIG_HAVE_AT91_SAM9X60_PLL/g - -Replace CONFIG_SOC_SAM9X60 with CONFIG_HAVE_AT91_SAM9X60_PLL as the -SAM9X60's PLL is also present on SAMA7G5. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-9-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -422,7 +422,7 @@ sr_dis_exit: - cmp tmp1, #AT91_PMC_V1 - beq 1f - --#ifdef CONFIG_SOC_SAM9X60 -+#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL - /* Save PLLA settings. */ - ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT] - bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID -@@ -489,7 +489,7 @@ sr_dis_exit: - cmp tmp3, #AT91_PMC_V1 - beq 4f - --#ifdef CONFIG_SOC_SAM9X60 -+#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL - /* step 1. */ - ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] - bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID diff --git a/target/linux/at91/patches-5.15/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch b/target/linux/at91/patches-5.15/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch deleted file mode 100644 index 16e733727f..0000000000 --- a/target/linux/at91/patches-5.15/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch +++ /dev/null @@ -1,150 +0,0 @@ -From 67face049c62cb37cf93da26b7fea037228d1d3d Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:55 +0300 -Subject: [PATCH 205/247] ARM: at91: pm: add support for waiting MCK1..4 - -SAMA7G5 has 5 master clocks 0..4. MCK0 is controlled differently than -MCK 1..4. MCK 1..4 should also be saved/restored in the last phase of -suspend/resume. Thus, adapt wait_mckrdy to support also MCK1..4. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-10-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 48 ++++++++++++++++++++++++--------- - 1 file changed, 35 insertions(+), 13 deletions(-) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -22,11 +22,23 @@ tmp3 .req r6 - - /* - * Wait until master clock is ready (after switching master clock source) -+ * -+ * @r_mckid: register holding master clock identifier -+ * -+ * Side effects: overwrites r7, r8 - */ -- .macro wait_mckrdy --1: ldr tmp1, [pmc, #AT91_PMC_SR] -- tst tmp1, #AT91_PMC_MCKRDY -- beq 1b -+ .macro wait_mckrdy r_mckid -+#ifdef CONFIG_SOC_SAMA7 -+ cmp \r_mckid, #0 -+ beq 1f -+ mov r7, #AT91_PMC_MCKXRDY -+ b 2f -+#endif -+1: mov r7, #AT91_PMC_MCKRDY -+2: ldr r8, [pmc, #AT91_PMC_SR] -+ and r8, r7 -+ cmp r8, r7 -+ bne 2b - .endm - - /* -@@ -231,7 +243,9 @@ sr_dis_exit: - bic tmp1, tmp1, #AT91_PMC_PRES - orr tmp1, tmp1, #AT91_PMC_PRES_64 - str tmp1, [pmc, tmp3] -- wait_mckrdy -+ -+ mov tmp3, #0 -+ wait_mckrdy tmp3 - b 1f - - 0: -@@ -267,10 +281,13 @@ sr_dis_exit: - bne 5f - - /* Set lowest prescaler for fast resume. */ -+ ldr tmp3, .mckr_offset - ldr tmp1, [pmc, tmp3] - bic tmp1, tmp1, #AT91_PMC_PRES - str tmp1, [pmc, tmp3] -- wait_mckrdy -+ -+ mov tmp3, #0 -+ wait_mckrdy tmp3 - b 6f - - 5: /* Restore RC oscillator state */ -@@ -307,6 +324,7 @@ sr_dis_exit: - .macro at91_pm_ulp1_mode - ldr pmc, .pmc_base - ldr tmp2, .mckr_offset -+ mov tmp3, #0 - - /* Save RC oscillator state and check if it is enabled. */ - ldr tmp1, [pmc, #AT91_PMC_SR] -@@ -348,7 +366,7 @@ sr_dis_exit: - orr tmp1, tmp1, #AT91_PMC_CSS_MAIN - str tmp1, [pmc, tmp2] - -- wait_mckrdy -+ wait_mckrdy tmp3 - - /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] -@@ -361,7 +379,7 @@ sr_dis_exit: - nop - nop - -- wait_mckrdy -+ wait_mckrdy tmp3 - - /* Enable the crystal oscillator */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] -@@ -377,7 +395,7 @@ sr_dis_exit: - bic tmp1, tmp1, #AT91_PMC_CSS - str tmp1, [pmc, tmp2] - -- wait_mckrdy -+ wait_mckrdy tmp3 - - /* Switch main clock source to crystal oscillator */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] -@@ -394,7 +412,7 @@ sr_dis_exit: - orr tmp1, tmp1, #AT91_PMC_CSS_MAIN - str tmp1, [pmc, tmp2] - -- wait_mckrdy -+ wait_mckrdy tmp3 - - /* Restore RC oscillator state */ - ldr tmp1, .saved_osc_status -@@ -573,10 +591,12 @@ sr_dis_exit: - save_mck: - str tmp1, [pmc, tmp2] - -- wait_mckrdy -+ mov tmp3, #0 -+ wait_mckrdy tmp3 - - at91_plla_disable - -+ ldr tmp3, .pm_mode - cmp tmp3, #AT91_PM_ULP1 - beq ulp1_mode - -@@ -599,7 +619,8 @@ ulp_exit: - ldr tmp2, .saved_mckr - str tmp2, [pmc, tmp1] - -- wait_mckrdy -+ mov tmp3, #0 -+ wait_mckrdy tmp3 - - .endm - -@@ -611,7 +632,8 @@ ulp_exit: - bic tmp1, tmp1, #AT91_PMC_CSS - str tmp1, [pmc, tmp2] - -- wait_mckrdy -+ mov tmp3, #0 -+ wait_mckrdy tmp3 - - /*BUMEN*/ - ldr r0, .sfrbu diff --git a/target/linux/at91/patches-5.15/206-ARM-at91-sfrbu-add-sfrbu-registers-definitions-for-s.patch b/target/linux/at91/patches-5.15/206-ARM-at91-sfrbu-add-sfrbu-registers-definitions-for-s.patch deleted file mode 100644 index 37a22885d7..0000000000 --- a/target/linux/at91/patches-5.15/206-ARM-at91-sfrbu-add-sfrbu-registers-definitions-for-s.patch +++ /dev/null @@ -1,53 +0,0 @@ -From c6b435625975d9a6daeffd81509a9877ddfb93b5 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:56 +0300 -Subject: [PATCH 206/247] ARM: at91: sfrbu: add sfrbu registers definitions for - sama7g5 - -Add SFRBU registers definitions for SAMA7G5. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-11-claudiu.beznea@microchip.com ---- - include/soc/at91/sama7-sfrbu.h | 34 ++++++++++++++++++++++++++++++++++ - 1 file changed, 34 insertions(+) - create mode 100644 include/soc/at91/sama7-sfrbu.h - ---- /dev/null -+++ b/include/soc/at91/sama7-sfrbu.h -@@ -0,0 +1,34 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Microchip SAMA7 SFRBU registers offsets and bit definitions. -+ * -+ * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries -+ * -+ * Author: Claudu Beznea -+ */ -+ -+#ifndef __SAMA7_SFRBU_H__ -+#define __SAMA7_SFRBU_H__ -+ -+#ifdef CONFIG_SOC_SAMA7 -+ -+#define AT91_SFRBU_PSWBU (0x00) /* SFRBU Power Switch BU Control Register */ -+#define AT91_SFRBU_PSWBU_PSWKEY (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */ -+#define AT91_SFRBU_PSWBU_STATE (1 << 2) /* Power switch BU state */ -+#define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */ -+#define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */ -+ -+#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */ -+#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */ -+#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */ -+#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */ -+#define AT91_SFRBU_PD_VALUE_MSK (0x3) -+#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */ -+ -+#define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */ -+#define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */ -+ -+#endif /* CONFIG_SOC_SAMA7 */ -+ -+#endif /* __SAMA7_SFRBU_H__ */ -+ diff --git a/target/linux/at91/patches-5.15/207-ARM-at91-ddr-add-registers-definitions-for-sama7g5-s.patch b/target/linux/at91/patches-5.15/207-ARM-at91-ddr-add-registers-definitions-for-sama7g5-s.patch deleted file mode 100644 index 1df310f216..0000000000 --- a/target/linux/at91/patches-5.15/207-ARM-at91-ddr-add-registers-definitions-for-sama7g5-s.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 0005be9abfcddf9a29c6d07afe06caa41560d424 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:57 +0300 -Subject: [PATCH 207/247] ARM: at91: ddr: add registers definitions for - sama7g5's ddr - -Add registers and bits definitions for SAMA7G5's UDDRC and DDR3PHY. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-12-claudiu.beznea@microchip.com ---- - include/soc/at91/sama7-ddr.h | 80 ++++++++++++++++++++++++++++++++++++ - 1 file changed, 80 insertions(+) - create mode 100644 include/soc/at91/sama7-ddr.h - ---- /dev/null -+++ b/include/soc/at91/sama7-ddr.h -@@ -0,0 +1,80 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Microchip SAMA7 UDDR Controller and DDR3 PHY Controller registers offsets -+ * and bit definitions. -+ * -+ * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries -+ * -+ * Author: Claudu Beznea -+ */ -+ -+#ifndef __SAMA7_DDR_H__ -+#define __SAMA7_DDR_H__ -+ -+#ifdef CONFIG_SOC_SAMA7 -+ -+/* DDR3PHY */ -+#define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */ -+#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */ -+#define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */ -+#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */ -+#define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */ -+#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */ -+ -+#define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */ -+#define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */ -+#define DDR3PHY_PGCR_CKDV0 (1 << 12) /* CK Disable Value */ -+ -+#define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */ -+#define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */ -+ -+#define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */ -+#define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */ -+#define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */ -+#define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */ -+ -+#define DDR3PHY_DXCCR (0x28) /* DDR3PHY DATX8 Common Configuration Register */ -+#define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */ -+ -+#define DDR3PHY_DSGCR (0x2C) /* DDR3PHY DDR System General Configuration Register */ -+#define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */ -+ -+#define DDR3PHY_ZQ0SR0 (0x188) /* ZQ status register 0 */ -+ -+/* UDDRC */ -+#define UDDRC_STAT (0x04) /* UDDRC Operating Mode Status Register */ -+#define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */ -+#define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PHY Master Request */ -+#define UDDRC_STAT_SELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automatic Self-refresh control */ -+#define UDDRC_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self-refresh only */ -+#define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */ -+#define UDDRC_STAT_OPMODE_INIT (0x0 << 0) /* Init */ -+#define UDDRC_STAT_OPMODE_NORMAL (0x1 << 0) /* Normal */ -+#define UDDRC_STAT_OPMODE_PWRDOWN (0x2 << 0) /* Power-down */ -+#define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */ -+#define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */ -+ -+#define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */ -+#define UDDRC_PWRCTRL_SELFREF_SW (1 << 5) /* Software self-refresh */ -+ -+#define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */ -+#define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */ -+ -+#define UDDRC_SWCTRL (0x320) /* UDDRC Software Register Programming Control Enable */ -+#define UDDRC_SWCTRL_SW_DONE (1 << 0) /* Enable quasi-dynamic register programming outside reset */ -+ -+#define UDDRC_SWSTAT (0x324) /* UDDRC Software Register Programming Control Status */ -+#define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */ -+ -+#define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */ -+#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */ -+ -+#define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */ -+#define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */ -+#define UDDRC_PCTRL_2 (0x5F0) /* UDDRC Port 2 Control Register */ -+#define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */ -+#define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */ -+ -+#endif /* CONFIG_SOC_SAMA7 */ -+ -+#endif /* __SAMA7_DDR_H__ */ diff --git a/target/linux/at91/patches-5.15/208-ARM-at91-pm-add-self-refresh-support-for-sama7g5.patch b/target/linux/at91/patches-5.15/208-ARM-at91-pm-add-self-refresh-support-for-sama7g5.patch deleted file mode 100644 index f8321e5042..0000000000 --- a/target/linux/at91/patches-5.15/208-ARM-at91-pm-add-self-refresh-support-for-sama7g5.patch +++ /dev/null @@ -1,274 +0,0 @@ -From 1bfd85d71703f80392a71043caf74f159bec97b8 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:58 +0300 -Subject: [PATCH 208/247] ARM: at91: pm: add self-refresh support for sama7g5 - -Add self-refresh support for SAMA7G5. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-13-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.h | 2 + - arch/arm/mach-at91/pm_data-offsets.c | 2 + - arch/arm/mach-at91/pm_suspend.S | 199 +++++++++++++++++++++++++++ - 3 files changed, 203 insertions(+) - ---- a/arch/arm/mach-at91/pm.h -+++ b/arch/arm/mach-at91/pm.h -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - - #define AT91_MEMCTRL_MC 0 - #define AT91_MEMCTRL_SDRAMC 1 -@@ -27,6 +28,7 @@ - struct at91_pm_data { - void __iomem *pmc; - void __iomem *ramc[2]; -+ void __iomem *ramc_phy; - unsigned long uhp_udp_mask; - unsigned int memctrl; - unsigned int mode; ---- a/arch/arm/mach-at91/pm_data-offsets.c -+++ b/arch/arm/mach-at91/pm_data-offsets.c -@@ -8,6 +8,8 @@ int main(void) - DEFINE(PM_DATA_PMC, offsetof(struct at91_pm_data, pmc)); - DEFINE(PM_DATA_RAMC0, offsetof(struct at91_pm_data, ramc[0])); - DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1])); -+ DEFINE(PM_DATA_RAMC_PHY, offsetof(struct at91_pm_data, -+ ramc_phy)); - DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl)); - DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode)); - DEFINE(PM_DATA_SHDWC, offsetof(struct at91_pm_data, shdwc)); ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -87,6 +87,200 @@ tmp3 .req r6 - - .arm - -+#ifdef CONFIG_SOC_SAMA7 -+/** -+ * Enable self-refresh -+ * -+ * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3, r7 -+ */ -+.macro at91_sramc_self_refresh_ena -+ ldr r2, .sramc_base -+ ldr r3, .sramc_phy_base -+ ldr r7, .pm_mode -+ -+ dsb -+ -+ /* Disable all AXI ports. */ -+ ldr tmp1, [r2, #UDDRC_PCTRL_0] -+ bic tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_0] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_1] -+ bic tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_1] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_2] -+ bic tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_2] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_3] -+ bic tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_3] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_4] -+ bic tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_4] -+ -+sr_ena_1: -+ /* Wait for all ports to disable. */ -+ ldr tmp1, [r2, #UDDRC_PSTAT] -+ ldr tmp2, =UDDRC_PSTAT_ALL_PORTS -+ tst tmp1, tmp2 -+ bne sr_ena_1 -+ -+ /* Switch to self-refresh. */ -+ ldr tmp1, [r2, #UDDRC_PWRCTL] -+ orr tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW -+ str tmp1, [r2, #UDDRC_PWRCTL] -+ -+sr_ena_2: -+ /* Wait for self-refresh enter. */ -+ ldr tmp1, [r2, #UDDRC_STAT] -+ bic tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK -+ cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW -+ bne sr_ena_2 -+ -+ /* Put DDR PHY's DLL in bypass mode for non-backup modes. */ -+ cmp r7, #AT91_PM_BACKUP -+ beq sr_ena_3 -+ ldr tmp1, [r3, #DDR3PHY_PIR] -+ orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP -+ str tmp1, [r3, #DDR3PHY_PIR] -+ -+sr_ena_3: -+ /* Power down DDR PHY data receivers. */ -+ ldr tmp1, [r3, #DDR3PHY_DXCCR] -+ orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR -+ str tmp1, [r3, #DDR3PHY_DXCCR] -+ -+ /* Power down ADDR/CMD IO. */ -+ ldr tmp1, [r3, #DDR3PHY_ACIOCR] -+ orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD -+ orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0 -+ orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0 -+ str tmp1, [r3, #DDR3PHY_ACIOCR] -+ -+ /* Power down ODT. */ -+ ldr tmp1, [r3, #DDR3PHY_DSGCR] -+ orr tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0 -+ str tmp1, [r3, #DDR3PHY_DSGCR] -+.endm -+ -+/** -+ * Disable self-refresh -+ * -+ * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3 -+ */ -+.macro at91_sramc_self_refresh_dis -+ ldr r2, .sramc_base -+ ldr r3, .sramc_phy_base -+ -+ /* Power up DDR PHY data receivers. */ -+ ldr tmp1, [r3, #DDR3PHY_DXCCR] -+ bic tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR -+ str tmp1, [r3, #DDR3PHY_DXCCR] -+ -+ /* Power up the output of CK and CS pins. */ -+ ldr tmp1, [r3, #DDR3PHY_ACIOCR] -+ bic tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD -+ bic tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0 -+ bic tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0 -+ str tmp1, [r3, #DDR3PHY_ACIOCR] -+ -+ /* Power up ODT. */ -+ ldr tmp1, [r3, #DDR3PHY_DSGCR] -+ bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0 -+ str tmp1, [r3, #DDR3PHY_DSGCR] -+ -+ /* Take DDR PHY's DLL out of bypass mode. */ -+ ldr tmp1, [r3, #DDR3PHY_PIR] -+ bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP -+ str tmp1, [r3, #DDR3PHY_PIR] -+ -+ /* Enable quasi-dynamic programming. */ -+ mov tmp1, #0 -+ str tmp1, [r2, #UDDRC_SWCTRL] -+ -+ /* De-assert SDRAM initialization. */ -+ ldr tmp1, [r2, #UDDRC_DFIMISC] -+ bic tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN -+ str tmp1, [r2, #UDDRC_DFIMISC] -+ -+ /* Quasi-dynamic programming done. */ -+ mov tmp1, #UDDRC_SWCTRL_SW_DONE -+ str tmp1, [r2, #UDDRC_SWCTRL] -+ -+sr_dis_1: -+ ldr tmp1, [r2, #UDDRC_SWSTAT] -+ tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK -+ beq sr_dis_1 -+ -+ /* DLL soft-reset + DLL lock wait + ITM reset */ -+ mov tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \ -+ DDR3PHY_PIR_DLLLOCK | DDR3PHY_PIR_ITMSRST) -+ str tmp1, [r3, #DDR3PHY_PIR] -+ -+sr_dis_4: -+ /* Wait for it. */ -+ ldr tmp1, [r3, #DDR3PHY_PGSR] -+ tst tmp1, #DDR3PHY_PGSR_IDONE -+ beq sr_dis_4 -+ -+ /* Enable quasi-dynamic programming. */ -+ mov tmp1, #0 -+ str tmp1, [r2, #UDDRC_SWCTRL] -+ -+ /* Assert PHY init complete enable signal. */ -+ ldr tmp1, [r2, #UDDRC_DFIMISC] -+ orr tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN -+ str tmp1, [r2, #UDDRC_DFIMISC] -+ -+ /* Programming is done. Set sw_done. */ -+ mov tmp1, #UDDRC_SWCTRL_SW_DONE -+ str tmp1, [r2, #UDDRC_SWCTRL] -+ -+sr_dis_5: -+ /* Wait for it. */ -+ ldr tmp1, [r2, #UDDRC_SWSTAT] -+ tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK -+ beq sr_dis_5 -+ -+ /* Trigger self-refresh exit. */ -+ ldr tmp1, [r2, #UDDRC_PWRCTL] -+ bic tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW -+ str tmp1, [r2, #UDDRC_PWRCTL] -+ -+sr_dis_6: -+ /* Wait for self-refresh exit done. */ -+ ldr tmp1, [r2, #UDDRC_STAT] -+ bic tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK -+ cmp tmp1, #UDDRC_STAT_OPMODE_NORMAL -+ bne sr_dis_6 -+ -+ /* Enable all AXI ports. */ -+ ldr tmp1, [r2, #UDDRC_PCTRL_0] -+ orr tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_0] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_1] -+ orr tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_1] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_2] -+ orr tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_2] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_3] -+ orr tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_3] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_4] -+ orr tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_4] -+ -+ dsb -+.endm -+#else - /** - * Enable self-refresh - * -@@ -228,6 +422,7 @@ sdramc_exit_sf: - - sr_dis_exit: - .endm -+#endif - - .macro at91_pm_ulp0_mode - ldr pmc, .pmc_base -@@ -668,6 +863,8 @@ ENTRY(at91_pm_suspend_in_sram) - str tmp1, .sramc_base - ldr tmp1, [r0, #PM_DATA_RAMC1] - str tmp1, .sramc1_base -+ ldr tmp1, [r0, #PM_DATA_RAMC_PHY] -+ str tmp1, .sramc_phy_base - ldr tmp1, [r0, #PM_DATA_MEMCTRL] - str tmp1, .memtype - ldr tmp1, [r0, #PM_DATA_MODE] -@@ -721,6 +918,8 @@ ENDPROC(at91_pm_suspend_in_sram) - .word 0 - .sramc1_base: - .word 0 -+.sramc_phy_base: -+ .word 0 - .shdwc: - .word 0 - .sfrbu: diff --git a/target/linux/at91/patches-5.15/209-ARM-at91-pm-add-support-for-MCK1.4-save-restore-for-.patch b/target/linux/at91/patches-5.15/209-ARM-at91-pm-add-support-for-MCK1.4-save-restore-for-.patch deleted file mode 100644 index 7c8614125c..0000000000 --- a/target/linux/at91/patches-5.15/209-ARM-at91-pm-add-support-for-MCK1.4-save-restore-for-.patch +++ /dev/null @@ -1,165 +0,0 @@ -From 9ee7fd7aa956671727752dac6bd131cf511c1137 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:59 +0300 -Subject: [PATCH 209/247] ARM: at91: pm: add support for MCK1..4 save/restore - for ulp modes - -Add support for MCK1..4 save restore for ULP modes. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-14-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 126 ++++++++++++++++++++++++++++++++ - 1 file changed, 126 insertions(+) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -765,7 +765,122 @@ sr_dis_exit: - 2: - .endm - -+/** -+ * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock -+ * -+ * Side effects: overwrites tmp1, tmp2 -+ */ -+.macro at91_mckx_ps_enable -+#ifdef CONFIG_SOC_SAMA7 -+ ldr pmc, .pmc_base -+ -+ /* There are 4 MCKs we need to handle: MCK1..4 */ -+ mov tmp1, #1 -+e_loop: cmp tmp1, #5 -+ beq e_done -+ -+ /* Write MCK ID to retrieve the settings. */ -+ str tmp1, [pmc, #AT91_PMC_MCR_V2] -+ ldr tmp2, [pmc, #AT91_PMC_MCR_V2] -+ -+e_save_mck1: -+ cmp tmp1, #1 -+ bne e_save_mck2 -+ str tmp2, .saved_mck1 -+ b e_ps -+ -+e_save_mck2: -+ cmp tmp1, #2 -+ bne e_save_mck3 -+ str tmp2, .saved_mck2 -+ b e_ps -+ -+e_save_mck3: -+ cmp tmp1, #3 -+ bne e_save_mck4 -+ str tmp2, .saved_mck3 -+ b e_ps -+ -+e_save_mck4: -+ str tmp2, .saved_mck4 -+ -+e_ps: -+ /* Use CSS=MAINCK and DIV=1. */ -+ bic tmp2, tmp2, #AT91_PMC_MCR_V2_CSS -+ bic tmp2, tmp2, #AT91_PMC_MCR_V2_DIV -+ orr tmp2, tmp2, #AT91_PMC_MCR_V2_CSS_MAINCK -+ orr tmp2, tmp2, #AT91_PMC_MCR_V2_DIV1 -+ str tmp2, [pmc, #AT91_PMC_MCR_V2] -+ -+ wait_mckrdy tmp1 -+ -+ add tmp1, tmp1, #1 -+ b e_loop -+ -+e_done: -+#endif -+.endm -+ -+/** -+ * at91_mckx_ps_restore: restore MCK1..4 settings -+ * -+ * Side effects: overwrites tmp1, tmp2 -+ */ -+.macro at91_mckx_ps_restore -+#ifdef CONFIG_SOC_SAMA7 -+ ldr pmc, .pmc_base -+ -+ /* There are 4 MCKs we need to handle: MCK1..4 */ -+ mov tmp1, #1 -+r_loop: cmp tmp1, #5 -+ beq r_done -+ -+r_save_mck1: -+ cmp tmp1, #1 -+ bne r_save_mck2 -+ ldr tmp2, .saved_mck1 -+ b r_ps -+ -+r_save_mck2: -+ cmp tmp1, #2 -+ bne r_save_mck3 -+ ldr tmp2, .saved_mck2 -+ b r_ps -+ -+r_save_mck3: -+ cmp tmp1, #3 -+ bne r_save_mck4 -+ ldr tmp2, .saved_mck3 -+ b r_ps -+ -+r_save_mck4: -+ ldr tmp2, .saved_mck4 -+ -+r_ps: -+ /* Write MCK ID to retrieve the settings. */ -+ str tmp1, [pmc, #AT91_PMC_MCR_V2] -+ ldr tmp3, [pmc, #AT91_PMC_MCR_V2] -+ -+ /* We need to restore CSS and DIV. */ -+ bic tmp3, tmp3, #AT91_PMC_MCR_V2_CSS -+ bic tmp3, tmp3, #AT91_PMC_MCR_V2_DIV -+ orr tmp3, tmp3, tmp2 -+ bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK -+ orr tmp3, tmp3, tmp1 -+ orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD -+ str tmp2, [pmc, #AT91_PMC_MCR_V2] -+ -+ wait_mckrdy tmp1 -+ -+ add tmp1, tmp1, #1 -+ b r_loop -+r_done: -+#endif -+.endm -+ - .macro at91_ulp_mode -+ at91_mckx_ps_enable -+ - ldr pmc, .pmc_base - ldr tmp2, .mckr_offset - ldr tmp3, .pm_mode -@@ -817,6 +932,7 @@ ulp_exit: - mov tmp3, #0 - wait_mckrdy tmp3 - -+ at91_mckx_ps_restore - .endm - - .macro at91_backup_mode -@@ -946,6 +1062,16 @@ ENDPROC(at91_pm_suspend_in_sram) - .word 0 - .saved_osc_status: - .word 0 -+#ifdef CONFIG_SOC_SAMA7 -+.saved_mck1: -+ .word 0 -+.saved_mck2: -+ .word 0 -+.saved_mck3: -+ .word 0 -+.saved_mck4: -+ .word 0 -+#endif - - ENTRY(at91_pm_suspend_in_sram_sz) - .word .-at91_pm_suspend_in_sram diff --git a/target/linux/at91/patches-5.15/210-ARM-at91-pm-add-support-for-2.5V-LDO-regulator-contr.patch b/target/linux/at91/patches-5.15/210-ARM-at91-pm-add-support-for-2.5V-LDO-regulator-contr.patch deleted file mode 100644 index ede839bf70..0000000000 --- a/target/linux/at91/patches-5.15/210-ARM-at91-pm-add-support-for-2.5V-LDO-regulator-contr.patch +++ /dev/null @@ -1,79 +0,0 @@ -From b2073cc043612bf95b115bd94103cfb2936f05bf Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:00 +0300 -Subject: [PATCH 210/247] ARM: at91: pm: add support for 2.5V LDO regulator - control - -Add support to disable/enable 2.5V LDO regulator when entering/exiting -any ULP mode. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-15-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.h | 1 + - arch/arm/mach-at91/pm_suspend.S | 29 +++++++++++++++++++++++++++++ - 2 files changed, 30 insertions(+) - ---- a/arch/arm/mach-at91/pm.h -+++ b/arch/arm/mach-at91/pm.h -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - - #define AT91_MEMCTRL_MC 0 - #define AT91_MEMCTRL_SDRAMC 1 ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -83,6 +83,29 @@ tmp3 .req r6 - - .endm - -+/** -+ * Set state for 2.5V low power regulator -+ * @ena: 0 - disable regulator -+ * 1 - enable regulator -+ * -+ * Side effects: overwrites r7, r8, r9, r10 -+ */ -+ .macro at91_2_5V_reg_set_low_power ena -+#ifdef CONFIG_SOC_SAMA7 -+ ldr r7, .sfrbu -+ mov r8, #\ena -+ ldr r9, [r7, #AT91_SFRBU_25LDOCR] -+ orr r9, r9, #AT91_SFRBU_25LDOCR_LP -+ cmp r8, #1 -+ beq lp_done_\ena -+ bic r9, r9, #AT91_SFRBU_25LDOCR_LP -+lp_done_\ena: -+ ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY -+ orr r9, r9, r10 -+ str r9, [r7, #AT91_SFRBU_25LDOCR] -+#endif -+ .endm -+ - .text - - .arm -@@ -906,6 +929,9 @@ save_mck: - - at91_plla_disable - -+ /* Enable low power mode for 2.5V regulator. */ -+ at91_2_5V_reg_set_low_power 1 -+ - ldr tmp3, .pm_mode - cmp tmp3, #AT91_PM_ULP1 - beq ulp1_mode -@@ -918,6 +944,9 @@ ulp1_mode: - b ulp_exit - - ulp_exit: -+ /* Disable low power mode for 2.5V regulator. */ -+ at91_2_5V_reg_set_low_power 0 -+ - ldr pmc, .pmc_base - - at91_plla_enable diff --git a/target/linux/at91/patches-5.15/211-ARM-at91-pm-wait-for-ddr-power-mode-off.patch b/target/linux/at91/patches-5.15/211-ARM-at91-pm-wait-for-ddr-power-mode-off.patch deleted file mode 100644 index 886f81e7ad..0000000000 --- a/target/linux/at91/patches-5.15/211-ARM-at91-pm-wait-for-ddr-power-mode-off.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 2b522a22243938dd7613e09c954172b1fa6217f5 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:01 +0300 -Subject: [PATCH 211/247] ARM: at91: pm: wait for ddr power mode off - -Wait for DDR power mode off before shutting down the core. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-16-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -980,6 +980,11 @@ ulp_exit: - mov tmp1, #0x1 - str tmp1, [r0, #0x10] - -+ /* Wait for it. */ -+1: ldr tmp1, [r0, #0x10] -+ tst tmp1, #0x1 -+ beq 1b -+ - /* Shutdown */ - ldr r0, .shdwc - mov tmp1, #0xA5000000 diff --git a/target/linux/at91/patches-5.15/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch b/target/linux/at91/patches-5.15/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch deleted file mode 100644 index e496245061..0000000000 --- a/target/linux/at91/patches-5.15/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 3f55310c00b8c478da1458704027036c1a414973 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:03 +0300 -Subject: [PATCH 212/247] ARM: at91: pm: add sama7g5 ddr controller - -Add SAMA7G5 DDR controller to the list of DDR controller compatibles. -At the moment there is no standby support. Adapt the code for this. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -548,6 +548,7 @@ static const struct of_device_id ramc_id - { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, - { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, - { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, -+ { .compatible = "microchip,sama7g5-uddrc", }, - { /*sentinel*/ } - }; - -@@ -569,9 +570,11 @@ static __init int at91_dt_ramc(void) - } - - ramc = of_id->data; -- if (!standby) -- standby = ramc->idle; -- soc_pm.data.memctrl = ramc->memctrl; -+ if (ramc) { -+ if (!standby) -+ standby = ramc->idle; -+ soc_pm.data.memctrl = ramc->memctrl; -+ } - - idx++; - } diff --git a/target/linux/at91/patches-5.15/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch b/target/linux/at91/patches-5.15/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch deleted file mode 100644 index 89dcacec92..0000000000 --- a/target/linux/at91/patches-5.15/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch +++ /dev/null @@ -1,94 +0,0 @@ -From bbbbf16c44f34a2d563fa7d71de64ffe3b4b82dc Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:04 +0300 -Subject: [PATCH 213/247] ARM: at91: pm: add sama7g5 ddr phy controller - -SAMA7G5 self-refresh procedure accesses also the DDR PHY registers. -Adapt the code so that the at91_dt_ramc() to look also for DDR PHYs, -in case it is mandatory. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-19-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 27 +++++++++++++++++++++------ - 1 file changed, 21 insertions(+), 6 deletions(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -552,7 +552,12 @@ static const struct of_device_id ramc_id - { /*sentinel*/ } - }; - --static __init int at91_dt_ramc(void) -+static const struct of_device_id ramc_phy_ids[] __initconst = { -+ { .compatible = "microchip,sama7g5-ddr3phy", }, -+ { /* Sentinel. */ }, -+}; -+ -+static __init void at91_dt_ramc(bool phy_mandatory) - { - struct device_node *np; - const struct of_device_id *of_id; -@@ -585,6 +590,16 @@ static __init int at91_dt_ramc(void) - goto unmap_ramc; - } - -+ /* Lookup for DDR PHY node, if any. */ -+ for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) { -+ soc_pm.data.ramc_phy = of_iomap(np, 0); -+ if (!soc_pm.data.ramc_phy) -+ panic(pr_fmt("unable to map ramc phy cpu registers\n")); -+ } -+ -+ if (phy_mandatory && !soc_pm.data.ramc_phy) -+ panic(pr_fmt("DDR PHY is mandatory!\n")); -+ - if (!standby) { - pr_warn("ramc no standby function available\n"); - return 0; -@@ -953,7 +968,7 @@ void __init at91rm9200_pm_init(void) - soc_pm.data.standby_mode = AT91_PM_STANDBY; - soc_pm.data.suspend_mode = AT91_PM_ULP0; - -- ret = at91_dt_ramc(); -+ ret = at91_dt_ramc(false); - if (ret) - return; - -@@ -980,7 +995,7 @@ void __init sam9x60_pm_init(void) - - at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); - at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); -- ret = at91_dt_ramc(); -+ ret = at91_dt_ramc(false); - if (ret) - return; - -@@ -1005,7 +1020,7 @@ void __init at91sam9_pm_init(void) - soc_pm.data.standby_mode = AT91_PM_STANDBY; - soc_pm.data.suspend_mode = AT91_PM_ULP0; - -- ret = at91_dt_ramc(); -+ ret = at91_dt_ramc(false); - if (ret) - return; - -@@ -1023,7 +1038,7 @@ void __init sama5_pm_init(void) - return; - - at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); -- ret = at91_dt_ramc(); -+ ret = at91_dt_ramc(false); - if (ret) - return; - -@@ -1048,7 +1063,7 @@ void __init sama5d2_pm_init(void) - - at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); - at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); -- ret = at91_dt_ramc(); -+ ret = at91_dt_ramc(false); - if (ret) - return; - diff --git a/target/linux/at91/patches-5.15/214-ARM-at91-pm-save-ddr-phy-calibration-data-to-securam.patch b/target/linux/at91/patches-5.15/214-ARM-at91-pm-save-ddr-phy-calibration-data-to-securam.patch deleted file mode 100644 index a46b5acb22..0000000000 --- a/target/linux/at91/patches-5.15/214-ARM-at91-pm-save-ddr-phy-calibration-data-to-securam.patch +++ /dev/null @@ -1,151 +0,0 @@ -From b355bb98eae3e343969fc5a0203e0dab472a6acd Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:05 +0300 -Subject: [PATCH 214/247] ARM: at91: pm: save ddr phy calibration data to - securam - -The resuming from backup mode is done with the help of bootloader. -The bootloader reconfigure the DDR controller and DDR PHY controller. -To speed-up the resuming process save the PHY calibration data into -SECURAM before suspending (securam is powered on backup mode). -This data will be later used by bootloader in DDR PHY reconfiguration -process. Also, in the process or recalibration the first 8 words of -the memory may get corrupted. To solve this, these 8 words are saved -in the securam and restored by bootloader in the process of PHY -configuration. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-20-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 60 ++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 59 insertions(+), 1 deletion(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -27,18 +28,23 @@ - #include "generic.h" - #include "pm.h" - -+#define BACKUP_DDR_PHY_CALIBRATION (9) -+ - /** - * struct at91_pm_bu - AT91 power management backup unit data structure - * @suspended: true if suspended to backup mode - * @reserved: reserved - * @canary: canary data for memory checking after exit from backup mode - * @resume: resume API -+ * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words -+ * of the memory - */ - struct at91_pm_bu { - int suspended; - unsigned long reserved; - phys_addr_t canary; - phys_addr_t resume; -+ unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; - }; - - /** -@@ -48,6 +54,7 @@ struct at91_pm_bu { - * @ws_ids: wakup sources of_device_id array - * @data: PM data to be used on last phase of suspend - * @bu: backup unit mapped data (for backup mode) -+ * @memcs: memory chip select - */ - struct at91_soc_pm { - int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); -@@ -55,6 +62,7 @@ struct at91_soc_pm { - const struct of_device_id *ws_ids; - struct at91_pm_bu *bu; - struct at91_pm_data data; -+ void *memcs; - }; - - /** -@@ -316,6 +324,19 @@ extern u32 at91_pm_suspend_in_sram_sz; - - static int at91_suspend_finish(unsigned long val) - { -+ int i; -+ -+ if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) { -+ /* -+ * The 1st 8 words of memory might get corrupted in the process -+ * of DDR PHY recalibration; it is saved here in securam and it -+ * will be restored later, after recalibration, by bootloader -+ */ -+ for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++) -+ soc_pm.bu->ddr_phy_calibration[i] = -+ *((unsigned int *)soc_pm.memcs + (i - 1)); -+ } -+ - flush_cache_all(); - outer_disable(); - -@@ -688,12 +709,40 @@ static bool __init at91_is_pm_mode_activ - soc_pm.data.suspend_mode == pm_mode); - } - -+static int __init at91_pm_backup_scan_memcs(unsigned long node, -+ const char *uname, int depth, -+ void *data) -+{ -+ const char *type; -+ const __be32 *reg; -+ int *located = data; -+ int size; -+ -+ /* Memory node already located. */ -+ if (*located) -+ return 0; -+ -+ type = of_get_flat_dt_prop(node, "device_type", NULL); -+ -+ /* We are scanning "memory" nodes only. */ -+ if (!type || strcmp(type, "memory")) -+ return 0; -+ -+ reg = of_get_flat_dt_prop(node, "reg", &size); -+ if (reg) { -+ soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg)); -+ *located = 1; -+ } -+ -+ return 0; -+} -+ - static int __init at91_pm_backup_init(void) - { - struct gen_pool *sram_pool; - struct device_node *np; - struct platform_device *pdev; -- int ret = -ENODEV; -+ int ret = -ENODEV, located = 0; - - if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) - return -EPERM; -@@ -728,6 +777,15 @@ static int __init at91_pm_backup_init(vo - soc_pm.bu->suspended = 0; - soc_pm.bu->canary = __pa_symbol(&canary); - soc_pm.bu->resume = __pa_symbol(cpu_resume); -+ if (soc_pm.data.ramc_phy) { -+ of_scan_flat_dt(at91_pm_backup_scan_memcs, &located); -+ if (!located) -+ goto securam_fail; -+ -+ /* DDR3PHY_ZQ0SR0 */ -+ soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy + -+ 0x188); -+ } - - return 0; - diff --git a/target/linux/at91/patches-5.15/215-ARM-at91-pm-add-backup-mode-support-for-SAMA7G5.patch b/target/linux/at91/patches-5.15/215-ARM-at91-pm-add-backup-mode-support-for-SAMA7G5.patch deleted file mode 100644 index cc5f4aec0a..0000000000 --- a/target/linux/at91/patches-5.15/215-ARM-at91-pm-add-backup-mode-support-for-SAMA7G5.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 62be32b56ff31b2cd048a53fac40a165c5bc66cd Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:06 +0300 -Subject: [PATCH 215/247] ARM: at91: pm: add backup mode support for SAMA7G5 - -Adapt at91_pm_backup_init() to work for SAMA7G5. Also, set the LPM pin -to shutdown controller. This will signal to PMIC that it needs to switch -to the state corresponding to backup mode. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-21-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 3 ++- - arch/arm/mach-at91/pm_suspend.S | 7 +++++++ - 2 files changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -744,7 +744,8 @@ static int __init at91_pm_backup_init(vo - struct platform_device *pdev; - int ret = -ENODEV, located = 0; - -- if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) -+ if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && -+ !IS_ENABLED(CONFIG_SOC_SAMA7G5)) - return -EPERM; - - if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -106,6 +106,12 @@ lp_done_\ena: - #endif - .endm - -+ .macro at91_backup_set_lpm reg -+#ifdef CONFIG_SOC_SAMA7 -+ orr \reg, \reg, #0x200000 -+#endif -+ .endm -+ - .text - - .arm -@@ -989,6 +995,7 @@ ulp_exit: - ldr r0, .shdwc - mov tmp1, #0xA5000000 - add tmp1, tmp1, #0x1 -+ at91_backup_set_lpm tmp1 - str tmp1, [r0, #0] - .endm - diff --git a/target/linux/at91/patches-5.15/216-ARM-at91-pm-add-sama7g5-s-pmc.patch b/target/linux/at91/patches-5.15/216-ARM-at91-pm-add-sama7g5-s-pmc.patch deleted file mode 100644 index a471195fbc..0000000000 --- a/target/linux/at91/patches-5.15/216-ARM-at91-pm-add-sama7g5-s-pmc.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e9855ac00e8d9a2c41cea42b4f38a2b0b010bef3 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:07 +0300 -Subject: [PATCH 216/247] ARM: at91: pm: add sama7g5's pmc - -Add SAMA7G5's PMC to compatible list. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-22-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -912,6 +912,11 @@ static const struct pmc_info pmc_infos[] - .mckr = 0x28, - .version = AT91_PMC_V2, - }, -+ { -+ .mckr = 0x28, -+ .version = AT91_PMC_V2, -+ }, -+ - }; - - static const struct of_device_id atmel_pmc_ids[] __initconst = { -@@ -927,6 +932,7 @@ static const struct of_device_id atmel_p - { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, - { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, - { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, -+ { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, - { /* sentinel */ }, - }; - diff --git a/target/linux/at91/patches-5.15/217-ARM-at91-sama7-introduce-sama7-SoC-family.patch b/target/linux/at91/patches-5.15/217-ARM-at91-sama7-introduce-sama7-SoC-family.patch deleted file mode 100644 index dca065971b..0000000000 --- a/target/linux/at91/patches-5.15/217-ARM-at91-sama7-introduce-sama7-SoC-family.patch +++ /dev/null @@ -1,63 +0,0 @@ -From dea645bce478cc72a2bf2413ec873927d1471442 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Thu, 15 Apr 2021 13:50:08 +0300 -Subject: [PATCH 217/247] ARM: at91: sama7: introduce sama7 SoC family - -Introduce new family of SoCs, sama7, and first SoC, sama7g5. - -Signed-off-by: Eugen Hristev -[claudiu.beznea@microchip.com: keep only the sama7_dt] -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-23-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/Makefile | 1 + - arch/arm/mach-at91/sama7.c | 32 ++++++++++++++++++++++++++++++++ - 2 files changed, 33 insertions(+) - create mode 100644 arch/arm/mach-at91/sama7.c - ---- a/arch/arm/mach-at91/Makefile -+++ b/arch/arm/mach-at91/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_AT91RM9200) += at91rm92 - obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o - obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o - obj-$(CONFIG_SOC_SAMA5) += sama5.o -+obj-$(CONFIG_SOC_SAMA7) += sama7.o - obj-$(CONFIG_SOC_SAMV7) += samv7.o - - # Power Management ---- /dev/null -+++ b/arch/arm/mach-at91/sama7.c -@@ -0,0 +1,32 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Setup code for SAMA7 -+ * -+ * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries -+ * -+ */ -+ -+#include -+#include -+ -+#include -+#include -+ -+#include "generic.h" -+ -+static void __init sama7_dt_device_init(void) -+{ -+ of_platform_default_populate(NULL, NULL, NULL); -+} -+ -+static const char *const sama7_dt_board_compat[] __initconst = { -+ "microchip,sama7", -+ NULL -+}; -+ -+DT_MACHINE_START(sama7_dt, "Microchip SAMA7") -+ /* Maintainer: Microchip */ -+ .init_machine = sama7_dt_device_init, -+ .dt_compat = sama7_dt_board_compat, -+MACHINE_END -+ diff --git a/target/linux/at91/patches-5.15/218-ARM-at91-pm-add-pm-support-for-SAMA7G5.patch b/target/linux/at91/patches-5.15/218-ARM-at91-pm-add-pm-support-for-SAMA7G5.patch deleted file mode 100644 index aada9c9679..0000000000 --- a/target/linux/at91/patches-5.15/218-ARM-at91-pm-add-pm-support-for-SAMA7G5.patch +++ /dev/null @@ -1,96 +0,0 @@ -From aba3984dc7a405d20b83bff603d23719d0e26bc7 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:09 +0300 -Subject: [PATCH 218/247] ARM: at91: pm: add pm support for SAMA7G5 - -Add support for SAMA7G5 power management modes: standby, ulp0, ulp1, backup. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-24-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/generic.h | 2 ++ - arch/arm/mach-at91/pm.c | 37 ++++++++++++++++++++++++++++++++++++ - arch/arm/mach-at91/sama7.c | 1 + - 3 files changed, 40 insertions(+) - ---- a/arch/arm/mach-at91/generic.h -+++ b/arch/arm/mach-at91/generic.h -@@ -14,12 +14,14 @@ extern void __init at91sam9_pm_init(void - extern void __init sam9x60_pm_init(void); - extern void __init sama5_pm_init(void); - extern void __init sama5d2_pm_init(void); -+extern void __init sama7_pm_init(void); - #else - static inline void __init at91rm9200_pm_init(void) { } - static inline void __init at91sam9_pm_init(void) { } - static inline void __init sam9x60_pm_init(void) { } - static inline void __init sama5_pm_init(void) { } - static inline void __init sama5d2_pm_init(void) { } -+static inline void __init sama7_pm_init(void) { } - #endif - - #endif /* _AT91_GENERIC_H */ ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -152,6 +152,17 @@ static const struct of_device_id sam9x60 - { /* sentinel */ } - }; - -+static const struct of_device_id sama7g5_ws_ids[] = { -+ { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, -+ { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, -+ { .compatible = "usb-ohci", .data = &ws_info[2] }, -+ { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, -+ { .compatible = "usb-ehci", .data = &ws_info[2] }, -+ { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, -+ { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, -+ { /* sentinel */ } -+}; -+ - static int at91_pm_config_ws(unsigned int pm_mode, bool set) - { - const struct wakeup_source_info *wsi; -@@ -1139,6 +1150,32 @@ void __init sama5d2_pm_init(void) - soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; - } - -+void __init sama7_pm_init(void) -+{ -+ static const int modes[] __initconst = { -+ AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, -+ }; -+ static const u32 iomaps[] __initconst = { -+ [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU), -+ [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) | -+ AT91_PM_IOMAP(SHDWC), -+ [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | -+ AT91_PM_IOMAP(SHDWC), -+ }; -+ -+ if (!IS_ENABLED(CONFIG_SOC_SAMA7)) -+ return; -+ -+ at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); -+ -+ at91_dt_ramc(true); -+ at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); -+ at91_pm_init(NULL); -+ -+ soc_pm.ws_ids = sama7g5_ws_ids; -+ soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; -+} -+ - static int __init at91_pm_modes_select(char *str) - { - char *s; ---- a/arch/arm/mach-at91/sama7.c -+++ b/arch/arm/mach-at91/sama7.c -@@ -17,6 +17,7 @@ - static void __init sama7_dt_device_init(void) - { - of_platform_default_populate(NULL, NULL, NULL); -+ sama7_pm_init(); - } - - static const char *const sama7_dt_board_compat[] __initconst = { diff --git a/target/linux/at91/patches-5.15/219-ARM-at91-pm-add-sama7g5-shdwc.patch b/target/linux/at91/patches-5.15/219-ARM-at91-pm-add-sama7g5-shdwc.patch deleted file mode 100644 index 062274c18f..0000000000 --- a/target/linux/at91/patches-5.15/219-ARM-at91-pm-add-sama7g5-shdwc.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 84ff37cc98e6aaefe27d6edd5e3ced2be99d9833 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:10 +0300 -Subject: [PATCH 219/247] ARM: at91: pm: add sama7g5 shdwc - -Add SAMA7G5 SHDWC. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-25-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -809,6 +809,7 @@ securam_fail: - static const struct of_device_id atmel_shdwc_ids[] = { - { .compatible = "atmel,sama5d2-shdwc" }, - { .compatible = "microchip,sam9x60-shdwc" }, -+ { .compatible = "microchip,sama7g5-shdwc" }, - { /* sentinel. */ } - }; - diff --git a/target/linux/at91/patches-5.15/220-ARM-configs-at91-add-defconfig-for-sama7-family-of-S.patch b/target/linux/at91/patches-5.15/220-ARM-configs-at91-add-defconfig-for-sama7-family-of-S.patch deleted file mode 100644 index fdb45afa7d..0000000000 --- a/target/linux/at91/patches-5.15/220-ARM-configs-at91-add-defconfig-for-sama7-family-of-S.patch +++ /dev/null @@ -1,233 +0,0 @@ -From 2223a85aed2d892bd7c13053f27e777c743e5332 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 28 Jun 2021 15:04:51 +0300 -Subject: [PATCH 220/247] ARM: configs: at91: add defconfig for sama7 family of - SoCs - -Add defconfig for sama7 SoC family. - -Signed-off-by: Eugen Hristev -[claudiu.beznea@microchip.com: add clocks, ethernet, timers, power] -Signed-off-by: Claudiu Beznea -[codrin.ciubotariu@microchip.com: add audio] -Signed-off-by: Codrin Ciubotariu -[nicolas.ferre@microchip.com: atags not set, mtd tests, spi gpio] -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210628120452.74408-3-eugen.hristev@microchip.com ---- - arch/arm/configs/sama7_defconfig | 209 +++++++++++++++++++++++++++++++ - 1 file changed, 209 insertions(+) - create mode 100644 arch/arm/configs/sama7_defconfig - ---- /dev/null -+++ b/arch/arm/configs/sama7_defconfig -@@ -0,0 +1,209 @@ -+# CONFIG_LOCALVERSION_AUTO is not set -+# CONFIG_SWAP is not set -+CONFIG_SYSVIPC=y -+CONFIG_NO_HZ_IDLE=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_LOG_BUF_SHIFT=16 -+CONFIG_CGROUPS=y -+CONFIG_CGROUP_DEBUG=y -+CONFIG_NAMESPACES=y -+CONFIG_SYSFS_DEPRECATED=y -+CONFIG_SYSFS_DEPRECATED_V2=y -+CONFIG_BLK_DEV_INITRD=y -+# CONFIG_FHANDLE is not set -+# CONFIG_IO_URING is not set -+CONFIG_KALLSYMS_ALL=y -+CONFIG_EMBEDDED=y -+# CONFIG_VM_EVENT_COUNTERS is not set -+CONFIG_SLAB=y -+CONFIG_ARCH_AT91=y -+CONFIG_SOC_SAMA7G5=y -+CONFIG_ATMEL_CLOCKSOURCE_TCB=y -+# CONFIG_CACHE_L2X0 is not set -+# CONFIG_ARM_PATCH_IDIV is not set -+# CONFIG_CPU_SW_DOMAIN_PAN is not set -+CONFIG_FORCE_MAX_ZONEORDER=15 -+CONFIG_UACCESS_WITH_MEMCPY=y -+# CONFIG_ATAGS is not set -+CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk ignore_loglevel" -+CONFIG_VFP=y -+CONFIG_NEON=y -+CONFIG_KERNEL_MODE_NEON=y -+CONFIG_MODULES=y -+CONFIG_MODULE_FORCE_LOAD=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODULE_FORCE_UNLOAD=y -+# CONFIG_BLK_DEV_BSG is not set -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_EFI_PARTITION is not set -+# CONFIG_COREDUMP is not set -+# CONFIG_COMPACTION is not set -+CONFIG_CMA=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+# CONFIG_INET_DIAG is not set -+CONFIG_IPV6_SIT_6RD=y -+CONFIG_BRIDGE=m -+CONFIG_BRIDGE_VLAN_FILTERING=y -+CONFIG_NET_DSA=m -+CONFIG_VLAN_8021Q=m -+CONFIG_CAN=y -+CONFIG_CAN_M_CAN=y -+CONFIG_CAN_M_CAN_PLATFORM=y -+CONFIG_BT=y -+CONFIG_BT_RFCOMM=y -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=y -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=y -+CONFIG_BT_HCIBTUSB=y -+CONFIG_BT_HCIUART=y -+CONFIG_BT_HCIUART_H4=y -+CONFIG_BT_HCIVHCI=y -+CONFIG_CFG80211=m -+# CONFIG_CFG80211_DEFAULT_PS is not set -+CONFIG_CFG80211_DEBUGFS=y -+CONFIG_CFG80211_WEXT=y -+CONFIG_MAC80211=m -+CONFIG_MAC80211_LEDS=y -+CONFIG_RFKILL=y -+CONFIG_RFKILL_INPUT=y -+CONFIG_PCCARD=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+# CONFIG_STANDALONE is not set -+# CONFIG_PREVENT_FIRMWARE_BUILD is not set -+# CONFIG_ALLOW_DEV_COREDUMP is not set -+CONFIG_MTD=y -+CONFIG_MTD_TESTS=m -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_COUNT=1 -+CONFIG_BLK_DEV_RAM_SIZE=8192 -+CONFIG_EEPROM_AT24=y -+CONFIG_SCSI=y -+CONFIG_BLK_DEV_SD=y -+CONFIG_NETDEVICES=y -+CONFIG_MACB=y -+CONFIG_MICREL_PHY=y -+CONFIG_INPUT_EVDEV=y -+CONFIG_KEYBOARD_GPIO=y -+# CONFIG_INPUT_MOUSE is not set -+CONFIG_LEGACY_PTY_COUNT=4 -+CONFIG_SERIAL_ATMEL=y -+CONFIG_SERIAL_ATMEL_CONSOLE=y -+CONFIG_HW_RANDOM=y -+CONFIG_I2C=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_AT91=y -+CONFIG_SPI=y -+CONFIG_SPI_MEM=y -+CONFIG_SPI_ATMEL=y -+CONFIG_SPI_GPIO=y -+CONFIG_PINCTRL_AT91=y -+CONFIG_PINCTRL_AT91PIO4=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_POWER_RESET=y -+CONFIG_POWER_RESET_AT91_RESET=y -+CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y -+# CONFIG_HWMON is not set -+CONFIG_WATCHDOG=y -+CONFIG_SAMA5D4_WATCHDOG=y -+CONFIG_MFD_ATMEL_FLEXCOM=y -+CONFIG_REGULATOR=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_MCP16502=y -+CONFIG_MEDIA_SUPPORT=y -+CONFIG_MEDIA_SUPPORT_FILTER=y -+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_PLATFORM_SUPPORT=y -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_IMX219=m -+CONFIG_VIDEO_IMX274=m -+CONFIG_VIDEO_OV5647=m -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_SOC=y -+CONFIG_SND_ATMEL_SOC=y -+CONFIG_SND_SOC_MIKROE_PROTO=m -+CONFIG_SND_MCHP_SOC_I2S_MCC=y -+CONFIG_SND_MCHP_SOC_SPDIFTX=y -+CONFIG_SND_MCHP_SOC_SPDIFRX=y -+CONFIG_SND_SOC_PCM5102A=y -+CONFIG_SND_SOC_SPDIF=y -+CONFIG_SND_SIMPLE_CARD=y -+CONFIG_USB=y -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -+CONFIG_USB_DYNAMIC_MINORS=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_UAS=y -+CONFIG_USB_GADGET=y -+CONFIG_U_SERIAL_CONSOLE=y -+CONFIG_USB_ATMEL_USBA=m -+CONFIG_USB_CONFIGFS=y -+CONFIG_USB_CONFIGFS_ACM=y -+CONFIG_USB_CONFIGFS_MASS_STORAGE=y -+CONFIG_USB_CONFIGFS_F_UVC=y -+CONFIG_USB_G_SERIAL=m -+CONFIG_MMC=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_OF_AT91=y -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_RTC_CLASS=y -+# CONFIG_RTC_NVMEM is not set -+CONFIG_RTC_DRV_AT91RM9200=y -+CONFIG_RTC_DRV_AT91SAM9=y -+CONFIG_DMADEVICES=y -+CONFIG_AT_XDMAC=y -+CONFIG_DMATEST=y -+CONFIG_STAGING=y -+CONFIG_MICROCHIP_PIT64B=y -+# CONFIG_IOMMU_SUPPORT is not set -+# CONFIG_ATMEL_EBI is not set -+CONFIG_IIO=y -+CONFIG_IIO_SW_TRIGGER=y -+CONFIG_AT91_SAMA5D2_ADC=y -+CONFIG_PWM=y -+CONFIG_PWM_ATMEL=y -+CONFIG_EXT2_FS=y -+CONFIG_EXT3_FS=y -+CONFIG_FANOTIFY=y -+CONFIG_VFAT_FS=y -+CONFIG_TMPFS=y -+CONFIG_NFS_FS=y -+CONFIG_ROOT_NFS=y -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_CODEPAGE_850=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_UTF8=y -+CONFIG_LSM="N" -+CONFIG_CRYPTO_DEFLATE=y -+CONFIG_CRYPTO_LZO=y -+# CONFIG_CRYPTO_HW is not set -+CONFIG_CRC_CCITT=y -+CONFIG_CRC_ITU_T=y -+CONFIG_DMA_CMA=y -+CONFIG_CMA_SIZE_MBYTES=32 -+CONFIG_CMA_ALIGNMENT=9 -+# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -+CONFIG_DEBUG_FS=y -+# CONFIG_DEBUG_MISC is not set -+# CONFIG_SCHED_DEBUG is not set -+CONFIG_STACKTRACE=y -+# CONFIG_FTRACE is not set -+CONFIG_DEBUG_USER=y -+# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/target/linux/at91/patches-5.15/221-ARM-multi_v7_defconfig-add-sama7g5-SoC.patch b/target/linux/at91/patches-5.15/221-ARM-multi_v7_defconfig-add-sama7g5-SoC.patch deleted file mode 100644 index 6c95d4a0f5..0000000000 --- a/target/linux/at91/patches-5.15/221-ARM-multi_v7_defconfig-add-sama7g5-SoC.patch +++ /dev/null @@ -1,33 +0,0 @@ -From a62536054548e85da84ed835dc87baa8e5e99b41 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 28 Jun 2021 15:04:52 +0300 -Subject: [PATCH 221/247] ARM: multi_v7_defconfig: add sama7g5 SoC - -Add the Microchip SAMA7G5 ARM v7 Cortex-A7 based SoC to multi_v7_defconfig. -Also add it's clock timer, the PIT64B. - -Signed-off-by: Eugen Hristev -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210628120452.74408-4-eugen.hristev@microchip.com ---- - arch/arm/configs/multi_v7_defconfig | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/configs/multi_v7_defconfig -+++ b/arch/arm/configs/multi_v7_defconfig -@@ -15,6 +15,7 @@ CONFIG_ARCH_AT91=y - CONFIG_SOC_SAMA5D2=y - CONFIG_SOC_SAMA5D3=y - CONFIG_SOC_SAMA5D4=y -+CONFIG_SOC_SAMA7G5=y - CONFIG_ARCH_BCM=y - CONFIG_ARCH_BCM_CYGNUS=y - CONFIG_ARCH_BCM_HR2=y -@@ -967,6 +968,7 @@ CONFIG_APQ_MMCC_8084=y - CONFIG_MSM_GCC_8660=y - CONFIG_MSM_MMCC_8960=y - CONFIG_MSM_MMCC_8974=y -+CONFIG_MICROCHIP_PIT64B=y - CONFIG_BCM2835_MBOX=y - CONFIG_ROCKCHIP_IOMMU=y - CONFIG_TEGRA_IOMMU_GART=y diff --git a/target/linux/at91/patches-5.15/222-ARM-dts-at91-add-sama7g5-SoC-DT-and-sama7g5-ek.patch b/target/linux/at91/patches-5.15/222-ARM-dts-at91-add-sama7g5-SoC-DT-and-sama7g5-ek.patch deleted file mode 100644 index b79ce5ab2e..0000000000 --- a/target/linux/at91/patches-5.15/222-ARM-dts-at91-add-sama7g5-SoC-DT-and-sama7g5-ek.patch +++ /dev/null @@ -1,2154 +0,0 @@ -From 969b39d51b7df0869cca9983b06cefb59dae72b0 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 28 Jun 2021 15:04:50 +0300 -Subject: [PATCH 222/247] ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek - -Add Device Tree for sama7g5 SoC and associated board sama7g5-ek - -Signed-off-by: Eugen Hristev -[claudiu.beznea@microchip.com: add clocks, ethernet, timers, power] -Signed-off-by: Claudiu Beznea -[codrin.ciubotariu@microchip.com: add audio] -Signed-off-by: Codrin Ciubotariu -[nicolas.ferre@microchip.com: removed eeproms, reorder i2s dma chans] -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210628120452.74408-2-eugen.hristev@microchip.com -[claudiu.beznea: adapt to kernel v5.10] -Signed-off-by: Claudiu Beznea ---- - arch/arm/boot/dts/Makefile | 2 + - arch/arm/boot/dts/at91-sama7g5ek.dts | 656 +++++++++++++++++++ - arch/arm/boot/dts/sama7g5-pinfunc.h | 923 +++++++++++++++++++++++++++ - arch/arm/boot/dts/sama7g5.dtsi | 528 +++++++++++++++ - 4 files changed, 2109 insertions(+) - create mode 100644 arch/arm/boot/dts/at91-sama7g5ek.dts - create mode 100644 arch/arm/boot/dts/sama7g5-pinfunc.h - create mode 100644 arch/arm/boot/dts/sama7g5.dtsi - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -79,6 +79,8 @@ dtb-$(CONFIG_ARCH_ATLAS6) += \ - atlas6-evb.dtb - dtb-$(CONFIG_ARCH_ATLAS7) += \ - atlas7-evb.dtb -+dtb-$(CONFIG_SOC_SAMA7G5) += \ -+ at91-sama7g5ek.dtb - dtb-$(CONFIG_ARCH_AXXIA) += \ - axm5516-amarillo.dtb - dtb-$(CONFIG_ARCH_BCM2835) += \ ---- /dev/null -+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts -@@ -0,0 +1,656 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * at91-sama7g5ek.dts - Device Tree file for SAMA7G5-EK board -+ * -+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries -+ * -+ * Author: Eugen Hristev -+ * Author: Claudiu Beznea -+ * -+ */ -+/dts-v1/; -+#include "sama7g5-pinfunc.h" -+#include "sama7g5.dtsi" -+#include -+#include -+ -+/ { -+ model = "Microchip SAMA7G5-EK"; -+ compatible = "microchip,sama7g5ek", "microchip,sama7g5", "microchip,sama7"; -+ -+ chosen { -+ bootargs = "rw root=/dev/mmcblk1p2 rootfstype=ext4 rootwait"; -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ aliases { -+ serial0 = &uart3; -+ serial1 = &uart4; -+ serial2 = &uart7; -+ serial3 = &uart0; -+ i2c0 = &i2c1; -+ i2c1 = &i2c8; -+ i2c2 = &i2c9; -+ }; -+ -+ clocks { -+ slow_xtal { -+ clock-frequency = <32768>; -+ }; -+ -+ main_xtal { -+ clock-frequency = <24000000>; -+ }; -+ }; -+ -+ gpio_keys { -+ compatible = "gpio-keys"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_key_gpio_default>; -+ -+ bp1 { -+ label = "PB_USER"; -+ gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_led_gpio_default>; -+ status = "okay"; /* Conflict with pwm. */ -+ -+ red_led { -+ label = "red"; -+ gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ green_led { -+ label = "green"; -+ gpios = <&pioA PIN_PA13 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ blue_led { -+ label = "blue"; -+ gpios = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ /* 512 M */ -+ memory@60000000 { -+ device_type = "memory"; -+ reg = <0x60000000 0x20000000>; -+ }; -+ -+ sound: sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "sama7g5ek audio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ simple-audio-card,dai-link@0 { -+ reg = <0>; -+ cpu { -+ sound-dai = <&spdiftx>; -+ }; -+ codec { -+ sound-dai = <&spdif_out>; -+ }; -+ }; -+ simple-audio-card,dai-link@1 { -+ reg = <1>; -+ cpu { -+ sound-dai = <&spdifrx>; -+ }; -+ codec { -+ sound-dai = <&spdif_in>; -+ }; -+ }; -+ }; -+ -+ spdif_in: spdif-in { -+ #sound-dai-cells = <0>; -+ compatible = "linux,spdif-dir"; -+ }; -+ -+ spdif_out: spdif-out { -+ #sound-dai-cells = <0>; -+ compatible = "linux,spdif-dit"; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vddcpu>; -+}; -+ -+&dma0 { -+ status = "okay"; -+}; -+ -+&dma1 { -+ status = "okay"; -+}; -+ -+&dma2 { -+ status = "okay"; -+}; -+ -+&flx0 { -+ atmel,flexcom-mode = ; -+ status = "disabled"; -+ -+ uart0: serial@200 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flx0_default>; -+ status = "disabled"; -+ }; -+}; -+ -+&flx1 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ i2c1: i2c@600 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1_default>; -+ i2c-analog-filter; -+ i2c-digital-filter; -+ i2c-digital-filter-width-ns = <35>; -+ status = "okay"; -+ -+ mcp16502@5b { -+ compatible = "microchip,mcp16502"; -+ reg = <0x5b>; -+ status = "okay"; -+ -+ regulators { -+ vdd_3v3: VDD_IO { -+ regulator-name = "VDD_IO"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <3700000>; -+ regulator-initial-mode = <2>; -+ regulator-allowed-modes = <2>, <4>; -+ regulator-always-on; -+ -+ regulator-state-standby { -+ regulator-on-in-suspend; -+ regulator-mode = <4>; -+ }; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-mode = <4>; -+ }; -+ }; -+ -+ vddioddr: VDD_DDR { -+ regulator-name = "VDD_DDR"; -+ regulator-min-microvolt = <1300000>; -+ regulator-max-microvolt = <1450000>; -+ regulator-initial-mode = <2>; -+ regulator-allowed-modes = <2>, <4>; -+ regulator-always-on; -+ -+ regulator-state-standby { -+ regulator-on-in-suspend; -+ regulator-mode = <4>; -+ }; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-mode = <4>; -+ }; -+ }; -+ -+ vddcore: VDD_CORE { -+ regulator-name = "VDD_CORE"; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1850000>; -+ regulator-initial-mode = <2>; -+ regulator-allowed-modes = <2>, <4>; -+ regulator-always-on; -+ -+ regulator-state-standby { -+ regulator-on-in-suspend; -+ regulator-mode = <4>; -+ }; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-mode = <4>; -+ }; -+ }; -+ -+ vddcpu: VDD_OTHER { -+ regulator-name = "VDD_OTHER"; -+ regulator-min-microvolt = <1125000>; -+ regulator-max-microvolt = <1850000>; -+ regulator-initial-mode = <2>; -+ regulator-allowed-modes = <2>, <4>; -+ regulator-ramp-delay = <3125>; -+ regulator-always-on; -+ -+ regulator-state-standby { -+ regulator-on-in-suspend; -+ regulator-mode = <4>; -+ }; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-mode = <4>; -+ }; -+ }; -+ -+ vldo1: LDO1 { -+ regulator-name = "LDO1"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <3700000>; -+ regulator-always-on; -+ -+ regulator-state-standby { -+ regulator-on-in-suspend; -+ }; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vldo2: LDO2 { -+ regulator-name = "LDO2"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <3700000>; -+ -+ regulator-state-standby { -+ regulator-on-in-suspend; -+ }; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&flx3 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ uart3: serial@200 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flx3_default>; -+ status = "okay"; -+ }; -+}; -+ -+&flx4 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ uart4: serial@200 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flx4_default>; -+ status = "okay"; -+ }; -+}; -+ -+&flx7 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ uart7: serial@200 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flx7_default>; -+ status = "okay"; -+ }; -+}; -+ -+&flx8 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ i2c8: i2c@600 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c8_default>; -+ i2c-analog-filter; -+ i2c-digital-filter; -+ i2c-digital-filter-width-ns = <35>; -+ status = "okay"; -+ }; -+}; -+ -+&flx9 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ i2c9: i2c@600 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c9_default>; -+ i2c-analog-filter; -+ i2c-digital-filter; -+ i2c-digital-filter-width-ns = <35>; -+ status = "okay"; -+ }; -+}; -+ -+&flx11 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ spi11: spi@400 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; -+ status = "okay"; -+ }; -+}; -+ -+&gmac0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>; -+ phy-mode = "rgmii-id"; -+ status = "okay"; -+ -+ ethernet-phy@7 { -+ reg = <0x7>; -+ interrupt-parent = <&pioA>; -+ interrupts = ; -+ }; -+}; -+ -+&gmac1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>; -+ phy-mode = "rmii"; -+ status = "okay"; -+ -+ ethernet-phy@0 { -+ reg = <0x0>; -+ interrupt-parent = <&pioA>; -+ interrupts = ; -+ }; -+}; -+ -+&i2s0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2s0_default>; -+}; -+ -+&pioA { -+ pinctrl_flx0_default: flx0_default { -+ pinmux = , -+ , -+ , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_flx3_default: flx3_default { -+ pinmux = , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_flx4_default: flx4_default { -+ pinmux = , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_flx7_default: flx7_default { -+ pinmux = , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_gmac0_default: gmac0_default { -+ pinmux = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_gmac0_txck_default: gmac0_txck_default { -+ pinmux = ; -+ bias-pull-up; -+ }; -+ -+ pinctrl_gmac0_phy_irq: gmac0_phy_irq { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_gmac1_default: gmac1_default { -+ pinmux = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_gmac1_phy_irq: gmac1_phy_irq { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_i2c1_default: i2c1_default { -+ pinmux = , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_i2c8_default: i2c8_default { -+ pinmux = , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_i2c9_default: i2c9_default { -+ pinmux = , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_i2s0_default: i2s0_default { -+ pinmux = , -+ , -+ , -+ , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_key_gpio_default: key_gpio_default { -+ pinmux = ; -+ bias-pull-up; -+ }; -+ -+ pinctrl_led_gpio_default: led_gpio_default { -+ pinmux = , -+ , -+ ; -+ bias-pull-up; -+ }; -+ -+ pinctrl_mikrobus1_an_default: mikrobus1_an_default { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_mikrobus2_an_default: mikrobus2_an_default { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_mikrobus1_pwm2_default: mikrobus1_pwm2_default { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_mikrobus2_pwm3_default: mikrobus2_pwm3_default { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_mikrobus1_spi: mikrobus1_spi { -+ pinmux = , -+ , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_sdmmc0_default: sdmmc0_default { -+ cmd_data { -+ pinmux = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ bias-pull-up; -+ }; -+ -+ ck_cd_rstn_vddsel { -+ pinmux = , -+ , -+ ; -+ bias-pull-up; -+ }; -+ }; -+ -+ pinctrl_sdmmc1_default: sdmmc1_default { -+ cmd_data { -+ pinmux = , -+ , -+ , -+ , -+ ; -+ bias-pull-up; -+ }; -+ -+ ck_cd_rstn_vddsel { -+ pinmux = , -+ , -+ , -+ ; -+ bias-pull-up; -+ }; -+ }; -+ -+ pinctrl_sdmmc2_default: sdmmc2_default { -+ cmd_data { -+ pinmux = , -+ , -+ , -+ , -+ ; -+ bias-pull-up; -+ }; -+ -+ ck { -+ pinmux = ; -+ bias-pull-up; -+ }; -+ }; -+ -+ pinctrl_spdifrx_default: spdifrx_default { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_spdiftx_default: spdiftx_default { -+ pinmux = ; -+ bias-disable; -+ }; -+}; -+ -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mikrobus1_pwm2_default &pinctrl_mikrobus2_pwm3_default>; -+ status = "disabled"; /* Conflict with leds. */ -+}; -+ -+&rtt { -+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>; -+}; -+ -+&sdmmc0 { -+ bus-width = <8>; -+ non-removable; -+ no-1-8-v; -+ sdhci-caps-mask = <0x0 0x00200000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sdmmc0_default>; -+ status = "okay"; -+}; -+ -+&sdmmc1 { -+ bus-width = <4>; -+ no-1-8-v; -+ sdhci-caps-mask = <0x0 0x00200000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sdmmc1_default>; -+ status = "okay"; -+}; -+ -+&sdmmc2 { -+ bus-width = <4>; -+ no-1-8-v; -+ sdhci-caps-mask = <0x0 0x00200000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sdmmc2_default>; -+}; -+ -+&spdifrx { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdifrx_default>; -+ status = "okay"; -+}; -+ -+&spdiftx { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdiftx_default>; -+ status = "okay"; -+}; -+ -+&trng { -+ status = "okay"; -+}; -+ -+&vddout25 { -+ vin-supply = <&vdd_3v3>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/sama7g5-pinfunc.h -@@ -0,0 +1,923 @@ -+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -+#define PINMUX_PIN(no, func, ioset) \ -+(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) -+ -+#define PIN_PA0 0 -+#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) -+#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) -+#define PIN_PA0__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA0, 2, 1) -+#define PIN_PA0__CANTX3 PINMUX_PIN(PIN_PA0, 3, 1) -+#define PIN_PA0__PWML0 PINMUX_PIN(PIN_PA0, 5, 2) -+#define PIN_PA1 1 -+#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) -+#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) -+#define PIN_PA1__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA1, 2, 1) -+#define PIN_PA1__CANRX3 PINMUX_PIN(PIN_PA1, 3, 1) -+#define PIN_PA1__D14 PINMUX_PIN(PIN_PA1, 4, 1) -+#define PIN_PA1__PWMH0 PINMUX_PIN(PIN_PA1, 5, 3) -+#define PIN_PA2 2 -+#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) -+#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1) -+#define PIN_PA2__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA2, 2, 1) -+#define PIN_PA2__PDMC1_CLK PINMUX_PIN(PIN_PA2, 3, 1) -+#define PIN_PA2__D15 PINMUX_PIN(PIN_PA2, 4, 1) -+#define PIN_PA2__PWMH1 PINMUX_PIN(PIN_PA2, 5, 3) -+#define PIN_PA2__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA2, 6, 3) -+#define PIN_PA3 3 -+#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) -+#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1) -+#define PIN_PA3__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA3, 2, 1) -+#define PIN_PA3__PDMC1_DS0 PINMUX_PIN(PIN_PA3, 3, 1) -+#define PIN_PA3__NWR1_NBS1 PINMUX_PIN(PIN_PA3, 4, 1) -+#define PIN_PA3__PWML3 PINMUX_PIN(PIN_PA3, 5, 3) -+#define PIN_PA3__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA3, 6, 3) -+#define PIN_PA4 4 -+#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) -+#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1) -+#define PIN_PA4__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA4, 2, 1) -+#define PIN_PA4__PDMC1_DS1 PINMUX_PIN(PIN_PA4, 3, 1) -+#define PIN_PA4__NCS2 PINMUX_PIN(PIN_PA4, 4, 1) -+#define PIN_PA4__PWMH3 PINMUX_PIN(PIN_PA4, 5, 3) -+#define PIN_PA4__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA4, 6, 3) -+#define PIN_PA5 5 -+#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) -+#define PIN_PA5__SDMMC0_DAT2 PINMUX_PIN(PIN_PA5, 1, 1) -+#define PIN_PA5__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA5, 2, 1) -+#define PIN_PA5__CANTX2 PINMUX_PIN(PIN_PA5, 3, 1) -+#define PIN_PA5__A23 PINMUX_PIN(PIN_PA5, 4, 1) -+#define PIN_PA5__PWMEXTRG0 PINMUX_PIN(PIN_PA5, 5, 3) -+#define PIN_PA5__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA5, 6, 3) -+#define PIN_PA6 6 -+#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) -+#define PIN_PA6__SDMMC0_DAT3 PINMUX_PIN(PIN_PA6, 1, 1) -+#define PIN_PA6__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA6, 2, 1) -+#define PIN_PA6__CANRX2 PINMUX_PIN(PIN_PA6, 3, 1) -+#define PIN_PA6__A24 PINMUX_PIN(PIN_PA6, 4, 1) -+#define PIN_PA6__PWMEXTRG1 PINMUX_PIN(PIN_PA6, 5, 3) -+#define PIN_PA6__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA6, 6, 3) -+#define PIN_PA7 7 -+#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) -+#define PIN_PA7__SDMMC0_DAT4 PINMUX_PIN(PIN_PA7, 1, 1) -+#define PIN_PA7__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA7, 2, 1) -+#define PIN_PA7__CANTX1 PINMUX_PIN(PIN_PA7, 3, 1) -+#define PIN_PA7__NWAIT PINMUX_PIN(PIN_PA7, 4, 1) -+#define PIN_PA7__PWMFI0 PINMUX_PIN(PIN_PA7, 5, 3) -+#define PIN_PA7__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA7, 6, 3) -+#define PIN_PA8 8 -+#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) -+#define PIN_PA8__SDMMC0_DAT5 PINMUX_PIN(PIN_PA8, 1, 1) -+#define PIN_PA8__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA8, 2, 1) -+#define PIN_PA8__CANRX1 PINMUX_PIN(PIN_PA8, 3, 1) -+#define PIN_PA8__NCS0 PINMUX_PIN(PIN_PA8, 4, 1) -+#define PIN_PA8__PWMIF1 PINMUX_PIN(PIN_PA8, 5, 3) -+#define PIN_PA8__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA8, 6, 3) -+#define PIN_PA9 9 -+#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) -+#define PIN_PA9__SDMMC0_DAT6 PINMUX_PIN(PIN_PA9, 1, 1) -+#define PIN_PA9__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA9, 2, 1) -+#define PIN_PA9__CANTX0 PINMUX_PIN(PIN_PA9, 3, 1) -+#define PIN_PA9__SMCK PINMUX_PIN(PIN_PA9, 4, 1) -+#define PIN_PA9__SPDIF_RX PINMUX_PIN(PIN_PA9, 5, 1) -+#define PIN_PA9__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA9, 6, 3) -+#define PIN_PA10 10 -+#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) -+#define PIN_PA10__SDMMC0_DAT7 PINMUX_PIN(PIN_PA10, 1, 1) -+#define PIN_PA10__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA10, 2, 1) -+#define PIN_PA10__CANRX0 PINMUX_PIN(PIN_PA10, 3, 1) -+#define PIN_PA10__NCS1 PINMUX_PIN(PIN_PA10, 4, 1) -+#define PIN_PA10__SPDIF_TX PINMUX_PIN(PIN_PA10, 5, 1) -+#define PIN_PA10__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA10, 6, 3) -+#define PIN_PA11 11 -+#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) -+#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1) -+#define PIN_PA11__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA11, 2, 1) -+#define PIN_PA11__A0_NBS0 PINMUX_PIN(PIN_PA11, 4, 1) -+#define PIN_PA11__TIOA0 PINMUX_PIN(PIN_PA11, 5, 1) -+#define PIN_PA11__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA11, 6, 3) -+#define PIN_PA12 12 -+#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) -+#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) -+#define PIN_PA12__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA12, 2, 1) -+#define PIN_PA12__FLEXCOM3_IO5 PINMUX_PIN(PIN_PA12, 4, 1) -+#define PIN_PA12__PWML2 PINMUX_PIN(PIN_PA12, 5, 3) -+#define PIN_PA12__FLEXCOM6_IO0 PINMUX_PIN(PIN_PA12, 6, 3) -+#define PIN_PA13 13 -+#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) -+#define PIN_PA13__SDMMC0_1V8SEL PINMUX_PIN(PIN_PA13, 1, 1) -+#define PIN_PA13__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA13, 2, 1) -+#define PIN_PA13__FLEXCOM3_IO6 PINMUX_PIN(PIN_PA13, 4, 1) -+#define PIN_PA13__PWMH2 PINMUX_PIN(PIN_PA13, 5, 3) -+#define PIN_PA13__FLEXCOM6_IO1 PINMUX_PIN(PIN_PA13, 6, 3) -+#define PIN_PA14 14 -+#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) -+#define PIN_PA14__SDMMC0_CD PINMUX_PIN(PIN_PA14, 1, 1) -+#define PIN_PA14__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA14, 2, 1) -+#define PIN_PA14__A25 PINMUX_PIN(PIN_PA14, 4, 1) -+#define PIN_PA14__PWML1 PINMUX_PIN(PIN_PA14, 5, 3) -+#define PIN_PA15 15 -+#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) -+#define PIN_PA15__G0_TXEN PINMUX_PIN(PIN_PA15, 1, 1) -+#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 2, 1) -+#define PIN_PA15__ISC_MCK PINMUX_PIN(PIN_PA15, 3, 1) -+#define PIN_PA15__A1 PINMUX_PIN(PIN_PA15, 4, 1) -+#define PIN_PA15__TIOB0 PINMUX_PIN(PIN_PA15, 5, 1) -+#define PIN_PA16 16 -+#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) -+#define PIN_PA16__G0_TX0 PINMUX_PIN(PIN_PA16, 1, 1) -+#define PIN_PA16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA16, 2, 1) -+#define PIN_PA16__ISC_D0 PINMUX_PIN(PIN_PA16, 3, 1) -+#define PIN_PA16__A2 PINMUX_PIN(PIN_PA16, 4, 1) -+#define PIN_PA16__TCLK0 PINMUX_PIN(PIN_PA16, 5, 1) -+#define PIN_PA17 17 -+#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) -+#define PIN_PA17__G0_TX1 PINMUX_PIN(PIN_PA17, 1, 1) -+#define PIN_PA17__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA17, 2, 1) -+#define PIN_PA17__ISC_D1 PINMUX_PIN(PIN_PA17, 3, 1) -+#define PIN_PA17__A3 PINMUX_PIN(PIN_PA17, 4, 1) -+#define PIN_PA17__TIOA1 PINMUX_PIN(PIN_PA17, 5, 1) -+#define PIN_PA18 18 -+#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) -+#define PIN_PA18__G0_RXDV PINMUX_PIN(PIN_PA18, 1, 1) -+#define PIN_PA18__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA18, 2, 1) -+#define PIN_PA18__ISC_D2 PINMUX_PIN(PIN_PA18, 3, 1) -+#define PIN_PA18__A4 PINMUX_PIN(PIN_PA18, 4, 1) -+#define PIN_PA18__TIOB1 PINMUX_PIN(PIN_PA18, 5, 1) -+#define PIN_PA19 19 -+#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) -+#define PIN_PA19__G0_RX0 PINMUX_PIN(PIN_PA19, 1, 1) -+#define PIN_PA19__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA19, 2, 1) -+#define PIN_PA19__ISC_D3 PINMUX_PIN(PIN_PA19, 3, 1) -+#define PIN_PA19__A5 PINMUX_PIN(PIN_PA19, 4, 1) -+#define PIN_PA19__TCLK1 PINMUX_PIN(PIN_PA19, 5, 1) -+#define PIN_PA20 20 -+#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) -+#define PIN_PA20__G0_RX1 PINMUX_PIN(PIN_PA20, 1, 1) -+#define PIN_PA20__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA20, 2, 1) -+#define PIN_PA20__ISC_D4 PINMUX_PIN(PIN_PA20, 3, 1) -+#define PIN_PA20__A6 PINMUX_PIN(PIN_PA20, 4, 1) -+#define PIN_PA20__TIOA2 PINMUX_PIN(PIN_PA20, 5, 1) -+#define PIN_PA21 21 -+#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) -+#define PIN_PA21__G0_RXER PINMUX_PIN(PIN_PA21, 1, 1) -+#define PIN_PA21__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA21, 2, 1) -+#define PIN_PA21__ISC_D5 PINMUX_PIN(PIN_PA21, 3, 1) -+#define PIN_PA21__A7 PINMUX_PIN(PIN_PA21, 4, 1) -+#define PIN_PA21__TIOB2 PINMUX_PIN(PIN_PA21, 5, 1) -+#define PIN_PA22 22 -+#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) -+#define PIN_PA22__G0_MDC PINMUX_PIN(PIN_PA22, 1, 1) -+#define PIN_PA22__FLEXCOM4_IO2 PINMUX_PIN(PIN_PA22, 2, 1) -+#define PIN_PA22__ISC_D6 PINMUX_PIN(PIN_PA22, 3, 1) -+#define PIN_PA22__A8 PINMUX_PIN(PIN_PA22, 4, 1) -+#define PIN_PA22__TCLK2 PINMUX_PIN(PIN_PA22, 5, 1) -+#define PIN_PA23 23 -+#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) -+#define PIN_PA23__G0_MDIO PINMUX_PIN(PIN_PA23, 1, 1) -+#define PIN_PA23__FLEXCOM4_IO3 PINMUX_PIN(PIN_PA23, 2, 1) -+#define PIN_PA23__ISC_D7 PINMUX_PIN(PIN_PA23, 3, 1) -+#define PIN_PA23__A9 PINMUX_PIN(PIN_PA23, 4, 1) -+#define PIN_PA24 24 -+#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) -+#define PIN_PA24__G0_TXCK PINMUX_PIN(PIN_PA24, 1, 1) -+#define PIN_PA24__FLEXCOM4_IO4 PINMUX_PIN(PIN_PA24, 2, 1) -+#define PIN_PA24__ISC_HSYNC PINMUX_PIN(PIN_PA24, 3, 1) -+#define PIN_PA24__A10 PINMUX_PIN(PIN_PA24, 4, 1) -+#define PIN_PA24__FLEXCOM0_IO5 PINMUX_PIN(PIN_PA24, 5, 1) -+#define PIN_PA25 25 -+#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) -+#define PIN_PA25__G0_125CK PINMUX_PIN(PIN_PA25, 1, 1) -+#define PIN_PA25__FLEXCOM5_IO4 PINMUX_PIN(PIN_PA25, 2, 1) -+#define PIN_PA25__ISC_VSYNC PINMUX_PIN(PIN_PA25, 3, 1) -+#define PIN_PA25__A11 PINMUX_PIN(PIN_PA25, 4, 1) -+#define PIN_PA25__FLEXCOM0_IO6 PINMUX_PIN(PIN_PA25, 5, 1) -+#define PIN_PA25__FLEXCOM7_IO0 PINMUX_PIN(PIN_PA25, 6, 3) -+#define PIN_PA26 26 -+#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) -+#define PIN_PA26__G0_TX2 PINMUX_PIN(PIN_PA26, 1, 1) -+#define PIN_PA26__FLEXCOM5_IO2 PINMUX_PIN(PIN_PA26, 2, 1) -+#define PIN_PA26__ISC_FIELD PINMUX_PIN(PIN_PA26, 3, 1) -+#define PIN_PA26__A12 PINMUX_PIN(PIN_PA26, 4, 1) -+#define PIN_PA26__TF0 PINMUX_PIN(PIN_PA26, 5, 1) -+#define PIN_PA26__FLEXCOM7_IO1 PINMUX_PIN(PIN_PA26, 6, 3) -+#define PIN_PA27 27 -+#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) -+#define PIN_PA27__G0_TX3 PINMUX_PIN(PIN_PA27, 1, 1) -+#define PIN_PA27__FLEXCOM5_IO3 PINMUX_PIN(PIN_PA27, 2, 1) -+#define PIN_PA27__ISC_PCK PINMUX_PIN(PIN_PA27, 3, 1) -+#define PIN_PA27__A13 PINMUX_PIN(PIN_PA27, 4, 1) -+#define PIN_PA27__TK0 PINMUX_PIN(PIN_PA27, 5, 1) -+#define PIN_PA27__FLEXCOM8_IO0 PINMUX_PIN(PIN_PA27, 6, 3) -+#define PIN_PA28 28 -+#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) -+#define PIN_PA28__G0_RX2 PINMUX_PIN(PIN_PA28, 1, 1) -+#define PIN_PA28__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA28, 2, 1) -+#define PIN_PA28__ISC_D8 PINMUX_PIN(PIN_PA28, 3, 1) -+#define PIN_PA28__A14 PINMUX_PIN(PIN_PA28, 4, 1) -+#define PIN_PA28__RD0 PINMUX_PIN(PIN_PA28, 5, 1) -+#define PIN_PA28__FLEXCOM8_IO1 PINMUX_PIN(PIN_PA28, 6, 3) -+#define PIN_PA29 29 -+#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) -+#define PIN_PA29__G0_RX3 PINMUX_PIN(PIN_PA29, 1, 1) -+#define PIN_PA29__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA29, 2, 1) -+#define PIN_PA29__ISC_D9 PINMUX_PIN(PIN_PA29, 3, 1) -+#define PIN_PA29__A15 PINMUX_PIN(PIN_PA29, 4, 1) -+#define PIN_PA29__RF0 PINMUX_PIN(PIN_PA29, 5, 1) -+#define PIN_PA29__FLEXCOM9_IO0 PINMUX_PIN(PIN_PA29, 6, 3) -+#define PIN_PA30 30 -+#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) -+#define PIN_PA30__G0_RXCK PINMUX_PIN(PIN_PA30, 1, 1) -+#define PIN_PA30__FLEXCOM6_IO4 PINMUX_PIN(PIN_PA30, 2, 1) -+#define PIN_PA30__ISC_D10 PINMUX_PIN(PIN_PA30, 3, 1) -+#define PIN_PA30__A16 PINMUX_PIN(PIN_PA30, 4, 1) -+#define PIN_PA30__RK0 PINMUX_PIN(PIN_PA30, 5, 1) -+#define PIN_PA30__FLEXCOM9_IO1 PINMUX_PIN(PIN_PA30, 6, 3) -+#define PIN_PA31 31 -+#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) -+#define PIN_PA31__G0_TXER PINMUX_PIN(PIN_PA31, 1, 1) -+#define PIN_PA31__FLEXCOM6_IO2 PINMUX_PIN(PIN_PA31, 2, 1) -+#define PIN_PA31__ISC_D11 PINMUX_PIN(PIN_PA31, 3, 1) -+#define PIN_PA31__A17 PINMUX_PIN(PIN_PA31, 4, 1) -+#define PIN_PA31__TD0 PINMUX_PIN(PIN_PA31, 5, 1) -+#define PIN_PA31__FLEXCOM10_IO0 PINMUX_PIN(PIN_PA31, 6, 3) -+#define PIN_PB0 32 -+#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) -+#define PIN_PB0__G0_COL PINMUX_PIN(PIN_PB0, 1, 1) -+#define PIN_PB0__FLEXCOM6_IO3 PINMUX_PIN(PIN_PB0, 2, 2) -+#define PIN_PB0__EXT_IRQ0 PINMUX_PIN(PIN_PB0, 3, 1) -+#define PIN_PB0__A18 PINMUX_PIN(PIN_PB0, 4, 1) -+#define PIN_PB0__SPDIF_RX PINMUX_PIN(PIN_PB0, 5, 2) -+#define PIN_PB0__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB0, 6, 3) -+#define PIN_PB1 33 -+#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) -+#define PIN_PB1__G0_CRS PINMUX_PIN(PIN_PB1, 1, 1) -+#define PIN_PB1__FLEXCOM6_IO1 PINMUX_PIN(PIN_PB1, 2, 2) -+#define PIN_PB1__EXT_IRQ1 PINMUX_PIN(PIN_PB1, 3, 1) -+#define PIN_PB1__A19 PINMUX_PIN(PIN_PB1, 4, 1) -+#define PIN_PB1__SPDIF_TX PINMUX_PIN(PIN_PB1, 5, 2) -+#define PIN_PB1__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB1, 6, 3) -+#define PIN_PB2 34 -+#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) -+#define PIN_PB2__G0_TSUCOMP PINMUX_PIN(PIN_PB2, 1, 1) -+#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1) -+#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1) -+#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1) -+#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3) -+#define PIN_PB3 35 -+#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) -+#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1) -+#define PIN_PB3__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB3, 2, 1) -+#define PIN_PB3__PCK2 PINMUX_PIN(PIN_PB3, 3, 2) -+#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 4, 1) -+#define PIN_PB4 36 -+#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) -+#define PIN_PB4__TF1 PINMUX_PIN(PIN_PB4, 1, 1) -+#define PIN_PB4__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB4, 2, 1) -+#define PIN_PB4__PCK3 PINMUX_PIN(PIN_PB4, 3, 2) -+#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 4, 1) -+#define PIN_PB5 37 -+#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) -+#define PIN_PB5__TK1 PINMUX_PIN(PIN_PB5, 1, 1) -+#define PIN_PB5__FLEXCOM11_IO2 PINMUX_PIN(PIN_PB5, 2, 1) -+#define PIN_PB5__PCK4 PINMUX_PIN(PIN_PB5, 3, 2) -+#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 4, 1) -+#define PIN_PB6 38 -+#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) -+#define PIN_PB6__RK1 PINMUX_PIN(PIN_PB6, 1, 1) -+#define PIN_PB6__FLEXCOM11_IO3 PINMUX_PIN(PIN_PB6, 2, 1) -+#define PIN_PB6__PCK5 PINMUX_PIN(PIN_PB6, 3, 2) -+#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 4, 1) -+#define PIN_PB7 39 -+#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) -+#define PIN_PB7__TD1 PINMUX_PIN(PIN_PB7, 1, 1) -+#define PIN_PB7__FLEXCOM11_IO4 PINMUX_PIN(PIN_PB7, 2, 1) -+#define PIN_PB7__FLEXCOM3_IO5 PINMUX_PIN(PIN_PB7, 3, 2) -+#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 4, 1) -+#define PIN_PB8 40 -+#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) -+#define PIN_PB8__RD1 PINMUX_PIN(PIN_PB8, 1, 1) -+#define PIN_PB8__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB8, 2, 1) -+#define PIN_PB8__FLEXCOM3_IO6 PINMUX_PIN(PIN_PB8, 3, 2) -+#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 4, 1) -+#define PIN_PB9 41 -+#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) -+#define PIN_PB9__QSPI0_IO3 PINMUX_PIN(PIN_PB9, 1, 1) -+#define PIN_PB9__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB9, 2, 1) -+#define PIN_PB9__PDMC0_CLK PINMUX_PIN(PIN_PB9, 3, 1) -+#define PIN_PB9__NCS3_NANDCS PINMUX_PIN(PIN_PB9, 4, 1) -+#define PIN_PB9__PWML0 PINMUX_PIN(PIN_PB9, 5, 2) -+#define PIN_PB10 42 -+#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) -+#define PIN_PB10__QSPI0_IO2 PINMUX_PIN(PIN_PB10, 1, 1) -+#define PIN_PB10__FLEXCOM8_IO2 PINMUX_PIN(PIN_PB10, 2, 1) -+#define PIN_PB10__PDMC0_DS0 PINMUX_PIN(PIN_PB10, 3, 1) -+#define PIN_PB10__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PB10, 4, 1) -+#define PIN_PB10__PWMH0 PINMUX_PIN(PIN_PB10, 5, 2) -+#define PIN_PB11 43 -+#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) -+#define PIN_PB11__QSPI0_IO1 PINMUX_PIN(PIN_PB11, 1, 1) -+#define PIN_PB11__FLEXCOM8_IO3 PINMUX_PIN(PIN_PB11, 2, 1) -+#define PIN_PB11__PDMC0_DS1 PINMUX_PIN(PIN_PB11, 3, 1) -+#define PIN_PB11__NRD_NANDOE PINMUX_PIN(PIN_PB11, 4, 1) -+#define PIN_PB11__PWML1 PINMUX_PIN(PIN_PB11, 5, 2) -+#define PIN_PB12 44 -+#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) -+#define PIN_PB12__QSPI0_IO0 PINMUX_PIN(PIN_PB12, 1, 1) -+#define PIN_PB12__FLEXCOM8_IO4 PINMUX_PIN(PIN_PB12, 2, 1) -+#define PIN_PB12__FLEXCOM6_IO5 PINMUX_PIN(PIN_PB12, 3, 1) -+#define PIN_PB12__A21_NANDALE PINMUX_PIN(PIN_PB12, 4, 1) -+#define PIN_PB12__PWMH1 PINMUX_PIN(PIN_PB12, 5, 2) -+#define PIN_PB13 45 -+#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) -+#define PIN_PB13__QSPI0_CS PINMUX_PIN(PIN_PB13, 1, 1) -+#define PIN_PB13__FLEXCOM9_IO0 PINMUX_PIN(PIN_PB13, 2, 1) -+#define PIN_PB13__FLEXCOM6_IO6 PINMUX_PIN(PIN_PB13, 3, 1) -+#define PIN_PB13__A22_NANDCLE PINMUX_PIN(PIN_PB13, 4, 1) -+#define PIN_PB13__PWML2 PINMUX_PIN(PIN_PB13, 5, 2) -+#define PIN_PB14 46 -+#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) -+#define PIN_PB14__QSPI0_SCK PINMUX_PIN(PIN_PB14, 1, 1) -+#define PIN_PB14__FLEXCOM9_IO1 PINMUX_PIN(PIN_PB14, 2, 1) -+#define PIN_PB14__D0 PINMUX_PIN(PIN_PB14, 4, 1) -+#define PIN_PB14__PWMH2 PINMUX_PIN(PIN_PB14, 5, 2) -+#define PIN_PB15 47 -+#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) -+#define PIN_PB15__QSPI0_SCKN PINMUX_PIN(PIN_PB15, 1, 1) -+#define PIN_PB15__FLEXCOM9_IO2 PINMUX_PIN(PIN_PB15, 2, 1) -+#define PIN_PB15__D1 PINMUX_PIN(PIN_PB15, 4, 1) -+#define PIN_PB15__PWML3 PINMUX_PIN(PIN_PB15, 5, 2) -+#define PIN_PB16 48 -+#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) -+#define PIN_PB16__QSPI0_IO4 PINMUX_PIN(PIN_PB16, 1, 1) -+#define PIN_PB16__FLEXCOM9_IO3 PINMUX_PIN(PIN_PB16, 2, 1) -+#define PIN_PB16__PCK0 PINMUX_PIN(PIN_PB16, 3, 1) -+#define PIN_PB16__D2 PINMUX_PIN(PIN_PB16, 4, 1) -+#define PIN_PB16__PWMH3 PINMUX_PIN(PIN_PB16, 5, 2) -+#define PIN_PB16__EXT_IRQ0 PINMUX_PIN(PIN_PB16, 6, 2) -+#define PIN_PB17 49 -+#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) -+#define PIN_PB17__QSPI0_IO5 PINMUX_PIN(PIN_PB17, 1, 1) -+#define PIN_PB17__FLEXCOM9_IO4 PINMUX_PIN(PIN_PB17, 2, 1) -+#define PIN_PB17__PCK1 PINMUX_PIN(PIN_PB17, 3, 1) -+#define PIN_PB17__D3 PINMUX_PIN(PIN_PB17, 4, 1) -+#define PIN_PB17__PWMEXTRG0 PINMUX_PIN(PIN_PB17, 5, 2) -+#define PIN_PB17__EXT_IRQ1 PINMUX_PIN(PIN_PB17, 6, 2) -+#define PIN_PB18 50 -+#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) -+#define PIN_PB18__QSPI0_IO6 PINMUX_PIN(PIN_PB18, 1, 1) -+#define PIN_PB18__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB18, 2, 1) -+#define PIN_PB18__PCK2 PINMUX_PIN(PIN_PB18, 3, 1) -+#define PIN_PB18__D4 PINMUX_PIN(PIN_PB18, 4, 1) -+#define PIN_PB18__PWMEXTRG1 PINMUX_PIN(PIN_PB18, 5, 2) -+#define PIN_PB19 51 -+#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) -+#define PIN_PB19__QSPI0_IO7 PINMUX_PIN(PIN_PB19, 1, 1) -+#define PIN_PB19__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB19, 2, 1) -+#define PIN_PB19__PCK3 PINMUX_PIN(PIN_PB19, 3, 1) -+#define PIN_PB19__D5 PINMUX_PIN(PIN_PB19, 4, 1) -+#define PIN_PB19__PWMFI0 PINMUX_PIN(PIN_PB19, 5, 2) -+#define PIN_PB20 52 -+#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) -+#define PIN_PB20__QSPI0_DQS PINMUX_PIN(PIN_PB20, 1, 1) -+#define PIN_PB20__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB20, 2, 1) -+#define PIN_PB20__D6 PINMUX_PIN(PIN_PB20, 4, 1) -+#define PIN_PB20__PWMFI1 PINMUX_PIN(PIN_PB20, 5, 2) -+#define PIN_PB21 53 -+#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) -+#define PIN_PB21__QSPI0_INT PINMUX_PIN(PIN_PB21, 1, 1) -+#define PIN_PB21__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB21, 2, 1) -+#define PIN_PB21__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB21, 3, 1) -+#define PIN_PB21__D7 PINMUX_PIN(PIN_PB21, 4, 1) -+#define PIN_PB22 54 -+#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) -+#define PIN_PB22__QSPI1_IO3 PINMUX_PIN(PIN_PB22, 1, 1) -+#define PIN_PB22__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB22, 2, 1) -+#define PIN_PB22__FLEXCOM9_IO6 PINMUX_PIN(PIN_PB22, 3, 1) -+#define PIN_PB22__NANDRDY PINMUX_PIN(PIN_PB22, 4, 1) -+#define PIN_PB23 55 -+#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) -+#define PIN_PB23__QSPI1_IO2 PINMUX_PIN(PIN_PB23, 1, 1) -+#define PIN_PB23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB23, 2, 1) -+#define PIN_PB23__I2SMCC0_CK PINMUX_PIN(PIN_PB23, 3, 1) -+#define PIN_PB23__PCK4 PINMUX_PIN(PIN_PB23, 6, 1) -+#define PIN_PB24 56 -+#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) -+#define PIN_PB24__QSPI1_IO1 PINMUX_PIN(PIN_PB24, 1, 1) -+#define PIN_PB24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB24, 2, 1) -+#define PIN_PB24__I2SMCC0_WS PINMUX_PIN(PIN_PB24, 3, 1) -+#define PIN_PB24__PCK5 PINMUX_PIN(PIN_PB24, 6, 1) -+#define PIN_PB25 57 -+#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) -+#define PIN_PB25__QSPI1_IO0 PINMUX_PIN(PIN_PB25, 1, 1) -+#define PIN_PB25__FLEXCOM7_IO2 PINMUX_PIN(PIN_PB25, 2, 1) -+#define PIN_PB25__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PB25, 3, 1) -+#define PIN_PB25__PCK6 PINMUX_PIN(PIN_PB25, 6, 1) -+#define PIN_PB26 58 -+#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) -+#define PIN_PB26__QSPI1_CS PINMUX_PIN(PIN_PB26, 1, 1) -+#define PIN_PB26__FLEXCOM7_IO3 PINMUX_PIN(PIN_PB26, 2, 1) -+#define PIN_PB26__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PB26, 3, 1) -+#define PIN_PB26__PWMEXTRG0 PINMUX_PIN(PIN_PB26, 5, 1) -+#define PIN_PB26__PCK7 PINMUX_PIN(PIN_PB26, 6, 1) -+#define PIN_PB27 59 -+#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) -+#define PIN_PB27__QSPI1_SCK PINMUX_PIN(PIN_PB27, 1, 1) -+#define PIN_PB27__FLEXCOM7_IO4 PINMUX_PIN(PIN_PB27, 2, 1) -+#define PIN_PB27__I2SMCC0_MCK PINMUX_PIN(PIN_PB27, 3, 1) -+#define PIN_PB27__PWMEXTRG1 PINMUX_PIN(PIN_PB27, 5, 1) -+#define PIN_PB28 60 -+#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) -+#define PIN_PB28__SDMMC1_RSTN PINMUX_PIN(PIN_PB28, 1, 1) -+#define PIN_PB28__ADTRG PINMUX_PIN(PIN_PB28, 2, 2) -+#define PIN_PB28__PWMFI0 PINMUX_PIN(PIN_PB28, 5, 1) -+#define PIN_PB28__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB28, 6, 4) -+#define PIN_PB29 61 -+#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) -+#define PIN_PB29__SDMMC1_CMD PINMUX_PIN(PIN_PB29, 1, 1) -+#define PIN_PB29__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB29, 2, 2) -+#define PIN_PB29__FLEXCOM0_IO5 PINMUX_PIN(PIN_PB29, 3, 2) -+#define PIN_PB29__TIOA3 PINMUX_PIN(PIN_PB29, 4, 2) -+#define PIN_PB29__PWMFI1 PINMUX_PIN(PIN_PB29, 5, 1) -+#define PIN_PB29__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB29, 6, 4) -+#define PIN_PB30 62 -+#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) -+#define PIN_PB30__SDMMC1_CK PINMUX_PIN(PIN_PB30, 1, 1) -+#define PIN_PB30__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB30, 2, 2) -+#define PIN_PB30__FLEXCOM0_IO6 PINMUX_PIN(PIN_PB30, 3, 2) -+#define PIN_PB30__TIOB3 PINMUX_PIN(PIN_PB30, 4, 1) -+#define PIN_PB30__PWMH0 PINMUX_PIN(PIN_PB30, 5, 1) -+#define PIN_PB30__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB30, 6, 4) -+#define PIN_PB31 63 -+#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) -+#define PIN_PB31__SDMMC1_DAT0 PINMUX_PIN(PIN_PB31, 1, 1) -+#define PIN_PB31__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB31, 2, 2) -+#define PIN_PB31__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB31, 3, 2) -+#define PIN_PB31__TCLK3 PINMUX_PIN(PIN_PB31, 4, 1) -+#define PIN_PB31__PWML0 PINMUX_PIN(PIN_PB31, 5, 1) -+#define PIN_PB31__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB31, 6, 4) -+#define PIN_PC0 64 -+#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) -+#define PIN_PC0__SDMMC1_DAT1 PINMUX_PIN(PIN_PC0, 1, 1) -+#define PIN_PC0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC0, 2, 2) -+#define PIN_PC0__TIOA4 PINMUX_PIN(PIN_PC0, 4, 1) -+#define PIN_PC0__PWML1 PINMUX_PIN(PIN_PC0, 5, 1) -+#define PIN_PC0__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC0, 6, 4) -+#define PIN_PC1 65 -+#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) -+#define PIN_PC1__SDMMC1_DAT2 PINMUX_PIN(PIN_PC1, 1, 1) -+#define PIN_PC1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC1, 2, 2) -+#define PIN_PC1__TIOB4 PINMUX_PIN(PIN_PC1, 4, 1) -+#define PIN_PC1__PWMH1 PINMUX_PIN(PIN_PC1, 5, 1) -+#define PIN_PC1__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC1, 6, 4) -+#define PIN_PC2 66 -+#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) -+#define PIN_PC2__SDMMC1_DAT3 PINMUX_PIN(PIN_PC2, 1, 1) -+#define PIN_PC2__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC2, 2, 2) -+#define PIN_PC2__TCLK4 PINMUX_PIN(PIN_PC2, 4, 1) -+#define PIN_PC2__PWML2 PINMUX_PIN(PIN_PC2, 5, 1) -+#define PIN_PC2__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC2, 6, 4) -+#define PIN_PC3 67 -+#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) -+#define PIN_PC3__SDMMC1_WP PINMUX_PIN(PIN_PC3, 1, 1) -+#define PIN_PC3__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC3, 2, 2) -+#define PIN_PC3__TIOA5 PINMUX_PIN(PIN_PC3, 4, 1) -+#define PIN_PC3__PWMH2 PINMUX_PIN(PIN_PC3, 5, 1) -+#define PIN_PC3__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC3, 6, 4) -+#define PIN_PC4 68 -+#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) -+#define PIN_PC4__SDMMC1_CD PINMUX_PIN(PIN_PC4, 1, 1) -+#define PIN_PC4__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC4, 2, 2) -+#define PIN_PC4__FLEXCOM9_IO6 PINMUX_PIN(PIN_PC4, 3, 2) -+#define PIN_PC4__TIOB5 PINMUX_PIN(PIN_PC4, 4, 1) -+#define PIN_PC4__PWML3 PINMUX_PIN(PIN_PC4, 5, 1) -+#define PIN_PC4__FLEXCOM11_IO0 PINMUX_PIN(PIN_PC4, 6, 4) -+#define PIN_PC5 69 -+#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) -+#define PIN_PC5__SDMMC1_1V8SEL PINMUX_PIN(PIN_PC5, 1, 1) -+#define PIN_PC5__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC5, 2, 2) -+#define PIN_PC5__FLEXCOM6_IO5 PINMUX_PIN(PIN_PC5, 3, 2) -+#define PIN_PC5__TCLK5 PINMUX_PIN(PIN_PC5, 4, 1) -+#define PIN_PC5__PWMH3 PINMUX_PIN(PIN_PC5, 5, 1) -+#define PIN_PC5__FLEXCOM11_IO1 PINMUX_PIN(PIN_PC5, 6, 4) -+#define PIN_PC6 70 -+#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) -+#define PIN_PC6__FLEXCOM4_IO4 PINMUX_PIN(PIN_PC6, 2, 2) -+#define PIN_PC6__FLEXCOM6_IO6 PINMUX_PIN(PIN_PC6, 3, 2) -+#define PIN_PC7 71 -+#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) -+#define PIN_PC7__I2SMCC0_DIN0 PINMUX_PIN(PIN_PC7, 1, 1) -+#define PIN_PC7__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC7, 2, 2) -+#define PIN_PC8 72 -+#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) -+#define PIN_PC8__I2SMCC0_DIN1 PINMUX_PIN(PIN_PC8, 1, 1) -+#define PIN_PC8__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC8, 2, 2) -+#define PIN_PC9 73 -+#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) -+#define PIN_PC9__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PC9, 1, 1) -+#define PIN_PC9__FLEXCOM7_IO2 PINMUX_PIN(PIN_PC9, 2, 2) -+#define PIN_PC9__FLEXCOM1_IO0 PINMUX_PIN(PIN_PC9, 6, 4) -+#define PIN_PC10 74 -+#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) -+#define PIN_PC10__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PC10, 1, 1) -+#define PIN_PC10__FLEXCOM7_IO3 PINMUX_PIN(PIN_PC10, 2, 2) -+#define PIN_PC10__FLEXCOM1_IO1 PINMUX_PIN(PIN_PC10, 6, 4) -+#define PIN_PC11 75 -+#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) -+#define PIN_PC11__I2SMCC1_CK PINMUX_PIN(PIN_PC11, 1, 1) -+#define PIN_PC11__FLEXCOM7_IO4 PINMUX_PIN(PIN_PC11, 2, 2) -+#define PIN_PC11__FLEXCOM2_IO0 PINMUX_PIN(PIN_PC11, 6, 4) -+#define PIN_PC12 76 -+#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) -+#define PIN_PC12__I2SMCC1_WS PINMUX_PIN(PIN_PC12, 1, 1) -+#define PIN_PC12__FLEXCOM8_IO2 PINMUX_PIN(PIN_PC12, 2, 2) -+#define PIN_PC12__FLEXCOM2_IO1 PINMUX_PIN(PIN_PC12, 6, 4) -+#define PIN_PC13 77 -+#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) -+#define PIN_PC13__I2SMCC1_MCK PINMUX_PIN(PIN_PC13, 1, 1) -+#define PIN_PC13__FLEXCOM8_IO1 PINMUX_PIN(PIN_PC13, 2, 2) -+#define PIN_PC13__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC13, 6, 4) -+#define PIN_PC14 78 -+#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) -+#define PIN_PC14__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PC14, 1, 1) -+#define PIN_PC14__FLEXCOM8_IO0 PINMUX_PIN(PIN_PC14, 2, 2) -+#define PIN_PC14__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC14, 6, 4) -+#define PIN_PC15 79 -+#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) -+#define PIN_PC15__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PC15, 1, 1) -+#define PIN_PC15__FLEXCOM8_IO3 PINMUX_PIN(PIN_PC15, 2, 2) -+#define PIN_PC15__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC15, 6, 4) -+#define PIN_PC16 80 -+#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) -+#define PIN_PC16__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PC16, 1, 1) -+#define PIN_PC16__FLEXCOM8_IO4 PINMUX_PIN(PIN_PC16, 2, 2) -+#define PIN_PC16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC16, 6, 4) -+#define PIN_PC17 81 -+#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) -+#define PIN_PC17__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PC17, 1, 1) -+#define PIN_PC17__EXT_IRQ0 PINMUX_PIN(PIN_PC17, 2, 3) -+#define PIN_PC17__FLEXCOM5_IO0 PINMUX_PIN(PIN_PC17, 6, 4) -+#define PIN_PC18 82 -+#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) -+#define PIN_PC18__I2SMCC1_DIN0 PINMUX_PIN(PIN_PC18, 1, 1) -+#define PIN_PC18__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC18, 2, 2) -+#define PIN_PC18__FLEXCOM5_IO1 PINMUX_PIN(PIN_PC18, 6, 4) -+#define PIN_PC19 83 -+#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) -+#define PIN_PC19__I2SMCC1_DIN1 PINMUX_PIN(PIN_PC19, 1, 1) -+#define PIN_PC19__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC19, 2, 2) -+#define PIN_PC19__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC19, 6, 4) -+#define PIN_PC20 84 -+#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) -+#define PIN_PC20__I2SMCC1_DIN2 PINMUX_PIN(PIN_PC20, 1, 1) -+#define PIN_PC20__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC20, 2, 2) -+#define PIN_PC20__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC20, 6, 4) -+#define PIN_PC21 85 -+#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) -+#define PIN_PC21__I2SMCC1_DIN3 PINMUX_PIN(PIN_PC21, 1, 1) -+#define PIN_PC21__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC21, 2, 2) -+#define PIN_PC21__D3 PINMUX_PIN(PIN_PC21, 4, 2) -+#define PIN_PC21__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC21, 6, 5) -+#define PIN_PC22 86 -+#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) -+#define PIN_PC22__I2SMCC0_DIN2 PINMUX_PIN(PIN_PC22, 1, 1) -+#define PIN_PC22__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC22, 2, 2) -+#define PIN_PC22__D4 PINMUX_PIN(PIN_PC22, 4, 2) -+#define PIN_PC22__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC22, 6, 5) -+#define PIN_PC23 87 -+#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) -+#define PIN_PC23__I2SMCC0_DIN3 PINMUX_PIN(PIN_PC23, 1, 1) -+#define PIN_PC23__FLEXCOM0_IO5 PINMUX_PIN(PIN_PC23, 2, 3) -+#define PIN_PC23__D5 PINMUX_PIN(PIN_PC23, 4, 2) -+#define PIN_PC23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC23, 6, 5) -+#define PIN_PC24 88 -+#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) -+#define PIN_PC24__FLEXCOM0_IO6 PINMUX_PIN(PIN_PC24, 2, 3) -+#define PIN_PC24__EXT_IRQ1 PINMUX_PIN(PIN_PC24, 3, 3) -+#define PIN_PC24__D6 PINMUX_PIN(PIN_PC24, 4, 2) -+#define PIN_PC24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC24, 6, 5) -+#define PIN_PC25 89 -+#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) -+#define PIN_PC25__NTRST PINMUX_PIN(PIN_PC25, 1, 1) -+#define PIN_PC26 90 -+#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) -+#define PIN_PC26__TCK_SWCLK PINMUX_PIN(PIN_PC26, 1, 1) -+#define PIN_PC27 91 -+#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) -+#define PIN_PC27__TMS_SWDIO PINMUX_PIN(PIN_PC27, 1, 1) -+#define PIN_PC28 92 -+#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) -+#define PIN_PC28__TDI PINMUX_PIN(PIN_PC28, 1, 1) -+#define PIN_PC29 93 -+#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) -+#define PIN_PC29__TDO PINMUX_PIN(PIN_PC29, 1, 1) -+#define PIN_PC30 94 -+#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) -+#define PIN_PC30__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC30, 2, 2) -+#define PIN_PC31 95 -+#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) -+#define PIN_PC31__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC31, 2, 2) -+#define PIN_PD0 96 -+#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) -+#define PIN_PD0__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD0, 2, 2) -+#define PIN_PD1 97 -+#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) -+#define PIN_PD1__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD1, 2, 2) -+#define PIN_PD2 98 -+#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) -+#define PIN_PD2__SDMMC2_RSTN PINMUX_PIN(PIN_PD2, 1, 1) -+#define PIN_PD2__PCK0 PINMUX_PIN(PIN_PD2, 2, 2) -+#define PIN_PD2__CANTX4 PINMUX_PIN(PIN_PD2, 3, 1) -+#define PIN_PD2__D7 PINMUX_PIN(PIN_PD2, 4, 2) -+#define PIN_PD2__TIOA0 PINMUX_PIN(PIN_PD2, 5, 2) -+#define PIN_PD2__FLEXCOM8_IO0 PINMUX_PIN(PIN_PD2, 6, 5) -+#define PIN_PD3 99 -+#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) -+#define PIN_PD3__SDMMC2_CMD PINMUX_PIN(PIN_PD3, 1, 1) -+#define PIN_PD3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD3, 2, 2) -+#define PIN_PD3__CANRX4 PINMUX_PIN(PIN_PD3, 3, 1) -+#define PIN_PD3__NANDRDY PINMUX_PIN(PIN_PD3, 4, 2) -+#define PIN_PD3__TIOB0 PINMUX_PIN(PIN_PD3, 5, 2) -+#define PIN_PD3__FLEXCOM8_IO1 PINMUX_PIN(PIN_PD3, 6, 5) -+#define PIN_PD4 100 -+#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) -+#define PIN_PD4__SDMMC2_CK PINMUX_PIN(PIN_PD4, 1, 1) -+#define PIN_PD4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD4, 2, 2) -+#define PIN_PD4__CANTX5 PINMUX_PIN(PIN_PD4, 3, 1) -+#define PIN_PD4__NCS3_NANDCS PINMUX_PIN(PIN_PD4, 4, 2) -+#define PIN_PD4__TCLK0 PINMUX_PIN(PIN_PD4, 5, 2) -+#define PIN_PD4__FLEXCOM9_IO0 PINMUX_PIN(PIN_PD4, 6, 5) -+#define PIN_PD5 101 -+#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) -+#define PIN_PD5__SDMMC2_DAT0 PINMUX_PIN(PIN_PD5, 1, 1) -+#define PIN_PD5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PD5, 2, 2) -+#define PIN_PD5__CANRX5 PINMUX_PIN(PIN_PD5, 3, 1) -+#define PIN_PD5__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PD5, 4, 2) -+#define PIN_PD5__TIOA1 PINMUX_PIN(PIN_PD5, 5, 2) -+#define PIN_PD5__FLEXCOM9_IO1 PINMUX_PIN(PIN_PD5, 6, 5) -+#define PIN_PD6 102 -+#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) -+#define PIN_PD6__SDMMC2_DAT1 PINMUX_PIN(PIN_PD6, 1, 1) -+#define PIN_PD6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PD6, 2, 2) -+#define PIN_PD6__SPDIF_RX PINMUX_PIN(PIN_PD6, 3, 3) -+#define PIN_PD6__NRD_NANDOE PINMUX_PIN(PIN_PD6, 4, 2) -+#define PIN_PD6__TIOB1 PINMUX_PIN(PIN_PD6, 5, 2) -+#define PIN_PD6__FLEXCOM10_IO0 PINMUX_PIN(PIN_PD6, 6, 5) -+#define PIN_PD7 103 -+#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) -+#define PIN_PD7__SDMMC2_DAT2 PINMUX_PIN(PIN_PD7, 1, 1) -+#define PIN_PD7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PD7, 2, 2) -+#define PIN_PD7__SPDIF_TX PINMUX_PIN(PIN_PD7, 2, 2) -+#define PIN_PD7__A21_NANDALE PINMUX_PIN(PIN_PD7, 4, 2) -+#define PIN_PD7__TCLK1 PINMUX_PIN(PIN_PD7, 5, 2) -+#define PIN_PD7__FLEXCOM10_IO1 PINMUX_PIN(PIN_PD7, 6, 5) -+#define PIN_PD8 104 -+#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) -+#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1) -+#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1) -+#define PIN_PD8__A11_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) -+#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2) -+#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5) -+#define PIN_PD9 105 -+#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) -+#define PIN_PD9__SDMMC2_WP PINMUX_PIN(PIN_PD9, 1, 1) -+#define PIN_PD9__I2SMCC0_DIN1 PINMUX_PIN(PIN_PD9, 3, 2) -+#define PIN_PD9__D0 PINMUX_PIN(PIN_PD9, 4, 2) -+#define PIN_PD9__TIOB2 PINMUX_PIN(PIN_PD9, 5, 2) -+#define PIN_PD9__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD9, 6, 5) -+#define PIN_PD10 106 -+#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) -+#define PIN_PD10__SDMMC2_CD PINMUX_PIN(PIN_PD10, 1, 1) -+#define PIN_PD10__PCK6 PINMUX_PIN(PIN_PD10, 2, 2) -+#define PIN_PD10__I2SMCC0_DIN2 PINMUX_PIN(PIN_PD10, 3, 2) -+#define PIN_PD10__D1 PINMUX_PIN(PIN_PD10, 4, 2) -+#define PIN_PD10__TCLK2 PINMUX_PIN(PIN_PD10, 5, 2) -+#define PIN_PD10__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD10, 6, 3) -+#define PIN_PD11 107 -+#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) -+#define PIN_PD11__SDMMC2_1V8SEL PINMUX_PIN(PIN_PD11, 1, 1) -+#define PIN_PD11__PCK7 PINMUX_PIN(PIN_PD11, 2, 2) -+#define PIN_PD11__I2SMCC0_DIN3 PINMUX_PIN(PIN_PD11, 3, 2) -+#define PIN_PD11__D2 PINMUX_PIN(PIN_PD11, 4, 2) -+#define PIN_PD11__TIOA3 PINMUX_PIN(PIN_PD11, 5, 2) -+#define PIN_PD11__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD11, 6, 3) -+#define PIN_PD12 108 -+#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) -+#define PIN_PD12__PCK1 PINMUX_PIN(PIN_PD12, 1, 2) -+#define PIN_PD12__FLEXCOM1_IO0 PINMUX_PIN(PIN_PD12, 2, 2) -+#define PIN_PD12__CANTX0 PINMUX_PIN(PIN_PD12, 4, 2) -+#define PIN_PD12__TIOB3 PINMUX_PIN(PIN_PD12, 5, 2) -+#define PIN_PD13 109 -+#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) -+#define PIN_PD13__I2SMCC0_CK PINMUX_PIN(PIN_PD13, 1, 2) -+#define PIN_PD13__FLEXCOM1_IO1 PINMUX_PIN(PIN_PD13, 2, 2) -+#define PIN_PD13__PWML0 PINMUX_PIN(PIN_PD13, 3, 4) -+#define PIN_PD13__CANRX0 PINMUX_PIN(PIN_PD13, 4, 2) -+#define PIN_PD13__TCLK3 PINMUX_PIN(PIN_PD13, 5, 2) -+#define PIN_PD14 110 -+#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) -+#define PIN_PD14__I2SMCC0_MCK PINMUX_PIN(PIN_PD14, 1, 2) -+#define PIN_PD14__FLEXCOM1_IO2 PINMUX_PIN(PIN_PD14, 2, 2) -+#define PIN_PD14__PWMH0 PINMUX_PIN(PIN_PD14, 3, 4) -+#define PIN_PD14__CANTX1 PINMUX_PIN(PIN_PD14, 4, 2) -+#define PIN_PD14__TIOA4 PINMUX_PIN(PIN_PD14, 5, 2) -+#define PIN_PD14__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD14, 6, 5) -+#define PIN_PD15 111 -+#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) -+#define PIN_PD15__I2SMCC0_WS PINMUX_PIN(PIN_PD15, 1, 2) -+#define PIN_PD15__FLEXCOM1_IO3 PINMUX_PIN(PIN_PD15, 2, 2) -+#define PIN_PD15__PWML1 PINMUX_PIN(PIN_PD15, 3, 4) -+#define PIN_PD15__CANRX1 PINMUX_PIN(PIN_PD15, 4, 2) -+#define PIN_PD15__TIOB4 PINMUX_PIN(PIN_PD15, 5, 2) -+#define PIN_PD15__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD15, 6, 5) -+#define PIN_PD16 112 -+#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) -+#define PIN_PD16__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PD16, 1, 2) -+#define PIN_PD16__FLEXCOM1_IO4 PINMUX_PIN(PIN_PD16, 2, 2) -+#define PIN_PD16__PWMH1 PINMUX_PIN(PIN_PD16, 3, 4) -+#define PIN_PD16__CANTX2 PINMUX_PIN(PIN_PD16, 4, 2) -+#define PIN_PD16__TCLK4 PINMUX_PIN(PIN_PD16, 5, 2) -+#define PIN_PD16__FLEXCOM3_IO0 PINMUX_PIN(PIN_PD16, 6, 5) -+#define PIN_PD17 113 -+#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) -+#define PIN_PD17__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PD17, 1, 2) -+#define PIN_PD17__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD17, 2, 2) -+#define PIN_PD17__PWML2 PINMUX_PIN(PIN_PD17, 3, 4) -+#define PIN_PD17__CANRX2 PINMUX_PIN(PIN_PD17, 4, 2) -+#define PIN_PD17__TIOA5 PINMUX_PIN(PIN_PD17, 5, 2) -+#define PIN_PD17__FLEXCOM3_IO1 PINMUX_PIN(PIN_PD17, 6, 5) -+#define PIN_PD18 114 -+#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) -+#define PIN_PD18__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PD18, 1, 2) -+#define PIN_PD18__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD18, 2, 2) -+#define PIN_PD18__PWMH2 PINMUX_PIN(PIN_PD18, 3, 4) -+#define PIN_PD18__CANTX3 PINMUX_PIN(PIN_PD18, 4, 2) -+#define PIN_PD18__TIOB5 PINMUX_PIN(PIN_PD18, 5, 2) -+#define PIN_PD18__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD18, 6, 5) -+#define PIN_PD19 115 -+#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) -+#define PIN_PD19__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PD19, 1, 2) -+#define PIN_PD19__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD19, 2, 2) -+#define PIN_PD19__PWML3 PINMUX_PIN(PIN_PD19, 3, 4) -+#define PIN_PD19__CANRX3 PINMUX_PIN(PIN_PD19, 4, 2) -+#define PIN_PD19__TCLK5 PINMUX_PIN(PIN_PD19, 5, 2) -+#define PIN_PD19__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD19, 6, 5) -+#define PIN_PD20 116 -+#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) -+#define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) -+#define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) -+#define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) -+#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 5, 2) -+#define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) -+#define PIN_PD21 117 -+#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) -+#define PIN_PD21__PCK1 PINMUX_PIN(PIN_PD21, 1, 3) -+#define PIN_PD21__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD21, 2, 2) -+#define PIN_PD21__CANRX4 PINMUX_PIN(PIN_PD21, 4, 2) -+#define PIN_PD21__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD21, 6, 5) -+#define PIN_PD21__G1_TXEN PINMUX_PIN(PIN_PD21, 7, 1) -+#define PIN_PD22 118 -+#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) -+#define PIN_PD22__PDMC0_CLK PINMUX_PIN(PIN_PD22, 1, 2) -+#define PIN_PD22__PWMEXTRG0 PINMUX_PIN(PIN_PD22, 3, 4) -+#define PIN_PD22__RD1 PINMUX_PIN(PIN_PD22, 4, 2) -+#define PIN_PD22__CANTX5 PINMUX_PIN(PIN_PD22, 6, 2) -+#define PIN_PD22__G1_TX0 PINMUX_PIN(PIN_PD22, 7, 1) -+#define PIN_PD23 119 -+#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) -+#define PIN_PD23__PDMC0_DS0 PINMUX_PIN(PIN_PD23, 1, 2) -+#define PIN_PD23__PWMEXTRG1 PINMUX_PIN(PIN_PD23, 3, 4) -+#define PIN_PD23__RF1 PINMUX_PIN(PIN_PD23, 4, 2) -+#define PIN_PD23__ISC_MCK PINMUX_PIN(PIN_PD23, 5, 2) -+#define PIN_PD23__CANRX5 PINMUX_PIN(PIN_PD23, 6, 2) -+#define PIN_PD23__G1_TX1 PINMUX_PIN(PIN_PD23, 7, 1) -+#define PIN_PD24 120 -+#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) -+#define PIN_PD24__PDMC0_DS1 PINMUX_PIN(PIN_PD24, 1, 2) -+#define PIN_PD24__PWMFI0 PINMUX_PIN(PIN_PD24, 3, 4) -+#define PIN_PD24__RK1 PINMUX_PIN(PIN_PD24, 4, 2) -+#define PIN_PD24__ISC_D0 PINMUX_PIN(PIN_PD24, 5, 2) -+#define PIN_PD24__G1_RXDV PINMUX_PIN(PIN_PD24, 7, 1) -+#define PIN_PD25 121 -+#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) -+#define PIN_PD25__PDMC1_CLK PINMUX_PIN(PIN_PD25, 1, 2) -+#define PIN_PD25__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD25, 2, 2) -+#define PIN_PD25__PWMFI1 PINMUX_PIN(PIN_PD25, 3, 4) -+#define PIN_PD25__TD1 PINMUX_PIN(PIN_PD25, 4, 2) -+#define PIN_PD25__ISC_D1 PINMUX_PIN(PIN_PD25, 5, 2) -+#define PIN_PD25__G1_RX0 PINMUX_PIN(PIN_PD25, 7, 1) -+#define PIN_PD26 122 -+#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) -+#define PIN_PD26__PDMC1_DS0 PINMUX_PIN(PIN_PD26, 1, 2) -+#define PIN_PD26__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD26, 2, 2) -+#define PIN_PD26__ADTRG PINMUX_PIN(PIN_PD26, 3, 3) -+#define PIN_PD26__TF1 PINMUX_PIN(PIN_PD26, 4, 2) -+#define PIN_PD26__ISC_D2 PINMUX_PIN(PIN_PD26, 5, 2) -+#define PIN_PD26__G1_RX1 PINMUX_PIN(PIN_PD26, 7, 1) -+#define PIN_PD27 123 -+#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) -+#define PIN_PD27__PDMC1_DS1 PINMUX_PIN(PIN_PD27, 1, 2) -+#define PIN_PD27__FLEXCOM5_IO2 PINMUX_PIN(PIN_PD27, 2, 2) -+#define PIN_PD27__TIOA0 PINMUX_PIN(PIN_PD27, 3, 3) -+#define PIN_PD27__TK1 PINMUX_PIN(PIN_PD27, 4, 2) -+#define PIN_PD27__ISC_D3 PINMUX_PIN(PIN_PD27, 5, 2) -+#define PIN_PD27__G1_RXER PINMUX_PIN(PIN_PD27, 7, 1) -+#define PIN_PD28 124 -+#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) -+#define PIN_PD28__RD0 PINMUX_PIN(PIN_PD28, 1, 2) -+#define PIN_PD28__FLEXCOM5_IO3 PINMUX_PIN(PIN_PD28, 2, 2) -+#define PIN_PD28__TIOB0 PINMUX_PIN(PIN_PD28, 3, 3) -+#define PIN_PD28__I2SMCC1_CK PINMUX_PIN(PIN_PD28, 4, 2) -+#define PIN_PD28__ISC_D4 PINMUX_PIN(PIN_PD28, 5, 2) -+#define PIN_PD28__PWML3 PINMUX_PIN(PIN_PD28, 6, 5) -+#define PIN_PD28__G1_MDC PINMUX_PIN(PIN_PD28, 7, 1) -+#define PIN_PD29 125 -+#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) -+#define PIN_PD29__RF0 PINMUX_PIN(PIN_PD29, 1, 2) -+#define PIN_PD29__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD29, 2, 2) -+#define PIN_PD29__TCLK0 PINMUX_PIN(PIN_PD29, 3, 3) -+#define PIN_PD29__I2SMCC1_WS PINMUX_PIN(PIN_PD29, 4, 2) -+#define PIN_PD29__ISC_D5 PINMUX_PIN(PIN_PD29, 5, 2) -+#define PIN_PD29__PWMH3 PINMUX_PIN(PIN_PD29, 6, 5) -+#define PIN_PD29__G1_MDIO PINMUX_PIN(PIN_PD29, 7, 1) -+#define PIN_PD30 126 -+#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) -+#define PIN_PD30__RK0 PINMUX_PIN(PIN_PD30, 1, 2) -+#define PIN_PD30__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD30, 2, 2) -+#define PIN_PD30__TIOA1 PINMUX_PIN(PIN_PD30, 3, 3) -+#define PIN_PD30__I2SMCC1_MCK PINMUX_PIN(PIN_PD30, 4, 2) -+#define PIN_PD30__ISC_D6 PINMUX_PIN(PIN_PD30, 5, 2) -+#define PIN_PD30__PWMEXTRG0 PINMUX_PIN(PIN_PD30, 6, 5) -+#define PIN_PD30__G1_TXCK PINMUX_PIN(PIN_PD30, 7, 1) -+#define PIN_PD31 127 -+#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) -+#define PIN_PD31__TD0 PINMUX_PIN(PIN_PD31, 1, 2) -+#define PIN_PD31__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD31, 2, 2) -+#define PIN_PD31__TIOB1 PINMUX_PIN(PIN_PD31, 3, 3) -+#define PIN_PD31__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PD31, 4, 2) -+#define PIN_PD31__ISC_D7 PINMUX_PIN(PIN_PD31, 5, 2) -+#define PIN_PD31__PWM_EXTRG1 PINMUX_PIN(PIN_PD31, 6, 5) -+#define PIN_PD31__G1_TX2 PINMUX_PIN(PIN_PD31, 7, 1) -+#define PIN_PE0 128 -+#define PIN_PE0__GPIO PINMUX_PIN(PIN_PE0, 0, 0) -+#define PIN_PE0__TF0 PINMUX_PIN(PIN_PE0, 1, 2) -+#define PIN_PE0__FLEXCOM6_IO2 PINMUX_PIN(PIN_PE0, 2, 2) -+#define PIN_PE0__TCLK1 PINMUX_PIN(PIN_PE0, 3, 3) -+#define PIN_PE0__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PE0, 4, 2) -+#define PIN_PE0__ISC_HSYNC PINMUX_PIN(PIN_PE0, 5, 2) -+#define PIN_PE0__PWMFI0 PINMUX_PIN(PIN_PE0, 6, 5) -+#define PIN_PE0__G1_TX3 PINMUX_PIN(PIN_PE0, 7, 1) -+#define PIN_PE1 129 -+#define PIN_PE1__GPIO PINMUX_PIN(PIN_PE1, 0, 0) -+#define PIN_PE1__TK0 PINMUX_PIN(PIN_PE1, 1, 2) -+#define PIN_PE1__FLEXCOM6_IO3 PINMUX_PIN(PIN_PE1, 2, 2) -+#define PIN_PE1__TIOA2 PINMUX_PIN(PIN_PE1, 3, 3) -+#define PIN_PE1__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PE1, 4, 2) -+#define PIN_PE1__ISC_VSYNC PINMUX_PIN(PIN_PE1, 5, 2) -+#define PIN_PE1__PWMFI1 PINMUX_PIN(PIN_PE1, 6, 5) -+#define PIN_PE1__G1_RX2 PINMUX_PIN(PIN_PE1, 7, 1) -+#define PIN_PE2 130 -+#define PIN_PE2__GPIO PINMUX_PIN(PIN_PE2, 0, 0) -+#define PIN_PE2__PWML0 PINMUX_PIN(PIN_PE2, 1, 5) -+#define PIN_PE2__FLEXCOM6_IO4 PINMUX_PIN(PIN_PE2, 2, 2) -+#define PIN_PE2__TIOB2 PINMUX_PIN(PIN_PE2, 3, 3) -+#define PIN_PE2__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PE2, 4, 2) -+#define PIN_PE2__ISC_FIELD PINMUX_PIN(PIN_PE2, 5, 2) -+#define PIN_PE2__G1_RX3 PINMUX_PIN(PIN_PE2, 7, 1) -+#define PIN_PE3 131 -+#define PIN_PE3__GPIO PINMUX_PIN(PIN_PE3, 0, 0) -+#define PIN_PE3__PWMH0 PINMUX_PIN(PIN_PE3, 1, 5) -+#define PIN_PE3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PE3, 2, 4) -+#define PIN_PE3__TCLK2 PINMUX_PIN(PIN_PE3, 3, 3) -+#define PIN_PE3__I2SMCC1_DIN0 PINMUX_PIN(PIN_PE3, 4, 2) -+#define PIN_PE3__ISC_PCK PINMUX_PIN(PIN_PE3, 5, 2) -+#define PIN_PE3__G1_RXCK PINMUX_PIN(PIN_PE3, 7, 1) -+#define PIN_PE4 132 -+#define PIN_PE4__GPIO PINMUX_PIN(PIN_PE4, 0, 0) -+#define PIN_PE4__PWML1 PINMUX_PIN(PIN_PE4, 1, 5) -+#define PIN_PE4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PE4, 2, 4) -+#define PIN_PE4__TIOA3 PINMUX_PIN(PIN_PE4, 3, 3) -+#define PIN_PE4__I2SMCC1_DIN1 PINMUX_PIN(PIN_PE4, 4, 2) -+#define PIN_PE4__ISC_D8 PINMUX_PIN(PIN_PE4, 5, 2) -+#define PIN_PE4__G1_TXER PINMUX_PIN(PIN_PE4, 7, 1) -+#define PIN_PE5 133 -+#define PIN_PE5__GPIO PINMUX_PIN(PIN_PE5, 0, 0) -+#define PIN_PE5__PWMH1 PINMUX_PIN(PIN_PE5, 1, 5) -+#define PIN_PE5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PE5, 2, 4) -+#define PIN_PE5__TIOB3 PINMUX_PIN(PIN_PE5, 3, 3) -+#define PIN_PE5__I2SMCC1_DIN2 PINMUX_PIN(PIN_PE5, 4, 2) -+#define PIN_PE5__ISC_D9 PINMUX_PIN(PIN_PE5, 5, 2) -+#define PIN_PE5__G1_COL PINMUX_PIN(PIN_PE5, 7, 1) -+#define PIN_PE6 134 -+#define PIN_PE6__GPIO PINMUX_PIN(PIN_PE6, 0, 0) -+#define PIN_PE6__PWML2 PINMUX_PIN(PIN_PE6, 1, 5) -+#define PIN_PE6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PE6, 2, 4) -+#define PIN_PE6__TCLK3 PINMUX_PIN(PIN_PE6, 3, 3) -+#define PIN_PE6__I2SMCC1_DIN3 PINMUX_PIN(PIN_PE6, 4, 2) -+#define PIN_PE6__ISC_D10 PINMUX_PIN(PIN_PE6, 5, 2) -+#define PIN_PE6__G1_CRS PINMUX_PIN(PIN_PE6, 7, 1) -+#define PIN_PE7 135 -+#define PIN_PE7__GPIO PINMUX_PIN(PIN_PE7, 0, 0) -+#define PIN_PE7__PWMH2 PINMUX_PIN(PIN_PE7, 1, 5) -+#define PIN_PE7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PE7, 2, 4) -+#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3) -+#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2) -+#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1) ---- /dev/null -+++ b/arch/arm/boot/dts/sama7g5.dtsi -@@ -0,0 +1,528 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC -+ * -+ * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries -+ * -+ * Author: Eugen Hristev -+ * Author: Claudiu Beznea -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ model = "Microchip SAMA7G5 family SoC"; -+ compatible = "microchip,sama7g5"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ interrupt-parent = <&gic>; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a7"; -+ reg = <0x0>; -+ }; -+ }; -+ -+ clocks { -+ slow_xtal: slow_xtal { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ }; -+ -+ main_xtal: main_xtal { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ }; -+ -+ usb_clk: usb_clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <48000000>; -+ }; -+ }; -+ -+ vddout25: fixed-regulator-vddout25 { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "VDDOUT25"; -+ regulator-min-microvolt = <2500000>; -+ regulator-max-microvolt = <2500000>; -+ regulator-boot-on; -+ status = "disabled"; -+ }; -+ -+ ns_sram: sram@100000 { -+ compatible = "mmio-sram"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x100000 0x20000>; -+ ranges; -+ }; -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ secumod: secumod@e0004000 { -+ compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; -+ reg = <0xe0004000 0x4000>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ sfrbu: sfr@e0008000 { -+ compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; -+ reg = <0xe0008000 0x20>; -+ }; -+ -+ pioA: pinctrl@e0014000 { -+ compatible = "microchip,sama7g5-pinctrl"; -+ reg = <0xe0014000 0x800>; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; -+ }; -+ -+ pmc: pmc@e0018000 { -+ compatible = "microchip,sama7g5-pmc", "syscon"; -+ reg = <0xe0018000 0x200>; -+ interrupts = ; -+ #clock-cells = <2>; -+ clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; -+ clock-names = "td_slck", "md_slck", "main_xtal"; -+ }; -+ -+ rtt: rtt@e001d020 { -+ compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; -+ reg = <0xe001d020 0x30>; -+ interrupts = ; -+ clocks = <&clk32k 0>; -+ }; -+ -+ clk32k: clock-controller@e001d050 { -+ compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; -+ reg = <0xe001d050 0x4>; -+ clocks = <&slow_xtal>; -+ #clock-cells = <1>; -+ }; -+ -+ gpbr: gpbr@e001d060 { -+ compatible = "microchip,sama7g5-gpbr", "syscon"; -+ reg = <0xe001d060 0x48>; -+ }; -+ -+ ps_wdt: watchdog@e001d180 { -+ compatible = "microchip,sama7g5-wdt"; -+ reg = <0xe001d180 0x24>; -+ interrupts = ; -+ clocks = <&clk32k 0>; -+ }; -+ -+ sdmmc0: mmc@e1204000 { -+ compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; -+ reg = <0xe1204000 0x4000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; -+ clock-names = "hclock", "multclk"; -+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; -+ assigned-clocks = <&pmc PMC_TYPE_GCK 80>; -+ assigned-clock-rates = <200000000>; -+ microchip,sdcal-inverted; -+ status = "disabled"; -+ }; -+ -+ sdmmc1: mmc@e1208000 { -+ compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; -+ reg = <0xe1208000 0x4000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; -+ clock-names = "hclock", "multclk"; -+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; -+ assigned-clocks = <&pmc PMC_TYPE_GCK 81>; -+ assigned-clock-rates = <200000000>; -+ microchip,sdcal-inverted; -+ status = "disabled"; -+ }; -+ -+ sdmmc2: mmc@e120c000 { -+ compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; -+ reg = <0xe120c000 0x4000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; -+ clock-names = "hclock", "multclk"; -+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; -+ assigned-clocks = <&pmc PMC_TYPE_GCK 82>; -+ assigned-clock-rates = <200000000>; -+ microchip,sdcal-inverted; -+ status = "disabled"; -+ }; -+ -+ pwm: pwm@e1604000 { -+ compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; -+ reg = <0xe1604000 0x4000>; -+ interrupts = ; -+ #pwm-cells = <3>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; -+ status = "disabled"; -+ }; -+ -+ spdifrx: spdifrx@e1614000 { -+ #sound-dai-cells = <0>; -+ compatible = "microchip,sama7g5-spdifrx"; -+ reg = <0xe1614000 0x4000>; -+ interrupts = ; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; -+ dma-names = "rx"; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; -+ clock-names = "pclk", "gclk"; -+ status = "disabled"; -+ }; -+ -+ spdiftx: spdiftx@e1618000 { -+ #sound-dai-cells = <0>; -+ compatible = "microchip,sama7g5-spdiftx"; -+ reg = <0xe1618000 0x4000>; -+ interrupts = ; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; -+ dma-names = "tx"; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; -+ clock-names = "pclk", "gclk"; -+ }; -+ -+ i2s0: i2s@e161c000 { -+ compatible = "microchip,sama7g5-i2smcc"; -+ #sound-dai-cells = <0>; -+ reg = <0xe161c000 0x4000>; -+ interrupts = ; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; -+ dma-names = "tx", "rx"; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; -+ clock-names = "pclk", "gclk"; -+ status = "disabled"; -+ }; -+ -+ i2s1: i2s@e1620000 { -+ compatible = "microchip,sama7g5-i2smcc"; -+ #sound-dai-cells = <0>; -+ reg = <0xe1620000 0x4000>; -+ interrupts = ; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; -+ dma-names = "tx", "rx"; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; -+ clock-names = "pclk", "gclk"; -+ status = "disabled"; -+ }; -+ -+ pit64b0: timer@e1800000 { -+ compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; -+ reg = <0xe1800000 0x4000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; -+ clock-names = "pclk", "gclk"; -+ }; -+ -+ pit64b1: timer@e1804000 { -+ compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; -+ reg = <0xe1804000 0x4000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; -+ clock-names = "pclk", "gclk"; -+ }; -+ -+ flx0: flexcom@e1818000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe1818000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe1818000 0x800>; -+ status = "disabled"; -+ -+ uart0: serial@200 { -+ compatible = "atmel,at91sam9260-usart"; -+ reg = <0x200 0x200>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; -+ clock-names = "usart"; -+ dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, -+ <&dma1 AT91_XDMAC_DT_PERID(5)>; -+ dma-names = "tx", "rx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ status = "disabled"; -+ }; -+ }; -+ -+ flx1: flexcom@e181c000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe181c000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe181c000 0x800>; -+ status = "disabled"; -+ -+ i2c1: i2c@600 { -+ compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; -+ reg = <0x600 0x200>; -+ interrupts = ; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; -+ atmel,fifo-size = <32>; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, -+ <&dma0 AT91_XDMAC_DT_PERID(8)>; -+ dma-names = "rx", "tx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ status = "disabled"; -+ }; -+ }; -+ -+ flx3: flexcom@e1824000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe1824000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe1824000 0x800>; -+ status = "disabled"; -+ -+ uart3: serial@200 { -+ compatible = "atmel,at91sam9260-usart"; -+ reg = <0x200 0x200>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; -+ clock-names = "usart"; -+ dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, -+ <&dma1 AT91_XDMAC_DT_PERID(11)>; -+ dma-names = "tx", "rx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ status = "disabled"; -+ }; -+ }; -+ -+ trng: rng@e2010000 { -+ compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; -+ reg = <0xe2010000 0x100>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; -+ status = "disabled"; -+ }; -+ -+ flx4: flexcom@e2018000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe2018000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe2018000 0x800>; -+ status = "disabled"; -+ -+ uart4: serial@200 { -+ compatible = "atmel,at91sam9260-usart"; -+ reg = <0x200 0x200>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; -+ clock-names = "usart"; -+ dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, -+ <&dma1 AT91_XDMAC_DT_PERID(13)>; -+ dma-names = "tx", "rx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ atmel,fifo-size = <16>; -+ status = "disabled"; -+ }; -+ }; -+ -+ flx7: flexcom@e2024000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe2024000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe2024000 0x800>; -+ status = "disabled"; -+ -+ uart7: serial@200 { -+ compatible = "atmel,at91sam9260-usart"; -+ reg = <0x200 0x200>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; -+ clock-names = "usart"; -+ dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, -+ <&dma1 AT91_XDMAC_DT_PERID(19)>; -+ dma-names = "tx", "rx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ atmel,fifo-size = <16>; -+ status = "disabled"; -+ }; -+ }; -+ -+ gmac0: ethernet@e2800000 { -+ compatible = "microchip,sama7g5-gem"; -+ reg = <0xe2800000 0x1000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; -+ clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; -+ assigned-clocks = <&pmc PMC_TYPE_GCK 51>; -+ assigned-clock-rates = <125000000>; -+ status = "disabled"; -+ }; -+ -+ gmac1: ethernet@e2804000 { -+ compatible = "microchip,sama7g5-emac"; -+ reg = <0xe2804000 0x1000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; -+ clock-names = "pclk", "hclk"; -+ status = "disabled"; -+ }; -+ -+ dma0: dma-controller@e2808000 { -+ compatible = "microchip,sama7g5-dma"; -+ reg = <0xe2808000 0x1000>; -+ interrupts = ; -+ #dma-cells = <1>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; -+ clock-names = "dma_clk"; -+ status = "disabled"; -+ }; -+ -+ dma1: dma-controller@e280c000 { -+ compatible = "microchip,sama7g5-dma"; -+ reg = <0xe280c000 0x1000>; -+ interrupts = ; -+ #dma-cells = <1>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; -+ clock-names = "dma_clk"; -+ status = "disabled"; -+ }; -+ -+ /* Place dma2 here despite it's address */ -+ dma2: dma-controller@e1200000 { -+ compatible = "microchip,sama7g5-dma"; -+ reg = <0xe1200000 0x1000>; -+ interrupts = ; -+ #dma-cells = <1>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; -+ clock-names = "dma_clk"; -+ dma-requests = <0>; -+ status = "disabled"; -+ }; -+ -+ flx8: flexcom@e2818000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe2818000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe2818000 0x800>; -+ status = "disabled"; -+ -+ i2c8: i2c@600 { -+ compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; -+ reg = <0x600 0x200>; -+ interrupts = ; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; -+ atmel,fifo-size = <32>; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>, -+ <&dma0 AT91_XDMAC_DT_PERID(22)>; -+ dma-names = "rx", "tx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ status = "disabled"; -+ }; -+ }; -+ -+ flx9: flexcom@e281c000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe281c000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe281c000 0x800>; -+ status = "disabled"; -+ -+ i2c9: i2c@600 { -+ compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; -+ reg = <0x600 0x200>; -+ interrupts = ; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; -+ atmel,fifo-size = <32>; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>, -+ <&dma0 AT91_XDMAC_DT_PERID(24)>; -+ dma-names = "rx", "tx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ status = "disabled"; -+ }; -+ }; -+ -+ flx11: flexcom@e2824000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe2824000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe2824000 0x800>; -+ status = "disabled"; -+ -+ spi11: spi@400 { -+ compatible = "atmel,at91rm9200-spi"; -+ reg = <0x400 0x200>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; -+ clock-names = "spi_clk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ atmel,fifo-size = <32>; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, -+ <&dma0 AT91_XDMAC_DT_PERID(28)>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ }; -+ -+ gic: interrupt-controller@e8c11000 { -+ compatible = "arm,cortex-a7-gic"; -+ #interrupt-cells = <3>; -+ #address-cells = <0>; -+ interrupt-controller; -+ interrupt-parent; -+ reg = <0xe8c11000 0x1000>, -+ <0xe8c12000 0x2000>; -+ }; -+ }; -+}; diff --git a/target/linux/at91/patches-5.15/223-ARM-at91-pm-do-not-panic-if-ram-controllers-are-not-.patch b/target/linux/at91/patches-5.15/223-ARM-at91-pm-do-not-panic-if-ram-controllers-are-not-.patch deleted file mode 100644 index 68bf447a03..0000000000 --- a/target/linux/at91/patches-5.15/223-ARM-at91-pm-do-not-panic-if-ram-controllers-are-not-.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 76dbc56ad65350d78d12bd9b36b00c36fb27addf Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 23 Aug 2021 16:19:12 +0300 -Subject: [PATCH 223/247] ARM: at91: pm: do not panic if ram controllers are - not enabled - -In case PM is enabled but there is no RAM controller information -in DT the code will panic. Avoid such scenarios by not initializing -platform specific PM code in case RAM controller is not provided -via DT. - -Reported-by: Eugen Hristev -Fixes: 827de1f123ba0 ("ARM: at91: remove at91_dt_initialize and machine init_early()") -Fixes: 892e1f4a3ae58 ("ARM: at91: pm: add sama7g5 ddr phy controller") -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210823131915.23857-2-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 22 ++++++++++++++++------ - 1 file changed, 16 insertions(+), 6 deletions(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -589,7 +589,7 @@ static const struct of_device_id ramc_ph - { /* Sentinel. */ }, - }; - --static __init void at91_dt_ramc(bool phy_mandatory) -+static __init int at91_dt_ramc(bool phy_mandatory) - { - struct device_node *np; - const struct of_device_id *of_id; -@@ -625,12 +625,18 @@ static __init void at91_dt_ramc(bool phy - /* Lookup for DDR PHY node, if any. */ - for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) { - soc_pm.data.ramc_phy = of_iomap(np, 0); -- if (!soc_pm.data.ramc_phy) -- panic(pr_fmt("unable to map ramc phy cpu registers\n")); -+ if (!soc_pm.data.ramc_phy) { -+ pr_err("unable to map ramc phy cpu registers\n"); -+ ret = -ENOMEM; -+ goto unmap_ramc; -+ } - } - -- if (phy_mandatory && !soc_pm.data.ramc_phy) -- panic(pr_fmt("DDR PHY is mandatory!\n")); -+ if (phy_mandatory && !soc_pm.data.ramc_phy) { -+ pr_err("DDR PHY is mandatory!\n"); -+ ret = -ENODEV; -+ goto unmap_ramc; -+ } - - if (!standby) { - pr_warn("ramc no standby function available\n"); -@@ -1163,13 +1169,17 @@ void __init sama7_pm_init(void) - [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | - AT91_PM_IOMAP(SHDWC), - }; -+ int ret; - - if (!IS_ENABLED(CONFIG_SOC_SAMA7)) - return; - - at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); - -- at91_dt_ramc(true); -+ ret = at91_dt_ramc(true); -+ if (ret) -+ return; -+ - at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); - at91_pm_init(NULL); - diff --git a/target/linux/at91/patches-5.15/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch b/target/linux/at91/patches-5.15/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch deleted file mode 100644 index 11c0f2c1e3..0000000000 --- a/target/linux/at91/patches-5.15/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch +++ /dev/null @@ -1,36 +0,0 @@ -From cf96a88e44f1fde9f1a30ab335329ff9e895e6f8 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 23 Aug 2021 16:19:13 +0300 -Subject: [PATCH 224/247] ARM: dts: at91: sama7g5: add ram controllers - -Add RAM and RAMC PHY controllers. These are necessary for platform -specific power management code. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210823131915.23857-3-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/sama7g5.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/arch/arm/boot/dts/sama7g5.dtsi -+++ b/arch/arm/boot/dts/sama7g5.dtsi -@@ -515,6 +515,18 @@ - }; - }; - -+ uddrc: uddrc@e3800000 { -+ compatible = "microchip,sama7g5-uddrc"; -+ reg = <0xe3800000 0x4000>; -+ status = "okay"; -+ }; -+ -+ ddr3phy: ddr3phy@e3804000 { -+ compatible = "microchip,sama7g5-ddr3phy"; -+ reg = <0xe3804000 0x1000>; -+ status = "okay"; -+ }; -+ - gic: interrupt-controller@e8c11000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; diff --git a/target/linux/at91/patches-5.15/225-ARM-dts-at91-sama7g5-add-securam-node.patch b/target/linux/at91/patches-5.15/225-ARM-dts-at91-sama7g5-add-securam-node.patch deleted file mode 100644 index f264f5c129..0000000000 --- a/target/linux/at91/patches-5.15/225-ARM-dts-at91-sama7g5-add-securam-node.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 1da1aae0b207d6a5ac7c3070b8d7c6ef61a32d71 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 23 Aug 2021 16:19:14 +0300 -Subject: [PATCH 225/247] ARM: dts: at91: sama7g5: add securam node - -Add securam node. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210823131915.23857-4-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/sama7g5.dtsi | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/arch/arm/boot/dts/sama7g5.dtsi -+++ b/arch/arm/boot/dts/sama7g5.dtsi -@@ -75,6 +75,17 @@ - #size-cells = <1>; - ranges; - -+ securam: securam@e0000000 { -+ compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; -+ reg = <0xe0000000 0x4000>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0xe0000000 0x4000>; -+ no-memory-wc; -+ status = "okay"; -+ }; -+ - secumod: secumod@e0004000 { - compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; - reg = <0xe0004000 0x4000>; diff --git a/target/linux/at91/patches-5.15/226-ARM-dts-at91-sama7g5-add-shdwc-node.patch b/target/linux/at91/patches-5.15/226-ARM-dts-at91-sama7g5-add-shdwc-node.patch deleted file mode 100644 index da941918a1..0000000000 --- a/target/linux/at91/patches-5.15/226-ARM-dts-at91-sama7g5-add-shdwc-node.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 372fa27d07f66f97a4bf45621c1b840ce8417a85 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 23 Aug 2021 16:19:15 +0300 -Subject: [PATCH 226/247] ARM: dts: at91: sama7g5: add shdwc node - -Add shutdown controller node and enable it. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210823131915.23857-5-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/at91-sama7g5ek.dts | 9 +++++++++ - arch/arm/boot/dts/sama7g5.dtsi | 11 +++++++++++ - 2 files changed, 20 insertions(+) - ---- a/arch/arm/boot/dts/at91-sama7g5ek.dts -+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts -@@ -634,6 +634,15 @@ - pinctrl-0 = <&pinctrl_sdmmc2_default>; - }; - -+&shdwc { -+ atmel,shdwc-debouncer = <976>; -+ status = "okay"; -+ -+ input@0 { -+ reg = <0>; -+ }; -+}; -+ - &spdifrx { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdifrx_default>; ---- a/arch/arm/boot/dts/sama7g5.dtsi -+++ b/arch/arm/boot/dts/sama7g5.dtsi -@@ -122,6 +122,17 @@ - clock-names = "td_slck", "md_slck", "main_xtal"; - }; - -+ shdwc: shdwc@e001d010 { -+ compatible = "microchip,sama7g5-shdwc", "syscon"; -+ reg = <0xe001d010 0x10>; -+ clocks = <&clk32k 0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ atmel,wakeup-rtc-timer; -+ atmel,wakeup-rtt-timer; -+ status = "disabled"; -+ }; -+ - rtt: rtt@e001d020 { - compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; - reg = <0xe001d020 0x30>; diff --git a/target/linux/at91/patches-5.15/227-ARM-dts-at91-sama7g5-add-chipid.patch b/target/linux/at91/patches-5.15/227-ARM-dts-at91-sama7g5-add-chipid.patch deleted file mode 100644 index 3e307e418e..0000000000 --- a/target/linux/at91/patches-5.15/227-ARM-dts-at91-sama7g5-add-chipid.patch +++ /dev/null @@ -1,28 +0,0 @@ -From d216c1ecf978574216ece8140146c8dc0ea400e3 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 8 Sep 2021 12:43:29 +0300 -Subject: [PATCH 227/247] ARM: dts: at91: sama7g5: add chipid - -Add chipid node for sama7g5. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210908094329.182477-1-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/sama7g5.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm/boot/dts/sama7g5.dtsi -+++ b/arch/arm/boot/dts/sama7g5.dtsi -@@ -159,6 +159,11 @@ - clocks = <&clk32k 0>; - }; - -+ chipid@e0020000 { -+ compatible = "microchip,sama7g5-chipid"; -+ reg = <0xe0020000 0x8>; -+ }; -+ - sdmmc0: mmc@e1204000 { - compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; - reg = <0xe1204000 0x4000>; diff --git a/target/linux/at91/patches-5.15/228-ARM-at91-pm-switch-backup-area-to-vbat-in-backup-mod.patch b/target/linux/at91/patches-5.15/228-ARM-at91-pm-switch-backup-area-to-vbat-in-backup-mod.patch deleted file mode 100644 index 02532b4722..0000000000 --- a/target/linux/at91/patches-5.15/228-ARM-at91-pm-switch-backup-area-to-vbat-in-backup-mod.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 2cd84ddf0e9623c6bc723b1df368cd8b16a3a8e2 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 30 Aug 2021 13:09:27 +0300 -Subject: [PATCH 228/247] ARM: at91: pm: switch backup area to vbat in backup - mode - -Backup area is now switched to VDDIN33 at boot (with the help of -bootloader). When switching to backup mode we need to switch backup area -to VBAT as all the other power sources are cut off. The resuming from -backup mode is done with the help of bootloader, so there is no need to -do something particular in Linux to restore backup area power source. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210830100927.22711-1-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 52 +++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 52 insertions(+) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -47,12 +47,26 @@ struct at91_pm_bu { - unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; - }; - -+/* -+ * struct at91_pm_sfrbu_offsets: registers mapping for SFRBU -+ * @pswbu: power switch BU control registers -+ */ -+struct at91_pm_sfrbu_regs { -+ struct { -+ u32 key; -+ u32 ctrl; -+ u32 state; -+ u32 softsw; -+ } pswbu; -+}; -+ - /** - * struct at91_soc_pm - AT91 SoC power management data structure - * @config_shdwc_ws: wakeup sources configuration function for SHDWC - * @config_pmc_ws: wakeup srouces configuration function for PMC - * @ws_ids: wakup sources of_device_id array - * @data: PM data to be used on last phase of suspend -+ * @sfrbu_regs: SFRBU registers mapping - * @bu: backup unit mapped data (for backup mode) - * @memcs: memory chip select - */ -@@ -62,6 +76,7 @@ struct at91_soc_pm { - const struct of_device_id *ws_ids; - struct at91_pm_bu *bu; - struct at91_pm_data data; -+ struct at91_pm_sfrbu_regs sfrbu_regs; - void *memcs; - }; - -@@ -356,9 +371,36 @@ static int at91_suspend_finish(unsigned - return 0; - } - -+static void at91_pm_switch_ba_to_vbat(void) -+{ -+ unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu); -+ unsigned int val; -+ -+ /* Just for safety. */ -+ if (!soc_pm.data.sfrbu) -+ return; -+ -+ val = readl(soc_pm.data.sfrbu + offset); -+ -+ /* Already on VBAT. */ -+ if (!(val & soc_pm.sfrbu_regs.pswbu.state)) -+ return; -+ -+ val &= ~soc_pm.sfrbu_regs.pswbu.softsw; -+ val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl; -+ writel(val, soc_pm.data.sfrbu + offset); -+ -+ /* Wait for update. */ -+ val = readl(soc_pm.data.sfrbu + offset); -+ while (val & soc_pm.sfrbu_regs.pswbu.state) -+ val = readl(soc_pm.data.sfrbu + offset); -+} -+ - static void at91_pm_suspend(suspend_state_t state) - { - if (soc_pm.data.mode == AT91_PM_BACKUP) { -+ at91_pm_switch_ba_to_vbat(); -+ - cpu_suspend(0, at91_suspend_finish); - - /* The SRAM is lost between suspend cycles */ -@@ -1155,6 +1197,11 @@ void __init sama5d2_pm_init(void) - soc_pm.ws_ids = sama5d2_ws_ids; - soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws; - soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; -+ -+ soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); -+ soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); -+ soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); -+ soc_pm.sfrbu_regs.pswbu.state = BIT(3); - } - - void __init sama7_pm_init(void) -@@ -1185,6 +1232,11 @@ void __init sama7_pm_init(void) - - soc_pm.ws_ids = sama7g5_ws_ids; - soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; -+ -+ soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); -+ soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); -+ soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); -+ soc_pm.sfrbu_regs.pswbu.state = BIT(2); - } - - static int __init at91_pm_modes_select(char *str) diff --git a/target/linux/at91/patches-5.15/229-ARM-dts-at91-sama7g5ek-add-suspend-voltage-for-ddr3l.patch b/target/linux/at91/patches-5.15/229-ARM-dts-at91-sama7g5ek-add-suspend-voltage-for-ddr3l.patch deleted file mode 100644 index b5074b58a0..0000000000 --- a/target/linux/at91/patches-5.15/229-ARM-dts-at91-sama7g5ek-add-suspend-voltage-for-ddr3l.patch +++ /dev/null @@ -1,42 +0,0 @@ -From e5f87471392b344b1261d1eaf93fd44710587ea9 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 30 Sep 2021 18:42:17 +0300 -Subject: [PATCH 229/247] ARM: dts: at91: sama7g5ek: add suspend voltage for - ddr3l rail - -SAMA7G5-EK board has DDR3L type of memory soldered. This needs 1.35V. The -1.35V for DDR3L rail at run-time is selected by the proper configuration -on SELV2 pin (for 1.35V it needs to be in high-z state). When suspended -the MCP16502 PMIC soldered on SAMA7G5-EK will use different sets of -configuration registers to provide proper voltages on its rail. Run-time -configuration registers could be configured differently than suspend -configuration register for MCP16502 (VSEL2 affects only run-time -configuration). In suspend states the DDR3L memory soldered on SAMA7G5-EK -switches to self-refresh. Even on self-refresh it needs to be powered by -a 1.35V rail. Thus, make sure the PMIC is configured properly when system -is suspended. - -Fixes: 7540629e2fc7 (ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210930154219.2214051-2-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/at91-sama7g5ek.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/boot/dts/at91-sama7g5ek.dts -+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts -@@ -196,11 +196,13 @@ - - regulator-state-standby { - regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1350000>; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1350000>; - regulator-mode = <4>; - }; - }; diff --git a/target/linux/at91/patches-5.15/230-ARM-at91-pm-group-constants-and-addresses-loading.patch b/target/linux/at91/patches-5.15/230-ARM-at91-pm-group-constants-and-addresses-loading.patch deleted file mode 100644 index e952f6c377..0000000000 --- a/target/linux/at91/patches-5.15/230-ARM-at91-pm-group-constants-and-addresses-loading.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 12330a9f6b99622e3c21ddcc720b02431b8a6e2d Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 30 Sep 2021 18:42:18 +0300 -Subject: [PATCH 230/247] ARM: at91: pm: group constants and addresses loading - -Group constants and addresses loading. This commit prepares the field for -the next one. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210930154219.2214051-3-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 17 +++++++++-------- - 1 file changed, 9 insertions(+), 8 deletions(-) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -1014,6 +1014,15 @@ ENTRY(at91_pm_suspend_in_sram) - mov tmp1, #0 - mcr p15, 0, tmp1, c7, c10, 4 - -+ ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] -+ str tmp1, .mckr_offset -+ ldr tmp1, [r0, #PM_DATA_PMC_VERSION] -+ str tmp1, .pmc_version -+ ldr tmp1, [r0, #PM_DATA_MEMCTRL] -+ str tmp1, .memtype -+ ldr tmp1, [r0, #PM_DATA_MODE] -+ str tmp1, .pm_mode -+ - ldr tmp1, [r0, #PM_DATA_PMC] - str tmp1, .pmc_base - ldr tmp1, [r0, #PM_DATA_RAMC0] -@@ -1022,14 +1031,6 @@ ENTRY(at91_pm_suspend_in_sram) - str tmp1, .sramc1_base - ldr tmp1, [r0, #PM_DATA_RAMC_PHY] - str tmp1, .sramc_phy_base -- ldr tmp1, [r0, #PM_DATA_MEMCTRL] -- str tmp1, .memtype -- ldr tmp1, [r0, #PM_DATA_MODE] -- str tmp1, .pm_mode -- ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] -- str tmp1, .mckr_offset -- ldr tmp1, [r0, #PM_DATA_PMC_VERSION] -- str tmp1, .pmc_version - /* Both ldrne below are here to preload their address in the TLB */ - ldr tmp1, [r0, #PM_DATA_SHDWC] - str tmp1, .shdwc diff --git a/target/linux/at91/patches-5.15/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch b/target/linux/at91/patches-5.15/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch deleted file mode 100644 index bd7fb4e39e..0000000000 --- a/target/linux/at91/patches-5.15/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 6075bbc75e55258a762d618cd459dbe0dd38aff9 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 30 Sep 2021 18:42:19 +0300 -Subject: [PATCH 231/247] ARM: at91: pm: preload base address of controllers in - tlb - -In suspend/resume procedure for AT91 architecture different controllers -(PMC, SHDWC, RAM, RAM PHY, SFRBU) are accessed to do the proper settings -for power saving. Commit f0bbf17958e8 ("ARM: at91: pm: add self-refresh -support for sama7g5") introduced the access to RAMC PHY controller for -SAMA7G5. The access to this controller is done after RAMC ports are -closed, thus any TLB walk necessary for RAMC PHY virtual address will -fail. In the development branch this was not encountered. However, on -current kernel the issue is reproducible. - -To solve the issue the previous mechanism of pre-loading the TLB with -the RAMC PHY virtual address has been used. However, only the addition -of this new pre-load breaks the functionality for ARMv5 based -devices (SAM9X60). This behavior has been encountered previously -while debugging this code and using the same mechanism for pre-loading -address for different controllers (e.g. pin controller, the assumption -being that other requested translations are replaced from TLB). - -To solve this new issue the TLB flush + the extension of pre-loading -the rest of controllers to TLB (e.g. PMC, RAMC) has been added. The -rest of the controllers should have been pre-loaded previously, anyway. - -Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5") -Depends-on: e42cbbe5c9a2 ("ARM: at91: pm: group constants and addresses loading") -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210930154219.2214051-4-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 25 ++++++++++++++++++++++++- - 1 file changed, 24 insertions(+), 1 deletion(-) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -1014,6 +1014,10 @@ ENTRY(at91_pm_suspend_in_sram) - mov tmp1, #0 - mcr p15, 0, tmp1, c7, c10, 4 - -+ /* Flush tlb. */ -+ mov r4, #0 -+ mcr p15, 0, r4, c8, c7, 0 -+ - ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] - str tmp1, .mckr_offset - ldr tmp1, [r0, #PM_DATA_PMC_VERSION] -@@ -1023,23 +1027,42 @@ ENTRY(at91_pm_suspend_in_sram) - ldr tmp1, [r0, #PM_DATA_MODE] - str tmp1, .pm_mode - -+ /* -+ * ldrne below are here to preload their address in the TLB as access -+ * to RAM may be limited while in self-refresh. -+ */ - ldr tmp1, [r0, #PM_DATA_PMC] - str tmp1, .pmc_base -+ cmp tmp1, #0 -+ ldrne tmp2, [tmp1, #0] -+ - ldr tmp1, [r0, #PM_DATA_RAMC0] - str tmp1, .sramc_base -+ cmp tmp1, #0 -+ ldrne tmp2, [tmp1, #0] -+ - ldr tmp1, [r0, #PM_DATA_RAMC1] - str tmp1, .sramc1_base -+ cmp tmp1, #0 -+ ldrne tmp2, [tmp1, #0] -+ -+#ifndef CONFIG_SOC_SAM_V4_V5 -+ /* ldrne below are here to preload their address in the TLB */ - ldr tmp1, [r0, #PM_DATA_RAMC_PHY] - str tmp1, .sramc_phy_base -- /* Both ldrne below are here to preload their address in the TLB */ -+ cmp tmp1, #0 -+ ldrne tmp2, [tmp1, #0] -+ - ldr tmp1, [r0, #PM_DATA_SHDWC] - str tmp1, .shdwc - cmp tmp1, #0 - ldrne tmp2, [tmp1, #0] -+ - ldr tmp1, [r0, #PM_DATA_SFRBU] - str tmp1, .sfrbu - cmp tmp1, #0 - ldrne tmp2, [tmp1, #0x10] -+#endif - - /* Active the self-refresh mode */ - at91_sramc_self_refresh_ena diff --git a/target/linux/at91/patches-5.15/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch b/target/linux/at91/patches-5.15/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch deleted file mode 100644 index 9b59d9521f..0000000000 --- a/target/linux/at91/patches-5.15/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 98d2c4ca97dde30616fa78ad5677825b1966cec6 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 15 Sep 2021 10:48:35 +0300 -Subject: [PATCH 232/247] ARM: dts: at91: sama7g5ek: use proper slew-rate - settings for GMACs - -Datasheet chapter "EMAC Timings" specifies that while in 3.3V domain -GMAC's MDIO pins should be configured with slew-rate enabled, while the -data + signaling pins should be configured with slew-rate disabled when -GMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets -the slew-rate as enabled for all pins. Adapt the device tree to comply -with these. - -Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210915074836.6574-2-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/at91-sama7g5ek.dts | 28 ++++++++++++++++++++++------ - 1 file changed, 22 insertions(+), 6 deletions(-) - ---- a/arch/arm/boot/dts/at91-sama7g5ek.dts -+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts -@@ -355,7 +355,10 @@ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>; -+ pinctrl-0 = <&pinctrl_gmac0_default -+ &pinctrl_gmac0_mdio_default -+ &pinctrl_gmac0_txck_default -+ &pinctrl_gmac0_phy_irq>; - phy-mode = "rgmii-id"; - status = "okay"; - -@@ -370,7 +373,9 @@ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>; -+ pinctrl-0 = <&pinctrl_gmac1_default -+ &pinctrl_gmac1_mdio_default -+ &pinctrl_gmac1_phy_irq>; - phy-mode = "rmii"; - status = "okay"; - -@@ -425,14 +430,20 @@ - , - , - , -- , -- , - ; -+ slew-rate = <0>; -+ bias-disable; -+ }; -+ -+ pinctrl_gmac0_mdio_default: gmac0_mdio_default { -+ pinmux = , -+ ; - bias-disable; - }; - - pinctrl_gmac0_txck_default: gmac0_txck_default { - pinmux = ; -+ slew-rate = <0>; - bias-pull-up; - }; - -@@ -449,8 +460,13 @@ - , - , - , -- , -- , -+ ; -+ slew-rate = <0>; -+ bias-disable; -+ }; -+ -+ pinctrl_gmac1_mdio_default: gmac1_mdio_default { -+ pinmux = , - ; - bias-disable; - }; diff --git a/target/linux/at91/patches-5.15/233-ARM-dts-at91-sama7g5ek-to-not-touch-slew-rate-for-SD.patch b/target/linux/at91/patches-5.15/233-ARM-dts-at91-sama7g5ek-to-not-touch-slew-rate-for-SD.patch deleted file mode 100644 index 61ed933f02..0000000000 --- a/target/linux/at91/patches-5.15/233-ARM-dts-at91-sama7g5ek-to-not-touch-slew-rate-for-SD.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 4c0b77276307d2cba8ae2595cbae4cc916c84c36 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 15 Sep 2021 10:48:36 +0300 -Subject: [PATCH 233/247] ARM: dts: at91: sama7g5ek: to not touch slew-rate for - SDMMC pins - -With commit c709135e576b ("pinctrl: at91-pio4: add support for slew-rate") -and commit cbde6c823bfa ("pinctrl: at91-pio4: Fix slew rate disablement") -the slew-rate is enabled by default for each configured pin. The datasheet -specifies at chapter "Output Driver AC Characteristics" that HSIO -drivers (use in SDMMCx and QSPI0 peripherals), don't have a slewrate -setting but are rather calibrated against an external 1% resistor mounted -on the SDMMCx_CAL or QSPI0_CAL pins. Depending on the target signal -frequency and the external load, it is possible to adjust their target -output impedance. Thus set slew-rate = <0> for SDMMC (QSPI is not enabled -at the moment in device tree). - -Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210915074836.6574-3-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/at91-sama7g5ek.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm/boot/dts/at91-sama7g5ek.dts -+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts -@@ -558,6 +558,7 @@ - , - , - ; -+ slew-rate = <0>; - bias-pull-up; - }; - -@@ -565,6 +566,7 @@ - pinmux = , - , - ; -+ slew-rate = <0>; - bias-pull-up; - }; - }; -@@ -576,6 +578,7 @@ - , - , - ; -+ slew-rate = <0>; - bias-pull-up; - }; - -@@ -584,6 +587,7 @@ - , - , - ; -+ slew-rate = <0>; - bias-pull-up; - }; - }; -@@ -595,11 +599,13 @@ - , - , - ; -+ slew-rate = <0>; - bias-pull-up; - }; - - ck { - pinmux = ; -+ slew-rate = <0>; - bias-pull-up; - }; - }; diff --git a/target/linux/at91/patches-5.15/236-clk-at91-sama7g5-add-securam-s-peripheral-clock.patch b/target/linux/at91/patches-5.15/236-clk-at91-sama7g5-add-securam-s-peripheral-clock.patch deleted file mode 100644 index 046acec453..0000000000 --- a/target/linux/at91/patches-5.15/236-clk-at91-sama7g5-add-securam-s-peripheral-clock.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 50edd53c26177e95995533b7d649801086a52f6c Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:07 +0300 -Subject: [PATCH 236/247] clk: at91: sama7g5: add securam's peripheral clock - -Add SECURAM's peripheral clock. - -Signed-off-by: Claudiu Beznea -Acked-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20211011112719.3951784-4-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -377,6 +377,7 @@ static const struct { - u8 id; - } sama7g5_periphck[] = { - { .n = "pioA_clk", .p = "mck0", .id = 11, }, -+ { .n = "securam_clk", .p = "mck0", .id = 18, }, - { .n = "sfr_clk", .p = "mck1", .id = 19, }, - { .n = "hsmc_clk", .p = "mck1", .id = 21, }, - { .n = "xdmac0_clk", .p = "mck1", .id = 22, }, diff --git a/target/linux/at91/patches-5.15/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch b/target/linux/at91/patches-5.15/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch deleted file mode 100644 index c78883c8d6..0000000000 --- a/target/linux/at91/patches-5.15/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch +++ /dev/null @@ -1,39 +0,0 @@ -From bb8e6ca274763fa98613dbe8b0833348a1d8fe4d Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:12 +0300 -Subject: [PATCH 240/247] clk: at91: clk-master: check if div or pres is zero - -Check if div or pres is zero before using it as argument for ffs(). -In case div is zero ffs() will return 0 and thus substracting from -zero will lead to invalid values to be setup in registers. - -Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") -Fixes: 75c88143f3b87 ("clk: at91: clk-master: add master clock support for SAMA7G5") -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-9-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-master.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -344,7 +344,7 @@ static int clk_master_pres_set_rate(stru - - else if (pres == 3) - pres = MASTER_PRES_MAX; -- else -+ else if (pres) - pres = ffs(pres) - 1; - - spin_lock_irqsave(master->lock, flags); -@@ -757,7 +757,7 @@ static int clk_sama7g5_master_set_rate(s - - if (div == 3) - div = MASTER_PRES_MAX; -- else -+ else if (div) - div = ffs(div) - 1; - - spin_lock_irqsave(master->lock, flags); diff --git a/target/linux/at91/patches-5.15/242-clk-at91-clk-master-fix-prescaler-logic.patch b/target/linux/at91/patches-5.15/242-clk-at91-clk-master-fix-prescaler-logic.patch deleted file mode 100644 index 950ca26afd..0000000000 --- a/target/linux/at91/patches-5.15/242-clk-at91-clk-master-fix-prescaler-logic.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 4375cd63b55860f5e82618dc5f50846b3129842a Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:14 +0300 -Subject: [PATCH 242/247] clk: at91: clk-master: fix prescaler logic - -When prescaler value read from register is MASTER_PRES_MAX it means -that the input clock will be divided by 3. Fix the code to reflect -this. - -Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-master.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -386,7 +386,7 @@ static unsigned long clk_master_pres_rec - - val &= master->layout->mask; - pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; -- if (pres == 3 && characteristics->have_div3_pres) -+ if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres) - pres = 3; - else - pres = (1 << pres); diff --git a/target/linux/at91/patches-5.15/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch b/target/linux/at91/patches-5.15/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch deleted file mode 100644 index 1ae5076da9..0000000000 --- a/target/linux/at91/patches-5.15/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 91a49481af7332853c4c921d46aded8210572210 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:17 +0300 -Subject: [PATCH 245/247] clk: at91: sama7g5: remove prescaler part of master - clock - -On SAMA7G5 the prescaler part of master clock has been implemented as a -changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit -must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is -done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has -been discovered that in some conditions the PMC_SR.MCKRDY is not rising -but the rate it provides it's stable. The workaround is to add a timeout -when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler -will be removed from Linux clock tree as all the frequencies for CPU could -be obtained from PLL and also there will be less overhead when changing -frequency via DVFS. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-14-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 11 +---------- - 1 file changed, 1 insertion(+), 10 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -992,16 +992,7 @@ static void __init sama7g5_pmc_setup(str - } - - parent_names[0] = "cpupll_divpmcck"; -- hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names, -- &mck0_layout, &mck0_characteristics, -- &pmc_mck0_lock, -- CLK_SET_RATE_PARENT, 0); -- if (IS_ERR(hw)) -- goto err_free; -- -- sama7g5_pmc->chws[PMC_CPU] = hw; -- -- hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", -+ hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck", - &mck0_layout, &mck0_characteristics, - &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); - if (IS_ERR(hw)) diff --git a/target/linux/at91/patches-5.15/99-scripts-fix-compilation-error.patch b/target/linux/at91/patches-5.15/99-scripts-fix-compilation-error.patch deleted file mode 100644 index 711c7dfbcc..0000000000 --- a/target/linux/at91/patches-5.15/99-scripts-fix-compilation-error.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 6d18eaaaff92f928eab6fad2708b6d28785b4872 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 13 Oct 2021 08:32:07 +0300 -Subject: [PATCH] scripts: fix compilation error - -Signed-off-by: Claudiu Beznea ---- - scripts/Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/scripts/Makefile -+++ b/scripts/Makefile -@@ -21,7 +21,7 @@ HOSTCFLAGS_asn1_compiler.o = -I$(srctree - HOSTCFLAGS_sign-file.o = $(CRYPTO_CFLAGS) - HOSTLDLIBS_sign-file = $(CRYPTO_LIBS) - HOSTCFLAGS_extract-cert.o = $(CRYPTO_CFLAGS) --HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS) -+HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS) -lpthread - - ifdef CONFIG_UNWINDER_ORC - ifeq ($(ARCH),x86_64) From fe7e34d7932c9266bd4008c74956bf5ff25ccfa4 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 29 Sep 2022 10:18:11 +0300 Subject: [PATCH 08/80] at91: kernel v5.15: refresh configs Refresh kernel v5.15 configs. Signed-off-by: Claudiu Beznea --- target/linux/at91/sam9x/config-5.15 | 14 +++++++++----- target/linux/at91/sama5/config-5.15 | 26 ++++++++++++++------------ target/linux/at91/sama7/config-5.15 | 18 +++++++++++++----- 3 files changed, 36 insertions(+), 22 deletions(-) diff --git a/target/linux/at91/sam9x/config-5.15 b/target/linux/at91/sam9x/config-5.15 index 609e182905..ffbd2aba62 100644 --- a/target/linux/at91/sam9x/config-5.15 +++ b/target/linux/at91/sam9x/config-5.15 @@ -21,7 +21,6 @@ CONFIG_ARM_L1_CACHE_SHIFT=5 CONFIG_ARM_PATCH_PHYS_VIRT=y CONFIG_ARM_THUMB=y CONFIG_ARM_UNWIND=y -# CONFIG_ASN1 is not set # CONFIG_AT91RM9200_WATCHDOG is not set CONFIG_AT91SAM9X_WATCHDOG=y # CONFIG_AT91_ADC is not set @@ -39,13 +38,11 @@ CONFIG_ATMEL_SDRAMC=y CONFIG_ATMEL_SSC=y CONFIG_ATMEL_ST=y CONFIG_ATMEL_TCB_CLKSRC=y -CONFIG_ATMEL_TCLIB=y CONFIG_AT_HDMAC=y CONFIG_AT_XDMAC=y CONFIG_AUTO_ZRELADDR=y CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y CONFIG_BLK_PM=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y CONFIG_COMMON_CLK=y @@ -75,7 +72,6 @@ CONFIG_CRC16=y CONFIG_CRC7=y CONFIG_CRC_CCITT=y CONFIG_CRC_ITU_T=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_HASH_INFO=y @@ -99,6 +95,7 @@ CONFIG_FIX_EARLYCON_MEM=y CONFIG_FREEZER=y CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y CONFIG_FW_CACHE=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_GENERIC_ALLOCATOR=y @@ -112,6 +109,7 @@ CONFIG_GENERIC_IRQ_CHIP=y CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PINCONF=y CONFIG_GENERIC_PINCTRL_GROUPS=y @@ -122,6 +120,7 @@ CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GLOB=y CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y @@ -161,6 +160,7 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_MACB=y +CONFIG_MACB_USE_HWSTAMP=y CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y @@ -196,6 +196,8 @@ CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_KUSER_HELPERS=y CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y CONFIG_NLS=y CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y @@ -207,7 +209,6 @@ CONFIG_OF_GPIO=y CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y -CONFIG_OF_NET=y CONFIG_OLD_SIGACTION=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_PAGE_OFFSET=0xC0000000 @@ -229,6 +230,9 @@ CONFIG_POWER_RESET_AT91_POWEROFF=y CONFIG_POWER_RESET_AT91_RESET=y CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_PWM=y CONFIG_PWM_ATMEL=y CONFIG_PWM_ATMEL_HLCDC_PWM=y diff --git a/target/linux/at91/sama5/config-5.15 b/target/linux/at91/sama5/config-5.15 index e7478cf5c7..e2fbc5ba7d 100644 --- a/target/linux/at91/sama5/config-5.15 +++ b/target/linux/at91/sama5/config-5.15 @@ -25,7 +25,6 @@ CONFIG_ARM_PATCH_PHYS_VIRT=y CONFIG_ARM_THUMB=y CONFIG_ARM_UNWIND=y CONFIG_ARM_VIRT_EXT=y -# CONFIG_ASN1 is not set CONFIG_AT91SAM9X_WATCHDOG=y CONFIG_AT91_ADC=y CONFIG_AT91_SAMA5D2_ADC=y @@ -39,7 +38,6 @@ CONFIG_ATMEL_PM=y CONFIG_ATMEL_SDRAMC=y CONFIG_ATMEL_SSC=y CONFIG_ATMEL_TCB_CLKSRC=y -CONFIG_ATMEL_TCLIB=y CONFIG_AT_HDMAC=y CONFIG_AT_XDMAC=y CONFIG_AUTO_ZRELADDR=y @@ -53,9 +51,7 @@ CONFIG_BLK_DEV_RAM_COUNT=4 CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_BLK_DEV_SD=y CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y CONFIG_CACHE_L2X0=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMA=y CONFIG_CMA_ALIGNMENT=8 @@ -67,6 +63,7 @@ CONFIG_CMA_SIZE_MBYTES=16 CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MIN is not set # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_AT91=y @@ -98,7 +95,6 @@ CONFIG_CRC16=y # CONFIG_CRC32_SARWATE is not set CONFIG_CRC32_SLICEBY8=y CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_DRBG=y @@ -115,6 +111,7 @@ CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_ZSTD=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" @@ -131,11 +128,11 @@ CONFIG_DNOTIFY=y CONFIG_DRM=y CONFIG_DRM_ATMEL_HLCDC=y CONFIG_DRM_BRIDGE=y +CONFIG_DRM_DP_AUX_BUS=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_GEM_CMA_HELPER=y CONFIG_DRM_KMS_CMA_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_PANEL=y CONFIG_DRM_PANEL_BRIDGE=y @@ -147,7 +144,6 @@ CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_EEPROM_AT24=y CONFIG_ELF_CORE=y -CONFIG_ENABLE_MUST_CHECK=y CONFIG_EXT4_FS=y CONFIG_FAT_FS=y CONFIG_FB=y @@ -166,12 +162,14 @@ CONFIG_FORCE_MAX_ZONEORDER=15 CONFIG_FREEZER=y CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y CONFIG_FW_CACHE=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IDLE_POLL_SETUP=y @@ -179,6 +177,7 @@ CONFIG_GENERIC_IRQ_CHIP=y CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PINCONF=y CONFIG_GENERIC_SCHED_CLOCK=y @@ -189,6 +188,7 @@ CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_VDSO_32=y CONFIG_GLOB=y CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_HARDIRQS_SW_RESEND=y @@ -246,8 +246,8 @@ CONFIG_LOG_BUF_SHIFT=16 CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_MACB=y +CONFIG_MACB_USE_HWSTAMP=y CONFIG_MAGIC_SYSRQ=y -CONFIG_MANDATORY_FILE_LOCKING=y CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y @@ -295,6 +295,8 @@ CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_PER_CPU_KM=y # CONFIG_NEON is not set +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y CONFIG_NLS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y @@ -312,7 +314,6 @@ CONFIG_OF_GPIO=y CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y -CONFIG_OF_NET=y CONFIG_OLD_SIGACTION=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OUTER_CACHE=y @@ -335,9 +336,12 @@ CONFIG_POWER_RESET_AT91_POWEROFF=y CONFIG_POWER_RESET_AT91_RESET=y CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y # CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_PRINTK_TIME=y CONFIG_PROC_VMCORE=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_PWM=y CONFIG_PWM_ATMEL=y CONFIG_PWM_ATMEL_HLCDC_PWM=y @@ -359,6 +363,7 @@ CONFIG_RTC_DRV_AT91RM9200=y CONFIG_RTC_I2C_AND_SPI=y CONFIG_SAMA5D4_WATCHDOG=y CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y # CONFIG_SCSI_LOWLEVEL is not set # CONFIG_SERIAL_8250 is not set CONFIG_SERIAL_ATMEL=y @@ -397,7 +402,6 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y CONFIG_SND_SOC_I2C_AND_SPI=y CONFIG_SND_SOC_MIKROE_PROTO=y -# CONFIG_SND_SOC_PCM5102A is not set CONFIG_SND_SOC_WM8731=y CONFIG_SND_SOC_WM8904=y CONFIG_SND_SPI=y @@ -437,7 +441,6 @@ CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y CONFIG_TINY_SRCU=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y -CONFIG_TOUCHSCREEN_PROPERTIES=y CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_UBIFS_FS=y CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" @@ -447,7 +450,6 @@ CONFIG_USB_ACM=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # CONFIG_USB_AT91 is not set # CONFIG_USB_ATMEL_USBA is not set -# CONFIG_USB_AUDIO is not set CONFIG_USB_COMMON=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_AT91=y diff --git a/target/linux/at91/sama7/config-5.15 b/target/linux/at91/sama7/config-5.15 index 45568112e4..4ff0d3df23 100644 --- a/target/linux/at91/sama7/config-5.15 +++ b/target/linux/at91/sama7/config-5.15 @@ -33,7 +33,6 @@ CONFIG_ATMEL_CLOCKSOURCE_TCB=y # CONFIG_ATMEL_EBI is not set CONFIG_ATMEL_SDRAMC=y CONFIG_ATMEL_TCB_CLKSRC=y -# CONFIG_ATMEL_TCLIB is not set # CONFIG_AT_HDMAC is not set CONFIG_AT_XDMAC=y CONFIG_AUTO_ZRELADDR=y @@ -43,10 +42,8 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_BLK_DEV_SD=y -CONFIG_BLK_SCSI_REQUEST=y # CONFIG_CACHE_L2X0 is not set CONFIG_CAN=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMA=y @@ -59,6 +56,7 @@ CONFIG_CMA_SIZE_MBYTES=256 CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MIN is not set # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk nocache ignore_loglevel" CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_AT91=y @@ -98,7 +96,6 @@ CONFIG_CPU_V7=y CONFIG_CRC16=y CONFIG_CRC_CCITT=y CONFIG_CRC_ITU_T=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CMAC=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_DEFLATE=y @@ -117,6 +114,7 @@ CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_AT91_SAMA7G5_FLEXCOM3=y CONFIG_DEBUG_AT91_UART=y @@ -151,6 +149,7 @@ CONFIG_FIX_EARLYCON_MEM=y CONFIG_FORCE_MAX_ZONEORDER=15 CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_BUG=y @@ -164,6 +163,7 @@ CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PINCONF=y CONFIG_GENERIC_PINCTRL_GROUPS=y @@ -176,6 +176,7 @@ CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_VDSO_32=y CONFIG_GLOB=y CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y CONFIG_GRACE_PERIOD=y CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HARDEN_BRANCH_PREDICTOR=y @@ -222,6 +223,7 @@ CONFIG_LSM="N" CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_MACB=y +CONFIG_MACB_USE_HWSTAMP=y CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y @@ -255,6 +257,8 @@ CONFIG_MTD_CMDLINE_PARTS=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_PER_CPU_KM=y CONFIG_NEON=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y CONFIG_NET_SWITCHDEV=y CONFIG_NFS_FS=y CONFIG_NLS=y @@ -274,7 +278,6 @@ CONFIG_OF_GPIO=y CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y -CONFIG_OF_NET=y CONFIG_OLD_SIGACTION=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_PAGE_OFFSET=0xC0000000 @@ -291,8 +294,11 @@ CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_AT91_POWEROFF is not set CONFIG_POWER_RESET_AT91_RESET=y CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y +CONFIG_PPS=y # CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_PWM=y CONFIG_PWM_ATMEL=y CONFIG_PWM_SYSFS=y @@ -313,6 +319,7 @@ CONFIG_RTC_MC146818_LIB=y # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_SAMA5D4_WATCHDOG=y CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y # CONFIG_SERIAL_8250 is not set CONFIG_SERIAL_ATMEL=y CONFIG_SERIAL_ATMEL_CONSOLE=y @@ -382,6 +389,7 @@ CONFIG_VFP=y CONFIG_VFPv3=y # CONFIG_VIDEO_ATMEL_XISC is not set CONFIG_VIDEO_DEV=y +# CONFIG_VIDEO_IMX208 is not set CONFIG_VIDEO_V4L2=y CONFIG_VIDEO_V4L2_I2C=y CONFIG_VIDEO_V4L2_SUBDEV_API=y From dd37b205f802ec7021912854ee7e37191c242713 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 29 Sep 2022 10:18:39 +0300 Subject: [PATCH 09/80] at91: kernel v5.10: refresh configs Refresh kernel v5.10 configs. Signed-off-by: Claudiu Beznea --- target/linux/at91/sam9x/config-5.10 | 1 - target/linux/at91/sama5/config-5.10 | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/linux/at91/sam9x/config-5.10 b/target/linux/at91/sam9x/config-5.10 index 609e182905..63575c6093 100644 --- a/target/linux/at91/sam9x/config-5.10 +++ b/target/linux/at91/sam9x/config-5.10 @@ -21,7 +21,6 @@ CONFIG_ARM_L1_CACHE_SHIFT=5 CONFIG_ARM_PATCH_PHYS_VIRT=y CONFIG_ARM_THUMB=y CONFIG_ARM_UNWIND=y -# CONFIG_ASN1 is not set # CONFIG_AT91RM9200_WATCHDOG is not set CONFIG_AT91SAM9X_WATCHDOG=y # CONFIG_AT91_ADC is not set diff --git a/target/linux/at91/sama5/config-5.10 b/target/linux/at91/sama5/config-5.10 index e7478cf5c7..ee607b484f 100644 --- a/target/linux/at91/sama5/config-5.10 +++ b/target/linux/at91/sama5/config-5.10 @@ -25,7 +25,6 @@ CONFIG_ARM_PATCH_PHYS_VIRT=y CONFIG_ARM_THUMB=y CONFIG_ARM_UNWIND=y CONFIG_ARM_VIRT_EXT=y -# CONFIG_ASN1 is not set CONFIG_AT91SAM9X_WATCHDOG=y CONFIG_AT91_ADC=y CONFIG_AT91_SAMA5D2_ADC=y @@ -172,6 +171,7 @@ CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IDLE_POLL_SETUP=y From 0a00189e412a9579c2a417553912276f16eaba1d Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 29 Sep 2022 10:19:18 +0300 Subject: [PATCH 10/80] at91: kernel v5.15: use KERNEL_TESTING_PATCHVER:=5.15 Use KERNEL_TESTING_PATCHVER:=15 for at91 targets. Signed-off-by: Claudiu Beznea --- target/linux/at91/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/at91/Makefile b/target/linux/at91/Makefile index af0dc3f338..20dc43cb9e 100644 --- a/target/linux/at91/Makefile +++ b/target/linux/at91/Makefile @@ -11,6 +11,7 @@ FEATURES:=ext4 squashfs targz usbgadget ubifs SUBTARGETS:=sama7 sama5 sam9x KERNEL_PATCHVER:=5.10 +KERNEL_TESTING_PATCHVER:=5.15 include $(INCLUDE_DIR)/target.mk From 1ea3510c5c68048cad65b355beaced1671056a02 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 22 Oct 2022 00:21:42 +0200 Subject: [PATCH 11/80] kernel: Add missing kernel configuration options The at91/sam9x targets misses these configuration options when using kernel 5.15. Signed-off-by: Hauke Mehrtens --- target/linux/generic/config-5.15 | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15 index 6636bd3204..e8b0b3a168 100644 --- a/target/linux/generic/config-5.15 +++ b/target/linux/generic/config-5.15 @@ -1504,6 +1504,7 @@ CONFIG_DQL=y # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_ARMADA is not set # CONFIG_DRM_AST is not set +# CONFIG_DRM_ATMEL_HLCDC is not set # CONFIG_DRM_BOCHS is not set # CONFIG_DRM_CDNS_DSI is not set # CONFIG_DRM_CDNS_MHDP8546 is not set @@ -1929,6 +1930,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FB_ARK is not set # CONFIG_FB_ARMCLCD is not set # CONFIG_FB_ASILIANT is not set +# CONFIG_FB_ATMEL is not set # CONFIG_FB_ATY is not set # CONFIG_FB_ATY128 is not set # CONFIG_FB_AUO_K190X is not set From b9b0407901f6518a0f5c4825208cff542f4b80cd Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 22 Oct 2022 02:26:05 +0200 Subject: [PATCH 12/80] kernel: x86: Add glue_helper.ko only on kernel < 5.12 This module was removed with kernel 5.12. This fixes the build of the x86 target. Signed-off-by: Hauke Mehrtens --- package/kernel/linux/modules/crypto.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/kernel/linux/modules/crypto.mk b/package/kernel/linux/modules/crypto.mk index f8af5f0a3b..83048e50d3 100644 --- a/package/kernel/linux/modules/crypto.mk +++ b/package/kernel/linux/modules/crypto.mk @@ -727,10 +727,10 @@ ifndef CONFIG_TARGET_x86_64 FILES+= \ $(LINUX_DIR)/arch/x86/crypto/twofish-i586.ko \ $(LINUX_DIR)/arch/x86/crypto/serpent-sse2-i586.ko \ - $(LINUX_DIR)/arch/x86/crypto/glue_helper.ko \ + $(LINUX_DIR)/arch/x86/crypto/glue_helper.ko@lt5.12 \ $(LINUX_DIR)/crypto/cryptd.ko \ $(LINUX_DIR)/crypto/crypto_simd.ko - AUTOLOAD+= $(call AutoLoad,10,cryptd glue_helper \ + AUTOLOAD+= $(call AutoLoad,10,cryptd glue_helper@lt5.12 \ serpent-sse2-i586 twofish-i586 blowfish_generic) endef endif From 350593307381c3021b6990efa6ff16550a5e59a8 Mon Sep 17 00:00:00 2001 From: Chen Minqiang Date: Mon, 3 Oct 2022 09:41:31 +0800 Subject: [PATCH 13/80] ipq40xx: convert to DSA and enable asus,rt-ac42u This convert board asus,rt-ac42u to DSA and re-enable it Reviewed-by: Robert Marko Signed-off-by: Chen Minqiang --- .../ipq40xx/base-files/etc/board.d/01_leds | 9 +++-- .../ipq40xx/base-files/etc/board.d/02_network | 4 ++ .../lib/preinit/05_set_iface_mac_ipq40xx.sh | 9 ++++- .../arm/boot/dts/qcom-ipq4019-rt-ac42u.dts | 40 +++++++++++++------ target/linux/ipq40xx/image/generic.mk | 3 +- 5 files changed, 45 insertions(+), 20 deletions(-) diff --git a/target/linux/ipq40xx/base-files/etc/board.d/01_leds b/target/linux/ipq40xx/base-files/etc/board.d/01_leds index cd68ed32c0..748b6f5b82 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/01_leds +++ b/target/linux/ipq40xx/base-files/etc/board.d/01_leds @@ -13,10 +13,11 @@ alfa-network,ap120c-ac) ucidef_set_led_netdev "wan" "WAN" "amber:wan" "wan" ;; asus,rt-ac42u) - ucidef_set_led_switch "lan1" "LAN1" "blue:lan-1" "switch0" "0x02" - ucidef_set_led_switch "lan2" "LAN2" "blue:lan-2" "switch0" "0x04" - ucidef_set_led_switch "lan3" "LAN3" "blue:lan-3" "switch0" "0x08" - ucidef_set_led_switch "lan4" "LAN4" "blue:lan-4" "switch0" "0x10" + ucidef_set_led_netdev "lan1" "LAN1" "blue:lan-1" "lan1" + ucidef_set_led_netdev "lan2" "LAN2" "blue:lan-2" "lan2" + ucidef_set_led_netdev "lan3" "LAN3" "blue:lan-3" "lan3" + ucidef_set_led_netdev "lan4" "LAN4" "blue:lan-4" "lan4" + ucidef_set_led_netdev "wan" "WAN" "blue:wan" "wan" ;; asus,rt-ac58u) ucidef_set_led_netdev "wan" "WAN" "blue:wan" "eth1" diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network index 36f1f7c24a..56d38bd6a7 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/02_network +++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network @@ -13,6 +13,7 @@ ipq40xx_setup_interfaces() case "$board" in 8dev,habanero-dvk|\ avm,fritzbox-4040|\ + asus,rt-ac42u|\ asus,rt-ac58u|\ linksys,ea6350v3|\ linksys,ea8300|\ @@ -81,6 +82,9 @@ ipq40xx_setup_macs() 8dev,habanero-dvk) label_mac=$(mtd_get_mac_binary "ART" 0x1006) ;; + asus,rt-ac42u) + label_mac=$(mtd_get_mac_binary_ubi Factory 0x1006) + ;; asus,rt-ac58u) wan_mac=$(mtd_get_mac_binary_ubi Factory 0x1006) lan_mac=$(mtd_get_mac_binary_ubi Factory 0x5006) diff --git a/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh b/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh index e4a5eb3e89..ddfef1ab2d 100644 --- a/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh +++ b/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh @@ -8,8 +8,13 @@ preinit_set_mac_address() { ip link set dev eth1 address $(macaddr_add "$base_mac" 3) ;; asus,rt-ac42u) - ip link set dev eth0 address $(mtd_get_mac_binary_ubi Factory 0x1006) - ip link set dev eth1 address $(mtd_get_mac_binary_ubi Factory 0x9006) + base_mac=$(mtd_get_mac_binary_ubi Factory 0x1006) + ip link set dev eth0 address $base_mac + ip link set dev lan1 address $base_mac + ip link set dev lan2 address $base_mac + ip link set dev lan3 address $base_mac + ip link set dev lan4 address $base_mac + ip link set dev wan address $(mtd_get_mac_binary_ubi Factory 0x9006) ;; engenius,eap2200) base_mac=$(cat /sys/class/net/eth0/address) diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts index 3d58eac09e..f746acfbb9 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts @@ -31,10 +31,6 @@ status = "okay"; }; - ess-psgmii@98000 { - status = "okay"; - }; - tcsr@1949000 { compatible = "qcom,tcsr"; reg = <0x1949000 0x100>; @@ -85,14 +81,6 @@ watchdog@b017000 { status = "okay"; }; - - ess-switch@c000000 { - status = "okay"; - }; - - edma@c080000 { - status = "okay"; - }; }; keys { @@ -282,6 +270,34 @@ status = "okay"; }; +&gmac { + status = "okay"; +}; + +&switch { + status = "okay"; +}; + +&swport1 { + status = "okay"; +}; + +&swport2 { + status = "okay"; +}; + +&swport3 { + status = "okay"; +}; + +&swport4 { + status = "okay"; +}; + +&swport5 { + status = "okay"; +}; + &wifi0 { status = "okay"; qcom,ath10k-calibration-variant = "ASUS-RT-AC42U"; diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 68ce31c205..0a7fee159d 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -228,8 +228,7 @@ define Device/asus_rt-ac42u UIMAGE_NAME:=$(shell echo -e '\03\01\01\01RT-AC82U') DEVICE_PACKAGES := ath10k-firmware-qca9984-ct kmod-usb-ledtrig-usbport endef -# Missing DSA Setup -#TARGET_DEVICES += asus_rt-ac42u +TARGET_DEVICES += asus_rt-ac42u define Device/asus_rt-ac58u $(call Device/FitImageLzma) From c783073894a89f52e8c53c8ff600fa84ebe7bbf0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 21 Mar 2022 18:32:41 +0100 Subject: [PATCH 14/80] lantiq: copy Linux 5.10 files in preparation for Linux 5.15 support Signed-off-by: Martin Blumenstingl --- target/linux/lantiq/ase/config-5.15 | 25 + target/linux/lantiq/config-5.15 | 225 + target/linux/lantiq/falcon/config-5.15 | 9 + .../0001-MIPS-lantiq-add-pcie-driver.patch | 5507 +++++++++++++++++ .../0004-MIPS-lantiq-add-atm-hack.patch | 482 ++ ...-MIPS-lantiq-backport-old-timer-code.patch | 1035 ++++ .../0018-MTD-nand-lots-of-xrx200-fixes.patch | 121 + ...antiq-handle-NO_XIP-on-cfi0001-flash.patch | 25 + ...T-PHY-add-led-support-for-intel-xway.patch | 294 + .../0028-NET-lantiq-various-etop-fixes.patch | 865 +++ ...PS-lantiq-add-FALC-ON-i2c-bus-master.patch | 1034 ++++ ...iq-wifi-and-ethernet-eeprom-handling.patch | 218 + ...42-arch-mips-increase-io_space_limit.patch | 24 + ...e-lantiq-settings-match-vendor-drive.patch | 78 + ...PS-lantiq-improve-USB-initialization.patch | 49 + .../patches-5.15/0101-find_active_root.patch | 93 + .../0151-lantiq-ifxmips_pcie-use-of.patch | 387 ++ .../lantiq/patches-5.15/0152-lantiq-VPE.patch | 180 + .../0154-lantiq-pci-bar11mask-fix.patch | 22 + .../patches-5.15/0155-lantiq-VPE-nosmp.patch | 14 + .../0160-owrt-lantiq-multiple-flash.patch | 220 + ...-cmdset-0001-disable-buffered-writes.patch | 11 + ...add-gphy-clk-src-device-tree-binding.patch | 30 + ...make-the-burst-length-configurable-b.patch | 86 + ...le-all-hardware-interrupts-on-second.patch | 86 + .../0701-NET-lantiq-etop-of-mido.patch | 37 + ...-lantiq-add-support-for-jumbo-frames.patch | 145 + ...q_xrx200-increase-buffer-reservation.patch | 122 + ...iq_xrx200-add-ingress-SG-DMA-support.patch | 104 + ...llow-to-use-all-GPHYs-on-xRX300-and-.patch | 275 + ...-lantiq-enable-jumbo-frames-on-GSWIP.patch | 127 + ...gure-the-burst-length-in-ethernet-dr.patch | 126 + ...x200-Hardcode-the-burst-length-value.patch | 73 + ...et-lantiq_etop-Fix-compilation-error.patch | 26 + ...-lantiq-dma-increase-descritor-count.patch | 28 + ...tiq_xrx200-increase-napi-poll-weigth.patch | 32 + ...t-lantiq_xrx200-convert-to-build_skb.patch | 206 + ...lantiq_xrx200-fix-use-after-free-bug.patch | 30 + ...0-confirm-skb-is-allocated-before-us.patch | 33 + ...rx200-fix-lock-under-memory-pressure.patch | 33 + ...0-restore-buffer-if-memory-allocatio.patch | 27 + target/linux/lantiq/xrx200/config-5.15 | 93 + target/linux/lantiq/xway/config-5.15 | 46 + target/linux/lantiq/xway_legacy/config-5.15 | 33 + 44 files changed, 12716 insertions(+) create mode 100644 target/linux/lantiq/ase/config-5.15 create mode 100644 target/linux/lantiq/config-5.15 create mode 100644 target/linux/lantiq/falcon/config-5.15 create mode 100644 target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch create mode 100644 target/linux/lantiq/patches-5.15/0004-MIPS-lantiq-add-atm-hack.patch create mode 100644 target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch create mode 100644 target/linux/lantiq/patches-5.15/0018-MTD-nand-lots-of-xrx200-fixes.patch create mode 100644 target/linux/lantiq/patches-5.15/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch create mode 100644 target/linux/lantiq/patches-5.15/0023-NET-PHY-add-led-support-for-intel-xway.patch create mode 100644 target/linux/lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch create mode 100644 target/linux/lantiq/patches-5.15/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch create mode 100644 target/linux/lantiq/patches-5.15/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch create mode 100644 target/linux/lantiq/patches-5.15/0042-arch-mips-increase-io_space_limit.patch create mode 100644 target/linux/lantiq/patches-5.15/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch create mode 100644 target/linux/lantiq/patches-5.15/0051-MIPS-lantiq-improve-USB-initialization.patch create mode 100644 target/linux/lantiq/patches-5.15/0101-find_active_root.patch create mode 100644 target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch create mode 100644 target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch create mode 100644 target/linux/lantiq/patches-5.15/0154-lantiq-pci-bar11mask-fix.patch create mode 100644 target/linux/lantiq/patches-5.15/0155-lantiq-VPE-nosmp.patch create mode 100644 target/linux/lantiq/patches-5.15/0160-owrt-lantiq-multiple-flash.patch create mode 100644 target/linux/lantiq/patches-5.15/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch create mode 100644 target/linux/lantiq/patches-5.15/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch create mode 100644 target/linux/lantiq/patches-5.15/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch create mode 100644 target/linux/lantiq/patches-5.15/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch create mode 100644 target/linux/lantiq/patches-5.15/0701-NET-lantiq-etop-of-mido.patch create mode 100644 target/linux/lantiq/patches-5.15/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch create mode 100644 target/linux/lantiq/patches-5.15/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch create mode 100644 target/linux/lantiq/patches-5.15/0704-v5.17-net-lantiq_xrx200-add-ingress-SG-DMA-support.patch create mode 100644 target/linux/lantiq/patches-5.15/0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch create mode 100644 target/linux/lantiq/patches-5.15/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch create mode 100644 target/linux/lantiq/patches-5.15/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch create mode 100644 target/linux/lantiq/patches-5.15/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch create mode 100644 target/linux/lantiq/patches-5.15/0712-v5.16-net-ethernet-lantiq_etop-Fix-compilation-error.patch create mode 100644 target/linux/lantiq/patches-5.15/0713-v5.17-MIPS-lantiq-dma-increase-descritor-count.patch create mode 100644 target/linux/lantiq/patches-5.15/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch create mode 100644 target/linux/lantiq/patches-5.15/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch create mode 100644 target/linux/lantiq/patches-5.15/0716-v5.17-net-lantiq_xrx200-fix-use-after-free-bug.patch create mode 100644 target/linux/lantiq/patches-5.15/0717-v6.0-net-lantiq_xrx200-confirm-skb-is-allocated-before-us.patch create mode 100644 target/linux/lantiq/patches-5.15/0718-v6.0-net-lantiq_xrx200-fix-lock-under-memory-pressure.patch create mode 100644 target/linux/lantiq/patches-5.15/0719-v6.0-net-lantiq_xrx200-restore-buffer-if-memory-allocatio.patch create mode 100644 target/linux/lantiq/xrx200/config-5.15 create mode 100644 target/linux/lantiq/xway/config-5.15 create mode 100644 target/linux/lantiq/xway_legacy/config-5.15 diff --git a/target/linux/lantiq/ase/config-5.15 b/target/linux/lantiq/ase/config-5.15 new file mode 100644 index 0000000000..195e49df69 --- /dev/null +++ b/target/linux/lantiq/ase/config-5.15 @@ -0,0 +1,25 @@ +CONFIG_ADM6996_PHY=y +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +CONFIG_CPU_MIPSR1=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_HW_RANDOM=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_ETOP=y +CONFIG_NLS=y +CONFIG_SGL_ALLOC=y +CONFIG_SOC_AMAZON_SE=y +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SWCONFIG=y +CONFIG_TARGET_ISA_REV=1 +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/config-5.15 b/target/linux/lantiq/config-5.15 new file mode 100644 index 0000000000..c37a543e1e --- /dev/null +++ b/target/linux/lantiq/config-5.15 @@ -0,0 +1,225 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_CEVT_R4K=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_LOAD_STORE_LR=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_BLAKE2S=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_RNG2=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y +CONFIG_DTC=y +# CONFIG_DT_EASY50712 is not set +CONFIG_EARLY_PRINTK=y +CONFIG_EFI_EARLYCON=y +CONFIG_FIXED_PHY=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIO_MM_LANTIQ=y +CONFIG_GPIO_STP_XWAY=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARCH_COMPILER_H=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KVM=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_LANTIQ=y +CONFIG_LANTIQ_DT_NONE=y +# CONFIG_LANTIQ_ETOP is not set +CONFIG_LANTIQ_WDT=y +# CONFIG_LANTIQ_XRX200 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CBPF_JIT=y +CONFIG_MIPS_CLOCK_VSYSCALL=y +# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CMDLINE_FROM_DTB=y +# CONFIG_MIPS_ELF_APPENDED_DTB is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_LD_CAN_LINK_VDSO=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_LANTIQ=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_BRNIMAGE_FW=y +CONFIG_MTD_SPLIT_EVA_FW=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_TPLINK_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NVMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +# CONFIG_PCIE_LANTIQ is not set +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHY_LANTIQ_RCU_USB2=y +# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_LANTIQ=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINCTRL_XWAY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_LANTIQ=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_LANTIQ=y +CONFIG_SERIAL_LANTIQ_CONSOLE=y +# CONFIG_SOC_AMAZON_SE is not set +# CONFIG_SOC_FALCON is not set +# CONFIG_SOC_XWAY is not set +CONFIG_SPI=y +CONFIG_SPI_LANTIQ_SSC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SRCU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_VPE_LOADER=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TINY_SRCU=y +CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/lantiq/falcon/config-5.15 b/target/linux/lantiq/falcon/config-5.15 new file mode 100644 index 0000000000..3041c65dbd --- /dev/null +++ b/target/linux/lantiq/falcon/config-5.15 @@ -0,0 +1,9 @@ +CONFIG_CPU_HAS_DIEI=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux" +CONFIG_PINCTRL_FALCON=y +CONFIG_SOC_FALCON=y +CONFIG_SPI_FALCON=y diff --git a/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch new file mode 100644 index 0000000000..99bed24cfd --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch @@ -0,0 +1,5507 @@ +From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:12:28 +0200 +Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/Kconfig | 10 + + arch/mips/lantiq/xway/sysctrl.c | 2 + + arch/mips/pci/Makefile | 2 + + arch/mips/pci/fixup-lantiq-pcie.c | 82 +++ + arch/mips/pci/fixup-lantiq.c | 5 +- + arch/mips/pci/ifxmips_pci_common.h | 57 ++ + arch/mips/pci/ifxmips_pcie.c | 1099 ++++++++++++++++++++++++++++++ + arch/mips/pci/ifxmips_pcie.h | 135 ++++ + arch/mips/pci/ifxmips_pcie_ar10.h | 290 ++++++++ + arch/mips/pci/ifxmips_pcie_msi.c | 392 +++++++++++ + arch/mips/pci/ifxmips_pcie_phy.c | 478 +++++++++++++ + arch/mips/pci/ifxmips_pcie_pm.c | 176 +++++ + arch/mips/pci/ifxmips_pcie_pm.h | 36 + + arch/mips/pci/ifxmips_pcie_reg.h | 1001 +++++++++++++++++++++++++++ + arch/mips/pci/ifxmips_pcie_vr9.h | 271 ++++++++ + arch/mips/pci/pci.c | 25 + + arch/mips/pci/pcie-lantiq.h | 1305 ++++++++++++++++++++++++++++++++++++ + drivers/pci/pcie/aer/Kconfig | 2 +- + include/linux/pci.h | 2 + + include/linux/pci_ids.h | 6 + + 20 files changed, 5374 insertions(+), 2 deletions(-) + create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c + create mode 100644 arch/mips/pci/ifxmips_pci_common.h + create mode 100644 arch/mips/pci/ifxmips_pcie.c + create mode 100644 arch/mips/pci/ifxmips_pcie.h + create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h + create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c + create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c + create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c + create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h + create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h + create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h + create mode 100644 arch/mips/pci/pcie-lantiq.h + +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -20,6 +20,7 @@ config SOC_XWAY + bool "XWAY" + select SOC_TYPE_XWAY + select HAVE_PCI ++ select ARCH_SUPPORTS_MSI + select MFD_SYSCON + select MFD_CORE + +@@ -52,4 +53,13 @@ config PCI_LANTIQ + bool "PCI Support" + depends on SOC_XWAY && PCI + ++config PCIE_LANTIQ ++ bool "PCIE Support" ++ depends on SOC_XWAY && PCI ++ ++config PCIE_LANTIQ_MSI ++ bool ++ depends on PCIE_LANTIQ && PCI_MSI ++ default y ++ + endif +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -43,6 +43,8 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o + obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o + obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o ++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o ++obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o + obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o + obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o + obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o +--- /dev/null ++++ b/arch/mips/pci/fixup-lantiq-pcie.c +@@ -0,0 +1,74 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_fixup_pcie.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \file ifxmips_fixup_pcie.c ++ \ingroup IFX_PCIE ++ \brief PCIe Fixup functions source file ++*/ ++#include ++#include ++#include ++ ++#include ++ ++#include "pcie-lantiq.h" ++ ++static void ++ifx_pcie_fixup_resource(struct pci_dev *dev) ++{ ++ u32 reg; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); ++ ++ printk("%s: fixup host controller %s (%04x:%04x)\n", ++ __func__, pci_name(dev), dev->vendor, dev->device); ++ ++ /* Setup COMMAND register */ ++ reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | ++ PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; ++ pci_write_config_word(dev, PCI_COMMAND, reg); ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); ++ ++static void ++ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); ++ ++ if (dev->devfn == PCI_DEVFN(0, 0) && ++ (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { ++ ++ dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); ++ ++ printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); ++ } ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); ++ mdelay(10); ++} ++ ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ++ ifx_pcie_rc_class_early_fixup); ++ ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, ++ ifx_pcie_rc_class_early_fixup); +--- a/arch/mips/pci/fixup-lantiq.c ++++ b/arch/mips/pci/fixup-lantiq.c +@@ -6,12 +6,19 @@ + + #include + #include ++#include ++#include "ifxmips_pci_common.h" + + int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; + int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; + + int pcibios_plat_dev_init(struct pci_dev *dev) + { ++#ifdef CONFIG_PCIE_LANTIQ ++ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) ++ ifx_pcie_bios_plat_dev_init(dev); ++#endif ++ + if (ltq_pci_plat_arch_init) + return ltq_pci_plat_arch_init(dev); + +@@ -23,5 +30,10 @@ int pcibios_plat_dev_init(struct pci_dev + + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) + { ++#ifdef CONFIG_PCIE_LANTIQ ++ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) ++ return ifx_pcie_bios_map_irq(dev, slot, pin); ++#endif ++ + return of_irq_parse_and_map_pci(dev, slot, pin); + } +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pci_common.h +@@ -0,0 +1,53 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pci_common.h ++** PROJECT : IFX UEIP ++** MODULES : PCI subsystem ++** ++** DATE : 30 June 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 30 June,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++ ++#ifndef IFXMIPS_PCI_COMMON_H ++#define IFXMIPS_PCI_COMMON_H ++#include ++/*! ++ \defgroup IFX_PCI_COM IFX PCI/PCIe common parts for OS integration ++ \brief PCI/PCIe common parts ++*/ ++ ++/*! ++ \defgroup IFX_PCI_COM_OS OS APIs ++ \ingroup IFX_PCI_COM ++ \brief PCI/PCIe bus driver OS interface functions ++*/ ++/*! ++ \file ifxmips_pci_common.h ++ \ingroup IFX_PCI_COM ++ \brief PCI/PCIe bus driver common OS header file ++*/ ++#define IFX_PCI_CONST const ++#ifdef CONFIG_IFX_PCI ++extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); ++extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev); ++#endif /* COFNIG_IFX_PCI */ ++ ++#ifdef CONFIG_PCIE_LANTIQ ++extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); ++extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev); ++#endif ++ ++#endif /* IFXMIPS_PCI_COMMON_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie.c +@@ -0,0 +1,1092 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2009 Lei Chuanhua ++ * Copyright (C) 2013 John Crispin ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie.h" ++#include "ifxmips_pcie_reg.h" ++ ++/* Enable 32bit io due to its mem mapped io nature */ ++#define IFX_PCIE_ERROR_INT ++#define IFX_PCIE_IO_32BIT ++ ++#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) ++#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) ++#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) ++#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) ++#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) ++#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) ++#define SM(_v, _f) (((_v) << _f##_S) & (_f)) ++#define IFX_REG_SET_BIT(_f, _r) \ ++ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) ++ ++#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 ++ ++static DEFINE_SPINLOCK(ifx_pcie_lock); ++ ++u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); ++ ++static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { ++ { ++ .ir_irq = { ++ .irq = IFX_PCIE_IR, ++ .name = "ifx_pcie_rc0", ++ }, ++ ++ .legacy_irq = { ++ { ++ .irq_bit = PCIE_IRN_INTA, ++ .irq = IFX_PCIE_INTA, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTB, ++ .irq = IFX_PCIE_INTB, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTC, ++ .irq = IFX_PCIE_INTC, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTD, ++ .irq = IFX_PCIE_INTD, ++ }, ++ }, ++ }, ++ ++}; ++ ++void ifx_pcie_debug(const char *fmt, ...) ++{ ++ static char buf[256] = {0}; /* XXX */ ++ va_list ap; ++ ++ va_start(ap, fmt); ++ vsnprintf(buf, sizeof(buf), fmt, ap); ++ va_end(ap); ++ ++ printk("%s", buf); ++} ++ ++ ++static inline int pcie_ltssm_enable(int pcie_port) ++{ ++ int i; ++ ++ /* Enable LTSSM */ ++ IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); ++ ++ /* Wait for the link to come up */ ++ for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { ++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) ++ return 0; ++ udelay(10); ++ } ++ ++ printk("%s link timeout!!!!!\n", __func__); ++ return -1; ++} ++ ++static inline void pcie_status_register_clear(int pcie_port) ++{ ++ IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); ++ IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_RSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_UES_R(pcie_port)); ++ IFX_REG_W32(0, PCIE_UEMR(pcie_port)); ++ IFX_REG_W32(0, PCIE_UESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_CESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_CEMR(pcie_port)); ++ IFX_REG_W32(0, PCIE_RESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); ++ IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); ++ IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_QSR(pcie_port)); ++ IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); ++} ++ ++static inline int ifx_pcie_link_up(int pcie_port) ++{ ++ return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; ++} ++ ++ ++static inline void pcie_mem_io_setup(int pcie_port) ++{ ++ u32 reg; ++ /* ++ * BAR[0:1] readonly register ++ * RC contains only minimal BARs for packets mapped to this device ++ * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that ++ * reside on the downstream side fo the bridge. ++ */ ++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) ++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); ++ ++ IFX_REG_W32(reg, PCIE_MBML(pcie_port)); ++ ++ ++#ifdef IFX_PCIE_PREFETCH_MEM_64BIT ++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR) ++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT) ++ | PCIE_PMBL_64BIT_ADDR; ++ IFX_REG_W32(reg, PCIE_PMBL(pcie_port)); ++ ++ /* Must configure upper 32bit */ ++ IFX_REG_W32(0, PCIE_PMBU32(pcie_port)); ++ IFX_REG_W32(0, PCIE_PMLU32(pcie_port)); ++#else ++ /* PCIe_PBML, same as MBML */ ++ IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); ++#endif ++ ++ /* IO Address Range */ ++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) ++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); ++#ifdef IFX_PCIE_IO_32BIT ++ reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; ++#endif /* IFX_PCIE_IO_32BIT */ ++ IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); ++ ++#ifdef IFX_PCIE_IO_32BIT ++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) ++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); ++ IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); ++ ++#endif /* IFX_PCIE_IO_32BIT */ ++} ++ ++static inline void ++pcie_device_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Device capability register, set up Maximum payload size */ ++ reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); ++ reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; ++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); ++ ++ /* Only available for EP */ ++ reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); ++ IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); ++ ++ /* Device control and status register */ ++ /* Set Maximum Read Request size for the device as a Requestor */ ++ reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); ++ ++ /* ++ * Request size can be larger than the MPS used, but the completions returned ++ * for the read will be bounded by the MPS size. ++ * In our system, Max request size depends on AHB burst size. It is 64 bytes. ++ * but we set it as 128 as minimum one. ++ */ ++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) ++ | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); ++ ++ /* Enable relaxed ordering, no snoop, and all kinds of errors */ ++ reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; ++ ++ IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); ++} ++ ++static inline void ++pcie_link_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* ++ * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM ++ * L0s is reported during link training via TS1 order set by N_FTS ++ */ ++ reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); ++ reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; ++ reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); ++ IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); ++ ++ /* Link control and status register */ ++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); ++ ++ /* Link Enable, ASPM enabled */ ++ reg &= ~PCIE_LCTLSTS_LINK_DISABLE; ++ ++#ifdef CONFIG_PCIEASPM ++ /* ++ * We use the same physical reference clock that the platform provides on the connector ++ * It paved the way for ASPM to calculate the new exit Latency ++ */ ++ reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; ++ reg |= PCIE_LCTLSTS_COM_CLK_CFG; ++ /* ++ * We should disable ASPM by default except that we have dedicated power management support ++ * Enable ASPM will cause the system hangup/instability, performance degration ++ */ ++ reg |= PCIE_LCTLSTS_ASPM_ENABLE; ++#else ++ reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; ++#endif /* CONFIG_PCIEASPM */ ++ ++ /* ++ * The maximum size of any completion with data packet is bounded by the MPS setting ++ * in device control register ++ */ ++ ++ /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ ++ reg &= ~ PCIE_LCTLSTS_RCB128; ++ ++ IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); ++} ++ ++static inline void pcie_error_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* ++ * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone ++ * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE ++ */ ++ reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); ++ reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; ++ ++ IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); ++ ++ /* Uncorrectable Error Mask Register, Unmask all bits in PCIE_UESR */ ++ reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); ++ reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; ++ IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); ++ ++ /* Uncorrectable Error Severity Register, ALL errors are FATAL */ ++ IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); ++ ++ /* Correctable Error Mask Register, unmask all bits */ ++ reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); ++ reg &= ~PCIE_CORRECTABLE_ERR; ++ IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); ++ ++ /* Advanced Error Capabilities and Control Registr */ ++ reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); ++ reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; ++ IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); ++ ++ /* Root Error Command Register, Report all types of errors */ ++ reg = IFX_REG_R32(PCIE_RECR(pcie_port)); ++ reg |= PCIE_RECR_ERR_REPORT_EN; ++ IFX_REG_W32(reg, PCIE_RECR(pcie_port)); ++ ++ /* Clear the Root status register */ ++ reg = IFX_REG_R32(PCIE_RESR(pcie_port)); ++ IFX_REG_W32(reg, PCIE_RESR(pcie_port)); ++} ++ ++static inline void pcie_port_logic_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ ++ reg = IFX_REG_R32(PCIE_AFR(pcie_port)); ++ reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); ++ reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) ++ | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); ++ /* L0s and L1 entry latency */ ++ reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); ++ reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) ++ | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); ++ IFX_REG_W32(reg, PCIE_AFR(pcie_port)); ++ ++ ++ /* Port Link Control Register */ ++ reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); ++ reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ ++ IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); ++ ++ /* Lane Skew Register */ ++ reg = IFX_REG_R32(PCIE_LSR(pcie_port)); ++ /* Enable ACK/NACK and FC */ ++ reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); ++ IFX_REG_W32(reg, PCIE_LSR(pcie_port)); ++ ++ /* Symbol Timer Register and Filter Mask Register 1 */ ++ reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); ++ ++ /* Default SKP interval is very accurate already, 5us */ ++ /* Enable IO/CFG transaction */ ++ reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; ++ /* Disable FC WDT */ ++ reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; ++ IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); ++ ++ /* Filter Masker Register 2 */ ++ reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); ++ reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; ++ IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); ++ ++ /* VC0 Completion Receive Queue Control Register */ ++ reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); ++ reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; ++ reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); ++ IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); ++} ++ ++static inline void pcie_rc_cfg_reg_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Disable LTSSM */ ++ IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */ ++ ++ pcie_mem_io_setup(pcie_port); ++ ++ /* XXX, MSI stuff should only apply to EP */ ++ /* MSI Capability: Only enable 32-bit addresses */ ++ reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); ++ reg &= ~PCIE_MCAPR_ADDR64_CAP; ++ ++ reg |= PCIE_MCAPR_MSI_ENABLE; ++ ++ /* Disable multiple message */ ++ reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); ++ IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); ++ ++ ++ /* Enable PME, Soft reset enabled */ ++ reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); ++ reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; ++ IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); ++ ++ /* setup the bus */ ++ reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); ++ IFX_REG_W32(reg, PCIE_BNR(pcie_port)); ++ ++ ++ pcie_device_setup(pcie_port); ++ pcie_link_setup(pcie_port); ++ pcie_error_setup(pcie_port); ++ ++ /* Root control and capabilities register */ ++ reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); ++ reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; ++ IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); ++ ++ /* Port VC Capability Register 2 */ ++ reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); ++ reg &= ~PCIE_PVC2_VC_ARB_WRR; ++ reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; ++ IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); ++ ++ /* VC0 Resource Capability Register */ ++ reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); ++ reg &= ~PCIE_VC0_RC_REJECT_SNOOP; ++ IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); ++ ++ pcie_port_logic_setup(pcie_port); ++} ++ ++static int ifx_pcie_wait_phy_link_up(int pcie_port) ++{ ++#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 /* XXX, tunable */ ++ int i; ++ ++ /* Wait for PHY link is up */ ++ for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { ++ if (ifx_pcie_link_up(pcie_port)) { ++ break; ++ } ++ udelay(100); ++ } ++ if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { ++ printk(KERN_ERR "%s timeout\n", __func__); ++ return -1; ++ } ++ ++ /* Check data link up or not */ ++ if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { ++ printk(KERN_ERR "%s DLL link is still down\n", __func__); ++ return -1; ++ } ++ ++ /* Check Data link active or not */ ++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { ++ printk(KERN_ERR "%s DLL is not active\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static inline int pcie_app_loigc_setup(int pcie_port) ++{ ++ /* supress ahb bus errrors */ ++ IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); ++ ++ /* Pull PCIe EP out of reset */ ++ pcie_device_rst_deassert(pcie_port); ++ ++ /* Start LTSSM training between RC and EP */ ++ pcie_ltssm_enable(pcie_port); ++ ++ /* Check PHY status after enabling LTSSM */ ++ if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) ++ return -1; ++ ++ return 0; ++} ++ ++/* ++ * The numbers below are directly from the PCIe spec table 3-4/5. ++ */ ++static inline void pcie_replay_time_update(int pcie_port) ++{ ++ u32 reg; ++ int nlw; ++ int rtl; ++ ++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); ++ ++ nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); ++ switch (nlw) { ++ case PCIE_MAX_LENGTH_WIDTH_X1: ++ rtl = 1677; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X2: ++ rtl = 867; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X4: ++ rtl = 462; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X8: ++ rtl = 258; ++ break; ++ default: ++ rtl = 1677; ++ break; ++ } ++ reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); ++ reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; ++ reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); ++ IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); ++} ++ ++/* ++ * Table 359 Enhanced Configuration Address Mapping1) ++ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 ++ * Memory Address PCI Express Configuration Space ++ * A[(20+n-1):20] Bus Number 1 < n < 8 ++ * A[19:15] Device Number ++ * A[14:12] Function Number ++ * A[11:8] Extended Register Number ++ * A[7:2] Register Number ++ * A[1:0] Along with size of the access, used to generate Byte Enables ++ * For VR9, only the address bits [22:0] are mapped to the configuration space: ++ * . Address bits [22:20] select the target bus (1-of-8)1) ++ * . Address bits [19:15] select the target device (1-of-32) on the bus ++ * . Address bits [14:12] select the target function (1-of-8) within the device. ++ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space ++ * . Address bits [1:0] define the start byte location within the selected dword. ++ */ ++static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where) ++{ ++ u32 addr; ++ u8 bus; ++ ++ if (!bus_num) { ++ /* type 0 */ ++ addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); ++ } else { ++ bus = bus_num; ++ /* type 1, only support 8 buses */ ++ addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | ++ ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); ++ } ++ return addr; ++} ++ ++static int pcie_valid_config(int pcie_port, int bus, int dev) ++{ ++ /* RC itself */ ++ if ((bus == 0) && (dev == 0)) { ++ return 1; ++ } ++ ++ /* No physical link */ ++ if (!ifx_pcie_link_up(pcie_port)) { ++ return 0; ++ } ++ ++ /* Bus zero only has RC itself ++ * XXX, check if EP will be integrated ++ */ ++ if ((bus == 0) && (dev != 0)) { ++ return 0; ++ } ++ ++ /* Maximum 8 buses supported for VRX */ ++ if (bus > 9) { ++ return 0; ++ } ++ ++ /* ++ * PCIe is PtP link, one bus only supports only one device ++ * except bus zero and PCIe switch which is virtual bus device ++ * The following two conditions really depends on the system design ++ * and attached the device. ++ * XXX, how about more new switch ++ */ ++ if ((bus == 1) && (dev != 0)) { ++ return 0; ++ } ++ ++ if ((bus >= 3) && (dev != 0)) { ++ return 0; ++ } ++ return 1; ++} ++ ++static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg) ++{ ++ return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val) ++{ ++ IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg) ++{ ++ return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val) ++{ ++ IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++u32 ifx_pcie_bus_enum_read_hack(int where, u32 value) ++{ ++ u32 tvalue = value; ++ ++ if (where == PCI_PRIMARY_BUS) { ++ u8 primary, secondary, subordinate; ++ ++ primary = tvalue & 0xFF; ++ secondary = (tvalue >> 8) & 0xFF; ++ subordinate = (tvalue >> 16) & 0xFF; ++ primary += pcibios_1st_host_bus_nr(); ++ secondary += pcibios_1st_host_bus_nr(); ++ subordinate += pcibios_1st_host_bus_nr(); ++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); ++ } ++ return tvalue; ++} ++ ++u32 ifx_pcie_bus_enum_write_hack(int where, u32 value) ++{ ++ u32 tvalue = value; ++ ++ if (where == PCI_PRIMARY_BUS) { ++ u8 primary, secondary, subordinate; ++ ++ primary = tvalue & 0xFF; ++ secondary = (tvalue >> 8) & 0xFF; ++ subordinate = (tvalue >> 16) & 0xFF; ++ if (primary > 0 && primary != 0xFF) { ++ primary -= pcibios_1st_host_bus_nr(); ++ } ++ ++ if (secondary > 0 && secondary != 0xFF) { ++ secondary -= pcibios_1st_host_bus_nr(); ++ } ++ if (subordinate > 0 && subordinate != 0xFF) { ++ subordinate -= pcibios_1st_host_bus_nr(); ++ } ++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); ++ } ++ else if (where == PCI_SUBORDINATE_BUS) { ++ u8 subordinate = tvalue & 0xFF; ++ ++ subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; ++ tvalue = subordinate; ++ } ++ return tvalue; ++} ++ ++static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 *value) ++{ ++ u32 data = 0; ++ int bus_number = bus->number; ++ static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; ++ int ret = PCIBIOS_SUCCESSFUL; ++ struct ifx_pci_controller *ctrl = bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ if (unlikely(size != 1 && size != 2 && size != 4)){ ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ ++ /* Make sure the address is aligned to natural boundary */ ++ if (unlikely(((size - 1) & where))) { ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ ++ /* ++ * If we are second controller, we have to cheat OS so that it assume ++ * its bus number starts from 0 in host controller ++ */ ++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); ++ ++ /* ++ * We need to force the bus number to be zero on the root ++ * bus. Linux numbers the 2nd root bus to start after all ++ * busses on root 0. ++ */ ++ if (bus->parent == NULL) { ++ bus_number = 0; ++ } ++ ++ /* ++ * PCIe only has a single device connected to it. It is ++ * always device ID 0. Don't bother doing reads for other ++ * device IDs on the first segment. ++ */ ++ if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { ++ ret = PCIBIOS_FUNC_NOT_SUPPORTED; ++ goto out; ++ } ++ ++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { ++ *value = 0xffffffff; ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ goto out; ++ } ++ ++ PCIE_IRQ_LOCK(ifx_pcie_lock); ++ if (bus_number == 0) { /* RC itself */ ++ u32 t; ++ ++ t = (where & ~3); ++ data = ifx_pcie_rc_cfg_rd(pcie_port, t); ++ } else { ++ u32 addr = pcie_bus_addr(bus_number, devfn, where); ++ ++ data = ifx_pcie_cfg_rd(pcie_port, addr); ++ #ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = le32_to_cpu(data); ++ #endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ } ++ /* To get a correct PCI topology, we have to restore the bus number to OS */ ++ data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); ++ ++ PCIE_IRQ_UNLOCK(ifx_pcie_lock); ++ ++ *value = (data >> (8 * (where & 3))) & mask[size & 7]; ++out: ++ return ret; ++} ++ ++static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value) ++{ ++ u32 shift; ++ u32 tdata = data; ++ ++ switch (size) { ++ case 1: ++ shift = (where & 0x3) << 3; ++ tdata &= ~(0xffU << shift); ++ tdata |= ((value & 0xffU) << shift); ++ break; ++ case 2: ++ shift = (where & 3) << 3; ++ tdata &= ~(0xffffU << shift); ++ tdata |= ((value & 0xffffU) << shift); ++ break; ++ case 4: ++ tdata = value; ++ break; ++ } ++ return tdata; ++} ++ ++static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 value) ++{ ++ int bus_number = bus->number; ++ int ret = PCIBIOS_SUCCESSFUL; ++ struct ifx_pci_controller *ctrl = bus->sysdata; ++ int pcie_port = ctrl->port; ++ u32 tvalue = value; ++ u32 data; ++ ++ /* Make sure the address is aligned to natural boundary */ ++ if (unlikely(((size - 1) & where))) { ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ /* ++ * If we are second controller, we have to cheat OS so that it assume ++ * its bus number starts from 0 in host controller ++ */ ++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); ++ ++ /* ++ * We need to force the bus number to be zero on the root ++ * bus. Linux numbers the 2nd root bus to start after all ++ * busses on root 0. ++ */ ++ if (bus->parent == NULL) { ++ bus_number = 0; ++ } ++ ++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ goto out; ++ } ++ ++ /* XXX, some PCIe device may need some delay */ ++ PCIE_IRQ_LOCK(ifx_pcie_lock); ++ ++ /* ++ * To configure the correct bus topology using native way, we have to cheat Os so that ++ * it can configure the PCIe hardware correctly. ++ */ ++ tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); ++ ++ if (bus_number == 0) { /* RC itself */ ++ u32 t; ++ ++ t = (where & ~3); ++ data = ifx_pcie_rc_cfg_rd(pcie_port, t); ++ ++ data = ifx_pcie_size_to_value(where, size, data, tvalue); ++ ++ ifx_pcie_rc_cfg_wr(pcie_port, t, data); ++ } else { ++ u32 addr = pcie_bus_addr(bus_number, devfn, where); ++ ++ data = ifx_pcie_cfg_rd(pcie_port, addr); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = le32_to_cpu(data); ++#endif ++ ++ data = ifx_pcie_size_to_value(where, size, data, tvalue); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = cpu_to_le32(data); ++#endif ++ ifx_pcie_cfg_wr(pcie_port, addr, data); ++ } ++ PCIE_IRQ_UNLOCK(ifx_pcie_lock); ++out: ++ return ret; ++} ++ ++static struct resource ifx_pcie_io_resource = { ++ .name = "PCIe0 I/O space", ++ .start = PCIE_IO_PHY_BASE, ++ .end = PCIE_IO_PHY_END, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource ifx_pcie_mem_resource = { ++ .name = "PCIe0 Memory space", ++ .start = PCIE_MEM_PHY_BASE, ++ .end = PCIE_MEM_PHY_END, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct pci_ops ifx_pcie_ops = { ++ .read = ifx_pcie_read_config, ++ .write = ifx_pcie_write_config, ++}; ++ ++static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { ++ { ++ .pcic = { ++ .pci_ops = &ifx_pcie_ops, ++ .mem_resource = &ifx_pcie_mem_resource, ++ .io_resource = &ifx_pcie_io_resource, ++ }, ++ .port = IFX_PCIE_PORT0, ++ }, ++}; ++ ++#ifdef IFX_PCIE_ERROR_INT ++ ++static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) ++{ ++ struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; ++ int pcie_port = ctrl->port; ++ u32 reg; ++ ++ pr_debug("PCIe RC error intr %d\n", irq); ++ reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); ++ reg &= PCIE_RC_CORE_COMBINED_INT; ++ IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ++pcie_rc_core_int_init(int pcie_port) ++{ ++ int ret; ++ ++ /* Enable core interrupt */ ++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); ++ ++ /* Clear it first */ ++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); ++ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0, ++ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); ++ if (ret) ++ printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); ++ ++ return ret; ++} ++#endif ++ ++int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ u32 irq_bit = 0; ++ int irq = 0; ++ struct ifx_pci_controller *ctrl = dev->bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); ++ ++ if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { ++ printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); ++ return -1; ++ } ++ ++ /* Pin index so minus one */ ++ irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; ++ irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; ++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); ++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); ++ printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); ++ return irq; ++} ++ ++int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) ++{ ++ u16 config; ++#ifdef IFX_PCIE_ERROR_INT ++ u32 dconfig; ++ int pos; ++#endif ++ ++ /* Enable reporting System errors and parity errors on all devices */ ++ /* Enable parity checking and error reporting */ ++ pci_read_config_word(dev, PCI_COMMAND, &config); ++ config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | ++ PCI_COMMAND_FAST_BACK*/; ++ pci_write_config_word(dev, PCI_COMMAND, config); ++ ++ if (dev->subordinate) { ++ /* Set latency timers on sub bridges */ ++ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ ++ /* More bridge error detection */ ++ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); ++ config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; ++ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); ++ } ++#ifdef IFX_PCIE_ERROR_INT ++ /* Enable the PCIe normal error reporting */ ++ pos = pci_find_capability(dev, PCI_CAP_ID_EXP); ++ if (pos) { ++ ++ /* Disable system error generation in response to error messages */ ++ pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); ++ config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); ++ pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); ++ ++ /* Clear PCIE Capability's Device Status */ ++ pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); ++ pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); ++ ++ /* Update Device Control */ ++ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); ++ /* Correctable Error Reporting */ ++ config |= PCI_EXP_DEVCTL_CERE; ++ /* Non-Fatal Error Reporting */ ++ config |= PCI_EXP_DEVCTL_NFERE; ++ /* Fatal Error Reporting */ ++ config |= PCI_EXP_DEVCTL_FERE; ++ /* Unsupported Request */ ++ config |= PCI_EXP_DEVCTL_URRE; ++ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); ++ } ++ ++ /* Find the Advanced Error Reporting capability */ ++ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); ++ if (pos) { ++ /* Clear Uncorrectable Error Status */ ++ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); ++ /* Enable reporting of all uncorrectable errors */ ++ /* Uncorrectable Error Mask - turned on bits disable errors */ ++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); ++ /* ++ * Leave severity at HW default. This only controls if ++ * errors are reported as uncorrectable or ++ * correctable, not if the error is reported. ++ */ ++ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ ++ /* Clear Correctable Error Status */ ++ pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); ++ /* Enable reporting of all correctable errors */ ++ /* Correctable Error Mask - turned on bits disable errors */ ++ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); ++ /* Advanced Error Capabilities */ ++ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); ++ /* ECRC Generation Enable */ ++ if (dconfig & PCI_ERR_CAP_ECRC_GENC) { ++ dconfig |= PCI_ERR_CAP_ECRC_GENE; ++ } ++ /* ECRC Check Enable */ ++ if (dconfig & PCI_ERR_CAP_ECRC_CHKC) { ++ dconfig |= PCI_ERR_CAP_ECRC_CHKE; ++ } ++ pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); ++ ++ /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ ++ /* Enable Root Port's interrupt in response to error messages */ ++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, ++ PCI_ERR_ROOT_CMD_COR_EN | ++ PCI_ERR_ROOT_CMD_NONFATAL_EN | ++ PCI_ERR_ROOT_CMD_FATAL_EN); ++ /* Clear the Root status register */ ++ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); ++ } ++#endif /* IFX_PCIE_ERROR_INT */ ++ /* WAR, only 128 MRRS is supported, force all EPs to support this value */ ++ pcie_set_readrq(dev, 128); ++ return 0; ++} ++ ++static int ++pcie_rc_initialize(int pcie_port) ++{ ++ int i; ++#define IFX_PCIE_PHY_LOOP_CNT 5 ++ ++ pcie_rcu_endian_setup(pcie_port); ++ ++ pcie_ep_gpio_rst_init(pcie_port); ++ ++ /* ++ * XXX, PCIe elastic buffer bug will cause not to be detected. One more ++ * reset PCIe PHY will solve this issue ++ */ ++ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { ++ /* Disable PCIe PHY Analog part for sanity check */ ++ pcie_phy_pmu_disable(pcie_port); ++ ++ pcie_phy_rst_assert(pcie_port); ++ pcie_phy_rst_deassert(pcie_port); ++ ++ /* Make sure PHY PLL is stable */ ++ udelay(20); ++ ++ /* PCIe Core reset enabled, low active, sw programmed */ ++ pcie_core_rst_assert(pcie_port); ++ ++ /* Put PCIe EP in reset status */ ++ pcie_device_rst_assert(pcie_port); ++ ++ /* PCI PHY & Core reset disabled, high active, sw programmed */ ++ pcie_core_rst_deassert(pcie_port); ++ ++ /* Already in a quiet state, program PLL, enable PHY, check ready bit */ ++ pcie_phy_clock_mode_setup(pcie_port); ++ ++ /* Enable PCIe PHY and Clock */ ++ pcie_core_pmu_setup(pcie_port); ++ ++ /* Clear status registers */ ++ pcie_status_register_clear(pcie_port); ++ ++#ifdef CONFIG_PCI_MSI ++ pcie_msi_init(pcie_port); ++#endif /* CONFIG_PCI_MSI */ ++ pcie_rc_cfg_reg_setup(pcie_port); ++ ++ /* Once link is up, break out */ ++ if (pcie_app_loigc_setup(pcie_port) == 0) ++ break; ++ } ++ if (i >= IFX_PCIE_PHY_LOOP_CNT) { ++ printk(KERN_ERR "%s link up failed!!!!!\n", __func__); ++ return -EIO; ++ } ++ /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ ++ pcie_replay_time_update(pcie_port); ++ return 0; ++} ++ ++static int __init ifx_pcie_bios_init(void) ++{ ++ void __iomem *io_map_base; ++ int pcie_port; ++ int startup_port; ++ ++ /* Enable AHB Master/ Slave */ ++ pcie_ahb_pmu_setup(); ++ ++ startup_port = IFX_PCIE_PORT0; ++ ++ for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ ++ if (pcie_rc_initialize(pcie_port) == 0) { ++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", ++ __func__, PCIE_CFG_PORT_TO_BASE(pcie_port)); ++ /* Otherwise, warning will pop up */ ++ io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); ++ if (io_map_base == NULL) { ++ IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__); ++ return -ENOMEM; ++ } ++ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; ++ ++ register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); ++ /* XXX, clear error status */ ++ ++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n", ++ __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, ++ &ifx_pcie_controller[pcie_port].pcic.io_resource); ++ ++ #ifdef IFX_PCIE_ERROR_INT ++ pcie_rc_core_int_init(pcie_port); ++ #endif /* IFX_PCIE_ERROR_INT */ ++ } ++ } ++ ++ return 0; ++} ++arch_initcall(ifx_pcie_bios_init); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); ++MODULE_SUPPORTED_DEVICE("Infineon builtin PCIe RC module"); ++MODULE_DESCRIPTION("Infineon builtin PCIe RC driver"); ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie.h +@@ -0,0 +1,131 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_H ++#define IFXMIPS_PCIE_H ++#include ++#include ++#include ++#include ++#include "ifxmips_pci_common.h" ++#include "ifxmips_pcie_reg.h" ++ ++/*! ++ \defgroup IFX_PCIE PCI Express bus driver module ++ \brief PCI Express IP module support VRX200 ++*/ ++ ++/*! ++ \defgroup IFX_PCIE_OS OS APIs ++ \ingroup IFX_PCIE ++ \brief PCIe bus driver OS interface functions ++*/ ++ ++/*! ++ \file ifxmips_pcie.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module common header file ++*/ ++#define PCIE_IRQ_LOCK(lock) do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(&(lock), flags); ++#define PCIE_IRQ_UNLOCK(lock) \ ++ spin_unlock_irqrestore(&(lock), flags); \ ++} while (0) ++ ++#define PCIE_MSG_MSI 0x00000001 ++#define PCIE_MSG_ISR 0x00000002 ++#define PCIE_MSG_FIXUP 0x00000004 ++#define PCIE_MSG_READ_CFG 0x00000008 ++#define PCIE_MSG_WRITE_CFG 0x00000010 ++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) ++#define PCIE_MSG_REG 0x00000020 ++#define PCIE_MSG_INIT 0x00000040 ++#define PCIE_MSG_ERR 0x00000080 ++#define PCIE_MSG_PHY 0x00000100 ++#define PCIE_MSG_ANY 0x000001ff ++ ++#define IFX_PCIE_PORT0 0 ++#define IFX_PCIE_PORT1 1 ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++#define IFX_PCIE_CORE_NR 2 ++#else ++#define IFX_PCIE_CORE_NR 1 ++#endif ++ ++#define IFX_PCIE_ERROR_INT ++ ++//#define IFX_PCIE_DBG ++ ++#if defined(IFX_PCIE_DBG) ++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ ++ ifx_pcie_debug((_fmt), ##args); \ ++} while (0) ++ ++#define INLINE ++#else ++#define IFX_PCIE_PRINT(_m, _fmt, args...) \ ++ do {} while(0) ++#define INLINE inline ++#endif ++ ++struct ifx_pci_controller { ++ struct pci_controller pcic; ++ ++ /* RC specific, per host bus information */ ++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ ++}; ++ ++typedef struct ifx_pcie_ir_irq { ++ const unsigned int irq; ++ const char name[16]; ++}ifx_pcie_ir_irq_t; ++ ++typedef struct ifx_pcie_legacy_irq{ ++ const u32 irq_bit; ++ const int irq; ++}ifx_pcie_legacy_irq_t; ++ ++typedef struct ifx_pcie_irq { ++ ifx_pcie_ir_irq_t ir_irq; ++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; ++}ifx_pcie_irq_t; ++ ++extern u32 g_pcie_debug_flag; ++extern void ifx_pcie_debug(const char *fmt, ...); ++extern void pcie_phy_clock_mode_setup(int pcie_port); ++extern void pcie_msi_pic_init(int pcie_port); ++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); ++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); ++ ++#define CONFIG_VR9 ++ ++#ifdef CONFIG_VR9 ++#include "ifxmips_pcie_vr9.h" ++#elif defined (CONFIG_AR10) ++#include "ifxmips_pcie_ar10.h" ++#else ++#error "PCIE: platform not defined" ++#endif /* CONFIG_VR9 */ ++ ++#endif /* IFXMIPS_PCIE_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_ar10.h +@@ -0,0 +1,290 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++/*! ++ \file ifxmips_pcie_ar10.h ++ \ingroup IFX_PCIE ++ \brief PCIe RC driver ar10 specific file ++*/ ++ ++#ifndef IFXMIPS_PCIE_AR10_H ++#define IFXMIPS_PCIE_AR10_H ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++ ++/* Project header file */ ++#include ++#include ++#include ++#include ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ ifx_ebu_led_enable(); ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 1); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 1); ++ } ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ /* XXX, moved to CGU to control AHBM */ ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ /* Inbound, big endian */ ++ reg |= IFX_RCU_BE_AHB4S; ++ if (pcie_port == 0) { ++ reg |= IFX_RCU_BE_PCIE0M; ++ ++ #ifdef CONFIG_IFX_PCIE_HW_SWAP ++ /* Outbound, software swap needed */ ++ reg |= IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE0S; ++ #else ++ /* Outbound little endian */ ++ reg &= ~IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE0S; ++ #endif ++ } ++ else { ++ reg |= IFX_RCU_BE_PCIE1M; ++ #ifdef CONFIG_IFX_PCIE1_HW_SWAP ++ /* Outbound, software swap needed */ ++ reg |= IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE1S; ++ #else ++ /* Outbound little endian */ ++ reg &= ~IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE1S; ++ #endif ++ } ++ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ if (pcie_port == 0) { /* XXX, should use macro*/ ++ PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_phy_pmu_disable(int pcie_port) ++{ ++ if (pcie_port == 0) { /* XXX, should use macro*/ ++ PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++ } ++ else { ++ PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++ } ++} ++ ++static inline void pcie_pdi_big_endian(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ if (pcie_port == 0) { ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_BE_PCIE0_PDI; ++ } ++ else { ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_BE_PCIE1_PDI; ++ } ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ /* Enable PDI to access PCIe PHY register */ ++ PDI0_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PDI1_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_core_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ ++ /* Reset Core, bit 22 */ ++ if (pcie_port == 0) { ++ reg |= 0x00400000; ++ } ++ else { ++ reg |= 0x08000000; /* Bit 27 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_core_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg &= ~0x00400000; /* bit 22 */ ++ } ++ else { ++ reg &= ~0x08000000; /* Bit 27 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg |= 0x00001000; /* Bit 12 */ ++ } ++ else { ++ reg |= 0x00002000; /* Bit 13 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg &= ~0x00001000; /* Bit 12 */ ++ } ++ else { ++ reg &= ~0x00002000; /* Bit 13 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 0); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 0); ++ } ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 1); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 1); ++ } ++ ifx_ebu_led_disable(); ++} ++ ++static inline void pcie_core_pmu_setup(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_msi_init(int pcie_port) ++{ ++ pcie_msi_pic_init(pcie_port); ++ if (pcie_port == 0) { ++ MSI0_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ MSI1_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline u32 ++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) ++{ ++ u32 tbus_number = bus_number; ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++ } ++#endif /* CONFIG_IFX_PCI */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ } ++ #endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_AR10_H */ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_msi.c +@@ -0,0 +1,392 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_msi.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCI MSI sub module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe MSI Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Date $Author $Comment ++** 02 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \defgroup IFX_PCIE_MSI MSI OS APIs ++ \ingroup IFX_PCIE ++ \brief PCIe bus driver OS interface functions ++*/ ++ ++/*! ++ \file ifxmips_pcie_msi.c ++ \ingroup IFX_PCIE ++ \brief PCIe MSI OS interface file ++*/ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie_reg.h" ++#include "ifxmips_pcie.h" ++ ++#define IFX_MSI_IRQ_NUM 16 ++ ++enum { ++ IFX_PCIE_MSI_IDX0 = 0, ++ IFX_PCIE_MSI_IDX1, ++ IFX_PCIE_MSI_IDX2, ++ IFX_PCIE_MSI_IDX3, ++}; ++ ++typedef struct ifx_msi_irq_idx { ++ const int irq; ++ const int idx; ++}ifx_msi_irq_idx_t; ++ ++struct ifx_msi_pic { ++ volatile u32 pic_table[IFX_MSI_IRQ_NUM]; ++ volatile u32 pic_endian; /* 0x40 */ ++}; ++typedef struct ifx_msi_pic *ifx_msi_pic_t; ++ ++typedef struct ifx_msi_irq { ++ const volatile ifx_msi_pic_t msi_pic_p; ++ const u32 msi_phy_base; ++ const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; ++ /* ++ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is ++ * in use. ++ */ ++ u16 msi_free_irq_bitmask; ++ ++ /* ++ * Each bit in msi_multiple_irq_bitmask tells that the device using ++ * this bit in msi_free_irq_bitmask is also using the next bit. This ++ * is used so we can disable all of the MSI interrupts when a device ++ * uses multiple. ++ */ ++ u16 msi_multiple_irq_bitmask; ++}ifx_msi_irq_t; ++ ++static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { ++ { ++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, ++ .msi_phy_base = PCIE_MSI_PHY_BASE, ++ .msi_irq_idx = { ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ }, ++ .msi_free_irq_bitmask = 0, ++ .msi_multiple_irq_bitmask= 0, ++ }, ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ { ++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, ++ .msi_phy_base = PCIE1_MSI_PHY_BASE, ++ .msi_irq_idx = { ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ }, ++ .msi_free_irq_bitmask = 0, ++ .msi_multiple_irq_bitmask= 0, ++ ++ }, ++#endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++}; ++ ++/* ++ * This lock controls updates to msi_free_irq_bitmask, ++ * msi_multiple_irq_bitmask and pic register settting ++ */ ++static DEFINE_SPINLOCK(ifx_pcie_msi_lock); ++ ++void pcie_msi_pic_init(int pcie_port) ++{ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; ++ spin_unlock(&ifx_pcie_msi_lock); ++} ++ ++/** ++ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ++ * \brief Called when a driver request MSI interrupts instead of the ++ * legacy INT A-D. This routine will allocate multiple interrupts ++ * for MSI devices that support them. A device can override this by ++ * programming the MSI control bits [6:4] before calling ++ * pci_enable_msi(). ++ * ++ * \param[in] pdev Device requesting MSI interrupts ++ * \param[in] desc MSI descriptor ++ * ++ * \return -EINVAL Invalid pcie root port or invalid msi bit ++ * \return 0 OK ++ * \ingroup IFX_PCIE_MSI ++ */ ++int ++arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ++{ ++ int irq, pos; ++ u16 control; ++ int irq_idx; ++ int irq_step; ++ int configured_private_bits; ++ int request_private_bits; ++ struct msi_msg msg; ++ u16 search_mask; ++ struct ifx_pci_controller *ctrl = pdev->bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); ++ ++ /* XXX, skip RC MSI itself */ ++ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* ++ * Read the MSI config to figure out how many IRQs this device ++ * wants. Most devices only want 1, which will give ++ * configured_private_bits and request_private_bits equal 0. ++ */ ++ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); ++ ++ /* ++ * If the number of private bits has been configured then use ++ * that value instead of the requested number. This gives the ++ * driver the chance to override the number of interrupts ++ * before calling pci_enable_msi(). ++ */ ++ configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; ++ if (configured_private_bits == 0) { ++ /* Nothing is configured, so use the hardware requested size */ ++ request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; ++ } ++ else { ++ /* ++ * Use the number of configured bits, assuming the ++ * driver wanted to override the hardware request ++ * value. ++ */ ++ request_private_bits = configured_private_bits; ++ } ++ ++ /* ++ * The PCI 2.3 spec mandates that there are at most 32 ++ * interrupts. If this device asks for more, only give it one. ++ */ ++ if (request_private_bits > 5) { ++ request_private_bits = 0; ++ } ++again: ++ /* ++ * The IRQs have to be aligned on a power of two based on the ++ * number being requested. ++ */ ++ irq_step = (1 << request_private_bits); ++ ++ /* Mask with one bit for each IRQ */ ++ search_mask = (1 << irq_step) - 1; ++ ++ /* ++ * We're going to search msi_free_irq_bitmask_lock for zero ++ * bits. This represents an MSI interrupt number that isn't in ++ * use. ++ */ ++ spin_lock(&ifx_pcie_msi_lock); ++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { ++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { ++ msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; ++ msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; ++ break; ++ } ++ } ++ spin_unlock(&ifx_pcie_msi_lock); ++ ++ /* Make sure the search for available interrupts didn't fail */ ++ if (pos >= IFX_MSI_IRQ_NUM) { ++ if (request_private_bits) { ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " ++ "interrupts, trying just one", __func__, 1 << request_private_bits); ++ request_private_bits = 0; ++ goto again; ++ } ++ else { ++ printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); ++ return -EINVAL; ++ } ++ } ++ irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; ++ irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); ++ ++ /* ++ * Initialize MSI. This has to match the memory-write endianess from the device ++ * Address bits [23:12] ++ */ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | ++ SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | ++ SM((1 << pos), IFX_MSI_PIC_MSG_DATA); ++ ++ /* Enable this entry */ ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; ++ spin_unlock(&ifx_pcie_msi_lock); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", ++ pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); ++ ++ /* Update the number of IRQs the device has available to it */ ++ control &= ~PCI_MSI_FLAGS_QSIZE; ++ control |= (request_private_bits << 4); ++ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); ++ ++ set_irq_msi(irq, desc); ++ msg.address_hi = 0x0; ++ msg.address_lo = msi_irqs[pcie_port].msi_phy_base; ++ msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); ++ ++ write_msi_msg(irq, &msg); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); ++ return 0; ++} ++ ++static int ++pcie_msi_irq_to_port(unsigned int irq, int *port) ++{ ++ int ret = 0; ++ ++ if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || ++ irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { ++ *port = IFX_PCIE_PORT0; ++ } ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || ++ irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { ++ *port = IFX_PCIE_PORT1; ++ } ++#endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++ else { ++ printk(KERN_ERR "%s: Attempted to teardown illegal " ++ "MSI interrupt (%d)\n", __func__, irq); ++ ret = -EINVAL; ++ } ++ return ret; ++} ++ ++/** ++ * \fn void arch_teardown_msi_irq(unsigned int irq) ++ * \brief Called when a device no longer needs its MSI interrupts. All ++ * MSI interrupts for the device are freed. ++ * ++ * \param irq The devices first irq number. There may be multple in sequence. ++ * \return none ++ * \ingroup IFX_PCIE_MSI ++ */ ++void ++arch_teardown_msi_irq(unsigned int irq) ++{ ++ int pos; ++ int number_irqs; ++ u16 bitmask; ++ int pcie_port; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); ++ ++ BUG_ON(irq > INT_NUM_IM4_IRL31); ++ ++ if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { ++ return; ++ } ++ ++ /* Shift the mask to the correct bit location, not always correct ++ * Probally, the first match will be chosen. ++ */ ++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { ++ if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) ++ && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { ++ break; ++ } ++ } ++ if (pos >= IFX_MSI_IRQ_NUM) { ++ printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); ++ return; ++ } ++ spin_lock(&ifx_pcie_msi_lock); ++ /* Disable this entry */ ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); ++ spin_unlock(&ifx_pcie_msi_lock); ++ /* ++ * Count the number of IRQs we need to free by looking at the ++ * msi_multiple_irq_bitmask. Each bit set means that the next ++ * IRQ is also owned by this device. ++ */ ++ number_irqs = 0; ++ while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && ++ (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { ++ number_irqs++; ++ } ++ number_irqs++; ++ ++ /* Mask with one bit for each IRQ */ ++ bitmask = (1 << number_irqs) - 1; ++ ++ bitmask <<= pos; ++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { ++ printk(KERN_ERR "%s: Attempted to teardown MSI " ++ "interrupt (%d) not in use\n", __func__, irq); ++ return; ++ } ++ /* Checks are done, update the in use bitmask */ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; ++ msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); ++ spin_unlock(&ifx_pcie_msi_lock); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); ++} ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); ++MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module"); ++MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_phy.c +@@ -0,0 +1,478 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_phy.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe PHY sub module ++** ++** DATE : 14 May 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 14 May,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \file ifxmips_pcie_phy.c ++ \ingroup IFX_PCIE ++ \brief PCIe PHY PLL register programming source file ++*/ ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie_reg.h" ++#include "ifxmips_pcie.h" ++ ++/* PCIe PDI only supports 16 bit operation */ ++ ++#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ ++ ((*(volatile u16 *) (__addr)) = (__data)) ++ ++#define IFX_PCIE_PHY_REG_READ16(__addr) \ ++ (*(volatile u16 *) (__addr)) ++ ++#define IFX_PCIE_PHY_REG16(__addr) \ ++ (*(volatile u16 *) (__addr)) ++ ++#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ ++ u16 read_data; \ ++ u16 write_data; \ ++ read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ ++ write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ ++ IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ ++} while (0) ++ ++#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ ++ ++//#define IFX_PCI_PHY_REG_DUMP ++ ++#ifdef IFX_PCI_PHY_REG_DUMP ++static void ++pcie_phy_reg_dump(int pcie_port) ++{ ++ printk("PLL REGFILE\n"); ++ printk("PCIE_PHY_PLL_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL4 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL5 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL6 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL7 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port))); ++ printk("PCIE_PHY_PLL_STATUS 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port))); ++ ++ printk("TX1 REGFILE\n"); ++ printk("PCIE_PHY_TX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX1_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port))); ++ printk("PCIE_PHY_TX1_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX1_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port))); ++ ++ printk("TX2 REGFILE\n"); ++ printk("PCIE_PHY_TX2_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX2_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX2_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX2_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port))); ++ ++ printk("RX1 REGFILE\n"); ++ printk("PCIE_PHY_RX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port))); ++ printk("PCIE_PHY_RX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port))); ++ printk("PCIE_PHY_RX1_CDR 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port))); ++ printk("PCIE_PHY_RX1_EI 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port))); ++ printk("PCIE_PHY_RX1_A_CTRL 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port))); ++} ++#endif /* IFX_PCI_PHY_REG_DUMP */ ++ ++static void ++pcie_phy_comm_setup(int pcie_port) ++{ ++ /* PLL Setting */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); ++ ++ /* increase the bias reference voltage */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); ++ ++ /* Endcnt */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); ++ ++ /* force */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); ++ ++ /* ctrl_lim */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); ++ ++ /* ctrl */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); ++ ++ /* RTERM*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); ++ ++ /* Improved 100MHz clock output */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); ++ ++ /* Reduced CDR BW to avoid glitches */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); ++} ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++static void ++pcie_phy_36mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE ++static void ++pcie_phy_36mhz_ssc_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ ++ /* PLL Setting */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); ++ ++ /* Increase the bias reference voltage */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); ++ ++ /* Endcnt */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); ++ ++ /* Force */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); ++ ++ /* Predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); ++ ++ /* ctrl_lim */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); ++ ++ /* ctrl */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); ++ ++ /* RTERM*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); ++ ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); ++ ++ /* improved 100MHz clock output */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); ++ ++ /* reduced CDR BW to avoid glitches */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE ++static void ++pcie_phy_25mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); ++ ++ /* en_ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE ++static void ++pcie_phy_100mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ ++ ++static int ++pcie_phy_wait_startup_ready(int pcie_port) ++{ ++ int i; ++ ++ for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { ++ if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { ++ break; ++ } ++ udelay(10); ++ } ++ if (i >= IFX_PCIE_PLL_TIMEOUT) { ++ printk(KERN_ERR "%s PLL Link timeout\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static void ++pcie_phy_load_enable(int pcie_port, int slice) ++{ ++ /* Set the load_en of tx/rx slice to '1' */ ++ switch (slice) { ++ case 1: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); ++ break; ++ case 2: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); ++ break; ++ case 3: ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); ++ break; ++ } ++} ++ ++static void ++pcie_phy_load_disable(int pcie_port, int slice) ++{ ++ /* set the load_en of tx/rx slice to '0' */ ++ switch (slice) { ++ case 1: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); ++ break; ++ case 2: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); ++ break; ++ case 3: ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); ++ break; ++ } ++} ++ ++static void ++pcie_phy_load_war(int pcie_port) ++{ ++ int slice; ++ ++ for (slice = 1; slice < 4; slice++) { ++ pcie_phy_load_enable(pcie_port, slice); ++ udelay(1); ++ pcie_phy_load_disable(pcie_port, slice); ++ } ++} ++ ++static void ++pcie_phy_tx2_modulation(int pcie_port) ++{ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); ++ mdelay(1); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); ++} ++ ++static void ++pcie_phy_tx1_modulation(int pcie_port) ++{ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); ++ mdelay(1); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); ++} ++ ++static void ++pcie_phy_tx_modulation_war(int pcie_port) ++{ ++ int i; ++ ++#define PCIE_PHY_MODULATION_NUM 5 ++ for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { ++ pcie_phy_tx2_modulation(pcie_port); ++ pcie_phy_tx1_modulation(pcie_port); ++ } ++#undef PCIE_PHY_MODULATION_NUM ++} ++ ++void ++pcie_phy_clock_mode_setup(int pcie_port) ++{ ++ pcie_pdi_big_endian(pcie_port); ++ ++ /* Enable PDI to access PCIe PHY register */ ++ pcie_pdi_pmu_enable(pcie_port); ++ ++ /* Configure PLL and PHY clock */ ++ pcie_phy_comm_setup(pcie_port); ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ pcie_phy_36mhz_mode_setup(pcie_port); ++#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) ++ pcie_phy_36mhz_ssc_mode_setup(pcie_port); ++#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) ++ pcie_phy_25mhz_mode_setup(pcie_port); ++#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) ++ pcie_phy_100mhz_mode_setup(pcie_port); ++#else ++ #error "PCIE PHY Clock Mode must be chosen first!!!!" ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ ++ ++ /* Enable PCIe PHY and make PLL setting take effect */ ++ pcie_phy_pmu_enable(pcie_port); ++ ++ /* Check if we are in startup_ready status */ ++ pcie_phy_wait_startup_ready(pcie_port); ++ ++ pcie_phy_load_war(pcie_port); ++ ++ /* Apply TX modulation workarounds */ ++ pcie_phy_tx_modulation_war(pcie_port); ++ ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++} ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_pm.c +@@ -0,0 +1,176 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_pm.c ++** PROJECT : IFX UEIP ++** MODULES : PCIE Root Complex Driver ++** ++** DATE : 21 Dec 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIE Root Complex Driver Power Managment ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 Dec,2009 Lei Chuanhua First UEIP release ++*******************************************************************************/ ++/*! ++ \defgroup IFX_PCIE_PM Power Management functions ++ \ingroup IFX_PCIE ++ \brief IFX PCIE Root Complex Driver power management functions ++*/ ++ ++/*! ++ \file ifxmips_pcie_pm.c ++ \ingroup IFX_PCIE ++ \brief source file for PCIE Root Complex Driver Power Management ++*/ ++ ++#ifndef EXPORT_SYMTAB ++#define EXPORT_SYMTAB ++#endif ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++ ++/* Project header */ ++#include ++#include ++#include ++#include ++#include "ifxmips_pcie_pm.h" ++ ++/** ++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) ++ * \brief the callback function to request pmcu state in the power management hardware-dependent module ++ * ++ * \param pmcuState This parameter is a PMCU state. ++ * ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) ++{ ++ switch(pmcuState) ++ { ++ case IFX_PMCU_STATE_D0: ++ return IFX_PMCU_RETURN_SUCCESS; ++ case IFX_PMCU_STATE_D1: // Not Applicable ++ return IFX_PMCU_RETURN_DENIED; ++ case IFX_PMCU_STATE_D2: // Not Applicable ++ return IFX_PMCU_RETURN_DENIED; ++ case IFX_PMCU_STATE_D3: // Module clock gating and Power gating ++ return IFX_PMCU_RETURN_SUCCESS; ++ default: ++ return IFX_PMCU_RETURN_DENIED; ++ } ++} ++ ++/** ++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) ++ * \brief the callback function to get pmcu state in the power management hardware-dependent module ++ ++ * \param pmcuState Pointer to return power state. ++ * ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule ++ * ++ * \param pmcuModule Module ++ * \param newState New state ++ * \param oldState Old state ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule ++ * ++ * \param pmcuModule Module ++ * \param newState New state ++ * \param oldState Old state ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn static void ifx_pcie_pmcu_init(void) ++ * \brief Register with central PMCU module ++ * \return none ++ * \ingroup IFX_PCIE_PM ++ */ ++void ++ifx_pcie_pmcu_init(void) ++{ ++ IFX_PMCU_REGISTER_t pmcuRegister; ++ ++ /* XXX, hook driver context */ ++ ++ /* State function register */ ++ memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t)); ++ pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; ++ pmcuRegister.pmcuModuleNr = 0; ++ pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change; ++ pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get; ++ pmcuRegister.pre = ifx_pcie_pmcu_prechange; ++ pmcuRegister.post= ifx_pcie_pmcu_postchange; ++ ifx_pmcu_register(&pmcuRegister); ++} ++ ++/** ++ * \fn static void ifx_pcie_pmcu_exit(void) ++ * \brief Unregister with central PMCU module ++ * ++ * \return none ++ * \ingroup IFX_PCIE_PM ++ */ ++void ++ifx_pcie_pmcu_exit(void) ++{ ++ IFX_PMCU_REGISTER_t pmcuUnRegister; ++ ++ /* XXX, hook driver context */ ++ ++ pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; ++ pmcuUnRegister.pmcuModuleNr = 0; ++ ifx_pmcu_unregister(&pmcuUnRegister); ++} ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_pm.h +@@ -0,0 +1,36 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_pm.h ++** PROJECT : IFX UEIP ++** MODULES : PCIe Root Complex Driver ++** ++** DATE : 21 Dec 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver Power Managment ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 Dec,2009 Lei Chuanhua First UEIP release ++*******************************************************************************/ ++/*! ++ \file ifxmips_pcie_pm.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe Root Complex Driver Power Management ++*/ ++ ++#ifndef IFXMIPS_PCIE_PM_H ++#define IFXMIPS_PCIE_PM_H ++ ++void ifx_pcie_pmcu_init(void); ++void ifx_pcie_pmcu_exit(void); ++ ++#endif /* IFXMIPS_PCIE_PM_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_reg.h +@@ -0,0 +1,1001 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_reg.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_REG_H ++#define IFXMIPS_PCIE_REG_H ++/*! ++ \file ifxmips_pcie_reg.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module register definition ++*/ ++/* PCIe Address Mapping Base */ ++#define PCIE_CFG_PHY_BASE 0x1D000000UL ++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) ++#define PCIE_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE_MEM_PHY_BASE 0x1C000000UL ++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) ++#define PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) ++ ++#define PCIE_IO_PHY_BASE 0x1D800000UL ++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) ++#define PCIE_IO_SIZE (1 * 1024 * 1024) ++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) ++ ++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) ++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) ++#define PCIE_MSI_PHY_BASE 0x1F600000UL ++ ++#define PCIE_PDI_PHY_BASE 0x1F106800UL ++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) ++#define PCIE_PDI_SIZE 0x400 ++ ++#define PCIE1_CFG_PHY_BASE 0x19000000UL ++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) ++#define PCIE1_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE1_MEM_PHY_BASE 0x18000000UL ++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) ++#define PCIE1_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) ++ ++#define PCIE1_IO_PHY_BASE 0x19800000UL ++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) ++#define PCIE1_IO_SIZE (1 * 1024 * 1024) ++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) ++ ++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) ++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) ++#define PCIE1_MSI_PHY_BASE 0x1F400000UL ++ ++#define PCIE1_PDI_PHY_BASE 0x1F700400UL ++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) ++#define PCIE1_PDI_SIZE 0x400 ++ ++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) ++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) ++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) ++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) ++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) ++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) ++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) ++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) ++ ++/* PCIe Application Logic Register */ ++/* RC Core Control Register */ ++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) ++/* This should be enabled after initializing configuratin registers ++ * Also should check link status retraining bit ++ */ ++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ ++ ++/* RC Core Debug Register */ ++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) ++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 ++ ++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ ++#define PCIE_RC_DR_PM_DEV_STATE_S 9 ++ ++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ ++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ ++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ ++ ++/* Current Power State Definition */ ++enum { ++ PCIE_RC_DR_D0 = 0, ++ PCIE_RC_DR_D1, /* Not supported */ ++ PCIE_RC_DR_D2, /* Not supported */ ++ PCIE_RC_DR_D3, ++ PCIE_RC_DR_UN, ++}; ++ ++/* PHY Link Status Register */ ++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) ++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ ++ ++/* Electromechanical Control Register */ ++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) ++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ ++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ ++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ ++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ ++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ ++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ ++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ ++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ ++ ++/* Interrupt Status Register */ ++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) ++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ ++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ ++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ ++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ ++#define PCIE_IR_SR_AHB_LU_ERR_S 4 ++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ ++#define PCIE_IR_SR_INT_MSG_NUM_S 9 ++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 ++ ++/* Message Control Register */ ++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) ++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ ++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ ++ ++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) ++ ++/* Vendor-Defined Message Requester ID Register */ ++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) ++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF ++#define PCIE_VDM_RID_VDMRID_S 0 ++ ++/* ASPM Control Register */ ++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) ++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ ++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ ++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ ++ ++/* Vendor Message DW0 Register */ ++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) ++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ ++#define PCIE_VM_MSG_DW0_TYPE_S 0 ++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ ++#define PCIE_VM_MSG_DW0_FORMAT_S 5 ++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ ++#define PCIE_VM_MSG_DW0_TC_S 12 ++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ ++#define PCIE_VM_MSG_DW0_ATTR_S 18 ++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ ++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ ++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ ++#define PCIE_VM_MSG_DW0_LEN_S 22 ++ ++/* Format Definition */ ++enum { ++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ ++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ ++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ ++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ ++}; ++ ++/* Traffic Class Definition */ ++enum { ++ PCIE_VM_MSG_TC0 = 0, ++ PCIE_VM_MSG_TC1, ++ PCIE_VM_MSG_TC2, ++ PCIE_VM_MSG_TC3, ++ PCIE_VM_MSG_TC4, ++ PCIE_VM_MSG_TC5, ++ PCIE_VM_MSG_TC6, ++ PCIE_VM_MSG_TC7, ++}; ++ ++/* Attributes Definition */ ++enum { ++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ ++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ ++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ ++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ ++}; ++ ++/* Payload Size Definition */ ++#define PCIE_VM_MSG_LEN_MIN 0 ++#define PCIE_VM_MSG_LEN_MAX 1024 ++ ++/* Vendor Message DW1 Register */ ++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) ++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ ++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 ++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ ++#define PCIE_VM_MSG_DW1_CODE_S 16 ++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ ++#define PCIE_VM_MSG_DW1_TAG_S 24 ++ ++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) ++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) ++ ++/* Vendor Message Request Register */ ++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) ++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ ++ ++ ++/* AHB Slave Side Band Control Register */ ++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) ++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ ++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ ++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ ++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ ++#define PCIE_AHB_SSB_REQ_ATTR_S 3 ++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ ++#define PCIE_AHB_SSB_REQ_TC_S 5 ++ ++/* AHB Master SideBand Ctrl Register */ ++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) ++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ ++#define PCIE_AHB_MSB_RESP_ATTR_S 0 ++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ ++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ ++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ ++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 ++ ++/* AHB Control Register, fixed bus enumeration exception */ ++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) ++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 ++ ++/* Interrupt Enalbe Register */ ++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) ++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) ++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) ++ ++/* PCIe interrupt enable/control/capture register definition */ ++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ ++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ ++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ ++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ ++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ ++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ ++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ ++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ ++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ ++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ ++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ ++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ ++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ ++#define PCIE_IRN_INTA 0x00002000 /* INTA */ ++#define PCIE_IRN_INTB 0x00004000 /* INTB */ ++#define PCIE_IRN_INTC 0x00008000 /* INTC */ ++#define PCIE_IRN_INTD 0x00010000 /* INTD */ ++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ ++ ++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ ++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ ++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ ++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ ++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) ++/* PCIe RC Configuration Register */ ++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) ++ ++/* Bit definition from pci_reg.h */ ++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) ++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) ++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ ++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ ++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ ++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ ++ ++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ ++/* Bus Number Register bits */ ++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF ++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 ++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 ++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 ++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 ++#define PCIE_PNR_SUB_BUS_NUM_S 16 ++ ++/* IO Base/Limit Register bits */ ++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ ++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 ++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 ++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 ++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 ++ ++/* Non-prefetchable Memory Base/Limit Register bit */ ++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ ++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 ++#define PCIE_MBML_MEM_BASE_ADDR_S 4 ++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 ++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 ++ ++/* Prefetchable Memory Base/Limit Register bit */ ++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ ++#define PCIE_PMBL_64BIT_ADDR 0x00000001 ++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 ++#define PCIE_PMBL_UPPER_12BIT_S 4 ++#define PCIE_PMBL_E64MA 0x00010000 ++#define PCIE_PMBL_END_ADDR 0xFFF00000 ++#define PCIE_PMBL_END_ADDR_S 20 ++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ ++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ ++ ++/* I/O Base/Limit Upper 16 bits register */ ++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 ++ ++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) ++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) ++ ++/* Interrupt and Secondary Bridge Control Register */ ++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) ++ ++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF ++#define PCIE_INTRBCTRL_INT_LINE_S 0 ++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 ++#define PCIE_INTRBCTRL_INT_PIN_S 8 ++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ ++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ ++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ ++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ ++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ ++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ ++/* Others are read only */ ++enum { ++ PCIE_INTRBCTRL_INT_NON = 0, ++ PCIE_INTRBCTRL_INTA, ++ PCIE_INTRBCTRL_INTB, ++ PCIE_INTRBCTRL_INTC, ++ PCIE_INTRBCTRL_INTD, ++}; ++ ++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) ++ ++/* Power Management Control and Status Register */ ++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) ++ ++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ ++#define PCIE_PM_CSR_POWER_STATE_S 0 ++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ ++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ ++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ ++ ++/* MSI Capability Register for EP */ ++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) ++ ++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ ++#define PCIE_MCAPR_MSI_CAP_ID_S 0 ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 ++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 ++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ ++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 ++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ ++ ++/* MSI Message Address Register */ ++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) ++ ++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ ++ ++/* MSI Message Upper Address Register */ ++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) ++ ++/* MSI Message Data Register */ ++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) ++ ++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ ++#define PCIE_MD_DATA_S 0 ++ ++/* PCI Express Capability Register */ ++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) ++ ++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ ++#define PCIE_XCAP_ID_S 0 ++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_XCAP_NEXT_CAP_S 8 ++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ ++#define PCIE_XCAP_VER_S 16 ++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ ++#define PCIE_XCAP_DEV_PORT_TYPE_S 20 ++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ ++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ ++#define PCIE_XCAP_MSG_INT_NUM_S 25 ++ ++/* Device Capability Register */ ++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) ++ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 ++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ ++#define PCIE_DCAP_PHANTOM_FUNC_S 3 ++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ ++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ ++#define PCIE_DCAP_EP_L0S_LATENCY_S 6 ++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ ++#define PCIE_DCAP_EP_L1_LATENCY_S 9 ++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ ++ ++/* Maximum payload size supported */ ++enum { ++ PCIE_MAX_PAYLOAD_128 = 0, ++ PCIE_MAX_PAYLOAD_256, ++ PCIE_MAX_PAYLOAD_512, ++ PCIE_MAX_PAYLOAD_1024, ++ PCIE_MAX_PAYLOAD_2048, ++ PCIE_MAX_PAYLOAD_4096, ++}; ++ ++/* Device Control and Status Register */ ++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) ++ ++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ ++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ ++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ ++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 ++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ ++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ ++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ ++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 ++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ ++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ ++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ ++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ ++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ ++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ ++ ++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ ++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ ++ PCIE_DCTLSYS_UR_REQ_EN) ++ ++/* Link Capability Register */ ++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) ++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ ++#define PCIE_LCAP_MAX_LINK_SPEED_S 0 ++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ ++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 ++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ ++#define PCIE_LCAP_ASPM_LEVEL_S 10 ++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ ++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 ++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ ++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 ++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ ++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ ++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ ++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ ++#define PCIE_LCAP_PORT_NUM_S 24 ++ ++/* Maximum Length width definition */ ++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 ++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ ++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 ++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 ++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 ++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C ++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 ++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 ++ ++/* Active State Link PM definition */ ++enum { ++ PCIE_ASPM_RES0 = 0, ++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ ++ PCIE_ASPM_RES1, ++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ ++}; ++ ++/* L0s Exit Latency definition */ ++enum { ++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ ++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ ++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ ++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ ++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ ++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ ++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ ++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ ++}; ++ ++/* L1 Exit Latency definition */ ++enum { ++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ ++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ ++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ ++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ ++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ ++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ ++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ ++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ ++}; ++ ++/* Link Control and Status Register */ ++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) ++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ ++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 ++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ ++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ ++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ ++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ ++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ ++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ ++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ ++#define PCIE_LCTLSTS_LINK_SPEED_S 16 ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 ++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ ++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ ++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ ++ ++/* Slot Capabilities Register */ ++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) ++ ++/* Slot Capabilities */ ++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) ++ ++/* Root Control and Capability Register */ ++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) ++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ ++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ ++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ ++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ ++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ ++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) ++/* Root Status Register */ ++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) ++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ ++#define PCIE_RSTS_PME_REQ_ID_S 0 ++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ ++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ ++ ++/* PCI Express Enhanced Capability Header */ ++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) ++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ ++#define PCIE_ENHANCED_CAP_ID_S 0 ++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ ++#define PCIE_ENHANCED_CAP_VER_S 16 ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 ++ ++/* Uncorrectable Error Status Register */ ++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) ++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ ++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ ++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ ++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ ++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ ++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ ++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ ++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ ++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ ++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ ++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ ++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ ++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ ++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ ++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) ++ ++/* Uncorrectable Error Mask Register, Mask means no report */ ++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) ++ ++/* Uncorrectable Error Severity Register */ ++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) ++ ++/* Correctable Error Status Register */ ++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) ++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ ++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ ++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ ++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ ++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ ++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ ++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ ++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) ++ ++/* Correctable Error Mask Register */ ++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) ++ ++/* Advanced Error Capabilities and Control Register */ ++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) ++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ ++#define PCIE_AECCR_FIRST_ERR_PTR_S 0 ++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ ++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ ++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ ++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ ++ ++/* Header Log Register 1 */ ++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) ++ ++/* Header Log Register 2 */ ++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) ++ ++/* Header Log Register 3 */ ++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) ++ ++/* Header Log Register 4 */ ++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) ++ ++/* Root Error Command Register */ ++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) ++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ ++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ ++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ ++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) ++ ++/* Root Error Status Register */ ++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) ++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ ++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ ++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ ++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ ++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ ++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_RESR_AER_INT_MSG_NUM_S 27 ++ ++/* Error Source Indentification Register */ ++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 ++ ++/* VC Enhanced Capability Header */ ++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) ++ ++/* Port VC Capability Register */ ++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) ++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ ++#define PCIE_PVC1_EXT_VC_CNT_S 0 ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 ++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ ++#define PCIE_PVC1_REF_CLK_S 8 ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 ++ ++/* Extended Virtual Channel Count Defintion */ ++#define PCIE_EXT_VC_CNT_MIN 0 ++#define PCIE_EXT_VC_CNT_MAX 7 ++ ++/* Port Arbitration Table Entry Size Definition */ ++enum { ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, ++}; ++ ++/* Port VC Capability Register 2 */ ++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) ++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ ++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 ++ ++/* Port VC Control and Status Register */ ++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) ++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ ++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ ++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 ++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ ++ ++/* VC0 Resource Capability Register */ ++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) ++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ ++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ ++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ ++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) ++ ++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 ++ ++/* VC0 Resource Control Register */ ++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) ++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ ++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ ++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ ++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ ++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ ++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ ++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ ++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ ++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ ++ ++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 ++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ ++#define PCIE_VC0_RC0_VC_ID_S 24 ++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ ++ ++/* VC0 Resource Status Register */ ++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) ++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ ++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ ++ ++/* Ack Latency Timer and Replay Timer Register */ ++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 ++ ++/* Other Message Register */ ++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) ++ ++/* Port Force Link Register */ ++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) ++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ ++#define PCIE_PFLR_LINK_NUM_S 0 ++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ ++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ ++#define PCIE_PFLR_LINK_STATE_S 16 ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 ++ ++/* Ack Frequency Register */ ++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) ++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ ++#define PCIE_AFR_AF_S 0 ++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ ++#define PCIE_AFR_FTS_NUM_S 8 ++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ ++#define PCIE_AFR_COM_FTS_NUM_S 16 ++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ ++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 ++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ ++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 ++#define PCIE_AFR_FTS_NUM_DEFAULT 32 ++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 ++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 ++ ++/* Port Link Control Register */ ++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) ++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ ++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ ++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ ++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ ++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ ++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ ++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ ++#define PCIE_PLCR_LINK_MODE_S 16 ++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ ++ ++/* Lane Skew Register */ ++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) ++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ ++#define PCIE_LSR_LANE_SKEW_NUM_S 0 ++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ ++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ ++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ ++ ++/* Symbol Number Register */ ++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) ++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ ++#define PCIE_SNR_TS_S 0 ++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ ++#define PCIE_SNR_SKP_S 8 ++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ ++#define PCIE_SNR_REPLAY_TIMER_S 14 ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 ++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ ++#define PCIE_SNR_FC_TIMER_S 28 ++ ++/* Symbol Timer Register and Filter Mask Register 1 */ ++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) ++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ ++#define PCIE_STRFMR_SKP_INTERVAL_S 0 ++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ ++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ ++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ ++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ ++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ ++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ ++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ ++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ ++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ ++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ ++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ ++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ ++ ++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ ++ ++/* Filter Masker Register 2 */ ++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) ++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ ++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ ++ ++/* Debug Register 0 */ ++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) ++ ++/* Debug Register 1 */ ++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) ++ ++/* Transmit Posted FC Credit Status Register */ ++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Non-Posted FC Credit Status */ ++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Complete FC Credit Status Register */ ++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 ++ ++/* Queue Status Register */ ++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) ++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ ++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ ++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ ++ ++/* VC Transmit Arbitration Register 1 */ ++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) ++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ ++ ++/* VC Transmit Arbitration Register 2 */ ++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) ++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ ++ ++/* VC0 Posted Receive Queue Control Register */ ++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 ++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ ++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ ++ ++/* VC0 Non-Posted Receive Queue Control */ ++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 ++ ++/* VC0 Completion Receive Queue Control */ ++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 ++ ++/* Applicable to the above three registers */ ++enum { ++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, ++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, ++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, ++}; ++ ++/* VC0 Posted Buffer Depth Register */ ++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Non-Posted Buffer Depth Register */ ++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Completion Buffer Depth Register */ ++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 ++ ++/* PHY Status Register, all zeros in VR9 */ ++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) ++ ++/* PHY Control Register, all zeros in VR9 */ ++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) ++ ++/* ++ * PCIe PDI PHY register definition, suppose all the following ++ * stuff is confidential. ++ * XXX, detailed bit definition ++ */ ++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) ++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) ++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) ++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) ++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) ++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) ++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) ++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) ++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) ++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) ++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) ++ ++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) ++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) ++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) ++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) ++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) ++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) ++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) ++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) ++ ++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) ++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) ++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) ++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) ++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) ++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) ++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) ++ ++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) ++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) ++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) ++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) ++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) ++ ++/* Interrupt related stuff */ ++#define PCIE_LEGACY_DISABLE 0 ++#define PCIE_LEGACY_INTA 1 ++#define PCIE_LEGACY_INTB 2 ++#define PCIE_LEGACY_INTC 3 ++#define PCIE_LEGACY_INTD 4 ++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD ++ ++#endif /* IFXMIPS_PCIE_REG_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_vr9.h +@@ -0,0 +1,269 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++/*! ++ \file ifxmips_pcie_vr9.h ++ \ingroup IFX_PCIE ++ \brief PCIe RC driver vr9 specific file ++*/ ++ ++#ifndef IFXMIPS_PCIE_VR9_H ++#define IFXMIPS_PCIE_VR9_H ++ ++#include ++#include ++ ++#include ++#include ++ ++#define IFX_PCIE_GPIO_RESET 494 ++ ++#define IFX_REG_R32 ltq_r32 ++#define IFX_REG_W32 ltq_w32 ++#define CONFIG_IFX_PCIE_HW_SWAP ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ ++#define IFX_PMU1_MODULE_PCIE_PHY (0) ++#define IFX_PMU1_MODULE_PCIE_CTRL (1) ++#define IFX_PMU1_MODULE_PDI (4) ++#define IFX_PMU1_MODULE_MSI (5) ++ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++ ++#define IFX_GPIO (KSEG1 | 0x1E100B00) ++#define ALT0 ((volatile u32*)(IFX_GPIO + 0x007c)) ++#define ALT1 ((volatile u32*)(IFX_GPIO + 0x0080)) ++#define OD ((volatile u32*)(IFX_GPIO + 0x0084)) ++#define DIR ((volatile u32*)(IFX_GPIO + 0x0078)) ++#define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) ++ ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ ++ gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); ++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); ++ gpio_set_value(IFX_PCIE_GPIO_RESET, 1); ++ ++/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ /* Enable AHB bus master/slave */ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "ahb"); ++ clk_enable(clk); ++ ++ //AHBM_PMU_SETUP(IFX_PMU_ENABLE); ++ //AHBS_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg |= IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#else ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg &= ~IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "phy"); ++ clk_enable(clk); ++ ++ //PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_phy_pmu_disable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "phy"); ++ clk_disable(clk); ++ ++// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++} ++ ++static inline void pcie_pdi_big_endian(int pcie_port) ++{ ++ u32 reg; ++ ++ /* SRAM2PDI endianness control. */ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_AHB_BE_PCIE_PDI; ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ /* Enable PDI to access PCIe PHY register */ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "pdi"); ++ clk_enable(clk); ++ //PDI_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_core_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ ++ /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ ++ reg |= 0x00400000; ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_core_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ /* Reset PCIe PHY & Core, bit 22 */ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg &= ~0x00400000; ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg |= 0x00001000; /* Bit 12 */ ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg &= ~0x00001000; /* Bit 12 */ ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ gpio_set_value(IFX_PCIE_GPIO_RESET, 0); ++// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); ++// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); ++ //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++} ++ ++static inline void pcie_core_pmu_setup(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "ctl"); ++ clk_enable(clk); ++ clk = clk_get_sys("1d900000.pcie", "bus"); ++ clk_enable(clk); ++ ++ /* PCIe Core controller enabled */ ++// PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ ++ /* Enable PCIe L0 Clock */ ++// PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_msi_init(int pcie_port) ++{ ++ struct clk *clk; ++ pcie_msi_pic_init(pcie_port); ++ clk = clk_get_sys("ltq_pcie", "msi"); ++ clk_enable(clk); ++// MSI_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline u32 ++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) ++{ ++ u32 tbus_number = bus_number; ++ ++#ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++#endif /* CONFIG_PCI_LANTIQ */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ #endif /* CONFIG_PCI_LANTIQ */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_VR9_H */ ++ +--- a/arch/mips/pci/pci-legacy.c ++++ b/arch/mips/pci/pci-legacy.c +@@ -313,3 +313,30 @@ char *__init pcibios_setup(char *str) + return pcibios_plat_setup(str); + return str; + } ++ ++int pcibios_host_nr(void) ++{ ++ int count = 0; ++ struct pci_controller *hose; ++ list_for_each_entry(hose, &controllers, list) { ++ count++; ++ } ++ return count; ++} ++EXPORT_SYMBOL(pcibios_host_nr); ++ ++int pcibios_1st_host_bus_nr(void) ++{ ++ int bus_nr = 0; ++ struct pci_controller *hose; ++ ++ hose = list_first_entry_or_null(&controllers, struct pci_controller, list); ++ ++ if (hose != NULL) { ++ if (hose->bus != NULL) { ++ bus_nr = hose->bus->number + 1; ++ } ++ } ++ return bus_nr; ++} ++EXPORT_SYMBOL(pcibios_1st_host_bus_nr); +--- /dev/null ++++ b/arch/mips/pci/pcie-lantiq.h +@@ -0,0 +1,1301 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_reg.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_REG_H ++#define IFXMIPS_PCIE_REG_H ++#include ++#include ++#include ++#include ++/*! ++ \file ifxmips_pcie_reg.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module register definition ++*/ ++/* PCIe Address Mapping Base */ ++#define PCIE_CFG_PHY_BASE 0x1D000000UL ++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) ++#define PCIE_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE_MEM_PHY_BASE 0x1C000000UL ++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) ++#define PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) ++ ++#define PCIE_IO_PHY_BASE 0x1D800000UL ++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) ++#define PCIE_IO_SIZE (1 * 1024 * 1024) ++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) ++ ++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) ++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) ++#define PCIE_MSI_PHY_BASE 0x1F600000UL ++ ++#define PCIE_PDI_PHY_BASE 0x1F106800UL ++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) ++#define PCIE_PDI_SIZE 0x400 ++ ++#define PCIE1_CFG_PHY_BASE 0x19000000UL ++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) ++#define PCIE1_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE1_MEM_PHY_BASE 0x18000000UL ++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) ++#define PCIE1_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) ++ ++#define PCIE1_IO_PHY_BASE 0x19800000UL ++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) ++#define PCIE1_IO_SIZE (1 * 1024 * 1024) ++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) ++ ++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) ++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) ++#define PCIE1_MSI_PHY_BASE 0x1F400000UL ++ ++#define PCIE1_PDI_PHY_BASE 0x1F700400UL ++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) ++#define PCIE1_PDI_SIZE 0x400 ++ ++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) ++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) ++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) ++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) ++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) ++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) ++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) ++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) ++ ++/* PCIe Application Logic Register */ ++/* RC Core Control Register */ ++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) ++/* This should be enabled after initializing configuratin registers ++ * Also should check link status retraining bit ++ */ ++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ ++ ++/* RC Core Debug Register */ ++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) ++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 ++ ++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ ++#define PCIE_RC_DR_PM_DEV_STATE_S 9 ++ ++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ ++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ ++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ ++ ++/* Current Power State Definition */ ++enum { ++ PCIE_RC_DR_D0 = 0, ++ PCIE_RC_DR_D1, /* Not supported */ ++ PCIE_RC_DR_D2, /* Not supported */ ++ PCIE_RC_DR_D3, ++ PCIE_RC_DR_UN, ++}; ++ ++/* PHY Link Status Register */ ++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) ++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ ++ ++/* Electromechanical Control Register */ ++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) ++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ ++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ ++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ ++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ ++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ ++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ ++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ ++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ ++ ++/* Interrupt Status Register */ ++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) ++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ ++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ ++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ ++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ ++#define PCIE_IR_SR_AHB_LU_ERR_S 4 ++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ ++#define PCIE_IR_SR_INT_MSG_NUM_S 9 ++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 ++ ++/* Message Control Register */ ++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) ++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ ++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ ++ ++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) ++ ++/* Vendor-Defined Message Requester ID Register */ ++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) ++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF ++#define PCIE_VDM_RID_VDMRID_S 0 ++ ++/* ASPM Control Register */ ++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) ++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ ++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ ++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ ++ ++/* Vendor Message DW0 Register */ ++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) ++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ ++#define PCIE_VM_MSG_DW0_TYPE_S 0 ++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ ++#define PCIE_VM_MSG_DW0_FORMAT_S 5 ++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ ++#define PCIE_VM_MSG_DW0_TC_S 12 ++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ ++#define PCIE_VM_MSG_DW0_ATTR_S 18 ++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ ++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ ++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ ++#define PCIE_VM_MSG_DW0_LEN_S 22 ++ ++/* Format Definition */ ++enum { ++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ ++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ ++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ ++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ ++}; ++ ++/* Traffic Class Definition */ ++enum { ++ PCIE_VM_MSG_TC0 = 0, ++ PCIE_VM_MSG_TC1, ++ PCIE_VM_MSG_TC2, ++ PCIE_VM_MSG_TC3, ++ PCIE_VM_MSG_TC4, ++ PCIE_VM_MSG_TC5, ++ PCIE_VM_MSG_TC6, ++ PCIE_VM_MSG_TC7, ++}; ++ ++/* Attributes Definition */ ++enum { ++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ ++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ ++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ ++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ ++}; ++ ++/* Payload Size Definition */ ++#define PCIE_VM_MSG_LEN_MIN 0 ++#define PCIE_VM_MSG_LEN_MAX 1024 ++ ++/* Vendor Message DW1 Register */ ++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) ++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ ++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 ++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ ++#define PCIE_VM_MSG_DW1_CODE_S 16 ++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ ++#define PCIE_VM_MSG_DW1_TAG_S 24 ++ ++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) ++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) ++ ++/* Vendor Message Request Register */ ++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) ++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ ++ ++ ++/* AHB Slave Side Band Control Register */ ++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) ++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ ++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ ++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ ++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ ++#define PCIE_AHB_SSB_REQ_ATTR_S 3 ++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ ++#define PCIE_AHB_SSB_REQ_TC_S 5 ++ ++/* AHB Master SideBand Ctrl Register */ ++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) ++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ ++#define PCIE_AHB_MSB_RESP_ATTR_S 0 ++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ ++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ ++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ ++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 ++ ++/* AHB Control Register, fixed bus enumeration exception */ ++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) ++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 ++ ++/* Interrupt Enalbe Register */ ++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) ++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) ++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) ++ ++/* PCIe interrupt enable/control/capture register definition */ ++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ ++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ ++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ ++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ ++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ ++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ ++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ ++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ ++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ ++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ ++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ ++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ ++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ ++#define PCIE_IRN_INTA 0x00002000 /* INTA */ ++#define PCIE_IRN_INTB 0x00004000 /* INTB */ ++#define PCIE_IRN_INTC 0x00008000 /* INTC */ ++#define PCIE_IRN_INTD 0x00010000 /* INTD */ ++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ ++ ++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ ++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ ++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ ++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ ++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) ++/* PCIe RC Configuration Register */ ++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) ++ ++/* Bit definition from pci_reg.h */ ++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) ++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) ++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ ++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ ++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ ++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ ++ ++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ ++/* Bus Number Register bits */ ++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF ++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 ++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 ++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 ++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 ++#define PCIE_PNR_SUB_BUS_NUM_S 16 ++ ++/* IO Base/Limit Register bits */ ++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ ++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 ++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 ++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 ++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 ++ ++/* Non-prefetchable Memory Base/Limit Register bit */ ++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ ++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 ++#define PCIE_MBML_MEM_BASE_ADDR_S 4 ++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 ++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 ++ ++/* Prefetchable Memory Base/Limit Register bit */ ++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ ++#define PCIE_PMBL_64BIT_ADDR 0x00000001 ++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 ++#define PCIE_PMBL_UPPER_12BIT_S 4 ++#define PCIE_PMBL_E64MA 0x00010000 ++#define PCIE_PMBL_END_ADDR 0xFFF00000 ++#define PCIE_PMBL_END_ADDR_S 20 ++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ ++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ ++ ++/* I/O Base/Limit Upper 16 bits register */ ++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 ++ ++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) ++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) ++ ++/* Interrupt and Secondary Bridge Control Register */ ++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) ++ ++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF ++#define PCIE_INTRBCTRL_INT_LINE_S 0 ++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 ++#define PCIE_INTRBCTRL_INT_PIN_S 8 ++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ ++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ ++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ ++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ ++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ ++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ ++/* Others are read only */ ++enum { ++ PCIE_INTRBCTRL_INT_NON = 0, ++ PCIE_INTRBCTRL_INTA, ++ PCIE_INTRBCTRL_INTB, ++ PCIE_INTRBCTRL_INTC, ++ PCIE_INTRBCTRL_INTD, ++}; ++ ++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) ++ ++/* Power Management Control and Status Register */ ++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) ++ ++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ ++#define PCIE_PM_CSR_POWER_STATE_S 0 ++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ ++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ ++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ ++ ++/* MSI Capability Register for EP */ ++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) ++ ++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ ++#define PCIE_MCAPR_MSI_CAP_ID_S 0 ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 ++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 ++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ ++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 ++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ ++ ++/* MSI Message Address Register */ ++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) ++ ++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ ++ ++/* MSI Message Upper Address Register */ ++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) ++ ++/* MSI Message Data Register */ ++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) ++ ++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ ++#define PCIE_MD_DATA_S 0 ++ ++/* PCI Express Capability Register */ ++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) ++ ++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ ++#define PCIE_XCAP_ID_S 0 ++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_XCAP_NEXT_CAP_S 8 ++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ ++#define PCIE_XCAP_VER_S 16 ++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ ++#define PCIE_XCAP_DEV_PORT_TYPE_S 20 ++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ ++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ ++#define PCIE_XCAP_MSG_INT_NUM_S 25 ++ ++/* Device Capability Register */ ++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) ++ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 ++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ ++#define PCIE_DCAP_PHANTOM_FUNC_S 3 ++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ ++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ ++#define PCIE_DCAP_EP_L0S_LATENCY_S 6 ++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ ++#define PCIE_DCAP_EP_L1_LATENCY_S 9 ++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ ++ ++/* Maximum payload size supported */ ++enum { ++ PCIE_MAX_PAYLOAD_128 = 0, ++ PCIE_MAX_PAYLOAD_256, ++ PCIE_MAX_PAYLOAD_512, ++ PCIE_MAX_PAYLOAD_1024, ++ PCIE_MAX_PAYLOAD_2048, ++ PCIE_MAX_PAYLOAD_4096, ++}; ++ ++/* Device Control and Status Register */ ++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) ++ ++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ ++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ ++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ ++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 ++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ ++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ ++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ ++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 ++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ ++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ ++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ ++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ ++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ ++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ ++ ++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ ++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ ++ PCIE_DCTLSYS_UR_REQ_EN) ++ ++/* Link Capability Register */ ++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) ++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ ++#define PCIE_LCAP_MAX_LINK_SPEED_S 0 ++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ ++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 ++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ ++#define PCIE_LCAP_ASPM_LEVEL_S 10 ++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ ++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 ++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ ++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 ++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ ++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ ++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ ++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ ++#define PCIE_LCAP_PORT_NUM_S 24 ++ ++/* Maximum Length width definition */ ++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 ++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ ++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 ++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 ++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 ++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C ++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 ++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 ++ ++/* Active State Link PM definition */ ++enum { ++ PCIE_ASPM_RES0 = 0, ++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ ++ PCIE_ASPM_RES1, ++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ ++}; ++ ++/* L0s Exit Latency definition */ ++enum { ++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ ++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ ++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ ++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ ++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ ++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ ++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ ++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ ++}; ++ ++/* L1 Exit Latency definition */ ++enum { ++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ ++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ ++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ ++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ ++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ ++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ ++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ ++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ ++}; ++ ++/* Link Control and Status Register */ ++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) ++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ ++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 ++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ ++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ ++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ ++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ ++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ ++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ ++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ ++#define PCIE_LCTLSTS_LINK_SPEED_S 16 ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 ++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ ++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ ++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ ++ ++/* Slot Capabilities Register */ ++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) ++ ++/* Slot Capabilities */ ++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) ++ ++/* Root Control and Capability Register */ ++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) ++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ ++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ ++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ ++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ ++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ ++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) ++/* Root Status Register */ ++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) ++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ ++#define PCIE_RSTS_PME_REQ_ID_S 0 ++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ ++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ ++ ++/* PCI Express Enhanced Capability Header */ ++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) ++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ ++#define PCIE_ENHANCED_CAP_ID_S 0 ++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ ++#define PCIE_ENHANCED_CAP_VER_S 16 ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 ++ ++/* Uncorrectable Error Status Register */ ++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) ++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ ++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ ++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ ++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ ++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ ++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ ++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ ++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ ++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ ++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ ++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ ++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ ++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ ++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ ++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) ++ ++/* Uncorrectable Error Mask Register, Mask means no report */ ++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) ++ ++/* Uncorrectable Error Severity Register */ ++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) ++ ++/* Correctable Error Status Register */ ++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) ++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ ++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ ++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ ++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ ++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ ++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ ++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ ++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) ++ ++/* Correctable Error Mask Register */ ++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) ++ ++/* Advanced Error Capabilities and Control Register */ ++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) ++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ ++#define PCIE_AECCR_FIRST_ERR_PTR_S 0 ++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ ++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ ++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ ++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ ++ ++/* Header Log Register 1 */ ++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) ++ ++/* Header Log Register 2 */ ++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) ++ ++/* Header Log Register 3 */ ++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) ++ ++/* Header Log Register 4 */ ++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) ++ ++/* Root Error Command Register */ ++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) ++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ ++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ ++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ ++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) ++ ++/* Root Error Status Register */ ++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) ++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ ++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ ++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ ++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ ++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ ++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_RESR_AER_INT_MSG_NUM_S 27 ++ ++/* Error Source Indentification Register */ ++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 ++ ++/* VC Enhanced Capability Header */ ++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) ++ ++/* Port VC Capability Register */ ++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) ++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ ++#define PCIE_PVC1_EXT_VC_CNT_S 0 ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 ++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ ++#define PCIE_PVC1_REF_CLK_S 8 ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 ++ ++/* Extended Virtual Channel Count Defintion */ ++#define PCIE_EXT_VC_CNT_MIN 0 ++#define PCIE_EXT_VC_CNT_MAX 7 ++ ++/* Port Arbitration Table Entry Size Definition */ ++enum { ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, ++}; ++ ++/* Port VC Capability Register 2 */ ++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) ++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ ++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 ++ ++/* Port VC Control and Status Register */ ++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) ++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ ++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ ++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 ++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ ++ ++/* VC0 Resource Capability Register */ ++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) ++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ ++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ ++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ ++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) ++ ++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 ++ ++/* VC0 Resource Control Register */ ++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) ++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ ++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ ++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ ++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ ++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ ++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ ++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ ++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ ++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ ++ ++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 ++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ ++#define PCIE_VC0_RC0_VC_ID_S 24 ++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ ++ ++/* VC0 Resource Status Register */ ++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) ++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ ++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ ++ ++/* Ack Latency Timer and Replay Timer Register */ ++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 ++ ++/* Other Message Register */ ++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) ++ ++/* Port Force Link Register */ ++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) ++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ ++#define PCIE_PFLR_LINK_NUM_S 0 ++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ ++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ ++#define PCIE_PFLR_LINK_STATE_S 16 ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 ++ ++/* Ack Frequency Register */ ++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) ++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ ++#define PCIE_AFR_AF_S 0 ++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ ++#define PCIE_AFR_FTS_NUM_S 8 ++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ ++#define PCIE_AFR_COM_FTS_NUM_S 16 ++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ ++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 ++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ ++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 ++#define PCIE_AFR_FTS_NUM_DEFAULT 32 ++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 ++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 ++ ++/* Port Link Control Register */ ++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) ++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ ++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ ++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ ++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ ++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ ++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ ++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ ++#define PCIE_PLCR_LINK_MODE_S 16 ++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ ++ ++/* Lane Skew Register */ ++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) ++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ ++#define PCIE_LSR_LANE_SKEW_NUM_S 0 ++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ ++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ ++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ ++ ++/* Symbol Number Register */ ++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) ++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ ++#define PCIE_SNR_TS_S 0 ++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ ++#define PCIE_SNR_SKP_S 8 ++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ ++#define PCIE_SNR_REPLAY_TIMER_S 14 ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 ++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ ++#define PCIE_SNR_FC_TIMER_S 28 ++ ++/* Symbol Timer Register and Filter Mask Register 1 */ ++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) ++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ ++#define PCIE_STRFMR_SKP_INTERVAL_S 0 ++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ ++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ ++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ ++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ ++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ ++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ ++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ ++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ ++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ ++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ ++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ ++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ ++ ++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ ++ ++/* Filter Masker Register 2 */ ++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) ++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ ++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ ++ ++/* Debug Register 0 */ ++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) ++ ++/* Debug Register 1 */ ++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) ++ ++/* Transmit Posted FC Credit Status Register */ ++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Non-Posted FC Credit Status */ ++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Complete FC Credit Status Register */ ++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 ++ ++/* Queue Status Register */ ++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) ++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ ++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ ++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ ++ ++/* VC Transmit Arbitration Register 1 */ ++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) ++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ ++ ++/* VC Transmit Arbitration Register 2 */ ++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) ++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ ++ ++/* VC0 Posted Receive Queue Control Register */ ++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 ++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ ++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ ++ ++/* VC0 Non-Posted Receive Queue Control */ ++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 ++ ++/* VC0 Completion Receive Queue Control */ ++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 ++ ++/* Applicable to the above three registers */ ++enum { ++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, ++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, ++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, ++}; ++ ++/* VC0 Posted Buffer Depth Register */ ++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Non-Posted Buffer Depth Register */ ++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Completion Buffer Depth Register */ ++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 ++ ++/* PHY Status Register, all zeros in VR9 */ ++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) ++ ++/* PHY Control Register, all zeros in VR9 */ ++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) ++ ++/* ++ * PCIe PDI PHY register definition, suppose all the following ++ * stuff is confidential. ++ * XXX, detailed bit definition ++ */ ++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) ++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) ++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) ++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) ++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) ++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) ++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) ++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) ++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) ++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) ++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) ++ ++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) ++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) ++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) ++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) ++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) ++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) ++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) ++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) ++ ++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) ++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) ++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) ++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) ++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) ++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) ++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) ++ ++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) ++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) ++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) ++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) ++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) ++ ++/* Interrupt related stuff */ ++#define PCIE_LEGACY_DISABLE 0 ++#define PCIE_LEGACY_INTA 1 ++#define PCIE_LEGACY_INTB 2 ++#define PCIE_LEGACY_INTC 3 ++#define PCIE_LEGACY_INTD 4 ++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD ++ ++#define PCIE_IRQ_LOCK(lock) do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(&(lock), flags); ++#define PCIE_IRQ_UNLOCK(lock) \ ++ spin_unlock_irqrestore(&(lock), flags); \ ++} while (0) ++ ++#define PCIE_MSG_MSI 0x00000001 ++#define PCIE_MSG_ISR 0x00000002 ++#define PCIE_MSG_FIXUP 0x00000004 ++#define PCIE_MSG_READ_CFG 0x00000008 ++#define PCIE_MSG_WRITE_CFG 0x00000010 ++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) ++#define PCIE_MSG_REG 0x00000020 ++#define PCIE_MSG_INIT 0x00000040 ++#define PCIE_MSG_ERR 0x00000080 ++#define PCIE_MSG_PHY 0x00000100 ++#define PCIE_MSG_ANY 0x000001ff ++ ++#define IFX_PCIE_PORT0 0 ++#define IFX_PCIE_PORT1 1 ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++#define IFX_PCIE_CORE_NR 2 ++#else ++#define IFX_PCIE_CORE_NR 1 ++#endif ++ ++//#define IFX_PCIE_ERROR_INT ++ ++//#define IFX_PCIE_DBG ++ ++#if defined(IFX_PCIE_DBG) ++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ ++ if (g_pcie_debug_flag & (_m)) { \ ++ ifx_pcie_debug((_fmt), ##args); \ ++ } \ ++} while (0) ++ ++#define INLINE ++#else ++#define IFX_PCIE_PRINT(_m, _fmt, args...) \ ++ do {} while(0) ++#define INLINE inline ++#endif ++ ++struct ifx_pci_controller { ++ struct pci_controller pcic; ++ ++ /* RC specific, per host bus information */ ++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ ++}; ++ ++typedef struct ifx_pcie_ir_irq { ++ const unsigned int irq; ++ const char name[16]; ++}ifx_pcie_ir_irq_t; ++ ++typedef struct ifx_pcie_legacy_irq{ ++ const u32 irq_bit; ++ const int irq; ++}ifx_pcie_legacy_irq_t; ++ ++typedef struct ifx_pcie_irq { ++ ifx_pcie_ir_irq_t ir_irq; ++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; ++}ifx_pcie_irq_t; ++ ++extern u32 g_pcie_debug_flag; ++extern void ifx_pcie_debug(const char *fmt, ...); ++extern void pcie_phy_clock_mode_setup(int pcie_port); ++extern void pcie_msi_pic_init(int pcie_port); ++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); ++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); ++ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define IFX_PCIE_GPIO_RESET 38 ++#define IFX_REG_R32 ltq_r32 ++#define IFX_REG_W32 ltq_w32 ++#define CONFIG_IFX_PCIE_HW_SWAP ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ ++#define IFX_PMU1_MODULE_PCIE_PHY (0) ++#define IFX_PMU1_MODULE_PCIE_CTRL (1) ++#define IFX_PMU1_MODULE_PDI (4) ++#define IFX_PMU1_MODULE_MSI (5) ++ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "ahb"); ++ clk_enable(clk); ++ //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg |= IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#else ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg &= ~IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "phy"); ++ clk_enable(clk); ++ //ltq_pmu1_enable(1<PCIe and PDI endianness */ ++ reg |= IFX_RCU_AHB_BE_PCIE_PDI; ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "pdi"); ++ clk_enable(clk); ++ //ltq_pmu1_enable(1< 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++#endif /* CONFIG_PCI_LANTIQ */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ #endif /* CONFIG_PCI_LANTIQ */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_VR9_H */ ++ +--- a/drivers/pci/pcie/Kconfig ++++ b/drivers/pci/pcie/Kconfig +@@ -51,6 +51,7 @@ config PCIEAER_INJECT + config PCIE_ECRC + bool "PCI Express ECRC settings control" + depends on PCIEAER ++ default n + help + Used to override firmware/bios settings for PCI Express ECRC + (transaction layer end-to-end CRC checking). +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -1420,6 +1420,8 @@ void pci_walk_bus(struct pci_bus *top, i + void *userdata); + int pci_cfg_space_size(struct pci_dev *dev); + unsigned char pci_bus_max_busnr(struct pci_bus *bus); ++int pcibios_host_nr(void); ++int pcibios_1st_host_bus_nr(void); + void pci_setup_bridge(struct pci_bus *bus); + resource_size_t pcibios_window_alignment(struct pci_bus *bus, + unsigned long type); +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -1079,6 +1079,12 @@ + #define PCI_DEVICE_ID_SGI_IOC3 0x0003 + #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 + ++#define PCI_VENDOR_ID_INFINEON 0x15D1 ++#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F ++#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 ++#define PCI_VENDOR_ID_LANTIQ 0x1BEF ++#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 ++ + #define PCI_VENDOR_ID_WINBOND 0x10ad + #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 + #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 diff --git a/target/linux/lantiq/patches-5.15/0004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-5.15/0004-MIPS-lantiq-add-atm-hack.patch new file mode 100644 index 0000000000..e215df60ee --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0004-MIPS-lantiq-add-atm-hack.patch @@ -0,0 +1,482 @@ +From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:27:25 +0200 +Subject: [PATCH 04/36] MIPS: lantiq: add atm hack + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++ + arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++ + arch/mips/lantiq/irq.c | 2 + + arch/mips/mm/cache.c | 4 + + include/uapi/linux/atm.h | 6 + + net/atm/common.c | 6 + + net/atm/proc.c | 2 +- + 7 files changed, 416 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h +@@ -0,0 +1,196 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_atm.h ++** PROJECT : UEIP ++** MODULES : ATM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global ATM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_ATM_H ++#define IFX_ATM_H ++ ++ ++ ++/*! ++ \defgroup IFX_ATM UEIP Project - ATM driver module ++ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_IOCTL IOCTL Commands ++ \ingroup IFX_ATM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_STRUCT Structures ++ \ingroup IFX_ATM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_atm.h ++ \ingroup IFX_ATM ++ \brief ATM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ATM MIB ++ */ ++ ++/*! ++ \struct atm_cell_ifEntry_t ++ \brief Structure used for Cell Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifInErrors; /*!< counter of error ingress cells */ ++ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ ++ __u32 ifOutErrors; /*!< counter of error egress cells */ ++} atm_cell_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_ifEntry_t ++ \brief Structure used for AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifInUcastPkts; /*!< counter of ingress packets */ ++ __u32 ifOutUcastPkts; /*!< counter of egress packets */ ++ __u32 ifInErrors; /*!< counter of error ingress packets */ ++ __u32 ifInDiscards; /*!< counter of dropped ingress packets */ ++ __u32 ifOutErros; /*!< counter of error egress packets */ ++ __u32 ifOutDiscards; /*!< counter of dropped egress packets */ ++} atm_aal5_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_vcc_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ This structure is a part of structure "atm_aal5_vcc_x_t". ++ */ ++typedef struct { ++ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ ++ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet ++ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ ++} atm_aal5_vcc_t; ++ ++/*! ++ \struct atm_aal5_vcc_x_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". ++ */ ++typedef struct { ++ int vpi; /*!< VPI of the VCC to get MIB counters */ ++ int vci; /*!< VCI of the VCC to get MIB counters */ ++ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ ++} atm_aal5_vcc_x_t; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief ATM IOCTL Magic Number ++ */ ++#define PPE_ATM_IOC_MAGIC 'o' ++/*! ++ \brief ATM IOCTL Command - Get Cell Level MIB Counters ++ ++ This command is obsolete. User can get cell level MIB from DSL API. ++ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters ++ ++ Get AAL5 packet counters. ++ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get Per PVC MIB Counters ++ ++ Get AAL5 packet counters for each PVC. ++ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. ++ */ ++#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) ++/*! ++ \brief Total Number of ATM IOCTL Commands ++ */ ++#define PPE_ATM_IOC_MAXNR 3 ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_ATM_H ++ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h +@@ -0,0 +1,203 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_ptm.h ++** PROJECT : UEIP ++** MODULES : PTM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global PTM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_PTM_H ++#define IFX_PTM_H ++ ++ ++ ++/*! ++ \defgroup IFX_PTM UEIP Project - PTM driver module ++ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_IOCTL IOCTL Commands ++ \ingroup IFX_PTM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_STRUCT Structures ++ \ingroup IFX_PTM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_ptm.h ++ \ingroup IFX_PTM ++ \brief PTM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_PTM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief PTM IOCTL Command - Get codeword MIB counters. ++ ++ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. ++ */ ++#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 ++/*! ++ \brief PTM IOCTL Command - Get packet MIB counters. ++ ++ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. ++ */ ++#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 ++/*! ++ \brief PTM IOCTL Command - Get firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 ++/*! ++ \brief PTM IOCTL Command - Set firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 ++/*! ++ \brief PTM IOCTL Command - Program priority value to TX queue mapping. ++ ++ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. ++ */ ++#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 ++ ++/*@}*/ ++ ++ ++/*! ++ \addtogroup IFX_PTM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Data Type ++ */ ++ ++/*! ++ \typedef PTM_CW_IF_ENTRY_T ++ \brief Wrapping of structure "ptm_cw_ifEntry_t". ++ */ ++/*! ++ \struct ptm_cw_ifEntry_t ++ \brief Structure used for CodeWord level MIB counters. ++ */ ++typedef struct ptm_cw_ifEntry_t { ++ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ ++ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ ++ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ ++ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ ++ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ ++} PTM_CW_IF_ENTRY_T; ++ ++/*! ++ \typedef PTM_FRAME_MIB_T ++ \brief Wrapping of structure "ptm_frame_mib_t". ++ */ ++/*! ++ \struct ptm_frame_mib_t ++ \brief Structure used for packet level MIB counters. ++ */ ++typedef struct ptm_frame_mib_t { ++ uint32_t RxCorrect; /*!< output, number of ingress packet */ ++ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ ++ uint32_t RxDropped; /*!< output, number of dropped ingress packet */ ++ uint32_t TxSend; /*!< output, number of egress packet */ ++} PTM_FRAME_MIB_T; ++ ++/*! ++ \typedef IFX_PTM_CFG_T ++ \brief Wrapping of structure "ptm_cfg_t". ++ */ ++/*! ++ \struct ptm_cfg_t ++ \brief Structure used for ETH/TC CRC configuration. ++ */ ++typedef struct ptm_cfg_t { ++ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ ++ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ ++ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ ++ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ ++ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ ++ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ ++ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ ++} IFX_PTM_CFG_T; ++ ++/*! ++ \typedef IFX_PTM_PRIO_Q_MAP_T ++ \brief Wrapping of structure "ppe_prio_q_map". ++ */ ++/*! ++ \struct ppe_prio_q_map ++ \brief Structure used for Priority Value to TX Queue mapping. ++ */ ++typedef struct ppe_prio_q_map { ++ int pkt_prio; ++ int qid; ++ int vpi; // ignored in eth interface ++ int vci; // ignored in eth interface ++} IFX_PTM_PRIO_Q_MAP_T; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_PTM_H ++ +--- a/arch/mips/lantiq/irq.c ++++ b/arch/mips/lantiq/irq.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -91,6 +92,7 @@ void ltq_disable_irq(struct irq_data *d) + } + raw_spin_unlock_irqrestore(<q_icu_lock, flags); + } ++EXPORT_SYMBOL(ltq_mask_and_ack_irq); + + void ltq_mask_and_ack_irq(struct irq_data *d) + { +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -61,6 +61,10 @@ void (*_dma_cache_wback_inv)(unsigned lo + void (*_dma_cache_wback)(unsigned long start, unsigned long size); + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + ++EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_wback); ++EXPORT_SYMBOL(_dma_cache_inv); ++ + #endif /* CONFIG_DMA_NONCOHERENT */ + + /* +--- a/include/uapi/linux/atm.h ++++ b/include/uapi/linux/atm.h +@@ -131,8 +131,14 @@ + #define ATM_ABR 4 + #define ATM_ANYCLASS 5 /* compatible with everything */ + ++#define ATM_VBR_NRT ATM_VBR ++#define ATM_VBR_RT 6 ++#define ATM_UBR_PLUS 7 ++#define ATM_GFR 8 ++ + #define ATM_MAX_PCR -1 /* maximum available PCR */ + ++ + struct atm_trafprm { + unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ + int max_pcr; /* maximum PCR in cells per second */ +--- a/net/atm/proc.c ++++ b/net/atm/proc.c +@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil + static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) + { + static const char *const class_name[] = { +- "off", "UBR", "CBR", "VBR", "ABR"}; ++ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; + static const char *const aal_name[] = { + "---", "1", "2", "3/4", /* 0- 3 */ + "???", "5", "???", "???", /* 4- 7 */ diff --git a/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch new file mode 100644 index 0000000000..1d869afd9a --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch @@ -0,0 +1,1035 @@ +From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:30:56 +0200 +Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ + arch/mips/lantiq/xway/Makefile | 2 +- + arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++ + 3 files changed, 1001 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h + create mode 100644 arch/mips/lantiq/xway/timer.c + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h +@@ -0,0 +1,155 @@ ++#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++ ++ ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/* ++ * Available Timer/Counter Index ++ */ ++#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) ++#define TIMER_ANY 0x00 ++#define TIMER1A TIMER(1, 0) ++#define TIMER1B TIMER(1, 1) ++#define TIMER2A TIMER(2, 0) ++#define TIMER2B TIMER(2, 1) ++#define TIMER3A TIMER(3, 0) ++#define TIMER3B TIMER(3, 1) ++ ++/* ++ * Flag of Timer/Counter ++ * These flags specify the way in which timer is configured. ++ */ ++/* Bit size of timer/counter. */ ++#define TIMER_FLAG_16BIT 0x0000 ++#define TIMER_FLAG_32BIT 0x0001 ++/* Switch between timer and counter. */ ++#define TIMER_FLAG_TIMER 0x0000 ++#define TIMER_FLAG_COUNTER 0x0002 ++/* Stop or continue when overflowing/underflowing. */ ++#define TIMER_FLAG_ONCE 0x0000 ++#define TIMER_FLAG_CYCLIC 0x0004 ++/* Count up or counter down. */ ++#define TIMER_FLAG_UP 0x0000 ++#define TIMER_FLAG_DOWN 0x0008 ++/* Count on specific level or edge. */ ++#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 ++#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 ++#define TIMER_FLAG_RISE_EDGE 0x0010 ++#define TIMER_FLAG_FALL_EDGE 0x0020 ++#define TIMER_FLAG_ANY_EDGE 0x0030 ++/* Signal is syncronous to module clock or not. */ ++#define TIMER_FLAG_UNSYNC 0x0000 ++#define TIMER_FLAG_SYNC 0x0080 ++/* Different interrupt handle type. */ ++#define TIMER_FLAG_NO_HANDLE 0x0000 ++#if defined(__KERNEL__) ++ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 ++#endif // defined(__KERNEL__) ++#define TIMER_FLAG_SIGNAL 0x0300 ++/* Internal clock source or external clock source */ ++#define TIMER_FLAG_INT_SRC 0x0000 ++#define TIMER_FLAG_EXT_SRC 0x1000 ++ ++ ++/* ++ * ioctl Command ++ */ ++#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ ++#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ ++#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ ++#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ ++#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ ++#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ ++#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ ++#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ ++ ++/* ++ * Data Type Used to Call ioctl ++ */ ++struct gptu_ioctl_param { ++ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field is ID of expected * ++ * timer/counter. If it's zero, a timer/counter would * ++ * be dynamically allocated and ID would be stored in * ++ * this field. * ++ * In command GPTU_GET_COUNT_VALUE, this field is * ++ * ignored. * ++ * In other command, this field is ID of timer/counter * ++ * allocated. */ ++ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field contains flags to * ++ * specify how to configure timer/counter. * ++ * In command GPTU_START_TIMER, zero indicate start * ++ * and non-zero indicate resume timer/counter. * ++ * In other command, this field is ignored. */ ++ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * ++ * init/reload value. * ++ * In command GPTU_SET_TIMER, this field contains * ++ * frequency (0.001Hz) of timer. * ++ * In command GPTU_GET_COUNT_VALUE, current count * ++ * value would be stored in this field. * ++ * In command GPTU_CALCULATE_DIVIDER, this field * ++ * contains frequency wanted, and after calculation, * ++ * divider would be stored in this field to overwrite * ++ * the frequency. * ++ * In other command, this field is ignored. */ ++ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains process * ++ * ID to which signal would be sent. * ++ * In other command, this field is ignored. */ ++ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains signal * ++ * number which would be sent. * ++ * In other command, this field is ignored. */ ++}; ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++typedef void (*timer_callback)(unsigned long arg); ++ ++extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); ++extern int lq_free_timer(unsigned int); ++extern int lq_start_timer(unsigned int, int); ++extern int lq_stop_timer(unsigned int); ++extern int lq_reset_counter_flags(u32 timer, u32 flags); ++extern int lq_get_count_value(unsigned int, unsigned long *); ++extern u32 lq_cal_divider(unsigned long); ++extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); ++extern int lq_set_counter(unsigned int timer, unsigned int flag, ++ u32 reload, unsigned long arg1, unsigned long arg2); ++ ++#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,4 +1,10 @@ + # SPDX-License-Identifier: GPL-2.0-only +-obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o ++obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o ++ ++ifdef CONFIG_SOC_AMAZON_SE ++obj-y += gptu.o ++else ++obj-y += timer.o ++endif + + obj-y += vmmc.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/timer.c +@@ -0,0 +1,846 @@ ++#ifndef CONFIG_SOC_AMAZON_SE ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "../clk.h" ++ ++#include ++#include ++#include ++ ++#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 ++ ++#ifdef TIMER1A ++#define FIRST_TIMER TIMER1A ++#else ++#define FIRST_TIMER 2 ++#endif ++ ++/* ++ * GPTC divider is set or not. ++ */ ++#define GPTU_CLC_RMC_IS_SET 0 ++ ++/* ++ * Timer Interrupt (IRQ) ++ */ ++/* Must be adjusted when ICU driver is available */ ++#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) ++ ++/* ++ * Bits Operation ++ */ ++#define GET_BITS(x, msb, lsb) \ ++ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) ++#define SET_BITS(x, msb, lsb, value) \ ++ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ ++ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) ++ ++/* ++ * GPTU Register Mapping ++ */ ++#define LQ_GPTU (KSEG1 + 0x1E100A00) ++#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) ++#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) ++#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) ++#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) ++#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) ++ ++/* ++ * Clock Control Register ++ */ ++#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) ++#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) ++#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) ++#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) ++#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) ++#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) ++#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) ++ ++#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) ++#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) ++#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) ++ ++/* ++ * ID Register ++ */ ++#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) ++#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) ++#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) ++ ++/* ++ * Control Register of Timer/Counter nX ++ * n is the index of block (1 based index) ++ * X is either A or B ++ */ ++#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) ++#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) ++#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) ++#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) ++#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) ++#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ ++#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) ++#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) ++#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) ++#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) ++ ++#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) ++#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) ++#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) ++#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) ++#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) ++ ++#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) ++#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) ++ ++#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++ ++#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) ++#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) ++#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) ++#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) ++#define TIMER_FLAG_NONE_EDGE 0x0000 ++#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) ++#define TIMER_FLAG_REAL 0x0000 ++#define TIMER_FLAG_INVERT 0x0040 ++#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) ++#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) ++#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) ++#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 ++#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) ++#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) ++ ++struct timer_dev_timer { ++ unsigned int f_irq_on; ++ unsigned int irq; ++ unsigned int flag; ++ unsigned long arg1; ++ unsigned long arg2; ++}; ++ ++struct timer_dev { ++ struct mutex gptu_mutex; ++ unsigned int number_of_timers; ++ unsigned int occupation; ++ unsigned int f_gptu_on; ++ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; ++}; ++ ++ ++unsigned int ltq_get_fpi_bus_clock(int fpi) { ++ struct clk *clk = clk_get_fpi(); ++ return clk_get_rate(clk); ++} ++ ++ ++static long gptu_ioctl(struct file *, unsigned int, unsigned long); ++static int gptu_open(struct inode *, struct file *); ++static int gptu_release(struct inode *, struct file *); ++ ++static struct file_operations gptu_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = gptu_ioctl, ++ .open = gptu_open, ++ .release = gptu_release ++}; ++ ++static struct miscdevice gptu_miscdev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "gptu", ++ .fops = &gptu_fops, ++}; ++ ++static struct timer_dev timer_dev; ++ ++static irqreturn_t timer_irq_handler(int irq, void *p) ++{ ++ unsigned int timer; ++ unsigned int flag; ++ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; ++ ++ timer = irq - TIMER_INTERRUPT; ++ if (timer < timer_dev.number_of_timers ++ && dev_timer == &timer_dev.timer[timer]) { ++ /* Clear interrupt. */ ++ ltq_w32(1 << timer, LQ_GPTU_IRNCR); ++ ++ /* Call user hanler or signal. */ ++ flag = dev_timer->flag; ++ if (!(timer & 0x01) ++ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ /* 16-bit timer or timer A of 32-bit timer */ ++ switch (TIMER_FLAG_MASK_HANDLE(flag)) { ++ case TIMER_FLAG_CALLBACK_IN_IRQ: ++ case TIMER_FLAG_CALLBACK_IN_HB: ++ if (dev_timer->arg1) ++ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); ++ break; ++ case TIMER_FLAG_SIGNAL: ++ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); ++ break; ++ } ++ } ++ } ++ return IRQ_HANDLED; ++} ++ ++static inline void lq_enable_gptu(void) ++{ ++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); ++ clk_enable(clk); ++ ++ //ltq_pmu_enable(PMU_GPT); ++ ++ /* Set divider as 1, disable write protection for SPEN, enable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x01) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(1) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(0); ++} ++ ++static inline void lq_disable_gptu(void) ++{ ++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); ++ ltq_w32(0x00, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ /* Set divider as 0, enable write protection for SPEN, disable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x00) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(0) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(1); ++ ++ clk_enable(clk); ++} ++ ++int lq_request_timer(unsigned int timer, unsigned int flag, ++ unsigned long value, unsigned long arg1, unsigned long arg2) ++{ ++ int ret = 0; ++ unsigned int con_reg, irnen_reg; ++ int n, X; ++ ++ if (timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", ++ timer, flag, value); ++ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) ++ value &= 0xFFFF; ++ else ++ timer &= ~0x01; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ /* ++ * Allocate timer. ++ */ ++ if (timer < FIRST_TIMER) { ++ unsigned int mask; ++ unsigned int shift; ++ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ ++ unsigned int offset = TIMER2A; ++ ++ /* ++ * Pick up a free timer. ++ */ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ mask = 1 << offset; ++ shift = 1; ++ } else { ++ mask = 3 << offset; ++ shift = 2; ++ } ++ for (timer = offset; ++ timer < offset + timer_dev.number_of_timers; ++ timer += shift, mask <<= shift) ++ if (!(timer_dev.occupation & mask)) { ++ timer_dev.occupation |= mask; ++ break; ++ } ++ if (timer >= offset + timer_dev.number_of_timers) { ++ printk("failed![%d]\n", __LINE__); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } else ++ ret = timer; ++ } else { ++ register unsigned int mask; ++ ++ /* ++ * Check if the requested timer is free. ++ */ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if ((timer_dev.occupation & mask)) { ++ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", ++ __LINE__, mask, timer_dev.occupation); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EBUSY; ++ } else { ++ timer_dev.occupation |= mask; ++ ret = 0; ++ } ++ } ++ ++ /* ++ * Prepare control register value. ++ */ ++ switch (TIMER_FLAG_MASK_EDGE(flag)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : ++ GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : ++ GPTU_CON_SRC_EG_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_SYNC(flag) == ++ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : ++ GPTU_CON_SYNC_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_INVERT(flag) == ++ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : ++ GPTU_CON_EXT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_STOP(flag) == ++ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_TYPE(flag) == ++ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : ++ GPTU_CON_CNT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_DIR(flag) == ++ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ /* ++ * Fill up running data. ++ */ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flag; ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; ++ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; ++ ++ /* ++ * Enable GPTU module. ++ */ ++ if (!timer_dev.f_gptu_on) { ++ lq_enable_gptu(); ++ timer_dev.f_gptu_on = 1; ++ } ++ ++ /* ++ * Enable IRQ. ++ */ ++ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = ++ (unsigned long) find_task_by_vpid((int) arg1); ++ ++ irnen_reg = 1 << (timer - FIRST_TIMER); ++ ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL ++ || (TIMER_FLAG_MASK_HANDLE(flag) == ++ TIMER_FLAG_CALLBACK_IN_IRQ ++ && timer_dev.timer[timer - FIRST_TIMER].arg1)) { ++ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; ++ } ++ } else ++ irnen_reg = 0; ++ ++ /* ++ * Write config register, reload value and enable interrupt. ++ */ ++ n = timer >> 1; ++ X = timer & 0x01; ++ *LQ_GPTU_CON(n, X) = con_reg; ++ *LQ_GPTU_RELOAD(n, X) = value; ++ /* printk("reload value = %d\n", (u32)value); */ ++ *LQ_GPTU_IRNEN |= irnen_reg; ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ printk("successful!\n"); ++ return ret; ++} ++EXPORT_SYMBOL(lq_request_timer); ++ ++int lq_free_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ if (GPTU_CON_EN(n, X)) ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); ++ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); ++ ++ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { ++ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; ++ } ++ ++ timer_dev.occupation &= ~mask; ++ if (!timer_dev.occupation && timer_dev.f_gptu_on) { ++ lq_disable_gptu(); ++ timer_dev.f_gptu_on = 0; ++ } ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_free_timer); ++ ++int lq_start_timer(unsigned int timer, int is_resume) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); ++ ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_start_timer); ++ ++int lq_stop_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_stop_timer); ++ ++int lq_reset_counter_flags(u32 timer, u32 flags) ++{ ++ unsigned int oflag; ++ unsigned int mask, con_reg; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ oflag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ switch (TIMER_FLAG_MASK_EDGE(flags)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); ++ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); ++ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flags; ++ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_CON(n, X) = con_reg; ++ smp_wmb(); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return 0; ++} ++EXPORT_SYMBOL(lq_reset_counter_flags); ++ ++int lq_get_count_value(unsigned int timer, unsigned long *value) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *value = *LQ_GPTU_COUNT(n, X); ++ ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_get_count_value); ++ ++u32 lq_cal_divider(unsigned long freq) ++{ ++ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); ++ u32 clock_divider = 1; ++ module_freq = fpi * 1000; ++ do_div(module_freq, clock_divider * freq); ++ return module_freq; ++} ++EXPORT_SYMBOL(lq_cal_divider); ++ ++int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, ++ int is_ext_src, unsigned int handle_flag, unsigned long arg1, ++ unsigned long arg2) ++{ ++ unsigned long divider; ++ unsigned int flag; ++ ++ divider = lq_cal_divider(freq); ++ if (divider == 0) ++ return -EINVAL; ++ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) ++ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) ++ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) ++ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN ++ | TIMER_FLAG_MASK_HANDLE(handle_flag); ++ ++ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", ++ timer, freq, divider); ++ return lq_request_timer(timer, flag, divider, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_timer); ++ ++int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, ++ unsigned long arg1, unsigned long arg2) ++{ ++ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); ++ return lq_request_timer(timer, flag, reload, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_counter); ++ ++static long gptu_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ int ret; ++ struct gptu_ioctl_param param; ++ ++ if (!access_ok((void __user *)arg, sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ copy_from_user(¶m, (void __user *)arg, sizeof(param)); ++ ++ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER ++ || GPTU_SET_COUNTER) && param.timer < 2) ++ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) ++ && !access_ok((void __user *)arg, ++ sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ ++ switch (cmd) { ++ case GPTU_REQUEST_TIMER: ++ ret = lq_request_timer(param.timer, param.flag, param.value, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ case GPTU_FREE_TIMER: ++ ret = lq_free_timer(param.timer); ++ break; ++ case GPTU_START_TIMER: ++ ret = lq_start_timer(param.timer, param.flag); ++ break; ++ case GPTU_STOP_TIMER: ++ ret = lq_stop_timer(param.timer); ++ break; ++ case GPTU_GET_COUNT_VALUE: ++ ret = lq_get_count_value(param.timer, ¶m.value); ++ if (!ret) ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value, ++ sizeof(param.value)); ++ break; ++ case GPTU_CALCULATE_DIVIDER: ++ param.value = lq_cal_divider(param.value); ++ if (param.value == 0) ++ ret = -EINVAL; ++ else { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value, ++ sizeof(param.value)); ++ ret = 0; ++ } ++ break; ++ case GPTU_SET_TIMER: ++ ret = lq_set_timer(param.timer, param.value, ++ TIMER_FLAG_MASK_STOP(param.flag) != ++ TIMER_FLAG_ONCE ? 1 : 0, ++ TIMER_FLAG_MASK_SRC(param.flag) == ++ TIMER_FLAG_EXT_SRC ? 1 : 0, ++ TIMER_FLAG_MASK_HANDLE(param.flag) == ++ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : ++ TIMER_FLAG_NO_HANDLE, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ case GPTU_SET_COUNTER: ++ lq_set_counter(param.timer, param.flag, param.value, 0, 0); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ default: ++ ret = -ENOTTY; ++ } ++ ++ return ret; ++} ++ ++static int gptu_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static int gptu_release(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++int __init lq_gptu_init(void) ++{ ++ int ret; ++ unsigned int i; ++ ++ ltq_w32(0, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ memset(&timer_dev, 0, sizeof(timer_dev)); ++ mutex_init(&timer_dev.gptu_mutex); ++ ++ lq_enable_gptu(); ++ timer_dev.number_of_timers = GPTU_ID_CFG * 2; ++ lq_disable_gptu(); ++ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) ++ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; ++ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); ++ ++ ret = misc_register(&gptu_miscdev); ++ if (ret) { ++ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); ++ return ret; ++ } else { ++ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); ++ } ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); ++ if (ret) { ++ for (; i >= 0; i--) ++ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); ++ misc_deregister(&gptu_miscdev); ++ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); ++ return ret; ++ } else { ++ timer_dev.timer[i].irq = TIMER_INTERRUPT + i; ++ disable_irq(timer_dev.timer[i].irq); ++ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); ++ } ++ } ++ ++ return 0; ++} ++ ++void __exit lq_gptu_exit(void) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ if (timer_dev.timer[i].f_irq_on) ++ disable_irq(timer_dev.timer[i].irq); ++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); ++ } ++ lq_disable_gptu(); ++ misc_deregister(&gptu_miscdev); ++} ++ ++module_init(lq_gptu_init); ++module_exit(lq_gptu_exit); ++ ++#endif diff --git a/target/linux/lantiq/patches-5.15/0018-MTD-nand-lots-of-xrx200-fixes.patch b/target/linux/lantiq/patches-5.15/0018-MTD-nand-lots-of-xrx200-fixes.patch new file mode 100644 index 0000000000..35f656da6e --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0018-MTD-nand-lots-of-xrx200-fixes.patch @@ -0,0 +1,121 @@ +From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 9 Sep 2014 23:12:15 +0200 +Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/raw/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 63 insertions(+) + +--- a/drivers/mtd/nand/raw/xway_nand.c ++++ b/drivers/mtd/nand/raw/xway_nand.c +@@ -61,6 +61,24 @@ + #define NAND_CON_CSMUX (1 << 1) + #define NAND_CON_NANDM 1 + ++#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr)) ++#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400) ++#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080) ++ ++/* ++ * req_mask provides a mechanism to prevent interference between ++ * nand and pci (probably only relevant for the BT Home Hub 2B). ++ * Setting it causes the corresponding pci req pins to be masked ++ * during nand access, and also moves ebu locking from the read/write ++ * functions to the chip select function to ensure that the whole ++ * operation runs with interrupts disabled. ++ * In addition it switches on some extra waiting in xway_cmd_ctrl(). ++ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled, ++ * which in turn seems to be necessary for the nor chip to be recognised ++ * reliably, on a board (Home Hub 2B again) which has both nor and nand. ++ */ ++static __be32 req_mask = 0; ++ + struct xway_nand_data { + struct nand_controller controller; + struct nand_chip chip; +@@ -92,10 +110,22 @@ static void xway_select_chip(struct nand + case -1: + ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); ++ ++ if (req_mask) { ++ /* Unmask all external PCI request */ ++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16); ++ } ++ + spin_unlock_irqrestore(&ebu_lock, data->csflags); + break; + case 0: + spin_lock_irqsave(&ebu_lock, data->csflags); ++ ++ if (req_mask) { ++ /* Mask all external PCI request */ ++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16); ++ } ++ + ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); + ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); + break; +@@ -108,6 +138,11 @@ static void xway_cmd_ctrl(struct nand_ch + { + struct mtd_info *mtd = nand_to_mtd(chip); + ++ if (req_mask) { ++ if (cmd != NAND_CMD_STATUS) ++ ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */ ++ } ++ + if (cmd == NAND_CMD_NONE) + return; + +@@ -118,6 +153,24 @@ static void xway_cmd_ctrl(struct nand_ch + + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; ++ ++ if (req_mask) { ++ /* ++ * program and erase have their own busy handlers ++ * status and sequential in needs no delay ++ */ ++ switch (cmd) { ++ case NAND_CMD_ERASE1: ++ case NAND_CMD_SEQIN: ++ case NAND_CMD_STATUS: ++ case NAND_CMD_READID: ++ return; ++ } ++ ++ /* wait until command is processed */ ++ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) ++ ; ++ } + } + + static int xway_dev_ready(struct nand_chip *chip) +@@ -170,6 +223,7 @@ static int xway_nand_probe(struct platfo + int err; + u32 cs; + u32 cs_flag = 0; ++ const __be32 *req_mask_ptr; + + /* Allocate memory for the device structure (and zero it) */ + data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), +@@ -206,6 +260,15 @@ static int xway_nand_probe(struct platfo + if (!err && cs == 1) + cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; + ++ req_mask_ptr = of_get_property(pdev->dev.of_node, ++ "req-mask", NULL); ++ ++ /* ++ * Load the PCI req lines to mask from the device tree. If the ++ * property is not present, setting req_mask to 0 disables masking. ++ */ ++ req_mask = (req_mask_ptr ? *req_mask_ptr : 0); ++ + /* setup the EBU to run in NAND mode on our base addr */ + ltq_ebu_w32(CPHYSADDR(data->nandaddr) + | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); diff --git a/target/linux/lantiq/patches-5.15/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch b/target/linux/lantiq/patches-5.15/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch new file mode 100644 index 0000000000..c1fc59487a --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch @@ -0,0 +1,25 @@ +From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:18:00 +0200 +Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash + +Signed-off-by: John Crispin +--- + drivers/mtd/maps/lantiq-flash.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -129,7 +129,11 @@ ltq_mtd_probe(struct platform_device *pd + if (!ltq_mtd->map) + return -ENOMEM; + +- ltq_mtd->map->phys = ltq_mtd->res->start; ++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) ++ ltq_mtd->map->phys = NO_XIP; ++ else ++ ltq_mtd->map->phys = ltq_mtd->res->start; ++ ltq_mtd->res->start; + ltq_mtd->map->size = resource_size(ltq_mtd->res); + ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); + if (IS_ERR(ltq_mtd->map->virt)) diff --git a/target/linux/lantiq/patches-5.15/0023-NET-PHY-add-led-support-for-intel-xway.patch b/target/linux/lantiq/patches-5.15/0023-NET-PHY-add-led-support-for-intel-xway.patch new file mode 100644 index 0000000000..fb8d975110 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0023-NET-PHY-add-led-support-for-intel-xway.patch @@ -0,0 +1,294 @@ +From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:15:36 +0200 +Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G + +Signed-off-by: John Crispin +--- + drivers/net/phy/Kconfig | 5 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 237 insertions(+) + create mode 100644 drivers/net/phy/lantiq.c + +--- a/drivers/net/phy/intel-xway.c ++++ b/drivers/net/phy/intel-xway.c +@@ -157,6 +157,51 @@ + #define PHY_ID_PHY11G_VR9_1_2 0xD565A409 + #define PHY_ID_PHY22F_VR9_1_2 0xD565A419 + ++#if IS_ENABLED(CONFIG_OF_MDIO) ++static int vr9_gphy_of_reg_init(struct phy_device *phydev) ++{ ++ u32 tmp; ++ ++ /* store the led values if one was passed by the devicetree */ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp); ++ ++ return 0; ++} ++#else ++static int vr9_gphy_of_reg_init(struct phy_device *phydev) ++{ ++ return 0; ++} ++#endif /* CONFIG_OF_MDIO */ ++ + static int xway_gphy_config_init(struct phy_device *phydev) + { + int err; +@@ -204,6 +249,7 @@ static int xway_gphy_config_init(struct + phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); + phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); + ++ vr9_gphy_of_reg_init(phydev); + return 0; + } + +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt +@@ -0,0 +1,216 @@ ++Lanitq PHY binding ++============================================ ++ ++This devicetree binding controls the lantiq ethernet phys led functionality. ++ ++Example: ++ mdio@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "lantiq,xrx200-mdio"; ++ phy5: ethernet-phy@5 { ++ reg = <0x1>; ++ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; ++ }; ++ phy11: ethernet-phy@11 { ++ reg = <0x11>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led2h = <0x00>; ++ lantiq,led2l = <0x03>; ++ }; ++ phy12: ethernet-phy@12 { ++ reg = <0x12>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led1h = <0x00>; ++ lantiq,led1l = <0x03>; ++ }; ++ phy13: ethernet-phy@13 { ++ reg = <0x13>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led2h = <0x00>; ++ lantiq,led2l = <0x03>; ++ }; ++ phy14: ethernet-phy@14 { ++ reg = <0x14>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led1h = <0x00>; ++ lantiq,led1l = <0x03>; ++ }; ++ }; ++ ++Register Description ++============================================ ++ ++LEDCH: ++ ++Name Hardware Reset Value ++LEDCH 0x00C5 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++| FBF | SBF |RES | NACS | ++========================================= ++ ++Field Bits Type Description ++FBF 7:6 RW Fast Blink Frequency ++ --- ++ 0x0 (00b) F02HZ 2 Hz blinking frequency ++ 0x1 (01b) F04HZ 4 Hz blinking frequency ++ 0x2 (10b) F08HZ 8 Hz blinking frequency ++ 0x3 (11b) F16HZ 16 Hz blinking frequency ++ ++SBF 5:4 RW Slow Blink Frequency ++ --- ++ 0x0 (00b) F02HZ 2 Hz blinking frequency ++ 0x1 (01b) F04HZ 4 Hz blinking frequency ++ 0x2 (10b) F08HZ 8 Hz blinking frequency ++ 0x3 (11b) F16HZ 16 Hz blinking frequency ++ ++NACS 2:0 RW Inverse of Scan Function ++ --- ++ 0x0 (000b) NONE No Function ++ 0x1 (001b) LINK Complex function enabled when link is up ++ 0x2 (010b) PDOWN Complex function enabled when device is powered-down ++ 0x3 (011b) EEE Complex function enabled when device is in EEE mode ++ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running ++ 0x5 (101b) ABIST Complex function enabled when analog self-test is running ++ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running ++ 0x7 (111b) TEST Complex function enabled when test mode is running ++ ++LEDCL: ++ ++Name Hardware Reset Value ++LEDCL 0x0067 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++|RES | SCAN |RES | CBLINK | ++========================================= ++ ++Field Bits Type Description ++SCAN 6:4 RW Complex Scan Configuration ++ --- ++ 000 B NONE No Function ++ 001 B LINK Complex function enabled when link is up ++ 010 B PDOWN Complex function enabled when device is powered-down ++ 011 B EEE Complex function enabled when device is in EEE mode ++ 100 B ANEG Complex function enabled when auto-negotiation is running ++ 101 B ABIST Complex function enabled when analog self-test is running ++ 110 B CDIAG Complex function enabled when cable diagnostics are running ++ 111 B TEST Complex function enabled when test mode is running ++ ++CBLINK 2:0 RW Complex Blinking Configuration ++ --- ++ 000 B NONE No Function ++ 001 B LINK Complex function enabled when link is up ++ 010 B PDOWN Complex function enabled when device is powered-down ++ 011 B EEE Complex function enabled when device is in EEE mode ++ 100 B ANEG Complex function enabled when auto-negotiation is running ++ 101 B ABIST Complex function enabled when analog self-test is running ++ 110 B CDIAG Complex function enabled when cable diagnostics are running ++ 111 B TEST Complex function enabled when test mode is running ++ ++LEDxH: ++ ++Name Hardware Reset Value ++LED0H 0x0070 ++LED1H 0x0020 ++LED2H 0x0040 ++LED3H 0x0040 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++| CON | BLINKF | ++========================================= ++ ++Field Bits Type Description ++CON 7:4 RW Constant On Configuration ++ --- ++ 0x0 (0000b) NONE LED does not light up constantly ++ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s ++ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s ++ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s ++ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s ++ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s ++ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s ++ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s ++ 0x8 (1000b) PDOWN LED is on when device is powered-down ++ 0x9 (1001b) EEE LED is on when device is in EEE mode ++ 0xA (1010b) ANEG LED is on when auto-negotiation is running ++ 0xB (1011b) ABIST LED is on when analog self-test is running ++ 0xC (1100b) CDIAG LED is on when cable diagnostics are running ++ ++BLINKF 3:0 RW Fast Blinking Configuration ++ --- ++ 0x0 (0000b) NONE No Blinking ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s ++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s ++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s ++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s ++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s ++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s ++ 0x8 (1000b) PDOWN Blink when device is powered-down ++ 0x9 (1001b) EEE Blink when device is in EEE mode ++ 0xA (1010b) ANEG Blink when auto-negotiation is running ++ 0xB (1011b) ABIST Blink when analog self-test is running ++ 0xC (1100b) CDIAG Blink when cable diagnostics are running ++ ++LEDxL: ++ ++Name Hardware Reset Value ++LED0L 0x0003 ++LED1L 0x0000 ++LED2L 0x0000 ++LED3L 0x0020 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++| BLINKS | PULSE | ++========================================= ++ ++Field Bits Type Description ++BLINKS 7:4 RW Slow Blinkin Configuration ++ --- ++ 0x0 (0000b) NONE No Blinking ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s ++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s ++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s ++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s ++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s ++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s ++ 0x8 (1000b) PDOWN Blink when device is powered-down ++ 0x9 (1001b) EEE Blink when device is in EEE mode ++ 0xA (1010b) ANEG Blink when auto-negotiation is running ++ 0xB (1011b) ABIST Blink when analog self-test is running ++ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning ++ ++PULSE 3:0 RW Pulsing Configuration ++ The pulse field is a mask field by which certain events can be combined ++ --- ++ 0x0 (0000b) NONE No pulsing ++ 0x1 (0001b) TXACT Transmit activity ++ 0x2 (0010b) RXACT Receive activity ++ 0x4 (0100b) COL Collision ++ 0x8 (1000b) RES Reserved diff --git a/target/linux/lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch b/target/linux/lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch new file mode 100644 index 0000000000..eb47010fa0 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch @@ -0,0 +1,865 @@ +From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 9 Sep 2014 22:45:34 +0200 +Subject: [PATCH 28/36] NET: lantiq: various etop fixes + +Signed-off-by: John Crispin +--- + drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- + 1 file changed, 389 insertions(+), 166 deletions(-) + +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* + * +- * Copyright (C) 2011 John Crispin ++ * Copyright (C) 2011-12 John Crispin + */ + + #include +@@ -20,11 +20,16 @@ + #include + #include + #include ++#include + #include + #include + #include + #include + #include ++#include ++#include ++#include ++#include + + #include + +@@ -32,7 +37,7 @@ + #include + #include + +-#define LTQ_ETOP_MDIO 0x11804 ++#define LTQ_ETOP_MDIO_ACC 0x11804 + #define MDIO_REQUEST 0x80000000 + #define MDIO_READ 0x40000000 + #define MDIO_ADDR_MASK 0x1f +@@ -41,44 +46,91 @@ + #define MDIO_REG_OFFSET 0x10 + #define MDIO_VAL_MASK 0xffff + +-#define PPE32_CGEN 0x800 +-#define LQ_PPE32_ENET_MAC_CFG 0x1840 ++#define LTQ_ETOP_MDIO_CFG 0x11800 ++#define MDIO_CFG_MASK 0x6 ++ ++#define LTQ_ETOP_CFG 0x11808 ++#define LTQ_ETOP_IGPLEN 0x11820 ++#define LTQ_ETOP_MAC_CFG 0x11840 + + #define LTQ_ETOP_ENETS0 0x11850 + #define LTQ_ETOP_MAC_DA0 0x1186C + #define LTQ_ETOP_MAC_DA1 0x11870 +-#define LTQ_ETOP_CFG 0x16020 +-#define LTQ_ETOP_IGPLEN 0x16080 ++ ++#define MAC_CFG_MASK 0xfff ++#define MAC_CFG_CGEN (1 << 11) ++#define MAC_CFG_DUPLEX (1 << 2) ++#define MAC_CFG_SPEED (1 << 1) ++#define MAC_CFG_LINK (1 << 0) + + #define MAX_DMA_CHAN 0x8 + #define MAX_DMA_CRC_LEN 0x4 + #define MAX_DMA_DATA_LEN 0x600 + + #define ETOP_FTCU BIT(28) +-#define ETOP_MII_MASK 0xf +-#define ETOP_MII_NORMAL 0xd +-#define ETOP_MII_REVERSE 0xe + #define ETOP_PLEN_UNDER 0x40 +-#define ETOP_CGEN 0x800 ++#define ETOP_CFG_MII0 0x01 + +-/* use 2 static channels for TX/RX */ +-#define LTQ_ETOP_TX_CHANNEL 1 +-#define LTQ_ETOP_RX_CHANNEL 6 +-#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) +-#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) ++#define ETOP_CFG_MASK 0xfff ++#define ETOP_CFG_FEN0 (1 << 8) ++#define ETOP_CFG_SEN0 (1 << 6) ++#define ETOP_CFG_OFF1 (1 << 3) ++#define ETOP_CFG_REMII0 (1 << 1) ++#define ETOP_CFG_OFF0 (1 << 0) ++ ++#define LTQ_GBIT_MDIO_CTL 0xCC ++#define LTQ_GBIT_MDIO_DATA 0xd0 ++#define LTQ_GBIT_GCTL0 0x68 ++#define LTQ_GBIT_PMAC_HD_CTL 0x8c ++#define LTQ_GBIT_P0_CTL 0x4 ++#define LTQ_GBIT_PMAC_RX_IPG 0xa8 ++#define LTQ_GBIT_RGMII_CTL 0x78 ++ ++#define PMAC_HD_CTL_AS (1 << 19) ++#define PMAC_HD_CTL_RXSH (1 << 22) ++ ++/* Switch Enable (0=disable, 1=enable) */ ++#define GCTL0_SE 0x80000000 ++/* Disable MDIO auto polling (0=disable, 1=enable) */ ++#define PX_CTL_DMDIO 0x00400000 ++ ++/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ ++#define MDC_CLOCK_MASK 0xff000000 ++#define MDC_CLOCK_OFFSET 24 ++ ++/* register information for the gbit's MDIO bus */ ++#define MDIO_XR9_REQUEST 0x00008000 ++#define MDIO_XR9_READ 0x00000800 ++#define MDIO_XR9_WRITE 0x00000400 ++#define MDIO_XR9_REG_MASK 0x1f ++#define MDIO_XR9_ADDR_MASK 0x1f ++#define MDIO_XR9_RD_MASK 0xffff ++#define MDIO_XR9_REG_OFFSET 0 ++#define MDIO_XR9_ADDR_OFFSET 5 ++#define MDIO_XR9_WR_OFFSET 16 + ++#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \ ++ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) ++ ++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ + #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) + #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) + #define ltq_etop_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_etop_membase + (z)) + +-#define DRV_VERSION "1.0" ++#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) ++#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) ++#define ltq_gbit_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) ++ ++#define DRV_VERSION "1.2" + + static void __iomem *ltq_etop_membase; ++static void __iomem *ltq_gbit_membase; + + struct ltq_etop_chan { +- int idx; + int tx_free; ++ int irq; + struct net_device *netdev; + struct napi_struct napi; + struct ltq_dma_channel dma; +@@ -88,23 +140,36 @@ struct ltq_etop_chan { + struct ltq_etop_priv { + struct net_device *netdev; + struct platform_device *pdev; +- struct ltq_eth_data *pldata; + struct resource *res; + + struct mii_bus *mii_bus; + +- struct ltq_etop_chan ch[MAX_DMA_CHAN]; +- int tx_free[MAX_DMA_CHAN >> 1]; ++ struct ltq_etop_chan txch; ++ struct ltq_etop_chan rxch; + +- spinlock_t lock; ++ int tx_irq; ++ int rx_irq; ++ ++ unsigned char mac[6]; ++ phy_interface_t mii_mode; ++ ++ spinlock_t lock; ++ ++ struct clk *clk_ppe; ++ struct clk *clk_switch; ++ struct clk *clk_ephy; ++ struct clk *clk_ephycgu; + }; + ++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data); ++ + static int + ltq_etop_alloc_skb(struct ltq_etop_chan *ch) + { + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + +- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); ++ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); + if (!ch->skb[ch->dma.desc]) + return -ENOMEM; + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev, +@@ -139,8 +204,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan + spin_unlock_irqrestore(&priv->lock, flags); + + skb_put(skb, len); ++ skb->dev = ch->netdev; + skb->protocol = eth_type_trans(skb, ch->netdev); + netif_receive_skb(skb); ++ ch->netdev->stats.rx_packets++; ++ ch->netdev->stats.rx_bytes += len; + } + + static int +@@ -148,7 +216,9 @@ ltq_etop_poll_rx(struct napi_struct *nap + { + struct ltq_etop_chan *ch = container_of(napi, + struct ltq_etop_chan, napi); ++ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + int work_done = 0; ++ unsigned long flags; + + while (work_done < budget) { + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +@@ -160,7 +230,9 @@ ltq_etop_poll_rx(struct napi_struct *nap + } + if (work_done < budget) { + napi_complete_done(&ch->napi, work_done); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + } + return work_done; + } +@@ -172,12 +244,14 @@ ltq_etop_poll_tx(struct napi_struct *nap + container_of(napi, struct ltq_etop_chan, napi); + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + struct netdev_queue *txq = +- netdev_get_tx_queue(ch->netdev, ch->idx >> 1); ++ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + while ((ch->dma.desc_base[ch->tx_free].ctl & + (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { ++ ch->netdev->stats.tx_packets++; ++ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len; + dev_kfree_skb_any(ch->skb[ch->tx_free]); + ch->skb[ch->tx_free] = NULL; + memset(&ch->dma.desc_base[ch->tx_free], 0, +@@ -190,7 +264,9 @@ ltq_etop_poll_tx(struct napi_struct *nap + if (netif_tx_queue_stopped(txq)) + netif_tx_start_queue(txq); + napi_complete(&ch->napi); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + return 1; + } + +@@ -198,9 +274,10 @@ static irqreturn_t + ltq_etop_dma_irq(int irq, void *_priv) + { + struct ltq_etop_priv *priv = _priv; +- int ch = irq - LTQ_DMA_CH0_INT; +- +- napi_schedule(&priv->ch[ch].napi); ++ if (irq == priv->txch.dma.irq) ++ napi_schedule(&priv->txch.napi); ++ else ++ napi_schedule(&priv->rxch.napi); + return IRQ_HANDLED; + } + +@@ -212,7 +289,7 @@ ltq_etop_free_channel(struct net_device + ltq_dma_free(&ch->dma); + if (ch->dma.irq) + free_irq(ch->dma.irq, priv); +- if (IS_RX(ch->idx)) { ++ if (ch == &priv->txch) { + int desc; + for (desc = 0; desc < LTQ_DESC_NUM; desc++) + dev_kfree_skb_any(ch->skb[ch->dma.desc]); +@@ -223,66 +300,135 @@ static void + ltq_etop_hw_exit(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; + +- ltq_pmu_disable(PMU_PPE); +- for (i = 0; i < MAX_DMA_CHAN; i++) +- if (IS_TX(i) || IS_RX(i)) +- ltq_etop_free_channel(dev, &priv->ch[i]); ++ clk_disable(priv->clk_ppe); ++ ++ if (of_machine_is_compatible("lantiq,ar9")) ++ clk_disable(priv->clk_switch); ++ ++ if (of_machine_is_compatible("lantiq,ase")) { ++ clk_disable(priv->clk_ephy); ++ clk_disable(priv->clk_ephycgu); ++ } ++ ++ ltq_etop_free_channel(dev, &priv->txch); ++ ltq_etop_free_channel(dev, &priv->rxch); ++} ++ ++static void ++ltq_etop_gbit_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ ++ clk_enable(priv->clk_switch); ++ ++ /* enable gbit port0 on the SoC */ ++ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL); ++ ++ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); ++ /* disable MDIO auto polling mode */ ++ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); ++ /* set 1522 packet size */ ++ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); ++ /* disable pmac & dmac headers */ ++ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, ++ LTQ_GBIT_PMAC_HD_CTL); ++ /* Due to traffic halt when burst length 8, ++ replace default IPG value with 0x3B */ ++ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); ++ /* set mdc clock to 2.5 MHz */ ++ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, ++ LTQ_GBIT_RGMII_CTL); + } + + static int + ltq_etop_hw_init(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ phy_interface_t mii_mode = priv->mii_mode; + +- ltq_pmu_enable(PMU_PPE); ++ clk_enable(priv->clk_ppe); + +- switch (priv->pldata->mii_mode) { ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ ltq_etop_gbit_init(dev); ++ /* force the etops link to the gbit to MII */ ++ mii_mode = PHY_INTERFACE_MODE_MII; ++ } ++ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG); ++ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX | ++ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG); ++ ++ switch (mii_mode) { + case PHY_INTERFACE_MODE_RMII: +- ltq_etop_w32_mask(ETOP_MII_MASK, +- ETOP_MII_REVERSE, LTQ_ETOP_CFG); ++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 | ++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); + break; + + case PHY_INTERFACE_MODE_MII: +- ltq_etop_w32_mask(ETOP_MII_MASK, +- ETOP_MII_NORMAL, LTQ_ETOP_CFG); ++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 | ++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); + break; + + default: ++ if (of_machine_is_compatible("lantiq,ase")) { ++ clk_enable(priv->clk_ephy); ++ /* disable external MII */ ++ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); ++ /* enable clock for internal PHY */ ++ clk_enable(priv->clk_ephycgu); ++ /* we need to write this magic to the internal phy to ++ make it work */ ++ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); ++ pr_info("Selected EPHY mode\n"); ++ break; ++ } + netdev_err(dev, "unknown mii mode %d\n", +- priv->pldata->mii_mode); ++ mii_mode); + return -ENOTSUPP; + } + +- /* enable crc generation */ +- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); ++ return 0; ++} ++ ++static int ++ltq_etop_dma_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ int tx = priv->tx_irq - LTQ_DMA_ETOP; ++ int rx = priv->rx_irq - LTQ_DMA_ETOP; ++ int err; + + ltq_dma_init_port(DMA_PORT_ETOP); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- int irq = LTQ_DMA_CH0_INT + i; +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- ch->idx = ch->dma.nr = i; +- ch->dma.dev = &priv->pdev->dev; +- +- if (IS_TX(i)) { +- ltq_dma_alloc_tx(&ch->dma); +- request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); +- } else if (IS_RX(i)) { +- ltq_dma_alloc_rx(&ch->dma); +- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; +- ch->dma.desc++) +- if (ltq_etop_alloc_skb(ch)) +- return -ENOMEM; +- ch->dma.desc = 0; +- request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); ++ priv->txch.dma.nr = tx; ++ priv->txch.dma.dev = &priv->pdev->dev; ++ ltq_dma_alloc_tx(&priv->txch.dma); ++ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv); ++ if (err) { ++ netdev_err(dev, "failed to allocate tx irq\n"); ++ goto err_out; ++ } ++ priv->txch.dma.irq = priv->tx_irq; ++ ++ priv->rxch.dma.nr = rx; ++ priv->rxch.dma.dev = &priv->pdev->dev; ++ ltq_dma_alloc_rx(&priv->rxch.dma); ++ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; ++ priv->rxch.dma.desc++) { ++ if (ltq_etop_alloc_skb(&priv->rxch)) { ++ netdev_err(dev, "failed to allocate skbs\n"); ++ err = -ENOMEM; ++ goto err_out; + } +- ch->dma.irq = irq; + } +- return 0; ++ priv->rxch.dma.desc = 0; ++ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv); ++ if (err) ++ netdev_err(dev, "failed to allocate rx irq\n"); ++ else ++ priv->rxch.dma.irq = priv->rx_irq; ++err_out: ++ return err; + } + + static void +@@ -301,6 +447,39 @@ static const struct ethtool_ops ltq_etop + }; + + static int ++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | ++ (phy_data << MDIO_XR9_WR_OFFSET) | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ return 0; ++} ++ ++static int ++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; ++ return val; ++} ++ ++static int + ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) + { + u32 val = MDIO_REQUEST | +@@ -308,9 +487,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | + phy_data; + +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- ltq_etop_w32(val, LTQ_ETOP_MDIO); ++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); + return 0; + } + +@@ -321,12 +500,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in + ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); + +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- ltq_etop_w32(val, LTQ_ETOP_MDIO); +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; ++ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK; + return val; + } + +@@ -342,7 +521,10 @@ ltq_etop_mdio_probe(struct net_device *d + struct ltq_etop_priv *priv = netdev_priv(dev); + struct phy_device *phydev; + +- phydev = phy_find_first(priv->mii_bus); ++ if (of_machine_is_compatible("lantiq,ase")) ++ phydev = mdiobus_get_phy(priv->mii_bus, 8); ++ else ++ phydev = mdiobus_get_phy(priv->mii_bus, 0); + + if (!phydev) { + netdev_err(dev, "no PHY found\n"); +@@ -350,14 +532,17 @@ ltq_etop_mdio_probe(struct net_device *d + } + + phydev = phy_connect(dev, phydev_name(phydev), +- <q_etop_mdio_link, priv->pldata->mii_mode); ++ <q_etop_mdio_link, priv->mii_mode); + + if (IS_ERR(phydev)) { + netdev_err(dev, "Could not attach to PHY\n"); + return PTR_ERR(phydev); + } + +- phy_set_max_speed(phydev, SPEED_100); ++ if (of_machine_is_compatible("lantiq,ar9")) ++ phy_set_max_speed(phydev, SPEED_1000); ++ else ++ phy_set_max_speed(phydev, SPEED_100); + + phy_attached_info(phydev); + +@@ -378,8 +563,13 @@ ltq_etop_mdio_init(struct net_device *de + } + + priv->mii_bus->priv = dev; +- priv->mii_bus->read = ltq_etop_mdio_rd; +- priv->mii_bus->write = ltq_etop_mdio_wr; ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; ++ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; ++ } else { ++ priv->mii_bus->read = ltq_etop_mdio_rd; ++ priv->mii_bus->write = ltq_etop_mdio_wr; ++ } + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + priv->pdev->name, priv->pdev->id); +@@ -416,18 +606,21 @@ static int + ltq_etop_open(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; ++ napi_enable(&priv->txch.napi); ++ napi_enable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_open(&priv->txch.dma); ++ ltq_dma_enable_irq(&priv->txch.dma); ++ ltq_dma_open(&priv->rxch.dma); ++ ltq_dma_enable_irq(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ if (dev->phydev) ++ phy_start(dev->phydev); + +- if (!IS_TX(i) && (!IS_RX(i))) +- continue; +- ltq_dma_open(&ch->dma); +- ltq_dma_enable_irq(&ch->dma); +- napi_enable(&ch->napi); +- } +- phy_start(dev->phydev); + netif_tx_start_all_queues(dev); + return 0; + } +@@ -436,18 +629,19 @@ static int + ltq_etop_stop(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + + netif_tx_stop_all_queues(dev); +- phy_stop(dev->phydev); +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- if (!IS_RX(i) && !IS_TX(i)) +- continue; +- napi_disable(&ch->napi); +- ltq_dma_close(&ch->dma); +- } ++ if (dev->phydev) ++ phy_stop(dev->phydev); ++ napi_disable(&priv->txch.napi); ++ napi_disable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_close(&priv->txch.dma); ++ ltq_dma_close(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ + return 0; + } + +@@ -457,16 +651,16 @@ ltq_etop_tx(struct sk_buff *skb, struct + int queue = skb_get_queue_mapping(skb); + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); + struct ltq_etop_priv *priv = netdev_priv(dev); +- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; +- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +- int len; ++ struct ltq_dma_desc *desc = ++ &priv->txch.dma.desc_base[priv->txch.dma.desc]; + unsigned long flags; + u32 byte_offset; ++ int len; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + +- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { +- dev_kfree_skb_any(skb); ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ++ priv->txch.skb[priv->txch.dma.desc]) { + netdev_err(dev, "tx ring full\n"); + netif_tx_stop_queue(txq); + return NETDEV_TX_BUSY; +@@ -474,7 +668,7 @@ ltq_etop_tx(struct sk_buff *skb, struct + + /* dma needs to start on a 16 byte aligned address */ + byte_offset = CPHYSADDR(skb->data) % 16; +- ch->skb[ch->dma.desc] = skb; ++ priv->txch.skb[priv->txch.dma.desc] = skb; + + netif_trans_update(dev); + +@@ -484,11 +678,11 @@ ltq_etop_tx(struct sk_buff *skb, struct + wmb(); + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); +- ch->dma.desc++; +- ch->dma.desc %= LTQ_DESC_NUM; ++ priv->txch.dma.desc++; ++ priv->txch.dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + +- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) ++ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) + netif_tx_stop_queue(txq); + + return NETDEV_TX_OK; +@@ -499,11 +693,14 @@ ltq_etop_change_mtu(struct net_device *d + { + struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned long flags; ++ int max; + + dev->mtu = new_mtu; + ++ max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN; ++ + spin_lock_irqsave(&priv->lock, flags); +- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); ++ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN); + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +@@ -556,6 +753,9 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_hw; + ltq_etop_change_mtu(dev, 1500); ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + + memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); + if (!is_valid_ether_addr(mac.sa_data)) { +@@ -573,9 +773,10 @@ ltq_etop_init(struct net_device *dev) + dev->addr_assign_type = NET_ADDR_RANDOM; + + ltq_etop_set_multicast_list(dev); +- err = ltq_etop_mdio_init(dev); +- if (err) +- goto err_netdev; ++ if (!ltq_etop_mdio_init(dev)) ++ dev->ethtool_ops = <q_etop_ethtool_ops; ++ else ++ pr_warn("etop: mdio probe failed\n");; + return 0; + + err_netdev: +@@ -595,6 +796,9 @@ ltq_etop_tx_timeout(struct net_device *d + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + netif_trans_update(dev); + netif_wake_queue(dev); + return; +@@ -618,14 +822,18 @@ static const struct net_device_ops ltq_e + .ndo_tx_timeout = ltq_etop_tx_timeout, + }; + +-static int __init +-ltq_etop_probe(struct platform_device *pdev) ++static int ltq_etop_probe(struct platform_device *pdev) + { + struct net_device *dev; + struct ltq_etop_priv *priv; +- struct resource *res; ++ struct resource *res, *gbit_res, irqres[2]; + int err; +- int i; ++ ++ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2); ++ if (err != 2) { ++ dev_err(&pdev->dev, "failed to get etop irqs\n"); ++ return -EINVAL; ++ } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { +@@ -651,31 +859,62 @@ ltq_etop_probe(struct platform_device *p + goto err_out; + } + +- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); +- if (!dev) { +- err = -ENOMEM; +- goto err_out; ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!gbit_res) { ++ dev_err(&pdev->dev, "failed to get gbit resource\n"); ++ err = -ENOENT; ++ goto err_out; ++ } ++ ltq_gbit_membase = devm_ioremap(&pdev->dev, ++ gbit_res->start, resource_size(gbit_res)); ++ if (!ltq_gbit_membase) { ++ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", ++ pdev->id); ++ err = -ENOMEM; ++ goto err_out; ++ } + } ++ ++ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = <q_eth_netdev_ops; +- dev->ethtool_ops = <q_etop_ethtool_ops; + priv = netdev_priv(dev); + priv->res = res; + priv->pdev = pdev; +- priv->pldata = dev_get_platdata(&pdev->dev); + priv->netdev = dev; ++ priv->tx_irq = irqres[0].start; ++ priv->rx_irq = irqres[1].start; ++ err = of_get_phy_mode(pdev->dev.of_node, &priv->mii_mode); ++ if (err) ++ pr_err("Can't find phy-mode for port\n"); ++ ++ of_get_mac_address(pdev->dev.of_node, priv->mac); ++ ++ priv->clk_ppe = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_ppe)) ++ return PTR_ERR(priv->clk_ppe); ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ priv->clk_switch = clk_get(&pdev->dev, "switch"); ++ if (IS_ERR(priv->clk_switch)) ++ return PTR_ERR(priv->clk_switch); ++ } ++ if (of_machine_is_compatible("lantiq,ase")) { ++ priv->clk_ephy = clk_get(&pdev->dev, "ephy"); ++ if (IS_ERR(priv->clk_ephy)) ++ return PTR_ERR(priv->clk_ephy); ++ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); ++ if (IS_ERR(priv->clk_ephycgu)) ++ return PTR_ERR(priv->clk_ephycgu); ++ } ++ + spin_lock_init(&priv->lock); + SET_NETDEV_DEV(dev, &pdev->dev); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- if (IS_TX(i)) +- netif_napi_add(dev, &priv->ch[i].napi, +- ltq_etop_poll_tx, 8); +- else if (IS_RX(i)) +- netif_napi_add(dev, &priv->ch[i].napi, +- ltq_etop_poll_rx, 32); +- priv->ch[i].netdev = dev; +- } ++ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); ++ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); ++ priv->txch.netdev = dev; ++ priv->rxch.netdev = dev; + + err = register_netdev(dev); + if (err) +@@ -704,31 +943,22 @@ ltq_etop_remove(struct platform_device * + return 0; + } + ++static const struct of_device_id ltq_etop_match[] = { ++ { .compatible = "lantiq,etop-xway" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_etop_match); ++ + static struct platform_driver ltq_mii_driver = { ++ .probe = ltq_etop_probe, + .remove = ltq_etop_remove, + .driver = { + .name = "ltq_etop", ++ .of_match_table = ltq_etop_match, + }, + }; + +-int __init +-init_ltq_etop(void) +-{ +- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); +- +- if (ret) +- pr_err("ltq_etop: Error registering platform driver!"); +- return ret; +-} +- +-static void __exit +-exit_ltq_etop(void) +-{ +- platform_driver_unregister(<q_mii_driver); +-} +- +-module_init(init_ltq_etop); +-module_exit(exit_ltq_etop); ++module_platform_driver(ltq_mii_driver); + + MODULE_AUTHOR("John Crispin "); + MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/target/linux/lantiq/patches-5.15/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-5.15/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch new file mode 100644 index 0000000000..154cf226c1 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch @@ -0,0 +1,1034 @@ +From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:26:42 +0200 +Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master + +This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. + +Signed-off-by: Thomas Langer +Signed-off-by: John Crispin +--- + drivers/i2c/busses/Kconfig | 10 + + drivers/i2c/busses/Makefile | 1 + + drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++ + drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++ + 4 files changed, 992 insertions(+) + create mode 100644 drivers/i2c/busses/i2c-lantiq.c + create mode 100644 drivers/i2c/busses/i2c-lantiq.h + +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -753,6 +753,16 @@ config I2C_MESON + If you say yes to this option, support will be included for the + I2C interface on the Amlogic Meson family of SoCs. + ++config I2C_LANTIQ ++ tristate "Lantiq I2C interface" ++ depends on LANTIQ && SOC_FALCON ++ help ++ If you say yes to this option, support will be included for the ++ Lantiq I2C core. ++ ++ This driver can also be built as a module. If so, the module ++ will be called i2c-lantiq. ++ + config I2C_MPC + tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" + depends on PPC +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -72,6 +72,7 @@ obj-$(CONFIG_I2C_IMX_LPI2C) += i2c-imx-l + obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o + obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o + obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o ++obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o + obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o + obj-$(CONFIG_I2C_MESON) += i2c-meson.o + obj-$(CONFIG_I2C_MPC) += i2c-mpc.o +--- /dev/null ++++ b/drivers/i2c/busses/i2c-lantiq.c +@@ -0,0 +1,747 @@ ++ ++/* ++ * Lantiq I2C bus adapter ++ * ++ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * Copyright (C) 2012 Thomas Langer ++ */ ++ ++#include ++#include ++#include ++#include /* for kzalloc, kfree */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "i2c-lantiq.h" ++ ++/* ++ * CURRENT ISSUES: ++ * - no high speed support ++ * - ten bit mode is not tested (no slave devices) ++ */ ++ ++/* access macros */ ++#define i2c_r32(reg) \ ++ __raw_readl(&(priv->membase)->reg) ++#define i2c_w32(val, reg) \ ++ __raw_writel(val, &(priv->membase)->reg) ++#define i2c_w32_mask(clear, set, reg) \ ++ i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg) ++ ++#define DRV_NAME "i2c-lantiq" ++#define DRV_VERSION "1.00" ++ ++#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */ ++ ++#ifdef DEBUG ++#define LTQ_I2C_XFER_TIMEOUT (25*HZ) ++#else ++#define LTQ_I2C_XFER_TIMEOUT HZ ++#endif ++ ++#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ ++ I2C_IMSC_I2C_ERR_INT_EN) ++ ++#define LTQ_I2C_ARB_LOST (1 << 0) ++#define LTQ_I2C_NACK (1 << 1) ++#define LTQ_I2C_RX_UFL (1 << 2) ++#define LTQ_I2C_RX_OFL (1 << 3) ++#define LTQ_I2C_TX_UFL (1 << 4) ++#define LTQ_I2C_TX_OFL (1 << 5) ++ ++struct ltq_i2c { ++ struct mutex mutex; ++ ++ ++ /* active clock settings */ ++ unsigned int input_clock; /* clock input for i2c hardware block */ ++ unsigned int i2c_clock; /* approximated bus clock in kHz */ ++ ++ struct clk *clk_gate; ++ struct clk *clk_input; ++ ++ ++ /* resources (memory and interrupts) */ ++ int irq_lb; /* last burst irq */ ++ ++ struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */ ++ ++ struct i2c_adapter adap; ++ struct device *dev; ++ ++ struct completion cmd_complete; ++ ++ ++ /* message transfer data */ ++ struct i2c_msg *current_msg; /* current message */ ++ int msgs_num; /* number of messages to handle */ ++ u8 *msg_buf; /* current buffer */ ++ u32 msg_buf_len; /* remaining length of current buffer */ ++ int msg_err; /* error status of the current transfer */ ++ ++ ++ /* master status codes */ ++ enum { ++ STATUS_IDLE, ++ STATUS_ADDR, /* address phase */ ++ STATUS_WRITE, ++ STATUS_READ, ++ STATUS_READ_END, ++ STATUS_STOP ++ } status; ++}; ++ ++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id); ++ ++static inline void enable_burst_irq(struct ltq_i2c *priv) ++{ ++ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); ++} ++static inline void disable_burst_irq(struct ltq_i2c *priv) ++{ ++ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); ++} ++ ++static void prepare_msg_send_addr(struct ltq_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */ ++ u16 addr = msg->addr; ++ ++ /* new i2c_msg */ ++ priv->msg_buf = msg->buf; ++ priv->msg_buf_len = msg->len; ++ if (rd) ++ priv->status = STATUS_READ; ++ else ++ priv->status = STATUS_WRITE; ++ ++ /* send slave address */ ++ if (msg->flags & I2C_M_TEN) { ++ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); ++ i2c_w32(addr & 0xff, txd); ++ } else { ++ i2c_w32((addr & 0x7f) << 1 | rd, txd); ++ } ++} ++ ++static void ltq_i2c_set_tx_len(struct ltq_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int len = (msg->flags & I2C_M_TEN) ? 2 : 1; ++ ++ pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T'); ++ ++ priv->status = STATUS_ADDR; ++ ++ if (!(msg->flags & I2C_M_RD)) ++ len += msg->len; ++ else ++ /* set maximum received packet size (before rx int!) */ ++ i2c_w32(msg->len, mrps_ctrl); ++ i2c_w32(len, tps_ctrl); ++ enable_burst_irq(priv); ++} ++ ++static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap) ++{ ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ unsigned int input_clock = clk_get_rate(priv->clk_input); ++ u32 dec, inc = 1; ++ ++ /* clock changed? */ ++ if (priv->input_clock == input_clock) ++ return 0; ++ ++ /* ++ * this formula is only an approximation, found by the recommended ++ * values in the "I2C Architecture Specification 1.7.1" ++ */ ++ dec = input_clock / (priv->i2c_clock * 2); ++ if (dec <= 6) ++ return -ENXIO; ++ ++ i2c_w32(0, fdiv_high_cfg); ++ i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) | ++ (dec << I2C_FDIV_CFG_DEC_OFFSET), ++ fdiv_cfg); ++ ++ dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n", ++ input_clock, priv->i2c_clock, dec); ++ ++ priv->input_clock = input_clock; ++ return 0; ++} ++ ++static int ltq_i2c_hw_init(struct i2c_adapter *adap) ++{ ++ int ret = 0; ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++#ifndef DEBUG ++ /* set normal operation clock divider */ ++ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); ++#else ++ /* for debugging a higher divider value! */ ++ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); ++#endif ++ ++ /* setup clock */ ++ ret = ltq_i2c_hw_set_clock(adap); ++ if (ret != 0) { ++ dev_warn(priv->dev, "invalid clock settings\n"); ++ return ret; ++ } ++ ++ /* configure fifo */ ++ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ ++ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ ++ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ ++ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ ++ fifo_cfg); ++ ++ /* configure address */ ++ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in ++ the fifo */ ++ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ ++ I2C_ADDR_CFG_MnS_EN | /* we are master device */ ++ 0, /* our slave address (not used!) */ ++ addr_cfg); ++ ++ /* enable bus */ ++ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); ++ ++ return 0; ++} ++ ++static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv) ++{ ++ unsigned long timeout; ++ ++ timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT); ++ ++ do { ++ u32 stat = i2c_r32(bus_stat); ++ ++ if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE) ++ return 0; ++ ++ cond_resched(); ++ } while (!time_after_eq(jiffies, timeout)); ++ ++ dev_err(priv->dev, "timeout waiting for bus ready\n"); ++ return -ETIMEDOUT; ++} ++ ++static void ltq_i2c_tx(struct ltq_i2c *priv, int last) ++{ ++ if (priv->msg_buf_len && priv->msg_buf) { ++ i2c_w32(*priv->msg_buf, txd); ++ ++ if (--priv->msg_buf_len) ++ priv->msg_buf++; ++ else ++ priv->msg_buf = NULL; ++ } else { ++ last = 1; ++ } ++ ++ if (last) ++ disable_burst_irq(priv); ++} ++ ++static void ltq_i2c_rx(struct ltq_i2c *priv, int last) ++{ ++ u32 fifo_stat, timeout; ++ if (priv->msg_buf_len && priv->msg_buf) { ++ timeout = 5000000; ++ do { ++ fifo_stat = i2c_r32(ffs_stat); ++ } while (!fifo_stat && --timeout); ++ if (!timeout) { ++ last = 1; ++ pr_debug("\nrx timeout\n"); ++ goto err; ++ } ++ while (fifo_stat) { ++ *priv->msg_buf = i2c_r32(rxd); ++ if (--priv->msg_buf_len) { ++ priv->msg_buf++; ++ } else { ++ priv->msg_buf = NULL; ++ last = 1; ++ break; ++ } ++ /* ++ * do not read more than burst size, otherwise no "last ++ * burst" is generated and the transaction is blocked! ++ */ ++ fifo_stat = 0; ++ } ++ } else { ++ last = 1; ++ } ++err: ++ if (last) { ++ disable_burst_irq(priv); ++ ++ if (priv->status == STATUS_READ_END) { ++ /* ++ * do the STATUS_STOP and complete() here, as sometimes ++ * the tx_end is already seen before this is finished ++ */ ++ priv->status = STATUS_STOP; ++ complete(&priv->cmd_complete); ++ } else { ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++ priv->status = STATUS_READ_END; ++ } ++ } ++} ++ ++static void ltq_i2c_xfer_init(struct ltq_i2c *priv) ++{ ++ /* enable interrupts */ ++ i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc); ++ ++ /* trigger transfer of first msg */ ++ ltq_i2c_set_tx_len(priv); ++} ++ ++static void dump_msgs(struct i2c_msg msgs[], int num, int rx) ++{ ++#if defined(DEBUG) ++ int i, j; ++ pr_debug("Messages %d %s\n", num, rx ? "out" : "in"); ++ for (i = 0; i < num; i++) { ++ pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i, ++ (msgs[i].flags & I2C_M_RD) ? 'R' : 'T', ++ msgs[i].len, msgs[i].addr); ++ if (!(msgs[i].flags & I2C_M_RD) || rx) { ++ for (j = 0; j < msgs[i].len; j++) ++ pr_debug("%02X ", msgs[i].buf[j]); ++ } ++ pr_debug("\n"); ++ } ++#endif ++} ++ ++static void ltq_i2c_release_bus(struct ltq_i2c *priv) ++{ ++ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++} ++ ++static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], ++ int num) ++{ ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ int ret; ++ ++ dev_dbg(priv->dev, "xfer %u messages\n", num); ++ dump_msgs(msgs, num, 0); ++ ++ mutex_lock(&priv->mutex); ++ ++ init_completion(&priv->cmd_complete); ++ priv->current_msg = msgs; ++ priv->msgs_num = num; ++ priv->msg_err = 0; ++ priv->status = STATUS_IDLE; ++ ++ /* wait for the bus to become ready */ ++ ret = ltq_i2c_wait_bus_not_busy(priv); ++ if (ret) ++ goto done; ++ ++ while (priv->msgs_num) { ++ /* start the transfers */ ++ ltq_i2c_xfer_init(priv); ++ ++ /* wait for transfers to complete */ ++ ret = wait_for_completion_interruptible_timeout( ++ &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT); ++ if (ret == 0) { ++ dev_err(priv->dev, "controller timed out\n"); ++ ltq_i2c_hw_init(adap); ++ ret = -ETIMEDOUT; ++ goto done; ++ } else if (ret < 0) ++ goto done; ++ ++ if (priv->msg_err) { ++ if (priv->msg_err & LTQ_I2C_NACK) ++ ret = -ENXIO; ++ else ++ ret = -EREMOTEIO; ++ goto done; ++ } ++ if (--priv->msgs_num) ++ priv->current_msg++; ++ } ++ /* no error? */ ++ ret = num; ++ ++done: ++ ltq_i2c_release_bus(priv); ++ ++ mutex_unlock(&priv->mutex); ++ ++ if (ret >= 0) ++ dump_msgs(msgs, num, 1); ++ ++ pr_debug("XFER ret %d\n", ret); ++ return ret; ++} ++ ++static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id) ++{ ++ struct ltq_i2c *priv = dev_id; ++ struct i2c_msg *msg = priv->current_msg; ++ int last = (irq == priv->irq_lb); ++ ++ if (last) ++ pr_debug("LB "); ++ else ++ pr_debug("B "); ++ ++ if (msg->flags & I2C_M_RD) { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ pr_debug("X"); ++ prepare_msg_send_addr(priv); ++ disable_burst_irq(priv); ++ break; ++ case STATUS_READ: ++ case STATUS_READ_END: ++ pr_debug("R"); ++ ltq_i2c_rx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ pr_warn("Status R %d\n", priv->status); ++ break; ++ } ++ } else { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ pr_debug("x"); ++ prepare_msg_send_addr(priv); ++ break; ++ case STATUS_WRITE: ++ pr_debug("w"); ++ ltq_i2c_tx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ pr_warn("Status W %d\n", priv->status); ++ break; ++ } ++ } ++ ++ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); ++ return IRQ_HANDLED; ++} ++ ++static void ltq_i2c_isr_prot(struct ltq_i2c *priv) ++{ ++ u32 i_pro = i2c_r32(p_irqss); ++ ++ pr_debug("i2c-p"); ++ ++ /* not acknowledge */ ++ if (i_pro & I2C_P_IRQSS_NACK) { ++ priv->msg_err |= LTQ_I2C_NACK; ++ pr_debug(" nack"); ++ } ++ ++ /* arbitration lost */ ++ if (i_pro & I2C_P_IRQSS_AL) { ++ priv->msg_err |= LTQ_I2C_ARB_LOST; ++ pr_debug(" arb-lost"); ++ } ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) ++ pr_debug(" rx"); ++ ++ /* tx end */ ++ if (i_pro & I2C_P_IRQSS_TX_END) ++ pr_debug(" txend"); ++ pr_debug("\n"); ++ ++ if (!priv->msg_err) { ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) { ++ priv->status = STATUS_READ; ++ enable_burst_irq(priv); ++ } ++ if (i_pro & I2C_P_IRQSS_TX_END) { ++ if (priv->status == STATUS_READ) ++ priv->status = STATUS_READ_END; ++ else { ++ disable_burst_irq(priv); ++ priv->status = STATUS_STOP; ++ } ++ } ++ } ++ ++ i2c_w32(i_pro, p_irqsc); ++} ++ ++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id) ++{ ++ u32 i_raw, i_err = 0; ++ struct ltq_i2c *priv = dev_id; ++ ++ i_raw = i2c_r32(mis); ++ pr_debug("i_raw 0x%08X\n", i_raw); ++ ++ /* error interrupt */ ++ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { ++ i_err = i2c_r32(err_irqss); ++ pr_debug("i_err 0x%08X bus_stat 0x%04X\n", ++ i_err, i2c_r32(bus_stat)); ++ ++ /* tx fifo overflow (8) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_OFL) ++ priv->msg_err |= LTQ_I2C_TX_OFL; ++ ++ /* tx fifo underflow (4) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_UFL) ++ priv->msg_err |= LTQ_I2C_TX_UFL; ++ ++ /* rx fifo overflow (2) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_OFL) ++ priv->msg_err |= LTQ_I2C_RX_OFL; ++ ++ /* rx fifo underflow (1) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_UFL) ++ priv->msg_err |= LTQ_I2C_RX_UFL; ++ ++ i2c_w32(i_err, err_irqsc); ++ } ++ ++ /* protocol interrupt */ ++ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) ++ ltq_i2c_isr_prot(priv); ++ ++ if ((priv->msg_err) || (priv->status == STATUS_STOP)) ++ complete(&priv->cmd_complete); ++ ++ return IRQ_HANDLED; ++} ++ ++static u32 ltq_i2c_functionality(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | ++ I2C_FUNC_10BIT_ADDR | ++ I2C_FUNC_SMBUS_EMUL; ++} ++ ++static struct i2c_algorithm ltq_i2c_algorithm = { ++ .master_xfer = ltq_i2c_xfer, ++ .functionality = ltq_i2c_functionality, ++}; ++ ++static int ltq_i2c_probe(struct platform_device *pdev) ++{ ++ struct device_node *node = pdev->dev.of_node; ++ struct ltq_i2c *priv; ++ struct i2c_adapter *adap; ++ struct resource *mmres, irqres[4]; ++ int ret = 0; ++ ++ dev_dbg(&pdev->dev, "probing\n"); ++ ++ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ret = of_irq_to_resource_table(node, irqres, 4); ++ if (!mmres || (ret != 4)) { ++ dev_err(&pdev->dev, "no resources\n"); ++ return -ENODEV; ++ } ++ ++ /* allocate private data */ ++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) { ++ dev_err(&pdev->dev, "can't allocate private data\n"); ++ return -ENOMEM; ++ } ++ ++ adap = &priv->adap; ++ i2c_set_adapdata(adap, priv); ++ adap->owner = THIS_MODULE; ++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; ++ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); ++ adap->algo = <q_i2c_algorithm; ++ adap->dev.parent = &pdev->dev; ++ adap->dev.of_node = pdev->dev.of_node; ++ ++ if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) { ++ dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n"); ++ priv->i2c_clock = 100000; ++ } ++ ++ init_completion(&priv->cmd_complete); ++ mutex_init(&priv->mutex); ++ ++ priv->membase = devm_ioremap_resource(&pdev->dev, mmres); ++ if (IS_ERR(priv->membase)) ++ return PTR_ERR(priv->membase); ++ ++ priv->dev = &pdev->dev; ++ priv->irq_lb = irqres[0].start; ++ ++ ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst, ++ 0x0, "i2c lb", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", ++ irqres[0].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst, ++ 0x0, "i2c b", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get burst IRQ %d\n", ++ irqres[1].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr, ++ 0x0, "i2c err", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get error IRQ %d\n", ++ irqres[2].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr, ++ 0x0, "i2c p", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", ++ irqres[3].start); ++ return -ENODEV; ++ } ++ ++ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); ++ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start, ++ irqres[1].start, irqres[2].start, irqres[3].start); ++ ++ priv->clk_gate = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_gate)) { ++ dev_err(&pdev->dev, "failed to get i2c clk\n"); ++ return -ENOENT; ++ } ++ ++ /* this is a static clock, which has no refcounting */ ++ priv->clk_input = clk_get_fpi(); ++ if (IS_ERR(priv->clk_input)) { ++ dev_err(&pdev->dev, "failed to get fpi clk\n"); ++ return -ENOENT; ++ } ++ ++ clk_activate(priv->clk_gate); ++ ++ /* add our adapter to the i2c stack */ ++ ret = i2c_add_numbered_adapter(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't register I2C adapter\n"); ++ goto out; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ i2c_set_adapdata(adap, priv); ++ ++ /* print module version information */ ++ dev_dbg(&pdev->dev, "module id=%u revision=%u\n", ++ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, ++ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); ++ ++ /* initialize HW */ ++ ret = ltq_i2c_hw_init(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't configure adapter\n"); ++ i2c_del_adapter(adap); ++ platform_set_drvdata(pdev, NULL); ++ goto out; ++ } else { ++ dev_info(&pdev->dev, "version %s\n", DRV_VERSION); ++ } ++ ++out: ++ /* if init failed, we need to deactivate the clock gate */ ++ if (ret) ++ clk_deactivate(priv->clk_gate); ++ ++ return ret; ++} ++ ++static int ltq_i2c_remove(struct platform_device *pdev) ++{ ++ struct ltq_i2c *priv = platform_get_drvdata(pdev); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++ /* power down the core */ ++ clk_deactivate(priv->clk_gate); ++ ++ /* remove driver */ ++ i2c_del_adapter(&priv->adap); ++ kfree(priv); ++ ++ dev_dbg(&pdev->dev, "removed\n"); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++static const struct of_device_id ltq_i2c_match[] = { ++ { .compatible = "lantiq,lantiq-i2c" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_i2c_match); ++ ++static struct platform_driver ltq_i2c_driver = { ++ .probe = ltq_i2c_probe, ++ .remove = ltq_i2c_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = ltq_i2c_match, ++ }, ++}; ++ ++module_platform_driver(ltq_i2c_driver); ++ ++MODULE_DESCRIPTION("Lantiq I2C bus adapter"); ++MODULE_AUTHOR("Thomas Langer "); ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); +--- /dev/null ++++ b/drivers/i2c/busses/i2c-lantiq.h +@@ -0,0 +1,234 @@ ++#ifndef I2C_LANTIQ_H ++#define I2C_LANTIQ_H ++ ++/* I2C register structure */ ++struct lantiq_reg_i2c { ++ /* I2C Kernel Clock Control Register */ ++ unsigned int clc; /* 0x00000000 */ ++ /* Reserved */ ++ unsigned int res_0; /* 0x00000004 */ ++ /* I2C Identification Register */ ++ unsigned int id; /* 0x00000008 */ ++ /* Reserved */ ++ unsigned int res_1; /* 0x0000000C */ ++ /* ++ * I2C RUN Control Register ++ * This register enables and disables the I2C peripheral. Before ++ * enabling, the I2C has to be configured properly. After enabling ++ * no configuration is possible ++ */ ++ unsigned int run_ctrl; /* 0x00000010 */ ++ /* ++ * I2C End Data Control Register ++ * This register is used to either turn around the data transmission ++ * direction or to address another slave without sending a stop ++ * condition. Also the software can stop the slave-transmitter by ++ * sending a not-accolade when working as master-receiver or even ++ * stop data transmission immediately when operating as ++ * master-transmitter. The writing to the bits of this control ++ * register is only effective when in MASTER RECEIVES BYTES, MASTER ++ * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state ++ */ ++ unsigned int endd_ctrl; /* 0x00000014 */ ++ /* ++ * I2C Fractional Divider Configuration Register ++ * These register is used to program the fractional divider of the I2C ++ * bus. Before the peripheral is switched on by setting the RUN-bit the ++ * two (fixed) values for the two operating frequencies are programmed ++ * into these (configuration) registers. The Register FDIV_HIGH_CFG has ++ * the same layout as I2C_FDIV_CFG. ++ */ ++ unsigned int fdiv_cfg; /* 0x00000018 */ ++ /* ++ * I2C Fractional Divider (highspeed mode) Configuration Register ++ * These register is used to program the fractional divider of the I2C ++ * bus. Before the peripheral is switched on by setting the RUN-bit the ++ * two (fixed) values for the two operating frequencies are programmed ++ * into these (configuration) registers. The Register FDIV_CFG has the ++ * same layout as I2C_FDIV_CFG. ++ */ ++ unsigned int fdiv_high_cfg; /* 0x0000001C */ ++ /* I2C Address Configuration Register */ ++ unsigned int addr_cfg; /* 0x00000020 */ ++ /* I2C Bus Status Register ++ * This register gives a status information of the I2C. This additional ++ * information can be used by the software to start proper actions. ++ */ ++ unsigned int bus_stat; /* 0x00000024 */ ++ /* I2C FIFO Configuration Register */ ++ unsigned int fifo_cfg; /* 0x00000028 */ ++ /* I2C Maximum Received Packet Size Register */ ++ unsigned int mrps_ctrl; /* 0x0000002C */ ++ /* I2C Received Packet Size Status Register */ ++ unsigned int rps_stat; /* 0x00000030 */ ++ /* I2C Transmit Packet Size Register */ ++ unsigned int tps_ctrl; /* 0x00000034 */ ++ /* I2C Filled FIFO Stages Status Register */ ++ unsigned int ffs_stat; /* 0x00000038 */ ++ /* Reserved */ ++ unsigned int res_2; /* 0x0000003C */ ++ /* I2C Timing Configuration Register */ ++ unsigned int tim_cfg; /* 0x00000040 */ ++ /* Reserved */ ++ unsigned int res_3[7]; /* 0x00000044 */ ++ /* I2C Error Interrupt Request Source Mask Register */ ++ unsigned int err_irqsm; /* 0x00000060 */ ++ /* I2C Error Interrupt Request Source Status Register */ ++ unsigned int err_irqss; /* 0x00000064 */ ++ /* I2C Error Interrupt Request Source Clear Register */ ++ unsigned int err_irqsc; /* 0x00000068 */ ++ /* Reserved */ ++ unsigned int res_4; /* 0x0000006C */ ++ /* I2C Protocol Interrupt Request Source Mask Register */ ++ unsigned int p_irqsm; /* 0x00000070 */ ++ /* I2C Protocol Interrupt Request Source Status Register */ ++ unsigned int p_irqss; /* 0x00000074 */ ++ /* I2C Protocol Interrupt Request Source Clear Register */ ++ unsigned int p_irqsc; /* 0x00000078 */ ++ /* Reserved */ ++ unsigned int res_5; /* 0x0000007C */ ++ /* I2C Raw Interrupt Status Register */ ++ unsigned int ris; /* 0x00000080 */ ++ /* I2C Interrupt Mask Control Register */ ++ unsigned int imsc; /* 0x00000084 */ ++ /* I2C Masked Interrupt Status Register */ ++ unsigned int mis; /* 0x00000088 */ ++ /* I2C Interrupt Clear Register */ ++ unsigned int icr; /* 0x0000008C */ ++ /* I2C Interrupt Set Register */ ++ unsigned int isr; /* 0x00000090 */ ++ /* I2C DMA Enable Register */ ++ unsigned int dmae; /* 0x00000094 */ ++ /* Reserved */ ++ unsigned int res_6[8154]; /* 0x00000098 */ ++ /* I2C Transmit Data Register */ ++ unsigned int txd; /* 0x00008000 */ ++ /* Reserved */ ++ unsigned int res_7[4095]; /* 0x00008004 */ ++ /* I2C Receive Data Register */ ++ unsigned int rxd; /* 0x0000C000 */ ++ /* Reserved */ ++ unsigned int res_8[4095]; /* 0x0000C004 */ ++}; ++ ++/* ++ * Clock Divider for Normal Run Mode ++ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long ++ * as the new divider value RMC is not valid, the register returns 0x0000 00xx ++ * on reading. ++ */ ++#define I2C_CLC_RMC_MASK 0x0000FF00 ++/* field offset */ ++#define I2C_CLC_RMC_OFFSET 8 ++ ++/* Fields of "I2C Identification Register" */ ++/* Module ID */ ++#define I2C_ID_ID_MASK 0x0000FF00 ++/* field offset */ ++#define I2C_ID_ID_OFFSET 8 ++/* Revision */ ++#define I2C_ID_REV_MASK 0x000000FF ++/* field offset */ ++#define I2C_ID_REV_OFFSET 0 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/* Enable */ ++#define I2C_IMSC_BREQ_INT_EN 0x00000008 ++/* Enable */ ++#define I2C_IMSC_LBREQ_INT_EN 0x00000004 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/* field offset */ ++#define I2C_FDIV_CFG_INC_OFFSET 16 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/* Enable */ ++#define I2C_IMSC_I2C_P_INT_EN 0x00000020 ++/* Enable */ ++#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 ++ ++/* Fields of "I2C Error Interrupt Request Source Status Register" */ ++/* TXF_OFL */ ++#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 ++/* TXF_UFL */ ++#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 ++/* RXF_OFL */ ++#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 ++/* RXF_UFL */ ++#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 ++ ++/* Fields of "I2C Raw Interrupt Status Register" */ ++/* Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 ++/* Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/* TX FIFO Flow Control */ ++#define I2C_FIFO_CFG_TXFC 0x00020000 ++/* RX FIFO Flow Control */ ++#define I2C_FIFO_CFG_RXFC 0x00010000 ++/* Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 ++/* Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 ++/* 1 word */ ++#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/* 1 word */ ++#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 ++/* Stop on Packet End Enable */ ++#define I2C_ADDR_CFG_SOPE_EN 0x00200000 ++/* Stop on Not Acknowledge Enable */ ++#define I2C_ADDR_CFG_SONA_EN 0x00100000 ++/* Enable */ ++#define I2C_ADDR_CFG_MnS_EN 0x00080000 ++ ++/* Fields of "I2C Interrupt Clear Register" */ ++/* Clear */ ++#define I2C_ICR_BREQ_INT_CLR 0x00000008 ++/* Clear */ ++#define I2C_ICR_LBREQ_INT_CLR 0x00000004 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/* field offset */ ++#define I2C_FDIV_CFG_DEC_OFFSET 0 ++ ++/* Fields of "I2C Bus Status Register" */ ++/* Bus Status */ ++#define I2C_BUS_STAT_BS_MASK 0x00000003 ++/* Read from I2C Bus. */ ++#define I2C_BUS_STAT_RNW_READ 0x00000004 ++/* I2C Bus is free. */ ++#define I2C_BUS_STAT_BS_FREE 0x00000000 ++/* ++ * The device is working as master and has claimed the control on the ++ * I2C-bus (busy master). ++ */ ++#define I2C_BUS_STAT_BS_BM 0x00000002 ++ ++/* Fields of "I2C RUN Control Register" */ ++/* Enable */ ++#define I2C_RUN_CTRL_RUN_EN 0x00000001 ++ ++/* Fields of "I2C End Data Control Register" */ ++/* ++ * Set End of Transmission ++ * Note:Do not write '1' to this bit when bus is free. This will cause an ++ * abort after the first byte when a new transfer is started. ++ */ ++#define I2C_ENDD_CTRL_SETEND 0x00000002 ++ ++/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ ++/* NACK */ ++#define I2C_P_IRQSS_NACK 0x00000010 ++/* AL */ ++#define I2C_P_IRQSS_AL 0x00000008 ++/* RX */ ++#define I2C_P_IRQSS_RX 0x00000040 ++/* TX_END */ ++#define I2C_P_IRQSS_TX_END 0x00000020 ++ ++ ++#endif /* I2C_LANTIQ_H */ diff --git a/target/linux/lantiq/patches-5.15/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-5.15/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch new file mode 100644 index 0000000000..c80045e878 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch @@ -0,0 +1,218 @@ +From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 10 Sep 2014 22:42:14 +0200 +Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling + +Signed-off-by: John Crispin +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + + arch/mips/lantiq/xway/Makefile | 3 + + arch/mips/lantiq/xway/ath5k_eep.c | 136 +++++++++++++++++++++ + arch/mips/lantiq/xway/eth_mac.c | 25 ++++ + drivers/net/ethernet/lantiq_etop.c | 6 +- + 5 files changed, 172 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c + create mode 100644 arch/mips/lantiq/xway/eth_mac.c + +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -102,5 +102,8 @@ int xrx200_gphy_boot(struct device *dev, + extern void ltq_pmu_enable(unsigned int module); + extern void ltq_pmu_disable(unsigned int module); + ++/* allow the ethernet driver to load a flash mapped mac addr */ ++const u8* ltq_get_eth_mac(void); ++ + #endif /* CONFIG_SOC_TYPE_XWAY */ + #endif /* _LTQ_XWAY_H__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -8,3 +8,6 @@ obj-y += timer.o + endif + + obj-y += vmmc.o ++ ++obj-y += eth_mac.o ++obj-$(CONFIG_PCI) += ath5k_eep.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/ath5k_eep.c +@@ -0,0 +1,136 @@ ++/* ++ * Copyright (C) 2011 Luca Olivetti ++ * Copyright (C) 2011 John Crispin ++ * Copyright (C) 2011 Andrej Vlašić ++ * Copyright (C) 2013 Álvaro Fernández Rojas ++ * Copyright (C) 2013 Daniel Gimpelevich ++ * Copyright (C) 2015 Vittorio Gambaletta ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); ++struct ath5k_platform_data ath5k_pdata; ++static u8 athxk_eeprom_mac[6]; ++ ++static int ath5k_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ dev->dev.platform_data = &ath5k_pdata; ++ return 0; ++} ++ ++static int ath5k_eep_load; ++int __init of_ath5k_eeprom_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node, *mtd_np = NULL; ++ int mac_offset; ++ u32 mac_inc = 0; ++ int i; ++ struct mtd_info *the_mtd; ++ size_t flash_readlen; ++ const __be32 *list; ++ const char *part; ++ phandle phandle; ++ ++ list = of_get_property(np, "ath,eep-flash", &i); ++ if (!list || (i != (2 * sizeof(*list)))) ++ return -ENODEV; ++ ++ phandle = be32_to_cpup(list++); ++ if (phandle) ++ mtd_np = of_find_node_by_phandle(phandle); ++ ++ if (!mtd_np) ++ return -ENODEV; ++ ++ part = of_get_property(mtd_np, "label", NULL); ++ if (!part) ++ part = mtd_np->name; ++ ++ the_mtd = get_mtd_device_nm(part); ++ if (IS_ERR(the_mtd)) ++ return -ENODEV; ++ ++ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL); ++ ++ i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1, ++ &flash_readlen, (void *) ath5k_pdata.eeprom_data); ++ ++ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) { ++ size_t mac_readlen; ++ mtd_read(the_mtd, mac_offset, 6, &mac_readlen, ++ (void *) athxk_eeprom_mac); ++ } ++ put_mtd_device(the_mtd); ++ ++ if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) { ++ dev_err(&pdev->dev, "failed to load eeprom from mtd\n"); ++ return -ENODEV; ++ } ++ ++ if (of_find_property(np, "ath,eep-swap", NULL)) ++ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++) ++ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]); ++ ++ if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac()) ++ ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac()); ++ ++ if (!is_valid_ether_addr(athxk_eeprom_mac)) { ++ dev_warn(&pdev->dev, "using random mac\n"); ++ random_ether_addr(athxk_eeprom_mac); ++ } ++ ++ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc)) ++ athxk_eeprom_mac[5] += mac_inc; ++ ++ ath5k_pdata.macaddr = athxk_eeprom_mac; ++ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init; ++ ++ dev_info(&pdev->dev, "loaded ath5k eeprom\n"); ++ ++ return 0; ++} ++ ++static struct of_device_id ath5k_eeprom_ids[] = { ++ { .compatible = "ath5k,eeprom" }, ++ { } ++}; ++ ++static struct platform_driver ath5k_eeprom_driver = { ++ .driver = { ++ .name = "ath5k,eeprom", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ath5k_eeprom_ids), ++ }, ++}; ++ ++static int __init of_ath5k_eeprom_init(void) ++{ ++ int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); ++ ++ if (ret) ++ ath5k_eep_load = 1; ++ ++ return ret; ++} ++ ++static int __init of_ath5k_eeprom_init_late(void) ++{ ++ if (!ath5k_eep_load) ++ return 0; ++ ++ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); ++} ++late_initcall(of_ath5k_eeprom_init_late); ++subsys_initcall(of_ath5k_eeprom_init); +--- /dev/null ++++ b/arch/mips/lantiq/xway/eth_mac.c +@@ -0,0 +1,25 @@ ++/* ++ * Copyright (C) 2012 John Crispin ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++static u8 eth_mac[6]; ++static int eth_mac_set; ++ ++const u8* ltq_get_eth_mac(void) ++{ ++ return eth_mac; ++} ++ ++static int __init setup_ethaddr(char *str) ++{ ++ eth_mac_set = mac_pton(str, eth_mac); ++ return !eth_mac_set; ++} ++early_param("ethaddr", setup_ethaddr); +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -757,7 +757,11 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_hw; + +- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); ++ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN); ++ ++ if (priv->mac && !is_valid_ether_addr(mac.sa_data)) ++ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); ++ + if (!is_valid_ether_addr(mac.sa_data)) { + pr_warn("etop: invalid MAC, using random\n"); + eth_random_addr(mac.sa_data); diff --git a/target/linux/lantiq/patches-5.15/0042-arch-mips-increase-io_space_limit.patch b/target/linux/lantiq/patches-5.15/0042-arch-mips-increase-io_space_limit.patch new file mode 100644 index 0000000000..c81222af57 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0042-arch-mips-increase-io_space_limit.patch @@ -0,0 +1,24 @@ +From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Jun 2016 13:12:20 +0200 +Subject: [PATCH] arch: mips: increase io_space_limit + +this value comes from x86 and breaks some pci devices + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/spaces.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + create mode 100644 arch/mips/include/asm/mach-lantiq/spaces.h + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/spaces.h +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef __ASM_MACH_LANTIQ_SPACES_H_ ++#define __ASM_MACH_LANTIQ_SPACES_H_ ++ ++#define IO_SPACE_LIMIT 0xffffffff ++ ++#include ++#endif diff --git a/target/linux/lantiq/patches-5.15/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch b/target/linux/lantiq/patches-5.15/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch new file mode 100644 index 0000000000..333a2e6377 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch @@ -0,0 +1,78 @@ +From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Fri, 6 Jan 2017 17:55:24 +0100 +Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs + +The size of the internal RAM of the DesignWare USB controller changed +between the different Lantiq SoCs. We have the following sizes: + +Amazon + Danube: 8 KByte +Amazon SE + arx100: 2 KByte +xrx200 + xrx300: 2.5 KByte + +For Danube SoC we do not provide the params and let the driver decide +to use sane defaults, for the Amazon SE and arx100 we use small fifos +and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo. +The auto detection of max_transfer_size and max_packet_count should +work, so remove it. + +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++------- + 1 file changed, 39 insertions(+), 7 deletions(-) + +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -92,7 +92,14 @@ static void dwc2_set_rk_params(struct dw + p->power_down = DWC2_POWER_DOWN_PARAM_NONE; + } + +-static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) ++static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg) ++{ ++ struct dwc2_core_params *p = &hsotg->params; ++ ++ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; ++} ++ ++static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg) + { + struct dwc2_core_params *p = &hsotg->params; + +@@ -100,12 +107,20 @@ static void dwc2_set_ltq_params(struct d + p->host_rx_fifo_size = 288; + p->host_nperio_tx_fifo_size = 128; + p->host_perio_tx_fifo_size = 96; +- p->max_transfer_size = 65535; +- p->max_packet_count = 511; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << + GAHBCFG_HBSTLEN_SHIFT; + } + ++static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg) ++{ ++ struct dwc2_core_params *p = &hsotg->params; ++ ++ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; ++ p->host_rx_fifo_size = 288; ++ p->host_nperio_tx_fifo_size = 128; ++ p->host_perio_tx_fifo_size = 136; ++} ++ + static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) + { + struct dwc2_core_params *p = &hsotg->params; +@@ -196,8 +211,11 @@ const struct of_device_id dwc2_of_match_ + { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, + { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, + { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, +- { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, +- { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, ++ { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params }, ++ { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params }, ++ { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params }, ++ { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params }, ++ { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params }, + { .compatible = "snps,dwc2" }, + { .compatible = "samsung,s3c6400-hsotg", + .data = dwc2_set_s3c6400_params }, diff --git a/target/linux/lantiq/patches-5.15/0051-MIPS-lantiq-improve-USB-initialization.patch b/target/linux/lantiq/patches-5.15/0051-MIPS-lantiq-improve-USB-initialization.patch new file mode 100644 index 0000000000..9d62892b56 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0051-MIPS-lantiq-improve-USB-initialization.patch @@ -0,0 +1,49 @@ +From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Fri, 6 Jan 2017 17:40:12 +0100 +Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization + +This adds code to initialize the USB controller and PHY also on Danube, +Amazon SE and AR10. This code is based on the Vendor driver from +different UGW versions and compared to the hardware documentation. + +Signed-off-by: Hauke Mehrtens +--- + arch/mips/lantiq/xway/sysctrl.c | 20 +++++++ + 2 files changed, 110 insertions(+), 30 deletions(-) + + +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -248,6 +248,25 @@ static void pmu_disable(struct clk *clk) + pr_warn("deactivating PMU module failed!"); + } + ++static void usb_set_clock(void) ++{ ++ unsigned int val = ltq_cgu_r32(ifccr); ++ ++ if (of_machine_is_compatible("lantiq,ar10") || ++ of_machine_is_compatible("lantiq,grx390")) { ++ val &= ~0x03; /* XTAL divided by 3 */ ++ } else if (of_machine_is_compatible("lantiq,ar9") || ++ of_machine_is_compatible("lantiq,vr9")) { ++ /* TODO: this depends on the XTAL frequency */ ++ val |= 0x03; /* XTAL divided by 3 */ ++ } else if (of_machine_is_compatible("lantiq,ase")) { ++ val |= 0x20; /* from XTAL */ ++ } else if (of_machine_is_compatible("lantiq,danube")) { ++ val |= 0x30; /* 12 MHz, generated from 36 MHz */ ++ } ++ ltq_cgu_w32(val, ifccr); ++} ++ + /* the pci enable helper */ + static int pci_enable(struct clk *clk) + { +@@ -585,4 +604,5 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); + clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); + } ++ usb_set_clock(); + } diff --git a/target/linux/lantiq/patches-5.15/0101-find_active_root.patch b/target/linux/lantiq/patches-5.15/0101-find_active_root.patch new file mode 100644 index 0000000000..925ac9dbba --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0101-find_active_root.patch @@ -0,0 +1,93 @@ +--- a/drivers/mtd/parsers/ofpart_core.c ++++ b/drivers/mtd/parsers/ofpart_core.c +@@ -38,6 +38,38 @@ static bool node_has_compatible(struct d + return of_get_property(pp, "compatible", NULL); + } + ++static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master, ++ loff_t offset) ++{ ++ static uint8_t root_id; ++ int err, len; ++ ++ err = mtd_read(master, offset, 0x01, &len, &root_id); ++ ++ if (mtd_is_bitflip(err) || !err) ++ return &root_id; ++ ++ return NULL; ++} ++ ++static void brnboot_set_active_root_part(struct mtd_partition *pparts, ++ struct device_node **part_nodes, ++ int nr_parts, ++ uint8_t *root_id) ++{ ++ int i; ++ ++ for (i = 0; i < nr_parts; i++) { ++ int part_root_id; ++ ++ if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id) ++ && part_root_id == *root_id) { ++ pparts[i].name = "firmware"; ++ break; ++ } ++ } ++} ++ + static int parse_fixed_partitions(struct mtd_info *master, + const struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +@@ -51,6 +83,8 @@ static int parse_fixed_partitions(struct + struct device_node *pp; + int nr_parts, i, ret = 0; + bool dedicated = true; ++ uint8_t *proot_id = NULL; ++ struct device_node **part_nodes; + + /* Pull of_node from the master device node */ + mtd_node = mtd_get_of_node(master); +@@ -95,7 +129,9 @@ static int parse_fixed_partitions(struct + return 0; + + parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); +- if (!parts) ++ part_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL); ++ ++ if (!parts || !part_nodes) + return -ENOMEM; + + i = 0; +@@ -147,6 +183,11 @@ static int parse_fixed_partitions(struct + if (of_property_read_bool(pp, "slc-mode")) + parts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION; + ++ if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector")) ++ proot_id = brnboot_get_selected_root_part(master, parts[i].offset); ++ ++ part_nodes[i] = pp; ++ + i++; + } + +@@ -156,6 +197,11 @@ static int parse_fixed_partitions(struct + if (quirks && quirks->post_parse) + quirks->post_parse(master, parts, nr_parts); + ++ if (proot_id) ++ brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id); ++ ++ kfree(part_nodes); ++ + *pparts = parts; + return nr_parts; + +@@ -166,6 +212,7 @@ ofpart_fail: + ofpart_none: + of_node_put(pp); + kfree(parts); ++ kfree(part_nodes); + return ret; + } + diff --git a/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch new file mode 100644 index 0000000000..10633199e6 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch @@ -0,0 +1,387 @@ +--- a/arch/mips/pci/ifxmips_pcie.c ++++ b/arch/mips/pci/ifxmips_pcie.c +@@ -16,8 +16,15 @@ + #include + #include + #include ++#include ++#include ++#include ++#include + #include + ++#include ++#include ++ + #include "ifxmips_pcie.h" + #include "ifxmips_pcie_reg.h" + +@@ -40,6 +47,10 @@ + static DEFINE_SPINLOCK(ifx_pcie_lock); + + u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); ++static int pcie_reset_gpio; ++static struct phy *ltq_pcie_phy; ++static struct reset_control *ltq_pcie_reset; ++static struct regmap *ltq_rcu_regmap; + + static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { + { +@@ -82,6 +93,22 @@ void ifx_pcie_debug(const char *fmt, ... + printk("%s", buf); + } + ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ gpio_direction_output(pcie_reset_gpio, 1); ++ gpio_set_value(pcie_reset_gpio, 1); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ gpio_set_value(pcie_reset_gpio, 0); ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ gpio_direction_output(pcie_reset_gpio, 1); ++} + + static inline int pcie_ltssm_enable(int pcie_port) + { +@@ -988,10 +1015,22 @@ int ifx_pcie_bios_plat_dev_init(struct + static int + pcie_rc_initialize(int pcie_port) + { +- int i; ++ int i, ret; + #define IFX_PCIE_PHY_LOOP_CNT 5 + +- pcie_rcu_endian_setup(pcie_port); ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_M, ++ IFX_RCU_AHB_BE_PCIE_M); ++ ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S, ++ IFX_RCU_AHB_BE_PCIE_S); ++#else ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S, ++ 0x0); ++#endif ++ ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_M, ++ 0x0); + + pcie_ep_gpio_rst_init(pcie_port); + +@@ -1000,26 +1039,21 @@ pcie_rc_initialize(int pcie_port) + * reset PCIe PHY will solve this issue + */ + for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { +- /* Disable PCIe PHY Analog part for sanity check */ +- pcie_phy_pmu_disable(pcie_port); +- +- pcie_phy_rst_assert(pcie_port); +- pcie_phy_rst_deassert(pcie_port); +- +- /* Make sure PHY PLL is stable */ +- udelay(20); +- +- /* PCIe Core reset enabled, low active, sw programmed */ +- pcie_core_rst_assert(pcie_port); ++ ret = phy_init(ltq_pcie_phy); ++ if (ret) ++ continue; + + /* Put PCIe EP in reset status */ + pcie_device_rst_assert(pcie_port); + +- /* PCI PHY & Core reset disabled, high active, sw programmed */ +- pcie_core_rst_deassert(pcie_port); ++ udelay(1); ++ reset_control_deassert(ltq_pcie_reset); + +- /* Already in a quiet state, program PLL, enable PHY, check ready bit */ +- pcie_phy_clock_mode_setup(pcie_port); ++ ret = phy_power_on(ltq_pcie_phy); ++ if (ret) { ++ phy_exit(ltq_pcie_phy); ++ continue; ++ } + + /* Enable PCIe PHY and Clock */ + pcie_core_pmu_setup(pcie_port); +@@ -1035,6 +1069,10 @@ pcie_rc_initialize(int pcie_port) + /* Once link is up, break out */ + if (pcie_app_loigc_setup(pcie_port) == 0) + break; ++ ++ phy_power_off(ltq_pcie_phy); ++ reset_control_assert(ltq_pcie_reset); ++ phy_exit(ltq_pcie_phy); + } + if (i >= IFX_PCIE_PHY_LOOP_CNT) { + printk(KERN_ERR "%s link up failed!!!!!\n", __func__); +@@ -1045,17 +1083,67 @@ pcie_rc_initialize(int pcie_port) + return 0; + } + +-static int __init ifx_pcie_bios_init(void) ++static int ifx_pcie_bios_probe(struct platform_device *pdev) + { ++ struct device_node *node = pdev->dev.of_node; + void __iomem *io_map_base; + int pcie_port; + int startup_port; ++ struct device_node *np; ++ struct pci_bus *bus; ++ ++ /* ++ * In case a PCI device is physical present, the Lantiq PCI driver need ++ * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them ++ * will work. ++ * ++ * In case the lantiq PCI driver is enabled in the device tree, check if ++ * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already ++ * registered. ++ * ++ * It will fail if there is another PCI controller, this controller is ++ * registered before the Lantiq PCIe driver is probe and the lantiq PCI ++ */ ++ np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway"); ++ ++ if (of_device_is_available(np)) { ++ bus = pci_find_next_bus(bus); ++ ++ if (!bus) ++ return -EPROBE_DEFER; ++ } + + /* Enable AHB Master/ Slave */ + pcie_ahb_pmu_setup(); + + startup_port = IFX_PCIE_PORT0; +- ++ ++ ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie"); ++ if (IS_ERR(ltq_pcie_phy)) { ++ dev_err(&pdev->dev, "failed to get the PCIe PHY\n"); ++ return PTR_ERR(ltq_pcie_phy); ++ } ++ ++ ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL); ++ if (IS_ERR(ltq_pcie_reset)) { ++ dev_err(&pdev->dev, "failed to get the PCIe reset line\n"); ++ return PTR_ERR(ltq_pcie_reset); ++ } ++ ++ ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu"); ++ if (IS_ERR(ltq_rcu_regmap)) ++ return PTR_ERR(ltq_rcu_regmap); ++ ++ pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); ++ if (gpio_is_valid(pcie_reset_gpio)) { ++ int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset"); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio); ++ return ret; ++ } ++ gpio_direction_output(pcie_reset_gpio, 1); ++ } ++ + for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ + if (pcie_rc_initialize(pcie_port) == 0) { + IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", +@@ -1067,6 +1155,7 @@ static int __init ifx_pcie_bios_init(voi + return -ENOMEM; + } + ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; ++ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node); + + register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); + /* XXX, clear error status */ +@@ -1083,6 +1172,30 @@ static int __init ifx_pcie_bios_init(voi + + return 0; + } ++ ++static const struct of_device_id ifxmips_pcie_match[] = { ++ { .compatible = "lantiq,pcie-xrx200" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ifxmips_pcie_match); ++ ++static struct platform_driver ltq_pci_driver = { ++ .probe = ifx_pcie_bios_probe, ++ .driver = { ++ .name = "pcie-xrx200", ++ .owner = THIS_MODULE, ++ .of_match_table = ifxmips_pcie_match, ++ }, ++}; ++ ++int __init ifx_pcie_bios_init(void) ++{ ++ int ret = platform_driver_register(<q_pci_driver); ++ if (ret) ++ pr_info("pcie-xrx200: Error registering platform driver!"); ++ return ret; ++} ++ + arch_initcall(ifx_pcie_bios_init); + + MODULE_LICENSE("GPL"); +--- a/arch/mips/pci/ifxmips_pcie_vr9.h ++++ b/arch/mips/pci/ifxmips_pcie_vr9.h +@@ -22,8 +22,6 @@ + #include + #include + +-#define IFX_PCIE_GPIO_RESET 494 +- + #define IFX_REG_R32 ltq_r32 + #define IFX_REG_W32 ltq_w32 + #define CONFIG_IFX_PCIE_HW_SWAP +@@ -53,21 +51,6 @@ + #define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) + + +-static inline void pcie_ep_gpio_rst_init(int pcie_port) +-{ +- +- gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); +- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); +- gpio_set_value(IFX_PCIE_GPIO_RESET, 1); +- +-/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ +-} +- + static inline void pcie_ahb_pmu_setup(void) + { + /* Enable AHB bus master/slave */ +@@ -79,24 +62,6 @@ static inline void pcie_ahb_pmu_setup(vo + //AHBS_PMU_SETUP(IFX_PMU_ENABLE); + } + +-static inline void pcie_rcu_endian_setup(int pcie_port) +-{ +- u32 reg; +- +- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); +-#ifdef CONFIG_IFX_PCIE_HW_SWAP +- reg |= IFX_RCU_AHB_BE_PCIE_M; +- reg |= IFX_RCU_AHB_BE_PCIE_S; +- reg &= ~IFX_RCU_AHB_BE_XBAR_M; +-#else +- reg |= IFX_RCU_AHB_BE_PCIE_M; +- reg &= ~IFX_RCU_AHB_BE_PCIE_S; +- reg &= ~IFX_RCU_AHB_BE_XBAR_M; +-#endif /* CONFIG_IFX_PCIE_HW_SWAP */ +- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); +- IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); +-} +- + static inline void pcie_phy_pmu_enable(int pcie_port) + { + struct clk *clk; +@@ -115,17 +80,6 @@ static inline void pcie_phy_pmu_disable( + // PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); + } + +-static inline void pcie_pdi_big_endian(int pcie_port) +-{ +- u32 reg; +- +- /* SRAM2PDI endianness control. */ +- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); +- /* Config AHB->PCIe and PDI endianness */ +- reg |= IFX_RCU_AHB_BE_PCIE_PDI; +- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); +-} +- + static inline void pcie_pdi_pmu_enable(int pcie_port) + { + /* Enable PDI to access PCIe PHY register */ +@@ -135,65 +89,6 @@ static inline void pcie_pdi_pmu_enable(i + //PDI_PMU_SETUP(IFX_PMU_ENABLE); + } + +-static inline void pcie_core_rst_assert(int pcie_port) +-{ +- u32 reg; +- +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- +- /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ +- reg |= 0x00400000; +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_core_rst_deassert(int pcie_port) +-{ +- u32 reg; +- +- /* Make sure one micro-second delay */ +- udelay(1); +- +- /* Reset PCIe PHY & Core, bit 22 */ +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- reg &= ~0x00400000; +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_phy_rst_assert(int pcie_port) +-{ +- u32 reg; +- +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- reg |= 0x00001000; /* Bit 12 */ +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_phy_rst_deassert(int pcie_port) +-{ +- u32 reg; +- +- /* Make sure one micro-second delay */ +- udelay(1); +- +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- reg &= ~0x00001000; /* Bit 12 */ +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_device_rst_assert(int pcie_port) +-{ +- gpio_set_value(IFX_PCIE_GPIO_RESET, 0); +-// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +-} +- +-static inline void pcie_device_rst_deassert(int pcie_port) +-{ +- mdelay(100); +- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); +-// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); +- //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +-} +- + static inline void pcie_core_pmu_setup(int pcie_port) + { + struct clk *clk; +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -43,7 +43,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o + obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o + obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o +-obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o ++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie.o fixup-lantiq-pcie.o + obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o + obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o + obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o diff --git a/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch new file mode 100644 index 0000000000..71e9886d2e --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch @@ -0,0 +1,180 @@ +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -2434,6 +2434,12 @@ config MIPS_VPE_LOADER + Includes a loader for loading an elf relocatable object + onto another VPE and running it. + ++config IFX_VPE_EXT ++ bool "IFX APRP Extensions" ++ depends on MIPS_VPE_LOADER ++ help ++ IFX included extensions in APRP ++ + config MIPS_VPE_LOADER_CMP + bool + default "y" +--- a/arch/mips/include/asm/vpe.h ++++ b/arch/mips/include/asm/vpe.h +@@ -127,4 +127,13 @@ void cleanup_tc(struct tc *tc); + + int __init vpe_module_init(void); + void __exit vpe_module_exit(void); ++ ++/* For the explanation of the APIs please refer the section "MT APRP Kernel ++ * Programming" in AR9 SW Architecture Specification ++ */ ++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags); ++int32_t vpe1_sw_stop(uint32_t flags); ++uint32_t vpe1_get_load_addr(uint32_t flags); ++uint32_t vpe1_get_max_mem(uint32_t flags); ++ + #endif /* _ASM_VPE_H */ +--- a/arch/mips/kernel/vpe-mt.c ++++ b/arch/mips/kernel/vpe-mt.c +@@ -29,6 +29,7 @@ int vpe_run(struct vpe *v) + struct vpe_notifications *notifier; + unsigned int vpeflags; + struct tc *t; ++ unsigned long physical_memsize = 0L; + + /* check we are the Master VPE */ + local_irq_save(flags); +@@ -417,6 +418,8 @@ int __init vpe_module_init(void) + } + + v->ntcs = hw_tcs - aprp_cpu_index(); ++ write_tc_c0_tcbind((read_tc_c0_tcbind() & ++ ~TCBIND_CURVPE) | 1); + + /* add the tc to the list of this vpe's tc's. */ + list_add(&t->tc, &v->tc); +@@ -519,3 +522,47 @@ void __exit vpe_module_exit(void) + release_vpe(v); + } + } ++ ++#ifdef CONFIG_IFX_VPE_EXT ++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags) ++{ ++ enum vpe_state state; ++ struct vpe *v = get_vpe(tclimit); ++ struct vpe_notifications *not; ++ ++ if (tcmask || flags) { ++ pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n"); ++ return -1; ++ } ++ ++ state = xchg(&v->state, VPE_STATE_INUSE); ++ if (state != VPE_STATE_UNUSED) { ++ vpe_stop(v); ++ ++ list_for_each_entry(not, &v->notify, list) { ++ not->stop(tclimit); ++ } ++ } ++ ++ v->__start = (unsigned long)sw_start_addr; ++ ++ if (!vpe_run(v)) { ++ pr_debug("VPE loader: VPE1 running successfully\n"); ++ return 0; ++ } ++ return -1; ++} ++EXPORT_SYMBOL(vpe1_sw_start); ++ ++int32_t vpe1_sw_stop(uint32_t flags) ++{ ++ struct vpe *v = get_vpe(tclimit); ++ ++ if (!vpe_free(v)) { ++ pr_debug("RP Stopped\n"); ++ return 0; ++ } else ++ return -1; ++} ++EXPORT_SYMBOL(vpe1_sw_stop); ++#endif +--- a/arch/mips/kernel/vpe.c ++++ b/arch/mips/kernel/vpe.c +@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = { + .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) + }; + ++#ifdef CONFIG_IFX_VPE_EXT ++unsigned int vpe1_load_addr; ++ ++static int __init load_address(char *str) ++{ ++ get_option(&str, &vpe1_load_addr); ++ return 1; ++} ++__setup("vpe1_load_addr=", load_address); ++ ++static unsigned int vpe1_mem; ++static int __init vpe1mem(char *str) ++{ ++ vpe1_mem = memparse(str, &str); ++ return 1; ++} ++__setup("vpe1_mem=", vpe1mem); ++ ++uint32_t vpe1_get_load_addr(uint32_t flags) ++{ ++ return vpe1_load_addr; ++} ++EXPORT_SYMBOL(vpe1_get_load_addr); ++ ++uint32_t vpe1_get_max_mem(uint32_t flags) ++{ ++ if (!vpe1_mem) ++ return P_SIZE; ++ else ++ return vpe1_mem; ++} ++EXPORT_SYMBOL(vpe1_get_max_mem); ++ ++#endif ++ + /* get the vpe associated with this minor */ + struct vpe *get_vpe(int minor) + { +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -34,10 +34,14 @@ unsigned long physical_memsize = 0L; + */ + static struct ltq_soc_info soc_info; + ++/* for Multithreading (APRP), vpe.c will use it */ ++unsigned long cp0_memsize; ++ + const char *get_system_type(void) + { + return soc_info.sys_type; + } ++EXPORT_SYMBOL(ltq_soc_type); + + int ltq_soc_type(void) + { +--- a/arch/mips/include/asm/mipsmtregs.h ++++ b/arch/mips/include/asm/mipsmtregs.h +@@ -32,6 +32,9 @@ + #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) + #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) + ++#define read_c0_vpeopt() __read_32bit_c0_register($1, 7) ++#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val) ++ + #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) + #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) + +@@ -378,6 +381,8 @@ do { \ + #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) + #define read_vpe_c0_vpeconf1() mftc0(1, 3) + #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) ++#define read_vpe_c0_vpeopt() mftc0(1, 7) ++#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val) + #define read_vpe_c0_count() mftc0(9, 0) + #define write_vpe_c0_count(val) mttc0(9, 0, val) + #define read_vpe_c0_status() mftc0(12, 0) diff --git a/target/linux/lantiq/patches-5.15/0154-lantiq-pci-bar11mask-fix.patch b/target/linux/lantiq/patches-5.15/0154-lantiq-pci-bar11mask-fix.patch new file mode 100644 index 0000000000..d6556d115d --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0154-lantiq-pci-bar11mask-fix.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/pci/pci-lantiq.c ++++ b/arch/mips/pci/pci-lantiq.c +@@ -59,6 +59,8 @@ + #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) + #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) + ++extern u32 max_low_pfn; ++ + __iomem void *ltq_pci_mapped_cfg; + static __iomem void *ltq_pci_membase; + +@@ -84,8 +86,8 @@ static inline u32 ltq_calc_bar11mask(voi + u32 mem, bar11mask; + + /* BAR11MASK value depends on available memory on system. */ +- mem = get_num_physpages() * PAGE_SIZE; +- bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; ++ mem = max_low_pfn << PAGE_SHIFT; ++ bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8; + + return bar11mask; + } diff --git a/target/linux/lantiq/patches-5.15/0155-lantiq-VPE-nosmp.patch b/target/linux/lantiq/patches-5.15/0155-lantiq-VPE-nosmp.patch new file mode 100644 index 0000000000..898c2d4821 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0155-lantiq-VPE-nosmp.patch @@ -0,0 +1,14 @@ +--- a/arch/mips/kernel/vpe-mt.c ++++ b/arch/mips/kernel/vpe-mt.c +@@ -132,7 +132,10 @@ int vpe_run(struct vpe *v) + * kernels need to turn it on, even if that wasn't the pre-dvpe() state. + */ + #ifdef CONFIG_SMP +- evpe(vpeflags); ++ if (!setup_max_cpus) /* nosmp is set */ ++ evpe(EVPE_ENABLE); ++ else ++ evpe(vpeflags); + #else + evpe(EVPE_ENABLE); + #endif diff --git a/target/linux/lantiq/patches-5.15/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-5.15/0160-owrt-lantiq-multiple-flash.patch new file mode 100644 index 0000000000..796220b2bc --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0160-owrt-lantiq-multiple-flash.patch @@ -0,0 +1,220 @@ +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -36,13 +37,16 @@ enum { + LTQ_NOR_NORMAL + }; + ++#define MAX_RESOURCES 4 ++ + struct ltq_mtd { +- struct resource *res; +- struct mtd_info *mtd; +- struct map_info *map; ++ struct mtd_info *mtd[MAX_RESOURCES]; ++ struct mtd_info *cmtd; ++ struct map_info map[MAX_RESOURCES]; + }; + + static const char ltq_map_name[] = "ltq_nor"; ++static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL }; + + static map_word + ltq_read16(struct map_info *map, unsigned long adr) +@@ -106,11 +110,43 @@ ltq_copy_to(struct map_info *map, unsign + } + + static int ++ltq_mtd_remove(struct platform_device *pdev) ++{ ++ struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); ++ int i; ++ ++ if (ltq_mtd == NULL) ++ return 0; ++ ++ if (ltq_mtd->cmtd) { ++ mtd_device_unregister(ltq_mtd->cmtd); ++ if (ltq_mtd->cmtd != ltq_mtd->mtd[0]) ++ mtd_concat_destroy(ltq_mtd->cmtd); ++ } ++ ++ for (i = 0; i < MAX_RESOURCES; i++) { ++ if (ltq_mtd->mtd[i] != NULL) ++ map_destroy(ltq_mtd->mtd[i]); ++ } ++ ++ kfree(ltq_mtd); ++ ++ return 0; ++} ++ ++static int + ltq_mtd_probe(struct platform_device *pdev) + { + struct ltq_mtd *ltq_mtd; + struct cfi_private *cfi; +- int err; ++ int err = 0; ++ int i; ++ int devices_found = 0; ++ ++ static const char *rom_probe_types[] = { ++ "cfi_probe", "jedec_probe", NULL ++ }; ++ const char **type; + + ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL); + if (!ltq_mtd) +@@ -118,75 +154,89 @@ ltq_mtd_probe(struct platform_device *pd + + platform_set_drvdata(pdev, ltq_mtd); + +- ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!ltq_mtd->res) { +- dev_err(&pdev->dev, "failed to get memory resource\n"); +- return -ENOENT; ++ for (i = 0; i < pdev->num_resources; i++) { ++ printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n", ++ (unsigned long long)resource_size(&pdev->resource[i]), ++ (unsigned long long)pdev->resource[i].start); ++ ++ if (!devm_request_mem_region(&pdev->dev, ++ pdev->resource[i].start, ++ resource_size(&pdev->resource[i]), ++ dev_name(&pdev->dev))) { ++ dev_err(&pdev->dev, "Could not reserve memory region\n"); ++ return -ENOMEM; ++ } ++ ++ ltq_mtd->map[i].name = ltq_map_name; ++ ltq_mtd->map[i].bankwidth = 2; ++ ltq_mtd->map[i].read = ltq_read16; ++ ltq_mtd->map[i].write = ltq_write16; ++ ltq_mtd->map[i].copy_from = ltq_copy_from; ++ ltq_mtd->map[i].copy_to = ltq_copy_to; ++ ++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) ++ ltq_mtd->map[i].phys = NO_XIP; ++ else ++ ltq_mtd->map[i].phys = pdev->resource[i].start; ++ ltq_mtd->map[i].size = resource_size(&pdev->resource[i]); ++ ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start, ++ ltq_mtd->map[i].size); ++ if (IS_ERR(ltq_mtd->map[i].virt)) ++ return PTR_ERR(ltq_mtd->map[i].virt); ++ ++ if (ltq_mtd->map[i].virt == NULL) { ++ dev_err(&pdev->dev, "Failed to ioremap flash region\n"); ++ err = PTR_ERR(ltq_mtd->map[i].virt); ++ goto err_out; ++ } ++ ++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING; ++ for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++) ++ ltq_mtd->mtd[i] = do_map_probe(*type, <q_mtd->map[i]); ++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL; ++ ++ if (!ltq_mtd->mtd[i]) { ++ dev_err(&pdev->dev, "probing failed\n"); ++ return -ENXIO; ++ } else { ++ devices_found++; ++ } ++ ++ ltq_mtd->mtd[i]->owner = THIS_MODULE; ++ ltq_mtd->mtd[i]->dev.parent = &pdev->dev; ++ ++ cfi = ltq_mtd->map[i].fldrv_priv; ++ cfi->addr_unlock1 ^= 1; ++ cfi->addr_unlock2 ^= 1; + } + +- ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info), +- GFP_KERNEL); +- if (!ltq_mtd->map) +- return -ENOMEM; +- +- if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) +- ltq_mtd->map->phys = NO_XIP; +- else +- ltq_mtd->map->phys = ltq_mtd->res->start; +- ltq_mtd->res->start; +- ltq_mtd->map->size = resource_size(ltq_mtd->res); +- ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); +- if (IS_ERR(ltq_mtd->map->virt)) +- return PTR_ERR(ltq_mtd->map->virt); +- +- ltq_mtd->map->name = ltq_map_name; +- ltq_mtd->map->bankwidth = 2; +- ltq_mtd->map->read = ltq_read16; +- ltq_mtd->map->write = ltq_write16; +- ltq_mtd->map->copy_from = ltq_copy_from; +- ltq_mtd->map->copy_to = ltq_copy_to; +- +- ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING; +- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map); +- ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL; +- +- if (!ltq_mtd->mtd) { +- dev_err(&pdev->dev, "probing failed\n"); +- return -ENXIO; ++ if (devices_found == 1) { ++ ltq_mtd->cmtd = ltq_mtd->mtd[0]; ++ } else if (devices_found > 1) { ++ /* ++ * We detected multiple devices. Concatenate them together. ++ */ ++ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev)); ++ if (ltq_mtd->cmtd == NULL) ++ err = -ENXIO; + } + +- ltq_mtd->mtd->dev.parent = &pdev->dev; +- mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node); +- +- cfi = ltq_mtd->map->fldrv_priv; +- cfi->addr_unlock1 ^= 1; +- cfi->addr_unlock2 ^= 1; ++ ltq_mtd->cmtd->dev.parent = &pdev->dev; ++ mtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node); + +- err = mtd_device_register(ltq_mtd->mtd, NULL, 0); ++ err = mtd_device_register(ltq_mtd->cmtd, NULL, 0); + if (err) { + dev_err(&pdev->dev, "failed to add partitions\n"); +- goto err_destroy; ++ goto err_out; + } + + return 0; + +-err_destroy: +- map_destroy(ltq_mtd->mtd); ++err_out: ++ ltq_mtd_remove(pdev); + return err; + } + +-static int +-ltq_mtd_remove(struct platform_device *pdev) +-{ +- struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); +- +- if (ltq_mtd && ltq_mtd->mtd) { +- mtd_device_unregister(ltq_mtd->mtd); +- map_destroy(ltq_mtd->mtd); +- } +- return 0; +-} +- + static const struct of_device_id ltq_mtd_match[] = { + { .compatible = "lantiq,nor" }, + {}, diff --git a/target/linux/lantiq/patches-5.15/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-5.15/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch new file mode 100644 index 0000000000..d153c521d3 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0001.c ++++ b/drivers/mtd/chips/cfi_cmdset_0001.c +@@ -39,7 +39,7 @@ + /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ + + // debugging, turns off buffer write mode if set to 1 +-#define FORCE_WORD_WRITE 0 ++#define FORCE_WORD_WRITE 1 + + /* Intel chips */ + #define I82802AB 0x00ad diff --git a/target/linux/lantiq/patches-5.15/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-5.15/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch new file mode 100644 index 0000000000..92c4b56493 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch @@ -0,0 +1,30 @@ +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -440,6 +440,20 @@ static void clkdev_add_clkout(void) + } + } + ++static void set_phy_clock_source(struct device_node *np_cgu) ++{ ++ u32 phy_clk_src, ifcc; ++ ++ if (!np_cgu) ++ return; ++ ++ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) ++ return; ++ ++ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); ++ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); ++} ++ + /* bring up all register ranges that we need for basic system control */ + void __init ltq_soc_init(void) + { +@@ -605,4 +619,6 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); + } + usb_set_clock(); ++ ++ set_phy_clock_source(np_cgu); + } diff --git a/target/linux/lantiq/patches-5.15/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch b/target/linux/lantiq/patches-5.15/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch new file mode 100644 index 0000000000..33c06e9d77 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch @@ -0,0 +1,86 @@ +From 49293bbc50cb7d44223eb49e0f7cb38e7dac2361 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 14 Sep 2021 23:21:01 +0200 +Subject: [PATCH 4/5] MIPS: lantiq: dma: make the burst length configurable by + the drivers + +Make the burst length configurable by the drivers. + +Signed-off-by: Aleksander Jan Bajkowski +Acked-by: Hauke Mehrtens +Signed-off-by: David S. Miller +--- + .../include/asm/mach-lantiq/xway/xway_dma.h | 2 +- + arch/mips/lantiq/xway/dma.c | 38 ++++++++++++++++--- + 2 files changed, 34 insertions(+), 6 deletions(-) + +--- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h +@@ -45,6 +45,6 @@ extern void ltq_dma_close(struct ltq_dma + extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch); + extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch); + extern void ltq_dma_free(struct ltq_dma_channel *ch); +-extern void ltq_dma_init_port(int p); ++extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst); + + #endif +--- a/arch/mips/lantiq/xway/dma.c ++++ b/arch/mips/lantiq/xway/dma.c +@@ -181,7 +181,7 @@ ltq_dma_free(struct ltq_dma_channel *ch) + EXPORT_SYMBOL_GPL(ltq_dma_free); + + void +-ltq_dma_init_port(int p) ++ltq_dma_init_port(int p, int tx_burst, int rx_burst) + { + ltq_dma_w32(p, LTQ_DMA_PS); + switch (p) { +@@ -190,16 +190,44 @@ ltq_dma_init_port(int p) + * Tell the DMA engine to swap the endianness of data frames and + * drop packets if the channel arbitration fails. + */ +- ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN, ++ ltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN), + LTQ_DMA_PCTRL); + break; + +- case DMA_PORT_DEU: +- ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) | +- (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT), ++ default: ++ break; ++ } ++ ++ switch (rx_burst) { ++ case 8: ++ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT), + LTQ_DMA_PCTRL); + break; ++ case 4: ++ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT), ++ LTQ_DMA_PCTRL); ++ break; ++ case 2: ++ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT), ++ LTQ_DMA_PCTRL); ++ break; ++ default: ++ break; ++ } + ++ switch (tx_burst) { ++ case 8: ++ ltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT), ++ LTQ_DMA_PCTRL); ++ break; ++ case 4: ++ ltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT), ++ LTQ_DMA_PCTRL); ++ break; ++ case 2: ++ ltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT), ++ LTQ_DMA_PCTRL); ++ break; + default: + break; + } diff --git a/target/linux/lantiq/patches-5.15/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch b/target/linux/lantiq/patches-5.15/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch new file mode 100644 index 0000000000..0ac9adfb96 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch @@ -0,0 +1,86 @@ +From 2025bc9c3a949b65bfd0601f727678b37962c6c5 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Fri, 4 Jun 2021 18:27:58 +0200 +Subject: [PATCH] MIPS: lantiq: enable all hardware interrupts on second VPE + +This patch is needed to handle interrupts by the second VPE on the Lantiq +ARX100, xRX200, xRX300 and xRX330 SoCs. Switching some ICU interrupts to +the second VPE results in a hang. Currently, the vsmp_init_secondary() +function is responsible for enabling these interrupts. It only enables +Malta-specific interrupts (SW0, SW1, HW4 and HW5). + +The MIPS core has 8 interrupts defined. On Lantiq SoCs, hardware +interrupts are wired to an ICU instance. Each VPE has an independent +instance of the ICU. The mapping of the ICU interrupts is shown below: +SW0(IP0) - IPI call, +SW1(IP1) - IPI resched, +HW0(IP2) - ICU 0-31, +HW1(IP3) - ICU 32-63, +HW2(IP4) - ICU 64-95, +HW3(IP5) - ICU 96-127, +HW4(IP6) - ICU 128-159, +HW5(IP7) - timer. + +This patch enables all interrupt lines on the second VPE. + +This problem affects multithreaded SoCs with a custom interrupt controller. +SOCs with 1004Kc core and newer use the MIPS GIC. At this point, I am aware +that the Realtek RTL839x and RTL930x SoCs may need a similar fix. In the +future, this may be replaced with some generic solution. + +Tested on Lantiq xRX200. + +Suggested-by: Thomas Bogendoerfer +Signed-off-by: Aleksander Jan Bajkowski +--- + arch/mips/lantiq/prom.c | 26 ++++++++++++++++++++++++-- + 1 file changed, 24 insertions(+), 2 deletions(-) + +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -37,6 +37,14 @@ static struct ltq_soc_info soc_info; + /* for Multithreading (APRP), vpe.c will use it */ + unsigned long cp0_memsize; + ++/* ++ * These structs are used to override vsmp_init_secondary() ++ */ ++#if defined(CONFIG_MIPS_MT_SMP) ++extern const struct plat_smp_ops vsmp_smp_ops; ++static struct plat_smp_ops lantiq_smp_ops; ++#endif ++ + const char *get_system_type(void) + { + return soc_info.sys_type; +@@ -100,6 +108,17 @@ void __init device_tree_init(void) + unflatten_and_copy_device_tree(); + } + ++#if defined(CONFIG_MIPS_MT_SMP) ++static void lantiq_init_secondary(void) ++{ ++ /* ++ * MIPS CPU startup function vsmp_init_secondary() will only ++ * enable some of the interrupts for the second CPU/VPE. ++ */ ++ set_c0_status(ST0_IM); ++} ++#endif ++ + void __init prom_init(void) + { + /* call the soc specific detetcion code and get it to fill soc_info */ +@@ -111,7 +130,10 @@ void __init prom_init(void) + prom_init_cmdline(); + + #if defined(CONFIG_MIPS_MT_SMP) +- if (register_vsmp_smp_ops()) +- panic("failed to register_vsmp_smp_ops()"); ++ if (cpu_has_mipsmt) { ++ lantiq_smp_ops = vsmp_smp_ops; ++ lantiq_smp_ops.init_secondary = lantiq_init_secondary; ++ register_smp_ops(&lantiq_smp_ops); ++ } + #endif + } diff --git a/target/linux/lantiq/patches-5.15/0701-NET-lantiq-etop-of-mido.patch b/target/linux/lantiq/patches-5.15/0701-NET-lantiq-etop-of-mido.patch new file mode 100644 index 0000000000..2cc541ae3c --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0701-NET-lantiq-etop-of-mido.patch @@ -0,0 +1,37 @@ +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -30,6 +30,7 @@ + #include + #include + #include ++#include + + #include + +@@ -553,7 +554,8 @@ static int + ltq_etop_mdio_init(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int err; ++ struct device_node *mdio_np = NULL; ++ int err, ret; + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { +@@ -573,7 +575,15 @@ ltq_etop_mdio_init(struct net_device *de + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + priv->pdev->name, priv->pdev->id); +- if (mdiobus_register(priv->mii_bus)) { ++ ++ mdio_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus"); ++ ++ if (mdio_np) ++ ret = of_mdiobus_register(priv->mii_bus, mdio_np); ++ else ++ ret = mdiobus_register(priv->mii_bus); ++ ++ if (ret) { + err = -ENXIO; + goto err_out_free_mdiobus; + } diff --git a/target/linux/lantiq/patches-5.15/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch b/target/linux/lantiq/patches-5.15/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch new file mode 100644 index 0000000000..5bbf752dba --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch @@ -0,0 +1,145 @@ +From 998ac358019e491217e752bc6dcbb3afb2a6fa3e Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Sun, 19 Sep 2021 20:24:28 +0200 +Subject: [PATCH] net: lantiq: add support for jumbo frames + +Add support for jumbo frames. Full support for jumbo frames requires +changes in the DSA switch driver (lantiq_gswip.c). + +Tested on BT Hone Hub 5A. + +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/lantiq_xrx200.c | 64 +++++++++++++++++++++++++--- + 1 file changed, 57 insertions(+), 7 deletions(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -14,13 +14,15 @@ + #include + #include + ++#include ++ + #include + #include + + #include + + /* DMA */ +-#define XRX200_DMA_DATA_LEN 0x600 ++#define XRX200_DMA_DATA_LEN (SZ_64K - 1) + #define XRX200_DMA_RX 0 + #define XRX200_DMA_TX 1 + +@@ -106,7 +108,8 @@ static void xrx200_flush_dma(struct xrx2 + break; + + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | +- XRX200_DMA_DATA_LEN; ++ (ch->priv->net_dev->mtu + VLAN_ETH_HLEN + ++ ETH_FCS_LEN); + ch->dma.desc++; + ch->dma.desc %= LTQ_DESC_NUM; + } +@@ -154,19 +157,20 @@ static int xrx200_close(struct net_devic + + static int xrx200_alloc_skb(struct xrx200_chan *ch) + { ++ int len = ch->priv->net_dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; + struct sk_buff *skb = ch->skb[ch->dma.desc]; + dma_addr_t mapping; + int ret = 0; + + ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev, +- XRX200_DMA_DATA_LEN); ++ len); + if (!ch->skb[ch->dma.desc]) { + ret = -ENOMEM; + goto skip; + } + + mapping = dma_map_single(ch->priv->dev, ch->skb[ch->dma.desc]->data, +- XRX200_DMA_DATA_LEN, DMA_FROM_DEVICE); ++ len, DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(ch->priv->dev, mapping))) { + dev_kfree_skb_any(ch->skb[ch->dma.desc]); + ch->skb[ch->dma.desc] = skb; +@@ -179,8 +183,7 @@ static int xrx200_alloc_skb(struct xrx20 + wmb(); + skip: + ch->dma.desc_base[ch->dma.desc].ctl = +- LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | +- XRX200_DMA_DATA_LEN; ++ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | len; + + return ret; + } +@@ -340,10 +343,57 @@ err_drop: + return NETDEV_TX_OK; + } + ++static int ++xrx200_change_mtu(struct net_device *net_dev, int new_mtu) ++{ ++ struct xrx200_priv *priv = netdev_priv(net_dev); ++ struct xrx200_chan *ch_rx = &priv->chan_rx; ++ int old_mtu = net_dev->mtu; ++ bool running = false; ++ struct sk_buff *skb; ++ int curr_desc; ++ int ret = 0; ++ ++ net_dev->mtu = new_mtu; ++ ++ if (new_mtu <= old_mtu) ++ return ret; ++ ++ running = netif_running(net_dev); ++ if (running) { ++ napi_disable(&ch_rx->napi); ++ ltq_dma_close(&ch_rx->dma); ++ } ++ ++ xrx200_poll_rx(&ch_rx->napi, LTQ_DESC_NUM); ++ curr_desc = ch_rx->dma.desc; ++ ++ for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; ++ ch_rx->dma.desc++) { ++ skb = ch_rx->skb[ch_rx->dma.desc]; ++ ret = xrx200_alloc_skb(ch_rx); ++ if (ret) { ++ net_dev->mtu = old_mtu; ++ break; ++ } ++ dev_kfree_skb_any(skb); ++ } ++ ++ ch_rx->dma.desc = curr_desc; ++ if (running) { ++ napi_enable(&ch_rx->napi); ++ ltq_dma_open(&ch_rx->dma); ++ ltq_dma_enable_irq(&ch_rx->dma); ++ } ++ ++ return ret; ++} ++ + static const struct net_device_ops xrx200_netdev_ops = { + .ndo_open = xrx200_open, + .ndo_stop = xrx200_close, + .ndo_start_xmit = xrx200_start_xmit, ++ .ndo_change_mtu = xrx200_change_mtu, + .ndo_set_mac_address = eth_mac_addr, + .ndo_validate_addr = eth_validate_addr, + }; +@@ -454,7 +504,7 @@ static int xrx200_probe(struct platform_ + net_dev->netdev_ops = &xrx200_netdev_ops; + SET_NETDEV_DEV(net_dev, dev); + net_dev->min_mtu = ETH_ZLEN; +- net_dev->max_mtu = XRX200_DMA_DATA_LEN; ++ net_dev->max_mtu = XRX200_DMA_DATA_LEN - VLAN_ETH_HLEN - ETH_FCS_LEN; + + /* load the memory ranges */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/target/linux/lantiq/patches-5.15/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch b/target/linux/lantiq/patches-5.15/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch new file mode 100644 index 0000000000..77c0eb6354 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch @@ -0,0 +1,122 @@ +From 1488fc204568f707fe2a42a913788c00a95af30e Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Fri, 17 Dec 2021 01:07:40 +0100 +Subject: [PATCH] net: lantiq_xrx200: increase buffer reservation + +If the user sets a lower mtu on the CPU port than on the switch, +then DMA inserts a few more bytes into the buffer than expected. +In the worst case, it may exceed the size of the buffer. The +experiments showed that the buffer should be a multiple of the +burst length value. This patch rounds the length of the rx buffer +upwards and fixes this bug. The reservation of FCS space in the +buffer has been removed as PMAC strips the FCS. + +Fixes: 998ac358019e ("net: lantiq: add support for jumbo frames") +Reported-by: Thomas Nixon +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/lantiq_xrx200.c | 34 ++++++++++++++++++++-------- + 1 file changed, 24 insertions(+), 10 deletions(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -70,6 +70,8 @@ struct xrx200_priv { + struct xrx200_chan chan_tx; + struct xrx200_chan chan_rx; + ++ u16 rx_buf_size; ++ + struct net_device *net_dev; + struct device *dev; + +@@ -96,6 +98,16 @@ static void xrx200_pmac_mask(struct xrx2 + xrx200_pmac_w32(priv, val, offset); + } + ++static int xrx200_max_frame_len(int mtu) ++{ ++ return VLAN_ETH_HLEN + mtu; ++} ++ ++static int xrx200_buffer_size(int mtu) ++{ ++ return round_up(xrx200_max_frame_len(mtu), 4 * XRX200_DMA_BURST_LEN); ++} ++ + /* drop all the packets from the DMA ring */ + static void xrx200_flush_dma(struct xrx200_chan *ch) + { +@@ -108,8 +120,7 @@ static void xrx200_flush_dma(struct xrx2 + break; + + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | +- (ch->priv->net_dev->mtu + VLAN_ETH_HLEN + +- ETH_FCS_LEN); ++ ch->priv->rx_buf_size; + ch->dma.desc++; + ch->dma.desc %= LTQ_DESC_NUM; + } +@@ -157,21 +168,21 @@ static int xrx200_close(struct net_devic + + static int xrx200_alloc_skb(struct xrx200_chan *ch) + { +- int len = ch->priv->net_dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; + struct sk_buff *skb = ch->skb[ch->dma.desc]; ++ struct xrx200_priv *priv = ch->priv; + dma_addr_t mapping; + int ret = 0; + +- ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev, +- len); ++ ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(priv->net_dev, ++ priv->rx_buf_size); + if (!ch->skb[ch->dma.desc]) { + ret = -ENOMEM; + goto skip; + } + +- mapping = dma_map_single(ch->priv->dev, ch->skb[ch->dma.desc]->data, +- len, DMA_FROM_DEVICE); +- if (unlikely(dma_mapping_error(ch->priv->dev, mapping))) { ++ mapping = dma_map_single(priv->dev, ch->skb[ch->dma.desc]->data, ++ priv->rx_buf_size, DMA_FROM_DEVICE); ++ if (unlikely(dma_mapping_error(priv->dev, mapping))) { + dev_kfree_skb_any(ch->skb[ch->dma.desc]); + ch->skb[ch->dma.desc] = skb; + ret = -ENOMEM; +@@ -183,7 +194,7 @@ static int xrx200_alloc_skb(struct xrx20 + wmb(); + skip: + ch->dma.desc_base[ch->dma.desc].ctl = +- LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | len; ++ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | priv->rx_buf_size; + + return ret; + } +@@ -355,6 +366,7 @@ xrx200_change_mtu(struct net_device *net + int ret = 0; + + net_dev->mtu = new_mtu; ++ priv->rx_buf_size = xrx200_buffer_size(new_mtu); + + if (new_mtu <= old_mtu) + return ret; +@@ -374,6 +386,7 @@ xrx200_change_mtu(struct net_device *net + ret = xrx200_alloc_skb(ch_rx); + if (ret) { + net_dev->mtu = old_mtu; ++ priv->rx_buf_size = xrx200_buffer_size(old_mtu); + break; + } + dev_kfree_skb_any(skb); +@@ -504,7 +517,8 @@ static int xrx200_probe(struct platform_ + net_dev->netdev_ops = &xrx200_netdev_ops; + SET_NETDEV_DEV(net_dev, dev); + net_dev->min_mtu = ETH_ZLEN; +- net_dev->max_mtu = XRX200_DMA_DATA_LEN - VLAN_ETH_HLEN - ETH_FCS_LEN; ++ net_dev->max_mtu = XRX200_DMA_DATA_LEN - xrx200_max_frame_len(0); ++ priv->rx_buf_size = xrx200_buffer_size(ETH_DATA_LEN); + + /* load the memory ranges */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/target/linux/lantiq/patches-5.15/0704-v5.17-net-lantiq_xrx200-add-ingress-SG-DMA-support.patch b/target/linux/lantiq/patches-5.15/0704-v5.17-net-lantiq_xrx200-add-ingress-SG-DMA-support.patch new file mode 100644 index 0000000000..f2c36952fc --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0704-v5.17-net-lantiq_xrx200-add-ingress-SG-DMA-support.patch @@ -0,0 +1,104 @@ +From c3e6b2c35b34214c58c1e90d65dab5f5393608e7 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Mon, 3 Jan 2022 20:43:16 +0100 +Subject: [PATCH] net: lantiq_xrx200: add ingress SG DMA support + +This patch adds support for scatter gather DMA. DMA in PMAC splits +the packet into several buffers when the MTU on the CPU port is +less than the MTU of the switch. The first buffer starts at an +offset of NET_IP_ALIGN. In subsequent buffers, dma ignores the +offset. Thanks to this patch, the user can still connect to the +device in such a situation. For normal configurations, the patch +has no effect on performance. + +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/lantiq_xrx200.c | 47 +++++++++++++++++++++++----- + 1 file changed, 40 insertions(+), 7 deletions(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -26,6 +26,9 @@ + #define XRX200_DMA_RX 0 + #define XRX200_DMA_TX 1 + ++#define XRX200_DMA_PACKET_COMPLETE 0 ++#define XRX200_DMA_PACKET_IN_PROGRESS 1 ++ + /* cpu port mac */ + #define PMAC_RX_IPG 0x0024 + #define PMAC_RX_IPG_MASK 0xf +@@ -61,6 +64,9 @@ struct xrx200_chan { + struct ltq_dma_channel dma; + struct sk_buff *skb[LTQ_DESC_NUM]; + ++ struct sk_buff *skb_head; ++ struct sk_buff *skb_tail; ++ + struct xrx200_priv *priv; + }; + +@@ -204,7 +210,8 @@ static int xrx200_hw_receive(struct xrx2 + struct xrx200_priv *priv = ch->priv; + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; + struct sk_buff *skb = ch->skb[ch->dma.desc]; +- int len = (desc->ctl & LTQ_DMA_SIZE_MASK); ++ u32 ctl = desc->ctl; ++ int len = (ctl & LTQ_DMA_SIZE_MASK); + struct net_device *net_dev = priv->net_dev; + int ret; + +@@ -220,12 +227,36 @@ static int xrx200_hw_receive(struct xrx2 + } + + skb_put(skb, len); +- skb->protocol = eth_type_trans(skb, net_dev); +- netif_receive_skb(skb); +- net_dev->stats.rx_packets++; +- net_dev->stats.rx_bytes += len; + +- return 0; ++ /* add buffers to skb via skb->frag_list */ ++ if (ctl & LTQ_DMA_SOP) { ++ ch->skb_head = skb; ++ ch->skb_tail = skb; ++ } else if (ch->skb_head) { ++ if (ch->skb_head == ch->skb_tail) ++ skb_shinfo(ch->skb_tail)->frag_list = skb; ++ else ++ ch->skb_tail->next = skb; ++ ch->skb_tail = skb; ++ skb_reserve(ch->skb_tail, -NET_IP_ALIGN); ++ ch->skb_head->len += skb->len; ++ ch->skb_head->data_len += skb->len; ++ ch->skb_head->truesize += skb->truesize; ++ } ++ ++ if (ctl & LTQ_DMA_EOP) { ++ ch->skb_head->protocol = eth_type_trans(ch->skb_head, net_dev); ++ netif_receive_skb(ch->skb_head); ++ net_dev->stats.rx_packets++; ++ net_dev->stats.rx_bytes += ch->skb_head->len; ++ ch->skb_head = NULL; ++ ch->skb_tail = NULL; ++ ret = XRX200_DMA_PACKET_COMPLETE; ++ } else { ++ ret = XRX200_DMA_PACKET_IN_PROGRESS; ++ } ++ ++ return ret; + } + + static int xrx200_poll_rx(struct napi_struct *napi, int budget) +@@ -240,7 +271,9 @@ static int xrx200_poll_rx(struct napi_st + + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { + ret = xrx200_hw_receive(ch); +- if (ret) ++ if (ret == XRX200_DMA_PACKET_IN_PROGRESS) ++ continue; ++ if (ret != XRX200_DMA_PACKET_COMPLETE) + return ret; + rx++; + } else { diff --git a/target/linux/lantiq/patches-5.15/0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch b/target/linux/lantiq/patches-5.15/0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch new file mode 100644 index 0000000000..a69f682c03 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch @@ -0,0 +1,275 @@ +From a09d042b086202735c4ed64573cdd79933020001 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Mon, 22 Mar 2021 21:37:15 +0100 +Subject: [PATCH] net: dsa: lantiq: allow to use all GPHYs on xRX300 and xRX330 + +This patch allows to use all PHYs on GRX300 and GRX330. The ARX300 +has 3 and the GRX330 has 4 integrated PHYs connected to different +ports compared to VRX200. Each integrated PHY can work as single +Gigabit Ethernet PHY (GMII) or as double Fast Ethernet PHY (MII). + +Allowed port configurations: + +xRX200: +GMAC0: RGMII, MII, REVMII or RMII port +GMAC1: RGMII, MII, REVMII or RMII port +GMAC2: GPHY0 (GMII) +GMAC3: GPHY0 (MII) +GMAC4: GPHY1 (GMII) +GMAC5: GPHY1 (MII) or RGMII port + +xRX300: +GMAC0: RGMII port +GMAC1: GPHY2 (GMII) +GMAC2: GPHY0 (GMII) +GMAC3: GPHY0 (MII) +GMAC4: GPHY1 (GMII) +GMAC5: GPHY1 (MII) or RGMII port + +xRX330: +GMAC0: RGMII, GMII or RMII port +GMAC1: GPHY2 (GMII) +GMAC2: GPHY0 (GMII) +GMAC3: GPHY0 (MII) or GPHY3 (GMII) +GMAC4: GPHY1 (GMII) +GMAC5: GPHY1 (MII), RGMII or RMII port + +Tested on D-Link DWR966 (xRX330) with OpenWRT. + +Signed-off-by: Aleksander Jan Bajkowski +Acked-by: Hauke Mehrtens +Signed-off-by: David S. Miller +--- + drivers/net/dsa/lantiq_gswip.c | 142 ++++++++++++++++++++++++++------- + 1 file changed, 113 insertions(+), 29 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0 + /* +- * Lantiq / Intel GSWIP switch driver for VRX200 SoCs ++ * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs + * + * Copyright (C) 2010 Lantiq Deutschland + * Copyright (C) 2012 John Crispin +@@ -104,6 +104,7 @@ + #define GSWIP_MII_CFG_MODE_RMIIP 0x2 + #define GSWIP_MII_CFG_MODE_RMIIM 0x3 + #define GSWIP_MII_CFG_MODE_RGMII 0x4 ++#define GSWIP_MII_CFG_MODE_GMII 0x9 + #define GSWIP_MII_CFG_MODE_MASK 0xf + #define GSWIP_MII_CFG_RATE_M2P5 0x00 + #define GSWIP_MII_CFG_RATE_M25 0x10 +@@ -241,6 +242,7 @@ + struct gswip_hw_info { + int max_ports; + int cpu_port; ++ const struct dsa_switch_ops *ops; + }; + + struct xway_gphy_match_data { +@@ -1438,12 +1440,42 @@ static int gswip_port_fdb_dump(struct ds + return 0; + } + +-static void gswip_phylink_validate(struct dsa_switch *ds, int port, +- unsigned long *supported, +- struct phylink_link_state *state) ++static void gswip_phylink_set_capab(unsigned long *supported, ++ struct phylink_link_state *state) + { + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + ++ /* Allow all the expected bits */ ++ phylink_set(mask, Autoneg); ++ phylink_set_port_modes(mask); ++ phylink_set(mask, Pause); ++ phylink_set(mask, Asym_Pause); ++ ++ /* With the exclusion of MII, Reverse MII and Reduced MII, we ++ * support Gigabit, including Half duplex ++ */ ++ if (state->interface != PHY_INTERFACE_MODE_MII && ++ state->interface != PHY_INTERFACE_MODE_REVMII && ++ state->interface != PHY_INTERFACE_MODE_RMII) { ++ phylink_set(mask, 1000baseT_Full); ++ phylink_set(mask, 1000baseT_Half); ++ } ++ ++ phylink_set(mask, 10baseT_Half); ++ phylink_set(mask, 10baseT_Full); ++ phylink_set(mask, 100baseT_Half); ++ phylink_set(mask, 100baseT_Full); ++ ++ bitmap_and(supported, supported, mask, ++ __ETHTOOL_LINK_MODE_MASK_NBITS); ++ bitmap_and(state->advertising, state->advertising, mask, ++ __ETHTOOL_LINK_MODE_MASK_NBITS); ++} ++ ++static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port, ++ unsigned long *supported, ++ struct phylink_link_state *state) ++{ + switch (port) { + case 0: + case 1: +@@ -1470,38 +1502,54 @@ static void gswip_phylink_validate(struc + return; + } + +- /* Allow all the expected bits */ +- phylink_set(mask, Autoneg); +- phylink_set_port_modes(mask); +- phylink_set(mask, Pause); +- phylink_set(mask, Asym_Pause); ++ gswip_phylink_set_capab(supported, state); + +- /* With the exclusion of MII, Reverse MII and Reduced MII, we +- * support Gigabit, including Half duplex +- */ +- if (state->interface != PHY_INTERFACE_MODE_MII && +- state->interface != PHY_INTERFACE_MODE_REVMII && +- state->interface != PHY_INTERFACE_MODE_RMII) { +- phylink_set(mask, 1000baseT_Full); +- phylink_set(mask, 1000baseT_Half); ++ return; ++ ++unsupported: ++ bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", ++ phy_modes(state->interface), port); ++} ++ ++static void gswip_xrx300_phylink_validate(struct dsa_switch *ds, int port, ++ unsigned long *supported, ++ struct phylink_link_state *state) ++{ ++ switch (port) { ++ case 0: ++ if (!phy_interface_mode_is_rgmii(state->interface) && ++ state->interface != PHY_INTERFACE_MODE_GMII && ++ state->interface != PHY_INTERFACE_MODE_RMII) ++ goto unsupported; ++ break; ++ case 1: ++ case 2: ++ case 3: ++ case 4: ++ if (state->interface != PHY_INTERFACE_MODE_INTERNAL) ++ goto unsupported; ++ break; ++ case 5: ++ if (!phy_interface_mode_is_rgmii(state->interface) && ++ state->interface != PHY_INTERFACE_MODE_INTERNAL && ++ state->interface != PHY_INTERFACE_MODE_RMII) ++ goto unsupported; ++ break; ++ default: ++ bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ dev_err(ds->dev, "Unsupported port: %i\n", port); ++ return; + } + +- phylink_set(mask, 10baseT_Half); +- phylink_set(mask, 10baseT_Full); +- phylink_set(mask, 100baseT_Half); +- phylink_set(mask, 100baseT_Full); ++ gswip_phylink_set_capab(supported, state); + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); + return; + + unsupported: + bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); + dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", + phy_modes(state->interface), port); +- return; + } + + static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) +@@ -1636,6 +1684,9 @@ static void gswip_phylink_mac_config(str + case PHY_INTERFACE_MODE_RGMII_TXID: + miicfg |= GSWIP_MII_CFG_MODE_RGMII; + break; ++ case PHY_INTERFACE_MODE_GMII: ++ miicfg |= GSWIP_MII_CFG_MODE_GMII; ++ break; + default: + dev_err(ds->dev, + "Unsupported interface: %d\n", state->interface); +@@ -1762,7 +1813,7 @@ static int gswip_get_sset_count(struct d + return ARRAY_SIZE(gswip_rmon_cnt); + } + +-static const struct dsa_switch_ops gswip_switch_ops = { ++static const struct dsa_switch_ops gswip_xrx200_switch_ops = { + .get_tag_protocol = gswip_get_tag_protocol, + .setup = gswip_setup, + .port_enable = gswip_port_enable, +@@ -1778,7 +1829,31 @@ static const struct dsa_switch_ops gswip + .port_fdb_add = gswip_port_fdb_add, + .port_fdb_del = gswip_port_fdb_del, + .port_fdb_dump = gswip_port_fdb_dump, +- .phylink_validate = gswip_phylink_validate, ++ .phylink_validate = gswip_xrx200_phylink_validate, ++ .phylink_mac_config = gswip_phylink_mac_config, ++ .phylink_mac_link_down = gswip_phylink_mac_link_down, ++ .phylink_mac_link_up = gswip_phylink_mac_link_up, ++ .get_strings = gswip_get_strings, ++ .get_ethtool_stats = gswip_get_ethtool_stats, ++ .get_sset_count = gswip_get_sset_count, ++}; ++ ++static const struct dsa_switch_ops gswip_xrx300_switch_ops = { ++ .get_tag_protocol = gswip_get_tag_protocol, ++ .setup = gswip_setup, ++ .port_enable = gswip_port_enable, ++ .port_disable = gswip_port_disable, ++ .port_bridge_join = gswip_port_bridge_join, ++ .port_bridge_leave = gswip_port_bridge_leave, ++ .port_fast_age = gswip_port_fast_age, ++ .port_vlan_filtering = gswip_port_vlan_filtering, ++ .port_vlan_add = gswip_port_vlan_add, ++ .port_vlan_del = gswip_port_vlan_del, ++ .port_stp_state_set = gswip_port_stp_state_set, ++ .port_fdb_add = gswip_port_fdb_add, ++ .port_fdb_del = gswip_port_fdb_del, ++ .port_fdb_dump = gswip_port_fdb_dump, ++ .phylink_validate = gswip_xrx300_phylink_validate, + .phylink_mac_config = gswip_phylink_mac_config, + .phylink_mac_link_down = gswip_phylink_mac_link_down, + .phylink_mac_link_up = gswip_phylink_mac_link_up, +@@ -2042,7 +2117,7 @@ static int gswip_probe(struct platform_d + priv->ds->dev = dev; + priv->ds->num_ports = priv->hw_info->max_ports; + priv->ds->priv = priv; +- priv->ds->ops = &gswip_switch_ops; ++ priv->ds->ops = priv->hw_info->ops; + priv->dev = dev; + version = gswip_switch_r(priv, GSWIP_VERSION); + +@@ -2126,10 +2201,19 @@ static int gswip_remove(struct platform_ + static const struct gswip_hw_info gswip_xrx200 = { + .max_ports = 7, + .cpu_port = 6, ++ .ops = &gswip_xrx200_switch_ops, ++}; ++ ++static const struct gswip_hw_info gswip_xrx300 = { ++ .max_ports = 7, ++ .cpu_port = 6, ++ .ops = &gswip_xrx300_switch_ops, + }; + + static const struct of_device_id gswip_of_match[] = { + { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, ++ { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 }, ++ { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 }, + {}, + }; + MODULE_DEVICE_TABLE(of, gswip_of_match); diff --git a/target/linux/lantiq/patches-5.15/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch b/target/linux/lantiq/patches-5.15/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch new file mode 100644 index 0000000000..49a19bebee --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch @@ -0,0 +1,127 @@ +From c40bb4fedcd6b8b6a714da5dd466eb88ed2652d1 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Wed, 9 Mar 2022 00:04:57 +0100 +Subject: net: dsa: lantiq_gswip: enable jumbo frames on GSWIP + +This enables non-standard MTUs on a per-port basis, with the overall +frame size set based on the CPU port. + +When the MTU is not changed, this should have no effect. + +Long packets crash the switch with MTUs of greater than 2526, so the +maximum is limited for now. Medium packets are sometimes dropped (e.g. +TCP over 2477, UDP over 2516-2519, ICMP over 2526), Hence an MTU value +of 2400 seems safe. + +Signed-off-by: Thomas Nixon +Signed-off-by: Aleksander Jan Bajkowski +Link: https://lore.kernel.org/r/20220308230457.1599237-1-olek2@wp.pl +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/lantiq_gswip.c | 53 ++++++++++++++++++++++++++++++++++++++---- + 1 file changed, 49 insertions(+), 4 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -213,6 +213,7 @@ + #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 + #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 + #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) ++#define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */ + #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ + + /* Ethernet Switch Fetch DMA Port Control Register */ +@@ -239,6 +240,15 @@ + + #define XRX200_GPHY_FW_ALIGN (16 * 1024) + ++/* Maximum packet size supported by the switch. In theory this should be 10240, ++ * but long packets currently cause lock-ups with an MTU of over 2526. Medium ++ * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP ++ * over 2526), hence an MTU value of 2400 seems safe. This issue only affects ++ * packet reception. This is probably caused by the PPA engine, which is on the ++ * RX part of the device. Packet transmission works properly up to 10240. ++ */ ++#define GSWIP_MAX_PACKET_LENGTH 2400 ++ + struct gswip_hw_info { + int max_ports; + int cpu_port; +@@ -858,10 +868,6 @@ static int gswip_setup(struct dsa_switch + gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, + GSWIP_PCE_PCTRL_0p(cpu_port)); + +- gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, +- GSWIP_MAC_CTRL_2p(cpu_port)); +- gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8 + ETH_FCS_LEN, +- GSWIP_MAC_FLEN); + gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, + GSWIP_BM_QUEUE_GCTRL); + +@@ -878,6 +884,8 @@ static int gswip_setup(struct dsa_switch + return err; + } + ++ ds->mtu_enforcement_ingress = true; ++ + gswip_port_enable(ds, cpu_port, NULL); + return 0; + } +@@ -1472,6 +1480,39 @@ static void gswip_phylink_set_capab(unsi + __ETHTOOL_LINK_MODE_MASK_NBITS); + } + ++static int gswip_port_max_mtu(struct dsa_switch *ds, int port) ++{ ++ /* Includes 8 bytes for special header. */ ++ return GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN; ++} ++ ++static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) ++{ ++ struct gswip_priv *priv = ds->priv; ++ int cpu_port = priv->hw_info->cpu_port; ++ ++ /* CPU port always has maximum mtu of user ports, so use it to set ++ * switch frame size, including 8 byte special header. ++ */ ++ if (port == cpu_port) { ++ new_mtu += 8; ++ gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN, ++ GSWIP_MAC_FLEN); ++ } ++ ++ /* Enable MLEN for ports with non-standard MTUs, including the special ++ * header on the CPU port added above. ++ */ ++ if (new_mtu != ETH_DATA_LEN) ++ gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, ++ GSWIP_MAC_CTRL_2p(port)); ++ else ++ gswip_switch_mask(priv, GSWIP_MAC_CTRL_2_MLEN, 0, ++ GSWIP_MAC_CTRL_2p(port)); ++ ++ return 0; ++} ++ + static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port, + unsigned long *supported, + struct phylink_link_state *state) +@@ -1829,6 +1870,8 @@ static const struct dsa_switch_ops gswip + .port_fdb_add = gswip_port_fdb_add, + .port_fdb_del = gswip_port_fdb_del, + .port_fdb_dump = gswip_port_fdb_dump, ++ .port_change_mtu = gswip_port_change_mtu, ++ .port_max_mtu = gswip_port_max_mtu, + .phylink_validate = gswip_xrx200_phylink_validate, + .phylink_mac_config = gswip_phylink_mac_config, + .phylink_mac_link_down = gswip_phylink_mac_link_down, +@@ -1853,6 +1896,8 @@ static const struct dsa_switch_ops gswip + .port_fdb_add = gswip_port_fdb_add, + .port_fdb_del = gswip_port_fdb_del, + .port_fdb_dump = gswip_port_fdb_dump, ++ .port_change_mtu = gswip_port_change_mtu, ++ .port_max_mtu = gswip_port_max_mtu, + .phylink_validate = gswip_xrx300_phylink_validate, + .phylink_mac_config = gswip_phylink_mac_config, + .phylink_mac_link_down = gswip_phylink_mac_link_down, diff --git a/target/linux/lantiq/patches-5.15/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch b/target/linux/lantiq/patches-5.15/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch new file mode 100644 index 0000000000..4fb7d0767b --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch @@ -0,0 +1,126 @@ +From 14d4e308e0aa0b78dc7a059716861a4380de3535 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 14 Sep 2021 23:21:02 +0200 +Subject: [PATCH 5/5] net: lantiq: configure the burst length in ethernet + drivers + +Configure the burst length in Ethernet drivers. This improves +Ethernet performance by 58%. According to the vendor BSP, +8W burst length is supported by ar9 and newer SoCs. + +The NAT benchmark results on xRX200 (Down/Up): +* 2W: 330 Mb/s +* 4W: 432 Mb/s 372 Mb/s +* 8W: 520 Mb/s 389 Mb/s + +Tested on xRX200 and xRX330. + +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/lantiq_etop.c | 21 ++++++++++++++++++--- + drivers/net/ethernet/lantiq_xrx200.c | 21 ++++++++++++++++++--- + 2 files changed, 36 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -148,6 +148,9 @@ struct ltq_etop_priv { + struct ltq_etop_chan txch; + struct ltq_etop_chan rxch; + ++ int tx_burst_len; ++ int rx_burst_len; ++ + int tx_irq; + int rx_irq; + +@@ -399,7 +402,7 @@ ltq_etop_dma_init(struct net_device *dev + int rx = priv->rx_irq - LTQ_DMA_ETOP; + int err; + +- ltq_dma_init_port(DMA_PORT_ETOP); ++ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); + + priv->txch.dma.nr = tx; + priv->txch.dma.dev = &priv->pdev->dev; +@@ -676,8 +679,8 @@ ltq_etop_tx(struct sk_buff *skb, struct + return NETDEV_TX_BUSY; + } + +- /* dma needs to start on a 16 byte aligned address */ +- byte_offset = CPHYSADDR(skb->data) % 16; ++ /* dma needs to start on a burst length value aligned address */ ++ byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4); + priv->txch.skb[priv->txch.dma.desc] = skb; + + netif_trans_update(dev); +@@ -925,6 +928,18 @@ static int ltq_etop_probe(struct platfor + spin_lock_init(&priv->lock); + SET_NETDEV_DEV(dev, &pdev->dev); + ++ err = device_property_read_u32(&pdev->dev, "lantiq,tx-burst-length", &priv->tx_burst_len); ++ if (err < 0) { ++ dev_err(&pdev->dev, "unable to read tx-burst-length property\n"); ++ return err; ++ } ++ ++ err = device_property_read_u32(&pdev->dev, "lantiq,rx-burst-length", &priv->rx_burst_len); ++ if (err < 0) { ++ dev_err(&pdev->dev, "unable to read rx-burst-length property\n"); ++ return err; ++ } ++ + netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); + netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); + priv->txch.netdev = dev; +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -81,6 +81,9 @@ struct xrx200_priv { + struct net_device *net_dev; + struct device *dev; + ++ int tx_burst_len; ++ int rx_burst_len; ++ + __iomem void *pmac_reg; + }; + +@@ -363,8 +366,8 @@ static netdev_tx_t xrx200_start_xmit(str + if (unlikely(dma_mapping_error(priv->dev, mapping))) + goto err_drop; + +- /* dma needs to start on a 16 byte aligned address */ +- byte_offset = mapping % 16; ++ /* dma needs to start on a burst length value aligned address */ ++ byte_offset = mapping % (priv->tx_burst_len * 4); + + desc->addr = mapping - byte_offset; + /* Make sure the address is written before we give it to HW */ +@@ -465,7 +468,7 @@ static int xrx200_dma_init(struct xrx200 + int ret = 0; + int i; + +- ltq_dma_init_port(DMA_PORT_ETOP); ++ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); + + ch_rx->dma.nr = XRX200_DMA_RX; + ch_rx->dma.dev = priv->dev; +@@ -584,6 +587,18 @@ static int xrx200_probe(struct platform_ + if (err) + eth_hw_addr_random(net_dev); + ++ err = device_property_read_u32(dev, "lantiq,tx-burst-length", &priv->tx_burst_len); ++ if (err < 0) { ++ dev_err(dev, "unable to read tx-burst-length property\n"); ++ return err; ++ } ++ ++ err = device_property_read_u32(dev, "lantiq,rx-burst-length", &priv->rx_burst_len); ++ if (err < 0) { ++ dev_err(dev, "unable to read rx-burst-length property\n"); ++ return err; ++ } ++ + /* bring up the dma engine and IP core */ + err = xrx200_dma_init(priv); + if (err) diff --git a/target/linux/lantiq/patches-5.15/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch b/target/linux/lantiq/patches-5.15/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch new file mode 100644 index 0000000000..7448af8c26 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch @@ -0,0 +1,73 @@ +From 7e553c44f09a8f536090904c6db5b8c9dbafa03b Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 26 Oct 2021 22:59:01 +0200 +Subject: [PATCH] net: lantiq_xrx200: Hardcode the burst length value + +All SoCs with this IP core support 8 burst length. Hauke +suggested to hardcode this value and simplify the driver. + +Link: https://lkml.org/lkml/2021/9/14/1533 +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/lantiq_xrx200.c | 21 ++++----------------- + 1 file changed, 4 insertions(+), 17 deletions(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -25,6 +25,7 @@ + #define XRX200_DMA_DATA_LEN (SZ_64K - 1) + #define XRX200_DMA_RX 0 + #define XRX200_DMA_TX 1 ++#define XRX200_DMA_BURST_LEN 8 + + #define XRX200_DMA_PACKET_COMPLETE 0 + #define XRX200_DMA_PACKET_IN_PROGRESS 1 +@@ -81,9 +82,6 @@ struct xrx200_priv { + struct net_device *net_dev; + struct device *dev; + +- int tx_burst_len; +- int rx_burst_len; +- + __iomem void *pmac_reg; + }; + +@@ -367,7 +365,7 @@ static netdev_tx_t xrx200_start_xmit(str + goto err_drop; + + /* dma needs to start on a burst length value aligned address */ +- byte_offset = mapping % (priv->tx_burst_len * 4); ++ byte_offset = mapping % (XRX200_DMA_BURST_LEN * 4); + + desc->addr = mapping - byte_offset; + /* Make sure the address is written before we give it to HW */ +@@ -468,7 +466,8 @@ static int xrx200_dma_init(struct xrx200 + int ret = 0; + int i; + +- ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); ++ ltq_dma_init_port(DMA_PORT_ETOP, XRX200_DMA_BURST_LEN, ++ XRX200_DMA_BURST_LEN); + + ch_rx->dma.nr = XRX200_DMA_RX; + ch_rx->dma.dev = priv->dev; +@@ -587,18 +586,6 @@ static int xrx200_probe(struct platform_ + if (err) + eth_hw_addr_random(net_dev); + +- err = device_property_read_u32(dev, "lantiq,tx-burst-length", &priv->tx_burst_len); +- if (err < 0) { +- dev_err(dev, "unable to read tx-burst-length property\n"); +- return err; +- } +- +- err = device_property_read_u32(dev, "lantiq,rx-burst-length", &priv->rx_burst_len); +- if (err < 0) { +- dev_err(dev, "unable to read rx-burst-length property\n"); +- return err; +- } +- + /* bring up the dma engine and IP core */ + err = xrx200_dma_init(priv); + if (err) diff --git a/target/linux/lantiq/patches-5.15/0712-v5.16-net-ethernet-lantiq_etop-Fix-compilation-error.patch b/target/linux/lantiq/patches-5.15/0712-v5.16-net-ethernet-lantiq_etop-Fix-compilation-error.patch new file mode 100644 index 0000000000..06f4bc2eee --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0712-v5.16-net-ethernet-lantiq_etop-Fix-compilation-error.patch @@ -0,0 +1,26 @@ +From 68eabc348148ae051631e8dab13c3b1a85c82896 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 9 Nov 2021 23:23:54 +0100 +Subject: [PATCH] net: ethernet: lantiq_etop: Fix compilation error + +This fixes the error detected when compiling the driver. + +Fixes: 14d4e308e0aa ("net: lantiq: configure the burst length in ethernet drivers") +Reported-by: kernel test robot +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/lantiq_etop.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -402,7 +402,7 @@ ltq_etop_dma_init(struct net_device *dev + int rx = priv->rx_irq - LTQ_DMA_ETOP; + int err; + +- ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); ++ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len); + + priv->txch.dma.nr = tx; + priv->txch.dma.dev = &priv->pdev->dev; diff --git a/target/linux/lantiq/patches-5.15/0713-v5.17-MIPS-lantiq-dma-increase-descritor-count.patch b/target/linux/lantiq/patches-5.15/0713-v5.17-MIPS-lantiq-dma-increase-descritor-count.patch new file mode 100644 index 0000000000..37ed1d4f31 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0713-v5.17-MIPS-lantiq-dma-increase-descritor-count.patch @@ -0,0 +1,28 @@ +From 5112e9234bbb89f8dd15c983206bd9107b8436d5 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 4 Jan 2022 16:11:42 +0100 +Subject: [PATCH 713/715] MIPS: lantiq: dma: increase descritor count + +NAT Performance results on BT Home Hub 5A (kernel 5.10.89, mtu 1500): + + Down Up +Before 539 Mbps 599 Mbps +After 545 Mbps 625 Mbps + +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + arch/mips/include/asm/mach-lantiq/xway/xway_dma.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h +@@ -8,7 +8,7 @@ + #define LTQ_DMA_H__ + + #define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */ +-#define LTQ_DESC_NUM 0x40 /* 64 descriptors / channel */ ++#define LTQ_DESC_NUM 0xC0 /* 192 descriptors / channel */ + + #define LTQ_DMA_OWN BIT(31) /* owner bit */ + #define LTQ_DMA_C BIT(30) /* complete bit */ diff --git a/target/linux/lantiq/patches-5.15/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch b/target/linux/lantiq/patches-5.15/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch new file mode 100644 index 0000000000..1fa49f406e --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch @@ -0,0 +1,32 @@ +From 768818d772d5d4ddc0c7eb2e62848929270ab7a3 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 4 Jan 2022 16:11:43 +0100 +Subject: [PATCH 714/715] net: lantiq_xrx200: increase napi poll weigth + +NAT Performance results on BT Home Hub 5A (kernel 5.10.89, mtu 1500): + + Down Up +Before 545 Mbps 625 Mbps +After 577 Mbps 648 Mbps + +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/lantiq_xrx200.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -606,8 +606,10 @@ static int xrx200_probe(struct platform_ + PMAC_HD_CTL); + + /* setup NAPI */ +- netif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, 32); +- netif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, 32); ++ netif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, ++ NAPI_POLL_WEIGHT); ++ netif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, ++ NAPI_POLL_WEIGHT); + + platform_set_drvdata(pdev, priv); + diff --git a/target/linux/lantiq/patches-5.15/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch b/target/linux/lantiq/patches-5.15/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch new file mode 100644 index 0000000000..b2b014832c --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch @@ -0,0 +1,206 @@ +From e015593573b3e3f74bd8a63c05fa92902194a354 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Tue, 4 Jan 2022 16:11:44 +0100 +Subject: [PATCH 715/715] net: lantiq_xrx200: convert to build_skb + +We can increase the efficiency of rx path by using buffers to receive +packets then build SKBs around them just before passing into the network +stack. In contrast, preallocating SKBs too early reduces CPU cache +efficiency. + +NAT Performance results on BT Home Hub 5A (kernel 5.10.89, mtu 1500): + + Down Up +Before 577 Mbps 648 Mbps +After 624 Mbps 695 Mbps + +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/lantiq_xrx200.c | 56 ++++++++++++++++++---------- + 1 file changed, 36 insertions(+), 20 deletions(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -63,7 +63,11 @@ struct xrx200_chan { + + struct napi_struct napi; + struct ltq_dma_channel dma; +- struct sk_buff *skb[LTQ_DESC_NUM]; ++ ++ union { ++ struct sk_buff *skb[LTQ_DESC_NUM]; ++ void *rx_buff[LTQ_DESC_NUM]; ++ }; + + struct sk_buff *skb_head; + struct sk_buff *skb_tail; +@@ -78,6 +82,7 @@ struct xrx200_priv { + struct xrx200_chan chan_rx; + + u16 rx_buf_size; ++ u16 rx_skb_size; + + struct net_device *net_dev; + struct device *dev; +@@ -115,6 +120,12 @@ static int xrx200_buffer_size(int mtu) + return round_up(xrx200_max_frame_len(mtu), 4 * XRX200_DMA_BURST_LEN); + } + ++static int xrx200_skb_size(u16 buf_size) ++{ ++ return SKB_DATA_ALIGN(buf_size + NET_SKB_PAD + NET_IP_ALIGN) + ++ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); ++} ++ + /* drop all the packets from the DMA ring */ + static void xrx200_flush_dma(struct xrx200_chan *ch) + { +@@ -173,30 +184,29 @@ static int xrx200_close(struct net_devic + return 0; + } + +-static int xrx200_alloc_skb(struct xrx200_chan *ch) ++static int xrx200_alloc_buf(struct xrx200_chan *ch, void *(*alloc)(unsigned int size)) + { +- struct sk_buff *skb = ch->skb[ch->dma.desc]; ++ void *buf = ch->rx_buff[ch->dma.desc]; + struct xrx200_priv *priv = ch->priv; + dma_addr_t mapping; + int ret = 0; + +- ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(priv->net_dev, +- priv->rx_buf_size); +- if (!ch->skb[ch->dma.desc]) { ++ ch->rx_buff[ch->dma.desc] = alloc(priv->rx_skb_size); ++ if (!ch->rx_buff[ch->dma.desc]) { + ret = -ENOMEM; + goto skip; + } + +- mapping = dma_map_single(priv->dev, ch->skb[ch->dma.desc]->data, ++ mapping = dma_map_single(priv->dev, ch->rx_buff[ch->dma.desc], + priv->rx_buf_size, DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(priv->dev, mapping))) { +- dev_kfree_skb_any(ch->skb[ch->dma.desc]); +- ch->skb[ch->dma.desc] = skb; ++ skb_free_frag(ch->rx_buff[ch->dma.desc]); ++ ch->rx_buff[ch->dma.desc] = buf; + ret = -ENOMEM; + goto skip; + } + +- ch->dma.desc_base[ch->dma.desc].addr = mapping; ++ ch->dma.desc_base[ch->dma.desc].addr = mapping + NET_SKB_PAD + NET_IP_ALIGN; + /* Make sure the address is written before we give it to HW */ + wmb(); + skip: +@@ -210,13 +220,14 @@ static int xrx200_hw_receive(struct xrx2 + { + struct xrx200_priv *priv = ch->priv; + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +- struct sk_buff *skb = ch->skb[ch->dma.desc]; ++ void *buf = ch->rx_buff[ch->dma.desc]; + u32 ctl = desc->ctl; + int len = (ctl & LTQ_DMA_SIZE_MASK); + struct net_device *net_dev = priv->net_dev; ++ struct sk_buff *skb; + int ret; + +- ret = xrx200_alloc_skb(ch); ++ ret = xrx200_alloc_buf(ch, napi_alloc_frag); + + ch->dma.desc++; + ch->dma.desc %= LTQ_DESC_NUM; +@@ -227,19 +238,21 @@ static int xrx200_hw_receive(struct xrx2 + return ret; + } + ++ skb = build_skb(buf, priv->rx_skb_size); ++ skb_reserve(skb, NET_SKB_PAD); + skb_put(skb, len); + + /* add buffers to skb via skb->frag_list */ + if (ctl & LTQ_DMA_SOP) { + ch->skb_head = skb; + ch->skb_tail = skb; ++ skb_reserve(skb, NET_IP_ALIGN); + } else if (ch->skb_head) { + if (ch->skb_head == ch->skb_tail) + skb_shinfo(ch->skb_tail)->frag_list = skb; + else + ch->skb_tail->next = skb; + ch->skb_tail = skb; +- skb_reserve(ch->skb_tail, -NET_IP_ALIGN); + ch->skb_head->len += skb->len; + ch->skb_head->data_len += skb->len; + ch->skb_head->truesize += skb->truesize; +@@ -395,12 +408,13 @@ xrx200_change_mtu(struct net_device *net + struct xrx200_chan *ch_rx = &priv->chan_rx; + int old_mtu = net_dev->mtu; + bool running = false; +- struct sk_buff *skb; ++ void *buff; + int curr_desc; + int ret = 0; + + net_dev->mtu = new_mtu; + priv->rx_buf_size = xrx200_buffer_size(new_mtu); ++ priv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size); + + if (new_mtu <= old_mtu) + return ret; +@@ -416,14 +430,15 @@ xrx200_change_mtu(struct net_device *net + + for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; + ch_rx->dma.desc++) { +- skb = ch_rx->skb[ch_rx->dma.desc]; +- ret = xrx200_alloc_skb(ch_rx); ++ buff = ch_rx->rx_buff[ch_rx->dma.desc]; ++ ret = xrx200_alloc_buf(ch_rx, netdev_alloc_frag); + if (ret) { + net_dev->mtu = old_mtu; + priv->rx_buf_size = xrx200_buffer_size(old_mtu); ++ priv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size); + break; + } +- dev_kfree_skb_any(skb); ++ skb_free_frag(buff); + } + + ch_rx->dma.desc = curr_desc; +@@ -476,7 +491,7 @@ static int xrx200_dma_init(struct xrx200 + ltq_dma_alloc_rx(&ch_rx->dma); + for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; + ch_rx->dma.desc++) { +- ret = xrx200_alloc_skb(ch_rx); ++ ret = xrx200_alloc_buf(ch_rx, netdev_alloc_frag); + if (ret) + goto rx_free; + } +@@ -511,7 +526,7 @@ rx_ring_free: + /* free the allocated RX ring */ + for (i = 0; i < LTQ_DESC_NUM; i++) { + if (priv->chan_rx.skb[i]) +- dev_kfree_skb_any(priv->chan_rx.skb[i]); ++ skb_free_frag(priv->chan_rx.rx_buff[i]); + } + + rx_free: +@@ -528,7 +543,7 @@ static void xrx200_hw_cleanup(struct xrx + + /* free the allocated RX ring */ + for (i = 0; i < LTQ_DESC_NUM; i++) +- dev_kfree_skb_any(priv->chan_rx.skb[i]); ++ skb_free_frag(priv->chan_rx.rx_buff[i]); + } + + static int xrx200_probe(struct platform_device *pdev) +@@ -554,6 +569,7 @@ static int xrx200_probe(struct platform_ + net_dev->min_mtu = ETH_ZLEN; + net_dev->max_mtu = XRX200_DMA_DATA_LEN - xrx200_max_frame_len(0); + priv->rx_buf_size = xrx200_buffer_size(ETH_DATA_LEN); ++ priv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size); + + /* load the memory ranges */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/target/linux/lantiq/patches-5.15/0716-v5.17-net-lantiq_xrx200-fix-use-after-free-bug.patch b/target/linux/lantiq/patches-5.15/0716-v5.17-net-lantiq_xrx200-fix-use-after-free-bug.patch new file mode 100644 index 0000000000..090b7e3111 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0716-v5.17-net-lantiq_xrx200-fix-use-after-free-bug.patch @@ -0,0 +1,30 @@ +From dd830aed23c6e07cd8e2a163742bf3d63c9add08 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Sat, 5 Mar 2022 12:20:39 +0100 +Subject: net: lantiq_xrx200: fix use after free bug + +The skb->len field is read after the packet is sent to the network +stack. In the meantime, skb can be freed. This patch fixes this bug. + +Fixes: c3e6b2c35b34 ("net: lantiq_xrx200: add ingress SG DMA support") +Reported-by: Eric Dumazet +Signed-off-by: Aleksander Jan Bajkowski +Acked-by: Hauke Mehrtens +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/lantiq_xrx200.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -260,9 +260,9 @@ static int xrx200_hw_receive(struct xrx2 + + if (ctl & LTQ_DMA_EOP) { + ch->skb_head->protocol = eth_type_trans(ch->skb_head, net_dev); +- netif_receive_skb(ch->skb_head); + net_dev->stats.rx_packets++; + net_dev->stats.rx_bytes += ch->skb_head->len; ++ netif_receive_skb(ch->skb_head); + ch->skb_head = NULL; + ch->skb_tail = NULL; + ret = XRX200_DMA_PACKET_COMPLETE; diff --git a/target/linux/lantiq/patches-5.15/0717-v6.0-net-lantiq_xrx200-confirm-skb-is-allocated-before-us.patch b/target/linux/lantiq/patches-5.15/0717-v6.0-net-lantiq_xrx200-confirm-skb-is-allocated-before-us.patch new file mode 100644 index 0000000000..9eaec58033 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0717-v6.0-net-lantiq_xrx200-confirm-skb-is-allocated-before-us.patch @@ -0,0 +1,33 @@ +From c8b043702dc0894c07721c5b019096cebc8c798f Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Wed, 24 Aug 2022 23:54:06 +0200 +Subject: [PATCH] net: lantiq_xrx200: confirm skb is allocated before using + +xrx200_hw_receive() assumes build_skb() always works and goes straight +to skb_reserve(). However, build_skb() can fail under memory pressure. + +Add a check in case build_skb() failed to allocate and return NULL. + +Fixes: e015593573b3 ("net: lantiq_xrx200: convert to build_skb") +Reported-by: Eric Dumazet +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/lantiq_xrx200.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -239,6 +239,12 @@ static int xrx200_hw_receive(struct xrx2 + } + + skb = build_skb(buf, priv->rx_skb_size); ++ if (!skb) { ++ skb_free_frag(buf); ++ net_dev->stats.rx_dropped++; ++ return -ENOMEM; ++ } ++ + skb_reserve(skb, NET_SKB_PAD); + skb_put(skb, len); + diff --git a/target/linux/lantiq/patches-5.15/0718-v6.0-net-lantiq_xrx200-fix-lock-under-memory-pressure.patch b/target/linux/lantiq/patches-5.15/0718-v6.0-net-lantiq_xrx200-fix-lock-under-memory-pressure.patch new file mode 100644 index 0000000000..929ae57ace --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0718-v6.0-net-lantiq_xrx200-fix-lock-under-memory-pressure.patch @@ -0,0 +1,33 @@ +From c4b6e9341f930e4dd089231c0414758f5f1f9dbd Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Wed, 24 Aug 2022 23:54:07 +0200 +Subject: [PATCH] net: lantiq_xrx200: fix lock under memory pressure + +When the xrx200_hw_receive() function returns -ENOMEM, the NAPI poll +function immediately returns an error. +This is incorrect for two reasons: +* the function terminates without enabling interrupts or scheduling NAPI, +* the error code (-ENOMEM) is returned instead of the number of received +packets. + +After the first memory allocation failure occurs, packet reception is +locked due to disabled interrupts from DMA.. + +Fixes: fe1a56420cf2 ("net: lantiq: Add Lantiq / Intel VRX200 Ethernet driver") +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/lantiq_xrx200.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -294,7 +294,7 @@ static int xrx200_poll_rx(struct napi_st + if (ret == XRX200_DMA_PACKET_IN_PROGRESS) + continue; + if (ret != XRX200_DMA_PACKET_COMPLETE) +- return ret; ++ break; + rx++; + } else { + break; diff --git a/target/linux/lantiq/patches-5.15/0719-v6.0-net-lantiq_xrx200-restore-buffer-if-memory-allocatio.patch b/target/linux/lantiq/patches-5.15/0719-v6.0-net-lantiq_xrx200-restore-buffer-if-memory-allocatio.patch new file mode 100644 index 0000000000..182da58ed9 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0719-v6.0-net-lantiq_xrx200-restore-buffer-if-memory-allocatio.patch @@ -0,0 +1,27 @@ +From c9c3b1775f80fa21f5bff874027d2ccb10f5d90c Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Wed, 24 Aug 2022 23:54:08 +0200 +Subject: [PATCH] net: lantiq_xrx200: restore buffer if memory allocation + failed + +In a situation where memory allocation fails, an invalid buffer address +is stored. When this descriptor is used again, the system panics in the +build_skb() function when accessing memory. + +Fixes: 7ea6cd16f159 ("lantiq: net: fix duplicated skb in rx descriptor ring") +Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/lantiq_xrx200.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -193,6 +193,7 @@ static int xrx200_alloc_buf(struct xrx20 + + ch->rx_buff[ch->dma.desc] = alloc(priv->rx_skb_size); + if (!ch->rx_buff[ch->dma.desc]) { ++ ch->rx_buff[ch->dma.desc] = buf; + ret = -ENOMEM; + goto skip; + } diff --git a/target/linux/lantiq/xrx200/config-5.15 b/target/linux/lantiq/xrx200/config-5.15 new file mode 100644 index 0000000000..4dfd55274a --- /dev/null +++ b/target/linux/lantiq/xrx200/config-5.15 @@ -0,0 +1,93 @@ +CONFIG_AT803X_PHY=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin" +CONFIG_EXTRA_FIRMWARE_DIR="firmware" +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GRO_CELLS=y +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_ICPLUS_PHY=y +CONFIG_IFX_VPE_EXT=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +CONFIG_INTEL_XWAY_PHY=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_XRX200=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MIPS_MT=y +# CONFIG_MIPS_MT_FPAFF is not set +CONFIG_MIPS_MT_SMP=y +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MIPS_VPE_APSP_API=y +CONFIG_MIPS_VPE_APSP_API_MT=y +CONFIG_MIPS_VPE_LOADER=y +CONFIG_MIPS_VPE_LOADER_MT=y +CONFIG_MIPS_VPE_LOADER_TOM=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MTD_NAND_XWAY=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_LANTIQ_GSWIP=y +CONFIG_NET_DSA_TAG_GSWIP=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NLS=y +CONFIG_NR_CPUS=2 +CONFIG_PADATA=y +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_LANTIQ=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_PHY_LANTIQ_VRX200_PCIE=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_SENSORS_LTQ_CPUTEMP=y +CONFIG_SGL_ALLOC=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SOC_XWAY=y +CONFIG_SYNC_R4K=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/lantiq/xway/config-5.15 b/target/linux/lantiq/xway/config-5.15 new file mode 100644 index 0000000000..8ff706fea9 --- /dev/null +++ b/target/linux/lantiq/xway/config-5.15 @@ -0,0 +1,46 @@ +CONFIG_ADM6996_PHY=y +CONFIG_AR8216_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LZO=y +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HW_RANDOM=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_ETOP=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_XWAY=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NLS=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_PSB6970_PHY=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTL8306_PHY=y +CONFIG_RTL8366RB_PHY=y +CONFIG_RTL8366_SMI=y +CONFIG_SGL_ALLOC=y +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SOC_XWAY=y +CONFIG_SWCONFIG=y +CONFIG_UBIFS_FS=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y diff --git a/target/linux/lantiq/xway_legacy/config-5.15 b/target/linux/lantiq/xway_legacy/config-5.15 new file mode 100644 index 0000000000..c177d2a935 --- /dev/null +++ b/target/linux/lantiq/xway_legacy/config-5.15 @@ -0,0 +1,33 @@ +CONFIG_ADM6996_PHY=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_GENERIC_ALLOCATOR=y +# CONFIG_GPIO_SYSFS is not set +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_ETOP=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_NLS=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTL8306_PHY=y +CONFIG_SGL_ALLOC=y +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SOC_XWAY=y +CONFIG_SWCONFIG=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y From d374e0346ecedf21b808c07260b31ae3a90f4653 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 21 Mar 2022 18:39:03 +0100 Subject: [PATCH 15/80] lantiq: 5.15: refresh patches 0001-MIPS-lantiq-add-pcie-driver.patch needs to drop MODULE_SUPPORTED_DEVICE because that macro is gone on newer kernels. Add checks for copy_{to,from}_user in 0008-MIPS-lantiq-backport-old-timer-code.patch which is now mandatory. 0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch get dropped because it's a backport from Linux 5.13. All other patches are refreshed. Signed-off-by: Martin Blumenstingl --- .../0001-MIPS-lantiq-add-pcie-driver.patch | 12 +- .../0004-MIPS-lantiq-add-atm-hack.patch | 6 +- ...-MIPS-lantiq-backport-old-timer-code.patch | 44 +-- ...T-PHY-add-led-support-for-intel-xway.patch | 12 +- ...PS-lantiq-add-FALC-ON-i2c-bus-master.patch | 2 +- ...e-lantiq-settings-match-vendor-drive.patch | 6 +- .../lantiq/patches-5.15/0152-lantiq-VPE.patch | 4 +- ...make-the-burst-length-configurable-b.patch | 4 +- ...le-all-hardware-interrupts-on-second.patch | 4 +- ...-lantiq-add-support-for-jumbo-frames.patch | 4 +- ...q_xrx200-increase-buffer-reservation.patch | 4 +- ...llow-to-use-all-GPHYs-on-xRX300-and-.patch | 275 ------------------ ...-lantiq-enable-jumbo-frames-on-GSWIP.patch | 16 +- ...gure-the-burst-length-in-ethernet-dr.patch | 2 +- ...x200-Hardcode-the-burst-length-value.patch | 2 +- ...tiq_xrx200-increase-napi-poll-weigth.patch | 2 +- ...t-lantiq_xrx200-convert-to-build_skb.patch | 4 +- 17 files changed, 66 insertions(+), 337 deletions(-) delete mode 100644 target/linux/lantiq/patches-5.15/0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch diff --git a/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch index 99bed24cfd..2276b38c6e 100644 --- a/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch +++ b/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch @@ -242,7 +242,7 @@ Signed-off-by: John Crispin + --- /dev/null +++ b/arch/mips/pci/ifxmips_pcie.c -@@ -0,0 +1,1092 @@ +@@ -0,0 +1,1091 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published @@ -1332,7 +1332,6 @@ Signed-off-by: John Crispin + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); -+MODULE_SUPPORTED_DEVICE("Infineon builtin PCIe RC module"); +MODULE_DESCRIPTION("Infineon builtin PCIe RC driver"); + --- /dev/null @@ -1764,7 +1763,7 @@ Signed-off-by: John Crispin +#endif /* IFXMIPS_PCIE_AR10_H */ --- /dev/null +++ b/arch/mips/pci/ifxmips_pcie_msi.c -@@ -0,0 +1,392 @@ +@@ -0,0 +1,391 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_pcie_msi.c @@ -2154,7 +2153,6 @@ Signed-off-by: John Crispin + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); -+MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module"); +MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); + --- /dev/null @@ -4134,7 +4132,7 @@ Signed-off-by: John Crispin + --- a/arch/mips/pci/pci-legacy.c +++ b/arch/mips/pci/pci-legacy.c -@@ -313,3 +313,30 @@ char *__init pcibios_setup(char *str) +@@ -305,3 +305,30 @@ char *__init pcibios_setup(char *str) return pcibios_plat_setup(str); return str; } @@ -5481,7 +5479,7 @@ Signed-off-by: John Crispin (transaction layer end-to-end CRC checking). --- a/include/linux/pci.h +++ b/include/linux/pci.h -@@ -1420,6 +1420,8 @@ void pci_walk_bus(struct pci_bus *top, i +@@ -1480,6 +1480,8 @@ void pci_walk_bus(struct pci_bus *top, i void *userdata); int pci_cfg_space_size(struct pci_dev *dev); unsigned char pci_bus_max_busnr(struct pci_bus *bus); @@ -5492,7 +5490,7 @@ Signed-off-by: John Crispin unsigned long type); --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h -@@ -1079,6 +1079,12 @@ +@@ -1085,6 +1085,12 @@ #define PCI_DEVICE_ID_SGI_IOC3 0x0003 #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 diff --git a/target/linux/lantiq/patches-5.15/0004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-5.15/0004-MIPS-lantiq-add-atm-hack.patch index e215df60ee..e32e4e2daa 100644 --- a/target/linux/lantiq/patches-5.15/0004-MIPS-lantiq-add-atm-hack.patch +++ b/target/linux/lantiq/patches-5.15/0004-MIPS-lantiq-add-atm-hack.patch @@ -423,7 +423,7 @@ Signed-off-by: John Crispin + --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c -@@ -12,6 +12,7 @@ +@@ -13,6 +13,7 @@ #include #include #include @@ -431,7 +431,7 @@ Signed-off-by: John Crispin #include #include -@@ -91,6 +92,7 @@ void ltq_disable_irq(struct irq_data *d) +@@ -92,6 +93,7 @@ void ltq_disable_irq(struct irq_data *d) } raw_spin_unlock_irqrestore(<q_icu_lock, flags); } @@ -441,7 +441,7 @@ Signed-off-by: John Crispin { --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c -@@ -61,6 +61,10 @@ void (*_dma_cache_wback_inv)(unsigned lo +@@ -63,6 +63,10 @@ void (*_dma_cache_wback_inv)(unsigned lo void (*_dma_cache_wback)(unsigned long start, unsigned long size); void (*_dma_cache_inv)(unsigned long start, unsigned long size); diff --git a/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch index 1d869afd9a..16b87ed0a5 100644 --- a/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch +++ b/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch @@ -186,7 +186,7 @@ Signed-off-by: John Crispin obj-y += vmmc.o --- /dev/null +++ b/arch/mips/lantiq/xway/timer.c -@@ -0,0 +1,846 @@ +@@ -0,0 +1,852 @@ +#ifndef CONFIG_SOC_AMAZON_SE + +#include @@ -883,7 +883,8 @@ Signed-off-by: John Crispin + + if (!access_ok((void __user *)arg, sizeof(struct gptu_ioctl_param))) + return -EFAULT; -+ copy_from_user(¶m, (void __user *)arg, sizeof(param)); ++ if (copy_from_user(¶m, (void __user *)arg, sizeof(param))) ++ return -EFAULT; + + if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER + || GPTU_SET_COUNTER) && param.timer < 2) @@ -898,9 +899,11 @@ Signed-off-by: John Crispin + (unsigned long) param.pid, + (unsigned long) param.sig); + if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; ++ if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret))) ++ ret = -EFAULT; ++ else ++ ret = 0; + } + break; + case GPTU_FREE_TIMER: @@ -914,21 +917,20 @@ Signed-off-by: John Crispin + break; + case GPTU_GET_COUNT_VALUE: + ret = lq_get_count_value(param.timer, ¶m.value); -+ if (!ret) -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ value, ¶m.value, -+ sizeof(param.value)); ++ if (!ret && copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value,sizeof(param.value))) ++ ret = -EFAULT; + break; + case GPTU_CALCULATE_DIVIDER: + param.value = lq_cal_divider(param.value); + if (param.value == 0) + ret = -EINVAL; -+ else { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ else if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> + value, ¶m.value, -+ sizeof(param.value)); ++ sizeof(param.value))) ++ ret = -EFAULT; ++ else + ret = 0; -+ } + break; + case GPTU_SET_TIMER: + ret = lq_set_timer(param.timer, param.value, @@ -942,17 +944,21 @@ Signed-off-by: John Crispin + (unsigned long) param.pid, + (unsigned long) param.sig); + if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; ++ if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret))) ++ ret = -EFAULT; ++ else ++ ret = 0; + } + break; + case GPTU_SET_COUNTER: + lq_set_counter(param.timer, param.flag, param.value, 0, 0); + if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; ++ if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret))) ++ ret = -EFAULT; ++ else ++ ret = 0; + } + break; + default: diff --git a/target/linux/lantiq/patches-5.15/0023-NET-PHY-add-led-support-for-intel-xway.patch b/target/linux/lantiq/patches-5.15/0023-NET-PHY-add-led-support-for-intel-xway.patch index fb8d975110..fcc760b911 100644 --- a/target/linux/lantiq/patches-5.15/0023-NET-PHY-add-led-support-for-intel-xway.patch +++ b/target/linux/lantiq/patches-5.15/0023-NET-PHY-add-led-support-for-intel-xway.patch @@ -13,9 +13,9 @@ Signed-off-by: John Crispin --- a/drivers/net/phy/intel-xway.c +++ b/drivers/net/phy/intel-xway.c -@@ -157,6 +157,51 @@ - #define PHY_ID_PHY11G_VR9_1_2 0xD565A409 - #define PHY_ID_PHY22F_VR9_1_2 0xD565A419 +@@ -229,6 +229,51 @@ static int xway_gphy_rgmii_init(struct p + XWAY_MDIO_MIICTRL_TXSKEW_MASK, val); + } +#if IS_ENABLED(CONFIG_OF_MDIO) +static int vr9_gphy_of_reg_init(struct phy_device *phydev) @@ -65,9 +65,9 @@ Signed-off-by: John Crispin static int xway_gphy_config_init(struct phy_device *phydev) { int err; -@@ -204,6 +249,7 @@ static int xway_gphy_config_init(struct - phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); - phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); +@@ -280,6 +325,7 @@ static int xway_gphy_config_init(struct + if (err) + return err; + vr9_gphy_of_reg_init(phydev); return 0; diff --git a/target/linux/lantiq/patches-5.15/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-5.15/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch index 154cf226c1..2d3b4e2996 100644 --- a/target/linux/lantiq/patches-5.15/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch +++ b/target/linux/lantiq/patches-5.15/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch @@ -18,7 +18,7 @@ Signed-off-by: John Crispin --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig -@@ -753,6 +753,16 @@ config I2C_MESON +@@ -757,6 +757,16 @@ config I2C_MESON If you say yes to this option, support will be included for the I2C interface on the Amlogic Meson family of SoCs. diff --git a/target/linux/lantiq/patches-5.15/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch b/target/linux/lantiq/patches-5.15/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch index 333a2e6377..6615a9edbf 100644 --- a/target/linux/lantiq/patches-5.15/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch +++ b/target/linux/lantiq/patches-5.15/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch @@ -23,7 +23,7 @@ Signed-off-by: Hauke Mehrtens --- a/drivers/usb/dwc2/params.c +++ b/drivers/usb/dwc2/params.c -@@ -92,7 +92,14 @@ static void dwc2_set_rk_params(struct dw +@@ -93,7 +93,14 @@ static void dwc2_set_rk_params(struct dw p->power_down = DWC2_POWER_DOWN_PARAM_NONE; } @@ -39,7 +39,7 @@ Signed-off-by: Hauke Mehrtens { struct dwc2_core_params *p = &hsotg->params; -@@ -100,12 +107,20 @@ static void dwc2_set_ltq_params(struct d +@@ -101,12 +108,20 @@ static void dwc2_set_ltq_params(struct d p->host_rx_fifo_size = 288; p->host_nperio_tx_fifo_size = 128; p->host_perio_tx_fifo_size = 96; @@ -62,7 +62,7 @@ Signed-off-by: Hauke Mehrtens static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) { struct dwc2_core_params *p = &hsotg->params; -@@ -196,8 +211,11 @@ const struct of_device_id dwc2_of_match_ +@@ -205,8 +220,11 @@ const struct of_device_id dwc2_of_match_ { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, diff --git a/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch index 71e9886d2e..34fe761d1e 100644 --- a/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch +++ b/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch @@ -1,6 +1,6 @@ --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -2434,6 +2434,12 @@ config MIPS_VPE_LOADER +@@ -2429,6 +2429,12 @@ config MIPS_VPE_LOADER Includes a loader for loading an elf relocatable object onto another VPE and running it. @@ -15,7 +15,7 @@ default "y" --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h -@@ -127,4 +127,13 @@ void cleanup_tc(struct tc *tc); +@@ -124,4 +124,13 @@ void cleanup_tc(struct tc *tc); int __init vpe_module_init(void); void __exit vpe_module_exit(void); diff --git a/target/linux/lantiq/patches-5.15/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch b/target/linux/lantiq/patches-5.15/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch index 33c06e9d77..4f3210a6c3 100644 --- a/target/linux/lantiq/patches-5.15/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch +++ b/target/linux/lantiq/patches-5.15/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch @@ -26,7 +26,7 @@ Signed-off-by: David S. Miller #endif --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c -@@ -181,7 +181,7 @@ ltq_dma_free(struct ltq_dma_channel *ch) +@@ -182,7 +182,7 @@ ltq_dma_free(struct ltq_dma_channel *ch) EXPORT_SYMBOL_GPL(ltq_dma_free); void @@ -35,7 +35,7 @@ Signed-off-by: David S. Miller { ltq_dma_w32(p, LTQ_DMA_PS); switch (p) { -@@ -190,16 +190,44 @@ ltq_dma_init_port(int p) +@@ -191,16 +191,44 @@ ltq_dma_init_port(int p) * Tell the DMA engine to swap the endianness of data frames and * drop packets if the channel arbitration fails. */ diff --git a/target/linux/lantiq/patches-5.15/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch b/target/linux/lantiq/patches-5.15/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch index 0ac9adfb96..ad7f781e21 100644 --- a/target/linux/lantiq/patches-5.15/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch +++ b/target/linux/lantiq/patches-5.15/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch @@ -53,7 +53,7 @@ Signed-off-by: Aleksander Jan Bajkowski const char *get_system_type(void) { return soc_info.sys_type; -@@ -100,6 +108,17 @@ void __init device_tree_init(void) +@@ -93,6 +101,17 @@ void __init device_tree_init(void) unflatten_and_copy_device_tree(); } @@ -71,7 +71,7 @@ Signed-off-by: Aleksander Jan Bajkowski void __init prom_init(void) { /* call the soc specific detetcion code and get it to fill soc_info */ -@@ -111,7 +130,10 @@ void __init prom_init(void) +@@ -104,7 +123,10 @@ void __init prom_init(void) prom_init_cmdline(); #if defined(CONFIG_MIPS_MT_SMP) diff --git a/target/linux/lantiq/patches-5.15/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch b/target/linux/lantiq/patches-5.15/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch index 5bbf752dba..4a4109c772 100644 --- a/target/linux/lantiq/patches-5.15/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch +++ b/target/linux/lantiq/patches-5.15/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch @@ -134,7 +134,7 @@ Signed-off-by: David S. Miller .ndo_set_mac_address = eth_mac_addr, .ndo_validate_addr = eth_validate_addr, }; -@@ -454,7 +504,7 @@ static int xrx200_probe(struct platform_ +@@ -453,7 +503,7 @@ static int xrx200_probe(struct platform_ net_dev->netdev_ops = &xrx200_netdev_ops; SET_NETDEV_DEV(net_dev, dev); net_dev->min_mtu = ETH_ZLEN; @@ -142,4 +142,4 @@ Signed-off-by: David S. Miller + net_dev->max_mtu = XRX200_DMA_DATA_LEN - VLAN_ETH_HLEN - ETH_FCS_LEN; /* load the memory ranges */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->pmac_reg = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); diff --git a/target/linux/lantiq/patches-5.15/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch b/target/linux/lantiq/patches-5.15/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch index 77c0eb6354..c197b1a1c9 100644 --- a/target/linux/lantiq/patches-5.15/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch +++ b/target/linux/lantiq/patches-5.15/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch @@ -110,7 +110,7 @@ Signed-off-by: Jakub Kicinski break; } dev_kfree_skb_any(skb); -@@ -504,7 +517,8 @@ static int xrx200_probe(struct platform_ +@@ -503,7 +516,8 @@ static int xrx200_probe(struct platform_ net_dev->netdev_ops = &xrx200_netdev_ops; SET_NETDEV_DEV(net_dev, dev); net_dev->min_mtu = ETH_ZLEN; @@ -119,4 +119,4 @@ Signed-off-by: Jakub Kicinski + priv->rx_buf_size = xrx200_buffer_size(ETH_DATA_LEN); /* load the memory ranges */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->pmac_reg = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); diff --git a/target/linux/lantiq/patches-5.15/0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch b/target/linux/lantiq/patches-5.15/0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch deleted file mode 100644 index a69f682c03..0000000000 --- a/target/linux/lantiq/patches-5.15/0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch +++ /dev/null @@ -1,275 +0,0 @@ -From a09d042b086202735c4ed64573cdd79933020001 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Mon, 22 Mar 2021 21:37:15 +0100 -Subject: [PATCH] net: dsa: lantiq: allow to use all GPHYs on xRX300 and xRX330 - -This patch allows to use all PHYs on GRX300 and GRX330. The ARX300 -has 3 and the GRX330 has 4 integrated PHYs connected to different -ports compared to VRX200. Each integrated PHY can work as single -Gigabit Ethernet PHY (GMII) or as double Fast Ethernet PHY (MII). - -Allowed port configurations: - -xRX200: -GMAC0: RGMII, MII, REVMII or RMII port -GMAC1: RGMII, MII, REVMII or RMII port -GMAC2: GPHY0 (GMII) -GMAC3: GPHY0 (MII) -GMAC4: GPHY1 (GMII) -GMAC5: GPHY1 (MII) or RGMII port - -xRX300: -GMAC0: RGMII port -GMAC1: GPHY2 (GMII) -GMAC2: GPHY0 (GMII) -GMAC3: GPHY0 (MII) -GMAC4: GPHY1 (GMII) -GMAC5: GPHY1 (MII) or RGMII port - -xRX330: -GMAC0: RGMII, GMII or RMII port -GMAC1: GPHY2 (GMII) -GMAC2: GPHY0 (GMII) -GMAC3: GPHY0 (MII) or GPHY3 (GMII) -GMAC4: GPHY1 (GMII) -GMAC5: GPHY1 (MII), RGMII or RMII port - -Tested on D-Link DWR966 (xRX330) with OpenWRT. - -Signed-off-by: Aleksander Jan Bajkowski -Acked-by: Hauke Mehrtens -Signed-off-by: David S. Miller ---- - drivers/net/dsa/lantiq_gswip.c | 142 ++++++++++++++++++++++++++------- - 1 file changed, 113 insertions(+), 29 deletions(-) - ---- a/drivers/net/dsa/lantiq_gswip.c -+++ b/drivers/net/dsa/lantiq_gswip.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0 - /* -- * Lantiq / Intel GSWIP switch driver for VRX200 SoCs -+ * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs - * - * Copyright (C) 2010 Lantiq Deutschland - * Copyright (C) 2012 John Crispin -@@ -104,6 +104,7 @@ - #define GSWIP_MII_CFG_MODE_RMIIP 0x2 - #define GSWIP_MII_CFG_MODE_RMIIM 0x3 - #define GSWIP_MII_CFG_MODE_RGMII 0x4 -+#define GSWIP_MII_CFG_MODE_GMII 0x9 - #define GSWIP_MII_CFG_MODE_MASK 0xf - #define GSWIP_MII_CFG_RATE_M2P5 0x00 - #define GSWIP_MII_CFG_RATE_M25 0x10 -@@ -241,6 +242,7 @@ - struct gswip_hw_info { - int max_ports; - int cpu_port; -+ const struct dsa_switch_ops *ops; - }; - - struct xway_gphy_match_data { -@@ -1438,12 +1440,42 @@ static int gswip_port_fdb_dump(struct ds - return 0; - } - --static void gswip_phylink_validate(struct dsa_switch *ds, int port, -- unsigned long *supported, -- struct phylink_link_state *state) -+static void gswip_phylink_set_capab(unsigned long *supported, -+ struct phylink_link_state *state) - { - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - -+ /* Allow all the expected bits */ -+ phylink_set(mask, Autoneg); -+ phylink_set_port_modes(mask); -+ phylink_set(mask, Pause); -+ phylink_set(mask, Asym_Pause); -+ -+ /* With the exclusion of MII, Reverse MII and Reduced MII, we -+ * support Gigabit, including Half duplex -+ */ -+ if (state->interface != PHY_INTERFACE_MODE_MII && -+ state->interface != PHY_INTERFACE_MODE_REVMII && -+ state->interface != PHY_INTERFACE_MODE_RMII) { -+ phylink_set(mask, 1000baseT_Full); -+ phylink_set(mask, 1000baseT_Half); -+ } -+ -+ phylink_set(mask, 10baseT_Half); -+ phylink_set(mask, 10baseT_Full); -+ phylink_set(mask, 100baseT_Half); -+ phylink_set(mask, 100baseT_Full); -+ -+ bitmap_and(supported, supported, mask, -+ __ETHTOOL_LINK_MODE_MASK_NBITS); -+ bitmap_and(state->advertising, state->advertising, mask, -+ __ETHTOOL_LINK_MODE_MASK_NBITS); -+} -+ -+static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port, -+ unsigned long *supported, -+ struct phylink_link_state *state) -+{ - switch (port) { - case 0: - case 1: -@@ -1470,38 +1502,54 @@ static void gswip_phylink_validate(struc - return; - } - -- /* Allow all the expected bits */ -- phylink_set(mask, Autoneg); -- phylink_set_port_modes(mask); -- phylink_set(mask, Pause); -- phylink_set(mask, Asym_Pause); -+ gswip_phylink_set_capab(supported, state); - -- /* With the exclusion of MII, Reverse MII and Reduced MII, we -- * support Gigabit, including Half duplex -- */ -- if (state->interface != PHY_INTERFACE_MODE_MII && -- state->interface != PHY_INTERFACE_MODE_REVMII && -- state->interface != PHY_INTERFACE_MODE_RMII) { -- phylink_set(mask, 1000baseT_Full); -- phylink_set(mask, 1000baseT_Half); -+ return; -+ -+unsupported: -+ bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); -+ dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", -+ phy_modes(state->interface), port); -+} -+ -+static void gswip_xrx300_phylink_validate(struct dsa_switch *ds, int port, -+ unsigned long *supported, -+ struct phylink_link_state *state) -+{ -+ switch (port) { -+ case 0: -+ if (!phy_interface_mode_is_rgmii(state->interface) && -+ state->interface != PHY_INTERFACE_MODE_GMII && -+ state->interface != PHY_INTERFACE_MODE_RMII) -+ goto unsupported; -+ break; -+ case 1: -+ case 2: -+ case 3: -+ case 4: -+ if (state->interface != PHY_INTERFACE_MODE_INTERNAL) -+ goto unsupported; -+ break; -+ case 5: -+ if (!phy_interface_mode_is_rgmii(state->interface) && -+ state->interface != PHY_INTERFACE_MODE_INTERNAL && -+ state->interface != PHY_INTERFACE_MODE_RMII) -+ goto unsupported; -+ break; -+ default: -+ bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); -+ dev_err(ds->dev, "Unsupported port: %i\n", port); -+ return; - } - -- phylink_set(mask, 10baseT_Half); -- phylink_set(mask, 10baseT_Full); -- phylink_set(mask, 100baseT_Half); -- phylink_set(mask, 100baseT_Full); -+ gswip_phylink_set_capab(supported, state); - -- bitmap_and(supported, supported, mask, -- __ETHTOOL_LINK_MODE_MASK_NBITS); -- bitmap_and(state->advertising, state->advertising, mask, -- __ETHTOOL_LINK_MODE_MASK_NBITS); - return; - - unsupported: - bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); - dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", - phy_modes(state->interface), port); -- return; - } - - static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) -@@ -1636,6 +1684,9 @@ static void gswip_phylink_mac_config(str - case PHY_INTERFACE_MODE_RGMII_TXID: - miicfg |= GSWIP_MII_CFG_MODE_RGMII; - break; -+ case PHY_INTERFACE_MODE_GMII: -+ miicfg |= GSWIP_MII_CFG_MODE_GMII; -+ break; - default: - dev_err(ds->dev, - "Unsupported interface: %d\n", state->interface); -@@ -1762,7 +1813,7 @@ static int gswip_get_sset_count(struct d - return ARRAY_SIZE(gswip_rmon_cnt); - } - --static const struct dsa_switch_ops gswip_switch_ops = { -+static const struct dsa_switch_ops gswip_xrx200_switch_ops = { - .get_tag_protocol = gswip_get_tag_protocol, - .setup = gswip_setup, - .port_enable = gswip_port_enable, -@@ -1778,7 +1829,31 @@ static const struct dsa_switch_ops gswip - .port_fdb_add = gswip_port_fdb_add, - .port_fdb_del = gswip_port_fdb_del, - .port_fdb_dump = gswip_port_fdb_dump, -- .phylink_validate = gswip_phylink_validate, -+ .phylink_validate = gswip_xrx200_phylink_validate, -+ .phylink_mac_config = gswip_phylink_mac_config, -+ .phylink_mac_link_down = gswip_phylink_mac_link_down, -+ .phylink_mac_link_up = gswip_phylink_mac_link_up, -+ .get_strings = gswip_get_strings, -+ .get_ethtool_stats = gswip_get_ethtool_stats, -+ .get_sset_count = gswip_get_sset_count, -+}; -+ -+static const struct dsa_switch_ops gswip_xrx300_switch_ops = { -+ .get_tag_protocol = gswip_get_tag_protocol, -+ .setup = gswip_setup, -+ .port_enable = gswip_port_enable, -+ .port_disable = gswip_port_disable, -+ .port_bridge_join = gswip_port_bridge_join, -+ .port_bridge_leave = gswip_port_bridge_leave, -+ .port_fast_age = gswip_port_fast_age, -+ .port_vlan_filtering = gswip_port_vlan_filtering, -+ .port_vlan_add = gswip_port_vlan_add, -+ .port_vlan_del = gswip_port_vlan_del, -+ .port_stp_state_set = gswip_port_stp_state_set, -+ .port_fdb_add = gswip_port_fdb_add, -+ .port_fdb_del = gswip_port_fdb_del, -+ .port_fdb_dump = gswip_port_fdb_dump, -+ .phylink_validate = gswip_xrx300_phylink_validate, - .phylink_mac_config = gswip_phylink_mac_config, - .phylink_mac_link_down = gswip_phylink_mac_link_down, - .phylink_mac_link_up = gswip_phylink_mac_link_up, -@@ -2042,7 +2117,7 @@ static int gswip_probe(struct platform_d - priv->ds->dev = dev; - priv->ds->num_ports = priv->hw_info->max_ports; - priv->ds->priv = priv; -- priv->ds->ops = &gswip_switch_ops; -+ priv->ds->ops = priv->hw_info->ops; - priv->dev = dev; - version = gswip_switch_r(priv, GSWIP_VERSION); - -@@ -2126,10 +2201,19 @@ static int gswip_remove(struct platform_ - static const struct gswip_hw_info gswip_xrx200 = { - .max_ports = 7, - .cpu_port = 6, -+ .ops = &gswip_xrx200_switch_ops, -+}; -+ -+static const struct gswip_hw_info gswip_xrx300 = { -+ .max_ports = 7, -+ .cpu_port = 6, -+ .ops = &gswip_xrx300_switch_ops, - }; - - static const struct of_device_id gswip_of_match[] = { - { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, -+ { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 }, -+ { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 }, - {}, - }; - MODULE_DEVICE_TABLE(of, gswip_of_match); diff --git a/target/linux/lantiq/patches-5.15/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch b/target/linux/lantiq/patches-5.15/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch index 49a19bebee..22aa2eea6e 100644 --- a/target/linux/lantiq/patches-5.15/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch +++ b/target/linux/lantiq/patches-5.15/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch @@ -47,7 +47,7 @@ Signed-off-by: Jakub Kicinski struct gswip_hw_info { int max_ports; int cpu_port; -@@ -858,10 +868,6 @@ static int gswip_setup(struct dsa_switch +@@ -846,10 +856,6 @@ static int gswip_setup(struct dsa_switch gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, GSWIP_PCE_PCTRL_0p(cpu_port)); @@ -58,17 +58,17 @@ Signed-off-by: Jakub Kicinski gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, GSWIP_BM_QUEUE_GCTRL); -@@ -878,6 +884,8 @@ static int gswip_setup(struct dsa_switch +@@ -866,6 +872,8 @@ static int gswip_setup(struct dsa_switch return err; } + ds->mtu_enforcement_ingress = true; + gswip_port_enable(ds, cpu_port, NULL); - return 0; - } -@@ -1472,6 +1480,39 @@ static void gswip_phylink_set_capab(unsi - __ETHTOOL_LINK_MODE_MASK_NBITS); + + ds->configure_vlan_while_not_filtering = false; +@@ -1456,6 +1464,39 @@ static void gswip_phylink_set_capab(unsi + linkmode_and(state->advertising, state->advertising, mask); } +static int gswip_port_max_mtu(struct dsa_switch *ds, int port) @@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port, unsigned long *supported, struct phylink_link_state *state) -@@ -1829,6 +1870,8 @@ static const struct dsa_switch_ops gswip +@@ -1812,6 +1853,8 @@ static const struct dsa_switch_ops gswip .port_fdb_add = gswip_port_fdb_add, .port_fdb_del = gswip_port_fdb_del, .port_fdb_dump = gswip_port_fdb_dump, @@ -116,7 +116,7 @@ Signed-off-by: Jakub Kicinski .phylink_validate = gswip_xrx200_phylink_validate, .phylink_mac_config = gswip_phylink_mac_config, .phylink_mac_link_down = gswip_phylink_mac_link_down, -@@ -1853,6 +1896,8 @@ static const struct dsa_switch_ops gswip +@@ -1836,6 +1879,8 @@ static const struct dsa_switch_ops gswip .port_fdb_add = gswip_port_fdb_add, .port_fdb_del = gswip_port_fdb_del, .port_fdb_dump = gswip_port_fdb_dump, diff --git a/target/linux/lantiq/patches-5.15/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch b/target/linux/lantiq/patches-5.15/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch index 4fb7d0767b..818fa811e9 100644 --- a/target/linux/lantiq/patches-5.15/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch +++ b/target/linux/lantiq/patches-5.15/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch @@ -105,7 +105,7 @@ Signed-off-by: David S. Miller ch_rx->dma.nr = XRX200_DMA_RX; ch_rx->dma.dev = priv->dev; -@@ -584,6 +587,18 @@ static int xrx200_probe(struct platform_ +@@ -575,6 +578,18 @@ static int xrx200_probe(struct platform_ if (err) eth_hw_addr_random(net_dev); diff --git a/target/linux/lantiq/patches-5.15/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch b/target/linux/lantiq/patches-5.15/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch index 7448af8c26..e002f81d5a 100644 --- a/target/linux/lantiq/patches-5.15/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch +++ b/target/linux/lantiq/patches-5.15/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch @@ -52,7 +52,7 @@ Signed-off-by: David S. Miller ch_rx->dma.nr = XRX200_DMA_RX; ch_rx->dma.dev = priv->dev; -@@ -587,18 +586,6 @@ static int xrx200_probe(struct platform_ +@@ -578,18 +577,6 @@ static int xrx200_probe(struct platform_ if (err) eth_hw_addr_random(net_dev); diff --git a/target/linux/lantiq/patches-5.15/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch b/target/linux/lantiq/patches-5.15/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch index 1fa49f406e..10791f9d53 100644 --- a/target/linux/lantiq/patches-5.15/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch +++ b/target/linux/lantiq/patches-5.15/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch @@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/lantiq_xrx200.c +++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -606,8 +606,10 @@ static int xrx200_probe(struct platform_ +@@ -597,8 +597,10 @@ static int xrx200_probe(struct platform_ PMAC_HD_CTL); /* setup NAPI */ diff --git a/target/linux/lantiq/patches-5.15/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch b/target/linux/lantiq/patches-5.15/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch index b2b014832c..6613d0bbd7 100644 --- a/target/linux/lantiq/patches-5.15/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch +++ b/target/linux/lantiq/patches-5.15/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch @@ -196,11 +196,11 @@ Signed-off-by: Jakub Kicinski } static int xrx200_probe(struct platform_device *pdev) -@@ -554,6 +569,7 @@ static int xrx200_probe(struct platform_ +@@ -553,6 +568,7 @@ static int xrx200_probe(struct platform_ net_dev->min_mtu = ETH_ZLEN; net_dev->max_mtu = XRX200_DMA_DATA_LEN - xrx200_max_frame_len(0); priv->rx_buf_size = xrx200_buffer_size(ETH_DATA_LEN); + priv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size); /* load the memory ranges */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->pmac_reg = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); From e4c76e6fa34b52bdbe3e7601a4ef43525fc0999b Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Tue, 3 May 2022 15:26:29 +0200 Subject: [PATCH 16/80] ltq-ifxos: add compatibility with kernel 5.15 set_fs is no longer supported since kernel 5.13 for mips. Signed-off-by: Jan Hoffmann Signed-off-by: Martin Blumenstingl --- .../lantiq/ltq-ifxos/patches/100-compat.patch | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch b/package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch index 0fc2c2c5e6..45059890e1 100644 --- a/package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch +++ b/package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch @@ -22,3 +22,71 @@ if (pVirtAddr == IFX_NULL) { IFXOS_PRN_USR_ERR_NL( IFXOS, IFXOS_PRN_LEVEL_ERR, +--- a/src/linux/ifxos_linux_socket_drv.c ++++ b/src/linux/ifxos_linux_socket_drv.c +@@ -165,8 +165,12 @@ IFX_int_t IFXOS_SocketRecvFrom( + IFXOS_sockAddr_t *pSocAddr) + { + struct msghdr msg; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,13,0) + struct iovec iov; + mm_segment_t old_fs; ++#else ++ struct kvec iov; ++#endif + int ret; + + IFXOS_RETURN_IF_POINTER_NULL(pBuffer, IFX_ERROR); +@@ -181,6 +185,8 @@ IFX_int_t IFXOS_SocketRecvFrom( + msg.msg_controllen = 0; + msg.msg_flags = 0; + ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,13,0) ++ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,19,0)) + msg.msg_iov = &iov; + msg.msg_iovlen = 1; +@@ -200,6 +206,10 @@ IFX_int_t IFXOS_SocketRecvFrom( + #endif + set_fs(old_fs); + ++#else ++ ret = kernel_recvmsg (socFd, &msg, &iov, 1, bufSize_byte, 0); ++#endif ++ + return ret; + } + +@@ -229,8 +239,12 @@ IFX_int_t IFXOS_SocketSendTo( + IFXOS_sockAddr_t *pSocAddr) + { + struct msghdr msg; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,13,0) + struct iovec iov; + mm_segment_t old_fs; ++#else ++ struct kvec iov; ++#endif + int ret; + + IFXOS_RETURN_IF_POINTER_NULL(pBuffer, IFX_ERROR); +@@ -245,6 +259,8 @@ IFX_int_t IFXOS_SocketSendTo( + msg.msg_controllen = 0; + msg.msg_flags = MSG_DONTWAIT; + ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,13,0) ++ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,19,0)) + msg.msg_iov = &iov; + msg.msg_iovlen = 1; +@@ -264,6 +280,10 @@ IFX_int_t IFXOS_SocketSendTo( + #endif + set_fs(old_fs); + ++#else ++ ret = kernel_sendmsg(socFd, &msg, &iov, 1, bufSize_byte); ++#endif ++ + return ret; + } + From d6e506eaaaef857c440e120bb6bea97773ce48c2 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 21 Mar 2022 20:05:27 +0100 Subject: [PATCH 17/80] kernel: ltq-deu: Fix compilation with Linux 5.15 struct of_device_id is not implicitly included anymore. Include to fix compilation on Linux 5.15. Also upstream commit a24d22b225ce15 ("crypto: sha - split sha.h into sha1.h and sha2.h") from Linux 5.11 moves functionality from sha.h to sha1.h. Signed-off-by: Martin Blumenstingl --- package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c | 1 + package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c | 5 +++++ package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c | 5 +++++ 3 files changed, 11 insertions(+) diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c index a102568f97..096b8b5bba 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c @@ -46,6 +46,7 @@ #include #endif #include +#include #include #include #include diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c index a20430c448..0e860b9ab5 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c @@ -43,7 +43,12 @@ #include #include #include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,11,0) #include +#else +#include +#endif #include #include #include diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c index 69504efe93..b58a91a5df 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c @@ -44,7 +44,12 @@ #include #include #include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,11,0) #include +#else +#include +#endif #include #include #include From 22fbc2d896a22701c907419f9df767e51d75693d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 21 Mar 2022 20:14:08 +0100 Subject: [PATCH 18/80] kernel: ltq-tapi: Fix compilation with Linux 5.15 MODULE_SUPPORTED_DEVICE was removed after Linux 5.10. Drop it from the driver as well. Signed-off-by: Martin Blumenstingl --- .../kernel/lantiq/ltq-tapi/patches/500-linux-509.patch | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/package/kernel/lantiq/ltq-tapi/patches/500-linux-509.patch b/package/kernel/lantiq/ltq-tapi/patches/500-linux-509.patch index 586af59d85..07f61aa632 100644 --- a/package/kernel/lantiq/ltq-tapi/patches/500-linux-509.patch +++ b/package/kernel/lantiq/ltq-tapi/patches/500-linux-509.patch @@ -34,6 +34,16 @@ } +@@ -3800,7 +3808,9 @@ module_exit (ifx_tapi_module_exit); + + MODULE_AUTHOR ("Lantiq Deutschland GmbH"); + MODULE_DESCRIPTION ("TAPI Driver - www.lantiq.com"); ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(5,10,0) + MODULE_SUPPORTED_DEVICE ("TAPI DEVICE"); ++#endif + MODULE_LICENSE ("Dual BSD/GPL"); + + EXPORT_SYMBOL (IFX_TAPI_Register_LL_Drv); --- a/src/drv_tapi_kpi.c +++ b/src/drv_tapi_kpi.c @@ -134,7 +134,11 @@ extern IFX_int32_t block_ingre From f4ce7df4fc56372f353066f4c0836b2ae1b089fd Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 21 Mar 2022 20:21:04 +0100 Subject: [PATCH 19/80] kernel: ltq-vdsl-vr9-mei: Fix compilation with Linux 5.15 The result of copy_to_user() now has to be checked explicitly. Also MODULE_SUPPORTED_DEVICE is gone after Linux 5.10. Signed-off-by: Martin Blumenstingl --- .../ltq-vdsl-vr9-mei/patches/100-compat.patch | 69 ++++++++++++++++--- .../patches/101_no-date-time.patch | 12 +++- 2 files changed, 71 insertions(+), 10 deletions(-) diff --git a/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/100-compat.patch b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/100-compat.patch index 61ea826cb4..7e7381a346 100644 --- a/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/100-compat.patch +++ b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/100-compat.patch @@ -43,7 +43,18 @@ #ifdef MODULE #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) MODULE_PARM(major_number, "b"); -@@ -1479,7 +1483,11 @@ struct proc_entry { +@@ -1256,7 +1260,9 @@ static long MEI_Ioctl( struct file *filp + MEI_IOCTL_RETURN: + + local_args.drv_ioctl.retCode = ret; +- copy_to_user( ((IOCTL_MEI_arg_t *)nArgument), &local_args, retSize); ++ if ( ret == IFX_SUCCESS && ++ copy_to_user( ((IOCTL_MEI_arg_t *)nArgument), &local_args, retSize) ) ++ ret = -e_MEI_ERR_RETURN_ARG; + + return (ret < 0) ? -1 : 0; + } +@@ -1479,7 +1485,11 @@ struct proc_entry { char name[32]; proc_rd_callback_t rd; proc_wr_callback_t wr; @@ -55,7 +66,7 @@ int entity; }; -@@ -1869,6 +1877,7 @@ static int mei_proc_single_open(struct i +@@ -1869,6 +1879,7 @@ static int mei_proc_single_open(struct i static void mei_proc_entry_create(struct proc_dir_entry *parent_node, struct proc_entry *proc_entry) { @@ -63,7 +74,7 @@ memset(&proc_entry->ops, 0, sizeof(struct file_operations)); proc_entry->ops.owner = THIS_MODULE; -@@ -1879,6 +1888,17 @@ static void mei_proc_entry_create(struct +@@ -1879,6 +1890,17 @@ static void mei_proc_entry_create(struct proc_entry->ops.llseek = seq_lseek; if (proc_entry->wr) proc_entry->ops.write = proc_entry->wr; @@ -81,7 +92,7 @@ proc_create_data(proc_entry->name, (S_IFREG | S_IRUGO), -@@ -2174,9 +2194,11 @@ static int MEI_module_init (void) +@@ -2174,9 +2196,11 @@ static int MEI_module_init (void) return (result); } @@ -93,7 +104,7 @@ return 0; } -@@ -2304,6 +2326,10 @@ static void MEI_module_exit (void) +@@ -2304,6 +2328,10 @@ static void MEI_module_exit (void) #else unregister_chrdev ( major_number , DRV_MEI_NAME ); @@ -104,7 +115,7 @@ #endif #if CONFIG_PROC_FS -@@ -2388,9 +2414,11 @@ static void MEI_module_exit (void) +@@ -2388,9 +2416,11 @@ static void MEI_module_exit (void) ("MEI_DRV: Chipset Basic Exit failed" MEI_DRV_CRLF)); } @@ -116,7 +127,7 @@ #if (MEI_SUPPORT_DEBUG_LOGGER == 1) if (nl_debug_sock) -@@ -2514,6 +2542,10 @@ static int MEI_InitModuleRegCharDev(cons +@@ -2514,6 +2544,10 @@ static int MEI_InitModuleRegCharDev(cons ("Using major number %d" MEI_DRV_CRLF, major_number)); } @@ -127,7 +138,7 @@ return 0; #endif /* CONFIG_DEVFS_FS */ } -@@ -2563,21 +2595,32 @@ static int MEI_InitModuleBasics(void) +@@ -2563,21 +2597,32 @@ static int MEI_InitModuleBasics(void) } #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)) @@ -160,7 +171,7 @@ return 0; } -@@ -2905,11 +2948,15 @@ IFX_int32_t MEI_IoctlInitDevice( +@@ -2905,11 +2950,15 @@ IFX_int32_t MEI_IoctlInitDevice( pMeiDev->eModePoll = e_MEI_DEV_ACCESS_MODE_IRQ; pMeiDev->intMask = ME_ARC2ME_INTERRUPT_UNMASK_ALL; @@ -176,6 +187,46 @@ pTmpXCntrl = MEI_VrxXDevToIrqListAdd( MEI_DRV_LINENUM_GET(pMeiDev), +@@ -3249,9 +3298,11 @@ static int MEI_IoctlMeiDbgAccessWr_Wrap( + ret = MEI_IoctlMeiDbgAccessWr( pMeiDynCntrl, pLocalArgument); + + /* return arguments - count */ +- copy_to_user( (void *)&pUserArgument->count, +- (void *)&pLocalArgument->count, +- sizeof(pUserArgument->count) ) ; ++ if ( ret == IFX_SUCCESS && ++ copy_to_user( (void *)&pUserArgument->count, ++ (void *)&pLocalArgument->count, ++ sizeof(pUserArgument->count) ) ) ++ ret = -e_MEI_ERR_RETURN_ARG; + + return ret; + } +@@ -3278,16 +3329,18 @@ static int MEI_IoctlMeiDbgAccessRd_Wrap( + if ( pLocalArgument->count ) + { + /* return the buffer */ +- copy_to_user( pUserBuf, +- pLocalArgument->pData_32, +- pLocalArgument->count * sizeof(IFX_uint32_t) ) ; ++ if ( copy_to_user( pUserBuf, ++ pLocalArgument->pData_32, ++ pLocalArgument->count * sizeof(IFX_uint32_t) ) ) ++ ret = -e_MEI_ERR_RETURN_ARG; + + } + + /* return count argument */ +- copy_to_user( (void *)&pUserArgument->count, +- (void *)&pLocalArgument->count, +- sizeof(pUserArgument->count) ) ; ++ if ( copy_to_user( (void *)&pUserArgument->count, ++ (void *)&pLocalArgument->count, ++ sizeof(pUserArgument->count) ) ) ++ ret = -e_MEI_ERR_RETURN_ARG; + + return ret; + } --- a/src/drv_mei_cpe_api_atm_ptm_intern.c +++ b/src/drv_mei_cpe_api_atm_ptm_intern.c @@ -147,6 +147,7 @@ IFX_int32_t MEI_InternalXtmSwhowtimeExit diff --git a/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/101_no-date-time.patch b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/101_no-date-time.patch index 055797ad4d..9785bfc4c1 100644 --- a/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/101_no-date-time.patch +++ b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/101_no-date-time.patch @@ -1,6 +1,6 @@ --- a/src/drv_mei_cpe_linux.c +++ b/src/drv_mei_cpe_linux.c -@@ -1503,8 +1503,8 @@ struct proc_entry { +@@ -1505,8 +1505,8 @@ struct proc_entry { static void MEI_GetVersionProc(struct seq_file *s) { seq_printf(s, "%s" MEI_DRV_CRLF, &MEI_WHATVERSION[4]); @@ -11,3 +11,13 @@ } /** +@@ -4233,7 +4233,9 @@ module_exit (MEI_module_exit); + #ifdef MODULE + MODULE_AUTHOR("www.lantiq.com"); + MODULE_DESCRIPTION("MEI CPE Driver - www.lantiq.com"); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,11,0)) + MODULE_SUPPORTED_DEVICE("MEI CPE Interface"); ++#endif + MODULE_LICENSE ("GPL"); + #endif /* #ifdef MODULE*/ + From 2964353927304997735fd27a4144e0e533a29601 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 21 Mar 2022 20:28:07 +0100 Subject: [PATCH 20/80] kernel: ltq-vmmc: Fix compilation with Linux 5.15 MODULE_SUPPORTED_DEVICE is gone after Linux 5.15. Drop it's usage on newer kernels to fix compilation with Linux 5.15. Signed-off-by: Martin Blumenstingl --- .../kernel/lantiq/ltq-vmmc/patches/200-compat.patch | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/package/kernel/lantiq/ltq-vmmc/patches/200-compat.patch b/package/kernel/lantiq/ltq-vmmc/patches/200-compat.patch index bf9f17ed05..dd6451b52d 100644 --- a/package/kernel/lantiq/ltq-vmmc/patches/200-compat.patch +++ b/package/kernel/lantiq/ltq-vmmc/patches/200-compat.patch @@ -9,6 +9,16 @@ /* ============================= */ /* Local Macros & Definitions */ /* ============================= */ +@@ -862,7 +864,9 @@ void vmmc_module_exit(void) + #ifdef MODULE + MODULE_DESCRIPTION("VMMC(VoiceMacroMipsCore) device driver - www.lantiq.com"); + MODULE_AUTHOR("Lantiq Deutschland GmbH"); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,11,0)) + MODULE_SUPPORTED_DEVICE("DANUBE, TWINPASS, INCA-IP2, AR9, VR9"); ++#endif + MODULE_LICENSE("Dual BSD/GPL"); + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17)) --- a/src/mps/drv_mps_vmmc_linux.c +++ b/src/mps/drv_mps_vmmc_linux.c @@ -80,11 +80,15 @@ From a075ddb8ca8febefc6f61befb508cb2c42e08bbb Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 26 Mar 2022 11:19:04 +0100 Subject: [PATCH 21/80] kernel: ltq-adsl-mei: Fix compilation with Linux 5.15 struct of_device_id is not implicitly included anymore. Include to fix compilation on Linux 5.15. Signed-off-by: Martin Blumenstingl --- package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c | 1 + 1 file changed, 1 insertion(+) diff --git a/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c b/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c index df04de73e0..2339d919b6 100644 --- a/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c +++ b/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c @@ -28,6 +28,7 @@ #include #include +#include #include #include #include From d4571e98ab0ed444c02bcdb25128109b73da5f6c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 21 Mar 2022 20:31:23 +0100 Subject: [PATCH 22/80] lantiq: Add Linux 5.15 as testing kernel version Signed-off-by: Martin Blumenstingl --- target/linux/lantiq/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/lantiq/Makefile b/target/linux/lantiq/Makefile index 89f457ec5f..08618fa9a3 100644 --- a/target/linux/lantiq/Makefile +++ b/target/linux/lantiq/Makefile @@ -10,7 +10,7 @@ FEATURES:=squashfs SUBTARGETS:=xrx200 xway xway_legacy falcon ase KERNEL_PATCHVER:=5.10 -KERNEL_TESTING_PATCHVER:=5.10 +KERNEL_TESTING_PATCHVER:=5.15 define Target/Description Build firmware images for Lantiq SoC From 3c0c775cabe7054cfd53e1eece5f73a4087cc2d7 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 21 Oct 2022 21:51:05 +0200 Subject: [PATCH 23/80] mtd-utils: update to 2.1.5 Release Notes: https://lore.kernel.org/buildroot/c0992bbb-9487-9a51-ea9f-39cf074b61ec@sigma-star.at/ Refresh patches: - 130-lzma_jffs2.patch Signed-off-by: Nick Hainke --- package/utils/mtd-utils/Makefile | 4 ++-- package/utils/mtd-utils/patches/130-lzma_jffs2.patch | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/package/utils/mtd-utils/Makefile b/package/utils/mtd-utils/Makefile index 2f54b3ad0d..afbfbceff5 100644 --- a/package/utils/mtd-utils/Makefile +++ b/package/utils/mtd-utils/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mtd-utils -PKG_VERSION:=2.1.4 +PKG_VERSION:=2.1.5 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:=https://infraroot.at/pub/mtd/ -PKG_HASH:=2c6711d15d282c47cb3867b6857340597e26d332c238465134c602e5eef71b99 +PKG_HASH:=386e27fd121699b6b729bc2e8e04dda987b31cca6b16e12fb6cc6dcf26449f46 PKG_INSTALL:=1 PKG_FIXUP:=autoreconf diff --git a/package/utils/mtd-utils/patches/130-lzma_jffs2.patch b/package/utils/mtd-utils/patches/130-lzma_jffs2.patch index 55930ddc86..db683063d5 100644 --- a/package/utils/mtd-utils/patches/130-lzma_jffs2.patch +++ b/package/utils/mtd-utils/patches/130-lzma_jffs2.patch @@ -5020,7 +5020,7 @@ +} --- a/jffsX-utils/mkfs.jffs2.c +++ b/jffsX-utils/mkfs.jffs2.c -@@ -1667,11 +1667,11 @@ int main(int argc, char **argv) +@@ -1668,11 +1668,11 @@ int main(int argc, char **argv) } erase_block_size *= units; From 555cd82c22072f0114b7d42537f2e14c81da66df Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 21 Oct 2022 14:17:33 +0200 Subject: [PATCH 24/80] linux-firmware: update to 20221012 Changes: cfbd668 rtl_bt: Update RTL8852C BT USB firmware to 0xD5B8_A40A f49effc amdgpu: update GC 10.3.6 RLC firmware f9a1c7f amdgpu: update GC 10.3.7 RLC firmware eb1e45c amdgpu: update Yellow Carp RLC firmware 88557e1 amdgpu: update Beige Goby RLC firmware 2d3c1f8 amdgpu: update Dimgrey Cavefish RLC firmware d513825 amdgpu: update Navy Flounder RLC firmware c132bef amdgpu: update Sienna Cichlid RLC firmware 675bd6a mediatek: Update mt8195 SOF firmware to v0.4.1 44fa25d qcom: add squashed version of a530 zap shader d2aac63 rtw89: 8852c: update fw to v0.27.56.1 c9a1ddf rtw89: 8852c: update fw to v0.27.56.0 b7d6c9f mediatek: Update mt8186 SCP firmware fdf1a65 linux-firmware: Update AMD cpu microcode 375d450 mediatek: mt8195: Update scp.img to v2.0.11956 daee413 mediatek: Add new mt8195 SOF firmware 213255f mediatek: Update mt8186 SOF firmware to v0.2.1 9f88ec4 linux-firmware: update firmware for mediatek bluetooth chip (MT7922) bb3f948 rtl_bt: Update RTL8852A BT USB firmware to 0xD9B8_8207 6be4c4c linux-firmware: update firmware for mediatek bluetooth chip (MT7921) ea94bda linux-firmware: update firmware for MT7922 WiFi device 9490e8a linux-firmware: update firmware for MT7921 WiFi device e6e48db cxgb4: Update firmware to revision 1.27.0.0 51fff4e i915: Add versionless HuC files for current platforms 067440c i915: Add GuC v70.5.1 for DG1, DG2, TGL and ADL-P 0e8f546 qca: Update firmware files for BT chip WCN3991. 3593bb7 Removing crnv32 Signed-off-by: Nick Hainke --- package/firmware/linux-firmware/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/firmware/linux-firmware/Makefile b/package/firmware/linux-firmware/Makefile index f383acf85a..15120b6bc8 100644 --- a/package/firmware/linux-firmware/Makefile +++ b/package/firmware/linux-firmware/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=linux-firmware -PKG_VERSION:=20220913 +PKG_VERSION:=20221012 PKG_RELEASE:=1 PKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz -PKG_HASH:=26fd00f2d8e96c4af6f44269a6b893eb857253044f75ad28ef6706a2250cd8e9 +PKG_HASH:=e9d174af729511c8cccb60ec4e0b223b3c44b67d813b42d1ab9813acfa667fa5 PKG_MAINTAINER:=Felix Fietkau From 91fa5992bdeb9c806e617e04e0db4364adec87c3 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 21 Oct 2022 14:10:28 +0200 Subject: [PATCH 25/80] uboot-envtools: update to 2022.10 Update to latest version. Signed-off-by: Nick Hainke --- package/boot/uboot-envtools/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/boot/uboot-envtools/Makefile b/package/boot/uboot-envtools/Makefile index 6840b9c586..5c4d585021 100644 --- a/package/boot/uboot-envtools/Makefile +++ b/package/boot/uboot-envtools/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=uboot-envtools PKG_DISTNAME:=u-boot -PKG_VERSION:=2022.07 +PKG_VERSION:=2022.10 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2 @@ -17,7 +17,7 @@ PKG_SOURCE_URL:= \ https://ftp.denx.de/pub/u-boot \ https://mirror.cyberbits.eu/u-boot \ ftp://ftp.denx.de/pub/u-boot -PKG_HASH:=92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e +PKG_HASH:=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8 PKG_SOURCE_SUBDIR:=$(PKG_DISTNAME)-$(PKG_VERSION) PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_DISTNAME)-$(PKG_VERSION) From 0dd124465c8c4d27b34c2e53c0d2369c86997b55 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Tue, 18 Oct 2022 17:51:49 +0200 Subject: [PATCH 26/80] trace-cmd: update to v3.1.4 ae6db8e trace-cmd record: Use result of fcntl(GETPIPE_SZ) Signed-off-by: Nick Hainke --- package/devel/trace-cmd/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/devel/trace-cmd/Makefile b/package/devel/trace-cmd/Makefile index 9e8c46bc6f..b6a28ab93a 100644 --- a/package/devel/trace-cmd/Makefile +++ b/package/devel/trace-cmd/Makefile @@ -1,12 +1,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=trace-cmd -PKG_VERSION:=v3.1.3 -PKG_RELEASE:=2 +PKG_VERSION:=v3.1.4 +PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://git.kernel.org/pub/scm/utils/trace-cmd/trace-cmd.git/snapshot/ -PKG_HASH:=1fd8515f38fc29fd7a66e7b6b5931856906522e8a1845999fc9033fc80d7b676 +PKG_HASH:=447e095dbdfb0d362ab8c2086d62d80c5a2ecf67aef09b8f6b0cc064c0e1bfb5 PKG_LICENSE:=GPL-2.0-only PKG_LICENSE_FILES:=COPYING From 8ad82d31a0b4f8e658680b683e7e63ba2333ba30 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 16 Oct 2022 20:19:01 +0200 Subject: [PATCH 27/80] libbsd: update to 0.11.7 Changes: 084911c Release libbsd 0.11.7 3538d38 man: Discourage using the library in non-overlay mode 03fccd1 include: Adjust reallocarray() per glibc adoption 6b6e686 include: Adjust arc4random() per glibc adoption da1f45a include: explicit_bzero() requires _DEFAULT_SOURCE 2f9eddc include: Simplify glibc version dependent macro handling 28298ac doc: Switch references from pkg-config to pkgconf ef981f9 doc: Add missing empty line to separate README sections 6928d78 doc: Refer to the main git repository as primary d586575 test: Fix explicit_bzero() test on the Hurd be327c6 fgetwln: Add comment about lack of getwline(3) for recommendation a14612d setmode: Dot not use saveset after free f4baceb man: Rewrite gerprogname(3bsd) from scratch f35c545 man: Lowercase man page title b466b14 man: Document that some arc4random(3) functions are now in glibc 2.36 1f6a48b Sync arc4random(3) implementation from OpenBSD 873639e Fix ELF support for big endian SH c9c78fd man: Use -compact also for alternative functions in libbsd(7) 5f21307 getentropy: Fix function cast for getauxval() Signed-off-by: Nick Hainke --- package/libs/libbsd/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/libs/libbsd/Makefile b/package/libs/libbsd/Makefile index 47af01f555..789126cb82 100644 --- a/package/libs/libbsd/Makefile +++ b/package/libs/libbsd/Makefile @@ -1,12 +1,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=libbsd -PKG_VERSION:=0.11.6 +PKG_VERSION:=0.11.7 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=https://libbsd.freedesktop.org/releases -PKG_HASH:=19b38f3172eaf693e6e1c68714636190c7e48851e45224d720b3b5bc0499b5df +PKG_HASH:=9baa186059ebbf25c06308e9f991fda31f7183c0f24931826d83aa6abd8a0261 PKG_LICENSE:=BSD-4-Clause PKG_LICENSE_FILES:=COPYING From b6d850317bb9ef8af61eb26e34d5f24ee053a362 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 16 Oct 2022 22:10:01 +0200 Subject: [PATCH 28/80] gettext-full: update to 0.21.1 Release Announcement: https://lists.gnu.org/archive/html/info-gnu/2020-07/msg00009.html Further, refresh 001-autotools.patch and manually refresh 010-m4.patch. Signed-off-by: Nick Hainke --- package/libs/gettext-full/Makefile | 6 +- .../gettext-full/patches/001-autotools.patch | 2 +- .../libs/gettext-full/patches/010-m4.patch | 128 ++++++------------ 3 files changed, 48 insertions(+), 88 deletions(-) diff --git a/package/libs/gettext-full/Makefile b/package/libs/gettext-full/Makefile index f5f5e00542..2319401baf 100644 --- a/package/libs/gettext-full/Makefile +++ b/package/libs/gettext-full/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=gettext-full -PKG_VERSION:=0.21 -PKG_RELEASE:=2 +PKG_VERSION:=0.21.1 +PKG_RELEASE:=1 PKG_SOURCE:=gettext-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=@GNU/gettext -PKG_HASH:=d20fcbb537e02dcf1383197ba05bd0734ef7bf5db06bdb241eb69b7d16b73192 +PKG_HASH:=50dbc8f39797950aa2c98e939947c527e5ac9ebd2c1b99dd7b06ba33a6767ae6 PKG_BUILD_DIR:=$(BUILD_DIR)/gettext-$(PKG_VERSION) HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/gettext-$(PKG_VERSION) diff --git a/package/libs/gettext-full/patches/001-autotools.patch b/package/libs/gettext-full/patches/001-autotools.patch index 034fc938a3..7e1f005dc5 100644 --- a/package/libs/gettext-full/patches/001-autotools.patch +++ b/package/libs/gettext-full/patches/001-autotools.patch @@ -12,7 +12,7 @@ $(INSTALL_DATA) $$dir/$$file $(DESTDIR)$(htmldir)/$$file; \ --- a/gettext-tools/man/Makefile.am +++ b/gettext-tools/man/Makefile.am -@@ -157,8 +157,7 @@ recode-sr-latin.1.html: recode-sr-latin. +@@ -158,8 +158,7 @@ recode-sr-latin.1.html: recode-sr-latin. gettextize.1.html: gettextize.1 autopoint.1.html: autopoint.1 diff --git a/package/libs/gettext-full/patches/010-m4.patch b/package/libs/gettext-full/patches/010-m4.patch index 6d08835e37..fe896db312 100644 --- a/package/libs/gettext-full/patches/010-m4.patch +++ b/package/libs/gettext-full/patches/010-m4.patch @@ -1,14 +1,14 @@ --- a/gettext-runtime/gnulib-m4/stddef_h.m4 +++ b/gettext-runtime/gnulib-m4/stddef_h.m4 -@@ -8,7 +8,7 @@ dnl with or without modifications, as lo - AC_DEFUN([gl_STDDEF_H], +@@ -9,7 +9,7 @@ dnl A placeholder for , for pl + AC_DEFUN_ONCE([gl_STDDEF_H], [ AC_REQUIRE([gl_STDDEF_H_DEFAULTS]) - AC_REQUIRE([gt_TYPE_WCHAR_T]) + AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) - STDDEF_H= - dnl Test whether the type max_align_t exists and whether its alignment + dnl Persuade OpenBSD to declare max_align_t. + AC_REQUIRE([gl_USE_SYSTEM_EXTENSIONS]) --- a/gettext-runtime/gnulib-m4/stdint.m4 +++ b/gettext-runtime/gnulib-m4/stdint.m4 @@ -15,7 +15,7 @@ AC_DEFUN_ONCE([gl_STDINT_H], @@ -22,7 +22,7 @@ dnl macros. --- a/gettext-runtime/gnulib-m4/wchar_h.m4 +++ b/gettext-runtime/gnulib-m4/wchar_h.m4 -@@ -27,7 +27,7 @@ AC_DEFUN([gl_WCHAR_H], +@@ -27,7 +27,7 @@ AC_DEFUN_ONCE([gl_WCHAR_H], AC_REQUIRE([gl_FEATURES_H]) @@ -44,7 +44,7 @@ [AC_COMPILE_IFELSE( --- a/gettext-runtime/gnulib-m4/wctype_h.m4 +++ b/gettext-runtime/gnulib-m4/wctype_h.m4 -@@ -22,7 +22,7 @@ AC_DEFUN([gl_WCTYPE_H], +@@ -22,7 +22,7 @@ AC_DEFUN_ONCE([gl_WCTYPE_H], fi AC_SUBST([HAVE_ISWCNTRL]) @@ -77,26 +77,6 @@ [ AC_CACHE_CHECK([for wint_t], [gt_cv_c_wint_t], [AC_COMPILE_IFELSE( ---- a/gettext-runtime/intl/Makefile.am -+++ b/gettext-runtime/intl/Makefile.am -@@ -274,7 +274,7 @@ libgnuintl.h: $(srcdir)/libgnuintl.in.h - -e 's,@''HAVE_ASPRINTF''@,@HAVE_ASPRINTF@,g' \ - -e 's,@''HAVE_SNPRINTF''@,@HAVE_SNPRINTF@,g' \ - -e 's,@''HAVE_WPRINTF''@,@HAVE_WPRINTF@,g' \ -- -e 's,@''HAVE_NAMELESS_LOCALES''@,@HAVE_NAMELESS_LOCALES@,g' \ -+ -e 's,@''HAVE_NAMELESS_LOCALES''@,0,g' \ - -e 's,@''HAVE_NEWLOCALE''@,@HAVE_NEWLOCALE@,g' \ - < $(srcdir)/libgnuintl.in.h \ - | if test '@WOE32DLL@' = yes; then \ -@@ -294,7 +294,7 @@ libintl.h: $(srcdir)/libgnuintl.in.h - -e 's,@''HAVE_ASPRINTF''@,@HAVE_ASPRINTF@,g' \ - -e 's,@''HAVE_SNPRINTF''@,@HAVE_SNPRINTF@,g' \ - -e 's,@''HAVE_WPRINTF''@,@HAVE_WPRINTF@,g' \ -- -e 's,@''HAVE_NAMELESS_LOCALES''@,@HAVE_NAMELESS_LOCALES@,g' \ -+ -e 's,@''HAVE_NAMELESS_LOCALES''@,0,g' \ - -e 's,@''HAVE_NEWLOCALE''@,@HAVE_NEWLOCALE@,g' \ - < $(srcdir)/libgnuintl.in.h > libintl.h - MOSTLYCLEANFILES += libintl.h --- a/gettext-runtime/libasprintf/configure.ac +++ b/gettext-runtime/libasprintf/configure.ac @@ -76,8 +76,8 @@ dnl Checks for typedefs, structures, and @@ -145,30 +125,6 @@ AC_REQUIRE([gl_AC_HEADER_INTTYPES_H]) AC_REQUIRE([gt_TYPE_INTMAX_T]) AC_REQUIRE([gt_PRINTF_POSIX]) ---- a/gettext-tools/gnulib-m4/gnulib-comp.m4 -+++ b/gettext-tools/gnulib-m4/gnulib-comp.m4 -@@ -1843,8 +1843,8 @@ changequote([, ])dnl - AC_REQUIRE([gl_SOCKETS]) - gl_TYPE_SOCKLEN_T - gl_STDALIGN_H -- AC_REQUIRE([gt_TYPE_WCHAR_T]) -- AC_REQUIRE([gt_TYPE_WINT_T]) -+ AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) -+ AC_REQUIRE([gt_TYPE_WINT_T_GT]) - gl_FUNC_STRERROR_R - if test $HAVE_DECL_STRERROR_R = 0 || test $REPLACE_STRERROR_R = 1; then - AC_LIBOBJ([strerror_r]) ---- a/gettext-tools/gnulib-m4/stddef_h.m4 -+++ b/gettext-tools/gnulib-m4/stddef_h.m4 -@@ -8,7 +8,7 @@ dnl with or without modifications, as lo - AC_DEFUN([gl_STDDEF_H], - [ - AC_REQUIRE([gl_STDDEF_H_DEFAULTS]) -- AC_REQUIRE([gt_TYPE_WCHAR_T]) -+ AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) - STDDEF_H= - - dnl Test whether the type max_align_t exists and whether its alignment --- a/gettext-tools/gnulib-m4/stdint.m4 +++ b/gettext-tools/gnulib-m4/stdint.m4 @@ -15,7 +15,7 @@ AC_DEFUN_ONCE([gl_STDINT_H], @@ -216,7 +172,7 @@ dnl is defined as a weak alias of snprintf; we prefer to use the latter). --- a/gettext-tools/gnulib-m4/wchar_h.m4 +++ b/gettext-tools/gnulib-m4/wchar_h.m4 -@@ -27,7 +27,7 @@ AC_DEFUN([gl_WCHAR_H], +@@ -27,7 +27,7 @@ AC_DEFUN_ONCE([gl_WCHAR_H], AC_REQUIRE([gl_FEATURES_H]) @@ -238,7 +194,7 @@ [AC_COMPILE_IFELSE( --- a/gettext-tools/gnulib-m4/wctype_h.m4 +++ b/gettext-tools/gnulib-m4/wctype_h.m4 -@@ -22,7 +22,7 @@ AC_DEFUN([gl_WCTYPE_H], +@@ -22,7 +22,7 @@ AC_DEFUN_ONCE([gl_WCTYPE_H], fi AC_SUBST([HAVE_ISWCNTRL]) @@ -271,37 +227,6 @@ [ AC_CACHE_CHECK([for wint_t], [gt_cv_c_wint_t], [AC_COMPILE_IFELSE( ---- a/gettext-tools/intl/Makefile.am -+++ b/gettext-tools/intl/Makefile.am -@@ -274,7 +274,7 @@ libgnuintl.h: $(srcdir)/libgnuintl.in.h - -e 's,@''HAVE_ASPRINTF''@,@HAVE_ASPRINTF@,g' \ - -e 's,@''HAVE_SNPRINTF''@,@HAVE_SNPRINTF@,g' \ - -e 's,@''HAVE_WPRINTF''@,@HAVE_WPRINTF@,g' \ -- -e 's,@''HAVE_NAMELESS_LOCALES''@,@HAVE_NAMELESS_LOCALES@,g' \ -+ -e 's,@''HAVE_NAMELESS_LOCALES''@,0,g' \ - -e 's,@''HAVE_NEWLOCALE''@,@HAVE_NEWLOCALE@,g' \ - < $(srcdir)/libgnuintl.in.h \ - | if test '@WOE32DLL@' = yes; then \ -@@ -294,7 +294,7 @@ libintl.h: $(srcdir)/libgnuintl.in.h - -e 's,@''HAVE_ASPRINTF''@,@HAVE_ASPRINTF@,g' \ - -e 's,@''HAVE_SNPRINTF''@,@HAVE_SNPRINTF@,g' \ - -e 's,@''HAVE_WPRINTF''@,@HAVE_WPRINTF@,g' \ -- -e 's,@''HAVE_NAMELESS_LOCALES''@,@HAVE_NAMELESS_LOCALES@,g' \ -+ -e 's,@''HAVE_NAMELESS_LOCALES''@,0,g' \ - -e 's,@''HAVE_NEWLOCALE''@,@HAVE_NEWLOCALE@,g' \ - < $(srcdir)/libgnuintl.in.h > libintl.h - MOSTLYCLEANFILES += libintl.h ---- a/libtextstyle/gnulib-m4/stddef_h.m4 -+++ b/libtextstyle/gnulib-m4/stddef_h.m4 -@@ -8,7 +8,7 @@ dnl with or without modifications, as lo - AC_DEFUN([gl_STDDEF_H], - [ - AC_REQUIRE([gl_STDDEF_H_DEFAULTS]) -- AC_REQUIRE([gt_TYPE_WCHAR_T]) -+ AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) - STDDEF_H= - - dnl Test whether the type max_align_t exists and whether its alignment --- a/libtextstyle/gnulib-m4/stdint.m4 +++ b/libtextstyle/gnulib-m4/stdint.m4 @@ -15,7 +15,7 @@ AC_DEFUN_ONCE([gl_STDINT_H], @@ -349,7 +274,7 @@ dnl is defined as a weak alias of snprintf; we prefer to use the latter). --- a/libtextstyle/gnulib-m4/wchar_h.m4 +++ b/libtextstyle/gnulib-m4/wchar_h.m4 -@@ -27,7 +27,7 @@ AC_DEFUN([gl_WCHAR_H], +@@ -27,7 +27,7 @@ AC_DEFUN_ONCE([gl_WCHAR_H], AC_REQUIRE([gl_FEATURES_H]) @@ -380,3 +305,38 @@ [ AC_CACHE_CHECK([for wint_t], [gt_cv_c_wint_t], [AC_COMPILE_IFELSE( +--- a/gettext-tools/gnulib-m4/gnulib-comp.m4 ++++ b/gettext-tools/gnulib-m4/gnulib-comp.m4 +@@ -2218,8 +2218,8 @@ changequote([, ])dnl + AC_REQUIRE([gl_SOCKETLIB]) + AC_REQUIRE([gl_SOCKETS]) + gl_TYPE_SOCKLEN_T +- AC_REQUIRE([gt_TYPE_WCHAR_T]) +- AC_REQUIRE([gt_TYPE_WINT_T]) ++ AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) ++ AC_REQUIRE([gt_TYPE_WINT_T_GT]) + gl_FUNC_STRERROR_R + AS_IF([test $HAVE_DECL_STRERROR_R = 0 || test $REPLACE_STRERROR_R = 1], [ + AC_LIBOBJ([strerror_r]) +--- a/libtextstyle/gnulib-m4/stddef_h.m4 ++++ b/libtextstyle/gnulib-m4/stddef_h.m4 +@@ -9,7 +9,7 @@ dnl A placeholder for , for pl + AC_DEFUN_ONCE([gl_STDDEF_H], + [ + AC_REQUIRE([gl_STDDEF_H_DEFAULTS]) +- AC_REQUIRE([gt_TYPE_WCHAR_T]) ++ AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) + + dnl Persuade OpenBSD to declare max_align_t. + AC_REQUIRE([gl_USE_SYSTEM_EXTENSIONS]) +--- a/gettext-tools/gnulib-m4/stddef_h.m4 ++++ b/gettext-tools/gnulib-m4/stddef_h.m4 +@@ -9,7 +9,7 @@ dnl A placeholder for , for pl + AC_DEFUN_ONCE([gl_STDDEF_H], + [ + AC_REQUIRE([gl_STDDEF_H_DEFAULTS]) +- AC_REQUIRE([gt_TYPE_WCHAR_T]) ++ AC_REQUIRE([gt_TYPE_WCHAR_T_GT]) + + dnl Persuade OpenBSD to declare max_align_t. + AC_REQUIRE([gl_USE_SYSTEM_EXTENSIONS]) From 5479281c727004ecfdeb4318dc96d5f232ddaaf8 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Mon, 26 Sep 2022 07:22:08 +0200 Subject: [PATCH 29/80] thc-ipv6: update to 3.8 Remove upstreamed patches: - 000-cflags_override.patch Manually refresh patches: - 100-no-ssl.patch Add patches: - 101-remove-march-native.patch Add THC_APPLETS: - toobigsniff6 - flood_unreach6 - connect6 Signed-off-by: Nick Hainke --- package/network/ipv6/thc-ipv6/Makefile | 6 +++--- .../ipv6/thc-ipv6/patches/100-no-ssl.patch | 7 ++++--- ...erride.patch => 101-remove-march-native.patch} | 15 +++++++-------- 3 files changed, 14 insertions(+), 14 deletions(-) rename package/network/ipv6/thc-ipv6/patches/{000-cflags_override.patch => 101-remove-march-native.patch} (69%) diff --git a/package/network/ipv6/thc-ipv6/Makefile b/package/network/ipv6/thc-ipv6/Makefile index 91bacf625e..b26b0507fb 100644 --- a/package/network/ipv6/thc-ipv6/Makefile +++ b/package/network/ipv6/thc-ipv6/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=thc-ipv6 -PKG_VERSION:=2.7 +PKG_VERSION:=3.8 PKG_RELEASE:=1 PKG_LICENSE:=GPL-3.0 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@GITHUB/vanhauser-thc/THC-Archive/master/Tools -PKG_HASH:=440a3ae98b57100c397ec4f8634468dbbb0c3b48788c6b74af2a597a90544a96 +PKG_HASH:=b60be61a8b0a944a66e3b719704b4c03c1bc2c22f32d5d21e99e434c82a9d769 PKG_MAINTAINER:=Jo-Philipp Wich @@ -31,7 +31,7 @@ THC_APPLETS := \ fuzz_dhcps6 implementation6 implementation6d inverse_lookup6 \ kill_router6 ndpexhaust6 node_query6 parasite6 passive_discovery6 \ randicmp6 redir6 rsmurf6 sendpees6 sendpeesmp6 smurf6 thcping6 \ - toobig6 trace6 + toobig6 trace6 toobigsniff6 flood_unreach6 connect6 THC_DEPENDS_dnsdict6 := +libpthread THC_DEPENDS_thcping6 := +librt diff --git a/package/network/ipv6/thc-ipv6/patches/100-no-ssl.patch b/package/network/ipv6/thc-ipv6/patches/100-no-ssl.patch index 1ef1f66be8..118c2a705b 100644 --- a/package/network/ipv6/thc-ipv6/patches/100-no-ssl.patch +++ b/package/network/ipv6/thc-ipv6/patches/100-no-ssl.patch @@ -1,9 +1,10 @@ --- a/Makefile +++ b/Makefile -@@ -1,5 +1,5 @@ +@@ -1,6 +1,6 @@ # Comment out if openssl-dev is not present + # of if you want to compile statc -HAVE_SSL=yes +#HAVE_SSL=yes - CC=gcc - #CFLAGS=-g + # comment in if you want to compile static tools + #STATIC=-static diff --git a/package/network/ipv6/thc-ipv6/patches/000-cflags_override.patch b/package/network/ipv6/thc-ipv6/patches/101-remove-march-native.patch similarity index 69% rename from package/network/ipv6/thc-ipv6/patches/000-cflags_override.patch rename to package/network/ipv6/thc-ipv6/patches/101-remove-march-native.patch index e1c36b6c6c..da6c7caa7c 100644 --- a/package/network/ipv6/thc-ipv6/patches/000-cflags_override.patch +++ b/package/network/ipv6/thc-ipv6/patches/101-remove-march-native.patch @@ -1,12 +1,11 @@ -diff -urN thc-ipv6-2.7/Makefile thc-ipv6-2.7.new/Makefile ---- thc-ipv6-2.7/Makefile 2014-12-27 05:05:30.000000000 -0800 -+++ thc-ipv6-2.7.new/Makefile 2017-02-04 20:55:51.679898101 -0800 -@@ -3,7 +3,7 @@ +--- a/Makefile ++++ b/Makefile +@@ -7,7 +7,7 @@ HAVE_SSL=yes - CC=gcc + #CC=gcc #CFLAGS=-g --CFLAGS=-O2 -+CFLAGS?=-O2 +-CFLAGS+=-g -O3 -march=native -flto -falign-functions -falign-jumps -falign-loops -falign-labels -freorder-blocks ++CFLAGS+=-g -O3 -flto -falign-functions -falign-jumps -falign-loops -falign-labels -freorder-blocks CFLAGS+=$(if $(HAVE_SSL),-D_HAVE_SSL,) LDFLAGS+=-lpcap $(if $(HAVE_SSL),-lssl -lcrypto,) - PROGRAMS=parasite6 dos-new-ip6 detect-new-ip6 fake_router6 fake_advertise6 fake_solicitate6 fake_mld6 fake_mld26 fake_mldrouter6 flood_mldrouter6 fake_mipv6 redir6 smurf6 alive6 toobig6 rsmurf6 implementation6 implementation6d sendpees6 sendpeesmp6 randicmp6 fuzz_ip6 flood_mld6 flood_mld26 flood_router6 flood_advertise6 flood_solicitate6 trace6 exploit6 denial6 fake_dhcps6 flood_dhcpc6 fake_dns6d fragmentation6 kill_router6 fake_dnsupdate6 ndpexhaust6 detect_sniffer6 dump_router6 fake_router26 flood_router26 passive_discovery6 dnsrevenum6 inverse_lookup6 node_query6 address6 covert_send6 covert_send6d inject_alive6 firewall6 ndpexhaust26 fake_pim6 thcsyn6 redirsniff6 flood_redir6 four2six dump_dhcp6 fuzz_dhcps6 flood_rs6 fuzz_dhcpc6 + PROGRAMS=parasite6 dos-new-ip6 detect-new-ip6 fake_router6 fake_advertise6 fake_solicitate6 fake_mld6 fake_mld26 fake_mldrouter6 flood_mldrouter6 fake_mipv6 redir6 smurf6 alive6 toobig6 rsmurf6 implementation6 implementation6d sendpees6 sendpeesmp6 randicmp6 fuzz_ip6 flood_mld6 flood_mld26 flood_router6 flood_advertise6 flood_solicitate6 trace6 exploit6 denial6 fake_dhcps6 flood_dhcpc6 fake_dns6d fragmentation6 kill_router6 fake_dnsupdate6 ndpexhaust6 detect_sniffer6 dump_router6 fake_router26 flood_router26 passive_discovery6 dnsrevenum6 inverse_lookup6 node_query6 address6 covert_send6 covert_send6d inject_alive6 firewall6 ndpexhaust26 fake_pim6 thcsyn6 redirsniff6 flood_redir6 four2six dump_dhcp6 flood_rs6 fuzz_dhcps6 fuzz_dhcpc6 toobigsniff6 flood_unreach6 connect6 From 0dfe1d2175940d710e8ae08e9e4229d110155977 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Wed, 5 Oct 2022 12:37:47 +0200 Subject: [PATCH 30/80] iproute2: update to 6.0.0 Release Notes: https://lore.kernel.org/netdev/20221004082610.56b04719@hermes.local/t/ Remove upstreamed patch: - 010-ipstats-Add-param.h-for-musl.patch Refreshed: - 140-keep_libmnl_optional.patch - 145-keep_libelf_optional.patch - 150-keep_libcap_optional.patch - 155-keep_tirpc_optional.patch - 170-ip_tiny.patch - 190-fix-nls-rpath-link.patch - 200-drop_libbsd_dependency.patch - 300-selinux-configurable.patch Signed-off-by: Nick Hainke --- package/network/utils/iproute2/Makefile | 4 ++-- .../010-ipstats-Add-param.h-for-musl.patch | 23 ------------------- .../patches/140-keep_libmnl_optional.patch | 2 +- .../patches/145-keep_libelf_optional.patch | 2 +- .../patches/150-keep_libcap_optional.patch | 2 +- .../patches/155-keep_tirpc_optional.patch | 2 +- .../utils/iproute2/patches/170-ip_tiny.patch | 2 +- .../patches/190-fix-nls-rpath-link.patch | 4 ++-- .../patches/200-drop_libbsd_dependency.patch | 2 +- .../patches/300-selinux-configurable.patch | 2 +- 10 files changed, 11 insertions(+), 34 deletions(-) delete mode 100644 package/network/utils/iproute2/patches/010-ipstats-Add-param.h-for-musl.patch diff --git a/package/network/utils/iproute2/Makefile b/package/network/utils/iproute2/Makefile index 5255400513..6ef0b1a96a 100644 --- a/package/network/utils/iproute2/Makefile +++ b/package/network/utils/iproute2/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=iproute2 -PKG_VERSION:=5.19.0 +PKG_VERSION:=6.0.0 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=@KERNEL/linux/utils/net/iproute2 -PKG_HASH:=26b7a34d6a7fd2f7a42e2b39c5a90cb61bac522d1096067ffeb195e5693d7791 +PKG_HASH:=523139e9e72aec996374fa2de74be4c53d2dd05589488934d21ff97bae19580a PKG_BUILD_PARALLEL:=1 PKG_BUILD_DEPENDS:=iptables PKG_LICENSE:=GPL-2.0 diff --git a/package/network/utils/iproute2/patches/010-ipstats-Add-param.h-for-musl.patch b/package/network/utils/iproute2/patches/010-ipstats-Add-param.h-for-musl.patch deleted file mode 100644 index d99ae6e65c..0000000000 --- a/package/network/utils/iproute2/patches/010-ipstats-Add-param.h-for-musl.patch +++ /dev/null @@ -1,23 +0,0 @@ -From cf6b60c504d4be5e1df2b2745e55d677967831d0 Mon Sep 17 00:00:00 2001 -From: Changhyeok Bae -Date: Tue, 9 Aug 2022 04:01:05 +0000 -Subject: [PATCH 1/5] ipstats: Add param.h for musl - -Fix build error for musl -| /usr/src/debug/iproute2/5.19.0-r0/iproute2-5.19.0/ip/ipstats.c:231: undefined reference to `MIN' - -Signed-off-by: Changhyeok Bae ---- - ip/ipstats.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/ip/ipstats.c -+++ b/ip/ipstats.c -@@ -1,6 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0+ - #include - #include -+#include - - #include "list.h" - #include "utils.h" diff --git a/package/network/utils/iproute2/patches/140-keep_libmnl_optional.patch b/package/network/utils/iproute2/patches/140-keep_libmnl_optional.patch index a8cdd103ba..7f68f43616 100644 --- a/package/network/utils/iproute2/patches/140-keep_libmnl_optional.patch +++ b/package/network/utils/iproute2/patches/140-keep_libmnl_optional.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -411,7 +411,7 @@ check_tirpc() +@@ -412,7 +412,7 @@ check_tirpc() check_mnl() { diff --git a/package/network/utils/iproute2/patches/145-keep_libelf_optional.patch b/package/network/utils/iproute2/patches/145-keep_libelf_optional.patch index 0c5c3f59ed..2eaae88198 100644 --- a/package/network/utils/iproute2/patches/145-keep_libelf_optional.patch +++ b/package/network/utils/iproute2/patches/145-keep_libelf_optional.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -266,7 +266,7 @@ EOF +@@ -267,7 +267,7 @@ EOF check_elf() { diff --git a/package/network/utils/iproute2/patches/150-keep_libcap_optional.patch b/package/network/utils/iproute2/patches/150-keep_libcap_optional.patch index 4cce2c3ca6..c574840fa8 100644 --- a/package/network/utils/iproute2/patches/150-keep_libcap_optional.patch +++ b/package/network/utils/iproute2/patches/150-keep_libcap_optional.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -469,7 +469,7 @@ EOF +@@ -470,7 +470,7 @@ EOF check_cap() { diff --git a/package/network/utils/iproute2/patches/155-keep_tirpc_optional.patch b/package/network/utils/iproute2/patches/155-keep_tirpc_optional.patch index 28ba7e5217..4ee6245d3b 100644 --- a/package/network/utils/iproute2/patches/155-keep_tirpc_optional.patch +++ b/package/network/utils/iproute2/patches/155-keep_tirpc_optional.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -398,7 +398,7 @@ check_selinux() +@@ -399,7 +399,7 @@ check_selinux() check_tirpc() { diff --git a/package/network/utils/iproute2/patches/170-ip_tiny.patch b/package/network/utils/iproute2/patches/170-ip_tiny.patch index ba2cb0637a..9e95bcc2d6 100644 --- a/package/network/utils/iproute2/patches/170-ip_tiny.patch +++ b/package/network/utils/iproute2/patches/170-ip_tiny.patch @@ -105,4 +105,4 @@ + UTILOBJ = utils.o utils_math.o rt_names.o ll_map.o ll_types.o ll_proto.o ll_addr.o \ inet_proto.o namespace.o json_writer.o json_print.o json_print_math.o \ - names.o color.o bpf_legacy.o bpf_glue.o exec.o fs.o cg_map.o + names.o color.o bpf_legacy.o bpf_glue.o exec.o fs.o cg_map.o ppp_proto.o diff --git a/package/network/utils/iproute2/patches/190-fix-nls-rpath-link.patch b/package/network/utils/iproute2/patches/190-fix-nls-rpath-link.patch index c7fceb2e22..2f3f90fe1a 100644 --- a/package/network/utils/iproute2/patches/190-fix-nls-rpath-link.patch +++ b/package/network/utils/iproute2/patches/190-fix-nls-rpath-link.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -290,7 +290,7 @@ int main(int argc, char **argv) { +@@ -291,7 +291,7 @@ int main(int argc, char **argv) { } EOF @@ -9,7 +9,7 @@ local ret=$? rm -f $TMPDIR/libbpf_test.c $TMPDIR/libbpf_test -@@ -308,7 +308,7 @@ int main(int argc, char **argv) { +@@ -309,7 +309,7 @@ int main(int argc, char **argv) { } EOF diff --git a/package/network/utils/iproute2/patches/200-drop_libbsd_dependency.patch b/package/network/utils/iproute2/patches/200-drop_libbsd_dependency.patch index d1948860e8..052bdd84eb 100644 --- a/package/network/utils/iproute2/patches/200-drop_libbsd_dependency.patch +++ b/package/network/utils/iproute2/patches/200-drop_libbsd_dependency.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -455,14 +455,8 @@ EOF +@@ -456,14 +456,8 @@ EOF if $CC -I$INCLUDE -o $TMPDIR/strtest $TMPDIR/strtest.c >/dev/null 2>&1; then echo "no" else diff --git a/package/network/utils/iproute2/patches/300-selinux-configurable.patch b/package/network/utils/iproute2/patches/300-selinux-configurable.patch index 817abf7d17..adfa405c7f 100644 --- a/package/network/utils/iproute2/patches/300-selinux-configurable.patch +++ b/package/network/utils/iproute2/patches/300-selinux-configurable.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -385,7 +385,7 @@ check_libbpf() +@@ -386,7 +386,7 @@ check_libbpf() check_selinux() # SELinux is a compile time option in the ss utility { From 6e245777bdfe75f73766ef06458de6313a7d4d5e Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 21 Oct 2022 22:53:58 +0200 Subject: [PATCH 31/80] tools/mkimage: update to 2022.10 Remove upstreamed patches: - 020-tools-mtk_image-split-gfh-header-verification-into-a.patch - 021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch - 022-tools-mtk_image-add-support-for-nand-headers-used-by.patch Refreshed manually: - 030-allow-to-use-different-magic.patch Signed-off-by: Nick Hainke --- tools/mkimage/Makefile | 4 +- ...split-gfh-header-verification-into-a.patch | 89 -- ...split-the-code-of-generating-NAND-he.patch | 821 ------------------ ...add-support-for-nand-headers-used-by.patch | 702 --------------- .../030-allow-to-use-different-magic.patch | 22 +- 5 files changed, 13 insertions(+), 1625 deletions(-) delete mode 100644 tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch delete mode 100644 tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch delete mode 100644 tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch diff --git a/tools/mkimage/Makefile b/tools/mkimage/Makefile index a7c98e755e..10fe6eea43 100644 --- a/tools/mkimage/Makefile +++ b/tools/mkimage/Makefile @@ -7,14 +7,14 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mkimage -PKG_VERSION:=2022.07 +PKG_VERSION:=2022.10 PKG_SOURCE:=u-boot-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:= \ https://mirror.cyberbits.eu/u-boot \ https://ftp.denx.de/pub/u-boot \ ftp://ftp.denx.de/pub/u-boot -PKG_HASH:=92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e +PKG_HASH:=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8 HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/u-boot-$(PKG_VERSION) diff --git a/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch b/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch deleted file mode 100644 index 62300af266..0000000000 --- a/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch +++ /dev/null @@ -1,89 +0,0 @@ -From b6bb61fd3818f4a3025fedbe4d15dbeeaef6ee82 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 2 Aug 2022 17:21:34 +0800 -Subject: [PATCH 28/31] tools: mtk_image: split gfh header verification into a - new function - -The verification code of gfh header for NAND and non-NAND are identical. -It's better to define a individual function to reduce redundancy. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - tools/mtk_image.c | 51 +++++++++++++++++++---------------------------- - 1 file changed, 21 insertions(+), 30 deletions(-) - ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -432,6 +432,25 @@ static int mtk_image_vrec_header(struct - return SHA256_SUM_LEN; - } - -+static int mtk_image_verify_gfh(struct gfh_header *gfh, uint32_t type, int print) -+{ -+ if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) -+ return -1; -+ -+ if (le32_to_cpu(gfh->file_info.flash_type) != type) -+ return -1; -+ -+ if (print) -+ printf("Load Address: %08x\n", -+ le32_to_cpu(gfh->file_info.load_addr) + -+ le32_to_cpu(gfh->file_info.jump_offset)); -+ -+ if (print) -+ printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); -+ -+ return 0; -+} -+ - static int mtk_image_verify_gen_header(const uint8_t *ptr, int print) - { - union gen_boot_header *gbh = (union gen_boot_header *)ptr; -@@ -494,21 +513,7 @@ static int mtk_image_verify_gen_header(c - - gfh = (struct gfh_header *)(ptr + gfh_offset); - -- if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) -- return -1; -- -- if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_GEN) -- return -1; -- -- if (print) -- printf("Load Address: %08x\n", -- le32_to_cpu(gfh->file_info.load_addr) + -- le32_to_cpu(gfh->file_info.jump_offset)); -- -- if (print) -- printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); -- -- return 0; -+ return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_GEN, print); - } - - static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) -@@ -562,21 +567,7 @@ static int mtk_image_verify_nand_header( - - gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); - -- if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) -- return -1; -- -- if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_NAND) -- return -1; -- -- if (print) -- printf("Load Address: %08x\n", -- le32_to_cpu(gfh->file_info.load_addr) + -- le32_to_cpu(gfh->file_info.jump_offset)); -- -- if (print) -- printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); -- -- return 0; -+ return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); - } - - static int mtk_image_verify_header(unsigned char *ptr, int image_size, diff --git a/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch b/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch deleted file mode 100644 index 0b4013864e..0000000000 --- a/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch +++ /dev/null @@ -1,821 +0,0 @@ -From 20ebf03eab571b25e9f62b2764ab84932111dcd6 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 2 Aug 2022 17:23:57 +0800 -Subject: [PATCH 29/31] tools: mtk_image: split the code of generating NAND - header into a new file - -The predefined NAND headers take too much spaces in the mtk_image.c. -Moving them into a new file can significantly improve the readability of -both mtk_image.c and the new mtk_nand_headers.c. - -This is a preparation for adding more NAND headers. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - tools/Makefile | 1 + - tools/mtk_image.c | 305 ++++++--------------------------------- - tools/mtk_image.h | 25 ---- - tools/mtk_nand_headers.c | 286 ++++++++++++++++++++++++++++++++++++ - tools/mtk_nand_headers.h | 61 ++++++++ - 5 files changed, 389 insertions(+), 289 deletions(-) - create mode 100644 tools/mtk_nand_headers.c - create mode 100644 tools/mtk_nand_headers.h - ---- a/tools/Makefile -+++ b/tools/Makefile -@@ -147,6 +147,7 @@ dumpimage-mkimage-objs := aisimage.o \ - gpimage.o \ - gpimage-common.o \ - mtk_image.o \ -+ mtk_nand_headers.o \ - $(ECDSA_OBJS-y) \ - $(RSA_OBJS-y) \ - $(AES_OBJS-y) ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -10,216 +10,7 @@ - #include - #include "imagetool.h" - #include "mtk_image.h" -- --/* NAND header for SPI-NAND with 2KB page + 64B spare */ --static const union nand_boot_header snand_hdr_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, -- 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, -- 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, -- 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 -- } --}; -- --/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ --static const union nand_boot_header snand_hdr_2k_128_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, -- 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, -- 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, -- 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 -- } --}; -- --/* NAND header for SPI-NAND with 4KB page + 256B spare */ --static const union nand_boot_header snand_hdr_4k_256_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, -- 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, -- 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, -- 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ --static const union nand_boot_header nand_hdr_1gb_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, -- 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, -- 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, -- 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ --static const union nand_boot_header nand_hdr_2gb_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, -- 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, -- 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, -- 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ --static const union nand_boot_header nand_hdr_4gb_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, -- 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, -- 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, -- 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ --static const union nand_boot_header nand_hdr_2gb_2k_128_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, -- 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, -- 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, -- 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ --static const union nand_boot_header nand_hdr_4gb_2k_128_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -- 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, -- 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, -- 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, -- 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 -- } --}; -- --static const struct nand_header_type { -- const char *name; -- const union nand_boot_header *data; --} nand_headers[] = { -- { -- .name = "2k+64", -- .data = &snand_hdr_2k_64_data -- }, { -- .name = "2k+120", -- .data = &snand_hdr_2k_128_data -- }, { -- .name = "2k+128", -- .data = &snand_hdr_2k_128_data -- }, { -- .name = "4k+256", -- .data = &snand_hdr_4k_256_data -- }, { -- .name = "1g:2k+64", -- .data = &nand_hdr_1gb_2k_64_data -- }, { -- .name = "2g:2k+64", -- .data = &nand_hdr_2gb_2k_64_data -- }, { -- .name = "4g:2k+64", -- .data = &nand_hdr_4gb_2k_64_data -- }, { -- .name = "2g:2k+128", -- .data = &nand_hdr_2gb_2k_128_data -- }, { -- .name = "4g:2k+128", -- .data = &nand_hdr_4gb_2k_128_data -- } --}; -+#include "mtk_nand_headers.h" - - static const struct brom_img_type { - const char *name; -@@ -258,6 +49,7 @@ static char lk_name[32] = "U-Boot"; - - /* NAND header selected by user */ - static const union nand_boot_header *hdr_nand; -+static uint32_t hdr_nand_size; - - /* GFH header + 2 * 4KB pages of NAND */ - static char hdr_tmp[sizeof(struct gfh_header) + 0x2000]; -@@ -361,12 +153,7 @@ static int mtk_brom_parse_imagename(cons - } - - /* parse nand header type */ -- for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { -- if (!strcmp(nand_headers[i].name, nandinfo)) { -- hdr_nand = nand_headers[i].data; -- break; -- } -- } -+ hdr_nand = mtk_nand_header_find(nandinfo); - - /* parse device header offset */ - if (hdr_offs && hdr_offs[0]) -@@ -391,6 +178,9 @@ static int mtk_brom_parse_imagename(cons - return -EINVAL; - } - -+ if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) -+ hdr_nand_size = mtk_nand_header_size(hdr_nand); -+ - return 0; - } - -@@ -420,7 +210,7 @@ static int mtk_image_vrec_header(struct - } - - if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) -- tparams->header_size = 2 * le16_to_cpu(hdr_nand->pagesize); -+ tparams->header_size = hdr_nand_size; - else - tparams->header_size = sizeof(struct gen_device_header); - -@@ -518,16 +308,17 @@ static int mtk_image_verify_gen_header(c - - static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) - { -- union nand_boot_header *nh = (union nand_boot_header *)ptr; - struct brom_layout_header *bh; -+ struct nand_header_info info; - struct gfh_header *gfh; - const char *bootmedia; -+ int ret; - -- if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || -- strcmp(nh->id, NAND_BOOT_ID)) -- return -1; -+ ret = mtk_nand_header_info(ptr, &info); -+ if (ret < 0) -+ return ret; - -- bh = (struct brom_layout_header *)(ptr + le16_to_cpu(nh->pagesize)); -+ bh = (struct brom_layout_header *)(ptr + info.page_size); - - if (strcmp(bh->name, BRLYT_NAME)) - return -1; -@@ -538,34 +329,23 @@ static int mtk_image_verify_nand_header( - if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) - bootmedia = "Parallel NAND"; - else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) -- bootmedia = "Serial NAND"; -+ bootmedia = "Serial NAND (SNFI/AP)"; - else - return -1; - } - - if (print) { -- printf("Boot Media: %s\n", bootmedia); -- -- if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) { -- uint64_t capacity = -- (uint64_t)le16_to_cpu(nh->numblocks) * -- (uint64_t)le16_to_cpu(nh->pages_of_block) * -- (uint64_t)le16_to_cpu(nh->pagesize) * 8; -- printf("Capacity: %dGb\n", -- (uint32_t)(capacity >> 30)); -- } -+ printf("Boot Media: %s\n", bootmedia); - -- if (le16_to_cpu(nh->pagesize) >= 1024) -- printf("Page Size: %dKB\n", -- le16_to_cpu(nh->pagesize) >> 10); -+ if (info.page_size >= 1024) -+ printf("Page Size: %dKB\n", info.page_size >> 10); - else -- printf("Page Size: %dB\n", -- le16_to_cpu(nh->pagesize)); -+ printf("Page Size: %dB\n", info.page_size); - -- printf("Spare Size: %dB\n", le16_to_cpu(nh->oobsize)); -+ printf("Spare Size: %dB\n", info.spare_size); - } - -- gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); -+ gfh = (struct gfh_header *)(ptr + info.gfh_offset); - - return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); - } -@@ -581,7 +361,7 @@ static int mtk_image_verify_header(unsig - - img_size = image_size; - -- if (!strcmp((char *)ptr, NAND_BOOT_NAME)) -+ if (is_mtk_nand_header(ptr)) - return mtk_image_verify_nand_header(ptr, 0); - else - return mtk_image_verify_gen_header(ptr, 0); -@@ -601,7 +381,7 @@ static void mtk_image_print_header(const - - printf("Image Type: MediaTek BootROM Loadable Image\n"); - -- if (!strcmp((char *)ptr, NAND_BOOT_NAME)) -+ if (is_mtk_nand_header(ptr)) - mtk_image_verify_nand_header(ptr, 1); - else - mtk_image_verify_gen_header(ptr, 1); -@@ -732,36 +512,33 @@ static void mtk_image_set_gen_header(voi - static void mtk_image_set_nand_header(void *ptr, off_t filesize, - uint32_t loadaddr) - { -- union nand_boot_header *nh = (union nand_boot_header *)ptr; - struct brom_layout_header *brlyt; - struct gfh_header *gfh; -- uint32_t payload_pages; -- int i; -+ uint32_t payload_pages, nand_page_size; - -- /* NAND device header, repeat 4 times */ -- for (i = 0; i < 4; i++) -- memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); -+ /* NAND header */ -+ nand_page_size = mtk_nand_header_put(hdr_nand, ptr); - -- /* BRLYT header */ -- payload_pages = (filesize + le16_to_cpu(hdr_nand->pagesize) - 1) / -- le16_to_cpu(hdr_nand->pagesize); -- brlyt = (struct brom_layout_header *) -- (ptr + le16_to_cpu(hdr_nand->pagesize)); -- put_brom_layout_header(brlyt, hdr_media); -- brlyt->header_size = cpu_to_le32(2); -- brlyt->total_size = cpu_to_le32(payload_pages); -- brlyt->header_size_2 = brlyt->header_size; -- brlyt->total_size_2 = brlyt->total_size; -- brlyt->unused = cpu_to_le32(1); -+ if (nand_page_size) { -+ /* BRLYT header */ -+ payload_pages = (filesize + nand_page_size - 1) / -+ nand_page_size; -+ brlyt = (struct brom_layout_header *)(ptr + nand_page_size); -+ put_brom_layout_header(brlyt, hdr_media); -+ brlyt->header_size = cpu_to_le32(2); -+ brlyt->total_size = cpu_to_le32(payload_pages); -+ brlyt->header_size_2 = brlyt->header_size; -+ brlyt->total_size_2 = brlyt->total_size; -+ brlyt->unused = cpu_to_le32(1); -+ } - - /* GFH header */ -- gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(hdr_nand->pagesize)); -- put_ghf_header(gfh, filesize, 2 * le16_to_cpu(hdr_nand->pagesize), -- loadaddr, GFH_FLASH_TYPE_NAND); -+ gfh = (struct gfh_header *)(ptr + hdr_nand_size); -+ put_ghf_header(gfh, filesize, hdr_nand_size, loadaddr, -+ GFH_FLASH_TYPE_NAND); - - /* Generate SHA256 hash */ -- put_hash((uint8_t *)gfh, -- filesize - 2 * le16_to_cpu(hdr_nand->pagesize) - SHA256_SUM_LEN); -+ put_hash((uint8_t *)gfh, filesize - hdr_nand_size - SHA256_SUM_LEN); - } - - static void mtk_image_set_header(void *ptr, struct stat *sbuf, int ifd, ---- a/tools/mtk_image.h -+++ b/tools/mtk_image.h -@@ -26,31 +26,6 @@ union gen_boot_header { - #define SF_BOOT_NAME "SF_BOOT" - #define SDMMC_BOOT_NAME "SDMMC_BOOT" - --/* Header for NAND */ --union nand_boot_header { -- struct { -- char name[12]; -- char version[4]; -- char id[8]; -- uint16_t ioif; -- uint16_t pagesize; -- uint16_t addrcycles; -- uint16_t oobsize; -- uint16_t pages_of_block; -- uint16_t numblocks; -- uint16_t writesize_shift; -- uint16_t erasesize_shift; -- uint8_t dummy[60]; -- uint8_t ecc_parity[28]; -- }; -- -- uint8_t data[0x80]; --}; -- --#define NAND_BOOT_NAME "BOOTLOADER!" --#define NAND_BOOT_VERSION "V006" --#define NAND_BOOT_ID "NFIINFO" -- - /* BootROM layout header */ - struct brom_layout_header { - char name[8]; ---- /dev/null -+++ b/tools/mtk_nand_headers.c -@@ -0,0 +1,286 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * MediaTek BootROM NAND header definitions -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Weijie Gao -+ */ -+ -+#include -+#include -+#include "imagetool.h" -+#include "mtk_image.h" -+#include "mtk_nand_headers.h" -+ -+/* NAND header for SPI-NAND with 2KB page + 64B spare */ -+static const union nand_boot_header snand_hdr_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, -+ 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, -+ 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, -+ 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ -+static const union nand_boot_header snand_hdr_2k_128_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, -+ 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, -+ 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, -+ 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for SPI-NAND with 4KB page + 256B spare */ -+static const union nand_boot_header snand_hdr_4k_256_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, -+ 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, -+ 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, -+ 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ -+static const union nand_boot_header nand_hdr_1gb_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, -+ 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, -+ 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, -+ 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ -+static const union nand_boot_header nand_hdr_2gb_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, -+ 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, -+ 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, -+ 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ -+static const union nand_boot_header nand_hdr_4gb_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, -+ 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, -+ 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, -+ 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ -+static const union nand_boot_header nand_hdr_2gb_2k_128_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, -+ 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, -+ 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, -+ 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ -+static const union nand_boot_header nand_hdr_4gb_2k_128_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -+ 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, -+ 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, -+ 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, -+ 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 -+ } -+}; -+ -+static const struct nand_header_type { -+ const char *name; -+ const union nand_boot_header *data; -+} nand_headers[] = { -+ { -+ .name = "2k+64", -+ .data = &snand_hdr_2k_64_data -+ }, { -+ .name = "2k+120", -+ .data = &snand_hdr_2k_128_data -+ }, { -+ .name = "2k+128", -+ .data = &snand_hdr_2k_128_data -+ }, { -+ .name = "4k+256", -+ .data = &snand_hdr_4k_256_data -+ }, { -+ .name = "1g:2k+64", -+ .data = &nand_hdr_1gb_2k_64_data -+ }, { -+ .name = "2g:2k+64", -+ .data = &nand_hdr_2gb_2k_64_data -+ }, { -+ .name = "4g:2k+64", -+ .data = &nand_hdr_4gb_2k_64_data -+ }, { -+ .name = "2g:2k+128", -+ .data = &nand_hdr_2gb_2k_128_data -+ }, { -+ .name = "4g:2k+128", -+ .data = &nand_hdr_4gb_2k_128_data -+ } -+}; -+ -+const union nand_boot_header *mtk_nand_header_find(const char *name) -+{ -+ uint32_t i; -+ -+ for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { -+ if (!strcmp(nand_headers[i].name, name)) -+ return nand_headers[i].data; -+ } -+ -+ return NULL; -+} -+ -+uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand) -+{ -+ return 2 * le16_to_cpu(hdr_nand->pagesize); -+} -+ -+static int mtk_nand_header_ap_info(const void *ptr, -+ struct nand_header_info *info) -+{ -+ union nand_boot_header *nh = (union nand_boot_header *)ptr; -+ -+ if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || -+ strcmp(nh->id, NAND_BOOT_ID)) -+ return -1; -+ -+ info->page_size = le16_to_cpu(nh->pagesize); -+ info->spare_size = le16_to_cpu(nh->oobsize); -+ info->gfh_offset = 2 * info->page_size; -+ -+ return 0; -+} -+ -+int mtk_nand_header_info(const void *ptr, struct nand_header_info *info) -+{ -+ if (!strcmp((char *)ptr, NAND_BOOT_NAME)) -+ return mtk_nand_header_ap_info(ptr, info); -+ -+ return -1; -+} -+ -+bool is_mtk_nand_header(const void *ptr) -+{ -+ struct nand_header_info info; -+ -+ if (mtk_nand_header_info(ptr, &info) >= 0) -+ return true; -+ -+ return false; -+} -+ -+uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr) -+{ -+ union nand_boot_header *nh = (union nand_boot_header *)ptr; -+ int i; -+ -+ /* NAND device header, repeat 4 times */ -+ for (i = 0; i < 4; i++) -+ memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); -+ -+ return le16_to_cpu(hdr_nand->pagesize); -+} ---- /dev/null -+++ b/tools/mtk_nand_headers.h -@@ -0,0 +1,61 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * MediaTek BootROM NAND header definitions -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Weijie Gao -+ */ -+ -+#ifndef _MTK_NAND_HEADERS_H -+#define _MTK_NAND_HEADERS_H -+ -+#include -+#include -+ -+struct nand_header_info { -+ uint32_t page_size; -+ uint32_t spare_size; -+ uint32_t gfh_offset; -+}; -+ -+/* AP BROM Header for NAND */ -+union nand_boot_header { -+ struct { -+ char name[12]; -+ char version[4]; -+ char id[8]; -+ uint16_t ioif; /* I/O interface */ -+ uint16_t pagesize; /* NAND page size */ -+ uint16_t addrcycles; /* Address cycles */ -+ uint16_t oobsize; /* NAND page spare size */ -+ uint16_t pages_of_block; /* Pages of one block */ -+ uint16_t numblocks; /* Total blocks of NAND chip */ -+ uint16_t writesize_shift; -+ uint16_t erasesize_shift; -+ uint8_t dummy[60]; -+ uint8_t ecc_parity[28]; /* ECC parity of this header */ -+ }; -+ -+ uint8_t data[0x80]; -+}; -+ -+#define NAND_BOOT_NAME "BOOTLOADER!" -+#define NAND_BOOT_VERSION "V006" -+#define NAND_BOOT_ID "NFIINFO" -+ -+/* Find nand header data by name */ -+const union nand_boot_header *mtk_nand_header_find(const char *name); -+ -+/* Device header size using this nand header */ -+uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); -+ -+/* Get nand info from nand header (page size, spare size, ...) */ -+int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); -+ -+/* Whether given header data is valid */ -+bool is_mtk_nand_header(const void *ptr); -+ -+/* Generate Device header using give nand header */ -+uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr); -+ -+#endif /* _MTK_NAND_HEADERS_H */ diff --git a/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch b/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch deleted file mode 100644 index 12ff7f32de..0000000000 --- a/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch +++ /dev/null @@ -1,702 +0,0 @@ -From fbf296f9ed5daab70020686e9ba072efe663bbab Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 3 Aug 2022 11:14:36 +0800 -Subject: [PATCH 30/31] tools: mtk_image: add support for nand headers used by - newer chips - -This patch adds more nand headers in two new types: -1. HSM header, used for spi-nand thru SNFI interface -2. SPIM header, used for spi-nand thru spi-mem interface - -The original nand header is renamed to AP header. - -Signed-off-by: Weijie Gao ---- - tools/mtk_image.c | 23 ++- - tools/mtk_nand_headers.c | 422 +++++++++++++++++++++++++++++++++++++-- - tools/mtk_nand_headers.h | 110 +++++++++- - 3 files changed, 525 insertions(+), 30 deletions(-) - ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -31,6 +31,9 @@ static const struct brom_img_type { - }, { - .name = "snand", - .type = BRLYT_TYPE_SNAND -+ }, { -+ .name = "spim-nand", -+ .type = BRLYT_TYPE_SNAND - } - }; - -@@ -48,7 +51,7 @@ static bool is_arm64_image; - static char lk_name[32] = "U-Boot"; - - /* NAND header selected by user */ --static const union nand_boot_header *hdr_nand; -+static const struct nand_header_type *hdr_nand; - static uint32_t hdr_nand_size; - - /* GFH header + 2 * 4KB pages of NAND */ -@@ -318,20 +321,26 @@ static int mtk_image_verify_nand_header( - if (ret < 0) - return ret; - -- bh = (struct brom_layout_header *)(ptr + info.page_size); -+ if (!ret) { -+ bh = (struct brom_layout_header *)(ptr + info.page_size); - -- if (strcmp(bh->name, BRLYT_NAME)) -- return -1; -+ if (strcmp(bh->name, BRLYT_NAME)) -+ return -1; -+ -+ if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) -+ return -1; - -- if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) { -- return -1; -- } else { - if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) - bootmedia = "Parallel NAND"; - else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) - bootmedia = "Serial NAND (SNFI/AP)"; - else - return -1; -+ } else { -+ if (info.snfi) -+ bootmedia = "Serial NAND (SNFI/HSM)"; -+ else -+ bootmedia = "Serial NAND (SPIM)"; - } - - if (print) { ---- a/tools/mtk_nand_headers.c -+++ b/tools/mtk_nand_headers.c -@@ -188,55 +188,346 @@ static const union nand_boot_header nand - } - }; - --static const struct nand_header_type { -+/* HSM BROM NAND header for SPI NAND with 2KB page + 64B spare */ -+static const union hsm_nand_boot_header hsm_nand_hdr_2k_64_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -+ 0xFF, 0x00, 0x00, 0x00, 0x21, 0xD2, 0xEE, 0xF6, -+ 0xAE, 0xDD, 0x5E, 0xC2, 0x82, 0x8E, 0x9A, 0x62, -+ 0x09, 0x8E, 0x80, 0xE2, 0x37, 0x0D, 0xC9, 0xFA, -+ 0xA9, 0xDD, 0xFC, 0x92, 0x34, 0x2A, 0xED, 0x51, -+ 0xA4, 0x1B, 0xF7, 0x63, 0xCC, 0x5A, 0xC7, 0xFB, -+ 0xED, 0x21, 0x02, 0x23, 0x51, 0x31 -+ } -+}; -+ -+/* HSM BROM NAND header for SPI NAND with 2KB page + 128B spare */ -+static const union hsm_nand_boot_header hsm_nand_hdr_2k_128_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -+ 0xFF, 0x00, 0x00, 0x00, 0x71, 0x7f, 0x71, 0xAC, -+ 0x42, 0xD0, 0x5B, 0xD2, 0x12, 0x81, 0x15, 0x0A, -+ 0x0C, 0xD4, 0xF6, 0x32, 0x1E, 0x63, 0xE7, 0x81, -+ 0x8A, 0x7F, 0xDE, 0xF9, 0x4B, 0x91, 0xEC, 0xC2, -+ 0x70, 0x00, 0x7F, 0x57, 0xAF, 0xDC, 0xE4, 0x24, -+ 0x57, 0x09, 0xBC, 0xC5, 0x35, 0xDC -+ } -+}; -+ -+/* HSM BROM NAND header for SPI NAND with 4KB page + 256B spare */ -+static const union hsm_nand_boot_header hsm_nand_hdr_4k_256_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -+ 0xFF, 0x00, 0x00, 0x00, 0x62, 0x04, 0xD6, 0x1F, -+ 0x2B, 0x57, 0x7A, 0x2D, 0xFE, 0xBB, 0x4A, 0x50, -+ 0xEC, 0xF8, 0x70, 0x1A, 0x44, 0x15, 0xF6, 0xA2, -+ 0x8E, 0xB0, 0xFD, 0xFA, 0xDC, 0xAA, 0x5A, 0x4E, -+ 0xCB, 0x8E, 0xC9, 0x72, 0x08, 0xDC, 0x20, 0xB9, -+ 0x98, 0xC8, 0x82, 0xD8, 0xBE, 0x44 -+ } -+}; -+ -+/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 64B spare */ -+static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_64_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x5F, 0x4B, 0xB2, 0x5B, 0x8B, 0x1C, 0x35, 0xDA, -+ 0x83, 0xE6, 0x6C, 0xC3, 0xFB, 0x8C, 0x78, 0x23, -+ 0xD0, 0x89, 0x24, 0xD9, 0x6C, 0x35, 0x2C, 0x5D, -+ 0x8F, 0xBB, 0xFC, 0x10, 0xD0, 0xE2, 0x22, 0x7D, -+ 0xC8, 0x97, 0x9A, 0xEF, 0xC6, 0xB5, 0xA7, 0x4E, -+ 0x4E, 0x0E -+ } -+}; -+ -+/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 128B spare */ -+static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_128_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xF8, 0x7E, 0xC1, 0x5D, 0x61, 0x54, 0xEA, 0x9F, -+ 0x5E, 0x66, 0x39, 0x66, 0x21, 0xFF, 0x8C, 0x3B, -+ 0xBE, 0xA7, 0x5A, 0x9E, 0xD7, 0xBD, 0x9E, 0x89, -+ 0xEE, 0x7E, 0x10, 0x31, 0x9A, 0x1D, 0x82, 0x49, -+ 0xA3, 0x4E, 0xD8, 0x47, 0xD7, 0x19, 0xF4, 0x2D, -+ 0x8E, 0x53 -+ } -+}; -+ -+/* HSM2.0 BROM NAND header for SPI NAND with 4KB page + 256B spare */ -+static const union hsm20_nand_boot_header hsm20_nand_hdr_4k_256_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x79, 0x01, 0x1F, 0x86, 0x62, 0x6A, 0x43, 0xAE, -+ 0xE6, 0xF8, 0xDD, 0x5B, 0x29, 0xB7, 0xA2, 0x7F, -+ 0x29, 0x72, 0x54, 0x37, 0xBE, 0x50, 0xD4, 0x24, -+ 0xAB, 0x60, 0xF4, 0x44, 0x97, 0x3B, 0x65, 0x21, -+ 0x73, 0x24, 0x1F, 0x93, 0x0E, 0x9E, 0x96, 0x88, -+ 0x78, 0x6C -+ } -+}; -+ -+/* SPIM-NAND header for SPI NAND with 2KB page + 64B spare */ -+static const union spim_nand_boot_header spim_nand_hdr_2k_64_data = { -+ .data = { -+ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30, -+ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ } -+}; -+ -+/* SPIM-NAND header for SPI NAND with 2KB page + 128B spare */ -+static const union spim_nand_boot_header spim_nand_hdr_2k_128_data = { -+ .data = { -+ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30, -+ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ } -+}; -+ -+/* SPIM-NAND header for SPI NAND with 4KB page + 256B spare */ -+static const union spim_nand_boot_header spim_nand_hdr_4k_256_data = { -+ .data = { -+ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, -+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, -+ 0x40, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x20, 0x30, -+ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ } -+}; -+ -+struct nand_header_type { - const char *name; -- const union nand_boot_header *data; -+ enum nand_boot_header_type type; -+ union { -+ const union nand_boot_header *ap; -+ const union hsm_nand_boot_header *hsm; -+ const union hsm20_nand_boot_header *hsm20; -+ const union spim_nand_boot_header *spim; -+ }; - } nand_headers[] = { - { - .name = "2k+64", -- .data = &snand_hdr_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_2k_64_data, - }, { - .name = "2k+120", -- .data = &snand_hdr_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_2k_128_data, - }, { - .name = "2k+128", -- .data = &snand_hdr_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_2k_128_data, - }, { - .name = "4k+256", -- .data = &snand_hdr_4k_256_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_4k_256_data, - }, { - .name = "1g:2k+64", -- .data = &nand_hdr_1gb_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_1gb_2k_64_data, - }, { - .name = "2g:2k+64", -- .data = &nand_hdr_2gb_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_2gb_2k_64_data, - }, { - .name = "4g:2k+64", -- .data = &nand_hdr_4gb_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_4gb_2k_64_data, - }, { - .name = "2g:2k+128", -- .data = &nand_hdr_2gb_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_2gb_2k_128_data, - }, { - .name = "4g:2k+128", -- .data = &nand_hdr_4gb_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_4gb_2k_128_data, -+ }, { -+ .name = "hsm:2k+64", -+ .type = NAND_BOOT_HSM_HEADER, -+ .hsm = &hsm_nand_hdr_2k_64_data, -+ }, { -+ .name = "hsm:2k+128", -+ .type = NAND_BOOT_HSM_HEADER, -+ .hsm = &hsm_nand_hdr_2k_128_data, -+ }, { -+ .name = "hsm:4k+256", -+ .type = NAND_BOOT_HSM_HEADER, -+ .hsm = &hsm_nand_hdr_4k_256_data, -+ }, { -+ .name = "hsm20:2k+64", -+ .type = NAND_BOOT_HSM20_HEADER, -+ .hsm20 = &hsm20_nand_hdr_2k_64_data, -+ }, { -+ .name = "hsm20:2k+128", -+ .type = NAND_BOOT_HSM20_HEADER, -+ .hsm20 = &hsm20_nand_hdr_2k_128_data, -+ }, { -+ .name = "hsm20:4k+256", -+ .type = NAND_BOOT_HSM20_HEADER, -+ .hsm20 = &hsm20_nand_hdr_4k_256_data, -+ }, { -+ .name = "spim:2k+64", -+ .type = NAND_BOOT_SPIM_HEADER, -+ .spim = &spim_nand_hdr_2k_64_data, -+ }, { -+ .name = "spim:2k+128", -+ .type = NAND_BOOT_SPIM_HEADER, -+ .spim = &spim_nand_hdr_2k_128_data, -+ }, { -+ .name = "spim:4k+256", -+ .type = NAND_BOOT_SPIM_HEADER, -+ .spim = &spim_nand_hdr_4k_256_data, - } - }; - --const union nand_boot_header *mtk_nand_header_find(const char *name) -+const struct nand_header_type *mtk_nand_header_find(const char *name) - { - uint32_t i; - - for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { - if (!strcmp(nand_headers[i].name, name)) -- return nand_headers[i].data; -+ return &nand_headers[i]; - } - - return NULL; - } - --uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand) -+uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand) - { -- return 2 * le16_to_cpu(hdr_nand->pagesize); -+ switch (hdr_nand->type) { -+ case NAND_BOOT_HSM_HEADER: -+ return le32_to_cpu(hdr_nand->hsm->page_size); -+ -+ case NAND_BOOT_HSM20_HEADER: -+ return le32_to_cpu(hdr_nand->hsm20->page_size); -+ -+ case NAND_BOOT_SPIM_HEADER: -+ return le32_to_cpu(hdr_nand->spim->page_size); -+ -+ default: -+ return 2 * le16_to_cpu(hdr_nand->ap->pagesize); -+ } - } - - static int mtk_nand_header_ap_info(const void *ptr, -@@ -251,14 +542,45 @@ static int mtk_nand_header_ap_info(const - info->page_size = le16_to_cpu(nh->pagesize); - info->spare_size = le16_to_cpu(nh->oobsize); - info->gfh_offset = 2 * info->page_size; -+ info->snfi = true; - - return 0; - } - -+static int mtk_nand_header_hsm_info(const void *ptr, -+ struct nand_header_info *info) -+{ -+ union hsm_nand_boot_header *nh = (union hsm_nand_boot_header *)ptr; -+ -+ info->page_size = le16_to_cpu(nh->page_size); -+ info->spare_size = le16_to_cpu(nh->spare_size); -+ info->gfh_offset = info->page_size; -+ info->snfi = true; -+ -+ return 1; -+} -+ -+static int mtk_nand_header_spim_info(const void *ptr, -+ struct nand_header_info *info) -+{ -+ union spim_nand_boot_header *nh = (union spim_nand_boot_header *)ptr; -+ -+ info->page_size = le16_to_cpu(nh->page_size); -+ info->spare_size = le16_to_cpu(nh->spare_size); -+ info->gfh_offset = info->page_size; -+ info->snfi = false; -+ -+ return 1; -+} -+ - int mtk_nand_header_info(const void *ptr, struct nand_header_info *info) - { - if (!strcmp((char *)ptr, NAND_BOOT_NAME)) - return mtk_nand_header_ap_info(ptr, info); -+ else if (!strncmp((char *)ptr, HSM_NAND_BOOT_NAME, 8)) -+ return mtk_nand_header_hsm_info(ptr, info); -+ else if (!strncmp((char *)ptr, SPIM_NAND_BOOT_NAME, 8)) -+ return mtk_nand_header_spim_info(ptr, info); - - return -1; - } -@@ -273,14 +595,74 @@ bool is_mtk_nand_header(const void *ptr) - return false; - } - --uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr) -+static uint16_t crc16(const uint8_t *p, uint32_t len) -+{ -+ uint16_t crc = 0x4f4e; -+ uint32_t i; -+ -+ while (len--) { -+ crc ^= *p++ << 8; -+ for (i = 0; i < 8; i++) -+ crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); -+ } -+ -+ return crc; -+} -+ -+static uint32_t mtk_nand_header_put_ap(const struct nand_header_type *hdr_nand, -+ void *ptr) - { -- union nand_boot_header *nh = (union nand_boot_header *)ptr; - int i; - - /* NAND device header, repeat 4 times */ -- for (i = 0; i < 4; i++) -- memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); -+ for (i = 0; i < 4; i++) { -+ memcpy(ptr, hdr_nand->ap, sizeof(*hdr_nand->ap)); -+ ptr += sizeof(*hdr_nand->ap); -+ } -+ -+ return le16_to_cpu(hdr_nand->ap->pagesize); -+} - -- return le16_to_cpu(hdr_nand->pagesize); -+static uint32_t mtk_nand_header_put_hsm(const struct nand_header_type *hdr_nand, -+ void *ptr) -+{ -+ memcpy(ptr, hdr_nand->hsm, sizeof(*hdr_nand->hsm)); -+ return 0; -+} -+ -+static uint32_t mtk_nand_header_put_hsm20(const struct nand_header_type *hdr_nand, -+ void *ptr) -+{ -+ memcpy(ptr, hdr_nand->hsm20, sizeof(*hdr_nand->hsm20)); -+ return 0; -+} -+ -+static uint32_t mtk_nand_header_put_spim(const struct nand_header_type *hdr_nand, -+ void *ptr) -+{ -+ uint16_t crc; -+ -+ memcpy(ptr, hdr_nand->spim, sizeof(*hdr_nand->spim)); -+ -+ crc = crc16(ptr, 0x4e); -+ memcpy(ptr + 0x4e, &crc, sizeof(uint16_t)); -+ -+ return 0; -+} -+ -+uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, void *ptr) -+{ -+ switch (hdr_nand->type) { -+ case NAND_BOOT_HSM_HEADER: -+ return mtk_nand_header_put_hsm(hdr_nand, ptr); -+ -+ case NAND_BOOT_HSM20_HEADER: -+ return mtk_nand_header_put_hsm20(hdr_nand, ptr); -+ -+ case NAND_BOOT_SPIM_HEADER: -+ return mtk_nand_header_put_spim(hdr_nand, ptr); -+ -+ default: -+ return mtk_nand_header_put_ap(hdr_nand, ptr); -+ } - } ---- a/tools/mtk_nand_headers.h -+++ b/tools/mtk_nand_headers.h -@@ -16,6 +16,7 @@ struct nand_header_info { - uint32_t page_size; - uint32_t spare_size; - uint32_t gfh_offset; -+ bool snfi; - }; - - /* AP BROM Header for NAND */ -@@ -39,15 +40,117 @@ union nand_boot_header { - uint8_t data[0x80]; - }; - -+/* HSM BROM Header for NAND */ -+union hsm_nand_boot_header { -+ struct { -+ char id[8]; -+ uint32_t version; /* Header version */ -+ uint32_t config; /* Header config */ -+ uint32_t sector_size; /* ECC step size */ -+ uint32_t fdm_size; /* User OOB size of a step */ -+ uint32_t fdm_ecc_size; /* ECC parity size of a step */ -+ uint32_t lbs; -+ uint32_t page_size; /* NAND page size */ -+ uint32_t spare_size; /* NAND page spare size */ -+ uint32_t page_per_block; /* Pages of one block */ -+ uint32_t blocks; /* Total blocks of NAND chip */ -+ uint32_t plane_sel_position; /* Plane bit position */ -+ uint32_t pll; /* Value of pll reg */ -+ uint32_t acccon; /* Value of access timing reg */ -+ uint32_t strobe_sel; /* Value of DQS selection reg*/ -+ uint32_t acccon1; /* Value of access timing reg */ -+ uint32_t dqs_mux; /* Value of DQS mux reg */ -+ uint32_t dqs_ctrl; /* Value of DQS control reg */ -+ uint32_t delay_ctrl; /* Value of delay ctrl reg */ -+ uint32_t latch_lat; /* Value of latch latency reg */ -+ uint32_t sample_delay; /* Value of sample delay reg */ -+ uint32_t driving; /* Value of driving reg */ -+ uint32_t bl_start; /* Bootloader start addr */ -+ uint32_t bl_end; /* Bootloader end addr */ -+ uint8_t ecc_parity[42]; /* ECC parity of this header */ -+ }; -+ -+ uint8_t data[0x8E]; -+}; -+ -+/* HSM2.0 BROM Header for NAND */ -+union hsm20_nand_boot_header { -+ struct { -+ char id[8]; -+ uint32_t version; /* Header version */ -+ uint32_t config; /* Header config */ -+ uint32_t sector_size; /* ECC step size */ -+ uint32_t fdm_size; /* User OOB size of a step */ -+ uint32_t fdm_ecc_size; /* ECC parity size of a step */ -+ uint32_t lbs; -+ uint32_t page_size; /* NAND page size */ -+ uint32_t spare_size; /* NAND page spare size */ -+ uint32_t page_per_block; /* Pages of one block */ -+ uint32_t blocks; /* Total blocks of NAND chip */ -+ uint32_t plane_sel_position; /* Plane bit position */ -+ uint32_t pll; /* Value of pll reg */ -+ uint32_t acccon; /* Value of access timing reg */ -+ uint32_t strobe_sel; /* Value of DQS selection reg*/ -+ uint32_t acccon1; /* Value of access timing reg */ -+ uint32_t dqs_mux; /* Value of DQS mux reg */ -+ uint32_t dqs_ctrl; /* Value of DQS control reg */ -+ uint32_t delay_ctrl; /* Value of delay ctrl reg */ -+ uint32_t latch_lat; /* Value of latch latency reg */ -+ uint32_t sample_delay; /* Value of sample delay reg */ -+ uint32_t driving; /* Value of driving reg */ -+ uint32_t reserved; -+ uint32_t bl0_start; /* Bootloader start addr */ -+ uint32_t bl0_end; /* Bootloader end addr */ -+ uint32_t bl0_type; /* Bootloader type */ -+ uint8_t bl_reserve[84]; -+ uint8_t ecc_parity[42]; /* ECC parity of this header */ -+ }; -+ -+ uint8_t data[0xEA]; -+}; -+ -+/* SPIM BROM Header for SPI-NAND */ -+union spim_nand_boot_header { -+ struct { -+ char id[8]; -+ uint32_t version; /* Header version */ -+ uint32_t config; /* Header config */ -+ uint32_t page_size; /* NAND page size */ -+ uint32_t spare_size; /* NAND page spare size */ -+ uint16_t page_per_block; /* Pages of one block */ -+ uint16_t plane_sel_position; /* Plane bit position */ -+ uint16_t reserve_reg; -+ uint16_t reserve_val; -+ uint16_t ecc_error; /* ECC error reg addr */ -+ uint16_t ecc_mask; /* ECC error bit mask */ -+ uint32_t bl_start; /* Bootloader start addr */ -+ uint32_t bl_end; /* Bootloader end addr */ -+ uint8_t ecc_parity[32]; /* ECC parity of this header */ -+ uint32_t integrity_crc; /* CRC of this header */ -+ }; -+ -+ uint8_t data[0x50]; -+}; -+ -+enum nand_boot_header_type { -+ NAND_BOOT_AP_HEADER, -+ NAND_BOOT_HSM_HEADER, -+ NAND_BOOT_HSM20_HEADER, -+ NAND_BOOT_SPIM_HEADER -+}; -+ - #define NAND_BOOT_NAME "BOOTLOADER!" - #define NAND_BOOT_VERSION "V006" - #define NAND_BOOT_ID "NFIINFO" - -+#define HSM_NAND_BOOT_NAME "NANDCFG!" -+#define SPIM_NAND_BOOT_NAME "SPINAND!" -+ - /* Find nand header data by name */ --const union nand_boot_header *mtk_nand_header_find(const char *name); -+const struct nand_header_type *mtk_nand_header_find(const char *name); - - /* Device header size using this nand header */ --uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); -+uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand); - - /* Get nand info from nand header (page size, spare size, ...) */ - int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); -@@ -56,6 +159,7 @@ int mtk_nand_header_info(const void *ptr - bool is_mtk_nand_header(const void *ptr); - - /* Generate Device header using give nand header */ --uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr); -+uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, -+ void *ptr); - - #endif /* _MTK_NAND_HEADERS_H */ diff --git a/tools/mkimage/patches/030-allow-to-use-different-magic.patch b/tools/mkimage/patches/030-allow-to-use-different-magic.patch index b97cd819cc..591edf24ea 100644 --- a/tools/mkimage/patches/030-allow-to-use-different-magic.patch +++ b/tools/mkimage/patches/030-allow-to-use-different-magic.patch @@ -2,7 +2,7 @@ This patch makes it possible to set a custom image magic. --- a/tools/mkimage.c +++ b/tools/mkimage.c -@@ -25,6 +25,7 @@ static struct image_tool_params params = +@@ -26,6 +26,7 @@ static struct image_tool_params params = .arch = IH_ARCH_PPC, .type = IH_TYPE_KERNEL, .comp = IH_COMP_GZIP, @@ -10,7 +10,7 @@ This patch makes it possible to set a custom image magic. .dtc = MKIMAGE_DEFAULT_DTC_OPTIONS, .imagename = "", .imagename2 = "", -@@ -88,11 +89,12 @@ static void usage(const char *msg) +@@ -89,11 +90,12 @@ static void usage(const char *msg) " -q ==> quiet\n", params.cmdname); fprintf(stderr, @@ -24,16 +24,16 @@ This patch makes it possible to set a custom image magic. " -a ==> set load address to 'addr' (hex)\n" " -e ==> set entry point to 'ep' (hex)\n" " -n ==> set image name to 'name'\n" -@@ -163,7 +165,7 @@ static void process_args(int argc, char - int opt; +@@ -159,7 +161,7 @@ static int add_content(int type, const c + } - while ((opt = getopt(argc, argv, -- "a:A:b:B:c:C:d:D:e:Ef:FG:k:i:K:ln:N:p:o:O:rR:qstT:vVx")) != -1) { -+ "a:A:b:B:c:C:d:D:e:Ef:FG:k:i:K:lM:n:N:p:o:O:rR:qstT:vVx")) != -1) { - switch (opt) { - case 'a': - params.addr = strtoull(optarg, &ptr, 16); -@@ -254,6 +256,14 @@ static void process_args(int argc, char + static const char optstring[] = +- "a:A:b:B:c:C:d:D:e:Ef:Fg:G:i:k:K:ln:N:o:O:p:qrR:stT:vVx"; ++ "a:A:b:B:c:C:d:D:e:Ef:Fg:G:i:k:K:lM:n:N:o:O:p:qrR:stT:vVx"; + + static const struct option longopts[] = { + { "load-address", required_argument, NULL, 'a' }, +@@ -298,6 +300,14 @@ static void process_args(int argc, char case 'l': params.lflag = 1; break; From ef51c0150a5c569d474891e0bc7ae93a12d99c1b Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 21 Oct 2022 22:06:49 +0200 Subject: [PATCH 32/80] tools/xz: update to 5.2.7 Update to latest version. Signed-off-by: Nick Hainke --- tools/xz/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/xz/Makefile b/tools/xz/Makefile index 8add2f21df..845fefe9af 100644 --- a/tools/xz/Makefile +++ b/tools/xz/Makefile @@ -7,12 +7,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=xz -PKG_VERSION:=5.2.6 +PKG_VERSION:=5.2.7 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:=@SF/lzmautils \ http://tukaani.org/xz -PKG_HASH:=13e3402e301b6018f6a71ef0e497f714c6d11e214ae82dab156b81c2a64acb25 +PKG_HASH:=b65f1d0c2708e57716f4dd2216989a73847ac6fdb4168ffceb155767e22b834b PKG_CPE_ID:=cpe:/a:tukaani:xz HOST_BUILD_PARALLEL:=1 From 1699ace3a4f97a1b971c4f92e13321000172da9c Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 21 Oct 2022 22:01:48 +0200 Subject: [PATCH 33/80] tools/mtools: update to 4.0.41 Release Notes: https://lists.gnu.org/archive/html/info-gnu/2022-09/msg00011.html Signed-off-by: Nick Hainke --- tools/mtools/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/mtools/Makefile b/tools/mtools/Makefile index 74007a88d0..964ef9db33 100644 --- a/tools/mtools/Makefile +++ b/tools/mtools/Makefile @@ -7,11 +7,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mtools -PKG_VERSION:=4.0.40 +PKG_VERSION:=4.0.41 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:=@GNU/$(PKG_NAME) -PKG_HASH:=a22fca42354011dd2293a7f51f228b46ebbd802e7740b0975912afecb79d5df4 +PKG_HASH:=2542152264fb3eff7ed70662abf4f4eef8133bc37d0b7a686c240df2b5f80a13 HOST_BUILD_PARALLEL:=1 From a8bbce498e9fab4fc11ab2b126c932929a27be0f Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 21 Oct 2022 22:23:47 +0200 Subject: [PATCH 34/80] tools/bc: update to 1.07.1 Changes: Fixed ibase extension causing problems for read() Fixed parallel make problem. Remove the "003-bc-fix-hang.patch" because the hang is fixed upstream. Signed-off-by: Nick Hainke --- tools/bc/Makefile | 4 ++-- tools/bc/patches/003-bc-fix-hang.patch | 11 ----------- 2 files changed, 2 insertions(+), 13 deletions(-) delete mode 100644 tools/bc/patches/003-bc-fix-hang.patch diff --git a/tools/bc/Makefile b/tools/bc/Makefile index ac6609e008..2c29e094e2 100644 --- a/tools/bc/Makefile +++ b/tools/bc/Makefile @@ -7,11 +7,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=bc -PKG_VERSION:=1.07 +PKG_VERSION:=1.07.1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@GNU/bc -PKG_HASH:=55cf1fc33a728d7c3d386cc7b0cb556eb5bacf8e0cb5a3fcca7f109fc61205ad +PKG_HASH:=62adfca89b0a1c0164c2cdca59ca210c1d44c3ffc46daf9931cf4942664cb02a PKG_FIXUP := autoreconf PKG_CPE_ID:=cpe:/a:gnu:bc diff --git a/tools/bc/patches/003-bc-fix-hang.patch b/tools/bc/patches/003-bc-fix-hang.patch deleted file mode 100644 index ba297051e2..0000000000 --- a/tools/bc/patches/003-bc-fix-hang.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/bc/execute.c -+++ b/bc/execute.c -@@ -595,7 +595,7 @@ input_char (void) - if (in_ch == '.' || in_ch == '+' || in_ch == '-') - return (in_ch); - if (in_ch <= ' ') -- return (' '); -+ return (':'); - - return (':'); - } From d1386dd32a56b274f192df985de24225a9cb306e Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 21 Oct 2022 22:41:06 +0200 Subject: [PATCH 35/80] tools/zlib: update to 1.2.13 Switch to "https github.com" for downloading source files. Release Announcements: https://github.com/madler/zlib/releases/tag/v1.2.13 Signed-off-by: Nick Hainke --- tools/zlib/Makefile | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/tools/zlib/Makefile b/tools/zlib/Makefile index 974de38154..17fe9fa233 100644 --- a/tools/zlib/Makefile +++ b/tools/zlib/Makefile @@ -8,13 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=zlib -PKG_VERSION:=1.2.12 +PKG_VERSION:=1.2.13 PKG_RELEASE:=1 -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://github.com/madler/zlib -PKG_MIRROR_HASH:=a162fc219763635f0c1591ec515d4b08684e4b0bfb4b1c8e65e4eab18d597c27 -PKG_SOURCE_VERSION:=21767c654d31d2dccdde4330529775c6c5fd5389 +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz +PKG_SOURCE_URL:=https://github.com/madler/zlib/releases/download/v$(PKG_VERSION) +PKG_HASH:=d14c38e313afc35a9a8760dadf26042f51ea0f5d154b0630a31da0540107fb98 PKG_LICENSE:=Zlib PKG_LICENSE_FILES:=README From d213f273391bc9fb8edb1ffcb7c907a2345dde4e Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 21 Oct 2022 22:14:12 +0200 Subject: [PATCH 36/80] tools/bash: update to 5.2 Release Notes: https://lists.gnu.org/archive/html/bug-bash/2022-09/msg00056.html Signed-off-by: Nick Hainke --- tools/bash/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/bash/Makefile b/tools/bash/Makefile index 992933c6bf..e5cf3b5945 100644 --- a/tools/bash/Makefile +++ b/tools/bash/Makefile @@ -8,11 +8,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=bash PKG_CPE_ID:=cpe:/a:gnu:bash -PKG_VERSION:=5.1.16 +PKG_VERSION:=5.2 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@GNU/bash -PKG_HASH:=5bac17218d3911834520dad13cd1f85ab944e1c09ae1aba55906be1f8192f558 +PKG_HASH:=a139c166df7ff4471c5e0733051642ee5556c1cc8a4a78f145583c5c81ab32fb HOST_BUILD_PARALLEL := 1 From 7179b06898b0c89c7f47385b6b64b40ef53bed04 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 21 Oct 2022 23:24:29 +0200 Subject: [PATCH 37/80] tools/dwarves: update to 1.24 Release Notes: https://lwn.net/Articles/905738/ Switch to https "fedorapeople.org"-mirror. Use $(AUTORELEASE). Signed-off-by: Nick Hainke --- tools/dwarves/Makefile | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tools/dwarves/Makefile b/tools/dwarves/Makefile index 41f0532701..d9a121aab1 100644 --- a/tools/dwarves/Makefile +++ b/tools/dwarves/Makefile @@ -3,11 +3,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=dwarves +PKG_VERSION:=1.24 +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz +PKG_SOURCE_URL:=https://fedorapeople.org/~acme/dwarves/ +PKG_HASH:=576bc112b95937dfbcd347c423696ee9e1992a338fdca1acacca736fd95f69c2 -PKG_SOURCE_VERSION:=v1.23 -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://git.kernel.org/pub/scm/devel/pahole/pahole.git -PKG_MIRROR_HASH:=6ab1bb1dbdf6c73ffcf485d909229dc1da1a3d24efd213e92c56489b58d6a4bd PKG_LICENSE:=GPL-2.0-only PKG_LICENSE_FILES:=COPYING From f21394c4d11bf5c773c4f7bd5a115977ddeb3e98 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 21 Aug 2022 08:43:52 +0200 Subject: [PATCH 38/80] tools/genext2fs: switch to codeload.github.com As written on the genext2fs.sourceforge.net page: "If you want bugfixes and nicer features though, you will have to grab the source from github and build it yourself." This commit switches the download from sourceforge to codeload.github.com. Signed-off-by: Nick Hainke --- tools/genext2fs/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/genext2fs/Makefile b/tools/genext2fs/Makefile index 3a911df91a..7bd7742d28 100644 --- a/tools/genext2fs/Makefile +++ b/tools/genext2fs/Makefile @@ -11,8 +11,8 @@ PKG_NAME:=genext2fs PKG_VERSION:=1.4.1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz -PKG_SOURCE_URL:=@SF/genext2fs -PKG_HASH:=404dbbfa7a86a6c3de8225c8da254d026b17fd288e05cec4df2cc7e1f4feecfc +PKG_SOURCE_URL:=https://codeload.github.com/bestouff/$(PKG_NAME)/tar.gz/v$(PKG_VERSION)? +PKG_HASH:=0d706f08b11051aae00fe67d88b7aac1fdd0d5d96163704508e21fb6460f899d include $(INCLUDE_DIR)/host-build.mk From b6d29af9475f162b7258695299c2e95ce55c0b7c Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 21 Aug 2022 09:33:46 +0200 Subject: [PATCH 39/80] tools/genext2fs: update to 1.5.0 Update to latest version. Remove patches: - 100-c99_scanf.patch - 200-autoconf.patch - 300-blocksize-creator.patch - 400-byteswap_fix.patch Signed-off-by: Nick Hainke --- tools/genext2fs/Makefile | 11 +- tools/genext2fs/patches/100-c99_scanf.patch | 21 - tools/genext2fs/patches/200-autoconf.patch | 13 - .../patches/300-blocksize-creator.patch | 558 ------------------ .../genext2fs/patches/400-byteswap_fix.patch | 44 -- 5 files changed, 9 insertions(+), 638 deletions(-) delete mode 100644 tools/genext2fs/patches/100-c99_scanf.patch delete mode 100644 tools/genext2fs/patches/200-autoconf.patch delete mode 100644 tools/genext2fs/patches/300-blocksize-creator.patch delete mode 100644 tools/genext2fs/patches/400-byteswap_fix.patch diff --git a/tools/genext2fs/Makefile b/tools/genext2fs/Makefile index 7bd7742d28..4e7abf8bb6 100644 --- a/tools/genext2fs/Makefile +++ b/tools/genext2fs/Makefile @@ -8,11 +8,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=genext2fs -PKG_VERSION:=1.4.1 +PKG_VERSION:=1.5.0 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://codeload.github.com/bestouff/$(PKG_NAME)/tar.gz/v$(PKG_VERSION)? -PKG_HASH:=0d706f08b11051aae00fe67d88b7aac1fdd0d5d96163704508e21fb6460f899d +PKG_HASH:=d3861e4fe89131bd21fbd25cf0b683b727b5c030c4c336fadcd738ada830aab0 include $(INCLUDE_DIR)/host-build.mk @@ -33,6 +33,13 @@ HOST_CONFIGURE_ARGS = \ --mandir=/usr/man \ --infodir=/usr/info \ +define Host/Configure + (cd $(HOST_BUILD_DIR); \ + ./autogen.sh \ + ); + $(call Host/Configure/Default) +endef + define Host/Compile $(MAKE) -C $(HOST_BUILD_DIR) \ CFLAGS="$(HOST_CFLAGS)" \ diff --git a/tools/genext2fs/patches/100-c99_scanf.patch b/tools/genext2fs/patches/100-c99_scanf.patch deleted file mode 100644 index e7aa17cc6f..0000000000 --- a/tools/genext2fs/patches/100-c99_scanf.patch +++ /dev/null @@ -1,21 +0,0 @@ -commit 3b8ca0ce9a0b58287a780747c90c449bdebfe464 -Author: Xavier Bestel -Date: Mon Jan 14 08:52:44 2008 +0000 - - removed use of %as is scanf (GNU conflicts with C99) by Giacomo Catenazzi - -diff --git a/genext2fs.c b/genext2fs.c -index 070b270..f0d797d 100644 ---- a/genext2fs.c -+++ b/genext2fs.c -@@ -286,7 +286,9 @@ typedef unsigned int uint32; - // older solaris. Note that this is still not very portable, in that - // the return value cannot be trusted. - --#if SCANF_CAN_MALLOC -+#if 0 // SCANF_CAN_MALLOC -+// C99 define "a" for floating point, so you can have runtime surprise -+// according the library versions - # define SCANF_PREFIX "a" - # define SCANF_STRING(s) (&s) - #else diff --git a/tools/genext2fs/patches/200-autoconf.patch b/tools/genext2fs/patches/200-autoconf.patch deleted file mode 100644 index b3317bdd10..0000000000 --- a/tools/genext2fs/patches/200-autoconf.patch +++ /dev/null @@ -1,13 +0,0 @@ -Index: genext2fs/m4/ac_func_scanf_can_malloc.m4 -=================================================================== ---- genext2fs.orig/m4/ac_func_scanf_can_malloc.m4 2011-09-03 21:28:49.000000000 +0200 -+++ genext2fs/m4/ac_func_scanf_can_malloc.m4 2011-09-03 21:29:41.000000000 +0200 -@@ -9,7 +9,7 @@ - # -------------------------------------- - AC_DEFUN([AC_FUNC_SCANF_CAN_MALLOC], - [ AC_CHECK_HEADERS([stdlib.h]) -- AC_CACHE_CHECK([whether scanf can malloc], [ac_scanf_can_malloc], -+ AC_CACHE_CHECK([whether scanf can malloc], [ac_cv_func_scanf_can_malloc], - [ AC_RUN_IFELSE( - [ AC_LANG_PROGRAM( - [ diff --git a/tools/genext2fs/patches/300-blocksize-creator.patch b/tools/genext2fs/patches/300-blocksize-creator.patch deleted file mode 100644 index 97a4836eeb..0000000000 --- a/tools/genext2fs/patches/300-blocksize-creator.patch +++ /dev/null @@ -1,558 +0,0 @@ -Index: genext2fs/genext2fs.c -=================================================================== ---- genext2fs.orig/genext2fs.c 2011-09-03 14:21:17.000000000 +0200 -+++ genext2fs/genext2fs.c 2011-09-03 14:21:17.000000000 +0200 -@@ -151,13 +151,24 @@ - - // block size - --#define BLOCKSIZE 1024 -+static int blocksize = 1024; -+ -+#define BLOCKSIZE blocksize - #define BLOCKS_PER_GROUP 8192 - #define INODES_PER_GROUP 8192 - /* Percentage of blocks that are reserved.*/ - #define RESERVED_BLOCKS 5/100 - #define MAX_RESERVED_BLOCKS 25/100 - -+/* The default value for s_creator_os. */ -+#if defined(__GNU__) -+# define CREATOR_OS 1 /* Hurd */ -+#elif defined(__FreeBSD__) -+# define CREATOR_OS 3 /* FreeBSD */ -+#else -+# define CREATOR_OS 0 /* Linux */ -+#endif -+ - - // inode block size (why is it != BLOCKSIZE ?!?) - /* The field i_blocks in the ext2 inode stores the number of data blocks -@@ -239,10 +250,10 @@ - (fs)->sb.s_blocks_per_group - 1) / (fs)->sb.s_blocks_per_group) - - // Get group block bitmap (bbm) given the group number --#define GRP_GET_GROUP_BBM(fs,grp) ( get_blk((fs),(fs)->gd[(grp)].bg_block_bitmap) ) -+#define GRP_GET_GROUP_BBM(fs,grp) ( get_blk((fs), get_gd((fs),(grp))->bg_block_bitmap) ) - - // Get group inode bitmap (ibm) given the group number --#define GRP_GET_GROUP_IBM(fs,grp) ( get_blk((fs),(fs)->gd[(grp)].bg_inode_bitmap) ) -+#define GRP_GET_GROUP_IBM(fs,grp) ( get_blk((fs), get_gd((fs),(grp))->bg_inode_bitmap) ) - - // Given an inode number find the group it belongs to - #define GRP_GROUP_OF_INODE(fs,nod) ( ((nod)-1) / (fs)->sb.s_inodes_per_group) -@@ -532,7 +543,7 @@ - char d_name[0]; - } directory; - --typedef uint8 block[BLOCKSIZE]; -+typedef uint8 *block; - - /* blockwalker fields: - The blockwalker is used to access all the blocks of a file (including -@@ -571,16 +582,12 @@ - - - /* Filesystem structure that support groups */ --#if BLOCKSIZE == 1024 - typedef struct - { -- block zero; // The famous block 0 -- superblock sb; // The superblock -- groupdescriptor gd[0]; // The group descriptors -+ uint8 zero[1024]; // Room for bootloader stuff -+ superblock sb; // The superblock, always at 1024 -+ // group descriptors come next, see get_gd() below - } filesystem; --#else --#error UNHANDLED BLOCKSIZE --#endif - - // now the endianness swap - -@@ -820,6 +827,14 @@ - return (uint8*)fs + blk*BLOCKSIZE; - } - -+// the group descriptors are aligned on the block size -+static inline groupdescriptor * -+get_gd(filesystem *fs, int no) -+{ -+ int gdblk = (sizeof (filesystem) + BLOCKSIZE - 1) / BLOCKSIZE; -+ return ((groupdescriptor *) get_blk(fs, gdblk)) + no; -+} -+ - // return a given inode from a filesystem - static inline inode * - get_nod(filesystem *fs, uint32 nod) -@@ -829,7 +844,7 @@ - - offset = GRP_IBM_OFFSET(fs,nod); - grp = GRP_GROUP_OF_INODE(fs,nod); -- itab = (inode *)get_blk(fs, fs->gd[grp].bg_inode_table); -+ itab = (inode *)get_blk(fs, get_gd(fs,grp)->bg_inode_table); - return itab+offset-1; - } - -@@ -875,18 +890,18 @@ - - grp = GRP_GROUP_OF_INODE(fs,nod); - nbgroups = GRP_NBGROUPS(fs); -- if(!(bk = allocate(get_blk(fs,fs->gd[grp].bg_block_bitmap), 0))) { -+ if(!(bk = allocate(GRP_GET_GROUP_BBM(fs, grp), 0))) { - for(grp=0;grpgd[grp].bg_block_bitmap),0); -+ bk = allocate(GRP_GET_GROUP_BBM(fs, grp), 0); - grp--; - } - if (!bk) - error_msg_and_die("couldn't allocate a block (no free space)"); -- if(!(fs->gd[grp].bg_free_blocks_count--)) -+ if(!(get_gd(fs, grp)->bg_free_blocks_count--)) - error_msg_and_die("group descr %d. free blocks count == 0 (corrupted fs?)",grp); - if(!(fs->sb.s_free_blocks_count--)) - error_msg_and_die("superblock free blocks count == 0 (corrupted fs?)"); -- return fs->sb.s_blocks_per_group*grp + bk; -+ return fs->sb.s_first_data_block + fs->sb.s_blocks_per_group*grp + (bk-1); - } - - // free a block -@@ -897,8 +912,8 @@ - - grp = bk / fs->sb.s_blocks_per_group; - bk %= fs->sb.s_blocks_per_group; -- deallocate(get_blk(fs,fs->gd[grp].bg_block_bitmap), bk); -- fs->gd[grp].bg_free_blocks_count++; -+ deallocate(GRP_GET_GROUP_BBM(fs, grp), bk); -+ get_gd(fs, grp)->bg_free_blocks_count++; - fs->sb.s_free_blocks_count++; - } - -@@ -918,16 +933,16 @@ - /* We do it for all inodes. */ - avefreei = fs->sb.s_free_inodes_count / nbgroups; - for(grp=0; grpgd[grp].bg_free_inodes_count < avefreei || -- fs->gd[grp].bg_free_inodes_count == 0) -+ if (get_gd(fs, grp)->bg_free_inodes_count < avefreei || -+ get_gd(fs, grp)->bg_free_inodes_count == 0) - continue; - if (!best_group || -- fs->gd[grp].bg_free_blocks_count > fs->gd[best_group].bg_free_blocks_count) -+ get_gd(fs, grp)->bg_free_blocks_count > get_gd(fs, best_group)->bg_free_blocks_count) - best_group = grp; - } -- if (!(nod = allocate(get_blk(fs,fs->gd[best_group].bg_inode_bitmap),0))) -+ if (!(nod = allocate(GRP_GET_GROUP_IBM(fs, best_group), 0))) - error_msg_and_die("couldn't allocate an inode (no free inode)"); -- if(!(fs->gd[best_group].bg_free_inodes_count--)) -+ if(!(get_gd(fs, best_group)->bg_free_inodes_count--)) - error_msg_and_die("group descr. free blocks count == 0 (corrupted fs?)"); - if(!(fs->sb.s_free_inodes_count--)) - error_msg_and_die("superblock free blocks count == 0 (corrupted fs?)"); -@@ -1390,7 +1405,7 @@ - case FM_IFDIR: - add2dir(fs, nod, nod, "."); - add2dir(fs, nod, parent_nod, ".."); -- fs->gd[GRP_GROUP_OF_INODE(fs,nod)].bg_used_dirs_count++; -+ get_gd(fs, GRP_GROUP_OF_INODE(fs,nod))->bg_used_dirs_count++; - break; - } - } -@@ -1860,7 +1875,7 @@ - swap_nod(nod); - } - for(i=0;igd[i])); -+ swap_gd(get_gd(fs, i)); - swap_sb(&fs->sb); - } - -@@ -1870,7 +1885,7 @@ - uint32 i; - swap_sb(&fs->sb); - for(i=0;igd[i])); -+ swap_gd(get_gd(fs, i)); - for(i = 1; i < fs->sb.s_inodes_count; i++) - { - inode *nod = get_nod(fs, i); -@@ -1895,7 +1910,8 @@ - - // initialize an empty filesystem - static filesystem * --init_fs(int nbblocks, int nbinodes, int nbresrvd, int holes, uint32 fs_timestamp) -+init_fs(int nbblocks, int nbinodes, int nbresrvd, int holes, -+ uint32 fs_timestamp, uint32 creator_os) - { - uint32 i; - filesystem *fs; -@@ -1921,10 +1937,14 @@ - */ - min_nbgroups = (nbinodes + INODES_PER_GROUP - 1) / INODES_PER_GROUP; - -+ /* On filesystems with 1k block size, the bootloader area uses a full -+ * block. For 2048 and up, the superblock can be fitted into block 0. -+ */ -+ first_block = (BLOCKSIZE == 1024); -+ - /* nbblocks is the total number of blocks in the filesystem. - * a block group can have no more than 8192 blocks. - */ -- first_block = (BLOCKSIZE == 1024); - nbgroups = (nbblocks - first_block + BLOCKS_PER_GROUP - 1) / BLOCKS_PER_GROUP; - if(nbgroups < min_nbgroups) nbgroups = min_nbgroups; - nbblocks_per_group = rndup((nbblocks - first_block + nbgroups - 1)/nbgroups, 8); -@@ -1936,10 +1956,10 @@ - gdsz = rndup(nbgroups*sizeof(groupdescriptor),BLOCKSIZE)/BLOCKSIZE; - itblsz = nbinodes_per_group * sizeof(inode)/BLOCKSIZE; - overhead_per_group = 3 /*sb,bbm,ibm*/ + gdsz + itblsz; -- if((uint32)nbblocks - 1 < overhead_per_group * nbgroups) -- error_msg_and_die("too much overhead, try fewer inodes or more blocks. Note: options have changed, see --help or the man page."); -- free_blocks = nbblocks - overhead_per_group*nbgroups - 1 /*boot block*/; -+ free_blocks = nbblocks - overhead_per_group*nbgroups - first_block; - free_blocks_per_group = nbblocks_per_group - overhead_per_group; -+ if(free_blocks < 0) -+ error_msg_and_die("too much overhead, try fewer inodes or more blocks. Note: options have changed, see --help or the man page."); - - if(!(fs = (filesystem*)calloc(nbblocks, BLOCKSIZE))) - error_msg_and_die("not enough memory for filesystem"); -@@ -1959,28 +1979,31 @@ - fs->sb.s_wtime = fs_timestamp; - fs->sb.s_magic = EXT2_MAGIC_NUMBER; - fs->sb.s_lastcheck = fs_timestamp; -+ fs->sb.s_creator_os = creator_os; - - // set up groupdescriptors -- for(i=0, bbmpos=gdsz+2, ibmpos=bbmpos+1, itblpos=ibmpos+1; -+ for(i=0, bbmpos=first_block+1+gdsz, ibmpos=bbmpos+1, itblpos=ibmpos+1; - i free_blocks_per_group) { -- fs->gd[i].bg_free_blocks_count = free_blocks_per_group; -+ gd->bg_free_blocks_count = free_blocks_per_group; - free_blocks -= free_blocks_per_group; - } else { -- fs->gd[i].bg_free_blocks_count = free_blocks; -+ gd->bg_free_blocks_count = free_blocks; - free_blocks = 0; // this is the last block group - } - if(i) -- fs->gd[i].bg_free_inodes_count = nbinodes_per_group; -+ gd->bg_free_inodes_count = nbinodes_per_group; - else -- fs->gd[i].bg_free_inodes_count = nbinodes_per_group - -+ gd->bg_free_inodes_count = nbinodes_per_group - - EXT2_FIRST_INO + 2; -- fs->gd[i].bg_used_dirs_count = 0; -- fs->gd[i].bg_block_bitmap = bbmpos; -- fs->gd[i].bg_inode_bitmap = ibmpos; -- fs->gd[i].bg_inode_table = itblpos; -+ gd->bg_used_dirs_count = 0; -+ gd->bg_block_bitmap = bbmpos; -+ gd->bg_inode_bitmap = ibmpos; -+ gd->bg_inode_table = itblpos; - } - - /* Mark non-filesystem blocks and inodes as allocated */ -@@ -1988,9 +2011,9 @@ - for(i = 0; igd[i].bg_block_bitmap); -+ bbm = GRP_GET_GROUP_BBM(fs, i); - //non-filesystem blocks -- for(j = fs->gd[i].bg_free_blocks_count -+ for(j = get_gd(fs, i)->bg_free_blocks_count - + overhead_per_group + 1; j <= BLOCKSIZE * 8; j++) - allocate(bbm, j); - //system blocks -@@ -1998,7 +2021,7 @@ - allocate(bbm, j); - - /* Inode bitmap */ -- ibm = get_blk(fs,fs->gd[i].bg_inode_bitmap); -+ ibm = GRP_GET_GROUP_IBM(fs, i); - //non-filesystem inodes - for(j = fs->sb.s_inodes_per_group+1; j <= BLOCKSIZE * 8; j++) - allocate(ibm, j); -@@ -2012,9 +2035,9 @@ - // make root inode and directory - /* We have groups now. Add the root filesystem in group 0 */ - /* Also increment the directory count for group 0 */ -- fs->gd[0].bg_free_inodes_count--; -- fs->gd[0].bg_used_dirs_count = 1; -- itab0 = (inode *)get_blk(fs,fs->gd[0].bg_inode_table); -+ get_gd(fs, 0)->bg_free_inodes_count--; -+ get_gd(fs, 0)->bg_used_dirs_count = 1; -+ itab0 = (inode *)get_blk(fs, get_gd(fs,0)->bg_inode_table); - itab0[EXT2_ROOT_INO-1].i_mode = FM_IFDIR | FM_IRWXU | FM_IRGRP | FM_IROTH | FM_IXGRP | FM_IXOTH; - itab0[EXT2_ROOT_INO-1].i_ctime = fs_timestamp; - itab0[EXT2_ROOT_INO-1].i_mtime = fs_timestamp; -@@ -2338,8 +2361,9 @@ - for (i = 0; i < GRP_NBGROUPS(fs); i++) { - printf("Group No: %d\n", i+1); - printf("block bitmap: block %d,inode bitmap: block %d, inode table: block %d\n", -- fs->gd[i].bg_block_bitmap, fs->gd[i].bg_inode_bitmap, -- fs->gd[i].bg_inode_table); -+ get_gd(fs, i)->bg_block_bitmap, -+ get_gd(fs, i)->bg_inode_bitmap, -+ get_gd(fs, i)->bg_inode_table); - printf("block bitmap allocation:\n"); - print_bm(GRP_GET_GROUP_BBM(fs, i),fs->sb.s_blocks_per_group); - printf("inode bitmap allocation:\n"); -@@ -2421,10 +2445,12 @@ - " -x, --starting-image \n" - " -d, --root \n" - " -D, --devtable \n" -+ " -B, --block-size \n" - " -b, --size-in-blocks \n" - " -i, --bytes-per-inode \n" - " -N, --number-of-inodes \n" - " -m, --reserved-percentage \n" -+ " -o, --creator-os 'linux', 'hurd', 'freebsd' or a numerical value.\n" - " -g, --block-map Generate a block map file for this path.\n" - " -e, --fill-value Fill unallocated blocks with value.\n" - " -z, --allow-holes Allow files with holes.\n" -@@ -2446,6 +2472,29 @@ - extern char* optarg; - extern int optind, opterr, optopt; - -+// parse the value for -o -+int -+lookup_creator_os(const char *name) -+{ -+ static const char *const creators[] = -+ {"linux", "hurd", "2", "freebsd", NULL}; -+ char *endptr; -+ int i; -+ -+ // numerical value ? -+ i = strtol(name, &endptr, 0); -+ if(name[0] && *endptr == '\0') -+ return i; -+ -+ // symbolic name ? -+ for(i=0; creators[i]; i++) -+ if(strcasecmp(creators[i], name) == 0) -+ return i; -+ -+ // whatever ? -+ return -1; -+} -+ - int - main(int argc, char **argv) - { -@@ -2455,6 +2504,7 @@ - float bytes_per_inode = -1; - float reserved_frac = -1; - int fs_timestamp = -1; -+ int creator_os = CREATOR_OS; - char * fsout = "-"; - char * fsin = 0; - char * dopt[MAX_DOPT]; -@@ -2478,10 +2528,12 @@ - { "starting-image", required_argument, NULL, 'x' }, - { "root", required_argument, NULL, 'd' }, - { "devtable", required_argument, NULL, 'D' }, -+ { "block-size", required_argument, NULL, 'B' }, - { "size-in-blocks", required_argument, NULL, 'b' }, - { "bytes-per-inode", required_argument, NULL, 'i' }, - { "number-of-inodes", required_argument, NULL, 'N' }, - { "reserved-percentage", required_argument, NULL, 'm' }, -+ { "creator-os", required_argument, NULL, 'o' }, - { "block-map", required_argument, NULL, 'g' }, - { "fill-value", required_argument, NULL, 'e' }, - { "allow-holes", no_argument, NULL, 'z' }, -@@ -2497,11 +2549,11 @@ - - app_name = argv[0]; - -- while((c = getopt_long(argc, argv, "x:d:D:b:i:N:m:g:e:zfqUPhVv", longopts, NULL)) != EOF) { -+ while((c = getopt_long(argc, argv, "x:d:D:B:b:i:N:m:o:g:e:zfqUPhVv", longopts, NULL)) != EOF) { - #else - app_name = argv[0]; - -- while((c = getopt(argc, argv, "x:d:D:b:i:N:m:g:e:zfqUPhVv")) != EOF) { -+ while((c = getopt(argc, argv, "x:d:D:B:b:i:N:m:o:g:e:zfqUPhVv")) != EOF) { - #endif /* HAVE_GETOPT_LONG */ - switch(c) - { -@@ -2512,6 +2564,9 @@ - case 'D': - dopt[didx++] = optarg; - break; -+ case 'B': -+ blocksize = SI_atof(optarg); -+ break; - case 'b': - nbblocks = SI_atof(optarg); - break; -@@ -2524,6 +2579,9 @@ - case 'm': - reserved_frac = SI_atof(optarg) / 100; - break; -+ case 'o': -+ creator_os = lookup_creator_os(optarg); -+ break; - case 'g': - gopt[gidx++] = optarg; - break; -@@ -2567,6 +2625,11 @@ - error_msg_and_die("Not enough arguments. Try --help or else see the man page."); - fsout = argv[optind]; - -+ if(blocksize != 1024 && blocksize != 2048 && blocksize != 4096) -+ error_msg_and_die("Valid block sizes: 1024, 2048 or 4096."); -+ if(creator_os < 0) -+ error_msg_and_die("Creator OS unknown."); -+ - hdlinks.hdl = (struct hdlink_s *)malloc(hdlink_cnt * sizeof(struct hdlink_s)); - if (!hdlinks.hdl) - error_msg_and_die("Not enough memory"); -@@ -2611,7 +2674,8 @@ - } - if(fs_timestamp == -1) - fs_timestamp = time(NULL); -- fs = init_fs(nbblocks, nbinodes, nbresrvd, holes, fs_timestamp); -+ fs = init_fs(nbblocks, nbinodes, nbresrvd, holes, -+ fs_timestamp, creator_os); - } - - populate_fs(fs, dopt, didx, squash_uids, squash_perms, fs_timestamp, NULL); -Index: genext2fs/test-gen.lib -=================================================================== ---- genext2fs.orig/test-gen.lib 2011-09-03 13:40:35.000000000 +0200 -+++ genext2fs/test-gen.lib 2011-09-03 14:21:17.000000000 +0200 -@@ -8,7 +8,7 @@ - # Creates an image with a file of given size - # Usage: dgen file-size number-of-blocks - dgen () { -- size=$1; blocks=$2 -+ size=$1; blocks=$2; blocksz=$3; - rm -rf test - mkdir -p test - cd test -@@ -20,7 +20,7 @@ - chmod 777 file.$1 - TZ=UTC-11 touch -t 200502070321.43 file.$1 . - cd .. -- ./genext2fs -N 17 -b $blocks -d test -f -q ext2.img -+ ./genext2fs -B $blocksz -N 17 -b $blocks -d test -f -o Linux -q ext2.img - } - - # fgen - Exercises the -f spec-file option of genext2fs -@@ -31,7 +31,7 @@ - mkdir -p test - cp $fname test - TZ=UTC-11 touch -t 200502070321.43 test/$fname -- ./genext2fs -N 92 -b $blocks -D test/$fname -f ext2.img -+ ./genext2fs -N 92 -b $blocks -D test/$fname -f -o Linux ext2.img - } - - # gen_cleanup - Remove the files generated by the above functions -Index: genext2fs/test-mount.sh -=================================================================== ---- genext2fs.orig/test-mount.sh 2011-09-03 13:40:35.000000000 +0200 -+++ genext2fs/test-mount.sh 2011-09-03 14:21:17.000000000 +0200 -@@ -33,9 +33,9 @@ - # and returns the command line with which to invoke dtest() - # Usage: dtest-mount file-size number-of-blocks - dtest_mount () { -- size=$1; blocks=$2 -- echo Testing with file of size $size -- dgen $size $blocks -+ size=$1; blocks=$2; blocksz=$3; -+ echo Testing $blocks blocks of $blocksz bytes with file of size $size -+ dgen $size $blocks $blocksz - /sbin/e2fsck -fn ext2.img || fail - mkdir -p mnt - mount -t ext2 -o ro,loop ext2.img mnt || fail -@@ -44,7 +44,7 @@ - awk '{print $5}'`" ] ; then - fail - fi -- pass dtest $size $blocks -+ pass dtest $size $blocks $blocksz - } - - # ftest-mount - Exercise the -f spec-file option of genext2fs -@@ -75,13 +75,21 @@ - pass ftest $fname $blocks - } - --dtest_mount 0 4096 --dtest_mount 0 8193 --dtest_mount 0 8194 --dtest_mount 1 4096 --dtest_mount 12288 4096 --dtest_mount 274432 4096 --dtest_mount 8388608 9000 --dtest_mount 16777216 20000 -+dtest_mount 0 4096 1024 -+dtest_mount 0 2048 2048 -+dtest_mount 0 1024 4096 -+dtest_mount 0 8193 1024 -+dtest_mount 0 8194 1024 -+dtest_mount 0 8193 4096 -+dtest_mount 0 8194 2048 -+dtest_mount 1 4096 1024 -+dtest_mount 1 1024 4096 -+dtest_mount 12288 4096 1024 -+dtest_mount 274432 4096 1024 -+dtest_mount 8388608 9000 1024 -+dtest_mount 8388608 4500 2048 -+dtest_mount 8388608 2250 4096 -+dtest_mount 16777216 20000 1024 -+dtest_mount 16777216 10000 2048 - - ftest_mount device_table.txt 4096 -Index: genext2fs/test.sh -=================================================================== ---- genext2fs.orig/test.sh 2011-09-03 13:40:35.000000000 +0200 -+++ genext2fs/test.sh 2011-09-03 14:21:17.000000000 +0200 -@@ -30,9 +30,9 @@ - # Creates an image with a file of given size and verifies it - # Usage: dtest file-size number-of-blocks correct-checksum - dtest () { -- size=$1; blocks=$2; checksum=$3 -+ size=$1; blocks=$2; blocksz=$3; checksum=$4 - echo Testing with file of size $size -- dgen $size $blocks -+ dgen $size $blocks $blocksz - md5cmp $checksum - gen_cleanup - } -@@ -53,12 +53,20 @@ - # replace the following lines with the output of - # sudo sh test-mount.sh|grep test - --dtest 0 4096 3bc6424b8fcd51a0de34ee59d91d5f16 --dtest 0 8193 f174804f6b433b552706cbbfc60c416d --dtest 0 8194 4855a55d0cbdc44584634df49ebd5711 --dtest 1 4096 09c569b6bfb45222c729c42d04d5451f --dtest 12288 4096 61febcbfbf32024ef99103fcdc282c39 --dtest 274432 4096 0c517803552c55c1806e4220b0a0164f --dtest 8388608 9000 e0e5ea15bced10ab486d8135584b5d8e --dtest 16777216 20000 fdf636eb905ab4dc1bf76dce5ac5d209 -+dtest 0 4096 1024 3bc6424b8fcd51a0de34ee59d91d5f16 -+dtest 0 2048 2048 230afa16496df019878cc2370c661cdc -+dtest 0 1024 4096 ebff5eeb38b70f3f1cd081e60eb44561 -+dtest 0 8193 1024 f174804f6b433b552706cbbfc60c416d -+dtest 0 8194 1024 4855a55d0cbdc44584634df49ebd5711 -+dtest 0 8193 4096 c493679698418ec7e6552005e2d2a6d8 -+dtest 0 8194 2048 ec13f328fa7543563f35f494bddc059c -+dtest 1 4096 1024 09c569b6bfb45222c729c42d04d5451f -+dtest 1 1024 4096 d318a326fdc907810ae9e6b0a20e9b06 -+dtest 12288 4096 1024 61febcbfbf32024ef99103fcdc282c39 -+dtest 274432 4096 1024 0c517803552c55c1806e4220b0a0164f -+dtest 8388608 9000 1024 e0e5ea15bced10ab486d8135584b5d8e -+dtest 8388608 4500 2048 39f4d537a72f5053fd6891721c59680d -+dtest 8388608 2250 4096 1d697fa4bc2cfffe02ac91edfadc40bf -+dtest 16777216 20000 1024 fdf636eb905ab4dc1bf76dce5ac5d209 -+dtest 16777216 10000 2048 f9824a81ea5e74fdf469c097927c292b - ftest device_table.txt 4096 a0af06d944b11d2902dfd705484c64cc diff --git a/tools/genext2fs/patches/400-byteswap_fix.patch b/tools/genext2fs/patches/400-byteswap_fix.patch deleted file mode 100644 index 7b3c00b5ee..0000000000 --- a/tools/genext2fs/patches/400-byteswap_fix.patch +++ /dev/null @@ -1,44 +0,0 @@ -Index: genext2fs/genext2fs.c -=================================================================== ---- genext2fs.orig/genext2fs.c 2011-11-29 17:36:06.000000000 +0100 -+++ genext2fs/genext2fs.c 2011-11-29 17:37:37.000000000 +0100 -@@ -1779,7 +1779,8 @@ - assert(nod->i_block[EXT2_DIND_BLOCK] != 0); - for(i = 0; i < BLOCKSIZE/4; i++) - if(nblk > EXT2_IND_BLOCK + BLOCKSIZE/4 + (BLOCKSIZE/4)*i ) -- swap_block(get_blk(fs, ((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i])); -+ if (((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i]) -+ swap_block(get_blk(fs, ((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i])); - swap_block(get_blk(fs, nod->i_block[EXT2_DIND_BLOCK])); - if(nblk <= EXT2_IND_BLOCK + BLOCKSIZE/4 + BLOCKSIZE/4 * BLOCKSIZE/4) - return; -@@ -1792,7 +1793,8 @@ - (BLOCKSIZE/4)*(BLOCKSIZE/4) + - i*(BLOCKSIZE/4)*(BLOCKSIZE/4) + - j*(BLOCKSIZE/4)) ) -- swap_block(get_blk(fs,b2[j])); -+ if (b2[j]) -+ swap_block(get_blk(fs,b2[j])); - else { - done = 1; - break; -@@ -1825,7 +1827,8 @@ - swap_block(get_blk(fs, nod->i_block[EXT2_DIND_BLOCK])); - for(i = 0; i < BLOCKSIZE/4; i++) - if(nblk > EXT2_IND_BLOCK + BLOCKSIZE/4 + (BLOCKSIZE/4)*i ) -- swap_block(get_blk(fs, ((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i])); -+ if (((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i]) -+ swap_block(get_blk(fs, ((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i])); - if(nblk <= EXT2_IND_BLOCK + BLOCKSIZE/4 + BLOCKSIZE/4 * BLOCKSIZE/4) - return; - /* Adding support for triple indirection */ -@@ -1839,7 +1842,8 @@ - (BLOCKSIZE/4)*(BLOCKSIZE/4) + - i*(BLOCKSIZE/4)*(BLOCKSIZE/4) + - j*(BLOCKSIZE/4)) ) -- swap_block(get_blk(fs,b2[j])); -+ if (b2[j]) -+ swap_block(get_blk(fs,b2[j])); - else { - done = 1; - break; From 2c603ecb55b2d9de83d4651e0cf2cc29db348fc7 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 23 Oct 2022 01:43:36 +0200 Subject: [PATCH 40/80] tools/genext2fs: Add dependency to libtool This fixes the following build error: ./autogen.sh: line 13: aclocal: command not found Fixes: b6d29af9475f ("tools/genext2fs: update to 1.5.0") Signed-off-by: Hauke Mehrtens --- tools/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/Makefile b/tools/Makefile index 10ac348bfe..1a65afdfca 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -52,6 +52,7 @@ $(curdir)/fakeroot/compile := $(curdir)/libtool/compile $(curdir)/findutils/compile := $(curdir)/bison/compile $(curdir)/firmware-utils/compile += $(curdir)/cmake/compile $(curdir)/flex/compile := $(curdir)/libtool/compile +$(curdir)/genext2fs/compile := $(curdir)/libtool/compile $(curdir)/gengetopt/compile := $(curdir)/libtool/compile $(curdir)/gmp/compile := $(curdir)/libtool/compile $(curdir)/isl/compile := $(curdir)/gmp/compile From 802ca492d85e6f6af05676518889d4de50697477 Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Wed, 5 Oct 2022 23:05:26 +0200 Subject: [PATCH 41/80] lantiq: add 6.1 tag to upstream patch Add 6.1 tag to upstream patch now that 6.1 got tagged. This permits to track patch in a better way and directly drop them on kernel bump. Signed-off-by: Aleksander Jan Bajkowski --- ...PS-lantiq-enable-all-hardware-interrupts-on-second.patch} | 5 +++-- ...PS-lantiq-enable-all-hardware-interrupts-on-second.patch} | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) rename target/linux/lantiq/patches-5.10/{0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch => 0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch} (94%) rename target/linux/lantiq/patches-5.15/{0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch => 0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch} (94%) diff --git a/target/linux/lantiq/patches-5.10/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch b/target/linux/lantiq/patches-5.10/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch similarity index 94% rename from target/linux/lantiq/patches-5.10/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch rename to target/linux/lantiq/patches-5.10/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch index 0ac9adfb96..b7b95d6bfc 100644 --- a/target/linux/lantiq/patches-5.10/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch +++ b/target/linux/lantiq/patches-5.10/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch @@ -1,6 +1,6 @@ -From 2025bc9c3a949b65bfd0601f727678b37962c6c5 Mon Sep 17 00:00:00 2001 +From 730320fd770d4114a2ecb6fb223dcc8c3cecdc5b Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski -Date: Fri, 4 Jun 2021 18:27:58 +0200 +Date: Wed, 21 Sep 2022 22:59:44 +0200 Subject: [PATCH] MIPS: lantiq: enable all hardware interrupts on second VPE This patch is needed to handle interrupts by the second VPE on the Lantiq @@ -32,6 +32,7 @@ Tested on Lantiq xRX200. Suggested-by: Thomas Bogendoerfer Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Thomas Bogendoerfer --- arch/mips/lantiq/prom.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/target/linux/lantiq/patches-5.15/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch b/target/linux/lantiq/patches-5.15/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch similarity index 94% rename from target/linux/lantiq/patches-5.15/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch rename to target/linux/lantiq/patches-5.15/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch index ad7f781e21..d83a3616b3 100644 --- a/target/linux/lantiq/patches-5.15/0320-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch +++ b/target/linux/lantiq/patches-5.15/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch @@ -1,6 +1,6 @@ -From 2025bc9c3a949b65bfd0601f727678b37962c6c5 Mon Sep 17 00:00:00 2001 +From 730320fd770d4114a2ecb6fb223dcc8c3cecdc5b Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski -Date: Fri, 4 Jun 2021 18:27:58 +0200 +Date: Wed, 21 Sep 2022 22:59:44 +0200 Subject: [PATCH] MIPS: lantiq: enable all hardware interrupts on second VPE This patch is needed to handle interrupts by the second VPE on the Lantiq @@ -32,6 +32,7 @@ Tested on Lantiq xRX200. Suggested-by: Thomas Bogendoerfer Signed-off-by: Aleksander Jan Bajkowski +Signed-off-by: Thomas Bogendoerfer --- arch/mips/lantiq/prom.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) From 7b863af180dac48ea392a5ee582e37d0f378b3d3 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 1 Jun 2022 23:16:04 +0800 Subject: [PATCH 42/80] kernel: move mac-address-ascii patches to generic This enables other targets to use the mac-address-ascii feature. Signed-off-by: Chukun Pan --- .../hack-5.10/601-of_net-add-mac-address-ascii-support.patch} | 4 ++-- .../hack-5.15/601-of_net-add-mac-address-ascii-support.patch} | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) rename target/linux/{ath79/patches-5.10/600-of_net-add-mac-address-ascii-support.patch => generic/hack-5.10/601-of_net-add-mac-address-ascii-support.patch} (95%) rename target/linux/{ath79/patches-5.15/600-of_net-add-mac-address-ascii-support.patch => generic/hack-5.15/601-of_net-add-mac-address-ascii-support.patch} (95%) diff --git a/target/linux/ath79/patches-5.10/600-of_net-add-mac-address-ascii-support.patch b/target/linux/generic/hack-5.10/601-of_net-add-mac-address-ascii-support.patch similarity index 95% rename from target/linux/ath79/patches-5.10/600-of_net-add-mac-address-ascii-support.patch rename to target/linux/generic/hack-5.10/601-of_net-add-mac-address-ascii-support.patch index 7f95852c7e..f73e262bba 100644 --- a/target/linux/ath79/patches-5.10/600-of_net-add-mac-address-ascii-support.patch +++ b/target/linux/generic/hack-5.10/601-of_net-add-mac-address-ascii-support.patch @@ -11,7 +11,7 @@ Submitted-by: Yousong Zhou --- a/net/ethernet/eth.c +++ b/net/ethernet/eth.c -@@ -545,6 +545,63 @@ int eth_platform_get_mac_address(struct +@@ -539,6 +539,63 @@ int eth_platform_get_mac_address(struct } EXPORT_SYMBOL(eth_platform_get_mac_address); @@ -75,7 +75,7 @@ Submitted-by: Yousong Zhou /** * Obtain the MAC address from an nvmem cell named 'mac-address' associated * with given device. -@@ -558,19 +615,23 @@ int nvmem_get_mac_address(struct device +@@ -552,19 +609,23 @@ int nvmem_get_mac_address(struct device { struct nvmem_cell *cell; const void *mac; diff --git a/target/linux/ath79/patches-5.15/600-of_net-add-mac-address-ascii-support.patch b/target/linux/generic/hack-5.15/601-of_net-add-mac-address-ascii-support.patch similarity index 95% rename from target/linux/ath79/patches-5.15/600-of_net-add-mac-address-ascii-support.patch rename to target/linux/generic/hack-5.15/601-of_net-add-mac-address-ascii-support.patch index ff22945eb4..83483751f8 100644 --- a/target/linux/ath79/patches-5.15/600-of_net-add-mac-address-ascii-support.patch +++ b/target/linux/generic/hack-5.15/601-of_net-add-mac-address-ascii-support.patch @@ -11,7 +11,7 @@ Submitted-by: Yousong Zhou --- a/net/ethernet/eth.c +++ b/net/ethernet/eth.c -@@ -544,6 +544,63 @@ int eth_platform_get_mac_address(struct +@@ -538,6 +538,63 @@ int eth_platform_get_mac_address(struct } EXPORT_SYMBOL(eth_platform_get_mac_address); @@ -75,7 +75,7 @@ Submitted-by: Yousong Zhou /** * nvmem_get_mac_address - Obtain the MAC address from an nvmem cell named * 'mac-address' associated with given device. -@@ -557,19 +614,23 @@ int nvmem_get_mac_address(struct device +@@ -551,19 +608,23 @@ int nvmem_get_mac_address(struct device { struct nvmem_cell *cell; const void *mac; From 4f9b360f0b9a85202422ef07ee573eeca06d11ab Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Thu, 2 Jun 2022 23:01:29 +0800 Subject: [PATCH 43/80] ramips: add A-040W-Q alternative name for MSG1500 X.00 The hardware of Nokia A-040W-Q and RAISECOM MSG1500 X.00 are exactly the same, both of which are customized by operators. Signed-off-by: Chukun Pan --- target/linux/ramips/image/mt7621.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk index c1a9ecfaeb..75e21bd93d 100644 --- a/target/linux/ramips/image/mt7621.mk +++ b/target/linux/ramips/image/mt7621.mk @@ -1669,6 +1669,8 @@ define Device/raisecom_msg1500-x-00 DEVICE_VENDOR := RAISECOM DEVICE_MODEL := MSG1500 DEVICE_VARIANT := X.00 + DEVICE_ALT0_VENDOR := Nokia + DEVICE_ALT0_MODEL := A-040W-Q DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3 \ kmod-usb-ledtrig-usbport uboot-envtools endef From f6099d797460b23e06fb0c391606346993b4593e Mon Sep 17 00:00:00 2001 From: Alex Khodin Date: Fri, 21 Oct 2022 17:47:38 +0000 Subject: [PATCH 44/80] ramips: mt7621: enable lzma-loader for Asus RT-N56U-B1 Fixes boot loader LZMA decompression issues. Without this change the board end up in a boot loop. Signed-off-by: Alex Khodin --- target/linux/ramips/image/mt7621.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk index 75e21bd93d..30d928fdad 100644 --- a/target/linux/ramips/image/mt7621.mk +++ b/target/linux/ramips/image/mt7621.mk @@ -291,6 +291,7 @@ TARGET_DEVICES += asus_rt-ac85p define Device/asus_rt-n56u-b1 $(Device/dsa-migration) + $(Device/uimage-lzma-loader) DEVICE_VENDOR := ASUS DEVICE_MODEL := RT-N56U DEVICE_VARIANT := B1 From ac296f621058119501ccd54e7cb2a243af5dc5a0 Mon Sep 17 00:00:00 2001 From: Robert Senderek Date: Mon, 17 Oct 2022 21:15:35 +0200 Subject: [PATCH 45/80] ramips: rt3883: enable lzma-loader for Belkin F9K1109v1 Fixes boot loader LZMA decompression issues Fixes: #10968 Signed-off-by: Robert Senderek --- target/linux/ramips/image/rt3883.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ramips/image/rt3883.mk b/target/linux/ramips/image/rt3883.mk index e76678be1a..f5439bd0a3 100644 --- a/target/linux/ramips/image/rt3883.mk +++ b/target/linux/ramips/image/rt3883.mk @@ -18,6 +18,7 @@ endef TARGET_DEVICES += asus_rt-n56u define Device/belkin_f9k1109v1 + $(Device/uimage-lzma-loader) SOC := rt3883 BLOCKSIZE := 64k DEVICE_VENDOR := Belkin @@ -25,7 +26,6 @@ define Device/belkin_f9k1109v1 DEVICE_VARIANT := Version 1.0 DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport IMAGE_SIZE := 7808k - KERNEL := kernel-bin | append-dtb | lzma -d16 | uImage lzma # Stock firmware checks for this uImage image name during upload. UIMAGE_NAME := N750F9K1103VB endef From 67660d36674c8c1504cbf3cd199409d0b209f802 Mon Sep 17 00:00:00 2001 From: David Bentham Date: Mon, 17 Oct 2022 15:43:29 +0100 Subject: [PATCH 46/80] ramips: fix WAN mac address allocation for Unielec 01 and 06 models Manufacturer has predetermined mac address values for lan and wan ports. This change keeps inline with other mt7621 devices mac address allocation from factory mtd partition. Example from hexdump output: 0xe000 0x6 (lan) - 0xe006 0x6 (wan) 0000e000 70 b3 d5 10 02 96 70 b3 d5 10 02 95 ff ff ff ff Previous change had created an overlapping mac address situation as it would increment by one based on the lan mac address location found in the factory partition, which would sometimes increment to the same as the mt7603 wifi chip. Tested on Unielec u7621-01 model Signed-off-by: David Bentham --- target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts | 7 +++++-- target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts | 7 +++++-- target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts | 7 +++++-- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts b/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts index 6e75d1b930..8780b17b80 100644 --- a/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts +++ b/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts @@ -53,9 +53,8 @@ }; &gmac1 { - nvmem-cells = <&macaddr_factory_e000>; + nvmem-cells = <&macaddr_factory_e006>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; &factory { @@ -66,4 +65,8 @@ macaddr_factory_e000: macaddr@e000 { reg = <0xe000 0x6>; }; + + macaddr_factory_e006: macaddr@e006 { + reg = <0xe006 0x6>; + }; }; diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts b/target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts index d7dd4ccd46..212c000942 100644 --- a/target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts +++ b/target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts @@ -58,9 +58,8 @@ }; &gmac1 { - nvmem-cells = <&macaddr_factory_e000>; + nvmem-cells = <&macaddr_factory_e006>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; &factory { @@ -71,4 +70,8 @@ macaddr_factory_e000: macaddr@e000 { reg = <0xe000 0x6>; }; + + macaddr_factory_e006: macaddr@e006 { + reg = <0xe006 0x6>; + }; }; diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts b/target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts index 669340f194..f196432111 100644 --- a/target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts +++ b/target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts @@ -59,9 +59,8 @@ }; &gmac1 { - nvmem-cells = <&macaddr_factory_e000>; + nvmem-cells = <&macaddr_factory_e006>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; &factory { @@ -72,4 +71,8 @@ macaddr_factory_e000: macaddr@e000 { reg = <0xe000 0x6>; }; + + macaddr_factory_e006: macaddr@e006 { + reg = <0xe006 0x6>; + }; }; From a716ac55649707e8279de6f2ea66c7f6060c982c Mon Sep 17 00:00:00 2001 From: Pavel Kamaev Date: Sun, 16 Oct 2022 21:27:47 +0300 Subject: [PATCH 47/80] ath79: fix reference clock for RouterBoard 912UAG This fixes reference clock frequency of RB912. 25 MHz frequency leads to system clock running too fast, uptime incrementing too fast and delays (like `sleep 10`) returning too early. Board has quartz with NSK 3KHAA Z 40 000 marking. Signed-off-by: Pavel Kamaev --- .../ath79/dts/ar9342_mikrotik_routerboard-912uag-2hpnd.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912uag-2hpnd.dts b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912uag-2hpnd.dts index 6435393a73..28a88db5df 100644 --- a/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912uag-2hpnd.dts +++ b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912uag-2hpnd.dts @@ -147,7 +147,7 @@ }; &ref { - clock-frequency = <25000000>; + clock-frequency = <40000000>; }; &spi { From 57577bb8ccaa79adc30e0c4b1f85a88a84e3ebfe Mon Sep 17 00:00:00 2001 From: Jack Chen Date: Fri, 14 Oct 2022 15:58:46 +0800 Subject: [PATCH 48/80] ipq40xx: convert to DSA and enable mobipromo,cm520-79f Convert to DSA and enable the MobiPromo CM520-79F device again. Signed-off-by: Jack Chen Reviewed-by: Robert Marko --- .../ipq40xx/base-files/etc/board.d/01_leds | 6 ++-- .../ipq40xx/base-files/etc/board.d/02_network | 3 +- .../arm/boot/dts/qcom-ipq4019-cm520-79f.dts | 30 +++++++++++++++++++ target/linux/ipq40xx/image/generic.mk | 3 +- 4 files changed, 36 insertions(+), 6 deletions(-) diff --git a/target/linux/ipq40xx/base-files/etc/board.d/01_leds b/target/linux/ipq40xx/base-files/etc/board.d/01_leds index 748b6f5b82..ac03c3317a 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/01_leds +++ b/target/linux/ipq40xx/base-files/etc/board.d/01_leds @@ -81,9 +81,9 @@ mikrotik,sxtsq-5-ac) ucidef_set_led_rssi "rssihigh" "rssihigh" "green:rssihigh" "wlan0" "81" "100" ;; mobipromo,cm520-79f) - ucidef_set_led_netdev "wan" "WAN" "blue:wan" "eth1" - ucidef_set_led_switch "lan1" "LAN1" "blue:lan1" "switch0" "0x10" - ucidef_set_led_switch "lan2" "LAN2" "blue:lan2" "switch0" "0x08" + ucidef_set_led_netdev "wan" "WAN" "blue:wan" "wan" + ucidef_set_led_netdev "lan1" "LAN1" "blue:lan1" "lan1" + ucidef_set_led_netdev "lan2" "LAN2" "blue:lan2" "lan2" ;; netgear,ex6100v2 |\ netgear,ex6150v2) diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network index 56d38bd6a7..fc9751eb13 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/02_network +++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network @@ -56,7 +56,8 @@ ipq40xx_setup_interfaces() compex,wpj428) ucidef_set_interface_lan "lan1 lan2" ;; - glinet,gl-b1300) + glinet,gl-b1300|\ + mobipromo,cm520-79f) ucidef_set_interfaces_lan_wan "lan1 lan2" "wan" ;; mikrotik,wap-ac) diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts index 036bace182..1dde17e293 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts @@ -342,6 +342,36 @@ status = "okay"; }; +&gmac { + status = "okay"; + + nvmem-cells = <&macaddr_art_1006>; + nvmem-cell-names = "mac-address"; +}; + +&switch { + status = "okay"; +}; + +&swport3 { + status = "okay"; + + label = "lan2"; +}; + +&swport4 { + status = "okay"; + + label = "lan1"; +}; + +&swport5 { + status = "okay"; + + nvmem-cells = <&macaddr_art_5006>; + nvmem-cell-names = "mac-address"; +}; + &wifi0 { status = "okay"; nvmem-cell-names = "pre-calibration"; diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 0a7fee159d..fd3140c2aa 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -761,8 +761,7 @@ define Device/mobipromo_cm520-79f PAGESIZE := 2048 DEVICE_PACKAGES := kmod-usb-ledtrig-usbport endef -# Missing DSA Setup -#TARGET_DEVICES += mobipromo_cm520-79f +TARGET_DEVICES += mobipromo_cm520-79f define Device/netgear_ex61x0v2 $(call Device/DniImage) From 78cbcc77cc33638b185f85c0e40daee1906a2c3c Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 21 Oct 2022 14:23:47 +0200 Subject: [PATCH 49/80] ksmbd: update to 3.4.6 Release Announcement: https://github.com/cifsd-team/ksmbd/releases/tag/3.4.6 Remove upstreamed: - 10-fix-build-on-kernel-5.15.52-or-higher.patch Signed-off-by: Nick Hainke --- package/kernel/ksmbd/Makefile | 4 +- ...ix-build-on-kernel-5.15.52-or-higher.patch | 69 ------------------- 2 files changed, 2 insertions(+), 71 deletions(-) delete mode 100644 package/kernel/ksmbd/patches/10-fix-build-on-kernel-5.15.52-or-higher.patch diff --git a/package/kernel/ksmbd/Makefile b/package/kernel/ksmbd/Makefile index 0f79644552..86207508e5 100644 --- a/package/kernel/ksmbd/Makefile +++ b/package/kernel/ksmbd/Makefile @@ -1,12 +1,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ksmbd -PKG_VERSION:=3.4.5 +PKG_VERSION:=3.4.6 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://codeload.github.com/cifsd-team/cifsd/tar.gz/$(PKG_VERSION)? -PKG_HASH:=2873c8ba1027fc5b04c5f5344804ef1469ad7019a033456c16ca4aa3f2c161f0 +PKG_HASH:=d742992692dbe164060d2a0ea668895ed2b86252f10427db3d3a002df44c445b PKG_LICENSE:=GPL-2.0-or-later PKG_LICENSE_FILES:=COPYING diff --git a/package/kernel/ksmbd/patches/10-fix-build-on-kernel-5.15.52-or-higher.patch b/package/kernel/ksmbd/patches/10-fix-build-on-kernel-5.15.52-or-higher.patch deleted file mode 100644 index 68cf168569..0000000000 --- a/package/kernel/ksmbd/patches/10-fix-build-on-kernel-5.15.52-or-higher.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 98bc509f92cccedd7d51d5ebadc424e2d7f5cbb4 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Tue, 5 Jul 2022 15:20:10 +0800 -Subject: [PATCH] ksmbd: fixes build on kernel 5.15.52 or higher - -The 5.15.52 kernel downported two commits "fs: remove unused low-level -mapping helpers" and "fs: use low-level mapping helpers", which broken -the compilation[1]. This commit fixed it. - -1. https://cdn.kernel.org/pub/linux/kernel/v5.x/ChangeLog-5.15.52 - -Signed-off-by: Chukun Pan -Signed-off-by: Namjae Jeon ---- - smbacl.c | 6 ++++-- - smbacl.h | 6 ++++-- - 2 files changed, 8 insertions(+), 4 deletions(-) - -diff --git a/smbacl.c b/smbacl.c -index 275e357..19c682a 100644 ---- a/smbacl.c -+++ b/smbacl.c -@@ -281,7 +281,8 @@ static int sid_to_id(struct user_namespace *user_ns, - uid_t id; - - id = le32_to_cpu(psid->sub_auth[psid->num_subauth - 1]); --#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) || \ -+ (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 52) && LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)) - uid = mapped_kuid_user(user_ns, &init_user_ns, KUIDT_INIT(id)); - #else - /* -@@ -304,7 +305,8 @@ static int sid_to_id(struct user_namespace *user_ns, - gid_t id; - - id = le32_to_cpu(psid->sub_auth[psid->num_subauth - 1]); --#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) || \ -+ (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 52) && LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)) - gid = mapped_kgid_user(user_ns, &init_user_ns, KGIDT_INIT(id)); - #else - /* -diff --git a/smbacl.h b/smbacl.h -index f2bcdb4..7368bf4 100644 ---- a/smbacl.h -+++ b/smbacl.h -@@ -221,7 +221,8 @@ static inline uid_t posix_acl_uid_translate(struct user_namespace *mnt_userns, - kuid_t kuid; - - /* If this is an idmapped mount, apply the idmapping. */ --#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) || \ -+ (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 52) && LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)) - kuid = mapped_kuid_fs(mnt_userns, &init_user_ns, pace->e_uid); - #else - kuid = kuid_into_mnt(mnt_userns, pace->e_uid); -@@ -241,7 +242,8 @@ static inline gid_t posix_acl_gid_translate(struct user_namespace *mnt_userns, - kgid_t kgid; - - /* If this is an idmapped mount, apply the idmapping. */ --#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) || \ -+ (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 52) && LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)) - kgid = mapped_kgid_fs(mnt_userns, &init_user_ns, pace->e_gid); - #else - kgid = kgid_into_mnt(mnt_userns, pace->e_gid); --- -2.36.1 - From a3da858ab03088088dca9aabf0c8b379385ad671 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Sat, 22 Oct 2022 13:00:38 -0700 Subject: [PATCH 50/80] ipq40xx: Convert Google Wifi to DSA, reenable Undo parts of these: 116feb4a1cad ipq40xx: remove non-converted network configs db19efee9512 ipq40xx: disable boards not converted to DSA Reintroduce the DT paths /soc/edma@c080000/gmac{0,1}, because the stock bootloader has memorized them (instead of following aliases); then plug the MAC address back in via 05_set_iface_mac_ipq40xx.sh, since the 'local-mac-address' property is no longer in the correct node. Cc: David Bauer Cc: Robert Marko Signed-off-by: Brian Norris --- .../ipq40xx/base-files/etc/board.d/02_network | 5 +++ .../arch/arm/boot/dts/qcom-ipq4019-wifi.dts | 42 +++++++++++++++++++ target/linux/ipq40xx/image/chromium.mk | 3 +- 3 files changed, 48 insertions(+), 2 deletions(-) diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network index fc9751eb13..57c228e123 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/02_network +++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network @@ -32,6 +32,7 @@ ipq40xx_setup_interfaces() cilab,meshpoint-one|\ edgecore,ecw5211|\ glinet,gl-b2200|\ + google,wifi|\ luma,wrtq-329acn|\ mikrotik,cap-ac|\ netgear,wac510|\ @@ -119,6 +120,10 @@ ipq40xx_setup_macs() ezviz,cs-w3-wd1200g-eup) label_mac=$(mtd_get_mac_binary "ART" 0x6) ;; + google,wifi) + wan_mac=$(get_mac_label) + lan_mac=$(macaddr_add "$wan_mac" 1) + ;; linksys,ea6350v3|\ linksys,ea8300 |\ linksys,mr8300) diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wifi.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wifi.dts index 643449f8e4..65f5933305 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wifi.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wifi.dts @@ -13,6 +13,10 @@ model = "Google WiFi (Gale)"; compatible = "google,wifi", "google,gale-v2", "qcom,ipq4019"; + aliases { + label-mac-device = &gmac0; + }; + chosen { /* * rootwait: in case we're booting from slow/async USB storage. @@ -25,6 +29,26 @@ device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512MB */ }; + + soc { + edma@c080000 { + /* + * Factory bootloader (depthcharge) will fail to boot + * if this exact path (soc/edma@c080000/gmac0) doesn't + * exist. + */ + gmac0: gmac0 { + }; + + /* + * Factory bootloader (depthcharge) will fail to boot + * if this exact path (soc/edma@c080000/gmac1) doesn't + * exist. + */ + gmac1 { + }; + }; + }; }; &tlmm { @@ -325,6 +349,10 @@ status = "okay"; }; +&gmac { + status = "okay"; +}; + &mdio { status = "okay"; pinctrl-0 = <&mdio_pins>; @@ -344,6 +372,20 @@ non-removable; }; +&switch { + status = "okay"; +}; + +&swport4 { + status = "okay"; + + label = "lan"; +}; + +&swport5 { + status = "okay"; +}; + &usb2 { status = "okay"; }; diff --git a/target/linux/ipq40xx/image/chromium.mk b/target/linux/ipq40xx/image/chromium.mk index 7410794fb4..2abd2df02a 100644 --- a/target/linux/ipq40xx/image/chromium.mk +++ b/target/linux/ipq40xx/image/chromium.mk @@ -33,5 +33,4 @@ define Device/google_wifi DEVICE_PACKAGES := partx-utils mkf2fs e2fsprogs \ kmod-fs-ext4 kmod-fs-f2fs kmod-google-firmware endef -# Missing DSA Setup -#TARGET_DEVICES += google_wifi +TARGET_DEVICES += google_wifi From e3706bf49756557636105f0d5f6ecf45d5b12e20 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 23 Oct 2022 16:21:26 +0100 Subject: [PATCH 51/80] tools/mkimage: bring back removed patches Patches for mtk_image supporting newer SoCs have been dropped in the process of updating mkimage to U-Boot 2022.10. While it is true that the patches have been merged upstream a while ago, they were not merged in time to be part of the U-Boot 2022.10 release. See also commit 537b423d9f ("uboot-mediatek: update to U-Boot 2022.10") which explicitly mentions that. Fixes: 6e245777bd ("tools/mkimage: update to 2022.10") Signed-off-by: Daniel Golle --- ...split-gfh-header-verification-into-a.patch | 89 ++ ...split-the-code-of-generating-NAND-he.patch | 821 ++++++++++++++++++ ...add-support-for-nand-headers-used-by.patch | 702 +++++++++++++++ 3 files changed, 1612 insertions(+) create mode 100644 tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch create mode 100644 tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch create mode 100644 tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch diff --git a/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch b/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch new file mode 100644 index 0000000000..c8747ae154 --- /dev/null +++ b/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch @@ -0,0 +1,89 @@ +From b6bb61fd3818f4a3025fedbe4d15dbeeaef6ee82 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Tue, 2 Aug 2022 17:21:34 +0800 +Subject: [PATCH 28/31] tools: mtk_image: split gfh header verification into a + new function + +The verification code of gfh header for NAND and non-NAND are identical. +It's better to define a individual function to reduce redundancy. + +Reviewed-by: Simon Glass +Signed-off-by: Weijie Gao +--- + tools/mtk_image.c | 51 +++++++++++++++++++---------------------------- + 1 file changed, 21 insertions(+), 30 deletions(-) + +--- a/tools/mtk_image.c ++++ b/tools/mtk_image.c +@@ -480,6 +480,25 @@ static int mtk_image_vrec_header(struct + return SHA256_SUM_LEN; + } + ++static int mtk_image_verify_gfh(struct gfh_header *gfh, uint32_t type, int print) ++{ ++ if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) ++ return -1; ++ ++ if (le32_to_cpu(gfh->file_info.flash_type) != type) ++ return -1; ++ ++ if (print) ++ printf("Load Address: %08x\n", ++ le32_to_cpu(gfh->file_info.load_addr) + ++ le32_to_cpu(gfh->file_info.jump_offset)); ++ ++ if (print) ++ printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); ++ ++ return 0; ++} ++ + static int mtk_image_verify_gen_header(const uint8_t *ptr, int print) + { + union gen_boot_header *gbh = (union gen_boot_header *)ptr; +@@ -542,21 +561,7 @@ static int mtk_image_verify_gen_header(c + + gfh = (struct gfh_header *)(ptr + gfh_offset); + +- if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) +- return -1; +- +- if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_GEN) +- return -1; +- +- if (print) +- printf("Load Address: %08x\n", +- le32_to_cpu(gfh->file_info.load_addr) + +- le32_to_cpu(gfh->file_info.jump_offset)); +- +- if (print) +- printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); +- +- return 0; ++ return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_GEN, print); + } + + static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) +@@ -610,21 +615,7 @@ static int mtk_image_verify_nand_header( + + gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); + +- if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) +- return -1; +- +- if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_NAND) +- return -1; +- +- if (print) +- printf("Load Address: %08x\n", +- le32_to_cpu(gfh->file_info.load_addr) + +- le32_to_cpu(gfh->file_info.jump_offset)); +- +- if (print) +- printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); +- +- return 0; ++ return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); + } + + static uint32_t crc32be_cal(const void *data, size_t length) diff --git a/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch b/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch new file mode 100644 index 0000000000..9a5332f695 --- /dev/null +++ b/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch @@ -0,0 +1,821 @@ +From 20ebf03eab571b25e9f62b2764ab84932111dcd6 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Tue, 2 Aug 2022 17:23:57 +0800 +Subject: [PATCH 29/31] tools: mtk_image: split the code of generating NAND + header into a new file + +The predefined NAND headers take too much spaces in the mtk_image.c. +Moving them into a new file can significantly improve the readability of +both mtk_image.c and the new mtk_nand_headers.c. + +This is a preparation for adding more NAND headers. + +Reviewed-by: Simon Glass +Signed-off-by: Weijie Gao +--- + tools/Makefile | 1 + + tools/mtk_image.c | 305 ++++++--------------------------------- + tools/mtk_image.h | 25 ---- + tools/mtk_nand_headers.c | 286 ++++++++++++++++++++++++++++++++++++ + tools/mtk_nand_headers.h | 61 ++++++++ + 5 files changed, 389 insertions(+), 289 deletions(-) + create mode 100644 tools/mtk_nand_headers.c + create mode 100644 tools/mtk_nand_headers.h + +--- a/tools/Makefile ++++ b/tools/Makefile +@@ -147,6 +147,7 @@ dumpimage-mkimage-objs := aisimage.o \ + gpimage.o \ + gpimage-common.o \ + mtk_image.o \ ++ mtk_nand_headers.o \ + $(ECDSA_OBJS-y) \ + $(RSA_OBJS-y) \ + $(AES_OBJS-y) +--- a/tools/mtk_image.c ++++ b/tools/mtk_image.c +@@ -12,216 +12,7 @@ + #include + #include "imagetool.h" + #include "mtk_image.h" +- +-/* NAND header for SPI-NAND with 2KB page + 64B spare */ +-static const union nand_boot_header snand_hdr_2k_64_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, +- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, +- 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, +- 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, +- 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 +- } +-}; +- +-/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ +-static const union nand_boot_header snand_hdr_2k_128_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, +- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, +- 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, +- 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, +- 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 +- } +-}; +- +-/* NAND header for SPI-NAND with 4KB page + 256B spare */ +-static const union nand_boot_header snand_hdr_4k_256_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, +- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, +- 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, +- 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, +- 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 +- } +-}; +- +-/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ +-static const union nand_boot_header nand_hdr_1gb_2k_64_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, +- 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, +- 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, +- 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, +- 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 +- } +-}; +- +-/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ +-static const union nand_boot_header nand_hdr_2gb_2k_64_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, +- 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, +- 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, +- 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, +- 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 +- } +-}; +- +-/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ +-static const union nand_boot_header nand_hdr_4gb_2k_64_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, +- 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, +- 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, +- 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, +- 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 +- } +-}; +- +-/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ +-static const union nand_boot_header nand_hdr_2gb_2k_128_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, +- 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, +- 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, +- 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, +- 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 +- } +-}; +- +-/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ +-static const union nand_boot_header nand_hdr_4gb_2k_128_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, +- 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, +- 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, +- 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, +- 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 +- } +-}; +- +-static const struct nand_header_type { +- const char *name; +- const union nand_boot_header *data; +-} nand_headers[] = { +- { +- .name = "2k+64", +- .data = &snand_hdr_2k_64_data +- }, { +- .name = "2k+120", +- .data = &snand_hdr_2k_128_data +- }, { +- .name = "2k+128", +- .data = &snand_hdr_2k_128_data +- }, { +- .name = "4k+256", +- .data = &snand_hdr_4k_256_data +- }, { +- .name = "1g:2k+64", +- .data = &nand_hdr_1gb_2k_64_data +- }, { +- .name = "2g:2k+64", +- .data = &nand_hdr_2gb_2k_64_data +- }, { +- .name = "4g:2k+64", +- .data = &nand_hdr_4gb_2k_64_data +- }, { +- .name = "2g:2k+128", +- .data = &nand_hdr_2gb_2k_128_data +- }, { +- .name = "4g:2k+128", +- .data = &nand_hdr_4gb_2k_128_data +- } +-}; ++#include "mtk_nand_headers.h" + + static const struct brom_img_type { + const char *name; +@@ -264,6 +55,7 @@ static uint32_t crc32tbl[256]; + + /* NAND header selected by user */ + static const union nand_boot_header *hdr_nand; ++static uint32_t hdr_nand_size; + + /* GFH header + 2 * 4KB pages of NAND */ + static char hdr_tmp[sizeof(struct gfh_header) + 0x2000]; +@@ -402,12 +194,7 @@ static int mtk_brom_parse_imagename(cons + } + + /* parse nand header type */ +- for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { +- if (!strcmp(nand_headers[i].name, nandinfo)) { +- hdr_nand = nand_headers[i].data; +- break; +- } +- } ++ hdr_nand = mtk_nand_header_find(nandinfo); + + /* parse device header offset */ + if (hdr_offs && hdr_offs[0]) +@@ -432,6 +219,9 @@ static int mtk_brom_parse_imagename(cons + return -EINVAL; + } + ++ if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) ++ hdr_nand_size = mtk_nand_header_size(hdr_nand); ++ + return 0; + } + +@@ -468,7 +258,7 @@ static int mtk_image_vrec_header(struct + } + + if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) +- tparams->header_size = 2 * le16_to_cpu(hdr_nand->pagesize); ++ tparams->header_size = hdr_nand_size; + else + tparams->header_size = sizeof(struct gen_device_header); + +@@ -566,16 +356,17 @@ static int mtk_image_verify_gen_header(c + + static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) + { +- union nand_boot_header *nh = (union nand_boot_header *)ptr; + struct brom_layout_header *bh; ++ struct nand_header_info info; + struct gfh_header *gfh; + const char *bootmedia; ++ int ret; + +- if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || +- strcmp(nh->id, NAND_BOOT_ID)) +- return -1; ++ ret = mtk_nand_header_info(ptr, &info); ++ if (ret < 0) ++ return ret; + +- bh = (struct brom_layout_header *)(ptr + le16_to_cpu(nh->pagesize)); ++ bh = (struct brom_layout_header *)(ptr + info.page_size); + + if (strcmp(bh->name, BRLYT_NAME)) + return -1; +@@ -586,34 +377,23 @@ static int mtk_image_verify_nand_header( + if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) + bootmedia = "Parallel NAND"; + else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) +- bootmedia = "Serial NAND"; ++ bootmedia = "Serial NAND (SNFI/AP)"; + else + return -1; + } + + if (print) { +- printf("Boot Media: %s\n", bootmedia); +- +- if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) { +- uint64_t capacity = +- (uint64_t)le16_to_cpu(nh->numblocks) * +- (uint64_t)le16_to_cpu(nh->pages_of_block) * +- (uint64_t)le16_to_cpu(nh->pagesize) * 8; +- printf("Capacity: %dGb\n", +- (uint32_t)(capacity >> 30)); +- } ++ printf("Boot Media: %s\n", bootmedia); + +- if (le16_to_cpu(nh->pagesize) >= 1024) +- printf("Page Size: %dKB\n", +- le16_to_cpu(nh->pagesize) >> 10); ++ if (info.page_size >= 1024) ++ printf("Page Size: %dKB\n", info.page_size >> 10); + else +- printf("Page Size: %dB\n", +- le16_to_cpu(nh->pagesize)); ++ printf("Page Size: %dB\n", info.page_size); + +- printf("Spare Size: %dB\n", le16_to_cpu(nh->oobsize)); ++ printf("Spare Size: %dB\n", info.spare_size); + } + +- gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); ++ gfh = (struct gfh_header *)(ptr + info.gfh_offset); + + return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); + } +@@ -713,7 +493,7 @@ static int mtk_image_verify_header(unsig + if (image_get_magic(hdr) == IH_MAGIC) + return mtk_image_verify_mt7621_header(ptr, 0); + +- if (!strcmp((char *)ptr, NAND_BOOT_NAME)) ++ if (is_mtk_nand_header(ptr)) + return mtk_image_verify_nand_header(ptr, 0); + else + return mtk_image_verify_gen_header(ptr, 0); +@@ -739,7 +519,7 @@ static void mtk_image_print_header(const + return; + } + +- if (!strcmp((char *)ptr, NAND_BOOT_NAME)) ++ if (is_mtk_nand_header(ptr)) + mtk_image_verify_nand_header(ptr, 1); + else + mtk_image_verify_gen_header(ptr, 1); +@@ -870,36 +650,33 @@ static void mtk_image_set_gen_header(voi + static void mtk_image_set_nand_header(void *ptr, off_t filesize, + uint32_t loadaddr) + { +- union nand_boot_header *nh = (union nand_boot_header *)ptr; + struct brom_layout_header *brlyt; + struct gfh_header *gfh; +- uint32_t payload_pages; +- int i; ++ uint32_t payload_pages, nand_page_size; + +- /* NAND device header, repeat 4 times */ +- for (i = 0; i < 4; i++) +- memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); ++ /* NAND header */ ++ nand_page_size = mtk_nand_header_put(hdr_nand, ptr); + +- /* BRLYT header */ +- payload_pages = (filesize + le16_to_cpu(hdr_nand->pagesize) - 1) / +- le16_to_cpu(hdr_nand->pagesize); +- brlyt = (struct brom_layout_header *) +- (ptr + le16_to_cpu(hdr_nand->pagesize)); +- put_brom_layout_header(brlyt, hdr_media); +- brlyt->header_size = cpu_to_le32(2); +- brlyt->total_size = cpu_to_le32(payload_pages); +- brlyt->header_size_2 = brlyt->header_size; +- brlyt->total_size_2 = brlyt->total_size; +- brlyt->unused = cpu_to_le32(1); ++ if (nand_page_size) { ++ /* BRLYT header */ ++ payload_pages = (filesize + nand_page_size - 1) / ++ nand_page_size; ++ brlyt = (struct brom_layout_header *)(ptr + nand_page_size); ++ put_brom_layout_header(brlyt, hdr_media); ++ brlyt->header_size = cpu_to_le32(2); ++ brlyt->total_size = cpu_to_le32(payload_pages); ++ brlyt->header_size_2 = brlyt->header_size; ++ brlyt->total_size_2 = brlyt->total_size; ++ brlyt->unused = cpu_to_le32(1); ++ } + + /* GFH header */ +- gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(hdr_nand->pagesize)); +- put_ghf_header(gfh, filesize, 2 * le16_to_cpu(hdr_nand->pagesize), +- loadaddr, GFH_FLASH_TYPE_NAND); ++ gfh = (struct gfh_header *)(ptr + hdr_nand_size); ++ put_ghf_header(gfh, filesize, hdr_nand_size, loadaddr, ++ GFH_FLASH_TYPE_NAND); + + /* Generate SHA256 hash */ +- put_hash((uint8_t *)gfh, +- filesize - 2 * le16_to_cpu(hdr_nand->pagesize) - SHA256_SUM_LEN); ++ put_hash((uint8_t *)gfh, filesize - hdr_nand_size - SHA256_SUM_LEN); + } + + static void mtk_image_set_mt7621_header(void *ptr, off_t filesize, +--- a/tools/mtk_image.h ++++ b/tools/mtk_image.h +@@ -26,31 +26,6 @@ union gen_boot_header { + #define SF_BOOT_NAME "SF_BOOT" + #define SDMMC_BOOT_NAME "SDMMC_BOOT" + +-/* Header for NAND */ +-union nand_boot_header { +- struct { +- char name[12]; +- char version[4]; +- char id[8]; +- uint16_t ioif; +- uint16_t pagesize; +- uint16_t addrcycles; +- uint16_t oobsize; +- uint16_t pages_of_block; +- uint16_t numblocks; +- uint16_t writesize_shift; +- uint16_t erasesize_shift; +- uint8_t dummy[60]; +- uint8_t ecc_parity[28]; +- }; +- +- uint8_t data[0x80]; +-}; +- +-#define NAND_BOOT_NAME "BOOTLOADER!" +-#define NAND_BOOT_VERSION "V006" +-#define NAND_BOOT_ID "NFIINFO" +- + /* BootROM layout header */ + struct brom_layout_header { + char name[8]; +--- /dev/null ++++ b/tools/mtk_nand_headers.c +@@ -0,0 +1,286 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * MediaTek BootROM NAND header definitions ++ * ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Weijie Gao ++ */ ++ ++#include ++#include ++#include "imagetool.h" ++#include "mtk_image.h" ++#include "mtk_nand_headers.h" ++ ++/* NAND header for SPI-NAND with 2KB page + 64B spare */ ++static const union nand_boot_header snand_hdr_2k_64_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, ++ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, ++ 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, ++ 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, ++ 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ ++static const union nand_boot_header snand_hdr_2k_128_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, ++ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, ++ 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, ++ 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, ++ 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for SPI-NAND with 4KB page + 256B spare */ ++static const union nand_boot_header snand_hdr_4k_256_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, ++ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, ++ 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, ++ 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, ++ 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ ++static const union nand_boot_header nand_hdr_1gb_2k_64_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, ++ 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, ++ 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, ++ 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, ++ 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ ++static const union nand_boot_header nand_hdr_2gb_2k_64_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, ++ 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, ++ 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, ++ 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, ++ 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ ++static const union nand_boot_header nand_hdr_4gb_2k_64_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, ++ 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, ++ 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, ++ 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, ++ 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ ++static const union nand_boot_header nand_hdr_2gb_2k_128_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, ++ 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, ++ 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, ++ 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, ++ 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ ++static const union nand_boot_header nand_hdr_4gb_2k_128_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, ++ 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, ++ 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, ++ 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, ++ 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 ++ } ++}; ++ ++static const struct nand_header_type { ++ const char *name; ++ const union nand_boot_header *data; ++} nand_headers[] = { ++ { ++ .name = "2k+64", ++ .data = &snand_hdr_2k_64_data ++ }, { ++ .name = "2k+120", ++ .data = &snand_hdr_2k_128_data ++ }, { ++ .name = "2k+128", ++ .data = &snand_hdr_2k_128_data ++ }, { ++ .name = "4k+256", ++ .data = &snand_hdr_4k_256_data ++ }, { ++ .name = "1g:2k+64", ++ .data = &nand_hdr_1gb_2k_64_data ++ }, { ++ .name = "2g:2k+64", ++ .data = &nand_hdr_2gb_2k_64_data ++ }, { ++ .name = "4g:2k+64", ++ .data = &nand_hdr_4gb_2k_64_data ++ }, { ++ .name = "2g:2k+128", ++ .data = &nand_hdr_2gb_2k_128_data ++ }, { ++ .name = "4g:2k+128", ++ .data = &nand_hdr_4gb_2k_128_data ++ } ++}; ++ ++const union nand_boot_header *mtk_nand_header_find(const char *name) ++{ ++ uint32_t i; ++ ++ for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { ++ if (!strcmp(nand_headers[i].name, name)) ++ return nand_headers[i].data; ++ } ++ ++ return NULL; ++} ++ ++uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand) ++{ ++ return 2 * le16_to_cpu(hdr_nand->pagesize); ++} ++ ++static int mtk_nand_header_ap_info(const void *ptr, ++ struct nand_header_info *info) ++{ ++ union nand_boot_header *nh = (union nand_boot_header *)ptr; ++ ++ if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || ++ strcmp(nh->id, NAND_BOOT_ID)) ++ return -1; ++ ++ info->page_size = le16_to_cpu(nh->pagesize); ++ info->spare_size = le16_to_cpu(nh->oobsize); ++ info->gfh_offset = 2 * info->page_size; ++ ++ return 0; ++} ++ ++int mtk_nand_header_info(const void *ptr, struct nand_header_info *info) ++{ ++ if (!strcmp((char *)ptr, NAND_BOOT_NAME)) ++ return mtk_nand_header_ap_info(ptr, info); ++ ++ return -1; ++} ++ ++bool is_mtk_nand_header(const void *ptr) ++{ ++ struct nand_header_info info; ++ ++ if (mtk_nand_header_info(ptr, &info) >= 0) ++ return true; ++ ++ return false; ++} ++ ++uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr) ++{ ++ union nand_boot_header *nh = (union nand_boot_header *)ptr; ++ int i; ++ ++ /* NAND device header, repeat 4 times */ ++ for (i = 0; i < 4; i++) ++ memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); ++ ++ return le16_to_cpu(hdr_nand->pagesize); ++} +--- /dev/null ++++ b/tools/mtk_nand_headers.h +@@ -0,0 +1,61 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * MediaTek BootROM NAND header definitions ++ * ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Weijie Gao ++ */ ++ ++#ifndef _MTK_NAND_HEADERS_H ++#define _MTK_NAND_HEADERS_H ++ ++#include ++#include ++ ++struct nand_header_info { ++ uint32_t page_size; ++ uint32_t spare_size; ++ uint32_t gfh_offset; ++}; ++ ++/* AP BROM Header for NAND */ ++union nand_boot_header { ++ struct { ++ char name[12]; ++ char version[4]; ++ char id[8]; ++ uint16_t ioif; /* I/O interface */ ++ uint16_t pagesize; /* NAND page size */ ++ uint16_t addrcycles; /* Address cycles */ ++ uint16_t oobsize; /* NAND page spare size */ ++ uint16_t pages_of_block; /* Pages of one block */ ++ uint16_t numblocks; /* Total blocks of NAND chip */ ++ uint16_t writesize_shift; ++ uint16_t erasesize_shift; ++ uint8_t dummy[60]; ++ uint8_t ecc_parity[28]; /* ECC parity of this header */ ++ }; ++ ++ uint8_t data[0x80]; ++}; ++ ++#define NAND_BOOT_NAME "BOOTLOADER!" ++#define NAND_BOOT_VERSION "V006" ++#define NAND_BOOT_ID "NFIINFO" ++ ++/* Find nand header data by name */ ++const union nand_boot_header *mtk_nand_header_find(const char *name); ++ ++/* Device header size using this nand header */ ++uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); ++ ++/* Get nand info from nand header (page size, spare size, ...) */ ++int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); ++ ++/* Whether given header data is valid */ ++bool is_mtk_nand_header(const void *ptr); ++ ++/* Generate Device header using give nand header */ ++uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr); ++ ++#endif /* _MTK_NAND_HEADERS_H */ diff --git a/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch b/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch new file mode 100644 index 0000000000..0ce095998f --- /dev/null +++ b/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch @@ -0,0 +1,702 @@ +From fbf296f9ed5daab70020686e9ba072efe663bbab Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 3 Aug 2022 11:14:36 +0800 +Subject: [PATCH 30/31] tools: mtk_image: add support for nand headers used by + newer chips + +This patch adds more nand headers in two new types: +1. HSM header, used for spi-nand thru SNFI interface +2. SPIM header, used for spi-nand thru spi-mem interface + +The original nand header is renamed to AP header. + +Signed-off-by: Weijie Gao +--- + tools/mtk_image.c | 23 ++- + tools/mtk_nand_headers.c | 422 +++++++++++++++++++++++++++++++++++++-- + tools/mtk_nand_headers.h | 110 +++++++++- + 3 files changed, 525 insertions(+), 30 deletions(-) + +--- a/tools/mtk_image.c ++++ b/tools/mtk_image.c +@@ -33,6 +33,9 @@ static const struct brom_img_type { + }, { + .name = "snand", + .type = BRLYT_TYPE_SNAND ++ }, { ++ .name = "spim-nand", ++ .type = BRLYT_TYPE_SNAND + } + }; + +@@ -54,7 +57,7 @@ static char lk_name[32] = "U-Boot"; + static uint32_t crc32tbl[256]; + + /* NAND header selected by user */ +-static const union nand_boot_header *hdr_nand; ++static const struct nand_header_type *hdr_nand; + static uint32_t hdr_nand_size; + + /* GFH header + 2 * 4KB pages of NAND */ +@@ -366,20 +369,26 @@ static int mtk_image_verify_nand_header( + if (ret < 0) + return ret; + +- bh = (struct brom_layout_header *)(ptr + info.page_size); ++ if (!ret) { ++ bh = (struct brom_layout_header *)(ptr + info.page_size); + +- if (strcmp(bh->name, BRLYT_NAME)) +- return -1; ++ if (strcmp(bh->name, BRLYT_NAME)) ++ return -1; ++ ++ if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) ++ return -1; + +- if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) { +- return -1; +- } else { + if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) + bootmedia = "Parallel NAND"; + else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) + bootmedia = "Serial NAND (SNFI/AP)"; + else + return -1; ++ } else { ++ if (info.snfi) ++ bootmedia = "Serial NAND (SNFI/HSM)"; ++ else ++ bootmedia = "Serial NAND (SPIM)"; + } + + if (print) { +--- a/tools/mtk_nand_headers.c ++++ b/tools/mtk_nand_headers.c +@@ -188,55 +188,346 @@ static const union nand_boot_header nand + } + }; + +-static const struct nand_header_type { ++/* HSM BROM NAND header for SPI NAND with 2KB page + 64B spare */ ++static const union hsm_nand_boot_header hsm_nand_hdr_2k_64_data = { ++ .data = { ++ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, ++ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, ++ 0xFF, 0x00, 0x00, 0x00, 0x21, 0xD2, 0xEE, 0xF6, ++ 0xAE, 0xDD, 0x5E, 0xC2, 0x82, 0x8E, 0x9A, 0x62, ++ 0x09, 0x8E, 0x80, 0xE2, 0x37, 0x0D, 0xC9, 0xFA, ++ 0xA9, 0xDD, 0xFC, 0x92, 0x34, 0x2A, 0xED, 0x51, ++ 0xA4, 0x1B, 0xF7, 0x63, 0xCC, 0x5A, 0xC7, 0xFB, ++ 0xED, 0x21, 0x02, 0x23, 0x51, 0x31 ++ } ++}; ++ ++/* HSM BROM NAND header for SPI NAND with 2KB page + 128B spare */ ++static const union hsm_nand_boot_header hsm_nand_hdr_2k_128_data = { ++ .data = { ++ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, ++ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, ++ 0xFF, 0x00, 0x00, 0x00, 0x71, 0x7f, 0x71, 0xAC, ++ 0x42, 0xD0, 0x5B, 0xD2, 0x12, 0x81, 0x15, 0x0A, ++ 0x0C, 0xD4, 0xF6, 0x32, 0x1E, 0x63, 0xE7, 0x81, ++ 0x8A, 0x7F, 0xDE, 0xF9, 0x4B, 0x91, 0xEC, 0xC2, ++ 0x70, 0x00, 0x7F, 0x57, 0xAF, 0xDC, 0xE4, 0x24, ++ 0x57, 0x09, 0xBC, 0xC5, 0x35, 0xDC ++ } ++}; ++ ++/* HSM BROM NAND header for SPI NAND with 4KB page + 256B spare */ ++static const union hsm_nand_boot_header hsm_nand_hdr_4k_256_data = { ++ .data = { ++ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, ++ 0x0C, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, ++ 0xFF, 0x00, 0x00, 0x00, 0x62, 0x04, 0xD6, 0x1F, ++ 0x2B, 0x57, 0x7A, 0x2D, 0xFE, 0xBB, 0x4A, 0x50, ++ 0xEC, 0xF8, 0x70, 0x1A, 0x44, 0x15, 0xF6, 0xA2, ++ 0x8E, 0xB0, 0xFD, 0xFA, 0xDC, 0xAA, 0x5A, 0x4E, ++ 0xCB, 0x8E, 0xC9, 0x72, 0x08, 0xDC, 0x20, 0xB9, ++ 0x98, 0xC8, 0x82, 0xD8, 0xBE, 0x44 ++ } ++}; ++ ++/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 64B spare */ ++static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_64_data = { ++ .data = { ++ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, ++ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, ++ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x5F, 0x4B, 0xB2, 0x5B, 0x8B, 0x1C, 0x35, 0xDA, ++ 0x83, 0xE6, 0x6C, 0xC3, 0xFB, 0x8C, 0x78, 0x23, ++ 0xD0, 0x89, 0x24, 0xD9, 0x6C, 0x35, 0x2C, 0x5D, ++ 0x8F, 0xBB, 0xFC, 0x10, 0xD0, 0xE2, 0x22, 0x7D, ++ 0xC8, 0x97, 0x9A, 0xEF, 0xC6, 0xB5, 0xA7, 0x4E, ++ 0x4E, 0x0E ++ } ++}; ++ ++/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 128B spare */ ++static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_128_data = { ++ .data = { ++ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, ++ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, ++ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xF8, 0x7E, 0xC1, 0x5D, 0x61, 0x54, 0xEA, 0x9F, ++ 0x5E, 0x66, 0x39, 0x66, 0x21, 0xFF, 0x8C, 0x3B, ++ 0xBE, 0xA7, 0x5A, 0x9E, 0xD7, 0xBD, 0x9E, 0x89, ++ 0xEE, 0x7E, 0x10, 0x31, 0x9A, 0x1D, 0x82, 0x49, ++ 0xA3, 0x4E, 0xD8, 0x47, 0xD7, 0x19, 0xF4, 0x2D, ++ 0x8E, 0x53 ++ } ++}; ++ ++/* HSM2.0 BROM NAND header for SPI NAND with 4KB page + 256B spare */ ++static const union hsm20_nand_boot_header hsm20_nand_hdr_4k_256_data = { ++ .data = { ++ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, ++ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, ++ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x79, 0x01, 0x1F, 0x86, 0x62, 0x6A, 0x43, 0xAE, ++ 0xE6, 0xF8, 0xDD, 0x5B, 0x29, 0xB7, 0xA2, 0x7F, ++ 0x29, 0x72, 0x54, 0x37, 0xBE, 0x50, 0xD4, 0x24, ++ 0xAB, 0x60, 0xF4, 0x44, 0x97, 0x3B, 0x65, 0x21, ++ 0x73, 0x24, 0x1F, 0x93, 0x0E, 0x9E, 0x96, 0x88, ++ 0x78, 0x6C ++ } ++}; ++ ++/* SPIM-NAND header for SPI NAND with 2KB page + 64B spare */ ++static const union spim_nand_boot_header spim_nand_hdr_2k_64_data = { ++ .data = { ++ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, ++ 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30, ++ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ } ++}; ++ ++/* SPIM-NAND header for SPI NAND with 2KB page + 128B spare */ ++static const union spim_nand_boot_header spim_nand_hdr_2k_128_data = { ++ .data = { ++ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, ++ 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30, ++ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ } ++}; ++ ++/* SPIM-NAND header for SPI NAND with 4KB page + 256B spare */ ++static const union spim_nand_boot_header spim_nand_hdr_4k_256_data = { ++ .data = { ++ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, ++ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, ++ 0x40, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x20, 0x30, ++ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ } ++}; ++ ++struct nand_header_type { + const char *name; +- const union nand_boot_header *data; ++ enum nand_boot_header_type type; ++ union { ++ const union nand_boot_header *ap; ++ const union hsm_nand_boot_header *hsm; ++ const union hsm20_nand_boot_header *hsm20; ++ const union spim_nand_boot_header *spim; ++ }; + } nand_headers[] = { + { + .name = "2k+64", +- .data = &snand_hdr_2k_64_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &snand_hdr_2k_64_data, + }, { + .name = "2k+120", +- .data = &snand_hdr_2k_128_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &snand_hdr_2k_128_data, + }, { + .name = "2k+128", +- .data = &snand_hdr_2k_128_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &snand_hdr_2k_128_data, + }, { + .name = "4k+256", +- .data = &snand_hdr_4k_256_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &snand_hdr_4k_256_data, + }, { + .name = "1g:2k+64", +- .data = &nand_hdr_1gb_2k_64_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &nand_hdr_1gb_2k_64_data, + }, { + .name = "2g:2k+64", +- .data = &nand_hdr_2gb_2k_64_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &nand_hdr_2gb_2k_64_data, + }, { + .name = "4g:2k+64", +- .data = &nand_hdr_4gb_2k_64_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &nand_hdr_4gb_2k_64_data, + }, { + .name = "2g:2k+128", +- .data = &nand_hdr_2gb_2k_128_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &nand_hdr_2gb_2k_128_data, + }, { + .name = "4g:2k+128", +- .data = &nand_hdr_4gb_2k_128_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &nand_hdr_4gb_2k_128_data, ++ }, { ++ .name = "hsm:2k+64", ++ .type = NAND_BOOT_HSM_HEADER, ++ .hsm = &hsm_nand_hdr_2k_64_data, ++ }, { ++ .name = "hsm:2k+128", ++ .type = NAND_BOOT_HSM_HEADER, ++ .hsm = &hsm_nand_hdr_2k_128_data, ++ }, { ++ .name = "hsm:4k+256", ++ .type = NAND_BOOT_HSM_HEADER, ++ .hsm = &hsm_nand_hdr_4k_256_data, ++ }, { ++ .name = "hsm20:2k+64", ++ .type = NAND_BOOT_HSM20_HEADER, ++ .hsm20 = &hsm20_nand_hdr_2k_64_data, ++ }, { ++ .name = "hsm20:2k+128", ++ .type = NAND_BOOT_HSM20_HEADER, ++ .hsm20 = &hsm20_nand_hdr_2k_128_data, ++ }, { ++ .name = "hsm20:4k+256", ++ .type = NAND_BOOT_HSM20_HEADER, ++ .hsm20 = &hsm20_nand_hdr_4k_256_data, ++ }, { ++ .name = "spim:2k+64", ++ .type = NAND_BOOT_SPIM_HEADER, ++ .spim = &spim_nand_hdr_2k_64_data, ++ }, { ++ .name = "spim:2k+128", ++ .type = NAND_BOOT_SPIM_HEADER, ++ .spim = &spim_nand_hdr_2k_128_data, ++ }, { ++ .name = "spim:4k+256", ++ .type = NAND_BOOT_SPIM_HEADER, ++ .spim = &spim_nand_hdr_4k_256_data, + } + }; + +-const union nand_boot_header *mtk_nand_header_find(const char *name) ++const struct nand_header_type *mtk_nand_header_find(const char *name) + { + uint32_t i; + + for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { + if (!strcmp(nand_headers[i].name, name)) +- return nand_headers[i].data; ++ return &nand_headers[i]; + } + + return NULL; + } + +-uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand) ++uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand) + { +- return 2 * le16_to_cpu(hdr_nand->pagesize); ++ switch (hdr_nand->type) { ++ case NAND_BOOT_HSM_HEADER: ++ return le32_to_cpu(hdr_nand->hsm->page_size); ++ ++ case NAND_BOOT_HSM20_HEADER: ++ return le32_to_cpu(hdr_nand->hsm20->page_size); ++ ++ case NAND_BOOT_SPIM_HEADER: ++ return le32_to_cpu(hdr_nand->spim->page_size); ++ ++ default: ++ return 2 * le16_to_cpu(hdr_nand->ap->pagesize); ++ } + } + + static int mtk_nand_header_ap_info(const void *ptr, +@@ -251,14 +542,45 @@ static int mtk_nand_header_ap_info(const + info->page_size = le16_to_cpu(nh->pagesize); + info->spare_size = le16_to_cpu(nh->oobsize); + info->gfh_offset = 2 * info->page_size; ++ info->snfi = true; + + return 0; + } + ++static int mtk_nand_header_hsm_info(const void *ptr, ++ struct nand_header_info *info) ++{ ++ union hsm_nand_boot_header *nh = (union hsm_nand_boot_header *)ptr; ++ ++ info->page_size = le16_to_cpu(nh->page_size); ++ info->spare_size = le16_to_cpu(nh->spare_size); ++ info->gfh_offset = info->page_size; ++ info->snfi = true; ++ ++ return 1; ++} ++ ++static int mtk_nand_header_spim_info(const void *ptr, ++ struct nand_header_info *info) ++{ ++ union spim_nand_boot_header *nh = (union spim_nand_boot_header *)ptr; ++ ++ info->page_size = le16_to_cpu(nh->page_size); ++ info->spare_size = le16_to_cpu(nh->spare_size); ++ info->gfh_offset = info->page_size; ++ info->snfi = false; ++ ++ return 1; ++} ++ + int mtk_nand_header_info(const void *ptr, struct nand_header_info *info) + { + if (!strcmp((char *)ptr, NAND_BOOT_NAME)) + return mtk_nand_header_ap_info(ptr, info); ++ else if (!strncmp((char *)ptr, HSM_NAND_BOOT_NAME, 8)) ++ return mtk_nand_header_hsm_info(ptr, info); ++ else if (!strncmp((char *)ptr, SPIM_NAND_BOOT_NAME, 8)) ++ return mtk_nand_header_spim_info(ptr, info); + + return -1; + } +@@ -273,14 +595,74 @@ bool is_mtk_nand_header(const void *ptr) + return false; + } + +-uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr) ++static uint16_t crc16(const uint8_t *p, uint32_t len) ++{ ++ uint16_t crc = 0x4f4e; ++ uint32_t i; ++ ++ while (len--) { ++ crc ^= *p++ << 8; ++ for (i = 0; i < 8; i++) ++ crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); ++ } ++ ++ return crc; ++} ++ ++static uint32_t mtk_nand_header_put_ap(const struct nand_header_type *hdr_nand, ++ void *ptr) + { +- union nand_boot_header *nh = (union nand_boot_header *)ptr; + int i; + + /* NAND device header, repeat 4 times */ +- for (i = 0; i < 4; i++) +- memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); ++ for (i = 0; i < 4; i++) { ++ memcpy(ptr, hdr_nand->ap, sizeof(*hdr_nand->ap)); ++ ptr += sizeof(*hdr_nand->ap); ++ } ++ ++ return le16_to_cpu(hdr_nand->ap->pagesize); ++} + +- return le16_to_cpu(hdr_nand->pagesize); ++static uint32_t mtk_nand_header_put_hsm(const struct nand_header_type *hdr_nand, ++ void *ptr) ++{ ++ memcpy(ptr, hdr_nand->hsm, sizeof(*hdr_nand->hsm)); ++ return 0; ++} ++ ++static uint32_t mtk_nand_header_put_hsm20(const struct nand_header_type *hdr_nand, ++ void *ptr) ++{ ++ memcpy(ptr, hdr_nand->hsm20, sizeof(*hdr_nand->hsm20)); ++ return 0; ++} ++ ++static uint32_t mtk_nand_header_put_spim(const struct nand_header_type *hdr_nand, ++ void *ptr) ++{ ++ uint16_t crc; ++ ++ memcpy(ptr, hdr_nand->spim, sizeof(*hdr_nand->spim)); ++ ++ crc = crc16(ptr, 0x4e); ++ memcpy(ptr + 0x4e, &crc, sizeof(uint16_t)); ++ ++ return 0; ++} ++ ++uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, void *ptr) ++{ ++ switch (hdr_nand->type) { ++ case NAND_BOOT_HSM_HEADER: ++ return mtk_nand_header_put_hsm(hdr_nand, ptr); ++ ++ case NAND_BOOT_HSM20_HEADER: ++ return mtk_nand_header_put_hsm20(hdr_nand, ptr); ++ ++ case NAND_BOOT_SPIM_HEADER: ++ return mtk_nand_header_put_spim(hdr_nand, ptr); ++ ++ default: ++ return mtk_nand_header_put_ap(hdr_nand, ptr); ++ } + } +--- a/tools/mtk_nand_headers.h ++++ b/tools/mtk_nand_headers.h +@@ -16,6 +16,7 @@ struct nand_header_info { + uint32_t page_size; + uint32_t spare_size; + uint32_t gfh_offset; ++ bool snfi; + }; + + /* AP BROM Header for NAND */ +@@ -39,15 +40,117 @@ union nand_boot_header { + uint8_t data[0x80]; + }; + ++/* HSM BROM Header for NAND */ ++union hsm_nand_boot_header { ++ struct { ++ char id[8]; ++ uint32_t version; /* Header version */ ++ uint32_t config; /* Header config */ ++ uint32_t sector_size; /* ECC step size */ ++ uint32_t fdm_size; /* User OOB size of a step */ ++ uint32_t fdm_ecc_size; /* ECC parity size of a step */ ++ uint32_t lbs; ++ uint32_t page_size; /* NAND page size */ ++ uint32_t spare_size; /* NAND page spare size */ ++ uint32_t page_per_block; /* Pages of one block */ ++ uint32_t blocks; /* Total blocks of NAND chip */ ++ uint32_t plane_sel_position; /* Plane bit position */ ++ uint32_t pll; /* Value of pll reg */ ++ uint32_t acccon; /* Value of access timing reg */ ++ uint32_t strobe_sel; /* Value of DQS selection reg*/ ++ uint32_t acccon1; /* Value of access timing reg */ ++ uint32_t dqs_mux; /* Value of DQS mux reg */ ++ uint32_t dqs_ctrl; /* Value of DQS control reg */ ++ uint32_t delay_ctrl; /* Value of delay ctrl reg */ ++ uint32_t latch_lat; /* Value of latch latency reg */ ++ uint32_t sample_delay; /* Value of sample delay reg */ ++ uint32_t driving; /* Value of driving reg */ ++ uint32_t bl_start; /* Bootloader start addr */ ++ uint32_t bl_end; /* Bootloader end addr */ ++ uint8_t ecc_parity[42]; /* ECC parity of this header */ ++ }; ++ ++ uint8_t data[0x8E]; ++}; ++ ++/* HSM2.0 BROM Header for NAND */ ++union hsm20_nand_boot_header { ++ struct { ++ char id[8]; ++ uint32_t version; /* Header version */ ++ uint32_t config; /* Header config */ ++ uint32_t sector_size; /* ECC step size */ ++ uint32_t fdm_size; /* User OOB size of a step */ ++ uint32_t fdm_ecc_size; /* ECC parity size of a step */ ++ uint32_t lbs; ++ uint32_t page_size; /* NAND page size */ ++ uint32_t spare_size; /* NAND page spare size */ ++ uint32_t page_per_block; /* Pages of one block */ ++ uint32_t blocks; /* Total blocks of NAND chip */ ++ uint32_t plane_sel_position; /* Plane bit position */ ++ uint32_t pll; /* Value of pll reg */ ++ uint32_t acccon; /* Value of access timing reg */ ++ uint32_t strobe_sel; /* Value of DQS selection reg*/ ++ uint32_t acccon1; /* Value of access timing reg */ ++ uint32_t dqs_mux; /* Value of DQS mux reg */ ++ uint32_t dqs_ctrl; /* Value of DQS control reg */ ++ uint32_t delay_ctrl; /* Value of delay ctrl reg */ ++ uint32_t latch_lat; /* Value of latch latency reg */ ++ uint32_t sample_delay; /* Value of sample delay reg */ ++ uint32_t driving; /* Value of driving reg */ ++ uint32_t reserved; ++ uint32_t bl0_start; /* Bootloader start addr */ ++ uint32_t bl0_end; /* Bootloader end addr */ ++ uint32_t bl0_type; /* Bootloader type */ ++ uint8_t bl_reserve[84]; ++ uint8_t ecc_parity[42]; /* ECC parity of this header */ ++ }; ++ ++ uint8_t data[0xEA]; ++}; ++ ++/* SPIM BROM Header for SPI-NAND */ ++union spim_nand_boot_header { ++ struct { ++ char id[8]; ++ uint32_t version; /* Header version */ ++ uint32_t config; /* Header config */ ++ uint32_t page_size; /* NAND page size */ ++ uint32_t spare_size; /* NAND page spare size */ ++ uint16_t page_per_block; /* Pages of one block */ ++ uint16_t plane_sel_position; /* Plane bit position */ ++ uint16_t reserve_reg; ++ uint16_t reserve_val; ++ uint16_t ecc_error; /* ECC error reg addr */ ++ uint16_t ecc_mask; /* ECC error bit mask */ ++ uint32_t bl_start; /* Bootloader start addr */ ++ uint32_t bl_end; /* Bootloader end addr */ ++ uint8_t ecc_parity[32]; /* ECC parity of this header */ ++ uint32_t integrity_crc; /* CRC of this header */ ++ }; ++ ++ uint8_t data[0x50]; ++}; ++ ++enum nand_boot_header_type { ++ NAND_BOOT_AP_HEADER, ++ NAND_BOOT_HSM_HEADER, ++ NAND_BOOT_HSM20_HEADER, ++ NAND_BOOT_SPIM_HEADER ++}; ++ + #define NAND_BOOT_NAME "BOOTLOADER!" + #define NAND_BOOT_VERSION "V006" + #define NAND_BOOT_ID "NFIINFO" + ++#define HSM_NAND_BOOT_NAME "NANDCFG!" ++#define SPIM_NAND_BOOT_NAME "SPINAND!" ++ + /* Find nand header data by name */ +-const union nand_boot_header *mtk_nand_header_find(const char *name); ++const struct nand_header_type *mtk_nand_header_find(const char *name); + + /* Device header size using this nand header */ +-uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); ++uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand); + + /* Get nand info from nand header (page size, spare size, ...) */ + int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); +@@ -56,6 +159,7 @@ int mtk_nand_header_info(const void *ptr + bool is_mtk_nand_header(const void *ptr); + + /* Generate Device header using give nand header */ +-uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr); ++uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, ++ void *ptr); + + #endif /* _MTK_NAND_HEADERS_H */ From 71cb448210e74e3d137c70fcb226a1d39f8e43d3 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 23 Oct 2022 14:26:20 +0200 Subject: [PATCH 52/80] gdb: add patch adding support for readline 8.2 Add "001-Add-support-for-readline-8.2.patch" adding support for readline 8.2. Signed-off-by: Nick Hainke --- .../001-Add-support-for-readline-8.2.patch | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 package/devel/gdb/patches/001-Add-support-for-readline-8.2.patch diff --git a/package/devel/gdb/patches/001-Add-support-for-readline-8.2.patch b/package/devel/gdb/patches/001-Add-support-for-readline-8.2.patch new file mode 100644 index 0000000000..eb93c7f290 --- /dev/null +++ b/package/devel/gdb/patches/001-Add-support-for-readline-8.2.patch @@ -0,0 +1,31 @@ +From 1add37b567a7dee39d99f37b37802034c3fce9c4 Mon Sep 17 00:00:00 2001 +From: Andreas Schwab +Date: Sun, 20 Mar 2022 14:01:54 +0100 +Subject: [PATCH] Add support for readline 8.2 + +In readline 8.2 the type of rl_completer_word_break_characters changed to +include const. +--- + gdb/completer.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/gdb/completer.c ++++ b/gdb/completer.c +@@ -36,7 +36,7 @@ + calling a hook instead so we eliminate the CLI dependency. */ + #include "gdbcmd.h" + +-/* Needed for rl_completer_word_break_characters() and for ++/* Needed for rl_completer_word_break_characters and for + rl_filename_completion_function. */ + #include "readline/readline.h" + +@@ -2011,7 +2011,7 @@ gdb_completion_word_break_characters_thr + rl_basic_quote_characters = NULL; + } + +- return rl_completer_word_break_characters; ++ return (char *) rl_completer_word_break_characters; + } + + char * From 96aa052c406d460de8c4c1c3cf0eb9a900ae09c5 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 21 Oct 2022 14:48:58 +0200 Subject: [PATCH 53/80] readline: update to 8.2 Release Announcement: https://lists.gnu.org/archive/html/info-gnu/2022-09/msg00013.html Signed-off-by: Nick Hainke --- package/libs/readline/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/libs/readline/Makefile b/package/libs/readline/Makefile index a6ceec1fce..015a1ae2da 100644 --- a/package/libs/readline/Makefile +++ b/package/libs/readline/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=readline -PKG_VERSION:=8.1.2 +PKG_VERSION:=8.2 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@GNU/readline -PKG_HASH:=7589a2381a8419e68654a47623ce7dfcb756815c8fee726b98f90bf668af7bc6 +PKG_HASH:=3feb7171f16a84ee82ca18a36d7b9be109a52c04f492a053331d7d1095007c35 PKG_LICENSE:=GPL-3.0-or-later PKG_LICENSE_FILES:=COPYING From 3cc8011171186d906c547bc6f0c1f8e350edc7cf Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Mon, 3 Oct 2022 14:45:21 +0200 Subject: [PATCH 54/80] realtek: resurrect timer driver Now that we provide a clock driver for the Reltek SOCs the CPU frequency might change on demand. This has direct visible effects during operation - the CEVT 4K timer is no longer a stable clocksource - after CPU frequencies changes time calculation works wrong - sched_clock falls back to kernel default interval (100 Hz) - timestamps in dmesg have only 2 digits left [ 0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps ... [ 0.060000] pid_max: default: 32768 minimum: 301 [ 0.070000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.070000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.080000] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build [ 0.090000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ... Looking around where we can start the CEVT timer for RTL930X is a good basis. Initially it was developed as a clocksource driver for the broken timer in that specific SOC series. Afterwards it was shifted around to the CEVT location, got SMP enablement and lost its clocksource feature. So we at least have something to copy from. As the timers on these devices are well understood the implementation follows this way: - leave the RTL930X implementation as is - provide a new driver for RTL83XX devices only - swap RTL930X driver at a later time Like the clock driver this patch contains a self contained module that is SOC independet and already provides full support for the RTL838X, RTL839X and RTL930X devices. Some of the new (or reestablished) features are: - simplified initialization routines - SMP setup with CPU hotplug framework - derived from LXB clock speed - supplied clocksource - dedicated register functions for better readability - documentation about some caveats Signed-off-by: Markus Stockhausen [remove unused header includes, remove old CONFIG_MIPS dependency, add REALTEK_ prefix to driver symbol] Signed-off-by: Sander Vanheule --- .../drivers/clocksource/timer-rtl-otto.c | 298 ++++++++++++++++++ .../302-clocksource-add-otto-driver.patch | 40 +++ 2 files changed, 338 insertions(+) create mode 100644 target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl-otto.c create mode 100644 target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch diff --git a/target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl-otto.c b/target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl-otto.c new file mode 100644 index 0000000000..12eed78653 --- /dev/null +++ b/target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl-otto.c @@ -0,0 +1,298 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include "timer-of.h" + +#define RTTM_DATA 0x0 +#define RTTM_CNT 0x4 +#define RTTM_CTRL 0x8 +#define RTTM_INT 0xc + +#define RTTM_CTRL_ENABLE BIT(28) +#define RTTM_INT_PENDING BIT(16) +#define RTTM_INT_ENABLE BIT(20) + +/* + * The Otto platform provides multiple 28 bit timers/counters with the following + * operating logic. If enabled the timer counts up. Per timer one can set a + * maximum counter value as an end marker. If end marker is reached the timer + * fires an interrupt. If the timer "overflows" by reaching the end marker or + * by adding 1 to 0x0fffffff the counter is reset to 0. When this happens and + * the timer is in operating mode COUNTER it stops. In mode TIMER it will + * continue to count up. + */ + +#define RTTM_CTRL_COUNTER 0 +#define RTTM_CTRL_TIMER BIT(24) + +#define RTTM_BIT_COUNT 28 +#define RTTM_MIN_DELTA 8 +#define RTTM_MAX_DELTA CLOCKSOURCE_MASK(28) + +/* + * Timers are derived from the LXB clock frequency. Usually this is a fixed + * multiple of the 25 MHz oscillator. The 930X SOC is an exception from that. + * Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its + * base. The only meaningful frequencies we can achieve from that are 175.000 + * MHz and 153.125 MHz. The greatest common divisor of all explained possible + * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency. + */ + +#define RTTM_TICKS_PER_SEC 3125000 + +struct rttm_cs { + struct timer_of to; + struct clocksource cs; +}; + +/* + * Simple internal register functions + */ + +static inline void rttm_set_counter(void __iomem *base, unsigned int counter) +{ + iowrite32(counter, base + RTTM_CNT); +} + +static inline unsigned int rttm_get_counter(void __iomem *base) +{ + return ioread32(base + RTTM_CNT); +} + +static inline void rttm_set_period(void __iomem *base, unsigned int period) +{ + iowrite32(period, base + RTTM_DATA); +} + +static inline void rttm_disable_timer(void __iomem *base) +{ + iowrite32(0, base + RTTM_CTRL); +} + +static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor) +{ + iowrite32(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL); +} + +static inline void rttm_ack_irq(void __iomem *base) +{ + iowrite32(ioread32(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT); +} + +static inline void rttm_enable_irq(void __iomem *base) +{ + iowrite32(RTTM_INT_ENABLE, base + RTTM_INT); +} + +static inline void rttm_disable_irq(void __iomem *base) +{ + iowrite32(0, base + RTTM_INT); +} + +/* + * Aggregated control functions for kernel clock framework + */ + +#define RTTM_DEBUG(base) \ + pr_debug("------------- %s %d %08x\n", __func__, \ + smp_processor_id(), (u32)base) + +static irqreturn_t rttm_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *clkevt = dev_id; + struct timer_of *to = to_timer_of(clkevt); + + rttm_ack_irq(to->of_base.base); + RTTM_DEBUG(to->of_base.base); + clkevt->event_handler(clkevt); + + return IRQ_HANDLED; +} + +static void rttm_stop_timer(void __iomem *base) +{ + rttm_disable_timer(base); + rttm_ack_irq(base); +} + +static void rttm_start_timer(struct timer_of *to, u32 mode) +{ + rttm_set_counter(to->of_base.base, 0); + rttm_enable_timer(to->of_base.base, mode, to->of_clk.rate / RTTM_TICKS_PER_SEC); +} + +static int rttm_next_event(unsigned long delta, struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + RTTM_DEBUG(to->of_base.base); + rttm_stop_timer(to->of_base.base); + rttm_set_period(to->of_base.base, delta); + rttm_start_timer(to, RTTM_CTRL_COUNTER); + + return 0; +} + +static int rttm_state_oneshot(struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + RTTM_DEBUG(to->of_base.base); + rttm_stop_timer(to->of_base.base); + rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ); + rttm_start_timer(to, RTTM_CTRL_COUNTER); + + return 0; +} + +static int rttm_state_periodic(struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + RTTM_DEBUG(to->of_base.base); + rttm_stop_timer(to->of_base.base); + rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ); + rttm_start_timer(to, RTTM_CTRL_TIMER); + + return 0; +} + +static int rttm_state_shutdown(struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + RTTM_DEBUG(to->of_base.base); + rttm_stop_timer(to->of_base.base); + + return 0; +} + +static void rttm_setup_timer(void __iomem *base) +{ + RTTM_DEBUG(base); + rttm_stop_timer(base); + rttm_set_period(base, 0); +} + +static u64 rttm_read_clocksource(struct clocksource *cs) +{ + struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs); + + return (u64)rttm_get_counter(rcs->to.of_base.base); +} + +/* + * Module initialization part. + */ + +static DEFINE_PER_CPU(struct timer_of, rttm_to) = { + .flags = TIMER_OF_BASE | TIMER_OF_CLOCK | TIMER_OF_IRQ, + .of_irq = { + .flags = IRQF_PERCPU | IRQF_TIMER, + .handler = rttm_timer_interrupt, + }, + .clkevt = { + .rating = 400, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_state_periodic = rttm_state_periodic, + .set_state_shutdown = rttm_state_shutdown, + .set_state_oneshot = rttm_state_oneshot, + .set_next_event = rttm_next_event + }, +}; + +static int rttm_enable_clocksource(struct clocksource *cs) +{ + struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs); + + rttm_disable_irq(rcs->to.of_base.base); + rttm_setup_timer(rcs->to.of_base.base); + rttm_enable_timer(rcs->to.of_base.base, RTTM_CTRL_TIMER, + rcs->to.of_clk.rate / RTTM_TICKS_PER_SEC); + + return 0; +} + +struct rttm_cs rttm_cs = { + .to = { + .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, + }, + .cs = { + .name = "realtek_otto_timer", + .rating = 400, + .mask = CLOCKSOURCE_MASK(RTTM_BIT_COUNT), + .read = rttm_read_clocksource, + .enable = rttm_enable_clocksource + } +}; + +static u64 notrace rttm_read_clock(void) +{ + return (u64)rttm_get_counter(rttm_cs.to.of_base.base); +} + +static int rttm_cpu_starting(unsigned int cpu) +{ + struct timer_of *to = per_cpu_ptr(&rttm_to, cpu); + + RTTM_DEBUG(to->of_base.base); + to->clkevt.cpumask = cpumask_of(cpu); + irq_set_affinity(to->of_irq.irq, to->clkevt.cpumask); + clockevents_config_and_register(&to->clkevt, RTTM_TICKS_PER_SEC, + RTTM_MIN_DELTA, RTTM_MAX_DELTA); + rttm_enable_irq(to->of_base.base); + + return 0; +} + +static int __init rttm_probe(struct device_node *np) +{ + int cpu, cpu_rollback; + struct timer_of *to; + int clkidx = num_possible_cpus(); +/* + * Use the first n timers as per CPU clock event generators + */ + for_each_possible_cpu(cpu) { + to = per_cpu_ptr(&rttm_to, cpu); + to->of_irq.index = to->of_base.index = cpu; + if (timer_of_init(np, to)) { + pr_err("%s: setup of timer %d failed\n", __func__, cpu); + goto rollback; + } + rttm_setup_timer(to->of_base.base); + } +/* + * Activate the n'th+1 timer as a stable CPU clocksource. + */ + to = &rttm_cs.to; + to->of_base.index = clkidx; + timer_of_init(np, to); + if (rttm_cs.to.of_base.base && rttm_cs.to.of_clk.rate) { + clocksource_register_hz(&rttm_cs.cs, RTTM_TICKS_PER_SEC); + sched_clock_register(rttm_read_clock, RTTM_BIT_COUNT, RTTM_TICKS_PER_SEC); + } else + pr_err("%s: setup of timer %d as clocksoure failed", __func__, clkidx); + + return cpuhp_setup_state(CPUHP_AP_REALTEK_TIMER_STARTING, + "timer/realtek:online", + rttm_cpu_starting, NULL); +rollback: + pr_err("%s: timer registration failed\n", __func__); + for_each_possible_cpu(cpu_rollback) { + if (cpu_rollback == cpu) + break; + to = per_cpu_ptr(&rttm_to, cpu_rollback); + timer_of_cleanup(to); + } + + return -EINVAL; +} + +TIMER_OF_DECLARE(otto_timer, "realtek,otto-timer", rttm_probe); diff --git a/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch b/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch new file mode 100644 index 0000000000..8b17ddaef0 --- /dev/null +++ b/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch @@ -0,0 +1,40 @@ +--- a/drivers/clocksource/Kconfig ++++ b/drivers/clocksource/Kconfig +@@ -127,6 +127,17 @@ config RDA_TIMER + help + Enables the support for the RDA Micro timer driver. + ++config REALTEK_OTTO_TIMER ++ bool "Clocksource/timer for the Realtek Otto platform" ++ select COMMON_CLK ++ select TIMER_OF ++ help ++ This driver adds support for the timers found in the Realtek RTL83xx ++ and RTL93xx SoCs series. This includes chips such as RTL8380, RTL8381 ++ and RTL832, as well as chips from the RTL839x series, such as RTL8390 ++ RT8391, RTL8392, RTL8393 and RTL8396 and chips of the RTL930x series ++ such as RTL9301, RTL9302 or RTL9303. ++ + config SUN4I_TIMER + bool "Sun4i timer driver" if COMPILE_TEST + depends on HAS_IOMEM +--- a/drivers/clocksource/Makefile ++++ b/drivers/clocksource/Makefile +@@ -63,6 +63,7 @@ obj-$(CONFIG_MILBEAUT_TIMER) += timer-mi + obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o + obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o + obj-$(CONFIG_RDA_TIMER) += timer-rda.o ++obj-$(CONFIG_REALTEK_OTTO_TIMER) += timer-rtl-otto.o + + obj-$(CONFIG_ARC_TIMERS) += arc_timer.o + obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o +--- a/include/linux/cpuhotplug.h ++++ b/include/linux/cpuhotplug.h +@@ -133,6 +133,7 @@ enum cpuhp_state { + CPUHP_AP_MARCO_TIMER_STARTING, + CPUHP_AP_MIPS_GIC_TIMER_STARTING, + CPUHP_AP_ARC_TIMER_STARTING, ++ CPUHP_AP_REALTEK_TIMER_STARTING, + CPUHP_AP_RISCV_TIMER_STARTING, + CPUHP_AP_CLINT_TIMER_STARTING, + CPUHP_AP_CSKY_TIMER_STARTING, From 5c677b2298ed435277782d224be1a10b3d3e9044 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Mon, 3 Oct 2022 14:47:18 +0200 Subject: [PATCH 55/80] realtek: timer driver: documentation Provide some helpful information about the devicetree configuration of our new driver Signed-off-by: Markus Stockhausen [correct compatible order in examples] Signed-off-by: Sander Vanheule --- .../bindings/realtek,otto-timer.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 target/linux/realtek/files-5.10/Documentation/devicetree/bindings/realtek,otto-timer.yaml diff --git a/target/linux/realtek/files-5.10/Documentation/devicetree/bindings/realtek,otto-timer.yaml b/target/linux/realtek/files-5.10/Documentation/devicetree/bindings/realtek,otto-timer.yaml new file mode 100644 index 0000000000..b508362a72 --- /dev/null +++ b/target/linux/realtek/files-5.10/Documentation/devicetree/bindings/realtek,otto-timer.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/realtek,rtl8300-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek Timer Device Tree Bindings + +maintainers: + - Markus Stockhausen + +description: | + The Realtek SOCs of the RTL83XX and RTL93XX series have at least 5 known + timers with corresponding interrupt lines . Their speed is derived from the + Lexra Bus (LXB) by dividers. Each timer has a block of 4 control registers in + the address range 0xb800xxxx with following start offsets. + + RTL83XX: 0x3100, 0x3110, 0x3120, 0x3130, 0x3140 + RTL93XX: 0x3200, 0x3210, 0x3220, 0x3230, 0x3240 + +properties: + compatible: + items: + - enum: + - realtek,rtl8380-timer + - realtek,rtl8390-timer + - realtek,rtl9300-timer + - const: realtek,otto-timer + + reg: + minItems: 5 + maxItems: 5 + description: + List of timer register addresses. + + interrupts: + minItems: 5 + maxItems: 5 + description: + List of timer interrupts. + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer0: timer@3100 { + compatible = "realtek,rtl8380-timer", "realtek,otto-timer"; + reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>, + <0x3130 0x10>, <0x3140 0x10>; + + interrupt-parent = <&intc>; + interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>; + clocks = <&ccu CLK_LXB>; + }; + - | + timer0: timer@3100 { + compatible = "realtek,rtl8390-timer", "realtek,otto-timer"; + reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>, + <0x3130 0x10>, <0x3140 0x10>; + + interrupt-parent = <&intc>; + interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>; + clocks = <&ccu CLK_LXB>; + }; + - | + timer0: timer@3200 { + compatible = "realtek,rtl9300-timer", "realtek,otto-timer"; + reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, + <0x3230 0x10>, <0x3240 0x10>; + + interrupt-parent = <&intc>; + interrupts = <7 4>, <8 4>, <9 4>, <10 4>, <11 4>; + clocks = <&ccu CLK_LXB>; + }; + +... From ec675fb7446f25e1dbbdbf72d525ba7f771b0cb1 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Mon, 3 Oct 2022 14:49:35 +0200 Subject: [PATCH 56/80] realtek: timer driver: activate for RTL838X devices Use the new timer driver for the RTL838X devices. Remove the no longer needed modules. Signed-off-by: Markus Stockhausen [correct timer compatible order, update selected symbols] Signed-off-by: Sander Vanheule --- target/linux/realtek/dts-5.10/rtl838x.dtsi | 10 ++++++++++ .../patches-5.10/300-mips-add-rtl838x-platform.patch | 4 +--- target/linux/realtek/rtl838x/config-5.10 | 6 +++--- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target/linux/realtek/dts-5.10/rtl838x.dtsi b/target/linux/realtek/dts-5.10/rtl838x.dtsi index 256efb1c05..64e13e1ff3 100644 --- a/target/linux/realtek/dts-5.10/rtl838x.dtsi +++ b/target/linux/realtek/dts-5.10/rtl838x.dtsi @@ -152,6 +152,16 @@ #size-cells = <0>; }; + timer0: timer@3100 { + compatible = "realtek,rtl8380-timer", "realtek,otto-timer"; + reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>, + <0x3130 0x10>, <0x3140 0x10>; + + interrupt-parent = <&intc>; + interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>; + clocks = <&ccu CLK_LXB>; + }; + uart0: uart@2000 { compatible = "ns16550a"; reg = <0x2000 0x100>; diff --git a/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch b/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch index 591b157d40..3e1ace9660 100644 --- a/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch +++ b/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch @@ -25,7 +25,7 @@ Submitted-by: Birger Koblitz platform-$(CONFIG_SGI_IP28) += sgi-ip22/ --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -1037,8 +1037,62 @@ config NLM_XLP_BOARD +@@ -1037,8 +1037,60 @@ config NLM_XLP_BOARD This board is based on Netlogic XLP Processor. Say Y here if you have a XLP based board. @@ -54,8 +54,6 @@ Submitted-by: Birger Koblitz + bool "Realtek RTL838X based platforms" + depends on RTL83XX + select CPU_SUPPORTS_CPUFREQ -+ select CSRC_R4K -+ select CEVT_R4K + select MIPS_EXTERNAL_TIMER + +config RTL839X diff --git a/target/linux/realtek/rtl838x/config-5.10 b/target/linux/realtek/rtl838x/config-5.10 index c45f10dee0..d69345e301 100644 --- a/target/linux/realtek/rtl838x/config-5.10 +++ b/target/linux/realtek/rtl838x/config-5.10 @@ -7,8 +7,8 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BMIPS_CPUFREQ is not set -CONFIG_CEVT_R4K=y -CONFIG_CEVT_RTL9300=y +# CONFIG_CEVT_R4K is not set +# CONFIG_CEVT_RTL9300 is not set CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y @@ -51,7 +51,6 @@ CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_DMA_NONCOHERENT=y CONFIG_DTC=y @@ -187,6 +186,7 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_POWER_RESET_SYSCON=y CONFIG_RATIONAL=y +CONFIG_REALTEK_OTTO_TIMER=y CONFIG_REALTEK_OTTO_WDT=y CONFIG_REALTEK_PHY=y CONFIG_REALTEK_SOC_PHY=y From beb5b079430d1fdb273532dfe270cc1173318506 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Mon, 3 Oct 2022 14:50:17 +0200 Subject: [PATCH 57/80] realtek: timer driver: activate for RTL839X devices Use the new timer driver for the RTL839X devices and remove the no longer needed modules. Signed-off-by: Markus Stockhausen [correct timer compatible order, update selected symbols] Signed-off-by: Sander Vanheule --- target/linux/realtek/dts-5.10/rtl839x.dtsi | 10 ++++++++++ .../patches-5.10/300-mips-add-rtl838x-platform.patch | 4 +--- target/linux/realtek/rtl839x/config-5.10 | 5 +---- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/target/linux/realtek/dts-5.10/rtl839x.dtsi b/target/linux/realtek/dts-5.10/rtl839x.dtsi index 78e2454b7e..91d6e17a9e 100644 --- a/target/linux/realtek/dts-5.10/rtl839x.dtsi +++ b/target/linux/realtek/dts-5.10/rtl839x.dtsi @@ -177,6 +177,16 @@ #size-cells = <0>; }; + timer0: timer@3100 { + compatible = "realtek,rtl8390-timer", "realtek,otto-timer"; + reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>, + <0x3130 0x10>, <0x3140 0x10>; + + interrupt-parent = <&intc>; + interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>; + clocks = <&ccu CLK_LXB>; + }; + uart0: uart@2000 { compatible = "ns16550a"; reg = <0x2000 0x100>; diff --git a/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch b/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch index 3e1ace9660..eaf03c74f9 100644 --- a/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch +++ b/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch @@ -25,7 +25,7 @@ Submitted-by: Birger Koblitz platform-$(CONFIG_SGI_IP28) += sgi-ip22/ --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -1037,8 +1037,60 @@ config NLM_XLP_BOARD +@@ -1037,8 +1037,58 @@ config NLM_XLP_BOARD This board is based on Netlogic XLP Processor. Say Y here if you have a XLP based board. @@ -60,8 +60,6 @@ Submitted-by: Birger Koblitz + bool "Realtek RTL839X based platforms" + depends on RTL83XX + select CPU_SUPPORTS_CPUFREQ -+ select CSRC_R4K -+ select CEVT_R4K + select MIPS_EXTERNAL_TIMER + select SYS_SUPPORTS_MULTITHREADING + diff --git a/target/linux/realtek/rtl839x/config-5.10 b/target/linux/realtek/rtl839x/config-5.10 index c685a3f24b..57eded97fc 100644 --- a/target/linux/realtek/rtl839x/config-5.10 +++ b/target/linux/realtek/rtl839x/config-5.10 @@ -7,10 +7,7 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BMIPS_CPUFREQ is not set -CONFIG_CEVT_R4K=y -CONFIG_CEVT_RTL9300=y CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_BOSTON=y @@ -53,7 +50,6 @@ CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_DMA_NONCOHERENT=y CONFIG_DTC=y @@ -185,6 +181,7 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_POWER_RESET_SYSCON=y CONFIG_RATIONAL=y +CONFIG_REALTEK_OTTO_TIMER=y CONFIG_REALTEK_OTTO_WDT=y CONFIG_REALTEK_PHY=y CONFIG_REALTEK_SOC_PHY=y From b295c7140bc39aa58993171fe1ef4345b3e9838d Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Mon, 3 Oct 2022 15:15:06 +0200 Subject: [PATCH 58/80] realtek: disable otto timer for RTL93xx targets The new timer is not yet ready for all targets. Avoid interactive questions during build Signed-off-by: Markus Stockhausen [rename symbol to CONFIG_REALTEK_OTTO_TIMER] Signed-off-by: Sander Vanheule --- target/linux/realtek/rtl930x/config-5.10 | 1 + target/linux/realtek/rtl931x/config-5.10 | 1 + 2 files changed, 2 insertions(+) diff --git a/target/linux/realtek/rtl930x/config-5.10 b/target/linux/realtek/rtl930x/config-5.10 index 9984533c06..3b2b327f08 100644 --- a/target/linux/realtek/rtl930x/config-5.10 +++ b/target/linux/realtek/rtl930x/config-5.10 @@ -171,6 +171,7 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_POWER_RESET_SYSCON=y CONFIG_RATIONAL=y +# CONFIG_REALTEK_OTTO_TIMER is not set CONFIG_REALTEK_OTTO_WDT=y CONFIG_REALTEK_PHY=y CONFIG_REALTEK_SOC_PHY=y diff --git a/target/linux/realtek/rtl931x/config-5.10 b/target/linux/realtek/rtl931x/config-5.10 index cc0fd34b38..567421c8d4 100644 --- a/target/linux/realtek/rtl931x/config-5.10 +++ b/target/linux/realtek/rtl931x/config-5.10 @@ -169,6 +169,7 @@ CONFIG_PINCTRL=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_RATIONAL=y +# CONFIG_REALTEK_OTTO_TIMER is not set # CONFIG_REALTEK_PHY is not set CONFIG_REALTEK_SOC_PHY=y CONFIG_REGMAP=y From 4657a5301eb5512b335de696d6a719c280826d46 Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Fri, 14 Oct 2022 23:06:14 +0200 Subject: [PATCH 59/80] realtek: avoid busy waiting for RTL839x PHY read/write Switch to a polling implementation similar to the one for RTL838x, to allow other kernel tasks to run while waiting. Signed-off-by: Jan Hoffmann --- .../drivers/net/dsa/rtl83xx/rtl839x.c | 45 ++++++++++++++----- 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c index 199ba347da..29912257e8 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c @@ -630,9 +630,23 @@ int rtl8390_sds_power(int mac, int val) return 0; } +static int rtl839x_smi_wait_op(int timeout) +{ + int ret = 0; + u32 val; + + ret = readx_poll_timeout(sw_r32, RTL839X_PHYREG_ACCESS_CTRL, + val, !(val & 0x1), 20, timeout); + if (ret) + pr_err("%s: timeout\n", __func__); + + return ret; +} + int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val) { u32 v; + int err = 0; if (port > 63 || page > 4095 || reg > 31) return -ENOTSUPP; @@ -652,13 +666,15 @@ int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val) v |= 1; sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - do { - } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1); + err = rtl839x_smi_wait_op(100000); + if (err) + goto errout; *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff; +errout: mutex_unlock(&smi_lock); - return 0; + return err; } int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val) @@ -689,12 +705,14 @@ int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val) v |= BIT(3) | 1; /* Write operation and execute */ sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - do { - } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1); + err = rtl839x_smi_wait_op(100000); + if (err) + goto errout; if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2) err = -EIO; +errout: mutex_unlock(&smi_lock); return err; } @@ -722,15 +740,16 @@ int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) v = BIT(2) | BIT(0); // MMD-access | EXEC sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - do { - v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL); - } while (v & BIT(0)); + err = rtl839x_smi_wait_op(100000); + if (err) + goto errout; + // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly *val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff); pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err); +errout: mutex_unlock(&smi_lock); - return err; } @@ -760,11 +779,13 @@ int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) v = BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - do { - v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL); - } while (v & BIT(0)); + err = rtl839x_smi_wait_op(100000); + if (err) + goto errout; pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err); + +errout: mutex_unlock(&smi_lock); return err; } From ae9487c535bc7bb084a00149c4c8bc8571cb36a7 Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Fri, 14 Oct 2022 23:06:16 +0200 Subject: [PATCH 60/80] realtek: add debugfs node for L2 table This allows to view all unicast and multicast entries that are currently in the L2 hash table and the CAM. Signed-off-by: Jan Hoffmann --- .../drivers/net/dsa/rtl83xx/debugfs.c | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c index 21f00096e5..6dd064c95b 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c @@ -270,6 +270,109 @@ static const struct file_operations drop_counter_fops = { .read = drop_counter_read, }; +static void l2_table_print_entry(struct seq_file *m, struct rtl838x_switch_priv *priv, + struct rtl838x_l2_entry *e) +{ + u64 portmask; + int i; + + if (e->type == L2_UNICAST) { + seq_puts(m, "L2_UNICAST\n"); + + seq_printf(m, " mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n", + e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5], + e->vid, e->rvid); + + seq_printf(m, " port %d age %d", e->port, e->age); + if (e->is_static) + seq_puts(m, " static"); + if (e->block_da) + seq_puts(m, " block_da"); + if (e->block_sa) + seq_puts(m, " block_sa"); + if (e->suspended) + seq_puts(m, " suspended"); + if (e->next_hop) + seq_printf(m, " next_hop route_id %u", e->nh_route_id); + seq_puts(m, "\n"); + + } else { + if (e->type == L2_MULTICAST) { + seq_puts(m, "L2_MULTICAST\n"); + + seq_printf(m, " mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n", + e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5], + e->vid, e->rvid); + } + + if (e->type == IP4_MULTICAST || e->type == IP6_MULTICAST) { + seq_puts(m, (e->type == IP4_MULTICAST) ? + "IP4_MULTICAST\n" : "IP6_MULTICAST\n"); + + seq_printf(m, " gip %08x sip %08x vid %u rvid %u\n", + e->mc_gip, e->mc_sip, e->vid, e->rvid); + } + + portmask = priv->r->read_mcast_pmask(e->mc_portmask_index); + seq_printf(m, " index %u ports", e->mc_portmask_index); + for (i = 0; i < 64; i++) { + if (portmask & BIT_ULL(i)) + seq_printf(m, " %d", i); + } + seq_puts(m, "\n"); + } + + seq_puts(m, "\n"); +} + +static int l2_table_show(struct seq_file *m, void *v) +{ + struct rtl838x_switch_priv *priv = m->private; + struct rtl838x_l2_entry e; + int i, bucket, index; + + mutex_lock(&priv->reg_mutex); + + for (i = 0; i < priv->fib_entries; i++) { + bucket = i >> 2; + index = i & 0x3; + priv->r->read_l2_entry_using_hash(bucket, index, &e); + + if (!e.valid) + continue; + + seq_printf(m, "Hash table bucket %d index %d ", bucket, index); + l2_table_print_entry(m, priv, &e); + } + + for (i = 0; i < 64; i++) { + priv->r->read_cam(i, &e); + + if (!e.valid) + continue; + + seq_printf(m, "CAM index %d ", i); + l2_table_print_entry(m, priv, &e); + } + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int l2_table_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, l2_table_show, inode->i_private); +} + +static const struct file_operations l2_table_fops = { + .owner = THIS_MODULE, + .open = l2_table_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + static ssize_t age_out_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos) { @@ -608,6 +711,8 @@ void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv) debugfs_create_file("drop_counters", 0400, rtl838x_dir, priv, &drop_counter_fops); + debugfs_create_file("l2_table", 0400, rtl838x_dir, priv, &l2_table_fops); + return; err: rtl838x_dbgfs_cleanup(priv); @@ -625,4 +730,6 @@ void rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv) priv->dbgfs_dir = dbg_dir; debugfs_create_file("drop_counters", 0400, dbg_dir, priv, &drop_counter_fops); + + debugfs_create_file("l2_table", 0400, dbg_dir, priv, &l2_table_fops); } From 19b86658b7f9d6080d7059896a57b8daa67ae941 Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Fri, 14 Oct 2022 23:06:17 +0200 Subject: [PATCH 61/80] realtek: reduce excessive logging for FDB operations Currently several messages at KERN_INFO level are printed for every FDB del/dump operation. This can cause a significant slowdown for example while using "bridge fdb", and may even trigger a watchdog. Remove most of these log messages, as the new L2 table debugfs node should be a good replacement. Change the remaining messages to KERN_DEBUG level. Signed-off-by: Jan Hoffmann --- .../files-5.10/drivers/net/dsa/rtl83xx/dsa.c | 55 +------------------ .../drivers/net/dsa/rtl83xx/rtl930x.c | 16 ------ 2 files changed, 3 insertions(+), 68 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c index 3ff1a96ed6..10e6103f0d 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c @@ -1535,28 +1535,6 @@ static int rtl83xx_vlan_del(struct dsa_switch *ds, int port, return 0; } -static void dump_l2_entry(struct rtl838x_l2_entry *e) -{ - pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n", - e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5], - e->vid, e->rvid, e->port, e->valid); - - if (e->type != L2_MULTICAST) { - pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n", - e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da); - pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n", - e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk); - } - if (e->type == L2_MULTICAST) - pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index); - if (e->is_ip_mc || e->is_ipv6_mc) - pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n", - e->mc_portmask_index, e->mc_gip, e->mc_sip); - pr_info(" stack_dev: %d\n", e->stack_dev); - if (e->next_hop) - pr_info(" nh_route_id: %d\n", e->nh_route_id); -} - static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac) { e->is_ip_mc = e->is_ipv6_mc = false; @@ -1685,15 +1663,14 @@ static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port, int err = 0, idx; u64 seed = priv->r->l2_hash_seed(mac, vid); - pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid); + pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid); mutex_lock(&priv->reg_mutex); idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e); if (idx >= 0) { - pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3); + pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3); e.valid = false; - dump_l2_entry(&e); priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); goto out; } @@ -1718,8 +1695,6 @@ static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port, struct rtl838x_l2_entry e; struct rtl838x_switch_priv *priv = ds->priv; int i; - u32 fid, pkey; - u64 mac; mutex_lock(&priv->reg_mutex); @@ -1729,30 +1704,8 @@ static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port, if (!e.valid) continue; - if (e.port == port || e.port == RTL930X_PORT_IGNORE) { - u64 seed; - u32 key; - - fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff); - mac = ether_addr_to_u64(&e.mac[0]); - pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid)); - fid = (pkey & 0x3ff) | (fid & ~0x3ff); - pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n", - i, i >> 2, i & 0x3, mac, fid, e.rvid); - dump_l2_entry(&e); - seed = priv->r->l2_hash_seed(mac, e.rvid); - key = priv->r->l2_hash_key(priv, seed); - pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key); + if (e.port == port || e.port == RTL930X_PORT_IGNORE) cb(e.mac, e.vid, e.is_static, data); - } - if (e.type == L2_MULTICAST) { - u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index); - - if (portmask & BIT_ULL(port)) { - dump_l2_entry(&e); - pr_info(" PM: %016llx\n", portmask); - } - } } for (i = 0; i < 64; i++) { @@ -1876,7 +1829,6 @@ int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port, portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port); if (!portmask) { e.valid = false; - // dump_l2_entry(&e); priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); } goto out; @@ -1889,7 +1841,6 @@ int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port, portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port); if (!portmask) { e.valid = false; - // dump_l2_entry(&e); priv->r->write_cam(idx, &e); } goto out; diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c index cd93e4bc8e..e89d75d4b9 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c @@ -579,22 +579,6 @@ static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e) rtl_table_release(q); } -static void dump_l2_entry(struct rtl838x_l2_entry *e) -{ - pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n", - e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5], - e->vid, e->rvid, e->port, e->valid); - pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n", - e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da); - pr_info(" block_sa: %d, suspended: %d, next_hop: %d, age: %d, is_trunk: %d, trunk: %d\n", - e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk); - if (e->is_ip_mc || e->is_ipv6_mc) - pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n", - e->mc_portmask_index, e->mc_gip, e->mc_sip); - pr_info(" stac_dev: %d, nh_route_id: %d, port: %d, dev_id\n", - e->stack_dev, e->nh_route_id, e->port); -} - static u64 rtl930x_read_mcast_pmask(int idx) { u32 portmask; From 039e5be4af2497bd40414eedb6f83a1c75d06cca Mon Sep 17 00:00:00 2001 From: Sander Vanheule Date: Fri, 9 Sep 2022 19:35:23 +0200 Subject: [PATCH 62/80] realtek: remove RTL839x path in RTL838x multicast The multicast setup function rtl838x_eth_set_multicast_list() checks if the current SoC is a RTL839x family device. However, the function is only included in the RTL838x ops table, so this path should never be taken, making this dead code. rtl839x_eth_set_multicast_list() is already present in the RTL839x ops table, so it should be safe to remove this branch. While touching the code, also re-sort the functions to match sorting elsewhere, with rtl838x coming before rtl839x. Signed-off-by: Sander Vanheule --- .../drivers/net/ethernet/rtl838x_eth.c | 33 ++++++++----------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c index d497b4cc8c..7a6057b445 100644 --- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c @@ -1030,6 +1030,20 @@ static int rtl838x_eth_stop(struct net_device *ndev) return 0; } +static void rtl838x_eth_set_multicast_list(struct net_device *ndev) +{ + if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { + sw_w32(0x0, RTL838X_RMA_CTRL_0); + sw_w32(0x0, RTL838X_RMA_CTRL_1); + } + if (ndev->flags & IFF_ALLMULTI) + sw_w32(0x1fffff, RTL838X_RMA_CTRL_0); + if (ndev->flags & IFF_PROMISC) { + sw_w32(0x1fffff, RTL838X_RMA_CTRL_0); + sw_w32(0x7fff, RTL838X_RMA_CTRL_1); + } +} + static void rtl839x_eth_set_multicast_list(struct net_device *ndev) { if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { @@ -1051,25 +1065,6 @@ static void rtl839x_eth_set_multicast_list(struct net_device *ndev) } } -static void rtl838x_eth_set_multicast_list(struct net_device *ndev) -{ - struct rtl838x_eth_priv *priv = netdev_priv(ndev); - - if (priv->family_id == RTL8390_FAMILY_ID) - return rtl839x_eth_set_multicast_list(ndev); - - if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { - sw_w32(0x0, RTL838X_RMA_CTRL_0); - sw_w32(0x0, RTL838X_RMA_CTRL_1); - } - if (ndev->flags & IFF_ALLMULTI) - sw_w32(0x1fffff, RTL838X_RMA_CTRL_0); - if (ndev->flags & IFF_PROMISC) { - sw_w32(0x1fffff, RTL838X_RMA_CTRL_0); - sw_w32(0x7fff, RTL838X_RMA_CTRL_1); - } -} - static void rtl930x_eth_set_multicast_list(struct net_device *ndev) { if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { From 9f6cbc78cd5da260d3fba83aae95f32e05e5f6a7 Mon Sep 17 00:00:00 2001 From: Sander Vanheule Date: Fri, 9 Sep 2022 21:25:17 +0200 Subject: [PATCH 63/80] realtek: consistently flood RMA frames The switches support different actions for incoming ethernet multicast frames with Reserved Multicast Addresses (01-80-C2-00-00-{01-2F}). The current code will set the 2-bit action field to FLOOD (0x3) for most classes, but the highest bit is always unset for the relevant control registers. This means the DROP (0x1) action being used for these classes; whatever class the MSB happens to be in. For RTL838x, this results in {20,23-2F} frames being dropped, instead of flooding all ports. On other switch generations, {0F,1F,2F} frames are dropped. This is inconsistent, and appears to be a mistake. Remove this inconsistency by flooding all multicast frames with RMA addresses. Signed-off-by: Sander Vanheule --- .../drivers/net/ethernet/rtl838x_eth.c | 70 +++++++++++-------- 1 file changed, 40 insertions(+), 30 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c index 7a6057b445..f5424bbfa3 100644 --- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c @@ -1032,20 +1032,30 @@ static int rtl838x_eth_stop(struct net_device *ndev) static void rtl838x_eth_set_multicast_list(struct net_device *ndev) { + /* + * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + * CTRL_0_FULL = GENMASK(21, 0) = 0x3FFFFF + */ if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { sw_w32(0x0, RTL838X_RMA_CTRL_0); sw_w32(0x0, RTL838X_RMA_CTRL_1); } if (ndev->flags & IFF_ALLMULTI) - sw_w32(0x1fffff, RTL838X_RMA_CTRL_0); + sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0); if (ndev->flags & IFF_PROMISC) { - sw_w32(0x1fffff, RTL838X_RMA_CTRL_0); + sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0); sw_w32(0x7fff, RTL838X_RMA_CTRL_1); } } static void rtl839x_eth_set_multicast_list(struct net_device *ndev) { + /* + * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC + * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00 + * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) + */ if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { sw_w32(0x0, RTL839X_RMA_CTRL_0); sw_w32(0x0, RTL839X_RMA_CTRL_1); @@ -1053,54 +1063,54 @@ static void rtl839x_eth_set_multicast_list(struct net_device *ndev) sw_w32(0x0, RTL839X_RMA_CTRL_3); } if (ndev->flags & IFF_ALLMULTI) { - sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0); - sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1); - sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2); + sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0); + sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1); + sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2); } if (ndev->flags & IFF_PROMISC) { - sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0); - sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1); - sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2); + sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0); + sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1); + sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2); sw_w32(0x3ff, RTL839X_RMA_CTRL_3); } } static void rtl930x_eth_set_multicast_list(struct net_device *ndev) { - if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { + /* + * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC + * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00 + * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) + */ + if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) { + sw_w32(GENMASK(31, 2), RTL930X_RMA_CTRL_0); + sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_1); + sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_2); + } else { sw_w32(0x0, RTL930X_RMA_CTRL_0); sw_w32(0x0, RTL930X_RMA_CTRL_1); sw_w32(0x0, RTL930X_RMA_CTRL_2); } - if (ndev->flags & IFF_ALLMULTI) { - sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0); - sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1); - sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2); - } - if (ndev->flags & IFF_PROMISC) { - sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0); - sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1); - sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2); - } } static void rtl931x_eth_set_multicast_list(struct net_device *ndev) { - if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { + /* + * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC + * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00. + * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) + */ + if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) { + sw_w32(GENMASK(31, 2), RTL931X_RMA_CTRL_0); + sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_1); + sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_2); + } else { sw_w32(0x0, RTL931X_RMA_CTRL_0); sw_w32(0x0, RTL931X_RMA_CTRL_1); sw_w32(0x0, RTL931X_RMA_CTRL_2); } - if (ndev->flags & IFF_ALLMULTI) { - sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0); - sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1); - sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2); - } - if (ndev->flags & IFF_PROMISC) { - sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0); - sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1); - sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2); - } } static void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue) From 58b65525f3165792a998fdb24fda11aa4097a7be Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 15 Oct 2022 11:31:42 +0200 Subject: [PATCH 64/80] mac80211: Update to version 5.15.74-1 This updates mac80211 to version 5.15.74-1 which is based on kernel 5.15.74. The removed patches were applied upstream. Signed-off-by: Hauke Mehrtens --- package/kernel/mac80211/Makefile | 8 +- ...ringified-name-of-command-in-error-l.patch | 2 +- ...-the-fwd_skb-dev-for-mesh-forwarding.patch | 2 +- ...211_hwsim-make-6-GHz-channels-usable.patch | 8 +- ...d-support-for-.ndo_fill_forward_path.patch | 2 +- ...11-MBSSID-beacon-handling-in-AP-mode.patch | 2 +- ...airtime-fairness-back-to-deficit-rou.patch | 12 +- ...er-PHY-AQL-limit-to-improve-fairness.patch | 2 +- ...x-decap-offload-for-stations-on-AP_V.patch | 4 +- ...-not-drop-packets-smaller-than-the-L.patch | 2 +- ...80211-mesh-clean-up-rx_bcn_presp-API.patch | 110 -- ...ove-CRC-into-struct-ieee802_11_elems.patch | 82 -- ...11-mlme-find-auth-challenge-directly.patch | 80 -- ...ays-allocate-struct-ieee802_11_elems.patch | 1143 ----------------- ...ix-memory-leaks-with-element-parsing.patch | 115 -- ...x-u8-overflow-in-cfg80211_update_not.patch | 41 - ...-mac80211-reject-bad-MBSSID-elements.patch | 47 - ...11-fix-MBSSID-parsing-use-after-free.patch | 94 -- ...sure-length-byte-is-present-before-a.patch | 41 - ...fi-cfg80211-fix-BSS-refcounting-bugs.patch | 87 -- ...oid-nontransmitted-BSS-list-corrupti.patch | 48 - ...sim-avoid-mac80211-warning-on-bad-ra.patch | 31 - ...x-crash-in-beacon-protection-for-P2P.patch | 52 - ...update-hidden-BSSes-to-avoid-WARN_ON.patch | 85 -- ...emory-leak-where-sta_info-is-not-fre.patch | 77 -- ...n-t-finalize-CSA-in-IBSS-mode-if-sta.patch | 47 - ...ac80211-Fix-UAF-in-ieee80211_scan_rx.patch | 55 - .../500-mac80211_configure_antenna_gain.patch | 2 +- .../patches/100-aggregation-definitions.patch | 13 + 29 files changed, 36 insertions(+), 2258 deletions(-) delete mode 100644 package/kernel/mac80211/patches/subsys/346-mac80211-mesh-clean-up-rx_bcn_presp-API.patch delete mode 100644 package/kernel/mac80211/patches/subsys/347-mac80211-move-CRC-into-struct-ieee802_11_elems.patch delete mode 100644 package/kernel/mac80211/patches/subsys/348-mac80211-mlme-find-auth-challenge-directly.patch delete mode 100644 package/kernel/mac80211/patches/subsys/349-mac80211-always-allocate-struct-ieee802_11_elems.patch delete mode 100644 package/kernel/mac80211/patches/subsys/350-mac80211-fix-memory-leaks-with-element-parsing.patch delete mode 100644 package/kernel/mac80211/patches/subsys/351-wifi-cfg80211-fix-u8-overflow-in-cfg80211_update_not.patch delete mode 100644 package/kernel/mac80211/patches/subsys/352-wifi-cfg80211-mac80211-reject-bad-MBSSID-elements.patch delete mode 100644 package/kernel/mac80211/patches/subsys/353-wifi-mac80211-fix-MBSSID-parsing-use-after-free.patch delete mode 100644 package/kernel/mac80211/patches/subsys/354-wifi-cfg80211-ensure-length-byte-is-present-before-a.patch delete mode 100644 package/kernel/mac80211/patches/subsys/355-wifi-cfg80211-fix-BSS-refcounting-bugs.patch delete mode 100644 package/kernel/mac80211/patches/subsys/356-wifi-cfg80211-avoid-nontransmitted-BSS-list-corrupti.patch delete mode 100644 package/kernel/mac80211/patches/subsys/357-wifi-mac80211_hwsim-avoid-mac80211-warning-on-bad-ra.patch delete mode 100644 package/kernel/mac80211/patches/subsys/358-wifi-mac80211-fix-crash-in-beacon-protection-for-P2P.patch delete mode 100644 package/kernel/mac80211/patches/subsys/359-wifi-cfg80211-update-hidden-BSSes-to-avoid-WARN_ON.patch delete mode 100644 package/kernel/mac80211/patches/subsys/360-mac80211-fix-a-memory-leak-where-sta_info-is-not-fre.patch delete mode 100644 package/kernel/mac80211/patches/subsys/361-wifi-mac80211-Don-t-finalize-CSA-in-IBSS-mode-if-sta.patch delete mode 100644 package/kernel/mac80211/patches/subsys/362-wifi-mac80211-Fix-UAF-in-ieee80211_scan_rx.patch create mode 100644 package/kernel/mt76/patches/100-aggregation-definitions.patch diff --git a/package/kernel/mac80211/Makefile b/package/kernel/mac80211/Makefile index 44428ca89f..6a3c126e6d 100644 --- a/package/kernel/mac80211/Makefile +++ b/package/kernel/mac80211/Makefile @@ -10,10 +10,10 @@ include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=mac80211 -PKG_VERSION:=5.15.58-1 -PKG_RELEASE:=2 -PKG_SOURCE_URL:=@KERNEL/linux/kernel/projects/backports/stable/v5.15.58/ -PKG_HASH:=a3c2a2b7bbaf8943c65fd72f4e7d7ad5e205aeae28b26c835f9d8afa0f9810bf +PKG_VERSION:=5.15.74-1 +PKG_RELEASE:=1 +PKG_SOURCE_URL:=@KERNEL/linux/kernel/projects/backports/stable/v5.15.74/ +PKG_HASH:=98098d0cab24cc76a04db738dc746a0c8d38d180398805481224f141cca06423 PKG_SOURCE:=backports-$(PKG_VERSION).tar.xz PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/backports-$(PKG_VERSION) diff --git a/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch b/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch index 8fa3924e60..396e66ac22 100644 --- a/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch +++ b/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch @@ -152,7 +152,7 @@ Signed-off-by: Pali Rohár --- a/drivers/net/wireless/marvell/mwifiex/main.h +++ b/drivers/net/wireless/marvell/mwifiex/main.h -@@ -1106,6 +1106,8 @@ void mwifiex_cancel_all_pending_cmd(stru +@@ -1108,6 +1108,8 @@ void mwifiex_cancel_all_pending_cmd(stru void mwifiex_cancel_pending_scan_cmd(struct mwifiex_adapter *adapter); void mwifiex_cancel_scan(struct mwifiex_adapter *adapter); diff --git a/package/kernel/mac80211/patches/subsys/303-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch b/package/kernel/mac80211/patches/subsys/303-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch index 1ceb2be25c..159aad564b 100644 --- a/package/kernel/mac80211/patches/subsys/303-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch +++ b/package/kernel/mac80211/patches/subsys/303-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch @@ -52,7 +52,7 @@ Signed-off-by: Xing Song --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c -@@ -2948,6 +2948,7 @@ ieee80211_rx_h_mesh_fwding(struct ieee80 +@@ -2950,6 +2950,7 @@ ieee80211_rx_h_mesh_fwding(struct ieee80 if (!fwd_skb) goto out; diff --git a/package/kernel/mac80211/patches/subsys/307-mac80211_hwsim-make-6-GHz-channels-usable.patch b/package/kernel/mac80211/patches/subsys/307-mac80211_hwsim-make-6-GHz-channels-usable.patch index fba0912e80..80c86e3d92 100644 --- a/package/kernel/mac80211/patches/subsys/307-mac80211_hwsim-make-6-GHz-channels-usable.patch +++ b/package/kernel/mac80211/patches/subsys/307-mac80211_hwsim-make-6-GHz-channels-usable.patch @@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/wireless/mac80211_hwsim.c +++ b/drivers/net/wireless/mac80211_hwsim.c -@@ -3004,15 +3004,19 @@ static void mac80211_hwsim_he_capab(stru +@@ -3003,15 +3003,19 @@ static void mac80211_hwsim_he_capab(stru { u16 n_iftype_data; @@ -34,7 +34,7 @@ Signed-off-by: Felix Fietkau return; } -@@ -3302,6 +3306,12 @@ static int mac80211_hwsim_new_radio(stru +@@ -3301,6 +3305,12 @@ static int mac80211_hwsim_new_radio(stru sband->vht_cap.vht_mcs.tx_mcs_map = sband->vht_cap.vht_mcs.rx_mcs_map; break; @@ -47,7 +47,7 @@ Signed-off-by: Felix Fietkau case NL80211_BAND_S1GHZ: memcpy(&sband->s1g_cap, &hwsim_s1g_cap, sizeof(sband->s1g_cap)); -@@ -3312,6 +3322,13 @@ static int mac80211_hwsim_new_radio(stru +@@ -3311,6 +3321,13 @@ static int mac80211_hwsim_new_radio(stru continue; } @@ -61,7 +61,7 @@ Signed-off-by: Felix Fietkau sband->ht_cap.ht_supported = true; sband->ht_cap.cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_GRN_FLD | -@@ -3325,10 +3342,6 @@ static int mac80211_hwsim_new_radio(stru +@@ -3324,10 +3341,6 @@ static int mac80211_hwsim_new_radio(stru sband->ht_cap.mcs.rx_mask[0] = 0xff; sband->ht_cap.mcs.rx_mask[1] = 0xff; sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; diff --git a/package/kernel/mac80211/patches/subsys/308-mac80211-add-support-for-.ndo_fill_forward_path.patch b/package/kernel/mac80211/patches/subsys/308-mac80211-add-support-for-.ndo_fill_forward_path.patch index 4b9d874cfe..a9a6182ab2 100644 --- a/package/kernel/mac80211/patches/subsys/308-mac80211-add-support-for-.ndo_fill_forward_path.patch +++ b/package/kernel/mac80211/patches/subsys/308-mac80211-add-support-for-.ndo_fill_forward_path.patch @@ -69,7 +69,7 @@ Signed-off-by: Johannes Berg #endif /* __MAC80211_DRIVER_OPS */ --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h -@@ -1490,7 +1490,7 @@ struct ieee80211_local { +@@ -1489,7 +1489,7 @@ struct ieee80211_local { }; static inline struct ieee80211_sub_if_data * diff --git a/package/kernel/mac80211/patches/subsys/324-mac80211-MBSSID-beacon-handling-in-AP-mode.patch b/package/kernel/mac80211/patches/subsys/324-mac80211-MBSSID-beacon-handling-in-AP-mode.patch index fdbcce9450..e2b05719db 100644 --- a/package/kernel/mac80211/patches/subsys/324-mac80211-MBSSID-beacon-handling-in-AP-mode.patch +++ b/package/kernel/mac80211/patches/subsys/324-mac80211-MBSSID-beacon-handling-in-AP-mode.patch @@ -246,7 +246,7 @@ Signed-off-by: Johannes Berg struct rcu_head rcu_head; }; -@@ -1083,6 +1084,20 @@ ieee80211_vif_get_shift(struct ieee80211 +@@ -1082,6 +1083,20 @@ ieee80211_vif_get_shift(struct ieee80211 return shift; } diff --git a/package/kernel/mac80211/patches/subsys/330-mac80211-switch-airtime-fairness-back-to-deficit-rou.patch b/package/kernel/mac80211/patches/subsys/330-mac80211-switch-airtime-fairness-back-to-deficit-rou.patch index 0ca53860a5..e59036f5a2 100644 --- a/package/kernel/mac80211/patches/subsys/330-mac80211-switch-airtime-fairness-back-to-deficit-rou.patch +++ b/package/kernel/mac80211/patches/subsys/330-mac80211-switch-airtime-fairness-back-to-deficit-rou.patch @@ -327,7 +327,7 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h -@@ -863,16 +863,20 @@ enum txq_info_flags { +@@ -862,16 +862,20 @@ enum txq_info_flags { * @def_flow: used as a fallback flow when a packet destined to @tin hashes to * a fq_flow which is already owned by a different tin * @def_cvars: codel vars for @def_flow @@ -350,7 +350,7 @@ Signed-off-by: Felix Fietkau unsigned long flags; /* keep last! */ -@@ -949,8 +953,6 @@ struct ieee80211_sub_if_data { +@@ -948,8 +952,6 @@ struct ieee80211_sub_if_data { struct ieee80211_tx_queue_params tx_conf[IEEE80211_NUM_ACS]; struct mac80211_qos_map __rcu *qos_map; @@ -359,7 +359,7 @@ Signed-off-by: Felix Fietkau struct work_struct csa_finalize_work; bool csa_block_tx; /* write-protected by sdata_lock and local->mtx */ struct cfg80211_chan_def csa_chandef; -@@ -1185,44 +1187,6 @@ enum mac80211_scan_state { +@@ -1184,44 +1186,6 @@ enum mac80211_scan_state { SCAN_ABORT, }; @@ -404,7 +404,7 @@ Signed-off-by: Felix Fietkau DECLARE_STATIC_KEY_FALSE(aql_disable); struct ieee80211_local { -@@ -1236,8 +1200,13 @@ struct ieee80211_local { +@@ -1235,8 +1199,13 @@ struct ieee80211_local { struct codel_params cparams; /* protects active_txqs and txqi->schedule_order */ @@ -419,7 +419,7 @@ Signed-off-by: Felix Fietkau u32 aql_threshold; atomic_t aql_total_pending_airtime; -@@ -1654,125 +1623,6 @@ static inline bool txq_has_queue(struct +@@ -1660,125 +1629,6 @@ static inline bool txq_has_queue(struct return !(skb_queue_empty(&txqi->frags) && !txqi->tin.backlog_packets); } @@ -545,7 +545,7 @@ Signed-off-by: Felix Fietkau static inline int ieee80211_bssid_match(const u8 *raddr, const u8 *addr) { return ether_addr_equal(raddr, addr) || -@@ -2018,14 +1868,6 @@ int ieee80211_tx_control_port(struct wip +@@ -2024,14 +1874,6 @@ int ieee80211_tx_control_port(struct wip u64 *cookie); int ieee80211_probe_mesh_link(struct wiphy *wiphy, struct net_device *dev, const u8 *buf, size_t len); diff --git a/package/kernel/mac80211/patches/subsys/334-mac80211-add-a-per-PHY-AQL-limit-to-improve-fairness.patch b/package/kernel/mac80211/patches/subsys/334-mac80211-add-a-per-PHY-AQL-limit-to-improve-fairness.patch index 42e1671ed6..fb6fd6eac6 100644 --- a/package/kernel/mac80211/patches/subsys/334-mac80211-add-a-per-PHY-AQL-limit-to-improve-fairness.patch +++ b/package/kernel/mac80211/patches/subsys/334-mac80211-add-a-per-PHY-AQL-limit-to-improve-fairness.patch @@ -15,7 +15,7 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h -@@ -1216,6 +1216,7 @@ struct ieee80211_local { +@@ -1215,6 +1215,7 @@ struct ieee80211_local { u32 aql_txq_limit_high[IEEE80211_NUM_ACS]; u32 aql_threshold; atomic_t aql_total_pending_airtime; diff --git a/package/kernel/mac80211/patches/subsys/343-wifi-mac80211-fix-decap-offload-for-stations-on-AP_V.patch b/package/kernel/mac80211/patches/subsys/343-wifi-mac80211-fix-decap-offload-for-stations-on-AP_V.patch index 0feb408d21..0246785475 100644 --- a/package/kernel/mac80211/patches/subsys/343-wifi-mac80211-fix-decap-offload-for-stations-on-AP_V.patch +++ b/package/kernel/mac80211/patches/subsys/343-wifi-mac80211-fix-decap-offload-for-stations-on-AP_V.patch @@ -13,7 +13,7 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c -@@ -4265,6 +4265,7 @@ void ieee80211_check_fast_rx(struct sta_ +@@ -4267,6 +4267,7 @@ void ieee80211_check_fast_rx(struct sta_ .vif_type = sdata->vif.type, .control_port_protocol = sdata->control_port_protocol, }, *old, *new = NULL; @@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau bool set_offload = false; bool assign = false; bool offload; -@@ -4380,10 +4381,10 @@ void ieee80211_check_fast_rx(struct sta_ +@@ -4382,10 +4383,10 @@ void ieee80211_check_fast_rx(struct sta_ if (assign) new = kmemdup(&fastrx, sizeof(fastrx), GFP_KERNEL); diff --git a/package/kernel/mac80211/patches/subsys/345-wifi-mac80211-do-not-drop-packets-smaller-than-the-L.patch b/package/kernel/mac80211/patches/subsys/345-wifi-mac80211-do-not-drop-packets-smaller-than-the-L.patch index 16cafc447c..23047f68c9 100644 --- a/package/kernel/mac80211/patches/subsys/345-wifi-mac80211-do-not-drop-packets-smaller-than-the-L.patch +++ b/package/kernel/mac80211/patches/subsys/345-wifi-mac80211-do-not-drop-packets-smaller-than-the-L.patch @@ -14,7 +14,7 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c -@@ -4601,7 +4601,7 @@ static bool ieee80211_invoke_fast_rx(str +@@ -4603,7 +4603,7 @@ static bool ieee80211_invoke_fast_rx(str if (!(status->rx_flags & IEEE80211_RX_AMSDU)) { if (!pskb_may_pull(skb, snap_offs + sizeof(*payload))) diff --git a/package/kernel/mac80211/patches/subsys/346-mac80211-mesh-clean-up-rx_bcn_presp-API.patch b/package/kernel/mac80211/patches/subsys/346-mac80211-mesh-clean-up-rx_bcn_presp-API.patch deleted file mode 100644 index 3fa70b05fd..0000000000 --- a/package/kernel/mac80211/patches/subsys/346-mac80211-mesh-clean-up-rx_bcn_presp-API.patch +++ /dev/null @@ -1,110 +0,0 @@ -From: Johannes Berg -Date: Mon, 20 Sep 2021 15:40:07 +0200 -Subject: [PATCH] mac80211: mesh: clean up rx_bcn_presp API - -commit a5b983c6073140b624f64e79fea6d33c3e4315a0 upstream. - -We currently pass the entire elements to the rx_bcn_presp() -method, but only need mesh_config. Additionally, we use the -length of the elements to calculate back the entire frame's -length, but that's confusing - just pass the length of the -frame instead. - -Link: https://lore.kernel.org/r/20210920154009.a18ed3d2da6c.I1824b773a0fbae4453e1433c184678ca14e8df45@changeid -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/ieee80211_i.h -+++ b/net/mac80211/ieee80211_i.h -@@ -645,10 +645,9 @@ struct ieee80211_if_ocb { - */ - struct ieee802_11_elems; - struct ieee80211_mesh_sync_ops { -- void (*rx_bcn_presp)(struct ieee80211_sub_if_data *sdata, -- u16 stype, -- struct ieee80211_mgmt *mgmt, -- struct ieee802_11_elems *elems, -+ void (*rx_bcn_presp)(struct ieee80211_sub_if_data *sdata, u16 stype, -+ struct ieee80211_mgmt *mgmt, unsigned int len, -+ const struct ieee80211_meshconf_ie *mesh_cfg, - struct ieee80211_rx_status *rx_status); - - /* should be called with beacon_data under RCU read lock */ ---- a/net/mac80211/mesh.c -+++ b/net/mac80211/mesh.c -@@ -1354,8 +1354,8 @@ static void ieee80211_mesh_rx_bcn_presp( - } - - if (ifmsh->sync_ops) -- ifmsh->sync_ops->rx_bcn_presp(sdata, -- stype, mgmt, &elems, rx_status); -+ ifmsh->sync_ops->rx_bcn_presp(sdata, stype, mgmt, len, -+ elems.mesh_config, rx_status); - } - - int ieee80211_mesh_finish_csa(struct ieee80211_sub_if_data *sdata) ---- a/net/mac80211/mesh_sync.c -+++ b/net/mac80211/mesh_sync.c -@@ -3,6 +3,7 @@ - * Copyright 2011-2012, Pavel Zubarev - * Copyright 2011-2012, Marco Porsch - * Copyright 2011-2012, cozybit Inc. -+ * Copyright (C) 2021 Intel Corporation - */ - - #include "ieee80211_i.h" -@@ -35,12 +36,12 @@ struct sync_method { - /** - * mesh_peer_tbtt_adjusting - check if an mp is currently adjusting its TBTT - * -- * @ie: information elements of a management frame from the mesh peer -+ * @cfg: mesh config element from the mesh peer (or %NULL) - */ --static bool mesh_peer_tbtt_adjusting(struct ieee802_11_elems *ie) -+static bool mesh_peer_tbtt_adjusting(const struct ieee80211_meshconf_ie *cfg) - { -- return (ie->mesh_config->meshconf_cap & -- IEEE80211_MESHCONF_CAPAB_TBTT_ADJUSTING) != 0; -+ return cfg && -+ (cfg->meshconf_cap & IEEE80211_MESHCONF_CAPAB_TBTT_ADJUSTING); - } - - void mesh_sync_adjust_tsf(struct ieee80211_sub_if_data *sdata) -@@ -76,11 +77,11 @@ void mesh_sync_adjust_tsf(struct ieee802 - } - } - --static void mesh_sync_offset_rx_bcn_presp(struct ieee80211_sub_if_data *sdata, -- u16 stype, -- struct ieee80211_mgmt *mgmt, -- struct ieee802_11_elems *elems, -- struct ieee80211_rx_status *rx_status) -+static void -+mesh_sync_offset_rx_bcn_presp(struct ieee80211_sub_if_data *sdata, u16 stype, -+ struct ieee80211_mgmt *mgmt, unsigned int len, -+ const struct ieee80211_meshconf_ie *mesh_cfg, -+ struct ieee80211_rx_status *rx_status) - { - struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; - struct ieee80211_local *local = sdata->local; -@@ -101,10 +102,7 @@ static void mesh_sync_offset_rx_bcn_pres - */ - if (ieee80211_have_rx_timestamp(rx_status)) - t_r = ieee80211_calculate_rx_timestamp(local, rx_status, -- 24 + 12 + -- elems->total_len + -- FCS_LEN, -- 24); -+ len + FCS_LEN, 24); - else - t_r = drv_get_tsf(local, sdata); - -@@ -119,7 +117,7 @@ static void mesh_sync_offset_rx_bcn_pres - * dot11MeshNbrOffsetMaxNeighbor non-peer non-MBSS neighbors - */ - -- if (elems->mesh_config && mesh_peer_tbtt_adjusting(elems)) { -+ if (mesh_peer_tbtt_adjusting(mesh_cfg)) { - msync_dbg(sdata, "STA %pM : is adjusting TBTT\n", - sta->sta.addr); - goto no_sync; diff --git a/package/kernel/mac80211/patches/subsys/347-mac80211-move-CRC-into-struct-ieee802_11_elems.patch b/package/kernel/mac80211/patches/subsys/347-mac80211-move-CRC-into-struct-ieee802_11_elems.patch deleted file mode 100644 index e44aac5cba..0000000000 --- a/package/kernel/mac80211/patches/subsys/347-mac80211-move-CRC-into-struct-ieee802_11_elems.patch +++ /dev/null @@ -1,82 +0,0 @@ -From: Johannes Berg -Date: Mon, 20 Sep 2021 15:40:08 +0200 -Subject: [PATCH] mac80211: move CRC into struct ieee802_11_elems - -commit c6e37ed498f958254b5459253199e816b6bfc52f upstream. - -We're currently returning this value, but to prepare for -returning the allocated structure, move it into there. - -Link: https://lore.kernel.org/r/20210920154009.479b8ebf999d.If0d4ba75ee38998dc3eeae25058aa748efcb2fc9@changeid -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/ieee80211_i.h -+++ b/net/mac80211/ieee80211_i.h -@@ -1530,6 +1530,7 @@ struct ieee80211_csa_ie { - struct ieee802_11_elems { - const u8 *ie_start; - size_t total_len; -+ u32 crc; - - /* pointers to IEs */ - const struct ieee80211_tdls_lnkie *lnk_id; -@@ -2089,10 +2090,10 @@ static inline void ieee80211_tx_skb(stru - ieee80211_tx_skb_tid(sdata, skb, 7); - } - --u32 ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, -- struct ieee802_11_elems *elems, -- u64 filter, u32 crc, u8 *transmitter_bssid, -- u8 *bss_bssid); -+void ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, -+ struct ieee802_11_elems *elems, -+ u64 filter, u32 crc, u8 *transmitter_bssid, -+ u8 *bss_bssid); - static inline void ieee802_11_parse_elems(const u8 *start, size_t len, - bool action, - struct ieee802_11_elems *elems, ---- a/net/mac80211/mlme.c -+++ b/net/mac80211/mlme.c -@@ -4102,10 +4102,11 @@ static void ieee80211_rx_mgmt_beacon(str - */ - if (!ieee80211_is_s1g_beacon(hdr->frame_control)) - ncrc = crc32_be(0, (void *)&mgmt->u.beacon.beacon_int, 4); -- ncrc = ieee802_11_parse_elems_crc(variable, -- len - baselen, false, &elems, -- care_about_ies, ncrc, -- mgmt->bssid, bssid); -+ ieee802_11_parse_elems_crc(variable, -+ len - baselen, false, &elems, -+ care_about_ies, ncrc, -+ mgmt->bssid, bssid); -+ ncrc = elems.crc; - - if (ieee80211_hw_check(&local->hw, PS_NULLFUNC_STACK) && - ieee80211_check_tim(elems.tim, elems.tim_len, bss_conf->aid)) { ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -1469,10 +1469,10 @@ static size_t ieee802_11_find_bssid_prof - return found ? profile_len : 0; - } - --u32 ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, -- struct ieee802_11_elems *elems, -- u64 filter, u32 crc, u8 *transmitter_bssid, -- u8 *bss_bssid) -+void ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, -+ struct ieee802_11_elems *elems, -+ u64 filter, u32 crc, u8 *transmitter_bssid, -+ u8 *bss_bssid) - { - const struct element *non_inherit = NULL; - u8 *nontransmitted_profile; -@@ -1524,7 +1524,7 @@ u32 ieee802_11_parse_elems_crc(const u8 - - kfree(nontransmitted_profile); - -- return crc; -+ elems->crc = crc; - } - - void ieee80211_regulatory_limit_wmm_params(struct ieee80211_sub_if_data *sdata, diff --git a/package/kernel/mac80211/patches/subsys/348-mac80211-mlme-find-auth-challenge-directly.patch b/package/kernel/mac80211/patches/subsys/348-mac80211-mlme-find-auth-challenge-directly.patch deleted file mode 100644 index 3432c25a91..0000000000 --- a/package/kernel/mac80211/patches/subsys/348-mac80211-mlme-find-auth-challenge-directly.patch +++ /dev/null @@ -1,80 +0,0 @@ -From: Johannes Berg -Date: Mon, 20 Sep 2021 15:40:09 +0200 -Subject: [PATCH] mac80211: mlme: find auth challenge directly - -commit 49a765d6785e99157ff5091cc37485732496864e upstream. - -There's no need to parse all elements etc. just to find the -authentication challenge - use cfg80211_find_elem() instead. -This also allows us to remove WLAN_EID_CHALLENGE handling -from the element parsing entirely. - -Link: https://lore.kernel.org/r/20210920154009.45f9b3a15722.Ice3159ffad03a007d6154cbf1fb3a8c48489e86f@changeid -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/ieee80211_i.h -+++ b/net/mac80211/ieee80211_i.h -@@ -1540,7 +1540,6 @@ struct ieee802_11_elems { - const u8 *supp_rates; - const u8 *ds_params; - const struct ieee80211_tim_ie *tim; -- const u8 *challenge; - const u8 *rsn; - const u8 *rsnx; - const u8 *erp_info; -@@ -1594,7 +1593,6 @@ struct ieee802_11_elems { - u8 ssid_len; - u8 supp_rates_len; - u8 tim_len; -- u8 challenge_len; - u8 rsn_len; - u8 rsnx_len; - u8 ext_supp_rates_len; ---- a/net/mac80211/mlme.c -+++ b/net/mac80211/mlme.c -@@ -2889,17 +2889,17 @@ static void ieee80211_auth_challenge(str - { - struct ieee80211_local *local = sdata->local; - struct ieee80211_mgd_auth_data *auth_data = sdata->u.mgd.auth_data; -+ const struct element *challenge; - u8 *pos; -- struct ieee802_11_elems elems; - u32 tx_flags = 0; - struct ieee80211_prep_tx_info info = { - .subtype = IEEE80211_STYPE_AUTH, - }; - - pos = mgmt->u.auth.variable; -- ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, &elems, -- mgmt->bssid, auth_data->bss->bssid); -- if (!elems.challenge) -+ challenge = cfg80211_find_elem(WLAN_EID_CHALLENGE, pos, -+ len - (pos - (u8 *)mgmt)); -+ if (!challenge) - return; - auth_data->expected_transaction = 4; - drv_mgd_prepare_tx(sdata->local, sdata, &info); -@@ -2907,7 +2907,8 @@ static void ieee80211_auth_challenge(str - tx_flags = IEEE80211_TX_CTL_REQ_TX_STATUS | - IEEE80211_TX_INTFL_MLME_CONN_TX; - ieee80211_send_auth(sdata, 3, auth_data->algorithm, 0, -- elems.challenge - 2, elems.challenge_len + 2, -+ (void *)challenge, -+ challenge->datalen + sizeof(*challenge), - auth_data->bss->bssid, auth_data->bss->bssid, - auth_data->key, auth_data->key_len, - auth_data->key_idx, tx_flags); ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -1120,10 +1120,6 @@ _ieee802_11_parse_elems_crc(const u8 *st - } else - elem_parse_failed = true; - break; -- case WLAN_EID_CHALLENGE: -- elems->challenge = pos; -- elems->challenge_len = elen; -- break; - case WLAN_EID_VENDOR_SPECIFIC: - if (elen >= 4 && pos[0] == 0x00 && pos[1] == 0x50 && - pos[2] == 0xf2) { diff --git a/package/kernel/mac80211/patches/subsys/349-mac80211-always-allocate-struct-ieee802_11_elems.patch b/package/kernel/mac80211/patches/subsys/349-mac80211-always-allocate-struct-ieee802_11_elems.patch deleted file mode 100644 index 75655279a9..0000000000 --- a/package/kernel/mac80211/patches/subsys/349-mac80211-always-allocate-struct-ieee802_11_elems.patch +++ /dev/null @@ -1,1143 +0,0 @@ -From: Johannes Berg -Date: Mon, 20 Sep 2021 15:40:10 +0200 -Subject: [PATCH] mac80211: always allocate struct ieee802_11_elems - -As the 802.11 spec evolves, we need to parse more and more -elements. This is causing the struct to grow, and we can no -longer get away with putting it on the stack. - -Change the API to always dynamically allocate and return an -allocated pointer that must be kfree()d later. - -As an alternative, I contemplated a scheme whereby we'd say -in the code which elements we needed, e.g. - - DECLARE_ELEMENT_PARSER(elems, - SUPPORTED_CHANNELS, - CHANNEL_SWITCH, - EXT(KEY_DELIVERY)); - - ieee802_11_parse_elems(..., &elems, ...); - -and while I think this is possible and will save us a lot -since most individual places only care about a small subset -of the elements, it ended up being a bit more work since a -lot of places do the parsing and then pass the struct to -other functions, sometimes with multiple levels. - -Link: https://lore.kernel.org/r/20210920154009.26caff6b5998.I05ae58768e990e611aee8eca8abefd9d7bc15e05@changeid -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/agg-rx.c -+++ b/net/mac80211/agg-rx.c -@@ -478,7 +478,7 @@ void ieee80211_process_addba_request(str - size_t len) - { - u16 capab, tid, timeout, ba_policy, buf_size, start_seq_num; -- struct ieee802_11_elems elems = { }; -+ struct ieee802_11_elems *elems = NULL; - u8 dialog_token; - int ies_len; - -@@ -496,16 +496,17 @@ void ieee80211_process_addba_request(str - ies_len = len - offsetof(struct ieee80211_mgmt, - u.action.u.addba_req.variable); - if (ies_len) { -- ieee802_11_parse_elems(mgmt->u.action.u.addba_req.variable, -- ies_len, true, &elems, mgmt->bssid, NULL); -- if (elems.parse_error) -+ elems = ieee802_11_parse_elems(mgmt->u.action.u.addba_req.variable, -+ ies_len, true, mgmt->bssid, NULL); -+ if (!elems || elems->parse_error) - return; - } - - __ieee80211_start_rx_ba_session(sta, dialog_token, timeout, - start_seq_num, ba_policy, tid, - buf_size, true, false, -- elems.addba_ext_ie); -+ elems ? elems->addba_ext_ie : NULL); -+ kfree(elems); - } - - void ieee80211_manage_rx_ba_offl(struct ieee80211_vif *vif, ---- a/net/mac80211/ibss.c -+++ b/net/mac80211/ibss.c -@@ -9,7 +9,7 @@ - * Copyright 2009, Johannes Berg - * Copyright 2013-2014 Intel Mobile Communications GmbH - * Copyright(c) 2016 Intel Deutschland GmbH -- * Copyright(c) 2018-2020 Intel Corporation -+ * Copyright(c) 2018-2021 Intel Corporation - */ - - #include -@@ -1589,7 +1589,7 @@ void ieee80211_rx_mgmt_probe_beacon(stru - struct ieee80211_rx_status *rx_status) - { - size_t baselen; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - - BUILD_BUG_ON(offsetof(typeof(mgmt->u.probe_resp), variable) != - offsetof(typeof(mgmt->u.beacon), variable)); -@@ -1602,10 +1602,14 @@ void ieee80211_rx_mgmt_probe_beacon(stru - if (baselen > len) - return; - -- ieee802_11_parse_elems(mgmt->u.probe_resp.variable, len - baselen, -- false, &elems, mgmt->bssid, NULL); -- -- ieee80211_rx_bss_info(sdata, mgmt, len, rx_status, &elems); -+ elems = ieee802_11_parse_elems(mgmt->u.probe_resp.variable, -+ len - baselen, false, -+ mgmt->bssid, NULL); -+ -+ if (elems) { -+ ieee80211_rx_bss_info(sdata, mgmt, len, rx_status, elems); -+ kfree(elems); -+ } - } - - void ieee80211_ibss_rx_queued_mgmt(struct ieee80211_sub_if_data *sdata, -@@ -1614,7 +1618,7 @@ void ieee80211_ibss_rx_queued_mgmt(struc - struct ieee80211_rx_status *rx_status; - struct ieee80211_mgmt *mgmt; - u16 fc; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - int ies_len; - - rx_status = IEEE80211_SKB_RXCB(skb); -@@ -1651,15 +1655,16 @@ void ieee80211_ibss_rx_queued_mgmt(struc - if (ies_len < 0) - break; - -- ieee802_11_parse_elems( -+ elems = ieee802_11_parse_elems( - mgmt->u.action.u.chan_switch.variable, -- ies_len, true, &elems, mgmt->bssid, NULL); -+ ies_len, true, mgmt->bssid, NULL); - -- if (elems.parse_error) -+ if (!elems || elems->parse_error) - break; - - ieee80211_rx_mgmt_spectrum_mgmt(sdata, mgmt, skb->len, -- rx_status, &elems); -+ rx_status, elems); -+ kfree(elems); - break; - } - } ---- a/net/mac80211/ieee80211_i.h -+++ b/net/mac80211/ieee80211_i.h -@@ -2088,18 +2088,18 @@ static inline void ieee80211_tx_skb(stru - ieee80211_tx_skb_tid(sdata, skb, 7); - } - --void ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, -- struct ieee802_11_elems *elems, -- u64 filter, u32 crc, u8 *transmitter_bssid, -- u8 *bss_bssid); --static inline void ieee802_11_parse_elems(const u8 *start, size_t len, -- bool action, -- struct ieee802_11_elems *elems, -- u8 *transmitter_bssid, -- u8 *bss_bssid) -+struct ieee802_11_elems *ieee802_11_parse_elems_crc(const u8 *start, size_t len, -+ bool action, -+ u64 filter, u32 crc, -+ const u8 *transmitter_bssid, -+ const u8 *bss_bssid); -+static inline struct ieee802_11_elems * -+ieee802_11_parse_elems(const u8 *start, size_t len, bool action, -+ const u8 *transmitter_bssid, -+ const u8 *bss_bssid) - { -- ieee802_11_parse_elems_crc(start, len, action, elems, 0, 0, -- transmitter_bssid, bss_bssid); -+ return ieee802_11_parse_elems_crc(start, len, action, 0, 0, -+ transmitter_bssid, bss_bssid); - } - - ---- a/net/mac80211/mesh.c -+++ b/net/mac80211/mesh.c -@@ -1247,7 +1247,7 @@ ieee80211_mesh_rx_probe_req(struct ieee8 - struct sk_buff *presp; - struct beacon_data *bcn; - struct ieee80211_mgmt *hdr; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - size_t baselen; - u8 *pos; - -@@ -1256,22 +1256,24 @@ ieee80211_mesh_rx_probe_req(struct ieee8 - if (baselen > len) - return; - -- ieee802_11_parse_elems(pos, len - baselen, false, &elems, mgmt->bssid, -- NULL); -- -- if (!elems.mesh_id) -+ elems = ieee802_11_parse_elems(pos, len - baselen, false, mgmt->bssid, -+ NULL); -+ if (!elems) - return; - -+ if (!elems->mesh_id) -+ goto free; -+ - /* 802.11-2012 10.1.4.3.2 */ - if ((!ether_addr_equal(mgmt->da, sdata->vif.addr) && - !is_broadcast_ether_addr(mgmt->da)) || -- elems.ssid_len != 0) -- return; -+ elems->ssid_len != 0) -+ goto free; - -- if (elems.mesh_id_len != 0 && -- (elems.mesh_id_len != ifmsh->mesh_id_len || -- memcmp(elems.mesh_id, ifmsh->mesh_id, ifmsh->mesh_id_len))) -- return; -+ if (elems->mesh_id_len != 0 && -+ (elems->mesh_id_len != ifmsh->mesh_id_len || -+ memcmp(elems->mesh_id, ifmsh->mesh_id, ifmsh->mesh_id_len))) -+ goto free; - - rcu_read_lock(); - bcn = rcu_dereference(ifmsh->beacon); -@@ -1295,6 +1297,8 @@ ieee80211_mesh_rx_probe_req(struct ieee8 - ieee80211_tx_skb(sdata, presp); - out: - rcu_read_unlock(); -+free: -+ kfree(elems); - } - - static void ieee80211_mesh_rx_bcn_presp(struct ieee80211_sub_if_data *sdata, -@@ -1305,7 +1309,7 @@ static void ieee80211_mesh_rx_bcn_presp( - { - struct ieee80211_local *local = sdata->local; - struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - struct ieee80211_channel *channel; - size_t baselen; - int freq; -@@ -1320,42 +1324,47 @@ static void ieee80211_mesh_rx_bcn_presp( - if (baselen > len) - return; - -- ieee802_11_parse_elems(mgmt->u.probe_resp.variable, len - baselen, -- false, &elems, mgmt->bssid, NULL); -+ elems = ieee802_11_parse_elems(mgmt->u.probe_resp.variable, -+ len - baselen, -+ false, mgmt->bssid, NULL); -+ if (!elems) -+ return; - - /* ignore non-mesh or secure / unsecure mismatch */ -- if ((!elems.mesh_id || !elems.mesh_config) || -- (elems.rsn && sdata->u.mesh.security == IEEE80211_MESH_SEC_NONE) || -- (!elems.rsn && sdata->u.mesh.security != IEEE80211_MESH_SEC_NONE)) -- return; -+ if ((!elems->mesh_id || !elems->mesh_config) || -+ (elems->rsn && sdata->u.mesh.security == IEEE80211_MESH_SEC_NONE) || -+ (!elems->rsn && sdata->u.mesh.security != IEEE80211_MESH_SEC_NONE)) -+ goto free; - -- if (elems.ds_params) -- freq = ieee80211_channel_to_frequency(elems.ds_params[0], band); -+ if (elems->ds_params) -+ freq = ieee80211_channel_to_frequency(elems->ds_params[0], band); - else - freq = rx_status->freq; - - channel = ieee80211_get_channel(local->hw.wiphy, freq); - - if (!channel || channel->flags & IEEE80211_CHAN_DISABLED) -- return; -+ goto free; - -- if (mesh_matches_local(sdata, &elems)) { -+ if (mesh_matches_local(sdata, elems)) { - mpl_dbg(sdata, "rssi_threshold=%d,rx_status->signal=%d\n", - sdata->u.mesh.mshcfg.rssi_threshold, rx_status->signal); - if (!sdata->u.mesh.user_mpm || - sdata->u.mesh.mshcfg.rssi_threshold == 0 || - sdata->u.mesh.mshcfg.rssi_threshold < rx_status->signal) -- mesh_neighbour_update(sdata, mgmt->sa, &elems, -+ mesh_neighbour_update(sdata, mgmt->sa, elems, - rx_status); - - if (ifmsh->csa_role != IEEE80211_MESH_CSA_ROLE_INIT && - !sdata->vif.csa_active) -- ieee80211_mesh_process_chnswitch(sdata, &elems, true); -+ ieee80211_mesh_process_chnswitch(sdata, elems, true); - } - - if (ifmsh->sync_ops) - ifmsh->sync_ops->rx_bcn_presp(sdata, stype, mgmt, len, -- elems.mesh_config, rx_status); -+ elems->mesh_config, rx_status); -+free: -+ kfree(elems); - } - - int ieee80211_mesh_finish_csa(struct ieee80211_sub_if_data *sdata) -@@ -1447,7 +1456,7 @@ static void mesh_rx_csa_frame(struct iee - struct ieee80211_mgmt *mgmt, size_t len) - { - struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - u16 pre_value; - bool fwd_csa = true; - size_t baselen; -@@ -1460,33 +1469,37 @@ static void mesh_rx_csa_frame(struct iee - pos = mgmt->u.action.u.chan_switch.variable; - baselen = offsetof(struct ieee80211_mgmt, - u.action.u.chan_switch.variable); -- ieee802_11_parse_elems(pos, len - baselen, true, &elems, -- mgmt->bssid, NULL); -- -- if (!mesh_matches_local(sdata, &elems)) -+ elems = ieee802_11_parse_elems(pos, len - baselen, true, -+ mgmt->bssid, NULL); -+ if (!elems) - return; - -- ifmsh->chsw_ttl = elems.mesh_chansw_params_ie->mesh_ttl; -+ if (!mesh_matches_local(sdata, elems)) -+ goto free; -+ -+ ifmsh->chsw_ttl = elems->mesh_chansw_params_ie->mesh_ttl; - if (!--ifmsh->chsw_ttl) - fwd_csa = false; - -- pre_value = le16_to_cpu(elems.mesh_chansw_params_ie->mesh_pre_value); -+ pre_value = le16_to_cpu(elems->mesh_chansw_params_ie->mesh_pre_value); - if (ifmsh->pre_value >= pre_value) -- return; -+ goto free; - - ifmsh->pre_value = pre_value; - - if (!sdata->vif.csa_active && -- !ieee80211_mesh_process_chnswitch(sdata, &elems, false)) { -+ !ieee80211_mesh_process_chnswitch(sdata, elems, false)) { - mcsa_dbg(sdata, "Failed to process CSA action frame"); -- return; -+ goto free; - } - - /* forward or re-broadcast the CSA frame */ - if (fwd_csa) { -- if (mesh_fwd_csa_frame(sdata, mgmt, len, &elems) < 0) -+ if (mesh_fwd_csa_frame(sdata, mgmt, len, elems) < 0) - mcsa_dbg(sdata, "Failed to forward the CSA frame"); - } -+free: -+ kfree(elems); - } - - static void ieee80211_mesh_rx_mgmt_action(struct ieee80211_sub_if_data *sdata, ---- a/net/mac80211/mesh_hwmp.c -+++ b/net/mac80211/mesh_hwmp.c -@@ -1,7 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0-only - /* - * Copyright (c) 2008, 2009 open80211s Ltd. -- * Copyright (C) 2019 Intel Corporation -+ * Copyright (C) 2019, 2021 Intel Corporation - * Author: Luis Carlos Cobo - */ - -@@ -908,7 +908,7 @@ static void hwmp_rann_frame_process(stru - void mesh_rx_path_sel_frame(struct ieee80211_sub_if_data *sdata, - struct ieee80211_mgmt *mgmt, size_t len) - { -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - size_t baselen; - u32 path_metric; - struct sta_info *sta; -@@ -926,37 +926,41 @@ void mesh_rx_path_sel_frame(struct ieee8 - rcu_read_unlock(); - - baselen = (u8 *) mgmt->u.action.u.mesh_action.variable - (u8 *) mgmt; -- ieee802_11_parse_elems(mgmt->u.action.u.mesh_action.variable, -- len - baselen, false, &elems, mgmt->bssid, NULL); -+ elems = ieee802_11_parse_elems(mgmt->u.action.u.mesh_action.variable, -+ len - baselen, false, mgmt->bssid, NULL); -+ if (!elems) -+ return; - -- if (elems.preq) { -- if (elems.preq_len != 37) -+ if (elems->preq) { -+ if (elems->preq_len != 37) - /* Right now we support just 1 destination and no AE */ -- return; -- path_metric = hwmp_route_info_get(sdata, mgmt, elems.preq, -+ goto free; -+ path_metric = hwmp_route_info_get(sdata, mgmt, elems->preq, - MPATH_PREQ); - if (path_metric) -- hwmp_preq_frame_process(sdata, mgmt, elems.preq, -+ hwmp_preq_frame_process(sdata, mgmt, elems->preq, - path_metric); - } -- if (elems.prep) { -- if (elems.prep_len != 31) -+ if (elems->prep) { -+ if (elems->prep_len != 31) - /* Right now we support no AE */ -- return; -- path_metric = hwmp_route_info_get(sdata, mgmt, elems.prep, -+ goto free; -+ path_metric = hwmp_route_info_get(sdata, mgmt, elems->prep, - MPATH_PREP); - if (path_metric) -- hwmp_prep_frame_process(sdata, mgmt, elems.prep, -+ hwmp_prep_frame_process(sdata, mgmt, elems->prep, - path_metric); - } -- if (elems.perr) { -- if (elems.perr_len != 15) -+ if (elems->perr) { -+ if (elems->perr_len != 15) - /* Right now we support only one destination per PERR */ -- return; -- hwmp_perr_frame_process(sdata, mgmt, elems.perr); -+ goto free; -+ hwmp_perr_frame_process(sdata, mgmt, elems->perr); - } -- if (elems.rann) -- hwmp_rann_frame_process(sdata, mgmt, elems.rann); -+ if (elems->rann) -+ hwmp_rann_frame_process(sdata, mgmt, elems->rann); -+free: -+ kfree(elems); - } - - /** ---- a/net/mac80211/mesh_plink.c -+++ b/net/mac80211/mesh_plink.c -@@ -1,7 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0-only - /* - * Copyright (c) 2008, 2009 open80211s Ltd. -- * Copyright (C) 2019 Intel Corporation -+ * Copyright (C) 2019, 2021 Intel Corporation - * Author: Luis Carlos Cobo - */ - #include -@@ -1200,7 +1200,7 @@ void mesh_rx_plink_frame(struct ieee8021 - struct ieee80211_mgmt *mgmt, size_t len, - struct ieee80211_rx_status *rx_status) - { -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - size_t baselen; - u8 *baseaddr; - -@@ -1228,7 +1228,8 @@ void mesh_rx_plink_frame(struct ieee8021 - if (baselen > len) - return; - } -- ieee802_11_parse_elems(baseaddr, len - baselen, true, &elems, -- mgmt->bssid, NULL); -- mesh_process_plink_frame(sdata, mgmt, &elems, rx_status); -+ elems = ieee802_11_parse_elems(baseaddr, len - baselen, true, -+ mgmt->bssid, NULL); -+ mesh_process_plink_frame(sdata, mgmt, elems, rx_status); -+ kfree(elems); - } ---- a/net/mac80211/mlme.c -+++ b/net/mac80211/mlme.c -@@ -3317,8 +3317,11 @@ static bool ieee80211_assoc_success(stru - aid = 0; /* TODO */ - } - capab_info = le16_to_cpu(mgmt->u.assoc_resp.capab_info); -- ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, elems, -- mgmt->bssid, assoc_data->bss->bssid); -+ elems = ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, -+ mgmt->bssid, assoc_data->bss->bssid); -+ -+ if (!elems) -+ return false; - - if (elems->aid_resp) - aid = le16_to_cpu(elems->aid_resp->aid); -@@ -3340,7 +3343,8 @@ static bool ieee80211_assoc_success(stru - - if (!is_s1g && !elems->supp_rates) { - sdata_info(sdata, "no SuppRates element in AssocResp\n"); -- return false; -+ ret = false; -+ goto out; - } - - sdata->vif.bss_conf.aid = aid; -@@ -3362,7 +3366,7 @@ static bool ieee80211_assoc_success(stru - (!(ifmgd->flags & IEEE80211_STA_DISABLE_VHT) && - (!elems->vht_cap_elem || !elems->vht_operation)))) { - const struct cfg80211_bss_ies *ies; -- struct ieee802_11_elems bss_elems; -+ struct ieee802_11_elems *bss_elems; - - rcu_read_lock(); - ies = rcu_dereference(cbss->ies); -@@ -3373,13 +3377,17 @@ static bool ieee80211_assoc_success(stru - if (!bss_ies) - return false; - -- ieee802_11_parse_elems(bss_ies->data, bss_ies->len, -- false, &bss_elems, -- mgmt->bssid, -- assoc_data->bss->bssid); -+ bss_elems = ieee802_11_parse_elems(bss_ies->data, bss_ies->len, -+ false, mgmt->bssid, -+ assoc_data->bss->bssid); -+ if (!bss_elems) { -+ ret = false; -+ goto out; -+ } -+ - if (assoc_data->wmm && -- !elems->wmm_param && bss_elems.wmm_param) { -- elems->wmm_param = bss_elems.wmm_param; -+ !elems->wmm_param && bss_elems->wmm_param) { -+ elems->wmm_param = bss_elems->wmm_param; - sdata_info(sdata, - "AP bug: WMM param missing from AssocResp\n"); - } -@@ -3388,30 +3396,32 @@ static bool ieee80211_assoc_success(stru - * Also check if we requested HT/VHT, otherwise the AP doesn't - * have to include the IEs in the (re)association response. - */ -- if (!elems->ht_cap_elem && bss_elems.ht_cap_elem && -+ if (!elems->ht_cap_elem && bss_elems->ht_cap_elem && - !(ifmgd->flags & IEEE80211_STA_DISABLE_HT)) { -- elems->ht_cap_elem = bss_elems.ht_cap_elem; -+ elems->ht_cap_elem = bss_elems->ht_cap_elem; - sdata_info(sdata, - "AP bug: HT capability missing from AssocResp\n"); - } -- if (!elems->ht_operation && bss_elems.ht_operation && -+ if (!elems->ht_operation && bss_elems->ht_operation && - !(ifmgd->flags & IEEE80211_STA_DISABLE_HT)) { -- elems->ht_operation = bss_elems.ht_operation; -+ elems->ht_operation = bss_elems->ht_operation; - sdata_info(sdata, - "AP bug: HT operation missing from AssocResp\n"); - } -- if (!elems->vht_cap_elem && bss_elems.vht_cap_elem && -+ if (!elems->vht_cap_elem && bss_elems->vht_cap_elem && - !(ifmgd->flags & IEEE80211_STA_DISABLE_VHT)) { -- elems->vht_cap_elem = bss_elems.vht_cap_elem; -+ elems->vht_cap_elem = bss_elems->vht_cap_elem; - sdata_info(sdata, - "AP bug: VHT capa missing from AssocResp\n"); - } -- if (!elems->vht_operation && bss_elems.vht_operation && -+ if (!elems->vht_operation && bss_elems->vht_operation && - !(ifmgd->flags & IEEE80211_STA_DISABLE_VHT)) { -- elems->vht_operation = bss_elems.vht_operation; -+ elems->vht_operation = bss_elems->vht_operation; - sdata_info(sdata, - "AP bug: VHT operation missing from AssocResp\n"); - } -+ -+ kfree(bss_elems); - } - - /* -@@ -3662,6 +3672,7 @@ static bool ieee80211_assoc_success(stru - - ret = true; - out: -+ kfree(elems); - kfree(bss_ies); - return ret; - } -@@ -3673,7 +3684,7 @@ static void ieee80211_rx_mgmt_assoc_resp - struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; - struct ieee80211_mgd_assoc_data *assoc_data = ifmgd->assoc_data; - u16 capab_info, status_code, aid; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - int ac, uapsd_queues = -1; - u8 *pos; - bool reassoc; -@@ -3730,14 +3741,16 @@ static void ieee80211_rx_mgmt_assoc_resp - fils_decrypt_assoc_resp(sdata, (u8 *)mgmt, &len, assoc_data) < 0) - return; - -- ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, &elems, -- mgmt->bssid, assoc_data->bss->bssid); -+ elems = ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, -+ mgmt->bssid, assoc_data->bss->bssid); -+ if (!elems) -+ goto notify_driver; - - if (status_code == WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY && -- elems.timeout_int && -- elems.timeout_int->type == WLAN_TIMEOUT_ASSOC_COMEBACK) { -+ elems->timeout_int && -+ elems->timeout_int->type == WLAN_TIMEOUT_ASSOC_COMEBACK) { - u32 tu, ms; -- tu = le32_to_cpu(elems.timeout_int->value); -+ tu = le32_to_cpu(elems->timeout_int->value); - ms = tu * 1024 / 1000; - sdata_info(sdata, - "%pM rejected association temporarily; comeback duration %u TU (%u ms)\n", -@@ -3757,7 +3770,7 @@ static void ieee80211_rx_mgmt_assoc_resp - event.u.mlme.reason = status_code; - drv_event_callback(sdata->local, sdata, &event); - } else { -- if (!ieee80211_assoc_success(sdata, cbss, mgmt, len, &elems)) { -+ if (!ieee80211_assoc_success(sdata, cbss, mgmt, len, elems)) { - /* oops -- internal error -- send timeout for now */ - ieee80211_destroy_assoc_data(sdata, false, false); - cfg80211_assoc_timeout(sdata->dev, cbss); -@@ -3787,6 +3800,7 @@ static void ieee80211_rx_mgmt_assoc_resp - ifmgd->assoc_req_ies, ifmgd->assoc_req_ies_len); - notify_driver: - drv_mgd_complete_tx(sdata->local, sdata, &info); -+ kfree(elems); - } - - static void ieee80211_rx_bss_info(struct ieee80211_sub_if_data *sdata, -@@ -3991,7 +4005,7 @@ static void ieee80211_rx_mgmt_beacon(str - struct ieee80211_bss_conf *bss_conf = &sdata->vif.bss_conf; - struct ieee80211_mgmt *mgmt = (void *) hdr; - size_t baselen; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - struct ieee80211_local *local = sdata->local; - struct ieee80211_chanctx_conf *chanctx_conf; - struct ieee80211_channel *chan; -@@ -4037,15 +4051,16 @@ static void ieee80211_rx_mgmt_beacon(str - - if (ifmgd->assoc_data && ifmgd->assoc_data->need_beacon && - ieee80211_rx_our_beacon(bssid, ifmgd->assoc_data->bss)) { -- ieee802_11_parse_elems(variable, -- len - baselen, false, &elems, -- bssid, -- ifmgd->assoc_data->bss->bssid); -+ elems = ieee802_11_parse_elems(variable, len - baselen, false, -+ bssid, -+ ifmgd->assoc_data->bss->bssid); -+ if (!elems) -+ return; - - ieee80211_rx_bss_info(sdata, mgmt, len, rx_status); - -- if (elems.dtim_period) -- ifmgd->dtim_period = elems.dtim_period; -+ if (elems->dtim_period) -+ ifmgd->dtim_period = elems->dtim_period; - ifmgd->have_beacon = true; - ifmgd->assoc_data->need_beacon = false; - if (ieee80211_hw_check(&local->hw, TIMING_BEACON_ONLY)) { -@@ -4053,17 +4068,17 @@ static void ieee80211_rx_mgmt_beacon(str - le64_to_cpu(mgmt->u.beacon.timestamp); - sdata->vif.bss_conf.sync_device_ts = - rx_status->device_timestamp; -- sdata->vif.bss_conf.sync_dtim_count = elems.dtim_count; -+ sdata->vif.bss_conf.sync_dtim_count = elems->dtim_count; - } - -- if (elems.mbssid_config_ie) -+ if (elems->mbssid_config_ie) - bss_conf->profile_periodicity = -- elems.mbssid_config_ie->profile_periodicity; -+ elems->mbssid_config_ie->profile_periodicity; - else - bss_conf->profile_periodicity = 0; - -- if (elems.ext_capab_len >= 11 && -- (elems.ext_capab[10] & WLAN_EXT_CAPA11_EMA_SUPPORT)) -+ if (elems->ext_capab_len >= 11 && -+ (elems->ext_capab[10] & WLAN_EXT_CAPA11_EMA_SUPPORT)) - bss_conf->ema_ap = true; - else - bss_conf->ema_ap = false; -@@ -4072,6 +4087,7 @@ static void ieee80211_rx_mgmt_beacon(str - ifmgd->assoc_data->timeout = jiffies; - ifmgd->assoc_data->timeout_started = true; - run_again(sdata, ifmgd->assoc_data->timeout); -+ kfree(elems); - return; - } - -@@ -4103,14 +4119,15 @@ static void ieee80211_rx_mgmt_beacon(str - */ - if (!ieee80211_is_s1g_beacon(hdr->frame_control)) - ncrc = crc32_be(0, (void *)&mgmt->u.beacon.beacon_int, 4); -- ieee802_11_parse_elems_crc(variable, -- len - baselen, false, &elems, -- care_about_ies, ncrc, -- mgmt->bssid, bssid); -- ncrc = elems.crc; -+ elems = ieee802_11_parse_elems_crc(variable, len - baselen, -+ false, care_about_ies, ncrc, -+ mgmt->bssid, bssid); -+ if (!elems) -+ return; -+ ncrc = elems->crc; - - if (ieee80211_hw_check(&local->hw, PS_NULLFUNC_STACK) && -- ieee80211_check_tim(elems.tim, elems.tim_len, bss_conf->aid)) { -+ ieee80211_check_tim(elems->tim, elems->tim_len, bss_conf->aid)) { - if (local->hw.conf.dynamic_ps_timeout > 0) { - if (local->hw.conf.flags & IEEE80211_CONF_PS) { - local->hw.conf.flags &= ~IEEE80211_CONF_PS; -@@ -4180,12 +4197,12 @@ static void ieee80211_rx_mgmt_beacon(str - le64_to_cpu(mgmt->u.beacon.timestamp); - sdata->vif.bss_conf.sync_device_ts = - rx_status->device_timestamp; -- sdata->vif.bss_conf.sync_dtim_count = elems.dtim_count; -+ sdata->vif.bss_conf.sync_dtim_count = elems->dtim_count; - } - - if ((ncrc == ifmgd->beacon_crc && ifmgd->beacon_crc_valid) || - ieee80211_is_s1g_short_beacon(mgmt->frame_control)) -- return; -+ goto free; - ifmgd->beacon_crc = ncrc; - ifmgd->beacon_crc_valid = true; - -@@ -4193,12 +4210,12 @@ static void ieee80211_rx_mgmt_beacon(str - - ieee80211_sta_process_chanswitch(sdata, rx_status->mactime, - rx_status->device_timestamp, -- &elems, true); -+ elems, true); - - if (!(ifmgd->flags & IEEE80211_STA_DISABLE_WMM) && -- ieee80211_sta_wmm_params(local, sdata, elems.wmm_param, -- elems.wmm_param_len, -- elems.mu_edca_param_set)) -+ ieee80211_sta_wmm_params(local, sdata, elems->wmm_param, -+ elems->wmm_param_len, -+ elems->mu_edca_param_set)) - changed |= BSS_CHANGED_QOS; - - /* -@@ -4207,7 +4224,7 @@ static void ieee80211_rx_mgmt_beacon(str - */ - if (!ifmgd->have_beacon) { - /* a few bogus AP send dtim_period = 0 or no TIM IE */ -- bss_conf->dtim_period = elems.dtim_period ?: 1; -+ bss_conf->dtim_period = elems->dtim_period ?: 1; - - changed |= BSS_CHANGED_BEACON_INFO; - ifmgd->have_beacon = true; -@@ -4219,9 +4236,9 @@ static void ieee80211_rx_mgmt_beacon(str - ieee80211_recalc_ps_vif(sdata); - } - -- if (elems.erp_info) { -+ if (elems->erp_info) { - erp_valid = true; -- erp_value = elems.erp_info[0]; -+ erp_value = elems->erp_info[0]; - } else { - erp_valid = false; - } -@@ -4234,12 +4251,12 @@ static void ieee80211_rx_mgmt_beacon(str - mutex_lock(&local->sta_mtx); - sta = sta_info_get(sdata, bssid); - -- changed |= ieee80211_recalc_twt_req(sdata, sta, &elems); -+ changed |= ieee80211_recalc_twt_req(sdata, sta, elems); - -- if (ieee80211_config_bw(sdata, sta, elems.ht_cap_elem, -- elems.vht_cap_elem, elems.ht_operation, -- elems.vht_operation, elems.he_operation, -- elems.s1g_oper, bssid, &changed)) { -+ if (ieee80211_config_bw(sdata, sta, elems->ht_cap_elem, -+ elems->vht_cap_elem, elems->ht_operation, -+ elems->vht_operation, elems->he_operation, -+ elems->s1g_oper, bssid, &changed)) { - mutex_unlock(&local->sta_mtx); - sdata_info(sdata, - "failed to follow AP %pM bandwidth change, disconnect\n", -@@ -4251,21 +4268,23 @@ static void ieee80211_rx_mgmt_beacon(str - sizeof(deauth_buf), true, - WLAN_REASON_DEAUTH_LEAVING, - false); -- return; -+ goto free; - } - -- if (sta && elems.opmode_notif) -- ieee80211_vht_handle_opmode(sdata, sta, *elems.opmode_notif, -+ if (sta && elems->opmode_notif) -+ ieee80211_vht_handle_opmode(sdata, sta, *elems->opmode_notif, - rx_status->band); - mutex_unlock(&local->sta_mtx); - - changed |= ieee80211_handle_pwr_constr(sdata, chan, mgmt, -- elems.country_elem, -- elems.country_elem_len, -- elems.pwr_constr_elem, -- elems.cisco_dtpc_elem); -+ elems->country_elem, -+ elems->country_elem_len, -+ elems->pwr_constr_elem, -+ elems->cisco_dtpc_elem); - - ieee80211_bss_info_change_notify(sdata, changed); -+free: -+ kfree(elems); - } - - void ieee80211_sta_rx_queued_ext(struct ieee80211_sub_if_data *sdata, -@@ -4294,7 +4313,6 @@ void ieee80211_sta_rx_queued_mgmt(struct - struct ieee80211_rx_status *rx_status; - struct ieee80211_mgmt *mgmt; - u16 fc; -- struct ieee802_11_elems elems; - int ies_len; - - rx_status = (struct ieee80211_rx_status *) skb->cb; -@@ -4326,6 +4344,8 @@ void ieee80211_sta_rx_queued_mgmt(struct - break; - case IEEE80211_STYPE_ACTION: - if (mgmt->u.action.category == WLAN_CATEGORY_SPECTRUM_MGMT) { -+ struct ieee802_11_elems *elems; -+ - ies_len = skb->len - - offsetof(struct ieee80211_mgmt, - u.action.u.chan_switch.variable); -@@ -4334,18 +4354,21 @@ void ieee80211_sta_rx_queued_mgmt(struct - break; - - /* CSA IE cannot be overridden, no need for BSSID */ -- ieee802_11_parse_elems( -- mgmt->u.action.u.chan_switch.variable, -- ies_len, true, &elems, mgmt->bssid, NULL); -+ elems = ieee802_11_parse_elems( -+ mgmt->u.action.u.chan_switch.variable, -+ ies_len, true, mgmt->bssid, NULL); - -- if (elems.parse_error) -+ if (!elems || elems->parse_error) - break; - - ieee80211_sta_process_chanswitch(sdata, - rx_status->mactime, - rx_status->device_timestamp, -- &elems, false); -+ elems, false); -+ kfree(elems); - } else if (mgmt->u.action.category == WLAN_CATEGORY_PUBLIC) { -+ struct ieee802_11_elems *elems; -+ - ies_len = skb->len - - offsetof(struct ieee80211_mgmt, - u.action.u.ext_chan_switch.variable); -@@ -4357,21 +4380,22 @@ void ieee80211_sta_rx_queued_mgmt(struct - * extended CSA IE can't be overridden, no need for - * BSSID - */ -- ieee802_11_parse_elems( -- mgmt->u.action.u.ext_chan_switch.variable, -- ies_len, true, &elems, mgmt->bssid, NULL); -+ elems = ieee802_11_parse_elems( -+ mgmt->u.action.u.ext_chan_switch.variable, -+ ies_len, true, mgmt->bssid, NULL); - -- if (elems.parse_error) -+ if (!elems || elems->parse_error) - break; - - /* for the handling code pretend this was also an IE */ -- elems.ext_chansw_ie = -+ elems->ext_chansw_ie = - &mgmt->u.action.u.ext_chan_switch.data; - - ieee80211_sta_process_chanswitch(sdata, - rx_status->mactime, - rx_status->device_timestamp, -- &elems, false); -+ elems, false); -+ kfree(elems); - } - break; - } ---- a/net/mac80211/scan.c -+++ b/net/mac80211/scan.c -@@ -9,7 +9,7 @@ - * Copyright 2007, Michael Wu - * Copyright 2013-2015 Intel Mobile Communications GmbH - * Copyright 2016-2017 Intel Deutschland GmbH -- * Copyright (C) 2018-2020 Intel Corporation -+ * Copyright (C) 2018-2021 Intel Corporation - */ - - #include -@@ -155,7 +155,7 @@ ieee80211_bss_info_update(struct ieee802 - }; - bool signal_valid; - struct ieee80211_sub_if_data *scan_sdata; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - size_t baselen; - u8 *elements; - -@@ -209,8 +209,10 @@ ieee80211_bss_info_update(struct ieee802 - if (baselen > len) - return NULL; - -- ieee802_11_parse_elems(elements, len - baselen, false, &elems, -- mgmt->bssid, cbss->bssid); -+ elems = ieee802_11_parse_elems(elements, len - baselen, false, -+ mgmt->bssid, cbss->bssid); -+ if (!elems) -+ return NULL; - - /* In case the signal is invalid update the status */ - signal_valid = channel == cbss->channel; -@@ -218,15 +220,17 @@ ieee80211_bss_info_update(struct ieee802 - rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; - - bss = (void *)cbss->priv; -- ieee80211_update_bss_from_elems(local, bss, &elems, rx_status, beacon); -+ ieee80211_update_bss_from_elems(local, bss, elems, rx_status, beacon); - - list_for_each_entry(non_tx_cbss, &cbss->nontrans_list, nontrans_list) { - non_tx_bss = (void *)non_tx_cbss->priv; - -- ieee80211_update_bss_from_elems(local, non_tx_bss, &elems, -+ ieee80211_update_bss_from_elems(local, non_tx_bss, elems, - rx_status, beacon); - } - -+ kfree(elems); -+ - return bss; - } - ---- a/net/mac80211/tdls.c -+++ b/net/mac80211/tdls.c -@@ -6,7 +6,7 @@ - * Copyright 2014, Intel Corporation - * Copyright 2014 Intel Mobile Communications GmbH - * Copyright 2015 - 2016 Intel Deutschland GmbH -- * Copyright (C) 2019 Intel Corporation -+ * Copyright (C) 2019, 2021 Intel Corporation - */ - - #include -@@ -1684,7 +1684,7 @@ ieee80211_process_tdls_channel_switch_re - struct sk_buff *skb) - { - struct ieee80211_local *local = sdata->local; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems = NULL; - struct sta_info *sta; - struct ieee80211_tdls_data *tf = (void *)skb->data; - bool local_initiator; -@@ -1718,16 +1718,20 @@ ieee80211_process_tdls_channel_switch_re - goto call_drv; - } - -- ieee802_11_parse_elems(tf->u.chan_switch_resp.variable, -- skb->len - baselen, false, &elems, -- NULL, NULL); -- if (elems.parse_error) { -+ elems = ieee802_11_parse_elems(tf->u.chan_switch_resp.variable, -+ skb->len - baselen, false, NULL, NULL); -+ if (!elems) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ if (elems->parse_error) { - tdls_dbg(sdata, "Invalid IEs in TDLS channel switch resp\n"); - ret = -EINVAL; - goto out; - } - -- if (!elems.ch_sw_timing || !elems.lnk_id) { -+ if (!elems->ch_sw_timing || !elems->lnk_id) { - tdls_dbg(sdata, "TDLS channel switch resp - missing IEs\n"); - ret = -EINVAL; - goto out; -@@ -1735,15 +1739,15 @@ ieee80211_process_tdls_channel_switch_re - - /* validate the initiator is set correctly */ - local_initiator = -- !memcmp(elems.lnk_id->init_sta, sdata->vif.addr, ETH_ALEN); -+ !memcmp(elems->lnk_id->init_sta, sdata->vif.addr, ETH_ALEN); - if (local_initiator == sta->sta.tdls_initiator) { - tdls_dbg(sdata, "TDLS chan switch invalid lnk-id initiator\n"); - ret = -EINVAL; - goto out; - } - -- params.switch_time = le16_to_cpu(elems.ch_sw_timing->switch_time); -- params.switch_timeout = le16_to_cpu(elems.ch_sw_timing->switch_timeout); -+ params.switch_time = le16_to_cpu(elems->ch_sw_timing->switch_time); -+ params.switch_timeout = le16_to_cpu(elems->ch_sw_timing->switch_timeout); - - params.tmpl_skb = - ieee80211_tdls_ch_sw_resp_tmpl_get(sta, ¶ms.ch_sw_tm_ie); -@@ -1763,6 +1767,7 @@ call_drv: - out: - mutex_unlock(&local->sta_mtx); - dev_kfree_skb_any(params.tmpl_skb); -+ kfree(elems); - return ret; - } - -@@ -1771,7 +1776,7 @@ ieee80211_process_tdls_channel_switch_re - struct sk_buff *skb) - { - struct ieee80211_local *local = sdata->local; -- struct ieee802_11_elems elems; -+ struct ieee802_11_elems *elems; - struct cfg80211_chan_def chandef; - struct ieee80211_channel *chan; - enum nl80211_channel_type chan_type; -@@ -1831,22 +1836,27 @@ ieee80211_process_tdls_channel_switch_re - return -EINVAL; - } - -- ieee802_11_parse_elems(tf->u.chan_switch_req.variable, -- skb->len - baselen, false, &elems, NULL, NULL); -- if (elems.parse_error) { -+ elems = ieee802_11_parse_elems(tf->u.chan_switch_req.variable, -+ skb->len - baselen, false, NULL, NULL); -+ if (!elems) -+ return -ENOMEM; -+ -+ if (elems->parse_error) { - tdls_dbg(sdata, "Invalid IEs in TDLS channel switch req\n"); -- return -EINVAL; -+ ret = -EINVAL; -+ goto free; - } - -- if (!elems.ch_sw_timing || !elems.lnk_id) { -+ if (!elems->ch_sw_timing || !elems->lnk_id) { - tdls_dbg(sdata, "TDLS channel switch req - missing IEs\n"); -- return -EINVAL; -+ ret = -EINVAL; -+ goto free; - } - -- if (!elems.sec_chan_offs) { -+ if (!elems->sec_chan_offs) { - chan_type = NL80211_CHAN_HT20; - } else { -- switch (elems.sec_chan_offs->sec_chan_offs) { -+ switch (elems->sec_chan_offs->sec_chan_offs) { - case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: - chan_type = NL80211_CHAN_HT40PLUS; - break; -@@ -1865,7 +1875,8 @@ ieee80211_process_tdls_channel_switch_re - if (!cfg80211_reg_can_beacon_relax(sdata->local->hw.wiphy, &chandef, - sdata->wdev.iftype)) { - tdls_dbg(sdata, "TDLS chan switch to forbidden channel\n"); -- return -EINVAL; -+ ret = -EINVAL; -+ goto free; - } - - mutex_lock(&local->sta_mtx); -@@ -1881,7 +1892,7 @@ ieee80211_process_tdls_channel_switch_re - - /* validate the initiator is set correctly */ - local_initiator = -- !memcmp(elems.lnk_id->init_sta, sdata->vif.addr, ETH_ALEN); -+ !memcmp(elems->lnk_id->init_sta, sdata->vif.addr, ETH_ALEN); - if (local_initiator == sta->sta.tdls_initiator) { - tdls_dbg(sdata, "TDLS chan switch invalid lnk-id initiator\n"); - ret = -EINVAL; -@@ -1889,16 +1900,16 @@ ieee80211_process_tdls_channel_switch_re - } - - /* peer should have known better */ -- if (!sta->sta.ht_cap.ht_supported && elems.sec_chan_offs && -- elems.sec_chan_offs->sec_chan_offs) { -+ if (!sta->sta.ht_cap.ht_supported && elems->sec_chan_offs && -+ elems->sec_chan_offs->sec_chan_offs) { - tdls_dbg(sdata, "TDLS chan switch - wide chan unsupported\n"); - ret = -ENOTSUPP; - goto out; - } - - params.chandef = &chandef; -- params.switch_time = le16_to_cpu(elems.ch_sw_timing->switch_time); -- params.switch_timeout = le16_to_cpu(elems.ch_sw_timing->switch_timeout); -+ params.switch_time = le16_to_cpu(elems->ch_sw_timing->switch_time); -+ params.switch_timeout = le16_to_cpu(elems->ch_sw_timing->switch_timeout); - - params.tmpl_skb = - ieee80211_tdls_ch_sw_resp_tmpl_get(sta, -@@ -1917,6 +1928,8 @@ ieee80211_process_tdls_channel_switch_re - out: - mutex_unlock(&local->sta_mtx); - dev_kfree_skb_any(params.tmpl_skb); -+free: -+ kfree(elems); - return ret; - } - ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -1399,8 +1399,8 @@ _ieee802_11_parse_elems_crc(const u8 *st - - static size_t ieee802_11_find_bssid_profile(const u8 *start, size_t len, - struct ieee802_11_elems *elems, -- u8 *transmitter_bssid, -- u8 *bss_bssid, -+ const u8 *transmitter_bssid, -+ const u8 *bss_bssid, - u8 *nontransmitted_profile) - { - const struct element *elem, *sub; -@@ -1465,16 +1465,20 @@ static size_t ieee802_11_find_bssid_prof - return found ? profile_len : 0; - } - --void ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, -- struct ieee802_11_elems *elems, -- u64 filter, u32 crc, u8 *transmitter_bssid, -- u8 *bss_bssid) -+struct ieee802_11_elems *ieee802_11_parse_elems_crc(const u8 *start, size_t len, -+ bool action, u64 filter, -+ u32 crc, -+ const u8 *transmitter_bssid, -+ const u8 *bss_bssid) - { -+ struct ieee802_11_elems *elems; - const struct element *non_inherit = NULL; - u8 *nontransmitted_profile; - int nontransmitted_profile_len = 0; - -- memset(elems, 0, sizeof(*elems)); -+ elems = kzalloc(sizeof(*elems), GFP_ATOMIC); -+ if (!elems) -+ return NULL; - elems->ie_start = start; - elems->total_len = len; - -@@ -1521,6 +1525,8 @@ void ieee802_11_parse_elems_crc(const u8 - kfree(nontransmitted_profile); - - elems->crc = crc; -+ -+ return elems; - } - - void ieee80211_regulatory_limit_wmm_params(struct ieee80211_sub_if_data *sdata, diff --git a/package/kernel/mac80211/patches/subsys/350-mac80211-fix-memory-leaks-with-element-parsing.patch b/package/kernel/mac80211/patches/subsys/350-mac80211-fix-memory-leaks-with-element-parsing.patch deleted file mode 100644 index f4906e8c03..0000000000 --- a/package/kernel/mac80211/patches/subsys/350-mac80211-fix-memory-leaks-with-element-parsing.patch +++ /dev/null @@ -1,115 +0,0 @@ -From: Johannes Berg -Date: Fri, 1 Oct 2021 21:11:08 +0200 -Subject: [PATCH] mac80211: fix memory leaks with element parsing - -commit 8223ac199a3849257e86ec27865dc63f034b1cf1 upstream. - -My previous commit 5d24828d05f3 ("mac80211: always allocate -struct ieee802_11_elems") had a few bugs and leaked the new -allocated struct in a few error cases, fix that. - -Fixes: 5d24828d05f3 ("mac80211: always allocate struct ieee802_11_elems") -Signed-off-by: Johannes Berg -Link: https://lore.kernel.org/r/20211001211108.9839928e42e0.Ib81ca187d3d3af7ed1bfeac2e00d08a4637c8025@changeid -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/agg-rx.c -+++ b/net/mac80211/agg-rx.c -@@ -499,13 +499,14 @@ void ieee80211_process_addba_request(str - elems = ieee802_11_parse_elems(mgmt->u.action.u.addba_req.variable, - ies_len, true, mgmt->bssid, NULL); - if (!elems || elems->parse_error) -- return; -+ goto free; - } - - __ieee80211_start_rx_ba_session(sta, dialog_token, timeout, - start_seq_num, ba_policy, tid, - buf_size, true, false, - elems ? elems->addba_ext_ie : NULL); -+free: - kfree(elems); - } - ---- a/net/mac80211/ibss.c -+++ b/net/mac80211/ibss.c -@@ -1659,11 +1659,11 @@ void ieee80211_ibss_rx_queued_mgmt(struc - mgmt->u.action.u.chan_switch.variable, - ies_len, true, mgmt->bssid, NULL); - -- if (!elems || elems->parse_error) -- break; -- -- ieee80211_rx_mgmt_spectrum_mgmt(sdata, mgmt, skb->len, -- rx_status, elems); -+ if (elems && !elems->parse_error) -+ ieee80211_rx_mgmt_spectrum_mgmt(sdata, mgmt, -+ skb->len, -+ rx_status, -+ elems); - kfree(elems); - break; - } ---- a/net/mac80211/mlme.c -+++ b/net/mac80211/mlme.c -@@ -3374,8 +3374,10 @@ static bool ieee80211_assoc_success(stru - bss_ies = kmemdup(ies, sizeof(*ies) + ies->len, - GFP_ATOMIC); - rcu_read_unlock(); -- if (!bss_ies) -- return false; -+ if (!bss_ies) { -+ ret = false; -+ goto out; -+ } - - bss_elems = ieee802_11_parse_elems(bss_ies->data, bss_ies->len, - false, mgmt->bssid, -@@ -4358,13 +4360,11 @@ void ieee80211_sta_rx_queued_mgmt(struct - mgmt->u.action.u.chan_switch.variable, - ies_len, true, mgmt->bssid, NULL); - -- if (!elems || elems->parse_error) -- break; -- -- ieee80211_sta_process_chanswitch(sdata, -- rx_status->mactime, -- rx_status->device_timestamp, -- elems, false); -+ if (elems && !elems->parse_error) -+ ieee80211_sta_process_chanswitch(sdata, -+ rx_status->mactime, -+ rx_status->device_timestamp, -+ elems, false); - kfree(elems); - } else if (mgmt->u.action.category == WLAN_CATEGORY_PUBLIC) { - struct ieee802_11_elems *elems; -@@ -4384,17 +4384,17 @@ void ieee80211_sta_rx_queued_mgmt(struct - mgmt->u.action.u.ext_chan_switch.variable, - ies_len, true, mgmt->bssid, NULL); - -- if (!elems || elems->parse_error) -- break; -+ if (elems && !elems->parse_error) { -+ /* for the handling code pretend it was an IE */ -+ elems->ext_chansw_ie = -+ &mgmt->u.action.u.ext_chan_switch.data; -+ -+ ieee80211_sta_process_chanswitch(sdata, -+ rx_status->mactime, -+ rx_status->device_timestamp, -+ elems, false); -+ } - -- /* for the handling code pretend this was also an IE */ -- elems->ext_chansw_ie = -- &mgmt->u.action.u.ext_chan_switch.data; -- -- ieee80211_sta_process_chanswitch(sdata, -- rx_status->mactime, -- rx_status->device_timestamp, -- elems, false); - kfree(elems); - } - break; diff --git a/package/kernel/mac80211/patches/subsys/351-wifi-cfg80211-fix-u8-overflow-in-cfg80211_update_not.patch b/package/kernel/mac80211/patches/subsys/351-wifi-cfg80211-fix-u8-overflow-in-cfg80211_update_not.patch deleted file mode 100644 index 9e1f781367..0000000000 --- a/package/kernel/mac80211/patches/subsys/351-wifi-cfg80211-fix-u8-overflow-in-cfg80211_update_not.patch +++ /dev/null @@ -1,41 +0,0 @@ -From: Johannes Berg -Date: Wed, 28 Sep 2022 21:56:15 +0200 -Subject: [PATCH] wifi: cfg80211: fix u8 overflow in - cfg80211_update_notlisted_nontrans() - -commit aebe9f4639b13a1f4e9a6b42cdd2e38c617b442d upstream. - -In the copy code of the elements, we do the following calculation -to reach the end of the MBSSID element: - - /* copy the IEs after MBSSID */ - cpy_len = mbssid[1] + 2; - -This looks fine, however, cpy_len is a u8, the same as mbssid[1], -so the addition of two can overflow. In this case the subsequent -memcpy() will overflow the allocated buffer, since it copies 256 -bytes too much due to the way the allocation and memcpy() sizes -are calculated. - -Fix this by using size_t for the cpy_len variable. - -This fixes CVE-2022-41674. - -Reported-by: Soenke Huster -Tested-by: Soenke Huster -Fixes: 0b8fb8235be8 ("cfg80211: Parsing of Multiple BSSID information in scanning") -Reviewed-by: Kees Cook -Signed-off-by: Johannes Berg ---- - ---- a/net/wireless/scan.c -+++ b/net/wireless/scan.c -@@ -2238,7 +2238,7 @@ cfg80211_update_notlisted_nontrans(struc - size_t new_ie_len; - struct cfg80211_bss_ies *new_ies; - const struct cfg80211_bss_ies *old; -- u8 cpy_len; -+ size_t cpy_len; - - lockdep_assert_held(&wiphy_to_rdev(wiphy)->bss_lock); - diff --git a/package/kernel/mac80211/patches/subsys/352-wifi-cfg80211-mac80211-reject-bad-MBSSID-elements.patch b/package/kernel/mac80211/patches/subsys/352-wifi-cfg80211-mac80211-reject-bad-MBSSID-elements.patch deleted file mode 100644 index 4c8e05e9ba..0000000000 --- a/package/kernel/mac80211/patches/subsys/352-wifi-cfg80211-mac80211-reject-bad-MBSSID-elements.patch +++ /dev/null @@ -1,47 +0,0 @@ -From: Johannes Berg -Date: Wed, 28 Sep 2022 22:01:37 +0200 -Subject: [PATCH] wifi: cfg80211/mac80211: reject bad MBSSID elements - -commit 8f033d2becc24aa6bfd2a5c104407963560caabc upstream - -Per spec, the maximum value for the MaxBSSID ('n') indicator is 8, -and the minimum is 1 since a multiple BSSID set with just one BSSID -doesn't make sense (the # of BSSIDs is limited by 2^n). - -Limit this in the parsing in both cfg80211 and mac80211, rejecting -any elements with an invalid value. - -This fixes potentially bad shifts in the processing of these inside -the cfg80211_gen_new_bssid() function later. - -I found this during the investigation of CVE-2022-41674 fixed by the -previous patch. - -Fixes: 0b8fb8235be8 ("cfg80211: Parsing of Multiple BSSID information in scanning") -Fixes: 78ac51f81532 ("mac80211: support multi-bssid") -Reviewed-by: Kees Cook -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -1413,6 +1413,8 @@ static size_t ieee802_11_find_bssid_prof - for_each_element_id(elem, WLAN_EID_MULTIPLE_BSSID, start, len) { - if (elem->datalen < 2) - continue; -+ if (elem->data[0] < 1 || elem->data[0] > 8) -+ continue; - - for_each_element(sub, elem->data + 1, elem->datalen - 1) { - u8 new_bssid[ETH_ALEN]; ---- a/net/wireless/scan.c -+++ b/net/wireless/scan.c -@@ -2103,6 +2103,8 @@ static void cfg80211_parse_mbssid_data(s - for_each_element_id(elem, WLAN_EID_MULTIPLE_BSSID, ie, ielen) { - if (elem->datalen < 4) - continue; -+ if (elem->data[0] < 1 || (int)elem->data[0] > 8) -+ continue; - for_each_element(sub, elem->data + 1, elem->datalen - 1) { - u8 profile_len; - diff --git a/package/kernel/mac80211/patches/subsys/353-wifi-mac80211-fix-MBSSID-parsing-use-after-free.patch b/package/kernel/mac80211/patches/subsys/353-wifi-mac80211-fix-MBSSID-parsing-use-after-free.patch deleted file mode 100644 index 6e97150e90..0000000000 --- a/package/kernel/mac80211/patches/subsys/353-wifi-mac80211-fix-MBSSID-parsing-use-after-free.patch +++ /dev/null @@ -1,94 +0,0 @@ -From: Johannes Berg -Date: Wed, 28 Sep 2022 22:07:15 +0200 -Subject: [PATCH] wifi: mac80211: fix MBSSID parsing use-after-free - -commit ff05d4b45dd89b922578dac497dcabf57cf771c6 - -When we parse a multi-BSSID element, we might point some -element pointers into the allocated nontransmitted_profile. -However, we free this before returning, causing UAF when the -relevant pointers in the parsed elements are accessed. - -Fix this by not allocating the scratch buffer separately but -as part of the returned structure instead, that way, there -are no lifetime issues with it. - -The scratch buffer introduction as part of the returned data -here is taken from MLO feature work done by Ilan. - -This fixes CVE-2022-42719. - -Fixes: 5023b14cf4df ("mac80211: support profile split between elements") -Co-developed-by: Ilan Peer -Signed-off-by: Ilan Peer -Reviewed-by: Kees Cook -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/ieee80211_i.h -+++ b/net/mac80211/ieee80211_i.h -@@ -1611,6 +1611,14 @@ struct ieee802_11_elems { - - /* whether a parse error occurred while retrieving these elements */ - bool parse_error; -+ -+ /* -+ * scratch buffer that can be used for various element parsing related -+ * tasks, e.g., element de-fragmentation etc. -+ */ -+ size_t scratch_len; -+ u8 *scratch_pos; -+ u8 scratch[]; - }; - - static inline struct ieee80211_local *hw_to_local( ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -1478,24 +1478,25 @@ struct ieee802_11_elems *ieee802_11_pars - u8 *nontransmitted_profile; - int nontransmitted_profile_len = 0; - -- elems = kzalloc(sizeof(*elems), GFP_ATOMIC); -+ elems = kzalloc(sizeof(*elems) + len, GFP_ATOMIC); - if (!elems) - return NULL; - elems->ie_start = start; - elems->total_len = len; - -- nontransmitted_profile = kmalloc(len, GFP_ATOMIC); -- if (nontransmitted_profile) { -- nontransmitted_profile_len = -- ieee802_11_find_bssid_profile(start, len, elems, -- transmitter_bssid, -- bss_bssid, -- nontransmitted_profile); -- non_inherit = -- cfg80211_find_ext_elem(WLAN_EID_EXT_NON_INHERITANCE, -- nontransmitted_profile, -- nontransmitted_profile_len); -- } -+ elems->scratch_len = len; -+ elems->scratch_pos = elems->scratch; -+ -+ nontransmitted_profile = elems->scratch_pos; -+ nontransmitted_profile_len = -+ ieee802_11_find_bssid_profile(start, len, elems, -+ transmitter_bssid, -+ bss_bssid, -+ nontransmitted_profile); -+ non_inherit = -+ cfg80211_find_ext_elem(WLAN_EID_EXT_NON_INHERITANCE, -+ nontransmitted_profile, -+ nontransmitted_profile_len); - - crc = _ieee802_11_parse_elems_crc(start, len, action, elems, filter, - crc, non_inherit); -@@ -1524,8 +1525,6 @@ struct ieee802_11_elems *ieee802_11_pars - offsetofend(struct ieee80211_bssid_index, dtim_count)) - elems->dtim_count = elems->bssid_index->dtim_count; - -- kfree(nontransmitted_profile); -- - elems->crc = crc; - - return elems; diff --git a/package/kernel/mac80211/patches/subsys/354-wifi-cfg80211-ensure-length-byte-is-present-before-a.patch b/package/kernel/mac80211/patches/subsys/354-wifi-cfg80211-ensure-length-byte-is-present-before-a.patch deleted file mode 100644 index da94840dac..0000000000 --- a/package/kernel/mac80211/patches/subsys/354-wifi-cfg80211-ensure-length-byte-is-present-before-a.patch +++ /dev/null @@ -1,41 +0,0 @@ -From: Johannes Berg -Date: Thu, 29 Sep 2022 21:50:44 +0200 -Subject: [PATCH] wifi: cfg80211: ensure length byte is present before - access - -commit 567e14e39e8f8c6997a1378bc3be615afca86063 upstream. - -When iterating the elements here, ensure the length byte is -present before checking it to see if the entire element will -fit into the buffer. - -Longer term, we should rewrite this code using the type-safe -element iteration macros that check all of this. - -Fixes: 0b8fb8235be8 ("cfg80211: Parsing of Multiple BSSID information in scanning") -Reported-by: Soenke Huster -Signed-off-by: Johannes Berg ---- - ---- a/net/wireless/scan.c -+++ b/net/wireless/scan.c -@@ -304,7 +304,8 @@ static size_t cfg80211_gen_new_ie(const - tmp_old = cfg80211_find_ie(WLAN_EID_SSID, ie, ielen); - tmp_old = (tmp_old) ? tmp_old + tmp_old[1] + 2 : ie; - -- while (tmp_old + tmp_old[1] + 2 - ie <= ielen) { -+ while (tmp_old + 2 - ie <= ielen && -+ tmp_old + tmp_old[1] + 2 - ie <= ielen) { - if (tmp_old[0] == 0) { - tmp_old++; - continue; -@@ -364,7 +365,8 @@ static size_t cfg80211_gen_new_ie(const - * copied to new ie, skip ssid, capability, bssid-index ie - */ - tmp_new = sub_copy; -- while (tmp_new + tmp_new[1] + 2 - sub_copy <= subie_len) { -+ while (tmp_new + 2 - sub_copy <= subie_len && -+ tmp_new + tmp_new[1] + 2 - sub_copy <= subie_len) { - if (!(tmp_new[0] == WLAN_EID_NON_TX_BSSID_CAP || - tmp_new[0] == WLAN_EID_SSID)) { - memcpy(pos, tmp_new, tmp_new[1] + 2); diff --git a/package/kernel/mac80211/patches/subsys/355-wifi-cfg80211-fix-BSS-refcounting-bugs.patch b/package/kernel/mac80211/patches/subsys/355-wifi-cfg80211-fix-BSS-refcounting-bugs.patch deleted file mode 100644 index 4680e1e815..0000000000 --- a/package/kernel/mac80211/patches/subsys/355-wifi-cfg80211-fix-BSS-refcounting-bugs.patch +++ /dev/null @@ -1,87 +0,0 @@ -From: Johannes Berg -Date: Fri, 30 Sep 2022 23:44:23 +0200 -Subject: [PATCH] wifi: cfg80211: fix BSS refcounting bugs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -commit 0b7808818cb9df6680f98996b8e9a439fa7bcc2f upstream. - -There are multiple refcounting bugs related to multi-BSSID: - - In bss_ref_get(), if the BSS has a hidden_beacon_bss, then - the bss pointer is overwritten before checking for the - transmitted BSS, which is clearly wrong. Fix this by using - the bss_from_pub() macro. - - - In cfg80211_bss_update() we copy the transmitted_bss pointer - from tmp into new, but then if we release new, we'll unref - it erroneously. We already set the pointer and ref it, but - need to NULL it since it was copied from the tmp data. - - - In cfg80211_inform_single_bss_data(), if adding to the non- - transmitted list fails, we unlink the BSS and yet still we - return it, but this results in returning an entry without - a reference. We shouldn't return it anyway if it was broken - enough to not get added there. - -This fixes CVE-2022-42720. - -Reported-by: Sönke Huster -Tested-by: Sönke Huster -Fixes: a3584f56de1c ("cfg80211: Properly track transmitting and non-transmitting BSS") -Signed-off-by: Johannes Berg ---- - ---- a/net/wireless/scan.c -+++ b/net/wireless/scan.c -@@ -143,18 +143,12 @@ static inline void bss_ref_get(struct cf - lockdep_assert_held(&rdev->bss_lock); - - bss->refcount++; -- if (bss->pub.hidden_beacon_bss) { -- bss = container_of(bss->pub.hidden_beacon_bss, -- struct cfg80211_internal_bss, -- pub); -- bss->refcount++; -- } -- if (bss->pub.transmitted_bss) { -- bss = container_of(bss->pub.transmitted_bss, -- struct cfg80211_internal_bss, -- pub); -- bss->refcount++; -- } -+ -+ if (bss->pub.hidden_beacon_bss) -+ bss_from_pub(bss->pub.hidden_beacon_bss)->refcount++; -+ -+ if (bss->pub.transmitted_bss) -+ bss_from_pub(bss->pub.transmitted_bss)->refcount++; - } - - static inline void bss_ref_put(struct cfg80211_registered_device *rdev, -@@ -1743,6 +1737,8 @@ cfg80211_bss_update(struct cfg80211_regi - new->refcount = 1; - INIT_LIST_HEAD(&new->hidden_list); - INIT_LIST_HEAD(&new->pub.nontrans_list); -+ /* we'll set this later if it was non-NULL */ -+ new->pub.transmitted_bss = NULL; - - if (rcu_access_pointer(tmp->pub.proberesp_ies)) { - hidden = rb_find_bss(rdev, tmp, BSS_CMP_HIDE_ZLEN); -@@ -1983,10 +1979,15 @@ cfg80211_inform_single_bss_data(struct w - spin_lock_bh(&rdev->bss_lock); - if (cfg80211_add_nontrans_list(non_tx_data->tx_bss, - &res->pub)) { -- if (__cfg80211_unlink_bss(rdev, res)) -+ if (__cfg80211_unlink_bss(rdev, res)) { - rdev->bss_generation++; -+ res = NULL; -+ } - } - spin_unlock_bh(&rdev->bss_lock); -+ -+ if (!res) -+ return NULL; - } - - trace_cfg80211_return_bss(&res->pub); diff --git a/package/kernel/mac80211/patches/subsys/356-wifi-cfg80211-avoid-nontransmitted-BSS-list-corrupti.patch b/package/kernel/mac80211/patches/subsys/356-wifi-cfg80211-avoid-nontransmitted-BSS-list-corrupti.patch deleted file mode 100644 index db0e51edc2..0000000000 --- a/package/kernel/mac80211/patches/subsys/356-wifi-cfg80211-avoid-nontransmitted-BSS-list-corrupti.patch +++ /dev/null @@ -1,48 +0,0 @@ -From: Johannes Berg -Date: Sat, 1 Oct 2022 00:01:44 +0200 -Subject: [PATCH] wifi: cfg80211: avoid nontransmitted BSS list - corruption -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -commit bcca852027e5878aec911a347407ecc88d6fff7f upstream. - -If a non-transmitted BSS shares enough information (both -SSID and BSSID!) with another non-transmitted BSS of a -different AP, then we can find and update it, and then -try to add it to the non-transmitted BSS list. We do a -search for it on the transmitted BSS, but if it's not -there (but belongs to another transmitted BSS), the list -gets corrupted. - -Since this is an erroneous situation, simply fail the -list insertion in this case and free the non-transmitted -BSS. - -This fixes CVE-2022-42721. - -Reported-by: Sönke Huster -Tested-by: Sönke Huster -Fixes: 0b8fb8235be8 ("cfg80211: Parsing of Multiple BSSID information in scanning") -Signed-off-by: Johannes Berg ---- - ---- a/net/wireless/scan.c -+++ b/net/wireless/scan.c -@@ -425,6 +425,15 @@ cfg80211_add_nontrans_list(struct cfg802 - - rcu_read_unlock(); - -+ /* -+ * This is a bit weird - it's not on the list, but already on another -+ * one! The only way that could happen is if there's some BSSID/SSID -+ * shared by multiple APs in their multi-BSSID profiles, potentially -+ * with hidden SSID mixed in ... ignore it. -+ */ -+ if (!list_empty(&nontrans_bss->nontrans_list)) -+ return -EINVAL; -+ - /* add to the list */ - list_add_tail(&nontrans_bss->nontrans_list, &trans_bss->nontrans_list); - return 0; diff --git a/package/kernel/mac80211/patches/subsys/357-wifi-mac80211_hwsim-avoid-mac80211-warning-on-bad-ra.patch b/package/kernel/mac80211/patches/subsys/357-wifi-mac80211_hwsim-avoid-mac80211-warning-on-bad-ra.patch deleted file mode 100644 index ed834ff296..0000000000 --- a/package/kernel/mac80211/patches/subsys/357-wifi-mac80211_hwsim-avoid-mac80211-warning-on-bad-ra.patch +++ /dev/null @@ -1,31 +0,0 @@ -From: Johannes Berg -Date: Wed, 5 Oct 2022 15:10:09 +0200 -Subject: [PATCH] wifi: mac80211_hwsim: avoid mac80211 warning on bad - rate -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -commit 1833b6f46d7e2830251a063935ab464256defe22 upstream. - -If the tool on the other side (e.g. wmediumd) gets confused -about the rate, we hit a warning in mac80211. Silence that -by effectively duplicating the check here and dropping the -frame silently (in mac80211 it's dropped with the warning). - -Reported-by: Sönke Huster -Tested-by: Sönke Huster -Signed-off-by: Johannes Berg ---- - ---- a/drivers/net/wireless/mac80211_hwsim.c -+++ b/drivers/net/wireless/mac80211_hwsim.c -@@ -3760,6 +3760,8 @@ static int hwsim_cloned_frame_received_n - - rx_status.band = channel->band; - rx_status.rate_idx = nla_get_u32(info->attrs[HWSIM_ATTR_RX_RATE]); -+ if (rx_status.rate_idx >= data2->hw->wiphy->bands[rx_status.band]->n_bitrates) -+ goto out; - rx_status.signal = nla_get_u32(info->attrs[HWSIM_ATTR_SIGNAL]); - - hdr = (void *)skb->data; diff --git a/package/kernel/mac80211/patches/subsys/358-wifi-mac80211-fix-crash-in-beacon-protection-for-P2P.patch b/package/kernel/mac80211/patches/subsys/358-wifi-mac80211-fix-crash-in-beacon-protection-for-P2P.patch deleted file mode 100644 index 44b8729977..0000000000 --- a/package/kernel/mac80211/patches/subsys/358-wifi-mac80211-fix-crash-in-beacon-protection-for-P2P.patch +++ /dev/null @@ -1,52 +0,0 @@ -From: Johannes Berg -Date: Wed, 5 Oct 2022 21:24:10 +0200 -Subject: [PATCH] wifi: mac80211: fix crash in beacon protection for - P2P-device -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -commit b2d03cabe2b2e150ff5a381731ea0355459be09f upstream. - -If beacon protection is active but the beacon cannot be -decrypted or is otherwise malformed, we call the cfg80211 -API to report this to userspace, but that uses a netdev -pointer, which isn't present for P2P-Device. Fix this to -call it only conditionally to ensure cfg80211 won't crash -in the case of P2P-Device. - -This fixes CVE-2022-42722. - -Reported-by: Sönke Huster -Fixes: 9eaf183af741 ("mac80211: Report beacon protection failures to user space") -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/rx.c -+++ b/net/mac80211/rx.c -@@ -1986,10 +1986,11 @@ ieee80211_rx_h_decrypt(struct ieee80211_ - - if (mmie_keyidx < NUM_DEFAULT_KEYS + NUM_DEFAULT_MGMT_KEYS || - mmie_keyidx >= NUM_DEFAULT_KEYS + NUM_DEFAULT_MGMT_KEYS + -- NUM_DEFAULT_BEACON_KEYS) { -- cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, -- skb->data, -- skb->len); -+ NUM_DEFAULT_BEACON_KEYS) { -+ if (rx->sdata->dev) -+ cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, -+ skb->data, -+ skb->len); - return RX_DROP_MONITOR; /* unexpected BIP keyidx */ - } - -@@ -2137,7 +2138,8 @@ ieee80211_rx_h_decrypt(struct ieee80211_ - /* either the frame has been decrypted or will be dropped */ - status->flag |= RX_FLAG_DECRYPTED; - -- if (unlikely(ieee80211_is_beacon(fc) && result == RX_DROP_UNUSABLE)) -+ if (unlikely(ieee80211_is_beacon(fc) && result == RX_DROP_UNUSABLE && -+ rx->sdata->dev)) - cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, - skb->data, skb->len); - diff --git a/package/kernel/mac80211/patches/subsys/359-wifi-cfg80211-update-hidden-BSSes-to-avoid-WARN_ON.patch b/package/kernel/mac80211/patches/subsys/359-wifi-cfg80211-update-hidden-BSSes-to-avoid-WARN_ON.patch deleted file mode 100644 index c689fac854..0000000000 --- a/package/kernel/mac80211/patches/subsys/359-wifi-cfg80211-update-hidden-BSSes-to-avoid-WARN_ON.patch +++ /dev/null @@ -1,85 +0,0 @@ -From: Johannes Berg -Date: Wed, 5 Oct 2022 23:11:43 +0200 -Subject: [PATCH] wifi: cfg80211: update hidden BSSes to avoid WARN_ON -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -commit c90b93b5b782891ebfda49d4e5da36632fefd5d1 upstream. - -When updating beacon elements in a non-transmitted BSS, -also update the hidden sub-entries to the same beacon -elements, so that a future update through other paths -won't trigger a WARN_ON(). - -The warning is triggered because the beacon elements in -the hidden BSSes that are children of the BSS should -always be the same as in the parent. - -Reported-by: Sönke Huster -Tested-by: Sönke Huster -Fixes: 0b8fb8235be8 ("cfg80211: Parsing of Multiple BSSID information in scanning") -Signed-off-by: Johannes Berg ---- - ---- a/net/wireless/scan.c -+++ b/net/wireless/scan.c -@@ -1609,6 +1609,23 @@ struct cfg80211_non_tx_bss { - u8 bssid_index; - }; - -+static void cfg80211_update_hidden_bsses(struct cfg80211_internal_bss *known, -+ const struct cfg80211_bss_ies *new_ies, -+ const struct cfg80211_bss_ies *old_ies) -+{ -+ struct cfg80211_internal_bss *bss; -+ -+ /* Assign beacon IEs to all sub entries */ -+ list_for_each_entry(bss, &known->hidden_list, hidden_list) { -+ const struct cfg80211_bss_ies *ies; -+ -+ ies = rcu_access_pointer(bss->pub.beacon_ies); -+ WARN_ON(ies != old_ies); -+ -+ rcu_assign_pointer(bss->pub.beacon_ies, new_ies); -+ } -+} -+ - static bool - cfg80211_update_known_bss(struct cfg80211_registered_device *rdev, - struct cfg80211_internal_bss *known, -@@ -1632,7 +1649,6 @@ cfg80211_update_known_bss(struct cfg8021 - kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); - } else if (rcu_access_pointer(new->pub.beacon_ies)) { - const struct cfg80211_bss_ies *old; -- struct cfg80211_internal_bss *bss; - - if (known->pub.hidden_beacon_bss && - !list_empty(&known->hidden_list)) { -@@ -1660,16 +1676,7 @@ cfg80211_update_known_bss(struct cfg8021 - if (old == rcu_access_pointer(known->pub.ies)) - rcu_assign_pointer(known->pub.ies, new->pub.beacon_ies); - -- /* Assign beacon IEs to all sub entries */ -- list_for_each_entry(bss, &known->hidden_list, hidden_list) { -- const struct cfg80211_bss_ies *ies; -- -- ies = rcu_access_pointer(bss->pub.beacon_ies); -- WARN_ON(ies != old); -- -- rcu_assign_pointer(bss->pub.beacon_ies, -- new->pub.beacon_ies); -- } -+ cfg80211_update_hidden_bsses(known, new->pub.beacon_ies, old); - - if (old) - kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); -@@ -2319,6 +2326,8 @@ cfg80211_update_notlisted_nontrans(struc - } else { - old = rcu_access_pointer(nontrans_bss->beacon_ies); - rcu_assign_pointer(nontrans_bss->beacon_ies, new_ies); -+ cfg80211_update_hidden_bsses(bss_from_pub(nontrans_bss), -+ new_ies, old); - rcu_assign_pointer(nontrans_bss->ies, new_ies); - if (old) - kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); diff --git a/package/kernel/mac80211/patches/subsys/360-mac80211-fix-a-memory-leak-where-sta_info-is-not-fre.patch b/package/kernel/mac80211/patches/subsys/360-mac80211-fix-a-memory-leak-where-sta_info-is-not-fre.patch deleted file mode 100644 index ff3cb7be53..0000000000 --- a/package/kernel/mac80211/patches/subsys/360-mac80211-fix-a-memory-leak-where-sta_info-is-not-fre.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 4db561ae4a90c2d0e15996634567559e292dc9e5 Mon Sep 17 00:00:00 2001 -From: Ahmed Zaki -Date: Sat, 2 Oct 2021 08:53:29 -0600 -Subject: [PATCH] mac80211: fix a memory leak where sta_info is not freed - -commit 8f9dcc29566626f683843ccac6113a12208315ca upstream. - -The following is from a system that went OOM due to a memory leak: - -wlan0: Allocated STA 74:83:c2:64:0b:87 -wlan0: Allocated STA 74:83:c2:64:0b:87 -wlan0: IBSS finish 74:83:c2:64:0b:87 (---from ieee80211_ibss_add_sta) -wlan0: Adding new IBSS station 74:83:c2:64:0b:87 -wlan0: moving STA 74:83:c2:64:0b:87 to state 2 -wlan0: moving STA 74:83:c2:64:0b:87 to state 3 -wlan0: Inserted STA 74:83:c2:64:0b:87 -wlan0: IBSS finish 74:83:c2:64:0b:87 (---from ieee80211_ibss_work) -wlan0: Adding new IBSS station 74:83:c2:64:0b:87 -wlan0: moving STA 74:83:c2:64:0b:87 to state 2 -wlan0: moving STA 74:83:c2:64:0b:87 to state 3 -. -. -wlan0: expiring inactive not authorized STA 74:83:c2:64:0b:87 -wlan0: moving STA 74:83:c2:64:0b:87 to state 2 -wlan0: moving STA 74:83:c2:64:0b:87 to state 1 -wlan0: Removed STA 74:83:c2:64:0b:87 -wlan0: Destroyed STA 74:83:c2:64:0b:87 - -The ieee80211_ibss_finish_sta() is called twice on the same STA from 2 -different locations. On the second attempt, the allocated STA is not -destroyed creating a kernel memory leak. - -This is happening because sta_info_insert_finish() does not call -sta_info_free() the second time when the STA already exists (returns --EEXIST). Note that the caller sta_info_insert_rcu() assumes STA is -destroyed upon errors. - -Same fix is applied to -ENOMEM. - -Signed-off-by: Ahmed Zaki -Link: https://lore.kernel.org/r/20211002145329.3125293-1-anzaki@gmail.com -[change the error path label to use the existing code] -Signed-off-by: Johannes Berg -Signed-off-by: Viacheslav Sablin -Signed-off-by: Greg Kroah-Hartman ---- - net/mac80211/sta_info.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/net/mac80211/sta_info.c -+++ b/net/mac80211/sta_info.c -@@ -646,13 +646,13 @@ static int sta_info_insert_finish(struct - /* check if STA exists already */ - if (sta_info_get_bss(sdata, sta->sta.addr)) { - err = -EEXIST; -- goto out_err; -+ goto out_cleanup; - } - - sinfo = kzalloc(sizeof(struct station_info), GFP_KERNEL); - if (!sinfo) { - err = -ENOMEM; -- goto out_err; -+ goto out_cleanup; - } - - local->num_sta++; -@@ -708,8 +708,8 @@ static int sta_info_insert_finish(struct - out_drop_sta: - local->num_sta--; - synchronize_net(); -+ out_cleanup: - cleanup_single_sta(sta); -- out_err: - mutex_unlock(&local->sta_mtx); - kfree(sinfo); - rcu_read_lock(); diff --git a/package/kernel/mac80211/patches/subsys/361-wifi-mac80211-Don-t-finalize-CSA-in-IBSS-mode-if-sta.patch b/package/kernel/mac80211/patches/subsys/361-wifi-mac80211-Don-t-finalize-CSA-in-IBSS-mode-if-sta.patch deleted file mode 100644 index dd3e934c00..0000000000 --- a/package/kernel/mac80211/patches/subsys/361-wifi-mac80211-Don-t-finalize-CSA-in-IBSS-mode-if-sta.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 552ba102a6898630a7d16887f29e606d6fabe508 Mon Sep 17 00:00:00 2001 -From: Siddh Raman Pant -Date: Sun, 14 Aug 2022 20:45:12 +0530 -Subject: [PATCH] wifi: mac80211: Don't finalize CSA in IBSS mode if state is - disconnected - -commit 15bc8966b6d3a5b9bfe4c9facfa02f2b69b1e5f0 upstream. - -When we are not connected to a channel, sending channel "switch" -announcement doesn't make any sense. - -The BSS list is empty in that case. This causes the for loop in -cfg80211_get_bss() to be bypassed, so the function returns NULL -(check line 1424 of net/wireless/scan.c), causing the WARN_ON() -in ieee80211_ibss_csa_beacon() to get triggered (check line 500 -of net/mac80211/ibss.c), which was consequently reported on the -syzkaller dashboard. - -Thus, check if we have an existing connection before generating -the CSA beacon in ieee80211_ibss_finish_csa(). - -Cc: stable@vger.kernel.org -Fixes: cd7760e62c2a ("mac80211: add support for CSA in IBSS mode") -Link: https://syzkaller.appspot.com/bug?id=05603ef4ae8926761b678d2939a3b2ad28ab9ca6 -Reported-by: syzbot+b6c9fe29aefe68e4ad34@syzkaller.appspotmail.com -Signed-off-by: Siddh Raman Pant -Tested-by: syzbot+b6c9fe29aefe68e4ad34@syzkaller.appspotmail.com -Link: https://lore.kernel.org/r/20220814151512.9985-1-code@siddh.me -Signed-off-by: Johannes Berg -Signed-off-by: Greg Kroah-Hartman ---- - net/mac80211/ibss.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/net/mac80211/ibss.c -+++ b/net/mac80211/ibss.c -@@ -534,6 +534,10 @@ int ieee80211_ibss_finish_csa(struct iee - - sdata_assert_lock(sdata); - -+ /* When not connected/joined, sending CSA doesn't make sense. */ -+ if (ifibss->state != IEEE80211_IBSS_MLME_JOINED) -+ return -ENOLINK; -+ - /* update cfg80211 bss information with the new channel */ - if (!is_zero_ether_addr(ifibss->bssid)) { - cbss = cfg80211_get_bss(sdata->local->hw.wiphy, diff --git a/package/kernel/mac80211/patches/subsys/362-wifi-mac80211-Fix-UAF-in-ieee80211_scan_rx.patch b/package/kernel/mac80211/patches/subsys/362-wifi-mac80211-Fix-UAF-in-ieee80211_scan_rx.patch deleted file mode 100644 index 50b6b94fbf..0000000000 --- a/package/kernel/mac80211/patches/subsys/362-wifi-mac80211-Fix-UAF-in-ieee80211_scan_rx.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 5d20c6f932f2758078d0454729129c894fe353e7 Mon Sep 17 00:00:00 2001 -From: Siddh Raman Pant -Date: Sat, 20 Aug 2022 01:33:40 +0530 -Subject: [PATCH] wifi: mac80211: Fix UAF in ieee80211_scan_rx() - -commit 60deb9f10eec5c6a20252ed36238b55d8b614a2c upstream. - -ieee80211_scan_rx() tries to access scan_req->flags after a -null check, but a UAF is observed when the scan is completed -and __ieee80211_scan_completed() executes, which then calls -cfg80211_scan_done() leading to the freeing of scan_req. - -Since scan_req is rcu_dereference()'d, prevent the racing in -__ieee80211_scan_completed() by ensuring that from mac80211's -POV it is no longer accessed from an RCU read critical section -before we call cfg80211_scan_done(). - -Cc: stable@vger.kernel.org -Link: https://syzkaller.appspot.com/bug?extid=f9acff9bf08a845f225d -Reported-by: syzbot+f9acff9bf08a845f225d@syzkaller.appspotmail.com -Suggested-by: Johannes Berg -Signed-off-by: Siddh Raman Pant -Link: https://lore.kernel.org/r/20220819200340.34826-1-code@siddh.me -Signed-off-by: Johannes Berg -Signed-off-by: Greg Kroah-Hartman ---- - net/mac80211/scan.c | 11 +++++++---- - 1 file changed, 7 insertions(+), 4 deletions(-) - ---- a/net/mac80211/scan.c -+++ b/net/mac80211/scan.c -@@ -465,16 +465,19 @@ static void __ieee80211_scan_completed(s - scan_req = rcu_dereference_protected(local->scan_req, - lockdep_is_held(&local->mtx)); - -- if (scan_req != local->int_scan_req) { -- local->scan_info.aborted = aborted; -- cfg80211_scan_done(scan_req, &local->scan_info); -- } - RCU_INIT_POINTER(local->scan_req, NULL); - RCU_INIT_POINTER(local->scan_sdata, NULL); - - local->scanning = 0; - local->scan_chandef.chan = NULL; - -+ synchronize_rcu(); -+ -+ if (scan_req != local->int_scan_req) { -+ local->scan_info.aborted = aborted; -+ cfg80211_scan_done(scan_req, &local->scan_info); -+ } -+ - /* Set power back to normal operating levels. */ - ieee80211_hw_config(local, 0); - diff --git a/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch b/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch index 50c24a7746..0e83e9bd8e 100644 --- a/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch +++ b/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch @@ -87,7 +87,7 @@ CFG80211_TESTMODE_DUMP(ieee80211_testmode_dump) --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h -@@ -1448,6 +1448,7 @@ struct ieee80211_local { +@@ -1447,6 +1447,7 @@ struct ieee80211_local { int dynamic_ps_forced_timeout; int user_power_level; /* in dBm, for all interfaces */ diff --git a/package/kernel/mt76/patches/100-aggregation-definitions.patch b/package/kernel/mt76/patches/100-aggregation-definitions.patch new file mode 100644 index 0000000000..a88d57133f --- /dev/null +++ b/package/kernel/mt76/patches/100-aggregation-definitions.patch @@ -0,0 +1,13 @@ +--- a/mt7915/init.c ++++ b/mt7915/init.c +@@ -327,8 +327,8 @@ mt7915_init_wiphy(struct ieee80211_hw *h + struct mt7915_dev *dev = phy->dev; + + hw->queues = 4; +- hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF; +- hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF; ++ hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; ++ hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; + hw->netdev_features = NETIF_F_RXCSUM; + + hw->radiotap_timestamp.units_pos = From a14544d1bb6f6840dd64c600c58d938b193c09e3 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 22 Oct 2022 16:15:16 +0200 Subject: [PATCH 65/80] toolchain: gcc: Remove gcc 8.x support This compiler is old and not used by OpenWrt for some time now. Signed-off-by: Hauke Mehrtens --- toolchain/gcc/Config.in | 3 - toolchain/gcc/Config.version | 5 - toolchain/gcc/common.mk | 4 - .../patches-8.x/002-case_insensitive.patch | 24 --- .../gcc/patches-8.x/010-documentation.patch | 35 ---- .../patches-8.x/110-Fix-MIPS-PR-84790.patch | 20 --- .../gcc/patches-8.x/230-musl_libssp.patch | 13 -- .../300-mips_Os_cpu_rtx_cost_model.patch | 21 --- .../800-arm_v5te_no_ldrd_strd.patch | 11 -- .../810-arm-softfloat-libgcc.patch | 33 ---- .../gcc/patches-8.x/820-libgcc_pic.patch | 44 ----- .../840-armv4_pass_fix-v4bx_to_ld.patch | 28 --- .../patches-8.x/850-use_shared_libgcc.patch | 54 ------ .../patches-8.x/851-libgcc_no_compat.patch | 22 --- .../patches-8.x/870-ppc_no_crtsavres.patch | 11 -- .../gcc/patches-8.x/881-no_tm_section.patch | 11 -- .../gcc/patches-8.x/900-bad-mips16-crt.patch | 9 - .../gcc/patches-8.x/910-mbsd_multi.patch | 146 --------------- .../920-specs_nonfatal_getenv.patch | 22 --- .../930-fix-mips-noexecstack.patch | 111 ------------ ...ibffi-fix-MIPS-softfloat-build-issue.patch | 168 ------------------ ...mpilation-when-making-cross-compiler.patch | 67 ------- 22 files changed, 862 deletions(-) delete mode 100644 toolchain/gcc/patches-8.x/002-case_insensitive.patch delete mode 100644 toolchain/gcc/patches-8.x/010-documentation.patch delete mode 100644 toolchain/gcc/patches-8.x/110-Fix-MIPS-PR-84790.patch delete mode 100644 toolchain/gcc/patches-8.x/230-musl_libssp.patch delete mode 100644 toolchain/gcc/patches-8.x/300-mips_Os_cpu_rtx_cost_model.patch delete mode 100644 toolchain/gcc/patches-8.x/800-arm_v5te_no_ldrd_strd.patch delete mode 100644 toolchain/gcc/patches-8.x/810-arm-softfloat-libgcc.patch delete mode 100644 toolchain/gcc/patches-8.x/820-libgcc_pic.patch delete mode 100644 toolchain/gcc/patches-8.x/840-armv4_pass_fix-v4bx_to_ld.patch delete mode 100644 toolchain/gcc/patches-8.x/850-use_shared_libgcc.patch delete mode 100644 toolchain/gcc/patches-8.x/851-libgcc_no_compat.patch delete mode 100644 toolchain/gcc/patches-8.x/870-ppc_no_crtsavres.patch delete mode 100644 toolchain/gcc/patches-8.x/881-no_tm_section.patch delete mode 100644 toolchain/gcc/patches-8.x/900-bad-mips16-crt.patch delete mode 100644 toolchain/gcc/patches-8.x/910-mbsd_multi.patch delete mode 100644 toolchain/gcc/patches-8.x/920-specs_nonfatal_getenv.patch delete mode 100644 toolchain/gcc/patches-8.x/930-fix-mips-noexecstack.patch delete mode 100644 toolchain/gcc/patches-8.x/931-libffi-fix-MIPS-softfloat-build-issue.patch delete mode 100644 toolchain/gcc/patches-8.x/960-gotools-fix-compilation-when-making-cross-compiler.patch diff --git a/toolchain/gcc/Config.in b/toolchain/gcc/Config.in index f725ad5785..df8f2b16cd 100644 --- a/toolchain/gcc/Config.in +++ b/toolchain/gcc/Config.in @@ -6,9 +6,6 @@ choice help Select the version of gcc you wish to use. - config GCC_USE_VERSION_8 - bool "gcc 8.x" - config GCC_USE_VERSION_10 bool "gcc 10.x" diff --git a/toolchain/gcc/Config.version b/toolchain/gcc/Config.version index a909979cf6..52f241996d 100644 --- a/toolchain/gcc/Config.version +++ b/toolchain/gcc/Config.version @@ -1,7 +1,3 @@ -config GCC_VERSION_8 - default y if GCC_USE_VERSION_8 - bool - config GCC_VERSION_10 default y if GCC_USE_VERSION_10 bool @@ -12,7 +8,6 @@ config GCC_VERSION_12 config GCC_VERSION string - default "8.4.0" if GCC_VERSION_8 default "10.3.0" if GCC_VERSION_10 default "12.2.0" if GCC_VERSION_12 default "11.3.0" diff --git a/toolchain/gcc/common.mk b/toolchain/gcc/common.mk index 83884dd54c..360580987e 100644 --- a/toolchain/gcc/common.mk +++ b/toolchain/gcc/common.mk @@ -29,10 +29,6 @@ GCC_DIR:=$(PKG_NAME)-$(PKG_VERSION) PKG_SOURCE_URL:=@GNU/gcc/gcc-$(PKG_VERSION) PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz -ifeq ($(PKG_VERSION),8.4.0) - PKG_HASH:=e30a6e52d10e1f27ed55104ad233c30bd1e99cfb5ff98ab022dc941edd1b2dd4 -endif - ifeq ($(PKG_VERSION),10.3.0) PKG_HASH:=64f404c1a650f27fc33da242e1f2df54952e3963a49e06e73f6940f3223ac344 endif diff --git a/toolchain/gcc/patches-8.x/002-case_insensitive.patch b/toolchain/gcc/patches-8.x/002-case_insensitive.patch deleted file mode 100644 index 3442076d7d..0000000000 --- a/toolchain/gcc/patches-8.x/002-case_insensitive.patch +++ /dev/null @@ -1,24 +0,0 @@ -commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e -Author: Felix Fietkau -Date: Sun Oct 19 21:45:51 2014 +0000 - - gcc: do not assume that the Mac OS X filesystem is case insensitive - - Signed-off-by: Felix Fietkau - - SVN-Revision: 42973 - ---- a/include/filenames.h -+++ b/include/filenames.h -@@ -43,11 +43,6 @@ extern "C" { - # define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c) - # define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f) - #else /* not DOSish */ --# if defined(__APPLE__) --# ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM --# define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1 --# endif --# endif /* __APPLE__ */ - # define HAS_DRIVE_SPEC(f) (0) - # define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c) - # define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f) diff --git a/toolchain/gcc/patches-8.x/010-documentation.patch b/toolchain/gcc/patches-8.x/010-documentation.patch deleted file mode 100644 index c7e3d4ad55..0000000000 --- a/toolchain/gcc/patches-8.x/010-documentation.patch +++ /dev/null @@ -1,35 +0,0 @@ -commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2 -Author: Luka Perkov -Date: Tue Feb 26 16:16:33 2013 +0000 - - gcc: don't build documentation - - This closes #13039. - - Signed-off-by: Luka Perkov - - SVN-Revision: 35807 - ---- a/gcc/Makefile.in -+++ b/gcc/Makefile.in -@@ -3204,18 +3204,10 @@ doc/gcc.info: $(TEXI_GCC_FILES) - doc/gccint.info: $(TEXI_GCCINT_FILES) - doc/cppinternals.info: $(TEXI_CPPINT_FILES) - --doc/%.info: %.texi -- if [ x$(BUILD_INFO) = xinfo ]; then \ -- $(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \ -- -I $(gcc_docdir)/include -o $@ $<; \ -- fi -+doc/%.info: - - # Duplicate entry to handle renaming of gccinstall.info --doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES) -- if [ x$(BUILD_INFO) = xinfo ]; then \ -- $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \ -- -I $(gcc_docdir)/include -o $@ $<; \ -- fi -+doc/gccinstall.info: - - doc/cpp.dvi: $(TEXI_CPP_FILES) - doc/gcc.dvi: $(TEXI_GCC_FILES) diff --git a/toolchain/gcc/patches-8.x/110-Fix-MIPS-PR-84790.patch b/toolchain/gcc/patches-8.x/110-Fix-MIPS-PR-84790.patch deleted file mode 100644 index b89eca2faf..0000000000 --- a/toolchain/gcc/patches-8.x/110-Fix-MIPS-PR-84790.patch +++ /dev/null @@ -1,20 +0,0 @@ -Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790. -MIPS16 functions have a static assembler prologue which clobbers -registers v0 and v1. Add these register clobbers to function call -instructions. - ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -3102,6 +3102,12 @@ mips_emit_call_insn (rtx pattern, rtx or - emit_insn (gen_update_got_version ()); - } - -+ if (TARGET_MIPS16 && TARGET_USE_GOT) -+ { -+ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP); -+ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode)); -+ } -+ - if (TARGET_MIPS16 - && TARGET_EXPLICIT_RELOCS - && TARGET_CALL_CLOBBERED_GP) diff --git a/toolchain/gcc/patches-8.x/230-musl_libssp.patch b/toolchain/gcc/patches-8.x/230-musl_libssp.patch deleted file mode 100644 index b3ab79cafb..0000000000 --- a/toolchain/gcc/patches-8.x/230-musl_libssp.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/gcc/gcc.c -+++ b/gcc/gcc.c -@@ -868,7 +868,9 @@ proper position among the other output f - #endif - - #ifndef LINK_SSP_SPEC --#ifdef TARGET_LIBC_PROVIDES_SSP -+#if DEFAULT_LIBC == LIBC_MUSL -+#define LINK_SSP_SPEC "-lssp_nonshared" -+#elif defined(TARGET_LIBC_PROVIDES_SSP) - #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ - "|fstack-protector-strong|fstack-protector-explicit:}" - #else diff --git a/toolchain/gcc/patches-8.x/300-mips_Os_cpu_rtx_cost_model.patch b/toolchain/gcc/patches-8.x/300-mips_Os_cpu_rtx_cost_model.patch deleted file mode 100644 index 2e2c609e48..0000000000 --- a/toolchain/gcc/patches-8.x/300-mips_Os_cpu_rtx_cost_model.patch +++ /dev/null @@ -1,21 +0,0 @@ -commit ecf7671b769fe96f7b5134be442089f8bdba55d2 -Author: Felix Fietkau -Date: Thu Aug 4 20:29:45 2016 +0200 - -gcc: add a patch to generate better code with Os on mips - -Also happens to reduce compressed code size a bit - -Signed-off-by: Felix Fietkau - ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -19847,7 +19847,7 @@ mips_option_override (void) - flag_pcc_struct_return = 0; - - /* Decide which rtx_costs structure to use. */ -- if (optimize_size) -+ if (0 && optimize_size) - mips_cost = &mips_rtx_cost_optimize_size; - else - mips_cost = &mips_rtx_cost_data[mips_tune]; diff --git a/toolchain/gcc/patches-8.x/800-arm_v5te_no_ldrd_strd.patch b/toolchain/gcc/patches-8.x/800-arm_v5te_no_ldrd_strd.patch deleted file mode 100644 index 172295f28b..0000000000 --- a/toolchain/gcc/patches-8.x/800-arm_v5te_no_ldrd_strd.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/gcc/config/arm/arm.h -+++ b/gcc/config/arm/arm.h -@@ -155,7 +155,7 @@ extern tree arm_fp16_type_node; - /* Thumb-1 only. */ - #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) - --#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ -+#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \ - && !TARGET_THUMB1) - - #define TARGET_CRC32 (arm_arch_crc) diff --git a/toolchain/gcc/patches-8.x/810-arm-softfloat-libgcc.patch b/toolchain/gcc/patches-8.x/810-arm-softfloat-libgcc.patch deleted file mode 100644 index 5c9d86aead..0000000000 --- a/toolchain/gcc/patches-8.x/810-arm-softfloat-libgcc.patch +++ /dev/null @@ -1,33 +0,0 @@ -commit 8570c4be394cff7282f332f97da2ff569a927ddb -Author: Imre Kaloz -Date: Wed Feb 2 20:06:12 2011 +0000 - - fixup arm soft-float symbols - - SVN-Revision: 25325 - ---- a/libgcc/config/arm/t-linux -+++ b/libgcc/config/arm/t-linux -@@ -1,6 +1,10 @@ - LIB1ASMSRC = arm/lib1funcs.S - LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \ -- _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 -+ _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \ -+ _arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \ -+ _arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \ -+ _arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \ -+ _arm_fixsfsi _arm_fixunssfsi - - # Just for these, we omit the frame pointer since it makes such a big - # difference. ---- a/gcc/config/arm/linux-elf.h -+++ b/gcc/config/arm/linux-elf.h -@@ -58,8 +58,6 @@ - %{shared:-lc} \ - %{!shared:%{profile:-lc_p}%{!profile:-lc}}" - --#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc" -- - #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" - - #define LINUX_TARGET_LINK_SPEC "%{h*} \ diff --git a/toolchain/gcc/patches-8.x/820-libgcc_pic.patch b/toolchain/gcc/patches-8.x/820-libgcc_pic.patch deleted file mode 100644 index 1a9678d480..0000000000 --- a/toolchain/gcc/patches-8.x/820-libgcc_pic.patch +++ /dev/null @@ -1,44 +0,0 @@ -commit c96312958c0621e72c9b32da5bc224ffe2161384 -Author: Felix Fietkau -Date: Mon Oct 19 23:26:09 2009 +0000 - - gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow) - - SVN-Revision: 18086 - ---- a/libgcc/Makefile.in -+++ b/libgcc/Makefile.in -@@ -923,11 +923,12 @@ $(libgcov-driver-objects): %$(objext): $ - - # Static libraries. - libgcc.a: $(libgcc-objects) -+libgcc_pic.a: $(libgcc-s-objects) - libgcov.a: $(libgcov-objects) - libunwind.a: $(libunwind-objects) - libgcc_eh.a: $(libgcc-eh-objects) - --libgcc.a libgcov.a libunwind.a libgcc_eh.a: -+libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a: - -rm -f $@ - - objects="$(objects)"; \ -@@ -948,7 +949,7 @@ all: libunwind.a - endif - - ifeq ($(enable_shared),yes) --all: libgcc_eh.a libgcc_s$(SHLIB_EXT) -+all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT) - ifneq ($(LIBUNWIND),) - all: libunwind$(SHLIB_EXT) - libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT) -@@ -1154,6 +1155,10 @@ install-shared: - chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a - $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a - -+ $(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/ -+ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a -+ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a -+ - $(subst @multilib_dir@,$(MULTIDIR),$(subst \ - @shlib_base_name@,libgcc_s,$(subst \ - @shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL)))) diff --git a/toolchain/gcc/patches-8.x/840-armv4_pass_fix-v4bx_to_ld.patch b/toolchain/gcc/patches-8.x/840-armv4_pass_fix-v4bx_to_ld.patch deleted file mode 100644 index b9c9b161ad..0000000000 --- a/toolchain/gcc/patches-8.x/840-armv4_pass_fix-v4bx_to_ld.patch +++ /dev/null @@ -1,28 +0,0 @@ -commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc -Author: Imre Kaloz -Date: Wed Feb 2 19:34:36 2011 +0000 - - add armv4 fixup patches - - SVN-Revision: 25322 - - ---- a/gcc/config/arm/linux-eabi.h -+++ b/gcc/config/arm/linux-eabi.h -@@ -88,10 +88,15 @@ - #define MUSL_DYNAMIC_LINKER \ - "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}.so.1" - -+/* For armv4 we pass --fix-v4bx to linker to support EABI */ -+#undef TARGET_FIX_V4BX_SPEC -+#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\ -+ "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}" -+ - /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to - use the GNU/Linux version, not the generic BPABI version. */ - #undef LINK_SPEC --#define LINK_SPEC EABI_LINK_SPEC \ -+#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC \ - LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \ - LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) - diff --git a/toolchain/gcc/patches-8.x/850-use_shared_libgcc.patch b/toolchain/gcc/patches-8.x/850-use_shared_libgcc.patch deleted file mode 100644 index f619f0e6a1..0000000000 --- a/toolchain/gcc/patches-8.x/850-use_shared_libgcc.patch +++ /dev/null @@ -1,54 +0,0 @@ -commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd -Author: Felix Fietkau -Date: Sun Feb 12 20:25:47 2012 +0000 - - gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary - - SVN-Revision: 30486 ---- a/gcc/config/arm/linux-eabi.h -+++ b/gcc/config/arm/linux-eabi.h -@@ -126,10 +126,6 @@ - "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} " \ - LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC) - --/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we -- do not use -lfloat. */ --#undef LIBGCC_SPEC -- - /* Clear the instruction cache from `beg' to `end'. This is - implemented in lib1funcs.S, so ensure an error if this definition - is used. */ ---- a/gcc/config/linux.h -+++ b/gcc/config/linux.h -@@ -53,6 +53,10 @@ see the files COPYING3 and COPYING.RUNTI - builtin_assert ("system=posix"); \ - } while (0) - -+#ifndef LIBGCC_SPEC -+#define LIBGCC_SPEC "%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}" -+#endif -+ - /* Determine which dynamic linker to use depending on whether GLIBC or - uClibc or Bionic or musl is the default C library and whether - -muclibc or -mglibc or -mbionic or -mmusl has been passed to change ---- a/libgcc/mkmap-symver.awk -+++ b/libgcc/mkmap-symver.awk -@@ -136,5 +136,5 @@ function output(lib) { - else if (inherit[lib]) - printf("} %s;\n", inherit[lib]); - else -- printf ("\n local:\n\t*;\n};\n"); -+ printf ("\n\t*;\n};\n"); - } ---- a/gcc/config/rs6000/linux.h -+++ b/gcc/config/rs6000/linux.h -@@ -60,6 +60,9 @@ - #undef CPP_OS_DEFAULT_SPEC - #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)" - -+#undef LIBGCC_SPEC -+#define LIBGCC_SPEC "%{!static:%{!static-libgcc:-lgcc_s}} -lgcc" -+ - #undef LINK_SHLIB_SPEC - #define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}} \ - %{static-pie:-static -pie --no-dynamic-linker -z text}" diff --git a/toolchain/gcc/patches-8.x/851-libgcc_no_compat.patch b/toolchain/gcc/patches-8.x/851-libgcc_no_compat.patch deleted file mode 100644 index d710e40717..0000000000 --- a/toolchain/gcc/patches-8.x/851-libgcc_no_compat.patch +++ /dev/null @@ -1,22 +0,0 @@ -commit 64661de100da1ec1061ef3e5e400285dce115e6b -Author: Felix Fietkau -Date: Sun May 10 13:16:35 2015 +0000 - - gcc: add some size optimization patches - - Signed-off-by: Felix Fietkau - - SVN-Revision: 45664 - ---- a/libgcc/config/t-libunwind -+++ b/libgcc/config/t-libunwind -@@ -2,8 +2,7 @@ - - HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER - --LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \ -- $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c -+LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c - LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c - - # Override the default value from t-slibgcc-elf-ver and mention -lunwind diff --git a/toolchain/gcc/patches-8.x/870-ppc_no_crtsavres.patch b/toolchain/gcc/patches-8.x/870-ppc_no_crtsavres.patch deleted file mode 100644 index 51d11c3d85..0000000000 --- a/toolchain/gcc/patches-8.x/870-ppc_no_crtsavres.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/gcc/config/rs6000/rs6000.c -+++ b/gcc/config/rs6000/rs6000.c -@@ -24780,7 +24780,7 @@ rs6000_savres_strategy (rs6000_stack_t * - /* Define cutoff for using out-of-line functions to save registers. */ - if (DEFAULT_ABI == ABI_V4 || TARGET_ELF) - { -- if (!optimize_size) -+ if (1) - { - strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS; - strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; diff --git a/toolchain/gcc/patches-8.x/881-no_tm_section.patch b/toolchain/gcc/patches-8.x/881-no_tm_section.patch deleted file mode 100644 index fab5db3be5..0000000000 --- a/toolchain/gcc/patches-8.x/881-no_tm_section.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/libgcc/crtstuff.c -+++ b/libgcc/crtstuff.c -@@ -152,7 +152,7 @@ call_ ## FUNC (void) \ - #endif - - #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF) --# define USE_TM_CLONE_REGISTRY 1 -+# define USE_TM_CLONE_REGISTRY 0 - #endif - - /* We do not want to add the weak attribute to the declarations of these diff --git a/toolchain/gcc/patches-8.x/900-bad-mips16-crt.patch b/toolchain/gcc/patches-8.x/900-bad-mips16-crt.patch deleted file mode 100644 index dd6e9dc889..0000000000 --- a/toolchain/gcc/patches-8.x/900-bad-mips16-crt.patch +++ /dev/null @@ -1,9 +0,0 @@ ---- a/libgcc/config/mips/t-mips16 -+++ b/libgcc/config/mips/t-mips16 -@@ -43,3 +43,6 @@ SYNC_CFLAGS = -mno-mips16 - - # Version these symbols if building libgcc.so. - SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver -+ -+CRTSTUFF_T_CFLAGS += -mno-mips16 -+CRTSTUFF_T_CFLAGS_S += -mno-mips16 diff --git a/toolchain/gcc/patches-8.x/910-mbsd_multi.patch b/toolchain/gcc/patches-8.x/910-mbsd_multi.patch deleted file mode 100644 index c566ea35e5..0000000000 --- a/toolchain/gcc/patches-8.x/910-mbsd_multi.patch +++ /dev/null @@ -1,146 +0,0 @@ -commit 99368862e44740ff4fd33760893f04e14f9dbdf1 -Author: Felix Fietkau -Date: Tue Jul 31 00:52:27 2007 +0000 - - Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly - - SVN-Revision: 8256 - - This patch brings over a feature from MirBSD: - * -fhonour-copts - If this option is not given, it's warned (depending - on environment variables). This is to catch errors - of misbuilt packages which override CFLAGS themselves. - - This patch was authored by Thorsten Glaser - with copyright assignment to the FSF in effect. - ---- a/gcc/c-family/c-opts.c -+++ b/gcc/c-family/c-opts.c -@@ -107,6 +107,9 @@ static dump_flags_t original_dump_flags; - /* Whether any standard preincluded header has been preincluded. */ - static bool done_preinclude; - -+/* Check if a port honours COPTS. */ -+static int honour_copts = 0; -+ - static void handle_OPT_d (const char *); - static void set_std_cxx98 (int); - static void set_std_cxx11 (int); -@@ -459,6 +462,12 @@ c_common_handle_option (size_t scode, co - flag_no_builtin = !value; - break; - -+ case OPT_fhonour_copts: -+ if (c_language == clk_c) { -+ honour_copts++; -+ } -+ break; -+ - case OPT_fconstant_string_class_: - constant_string_class_name = arg; - break; -@@ -1125,6 +1134,47 @@ c_common_init (void) - return false; - } - -+ if (c_language == clk_c) { -+ char *ev = getenv ("GCC_HONOUR_COPTS"); -+ int evv; -+ if (ev == NULL) -+ evv = -1; -+ else if ((*ev == '0') || (*ev == '\0')) -+ evv = 0; -+ else if (*ev == '1') -+ evv = 1; -+ else if (*ev == '2') -+ evv = 2; -+ else if (*ev == 's') -+ evv = -1; -+ else { -+ warning (0, "unknown GCC_HONOUR_COPTS value, assuming 1"); -+ evv = 1; /* maybe depend this on something like MIRBSD_NATIVE? */ -+ } -+ if (evv == 1) { -+ if (honour_copts == 0) { -+ error ("someone does not honour COPTS at all in lenient mode"); -+ return false; -+ } else if (honour_copts != 1) { -+ warning (0, "someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ } -+ } else if (evv == 2) { -+ if (honour_copts == 0) { -+ error ("someone does not honour COPTS at all in strict mode"); -+ return false; -+ } else if (honour_copts != 1) { -+ error ("someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ return false; -+ } -+ } else if (evv == 0) { -+ if (honour_copts != 1) -+ inform (UNKNOWN_LOCATION, "someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ } -+ } -+ - return true; - } - ---- a/gcc/c-family/c.opt -+++ b/gcc/c-family/c.opt -@@ -1469,6 +1469,9 @@ C++ ObjC++ Optimization Alias(fexception - fhonor-std - C++ ObjC++ Ignore Warn(switch %qs is no longer supported) - -+fhonour-copts -+C ObjC C++ ObjC++ RejectNegative -+ - fhosted - C ObjC - Assume normal C execution environment. ---- a/gcc/common.opt -+++ b/gcc/common.opt -@@ -1551,6 +1551,9 @@ fguess-branch-probability - Common Report Var(flag_guess_branch_prob) Optimization - Enable guessing of branch probabilities. - -+fhonour-copts -+Common RejectNegative -+ - ; Nonzero means ignore `#ident' directives. 0 means handle them. - ; Generate position-independent code for executables if possible - ; On SVR4 targets, it also controls whether or not to emit a ---- a/gcc/opts.c -+++ b/gcc/opts.c -@@ -2073,6 +2073,9 @@ common_handle_option (struct gcc_options - opts, opts_set, loc, dc); - break; - -+ case OPT_fhonour_copts: -+ break; -+ - case OPT_Wlarger_than_: - opts->x_larger_than_size = value; - opts->x_warn_larger_than = value != -1; ---- a/gcc/doc/invoke.texi -+++ b/gcc/doc/invoke.texi -@@ -7013,6 +7013,17 @@ This option is only supported for C and - @option{-Wall} and by @option{-Wpedantic}, which can be disabled with - @option{-Wno-pointer-sign}. - -+@item -fhonour-copts -+@opindex fhonour-copts -+If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not -+given at least once, and warn if it is given more than once. -+If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not -+given exactly once. -+If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option -+is not given exactly once. -+The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}. -+This flag and environment variable only affect the C language. -+ - @item -Wstack-protector - @opindex Wstack-protector - @opindex Wno-stack-protector diff --git a/toolchain/gcc/patches-8.x/920-specs_nonfatal_getenv.patch b/toolchain/gcc/patches-8.x/920-specs_nonfatal_getenv.patch deleted file mode 100644 index c3836e63af..0000000000 --- a/toolchain/gcc/patches-8.x/920-specs_nonfatal_getenv.patch +++ /dev/null @@ -1,22 +0,0 @@ -Author: Jo-Philipp Wich -Date: Sat Apr 21 03:02:39 2012 +0000 - - gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset - - SVN-Revision: 31390 - ---- a/gcc/gcc.c -+++ b/gcc/gcc.c -@@ -9347,8 +9347,10 @@ getenv_spec_function (int argc, const ch - value = varname; - - if (!value) -- fatal_error (input_location, -- "environment variable %qs not defined", varname); -+ { -+ warning (input_location, "environment variable %qs not defined", varname); -+ value = ""; -+ } - - /* We have to escape every character of the environment variable so - they are not interpreted as active spec characters. A diff --git a/toolchain/gcc/patches-8.x/930-fix-mips-noexecstack.patch b/toolchain/gcc/patches-8.x/930-fix-mips-noexecstack.patch deleted file mode 100644 index ed8ada22a1..0000000000 --- a/toolchain/gcc/patches-8.x/930-fix-mips-noexecstack.patch +++ /dev/null @@ -1,111 +0,0 @@ -From da45b3fde60095756f5f6030f6012c23a3d34429 Mon Sep 17 00:00:00 2001 -From: Andrew McDonnell -Date: Fri, 3 Oct 2014 19:09:00 +0930 -Subject: Add .note.GNU-stack section - -See http://lists.busybox.net/pipermail/uclibc/2014-October/048671.html -Below copied from https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02430.html - -Re: [Patch, MIPS] Add .note.GNU-stack section - - From: Steve Ellcey - -On Wed, 2014-09-10 at 10:15 -0700, Eric Christopher wrote: -> -> -> On Wed, Sep 10, 2014 at 9:27 AM, wrote: - -> This works except you did not update the assembly files in -> libgcc or glibc. We (Cavium) have the same patch in our tree -> for a few released versions. - -> Mind just checking yours in then Andrew? - -> Thanks! -> -eric - -I talked to Andrew about what files he changed in GCC and created and -tested this new patch. Andrew also mentioned changing some assembly -files in glibc but I don't see any use of '.section .note.GNU-stack' in -any assembly files in glibc (for any platform) so I wasn't planning on -creating a glibc to add them to mips glibc assembly language files. - -OK to check in this patch? - -Steve Ellcey -sellcey@mips.com - - - -2014-09-26 Steve Ellcey ---- - gcc/config/mips/mips.c | 3 +++ - libgcc/config/mips/crti.S | 4 ++++ - libgcc/config/mips/crtn.S | 3 +++ - libgcc/config/mips/mips16.S | 4 ++++ - libgcc/config/mips/vr4120-div.S | 4 ++++ - 5 files changed, 18 insertions(+) - ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -22640,6 +22640,9 @@ mips_starting_frame_offset (void) - #undef TARGET_STARTING_FRAME_OFFSET - #define TARGET_STARTING_FRAME_OFFSET mips_starting_frame_offset - -+#undef TARGET_ASM_FILE_END -+#define TARGET_ASM_FILE_END file_end_indicate_exec_stack -+ - struct gcc_target targetm = TARGET_INITIALIZER; - - #include "gt-mips.h" ---- a/libgcc/config/mips/crti.S -+++ b/libgcc/config/mips/crti.S -@@ -21,6 +21,10 @@ a copy of the GCC Runtime Library Except - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - -+ -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ - /* 4 slots for argument spill area. 1 for cpreturn, 1 for stack. - Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */ - ---- a/libgcc/config/mips/crtn.S -+++ b/libgcc/config/mips/crtn.S -@@ -21,6 +21,9 @@ a copy of the GCC Runtime Library Except - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ - /* 4 slots for argument spill area. 1 for cpreturn, 1 for stack. - Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */ - ---- a/libgcc/config/mips/mips16.S -+++ b/libgcc/config/mips/mips16.S -@@ -48,6 +48,10 @@ see the files COPYING3 and COPYING.RUNTI - values using the soft-float calling convention, but do the actual - operation using the hard floating point instructions. */ - -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ .previous -+ - #if defined _MIPS_SIM && (_MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIO64) - - /* This file contains 32-bit assembly code. */ ---- a/libgcc/config/mips/vr4120-div.S -+++ b/libgcc/config/mips/vr4120-div.S -@@ -26,6 +26,10 @@ see the files COPYING3 and COPYING.RUNTI - -mfix-vr4120. div and ddiv do not give the correct result when one - of the operands is negative. */ - -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ .previous -+ - .set nomips16 - - #define DIV \ diff --git a/toolchain/gcc/patches-8.x/931-libffi-fix-MIPS-softfloat-build-issue.patch b/toolchain/gcc/patches-8.x/931-libffi-fix-MIPS-softfloat-build-issue.patch deleted file mode 100644 index fb4cb1533a..0000000000 --- a/toolchain/gcc/patches-8.x/931-libffi-fix-MIPS-softfloat-build-issue.patch +++ /dev/null @@ -1,168 +0,0 @@ -From c0c62fa4256f805389f16ebfc4a60cf789129b50 Mon Sep 17 00:00:00 2001 -From: BangLang Huang -Date: Wed, 9 Nov 2016 10:36:49 +0800 -Subject: [PATCH] libffi: fix MIPS softfloat build issue - -Backported from github.com/libffi/libffi#272 - -Signed-off-by: BangLang Huang -Signed-off-by: Yousong Zhou ---- - libffi/src/mips/n32.S | 17 +++++++++++++++++ - libffi/src/mips/o32.S | 17 +++++++++++++++++ - 2 files changed, 34 insertions(+) - ---- a/libffi/src/mips/n32.S -+++ b/libffi/src/mips/n32.S -@@ -107,6 +107,16 @@ loadregs: - - REG_L t6, 3*FFI_SIZEOF_ARG($fp) # load the flags word into t6. - -+#ifdef __mips_soft_float -+ REG_L a0, 0*FFI_SIZEOF_ARG(t9) -+ REG_L a1, 1*FFI_SIZEOF_ARG(t9) -+ REG_L a2, 2*FFI_SIZEOF_ARG(t9) -+ REG_L a3, 3*FFI_SIZEOF_ARG(t9) -+ REG_L a4, 4*FFI_SIZEOF_ARG(t9) -+ REG_L a5, 5*FFI_SIZEOF_ARG(t9) -+ REG_L a6, 6*FFI_SIZEOF_ARG(t9) -+ REG_L a7, 7*FFI_SIZEOF_ARG(t9) -+#else - and t4, t6, ((1< -Date: Fri, 4 May 2018 18:20:53 +0800 -Subject: [PATCH] gotools: fix compilation when making cross compiler - -libgo is "the runtime support library for the Go programming language. -This library is intended for use with the Go frontend." - -gccgo will link target files with libgo.so which depends on libgcc_s.so.1, but -the linker will complain that it cannot find it. That's because shared libgcc -is not present in the install directory yet. libgo.so was made without problem -because gcc will emit -lgcc_s when compiled with -shared option. When gotools -were being made, it was supplied with -static-libgcc thus no link option was -provided. Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec -for linking with libgo.so - -- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation -- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html - -When 3-pass GCC compilation is used, shared libgcc runtime libraries will be -available after gcc pass2 completed and will meet the gotools link requirement -at gcc pass3 ---- - gotools/Makefile.am | 4 +++- - gotools/Makefile.in | 4 +++- - 2 files changed, 6 insertions(+), 2 deletions(-) - ---- a/gotools/Makefile.am -+++ b/gotools/Makefile.am -@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd} - STAMP = echo timestamp > - - libgodir = ../$(target_noncanonical)/libgo -+libgccdir = ../$(target_noncanonical)/libgcc - LIBGODEP = $(libgodir)/libgo.la - - LIBGOTOOL = $(libgodir)/libgotool.a -@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET) - GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS) - - AM_GOCFLAGS = -I $(libgodir) --AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs -+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \ -+ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s - GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@ - - libgosrcdir = $(srcdir)/../libgo/go ---- a/gotools/Makefile.in -+++ b/gotools/Makefile.in -@@ -263,6 +263,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd - PWD_COMMAND = $${PWDCMD-pwd} - STAMP = echo timestamp > - libgodir = ../$(target_noncanonical)/libgo -+libgccdir = ../$(target_noncanonical)/libgcc - LIBGODEP = $(libgodir)/libgo.la - LIBGOTOOL = $(libgodir)/libgotool.a - @NATIVE_FALSE@GOCOMPILER = $(GOC) -@@ -271,7 +272,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a - @NATIVE_TRUE@GOCOMPILER = $(GOC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) - GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS) - AM_GOCFLAGS = -I $(libgodir) --AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs -+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \ -+ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s - GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@ - libgosrcdir = $(srcdir)/../libgo/go - cmdsrcdir = $(libgosrcdir)/cmd From 9db3caa7490907d05a7378e48a69ee01a4461e99 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 22 Oct 2022 16:16:55 +0200 Subject: [PATCH 66/80] toolchain: gcc: Remove gcc 10.x support This compiler is old and was never used by default in OpenWrt. Signed-off-by: Hauke Mehrtens --- toolchain/gcc/Config.in | 3 - toolchain/gcc/Config.version | 5 - toolchain/gcc/common.mk | 4 - .../patches-10.x/002-case_insensitive.patch | 24 --- .../gcc/patches-10.x/010-documentation.patch | 35 ---- .../patches-10.x/110-Fix-MIPS-PR-84790.patch | 20 --- .../gcc/patches-10.x/230-musl_libssp.patch | 13 -- .../300-mips_Os_cpu_rtx_cost_model.patch | 21 --- .../810-arm-softfloat-libgcc.patch | 33 ---- .../gcc/patches-10.x/820-libgcc_pic.patch | 44 ----- .../840-armv4_pass_fix-v4bx_to_ld.patch | 28 --- .../patches-10.x/850-use_shared_libgcc.patch | 54 ------ .../patches-10.x/851-libgcc_no_compat.patch | 22 --- .../patches-10.x/870-ppc_no_crtsavres.patch | 11 -- .../gcc/patches-10.x/881-no_tm_section.patch | 11 -- .../gcc/patches-10.x/900-bad-mips16-crt.patch | 9 - .../gcc/patches-10.x/910-mbsd_multi.patch | 146 --------------- .../920-specs_nonfatal_getenv.patch | 22 --- .../930-fix-mips-noexecstack.patch | 111 ------------ ...ibffi-fix-MIPS-softfloat-build-issue.patch | 168 ------------------ ...mpilation-when-making-cross-compiler.patch | 67 ------- 21 files changed, 851 deletions(-) delete mode 100644 toolchain/gcc/patches-10.x/002-case_insensitive.patch delete mode 100644 toolchain/gcc/patches-10.x/010-documentation.patch delete mode 100644 toolchain/gcc/patches-10.x/110-Fix-MIPS-PR-84790.patch delete mode 100644 toolchain/gcc/patches-10.x/230-musl_libssp.patch delete mode 100644 toolchain/gcc/patches-10.x/300-mips_Os_cpu_rtx_cost_model.patch delete mode 100644 toolchain/gcc/patches-10.x/810-arm-softfloat-libgcc.patch delete mode 100644 toolchain/gcc/patches-10.x/820-libgcc_pic.patch delete mode 100644 toolchain/gcc/patches-10.x/840-armv4_pass_fix-v4bx_to_ld.patch delete mode 100644 toolchain/gcc/patches-10.x/850-use_shared_libgcc.patch delete mode 100644 toolchain/gcc/patches-10.x/851-libgcc_no_compat.patch delete mode 100644 toolchain/gcc/patches-10.x/870-ppc_no_crtsavres.patch delete mode 100644 toolchain/gcc/patches-10.x/881-no_tm_section.patch delete mode 100644 toolchain/gcc/patches-10.x/900-bad-mips16-crt.patch delete mode 100644 toolchain/gcc/patches-10.x/910-mbsd_multi.patch delete mode 100644 toolchain/gcc/patches-10.x/920-specs_nonfatal_getenv.patch delete mode 100644 toolchain/gcc/patches-10.x/930-fix-mips-noexecstack.patch delete mode 100644 toolchain/gcc/patches-10.x/931-libffi-fix-MIPS-softfloat-build-issue.patch delete mode 100644 toolchain/gcc/patches-10.x/960-gotools-fix-compilation-when-making-cross-compiler.patch diff --git a/toolchain/gcc/Config.in b/toolchain/gcc/Config.in index df8f2b16cd..3c074c99b2 100644 --- a/toolchain/gcc/Config.in +++ b/toolchain/gcc/Config.in @@ -6,9 +6,6 @@ choice help Select the version of gcc you wish to use. - config GCC_USE_VERSION_10 - bool "gcc 10.x" - config GCC_USE_VERSION_11 bool "gcc 11.x" diff --git a/toolchain/gcc/Config.version b/toolchain/gcc/Config.version index 52f241996d..65f272746b 100644 --- a/toolchain/gcc/Config.version +++ b/toolchain/gcc/Config.version @@ -1,13 +1,8 @@ -config GCC_VERSION_10 - default y if GCC_USE_VERSION_10 - bool - config GCC_VERSION_12 default y if GCC_USE_VERSION_12 bool config GCC_VERSION string - default "10.3.0" if GCC_VERSION_10 default "12.2.0" if GCC_VERSION_12 default "11.3.0" diff --git a/toolchain/gcc/common.mk b/toolchain/gcc/common.mk index 360580987e..6661b0aa38 100644 --- a/toolchain/gcc/common.mk +++ b/toolchain/gcc/common.mk @@ -29,10 +29,6 @@ GCC_DIR:=$(PKG_NAME)-$(PKG_VERSION) PKG_SOURCE_URL:=@GNU/gcc/gcc-$(PKG_VERSION) PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz -ifeq ($(PKG_VERSION),10.3.0) - PKG_HASH:=64f404c1a650f27fc33da242e1f2df54952e3963a49e06e73f6940f3223ac344 -endif - ifeq ($(PKG_VERSION),11.3.0) PKG_HASH:=b47cf2818691f5b1e21df2bb38c795fac2cfbd640ede2d0a5e1c89e338a3ac39 endif diff --git a/toolchain/gcc/patches-10.x/002-case_insensitive.patch b/toolchain/gcc/patches-10.x/002-case_insensitive.patch deleted file mode 100644 index 409497e5a3..0000000000 --- a/toolchain/gcc/patches-10.x/002-case_insensitive.patch +++ /dev/null @@ -1,24 +0,0 @@ -commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e -Author: Felix Fietkau -Date: Sun Oct 19 21:45:51 2014 +0000 - - gcc: do not assume that the Mac OS X filesystem is case insensitive - - Signed-off-by: Felix Fietkau - - SVN-Revision: 42973 - ---- a/include/filenames.h -+++ b/include/filenames.h -@@ -44,11 +44,6 @@ extern "C" { - # define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c) - # define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f) - #else /* not DOSish */ --# if defined(__APPLE__) --# ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM --# define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1 --# endif --# endif /* __APPLE__ */ - # define HAS_DRIVE_SPEC(f) (0) - # define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c) - # define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f) diff --git a/toolchain/gcc/patches-10.x/010-documentation.patch b/toolchain/gcc/patches-10.x/010-documentation.patch deleted file mode 100644 index 85990e5acc..0000000000 --- a/toolchain/gcc/patches-10.x/010-documentation.patch +++ /dev/null @@ -1,35 +0,0 @@ -commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2 -Author: Luka Perkov -Date: Tue Feb 26 16:16:33 2013 +0000 - - gcc: don't build documentation - - This closes #13039. - - Signed-off-by: Luka Perkov - - SVN-Revision: 35807 - ---- a/gcc/Makefile.in -+++ b/gcc/Makefile.in -@@ -3285,18 +3285,10 @@ doc/gcc.info: $(TEXI_GCC_FILES) - doc/gccint.info: $(TEXI_GCCINT_FILES) - doc/cppinternals.info: $(TEXI_CPPINT_FILES) - --doc/%.info: %.texi -- if [ x$(BUILD_INFO) = xinfo ]; then \ -- $(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \ -- -I $(gcc_docdir)/include -o $@ $<; \ -- fi -+doc/%.info: - - # Duplicate entry to handle renaming of gccinstall.info --doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES) -- if [ x$(BUILD_INFO) = xinfo ]; then \ -- $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \ -- -I $(gcc_docdir)/include -o $@ $<; \ -- fi -+doc/gccinstall.info: - - doc/cpp.dvi: $(TEXI_CPP_FILES) - doc/gcc.dvi: $(TEXI_GCC_FILES) diff --git a/toolchain/gcc/patches-10.x/110-Fix-MIPS-PR-84790.patch b/toolchain/gcc/patches-10.x/110-Fix-MIPS-PR-84790.patch deleted file mode 100644 index 82ac013d30..0000000000 --- a/toolchain/gcc/patches-10.x/110-Fix-MIPS-PR-84790.patch +++ /dev/null @@ -1,20 +0,0 @@ -Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790. -MIPS16 functions have a static assembler prologue which clobbers -registers v0 and v1. Add these register clobbers to function call -instructions. - ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -3132,6 +3132,12 @@ mips_emit_call_insn (rtx pattern, rtx or - emit_insn (gen_update_got_version ()); - } - -+ if (TARGET_MIPS16 && TARGET_USE_GOT) -+ { -+ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP); -+ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode)); -+ } -+ - if (TARGET_MIPS16 - && TARGET_EXPLICIT_RELOCS - && TARGET_CALL_CLOBBERED_GP) diff --git a/toolchain/gcc/patches-10.x/230-musl_libssp.patch b/toolchain/gcc/patches-10.x/230-musl_libssp.patch deleted file mode 100644 index 63f37662f4..0000000000 --- a/toolchain/gcc/patches-10.x/230-musl_libssp.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/gcc/gcc.c -+++ b/gcc/gcc.c -@@ -875,7 +875,9 @@ proper position among the other output f - #endif - - #ifndef LINK_SSP_SPEC --#ifdef TARGET_LIBC_PROVIDES_SSP -+#if DEFAULT_LIBC == LIBC_MUSL -+#define LINK_SSP_SPEC "-lssp_nonshared" -+#elif defined(TARGET_LIBC_PROVIDES_SSP) - #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ - "|fstack-protector-strong|fstack-protector-explicit:}" - #else diff --git a/toolchain/gcc/patches-10.x/300-mips_Os_cpu_rtx_cost_model.patch b/toolchain/gcc/patches-10.x/300-mips_Os_cpu_rtx_cost_model.patch deleted file mode 100644 index 8c4a5fce19..0000000000 --- a/toolchain/gcc/patches-10.x/300-mips_Os_cpu_rtx_cost_model.patch +++ /dev/null @@ -1,21 +0,0 @@ -commit ecf7671b769fe96f7b5134be442089f8bdba55d2 -Author: Felix Fietkau -Date: Thu Aug 4 20:29:45 2016 +0200 - -gcc: add a patch to generate better code with Os on mips - -Also happens to reduce compressed code size a bit - -Signed-off-by: Felix Fietkau - ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -20041,7 +20041,7 @@ mips_option_override (void) - flag_pcc_struct_return = 0; - - /* Decide which rtx_costs structure to use. */ -- if (optimize_size) -+ if (0 && optimize_size) - mips_cost = &mips_rtx_cost_optimize_size; - else - mips_cost = &mips_rtx_cost_data[mips_tune]; diff --git a/toolchain/gcc/patches-10.x/810-arm-softfloat-libgcc.patch b/toolchain/gcc/patches-10.x/810-arm-softfloat-libgcc.patch deleted file mode 100644 index 5c9d86aead..0000000000 --- a/toolchain/gcc/patches-10.x/810-arm-softfloat-libgcc.patch +++ /dev/null @@ -1,33 +0,0 @@ -commit 8570c4be394cff7282f332f97da2ff569a927ddb -Author: Imre Kaloz -Date: Wed Feb 2 20:06:12 2011 +0000 - - fixup arm soft-float symbols - - SVN-Revision: 25325 - ---- a/libgcc/config/arm/t-linux -+++ b/libgcc/config/arm/t-linux -@@ -1,6 +1,10 @@ - LIB1ASMSRC = arm/lib1funcs.S - LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \ -- _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 -+ _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \ -+ _arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \ -+ _arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \ -+ _arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \ -+ _arm_fixsfsi _arm_fixunssfsi - - # Just for these, we omit the frame pointer since it makes such a big - # difference. ---- a/gcc/config/arm/linux-elf.h -+++ b/gcc/config/arm/linux-elf.h -@@ -58,8 +58,6 @@ - %{shared:-lc} \ - %{!shared:%{profile:-lc_p}%{!profile:-lc}}" - --#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc" -- - #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" - - #define LINUX_TARGET_LINK_SPEC "%{h*} \ diff --git a/toolchain/gcc/patches-10.x/820-libgcc_pic.patch b/toolchain/gcc/patches-10.x/820-libgcc_pic.patch deleted file mode 100644 index ddd6cf8732..0000000000 --- a/toolchain/gcc/patches-10.x/820-libgcc_pic.patch +++ /dev/null @@ -1,44 +0,0 @@ -commit c96312958c0621e72c9b32da5bc224ffe2161384 -Author: Felix Fietkau -Date: Mon Oct 19 23:26:09 2009 +0000 - - gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow) - - SVN-Revision: 18086 - ---- a/libgcc/Makefile.in -+++ b/libgcc/Makefile.in -@@ -929,11 +929,12 @@ $(libgcov-driver-objects): %$(objext): $ - - # Static libraries. - libgcc.a: $(libgcc-objects) -+libgcc_pic.a: $(libgcc-s-objects) - libgcov.a: $(libgcov-objects) - libunwind.a: $(libunwind-objects) - libgcc_eh.a: $(libgcc-eh-objects) - --libgcc.a libgcov.a libunwind.a libgcc_eh.a: -+libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a: - -rm -f $@ - - objects="$(objects)"; \ -@@ -957,7 +958,7 @@ all: libunwind.a - endif - - ifeq ($(enable_shared),yes) --all: libgcc_eh.a libgcc_s$(SHLIB_EXT) -+all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT) - ifneq ($(LIBUNWIND),) - all: libunwind$(SHLIB_EXT) - libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT) -@@ -1163,6 +1164,10 @@ install-shared: - chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a - $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a - -+ $(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/ -+ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a -+ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a -+ - $(subst @multilib_dir@,$(MULTIDIR),$(subst \ - @shlib_base_name@,libgcc_s,$(subst \ - @shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL)))) diff --git a/toolchain/gcc/patches-10.x/840-armv4_pass_fix-v4bx_to_ld.patch b/toolchain/gcc/patches-10.x/840-armv4_pass_fix-v4bx_to_ld.patch deleted file mode 100644 index e3cb616c4e..0000000000 --- a/toolchain/gcc/patches-10.x/840-armv4_pass_fix-v4bx_to_ld.patch +++ /dev/null @@ -1,28 +0,0 @@ -commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc -Author: Imre Kaloz -Date: Wed Feb 2 19:34:36 2011 +0000 - - add armv4 fixup patches - - SVN-Revision: 25322 - - ---- a/gcc/config/arm/linux-eabi.h -+++ b/gcc/config/arm/linux-eabi.h -@@ -91,10 +91,15 @@ - #define MUSL_DYNAMIC_LINKER \ - "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1" - -+/* For armv4 we pass --fix-v4bx to linker to support EABI */ -+#undef TARGET_FIX_V4BX_SPEC -+#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\ -+ "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}" -+ - /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to - use the GNU/Linux version, not the generic BPABI version. */ - #undef LINK_SPEC --#define LINK_SPEC EABI_LINK_SPEC \ -+#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC \ - LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \ - LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) - diff --git a/toolchain/gcc/patches-10.x/850-use_shared_libgcc.patch b/toolchain/gcc/patches-10.x/850-use_shared_libgcc.patch deleted file mode 100644 index 8b17f1374f..0000000000 --- a/toolchain/gcc/patches-10.x/850-use_shared_libgcc.patch +++ /dev/null @@ -1,54 +0,0 @@ -commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd -Author: Felix Fietkau -Date: Sun Feb 12 20:25:47 2012 +0000 - - gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary - - SVN-Revision: 30486 ---- a/gcc/config/arm/linux-eabi.h -+++ b/gcc/config/arm/linux-eabi.h -@@ -132,10 +132,6 @@ - "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} " \ - LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC) - --/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we -- do not use -lfloat. */ --#undef LIBGCC_SPEC -- - /* Clear the instruction cache from `beg' to `end'. This is - implemented in lib1funcs.S, so ensure an error if this definition - is used. */ ---- a/gcc/config/linux.h -+++ b/gcc/config/linux.h -@@ -66,6 +66,10 @@ see the files COPYING3 and COPYING.RUNTI - builtin_version ("CRuntime_Musl"); \ - } while (0) - -+#ifndef LIBGCC_SPEC -+#define LIBGCC_SPEC "%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}" -+#endif -+ - /* Determine which dynamic linker to use depending on whether GLIBC or - uClibc or Bionic or musl is the default C library and whether - -muclibc or -mglibc or -mbionic or -mmusl has been passed to change ---- a/libgcc/mkmap-symver.awk -+++ b/libgcc/mkmap-symver.awk -@@ -136,5 +136,5 @@ function output(lib) { - else if (inherit[lib]) - printf("} %s;\n", inherit[lib]); - else -- printf ("\n local:\n\t*;\n};\n"); -+ printf ("\n\t*;\n};\n"); - } ---- a/gcc/config/rs6000/linux.h -+++ b/gcc/config/rs6000/linux.h -@@ -62,6 +62,9 @@ - #undef CPP_OS_DEFAULT_SPEC - #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)" - -+#undef LIBGCC_SPEC -+#define LIBGCC_SPEC "%{!static:%{!static-libgcc:-lgcc_s}} -lgcc" -+ - #undef LINK_SHLIB_SPEC - #define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}} \ - %{static-pie:-static -pie --no-dynamic-linker -z text}" diff --git a/toolchain/gcc/patches-10.x/851-libgcc_no_compat.patch b/toolchain/gcc/patches-10.x/851-libgcc_no_compat.patch deleted file mode 100644 index d710e40717..0000000000 --- a/toolchain/gcc/patches-10.x/851-libgcc_no_compat.patch +++ /dev/null @@ -1,22 +0,0 @@ -commit 64661de100da1ec1061ef3e5e400285dce115e6b -Author: Felix Fietkau -Date: Sun May 10 13:16:35 2015 +0000 - - gcc: add some size optimization patches - - Signed-off-by: Felix Fietkau - - SVN-Revision: 45664 - ---- a/libgcc/config/t-libunwind -+++ b/libgcc/config/t-libunwind -@@ -2,8 +2,7 @@ - - HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER - --LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \ -- $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c -+LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c - LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c - - # Override the default value from t-slibgcc-elf-ver and mention -lunwind diff --git a/toolchain/gcc/patches-10.x/870-ppc_no_crtsavres.patch b/toolchain/gcc/patches-10.x/870-ppc_no_crtsavres.patch deleted file mode 100644 index bc182f0cec..0000000000 --- a/toolchain/gcc/patches-10.x/870-ppc_no_crtsavres.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/gcc/config/rs6000/rs6000-logue.c -+++ b/gcc/config/rs6000/rs6000-logue.c -@@ -348,7 +348,7 @@ rs6000_savres_strategy (rs6000_stack_t * - /* Define cutoff for using out-of-line functions to save registers. */ - if (DEFAULT_ABI == ABI_V4 || TARGET_ELF) - { -- if (!optimize_size) -+ if (1) - { - strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS; - strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; diff --git a/toolchain/gcc/patches-10.x/881-no_tm_section.patch b/toolchain/gcc/patches-10.x/881-no_tm_section.patch deleted file mode 100644 index 2029910fd0..0000000000 --- a/toolchain/gcc/patches-10.x/881-no_tm_section.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/libgcc/crtstuff.c -+++ b/libgcc/crtstuff.c -@@ -152,7 +152,7 @@ call_ ## FUNC (void) \ - #endif - - #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF) --# define USE_TM_CLONE_REGISTRY 1 -+# define USE_TM_CLONE_REGISTRY 0 - #elif !defined(USE_TM_CLONE_REGISTRY) - # define USE_TM_CLONE_REGISTRY 0 - #endif diff --git a/toolchain/gcc/patches-10.x/900-bad-mips16-crt.patch b/toolchain/gcc/patches-10.x/900-bad-mips16-crt.patch deleted file mode 100644 index dd6e9dc889..0000000000 --- a/toolchain/gcc/patches-10.x/900-bad-mips16-crt.patch +++ /dev/null @@ -1,9 +0,0 @@ ---- a/libgcc/config/mips/t-mips16 -+++ b/libgcc/config/mips/t-mips16 -@@ -43,3 +43,6 @@ SYNC_CFLAGS = -mno-mips16 - - # Version these symbols if building libgcc.so. - SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver -+ -+CRTSTUFF_T_CFLAGS += -mno-mips16 -+CRTSTUFF_T_CFLAGS_S += -mno-mips16 diff --git a/toolchain/gcc/patches-10.x/910-mbsd_multi.patch b/toolchain/gcc/patches-10.x/910-mbsd_multi.patch deleted file mode 100644 index 3ed6238310..0000000000 --- a/toolchain/gcc/patches-10.x/910-mbsd_multi.patch +++ /dev/null @@ -1,146 +0,0 @@ -commit 99368862e44740ff4fd33760893f04e14f9dbdf1 -Author: Felix Fietkau -Date: Tue Jul 31 00:52:27 2007 +0000 - - Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly - - SVN-Revision: 8256 - - This patch brings over a feature from MirBSD: - * -fhonour-copts - If this option is not given, it's warned (depending - on environment variables). This is to catch errors - of misbuilt packages which override CFLAGS themselves. - - This patch was authored by Thorsten Glaser - with copyright assignment to the FSF in effect. - ---- a/gcc/c-family/c-opts.c -+++ b/gcc/c-family/c-opts.c -@@ -107,6 +107,9 @@ static dump_flags_t original_dump_flags; - /* Whether any standard preincluded header has been preincluded. */ - static bool done_preinclude; - -+/* Check if a port honours COPTS. */ -+static int honour_copts = 0; -+ - static void handle_OPT_d (const char *); - static void set_std_cxx98 (int); - static void set_std_cxx11 (int); -@@ -455,6 +458,12 @@ c_common_handle_option (size_t scode, co - flag_no_builtin = !value; - break; - -+ case OPT_fhonour_copts: -+ if (c_language == clk_c) { -+ honour_copts++; -+ } -+ break; -+ - case OPT_fconstant_string_class_: - constant_string_class_name = arg; - break; -@@ -1168,6 +1177,47 @@ c_common_init (void) - return false; - } - -+ if (c_language == clk_c) { -+ char *ev = getenv ("GCC_HONOUR_COPTS"); -+ int evv; -+ if (ev == NULL) -+ evv = -1; -+ else if ((*ev == '0') || (*ev == '\0')) -+ evv = 0; -+ else if (*ev == '1') -+ evv = 1; -+ else if (*ev == '2') -+ evv = 2; -+ else if (*ev == 's') -+ evv = -1; -+ else { -+ warning (0, "unknown GCC_HONOUR_COPTS value, assuming 1"); -+ evv = 1; /* maybe depend this on something like MIRBSD_NATIVE? */ -+ } -+ if (evv == 1) { -+ if (honour_copts == 0) { -+ error ("someone does not honour COPTS at all in lenient mode"); -+ return false; -+ } else if (honour_copts != 1) { -+ warning (0, "someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ } -+ } else if (evv == 2) { -+ if (honour_copts == 0) { -+ error ("someone does not honour COPTS at all in strict mode"); -+ return false; -+ } else if (honour_copts != 1) { -+ error ("someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ return false; -+ } -+ } else if (evv == 0) { -+ if (honour_copts != 1) -+ inform (UNKNOWN_LOCATION, "someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ } -+ } -+ - return true; - } - ---- a/gcc/c-family/c.opt -+++ b/gcc/c-family/c.opt -@@ -1590,6 +1590,9 @@ C++ ObjC++ Optimization Alias(fexception - fhonor-std - C++ ObjC++ WarnRemoved - -+fhonour-copts -+C ObjC C++ ObjC++ RejectNegative -+ - fhosted - C ObjC - Assume normal C execution environment. ---- a/gcc/common.opt -+++ b/gcc/common.opt -@@ -1660,6 +1660,9 @@ fguess-branch-probability - Common Report Var(flag_guess_branch_prob) Optimization - Enable guessing of branch probabilities. - -+fhonour-copts -+Common RejectNegative -+ - ; Nonzero means ignore `#ident' directives. 0 means handle them. - ; Generate position-independent code for executables if possible - ; On SVR4 targets, it also controls whether or not to emit a ---- a/gcc/doc/invoke.texi -+++ b/gcc/doc/invoke.texi -@@ -8171,6 +8171,17 @@ This option is only supported for C and - @option{-Wall} and by @option{-Wpedantic}, which can be disabled with - @option{-Wno-pointer-sign}. - -+@item -fhonour-copts -+@opindex fhonour-copts -+If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not -+given at least once, and warn if it is given more than once. -+If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not -+given exactly once. -+If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option -+is not given exactly once. -+The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}. -+This flag and environment variable only affect the C language. -+ - @item -Wstack-protector - @opindex Wstack-protector - @opindex Wno-stack-protector ---- a/gcc/opts.c -+++ b/gcc/opts.c -@@ -2318,6 +2318,9 @@ common_handle_option (struct gcc_options - /* Currently handled in a prescan. */ - break; - -+ case OPT_fhonour_copts: -+ break; -+ - case OPT_Werror: - dc->warning_as_error_requested = value; - break; diff --git a/toolchain/gcc/patches-10.x/920-specs_nonfatal_getenv.patch b/toolchain/gcc/patches-10.x/920-specs_nonfatal_getenv.patch deleted file mode 100644 index 487b9e47cb..0000000000 --- a/toolchain/gcc/patches-10.x/920-specs_nonfatal_getenv.patch +++ /dev/null @@ -1,22 +0,0 @@ -Author: Jo-Philipp Wich -Date: Sat Apr 21 03:02:39 2012 +0000 - - gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset - - SVN-Revision: 31390 - ---- a/gcc/gcc.c -+++ b/gcc/gcc.c -@@ -9396,8 +9396,10 @@ getenv_spec_function (int argc, const ch - } - - if (!value) -- fatal_error (input_location, -- "environment variable %qs not defined", varname); -+ { -+ warning (input_location, "environment variable %qs not defined", varname); -+ value = ""; -+ } - - /* We have to escape every character of the environment variable so - they are not interpreted as active spec characters. A diff --git a/toolchain/gcc/patches-10.x/930-fix-mips-noexecstack.patch b/toolchain/gcc/patches-10.x/930-fix-mips-noexecstack.patch deleted file mode 100644 index e795acd1de..0000000000 --- a/toolchain/gcc/patches-10.x/930-fix-mips-noexecstack.patch +++ /dev/null @@ -1,111 +0,0 @@ -From da45b3fde60095756f5f6030f6012c23a3d34429 Mon Sep 17 00:00:00 2001 -From: Andrew McDonnell -Date: Fri, 3 Oct 2014 19:09:00 +0930 -Subject: Add .note.GNU-stack section - -See http://lists.busybox.net/pipermail/uclibc/2014-October/048671.html -Below copied from https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02430.html - -Re: [Patch, MIPS] Add .note.GNU-stack section - - From: Steve Ellcey - -On Wed, 2014-09-10 at 10:15 -0700, Eric Christopher wrote: -> -> -> On Wed, Sep 10, 2014 at 9:27 AM, wrote: - -> This works except you did not update the assembly files in -> libgcc or glibc. We (Cavium) have the same patch in our tree -> for a few released versions. - -> Mind just checking yours in then Andrew? - -> Thanks! -> -eric - -I talked to Andrew about what files he changed in GCC and created and -tested this new patch. Andrew also mentioned changing some assembly -files in glibc but I don't see any use of '.section .note.GNU-stack' in -any assembly files in glibc (for any platform) so I wasn't planning on -creating a glibc to add them to mips glibc assembly language files. - -OK to check in this patch? - -Steve Ellcey -sellcey@mips.com - - - -2014-09-26 Steve Ellcey ---- - gcc/config/mips/mips.c | 3 +++ - libgcc/config/mips/crti.S | 4 ++++ - libgcc/config/mips/crtn.S | 3 +++ - libgcc/config/mips/mips16.S | 4 ++++ - libgcc/config/mips/vr4120-div.S | 4 ++++ - 5 files changed, 18 insertions(+) - ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -22881,6 +22881,9 @@ mips_asm_file_end (void) - #define TARGET_ASM_FILE_END mips_asm_file_end - - -+#undef TARGET_ASM_FILE_END -+#define TARGET_ASM_FILE_END file_end_indicate_exec_stack -+ - struct gcc_target targetm = TARGET_INITIALIZER; - - #include "gt-mips.h" ---- a/libgcc/config/mips/crti.S -+++ b/libgcc/config/mips/crti.S -@@ -24,6 +24,10 @@ see the files COPYING3 and COPYING.RUNTI - /* An executable stack is *not* required for these functions. */ - #include "gnustack.h" - -+ -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ - /* 4 slots for argument spill area. 1 for cpreturn, 1 for stack. - Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */ - ---- a/libgcc/config/mips/crtn.S -+++ b/libgcc/config/mips/crtn.S -@@ -24,6 +24,9 @@ see the files COPYING3 and COPYING.RUNTI - /* An executable stack is *not* required for these functions. */ - #include "gnustack.h" - -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ - /* 4 slots for argument spill area. 1 for cpreturn, 1 for stack. - Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */ - ---- a/libgcc/config/mips/mips16.S -+++ b/libgcc/config/mips/mips16.S -@@ -51,6 +51,10 @@ see the files COPYING3 and COPYING.RUNTI - values using the soft-float calling convention, but do the actual - operation using the hard floating point instructions. */ - -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ .previous -+ - #if defined _MIPS_SIM && (_MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIO64) - - /* This file contains 32-bit assembly code. */ ---- a/libgcc/config/mips/vr4120-div.S -+++ b/libgcc/config/mips/vr4120-div.S -@@ -29,6 +29,10 @@ see the files COPYING3 and COPYING.RUNTI - -mfix-vr4120. div and ddiv do not give the correct result when one - of the operands is negative. */ - -+/* An executable stack is *not* required for these functions. */ -+ .section .note.GNU-stack,"",%progbits -+ .previous -+ - .set nomips16 - - #define DIV \ diff --git a/toolchain/gcc/patches-10.x/931-libffi-fix-MIPS-softfloat-build-issue.patch b/toolchain/gcc/patches-10.x/931-libffi-fix-MIPS-softfloat-build-issue.patch deleted file mode 100644 index fb4cb1533a..0000000000 --- a/toolchain/gcc/patches-10.x/931-libffi-fix-MIPS-softfloat-build-issue.patch +++ /dev/null @@ -1,168 +0,0 @@ -From c0c62fa4256f805389f16ebfc4a60cf789129b50 Mon Sep 17 00:00:00 2001 -From: BangLang Huang -Date: Wed, 9 Nov 2016 10:36:49 +0800 -Subject: [PATCH] libffi: fix MIPS softfloat build issue - -Backported from github.com/libffi/libffi#272 - -Signed-off-by: BangLang Huang -Signed-off-by: Yousong Zhou ---- - libffi/src/mips/n32.S | 17 +++++++++++++++++ - libffi/src/mips/o32.S | 17 +++++++++++++++++ - 2 files changed, 34 insertions(+) - ---- a/libffi/src/mips/n32.S -+++ b/libffi/src/mips/n32.S -@@ -107,6 +107,16 @@ loadregs: - - REG_L t6, 3*FFI_SIZEOF_ARG($fp) # load the flags word into t6. - -+#ifdef __mips_soft_float -+ REG_L a0, 0*FFI_SIZEOF_ARG(t9) -+ REG_L a1, 1*FFI_SIZEOF_ARG(t9) -+ REG_L a2, 2*FFI_SIZEOF_ARG(t9) -+ REG_L a3, 3*FFI_SIZEOF_ARG(t9) -+ REG_L a4, 4*FFI_SIZEOF_ARG(t9) -+ REG_L a5, 5*FFI_SIZEOF_ARG(t9) -+ REG_L a6, 6*FFI_SIZEOF_ARG(t9) -+ REG_L a7, 7*FFI_SIZEOF_ARG(t9) -+#else - and t4, t6, ((1< -Date: Fri, 4 May 2018 18:20:53 +0800 -Subject: [PATCH] gotools: fix compilation when making cross compiler - -libgo is "the runtime support library for the Go programming language. -This library is intended for use with the Go frontend." - -gccgo will link target files with libgo.so which depends on libgcc_s.so.1, but -the linker will complain that it cannot find it. That's because shared libgcc -is not present in the install directory yet. libgo.so was made without problem -because gcc will emit -lgcc_s when compiled with -shared option. When gotools -were being made, it was supplied with -static-libgcc thus no link option was -provided. Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec -for linking with libgo.so - -- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation -- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html - -When 3-pass GCC compilation is used, shared libgcc runtime libraries will be -available after gcc pass2 completed and will meet the gotools link requirement -at gcc pass3 ---- - gotools/Makefile.am | 4 +++- - gotools/Makefile.in | 4 +++- - 2 files changed, 6 insertions(+), 2 deletions(-) - ---- a/gotools/Makefile.am -+++ b/gotools/Makefile.am -@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd} - STAMP = echo timestamp > - - libgodir = ../$(target_noncanonical)/libgo -+libgccdir = ../$(target_noncanonical)/libgcc - LIBGODEP = $(libgodir)/libgo.la - - LIBGOTOOL = $(libgodir)/libgotool.a -@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET) - GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS) - - AM_GOCFLAGS = -I $(libgodir) --AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs -+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \ -+ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s - GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@ - - libgosrcdir = $(srcdir)/../libgo/go ---- a/gotools/Makefile.in -+++ b/gotools/Makefile.in -@@ -337,6 +337,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd - PWD_COMMAND = $${PWDCMD-pwd} - STAMP = echo timestamp > - libgodir = ../$(target_noncanonical)/libgo -+libgccdir = ../$(target_noncanonical)/libgcc - LIBGODEP = $(libgodir)/libgo.la - LIBGOTOOL = $(libgodir)/libgotool.a - @NATIVE_FALSE@GOCOMPILER = $(GOC) -@@ -346,7 +347,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a - GOCFLAGS = $(CFLAGS_FOR_TARGET) - GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS) - AM_GOCFLAGS = -I $(libgodir) --AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs -+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \ -+ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s - GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@ - libgosrcdir = $(srcdir)/../libgo/go - cmdsrcdir = $(libgosrcdir)/cmd From 288b36c2ea32e1de1b7ad4772612d718199804e4 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Sat, 17 Sep 2022 18:50:00 +0800 Subject: [PATCH 67/80] ramips: add missing WAN LED for Xiaomi Mi Router 4A / 4C The blue WAN LED connected to GPIO37 is missing, so re-add it. Signed-off-by: Shiji Yang --- target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi | 7 ++++++- target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds | 7 +++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi b/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi index 0a48c06019..ff738a5261 100644 --- a/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi +++ b/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi @@ -30,6 +30,11 @@ label = "yellow:power"; gpios = <&gpio 44 GPIO_ACTIVE_LOW>; }; + + wan { + label = "blue:wan"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + }; }; keys { @@ -93,7 +98,7 @@ &state_default { gpio { - groups = "gpio", "wdt", "wled_an"; + groups = "gpio", "refclk", "wdt", "wled_an"; function = "gpio"; }; }; diff --git a/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds b/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds index 0af01d4393..8a21756225 100644 --- a/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds +++ b/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds @@ -144,6 +144,13 @@ wavlink,wl-wn578a2) ucidef_set_led_switch "lan" "lan" "green:lan" "switch0" "0x8" ucidef_set_led_switch "wan" "wan" "green:wan" "switch0" "0x10" ;; +xiaomi,mi-router-4a-100m|\ +xiaomi,mi-router-4a-100m-intl) + ucidef_set_led_switch "wan" "WAN" "blue:wan" "switch0" "0x01" + ;; +xiaomi,mi-router-4c) + ucidef_set_led_switch "wan" "WAN" "blue:wan" "switch0" "0x02" + ;; zbtlink,zbt-we1226) ucidef_set_led_netdev "wifi_led" "wifi" "green:wlan" "wlan0" ucidef_set_led_switch "lan1" "LAN1" "green:lan1" "switch0" "0x01" From 24bf94ecb728d47d45ec9a419b92bb8440eb64ce Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Mon, 24 Oct 2022 18:16:56 +0200 Subject: [PATCH 68/80] button-hotplug: simplify build Remove unnecessary kconfig junk Signed-off-by: Felix Fietkau --- package/kernel/button-hotplug/Makefile | 17 +---------------- package/kernel/button-hotplug/src/Kconfig | 2 -- package/kernel/button-hotplug/src/Makefile | 2 +- 3 files changed, 2 insertions(+), 19 deletions(-) delete mode 100644 package/kernel/button-hotplug/src/Kconfig diff --git a/package/kernel/button-hotplug/Makefile b/package/kernel/button-hotplug/Makefile index 55412e5685..8e8c02609c 100644 --- a/package/kernel/button-hotplug/Makefile +++ b/package/kernel/button-hotplug/Makefile @@ -28,23 +28,8 @@ define KernelPackage/button-hotplug/description If your device uses GPIO buttons, see gpio-button-hotplug. endef -EXTRA_KCONFIG:= \ - CONFIG_BUTTON_HOTPLUG=m - -EXTRA_CFLAGS:= \ - $(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=m,%,$(filter %=m,$(EXTRA_KCONFIG)))) \ - $(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=y,%,$(filter %=y,$(EXTRA_KCONFIG)))) \ - -MAKE_OPTS:= \ - $(KERNEL_MAKE_FLAGS) \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - $(EXTRA_KCONFIG) - define Build/Compile - $(MAKE) -C "$(LINUX_DIR)" \ - $(MAKE_OPTS) \ - modules + $(KERNEL_MAKE) M="$(PKG_BUILD_DIR)" modules endef $(eval $(call KernelPackage,button-hotplug)) diff --git a/package/kernel/button-hotplug/src/Kconfig b/package/kernel/button-hotplug/src/Kconfig deleted file mode 100644 index aa292e9c13..0000000000 --- a/package/kernel/button-hotplug/src/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config BUTTON_HOTPLUG - tristate "Button Hotplug driver" diff --git a/package/kernel/button-hotplug/src/Makefile b/package/kernel/button-hotplug/src/Makefile index 230d604f8c..e38fa40bb4 100644 --- a/package/kernel/button-hotplug/src/Makefile +++ b/package/kernel/button-hotplug/src/Makefile @@ -1 +1 @@ -obj-${CONFIG_BUTTON_HOTPLUG} += button-hotplug.o \ No newline at end of file +obj-m := button-hotplug.o From e4b9538ddbcc7c98119249f5b862bbb3f3c88cb5 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Mon, 24 Oct 2022 20:43:14 +0200 Subject: [PATCH 69/80] mac80211: use KERNEL_MAKEOPTS instead of KERNEL_MAKE_FLAGS Fixes issues with disabling stack validation on non-linux systems Signed-off-by: Felix Fietkau --- package/kernel/mac80211/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/kernel/mac80211/Makefile b/package/kernel/mac80211/Makefile index 6a3c126e6d..91dad18254 100644 --- a/package/kernel/mac80211/Makefile +++ b/package/kernel/mac80211/Makefile @@ -426,8 +426,8 @@ ifeq ($(BUILD_VARIANT),smallbuffers) C_DEFINES+= -DCONFIG_ATH10K_SMALLBUFFERS endif -MAKE_OPTS:= -C "$(PKG_BUILD_DIR)" \ - $(KERNEL_MAKE_FLAGS) \ +MAKE_OPTS:= \ + $(subst -C $(LINUX_DIR),-C "$(PKG_BUILD_DIR)",$(KERNEL_MAKEOPTS)) \ EXTRA_CFLAGS="-I$(PKG_BUILD_DIR)/include $(IREMAP_CFLAGS) $(C_DEFINES)" \ KLIB_BUILD="$(LINUX_DIR)" \ MODPROBE=true \ From 8246ab6a27c1f50a10051055188119230f8f0650 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Thu, 20 Oct 2022 12:52:17 +0200 Subject: [PATCH 70/80] mac80211: fix masking nested A-MSDU support for mesh CONFIG_MAC80211_MESH isn't defined for this package, rendering the patch useless. Match protecting the access of sta_info.mesh with the very same define declaring it. Fixes 45109f69a6 "mac80211: fix compile error when mesh is disabled" Signed-off-by: Andre Heider --- .../800-mac80211-mask-nested-A-MSDU-support-for-mesh.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/kernel/mac80211/patches/subsys/800-mac80211-mask-nested-A-MSDU-support-for-mesh.patch b/package/kernel/mac80211/patches/subsys/800-mac80211-mask-nested-A-MSDU-support-for-mesh.patch index e7da94c9cd..a17d6f6161 100644 --- a/package/kernel/mac80211/patches/subsys/800-mac80211-mask-nested-A-MSDU-support-for-mesh.patch +++ b/package/kernel/mac80211/patches/subsys/800-mac80211-mask-nested-A-MSDU-support-for-mesh.patch @@ -24,7 +24,7 @@ Signed-off-by: David Bauer - capab = u16_encode_bits(amsdu, IEEE80211_ADDBA_PARAM_AMSDU_MASK); + capab = 0; -+#ifdef CONFIG_MAC80211_MESH ++#ifdef CPTCFG_MAC80211_MESH + if (!sta->mesh) +#endif + capab = u16_encode_bits(amsdu, IEEE80211_ADDBA_PARAM_AMSDU_MASK); From b1826346890fae87a2ed2f6242c5f074f3736c0a Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 21 Oct 2022 22:14:22 +0200 Subject: [PATCH 71/80] generic: 5.15: move MIPS cpuinfo patch from pending to backport Move MIPS cpuinfo patch from pending to backport as it got merged upstream. Signed-off-by: Christian Marangi --- ...kernel-proc-add-CPU-option-reporting.patch | 162 ++++++++++++++++++ ...mp_processor_id-in-preemptible-in-sh.patch | 62 +++++++ ...CPU-option-reporting-to-proc-cpuinfo.patch | 136 --------------- 3 files changed, 224 insertions(+), 136 deletions(-) create mode 100644 target/linux/generic/backport-5.15/330-v5.16-01-MIPS-kernel-proc-add-CPU-option-reporting.patch create mode 100644 target/linux/generic/backport-5.15/330-v5.16-02-MIPS-Fix-using-smp_processor_id-in-preemptible-in-sh.patch delete mode 100644 target/linux/generic/pending-5.15/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch diff --git a/target/linux/generic/backport-5.15/330-v5.16-01-MIPS-kernel-proc-add-CPU-option-reporting.patch b/target/linux/generic/backport-5.15/330-v5.16-01-MIPS-kernel-proc-add-CPU-option-reporting.patch new file mode 100644 index 0000000000..c66a3f11b4 --- /dev/null +++ b/target/linux/generic/backport-5.15/330-v5.16-01-MIPS-kernel-proc-add-CPU-option-reporting.patch @@ -0,0 +1,162 @@ +From 626bfa03729959ea9917181fb3d8ffaa1594d02a Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Wed, 13 Oct 2021 22:40:18 -0700 +Subject: [PATCH 1/1] MIPS: kernel: proc: add CPU option reporting + +Many MIPS CPUs have optional CPU features which are not activated for +all CPU cores. Print the CPU options, which are implemented in the core, +in /proc/cpuinfo. This makes it possible to see which features are +supported and which are not supported. This should cover all standard +MIPS extensions. Before, it only printed information about the main MIPS +ASEs. + +Signed-off-by: Hauke Mehrtens + +Changes from original patch[0]: +- Remove cpu_has_6k_cache and cpu_has_8k_cache due to commit 6ce91ba8589a + ("MIPS: Remove cpu_has_6k_cache and cpu_has_8k_cache in cpu_cache_init()") +- Add new options: mac2008_only, ftlbparex, gsexcex, mmid, mm_sysad, + mm_full +- Use seq_puts instead of seq_printf as suggested by checkpatch +- Minor commit message reword + +[0]: https://lore.kernel.org/linux-mips/20181223225224.23042-1-hauke@hauke-m.de/ + +Signed-off-by: Ilya Lipnitskiy +Acked-by: Hauke Mehrtens +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/kernel/proc.c | 122 ++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 122 insertions(+) + +--- a/arch/mips/kernel/proc.c ++++ b/arch/mips/kernel/proc.c +@@ -138,6 +138,128 @@ static int show_cpuinfo(struct seq_file + seq_printf(m, "micromips kernel\t: %s\n", + (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no"); + } ++ ++ seq_puts(m, "Options implemented\t:"); ++ if (cpu_has_tlb) ++ seq_puts(m, " tlb"); ++ if (cpu_has_ftlb) ++ seq_puts(m, " ftlb"); ++ if (cpu_has_tlbinv) ++ seq_puts(m, " tlbinv"); ++ if (cpu_has_segments) ++ seq_puts(m, " segments"); ++ if (cpu_has_rixiex) ++ seq_puts(m, " rixiex"); ++ if (cpu_has_ldpte) ++ seq_puts(m, " ldpte"); ++ if (cpu_has_maar) ++ seq_puts(m, " maar"); ++ if (cpu_has_rw_llb) ++ seq_puts(m, " rw_llb"); ++ if (cpu_has_4kex) ++ seq_puts(m, " 4kex"); ++ if (cpu_has_3k_cache) ++ seq_puts(m, " 3k_cache"); ++ if (cpu_has_4k_cache) ++ seq_puts(m, " 4k_cache"); ++ if (cpu_has_tx39_cache) ++ seq_puts(m, " tx39_cache"); ++ if (cpu_has_octeon_cache) ++ seq_puts(m, " octeon_cache"); ++ if (cpu_has_fpu) ++ seq_puts(m, " fpu"); ++ if (cpu_has_32fpr) ++ seq_puts(m, " 32fpr"); ++ if (cpu_has_cache_cdex_p) ++ seq_puts(m, " cache_cdex_p"); ++ if (cpu_has_cache_cdex_s) ++ seq_puts(m, " cache_cdex_s"); ++ if (cpu_has_prefetch) ++ seq_puts(m, " prefetch"); ++ if (cpu_has_mcheck) ++ seq_puts(m, " mcheck"); ++ if (cpu_has_ejtag) ++ seq_puts(m, " ejtag"); ++ if (cpu_has_llsc) ++ seq_puts(m, " llsc"); ++ if (cpu_has_guestctl0ext) ++ seq_puts(m, " guestctl0ext"); ++ if (cpu_has_guestctl1) ++ seq_puts(m, " guestctl1"); ++ if (cpu_has_guestctl2) ++ seq_puts(m, " guestctl2"); ++ if (cpu_has_guestid) ++ seq_puts(m, " guestid"); ++ if (cpu_has_drg) ++ seq_puts(m, " drg"); ++ if (cpu_has_rixi) ++ seq_puts(m, " rixi"); ++ if (cpu_has_lpa) ++ seq_puts(m, " lpa"); ++ if (cpu_has_mvh) ++ seq_puts(m, " mvh"); ++ if (cpu_has_vtag_icache) ++ seq_puts(m, " vtag_icache"); ++ if (cpu_has_dc_aliases) ++ seq_puts(m, " dc_aliases"); ++ if (cpu_has_ic_fills_f_dc) ++ seq_puts(m, " ic_fills_f_dc"); ++ if (cpu_has_pindexed_dcache) ++ seq_puts(m, " pindexed_dcache"); ++ if (cpu_has_userlocal) ++ seq_puts(m, " userlocal"); ++ if (cpu_has_nofpuex) ++ seq_puts(m, " nofpuex"); ++ if (cpu_has_vint) ++ seq_puts(m, " vint"); ++ if (cpu_has_veic) ++ seq_puts(m, " veic"); ++ if (cpu_has_inclusive_pcaches) ++ seq_puts(m, " inclusive_pcaches"); ++ if (cpu_has_perf_cntr_intr_bit) ++ seq_puts(m, " perf_cntr_intr_bit"); ++ if (cpu_has_ufr) ++ seq_puts(m, " ufr"); ++ if (cpu_has_fre) ++ seq_puts(m, " fre"); ++ if (cpu_has_cdmm) ++ seq_puts(m, " cdmm"); ++ if (cpu_has_small_pages) ++ seq_puts(m, " small_pages"); ++ if (cpu_has_nan_legacy) ++ seq_puts(m, " nan_legacy"); ++ if (cpu_has_nan_2008) ++ seq_puts(m, " nan_2008"); ++ if (cpu_has_ebase_wg) ++ seq_puts(m, " ebase_wg"); ++ if (cpu_has_badinstr) ++ seq_puts(m, " badinstr"); ++ if (cpu_has_badinstrp) ++ seq_puts(m, " badinstrp"); ++ if (cpu_has_contextconfig) ++ seq_puts(m, " contextconfig"); ++ if (cpu_has_perf) ++ seq_puts(m, " perf"); ++ if (cpu_has_mac2008_only) ++ seq_puts(m, " mac2008_only"); ++ if (cpu_has_ftlbparex) ++ seq_puts(m, " ftlbparex"); ++ if (cpu_has_gsexcex) ++ seq_puts(m, " gsexcex"); ++ if (cpu_has_shared_ftlb_ram) ++ seq_puts(m, " shared_ftlb_ram"); ++ if (cpu_has_shared_ftlb_entries) ++ seq_puts(m, " shared_ftlb_entries"); ++ if (cpu_has_mipsmt_pertccounters) ++ seq_puts(m, " mipsmt_pertccounters"); ++ if (cpu_has_mmid) ++ seq_puts(m, " mmid"); ++ if (cpu_has_mm_sysad) ++ seq_puts(m, " mm_sysad"); ++ if (cpu_has_mm_full) ++ seq_puts(m, " mm_full"); ++ seq_puts(m, "\n"); ++ + seq_printf(m, "shadow register sets\t: %d\n", + cpu_data[n].srsets); + seq_printf(m, "kscratch registers\t: %d\n", diff --git a/target/linux/generic/backport-5.15/330-v5.16-02-MIPS-Fix-using-smp_processor_id-in-preemptible-in-sh.patch b/target/linux/generic/backport-5.15/330-v5.16-02-MIPS-Fix-using-smp_processor_id-in-preemptible-in-sh.patch new file mode 100644 index 0000000000..6caf7d06d4 --- /dev/null +++ b/target/linux/generic/backport-5.15/330-v5.16-02-MIPS-Fix-using-smp_processor_id-in-preemptible-in-sh.patch @@ -0,0 +1,62 @@ +From 1cab5bd69eb1f995ced2d7576cb15f8a8941fd85 Mon Sep 17 00:00:00 2001 +From: Tiezhu Yang +Date: Thu, 25 Nov 2021 19:39:32 +0800 +Subject: [PATCH 1/1] MIPS: Fix using smp_processor_id() in preemptible in + show_cpuinfo() + +There exists the following issue under DEBUG_PREEMPT: + + BUG: using smp_processor_id() in preemptible [00000000] code: systemd/1 + caller is show_cpuinfo+0x460/0xea0 + ... + Call Trace: + [] show_stack+0x94/0x128 + [] dump_stack_lvl+0x94/0xd8 + [] check_preemption_disabled+0x104/0x110 + [] show_cpuinfo+0x460/0xea0 + [] seq_read_iter+0xfc/0x4f8 + [] new_sync_read+0x110/0x1b8 + [] vfs_read+0x1b4/0x1d0 + [] ksys_read+0xd0/0x110 + [] syscall_common+0x34/0x58 + +We can see the following call trace: + show_cpuinfo() + cpu_has_fpu + current_cpu_data + smp_processor_id() + + $ addr2line -f -e vmlinux 0xffffffff802209c8 + show_cpuinfo + arch/mips/kernel/proc.c:188 + + $ head -188 arch/mips/kernel/proc.c | tail -1 + if (cpu_has_fpu) + + arch/mips/include/asm/cpu-features.h + # define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) + + arch/mips/include/asm/cpu-info.h + #define current_cpu_data cpu_data[smp_processor_id()] + +Based on the above analysis, fix the issue by using raw_cpu_has_fpu +which calls raw_smp_processor_id() in show_cpuinfo(). + +Fixes: 626bfa037299 ("MIPS: kernel: proc: add CPU option reporting") +Signed-off-by: Tiezhu Yang +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/kernel/proc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/kernel/proc.c ++++ b/arch/mips/kernel/proc.c +@@ -166,7 +166,7 @@ static int show_cpuinfo(struct seq_file + seq_puts(m, " tx39_cache"); + if (cpu_has_octeon_cache) + seq_puts(m, " octeon_cache"); +- if (cpu_has_fpu) ++ if (raw_cpu_has_fpu) + seq_puts(m, " fpu"); + if (cpu_has_32fpr) + seq_puts(m, " 32fpr"); diff --git a/target/linux/generic/pending-5.15/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch b/target/linux/generic/pending-5.15/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch deleted file mode 100644 index 318c0b1b25..0000000000 --- a/target/linux/generic/pending-5.15/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch +++ /dev/null @@ -1,136 +0,0 @@ -From 87ec87c2ad615c1a177cd08ef5fa29fc739f6e50 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sun, 23 Dec 2018 18:06:53 +0100 -Subject: [PATCH] MIPS: Add CPU option reporting to /proc/cpuinfo - -Many MIPS CPUs have optional CPU features which are not activates for -all CPU cores. Print the CPU options which are implemented in the core -in /proc/cpuinfo. This makes it possible to see what features are -supported and which are not supported. This should cover all standard -MIPS extensions, before it only printed information about the main MIPS -ASEs. - -Signed-off-by: Hauke Mehrtens ---- - arch/mips/kernel/proc.c | 116 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 116 insertions(+) - ---- a/arch/mips/kernel/proc.c -+++ b/arch/mips/kernel/proc.c -@@ -138,6 +138,116 @@ static int show_cpuinfo(struct seq_file - seq_printf(m, "micromips kernel\t: %s\n", - (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no"); - } -+ -+ seq_printf(m, "Options implemented\t:"); -+ if (cpu_has_tlb) -+ seq_printf(m, "%s", " tlb"); -+ if (cpu_has_ftlb) -+ seq_printf(m, "%s", " ftlb"); -+ if (cpu_has_tlbinv) -+ seq_printf(m, "%s", " tlbinv"); -+ if (cpu_has_segments) -+ seq_printf(m, "%s", " segments"); -+ if (cpu_has_rixiex) -+ seq_printf(m, "%s", " rixiex"); -+ if (cpu_has_ldpte) -+ seq_printf(m, "%s", " ldpte"); -+ if (cpu_has_maar) -+ seq_printf(m, "%s", " maar"); -+ if (cpu_has_rw_llb) -+ seq_printf(m, "%s", " rw_llb"); -+ if (cpu_has_4kex) -+ seq_printf(m, "%s", " 4kex"); -+ if (cpu_has_3k_cache) -+ seq_printf(m, "%s", " 3k_cache"); -+ if (cpu_has_4k_cache) -+ seq_printf(m, "%s", " 4k_cache"); -+ if (cpu_has_tx39_cache) -+ seq_printf(m, "%s", " tx39_cache"); -+ if (cpu_has_octeon_cache) -+ seq_printf(m, "%s", " octeon_cache"); -+ if (cpu_has_fpu) -+ seq_printf(m, "%s", " fpu"); -+ if (cpu_has_32fpr) -+ seq_printf(m, "%s", " 32fpr"); -+ if (cpu_has_cache_cdex_p) -+ seq_printf(m, "%s", " cache_cdex_p"); -+ if (cpu_has_cache_cdex_s) -+ seq_printf(m, "%s", " cache_cdex_s"); -+ if (cpu_has_prefetch) -+ seq_printf(m, "%s", " prefetch"); -+ if (cpu_has_mcheck) -+ seq_printf(m, "%s", " mcheck"); -+ if (cpu_has_ejtag) -+ seq_printf(m, "%s", " ejtag"); -+ if (cpu_has_llsc) -+ seq_printf(m, "%s", " llsc"); -+ if (cpu_has_guestctl0ext) -+ seq_printf(m, "%s", " guestctl0ext"); -+ if (cpu_has_guestctl1) -+ seq_printf(m, "%s", " guestctl1"); -+ if (cpu_has_guestctl2) -+ seq_printf(m, "%s", " guestctl2"); -+ if (cpu_has_guestid) -+ seq_printf(m, "%s", " guestid"); -+ if (cpu_has_drg) -+ seq_printf(m, "%s", " drg"); -+ if (cpu_has_rixi) -+ seq_printf(m, "%s", " rixi"); -+ if (cpu_has_lpa) -+ seq_printf(m, "%s", " lpa"); -+ if (cpu_has_mvh) -+ seq_printf(m, "%s", " mvh"); -+ if (cpu_has_vtag_icache) -+ seq_printf(m, "%s", " vtag_icache"); -+ if (cpu_has_dc_aliases) -+ seq_printf(m, "%s", " dc_aliases"); -+ if (cpu_has_ic_fills_f_dc) -+ seq_printf(m, "%s", " ic_fills_f_dc"); -+ if (cpu_has_pindexed_dcache) -+ seq_printf(m, "%s", " pindexed_dcache"); -+ if (cpu_has_userlocal) -+ seq_printf(m, "%s", " userlocal"); -+ if (cpu_has_nofpuex) -+ seq_printf(m, "%s", " nofpuex"); -+ if (cpu_has_vint) -+ seq_printf(m, "%s", " vint"); -+ if (cpu_has_veic) -+ seq_printf(m, "%s", " veic"); -+ if (cpu_has_inclusive_pcaches) -+ seq_printf(m, "%s", " inclusive_pcaches"); -+ if (cpu_has_perf_cntr_intr_bit) -+ seq_printf(m, "%s", " perf_cntr_intr_bit"); -+ if (cpu_has_ufr) -+ seq_printf(m, "%s", " ufr"); -+ if (cpu_has_fre) -+ seq_printf(m, "%s", " fre"); -+ if (cpu_has_cdmm) -+ seq_printf(m, "%s", " cdmm"); -+ if (cpu_has_small_pages) -+ seq_printf(m, "%s", " small_pages"); -+ if (cpu_has_nan_legacy) -+ seq_printf(m, "%s", " nan_legacy"); -+ if (cpu_has_nan_2008) -+ seq_printf(m, "%s", " nan_2008"); -+ if (cpu_has_ebase_wg) -+ seq_printf(m, "%s", " ebase_wg"); -+ if (cpu_has_badinstr) -+ seq_printf(m, "%s", " badinstr"); -+ if (cpu_has_badinstrp) -+ seq_printf(m, "%s", " badinstrp"); -+ if (cpu_has_contextconfig) -+ seq_printf(m, "%s", " contextconfig"); -+ if (cpu_has_perf) -+ seq_printf(m, "%s", " perf"); -+ if (cpu_has_shared_ftlb_ram) -+ seq_printf(m, "%s", " shared_ftlb_ram"); -+ if (cpu_has_shared_ftlb_entries) -+ seq_printf(m, "%s", " shared_ftlb_entries"); -+ if (cpu_has_mipsmt_pertccounters) -+ seq_printf(m, "%s", " mipsmt_pertccounters"); -+ seq_printf(m, "\n"); -+ - seq_printf(m, "shadow register sets\t: %d\n", - cpu_data[n].srsets); - seq_printf(m, "kscratch registers\t: %d\n", From f846945bd2adfcb60e2a4f24cb8fc08c0e495b48 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 21 Oct 2022 22:37:06 +0200 Subject: [PATCH 72/80] generic: 5.15: move dtc drop interrupt check from pending to backport Move dtc drop interrupto check from pending to backport as it got merged upstream. Signed-off-by: Christian Marangi --- ...te-to-upstream-version-v1.6.1-19-g0a.patch | 997 ++++++++++++++++++ ...terrupt-provider-address-cells-check.patch | 28 - 2 files changed, 997 insertions(+), 28 deletions(-) create mode 100644 target/linux/generic/backport-5.15/201-v5.16-scripts-dtc-Update-to-upstream-version-v1.6.1-19-g0a.patch delete mode 100644 target/linux/generic/pending-5.15/050-dtc-checks-Drop-interrupt-provider-address-cells-check.patch diff --git a/target/linux/generic/backport-5.15/201-v5.16-scripts-dtc-Update-to-upstream-version-v1.6.1-19-g0a.patch b/target/linux/generic/backport-5.15/201-v5.16-scripts-dtc-Update-to-upstream-version-v1.6.1-19-g0a.patch new file mode 100644 index 0000000000..d1bef74f32 --- /dev/null +++ b/target/linux/generic/backport-5.15/201-v5.16-scripts-dtc-Update-to-upstream-version-v1.6.1-19-g0a.patch @@ -0,0 +1,997 @@ +From a77725a9a3c5924e2fd4cd5b3557dd92a8e46f87 Mon Sep 17 00:00:00 2001 +From: Rob Herring +Date: Mon, 25 Oct 2021 11:05:45 -0500 +Subject: [PATCH 1/1] scripts/dtc: Update to upstream version + v1.6.1-19-g0a3a9d3449c8 + +This adds the following commits from upstream: + +0a3a9d3449c8 checks: Add an interrupt-map check +8fd24744e361 checks: Ensure '#interrupt-cells' only exists in interrupt providers +d8d1a9a77863 checks: Drop interrupt provider '#address-cells' check +52a16fd72824 checks: Make interrupt_provider check dependent on interrupts_extended_is_cell +37fd700685da treesource: Maintain phandle label/path on output +e33ce1d6a8c7 flattree: Use '\n', not ';' to separate asm pseudo-ops +d24cc189dca6 asm: Use assembler macros instead of cpp macros +ff3a30c115ad asm: Use .asciz and .ascii instead of .string +5eb5927d81ee fdtdump: fix -Werror=int-to-pointer-cast +0869f8269161 libfdt: Add ALIGNMENT error string +69595a167f06 checks: Fix bus-range check +72d09e2682a4 Makefile: add -Wsign-compare to warning options +b587787ef388 checks: Fix signedness comparisons warnings +69bed6c2418f dtc: Wrap phandle validity check +910221185560 fdtget: Fix signedness comparisons warnings +d966f08fcd21 tests: Fix signedness comparisons warnings +ecfb438c07fa dtc: Fix signedness comparisons warnings: pointer diff +5bec74a6d135 dtc: Fix signedness comparisons warnings: reservednum +24e7f511fd4a fdtdump: Fix signedness comparisons warnings +b6910bec1161 Bump version to v1.6.1 +21d61d18f968 Fix CID 1461557 +4c2ef8f4d14c checks: Introduce is_multiple_of() +e59ca36fb70e Make handling of cpp line information more tolerant +0c3fd9b6aceb checks: Drop interrupt_cells_is_cell check +6b3081abc4ac checks: Add check_is_cell() for all phandle+arg properties +2dffc192a77f yamltree: Remove marker ordering dependency +61e513439e40 pylibfdt: Rework "avoid unused variable warning" lines +c8bddd106095 tests: add a positive gpio test case +ad4abfadb687 checks: replace strstr and strrchr with strends +09c6a6e88718 dtc.h: add strends for suffix matching +9bb9b8d0b4a0 checks: tigthen up nr-gpios prop exception +b07b62ee3342 libfdt: Add FDT alignment check to fdt_check_header() +a2def5479950 libfdt: Check that the root-node name is empty +4ca61f84dc21 libfdt: Check that there is only one root node +34d708249a91 dtc: Remove -O dtbo support +8e7ff260f755 libfdt: Fix a possible "unchecked return value" warning +88875268c05c checks: Warn on node-name and property name being the same +9d2279e7e6ee checks: Change node-name check to match devicetree spec +f527c867a8c6 util: limit gnu_printf format attribute to gcc >= 4.4.0 + +Reviewed-by: Frank Rowand +Tested-by: Frank Rowand +Signed-off-by: Rob Herring +--- + scripts/dtc/checks.c | 222 ++++++++++++++++++++++-------- + scripts/dtc/dtc-lexer.l | 2 +- + scripts/dtc/dtc.c | 6 +- + scripts/dtc/dtc.h | 40 +++++- + scripts/dtc/flattree.c | 11 +- + scripts/dtc/libfdt/fdt.c | 4 + + scripts/dtc/libfdt/fdt_rw.c | 18 ++- + scripts/dtc/libfdt/fdt_strerror.c | 1 + + scripts/dtc/libfdt/libfdt.h | 7 + + scripts/dtc/livetree.c | 6 +- + scripts/dtc/treesource.c | 48 +++---- + scripts/dtc/util.h | 6 +- + scripts/dtc/version_gen.h | 2 +- + scripts/dtc/yamltree.c | 16 ++- + 14 files changed, 275 insertions(+), 114 deletions(-) + +--- a/scripts/dtc/checks.c ++++ b/scripts/dtc/checks.c +@@ -143,6 +143,14 @@ static void check_nodes_props(struct che + check_nodes_props(c, dti, child); + } + ++static bool is_multiple_of(int multiple, int divisor) ++{ ++ if (divisor == 0) ++ return multiple == 0; ++ else ++ return (multiple % divisor) == 0; ++} ++ + static bool run_check(struct check *c, struct dt_info *dti) + { + struct node *dt = dti->dt; +@@ -297,19 +305,20 @@ ERROR(duplicate_property_names, check_du + #define LOWERCASE "abcdefghijklmnopqrstuvwxyz" + #define UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ" + #define DIGITS "0123456789" +-#define PROPNODECHARS LOWERCASE UPPERCASE DIGITS ",._+*#?-" ++#define NODECHARS LOWERCASE UPPERCASE DIGITS ",._+-@" ++#define PROPCHARS LOWERCASE UPPERCASE DIGITS ",._+*#?-" + #define PROPNODECHARSSTRICT LOWERCASE UPPERCASE DIGITS ",-" + + static void check_node_name_chars(struct check *c, struct dt_info *dti, + struct node *node) + { +- int n = strspn(node->name, c->data); ++ size_t n = strspn(node->name, c->data); + + if (n < strlen(node->name)) + FAIL(c, dti, node, "Bad character '%c' in node name", + node->name[n]); + } +-ERROR(node_name_chars, check_node_name_chars, PROPNODECHARS "@"); ++ERROR(node_name_chars, check_node_name_chars, NODECHARS); + + static void check_node_name_chars_strict(struct check *c, struct dt_info *dti, + struct node *node) +@@ -330,6 +339,20 @@ static void check_node_name_format(struc + } + ERROR(node_name_format, check_node_name_format, NULL, &node_name_chars); + ++static void check_node_name_vs_property_name(struct check *c, ++ struct dt_info *dti, ++ struct node *node) ++{ ++ if (!node->parent) ++ return; ++ ++ if (get_property(node->parent, node->name)) { ++ FAIL(c, dti, node, "node name and property name conflict"); ++ } ++} ++WARNING(node_name_vs_property_name, check_node_name_vs_property_name, ++ NULL, &node_name_chars); ++ + static void check_unit_address_vs_reg(struct check *c, struct dt_info *dti, + struct node *node) + { +@@ -363,14 +386,14 @@ static void check_property_name_chars(st + struct property *prop; + + for_each_property(node, prop) { +- int n = strspn(prop->name, c->data); ++ size_t n = strspn(prop->name, c->data); + + if (n < strlen(prop->name)) + FAIL_PROP(c, dti, node, prop, "Bad character '%c' in property name", + prop->name[n]); + } + } +-ERROR(property_name_chars, check_property_name_chars, PROPNODECHARS); ++ERROR(property_name_chars, check_property_name_chars, PROPCHARS); + + static void check_property_name_chars_strict(struct check *c, + struct dt_info *dti, +@@ -380,7 +403,7 @@ static void check_property_name_chars_st + + for_each_property(node, prop) { + const char *name = prop->name; +- int n = strspn(name, c->data); ++ size_t n = strspn(name, c->data); + + if (n == strlen(prop->name)) + continue; +@@ -497,7 +520,7 @@ static cell_t check_phandle_prop(struct + + phandle = propval_cell(prop); + +- if ((phandle == 0) || (phandle == -1)) { ++ if (!phandle_is_valid(phandle)) { + FAIL_PROP(c, dti, node, prop, "bad value (0x%x) in %s property", + phandle, prop->name); + return 0; +@@ -556,7 +579,7 @@ static void check_name_properties(struct + if (!prop) + return; /* No name property, that's fine */ + +- if ((prop->val.len != node->basenamelen+1) ++ if ((prop->val.len != node->basenamelen + 1U) + || (memcmp(prop->val.val, node->name, node->basenamelen) != 0)) { + FAIL(c, dti, node, "\"name\" property is incorrect (\"%s\" instead" + " of base node name)", prop->val.val); +@@ -657,7 +680,6 @@ ERROR(omit_unused_nodes, fixup_omit_unus + */ + WARNING_IF_NOT_CELL(address_cells_is_cell, "#address-cells"); + WARNING_IF_NOT_CELL(size_cells_is_cell, "#size-cells"); +-WARNING_IF_NOT_CELL(interrupt_cells_is_cell, "#interrupt-cells"); + + WARNING_IF_NOT_STRING(device_type_is_string, "device_type"); + WARNING_IF_NOT_STRING(model_is_string, "model"); +@@ -672,8 +694,7 @@ static void check_names_is_string_list(s + struct property *prop; + + for_each_property(node, prop) { +- const char *s = strrchr(prop->name, '-'); +- if (!s || !streq(s, "-names")) ++ if (!strends(prop->name, "-names")) + continue; + + c->data = prop->name; +@@ -753,7 +774,7 @@ static void check_reg_format(struct chec + size_cells = node_size_cells(node->parent); + entrylen = (addr_cells + size_cells) * sizeof(cell_t); + +- if (!entrylen || (prop->val.len % entrylen) != 0) ++ if (!is_multiple_of(prop->val.len, entrylen)) + FAIL_PROP(c, dti, node, prop, "property has invalid length (%d bytes) " + "(#address-cells == %d, #size-cells == %d)", + prop->val.len, addr_cells, size_cells); +@@ -794,7 +815,7 @@ static void check_ranges_format(struct c + "#size-cells (%d) differs from %s (%d)", + ranges, c_size_cells, node->parent->fullpath, + p_size_cells); +- } else if ((prop->val.len % entrylen) != 0) { ++ } else if (!is_multiple_of(prop->val.len, entrylen)) { + FAIL_PROP(c, dti, node, prop, "\"%s\" property has invalid length (%d bytes) " + "(parent #address-cells == %d, child #address-cells == %d, " + "#size-cells == %d)", ranges, prop->val.len, +@@ -871,7 +892,7 @@ static void check_pci_device_bus_num(str + } else { + cells = (cell_t *)prop->val.val; + min_bus = fdt32_to_cpu(cells[0]); +- max_bus = fdt32_to_cpu(cells[0]); ++ max_bus = fdt32_to_cpu(cells[1]); + } + if ((bus_num < min_bus) || (bus_num > max_bus)) + FAIL_PROP(c, dti, node, prop, "PCI bus number %d out of range, expected (%d - %d)", +@@ -1367,9 +1388,9 @@ static void check_property_phandle_args( + const struct provider *provider) + { + struct node *root = dti->dt; +- int cell, cellsize = 0; ++ unsigned int cell, cellsize = 0; + +- if (prop->val.len % sizeof(cell_t)) { ++ if (!is_multiple_of(prop->val.len, sizeof(cell_t))) { + FAIL_PROP(c, dti, node, prop, + "property size (%d) is invalid, expected multiple of %zu", + prop->val.len, sizeof(cell_t)); +@@ -1379,14 +1400,14 @@ static void check_property_phandle_args( + for (cell = 0; cell < prop->val.len / sizeof(cell_t); cell += cellsize + 1) { + struct node *provider_node; + struct property *cellprop; +- int phandle; ++ cell_t phandle; + + phandle = propval_cell_n(prop, cell); + /* + * Some bindings use a cell value 0 or -1 to skip over optional + * entries when each index position has a specific definition. + */ +- if (phandle == 0 || phandle == -1) { ++ if (!phandle_is_valid(phandle)) { + /* Give up if this is an overlay with external references */ + if (dti->dtsflags & DTSF_PLUGIN) + break; +@@ -1452,7 +1473,8 @@ static void check_provider_cells_propert + } + #define WARNING_PROPERTY_PHANDLE_CELLS(nm, propname, cells_name, ...) \ + static struct provider nm##_provider = { (propname), (cells_name), __VA_ARGS__ }; \ +- WARNING(nm##_property, check_provider_cells_property, &nm##_provider, &phandle_references); ++ WARNING_IF_NOT_CELL(nm##_is_cell, cells_name); \ ++ WARNING(nm##_property, check_provider_cells_property, &nm##_provider, &nm##_is_cell, &phandle_references); + + WARNING_PROPERTY_PHANDLE_CELLS(clocks, "clocks", "#clock-cells"); + WARNING_PROPERTY_PHANDLE_CELLS(cooling_device, "cooling-device", "#cooling-cells"); +@@ -1473,24 +1495,17 @@ WARNING_PROPERTY_PHANDLE_CELLS(thermal_s + + static bool prop_is_gpio(struct property *prop) + { +- char *str; +- + /* + * *-gpios and *-gpio can appear in property names, + * so skip over any false matches (only one known ATM) + */ +- if (strstr(prop->name, "nr-gpio")) ++ if (strends(prop->name, ",nr-gpios")) + return false; + +- str = strrchr(prop->name, '-'); +- if (str) +- str++; +- else +- str = prop->name; +- if (!(streq(str, "gpios") || streq(str, "gpio"))) +- return false; +- +- return true; ++ return strends(prop->name, "-gpios") || ++ streq(prop->name, "gpios") || ++ strends(prop->name, "-gpio") || ++ streq(prop->name, "gpio"); + } + + static void check_gpios_property(struct check *c, +@@ -1525,13 +1540,10 @@ static void check_deprecated_gpio_proper + struct property *prop; + + for_each_property(node, prop) { +- char *str; +- + if (!prop_is_gpio(prop)) + continue; + +- str = strstr(prop->name, "gpio"); +- if (!streq(str, "gpio")) ++ if (!strends(prop->name, "gpio")) + continue; + + FAIL_PROP(c, dti, node, prop, +@@ -1561,21 +1573,106 @@ static void check_interrupt_provider(str + struct node *node) + { + struct property *prop; ++ bool irq_provider = node_is_interrupt_provider(node); + +- if (!node_is_interrupt_provider(node)) ++ prop = get_property(node, "#interrupt-cells"); ++ if (irq_provider && !prop) { ++ FAIL(c, dti, node, ++ "Missing '#interrupt-cells' in interrupt provider"); + return; ++ } + +- prop = get_property(node, "#interrupt-cells"); +- if (!prop) ++ if (!irq_provider && prop) { + FAIL(c, dti, node, +- "Missing #interrupt-cells in interrupt provider"); ++ "'#interrupt-cells' found, but node is not an interrupt provider"); ++ return; ++ } ++} ++WARNING(interrupt_provider, check_interrupt_provider, NULL, &interrupts_extended_is_cell); + +- prop = get_property(node, "#address-cells"); +- if (!prop) ++static void check_interrupt_map(struct check *c, ++ struct dt_info *dti, ++ struct node *node) ++{ ++ struct node *root = dti->dt; ++ struct property *prop, *irq_map_prop; ++ size_t cellsize, cell, map_cells; ++ ++ irq_map_prop = get_property(node, "interrupt-map"); ++ if (!irq_map_prop) ++ return; ++ ++ if (node->addr_cells < 0) { + FAIL(c, dti, node, +- "Missing #address-cells in interrupt provider"); ++ "Missing '#address-cells' in interrupt-map provider"); ++ return; ++ } ++ cellsize = node_addr_cells(node); ++ cellsize += propval_cell(get_property(node, "#interrupt-cells")); ++ ++ prop = get_property(node, "interrupt-map-mask"); ++ if (prop && (prop->val.len != (cellsize * sizeof(cell_t)))) ++ FAIL_PROP(c, dti, node, prop, ++ "property size (%d) is invalid, expected %zu", ++ prop->val.len, cellsize * sizeof(cell_t)); ++ ++ if (!is_multiple_of(irq_map_prop->val.len, sizeof(cell_t))) { ++ FAIL_PROP(c, dti, node, irq_map_prop, ++ "property size (%d) is invalid, expected multiple of %zu", ++ irq_map_prop->val.len, sizeof(cell_t)); ++ return; ++ } ++ ++ map_cells = irq_map_prop->val.len / sizeof(cell_t); ++ for (cell = 0; cell < map_cells; ) { ++ struct node *provider_node; ++ struct property *cellprop; ++ int phandle; ++ size_t parent_cellsize; ++ ++ if ((cell + cellsize) >= map_cells) { ++ FAIL_PROP(c, dti, node, irq_map_prop, ++ "property size (%d) too small, expected > %zu", ++ irq_map_prop->val.len, (cell + cellsize) * sizeof(cell_t)); ++ break; ++ } ++ cell += cellsize; ++ ++ phandle = propval_cell_n(irq_map_prop, cell); ++ if (!phandle_is_valid(phandle)) { ++ /* Give up if this is an overlay with external references */ ++ if (!(dti->dtsflags & DTSF_PLUGIN)) ++ FAIL_PROP(c, dti, node, irq_map_prop, ++ "Cell %zu is not a phandle(%d)", ++ cell, phandle); ++ break; ++ } ++ ++ provider_node = get_node_by_phandle(root, phandle); ++ if (!provider_node) { ++ FAIL_PROP(c, dti, node, irq_map_prop, ++ "Could not get phandle(%d) node for (cell %zu)", ++ phandle, cell); ++ break; ++ } ++ ++ cellprop = get_property(provider_node, "#interrupt-cells"); ++ if (cellprop) { ++ parent_cellsize = propval_cell(cellprop); ++ } else { ++ FAIL(c, dti, node, "Missing property '#interrupt-cells' in node %s or bad phandle (referred from interrupt-map[%zu])", ++ provider_node->fullpath, cell); ++ break; ++ } ++ ++ cellprop = get_property(provider_node, "#address-cells"); ++ if (cellprop) ++ parent_cellsize += propval_cell(cellprop); ++ ++ cell += 1 + parent_cellsize; ++ } + } +-WARNING(interrupt_provider, check_interrupt_provider, NULL); ++WARNING(interrupt_map, check_interrupt_map, NULL, &phandle_references, &addr_size_cells, &interrupt_provider); + + static void check_interrupts_property(struct check *c, + struct dt_info *dti, +@@ -1584,13 +1681,13 @@ static void check_interrupts_property(st + struct node *root = dti->dt; + struct node *irq_node = NULL, *parent = node; + struct property *irq_prop, *prop = NULL; +- int irq_cells, phandle; ++ cell_t irq_cells, phandle; + + irq_prop = get_property(node, "interrupts"); + if (!irq_prop) + return; + +- if (irq_prop->val.len % sizeof(cell_t)) ++ if (!is_multiple_of(irq_prop->val.len, sizeof(cell_t))) + FAIL_PROP(c, dti, node, irq_prop, "size (%d) is invalid, expected multiple of %zu", + irq_prop->val.len, sizeof(cell_t)); + +@@ -1603,7 +1700,7 @@ static void check_interrupts_property(st + prop = get_property(parent, "interrupt-parent"); + if (prop) { + phandle = propval_cell(prop); +- if ((phandle == 0) || (phandle == -1)) { ++ if (!phandle_is_valid(phandle)) { + /* Give up if this is an overlay with + * external references */ + if (dti->dtsflags & DTSF_PLUGIN) +@@ -1639,7 +1736,7 @@ static void check_interrupts_property(st + } + + irq_cells = propval_cell(prop); +- if (irq_prop->val.len % (irq_cells * sizeof(cell_t))) { ++ if (!is_multiple_of(irq_prop->val.len, irq_cells * sizeof(cell_t))) { + FAIL_PROP(c, dti, node, prop, + "size is (%d), expected multiple of %d", + irq_prop->val.len, (int)(irq_cells * sizeof(cell_t))); +@@ -1750,7 +1847,7 @@ WARNING(graph_port, check_graph_port, NU + static struct node *get_remote_endpoint(struct check *c, struct dt_info *dti, + struct node *endpoint) + { +- int phandle; ++ cell_t phandle; + struct node *node; + struct property *prop; + +@@ -1760,7 +1857,7 @@ static struct node *get_remote_endpoint( + + phandle = propval_cell(prop); + /* Give up if this is an overlay with external references */ +- if (phandle == 0 || phandle == -1) ++ if (!phandle_is_valid(phandle)) + return NULL; + + node = get_node_by_phandle(dti->dt, phandle); +@@ -1796,7 +1893,7 @@ WARNING(graph_endpoint, check_graph_endp + static struct check *check_table[] = { + &duplicate_node_names, &duplicate_property_names, + &node_name_chars, &node_name_format, &property_name_chars, +- &name_is_string, &name_properties, ++ &name_is_string, &name_properties, &node_name_vs_property_name, + + &duplicate_label, + +@@ -1804,7 +1901,7 @@ static struct check *check_table[] = { + &phandle_references, &path_references, + &omit_unused_nodes, + +- &address_cells_is_cell, &size_cells_is_cell, &interrupt_cells_is_cell, ++ &address_cells_is_cell, &size_cells_is_cell, + &device_type_is_string, &model_is_string, &status_is_string, + &label_is_string, + +@@ -1839,26 +1936,43 @@ static struct check *check_table[] = { + &chosen_node_is_root, &chosen_node_bootargs, &chosen_node_stdout_path, + + &clocks_property, ++ &clocks_is_cell, + &cooling_device_property, ++ &cooling_device_is_cell, + &dmas_property, ++ &dmas_is_cell, + &hwlocks_property, ++ &hwlocks_is_cell, + &interrupts_extended_property, ++ &interrupts_extended_is_cell, + &io_channels_property, ++ &io_channels_is_cell, + &iommus_property, ++ &iommus_is_cell, + &mboxes_property, ++ &mboxes_is_cell, + &msi_parent_property, ++ &msi_parent_is_cell, + &mux_controls_property, ++ &mux_controls_is_cell, + &phys_property, ++ &phys_is_cell, + &power_domains_property, ++ &power_domains_is_cell, + &pwms_property, ++ &pwms_is_cell, + &resets_property, ++ &resets_is_cell, + &sound_dai_property, ++ &sound_dai_is_cell, + &thermal_sensors_property, ++ &thermal_sensors_is_cell, + + &deprecated_gpio_property, + &gpios_property, + &interrupts_property, + &interrupt_provider, ++ &interrupt_map, + + &alias_paths, + +@@ -1882,7 +1996,7 @@ static void enable_warning_error(struct + + static void disable_warning_error(struct check *c, bool warn, bool error) + { +- int i; ++ unsigned int i; + + /* Lowering level, also lower it for things this is the prereq + * for */ +@@ -1903,7 +2017,7 @@ static void disable_warning_error(struct + + void parse_checks_option(bool warn, bool error, const char *arg) + { +- int i; ++ unsigned int i; + const char *name = arg; + bool enable = true; + +@@ -1930,7 +2044,7 @@ void parse_checks_option(bool warn, bool + + void process_checks(bool force, struct dt_info *dti) + { +- int i; ++ unsigned int i; + int error = 0; + + for (i = 0; i < ARRAY_SIZE(check_table); i++) { +--- a/scripts/dtc/dtc-lexer.l ++++ b/scripts/dtc/dtc-lexer.l +@@ -57,7 +57,7 @@ static void PRINTF(1, 2) lexical_error(c + push_input_file(name); + } + +-<*>^"#"(line)?[ \t]+[0-9]+[ \t]+{STRING}([ \t]+[0-9]+)? { ++<*>^"#"(line)?[ \t]+[0-9]+[ \t]+{STRING}([ \t]+[0-9]+)* { + char *line, *fnstart, *fnend; + struct data fn; + /* skip text before line # */ +--- a/scripts/dtc/dtc.c ++++ b/scripts/dtc/dtc.c +@@ -12,7 +12,7 @@ + * Command line options + */ + int quiet; /* Level of quietness */ +-int reservenum; /* Number of memory reservation slots */ ++unsigned int reservenum;/* Number of memory reservation slots */ + int minsize; /* Minimum blob size */ + int padsize; /* Additional padding to blob */ + int alignsize; /* Additional padding to blob accroding to the alignsize */ +@@ -197,7 +197,7 @@ int main(int argc, char *argv[]) + depname = optarg; + break; + case 'R': +- reservenum = strtol(optarg, NULL, 0); ++ reservenum = strtoul(optarg, NULL, 0); + break; + case 'S': + minsize = strtol(optarg, NULL, 0); +@@ -359,8 +359,6 @@ int main(int argc, char *argv[]) + #endif + } else if (streq(outform, "dtb")) { + dt_to_blob(outf, dti, outversion); +- } else if (streq(outform, "dtbo")) { +- dt_to_blob(outf, dti, outversion); + } else if (streq(outform, "asm")) { + dt_to_asm(outf, dti, outversion); + } else if (streq(outform, "null")) { +--- a/scripts/dtc/dtc.h ++++ b/scripts/dtc/dtc.h +@@ -35,7 +35,7 @@ + * Command line options + */ + extern int quiet; /* Level of quietness */ +-extern int reservenum; /* Number of memory reservation slots */ ++extern unsigned int reservenum; /* Number of memory reservation slots */ + extern int minsize; /* Minimum blob size */ + extern int padsize; /* Additional padding to blob */ + extern int alignsize; /* Additional padding to blob accroding to the alignsize */ +@@ -51,6 +51,11 @@ extern int annotate; /* annotate .dts w + + typedef uint32_t cell_t; + ++static inline bool phandle_is_valid(cell_t phandle) ++{ ++ return phandle != 0 && phandle != ~0U; ++} ++ + static inline uint16_t dtb_ld16(const void *p) + { + const uint8_t *bp = (const uint8_t *)p; +@@ -86,6 +91,16 @@ static inline uint64_t dtb_ld64(const vo + #define streq(a, b) (strcmp((a), (b)) == 0) + #define strstarts(s, prefix) (strncmp((s), (prefix), strlen(prefix)) == 0) + #define strprefixeq(a, n, b) (strlen(b) == (n) && (memcmp(a, b, n) == 0)) ++static inline bool strends(const char *str, const char *suffix) ++{ ++ unsigned int len, suffix_len; ++ ++ len = strlen(str); ++ suffix_len = strlen(suffix); ++ if (len < suffix_len) ++ return false; ++ return streq(str + len - suffix_len, suffix); ++} + + #define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) + +@@ -101,6 +116,12 @@ enum markertype { + TYPE_UINT64, + TYPE_STRING, + }; ++ ++static inline bool is_type_marker(enum markertype type) ++{ ++ return type >= TYPE_UINT8; ++} ++ + extern const char *markername(enum markertype markertype); + + struct marker { +@@ -125,7 +146,22 @@ struct data { + for_each_marker(m) \ + if ((m)->type == (t)) + +-size_t type_marker_length(struct marker *m); ++static inline struct marker *next_type_marker(struct marker *m) ++{ ++ for_each_marker(m) ++ if (is_type_marker(m->type)) ++ break; ++ return m; ++} ++ ++static inline size_t type_marker_length(struct marker *m) ++{ ++ struct marker *next = next_type_marker(m->next); ++ ++ if (next) ++ return next->offset - m->offset; ++ return 0; ++} + + void data_free(struct data d); + +--- a/scripts/dtc/flattree.c ++++ b/scripts/dtc/flattree.c +@@ -124,7 +124,8 @@ static void asm_emit_cell(void *e, cell_ + { + FILE *f = e; + +- fprintf(f, "\t.byte 0x%02x; .byte 0x%02x; .byte 0x%02x; .byte 0x%02x\n", ++ fprintf(f, "\t.byte\t0x%02x\n" "\t.byte\t0x%02x\n" ++ "\t.byte\t0x%02x\n" "\t.byte\t0x%02x\n", + (val >> 24) & 0xff, (val >> 16) & 0xff, + (val >> 8) & 0xff, val & 0xff); + } +@@ -134,9 +135,9 @@ static void asm_emit_string(void *e, con + FILE *f = e; + + if (len != 0) +- fprintf(f, "\t.string\t\"%.*s\"\n", len, str); ++ fprintf(f, "\t.asciz\t\"%.*s\"\n", len, str); + else +- fprintf(f, "\t.string\t\"%s\"\n", str); ++ fprintf(f, "\t.asciz\t\"%s\"\n", str); + } + + static void asm_emit_align(void *e, int a) +@@ -295,7 +296,7 @@ static struct data flatten_reserve_list( + { + struct reserve_info *re; + struct data d = empty_data; +- int j; ++ unsigned int j; + + for (re = reservelist; re; re = re->next) { + d = data_append_re(d, re->address, re->size); +@@ -438,7 +439,7 @@ static void dump_stringtable_asm(FILE *f + + while (p < (strbuf.val + strbuf.len)) { + len = strlen(p); +- fprintf(f, "\t.string \"%s\"\n", p); ++ fprintf(f, "\t.asciz \"%s\"\n", p); + p += len+1; + } + } +--- a/scripts/dtc/libfdt/fdt.c ++++ b/scripts/dtc/libfdt/fdt.c +@@ -90,6 +90,10 @@ int fdt_check_header(const void *fdt) + { + size_t hdrsize; + ++ /* The device tree must be at an 8-byte aligned address */ ++ if ((uintptr_t)fdt & 7) ++ return -FDT_ERR_ALIGNMENT; ++ + if (fdt_magic(fdt) != FDT_MAGIC) + return -FDT_ERR_BADMAGIC; + if (!can_assume(LATEST)) { +--- a/scripts/dtc/libfdt/fdt_rw.c ++++ b/scripts/dtc/libfdt/fdt_rw.c +@@ -349,7 +349,10 @@ int fdt_add_subnode_namelen(void *fdt, i + return offset; + + /* Try to place the new node after the parent's properties */ +- fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */ ++ tag = fdt_next_tag(fdt, parentoffset, &nextoffset); ++ /* the fdt_subnode_offset_namelen() should ensure this never hits */ ++ if (!can_assume(LIBFDT_FLAWLESS) && (tag != FDT_BEGIN_NODE)) ++ return -FDT_ERR_INTERNAL; + do { + offset = nextoffset; + tag = fdt_next_tag(fdt, offset, &nextoffset); +@@ -391,7 +394,9 @@ int fdt_del_node(void *fdt, int nodeoffs + } + + static void fdt_packblocks_(const char *old, char *new, +- int mem_rsv_size, int struct_size) ++ int mem_rsv_size, ++ int struct_size, ++ int strings_size) + { + int mem_rsv_off, struct_off, strings_off; + +@@ -406,8 +411,7 @@ static void fdt_packblocks_(const char * + fdt_set_off_dt_struct(new, struct_off); + fdt_set_size_dt_struct(new, struct_size); + +- memmove(new + strings_off, old + fdt_off_dt_strings(old), +- fdt_size_dt_strings(old)); ++ memmove(new + strings_off, old + fdt_off_dt_strings(old), strings_size); + fdt_set_off_dt_strings(new, strings_off); + fdt_set_size_dt_strings(new, fdt_size_dt_strings(old)); + } +@@ -467,7 +471,8 @@ int fdt_open_into(const void *fdt, void + return -FDT_ERR_NOSPACE; + } + +- fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size); ++ fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size, ++ fdt_size_dt_strings(fdt)); + memmove(buf, tmp, newsize); + + fdt_set_magic(buf, FDT_MAGIC); +@@ -487,7 +492,8 @@ int fdt_pack(void *fdt) + + mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) + * sizeof(struct fdt_reserve_entry); +- fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt)); ++ fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt), ++ fdt_size_dt_strings(fdt)); + fdt_set_totalsize(fdt, fdt_data_size_(fdt)); + + return 0; +--- a/scripts/dtc/libfdt/fdt_strerror.c ++++ b/scripts/dtc/libfdt/fdt_strerror.c +@@ -39,6 +39,7 @@ static struct fdt_errtabent fdt_errtable + FDT_ERRTABENT(FDT_ERR_BADOVERLAY), + FDT_ERRTABENT(FDT_ERR_NOPHANDLES), + FDT_ERRTABENT(FDT_ERR_BADFLAGS), ++ FDT_ERRTABENT(FDT_ERR_ALIGNMENT), + }; + #define FDT_ERRTABSIZE ((int)(sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))) + +--- a/scripts/dtc/libfdt/libfdt.h ++++ b/scripts/dtc/libfdt/libfdt.h +@@ -131,6 +131,13 @@ uint32_t fdt_next_tag(const void *fdt, i + * to work even with unaligned pointers on platforms (such as ARMv5) that don't + * like unaligned loads and stores. + */ ++static inline uint16_t fdt16_ld(const fdt16_t *p) ++{ ++ const uint8_t *bp = (const uint8_t *)p; ++ ++ return ((uint16_t)bp[0] << 8) | bp[1]; ++} ++ + static inline uint32_t fdt32_ld(const fdt32_t *p) + { + const uint8_t *bp = (const uint8_t *)p; +--- a/scripts/dtc/livetree.c ++++ b/scripts/dtc/livetree.c +@@ -526,7 +526,7 @@ struct node *get_node_by_path(struct nod + p = strchr(path, '/'); + + for_each_child(tree, child) { +- if (p && strprefixeq(path, p - path, child->name)) ++ if (p && strprefixeq(path, (size_t)(p - path), child->name)) + return get_node_by_path(child, p+1); + else if (!p && streq(path, child->name)) + return child; +@@ -559,7 +559,7 @@ struct node *get_node_by_phandle(struct + { + struct node *child, *node; + +- if ((phandle == 0) || (phandle == -1)) { ++ if (!phandle_is_valid(phandle)) { + assert(generate_fixups); + return NULL; + } +@@ -594,7 +594,7 @@ cell_t get_node_phandle(struct node *roo + static cell_t phandle = 1; /* FIXME: ick, static local */ + struct data d = empty_data; + +- if ((node->phandle != 0) && (node->phandle != -1)) ++ if (phandle_is_valid(node->phandle)) + return node->phandle; + + while (get_node_by_phandle(root, phandle)) +--- a/scripts/dtc/treesource.c ++++ b/scripts/dtc/treesource.c +@@ -124,27 +124,6 @@ static void write_propval_int(FILE *f, c + } + } + +-static bool has_data_type_information(struct marker *m) +-{ +- return m->type >= TYPE_UINT8; +-} +- +-static struct marker *next_type_marker(struct marker *m) +-{ +- while (m && !has_data_type_information(m)) +- m = m->next; +- return m; +-} +- +-size_t type_marker_length(struct marker *m) +-{ +- struct marker *next = next_type_marker(m->next); +- +- if (next) +- return next->offset - m->offset; +- return 0; +-} +- + static const char *delim_start[] = { + [TYPE_UINT8] = "[", + [TYPE_UINT16] = "/bits/ 16 <", +@@ -229,26 +208,39 @@ static void write_propval(FILE *f, struc + size_t chunk_len = (m->next ? m->next->offset : len) - m->offset; + size_t data_len = type_marker_length(m) ? : len - m->offset; + const char *p = &prop->val.val[m->offset]; ++ struct marker *m_phandle; + +- if (has_data_type_information(m)) { ++ if (is_type_marker(m->type)) { + emit_type = m->type; + fprintf(f, " %s", delim_start[emit_type]); + } else if (m->type == LABEL) + fprintf(f, " %s:", m->ref); +- else if (m->offset) +- fputc(' ', f); + +- if (emit_type == TYPE_NONE) { +- assert(chunk_len == 0); ++ if (emit_type == TYPE_NONE || chunk_len == 0) + continue; +- } + + switch(emit_type) { + case TYPE_UINT16: + write_propval_int(f, p, chunk_len, 2); + break; + case TYPE_UINT32: +- write_propval_int(f, p, chunk_len, 4); ++ m_phandle = prop->val.markers; ++ for_each_marker_of_type(m_phandle, REF_PHANDLE) ++ if (m->offset == m_phandle->offset) ++ break; ++ ++ if (m_phandle) { ++ if (m_phandle->ref[0] == '/') ++ fprintf(f, "&{%s}", m_phandle->ref); ++ else ++ fprintf(f, "&%s", m_phandle->ref); ++ if (chunk_len > 4) { ++ fputc(' ', f); ++ write_propval_int(f, p + 4, chunk_len - 4, 4); ++ } ++ } else { ++ write_propval_int(f, p, chunk_len, 4); ++ } + break; + case TYPE_UINT64: + write_propval_int(f, p, chunk_len, 8); +--- a/scripts/dtc/util.h ++++ b/scripts/dtc/util.h +@@ -13,10 +13,10 @@ + */ + + #ifdef __GNUC__ +-#ifdef __clang__ +-#define PRINTF(i, j) __attribute__((format (printf, i, j))) +-#else ++#if __GNUC__ >= 5 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4) + #define PRINTF(i, j) __attribute__((format (gnu_printf, i, j))) ++#else ++#define PRINTF(i, j) __attribute__((format (printf, i, j))) + #endif + #define NORETURN __attribute__((noreturn)) + #else +--- a/scripts/dtc/version_gen.h ++++ b/scripts/dtc/version_gen.h +@@ -1 +1 @@ +-#define DTC_VERSION "DTC 1.6.0-g183df9e9" ++#define DTC_VERSION "DTC 1.6.1-g0a3a9d34" +--- a/scripts/dtc/yamltree.c ++++ b/scripts/dtc/yamltree.c +@@ -29,11 +29,12 @@ char *yaml_error_name[] = { + (emitter)->problem, __func__, __LINE__); \ + }) + +-static void yaml_propval_int(yaml_emitter_t *emitter, struct marker *markers, char *data, unsigned int len, int width) ++static void yaml_propval_int(yaml_emitter_t *emitter, struct marker *markers, ++ char *data, unsigned int seq_offset, unsigned int len, int width) + { + yaml_event_t event; + void *tag; +- unsigned int off, start_offset = markers->offset; ++ unsigned int off; + + switch(width) { + case 1: tag = "!u8"; break; +@@ -66,7 +67,7 @@ static void yaml_propval_int(yaml_emitte + m = markers; + is_phandle = false; + for_each_marker_of_type(m, REF_PHANDLE) { +- if (m->offset == (start_offset + off)) { ++ if (m->offset == (seq_offset + off)) { + is_phandle = true; + break; + } +@@ -114,6 +115,7 @@ static void yaml_propval(yaml_emitter_t + yaml_event_t event; + unsigned int len = prop->val.len; + struct marker *m = prop->val.markers; ++ struct marker *markers = prop->val.markers; + + /* Emit the property name */ + yaml_scalar_event_initialize(&event, NULL, +@@ -151,19 +153,19 @@ static void yaml_propval(yaml_emitter_t + + switch(m->type) { + case TYPE_UINT16: +- yaml_propval_int(emitter, m, data, chunk_len, 2); ++ yaml_propval_int(emitter, markers, data, m->offset, chunk_len, 2); + break; + case TYPE_UINT32: +- yaml_propval_int(emitter, m, data, chunk_len, 4); ++ yaml_propval_int(emitter, markers, data, m->offset, chunk_len, 4); + break; + case TYPE_UINT64: +- yaml_propval_int(emitter, m, data, chunk_len, 8); ++ yaml_propval_int(emitter, markers, data, m->offset, chunk_len, 8); + break; + case TYPE_STRING: + yaml_propval_string(emitter, data, chunk_len); + break; + default: +- yaml_propval_int(emitter, m, data, chunk_len, 1); ++ yaml_propval_int(emitter, markers, data, m->offset, chunk_len, 1); + break; + } + } diff --git a/target/linux/generic/pending-5.15/050-dtc-checks-Drop-interrupt-provider-address-cells-check.patch b/target/linux/generic/pending-5.15/050-dtc-checks-Drop-interrupt-provider-address-cells-check.patch deleted file mode 100644 index 75f63728ec..0000000000 --- a/target/linux/generic/pending-5.15/050-dtc-checks-Drop-interrupt-provider-address-cells-check.patch +++ /dev/null @@ -1,28 +0,0 @@ -From d8d1a9a77863a8c7031ae82a1d461aa78eb72a7b Mon Sep 17 00:00:00 2001 -From: Rob Herring -Date: Mon, 11 Oct 2021 14:12:43 -0500 -Subject: [PATCH] checks: Drop interrupt provider '#address-cells' check - -'#address-cells' is only needed when parsing 'interrupt-map' properties, so -remove it from the common interrupt-provider test. - -Cc: Andre Przywara -Reviewed-by: David Gibson -Signed-off-by: Rob Herring -Message-Id: <20211011191245.1009682-3-robh@kernel.org> -Signed-off-by: David Gibson ---- ---- a/scripts/dtc/checks.c -+++ b/scripts/dtc/checks.c -@@ -1569,11 +1569,6 @@ static void check_interrupt_provider(str - if (!prop) - FAIL(c, dti, node, - "Missing #interrupt-cells in interrupt provider"); -- -- prop = get_property(node, "#address-cells"); -- if (!prop) -- FAIL(c, dti, node, -- "Missing #address-cells in interrupt provider"); - } - WARNING(interrupt_provider, check_interrupt_provider, NULL); - From 90629d82daa467c03626b8abc4671046dc548118 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 21 Oct 2022 22:43:07 +0200 Subject: [PATCH 73/80] generic: 5.15: move pending xtx nand patch from pending to backport Move pending xtx nand patch from pending to backport as it got merged upstream. Signed-off-by: Christian Marangi --- ...pinand-Add-support-for-XTX-XT26G0xA.patch} | 36 +++++++++++-------- 1 file changed, 22 insertions(+), 14 deletions(-) rename target/linux/generic/{pending-5.15/483-mtd-spinand-add-support-for-xtx-xt26g0xa.patch => backport-5.15/331-v5.19-mtd-spinand-Add-support-for-XTX-XT26G0xA.patch} (85%) diff --git a/target/linux/generic/pending-5.15/483-mtd-spinand-add-support-for-xtx-xt26g0xa.patch b/target/linux/generic/backport-5.15/331-v5.19-mtd-spinand-Add-support-for-XTX-XT26G0xA.patch similarity index 85% rename from target/linux/generic/pending-5.15/483-mtd-spinand-add-support-for-xtx-xt26g0xa.patch rename to target/linux/generic/backport-5.15/331-v5.19-mtd-spinand-Add-support-for-XTX-XT26G0xA.patch index a73c9fa97d..541d247542 100644 --- a/target/linux/generic/pending-5.15/483-mtd-spinand-add-support-for-xtx-xt26g0xa.patch +++ b/target/linux/generic/backport-5.15/331-v5.19-mtd-spinand-Add-support-for-XTX-XT26G0xA.patch @@ -1,7 +1,7 @@ -From a07e31adf2753cad2fd9790db5bfc047c81e8152 Mon Sep 17 00:00:00 2001 +From f4c5c7f9d2e5ab005d57826b740b694b042a737c Mon Sep 17 00:00:00 2001 From: Felix Matouschek -Date: Fri, 2 Jul 2021 20:31:23 +0200 -Subject: [PATCH] mtd: spinand: Add support for XTX XT26G0xA +Date: Mon, 18 Apr 2022 15:28:03 +0200 +Subject: [PATCH 1/1] mtd: spinand: Add support for XTX XT26G0xA Add support for XTX Technology XT26G01AXXXXX, XTX26G02AXXXXX and XTX26G04AXXXXX SPI NAND. @@ -11,17 +11,18 @@ These are 3V, 1G/2G/4Gbit serial SLC NAND flash devices with on-die ECC Tested on Teltonika RUTX10 flashed with OpenWrt. -Datasheets available at -http://www.xtxtech.com/download/?AId=225 -https://datasheet.lcsc.com/szlcsc/2005251034_XTX-XT26G01AWSEGA_C558841.pdf - +Links: + - http://www.xtxtech.com/download/?AId=225 + - https://datasheet.lcsc.com/szlcsc/2005251034_XTX-XT26G01AWSEGA_C558841.pdf Signed-off-by: Felix Matouschek +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20220418132803.664103-1-felix@matouschek.org --- drivers/mtd/nand/spi/Makefile | 2 +- drivers/mtd/nand/spi/core.c | 1 + - drivers/mtd/nand/spi/xtx.c | 122 ++++++++++++++++++++++++++++++++++ + drivers/mtd/nand/spi/xtx.c | 129 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + - 4 files changed, 125 insertions(+), 1 deletion(-) + 4 files changed, 132 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/spi/xtx.c --- a/drivers/mtd/nand/spi/Makefile @@ -43,7 +44,7 @@ Signed-off-by: Felix Matouschek static int spinand_manufacturer_match(struct spinand_device *spinand, --- /dev/null +++ b/drivers/mtd/nand/spi/xtx.c -@@ -0,0 +1,122 @@ +@@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Author: @@ -109,18 +110,25 @@ Signed-off-by: Felix Matouschek +static int xt26g0xa_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ -+ switch (status & XT26G0XA_STATUS_ECC_MASK) { ++ status = status & XT26G0XA_STATUS_ECC_MASK; ++ ++ switch (status) { + case XT26G0XA_STATUS_ECC_NO_DETECTED: + return 0; + case XT26G0XA_STATUS_ECC_8_CORRECTED: + return 8; + case XT26G0XA_STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; -+ default: /* (1 << 2) through (7 << 2) are 1-7 corrected errors */ -+ return (status & XT26G0XA_STATUS_ECC_MASK) >> 2; ++ default: ++ break; + } + -+ return -EINVAL; ++ /* At this point values greater than (2 << 4) are invalid */ ++ if (status > XT26G0XA_STATUS_ECC_UNCOR_ERROR) ++ return -EINVAL; ++ ++ /* (1 << 2) through (7 << 2) are 1-7 corrected errors */ ++ return status >> 2; +} + +static const struct spinand_info xtx_spinand_table[] = { From d7a6e171c048d07644e3a39e8cefabeb0be06d8d Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 21 Oct 2022 23:08:54 +0200 Subject: [PATCH 74/80] generic: 5.15: move sfp HALNy patch from pending to backport Move sfp HALNy patch from pending to backport as they got merged upstream. The patch was reordered and one was squashed in the upstream variant. Signed-off-by: Christian Marangi --- ...add-support-for-in-band-link-status.patch} | 63 ++++++------ ...e-implement-soft-state-polling-setup.patch | 98 +++++++++++++++++++ ...-sfp-move-quirk-handling-into-sfp.c.patch} | 15 +-- ...ove-Alcatel-Lucent-3FE46541AA-fixup.patch} | 19 ++-- ...1-net-sfp-move-Huawei-MA5671A-fixup.patch} | 13 +-- ...-sfp-add-support-for-HALNy-GPON-SFP.patch} | 41 ++++---- .../790-SFP-GE-T-ignore-TX_FAULT.patch | 6 +- ...774--net-sfp-redo-soft-state-polling.patch | 79 --------------- ...change-HALNy-to-ignore-hardware-pins.patch | 35 ------- 9 files changed, 178 insertions(+), 191 deletions(-) rename target/linux/generic/{pending-5.15/731-net-dsa-mt7530-add-support-for-in-band-link-status.patch => backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch} (63%) create mode 100644 target/linux/generic/backport-5.15/783-v6.1-net-sfp-re-implement-soft-state-polling-setup.patch rename target/linux/generic/{pending-5.15/770-net-sfp-move-quirk-handling-into-sfp.c.patch => backport-5.15/784-v6.1-net-sfp-move-quirk-handling-into-sfp.c.patch} (94%) rename target/linux/generic/{pending-5.15/771-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch => backport-5.15/785-v6.1-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch} (76%) rename target/linux/generic/{pending-5.15/772-net-sfp-move-Huawei-MA5671A-fixup.patch => backport-5.15/786-v6.1-net-sfp-move-Huawei-MA5671A-fixup.patch} (74%) rename target/linux/generic/{pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch => backport-5.15/787-v6.1-net-sfp-add-support-for-HALNy-GPON-SFP.patch} (60%) delete mode 100644 target/linux/generic/pending-5.15/774--net-sfp-redo-soft-state-polling.patch delete mode 100644 target/linux/generic/pending-5.15/775-net-sfp-change-HALNy-to-ignore-hardware-pins.patch diff --git a/target/linux/generic/pending-5.15/731-net-dsa-mt7530-add-support-for-in-band-link-status.patch b/target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch similarity index 63% rename from target/linux/generic/pending-5.15/731-net-dsa-mt7530-add-support-for-in-band-link-status.patch rename to target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch index 8196f19540..7bb6530266 100644 --- a/target/linux/generic/pending-5.15/731-net-dsa-mt7530-add-support-for-in-band-link-status.patch +++ b/target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch @@ -1,37 +1,25 @@ -From 8e18c5fef75debfae3531fbd6901f3bf317d91ed Mon Sep 17 00:00:00 2001 +From e19de30d20809af3221ef8a2648b8a8a52e02d90 Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Fri, 9 Sep 2022 04:28:43 +0100 -Subject: [PATCH] net: dsa: mt7530: add support for in-band link status -To: linux-mediatek@lists.infradead.org, - netdev@vger.kernel.org -Cc: Russell King , - Sean Wang , - Landen Chao , - DENG Qingfang , - Andrew Lunn , - Vivien Didelot , - Florian Fainelli , - Vladimir Oltean , - David S. Miller , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Matthias Brugger , - Philipp Zabel +Date: Wed, 21 Sep 2022 01:23:14 +0100 +Subject: [PATCH 1/1] net: dsa: mt7530: add support for in-band link status Read link status from SGMII PCS for in-band managed 2500Base-X and 1000Base-X connection on a MAC port of the MT7531. This is needed to get the SFP cage working which is connected to SGMII interface of port 5 of the MT7531 switch IC on the Bananapi BPi-R3 board. +While at it also handle an_complete for both the autoneg and the +non-autoneg codepath. Signed-off-by: Daniel Golle +Signed-off-by: David S. Miller --- - drivers/net/dsa/mt7530.c | 48 +++++++++++++++++++++++++++++----------- - 1 file changed, 35 insertions(+), 13 deletions(-) + drivers/net/dsa/mt7530.c | 50 +++++++++++++++++++++++++++++----------- + drivers/net/dsa/mt7530.h | 1 + + 2 files changed, 38 insertions(+), 13 deletions(-) --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2703,9 +2703,6 @@ mt7531_mac_config(struct dsa_switch *ds, +@@ -2699,9 +2699,6 @@ mt7531_mac_config(struct dsa_switch *ds, case PHY_INTERFACE_MODE_NA: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: @@ -41,7 +29,7 @@ Signed-off-by: Daniel Golle return mt7531_sgmii_setup_mode_force(priv, port, interface); default: return -EINVAL; -@@ -2781,13 +2778,6 @@ unsupported: +@@ -2777,13 +2774,6 @@ unsupported: return; } @@ -55,7 +43,7 @@ Signed-off-by: Daniel Golle mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); mcr_new = mcr_cur; mcr_new &= ~PMCR_LINK_SETTINGS_MASK; -@@ -2924,6 +2914,9 @@ static void mt753x_phylink_get_caps(stru +@@ -2920,6 +2910,9 @@ static void mt753x_phylink_get_caps(stru config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; @@ -65,7 +53,15 @@ Signed-off-by: Daniel Golle /* This driver does not make use of the speed, duplex, pause or the * advertisement in its mac_config, so it is safe to mark this driver * as non-legacy. -@@ -3019,16 +3012,43 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 +@@ -2985,6 +2978,7 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 + + status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); + state->link = !!(status & MT7531_SGMII_LINK_STATUS); ++ state->an_complete = !!(status & MT7531_SGMII_AN_COMPLETE); + if (state->interface == PHY_INTERFACE_MODE_SGMII && + (status & MT7531_SGMII_AN_ENABLE)) { + val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); +@@ -3015,16 +3009,44 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 return 0; } @@ -80,13 +76,15 @@ Signed-off-by: Daniel Golle + if (!state->link) + return; + ++ state->an_complete = state->link; ++ + if (state->interface == PHY_INTERFACE_MODE_2500BASEX) + state->speed = SPEED_2500; + else + state->speed = SPEED_1000; + + state->duplex = DUPLEX_FULL; -+ state->pause = 0; ++ state->pause = MLO_PAUSE_NONE; +} + static void mt7531_pcs_get_state(struct phylink_pcs *pcs, @@ -94,7 +92,6 @@ Signed-off-by: Daniel Golle { struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; int port = pcs_to_mt753x_pcs(pcs)->port; -+ unsigned int val; - if (state->interface == PHY_INTERFACE_MODE_SGMII) + if (state->interface == PHY_INTERFACE_MODE_SGMII) { @@ -112,7 +109,7 @@ Signed-off-by: Daniel Golle } static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, -@@ -3069,6 +3089,8 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3065,6 +3087,8 @@ mt753x_setup(struct dsa_switch *ds) priv->pcs[i].pcs.ops = priv->info->pcs_ops; priv->pcs[i].priv = priv; priv->pcs[i].port = i; @@ -121,3 +118,13 @@ Signed-off-by: Daniel Golle } ret = priv->info->sw_setup(ds); +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -373,6 +373,7 @@ enum mt7530_vlan_port_acc_frm { + #define MT7531_SGMII_LINK_STATUS BIT(18) + #define MT7531_SGMII_AN_ENABLE BIT(12) + #define MT7531_SGMII_AN_RESTART BIT(9) ++#define MT7531_SGMII_AN_COMPLETE BIT(21) + + /* Register for SGMII PCS_SPPED_ABILITY */ + #define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08) diff --git a/target/linux/generic/backport-5.15/783-v6.1-net-sfp-re-implement-soft-state-polling-setup.patch b/target/linux/generic/backport-5.15/783-v6.1-net-sfp-re-implement-soft-state-polling-setup.patch new file mode 100644 index 0000000000..6f69b7ddfe --- /dev/null +++ b/target/linux/generic/backport-5.15/783-v6.1-net-sfp-re-implement-soft-state-polling-setup.patch @@ -0,0 +1,98 @@ +From 8475c4b70b040f9d8cbc308100f2c4d865f810b3 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 13 Sep 2022 20:06:27 +0100 +Subject: [PATCH 1/1] net: sfp: re-implement soft state polling setup + +Re-implement the decision making for soft state polling. Instead of +generating the soft state mask in sfp_soft_start_poll() by looking at +which GPIOs are available, record their availability in +sfp_sm_mod_probe() in sfp->state_hw_mask. + +This will then allow us to clear bits in sfp->state_hw_mask in module +specific quirks when the hardware signals should not be used, thereby +allowing us to switch to using the software state polling. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/sfp.c | 38 ++++++++++++++++++++++++++------------ + 1 file changed, 26 insertions(+), 12 deletions(-) + +--- a/drivers/net/phy/sfp.c ++++ b/drivers/net/phy/sfp.c +@@ -234,6 +234,7 @@ struct sfp { + bool need_poll; + + struct mutex st_mutex; /* Protects state */ ++ unsigned int state_hw_mask; + unsigned int state_soft_mask; + unsigned int state; + struct delayed_work poll; +@@ -499,17 +500,18 @@ static void sfp_soft_set_state(struct sf + static void sfp_soft_start_poll(struct sfp *sfp) + { + const struct sfp_eeprom_id *id = &sfp->id; ++ unsigned int mask = 0; + + sfp->state_soft_mask = 0; +- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_DISABLE && +- !sfp->gpio[GPIO_TX_DISABLE]) +- sfp->state_soft_mask |= SFP_F_TX_DISABLE; +- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_FAULT && +- !sfp->gpio[GPIO_TX_FAULT]) +- sfp->state_soft_mask |= SFP_F_TX_FAULT; +- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_RX_LOS && +- !sfp->gpio[GPIO_LOS]) +- sfp->state_soft_mask |= SFP_F_LOS; ++ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_DISABLE) ++ mask |= SFP_F_TX_DISABLE; ++ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_FAULT) ++ mask |= SFP_F_TX_FAULT; ++ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_RX_LOS) ++ mask |= SFP_F_LOS; ++ ++ // Poll the soft state for hardware pins we want to ignore ++ sfp->state_soft_mask = ~sfp->state_hw_mask & mask; + + if (sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT) && + !sfp->need_poll) +@@ -523,10 +525,11 @@ static void sfp_soft_stop_poll(struct sf + + static unsigned int sfp_get_state(struct sfp *sfp) + { +- unsigned int state = sfp->get_state(sfp); ++ unsigned int soft = sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT); ++ unsigned int state; + +- if (state & SFP_F_PRESENT && +- sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT)) ++ state = sfp->get_state(sfp) & sfp->state_hw_mask; ++ if (state & SFP_F_PRESENT && soft) + state |= sfp_soft_get_state(sfp); + + return state; +@@ -1940,6 +1943,15 @@ static int sfp_sm_mod_probe(struct sfp * + if (ret < 0) + return ret; + ++ /* Initialise state bits to use from hardware */ ++ sfp->state_hw_mask = SFP_F_PRESENT; ++ if (sfp->gpio[GPIO_TX_DISABLE]) ++ sfp->state_hw_mask |= SFP_F_TX_DISABLE; ++ if (sfp->gpio[GPIO_TX_FAULT]) ++ sfp->state_hw_mask |= SFP_F_TX_FAULT; ++ if (sfp->gpio[GPIO_LOS]) ++ sfp->state_hw_mask |= SFP_F_LOS; ++ + if (!memcmp(id.base.vendor_name, "ALCATELLUCENT ", 16) && + !memcmp(id.base.vendor_pn, "3FE46541AA ", 16)) + sfp->module_t_start_up = T_START_UP_BAD_GPON; +@@ -2565,6 +2577,8 @@ static int sfp_probe(struct platform_dev + return PTR_ERR(sfp->gpio[i]); + } + ++ sfp->state_hw_mask = SFP_F_PRESENT; ++ + sfp->get_state = sfp_gpio_get_state; + sfp->set_state = sfp_gpio_set_state; + diff --git a/target/linux/generic/pending-5.15/770-net-sfp-move-quirk-handling-into-sfp.c.patch b/target/linux/generic/backport-5.15/784-v6.1-net-sfp-move-quirk-handling-into-sfp.c.patch similarity index 94% rename from target/linux/generic/pending-5.15/770-net-sfp-move-quirk-handling-into-sfp.c.patch rename to target/linux/generic/backport-5.15/784-v6.1-net-sfp-move-quirk-handling-into-sfp.c.patch index 8d43ccb3e9..e5f8031636 100644 --- a/target/linux/generic/pending-5.15/770-net-sfp-move-quirk-handling-into-sfp.c.patch +++ b/target/linux/generic/backport-5.15/784-v6.1-net-sfp-move-quirk-handling-into-sfp.c.patch @@ -1,13 +1,14 @@ -From a4648a1957cd79bc389538aa0472db39a56e3df6 Mon Sep 17 00:00:00 2001 +From 23571c7b96437483d28a990c906cc81f5f66374e Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" -Date: Fri, 26 Aug 2022 08:43:30 +0100 -Subject: [PATCH 1/6] net: sfp: move quirk handling into sfp.c +Date: Tue, 13 Sep 2022 20:06:32 +0100 +Subject: [PATCH 1/1] net: sfp: move quirk handling into sfp.c We need to handle more quirks than just those which affect the link modes of the module. Move the quirk lookup into sfp.c, and pass the quirk to sfp-bus.c Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski --- drivers/net/phy/sfp-bus.c | 98 ++------------------------------------- drivers/net/phy/sfp.c | 94 ++++++++++++++++++++++++++++++++++++- @@ -141,7 +142,7 @@ Signed-off-by: Russell King (Oracle) ret = ops->module_insert(bus->upstream, id); --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c -@@ -252,6 +252,8 @@ struct sfp { +@@ -253,6 +253,8 @@ struct sfp { unsigned int module_t_start_up; bool tx_fault_ignore; @@ -150,7 +151,7 @@ Signed-off-by: Russell King (Oracle) #if IS_ENABLED(CONFIG_HWMON) struct sfp_diag diag; struct delayed_work hwmon_probe; -@@ -308,6 +310,93 @@ static const struct of_device_id sfp_of_ +@@ -309,6 +311,93 @@ static const struct of_device_id sfp_of_ }; MODULE_DEVICE_TABLE(of, sfp_of_match); @@ -244,7 +245,7 @@ Signed-off-by: Russell King (Oracle) static unsigned long poll_jiffies; static unsigned int sfp_gpio_get_state(struct sfp *sfp) -@@ -1952,6 +2041,8 @@ static int sfp_sm_mod_probe(struct sfp * +@@ -1964,6 +2053,8 @@ static int sfp_sm_mod_probe(struct sfp * else sfp->tx_fault_ignore = false; @@ -253,7 +254,7 @@ Signed-off-by: Russell King (Oracle) return 0; } -@@ -2063,7 +2154,8 @@ static void sfp_sm_module(struct sfp *sf +@@ -2075,7 +2166,8 @@ static void sfp_sm_module(struct sfp *sf break; /* Report the module insertion to the upstream device */ diff --git a/target/linux/generic/pending-5.15/771-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch b/target/linux/generic/backport-5.15/785-v6.1-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch similarity index 76% rename from target/linux/generic/pending-5.15/771-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch rename to target/linux/generic/backport-5.15/785-v6.1-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch index f285561ebb..aa3112e585 100644 --- a/target/linux/generic/pending-5.15/771-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch +++ b/target/linux/generic/backport-5.15/785-v6.1-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch @@ -1,12 +1,13 @@ -From 21fdd8281de3022aee35dd5bfccc892bd46529a3 Mon Sep 17 00:00:00 2001 +From 275416754e9a262c97a1ad6f806a4bc6e0464aa2 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" -Date: Fri, 26 Aug 2022 08:43:35 +0100 -Subject: [PATCH 2/6] net: sfp: move Alcatel Lucent 3FE46541AA fixup +Date: Tue, 13 Sep 2022 20:06:37 +0100 +Subject: [PATCH 1/1] net: sfp: move Alcatel Lucent 3FE46541AA fixup Add a new fixup mechanism to the SFP quirks, and use it for this module. Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski --- drivers/net/phy/sfp.c | 14 +++++++++----- drivers/net/phy/sfp.h | 1 + @@ -14,7 +15,7 @@ Signed-off-by: Russell King (Oracle) --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c -@@ -310,6 +310,11 @@ static const struct of_device_id sfp_of_ +@@ -311,6 +311,11 @@ static const struct of_device_id sfp_of_ }; MODULE_DEVICE_TABLE(of, sfp_of_match); @@ -26,7 +27,7 @@ Signed-off-by: Russell King (Oracle) static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, unsigned long *modes) { -@@ -340,6 +345,7 @@ static const struct sfp_quirk sfp_quirks +@@ -341,6 +346,7 @@ static const struct sfp_quirk sfp_quirks .vendor = "ALCATELLUCENT", .part = "3FE46541AA", .modes = sfp_quirk_2500basex, @@ -34,9 +35,9 @@ Signed-off-by: Russell King (Oracle) }, { // Huawei MA5671A can operate at 2500base-X, but report 1.2GBd // NRZ in their EEPROM -@@ -2029,11 +2035,7 @@ static int sfp_sm_mod_probe(struct sfp * - if (ret < 0) - return ret; +@@ -2041,11 +2047,7 @@ static int sfp_sm_mod_probe(struct sfp * + if (sfp->gpio[GPIO_LOS]) + sfp->state_hw_mask |= SFP_F_LOS; - if (!memcmp(id.base.vendor_name, "ALCATELLUCENT ", 16) && - !memcmp(id.base.vendor_pn, "3FE46541AA ", 16)) @@ -47,7 +48,7 @@ Signed-off-by: Russell King (Oracle) if (!memcmp(id.base.vendor_name, "HUAWEI ", 16) && !memcmp(id.base.vendor_pn, "MA5671A ", 16)) -@@ -2042,6 +2044,8 @@ static int sfp_sm_mod_probe(struct sfp * +@@ -2054,6 +2056,8 @@ static int sfp_sm_mod_probe(struct sfp * sfp->tx_fault_ignore = false; sfp->quirk = sfp_lookup_quirk(&id); diff --git a/target/linux/generic/pending-5.15/772-net-sfp-move-Huawei-MA5671A-fixup.patch b/target/linux/generic/backport-5.15/786-v6.1-net-sfp-move-Huawei-MA5671A-fixup.patch similarity index 74% rename from target/linux/generic/pending-5.15/772-net-sfp-move-Huawei-MA5671A-fixup.patch rename to target/linux/generic/backport-5.15/786-v6.1-net-sfp-move-Huawei-MA5671A-fixup.patch index dfd08af671..14b0f9b8c3 100644 --- a/target/linux/generic/pending-5.15/772-net-sfp-move-Huawei-MA5671A-fixup.patch +++ b/target/linux/generic/backport-5.15/786-v6.1-net-sfp-move-Huawei-MA5671A-fixup.patch @@ -1,18 +1,19 @@ -From 4c9d8c654827ef42da702c5b6c3392e8ac0bc60a Mon Sep 17 00:00:00 2001 +From 5029be761161374a3624aa7b4670174c35449bf5 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" -Date: Fri, 26 Aug 2022 08:43:40 +0100 -Subject: [PATCH 3/6] net: sfp: move Huawei MA5671A fixup +Date: Tue, 13 Sep 2022 20:06:42 +0100 +Subject: [PATCH 1/1] net: sfp: move Huawei MA5671A fixup Move this module over to the new fixup mechanism. Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski --- drivers/net/phy/sfp.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c -@@ -315,6 +315,11 @@ static void sfp_fixup_long_startup(struc +@@ -316,6 +316,11 @@ static void sfp_fixup_long_startup(struc sfp->module_t_start_up = T_START_UP_BAD_GPON; } @@ -24,7 +25,7 @@ Signed-off-by: Russell King (Oracle) static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, unsigned long *modes) { -@@ -352,6 +357,7 @@ static const struct sfp_quirk sfp_quirks +@@ -353,6 +358,7 @@ static const struct sfp_quirk sfp_quirks .vendor = "HUAWEI", .part = "MA5671A", .modes = sfp_quirk_2500basex, @@ -32,7 +33,7 @@ Signed-off-by: Russell King (Oracle) }, { // Lantech 8330-262D-E can operate at 2500base-X, but // incorrectly report 2500MBd NRZ in their EEPROM -@@ -2037,11 +2043,7 @@ static int sfp_sm_mod_probe(struct sfp * +@@ -2049,11 +2055,7 @@ static int sfp_sm_mod_probe(struct sfp * sfp->module_t_start_up = T_START_UP; diff --git a/target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch b/target/linux/generic/backport-5.15/787-v6.1-net-sfp-add-support-for-HALNy-GPON-SFP.patch similarity index 60% rename from target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch rename to target/linux/generic/backport-5.15/787-v6.1-net-sfp-add-support-for-HALNy-GPON-SFP.patch index 85c1d5b203..0c65de5ab8 100644 --- a/target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch +++ b/target/linux/generic/backport-5.15/787-v6.1-net-sfp-add-support-for-HALNy-GPON-SFP.patch @@ -1,18 +1,19 @@ -From 43ac680124bc57951a6d0356b41498c2324388bf Mon Sep 17 00:00:00 2001 +From 73472c830eae5fce2107f7f086f1e6827d215caf Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" -Date: Fri, 26 Aug 2022 08:43:45 +0100 -Subject: [PATCH 4/6] net: sfp: add support for HALNy GPON SFP +Date: Tue, 13 Sep 2022 20:06:48 +0100 +Subject: [PATCH 1/1] net: sfp: add support for HALNy GPON SFP Add a quirk for the HALNy HL-GSFP module, which appears to have an -inverted RX_LOS signal, and possibly uses TX_FAULT as an inverted -host-link status signal. As we can't be certain about the modules -use of TX_FAULT, we ignore it. +inverted RX_LOS signal, and maybe uses TX_FAULT as a serial port +transmit pin. Rather than use these hardware signals, switch to +using software polling for these status signals. Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski --- drivers/net/phy/sfp-bus.c | 2 +- - drivers/net/phy/sfp.c | 29 ++++++++++++++++++++++++++--- - 2 files changed, 27 insertions(+), 4 deletions(-) + drivers/net/phy/sfp.c | 21 ++++++++++++++++++--- + 2 files changed, 19 insertions(+), 4 deletions(-) --- a/drivers/net/phy/sfp-bus.c +++ b/drivers/net/phy/sfp-bus.c @@ -27,31 +28,23 @@ Signed-off-by: Russell King (Oracle) linkmode_or(support, support, modes); --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c -@@ -320,6 +320,23 @@ static void sfp_fixup_ignore_tx_fault(st +@@ -321,6 +321,15 @@ static void sfp_fixup_ignore_tx_fault(st sfp->tx_fault_ignore = true; } -+static void sfp_fixup_inverted_los(struct sfp *sfp) -+{ -+ const __be16 los_inverted = cpu_to_be16(SFP_OPTIONS_LOS_INVERTED); -+ const __be16 los_normal = cpu_to_be16(SFP_OPTIONS_LOS_NORMAL); -+ -+ sfp->id.ext.options &= ~los_normal; -+ sfp->id.ext.options |= los_inverted; -+} -+ +static void sfp_fixup_halny_gsfp(struct sfp *sfp) +{ -+ /* LOS is inverted */ -+ sfp_fixup_inverted_los(sfp); -+ /* TX fault might be inverted, but we don't know for certain. */ -+ sfp_fixup_ignore_tx_fault(sfp); ++ /* Ignore the TX_FAULT and LOS signals on this module. ++ * these are possibly used for other purposes on this ++ * module, e.g. a serial port. ++ */ ++ sfp->state_hw_mask &= ~(SFP_F_TX_FAULT | SFP_F_LOS); +} + static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, unsigned long *modes) { -@@ -352,6 +369,10 @@ static const struct sfp_quirk sfp_quirks +@@ -353,6 +362,10 @@ static const struct sfp_quirk sfp_quirks .modes = sfp_quirk_2500basex, .fixup = sfp_fixup_long_startup, }, { @@ -62,7 +55,7 @@ Signed-off-by: Russell King (Oracle) // Huawei MA5671A can operate at 2500base-X, but report 1.2GBd // NRZ in their EEPROM .vendor = "HUAWEI", -@@ -368,16 +389,18 @@ static const struct sfp_quirk sfp_quirks +@@ -369,16 +382,18 @@ static const struct sfp_quirk sfp_quirks .vendor = "UBNT", .part = "UF-INSTANT", .modes = sfp_quirk_ubnt_uf_instant, diff --git a/target/linux/generic/hack-5.15/790-SFP-GE-T-ignore-TX_FAULT.patch b/target/linux/generic/hack-5.15/790-SFP-GE-T-ignore-TX_FAULT.patch index d9835f8896..83b2c304e2 100644 --- a/target/linux/generic/hack-5.15/790-SFP-GE-T-ignore-TX_FAULT.patch +++ b/target/linux/generic/hack-5.15/790-SFP-GE-T-ignore-TX_FAULT.patch @@ -26,7 +26,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c -@@ -369,6 +369,11 @@ static const struct sfp_quirk sfp_quirks +@@ -373,6 +373,11 @@ static const struct sfp_quirk sfp_quirks .modes = sfp_quirk_2500basex, .fixup = sfp_fixup_ignore_tx_fault, }, { @@ -38,7 +38,7 @@ Signed-off-by: Daniel Golle // Lantech 8330-262D-E can operate at 2500base-X, but // incorrectly report 2500MBd NRZ in their EEPROM .vendor = "Lantech", -@@ -2303,7 +2308,8 @@ static void sfp_sm_main(struct sfp *sfp, +@@ -2306,7 +2311,8 @@ static void sfp_sm_main(struct sfp *sfp, * or t_start_up, so assume there is a fault. */ sfp_sm_fault(sfp, SFP_S_INIT_TX_FAULT, @@ -48,7 +48,7 @@ Signed-off-by: Daniel Golle } else if (event == SFP_E_TIMEOUT || event == SFP_E_TX_CLEAR) { init_done: sfp->sm_phy_retries = R_PHY_RETRY; -@@ -2526,10 +2532,12 @@ static void sfp_check_state(struct sfp * +@@ -2529,10 +2535,12 @@ static void sfp_check_state(struct sfp * mutex_lock(&sfp->st_mutex); state = sfp_get_state(sfp); changed = state ^ sfp->state; diff --git a/target/linux/generic/pending-5.15/774--net-sfp-redo-soft-state-polling.patch b/target/linux/generic/pending-5.15/774--net-sfp-redo-soft-state-polling.patch deleted file mode 100644 index 3aa51deb3c..0000000000 --- a/target/linux/generic/pending-5.15/774--net-sfp-redo-soft-state-polling.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 9a84d699ddde0d4e272aa919ad8fd50271a3f932 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Fri, 26 Aug 2022 08:48:20 +0100 -Subject: [PATCH 5/6] net: sfp: redo soft state polling - -Signed-off-by: Russell King (Oracle) ---- - drivers/net/phy/sfp.c | 35 ++++++++++++++++++++++++----------- - 1 file changed, 24 insertions(+), 11 deletions(-) - ---- a/drivers/net/phy/sfp.c -+++ b/drivers/net/phy/sfp.c -@@ -234,6 +234,7 @@ struct sfp { - bool need_poll; - - struct mutex st_mutex; /* Protects state */ -+ unsigned int state_ignore_hw_mask; - unsigned int state_soft_mask; - unsigned int state; - struct delayed_work poll; -@@ -623,17 +624,18 @@ static void sfp_soft_set_state(struct sf - static void sfp_soft_start_poll(struct sfp *sfp) - { - const struct sfp_eeprom_id *id = &sfp->id; -+ unsigned int mask = 0; - - sfp->state_soft_mask = 0; -- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_DISABLE && -- !sfp->gpio[GPIO_TX_DISABLE]) -- sfp->state_soft_mask |= SFP_F_TX_DISABLE; -- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_FAULT && -- !sfp->gpio[GPIO_TX_FAULT]) -- sfp->state_soft_mask |= SFP_F_TX_FAULT; -- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_RX_LOS && -- !sfp->gpio[GPIO_LOS]) -- sfp->state_soft_mask |= SFP_F_LOS; -+ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_DISABLE) -+ mask |= SFP_F_TX_DISABLE; -+ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_FAULT) -+ mask |= SFP_F_TX_FAULT; -+ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_RX_LOS) -+ mask |= SFP_F_LOS; -+ -+ // Poll the soft state for hardware pins we want to ignore -+ sfp->state_soft_mask = sfp->state_ignore_hw_mask & mask; - - if (sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT) && - !sfp->need_poll) -@@ -647,10 +649,12 @@ static void sfp_soft_stop_poll(struct sf - - static unsigned int sfp_get_state(struct sfp *sfp) - { -+ unsigned int soft = sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT); - unsigned int state = sfp->get_state(sfp); - -- if (state & SFP_F_PRESENT && -- sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT)) -+ state &= ~sfp->state_ignore_hw_mask; -+ -+ if (state & SFP_F_PRESENT && soft) - state |= sfp_soft_get_state(sfp); - - return state; -@@ -2064,6 +2068,15 @@ static int sfp_sm_mod_probe(struct sfp * - if (ret < 0) - return ret; - -+ /* Initialise state bits to ignore from hardware */ -+ sfp->state_ignore_hw_mask = 0; -+ if (!sfp->gpio[GPIO_TX_DISABLE]) -+ sfp->state_ignore_hw_mask |= SFP_F_TX_DISABLE; -+ if (!sfp->gpio[GPIO_TX_FAULT]) -+ sfp->state_ignore_hw_mask |= SFP_F_TX_FAULT; -+ if (!sfp->gpio[GPIO_LOS]) -+ sfp->state_ignore_hw_mask |= SFP_F_LOS; -+ - sfp->module_t_start_up = T_START_UP; - - sfp->tx_fault_ignore = false; diff --git a/target/linux/generic/pending-5.15/775-net-sfp-change-HALNy-to-ignore-hardware-pins.patch b/target/linux/generic/pending-5.15/775-net-sfp-change-HALNy-to-ignore-hardware-pins.patch deleted file mode 100644 index 7aa29cd722..0000000000 --- a/target/linux/generic/pending-5.15/775-net-sfp-change-HALNy-to-ignore-hardware-pins.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 32a59a1c5dc8f6fa755bab9a5f9751fdb66bb234 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Fri, 26 Aug 2022 08:48:25 +0100 -Subject: [PATCH 6/6] net: sfp: change HALNy to ignore hardware pins - -Signed-off-by: Russell King (Oracle) ---- - drivers/net/phy/sfp.c | 14 +------------- - 1 file changed, 1 insertion(+), 13 deletions(-) - ---- a/drivers/net/phy/sfp.c -+++ b/drivers/net/phy/sfp.c -@@ -321,21 +321,9 @@ static void sfp_fixup_ignore_tx_fault(st - sfp->tx_fault_ignore = true; - } - --static void sfp_fixup_inverted_los(struct sfp *sfp) --{ -- const __be16 los_inverted = cpu_to_be16(SFP_OPTIONS_LOS_INVERTED); -- const __be16 los_normal = cpu_to_be16(SFP_OPTIONS_LOS_NORMAL); -- -- sfp->id.ext.options &= ~los_normal; -- sfp->id.ext.options |= los_inverted; --} -- - static void sfp_fixup_halny_gsfp(struct sfp *sfp) - { -- /* LOS is inverted */ -- sfp_fixup_inverted_los(sfp); -- /* TX fault might be inverted, but we don't know for certain. */ -- sfp_fixup_ignore_tx_fault(sfp); -+ sfp->state_ignore_hw_mask |= SFP_F_TX_FAULT | SFP_F_LOS; - } - - static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, From a1522ec156ff5b5aabe79c53450ff5d02598dd20 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 21 Oct 2022 23:19:44 +0200 Subject: [PATCH 75/80] generic: 5.15: move mtk eth soc patch from pending to backport Move mtk eth soc patch from pending to backport as it got merged upstream. Signed-off-by: Christian Marangi --- ...eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch} | 23 ++++------------ ...eth_soc-fix-state-in-__mtk_foe_entr.patch} | 26 +++++-------------- 2 files changed, 11 insertions(+), 38 deletions(-) rename target/linux/generic/{pending-5.15/781-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch => backport-5.15/788-v6.0-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch} (57%) rename target/linux/generic/{pending-5.15/782-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch => backport-5.15/789-v6.1-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch} (58%) diff --git a/target/linux/generic/pending-5.15/781-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch b/target/linux/generic/backport-5.15/788-v6.0-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch similarity index 57% rename from target/linux/generic/pending-5.15/781-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch rename to target/linux/generic/backport-5.15/788-v6.0-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch index 65845ea4c6..27c719b663 100644 --- a/target/linux/generic/pending-5.15/781-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch +++ b/target/linux/generic/backport-5.15/788-v6.0-net-ethernet-mtk_eth_soc-fix-mask-of-RX_DMA_GET_SPOR.patch @@ -1,23 +1,8 @@ -From 8743af8a77dd909970462ca578358128cce5d027 Mon Sep 17 00:00:00 2001 +From c9da02bfb1112461e048d3b736afb1873f6f4ccf Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Tue, 27 Sep 2022 15:39:39 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: fix mask of +Date: Tue, 27 Sep 2022 16:30:02 +0100 +Subject: [PATCH 1/1] net: ethernet: mtk_eth_soc: fix mask of RX_DMA_GET_SPORT{,_V2} -To: linux-mediatek@lists.infradead.org, - netdev@vger.kernel.org, - Lorenzo Bianconi -Cc: Sujuan Chen , - Bo Jiao , - Felix Fietkau , - John Crispin , - Sean Wang , - Mark Lee , - David S. Miller , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Matthias Brugger , - Chen Minqiang The bitmasks applied in RX_DMA_GET_SPORT and RX_DMA_GET_SPORT_V2 macros were swapped. Fix that. @@ -26,6 +11,8 @@ Reported-by: Chen Minqiang Fixes: 160d3a9b192985 ("net: ethernet: mtk_eth_soc: introduce MTK_NETSYS_V2 support") Acked-by: Lorenzo Bianconi Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/YzMW+mg9UsaCdKRQ@makrotopia.org +Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/generic/pending-5.15/782-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch b/target/linux/generic/backport-5.15/789-v6.1-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch similarity index 58% rename from target/linux/generic/pending-5.15/782-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch rename to target/linux/generic/backport-5.15/789-v6.1-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch index cc71ec60f3..11465c1c5b 100644 --- a/target/linux/generic/pending-5.15/782-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch +++ b/target/linux/generic/backport-5.15/789-v6.1-net-ethernet-mtk_eth_soc-fix-state-in-__mtk_foe_entr.patch @@ -1,24 +1,8 @@ -From cd8e1f340c3e571b78952d4ca2c128d183a47cc2 Mon Sep 17 00:00:00 2001 +From ae3ed15da5889263de372ff9df2e83e16acca4cb Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Wed, 28 Sep 2022 02:17:02 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: fix state in +Date: Fri, 30 Sep 2022 01:56:53 +0100 +Subject: [PATCH 1/1] net: ethernet: mtk_eth_soc: fix state in __mtk_foe_entry_clear -To: linux-mediatek@lists.infradead.org, - netdev@vger.kernel.org, - Lorenzo Bianconi -Cc: Sujuan Chen , - Bo Jiao , - Felix Fietkau , - John Crispin , - Sean Wang , - Mark Lee , - David S. Miller , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Matthias Brugger , - Chen Minqiang , - Thomas Hühn Setting ib1 state to MTK_FOE_STATE_UNBIND in __mtk_foe_entry_clear routine as done by commit 0e80707d94e4c8 ("net: ethernet: mtk_eth_soc: @@ -32,8 +16,10 @@ Tested on MT7622 (Linksys E8450) and MT7986 (BananaPi BPI-R3). Suggested-by: Felix Fietkau Fixes: 0e80707d94e4c8 ("net: ethernet: mtk_eth_soc: fix typo in __mtk_foe_entry_clear") -Fixes: 33fc42de33278 ("net: ethernet: mtk_eth_soc: support creating mac address based offload entries") +Fixes: 33fc42de33278b ("net: ethernet: mtk_eth_soc: support creating mac address based offload entries") Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/YzY+1Yg0FBXcnrtc@makrotopia.org +Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/mediatek/mtk_ppe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) From e25890ce45c3bf94d7cd77630771decf54211352 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 21 Oct 2022 23:29:39 +0200 Subject: [PATCH 76/80] generic: 5.15: move bluetooth mt79 usb id patch from pending to backport Move bluetooth mt79 usb id patch from pending to backport as it got merged upstream. Signed-off-by: Christian Marangi --- ...tusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch} | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) rename target/linux/generic/{pending-5.15/825-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch => backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch} (86%) diff --git a/target/linux/generic/pending-5.15/825-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch b/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch similarity index 86% rename from target/linux/generic/pending-5.15/825-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch rename to target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch index 4f9dfc2755..8957ff8e22 100644 --- a/target/linux/generic/pending-5.15/825-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch +++ b/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch @@ -1,13 +1,7 @@ -From ced9d535126a81a85b022cff1e2fd8e0da46c7ae Mon Sep 17 00:00:00 2001 +From be55622ce673f9692cc15d26d77a050cda42a3d3 Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Fri, 9 Sep 2022 18:25:21 +0100 -Subject: [PATCH] Bluetooth: btusb: Add a new VID/PID 0e8d/0608 for MT7921 -To: linux-mediatek@lists.infradead.org, - linux-bluetooth@vger.kernel.org -Cc: Matthias Brugger , - Luiz Augusto von Dentz , - Johan Hedberg , - Marcel Holtmann +Date: Fri, 9 Sep 2022 21:00:30 +0100 +Subject: [PATCH 1/1] Bluetooth: btusb: Add a new VID/PID 0e8d/0608 for MT7921 Add a new PID/VID 0e8d/0608 for MT7921K chip found on AMD RZ608 module. @@ -53,6 +47,7 @@ E: Ad=8a(I) Atr=03(Int.) MxPS= 64 Ivl=125us E: Ad=0a(O) Atr=03(Int.) MxPS= 64 Ivl=125us Signed-off-by: Daniel Golle +Signed-off-by: Luiz Augusto von Dentz --- drivers/bluetooth/btusb.c | 3 +++ 1 file changed, 3 insertions(+) From 08c6c0c217d2ddc6bd6cec53ed3262c118c91527 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 21 Oct 2022 23:36:04 +0200 Subject: [PATCH 77/80] generic: 5.15: move ZTE MF286D modem patch from pending to backport Move ZTE MF286D modem patch from pending to backport as it was merged upstream. Signed-off-by: Christian Marangi --- ...810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename target/linux/generic/{pending-5.15/842-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch => backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch} (97%) diff --git a/target/linux/generic/pending-5.15/842-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch b/target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch similarity index 97% rename from target/linux/generic/pending-5.15/842-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch rename to target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch index 05eadcf764..25802be7e3 100644 --- a/target/linux/generic/pending-5.15/842-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch +++ b/target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch @@ -1,7 +1,7 @@ From 078c6a1cbd4cd7496048786beec2e312577bebbf Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Tue, 11 Jan 2022 23:11:32 +0100 -Subject: [PATCH] net: qmi_wwan: add ZTE MF286D modem 19d2:1485 +Subject: [PATCH 1/1] net: qmi_wwan: add ZTE MF286D modem 19d2:1485 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From ccedd7175d19b03dadf4b2bcd85f5c762a41b363 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 21 Oct 2022 23:55:37 +0200 Subject: [PATCH 78/80] generic: 5.15: move mvebu aardvark patch from pending to backport Move mvebu aardvark patch from pending to backport as they got merged upstream. One additional patch is needed as a later fixup for it. Signed-off-by: Christian Marangi --- ...vebu-a3700-comphy-Remove-port-from-.patch} | 10 +- ...vebu-a3700-comphy-Add-native-kernel.patch} | 138 ++++++------- ...-armada-37xx-Add-xtal-clock-to-comp.patch} | 9 +- ...vebu-Make-SATA-PHY-optional-for-Arm.patch} | 11 +- ...hci-mvebu-make-USB-3.0-PHY-optional.patch} | 11 +- ...rk-Fix-initialization-with-old-Marv.patch} | 13 +- ...mvebu-a3700-comphy-Remove-broken-res.patch | 194 ++++++++++++++++++ 7 files changed, 290 insertions(+), 96 deletions(-) rename target/linux/generic/{pending-5.15/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch => backport-5.15/344-v5.18-01-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch} (95%) rename target/linux/generic/{pending-5.15/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch => backport-5.15/344-v5.18-02-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch} (95%) rename target/linux/generic/{pending-5.15/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch => backport-5.15/345-v5.17-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch} (78%) rename target/linux/generic/{pending-5.15/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch => backport-5.15/346-v5.18-01-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch} (84%) rename target/linux/generic/{pending-5.15/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch => backport-5.15/346-v5.18-02-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch} (92%) rename target/linux/generic/{pending-5.15/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch => backport-5.15/346-v5.18-03-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch} (67%) create mode 100644 target/linux/generic/backport-5.15/347-v6.0-phy-marvell-phy-mvebu-a3700-comphy-Remove-broken-res.patch diff --git a/target/linux/generic/pending-5.15/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch b/target/linux/generic/backport-5.15/344-v5.18-01-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch similarity index 95% rename from target/linux/generic/pending-5.15/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch rename to target/linux/generic/backport-5.15/344-v5.18-01-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch index 4a963be952..d6c4b4fd1e 100644 --- a/target/linux/generic/pending-5.15/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch +++ b/target/linux/generic/backport-5.15/344-v5.18-01-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch @@ -1,8 +1,8 @@ -From a719f7ba7fcba05d85801c6f0267f389a21627c1 Mon Sep 17 00:00:00 2001 +From 4bf18d5a2dd02db8c5b16a2cfae513510506df5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Fri, 24 Sep 2021 13:03:02 +0200 -Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Remove port from driver - configuration +Date: Thu, 3 Feb 2022 22:44:40 +0100 +Subject: [PATCH 1/2] phy: marvell: phy-mvebu-a3700-comphy: Remove port from + driver configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -25,6 +25,8 @@ driver code which parses it. This also simplifies the driver. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Reviewed-by: Miquel Raynal +Link: https://lore.kernel.org/r/20220203214444.1508-2-kabel@kernel.org +Signed-off-by: Vinod Koul --- drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 62 +++++++++----------- 1 file changed, 29 insertions(+), 33 deletions(-) diff --git a/target/linux/generic/pending-5.15/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch b/target/linux/generic/backport-5.15/344-v5.18-02-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch similarity index 95% rename from target/linux/generic/pending-5.15/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch rename to target/linux/generic/backport-5.15/344-v5.18-02-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch index 73ead1e16c..4593d14bfe 100644 --- a/target/linux/generic/pending-5.15/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch +++ b/target/linux/generic/backport-5.15/344-v5.18-02-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch @@ -1,7 +1,7 @@ -From 9d276da259cce20b2ed7a868b6e6a6a205f7bb04 Mon Sep 17 00:00:00 2001 +From 934337080c6c59b75db76b180b509f218640ad48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:20:13 +0200 -Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Add native kernel +Date: Thu, 3 Feb 2022 22:44:41 +0100 +Subject: [PATCH 2/2] phy: marvell: phy-mvebu-a3700-comphy: Add native kernel implementation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -46,16 +46,19 @@ original code not conforming to kernel standards. Also PCIe mode poweroff support was added here, and PHY reset support. These changes are also going to be sent to ARM Trusted Firmware. -Signed-off-by: Pali Rohár -Acked-by: Miquel Raynal [ Pali did the porting from ATF. I (Marek) then fixed some register names, some various other things, added some comments and refactored the code to kernel standards. Also fixed PHY poweroff and added PHY reset. ] + +Signed-off-by: Pali Rohár +Acked-by: Miquel Raynal Signed-off-by: Marek Behún +Link: https://lore.kernel.org/r/20220203214444.1508-3-kabel@kernel.org +Signed-off-by: Vinod Koul --- - drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 1351 ++++++++++++++++-- - 1 file changed, 1234 insertions(+), 117 deletions(-) + drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 1332 ++++++++++++++++-- + 1 file changed, 1215 insertions(+), 117 deletions(-) --- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c +++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c @@ -78,7 +81,7 @@ Signed-off-by: Marek Behún #include #include #include -@@ -18,103 +22,1147 @@ +@@ -18,103 +22,1118 @@ #include #include #include @@ -480,23 +483,23 @@ Signed-off-by: Marek Behún - struct arm_smccc_res res; - s32 ret; + u32 val; - -- arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res); -- ret = res.a0; ++ + val = readl(addr); + val = (val & ~mask) | (data & mask); + writel(val, addr); +} +- arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res); +- ret = res.a0; ++static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask) ++{ ++ u16 val; + - switch (ret) { - case SMCCC_RET_SUCCESS: - return 0; - case SMCCC_RET_NOT_SUPPORTED: - return -EOPNOTSUPP; -+static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask) -+{ -+ u16 val; -+ + val = readw(addr); + val = (val & ~mask) | (data & mask); + writew(val, addr); @@ -708,12 +711,10 @@ Signed-off-by: Marek Behún + ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN, + PLL_READY_TX_BIT, COMPHY_PLL_SLEEP, + COMPHY_PLL_TIMEOUT); -+ if (ret) { ++ if (ret) + dev_err(lane->dev, "Failed to lock SATA PLL\n"); -+ return ret; -+ } + -+ return 0; ++ return ret; +} + +static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane, @@ -827,7 +828,8 @@ Signed-off-by: Marek Behún + mask = REF_FREF_SEL_MASK; + comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); + -+ /* 10. Program COMPHY register PHY_GEN_MAX[1:0] ++ /* ++ * 10. Program COMPHY register PHY_GEN_MAX[1:0] + * This step is mentioned in the flow received from verification team. + * However the PHY_GEN_MAX value is only meaningful for other interfaces + * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or @@ -846,9 +848,8 @@ Signed-off-by: Marek Behún + * 12. As long as DFE function needs to be enabled in any mode, + * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F + * for real chip during COMPHY power on. -+ * The step 14 exists (and empty) in the original initialization flow -+ * obtained from the verification team. According to the functional -+ * specification DFE_UPDATE_EN already has the default value 0x3F ++ * The value of the DFE_UPDATE_EN already is 0x3F, because it is the ++ * default value after reset of the PHY. + */ + + /* @@ -867,19 +868,7 @@ Signed-off-by: Marek Behún + lane->submode != PHY_INTERFACE_MODE_2500BASEX); + + /* -+ * 14. [Simulation Only] should not be used for real chip. -+ * By pass power up calibration by programming EXT_FORCE_CAL_DONE -+ * (R02h[9]) to 1 to shorten COMPHY simulation time. -+ */ -+ -+ /* -+ * 15. [Simulation Only: should not be used for real chip] -+ * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training -+ * simulation time. -+ */ -+ -+ /* -+ * 16. Check the PHY Polarity invert bit ++ * 14. Check the PHY Polarity invert bit + */ + data = 0x0; + if (lane->invert_tx) @@ -890,7 +879,7 @@ Signed-off-by: Marek Behún + comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); + + /* -+ * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to ++ * 15. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to + * start PHY power up sequence. All the PHY register programming should + * be done before PIN_PU_PLL=1. There should be no register programming + * for normal PHY operation from this point. @@ -900,7 +889,7 @@ Signed-off-by: Marek Behún + comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); + + /* -+ * 18. Wait for PHY power up sequence to finish by checking output ports ++ * 16. Wait for PHY power up sequence to finish by checking output ports + * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. + */ + ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, @@ -914,12 +903,12 @@ Signed-off-by: Marek Behún + } + + /* -+ * 19. Set COMPHY input port PIN_TX_IDLE=0 ++ * 17. Set COMPHY input port PIN_TX_IDLE=0 + */ + comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT); + + /* -+ * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To ++ * 18. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To + * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the + * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to + * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please @@ -941,13 +930,11 @@ Signed-off-by: Marek Behún + ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, + PHY_RX_INIT_DONE_BIT, + COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); -+ if (ret) { ++ if (ret) + dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n", + lane->id); -+ return ret; -+ } + -+ return 0; ++ return ret; } -static int mvebu_a3700_comphy_get_fw_mode(int lane, @@ -1107,12 +1094,10 @@ Signed-off-by: Marek Behún + + ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, + COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); -+ if (ret) { ++ if (ret) + dev_err(lane->dev, "Failed to lock USB3 PLL\n"); -+ return ret; -+ } + -+ return 0; ++ return ret; +} + +static int @@ -1197,21 +1182,10 @@ Signed-off-by: Marek Behún + + ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, + COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); -+ if (ret) { ++ if (ret) + dev_err(lane->dev, "Failed to lock PCIE PLL\n"); -+ return ret; -+ } + -+ return 0; -+} -+ -+static void -+mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane) -+{ -+ /* -+ * Currently the USB3 MAC sets the USB3 PHY to low state, so we do not -+ * need to power off USB3 PHY again. -+ */ ++ return ret; +} + +static void @@ -1285,7 +1259,7 @@ Signed-off-by: Marek Behún enum phy_mode mode, int submode) { -@@ -122,7 +1170,7 @@ static int mvebu_a3700_comphy_get_fw_mod +@@ -122,7 +1141,7 @@ static int mvebu_a3700_comphy_get_fw_mod /* Unused PHY mux value is 0x0 */ if (mode == PHY_MODE_INVALID) @@ -1294,7 +1268,7 @@ Signed-off-by: Marek Behún for (i = 0; i < n; i++) { if (mvebu_a3700_comphy_modes[i].lane == lane && -@@ -132,27 +1180,30 @@ static int mvebu_a3700_comphy_get_fw_mod +@@ -132,27 +1151,30 @@ static int mvebu_a3700_comphy_get_fw_mod } if (i == n) @@ -1310,10 +1284,10 @@ Signed-off-by: Marek Behún { struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); - int fw_mode; -- + - if (submode == PHY_INTERFACE_MODE_1000BASEX) - submode = PHY_INTERFACE_MODE_SGMII; - +- - fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, mode, - submode); - if (fw_mode < 0) { @@ -1335,7 +1309,7 @@ Signed-off-by: Marek Behún /* Just remember the mode, ->power_on() will do the real setup */ lane->mode = mode; lane->submode = submode; -@@ -163,76 +1214,68 @@ static int mvebu_a3700_comphy_set_mode(s +@@ -163,76 +1185,77 @@ static int mvebu_a3700_comphy_set_mode(s static int mvebu_a3700_comphy_power_on(struct phy *phy) { struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); @@ -1423,21 +1397,30 @@ Signed-off-by: Marek Behún - return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0); + switch (lane->mode) { + case PHY_MODE_USB_HOST_SS: -+ mvebu_a3700_comphy_usb3_power_off(lane); -+ return 0; ++ /* ++ * The USB3 MAC sets the USB3 PHY to low state, so we do not ++ * need to power off USB3 PHY again. ++ */ ++ break; ++ + case PHY_MODE_SATA: + mvebu_a3700_comphy_sata_power_off(lane); -+ return 0; ++ break; ++ + case PHY_MODE_ETHERNET: + mvebu_a3700_comphy_ethernet_power_off(lane); -+ return 0; ++ break; ++ + case PHY_MODE_PCIE: + mvebu_a3700_comphy_pcie_power_off(lane); -+ return 0; ++ break; ++ + default: + dev_err(lane->dev, "invalid COMPHY mode\n"); + return -EINVAL; + } ++ ++ return 0; } static const struct phy_ops mvebu_a3700_comphy_ops = { @@ -1447,7 +1430,7 @@ Signed-off-by: Marek Behún .set_mode = mvebu_a3700_comphy_set_mode, .owner = THIS_MODULE, }; -@@ -256,13 +1299,75 @@ static struct phy *mvebu_a3700_comphy_xl +@@ -256,13 +1279,75 @@ static struct phy *mvebu_a3700_comphy_xl return ERR_PTR(-EINVAL); } @@ -1523,7 +1506,7 @@ Signed-off-by: Marek Behún for_each_available_child_of_node(pdev->dev.of_node, child) { struct mvebu_a3700_comphy_lane *lane; -@@ -277,7 +1382,7 @@ static int mvebu_a3700_comphy_probe(stru +@@ -277,7 +1362,7 @@ static int mvebu_a3700_comphy_probe(stru continue; } @@ -1532,7 +1515,7 @@ Signed-off-by: Marek Behún dev_err(&pdev->dev, "invalid 'reg' property\n"); continue; } -@@ -295,11 +1400,21 @@ static int mvebu_a3700_comphy_probe(stru +@@ -295,15 +1380,26 @@ static int mvebu_a3700_comphy_probe(stru return PTR_ERR(phy); } @@ -1554,7 +1537,12 @@ Signed-off-by: Marek Behún } provider = devm_of_phy_provider_register(&pdev->dev, -@@ -323,5 +1438,7 @@ static struct platform_driver mvebu_a370 + mvebu_a3700_comphy_xlate); ++ + return PTR_ERR_OR_ZERO(provider); + } + +@@ -323,5 +1419,7 @@ static struct platform_driver mvebu_a370 module_platform_driver(mvebu_a3700_comphy_driver); MODULE_AUTHOR("Miquèl Raynal "); diff --git a/target/linux/generic/pending-5.15/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch b/target/linux/generic/backport-5.15/345-v5.17-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch similarity index 78% rename from target/linux/generic/pending-5.15/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch rename to target/linux/generic/backport-5.15/345-v5.17-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch index 33203a154d..03b6a5754d 100644 --- a/target/linux/generic/pending-5.15/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch +++ b/target/linux/generic/backport-5.15/345-v5.17-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch @@ -1,8 +1,8 @@ -From 66c51c39fd4bf05e99debf0e71de5704231c57dc Mon Sep 17 00:00:00 2001 +From 73a78b6130d9e13daca22b86ad52f063b9403e03 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:26:26 +0200 -Subject: [PATCH] arm64: dts: marvell: armada-37xx: Add xtal clock to comphy - node +Date: Wed, 8 Dec 2021 03:40:35 +0100 +Subject: [PATCH 1/1] arm64: dts: marvell: armada-37xx: Add xtal clock to + comphy node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -14,6 +14,7 @@ xtal rate (which, as far as we know, is used by all the existing boards). Signed-off-by: Pali Rohár Signed-off-by: Marek Behún +Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/generic/pending-5.15/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch b/target/linux/generic/backport-5.15/346-v5.18-01-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch similarity index 84% rename from target/linux/generic/pending-5.15/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch rename to target/linux/generic/backport-5.15/346-v5.18-01-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch index 3c994d2548..b254e7c0b3 100644 --- a/target/linux/generic/pending-5.15/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch +++ b/target/linux/generic/backport-5.15/346-v5.18-01-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch @@ -1,8 +1,8 @@ -From 750bb44dbbe9dfb4ba3e1f8a746b831b39ba3cd9 Mon Sep 17 00:00:00 2001 +From ee995101fde67f85a3cd4c74f4f92fc4592e726b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:35:57 +0200 -Subject: [PATCH] Revert "ata: ahci: mvebu: Make SATA PHY optional for Armada - 3720" +Date: Thu, 3 Feb 2022 22:44:42 +0100 +Subject: [PATCH 1/3] Revert "ata: ahci: mvebu: Make SATA PHY optional for + Armada 3720" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -20,6 +20,9 @@ remove this flag completely. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Acked-by: Miquel Raynal +Acked-by: Damien Le Moal +Link: https://lore.kernel.org/r/20220203214444.1508-4-kabel@kernel.org +Signed-off-by: Vinod Koul --- drivers/ata/ahci.h | 2 -- drivers/ata/ahci_mvebu.c | 2 +- diff --git a/target/linux/generic/pending-5.15/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch b/target/linux/generic/backport-5.15/346-v5.18-02-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch similarity index 92% rename from target/linux/generic/pending-5.15/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch rename to target/linux/generic/backport-5.15/346-v5.18-02-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch index b8a3e880ce..1e8afb7bbf 100644 --- a/target/linux/generic/pending-5.15/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch +++ b/target/linux/generic/backport-5.15/346-v5.18-02-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch @@ -1,8 +1,8 @@ -From 9f0dfb279b1dd505d5e10b10e4a78a62030978d8 Mon Sep 17 00:00:00 2001 +From 8e10548f7f4814e530857d2049d6af6bc78add53 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:40:06 +0200 -Subject: [PATCH] Revert "usb: host: xhci: mvebu: make USB 3.0 PHY optional for - Armada 3720" +Date: Thu, 3 Feb 2022 22:44:43 +0100 +Subject: [PATCH 2/3] Revert "usb: host: xhci: mvebu: make USB 3.0 PHY optional + for Armada 3720" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -22,6 +22,9 @@ remove this callback completely. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Acked-by: Miquel Raynal +Acked-by: Greg Kroah-Hartman +Link: https://lore.kernel.org/r/20220203214444.1508-5-kabel@kernel.org +Signed-off-by: Vinod Koul --- drivers/usb/host/xhci-mvebu.c | 42 ----------------------------------- drivers/usb/host/xhci-mvebu.h | 6 ----- diff --git a/target/linux/generic/pending-5.15/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch b/target/linux/generic/backport-5.15/346-v5.18-03-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch similarity index 67% rename from target/linux/generic/pending-5.15/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch rename to target/linux/generic/backport-5.15/346-v5.18-03-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch index 76b39452ad..fcfb02d35a 100644 --- a/target/linux/generic/pending-5.15/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch +++ b/target/linux/generic/backport-5.15/346-v5.18-03-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch @@ -1,8 +1,8 @@ -From 9a352062b7e3857742389dff6f64393481dc755e Mon Sep 17 00:00:00 2001 +From 9a4556dad7bd0a6b8339cb72e169f5c76f2af6f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:37:05 +0200 -Subject: [PATCH] Revert "PCI: aardvark: Fix initialization with old Marvell's - Arm Trusted Firmware" +Date: Thu, 3 Feb 2022 22:44:44 +0100 +Subject: [PATCH 3/3] Revert "PCI: aardvark: Fix initialization with old + Marvell's Arm Trusted Firmware" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -17,13 +17,16 @@ So remove dead code which handles -EOPNOTSUPP return value. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Acked-by: Miquel Raynal +Acked-by: Lorenzo Pieralisi +Link: https://lore.kernel.org/r/20220203214444.1508-6-kabel@kernel.org +Signed-off-by: Vinod Koul --- drivers/pci/controller/pci-aardvark.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c -@@ -1631,9 +1631,7 @@ static int advk_pcie_enable_phy(struct a +@@ -1642,9 +1642,7 @@ static int advk_pcie_enable_phy(struct a } ret = phy_power_on(pcie->phy); diff --git a/target/linux/generic/backport-5.15/347-v6.0-phy-marvell-phy-mvebu-a3700-comphy-Remove-broken-res.patch b/target/linux/generic/backport-5.15/347-v6.0-phy-marvell-phy-mvebu-a3700-comphy-Remove-broken-res.patch new file mode 100644 index 0000000000..a2c897b7a9 --- /dev/null +++ b/target/linux/generic/backport-5.15/347-v6.0-phy-marvell-phy-mvebu-a3700-comphy-Remove-broken-res.patch @@ -0,0 +1,194 @@ +From 0a6fc70d76bddf98278af2ac000379c82aec8f11 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Mon, 29 Aug 2022 10:30:46 +0200 +Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Remove broken reset + support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Reset support for SATA PHY is somehow broken and after calling it, kernel +is not able to detect and initialize SATA disk Samsung SSD 850 EMT0 [1]. + +Reset support was introduced in commit 934337080c6c ("phy: marvell: +phy-mvebu-a3700-comphy: Add native kernel implementation") as part of +complete rewrite of this driver. v1 patch series of that commit [2] did +not contain reset support and was tested that is working fine with +Ethernet, SATA and USB PHYs without issues too. + +So for now remove broken reset support and change implementation of +power_off callback to power off all functions on specified lane (and not +only selected function) because during startup kernel does not know which +function was selected and configured by bootloader. Same logic was used +also in v1 patch series of that commit. + +This change fixes issues with initialization of SATA disk Samsung SSD 850 +and disk is working again, like before mentioned commit. + +Once problem with PHY reset callback is solved its functionality could be +re-introduced. But for now it is unknown why it does not work. + +[1] - https://lore.kernel.org/r/20220531124159.3e4lgn2v462irbtz@shindev/ +[2] - https://lore.kernel.org/r/20211028184242.22105-1-kabel@kernel.org/ + +Reported-by: Shinichiro Kawasaki +Fixes: 934337080c6c ("phy: marvell: phy-mvebu-a3700-comphy: Add native kernel implementation") +Cc: stable@vger.kernel.org # v5.18+ +Signed-off-by: Pali Rohár +Tested-by: Shinichiro Kawasaki +Link: https://lore.kernel.org/r/20220829083046.15082-1-pali@kernel.org +Signed-off-by: Vinod Koul +--- + drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 87 ++++---------------- + 1 file changed, 17 insertions(+), 70 deletions(-) + +--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c ++++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c +@@ -274,7 +274,6 @@ struct mvebu_a3700_comphy_lane { + int submode; + bool invert_tx; + bool invert_rx; +- bool needs_reset; + }; + + struct gbe_phy_init_data_fix { +@@ -1097,40 +1096,12 @@ mvebu_a3700_comphy_pcie_power_off(struct + 0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); + } + +-static int mvebu_a3700_comphy_reset(struct phy *phy) ++static void mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane) + { +- struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); +- u16 mask, data; +- +- dev_dbg(lane->dev, "resetting lane %d\n", lane->id); +- +- /* COMPHY reset for internal logic */ +- comphy_lane_reg_set(lane, COMPHY_SFT_RESET, +- SFT_RST_NO_REG, SFT_RST_NO_REG); +- +- /* COMPHY register reset (cleared automatically) */ +- comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST); +- +- /* PIPE soft and register reset */ +- data = PIPE_SOFT_RESET | PIPE_REG_RESET; +- mask = data; +- comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); +- +- /* Release PIPE register reset */ +- comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, +- 0x0, PIPE_REG_RESET); +- +- /* Reset SB configuration register (only for lanes 0 and 1) */ +- if (lane->id == 0 || lane->id == 1) { +- u32 mask, data; +- +- data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | +- PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT; +- mask = data | PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT; +- comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); +- } +- +- return 0; ++ /* ++ * The USB3 MAC sets the USB3 PHY to low state, so we do not ++ * need to power off USB3 PHY again. ++ */ + } + + static bool mvebu_a3700_comphy_check_mode(int lane, +@@ -1171,10 +1142,6 @@ static int mvebu_a3700_comphy_set_mode(s + (lane->mode != mode || lane->submode != submode)) + return -EBUSY; + +- /* If changing mode, ensure reset is called */ +- if (lane->mode != PHY_MODE_INVALID && lane->mode != mode) +- lane->needs_reset = true; +- + /* Just remember the mode, ->power_on() will do the real setup */ + lane->mode = mode; + lane->submode = submode; +@@ -1185,7 +1152,6 @@ static int mvebu_a3700_comphy_set_mode(s + static int mvebu_a3700_comphy_power_on(struct phy *phy) + { + struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); +- int ret; + + if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode, + lane->submode)) { +@@ -1193,14 +1159,6 @@ static int mvebu_a3700_comphy_power_on(s + return -EINVAL; + } + +- if (lane->needs_reset) { +- ret = mvebu_a3700_comphy_reset(phy); +- if (ret) +- return ret; +- +- lane->needs_reset = false; +- } +- + switch (lane->mode) { + case PHY_MODE_USB_HOST_SS: + dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id); +@@ -1224,38 +1182,28 @@ static int mvebu_a3700_comphy_power_off( + { + struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); + +- switch (lane->mode) { +- case PHY_MODE_USB_HOST_SS: +- /* +- * The USB3 MAC sets the USB3 PHY to low state, so we do not +- * need to power off USB3 PHY again. +- */ +- break; +- +- case PHY_MODE_SATA: +- mvebu_a3700_comphy_sata_power_off(lane); +- break; +- +- case PHY_MODE_ETHERNET: ++ switch (lane->id) { ++ case 0: ++ mvebu_a3700_comphy_usb3_power_off(lane); + mvebu_a3700_comphy_ethernet_power_off(lane); +- break; +- +- case PHY_MODE_PCIE: ++ return 0; ++ case 1: + mvebu_a3700_comphy_pcie_power_off(lane); +- break; +- ++ mvebu_a3700_comphy_ethernet_power_off(lane); ++ return 0; ++ case 2: ++ mvebu_a3700_comphy_usb3_power_off(lane); ++ mvebu_a3700_comphy_sata_power_off(lane); ++ return 0; + default: + dev_err(lane->dev, "invalid COMPHY mode\n"); + return -EINVAL; + } +- +- return 0; + } + + static const struct phy_ops mvebu_a3700_comphy_ops = { + .power_on = mvebu_a3700_comphy_power_on, + .power_off = mvebu_a3700_comphy_power_off, +- .reset = mvebu_a3700_comphy_reset, + .set_mode = mvebu_a3700_comphy_set_mode, + .owner = THIS_MODULE, + }; +@@ -1393,8 +1341,7 @@ static int mvebu_a3700_comphy_probe(stru + * To avoid relying on the bootloader/firmware configuration, + * power off all comphys. + */ +- mvebu_a3700_comphy_reset(phy); +- lane->needs_reset = false; ++ mvebu_a3700_comphy_power_off(phy); + } + + provider = devm_of_phy_provider_register(&pdev->dev, From 2a7bdde29bebcaeb18c8595d31ca0d89b5719a1a Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 22 Oct 2022 00:24:49 +0200 Subject: [PATCH 79/80] generic: 5.15: move MGLRU patches from pending to backport Move MGLRU patches from pending to backport as they got merged upstream. These are direct porting from one of the dev so it's better to just move than trying to backport them again from upstream. Signed-off-by: Christian Marangi --- ...x86-arm64-add-arch_has_hw_pte_young.patch} | 0 ...d-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch} | 0 ...03-mm-vmscan.c-refactor-shrink_node.patch} | 0 ...mm-multigenerational-lru-groundwork.patch} | 0 ...ultigenerational-lru-mm_struct-list.patch} | 0 ...1-06-mm-multigenerational-lru-aging.patch} | 0 ...7-mm-multigenerational-lru-eviction.patch} | 0 ...ultigenerational-lru-user-interface.patch} | 0 ...09-mm-multigenerational-lru-Kconfig.patch} | 0 ...multigenerational-lru-documentation.patch} | 0 ...don-t-sync-disk-for-each-aging-cycle.patch | 32 +++++++++++++++++++ 11 files changed, 32 insertions(+) rename target/linux/generic/{pending-5.15/020-00-mm-x86-arm64-add-arch_has_hw_pte_young.patch => backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch} (100%) rename target/linux/generic/{pending-5.15/020-01-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch => backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch} (100%) rename target/linux/generic/{pending-5.15/020-02-mm-vmscan.c-refactor-shrink_node.patch => backport-5.15/020-v6.1-03-mm-vmscan.c-refactor-shrink_node.patch} (100%) rename target/linux/generic/{pending-5.15/020-03-mm-multigenerational-lru-groundwork.patch => backport-5.15/020-v6.1-04-mm-multigenerational-lru-groundwork.patch} (100%) rename target/linux/generic/{pending-5.15/020-04-mm-multigenerational-lru-mm_struct-list.patch => backport-5.15/020-v6.1-05-mm-multigenerational-lru-mm_struct-list.patch} (100%) rename target/linux/generic/{pending-5.15/020-05-mm-multigenerational-lru-aging.patch => backport-5.15/020-v6.1-06-mm-multigenerational-lru-aging.patch} (100%) rename target/linux/generic/{pending-5.15/020-06-mm-multigenerational-lru-eviction.patch => backport-5.15/020-v6.1-07-mm-multigenerational-lru-eviction.patch} (100%) rename target/linux/generic/{pending-5.15/020-07-mm-multigenerational-lru-user-interface.patch => backport-5.15/020-v6.1-08-mm-multigenerational-lru-user-interface.patch} (100%) rename target/linux/generic/{pending-5.15/020-08-mm-multigenerational-lru-Kconfig.patch => backport-5.15/020-v6.1-09-mm-multigenerational-lru-Kconfig.patch} (100%) rename target/linux/generic/{pending-5.15/020-09-mm-multigenerational-lru-documentation.patch => backport-5.15/020-v6.1-10-mm-multigenerational-lru-documentation.patch} (100%) create mode 100644 target/linux/generic/backport-5.15/021-v6.1-mm-mglru-don-t-sync-disk-for-each-aging-cycle.patch diff --git a/target/linux/generic/pending-5.15/020-00-mm-x86-arm64-add-arch_has_hw_pte_young.patch b/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-00-mm-x86-arm64-add-arch_has_hw_pte_young.patch rename to target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch diff --git a/target/linux/generic/pending-5.15/020-01-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch b/target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-01-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch rename to target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch diff --git a/target/linux/generic/pending-5.15/020-02-mm-vmscan.c-refactor-shrink_node.patch b/target/linux/generic/backport-5.15/020-v6.1-03-mm-vmscan.c-refactor-shrink_node.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-02-mm-vmscan.c-refactor-shrink_node.patch rename to target/linux/generic/backport-5.15/020-v6.1-03-mm-vmscan.c-refactor-shrink_node.patch diff --git a/target/linux/generic/pending-5.15/020-03-mm-multigenerational-lru-groundwork.patch b/target/linux/generic/backport-5.15/020-v6.1-04-mm-multigenerational-lru-groundwork.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-03-mm-multigenerational-lru-groundwork.patch rename to target/linux/generic/backport-5.15/020-v6.1-04-mm-multigenerational-lru-groundwork.patch diff --git a/target/linux/generic/pending-5.15/020-04-mm-multigenerational-lru-mm_struct-list.patch b/target/linux/generic/backport-5.15/020-v6.1-05-mm-multigenerational-lru-mm_struct-list.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-04-mm-multigenerational-lru-mm_struct-list.patch rename to target/linux/generic/backport-5.15/020-v6.1-05-mm-multigenerational-lru-mm_struct-list.patch diff --git a/target/linux/generic/pending-5.15/020-05-mm-multigenerational-lru-aging.patch b/target/linux/generic/backport-5.15/020-v6.1-06-mm-multigenerational-lru-aging.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-05-mm-multigenerational-lru-aging.patch rename to target/linux/generic/backport-5.15/020-v6.1-06-mm-multigenerational-lru-aging.patch diff --git a/target/linux/generic/pending-5.15/020-06-mm-multigenerational-lru-eviction.patch b/target/linux/generic/backport-5.15/020-v6.1-07-mm-multigenerational-lru-eviction.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-06-mm-multigenerational-lru-eviction.patch rename to target/linux/generic/backport-5.15/020-v6.1-07-mm-multigenerational-lru-eviction.patch diff --git a/target/linux/generic/pending-5.15/020-07-mm-multigenerational-lru-user-interface.patch b/target/linux/generic/backport-5.15/020-v6.1-08-mm-multigenerational-lru-user-interface.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-07-mm-multigenerational-lru-user-interface.patch rename to target/linux/generic/backport-5.15/020-v6.1-08-mm-multigenerational-lru-user-interface.patch diff --git a/target/linux/generic/pending-5.15/020-08-mm-multigenerational-lru-Kconfig.patch b/target/linux/generic/backport-5.15/020-v6.1-09-mm-multigenerational-lru-Kconfig.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-08-mm-multigenerational-lru-Kconfig.patch rename to target/linux/generic/backport-5.15/020-v6.1-09-mm-multigenerational-lru-Kconfig.patch diff --git a/target/linux/generic/pending-5.15/020-09-mm-multigenerational-lru-documentation.patch b/target/linux/generic/backport-5.15/020-v6.1-10-mm-multigenerational-lru-documentation.patch similarity index 100% rename from target/linux/generic/pending-5.15/020-09-mm-multigenerational-lru-documentation.patch rename to target/linux/generic/backport-5.15/020-v6.1-10-mm-multigenerational-lru-documentation.patch diff --git a/target/linux/generic/backport-5.15/021-v6.1-mm-mglru-don-t-sync-disk-for-each-aging-cycle.patch b/target/linux/generic/backport-5.15/021-v6.1-mm-mglru-don-t-sync-disk-for-each-aging-cycle.patch new file mode 100644 index 0000000000..269e5eb204 --- /dev/null +++ b/target/linux/generic/backport-5.15/021-v6.1-mm-mglru-don-t-sync-disk-for-each-aging-cycle.patch @@ -0,0 +1,32 @@ +From 14aa8b2d5c2ebead01b542f62d68029023054774 Mon Sep 17 00:00:00 2001 +From: Yu Zhao +Date: Wed, 28 Sep 2022 13:36:58 -0600 +Subject: [PATCH 1/1] mm/mglru: don't sync disk for each aging cycle + +wakeup_flusher_threads() was added under the assumption that if a system +runs out of clean cold pages, it might want to write back dirty pages more +aggressively so that they can become clean and be dropped. + +However, doing so can breach the rate limit a system wants to impose on +writeback, resulting in early SSD wearout. + +Link: https://lkml.kernel.org/r/YzSiWq9UEER5LKup@google.com +Fixes: bd74fdaea146 ("mm: multi-gen LRU: support page table walks") +Signed-off-by: Yu Zhao +Reported-by: Axel Rasmussen +Signed-off-by: Andrew Morton +--- + mm/vmscan.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/mm/vmscan.c ++++ b/mm/vmscan.c +@@ -4072,8 +4072,6 @@ static bool try_to_inc_max_seq(struct lr + if (wq_has_sleeper(&lruvec->mm_walk.wait)) + wake_up_all(&lruvec->mm_walk.wait); + +- wakeup_flusher_threads(WB_REASON_VMSCAN); +- + return true; + } + From ffe91ca478082b85d44a9c2e78a0e3818fd2093a Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 22 Oct 2022 15:43:47 +0200 Subject: [PATCH 80/80] generic: 5.15: move not backport patch to pending dir Move patch wrongly placed in backport dir to pending dir as they still didn't got merged upstream. Signed-off-by: Christian Marangi --- .../103-kbuild-export-SUBARCH.patch} | 0 ...00-netfilter-nft_flow_offload-handle-netdevice-events-f.patch} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename target/linux/generic/{backport-5.15/011-kbuild-export-SUBARCH.patch => pending-5.15/103-kbuild-export-SUBARCH.patch} (100%) rename target/linux/generic/{backport-5.15/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch => pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch} (100%) diff --git a/target/linux/generic/backport-5.15/011-kbuild-export-SUBARCH.patch b/target/linux/generic/pending-5.15/103-kbuild-export-SUBARCH.patch similarity index 100% rename from target/linux/generic/backport-5.15/011-kbuild-export-SUBARCH.patch rename to target/linux/generic/pending-5.15/103-kbuild-export-SUBARCH.patch diff --git a/target/linux/generic/backport-5.15/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch b/target/linux/generic/pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch similarity index 100% rename from target/linux/generic/backport-5.15/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch rename to target/linux/generic/pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch