From 061a70d33cc886db54fcf0f8d1882c448a6163a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 29 Dec 2023 10:45:08 +0100 Subject: [PATCH 01/20] mediatek: filogic: reorder nodes in mt7988a.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use order described as preferred in DTS Coding Style: 1. Sort bus nodes by unit address 2. Use alpha-numerical order for the rest Signed-off-by: Rafał Miłecki --- .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 432 +++++++++--------- .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 432 +++++++++--------- 2 files changed, 432 insertions(+), 432 deletions(-) diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 7fed1e1384..bda50936f2 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -19,11 +19,13 @@ #address-cells = <2>; #size-cells = <2>; - clk40m: oscillator@0 { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - clock-output-names = "clkxtal"; + cci: cci { + compatible = "mediatek,mt7988-cci", + "mediatek,mt8183-cci"; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cci", "intermediate"; + operating-points-v2 = <&cci_opp>; }; cpus { @@ -99,15 +101,6 @@ }; }; - cci: cci { - compatible = "mediatek,mt7988-cci", - "mediatek,mt8183-cci"; - clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cci", "intermediate"; - operating-points-v2 = <&cci_opp>; - }; - cci_opp: opp_table_cci { compatible = "operating-points-v2"; opp-shared; @@ -129,6 +122,13 @@ }; }; + clk40m: oscillator@0 { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "clkxtal"; + }; + pmu { compatible = "arm,cortex-a73-pmu"; interrupt-parent = <&gic>; @@ -140,86 +140,6 @@ method = "smc"; }; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x50000>; - no-map; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&lvts 0>; - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <40000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-low { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-passive { - /* passive: set fan to cooling level 0 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -238,6 +158,18 @@ regulator-always-on; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x50000>; + no-map; + }; + }; + soc { #address-cells = <2>; #size-cells = <2>; @@ -539,6 +471,25 @@ }; }; + pwm: pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&infracfg CLK_INFRA_66M_PWM_CK1>, + <&infracfg CLK_INFRA_66M_PWM_CK2>, + <&infracfg CLK_INFRA_66M_PWM_CK3>, + <&infracfg CLK_INFRA_66M_PWM_CK4>, + <&infracfg CLK_INFRA_66M_PWM_CK5>, + <&infracfg CLK_INFRA_66M_PWM_CK6>, + <&infracfg CLK_INFRA_66M_PWM_CK7>, + <&infracfg CLK_INFRA_66M_PWM_CK8>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4","pwm5","pwm6","pwm7","pwm8"; + status = "disabled"; + }; + sgmiisys0: syscon@10060000 { compatible = "mediatek,mt7988-sgmiisys", "mediatek,mt7988-sgmiisys_0", @@ -571,28 +522,6 @@ #clock-cells = <1>; }; - xfi_pextp0: xfi-pextp@11f20000 { - compatible = "mediatek,mt7988-xfi-pextp", - "mediatek,mt7988-xfi-pextp_0", - "syscon"; - reg = <0 0x11f20000 0 0x10000>; - #clock-cells = <1>; - }; - - xfi_pextp1: xfi-pextp@11f30000 { - compatible = "mediatek,mt7988-xfi-pextp", - "mediatek,mt7988-xfi-pextp_1", - "syscon"; - reg = <0 0x11f30000 0 0x10000>; - #clock-cells = <1>; - }; - - xfi_pll: xfi-pll@11f40000 { - compatible = "mediatek,mt7988-xfi-pll", "syscon"; - reg = <0 0x11f40000 0 0x1000>; - #clock-cells = <1>; - }; - mcusys: mcusys@100e0000 { compatible = "mediatek,mt7988-mcusys", "syscon"; reg = <0 0x100e0000 0 0x1000>; @@ -742,25 +671,6 @@ status = "disabled"; }; - pwm: pwm@10048000 { - compatible = "mediatek,mt7988-pwm"; - reg = <0 0x10048000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, - <&infracfg CLK_INFRA_66M_PWM_HCK>, - <&infracfg CLK_INFRA_66M_PWM_CK1>, - <&infracfg CLK_INFRA_66M_PWM_CK2>, - <&infracfg CLK_INFRA_66M_PWM_CK3>, - <&infracfg CLK_INFRA_66M_PWM_CK4>, - <&infracfg CLK_INFRA_66M_PWM_CK5>, - <&infracfg CLK_INFRA_66M_PWM_CK6>, - <&infracfg CLK_INFRA_66M_PWM_CK7>, - <&infracfg CLK_INFRA_66M_PWM_CK8>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3", - "pwm4","pwm5","pwm6","pwm7","pwm8"; - status = "disabled"; - }; - fan: pwm-fan { compatible = "pwm-fan"; /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ @@ -780,15 +690,53 @@ nvmem-cell-names = "e_data1"; }; - crypto: crypto@15600000 { - compatible = "inside-secure,safexcel-eip197b"; - reg = <0 0x15600000 0 0x180000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - status = "okay"; + ssusb0: usb@11190000 { + compatible = "mediatek,mt7988-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, + <0 0x11193e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&xphyu2port0 PHY_TYPE_USB2>, + <&xphyu3port0 PHY_TYPE_USB3>; + clocks = <&infracfg CLK_INFRA_USB_SYS>, + <&infracfg CLK_INFRA_USB_XHCI>, + <&infracfg CLK_INFRA_USB_REF>, + <&infracfg CLK_INFRA_66M_USB_HCK>, + <&infracfg CLK_INFRA_133M_USB_HCK>; + clock-names = "sys_ck", + "xhci_ck", + "ref_ck", + "mcu_ck", + "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + mediatek,p0_speed_fixup; + status = "disabled"; + }; + + ssusb1: usb@11200000 { + compatible = "mediatek,mt7988-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&tphyu2port0 PHY_TYPE_USB2>, + <&tphyu3port0 PHY_TYPE_USB3>; + clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, + <&infracfg CLK_INFRA_USB_CK_P1>, + <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; + clock-names = "sys_ck", + "xhci_ck", + "ref_ck", + "mcu_ck", + "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; }; afe: audio-controller@11210000 { @@ -820,6 +768,29 @@ status = "disabled"; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc", + "mediatek,mt7981-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11D60000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_MSDC400>, + <&infracfg CLK_INFRA_MSDC2_HCK>, + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, + <&topckgen CLK_TOP_EMMC_400M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, + <&apmixedsys CLK_APMIXED_MSDCPLL>; + clock-names = "source", + "hclk", + "axi_cg", + "ahb_cg"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pcie2: pcie@11280000 { compatible = "mediatek,mt7988-pcie", "mediatek,mt7986-pcie", @@ -979,78 +950,6 @@ }; }; - ssusb0: usb@11190000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11190000 0 0x2e00>, - <0 0x11193e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&xphyu2port0 PHY_TYPE_USB2>, - <&xphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS>, - <&infracfg CLK_INFRA_USB_XHCI>, - <&infracfg CLK_INFRA_USB_REF>, - <&infracfg CLK_INFRA_66M_USB_HCK>, - <&infracfg CLK_INFRA_133M_USB_HCK>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - mediatek,p0_speed_fixup; - status = "disabled"; - }; - - ssusb1: usb@11200000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&tphyu2port0 PHY_TYPE_USB2>, - <&tphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, - <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, - <&infracfg CLK_INFRA_USB_CK_P1>, - <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, - <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc", - "mediatek,mt7981-mmc"; - reg = <0 0x11230000 0 0x1000>, - <0 0x11D60000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_MSDC400>, - <&infracfg CLK_INFRA_MSDC2_HCK>, - <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, - <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, - <&topckgen CLK_TOP_EMMC_400M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, - <&apmixedsys CLK_APMIXED_MSDCPLL>; - clock-names = "source", - "hclk", - "axi_cg", - "ahb_cg"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - tphy: tphy@11c50000 { compatible = "mediatek,mt7988", "mediatek,generic-tphy-v2"; @@ -1108,6 +1007,28 @@ }; }; + xfi_pextp0: xfi-pextp@11f20000 { + compatible = "mediatek,mt7988-xfi-pextp", + "mediatek,mt7988-xfi-pextp_0", + "syscon"; + reg = <0 0x11f20000 0 0x10000>; + #clock-cells = <1>; + }; + + xfi_pextp1: xfi-pextp@11f30000 { + compatible = "mediatek,mt7988-xfi-pextp", + "mediatek,mt7988-xfi-pextp_1", + "syscon"; + reg = <0 0x11f30000 0 0x10000>; + #clock-cells = <1>; + }; + + xfi_pll: xfi-pll@11f40000 { + compatible = "mediatek,mt7988-xfi-pll", "syscon"; + reg = <0 0x11f40000 0 0x1000>; + #clock-cells = <1>; + }; + efuse: efuse@11f50000 { compatible = "mediatek,efuse"; reg = <0 0x11f50000 0 0x1000>; @@ -1437,5 +1358,84 @@ }; }; }; + + crypto: crypto@15600000 { + compatible = "inside-secure,safexcel-eip197b"; + reg = <0 0x15600000 0 0x180000>; + interrupts = , + , + , + ; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + status = "okay"; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 0>; + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_med: active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_med>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; }; }; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 7fed1e1384..bda50936f2 100644 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -19,11 +19,13 @@ #address-cells = <2>; #size-cells = <2>; - clk40m: oscillator@0 { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - clock-output-names = "clkxtal"; + cci: cci { + compatible = "mediatek,mt7988-cci", + "mediatek,mt8183-cci"; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cci", "intermediate"; + operating-points-v2 = <&cci_opp>; }; cpus { @@ -99,15 +101,6 @@ }; }; - cci: cci { - compatible = "mediatek,mt7988-cci", - "mediatek,mt8183-cci"; - clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cci", "intermediate"; - operating-points-v2 = <&cci_opp>; - }; - cci_opp: opp_table_cci { compatible = "operating-points-v2"; opp-shared; @@ -129,6 +122,13 @@ }; }; + clk40m: oscillator@0 { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "clkxtal"; + }; + pmu { compatible = "arm,cortex-a73-pmu"; interrupt-parent = <&gic>; @@ -140,86 +140,6 @@ method = "smc"; }; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x50000>; - no-map; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&lvts 0>; - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <40000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-low { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-passive { - /* passive: set fan to cooling level 0 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -238,6 +158,18 @@ regulator-always-on; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x50000>; + no-map; + }; + }; + soc { #address-cells = <2>; #size-cells = <2>; @@ -539,6 +471,25 @@ }; }; + pwm: pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&infracfg CLK_INFRA_66M_PWM_CK1>, + <&infracfg CLK_INFRA_66M_PWM_CK2>, + <&infracfg CLK_INFRA_66M_PWM_CK3>, + <&infracfg CLK_INFRA_66M_PWM_CK4>, + <&infracfg CLK_INFRA_66M_PWM_CK5>, + <&infracfg CLK_INFRA_66M_PWM_CK6>, + <&infracfg CLK_INFRA_66M_PWM_CK7>, + <&infracfg CLK_INFRA_66M_PWM_CK8>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4","pwm5","pwm6","pwm7","pwm8"; + status = "disabled"; + }; + sgmiisys0: syscon@10060000 { compatible = "mediatek,mt7988-sgmiisys", "mediatek,mt7988-sgmiisys_0", @@ -571,28 +522,6 @@ #clock-cells = <1>; }; - xfi_pextp0: xfi-pextp@11f20000 { - compatible = "mediatek,mt7988-xfi-pextp", - "mediatek,mt7988-xfi-pextp_0", - "syscon"; - reg = <0 0x11f20000 0 0x10000>; - #clock-cells = <1>; - }; - - xfi_pextp1: xfi-pextp@11f30000 { - compatible = "mediatek,mt7988-xfi-pextp", - "mediatek,mt7988-xfi-pextp_1", - "syscon"; - reg = <0 0x11f30000 0 0x10000>; - #clock-cells = <1>; - }; - - xfi_pll: xfi-pll@11f40000 { - compatible = "mediatek,mt7988-xfi-pll", "syscon"; - reg = <0 0x11f40000 0 0x1000>; - #clock-cells = <1>; - }; - mcusys: mcusys@100e0000 { compatible = "mediatek,mt7988-mcusys", "syscon"; reg = <0 0x100e0000 0 0x1000>; @@ -742,25 +671,6 @@ status = "disabled"; }; - pwm: pwm@10048000 { - compatible = "mediatek,mt7988-pwm"; - reg = <0 0x10048000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, - <&infracfg CLK_INFRA_66M_PWM_HCK>, - <&infracfg CLK_INFRA_66M_PWM_CK1>, - <&infracfg CLK_INFRA_66M_PWM_CK2>, - <&infracfg CLK_INFRA_66M_PWM_CK3>, - <&infracfg CLK_INFRA_66M_PWM_CK4>, - <&infracfg CLK_INFRA_66M_PWM_CK5>, - <&infracfg CLK_INFRA_66M_PWM_CK6>, - <&infracfg CLK_INFRA_66M_PWM_CK7>, - <&infracfg CLK_INFRA_66M_PWM_CK8>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3", - "pwm4","pwm5","pwm6","pwm7","pwm8"; - status = "disabled"; - }; - fan: pwm-fan { compatible = "pwm-fan"; /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ @@ -780,15 +690,53 @@ nvmem-cell-names = "e_data1"; }; - crypto: crypto@15600000 { - compatible = "inside-secure,safexcel-eip197b"; - reg = <0 0x15600000 0 0x180000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - status = "okay"; + ssusb0: usb@11190000 { + compatible = "mediatek,mt7988-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, + <0 0x11193e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&xphyu2port0 PHY_TYPE_USB2>, + <&xphyu3port0 PHY_TYPE_USB3>; + clocks = <&infracfg CLK_INFRA_USB_SYS>, + <&infracfg CLK_INFRA_USB_XHCI>, + <&infracfg CLK_INFRA_USB_REF>, + <&infracfg CLK_INFRA_66M_USB_HCK>, + <&infracfg CLK_INFRA_133M_USB_HCK>; + clock-names = "sys_ck", + "xhci_ck", + "ref_ck", + "mcu_ck", + "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + mediatek,p0_speed_fixup; + status = "disabled"; + }; + + ssusb1: usb@11200000 { + compatible = "mediatek,mt7988-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&tphyu2port0 PHY_TYPE_USB2>, + <&tphyu3port0 PHY_TYPE_USB3>; + clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, + <&infracfg CLK_INFRA_USB_CK_P1>, + <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; + clock-names = "sys_ck", + "xhci_ck", + "ref_ck", + "mcu_ck", + "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; }; afe: audio-controller@11210000 { @@ -820,6 +768,29 @@ status = "disabled"; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc", + "mediatek,mt7981-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11D60000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_MSDC400>, + <&infracfg CLK_INFRA_MSDC2_HCK>, + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, + <&topckgen CLK_TOP_EMMC_400M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, + <&apmixedsys CLK_APMIXED_MSDCPLL>; + clock-names = "source", + "hclk", + "axi_cg", + "ahb_cg"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pcie2: pcie@11280000 { compatible = "mediatek,mt7988-pcie", "mediatek,mt7986-pcie", @@ -979,78 +950,6 @@ }; }; - ssusb0: usb@11190000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11190000 0 0x2e00>, - <0 0x11193e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&xphyu2port0 PHY_TYPE_USB2>, - <&xphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS>, - <&infracfg CLK_INFRA_USB_XHCI>, - <&infracfg CLK_INFRA_USB_REF>, - <&infracfg CLK_INFRA_66M_USB_HCK>, - <&infracfg CLK_INFRA_133M_USB_HCK>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - mediatek,p0_speed_fixup; - status = "disabled"; - }; - - ssusb1: usb@11200000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&tphyu2port0 PHY_TYPE_USB2>, - <&tphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, - <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, - <&infracfg CLK_INFRA_USB_CK_P1>, - <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, - <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc", - "mediatek,mt7981-mmc"; - reg = <0 0x11230000 0 0x1000>, - <0 0x11D60000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_MSDC400>, - <&infracfg CLK_INFRA_MSDC2_HCK>, - <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, - <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, - <&topckgen CLK_TOP_EMMC_400M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, - <&apmixedsys CLK_APMIXED_MSDCPLL>; - clock-names = "source", - "hclk", - "axi_cg", - "ahb_cg"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - tphy: tphy@11c50000 { compatible = "mediatek,mt7988", "mediatek,generic-tphy-v2"; @@ -1108,6 +1007,28 @@ }; }; + xfi_pextp0: xfi-pextp@11f20000 { + compatible = "mediatek,mt7988-xfi-pextp", + "mediatek,mt7988-xfi-pextp_0", + "syscon"; + reg = <0 0x11f20000 0 0x10000>; + #clock-cells = <1>; + }; + + xfi_pextp1: xfi-pextp@11f30000 { + compatible = "mediatek,mt7988-xfi-pextp", + "mediatek,mt7988-xfi-pextp_1", + "syscon"; + reg = <0 0x11f30000 0 0x10000>; + #clock-cells = <1>; + }; + + xfi_pll: xfi-pll@11f40000 { + compatible = "mediatek,mt7988-xfi-pll", "syscon"; + reg = <0 0x11f40000 0 0x1000>; + #clock-cells = <1>; + }; + efuse: efuse@11f50000 { compatible = "mediatek,efuse"; reg = <0 0x11f50000 0 0x1000>; @@ -1437,5 +1358,84 @@ }; }; }; + + crypto: crypto@15600000 { + compatible = "inside-secure,safexcel-eip197b"; + reg = <0 0x15600000 0 0x180000>; + interrupts = , + , + , + ; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + status = "okay"; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 0>; + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_med: active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_med>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; }; }; From 1fa705dbec070014358be432096aef7defc4af4a Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Thu, 30 Nov 2023 13:38:51 -0800 Subject: [PATCH 02/20] realtek: fix addresses in DT node names Mostly wrong address format, one missing address, and one spurious address suffix. Signed-off-by: Rosen Penev [amend commit message] Signed-off-by: Sander Vanheule --- .../linux/realtek/dts-5.15/rtl838x_hpe_1920.dtsi | 14 +++++++------- .../realtek/dts-5.15/rtl9302_zyxel_xgs1250-12.dts | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/linux/realtek/dts-5.15/rtl838x_hpe_1920.dtsi b/target/linux/realtek/dts-5.15/rtl838x_hpe_1920.dtsi index e18f61345e..c7b6013117 100644 --- a/target/linux/realtek/dts-5.15/rtl838x_hpe_1920.dtsi +++ b/target/linux/realtek/dts-5.15/rtl838x_hpe_1920.dtsi @@ -50,43 +50,43 @@ read-only; }; - partition@0x60000 { + partition@60000 { label = "bootware_data"; reg = <0x60000 0x30000>; read-only; }; - partition@0x90000 { + partition@90000 { label = "bootware_extend"; reg = <0x90000 0x40000>; read-only; }; - partition@0x100000 { + partition@100000 { label = "bootware_basic_backup"; reg = <0x100000 0x50000>; read-only; }; - partition@0x160000 { + partition@160000 { label = "bootware_data_backup"; reg = <0x160000 0x30000>; read-only; }; - partition@0x190000 { + partition@190000 { label = "bootware_extend_backup"; reg = <0x190000 0x40000>; read-only; }; - partition@0x300000 { + partition@300000 { label = "firmware"; compatible = "h3c,vfs-firmware"; reg = <0x300000 0x1cf0000>; }; - partition@0x1ff0000 { + partition@1ff0000 { label = "factory"; reg = <0x1ff0000 0x10000>; read-only; diff --git a/target/linux/realtek/dts-5.15/rtl9302_zyxel_xgs1250-12.dts b/target/linux/realtek/dts-5.15/rtl9302_zyxel_xgs1250-12.dts index a9821b2cc6..0fe8f1997e 100644 --- a/target/linux/realtek/dts-5.15/rtl9302_zyxel_xgs1250-12.dts +++ b/target/linux/realtek/dts-5.15/rtl9302_zyxel_xgs1250-12.dts @@ -29,7 +29,7 @@ }; /* i2c of the SFP cage: port 12 */ - i2c0: i2c-rtl9300 { + i2c0: i2c-rtl9300@1b00036c { compatible = "realtek,rtl9300-i2c"; reg = <0x1b00036c 0x3c>; #address-cells = <1>; @@ -62,7 +62,7 @@ tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; - led_set: led_set@0 { + led_set: led_set { compatible = "realtek,rtl9300-leds"; active-low; From 782eb050082acac93c2f9b3eb22348234bc93e99 Mon Sep 17 00:00:00 2001 From: Xavier Franquet Date: Mon, 20 Nov 2023 08:18:00 +0100 Subject: [PATCH 03/20] mediatek: filogic: add support ASUS RT-AX59U (based on support for ASUS RT-AX59U by liushiyou006) SOC: MediaTek MT7986 RAM: 512MB DDR4 FLASH: 128MB SPI-NAND (Winbond W25N01GV) WIFI: Mediatek MT7986 DBDC 802.11ax 2.4/5 GHz ETH: MediaTek MT7531 Switch UART: 3V3 115200 8N1 (Pinout silkscreened / Do not connect VCC) Upgrade from AsusWRT to OpenWRT using UART Download the OpenWrt initramfs image. Copy the image to a TFTP server reachable at 192.168.1.70/24. Rename the image to rtax59u.bin. Connect the PC with TFTP server to the RT-AX59U. Set a static ip on the ethernet interface of your PC. (ip address: 192.168.1.70, subnet mask:255.255.255.0) Conect to the serial console, interrupt the autoboot process by pressing '4' when prompted. Download & Boot the OpenWrt initramfs image. $ setenv ipaddr 192.168.1.1 $ setenv serverip 192.168.1.70 $ tftpboot 0x46000000 rtax59u.bin $ bootm 0x46000000 Wait for OpenWrt to boot. Transfer the sysupgrade image to the device using scp and install using sysupgrade. $ sysupgrade -n Upgrade from AsusWRT to OpenWRT using WebUI Download transit TRX file from https://drive.google.com/drive/folders/1A20QdjK7Udagu31FSszpWAk8-cGlCwsq Upgrade firmware from WebUI (192.168.50.1) using downloaded TRX file Wait for OpenWRT to boot (192.168.1.1). Upgrade system with sysupgrade image using luci or uploading it through scp and executing sysupgrade command MAC Address for WLAN 5g is not following the same algorithm as in AsusWRT. We have increased by one the WLAN 5g to avoid collisions with other networks from WLAN 2g when bit 28 is already set. : Stock : OpenWrt WLAN 2g (1) : C8:xx:xx:0D:xx:D4 : C8:xx:xx:0D:xx:D4 WLAN 2g (2) : : CA:xx:xx:0D:xx:D4 WLAN 2g (3) : : CE:xx:xx:0D:xx:D4 WLAN 5g (1) : CA:xx:xx:1D:xx:D4 : CA:xx:xx:1D:xx:D5 WLAN 5g (2) : : CE:xx:xx:1D:xx:D5 WLAN 5g (3) : : C2:xx:xx:1D:xx:D5 WLAN 2g (1) : 08:xx:xx:76:xx:BE : 08:xx:xx:76:xx:BE WLAN 2g (2) : : 0A:xx:xx:76:xx:BE WLAN 2g (3) : : 0E:xx:xx:76:xx:BE WLAN 5g (1) : 0A:xx:xx:76:xx:BE : 0A:xx:xx:76:xx:BF WLAN 5g (2) : : 0E:xx:xx:76:xx:BF WLAN 5g (3) : : 02:xx:xx:76:xx:BF Signed-off-by: Xavier Franquet --- .../uboot-envtools/files/mediatek_filogic | 3 + .../mediatek/dts/mt7986a-asus-rt-ax59u.dts | 263 ++++++++++++++++++ .../filogic/base-files/etc/board.d/02_network | 18 +- .../etc/hotplug.d/firmware/11-mt76-caldata | 1 + .../etc/hotplug.d/ieee80211/11_fix_wifi_mac | 10 + .../base-files/lib/upgrade/platform.sh | 17 ++ target/linux/mediatek/image/filogic.mk | 10 + 7 files changed, 314 insertions(+), 8 deletions(-) create mode 100644 target/linux/mediatek/dts/mt7986a-asus-rt-ax59u.dts diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic index 8e8cb67a71..b4957c212b 100644 --- a/package/boot/uboot-envtools/files/mediatek_filogic +++ b/package/boot/uboot-envtools/files/mediatek_filogic @@ -12,6 +12,9 @@ touch /etc/config/ubootenv board=$(board_name) case "$board" in +asus,rt-ax59u) + ubootenv_add_uci_config "/dev/mtd0" "0x100000" "0x20000" "0x20000" + ;; bananapi,bpi-r3) rootdev="$(cmdline_get_var root)" rootdev="${rootdev##*/}" diff --git a/target/linux/mediatek/dts/mt7986a-asus-rt-ax59u.dts b/target/linux/mediatek/dts/mt7986a-asus-rt-ax59u.dts new file mode 100644 index 0000000000..15cd69aaae --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-asus-rt-ax59u.dts @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + + model = "ASUS RT-AX59U"; + compatible = "asus,rt-ax59u", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + led-boot = &led_status_green; + led-failsafe = &led_status_red; + led-running = &led_status_green; + led-upgrade = &led_status_blue; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-override = "ubi.mtd=UBI_DEV"; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + keys { + compatible = "gpio-keys"; + + button-0 { + label = "wps"; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-1 { + label = "reset"; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_green: led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + led_status_red: led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + + led_status_blue: led-2 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 13 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-export { + compatible = "gpio-export"; + + out { + gpio-export,name = "led-light"; + gpio-export,output = <0>; + gpios = <&pio 22 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + /* LAN */ + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "wan"; + }; + + port@2 { + reg = <2>; + label = "lan1"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan3"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&pio { + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <20000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x400000>; + read-only; + }; + + partition@400000 { + label = "UBI_DEV"; + reg = <0x400000 0x7c00000>; + }; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&ssusb { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index adbd937acf..a36d998a40 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -14,6 +14,15 @@ mediatek_setup_interfaces() acer,predator-w6) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 game" eth1 ;; + asus,rt-ax59u|\ + cetron,ct3003|\ + confiabits,mt7981|\ + cudy,wr3000-v1|\ + jcg,q30-pro|\ + qihoo,360t7|\ + routerich,ax3000) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" wan + ;; asus,tuf-ax4200|\ mediatek,mt7981-rfb|\ zbtlink,zbt-z8102ax) @@ -25,14 +34,6 @@ mediatek_setup_interfaces() bananapi,bpi-r3) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 sfp2" "eth1 wan" ;; - cetron,ct3003|\ - confiabits,mt7981|\ - cudy,wr3000-v1|\ - jcg,q30-pro|\ - qihoo,360t7|\ - routerich,ax3000) - ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" wan - ;; cmcc,rax3000m|\ h3c,magic-nx30-pro|\ zbtlink,zbt-z8103ax) @@ -96,6 +97,7 @@ mediatek_setup_macs() local label_mac="" case $board in + asus,rt-ax59u|\ asus,tuf-ax4200|\ asus,tuf-ax6000) CI_UBIPART="UBI_DEV" diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata index e3181b2d8c..cbbf1871a5 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata @@ -59,6 +59,7 @@ case "$FIRMWARE" in ;; "mediatek/mt7986_eeprom_mt7976_dbdc.bin") case "$board" in + asus,rt-ax59u|\ asus,tuf-ax4200) CI_UBIPART="UBI_DEV" caldata_extract_ubi "Factory" 0x0 0x1000 diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index ca98350a1b..7f013732d3 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -16,6 +16,16 @@ case "$board" in [ "$PHYNBR" = "1" ] && cat $key_path/6gMAC > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "2" ] && cat $key_path/5gMAC > /sys${DEVPATH}/macaddress ;; + asus,rt-ax59u) + CI_UBIPART="UBI_DEV" + addr=$(mtd_get_mac_binary_ubi "Factory" 0x4) + # Originally, phy1 is phy0 mac with LA and 28th bits set. However, this would conflict + # addresses on multiple VIFs with the other radio when bit 28 is already set. + # Set LA and 28 bits and increment mac-address instead. + [ "$PHYNBR" = "1" ] && \ + macaddr_setbit_la $(macaddr_setbit $(macaddr_add $addr 1) 28) > \ + /sys${DEVPATH}/macaddress + ;; asus,tuf-ax4200|\ asus,tuf-ax6000) CI_UBIPART="UBI_DEV" diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index e59ffcfbc7..9600f8745f 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -1,5 +1,16 @@ REQUIRE_IMAGE_METADATA=1 +asus_initial_setup() +{ + # initialize UBI if it's running on initramfs + [ "$(rootfs_type)" = "tmpfs" ] || return 0 + + ubirmvol /dev/ubi0 -N rootfs + ubirmvol /dev/ubi0 -N rootfs_data + ubirmvol /dev/ubi0 -N jffs2 + ubimkvol /dev/ubi0 -N jffs2 -s 0x3e000 +} + xiaomi_initial_setup() { # initialize UBI and setup uboot-env if it's running on initramfs @@ -60,6 +71,7 @@ platform_do_upgrade() { CI_ROOTPART="rootfs" emmc_do_upgrade "$1" ;; + asus,rt-ax59u|\ asus,tuf-ax4200|\ asus,tuf-ax6000) CI_UBIPART="UBI_DEV" @@ -194,6 +206,11 @@ platform_pre_upgrade() { local board=$(board_name) case "$board" in + asus,rt-ax59u|\ + asus,tuf-ax4200|\ + asus,tuf-ax6000) + asus_initial_setup + ;; xiaomi,mi-router-wr30u-stock|\ xiaomi,redmi-router-ax6000-stock) xiaomi_initial_setup diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 249810bcd8..15951df1ec 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -175,6 +175,16 @@ $(call Device/adtran_smartrg) endef TARGET_DEVICES += smartrg_sdg-8632 +define Device/asus_rt-ax59u + DEVICE_VENDOR := ASUS + DEVICE_MODEL := RT-AX59U + DEVICE_DTS := mt7986a-asus-rt-ax59u + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += asus_rt-ax59u + define Device/asus_tuf-ax4200 DEVICE_VENDOR := ASUS DEVICE_MODEL := TUF-AX4200 From 4e8c9cebe5b00033ef24330cd175ec1c0ec958b2 Mon Sep 17 00:00:00 2001 From: Pascal Ernster Date: Sun, 28 May 2023 14:07:20 +0200 Subject: [PATCH 04/20] realtek: Use hex for "soc" identifier in debugfs The upper 16 bits of the 32 bit value encode the SoC model in BCD notation (for example 0x83806800 on a Netgear GS108Tv3 with an RTL8380M), so it makes more sense to output the value in hex notation than in decimal notation. Signed-off-by: Pascal Ernster --- .../linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c index f46833f6f7..1c32d47c6f 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c @@ -605,7 +605,7 @@ void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv) priv->dbgfs_dir = rtl838x_dir; - debugfs_create_u32("soc", 0444, rtl838x_dir, + debugfs_create_x32("soc", 0444, rtl838x_dir, (u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO)); /* Create one directory per port */ From 4693514ca8879576442024368736d0ddd8c7dc3f Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Fri, 1 Dec 2023 15:51:42 -0800 Subject: [PATCH 05/20] oxnas: do not use pcie-controller This was deprecated in kernel 4.14 Signed-off-by: Rosen Penev --- target/linux/oxnas/patches-5.15/340-oxnas-pcie.patch | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/oxnas/patches-5.15/340-oxnas-pcie.patch b/target/linux/oxnas/patches-5.15/340-oxnas-pcie.patch index 8de7ec5386..8315acaee9 100644 --- a/target/linux/oxnas/patches-5.15/340-oxnas-pcie.patch +++ b/target/linux/oxnas/patches-5.15/340-oxnas-pcie.patch @@ -38,7 +38,7 @@ }; }; + -+ pcie0: pcie-controller@47c00000 { ++ pcie0: pcie@47c00000 { + compatible = "plxtech,nas782x-pcie"; + device_type = "pci"; + #address-cells = <3>; @@ -78,7 +78,7 @@ + status = "disabled"; + }; + -+ pcie1: pcie-controller@47e00000 { ++ pcie1: pcie@47e00000 { + compatible = "plxtech,nas782x-pcie"; + device_type = "pci"; + #address-cells = <3>; From 511578c128121326a3c48fdb35e4e62f96dc7b9d Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Wed, 27 Dec 2023 14:21:46 +0100 Subject: [PATCH 06/20] wolfssl: update to 5.6.6 Release Notes: https://github.com/wolfSSL/wolfssl/releases/tag/v5.6.6-stable Refresh patches: - 100-disable-hardening-check.patch Fixes: CVE-2023-6935 CVE-2023-6936 CVE-2023-6937 Signed-off-by: Nick Hainke --- package/libs/wolfssl/Makefile | 4 ++-- .../libs/wolfssl/patches/100-disable-hardening-check.patch | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/package/libs/wolfssl/Makefile b/package/libs/wolfssl/Makefile index 6451dca68d..8477fb85c5 100644 --- a/package/libs/wolfssl/Makefile +++ b/package/libs/wolfssl/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=wolfssl -PKG_VERSION:=5.6.4-stable +PKG_VERSION:=5.6.6-stable PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://github.com/wolfSSL/wolfssl/archive/v$(PKG_VERSION) -PKG_HASH:=031691906794ff45e1e792561cf31759f5d29ac74936bc8dffb8b14f16d820b4 +PKG_HASH:=3d2ca672d41c2c2fa667885a80d6fa03c3e91f0f4f72f87aef2bc947e8c87237 PKG_FIXUP:=libtool libtool-abiver PKG_INSTALL:=1 diff --git a/package/libs/wolfssl/patches/100-disable-hardening-check.patch b/package/libs/wolfssl/patches/100-disable-hardening-check.patch index 368ec3e7e0..019645d796 100644 --- a/package/libs/wolfssl/patches/100-disable-hardening-check.patch +++ b/package/libs/wolfssl/patches/100-disable-hardening-check.patch @@ -1,6 +1,6 @@ --- a/wolfssl/wolfcrypt/settings.h +++ b/wolfssl/wolfcrypt/settings.h -@@ -2630,7 +2630,7 @@ extern void uITRON4_free(void *p) ; +@@ -2774,7 +2774,7 @@ extern void uITRON4_free(void *p) ; /* warning for not using harden build options (default with ./configure) */ /* do not warn if big integer support is disabled */ From 131403d8aae659a4e1393ad252e19bf1fd5fb428 Mon Sep 17 00:00:00 2001 From: John Audia Date: Mon, 1 Jan 2024 09:47:05 -0500 Subject: [PATCH 07/20] kernel: bump 6.1 to 6.1.70 Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.1.70 All patches automatically rebased. Build system: x86/64 Build-tested: x86/64/AMD Cezanne, filogic/xiaomi_redmi-router-ax6000-ubootmod Run-tested: x86/64/AMD Cezanne, filogic/xiaomi_redmi-router-ax6000-ubootmod Signed-off-by: John Audia --- include/kernel-6.1 | 4 ++-- ...ers-remove-legacy_cursor_update-hacks.patch | 2 +- ...h-Always-request-for-user-confirmatio.patch | 4 ++-- .../721-net-add-packet-mangeling.patch | 2 +- .../780-usb-net-MeigLink_modem_support.patch | 4 ++-- ...ET-skip-GRO-for-foreign-MAC-addresses.patch | 8 ++++---- ...tional-threading-for-backlog-processi.patch | 18 +++++++++--------- ...et-introduce-napi_is_scheduled-helper.patch | 2 +- 8 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/kernel-6.1 b/include/kernel-6.1 index b42886811e..8cfdaad6d7 100644 --- a/include/kernel-6.1 +++ b/include/kernel-6.1 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.1 = .69 -LINUX_KERNEL_HASH-6.1.69 = 7e3d2694d18ce502068cc88a430da809abbd17d0773268524ebece442612b541 +LINUX_VERSION-6.1 = .70 +LINUX_KERNEL_HASH-6.1.70 = ed1365266456c07696a7499581aec5d851ca2296f4f6f90f23d189ea5a56afef diff --git a/target/linux/bcm27xx/patches-6.1/950-0045-drm-atomic-helpers-remove-legacy_cursor_update-hacks.patch b/target/linux/bcm27xx/patches-6.1/950-0045-drm-atomic-helpers-remove-legacy_cursor_update-hacks.patch index 178d0c514e..b64f2972c5 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0045-drm-atomic-helpers-remove-legacy_cursor_update-hacks.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0045-drm-atomic-helpers-remove-legacy_cursor_update-hacks.patch @@ -88,7 +88,7 @@ Signed-off-by: Maxime Ripard commit->event = kzalloc(sizeof(*commit->event), --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c -@@ -7743,6 +7743,19 @@ static int intel_atomic_commit(struct dr +@@ -7754,6 +7754,19 @@ static int intel_atomic_commit(struct dr state->base.legacy_cursor_update = false; } diff --git a/target/linux/bcm27xx/patches-6.1/950-0078-Revert-Bluetooth-Always-request-for-user-confirmatio.patch b/target/linux/bcm27xx/patches-6.1/950-0078-Revert-Bluetooth-Always-request-for-user-confirmatio.patch index 7304bf8bb6..bd2ccaa197 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0078-Revert-Bluetooth-Always-request-for-user-confirmatio.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0078-Revert-Bluetooth-Always-request-for-user-confirmatio.patch @@ -24,7 +24,7 @@ Signed-off-by: Phil Elwell --- a/net/bluetooth/smp.c +++ b/net/bluetooth/smp.c -@@ -2207,7 +2207,7 @@ mackey_and_ltk: +@@ -2214,7 +2214,7 @@ mackey_and_ltk: if (err) return SMP_UNSPECIFIED; @@ -33,7 +33,7 @@ Signed-off-by: Phil Elwell if (hcon->out) { sc_dhkey_check(smp); SMP_ALLOW_CMD(smp, SMP_CMD_DHKEY_CHECK); -@@ -2222,9 +2222,6 @@ mackey_and_ltk: +@@ -2229,9 +2229,6 @@ mackey_and_ltk: confirm_hint = 0; confirm: diff --git a/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch b/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch index 9ce8f82af0..40aeb5da6f 100644 --- a/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch +++ b/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch @@ -105,7 +105,7 @@ Signed-off-by: Felix Fietkau help --- a/net/core/dev.c +++ b/net/core/dev.c -@@ -3604,6 +3604,11 @@ static int xmit_one(struct sk_buff *skb, +@@ -3607,6 +3607,11 @@ static int xmit_one(struct sk_buff *skb, if (dev_nit_active(dev)) dev_queue_xmit_nit(skb, dev); diff --git a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch index 481185122f..51f939356f 100644 --- a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch +++ b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch @@ -43,7 +43,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support #define QUECTEL_VENDOR_ID 0x2c7c /* These Quectel products use Quectel's vendor ID */ -@@ -1146,6 +1151,11 @@ static const struct usb_device_id option +@@ -1147,6 +1152,11 @@ static const struct usb_device_id option { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */ { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */ .driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) }, @@ -55,7 +55,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support /* Quectel products using Qualcomm vendor ID */ { USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)}, { USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20), -@@ -1187,6 +1197,11 @@ static const struct usb_device_id option +@@ -1188,6 +1198,11 @@ static const struct usb_device_id option .driver_info = ZLP }, { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), .driver_info = RSVD(4) }, diff --git a/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch index 094d63dd89..8763b92c02 100644 --- a/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch +++ b/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch @@ -44,7 +44,7 @@ Signed-off-by: Felix Fietkau --- a/net/core/dev.c +++ b/net/core/dev.c -@@ -7622,6 +7622,48 @@ static void __netdev_adjacent_dev_unlink +@@ -7625,6 +7625,48 @@ static void __netdev_adjacent_dev_unlink &upper_dev->adj_list.lower); } @@ -93,7 +93,7 @@ Signed-off-by: Felix Fietkau static int __netdev_upper_dev_link(struct net_device *dev, struct net_device *upper_dev, bool master, void *upper_priv, void *upper_info, -@@ -7673,6 +7715,7 @@ static int __netdev_upper_dev_link(struc +@@ -7676,6 +7718,7 @@ static int __netdev_upper_dev_link(struc if (ret) return ret; @@ -101,7 +101,7 @@ Signed-off-by: Felix Fietkau ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER, &changeupper_info.info); ret = notifier_to_errno(ret); -@@ -7769,6 +7812,7 @@ static void __netdev_upper_dev_unlink(st +@@ -7772,6 +7815,7 @@ static void __netdev_upper_dev_unlink(st __netdev_adjacent_dev_unlink_neighbour(dev, upper_dev); @@ -109,7 +109,7 @@ Signed-off-by: Felix Fietkau call_netdevice_notifiers_info(NETDEV_CHANGEUPPER, &changeupper_info.info); -@@ -8821,6 +8865,7 @@ int dev_set_mac_address(struct net_devic +@@ -8824,6 +8868,7 @@ int dev_set_mac_address(struct net_devic if (err) return err; dev->addr_assign_type = NET_ADDR_SET; diff --git a/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch b/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch index e50a3ef699..baaf850fe4 100644 --- a/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch +++ b/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau #endif --- a/net/core/dev.c +++ b/net/core/dev.c -@@ -4622,7 +4622,7 @@ static int napi_schedule_rps(struct soft +@@ -4625,7 +4625,7 @@ static int napi_schedule_rps(struct soft struct softnet_data *mysd = this_cpu_ptr(&softnet_data); #ifdef CONFIG_RPS @@ -39,7 +39,7 @@ Signed-off-by: Felix Fietkau sd->rps_ipi_next = mysd->rps_ipi_list; mysd->rps_ipi_list = sd; -@@ -5803,6 +5803,8 @@ static DEFINE_PER_CPU(struct work_struct +@@ -5806,6 +5806,8 @@ static DEFINE_PER_CPU(struct work_struct /* Network device is going away, flush any packets still pending */ static void flush_backlog(struct work_struct *work) { @@ -48,7 +48,7 @@ Signed-off-by: Felix Fietkau struct sk_buff *skb, *tmp; struct softnet_data *sd; -@@ -5817,8 +5819,17 @@ static void flush_backlog(struct work_st +@@ -5820,8 +5822,17 @@ static void flush_backlog(struct work_st input_queue_head_incr(sd); } } @@ -66,7 +66,7 @@ Signed-off-by: Felix Fietkau skb_queue_walk_safe(&sd->process_queue, skb, tmp) { if (skb->dev->reg_state == NETREG_UNREGISTERING) { __skb_unlink(skb, &sd->process_queue); -@@ -5826,7 +5837,16 @@ static void flush_backlog(struct work_st +@@ -5829,7 +5840,16 @@ static void flush_backlog(struct work_st input_queue_head_incr(sd); } } @@ -83,7 +83,7 @@ Signed-off-by: Felix Fietkau } static bool flush_required(int cpu) -@@ -5958,6 +5978,7 @@ static int process_backlog(struct napi_s +@@ -5961,6 +5981,7 @@ static int process_backlog(struct napi_s } rps_lock_irq_disable(sd); @@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau if (skb_queue_empty(&sd->input_pkt_queue)) { /* * Inline a custom version of __napi_complete(). -@@ -5967,7 +5988,8 @@ static int process_backlog(struct napi_s +@@ -5970,7 +5991,8 @@ static int process_backlog(struct napi_s * We can use a plain write instead of clear_bit(), * and we dont need an smp_mb() memory barrier. */ @@ -101,7 +101,7 @@ Signed-off-by: Felix Fietkau again = false; } else { skb_queue_splice_tail_init(&sd->input_pkt_queue, -@@ -6383,6 +6405,55 @@ int dev_set_threaded(struct net_device * +@@ -6386,6 +6408,55 @@ int dev_set_threaded(struct net_device * } EXPORT_SYMBOL(dev_set_threaded); @@ -157,7 +157,7 @@ Signed-off-by: Felix Fietkau void netif_napi_add_weight(struct net_device *dev, struct napi_struct *napi, int (*poll)(struct napi_struct *, int), int weight) { -@@ -11165,6 +11236,9 @@ static int dev_cpu_dead(unsigned int old +@@ -11168,6 +11239,9 @@ static int dev_cpu_dead(unsigned int old raise_softirq_irqoff(NET_TX_SOFTIRQ); local_irq_enable(); @@ -167,7 +167,7 @@ Signed-off-by: Felix Fietkau #ifdef CONFIG_RPS remsd = oldsd->rps_ipi_list; oldsd->rps_ipi_list = NULL; -@@ -11468,6 +11542,7 @@ static int __init net_dev_init(void) +@@ -11471,6 +11545,7 @@ static int __init net_dev_init(void) INIT_CSD(&sd->defer_csd, trigger_rx_softirq, sd); spin_lock_init(&sd->defer_lock); diff --git a/target/linux/ipq806x/patches-6.1/700-01-net-introduce-napi_is_scheduled-helper.patch b/target/linux/ipq806x/patches-6.1/700-01-net-introduce-napi_is_scheduled-helper.patch index 35c0d850cd..f59c461f65 100644 --- a/target/linux/ipq806x/patches-6.1/700-01-net-introduce-napi_is_scheduled-helper.patch +++ b/target/linux/ipq806x/patches-6.1/700-01-net-introduce-napi_is_scheduled-helper.patch @@ -66,7 +66,7 @@ Signed-off-by: Christian Marangi /** --- a/net/core/dev.c +++ b/net/core/dev.c -@@ -6591,7 +6591,7 @@ static int __napi_poll(struct napi_struc +@@ -6594,7 +6594,7 @@ static int __napi_poll(struct napi_struc * accidentally calling ->poll() when NAPI is not scheduled. */ work = 0; From b22539b5fef9572f9ce2bedcd01d083c918d82f1 Mon Sep 17 00:00:00 2001 From: Patryk Kowalczyk Date: Tue, 2 Jan 2024 10:37:47 +0100 Subject: [PATCH 08/20] mediatek: filogic: Asus TUF AX6000 fix inverted LED for 2.5Gb LAN port Router Asus TUF AX6000 have second MaxLinear GPY211 PHY controller for 2.5Gb LAN port. The 5'th LAN port have inverted status of the LED. Based on the commit from main branch 90fbec8 we could set proper status of the LED. Signed-off-by: Patryk Kowalczyk --- target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts b/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts index 41e6d2471d..b05dec93b4 100644 --- a/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts +++ b/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts @@ -131,6 +131,7 @@ compatible = "ethernet-phy-ieee802.3-c45"; reg = <5>; + mxl,led-drive-vdd; mxl,led-config = <0x03f0 0x0 0x0 0x0>; }; From fdb87a91b4202ad1a58fe46f499e4e68bf82de4e Mon Sep 17 00:00:00 2001 From: Roland Reinl Date: Sun, 12 Nov 2023 19:04:32 +0100 Subject: [PATCH 09/20] mediatek: Add support for D-Link EAGLE PRO AI R32 R32 is like the M32 part of the EAGLE PRO AI series from D-Link. Specification: - MT7622BV SoC with 2.4GHz wifi - MT7975AN + MT7915AN for 5GHz - MT7531BE Switch - 512MB RAM - 128 MB flash - 2 LEDs (Status and Internet, both can be either orange or white) - 2 buttons (WPS and Reset) Compared to M32, the R32 has the following differences: - 4 LAN ports instead of 2 - The recory image starts with DLK6E6015001 instaed of DLK6E6010001 - Individual LEDs for power and internet - MAC address is stored at another offset in the ODM partition MAC addresses: - WAN MAC is stored in partition "Odm" at offset 0x81 - LAN (as printed on the device) is WAN MAC + 1 - WLAN MAC (2.4 GHz) is WAN MAC + 2 - WLAN MAC (5GHz) is WAN MAC + 3 Flashing via Recovery Web Interface: - Set your IP address to 192.168.0.10, subnetmask 255.255.255.0 - Press the reset button while powering on the deivce - Keep the reset button pressed until the internet LED blinks fast - Open a Chromium based and goto http://192.168.0.1 - Download openwrt-mediatek-mt7622-dlink_eagle-pro-ai-r32-a1-squashfs-recovery.bin Flashing via uBoot: - Open the case, connect to the UART console - Set your IP address to 10.10.10.3, subnet mask 255.255.255.0. Connect to one of the LAN interfaces of the router - Run a tftp server which provides openwrt-mediatek-mt7622-dlink_eagle-pro-ai-r32-initramfs-kernel.bin. - You can rename the file to iverson_uImage (no extension), then you don't have to enter the whole file name in uboot later. - Power on the device and select "1. System Load Linux to SDRAM via TFTP." in the boot menu - Enter image file, tftp server IP and device IP (if they differ from the default). - TFTP download to RAM will start. After a few seconds OpenWrt initramfs should start - The initramfs is accessible via 192.168.1.1, change your IP address accordingly (or use multiple IP addresses on your interface) - Create a backup of the Kernel1 partition, this file is required if a revert to stock should be done later - Perform a sysupgrade using openwrt-mediatek-mt7622-dlink_eagle-pro-ai-r32-squashfs-sysupgrade.bin - Reboot the device. OpenWrt should start from flash now Revert back to stock using the Recovery Web Interface: - Set your IP address to 192.168.0.10, subnetmask 255.255.255.0 - Press the reset button while powering on the deivce - Keep the reset button pressed until the internet LED blinks fast - Open a Chromium based and goto http://192.168.0.1 - Flash a decrypted firmware image from D-Link. Decrypting an firmware image is described below. Decrypting a D-Link firmware image: - Download https://github.com/RolandoMagico/firmware-utils/blob/M32/src/m32-firmware-util.c - Compile a binary from the downloaded file, e.g. gcc m32-firmware-util.c -lcrypto -o m32-firmware-util - Run ./m32-firmware-util R32 --DecryptFactoryImage - Example for firmware R32A1_FW103B01: ./m32-firmware-util R32 --DecryptFactoryImage R32A1_FW103B01.bin R32A1_FW103B01.decrypted.bin Revert back to stock using uBoot: - Open the case, connect to the UART console - Set your IP address to 10.10.10.3, subnet mask 255.255.255.0. Connect to one of the LAN interfaces of the router - Run a tftp server which provides the previously created backup of the Kernel1 partition. - You can rename the file to iverson_uImage (no extension), then you don't have to enter the whole file name in uboot later. - Power on the device and select "2. System Load Linux Kernel then write to Flash via TFTP." in the boot menu - Enter image file, tftp server IP and device IP (if they differ from the default). - TFTP download to FLASH will start. After a few seconds the stock firmware should start again There is also an image openwrt-mediatek-mt7622-dlink_eagle-pro-ai-r32-a1-squashfs-tftp.bin which can directly be flashed via U-Boot and TFTP. It can be used if no backup of the Kernel1 partition is reuqired. Flahsing via OEM web interface is currently not possible, the OEM images are encrypted. Creating images is only possible manually at the moment. The support for the M32/R32 already includes support for flashing from the OEM web interface: - The device tree contains both partitions (Kernel1 and Kernel2) with conditions to select the correct one based on the kernel command line - The U-Boot variable "boot_part" is set accordingly during startup to finish the partition swap after flashing from the OEM web interface - OpenWrt sysupgrade flashing always uses the partition where it was initially flashed to (no partition swap) Signed-off-by: Roland Reinl --- .../boot/uboot-envtools/files/mediatek_mt7622 | 4 + .../mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi | 369 ++++++++++++++++ .../dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts | 394 ++---------------- .../dts/mt7622-dlink-eagle-pro-ai-r32-a1.dts | 78 ++++ target/linux/mediatek/image/mt7622.mk | 40 +- .../mt7622/base-files/etc/board.d/02_network | 5 +- .../etc/hotplug.d/ieee80211/11_fix_wifi_mac | 4 - .../mt7622/base-files/etc/init.d/bootcount | 8 + .../mt7622/base-files/lib/upgrade/platform.sh | 4 +- 9 files changed, 521 insertions(+), 385 deletions(-) create mode 100644 target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi create mode 100644 target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-r32-a1.dts diff --git a/package/boot/uboot-envtools/files/mediatek_mt7622 b/package/boot/uboot-envtools/files/mediatek_mt7622 index e01dcc4fef..fdf0d331fc 100644 --- a/package/boot/uboot-envtools/files/mediatek_mt7622 +++ b/package/boot/uboot-envtools/files/mediatek_mt7622 @@ -12,6 +12,10 @@ touch /etc/config/ubootenv board=$(board_name) case "$board" in +dlink,eagle-pro-ai-m32-a1|\ +dlink,eagle-pro-ai-r32-a1) + ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x2000" "0x2000" + ;; linksys,e8450-ubi) ubootenv_add_uci_config "/dev/ubi0_0" "0x0" "0x1f000" "0x1f000" "1" ubootenv_add_uci_config "/dev/ubi0_1" "0x0" "0x1f000" "0x1f000" "1" diff --git a/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi new file mode 100644 index 0000000000..6d87454370 --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7622.dtsi" +#include "mt6380.dtsi" +#include +#include + +/ { + aliases { + serial0 = &uart0; + label-mac-device = &gmac0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512"; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + + cpu@1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = ; + }; + + button-wps { + gpios = <&pio 102 GPIO_ACTIVE_LOW>; + label = "wps"; + linux,code = ; + }; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&bch { + status = "okay"; +}; + +&btif { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + phy-mode = "2500base-x"; + reg = <0>; + nvmem-cells = <&macaddr_odm 1>; + nvmem-cell-names = "mac-address"; + fixed-link { + full-duplex; + pause; + speed = <2500>; + }; + }; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 54 0>; + + ports { + wan: port@4 { + reg = <4>; + label = "wan"; + nvmem-cells = <&macaddr_odm 0>; + nvmem-cell-names = "mac-address"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&pio { + epa_elna_pins: epa-elna-pins { + mux { + function = "antsel"; + groups = "antsel0", "antsel1", "antsel2", "antsel3", + "antsel4", "antsel5", "antsel6", "antsel7", + "antsel8", "antsel9", "antsel12", "antsel13", + "antsel14", "antsel15", "antsel16", "antsel17"; + }; + }; + + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio", "rgmii_via_gmac2"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pad_perst", + "pcie0_1_waken", + "pcie0_1_clkreq"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie1_pad_perst", + "pcie1_0_waken", + "pcie1_0_clkreq"; + }; + }; + + pmic_bus_pins: pmic-bus-pins { + mux { + function = "pmic"; + groups = "pmic_bus"; + }; + }; + + /* Serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_0_tx_rx"; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&pwrap { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; + status = "okay"; +}; + +&rtc { + status = "disabled"; +}; + +&sata { + status = "disabled"; +}; + +&sata_phy { + status = "disabled"; +}; + +&slot0 { + wmac1: mt7915@0,0 { + reg = <0x0000 0 0 0 0>; + ieee80211-freq-limit = <5000000 6000000>; + mediatek,mtd-eeprom = <&factory 0x05000>; + nvmem-cells = <&macaddr_odm 3>; + nvmem-cell-names = "mac-address"; + }; +}; + +&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; + + snand: flash@0 { + compatible = "spi-nand"; + mediatek,bmt-table-size = <0x1000>; + mediatek,bmt-v2; + nand-ecc-engine = <&snfi>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Preloader"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + partition@80000 { + label = "ATF"; + reg = <0x00080000 0x00040000>; + read-only; + }; + + partition@C0000 { + label = "Bootloader"; + reg = <0x000C0000 0x00080000>; + read-only; + }; + + partition@140000 { + label = "BootConfig"; + reg = <0x00140000 0x00040000>; + }; + + partition@180000 { + label = "Odm"; + reg = <0x00180000 0x00040000>; + read-only; + odm_partition: nvmem-layout { + compatible = "fixed-layout"; + }; + }; + + config1: partition@1C0000 { + compatible = "nvmem-cells"; + label = "Config1"; + reg = <0x001C0000 0x00080000>; + read-only; + }; + + partition@240000 { + label = "Config2"; + reg = <0x00240000 0x00080000>; + read-only; + }; + + partition@2C0000 { + label = "Kernel1"; + reg = <0x002C0000 0x02D00000>; + + compatible = "denx,fit"; + openwrt,cmdline-match = "boot_part=Kernel1"; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00800000>; + }; + + partition@800000 { + label = "ubi"; + reg = <0x00800000 0x02500000>; + }; + }; + + partition@2FC0000 { + label = "Kernel2"; + reg = <0x02FC0000 0x02D00000>; + + compatible = "denx,fit"; + openwrt,cmdline-match = "boot_part=Kernel2"; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00800000>; + }; + + partition@800000 { + label = "ubi"; + reg = <0x00800000 0x02500000>; + }; + }; + + factory: partition@5CC0000 { + label = "Factory"; + reg = <0x05CC0000 0x00100000>; + read-only; + }; + + partition@5DC0000 { + label = "Mydlink"; + reg = <0x05DC0000 0x00200000>; + read-only; + }; + + partition@5FC0000 { + label = "Storage"; + reg = <0x05FC0000 0x00300000>; + read-only; + }; + }; + }; +}; + +&ssusb { + status = "disabled"; +}; + +&u3phy { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; + +&wmac { + pinctrl-names = "default"; + pinctrl-0 = <&epa_elna_pins>; + mediatek,mtd-eeprom = <&factory 0x0000>; + nvmem-cells = <&macaddr_odm 2>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + diff --git a/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts index 9c90cee516..2b40c5e7d5 100644 --- a/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts +++ b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts @@ -1,401 +1,63 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include "mt7622.dtsi" -#include "mt6380.dtsi" -#include -#include +#include "mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi" +#include / { model = "D-Link EAGLE PRO AI M32 A1"; compatible = "dlink,eagle-pro-ai-m32-a1", "mediatek,mt7622"; aliases { - led-boot = &status_orange; - led-failsafe = &status_red; - led-running = &status_white; - led-upgrade = &status_red; - serial0 = &uart0; - label-mac-device = &gmac0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512"; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; - }; - - cpu@1 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - reset { - gpios = <&pio 0 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - }; - - wps { - gpios = <&pio 102 GPIO_ACTIVE_LOW>; - label = "wps"; - linux,code = ; - }; + led-boot = &led_status_orange; + led-failsafe = &led_status_red; + led-running = &led_status_white; + led-upgrade = &led_status_red; }; leds { compatible = "gpio-leds"; - status_white: status_white { - label = "white:status"; + led_status_white: led-status-white { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&pio 85 GPIO_ACTIVE_LOW>; }; - status_orange: status_orange { - label = "orange:status"; + led_status_orange: led-status-orange { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&pio 20 GPIO_ACTIVE_LOW>; default-state = "on"; }; - status_red: status_red { - label = "red:status"; + led_status_red: led-status-red { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&pio 17 GPIO_ACTIVE_LOW>; }; }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; }; -&bch { - status = "okay"; -}; - -&btif { - status = "okay"; -}; - -ð { - pinctrl-names = "default"; - pinctrl-0 = <ð_pins>; - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - nvmem-cells = <&macaddr_odm_83>; - nvmem-cell-names = "mac-address"; - phy-mode = "2500base-x"; - reg = <0>; - - fixed-link { - full-duplex; - pause; - speed = <2500>; +&switch { + ports { + port@2 { + reg = <2>; + label = "lan2"; }; - }; - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "mediatek,mt7531"; - reg = <0>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&pio>; - interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 54 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - wan: port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; + port@3 { + reg = <3>; + label = "lan1"; }; }; }; -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - status = "okay"; -}; - -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_pins>; - status = "okay"; -}; - -&pio { - epa_elna_pins: epa-elna-pins { - mux { - function = "antsel"; - groups = "antsel0", "antsel1", "antsel2", "antsel3", - "antsel4", "antsel5", "antsel6", "antsel7", - "antsel8", "antsel9", "antsel12", "antsel13", - "antsel14", "antsel15", "antsel16", "antsel17"; - }; - }; - - eth_pins: eth-pins { - mux { - function = "eth"; - groups = "mdc_mdio", "rgmii_via_gmac2"; - }; - }; - - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie0_pad_perst", - "pcie0_1_waken", - "pcie0_1_clkreq"; - }; - }; - - pcie1_pins: pcie1-pins { - mux { - function = "pcie"; - groups = "pcie1_pad_perst", - "pcie1_0_waken", - "pcie1_0_clkreq"; - }; - }; - - pmic_bus_pins: pmic-bus-pins { - mux { - function = "pmic"; - groups = "pmic_bus"; - }; - }; - - /* Serial NAND is shared pin with SPI-NOR */ - serial_nand_pins: serial-nand-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0_0_tx_rx"; - }; - }; - - watchdog_pins: watchdog-pins { - mux { - function = "watchdog"; - groups = "watchdog"; - }; +&odm_partition { + macaddr_odm: macaddr@83 { + compatible = "mac-base"; + reg = <0x83 0x6>; + #nvmem-cell-cells = <1>; }; }; -&pwrap { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_bus_pins>; - status = "okay"; -}; - -&rtc { - status = "disabled"; -}; - -&sata { - status = "disabled"; -}; - -&sata_phy { - status = "disabled"; -}; - -&slot0 { - wmac1: mt7915@0,0 { - reg = <0x0000 0 0 0 0>; - ieee80211-freq-limit = <5000000 6000000>; - mediatek,mtd-eeprom = <&factory 0x05000>; - }; -}; - -&snfi { - pinctrl-names = "default"; - pinctrl-0 = <&serial_nand_pins>; - status = "okay"; - - snand: flash@0 { - compatible = "spi-nand"; - mediatek,bmt-table-size = <0x1000>; - mediatek,bmt-v2; - nand-ecc-engine = <&snfi>; - reg = <0>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Preloader"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - partition@80000 { - label = "ATF"; - reg = <0x00080000 0x00040000>; - read-only; - }; - - partition@C0000 { - label = "Bootloader"; - reg = <0x000C0000 0x00080000>; - read-only; - }; - - partition@140000 { - label = "BootConfig"; - reg = <0x00140000 0x00040000>; - read-only; - }; - - odm: partition@180000 { - label = "Odm"; - reg = <0x00180000 0x00040000>; - read-only; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_odm_83: macaddr@83 { - reg = <0x83 0x6>; - }; - }; - }; - - config1: partition@1C0000 { - label = "Config1"; - reg = <0x001C0000 0x00080000>; - read-only; - }; - - partition@240000 { - label = "Config2"; - reg = <0x00240000 0x00080000>; - read-only; - }; - - partition@2C0000 { - label = "Kernel1"; - reg = <0x002C0000 0x02D00000>; - - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "kernel"; - reg = <0x00000000 0x00800000>; - }; - - partition@800000 { - label = "ubi"; - reg = <0x00800000 0x02500000>; - }; - }; - - partition@2FC0000 { - label = "Kernel2"; - reg = <0x02FC0000 0x02D00000>; - read-only; - }; - - factory: partition@5CC0000 { - label = "Factory"; - reg = <0x05CC0000 0x00100000>; - read-only; - }; - - partition@5DC0000 { - label = "Mydlink"; - reg = <0x05DC0000 0x00200000>; - read-only; - }; - - partition@5FC0000 { - label = "Storage"; - reg = <0x05FC0000 0x00300000>; - read-only; - }; - }; - }; -}; - -&ssusb { - status = "disabled"; -}; - -&u3phy { - status = "disabled"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&watchdog { - pinctrl-names = "default"; - pinctrl-0 = <&watchdog_pins>; - status = "okay"; -}; - -&wmac { - pinctrl-names = "default"; - pinctrl-0 = <&epa_elna_pins>; - mediatek,mtd-eeprom = <&factory 0x0000>; - status = "okay"; -}; - diff --git a/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-r32-a1.dts b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-r32-a1.dts new file mode 100644 index 0000000000..b21ba36cfc --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-r32-a1.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi" +#include + +/ { + model = "D-Link EAGLE PRO AI R32 A1"; + compatible = "dlink,eagle-pro-ai-r32-a1", "mediatek,mt7622"; + + aliases { + led-boot = &led_power_orange; + led-failsafe = &led_power_orange; + led-running = &led_power_white; + led-upgrade = &led_power_orange; + }; + + leds { + compatible = "gpio-leds"; + + led_power_orange: led-power-orange { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + }; + + led_power_white: led-power-white { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 85 GPIO_ACTIVE_LOW>; + }; + + led_internet_orange: led-internet-orange { + color = ; + function = "internet"; // LED_FUNCTION_INTERNET; + gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; + + led_internet_white: led-internet-white { + color = ; + function = "internet"; // LED_FUNCTION_INTERNET; + gpios = <&pio 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&switch { + ports { + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + }; +}; + +&odm_partition { + macaddr_odm: macaddr@81 { + compatible = "mac-base"; + reg = <0x81 0x6>; + #nvmem-cell-cells = <1>; + }; +}; + diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk index d0f5280dcf..e393b8433e 100644 --- a/target/linux/mediatek/image/mt7622.mk +++ b/target/linux/mediatek/image/mt7622.mk @@ -37,9 +37,15 @@ define Build/bl31-uboot cat $(STAGING_DIR_IMAGE)/mt7622_$1-u-boot.fip >> $@ endef -# Append header to a D-Link M32 Kernel 1 partition -define Build/m32-recovery-header-kernel1 - echo -en "DLK6E6010001\x00\x00\xCF\x33" > "$@.header" +# Append header to a D-Link M32/R32 Kernel 1 partition +define Build/m32-r32-recovery-header-kernel1 + $(eval header_start=$(word 1,$(1))) +# create $@.header without the checksum + echo -en "$(header_start)\x00\x00" > "$@.header" +# Calculate checksum over data area ($@) and append it to the header. +# The checksum is the 2byte-sum over the whole data area. +# Every overflow during the checksum calculation must increment the current checksum value by 1. + od -v -w2 -tu2 -An --endian little "$@" | awk '{ s+=$$1; } END { s%=65535; printf "%c%c",s%256,s/256; }' >> "$@.header" echo -en "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\x00\x8D\x57\x30\x0B" >> "$@.header" # Byte 0-3: Erase Start 0x002C0000 # Byte 4-7: Erase Length 0x02D00000 @@ -48,9 +54,11 @@ define Build/m32-recovery-header-kernel1 echo -en "\x00\x00\x2C\x00\x00\x00\xD0\x02\x00\x00\x2C\x00\x00\x00\xD0\x02" >> "$@.header" # Only zeros echo -en "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" >> "$@.header" -# Note: The last 2 bytes of the following line are the checksum of the header -# If any data in the header will be changed, the checksum must be re-calculated - echo -en "\x42\x48\x02\x00\x00\x00\x08\x00\x00\x00\x00\x00\x60\x6E\x68\x61" >> "$@.header" +# Last 16 bytes, but without checksum + echo -en "\x42\x48\x02\x00\x00\x00\x08\x00\x00\x00\x00\x00\x60\x6E" >> "$@.header" +# Calculate and append checksum: The checksum must be set so that the 2byte-sum of the whole header is 0. +# Every overflow during the checksum calculation must increment the current checksum value by 1. + od -v -w2 -tu2 -An --endian little "$@.header" | awk '{s+=65535-$$1;}END{s%=65535;printf "%c%c",s%256,s/256;}' >> "$@.header" cat "$@.header" "$@" > "$@.new" mv "$@.new" "$@" rm "$@.header" @@ -168,12 +176,10 @@ define Device/buffalo_wsr-3200ax4s endef TARGET_DEVICES += buffalo_wsr-3200ax4s -define Device/dlink_eagle-pro-ai-m32-a1 +define Device/dlink_eagle-pro-ai-ax3200-a1 IMAGE_SIZE := 46080k DEVICE_VENDOR := D-Link - DEVICE_MODEL := EAGLE PRO AI M32 DEVICE_VARIANT := A1 - DEVICE_DTS := mt7622-dlink-eagle-pro-ai-m32-a1 DEVICE_DTS_DIR := ../dts DEVICE_PACKAGES := kmod-mt7915-firmware KERNEL_SIZE := 8192k @@ -183,10 +189,24 @@ define Device/dlink_eagle-pro-ai-m32-a1 IMAGES += tftp.bin recovery.bin IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata IMAGE/tftp.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | check-size - IMAGE/recovery.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | pad-to $$(IMAGE_SIZE) | m32-recovery-header-kernel1 +endef + +define Device/dlink_eagle-pro-ai-m32-a1 + $(Device/dlink_eagle-pro-ai-ax3200-a1) + DEVICE_MODEL := EAGLE PRO AI M32 + DEVICE_DTS := mt7622-dlink-eagle-pro-ai-m32-a1 + IMAGE/recovery.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | pad-to $$(IMAGE_SIZE) | m32-r32-recovery-header-kernel1 DLK6E6010001 endef TARGET_DEVICES += dlink_eagle-pro-ai-m32-a1 +define Device/dlink_eagle-pro-ai-r32-a1 + $(Device/dlink_eagle-pro-ai-ax3200-a1) + DEVICE_MODEL := EAGLE PRO AI R32 + DEVICE_DTS := mt7622-dlink-eagle-pro-ai-r32-a1 + IMAGE/recovery.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | pad-to $$(IMAGE_SIZE) | m32-r32-recovery-header-kernel1 DLK6E6015001 +endef +TARGET_DEVICES += dlink_eagle-pro-ai-r32-a1 + define Device/elecom_wrc-2533gent DEVICE_VENDOR := Elecom DEVICE_MODEL := WRC-2533GENT diff --git a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network index 75c5e37be1..6c43e46222 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network @@ -10,6 +10,7 @@ mediatek_setup_interfaces() case $board in bananapi,bpi-r64|\ buffalo,wsr-3200ax4s|\ + dlink,eagle-pro-ai-r32-a1|\ elecom,wrc-x3200gst3|\ linksys,e8450|\ linksys,e8450-ubi|\ @@ -64,10 +65,6 @@ mediatek_setup_macs() wan_mac=$lan_mac label_mac=$lan_mac ;; - dlink,eagle-pro-ai-m32-a1) - wan_mac=$(get_mac_label) - lan_mac=$(macaddr_add $(get_mac_label) 1) - ;; reyee,ax3200-e5|\ ruijie,rg-ew3200gx-pro) lan_mac=$(macaddr_add $(get_mac_label) 1) diff --git a/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index e9cc592237..7ee9f24071 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -18,10 +18,6 @@ case "$board" in [ "$PHYNBR" = "0" ] && macaddr_add $basemac 1 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $basemac 8 > /sys${DEVPATH}/macaddress ;; - dlink,eagle-pro-ai-m32-a1) - [ "$PHYNBR" = "0" ] && macaddr_add $(cat /sys/class/net/eth0/address) 2 > /sys${DEVPATH}/macaddress - [ "$PHYNBR" = "1" ] && macaddr_add $(cat /sys/class/net/eth0/address) 3 > /sys${DEVPATH}/macaddress - ;; reyee,ax3200-e5|\ ruijie,rg-ew3200gx-pro) [ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress diff --git a/target/linux/mediatek/mt7622/base-files/etc/init.d/bootcount b/target/linux/mediatek/mt7622/base-files/etc/init.d/bootcount index bc4eeb6530..19a321b48b 100755 --- a/target/linux/mediatek/mt7622/base-files/etc/init.d/bootcount +++ b/target/linux/mediatek/mt7622/base-files/etc/init.d/bootcount @@ -4,6 +4,14 @@ START=99 boot() { case $(board_name) in + dlink,eagle-pro-ai-m32-a1|\ + dlink,eagle-pro-ai-r32-a1) + if grep -q boot_part=Kernel1 /proc/cmdline; then + fw_setenv boot_part 1 + else + fw_setenv boot_part 2 + fi + ;; linksys,e8450) mtd erase senv || true ;; diff --git a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh index e256d2b533..3a2d7a4cd6 100755 --- a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh @@ -35,6 +35,7 @@ platform_do_upgrade() { fi ;; dlink,eagle-pro-ai-m32-a1|\ + dlink,eagle-pro-ai-r32-a1|\ elecom,wrc-x3200gst3|\ mediatek,mt7622-rfb1-ubi|\ netgear,wax206|\ @@ -73,7 +74,8 @@ platform_check_image() { buffalo,wsr-3200ax4s) buffalo_check_image "$board" "$magic" "$1" || return 1 ;; - dlink,eagle-pro-ai-m32-a1|\ + dlink,eagle-pro-ai-m32-a1|\ + dlink,eagle-pro-ai-r32-a1|\ elecom,wrc-x3200gst3|\ mediatek,mt7622-rfb1-ubi|\ netgear,wax206|\ From 3f1be8edee29fe79fc33c88cbd9d647a490410e5 Mon Sep 17 00:00:00 2001 From: Lech Perczak Date: Fri, 15 Dec 2023 17:15:47 +0100 Subject: [PATCH 10/20] ramips: mtk_eth_soc: allow multiple resets Use devm_reset_control_array_get_exclusive to register multiple reset lines in FE driver. This is required to reattach ESW reset to FE driver again, based on device tree bindings. While at that, remove unused fe_priv.rst_ppe field, and add error message if getting the reset fails. Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe") Co-developed-by: Maxim Anisimov Signed-off-by: Maxim Anisimov [Split out of the bigger commit, provide commit mesage, refactor error handling] Signed-off-by: Lech Perczak --- .../drivers/net/ethernet/ralink/mtk_eth_soc.c | 14 ++++++++------ .../drivers/net/ethernet/ralink/mtk_eth_soc.h | 3 +-- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c index b79b348938..78b17605d2 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c @@ -143,12 +143,12 @@ void fe_reset(u32 reset_bits) void fe_reset_fe(struct fe_priv *priv) { - if (!priv->rst_fe) + if (!priv->resets) return; - reset_control_assert(priv->rst_fe); + reset_control_assert(priv->resets); usleep_range(60, 120); - reset_control_deassert(priv->rst_fe); + reset_control_deassert(priv->resets); usleep_range(60, 120); } @@ -1595,9 +1595,11 @@ static int fe_probe(struct platform_device *pdev) priv = netdev_priv(netdev); spin_lock_init(&priv->page_lock); - priv->rst_fe = devm_reset_control_get(&pdev->dev, "fe"); - if (IS_ERR(priv->rst_fe)) - priv->rst_fe = NULL; + priv->resets = devm_reset_control_array_get_exclusive(&pdev->dev); + if (IS_ERR(priv->resets)) { + dev_err(&pdev->dev, "Failed to get resets for FE and ESW cores: %pe\n", priv->resets); + priv->resets = NULL; + } if (soc->init_data) soc->init_data(soc, netdev); diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h index 968db366cf..892ffb2126 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h @@ -497,8 +497,7 @@ struct fe_priv { struct work_struct pending_work; DECLARE_BITMAP(pending_flags, FE_FLAG_MAX); - struct reset_control *rst_ppe; - struct reset_control *rst_fe; + struct reset_control *resets; struct mtk_foe_entry *foe_table; dma_addr_t foe_table_phys; struct flow_offload __rcu **foe_flow_table; From 7eb0458c1f7e4f681b16d2721cfc3fcb69774c95 Mon Sep 17 00:00:00 2001 From: Maxim Anisimov Date: Sun, 10 Dec 2023 16:27:32 +0100 Subject: [PATCH 11/20] ramips: mtk_eth_soc: wait longer after FE core reset to settle Enabling the FE core too early causes the system to hang during boot uncondtionally, after the reset is released. Increate it to 1-1.2ms range. Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe") Signed-off-by: Maxim Anisimov [Split previous commit, provide rationale] Signed-off-by: Lech Perczak --- .../ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c index 78b17605d2..dab8a173f7 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c @@ -149,7 +149,7 @@ void fe_reset_fe(struct fe_priv *priv) reset_control_assert(priv->resets); usleep_range(60, 120); reset_control_deassert(priv->resets); - usleep_range(60, 120); + usleep_range(1000, 1200); } static inline void fe_int_disable(u32 mask) From 8d75b1de0ff7b9e9e0138f822a5475bb8ad7fedf Mon Sep 17 00:00:00 2001 From: Maxim Anisimov Date: Fri, 8 Dec 2023 08:34:30 +0300 Subject: [PATCH 12/20] ramips: dts: rt3352: reset FE and ESW cores together Failing to do so will cause the DMA engine to not initialize properly and fail to forward packets between them, and in some cases will cause spurious transmission with size exceeding allowed packet size, causing a kernel panic. Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe") Signed-off-by: Maxim Anisimov [Provide commit description, split into logical changes] Signed-off-by: Lech Perczak --- target/linux/ramips/dts/rt3352.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/ramips/dts/rt3352.dtsi b/target/linux/ramips/dts/rt3352.dtsi index 0ac3227ce0..b4829cb1b1 100644 --- a/target/linux/ramips/dts/rt3352.dtsi +++ b/target/linux/ramips/dts/rt3352.dtsi @@ -319,8 +319,8 @@ clocks = <&sysc 12>; - resets = <&sysc 21>; - reset-names = "fe"; + resets = <&sysc 21>, <&sysc 23>; + reset-names = "fe", "esw"; interrupt-parent = <&cpuintc>; interrupts = <5>; @@ -332,8 +332,8 @@ compatible = "ralink,rt3352-esw", "ralink,rt3050-esw"; reg = <0x10110000 0x8000>; - resets = <&sysc 23>, <&sysc 24>; - reset-names = "esw", "ephy"; + resets = <&sysc 24>; + reset-names = "ephy"; interrupt-parent = <&intc>; interrupts = <17>; From c5a399f372535886582f89f3da624ae7465c8ff4 Mon Sep 17 00:00:00 2001 From: Lech Perczak Date: Tue, 12 Dec 2023 00:22:04 +0100 Subject: [PATCH 13/20] ramips: dts: rt3050: reset FE and ESW cores together Failing to do so will cause the DMA engine to not initialize properly and fail to forward packets between them, and in some cases will cause spurious transmission with size exceeding allowed packet size, causing a kernel panic. This is behaviour of downstream driver as well, however I haven't observed bug reports about this SoC in the wild, so this commit's purpose is to align this chip with all other SoC's - MT7620 were already using this arrangement. Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe") Signed-off-by: Lech Perczak --- target/linux/ramips/dts/rt3050.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/ramips/dts/rt3050.dtsi b/target/linux/ramips/dts/rt3050.dtsi index 4d70773ed1..d23303964f 100644 --- a/target/linux/ramips/dts/rt3050.dtsi +++ b/target/linux/ramips/dts/rt3050.dtsi @@ -301,8 +301,8 @@ clocks = <&sysc 11>; - resets = <&sysc 21>; - reset-names = "fe"; + resets = <&sysc 21>, <&sysc 23>; + reset-names = "fe", "esw"; interrupt-parent = <&cpuintc>; interrupts = <5>; @@ -314,8 +314,8 @@ compatible = "ralink,rt3050-esw"; reg = <0x10110000 0x8000>; - resets = <&sysc 23>, <&sysc 24>; - reset-names = "esw", "ephy"; + resets = <&sysc 24>; + reset-names = "ephy"; interrupt-parent = <&intc>; interrupts = <17>; From fc92fecfc7ddf19bbfd7d1305a29c666f00543af Mon Sep 17 00:00:00 2001 From: Lech Perczak Date: Tue, 12 Dec 2023 00:25:02 +0100 Subject: [PATCH 14/20] ramips: dts: rt5350: reset FE and ESW cores together Failing to do so will cause the DMA engine to not initialize properly and fail to forward packets between them, and in some cases will cause spurious transmission with size exceeding allowed packet size, causing a kernel panic. This is behaviour of downstream driver as well, however I haven't observed bug reports about this SoC in the wild, so this commit's purpose is to align this chip with all other SoC's - MT7620 were already using this arrangement. Fixes: #9284 Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe") Signed-off-by: Lech Perczak --- target/linux/ramips/dts/rt5350.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/ramips/dts/rt5350.dtsi b/target/linux/ramips/dts/rt5350.dtsi index 9bbbc611ed..30f6435842 100644 --- a/target/linux/ramips/dts/rt5350.dtsi +++ b/target/linux/ramips/dts/rt5350.dtsi @@ -340,8 +340,8 @@ clocks = <&sysc 12>; - resets = <&sysc 21>; - reset-names = "fe"; + resets = <&sysc 21>, <&sysc 23>; + reset-names = "fe", "esw"; interrupt-parent = <&cpuintc>; interrupts = <5>; @@ -353,8 +353,8 @@ compatible = "ralink,rt5350-esw", "ralink,rt3050-esw"; reg = <0x10110000 0x8000>; - resets = <&sysc 23>, <&sysc 24>; - reset-names = "esw", "ephy"; + resets = <&sysc 24>; + reset-names = "ephy"; interrupt-parent = <&intc>; interrupts = <17>; From f87b66507e9245e6e02dbc76e2e7b27c9e0bf364 Mon Sep 17 00:00:00 2001 From: Maxim Anisimov Date: Sun, 10 Dec 2023 16:40:39 +0100 Subject: [PATCH 15/20] ramips: dts: mt7628an: reset FE and ESW cores together Failing to do so will cause the DMA engine to not initialize properly and fail to forward packets between them, and in some cases will cause spurious transmission with size exceeding allowed packet size, causing a kernel panic. Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe") Signed-off-by: Maxim Anisimov [Provide commit description, split into logical changes] Signed-off-by: Lech Perczak --- target/linux/ramips/dts/mt7628an.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/ramips/dts/mt7628an.dtsi b/target/linux/ramips/dts/mt7628an.dtsi index ddc3011aab..97f77f6b38 100644 --- a/target/linux/ramips/dts/mt7628an.dtsi +++ b/target/linux/ramips/dts/mt7628an.dtsi @@ -411,8 +411,8 @@ interrupt-parent = <&cpuintc>; interrupts = <5>; - resets = <&sysc 21>; - reset-names = "fe"; + resets = <&sysc 21>, <&sysc 23>; + reset-names = "fe", "esw"; mediatek,switch = <&esw>; }; @@ -421,8 +421,8 @@ compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw"; reg = <0x10110000 0x8000>; - resets = <&sysc 23>, <&sysc 24>; - reset-names = "esw", "ephy"; + resets = <&sysc 24>; + reset-names = "ephy"; interrupt-parent = <&intc>; interrupts = <17>; From f393ffcac163926bf9dbbda47c25cc7809952609 Mon Sep 17 00:00:00 2001 From: Lech Perczak Date: Fri, 15 Dec 2023 17:25:05 +0100 Subject: [PATCH 16/20] raimps: mtk_eth_soc: drop rst_esw from ESW driver The ESW core needs to be reset together with FE core, so after the relevant reset controller lines are moved under FE, drop rst_esw and all related code, which would not execute anyway, because rst_esw would be NULL. While at that, ensure that if reset line for EPHY cannot be claimed, a proper error message is reported. Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe") Co-developed-by: Maxim Anisimov Signed-off-by: Maxim Anisimov [Split out of the bigger commit, provide commit mesage, refactor error handling] Signed-off-by: Lech Perczak --- .../drivers/net/ethernet/ralink/esw_rt3050.c | 24 ++++--------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c index 47471eb197..5a36652a11 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c @@ -237,7 +237,6 @@ struct rt305x_esw { int led_frequency; struct esw_vlan vlans[RT305X_ESW_NUM_VLANS]; struct esw_port ports[RT305X_ESW_NUM_PORTS]; - struct reset_control *rst_esw; struct reset_control *rst_ephy; }; @@ -261,18 +260,6 @@ static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, __raw_writel(t | val, esw->base + reg); } -static void esw_reset(struct rt305x_esw *esw) -{ - if (!esw->rst_esw) - return; - - reset_control_assert(esw->rst_esw); - usleep_range(60, 120); - reset_control_deassert(esw->rst_esw); - /* the esw takes long to reset otherwise the board hang */ - msleep(10); -} - static void esw_reset_ephy(struct rt305x_esw *esw) { if (!esw->rst_ephy) @@ -466,8 +453,6 @@ static void esw_hw_init(struct rt305x_esw *esw) u8 port_disable = 0; u8 port_map = RT305X_ESW_PMAP_LLLLLL; - esw_reset(esw); - /* vodoo from original driver */ esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0); esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2); @@ -1441,12 +1426,11 @@ static int esw_probe(struct platform_device *pdev) if (reg_init) esw->reg_led_source = be32_to_cpu(*reg_init); - esw->rst_esw = devm_reset_control_get(&pdev->dev, "esw"); - if (IS_ERR(esw->rst_esw)) - esw->rst_esw = NULL; - esw->rst_ephy = devm_reset_control_get(&pdev->dev, "ephy"); - if (IS_ERR(esw->rst_ephy)) + esw->rst_ephy = devm_reset_control_get_exclusive(&pdev->dev, "ephy"); + if (IS_ERR(esw->rst_ephy)) { + dev_err(esw->dev, "failed to get EPHY reset: %pe\n", esw->rst_ephy); esw->rst_ephy = NULL; + } spin_lock_init(&esw->reg_rw_lock); platform_set_drvdata(pdev, esw); From 4c1e9bd8581e01793b26f3bc964975311450ece0 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Tue, 5 Dec 2023 18:36:42 -0500 Subject: [PATCH 17/20] ramips: lzma-loader: use virtual memory segments for uart base address The native bus address for UART was entered for rt305x UART_BASE, but the bootloaders have memory space remapped with the same virtual memory map the kernel uses for program addressing at boot time. In UBoot, the remapped address is often defined as TEXT_BASE. In the kernel, for rt305x this remapped address is RT305X_SYSC_BASE. (arch/mips/include/asm/mach-ralink/rt305x.h) Because the ralink I/O busses begin at a low address of 0x10000000, they are remapped using KSEG0 or KSEG1, which for all 32-bit MIPS SOCs (arch/mips/include/asm/addrspace.h) are offsets of 0x80000000 and 0xa0000000 respectively. This is consistent with the other UART_BASE macros here and with MIPS memory map documentation. Before the recent rework of the lzma-loader for ramips, the original board-$(PLATFORM).c files also did not use KSEG1ADDR for UART_BASE despite being defined, which made this mistake easier to occur. Fix this by defining KSEG1ADDR again and actually use it. Copy and paste from the kernel's macros for consistency. Link: https://training.mips.com/basic_mips/PDF/Memory_Map.pdf Fixes: c31319b66 ("ramips: lzma-loader: Refactor loader") Reported-by: Lech Perczak Signed-off-by: Michael Pratt --- .../ramips/image/lzma-loader/src/board.c | 20 ++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/target/linux/ramips/image/lzma-loader/src/board.c b/target/linux/ramips/image/lzma-loader/src/board.c index ae9da38073..050ef695f9 100644 --- a/target/linux/ramips/image/lzma-loader/src/board.c +++ b/target/linux/ramips/image/lzma-loader/src/board.c @@ -11,19 +11,33 @@ */ #include +#include + +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 + +#define _ATYPE_ __PTRDIFF_TYPE__ +#define _ATYPE32_ int + +#define _ACAST32_ (_ATYPE_)(_ATYPE32_) + +#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) + +#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) +#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) #if defined(SOC_MT7620) || defined(SOC_RT3883) -#define UART_BASE 0xb0000c00 +#define UART_BASE KSEG1ADDR(0x10000c00) #define UART_THR (UART_BASE + 0x04) #define UART_LSR (UART_BASE + 0x1c) #define UART_LSR_THRE_MASK 0x40 #elif defined(SOC_MT7621) -#define UART_BASE 0xbe000c00 +#define UART_BASE KSEG1ADDR(0x1e000c00) #define UART_THR (UART_BASE + 0x00) #define UART_LSR (UART_BASE + 0x14) #define UART_LSR_THRE_MASK 0x20 #elif defined(SOC_RT305X) -#define UART_BASE 0x10000500 +#define UART_BASE KSEG1ADDR(0x10000500) #define UART_THR (UART_BASE + 0x04) #define UART_LSR (UART_BASE + 0x1c) #define UART_LSR_THRE_MASK 0x20 From 2e47913c644c59aa25fbac2bc6c4297956406b82 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Wed, 6 Dec 2023 14:12:03 -0500 Subject: [PATCH 18/20] ramips: lzma-loader: use proper register names Before this was reworked, in the file for mt7621 subtarget (target/linux/ramips/image/lzma-loader/src/board-mt7621.c) the "Transmitter shift register empty" bit TEMT was used instead of the "Transmitter holding register empty" bit THRE, but after the rework, this value was labeled as the THRE bit instead. Functionally there is no difference, but this is confusing to read, as it suggests that the subtargets have different bits for the same register in UART when in reality they are exactly the same. One can use either bit, or both, at user's descretion in order to determine whether the UART TX buffer is ready. The generic kernel early-printk uses both, (arch/mips/kernel/early_printk_8250.c) while the ralink-specific early-printk uses only THRE, (arch/mips/ralink/early_printk.c). Define both bits and rewrite macros for readability, keep the same values, as changing which to use should be tested first. Ref: c31319b66 ("ramips: lzma-loader: Refactor loader") Signed-off-by: Michael Pratt --- target/linux/ramips/image/lzma-loader/src/board.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/linux/ramips/image/lzma-loader/src/board.c b/target/linux/ramips/image/lzma-loader/src/board.c index 050ef695f9..9f87cddec7 100644 --- a/target/linux/ramips/image/lzma-loader/src/board.c +++ b/target/linux/ramips/image/lzma-loader/src/board.c @@ -26,21 +26,24 @@ #define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) #define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) +#define UART_LSR_THRE 0x20 +#define UART_LSR_TEMT 0x40 + #if defined(SOC_MT7620) || defined(SOC_RT3883) #define UART_BASE KSEG1ADDR(0x10000c00) #define UART_THR (UART_BASE + 0x04) #define UART_LSR (UART_BASE + 0x1c) -#define UART_LSR_THRE_MASK 0x40 +#define UART_LSR_MASK UART_LSR_TEMT #elif defined(SOC_MT7621) #define UART_BASE KSEG1ADDR(0x1e000c00) #define UART_THR (UART_BASE + 0x00) #define UART_LSR (UART_BASE + 0x14) -#define UART_LSR_THRE_MASK 0x20 +#define UART_LSR_MASK UART_LSR_THRE #elif defined(SOC_RT305X) #define UART_BASE KSEG1ADDR(0x10000500) #define UART_THR (UART_BASE + 0x04) #define UART_LSR (UART_BASE + 0x1c) -#define UART_LSR_THRE_MASK 0x20 +#define UART_LSR_MASK UART_LSR_THRE #else #error "Unsupported SOC..." #endif @@ -56,7 +59,7 @@ void board_init(void) void board_putc(int ch) { - while ((READREG(UART_LSR) & UART_LSR_THRE_MASK) == 0); + while ((READREG(UART_LSR) & UART_LSR_MASK) == 0); WRITEREG(UART_THR, ch); - while ((READREG(UART_LSR) & UART_LSR_THRE_MASK) == 0); + while ((READREG(UART_LSR) & UART_LSR_MASK) == 0); } From bc00c78b4338779ca1b7cd08411f76218d1f3205 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Wed, 6 Dec 2023 14:29:26 -0500 Subject: [PATCH 19/20] ramips: lzma-loader: use default uart for rt305x The rt305x series SOC have two UART devices, and the one at bus address 0x500 is disabled by default. Some boards do not even have a pinout for the first one, so use the same one that the kernel uses at 0xc00 instead. This allows the lzma-loader printing to be visible alongside the kernel log in the same console. Tested-by: Lech Perczak # zte,mf283plus Signed-off-by: Michael Pratt --- target/linux/ramips/image/lzma-loader/src/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ramips/image/lzma-loader/src/board.c b/target/linux/ramips/image/lzma-loader/src/board.c index 9f87cddec7..de02f58b9f 100644 --- a/target/linux/ramips/image/lzma-loader/src/board.c +++ b/target/linux/ramips/image/lzma-loader/src/board.c @@ -40,7 +40,7 @@ #define UART_LSR (UART_BASE + 0x14) #define UART_LSR_MASK UART_LSR_THRE #elif defined(SOC_RT305X) -#define UART_BASE KSEG1ADDR(0x10000500) +#define UART_BASE KSEG1ADDR(0x10000c00) #define UART_THR (UART_BASE + 0x04) #define UART_LSR (UART_BASE + 0x1c) #define UART_LSR_MASK UART_LSR_THRE From 443e3bd1c6e61aa39f4fc176b22ad2d75f33bcb4 Mon Sep 17 00:00:00 2001 From: David Bentham Date: Mon, 25 Dec 2023 11:51:16 +0000 Subject: [PATCH 20/20] ramips: unielec-u7621-01: Increase SPI frequency to 50MHz Flash: 16MB SPI NOR flash (Macronix MX25L12805D) Based on the manufactured datasheet this chip is capable of 50MHz. We dont enable fast-read as mt7621 are only capable of 44mhz in a read state. Tested on this unit without any issues. Signed-off-by: David Bentham --- target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts b/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts index c933e443c1..d6189f3d58 100644 --- a/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts +++ b/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts @@ -13,7 +13,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <14000000>; + spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions";