rockchip: add Ariaboard Photonicat support
Hardware -------- RockChip RK3568 ARM64 (4 cores) 2GB or 4GB LPDDR4 RAM 2x 1000 Base-T QCA1023 Wi-Fi 5 / Bluetooth 16GB or 64GB eMMC on-board 2x M.2 Slot (B+E Key) Micro-SD Slot HDMI Port USB 3.0 Port 7000 mAh Battery Type-C Power Note ---- The sdio card QCA1023 is not supported for now due to broken ath10k-sdio driver. Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
parent
abffb3e074
commit
938cf080db
@ -7,6 +7,7 @@ rockchip_setup_interfaces()
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local board="$1"
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case "$board" in
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ariaboard,photonicat|\
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ezpro,mrkaio-m68s|\
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firefly,rk3568-roc-pc|\
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friendlyarm,nanopi-r2c|\
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@ -29,6 +29,7 @@ set_interface_core() {
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}
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case "$(board_name)" in
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ariaboard,photonicat|\
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ezpro,mrkaio-m68s|\
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firefly,rk3568-roc-pc|\
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friendlyarm,nanopi-r5c|\
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@ -0,0 +1,600 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/soc/rockchip,vop2.h>
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#include "rk3568.dtsi"
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/ {
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model = "Ariaboard Photonicat";
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compatible = "ariaboard,photonicat", "rockchip,rk3568";
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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mmc0 = &sdhci;
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mmc1 = &sdmmc0;
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mmc2 = &sdmmc1;
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};
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chosen: chosen {
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stdout-path = "serial2:1500000n8";
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};
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gpio-poweroff {
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compatible = "gpio-poweroff";
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gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
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timeout-ms = <3000>;
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};
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hdmi-con {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con_in: endpoint {
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remote-endpoint = <&hdmi_out_con>;
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};
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};
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};
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modem-rfkill {
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compatible = "rfkill-gpio";
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label = "modem-rfkill";
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radio-type = "wwan";
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reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
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shutdown-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
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};
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sdio_pwrseq: sdio-pwrseq {
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compatible = "mmc-pwrseq-simple";
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clocks = <&pmucru CLK_RTC_32K>;
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clock-names = "ext_clock";
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pinctrl-names = "default";
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pinctrl-0 = <&wifi_enable_h &clk32k_out1>;
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reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
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};
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vcc_sysin: vcc-sysin-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_sysin";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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vcc_syson: vcc-syson-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_syson";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc_sysin>;
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};
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vcc_1v8: vcc-1v8-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_1v8";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc3v3_sys>;
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};
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vcc_3v3: vcc-3v3-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_3v3";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc3v3_sys>;
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};
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vcc3v3_ngff: vcc3v3-ngff-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
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regulator-name = "vcc3v3_ngff";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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/* pi6c pcie clock generator */
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vcc3v3_pi6c: vcc3v3-pi6c-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_enable_h>;
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regulator-name = "vcc3v3_pi6c";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc_syson>;
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};
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/* actually fed by vcc_syson, dependent on pi6c clock generator */
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vcc3v3_pcie: vcc3v3-pcie-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_pcie";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc3v3_pi6c>;
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};
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vcc3v3_sd: vcc3v3-sd-regulator {
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compatible = "regulator-fixed";
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gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc_sd_h>;
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regulator-boot-on;
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regulator-name = "vcc3v3_sd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc_3v3>;
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};
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vcc3v3_sys: vcc3v3-sys-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc_syson>;
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};
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vcc5v0_boost: vcc5v0-boost-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc5v0_boost_en>;
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regulator-name = "vcc5v0_boost";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc5v0_usb_otg_en>;
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regulator-name = "vcc5v0_usb_otg";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc_sysin>;
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};
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vcca_1v8: vcca-1v8-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcca_1v8";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc3v3_sys>;
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};
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vdda_0v9: vdda-0v9-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vdda_0v9";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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vin-supply = <&vcc3v3_sys>;
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};
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vdd_gpu: vdd-gpu-regulator {
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compatible = "pwm-regulator";
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pwms = <&pwm2 0 5000 1>;
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regulator-name = "vdd_gpu";
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regulator-always-on;
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regulator-boot-on;
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regulator-init-microvolt = <900000>;
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1350000>;
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regulator-ramp-delay = <6001>;
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regulator-settling-time-up-us = <250>;
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pwm-supply = <&vcc_syson>;
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};
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vdd_logic: vdd-logic-regulator {
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compatible = "pwm-regulator";
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pwms = <&pwm1 0 5000 1>;
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regulator-name = "vdd_logic";
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regulator-always-on;
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regulator-boot-on;
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regulator-init-microvolt = <900000>;
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1350000>;
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regulator-ramp-delay = <6001>;
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regulator-settling-time-up-us = <250>;
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pwm-supply = <&vcc_syson>;
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};
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};
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&combphy0 {
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status = "okay";
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};
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&combphy1 {
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status = "okay";
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};
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&combphy2 {
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status = "okay";
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};
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&cpu0 {
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cpu-supply = <&vdd_cpu>;
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};
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&cpu1 {
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cpu-supply = <&vdd_cpu>;
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};
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&cpu2 {
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cpu-supply = <&vdd_cpu>;
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};
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&cpu3 {
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cpu-supply = <&vdd_cpu>;
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};
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&gmac0 {
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assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
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assigned-clock-parents = <&gmac0_xpcsclk>;
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power-domains = <&power RK3568_PD_PIPE>;
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phys = <&combphy2 PHY_TYPE_SGMII>;
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phy-handle = <&sgmii_phy>;
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phy-mode = "sgmii";
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phy-supply = <&vcc_3v3>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac0_miim>;
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rockchip,xpcs = <&xpcs>;
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snps,reset-gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 15000 50000>;
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tx_delay = <0xff>;
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rx_delay = <0xff>;
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status = "okay";
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};
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&gmac1 {
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assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
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assigned-clock-rates = <0>, <125000000>;
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clock_in_out = "output";
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phy-handle = <&rgmii_phy>;
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phy-mode = "rgmii";
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phy-supply = <&vcc_3v3>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1m1_miim
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&gmac1m1_tx_bus2
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&gmac1m1_rx_bus2
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&gmac1m1_rgmii_clk
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&gmac1m1_rgmii_bus>;
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snps,reset-gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 15000 50000>;
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tx_delay = <0x30>;
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rx_delay = <0x10>;
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status = "okay";
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};
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&gpu {
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mali-supply = <&vdd_gpu>;
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status = "okay";
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};
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&hdmi {
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avdd-0v9-supply = <&vdda_0v9>;
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avdd-1v8-supply = <&vcca_1v8>;
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status = "okay";
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};
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&hdmi_in {
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hdmi_in_vp0: endpoint {
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remote-endpoint = <&vp0_out_hdmi>;
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};
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};
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&hdmi_out {
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hdmi_out_con: endpoint {
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remote-endpoint = <&hdmi_con_in>;
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};
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};
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&hdmi_sound {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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vdd_cpu: regulator@1c {
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compatible = "tcs,tcs4525";
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reg = <0x1c>;
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fcs,suspend-voltage-selector = <1>;
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regulator-name = "vdd_cpu";
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regulator-always-on;
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regulator-boot-on;
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regulator-init-microvolt = <900000>;
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regulator-min-microvolt = <712500>;
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regulator-max-microvolt = <1390000>;
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regulator-ramp-delay = <2300>;
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vin-supply = <&vcc_syson>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2m1_xfer>;
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status = "okay";
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};
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&i2s0_8ch {
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status = "okay";
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};
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&mdio0 {
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sgmii_phy: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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motorcomm,led-data = <0xe004 0x0000 0x2600 0x0070 0x000a>;
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};
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};
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&mdio1 {
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rgmii_phy: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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motorcomm,led-data = <0xe004 0x0000 0x2600 0x0070 0x000a>;
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};
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};
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&pcie30phy {
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phy-supply = <&vcc3v3_pi6c>;
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status = "okay";
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};
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&pcie3x2 {
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reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie>;
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status = "okay";
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};
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&pinctrl {
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bt {
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bt_enable_h: bt-enable-h {
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rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pcie {
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pcie_enable_h: pcie-enable-h {
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rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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sdio-pwrseq {
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wifi_enable_h: wifi-enable-h {
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rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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usb {
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vcc5v0_boost_en: vcc5v0-boost-en {
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rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
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rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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vcc-sd {
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vcc_sd_h: vcc-sd-h {
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rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&pmu_io_domains {
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pmuio1-supply = <&vcc_3v3>;
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pmuio2-supply = <&vcc_3v3>;
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vccio1-supply = <&vcc_3v3>;
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vccio3-supply = <&vcc_3v3>;
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vccio4-supply = <&vcc_1v8>;
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vccio5-supply = <&vcc_3v3>;
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vccio6-supply = <&vcc_3v3>;
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vccio7-supply = <&vcc_3v3>;
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status = "okay";
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};
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&pwm1 {
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status = "okay";
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};
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&pwm2 {
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status = "okay";
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};
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&rng {
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status = "okay";
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};
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&saradc {
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vref-supply = <&vcca_1v8>;
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status = "okay";
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};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
max-frequency = <50000000>;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
|
||||
sd-uhs-sdr20;
|
||||
vmmc-supply = <&vcc3v3_sys>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
|
||||
sdio-wifi@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host-wake";
|
||||
};
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
|
||||
status = "okay";
|
||||
uart-has-rtscts;
|
||||
|
||||
bluetooth {
|
||||
compatible = "qcom,qca9377-bt";
|
||||
enable-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&pmucru CLK_RTC_32K>;
|
||||
clock-names = "lpo";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bt_enable_h>;
|
||||
vddio-supply = <&vcc_1v8>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
|
||||
&xin32k {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&clk32k_out1>;
|
||||
};
|
||||
|
||||
&xpcs {
|
||||
status = "okay";
|
||||
};
|
||||
@ -10,6 +10,16 @@ define Device/IfnameMigration
|
||||
DEVICE_COMPAT_MESSAGE := Network interface names have been changed
|
||||
endef
|
||||
|
||||
define Device/ariaboard_photonicat
|
||||
DEVICE_VENDOR := Ariaboard
|
||||
DEVICE_MODEL := Photonicat
|
||||
SOC := rk3568
|
||||
BOOT_FLOW := pine64-img
|
||||
DEVICE_PACKAGES := pcat-manager kmod-usb-net-cdc-mbim \
|
||||
kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi
|
||||
endef
|
||||
TARGET_DEVICES += ariaboard_photonicat
|
||||
|
||||
define Device/ezpro_mrkaio-m68s
|
||||
DEVICE_VENDOR := EZPRO
|
||||
DEVICE_MODEL := Mrkaio M68S
|
||||
|
||||
@ -0,0 +1,32 @@
|
||||
From 64b69474edf3b885c19a89bb165f978ba1b4be00 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Tue, 10 Jan 2023 22:55:50 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x
|
||||
|
||||
clk_rtc_32k and its child clock clk_hdmi_cec detauls to a rate of 24 MHz
|
||||
and not to 32 kHz on RK356x.
|
||||
|
||||
Fix this by assigning clk_rtc_32k a rate of 32768, also assign the parent
|
||||
to clk_rtc32k_frac.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://lore.kernel.org/r/20230110225547.1563119-2-jonas@kwiboo.se
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++--
|
||||
1 file changed, 3 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -422,8 +422,9 @@
|
||||
clock-names = "xin24m";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
- assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
|
||||
- assigned-clock-rates = <1200000000>, <200000000>;
|
||||
+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
|
||||
+ assigned-clock-rates = <32768>, <1200000000>, <200000000>;
|
||||
+ assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
|
||||
rockchip,grf = <&grf>;
|
||||
};
|
||||
|
||||
@ -0,0 +1,34 @@
|
||||
From b4aeb93e697e4dbe2d336d01290e92e98acfd83c Mon Sep 17 00:00:00 2001
|
||||
From: jensen <jensenhuang@friendlyarm.com>
|
||||
Date: Sat, 15 Oct 2022 18:47:24 +0800
|
||||
Subject: [PATCH] rfkill: gpio: add of_match_table support
|
||||
|
||||
Signed-off-by: jensen <jensenhuang@friendlyarm.com>
|
||||
---
|
||||
net/rfkill/rfkill-gpio.c | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/net/rfkill/rfkill-gpio.c
|
||||
+++ b/net/rfkill/rfkill-gpio.c
|
||||
@@ -164,6 +164,13 @@ static const struct acpi_device_id rfkil
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, rfkill_acpi_match);
|
||||
#endif
|
||||
+#ifdef CONFIG_OF
|
||||
+static struct of_device_id rfkill_gpio_of_match[] = {
|
||||
+ { .compatible = "rfkill-gpio" },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rfkill_gpio_of_match);
|
||||
+#endif
|
||||
|
||||
static struct platform_driver rfkill_gpio_driver = {
|
||||
.probe = rfkill_gpio_probe,
|
||||
@@ -171,6 +178,7 @@ static struct platform_driver rfkill_gpi
|
||||
.driver = {
|
||||
.name = "rfkill_gpio",
|
||||
.acpi_match_table = ACPI_PTR(rfkill_acpi_match),
|
||||
+ .of_match_table = of_match_ptr(rfkill_gpio_of_match),
|
||||
},
|
||||
};
|
||||
|
||||
@ -66,7 +66,7 @@
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@fd800000 {
|
||||
@@ -976,7 +983,7 @@
|
||||
@@ -977,7 +984,7 @@
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <2>;
|
||||
|
||||
@ -0,0 +1,320 @@
|
||||
From ca89ea7e0760c096c6fd807d321ecb8416f8cd9d Mon Sep 17 00:00:00 2001
|
||||
From: David Wu <david.wu@rock-chips.com>
|
||||
Date: Thu, 31 Dec 2020 18:32:03 +0800
|
||||
Subject: [PATCH] ethernet: stmicro: stmmac: Add SGMII/QSGMII support for
|
||||
RK3568
|
||||
|
||||
After the completion of Clause 37 auto-negotiation, xpcs automatically
|
||||
switches to the negotiated speed for 10/100/1000M.
|
||||
|
||||
Change-Id: Iab9dd6ee61a35bf89fd3a0721f5d398de501a7ec
|
||||
Signed-off-by: David Wu <david.wu@rock-chips.com>
|
||||
---
|
||||
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 228 +++++++++++++++++-
|
||||
1 file changed, 217 insertions(+), 11 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
|
||||
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
|
||||
@@ -11,6 +11,7 @@
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/phy.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
#include <linux/of_net.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/module.h>
|
||||
@@ -30,6 +31,8 @@ struct rk_gmac_ops {
|
||||
void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
|
||||
int tx_delay, int rx_delay);
|
||||
void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
|
||||
+ void (*set_to_sgmii)(struct rk_priv_data *bsp_priv);
|
||||
+ void (*set_to_qsgmii)(struct rk_priv_data *bsp_priv);
|
||||
void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
|
||||
void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
|
||||
void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
|
||||
@@ -40,7 +43,7 @@ struct rk_gmac_ops {
|
||||
};
|
||||
|
||||
static const char * const rk_clocks[] = {
|
||||
- "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed",
|
||||
+ "aclk_mac", "pclk_mac", "pclk_xpcs", "mac_clk_tx", "clk_mac_speed",
|
||||
};
|
||||
|
||||
static const char * const rk_rmii_clocks[] = {
|
||||
@@ -50,6 +53,7 @@ static const char * const rk_rmii_clocks
|
||||
enum rk_clocks_index {
|
||||
RK_ACLK_MAC = 0,
|
||||
RK_PCLK_MAC,
|
||||
+ RK_PCLK_XPCS,
|
||||
RK_MAC_CLK_TX,
|
||||
RK_CLK_MAC_SPEED,
|
||||
RK_MAC_CLK_RX,
|
||||
@@ -81,6 +85,7 @@ struct rk_priv_data {
|
||||
|
||||
struct regmap *grf;
|
||||
struct regmap *php_grf;
|
||||
+ struct regmap *xpcs;
|
||||
};
|
||||
|
||||
#define HIWORD_UPDATE(val, mask, shift) \
|
||||
@@ -93,6 +98,128 @@ struct rk_priv_data {
|
||||
(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
|
||||
((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
|
||||
|
||||
+/* XPCS */
|
||||
+#define XPCS_APB_INCREMENT (0x4)
|
||||
+#define XPCS_APB_MASK GENMASK_ULL(20, 0)
|
||||
+
|
||||
+#define SR_MII_BASE (0x1F0000)
|
||||
+#define SR_MII1_BASE (0x1A0000)
|
||||
+
|
||||
+#define VR_MII_DIG_CTRL1 (0x8000)
|
||||
+#define VR_MII_AN_CTRL (0x8001)
|
||||
+#define VR_MII_AN_INTR_STS (0x8002)
|
||||
+#define VR_MII_LINK_TIMER_CTRL (0x800A)
|
||||
+
|
||||
+#define SR_MII_CTRL_AN_ENABLE \
|
||||
+ (BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000)
|
||||
+#define MII_MAC_AUTO_SW (0x0200)
|
||||
+#define PCS_MODE_OFFSET (0x1)
|
||||
+#define MII_AN_INTR_EN (0x1)
|
||||
+#define PCS_SGMII_MODE (0x2 << PCS_MODE_OFFSET)
|
||||
+#define PCS_QSGMII_MODE (0X3 << PCS_MODE_OFFSET)
|
||||
+#define VR_MII_CTRL_SGMII_AN_EN (PCS_SGMII_MODE | MII_AN_INTR_EN)
|
||||
+#define VR_MII_CTRL_QSGMII_AN_EN (PCS_QSGMII_MODE | MII_AN_INTR_EN)
|
||||
+
|
||||
+#define SR_MII_OFFSET(_x) ({ \
|
||||
+ typeof(_x) (x) = (_x); \
|
||||
+ (((x) == 0) ? SR_MII_BASE : (SR_MII1_BASE + ((x) - 1) * 0x10000)); \
|
||||
+}) \
|
||||
+
|
||||
+static int xpcs_read(void *priv, int reg)
|
||||
+{
|
||||
+ struct rk_priv_data *bsp_priv = (struct rk_priv_data *)priv;
|
||||
+ int ret, val;
|
||||
+
|
||||
+ ret = regmap_read(bsp_priv->xpcs,
|
||||
+ (u32)(reg * XPCS_APB_INCREMENT) & XPCS_APB_MASK,
|
||||
+ &val);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ return val;
|
||||
+}
|
||||
+
|
||||
+static int xpcs_write(void *priv, int reg, u16 value)
|
||||
+{
|
||||
+ struct rk_priv_data *bsp_priv = (struct rk_priv_data *)priv;
|
||||
+
|
||||
+ return regmap_write(bsp_priv->xpcs,
|
||||
+ (reg * XPCS_APB_INCREMENT) & XPCS_APB_MASK, value);
|
||||
+}
|
||||
+
|
||||
+static int xpcs_poll_reset(struct rk_priv_data *bsp_priv, int dev)
|
||||
+{
|
||||
+ /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
|
||||
+ unsigned int retries = 12;
|
||||
+ int ret;
|
||||
+
|
||||
+ do {
|
||||
+ msleep(50);
|
||||
+ ret = xpcs_read(bsp_priv, SR_MII_OFFSET(dev) + MDIO_CTRL1);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+ } while (ret & MDIO_CTRL1_RESET && --retries);
|
||||
+
|
||||
+ return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0;
|
||||
+}
|
||||
+
|
||||
+static int xpcs_soft_reset(struct rk_priv_data *bsp_priv, int dev)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = xpcs_write(bsp_priv, SR_MII_OFFSET(dev) + MDIO_CTRL1,
|
||||
+ MDIO_CTRL1_RESET);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ return xpcs_poll_reset(bsp_priv, dev);
|
||||
+}
|
||||
+
|
||||
+static int xpcs_setup(struct rk_priv_data *bsp_priv, int mode)
|
||||
+{
|
||||
+ int ret, i, idx = bsp_priv->id;
|
||||
+ u32 val;
|
||||
+
|
||||
+ if (mode == PHY_INTERFACE_MODE_QSGMII && idx > 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ ret = xpcs_soft_reset(bsp_priv, idx);
|
||||
+ if (ret) {
|
||||
+ dev_err(&bsp_priv->pdev->dev, "xpcs_soft_reset fail %d\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_INTR_STS, 0x0);
|
||||
+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_LINK_TIMER_CTRL, 0x1);
|
||||
+
|
||||
+ if (mode == PHY_INTERFACE_MODE_SGMII)
|
||||
+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_CTRL,
|
||||
+ VR_MII_CTRL_SGMII_AN_EN);
|
||||
+ else
|
||||
+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_CTRL,
|
||||
+ VR_MII_CTRL_QSGMII_AN_EN);
|
||||
+
|
||||
+ if (mode == PHY_INTERFACE_MODE_QSGMII) {
|
||||
+ for (i = 0; i < 4; i++) {
|
||||
+ val = xpcs_read(bsp_priv,
|
||||
+ SR_MII_OFFSET(i) + VR_MII_DIG_CTRL1);
|
||||
+ xpcs_write(bsp_priv,
|
||||
+ SR_MII_OFFSET(i) + VR_MII_DIG_CTRL1,
|
||||
+ val | MII_MAC_AUTO_SW);
|
||||
+ xpcs_write(bsp_priv, SR_MII_OFFSET(i) + MII_BMCR,
|
||||
+ SR_MII_CTRL_AN_ENABLE);
|
||||
+ }
|
||||
+ } else {
|
||||
+ val = xpcs_read(bsp_priv, SR_MII_OFFSET(idx) + VR_MII_DIG_CTRL1);
|
||||
+ xpcs_write(bsp_priv, SR_MII_OFFSET(idx) + VR_MII_DIG_CTRL1,
|
||||
+ val | MII_MAC_AUTO_SW);
|
||||
+ xpcs_write(bsp_priv, SR_MII_OFFSET(idx) + MII_BMCR,
|
||||
+ SR_MII_CTRL_AN_ENABLE);
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
#define PX30_GRF_GMAC_CON1 0x0904
|
||||
|
||||
/* PX30_GRF_GMAC_CON1 */
|
||||
@@ -1021,6 +1148,7 @@ static const struct rk_gmac_ops rk3399_o
|
||||
#define RK3568_GRF_GMAC1_CON1 0x038c
|
||||
|
||||
/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
|
||||
+#define RK3568_GMAC_GMII_MODE GRF_BIT(7)
|
||||
#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
|
||||
(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
|
||||
#define RK3568_GMAC_PHY_INTF_SEL_RMII \
|
||||
@@ -1036,6 +1164,46 @@ static const struct rk_gmac_ops rk3399_o
|
||||
#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
|
||||
#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
|
||||
|
||||
+#define RK3568_PIPE_GRF_XPCS_CON0 0X0040
|
||||
+
|
||||
+#define RK3568_PIPE_GRF_XPCS_QGMII_MAC_SEL GRF_BIT(0)
|
||||
+#define RK3568_PIPE_GRF_XPCS_SGMII_MAC_SEL GRF_BIT(1)
|
||||
+#define RK3568_PIPE_GRF_XPCS_PHY_READY GRF_BIT(2)
|
||||
+
|
||||
+static void rk3568_set_to_sgmii(struct rk_priv_data *bsp_priv)
|
||||
+{
|
||||
+ struct device *dev = &bsp_priv->pdev->dev;
|
||||
+ u32 con1;
|
||||
+
|
||||
+ if (IS_ERR(bsp_priv->grf)) {
|
||||
+ dev_err(dev, "Missing rockchip,grf property\n");
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
|
||||
+ RK3568_GRF_GMAC0_CON1;
|
||||
+ regmap_write(bsp_priv->grf, con1, RK3568_GMAC_GMII_MODE);
|
||||
+
|
||||
+ xpcs_setup(bsp_priv, PHY_INTERFACE_MODE_SGMII);
|
||||
+}
|
||||
+
|
||||
+static void rk3568_set_to_qsgmii(struct rk_priv_data *bsp_priv)
|
||||
+{
|
||||
+ struct device *dev = &bsp_priv->pdev->dev;
|
||||
+ u32 con1;
|
||||
+
|
||||
+ if (IS_ERR(bsp_priv->grf)) {
|
||||
+ dev_err(dev, "Missing rockchip,grf property\n");
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
|
||||
+ RK3568_GRF_GMAC0_CON1;
|
||||
+ regmap_write(bsp_priv->grf, con1, RK3568_GMAC_GMII_MODE);
|
||||
+
|
||||
+ xpcs_setup(bsp_priv, PHY_INTERFACE_MODE_QSGMII);
|
||||
+}
|
||||
+
|
||||
static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
|
||||
int tx_delay, int rx_delay)
|
||||
{
|
||||
@@ -1108,6 +1276,8 @@ static void rk3568_set_gmac_speed(struct
|
||||
static const struct rk_gmac_ops rk3568_ops = {
|
||||
.set_to_rgmii = rk3568_set_to_rgmii,
|
||||
.set_to_rmii = rk3568_set_to_rmii,
|
||||
+ .set_to_sgmii = rk3568_set_to_sgmii,
|
||||
+ .set_to_qsgmii = rk3568_set_to_qsgmii,
|
||||
.set_rgmii_speed = rk3568_set_gmac_speed,
|
||||
.set_rmii_speed = rk3568_set_gmac_speed,
|
||||
.regs_valid = true,
|
||||
@@ -1580,7 +1750,7 @@ static int gmac_clk_enable(struct rk_pri
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
|
||||
+static int rk_gmac_phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
|
||||
{
|
||||
struct regulator *ldo = bsp_priv->regulator;
|
||||
int ret;
|
||||
@@ -1679,6 +1849,18 @@ static struct rk_priv_data *rk_gmac_setu
|
||||
"rockchip,grf");
|
||||
bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||
"rockchip,php-grf");
|
||||
+ bsp_priv->xpcs = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||
+ "rockchip,xpcs");
|
||||
+ if (!IS_ERR(bsp_priv->xpcs)) {
|
||||
+ struct phy *comphy;
|
||||
+
|
||||
+ comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
|
||||
+ if (IS_ERR(comphy))
|
||||
+ dev_err(dev, "devm_of_phy_get error\n");
|
||||
+ ret = phy_init(comphy);
|
||||
+ if (ret)
|
||||
+ dev_err(dev, "phy_init error\n");
|
||||
+ }
|
||||
|
||||
if (plat->phy_node) {
|
||||
bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
|
||||
@@ -1756,11 +1938,19 @@ static int rk_gmac_powerup(struct rk_pri
|
||||
dev_info(dev, "init for RMII\n");
|
||||
bsp_priv->ops->set_to_rmii(bsp_priv);
|
||||
break;
|
||||
+ case PHY_INTERFACE_MODE_SGMII:
|
||||
+ dev_info(dev, "init for SGMII\n");
|
||||
+ bsp_priv->ops->set_to_sgmii(bsp_priv);
|
||||
+ break;
|
||||
+ case PHY_INTERFACE_MODE_QSGMII:
|
||||
+ dev_info(dev, "init for QSGMII\n");
|
||||
+ bsp_priv->ops->set_to_qsgmii(bsp_priv);
|
||||
+ break;
|
||||
default:
|
||||
dev_err(dev, "NO interface defined!\n");
|
||||
}
|
||||
|
||||
- ret = phy_power_on(bsp_priv, true);
|
||||
+ ret = rk_gmac_phy_power_on(bsp_priv, true);
|
||||
if (ret) {
|
||||
gmac_clk_enable(bsp_priv, false);
|
||||
return ret;
|
||||
@@ -1781,7 +1971,7 @@ static void rk_gmac_powerdown(struct rk_
|
||||
|
||||
pm_runtime_put_sync(&gmac->pdev->dev);
|
||||
|
||||
- phy_power_on(gmac, false);
|
||||
+ rk_gmac_phy_power_on(gmac, false);
|
||||
gmac_clk_enable(gmac, false);
|
||||
}
|
||||
|
||||
@@ -1802,6 +1992,9 @@ static void rk_fix_speed(void *priv, uns
|
||||
if (bsp_priv->ops->set_rmii_speed)
|
||||
bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
|
||||
break;
|
||||
+ case PHY_INTERFACE_MODE_SGMII:
|
||||
+ case PHY_INTERFACE_MODE_QSGMII:
|
||||
+ break;
|
||||
default:
|
||||
dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
|
||||
}
|
||||
@ -0,0 +1,89 @@
|
||||
From 1847729a77175ba5cd64adb419d15dca0f19eb48 Mon Sep 17 00:00:00 2001
|
||||
From: David Wu <david.wu@rock-chips.com>
|
||||
Date: Thu, 31 Dec 2020 18:34:12 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3568: Add xpcs support
|
||||
|
||||
Change-Id: I431393b2346f5f7fd6b0d74f79e643df9a586479
|
||||
Signed-off-by: David Wu <david.wu@rock-chips.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3566.dtsi | 1 +
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 32 +++++++++++++++++++++---
|
||||
2 files changed, 29 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -222,6 +222,13 @@
|
||||
arm,no-tick-in-suspend;
|
||||
};
|
||||
|
||||
+ gmac1_xpcsclk: xpcs-gmac1-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "clk_gmac1_xpcs_mii";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
xin24m: xin24m {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
@@ -376,6 +383,12 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ xpcs: syscon@fda00000 {
|
||||
+ compatible = "rockchip,rk3568-xpcs", "syscon";
|
||||
+ reg = <0x0 0xfda00000 0x0 0x200000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pmugrf: syscon@fdc20000 {
|
||||
compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfdc20000 0x0 0x10000>;
|
||||
@@ -663,11 +676,13 @@
|
||||
clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
|
||||
<&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
|
||||
<&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
|
||||
- <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
|
||||
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
|
||||
+ <&cru PCLK_XPCS>;
|
||||
clock-names = "stmmaceth", "mac_clk_rx",
|
||||
"mac_clk_tx", "clk_mac_refout",
|
||||
"aclk_mac", "pclk_mac",
|
||||
- "clk_mac_speed", "ptp_ref";
|
||||
+ "clk_mac_speed", "ptp_ref",
|
||||
+ "pclk_xpcs";
|
||||
resets = <&cru SRST_A_GMAC1>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -8,6 +8,13 @@
|
||||
/ {
|
||||
compatible = "rockchip,rk3568";
|
||||
|
||||
+ gmac0_xpcsclk: xpcs-gmac0-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "clk_gmac0_xpcs_mii";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
sata0: sata@fc000000 {
|
||||
compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
|
||||
reg = <0 0xfc000000 0 0x1000>;
|
||||
@@ -175,11 +182,13 @@
|
||||
clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
||||
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
||||
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
||||
- <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
|
||||
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
|
||||
+ <&cru PCLK_XPCS>;
|
||||
clock-names = "stmmaceth", "mac_clk_rx",
|
||||
"mac_clk_tx", "clk_mac_refout",
|
||||
"aclk_mac", "pclk_mac",
|
||||
- "clk_mac_speed", "ptp_ref";
|
||||
+ "clk_mac_speed", "ptp_ref",
|
||||
+ "pclk_xpcs";
|
||||
resets = <&cru SRST_A_GMAC0>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
@ -11,7 +11,7 @@ Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -1006,6 +1006,16 @@
|
||||
@@ -1022,6 +1022,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -16,15 +16,17 @@
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s-enterprise.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb
|
||||
@@ -78,6 +80,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bp
|
||||
@@ -78,13 +80,17 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bp
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mrkaio-m68s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
|
||||
@@ -86,5 +89,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ev
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
|
||||
|
||||
Loading…
Reference in New Issue
Block a user