diff --git a/package/libs/wolfssl/patches/300-fix-SSL_get_verify_result-regression.patch b/package/libs/wolfssl/patches/300-fix-SSL_get_verify_result-regression.patch
new file mode 100644
index 0000000000..9651c03af6
--- /dev/null
+++ b/package/libs/wolfssl/patches/300-fix-SSL_get_verify_result-regression.patch
@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Juliusz Sosinowicz <juliusz@wolfssl.com>
+Date: Sat, 12 Feb 2022 00:34:24 +0100
+Subject: [PATCH] Reported in ZD13631
+
+`ssl->peerVerifyRet` wasn't being cleared when retrying with an alternative cert chain
+
+References: https://github.com/wolfSSL/wolfssl/issues/4879
+---
+ src/internal.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/src/internal.c b/src/internal.c
+index 0dded42a76c4..f5814d30607c 100644
+--- a/src/internal.c
++++ b/src/internal.c
+@@ -12372,6 +12372,9 @@ int ProcessPeerCerts(WOLFSSL* ssl, byte* input, word32* inOutIdx,
+                             }
+ 
+                             ret = 0; /* clear errors and continue */
++                    #if defined(OPENSSL_EXTRA) || defined(OPENSSL_EXTRA_X509_SMALL)
++                            ssl->peerVerifyRet = 0;
++                    #endif
+                             args->verifyErr = 0;
+                         }
+ 
diff --git a/package/system/rpcd/Makefile b/package/system/rpcd/Makefile
index 0896a7dada..7f5f527d3e 100644
--- a/package/system/rpcd/Makefile
+++ b/package/system/rpcd/Makefile
@@ -12,10 +12,10 @@ PKG_RELEASE:=1
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/rpcd.git
-PKG_SOURCE_DATE:=2021-03-11
-PKG_SOURCE_VERSION:=ccb75178cf6a726896729c6904bd623636aa0b29
+PKG_SOURCE_DATE:=2022-02-19
+PKG_SOURCE_VERSION:=8d26a1ba3a175016b342cc5e25d340c08ae20eed
 PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
-PKG_MIRROR_HASH:=87b1839275c209f9767057d6da5272cae973a064767fa28f380a37fb65e2e643
+PKG_MIRROR_HASH:=0a692c87811e38022e7446d37fea75cc823d00534d5b91faefc58eba3b6debb1
 
 PKG_LICENSE:=ISC
 PKG_LICENSE_FILES:=
diff --git a/target/linux/ramips/patches-5.4/325-mt7621-fix-memory-detect.patch b/target/linux/ramips/patches-5.4/325-mt7621-fix-memory-detect.patch
new file mode 100644
index 0000000000..f8616c31fc
--- /dev/null
+++ b/target/linux/ramips/patches-5.4/325-mt7621-fix-memory-detect.patch
@@ -0,0 +1,62 @@
+--- a/arch/mips/ralink/mt7621.c
++++ b/arch/mips/ralink/mt7621.c
+@@ -58,7 +58,9 @@
+ #define MT7621_GPIO_MODE_SDHCI_SHIFT	18
+ #define MT7621_GPIO_MODE_SDHCI_GPIO	1
+ 
+-static void *detect_magic __initdata = detect_memory_region;
++#define MT7621_MEM_TEST_PATTERN         0xaa5555aa
++
++static u32 detect_magic __initdata;
+ 
+ static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) };
+ static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };
+@@ -144,26 +146,34 @@ static struct clk *__init mt7621_add_sys
+ 	return clk;
+ }
+ 
++static bool __init mt7621_addr_wraparound_test(phys_addr_t size)
++{
++	void *dm = (void *)KSEG1ADDR(&detect_magic);
++	if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE)
++		return true;
++	__raw_writel(MT7621_MEM_TEST_PATTERN, dm);
++	if (__raw_readl(dm) != __raw_readl(dm + size))
++		return false;
++	__raw_writel(!MT7621_MEM_TEST_PATTERN, dm);
++	return __raw_readl(dm) == __raw_readl(dm + size);
++}
++
+ void __init mt7621_memory_detect(void)
+ {
+-	void *dm = &detect_magic;
+ 	phys_addr_t size;
+ 
+-	for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) {
+-		if (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic)))
+-			break;
++	for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) {
++		if (mt7621_addr_wraparound_test(size)) {
++			add_memory_region(MT7621_LOWMEM_BASE, size, BOOT_MEM_RAM);
++			return;
++		}
+ 	}
+ 
+-	if ((size == 256 * SZ_1M) &&
+-	    (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) &&
+-	    __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) {
+-		add_memory_region(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE,
+-				  BOOT_MEM_RAM);
+-		add_memory_region(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE,
+-				  BOOT_MEM_RAM);
+-	} else {
+-		add_memory_region(MT7621_LOWMEM_BASE, size, BOOT_MEM_RAM);
+-	}
++	/* addr doesn't wrap around at dm + 256M, assume 512M memory. */
++	add_memory_region(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE,
++			  BOOT_MEM_RAM);
++	add_memory_region(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE,
++			  BOOT_MEM_RAM);
+ }
+ 
+ void __init ralink_clk_init(void)