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fix AC58U can't working

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This commit is contained in:
coolsnowwolf 2017-11-29 21:17:19 +08:00
parent f3ede8db8a
commit 98760ec871
35 changed files with 1137 additions and 2102 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
target/linux/ipq806x/patches-4.9/0017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch
View File

@ -45,7 +45,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
};
cpu@3 {
@@ -81,6 +76,29 @@
@@ -81,6 +76,33 @@
reg = <0x3>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
@ -71,6 +71,10 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+ };
+ opp@666000000 {
+ opp-hz = /bits/ 64 <666000000>;
+ clock-latency-ns = <256000>;
+ };
+ opp@717000000 {
+ opp-hz = /bits/ 64 <717000000>;
+ clock-latency-ns = <256000>;
};
};

2
target/linux/ipq806x/patches-4.9/0018-qcom-ipq4019-turn-on-DMA-for-i2c.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -179,6 +179,8 @@
@@ -183,6 +183,8 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;

2
target/linux/ipq806x/patches-4.9/0019-qcom-ipq4019-use-correct-clock-for-i2c-bus-0.patch
View File

@ -17,7 +17,7 @@ Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -175,7 +175,7 @@
@@ -179,7 +179,7 @@
reg = <0x78b7000 0x6000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,

2
target/linux/ipq806x/patches-4.9/0020-qcom-ipq4019-enable-DMA-for-spi.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -167,6 +167,8 @@
@@ -171,6 +171,8 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;

2
target/linux/ipq806x/patches-4.9/0022-dts-ipq4019-support-ARMv7-PMU.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -108,6 +108,12 @@
@@ -112,6 +112,12 @@
IRQ_TYPE_LEVEL_HIGH)>;
};

2
target/linux/ipq806x/patches-4.9/0065-arm-override-compiler-flags.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
# testing for a specific architecture or later rather impossible.
arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
-arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
+arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -mcpu=cortex-a15
+arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -mcpu=cortex-a15 -mtune=cortex-a15
arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
# Only override the compiler option if ARMv6. The ARMv6K extensions are
# always available in ARMv7

4
target/linux/ipq806x/patches-4.9/0069-arm-boot-add-dts-files.patch
View File

@ -5,8 +5,8 @@ Subject: [PATCH 69/69] arm: boot: add dts files
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/arm/boot/dts/Makefile | 8 ++++++++
1 file changed, 8 insertions(+)
arch/arm/boot/dts/Makefile | 9 ++++++++
1 file changed, 9 insertions(+)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile

516
target/linux/ipq806x/patches-4.9/131-pinctrl-qcom-ipq4019-add-remaining-pin-definitions.patch Normal file
View File

@ -0,0 +1,516 @@
From 941e3869bdeddb2bebcc52ebfd57efe014887bc6 Mon Sep 17 00:00:00 2001
Message-Id: <941e3869bdeddb2bebcc52ebfd57efe014887bc6.1500038134.git.chunkeey@googlemail.com>
In-Reply-To: <d45ae31e888ad858d9f4396cabb4dc32a3f0365e.1500038134.git.chunkeey@googlemail.com>
References: <d45ae31e888ad858d9f4396cabb4dc32a3f0365e.1500038134.git.chunkeey@googlemail.com>
From: Ram Chandra Jangir <rjangir@codeaurora.org>
Date: Wed, 10 May 2017 12:51:51 +0200
Subject: [PATCH v3 2/3] pinctrl: qcom: ipq4019: add most remaining pin
definitions
To: linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
This patch adds multiple pinctrl functions and mappings
for SDIO, NAND, I2S, WIFI, PCIE, LEDs, etc... that have
been missing from the current minimal version.
This patch has been updated from the original version
that was posted by Ram Chandra Jangir on the LEDE-DEV ML:
<https://patchwork.ozlabs.org/patch/752962/>. A short
summary of the changes are documented in the device-tree
patch of this series:
"dt-bindings: pinctrl: add most other IPQ4019 pin functions and groups"
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: John Crispin <john@phrozen.org>
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 431 ++++++++++++++++++++++++++-------
1 file changed, 346 insertions(+), 85 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 743d1f458205..9e7f23d29cda 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -277,12 +277,49 @@ DECLARE_QCA_GPIO_PINS(99);
enum ipq4019_functions {
qca_mux_gpio,
- qca_mux_blsp_uart1,
+ qca_mux_aud_pin,
+ qca_mux_audio_pwm,
qca_mux_blsp_i2c0,
qca_mux_blsp_i2c1,
- qca_mux_blsp_uart0,
- qca_mux_blsp_spi1,
qca_mux_blsp_spi0,
+ qca_mux_blsp_spi1,
+ qca_mux_blsp_uart0,
+ qca_mux_blsp_uart1,
+ qca_mux_chip_rst,
+ qca_mux_i2s_rx,
+ qca_mux_i2s_spdif_in,
+ qca_mux_i2s_spdif_out,
+ qca_mux_i2s_td,
+ qca_mux_i2s_tx,
+ qca_mux_jtag,
+ qca_mux_led0,
+ qca_mux_led1,
+ qca_mux_led2,
+ qca_mux_led3,
+ qca_mux_led4,
+ qca_mux_led5,
+ qca_mux_led6,
+ qca_mux_led7,
+ qca_mux_led8,
+ qca_mux_led9,
+ qca_mux_led10,
+ qca_mux_led11,
+ qca_mux_mdc,
+ qca_mux_mdio,
+ qca_mux_pcie,
+ qca_mux_pmu,
+ qca_mux_prng_rosc,
+ qca_mux_qpic,
+ qca_mux_rgmii,
+ qca_mux_rmii,
+ qca_mux_sdio,
+ qca_mux_smart0,
+ qca_mux_smart1,
+ qca_mux_smart2,
+ qca_mux_smart3,
+ qca_mux_tm,
+ qca_mux_wifi0,
+ qca_mux_wifi1,
qca_mux_NA,
};
@@ -303,108 +340,331 @@ static const char * const gpio_groups[] = {
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
"gpio99",
};
-
-static const char * const blsp_uart1_groups[] = {
- "gpio8", "gpio9", "gpio10", "gpio11",
+static const char * const aud_pin_groups[] = {
+ "gpio48", "gpio49", "gpio50", "gpio51",
+};
+static const char * const audio_pwm_groups[] = {
+ "gpio30", "gpio31", "gpio32", "gpio33", "gpio64", "gpio65", "gpio66",
+ "gpio67",
};
static const char * const blsp_i2c0_groups[] = {
"gpio10", "gpio11", "gpio20", "gpio21", "gpio58", "gpio59",
};
-static const char * const blsp_spi0_groups[] = {
- "gpio12", "gpio13", "gpio14", "gpio15", "gpio45",
- "gpio54", "gpio55", "gpio56", "gpio57",
-};
static const char * const blsp_i2c1_groups[] = {
"gpio12", "gpio13", "gpio34", "gpio35",
};
-static const char * const blsp_uart0_groups[] = {
- "gpio16", "gpio17", "gpio60", "gpio61",
+static const char * const blsp_spi0_groups[] = {
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio45", "gpio54", "gpio55",
+ "gpio56", "gpio57",
};
static const char * const blsp_spi1_groups[] = {
"gpio44", "gpio45", "gpio46", "gpio47",
};
+static const char * const blsp_uart0_groups[] = {
+ "gpio16", "gpio17", "gpio60", "gpio61",
+};
+static const char * const blsp_uart1_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+static const char * const chip_rst_groups[] = {
+ "gpio62",
+};
+static const char * const i2s_rx_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio58", "gpio60", "gpio61", "gpio63",
+};
+static const char * const i2s_spdif_in_groups[] = {
+ "gpio34", "gpio59", "gpio63",
+};
+static const char * const i2s_spdif_out_groups[] = {
+ "gpio35", "gpio62", "gpio63",
+};
+static const char * const i2s_td_groups[] = {
+ "gpio27", "gpio28", "gpio29", "gpio54", "gpio55", "gpio56", "gpio63",
+};
+static const char * const i2s_tx_groups[] = {
+ "gpio24", "gpio25", "gpio26", "gpio52", "gpio53", "gpio57", "gpio60",
+ "gpio61",
+};
+static const char * const jtag_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
+};
+static const char * const led0_groups[] = {
+ "gpio16", "gpio36", "gpio60",
+};
+static const char * const led1_groups[] = {
+ "gpio17", "gpio37", "gpio61",
+};
+static const char * const led2_groups[] = {
+ "gpio36", "gpio38", "gpio58",
+};
+static const char * const led3_groups[] = {
+ "gpio39",
+};
+static const char * const led4_groups[] = {
+ "gpio40",
+};
+static const char * const led5_groups[] = {
+ "gpio44",
+};
+static const char * const led6_groups[] = {
+ "gpio45",
+};
+static const char * const led7_groups[] = {
+ "gpio46",
+};
+static const char * const led8_groups[] = {
+ "gpio47",
+};
+static const char * const led9_groups[] = {
+ "gpio48",
+};
+static const char * const led10_groups[] = {
+ "gpio49",
+};
+static const char * const led11_groups[] = {
+ "gpio50",
+};
+static const char * const mdc_groups[] = {
+ "gpio7", "gpio52",
+};
+static const char * const mdio_groups[] = {
+ "gpio6", "gpio53",
+};
+static const char * const pcie_groups[] = {
+ "gpio39", "gpio52",
+};
+static const char * const pmu_groups[] = {
+ "gpio54", "gpio55",
+};
+static const char * const prng_rosc_groups[] = {
+ "gpio53",
+};
+static const char * const qpic_groups[] = {
+ "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58",
+ "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
+ "gpio66", "gpio67", "gpio68", "gpio69",
+};
+static const char * const rgmii_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33",
+};
+static const char * const rmii_groups[] = {
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51",
+};
+static const char * const sdio_groups[] = {
+ "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio32",
+};
+static const char * const smart0_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio5", "gpio44", "gpio45", "gpio46",
+ "gpio47",
+};
+static const char * const smart1_groups[] = {
+ "gpio8", "gpio9", "gpio16", "gpio17", "gpio58", "gpio59", "gpio60",
+ "gpio61",
+};
+static const char * const smart2_groups[] = {
+ "gpio40", "gpio41", "gpio48", "gpio49",
+};
+static const char * const smart3_groups[] = {
+ "gpio58", "gpio59", "gpio60", "gpio61",
+};
+static const char * const tm_groups[] = {
+ "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58",
+ "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+};
+static const char * const wifi0_groups[] = {
+ "gpio37", "gpio40", "gpio41", "gpio42", "gpio50", "gpio51", "gpio52",
+ "gpio53", "gpio56", "gpio57", "gpio58", "gpio98",
+};
+static const char * const wifi1_groups[] = {
+ "gpio37", "gpio40", "gpio41", "gpio43", "gpio50", "gpio51", "gpio52",
+ "gpio53", "gpio56", "gpio57", "gpio58", "gpio98",
+};
static const struct msm_function ipq4019_functions[] = {
- FUNCTION(gpio),
- FUNCTION(blsp_uart1),
+ FUNCTION(aud_pin),
+ FUNCTION(audio_pwm),
FUNCTION(blsp_i2c0),
FUNCTION(blsp_i2c1),
- FUNCTION(blsp_uart0),
- FUNCTION(blsp_spi1),
FUNCTION(blsp_spi0),
+ FUNCTION(blsp_spi1),
+ FUNCTION(blsp_uart0),
+ FUNCTION(blsp_uart1),
+ FUNCTION(chip_rst),
+ FUNCTION(gpio),
+ FUNCTION(i2s_rx),
+ FUNCTION(i2s_spdif_in),
+ FUNCTION(i2s_spdif_out),
+ FUNCTION(i2s_td),
+ FUNCTION(i2s_tx),
+ FUNCTION(jtag),
+ FUNCTION(led0),
+ FUNCTION(led1),
+ FUNCTION(led2),
+ FUNCTION(led3),
+ FUNCTION(led4),
+ FUNCTION(led5),
+ FUNCTION(led6),
+ FUNCTION(led7),
+ FUNCTION(led8),
+ FUNCTION(led9),
+ FUNCTION(led10),
+ FUNCTION(led11),
+ FUNCTION(mdc),
+ FUNCTION(mdio),
+ FUNCTION(pcie),
+ FUNCTION(pmu),
+ FUNCTION(prng_rosc),
+ FUNCTION(qpic),
+ FUNCTION(rgmii),
+ FUNCTION(rmii),
+ FUNCTION(sdio),
+ FUNCTION(smart0),
+ FUNCTION(smart1),
+ FUNCTION(smart2),
+ FUNCTION(smart3),
+ FUNCTION(tm),
+ FUNCTION(wifi0),
+ FUNCTION(wifi1),
};
static const struct msm_pingroup ipq4019_groups[] = {
- PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(8, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(9, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(16, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(17, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(0, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(1, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(2, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(3, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(4, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(5, jtag, smart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(6, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(7, mdc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(8, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(9, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(16, blsp_uart0, led0, smart1, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(17, blsp_uart0, led1, smart1, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(20, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(21, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(22, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(24, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(25, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(27, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(28, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(34, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(35, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(44, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(45, NA, blsp_spi1, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(46, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(47, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(54, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(55, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(56, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(57, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(58, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(59, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(60, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(61, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(20, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(21, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(22, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(23, sdio, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(24, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(25, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(26, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(27, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(28, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(29, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(30, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(31, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(32, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(33, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(34, blsp_i2c1, i2s_spdif_in, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA, NA),
+ PINGROUP(35, blsp_i2c1, i2s_spdif_out, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA, NA),
+ PINGROUP(36, rmii, led2, led0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(37, rmii, wifi0, wifi1, led1, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(38, rmii, led2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(39, rmii, pcie, led3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(40, rmii, wifi0, wifi1, smart2, led4, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(41, rmii, wifi0, wifi1, smart2, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(42, rmii, wifi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(43, rmii, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(44, rmii, blsp_spi1, smart0, led5, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(45, rmii, blsp_spi1, blsp_spi0, smart0, led6, NA, NA, NA, NA,
+ NA, NA, NA, NA, NA),
+ PINGROUP(46, rmii, blsp_spi1, smart0, led7, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(47, rmii, blsp_spi1, smart0, led8, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(48, rmii, aud_pin, smart2, led9, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(49, rmii, aud_pin, smart2, led10, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(50, rmii, aud_pin, wifi0, wifi1, led11, NA, NA, NA, NA, NA,
+ NA, NA, NA, NA),
+ PINGROUP(51, rmii, aud_pin, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(52, qpic, mdc, pcie, i2s_tx, NA, NA, NA, tm, wifi0, wifi1, NA,
+ NA, NA, NA),
+ PINGROUP(53, qpic, mdio, i2s_tx, prng_rosc, NA, tm, wifi0, wifi1, NA,
+ NA, NA, NA, NA, NA),
+ PINGROUP(54, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA,
+ NA, NA, NA),
+ PINGROUP(55, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA,
+ NA, NA, NA),
+ PINGROUP(56, qpic, blsp_spi0, i2s_td, NA, NA, tm, wifi0, wifi1, NA, NA,
+ NA, NA, NA, NA),
+ PINGROUP(57, qpic, blsp_spi0, i2s_tx, NA, NA, tm, wifi0, wifi1, NA, NA,
+ NA, NA, NA, NA),
+ PINGROUP(58, qpic, led2, blsp_i2c0, smart3, smart1, i2s_rx, NA, NA, tm,
+ wifi0, wifi1, NA, NA, NA),
+ PINGROUP(59, qpic, blsp_i2c0, smart3, smart1, i2s_spdif_in, NA, NA, NA,
+ NA, NA, tm, NA, NA, NA),
+ PINGROUP(60, qpic, blsp_uart0, smart1, smart3, led0, i2s_tx, i2s_rx,
+ NA, NA, NA, NA, NA, tm, NA),
+ PINGROUP(61, qpic, blsp_uart0, smart1, smart3, led1, i2s_tx, i2s_rx,
+ NA, NA, NA, NA, NA, tm, NA),
+ PINGROUP(62, qpic, chip_rst, NA, NA, i2s_spdif_out, NA, NA, NA, NA, NA,
+ tm, NA, NA, NA),
+ PINGROUP(63, qpic, NA, NA, NA, i2s_td, i2s_rx, i2s_spdif_out,
+ i2s_spdif_in, NA, NA, NA, NA, tm, NA),
+ PINGROUP(64, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(65, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(66, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(67, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(68, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(69, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
@@ -433,7 +693,8 @@ static const struct msm_pingroup ipq4019_groups[] = {
PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(98, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
+ NA),
PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
};
--
2.13.2

149
target/linux/ipq806x/patches-4.9/132-pinctrl-qcom-add-support-to-configure-ipq40xx-GPIO_P.patch Normal file
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@ -0,0 +1,149 @@
From 895bbe5061fe2a6825503f57263a4eff9bb78a3c Mon Sep 17 00:00:00 2001
Message-Id: <895bbe5061fe2a6825503f57263a4eff9bb78a3c.1500038134.git.chunkeey@googlemail.com>
In-Reply-To: <941e3869bdeddb2bebcc52ebfd57efe014887bc6.1500038134.git.chunkeey@googlemail.com>
References: <d45ae31e888ad858d9f4396cabb4dc32a3f0365e.1500038134.git.chunkeey@googlemail.com>
<941e3869bdeddb2bebcc52ebfd57efe014887bc6.1500038134.git.chunkeey@googlemail.com>
From: Ram Chandra Jangir <rjangir@codeaurora.org>
Date: Sun, 4 Jun 2017 21:38:21 +0200
Subject: [PATCH v3 3/3] pinctrl: msm: add support to configure ipq40xx
GPIO_PULL bits
To: linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
GPIO_PULL bits configurations in TLMM_GPIO_CFG register
differs for IPQ40xx from rest of the other qcom SoCs.
As it does not support the keeper state and therefore can't
support bias-bus-hold property.
This patch adds a pull_no_keeper setting which configures the
msm_gpio_pull bits for ipq40xx. This is required to fix the
proper configurations of gpio-pull bits for nand pins mux.
IPQ40xx SoC:
2'b10: Internal pull up enable.
2'b11: Unsupport
For other SoC's:
2'b10: Keeper
2'b11: Pull-Up
Note: Due to pull_no_keeper length, all kerneldoc entries
in the msm_pinctrl_soc_data struct had to be realigned.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1 +
drivers/pinctrl/qcom/pinctrl-msm.c | 25 +++++++++++++++++++------
drivers/pinctrl/qcom/pinctrl-msm.h | 16 +++++++++-------
3 files changed, 29 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 9e7f23d29cda..1979b14b6fc3 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -706,6 +706,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
.groups = ipq4019_groups,
.ngroups = ARRAY_SIZE(ipq4019_groups),
.ngpios = 100,
+ .pull_no_keeper = true,
};
static int ipq4019_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 273badd92561..e5e27d79f5ef 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -202,10 +202,11 @@ static int msm_config_reg(struct msm_pinctrl *pctrl,
return 0;
}
-#define MSM_NO_PULL 0
-#define MSM_PULL_DOWN 1
-#define MSM_KEEPER 2
-#define MSM_PULL_UP 3
+#define MSM_NO_PULL 0
+#define MSM_PULL_DOWN 1
+#define MSM_KEEPER 2
+#define MSM_PULL_UP_NO_KEEPER 2
+#define MSM_PULL_UP 3
static unsigned msm_regval_to_drive(u32 val)
{
@@ -243,10 +244,16 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
arg = arg == MSM_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
+ if (pctrl->soc->pull_no_keeper)
+ return -ENOTSUPP;
+
arg = arg == MSM_KEEPER;
break;
case PIN_CONFIG_BIAS_PULL_UP:
- arg = arg == MSM_PULL_UP;
+ if (pctrl->soc->pull_no_keeper)
+ arg = arg == MSM_PULL_UP_NO_KEEPER;
+ else
+ arg = arg == MSM_PULL_UP;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
arg = msm_regval_to_drive(arg);
@@ -309,10 +316,16 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
arg = MSM_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
+ if (pctrl->soc->pull_no_keeper)
+ return -ENOTSUPP;
+
arg = MSM_KEEPER;
break;
case PIN_CONFIG_BIAS_PULL_UP:
- arg = MSM_PULL_UP;
+ if (pctrl->soc->pull_no_keeper)
+ arg = MSM_PULL_UP_NO_KEEPER;
+ else
+ arg = MSM_PULL_UP;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
/* Check for invalid values */
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 54fdd04ce9d5..9b9feea540ff 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -99,13 +99,14 @@ struct msm_pingroup {
/**
* struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
- * @pins: An array describing all pins the pin controller affects.
- * @npins: The number of entries in @pins.
- * @functions: An array describing all mux functions the SoC supports.
- * @nfunctions: The number of entries in @functions.
- * @groups: An array describing all pin groups the pin SoC supports.
- * @ngroups: The numbmer of entries in @groups.
- * @ngpio: The number of pingroups the driver should expose as GPIOs.
+ * @pins: An array describing all pins the pin controller affects.
+ * @npins: The number of entries in @pins.
+ * @functions: An array describing all mux functions the SoC supports.
+ * @nfunctions: The number of entries in @functions.
+ * @groups: An array describing all pin groups the pin SoC supports.
+ * @ngroups: The numbmer of entries in @groups.
+ * @ngpio: The number of pingroups the driver should expose as GPIOs.
+ * @pull_no_keeper: The SoC does not support keeper bias.
*/
struct msm_pinctrl_soc_data {
const struct pinctrl_pin_desc *pins;
@@ -115,6 +116,7 @@ struct msm_pinctrl_soc_data {
const struct msm_pingroup *groups;
unsigned ngroups;
unsigned ngpios;
+ bool pull_no_keeper;
};
int msm_pinctrl_probe(struct platform_device *pdev,
--
2.13.2

28
target/linux/ipq806x/patches-4.9/140-qcom-ipq4019-fix-i2c_0-node.patch Normal file
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@ -0,0 +1,28 @@
From 830a63791185f4daaecb8d1102c4ee3c9210c03c Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@googlemail.com>
Date: Mon, 1 May 2017 13:42:41 +0200
Subject: [PATCH 1/2] qcom: ipq4019: fix i2c_0 node
This patch fixes two typos in the i2c_0 node for the ipq4019.
The register size is just 0x600. The core clock is
GCC_BLSP1_QUP1_I2C_APPS_CLK. GCC_BLSP1_QUP2_I2C_APPS_CLK is
used by the second i2c.
Fixes: e76b4284b520ba3 ("qcom: ipq4019: add i2c node to ipq4019 SoC and DK01 device tree")
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -184,7 +184,7 @@
i2c_0: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
- reg = <0x78b7000 0x6000>;
+ reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;

46
target/linux/ipq806x/patches-4.9/141-qcom-ipq4019-add-second-i2c.patch Normal file
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@ -0,0 +1,46 @@
From 5110346bcc17b037edd5b0193f31ad046e6242db Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@googlemail.com>
Date: Mon, 1 May 2017 13:53:07 +0200
Subject: [PATCH 2/2] qcom: ipq4019: add second i2c
This patch adds the second i2c block to the IPQ4019 platform.
The second i2c has been successfully tested on the
Cisco Meraki MR33.
Cc: Chris Blake <chrisrblake93@gmail.com>
Cc: Matthew McClintock <msm-oss@mcclintock.net>
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -26,6 +26,7 @@
aliases {
spi0 = &spi_0;
i2c0 = &i2c_0;
+ i2c1 = &i2c_1;
};
cpus {
@@ -196,6 +197,19 @@
status = "disabled";
};
+ i2c_1: i2c@78b8000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x78b8000 0x600>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
+ dma-names = "rx", "tx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
cryptobam: dma@8e04000 {
compatible = "qcom,bam-v1.7.0";

10
target/linux/ipq806x/patches-4.9/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch
View File

@ -17,7 +17,7 @@ Changes:
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -34,19 +34,27 @@
@@ -35,19 +35,27 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
@ -47,7 +47,7 @@ Changes:
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
reg = <0x1>;
@@ -58,7 +66,8 @@
@@ -59,7 +67,8 @@
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
@ -57,7 +57,7 @@ Changes:
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
reg = <0x2>;
@@ -70,7 +79,8 @@
@@ -71,7 +80,8 @@
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
@ -67,7 +67,7 @@ Changes:
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
reg = <0x3>;
@@ -218,22 +228,22 @@
@@ -236,22 +246,22 @@
};
acc0: clock-controller@b088000 {
@ -94,7 +94,7 @@ Changes:
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
};
@@ -261,6 +271,12 @@
@@ -279,6 +289,12 @@
regulator;
};

2
target/linux/ipq806x/patches-4.9/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch
View File

@ -51,7 +51,7 @@ Changes:
};
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -313,5 +313,76 @@
@@ -331,5 +331,76 @@
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>;
};

170
target/linux/ipq806x/patches-4.9/308-dts-ipq4019-add-both-IPQ4019-wifi-block-definitions.patch
View File

@ -1,57 +1,100 @@
From 6091a49b0b06bf838fed80498c4f5f40d0fbd447 Mon Sep 17 00:00:00 2001
From 45e183ad169db4e233ce8337cf8b735545151f0e Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sat, 19 Nov 2016 01:22:46 +0100
Subject: [PATCH] dts: ipq4019: add both IPQ4019 wifi block definitions
Subject: [PATCH] arm: dts: qcom: add both IPQ4019 wifi blocks
The IPQ4019 has two ath10k blocks on the AHB. Both wifi's
are already supported by ath10k.
This patch adds and enables the device-tree definitions for
both qcom,ipq4019-wifi blocks for the IPQ4019.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Support for these have been added into the ath10k driver since:
280e762e9c72 ("ath10k: enable ipq4019 device probe in ahb module")
The binding documentation was added in commit:
a47aaa69de88 ("dt: bindings: add new dt entry for pre calibration in qcom, ath10k.txt")
This has been tested on an ASUS RT-AC58U (IPQ4019),
an AVM Fritz!Box 4040 (IPQ4018), a Compex WPJ428(IPQ4028)
and a Meraki MR33 (IPQ4029).
| a000000.wifi: qca4019 hw1.0 target 0x01000000 chip_id 0x003b00ff [...]
| a000000.wifi: kconfig debug 0 debugfs 1 tracing 0 dfs 1 testmode 1
| a000000.wifi: firmware ver 10.4-3.4-00082 api 5 features no-p2p,mfp,[...]
| a000000.wifi: board_file api 2 bmi_id 0:16 crc32 5773b188
| a000000.wifi: htt-ver 2.2 wmi-op 6 htt-op 4 cal pre-cal-file [...]
...
| a800000.wifi: qca4019 hw1.0 target 0x01000000 chip_id 0x003b00ff sub 0000:0000
| a800000.wifi: kconfig debug 0 debugfs 1 tracing 0 dfs 1 testmode 1
| a800000.wifi: firmware ver 10.4-3.4-00082 api 5 features no-p2p, [...]
| a800000.wifi: board_file api 2 bmi_id 0:17 crc32 5773b188
| a800000.wifi: htt-ver 2.2 wmi-op 6 htt-op 4 cal pre-cal-file [...]
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 84 +++++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8 +++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 84 +++++++++++++++++++++++++++
2 files changed, 92 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index c25d8f5c669d..cfa0c9970d5b 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -112,5 +112,13 @@
watchdog@b017000 {
status = "ok";
};
+
+ wifi@a000000 {
+ status = "ok";
+ };
+
+ wifi@a800000 {
+ status = "ok";
+ };
};
};
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index d1a56331ce96..1ddcc96b510c 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -384,5 +384,89 @@
dr_mode = "host";
};
@@ -291,5 +291,89 @@
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>;
};
+
+ wifi0: wifi@a000000 {
+ compatible = "qcom,ipq4019-wifi";
+ reg = <0xa000000 0x200000>;
+ resets = <&gcc WIFI0_CPU_INIT_RESET
+ &gcc WIFI0_RADIO_SRIF_RESET
+ &gcc WIFI0_RADIO_WARM_RESET
+ &gcc WIFI0_RADIO_COLD_RESET
+ &gcc WIFI0_CORE_WARM_RESET
+ &gcc WIFI0_CORE_COLD_RESET>;
+ resets = <&gcc WIFI0_CPU_INIT_RESET>,
+ <&gcc WIFI0_RADIO_SRIF_RESET>,
+ <&gcc WIFI0_RADIO_WARM_RESET>,
+ <&gcc WIFI0_RADIO_COLD_RESET>,
+ <&gcc WIFI0_CORE_WARM_RESET>,
+ <&gcc WIFI0_CORE_COLD_RESET>;
+ reset-names = "wifi_cpu_init", "wifi_radio_srif",
+ "wifi_radio_warm", "wifi_radio_cold",
+ "wifi_core_warm", "wifi_core_cold";
+ clocks = <&gcc GCC_WCSS2G_CLK
+ &gcc GCC_WCSS2G_REF_CLK
+ &gcc GCC_WCSS2G_RTC_CLK>;
+ clocks = <&gcc GCC_WCSS2G_CLK>,
+ <&gcc GCC_WCSS2G_REF_CLK>,
+ <&gcc GCC_WCSS2G_RTC_CLK>;
+ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
+ "wifi_wcss_rtc";
+ interrupts = <0 32 IRQ_TYPE_EDGE_RISING
+ 0 33 IRQ_TYPE_EDGE_RISING
+ 0 34 IRQ_TYPE_EDGE_RISING
+ 0 35 IRQ_TYPE_EDGE_RISING
+ 0 36 IRQ_TYPE_EDGE_RISING
+ 0 37 IRQ_TYPE_EDGE_RISING
+ 0 38 IRQ_TYPE_EDGE_RISING
+ 0 39 IRQ_TYPE_EDGE_RISING
+ 0 40 IRQ_TYPE_EDGE_RISING
+ 0 41 IRQ_TYPE_EDGE_RISING
+ 0 42 IRQ_TYPE_EDGE_RISING
+ 0 43 IRQ_TYPE_EDGE_RISING
+ 0 44 IRQ_TYPE_EDGE_RISING
+ 0 45 IRQ_TYPE_EDGE_RISING
+ 0 46 IRQ_TYPE_EDGE_RISING
+ 0 47 IRQ_TYPE_EDGE_RISING
+ 0 168 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 168 IRQ_TYPE_NONE>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7",
+ "msi8", "msi9", "msi10", "msi11",
@ -63,37 +106,37 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+ wifi1: wifi@a800000 {
+ compatible = "qcom,ipq4019-wifi";
+ reg = <0xa800000 0x200000>;
+ resets = <&gcc WIFI1_CPU_INIT_RESET
+ &gcc WIFI1_RADIO_SRIF_RESET
+ &gcc WIFI1_RADIO_WARM_RESET
+ &gcc WIFI1_RADIO_COLD_RESET
+ &gcc WIFI1_CORE_WARM_RESET
+ &gcc WIFI1_CORE_COLD_RESET>;
+ resets = <&gcc WIFI1_CPU_INIT_RESET>,
+ <&gcc WIFI1_RADIO_SRIF_RESET>,
+ <&gcc WIFI1_RADIO_WARM_RESET>,
+ <&gcc WIFI1_RADIO_COLD_RESET>,
+ <&gcc WIFI1_CORE_WARM_RESET>,
+ <&gcc WIFI1_CORE_COLD_RESET>;
+ reset-names = "wifi_cpu_init", "wifi_radio_srif",
+ "wifi_radio_warm", "wifi_radio_cold",
+ "wifi_core_warm", "wifi_core_cold";
+ clocks = <&gcc GCC_WCSS5G_CLK
+ &gcc GCC_WCSS5G_REF_CLK
+ &gcc GCC_WCSS5G_RTC_CLK>;
+ clocks = <&gcc GCC_WCSS5G_CLK>,
+ <&gcc GCC_WCSS5G_REF_CLK>,
+ <&gcc GCC_WCSS5G_RTC_CLK>;
+ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
+ "wifi_wcss_rtc";
+ interrupts = <0 48 IRQ_TYPE_EDGE_RISING
+ 0 49 IRQ_TYPE_EDGE_RISING
+ 0 50 IRQ_TYPE_EDGE_RISING
+ 0 51 IRQ_TYPE_EDGE_RISING
+ 0 52 IRQ_TYPE_EDGE_RISING
+ 0 53 IRQ_TYPE_EDGE_RISING
+ 0 54 IRQ_TYPE_EDGE_RISING
+ 0 55 IRQ_TYPE_EDGE_RISING
+ 0 56 IRQ_TYPE_EDGE_RISING
+ 0 57 IRQ_TYPE_EDGE_RISING
+ 0 58 IRQ_TYPE_EDGE_RISING
+ 0 59 IRQ_TYPE_EDGE_RISING
+ 0 60 IRQ_TYPE_EDGE_RISING
+ 0 61 IRQ_TYPE_EDGE_RISING
+ 0 62 IRQ_TYPE_EDGE_RISING
+ 0 63 IRQ_TYPE_EDGE_RISING
+ 0 169 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 169 IRQ_TYPE_NONE>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7",
+ "msi8", "msi9", "msi10", "msi11",
@ -103,3 +146,6 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+ };
};
};
--
2.13.3

2
target/linux/ipq806x/patches-4.9/309-dts-ipq4019-add-pseudo-random-number-generator.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -277,6 +277,13 @@
@@ -295,6 +295,13 @@
regulator;
};

25
target/linux/ipq806x/patches-4.9/311-dts-ARM-qcom-ipq4019-add-scm-node.patch Normal file
View File

@ -0,0 +1,25 @@
From: Christian Lamparter <chunkeey@googlemail.com>
Date: Mon, 20 Mar 2017 18:08:03 +0100
Subject: [PATCH] dts: ARM: qcom-ipq4019: add scm node
This patch adds the device-tree node necessary for communicating
with Qualcomm's TrustZone/Secure Execution Environment
implementation.
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
---
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -137,6 +137,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq4019", "qcom,scm-ipq40xx";
+ };
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;

98
target/linux/ipq806x/patches-4.9/312-firmware-qcom-scm-fuse-access.patch Normal file
View File

@ -0,0 +1,98 @@
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -578,3 +578,33 @@ int __qcom_scm_pinmux_write(u32 svc_id,
return ret;
}
+
+int __qcom_scm_fuse(struct device *dev, u32 address, u32 *val)
+{
+ __le32 *otp_value;
+ dma_addr_t in;
+ int ret;
+
+ otp_value = kzalloc(PAGE_ALIGN(sizeof(*otp_value)), GFP_KERNEL);
+ if (!otp_value)
+ return -ENOMEM;
+
+ in = dma_map_single(dev, otp_value, sizeof(in), DMA_FROM_DEVICE);
+
+ ret = dma_mapping_error(dev, in);
+ if (ret != 0) {
+ kfree(otp_value);
+ pr_err("DMA Mapping Error %d\n", ret);
+ return ret;
+ }
+
+ ret = qcom_scm_call(dev, QCOM_SCM_SVC_FUSE, address,
+ &in, sizeof(in), NULL, 0);
+
+ dma_unmap_single(dev, in, sizeof(in), DMA_FROM_DEVICE);
+
+ *val = le32_to_cpu(*otp_value);
+ kfree(otp_value);
+
+ return ret;
+}
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -165,6 +165,25 @@ int qcom_scm_hdcp_req(struct qcom_scm_hd
EXPORT_SYMBOL(qcom_scm_hdcp_req);
/**
+ * qcom_scm_fuse() - Reads a value from the OTP
+ * @address: address
+ *
+ * Returns the value of the OTP at the specified address.
+ */
+int qcom_scm_fuse(u32 address, u32 *val)
+{
+ int ret = qcom_scm_clk_enable();
+
+ if (ret)
+ return ret;
+
+ ret = __qcom_scm_fuse(__scm->dev, address, val);
+ qcom_scm_clk_disable();
+ return ret;
+}
+EXPORT_SYMBOL(qcom_scm_fuse);
+
+/**
* qcom_scm_pas_supported() - Check if the peripheral authentication service is
* available for the given peripherial
* @peripheral: peripheral id
--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
@@ -63,6 +63,9 @@ extern int __qcom_scm_pas_mss_reset(str
s32 __qcom_scm_pinmux_read(u32 svc_id, u32 cmd_id, u32 arg1);
s32 __qcom_scm_pinmux_write(u32 svc_id, u32 cmd_id, u32 arg1, u32 arg2);
+#define QCOM_SCM_SVC_FUSE 0x8
+extern int __qcom_scm_fuse(struct device *dev, u32 address, u32 *val);
+
/* common error codes */
#define QCOM_SCM_V2_EBUSY -12
#define QCOM_SCM_ENOMEM -5
--- a/include/linux/qcom_scm.h
+++ b/include/linux/qcom_scm.h
@@ -48,4 +48,7 @@ extern u32 qcom_scm_get_version(void);
extern s32 qcom_scm_pinmux_read(u32 arg1);
extern s32 qcom_scm_pinmux_write(u32 arg1, u32 arg2);
+
+extern int qcom_scm_fuse(u32 address, u32 *val);
+
#endif
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -374,3 +374,9 @@ int __qcom_scm_pinmux_write(u32 svc_id,
{
return -ENOTSUPP;
}
+
+int __qcom_scm_fuse(struct device *dev, u32 address, u32 *val)
+{
+ *val = -1;
+ return -ENOTSUPP;
+}

2
target/linux/ipq806x/patches-4.9/701-dts-ipq4019-add-mdio-node.patch
View File

@ -15,7 +15,7 @@ so the info might change.
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -321,6 +321,34 @@
@@ -345,6 +345,34 @@
reg = <0x4ab000 0x4>;
};

2
target/linux/ipq806x/patches-4.9/702-dts-ipq4019-add-PHY-switch-nodes.patch
View File

@ -14,7 +14,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -349,6 +349,29 @@
@@ -373,6 +373,29 @@
};
};

6
target/linux/ipq806x/patches-4.9/711-dts-ipq4019-add-ethernet-essedma-node.patch
View File

@ -16,16 +16,16 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -26,6 +26,8 @@
aliases {
@@ -27,6 +27,8 @@
spi0 = &spi_0;
i2c0 = &i2c_0;
i2c1 = &i2c_1;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
};
cpus {
@@ -372,6 +374,64 @@
@@ -396,6 +398,64 @@
status = "disabled";
};

69
target/linux/ipq806x/patches-4.9/712-net-essedma-disable-default-vlan.patch Normal file
View File

@ -0,0 +1,69 @@
From: Christian Lamparter <chunkeey@googlemail.com>
Subject: [PATCH] net: essedma: disable default vlan tagging
Date: Tue, 21 Mar 13:59:02 CET 2017 +0100
The essedma driver has its own unique take on VLAN management
and its configuration. In the original SDK, each VLAN is
assigned one virtual ethernet netdev.
However, this is non-standard. So, this patch does away
with the default_vlan_tag property the driver is using
and therefore forces the user to use the kernel's vlan
feature.
This patch also removes the "qcom,poll_required = <1>;" from
the essedma node.
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
---
--- a/drivers/net/ethernet/qualcomm/essedma/edma.c
+++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
@@ -715,13 +715,11 @@ static void edma_rx_complete(struct edma
edma_receive_checksum(rd, skb);
/* Process VLAN HW acceleration indication provided by HW */
- if (unlikely(adapter->default_vlan_tag != rd->rrd4)) {
- vlan = rd->rrd4;
- if (likely(rd->rrd7 & EDMA_RRD_CVLAN))
- __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
- else if (rd->rrd1 & EDMA_RRD_SVLAN)
- __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), vlan);
- }
+ vlan = rd->rrd4;
+ if (likely(rd->rrd7 & EDMA_RRD_CVLAN))
+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
+ else if (rd->rrd1 & EDMA_RRD_SVLAN)
+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), vlan);
/* Update rx statistics */
adapter->stats.rx_packets++;
@@ -1390,8 +1388,6 @@ netdev_tx_t edma_xmit(struct sk_buff *sk
/* Check and mark VLAN tag offload */
if (skb_vlan_tag_present(skb))
flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG;
- else if (adapter->default_vlan_tag)
- flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG;
/* Check and mark checksum offload */
if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -404,8 +404,7 @@
qcom,page-mode = <0>;
qcom,rx_head_buf_size = <1540>;
qcom,mdio_supported;
- qcom,poll_required = <1>;
- qcom,num_gmac = <2>;
+ qcom,num_gmac = <1>;
interrupts = <0 65 IRQ_TYPE_EDGE_RISING
0 66 IRQ_TYPE_EDGE_RISING
0 67 IRQ_TYPE_EDGE_RISING
@@ -443,7 +442,7 @@
gmac0: gmac0 {
local-mac-address = [00 00 00 00 00 00];
- vlan_tag = <1 0x1f>;
+ vlan_tag = <1 0x3f>;
};
gmac1: gmac1 {

71
target/linux/ipq806x/patches-4.9/820-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch
View File

@ -291,7 +291,7 @@ Changed:
+MODULE_DESCRIPTION("USB3 QCA BALDUR HSPHY driver");
--- /dev/null
+++ b/drivers/usb/phy/phy-qca-uniphy.c
@@ -0,0 +1,135 @@
@@ -0,0 +1,202 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
@ -318,6 +318,18 @@ Changed:
+#include <linux/usb/phy.h>
+#include <linux/reset.h>
+#include <linux/of_device.h>
+#include <linux/qcom_scm.h>
+
+#define USB_CALIBRATION_CMD 0x10
+#define USB3PHY_SPARE_1 0x7FC
+#define RX_LOS_1 0x7C8
+#define MISC_SOURCE_REG 0x21c
+#define CDR_CONTROL_REG_1 0x80
+#define PCS_INTERNAL_CONTROL14 0x364
+#define MMD1_REG_REG_MASK (0x7F << 8)
+#define OTP_MASK (0x7F << 5)
+#define MMD1_REG_AUTOLOAD_MASK (0x1 << 7)
+#define SPARE_1_BIT14_MASK (0x1 << 14)
+
+struct qca_uni_ss_phy {
+ struct usb_phy phy;
@ -338,6 +350,60 @@ Changed:
+ reset_control_assert(phy->por_rst);
+}
+
+int qca_uni_ss_phy_usb_los_calibration(void __iomem *base)
+{
+ int err;
+ uint32_t data, otp_val = 0;
+
+ /* Get OTP value */
+ err = qcom_scm_fuse(USB_CALIBRATION_CMD, &otp_val);
+ if (err < 0 || !(otp_val & OTP_MASK)) {
+ pr_err("USB Calibration Failed with error %d %d\n", err, otp_val);
+ return 0;
+ }
+
+ pr_info("Raw USB3 Calibration value %x\n", otp_val);
+
+ /*
+ * Read the USB3PHY_SPARE_1 register and
+ * set bit 14 to 0
+ */
+ data = readl_relaxed(base + USB3PHY_SPARE_1);
+ data = data & (~SPARE_1_BIT14_MASK);
+ writel(data, base + USB3PHY_SPARE_1);
+ udelay(100);
+
+ /*
+ * Get bit 11:5 value, add with 0x14 and set to the
+ * register USB3PHY_RX_LOS_1 bit MMD1_REG_REG
+ */
+ data = readl_relaxed(base + RX_LOS_1);
+ otp_val = ((otp_val & OTP_MASK) >> 5) + 0x14;
+ otp_val = otp_val << 8;
+ data = data & (~MMD1_REG_REG_MASK);
+ data = data | otp_val;
+ writel(data, base + RX_LOS_1);
+ udelay(100);
+
+ /*
+ * Set bit MMD1_REG_AUTOLOAD_SEL_RX_LOS_THRES in
+ * USB3PHY_RX_LOS_1 to 1
+ */
+ data = readl_relaxed(base + RX_LOS_1);
+ data = data | MMD1_REG_AUTOLOAD_MASK;
+ writel(data, base + RX_LOS_1);
+ udelay(100);
+
+ writel(0x4000, base + PCS_INTERNAL_CONTROL14);
+ udelay(100);
+ writel(0xaa0a, base + MISC_SOURCE_REG);
+ udelay(100);
+ writel(0x0202, base + CDR_CONTROL_REG_1);
+ udelay(100);
+
+ return 0;
+}
+
+static int qca_uni_ss_phy_init(struct usb_phy *x)
+{
+ struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
@ -350,7 +416,8 @@ Changed:
+ /* deassert SS PHY POR reset */
+ reset_control_deassert(phy->por_rst);
+
+ return 0;
+ /* USB LOS Calibration */
+ return qca_uni_ss_phy_usb_los_calibration(phy->base);
+}
+
+static int qca_uni_ss_get_resources(struct platform_device *pdev,

1328
target/linux/ipq806x/patches-4.9/852-ipq4019-pinctrl-Updated-various-Pin-definitions.patch
View File

File diff suppressed because it is too large Load Diff

236
target/linux/ipq806x/patches-4.9/859-msm-pinctrl-Add-support-to-configure-ipq40xx-GPIO_PU.patch
View File

@ -1,236 +0,0 @@
From e77af7de404eb464f7da9e0daeb8b362cc66a7ba Mon Sep 17 00:00:00 2001
From: Ram Chandra Jangir <rjangir@codeaurora.org>
Date: Tue, 9 May 2017 11:45:00 +0530
Subject: [PATCH] msm: pinctrl: Add support to configure ipq40xx GPIO_PULL bits
GPIO_PULL bits configurations in TLMM_GPIO_CFG register
differs for IPQ40xx from rest of the other qcom SoC's.
This change add support to configure the msm_gpio_pull
bits for ipq40xx, It is required to fix the proper
configurations of gpio-pull bits for nand pins mux.
IPQ40xx SoC:
2'b10: Internal pull up enable.
2'b11: Unsupport
For other SoC's:
2'b10: Keeper
2'b11: Pull-Up
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
---
drivers/pinctrl/qcom/pinctrl-apq8064.c | 1 +
drivers/pinctrl/qcom/pinctrl-apq8084.c | 1 +
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 8 ++++++++
drivers/pinctrl/qcom/pinctrl-ipq8064.c | 1 +
drivers/pinctrl/qcom/pinctrl-mdm9615.c | 1 +
drivers/pinctrl/qcom/pinctrl-msm.c | 21 ++++++++-------------
drivers/pinctrl/qcom/pinctrl-msm.h | 19 +++++++++++++++++++
drivers/pinctrl/qcom/pinctrl-msm8660.c | 1 +
drivers/pinctrl/qcom/pinctrl-msm8916.c | 1 +
drivers/pinctrl/qcom/pinctrl-msm8960.c | 1 +
drivers/pinctrl/qcom/pinctrl-msm8x74.c | 1 +
11 files changed, 43 insertions(+), 13 deletions(-)
--- a/drivers/pinctrl/qcom/pinctrl-apq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
@@ -597,6 +597,7 @@ static const struct msm_pinctrl_soc_data
.groups = apq8064_groups,
.ngroups = ARRAY_SIZE(apq8064_groups),
.ngpios = NUM_GPIO_PINGROUPS,
+ .gpio_pull = &msm_gpio_pull,
};
static int apq8064_pinctrl_probe(struct platform_device *pdev)
--- a/drivers/pinctrl/qcom/pinctrl-apq8084.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
@@ -1206,6 +1206,7 @@ static const struct msm_pinctrl_soc_data
.groups = apq8084_groups,
.ngroups = ARRAY_SIZE(apq8084_groups),
.ngpios = NUM_GPIO_PINGROUPS,
+ .gpio_pull = &msm_gpio_pull,
};
static int apq8084_pinctrl_probe(struct platform_device *pdev)
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -1531,6 +1531,13 @@ static const struct msm_pingroup ipq4019
PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
};
+static const struct msm_pinctrl_gpio_pull ipq4019_gpio_pull = {
+ .no_pull = 0,
+ .pull_down = 1,
+ .keeper = 0,
+ .pull_up = 2,
+};
+
static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
.pins = ipq4019_pins,
.npins = ARRAY_SIZE(ipq4019_pins),
@@ -1539,6 +1546,7 @@ static const struct msm_pinctrl_soc_data
.groups = ipq4019_groups,
.ngroups = ARRAY_SIZE(ipq4019_groups),
.ngpios = 100,
+ .gpio_pull = &ipq4019_gpio_pull,
};
static int ipq4019_pinctrl_probe(struct platform_device *pdev)
--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
@@ -630,6 +630,7 @@ static const struct msm_pinctrl_soc_data
.groups = ipq8064_groups,
.ngroups = ARRAY_SIZE(ipq8064_groups),
.ngpios = NUM_GPIO_PINGROUPS,
+ .gpio_pull = &msm_gpio_pull,
};
static int ipq8064_pinctrl_probe(struct platform_device *pdev)
--- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c
+++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c
@@ -444,6 +444,7 @@ static const struct msm_pinctrl_soc_data
.groups = mdm9615_groups,
.ngroups = ARRAY_SIZE(mdm9615_groups),
.ngpios = NUM_GPIO_PINGROUPS,
+ .gpio_pull = &msm_gpio_pull,
};
static int mdm9615_pinctrl_probe(struct platform_device *pdev)
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -203,11 +203,6 @@ static int msm_config_reg(struct msm_pin
return 0;
}
-#define MSM_NO_PULL 0
-#define MSM_PULL_DOWN 1
-#define MSM_KEEPER 2
-#define MSM_PULL_UP 3
-
static unsigned msm_regval_to_drive(u32 val)
{
return (val + 1) * 2;
@@ -238,16 +233,16 @@ static int msm_config_group_get(struct p
/* Convert register value to pinconf value */
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
- arg = arg == MSM_NO_PULL;
+ arg = arg == pctrl->soc->gpio_pull->no_pull;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
- arg = arg == MSM_PULL_DOWN;
+ arg = arg == pctrl->soc->gpio_pull->pull_down;
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
- arg = arg == MSM_KEEPER;
+ arg = arg == pctrl->soc->gpio_pull->keeper;
break;
case PIN_CONFIG_BIAS_PULL_UP:
- arg = arg == MSM_PULL_UP;
+ arg = arg == pctrl->soc->gpio_pull->pull_up;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
arg = msm_regval_to_drive(arg);
@@ -304,16 +299,16 @@ static int msm_config_group_set(struct p
/* Convert pinconf values to register values */
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
- arg = MSM_NO_PULL;
+ arg = pctrl->soc->gpio_pull->no_pull;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
- arg = MSM_PULL_DOWN;
+ arg = pctrl->soc->gpio_pull->pull_down;
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
- arg = MSM_KEEPER;
+ arg = pctrl->soc->gpio_pull->keeper;
break;
case PIN_CONFIG_BIAS_PULL_UP:
- arg = MSM_PULL_UP;
+ arg = pctrl->soc->gpio_pull->pull_up;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
/* Check for invalid values */
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -98,6 +98,16 @@ struct msm_pingroup {
};
/**
+ * struct msm_pinctrl_gpio_pull - pinctrl pull value bit field descriptor
+ */
+struct msm_pinctrl_gpio_pull {
+ unsigned no_pull;
+ unsigned pull_down;
+ unsigned keeper;
+ unsigned pull_up;
+};
+
+/**
* struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
* @pins: An array describing all pins the pin controller affects.
* @npins: The number of entries in @pins.
@@ -106,6 +116,7 @@ struct msm_pingroup {
* @groups: An array describing all pin groups the pin SoC supports.
* @ngroups: The numbmer of entries in @groups.
* @ngpio: The number of pingroups the driver should expose as GPIOs.
+ * @gpio_pull_val: The pull value bit field descriptor.
*/
struct msm_pinctrl_soc_data {
const struct pinctrl_pin_desc *pins;
@@ -115,6 +126,14 @@ struct msm_pinctrl_soc_data {
const struct msm_pingroup *groups;
unsigned ngroups;
unsigned ngpios;
+ const struct msm_pinctrl_gpio_pull *gpio_pull;
+};
+
+static const struct msm_pinctrl_gpio_pull msm_gpio_pull = {
+ .no_pull = 0,
+ .pull_down = 1,
+ .keeper = 2,
+ .pull_up = 3,
};
int msm_pinctrl_probe(struct platform_device *pdev,
--- a/drivers/pinctrl/qcom/pinctrl-msm8660.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c
@@ -979,6 +979,7 @@ static const struct msm_pinctrl_soc_data
.groups = msm8660_groups,
.ngroups = ARRAY_SIZE(msm8660_groups),
.ngpios = NUM_GPIO_PINGROUPS,
+ .gpio_pull = &msm_gpio_pull,
};
static int msm8660_pinctrl_probe(struct platform_device *pdev)
--- a/drivers/pinctrl/qcom/pinctrl-msm8916.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c
@@ -967,6 +967,7 @@ static const struct msm_pinctrl_soc_data
.groups = msm8916_groups,
.ngroups = ARRAY_SIZE(msm8916_groups),
.ngpios = NUM_GPIO_PINGROUPS,
+ .gpio_pull = &msm_gpio_pull,
};
static int msm8916_pinctrl_probe(struct platform_device *pdev)
--- a/drivers/pinctrl/qcom/pinctrl-msm8960.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
@@ -1244,6 +1244,7 @@ static const struct msm_pinctrl_soc_data
.groups = msm8960_groups,
.ngroups = ARRAY_SIZE(msm8960_groups),
.ngpios = NUM_GPIO_PINGROUPS,
+ .gpio_pull = &msm_gpio_pull,
};
static int msm8960_pinctrl_probe(struct platform_device *pdev)
--- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
@@ -1069,6 +1069,7 @@ static const struct msm_pinctrl_soc_data
.groups = msm8x74_groups,
.ngroups = ARRAY_SIZE(msm8x74_groups),
.ngpios = NUM_GPIO_PINGROUPS,
+ .gpio_pull = &msm_gpio_pull,
};
static int msm8x74_pinctrl_probe(struct platform_device *pdev)

70
target/linux/ipq806x/patches-4.9/863-dts-ipq4019-add-nand-and-qpic-bam-dma-node.patch
View File

@ -15,78 +15,17 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -88,6 +88,86 @@
@@ -88,6 +88,26 @@
bias-disable;
};
};
+
+ nand_pins: nand_pins {
+
+ mux_1 {
+ pins = "gpio52", "gpio53", "gpio54",
+ "gpio55", "gpio56", "gpio61",
+ "gpio62", "gpio63", "gpio69";
+ function = "qpic_pad";
+ bias-disable;
+ };
+
+ mux_2 {
+ pins = "gpio67";
+ function = "qpic_pad0";
+ bias-disable;
+ };
+
+ mux_3 {
+ pins = "gpio64";
+ function = "qpic_pad1";
+ bias-disable;
+ };
+
+ mux_4 {
+ pins = "gpio65";
+ function = "qpic_pad2";
+ bias-disable;
+ };
+
+ mux_5 {
+ pins = "gpio66";
+ function = "qpic_pad3";
+ bias-disable;
+ };
+
+ mux_6 {
+ pins = "gpio57";
+ function = "qpic_pad4";
+ bias-disable;
+ };
+
+ mux_7 {
+ pins = "gpio58";
+ function = "qpic_pad5";
+ bias-disable;
+ };
+
+ mux_8 {
+ pins = "gpio59";
+ function = "qpic_pad6";
+ bias-disable;
+ };
+
+ mux_9 {
+ pins = "gpio60";
+ function = "qpic_pad7";
+ bias-disable;
+ };
+
+ mux_10 {
+ pins = "gpio68";
+ function = "qpic_pad8";
+ bias-disable;
+ };
+
+ pullups {
+ pins = "gpio52", "gpio53", "gpio58",
+ "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
@ -96,13 +35,14 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
+ };
};
blsp_dma: dma@7884000 {
@@ -159,5 +239,15 @@
@@ -159,5 +179,15 @@
watchdog@b017000 {
status = "ok";
};
@ -120,7 +60,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
};
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -586,5 +586,43 @@
@@ -609,5 +609,43 @@
"legacy";
status = "disabled";
};

44
target/linux/ipq806x/patches-4.9/864-00-v3-1-2-dts-ipq4019-Fix-pinctrl-node-name.patch
View File

@ -1,44 +0,0 @@
From patchwork Mon Jul 3 07:47:12 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v3,1/2] dts: ipq4019: Fix pinctrl node name
From: Varadarajan Narayanan <varada@codeaurora.org>
X-Patchwork-Id: 9822099
Message-Id: <1499068033-24000-2-git-send-email-varada@codeaurora.org>
To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org,
mark.rutland@arm.com, linux@armlinux.org.uk,
linux-arm-msm@vger.kernel.org,
linux-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Varadarajan Narayanan <varada@codeaurora.org>
Date: Mon, 3 Jul 2017 13:17:12 +0530
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -40,7 +40,7 @@
clock-frequency = <48000000>;
};
- pinctrl@0x01000000 {
+ pinctrl@1000000 {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -155,7 +155,7 @@
reg = <0x1800000 0x60000>;
};
- tlmm: pinctrl@0x01000000 {
+ tlmm: pinctrl@1000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x01000000 0x300000>;
gpio-controller;

78
target/linux/ipq806x/patches-4.9/864-00-v3-2-2-dts-ipq4019-Move-xo-and-timer-nodes-to-SoC-dtsi.patch
View File

@ -1,78 +0,0 @@
From patchwork Mon Jul 3 07:47:13 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v3,2/2] dts: ipq4019: Move xo and timer nodes to SoC dtsi
From: Varadarajan Narayanan <varada@codeaurora.org>
X-Patchwork-Id: 9822107
Message-Id: <1499068033-24000-3-git-send-email-varada@codeaurora.org>
To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org,
mark.rutland@arm.com, linux@armlinux.org.uk,
linux-arm-msm@vger.kernel.org,
linux-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Varadarajan Narayanan <varada@codeaurora.org>
Date: Mon, 3 Jul 2017 13:17:13 +0530
The node for xo and timer belong to the SoC DTS file.
Else, new board DT files may not inherit these nodes.
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 19 -------------------
arch/arm/boot/dts/qcom-ipq4019.dtsi | 15 +++++++++++++++
2 files changed, 15 insertions(+), 19 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,26 +20,7 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
- clocks {
- xo: xo {
- compatible = "fixed-clock";
- clock-frequency = <48000000>;
- #clock-cells = <0>;
- };
- };
-
soc {
-
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <1 2 0xf08>,
- <1 3 0xf08>,
- <1 4 0xf08>,
- <1 1 0xf08>;
- clock-frequency = <48000000>;
- };
-
pinctrl@1000000 {
serial_pins: serial_pinmux {
mux {
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -132,6 +132,21 @@
clock-frequency = <32768>;
#clock-cells = <0>;
};
+
+ xo: xo {
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 2 0xf08>,
+ <1 3 0xf08>,
+ <1 4 0xf08>,
+ <1 1 0xf08>;
+ clock-frequency = <48000000>;
};
soc {

11
target/linux/ipq806x/patches-4.9/864-01-dts-ipq4019-ap-dk04-fix-pinctrl-node-name.patch
View File

@ -1,11 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -38,7 +38,7 @@
clock-frequency = <48000000>;
};
- pinctrl@0x01000000 {
+ pinctrl@1000000 {
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";

27
target/linux/ipq806x/patches-4.9/864-02-dts-ipq4019-ap-dk04-remove-xo-and-timer-nodes.patch
View File

@ -1,27 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -20,24 +20,7 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
compatible = "qcom,ipq4019";
- clocks {
- xo: xo {
- compatible = "fixed-clock";
- clock-frequency = <48000000>;
- #clock-cells = <0>;
- };
- };
-
soc {
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <1 2 0xf08>,
- <1 3 0xf08>,
- <1 4 0xf08>,
- <1 1 0xf08>;
- clock-frequency = <48000000>;
- };
-
pinctrl@1000000 {
serial_0_pins: serial_pinmux {
mux {

42
target/linux/ipq806x/patches-4.9/864-03-dts-ipq4019-ap-dk01-add-tcsr-config-to-dtsi.patch
View File

@ -1,42 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -15,12 +15,39 @@
*/
#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
soc {
+ tcsr@194b000 {
+ /* select hostmode */
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "ok";
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
pinctrl@1000000 {
serial_pins: serial_pinmux {
mux {

32
target/linux/ipq806x/patches-4.9/864-04-dts-ipq4019-ap-dk01-add-network-nodes-to-dtsi.patch
View File

@ -1,32 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -136,5 +136,29 @@
usb2: usb2@60f8800 {
status = "ok";
};
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+
+ wifi@a000000 {
+ status = "okay";
+ };
+
+ wifi@a800000 {
+ status = "okay";
+ };
};
};

17
target/linux/ipq806x/patches-4.9/864-05-dts-ipq4019-ap-dk01-remove-spi-chip-node-from-dtsi.patch
View File

@ -1,17 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -89,14 +89,6 @@
pinctrl-names = "default";
status = "ok";
cs-gpios = <&tlmm 54 0>;
-
- mx25l25635e@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "mx25l25635e";
- spi-max-frequency = <24000000>;
- };
};
serial@78af000 {

13
target/linux/ipq806x/patches-4.9/864-06-dts-ipq4019-fix-max-cpu-speed.patch
View File

@ -1,13 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -108,8 +108,8 @@
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <256000>;
};
- opp@666000000 {
- opp-hz = /bits/ 64 <666000000>;
+ opp@716800000 {
+ opp-hz = /bits/ 64 <716800000>;
clock-latency-ns = <256000>;
};
};

115
target/linux/ipq806x/patches-4.9/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch
View File

@ -1,115 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -19,4 +19,112 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges;
+
+ apps_bl@87000000 {
+ reg = <0x87000000 0x400000>;
+ no-map;
+ };
+
+ sbl@87400000 {
+ reg = <0x87400000 0x100000>;
+ no-map;
+ };
+
+ cnss_debug@87500000 {
+ reg = <0x87500000 0x600000>;
+ no-map;
+ };
+
+ cpu_context_dump@87b00000 {
+ reg = <0x87b00000 0x080000>;
+ no-map;
+ };
+
+ tz_apps@87b80000 {
+ reg = <0x87b80000 0x280000>;
+ no-map;
+ };
+
+ smem@87e00000 {
+ reg = <0x87e00000 0x080000>;
+ no-map;
+ };
+
+ tz@87e80000 {
+ reg = <0x87e80000 0x180000>;
+ no-map;
+ };
+ };
+};
+
+&spi_0 {
+ mx25l25635f@0 {
+ compatible = "mx25l25635f", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ SBL1@0 {
+ label = "SBL1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+ MIBIB@40000 {
+ label = "MIBIB";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+ QSEE@60000 {
+ label = "QSEE";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+ CDT@c0000 {
+ label = "CDT";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+ DDRPARAMS@d0000 {
+ label = "DDRPARAMS";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+ APPSBLENV@e0000 {
+ label = "APPSBLENV";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+ APPSBL@f0000 {
+ label = "APPSBL";
+ reg = <0xf0000 0x80000>;
+ read-only;
+ };
+ ART@170000 {
+ label = "ART";
+ reg = <0x170000 0x10000>;
+ read-only;
+ };
+ kernel@180000 {
+ label = "kernel";
+ reg = <0x180000 0x400000>;
+ };
+ rootfs@580000 {
+ label = "rootfs";
+ reg = <0x580000 0x1600000>;
+ };
+ firmware@180000 {
+ label = "firmware";
+ reg = <0x180000 0x1a00000>;
+ };
+ };
};

10
target/linux/ipq806x/patches-4.9/864-08-dts-ipq4019-ap-dk01.1-c1-add-compatible-string.patch
View File

@ -1,10 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -18,6 +18,7 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1", "qcom,ipq4019";
memory {
device_type = "memory";