diff --git a/target/linux/rockchip/armv8/config-5.10 b/target/linux/rockchip/armv8/config-5.10 index 80230a722b..ebb5ed3a3a 100644 --- a/target/linux/rockchip/armv8/config-5.10 +++ b/target/linux/rockchip/armv8/config-5.10 @@ -165,12 +165,19 @@ CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRCT10DIF=y +# CONFIG_CRYPTO_DEV_ROCKCHIP is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEVFREQ_GOV_PASSIVE is not set @@ -274,6 +281,8 @@ CONFIG_HUGETLB_PAGE=y CONFIG_HWMON=y CONFIG_HWSPINLOCK=y CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ROCKCHIP=y CONFIG_HZ=250 CONFIG_HZ_250=y CONFIG_I2C=y diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index c6aacf5e34..a7b4389130 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -18,7 +18,7 @@ define Device/friendlyarm_nanopi-r4s SOC := rk3399 UBOOT_DEVICE_NAME := nanopi-r4s-rk3399 IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-img | gzip | append-metadata - DEVICE_PACKAGES := kmod-r8168 + DEVICE_PACKAGES := kmod-r8169 endef TARGET_DEVICES += friendlyarm_nanopi-r4s diff --git a/target/linux/rockchip/patches-5.10/002-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/rockchip/patches-5.10/002-net-usb-r8152-add-LED-configuration-from-OF.patch index 53b6413cf3..e1cf2a2e7b 100644 --- a/target/linux/rockchip/patches-5.10/002-net-usb-r8152-add-LED-configuration-from-OF.patch +++ b/target/linux/rockchip/patches-5.10/002-net-usb-r8152-add-LED-configuration-from-OF.patch @@ -22,7 +22,7 @@ Signed-off-by: David Bauer #include #include #include -@@ -4363,6 +4364,22 @@ static void rtl_tally_reset(struct r8152 +@@ -5328,6 +5329,22 @@ static void rtl_tally_reset(struct r8152 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); } @@ -36,7 +36,7 @@ Signed-off-by: David Bauer + + if (ret) + return ret; -+ ++ + ocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, led_data); + + return 0; @@ -45,7 +45,7 @@ Signed-off-by: David Bauer static void r8152b_init(struct r8152 *tp) { u32 ocp_data; -@@ -4404,6 +4421,8 @@ static void r8152b_init(struct r8152 *tp +@@ -5369,6 +5386,8 @@ static void r8152b_init(struct r8152 *tp ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); @@ -54,7 +54,7 @@ Signed-off-by: David Bauer } static void r8153_init(struct r8152 *tp) -@@ -4533,6 +4552,8 @@ static void r8153_init(struct r8152 *tp) +@@ -5509,6 +5528,8 @@ static void r8153_init(struct r8152 *tp) tp->coalesce = COALESCE_SLOW; break; } @@ -63,7 +63,7 @@ Signed-off-by: David Bauer } static void r8153b_init(struct r8152 *tp) -@@ -4609,6 +4630,8 @@ static void r8153b_init(struct r8152 *tp +@@ -5595,6 +5616,8 @@ static void r8153b_init(struct r8152 *tp rtl_tally_reset(tp); tp->coalesce = 15000; /* 15 us */ diff --git a/target/linux/rockchip/patches-5.10/005-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch b/target/linux/rockchip/patches-5.10/005-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch new file mode 100644 index 0000000000..897a42fea2 --- /dev/null +++ b/target/linux/rockchip/patches-5.10/005-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch @@ -0,0 +1,25 @@ +From bc6c96d850419e71dbc9b0094ccc9b668ba9be43 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Mon, 28 Sep 2020 22:54:52 +0200 +Subject: [PATCH] rockchip: rk3328: add compatible to NanoPi R2S ethernet PHY + +This adds the compatible property to the NanoPi R2S ethernet PHY node. +Otherwise, the PHY might not be probed, as the PHY ID reads all 0xff +when it is still in reset. + +Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -134,6 +134,8 @@ + #size-cells = <0>; + + rtl8211e: ethernet-phy@1 { ++ compatible = "ethernet-phy-id001c.c915", ++ "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-0 = <ð_phy_reset_pin>; + pinctrl-names = "default"; diff --git a/target/linux/rockchip/patches-5.10/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.10/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch index 20d18597db..243c1ac78d 100644 --- a/target/linux/rockchip/patches-5.10/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch +++ b/target/linux/rockchip/patches-5.10/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch @@ -32,7 +32,7 @@ Signed-off-by: David Bauer leds { compatible = "gpio-leds"; pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -@@ -267,6 +279,12 @@ +@@ -269,6 +281,12 @@ }; }; }; @@ -45,7 +45,7 @@ Signed-off-by: David Bauer }; &io_domains { -@@ -373,3 +391,12 @@ +@@ -375,3 +393,12 @@ &usb_host0_ohci { status = "okay"; }; diff --git a/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch index 473c265016..e318f3136f 100644 --- a/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch +++ b/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch @@ -14,7 +14,7 @@ Signed-off-by: David Bauer --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -399,4 +399,11 @@ +@@ -401,4 +401,11 @@ &usbdrd_dwc3 { dr_mode = "host"; status = "okay"; diff --git a/target/linux/rockchip/patches-5.10/105-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-5.10/105-mmc-core-set-initial-signal-voltage-on-power-off.patch new file mode 100644 index 0000000000..2a0f8d9bd0 --- /dev/null +++ b/target/linux/rockchip/patches-5.10/105-mmc-core-set-initial-signal-voltage-on-power-off.patch @@ -0,0 +1,35 @@ +From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Wed, 20 Feb 2019 07:38:34 +0000 +Subject: [PATCH] mmc: core: set initial signal voltage on power off + +Some boards have SD card connectors where the power rail cannot be switched +off by the driver. If the card has not been power cycled, it may still be +using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling +will fail to boot from a UHS card that continue to use 1.8V signaling. + +Set initial signal voltage in mmc_power_off() to allow re-boot to function. + +This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288), +same issue have been seen on some Rockchip RK3399 boards. + +I am sending this as a RFC because I have no insights into SD/MMC subsystem, +this change fix a re-boot issue on my boards and does not break emmc/sdio. +Is this an acceptable workaround? Any advice is appreciated. + +Signed-off-by: Jonas Karlman +--- + drivers/mmc/core/core.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/mmc/core/core.c ++++ b/drivers/mmc/core/core.c +@@ -1351,6 +1351,8 @@ void mmc_power_off(struct mmc_host *host + + mmc_pwrseq_power_off(host); + ++ mmc_set_initial_signal_voltage(host); ++ + host->ios.clock = 0; + host->ios.vdd = 0; + diff --git a/target/linux/rockchip/patches-5.10/200-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch b/target/linux/rockchip/patches-5.10/200-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 0000000000..69c880db9f --- /dev/null +++ b/target/linux/rockchip/patches-5.10/200-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,218 @@ +From 11c2b38cf0a04b0edb3eabae24fb1484489725e2 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Fri, 8 Jan 2021 07:12:30 +0000 +Subject: [PATCH] rockchip: rk3399: Add support for FriendlyARM NanoPi R4S + +This adds support for the NanoPi R4S from FriendlyArm. + +Rockchip RK3399 SoC +1GB DDR3 or 4GB LPDDR4 RAM +Gigabit Ethernet (WAN) +Gigabit Ethernet (PCIe) (LAN) +USB 3.0 Host Port x 2 +MicroSD slot +Reset button +WAN - LAN - SYS LED + +Signed-off-by: Tianling Shen +Co-authored-by: Jensen Huang +Signed-off-by: Jensen Huang +Co-authored-by: Marty Jones +Signed-off-by: Marty Jones +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 178 ++++++++++++++++++ + 2 files changed, 179 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-le + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +@@ -0,0 +1,178 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 Jensen Huang ++ * Copyright (c) 2020 Marty Jones ++ * Copyright (c) 2020 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3399-nanopi4.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R4S"; ++ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; ++ ++ aliases { ++ led-boot = &sys_led; ++ led-failsafe = &sys_led; ++ led-running = &sys_led; ++ led-upgrade = &sys_led; ++ }; ++ ++ /delete-node/ gpio-leds; ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; ++ pinctrl-names = "default"; ++ ++ lan_led: led-0 { ++ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r4s:green:lan"; ++ }; ++ ++ sys_led: led-1 { ++ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r4s:red:sys"; ++ }; ++ ++ wan_led: led-2 { ++ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r4s:green:wan"; ++ }; ++ }; ++ ++ /delete-node/ gpio-keys; ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&reset_button_pin>; ++ ++ reset { ++ debounce-interval = <50>; ++ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ label = "reset"; ++ linux,code = ; ++ }; ++ }; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ /* ++ * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels ++ * work out to 0, ~1200, ~3000, and 5000RPM respectively. ++ */ ++ cooling-levels = <0 12 18 255>; ++ #cooling-cells = <2>; ++ fan-supply = <&vdd_5v>; ++ pwms = <&pwm1 0 50000 0>; ++ }; ++}; ++ ++&cpu_thermal { ++ trips { ++ cpu_warm: cpu_warm { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_hot: cpu_hot { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map2 { ++ trip = <&cpu_warm>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map3 { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ ++&emmc_phy { ++ status = "disabled"; ++}; ++ ++&fusb0 { ++ status = "disabled"; ++}; ++ ++&pcie0 { ++ max-link-speed = <1>; ++ num-lanes = <1>; ++ vpcie3v3-supply = <&vcc3v3_sys>; ++ ++ pcie@0 { ++ reg = <0x00000000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ }; ++}; ++ ++&pinctrl { ++ /delete-node/ gpio-leds; ++ gpio-leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ /delete-node/ rockchip-key; ++ rockchip-key { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&sdhci { ++ status = "disabled"; ++}; ++ ++&sdio0 { ++ status = "disabled"; ++}; ++ ++&sdmmc { ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++}; ++ ++&u2phy0_host { ++ phy-supply = <&vdd_5v>; ++}; ++ ++&u2phy1_host { ++ status = "disabled"; ++}; ++ ++&usbdrd_dwc3_0 { ++ dr_mode = "host"; ++}; ++ ++&vcc3v3_sys { ++ vin-supply = <&vcc5v0_sys>; ++}; diff --git a/target/linux/rockchip/patches-5.10/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch b/target/linux/rockchip/patches-5.10/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch new file mode 100644 index 0000000000..28798047fd --- /dev/null +++ b/target/linux/rockchip/patches-5.10/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch @@ -0,0 +1,22 @@ +From 3b7eb946b1d640d684a921e53e1e50985ab7eb89 Mon Sep 17 00:00:00 2001 +From: QiuSimons <45143996+QiuSimons@users.noreply.github.com> +Date: Tue, 4 Aug 2020 20:17:53 +0800 +Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s + +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4 ++++ + 1 files changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -165,6 +165,10 @@ + }; + }; + ++&i2c0 { ++ status = "okay"; ++}; ++ + &i2c1 { + status = "okay"; + diff --git a/target/linux/rockchip/patches-5.10/801-char-add-support-for-rockchip-hardware-random-number.patch b/target/linux/rockchip/patches-5.10/801-char-add-support-for-rockchip-hardware-random-number.patch new file mode 100644 index 0000000000..16ca6279e7 --- /dev/null +++ b/target/linux/rockchip/patches-5.10/801-char-add-support-for-rockchip-hardware-random-number.patch @@ -0,0 +1,45 @@ +From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001 +From: wevsty +Date: Mon, 24 Aug 2020 02:27:11 +0800 +Subject: [PATCH] char: add support for rockchip hardware random number + generator + +This patch provides hardware random number generator support for all rockchip SOC. + +rockchip-rng.c from https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/char/hw_random/rockchip-rng.c + +Signed-off-by: wevsty +--- + +--- a/drivers/char/hw_random/Kconfig ++++ b/drivers/char/hw_random/Kconfig +@@ -398,6 +398,19 @@ config HW_RANDOM_STM32 + + If unsure, say N. + ++config HW_RANDOM_ROCKCHIP ++ tristate "Rockchip Random Number Generator support" ++ depends on ARCH_ROCKCHIP ++ default HW_RANDOM ++ help ++ This driver provides kernel-side support for the Random Number ++ Generator hardware found on Rockchip cpus. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called rockchip-rng. ++ ++ If unsure, say Y. ++ + config HW_RANDOM_PIC32 + tristate "Microchip PIC32 Random Number Generator support" + depends on HW_RANDOM && MACH_PIC32 +--- a/drivers/char/hw_random/Makefile ++++ b/drivers/char/hw_random/Makefile +@@ -36,6 +36,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += + obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o + obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o + obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o ++obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o + obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o + obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o + obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o diff --git a/target/linux/rockchip/patches-5.10/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-5.10/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch new file mode 100644 index 0000000000..1de560e33f --- /dev/null +++ b/target/linux/rockchip/patches-5.10/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch @@ -0,0 +1,50 @@ +From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001 +From: wevsty +Date: Mon, 24 Aug 2020 02:27:11 +0800 +Subject: [PATCH] arm64: dts: rockchip: add hardware random number generator + for RK3328 and RK3399 + +Adding Hardware Random Number Generator Resources to the RK3328 and RK3399. + +Signed-off-by: wevsty +--- + +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -297,6 +297,17 @@ + status = "disabled"; + }; + ++ rng: rng@ff060000 { ++ compatible = "rockchip,cryptov1-rng"; ++ reg = <0x0 0xff060000 0x0 0x4000>; ++ ++ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>; ++ clock-names = "clk_crypto", "hclk_crypto"; ++ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>; ++ assigned-clock-rates = <150000000>, <100000000>; ++ status = "disabled"; ++ }; ++ + grf: syscon@ff100000 { + compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff100000 0x0 0x1000>; +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1906,6 +1906,16 @@ + }; + }; + ++ rng: rng@ff8b8000 { ++ compatible = "rockchip,cryptov1-rng"; ++ reg = <0x0 0xff8b8000 0x0 0x1000>; ++ clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; ++ clock-names = "clk_crypto", "hclk_crypto"; ++ assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; ++ assigned-clock-rates = <150000000>, <100000000>; ++ status = "okay"; ++ }; ++ + gpu: gpu@ff9a0000 { + compatible = "rockchip,rk3399-mali", "arm,mali-t860"; + reg = <0x0 0xff9a0000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-5.10/911-kernel-dma-adjust-default-coherent_pool-to-2MiB.patch b/target/linux/rockchip/patches-5.10/911-kernel-dma-adjust-default-coherent_pool-to-2MiB.patch new file mode 100644 index 0000000000..f589ce2a7b --- /dev/null +++ b/target/linux/rockchip/patches-5.10/911-kernel-dma-adjust-default-coherent_pool-to-2MiB.patch @@ -0,0 +1,28 @@ +From 16bdf3e76fec6ddb44f1fcf221139fb39d225031 Mon Sep 17 00:00:00 2001 +From: Igor Pecovnik +Date: Sat, 2 Jan 2021 05:23:55 +0000 +Subject: [PATCH] kernel: dma: adjust default coherent_pool to 2MiB + +--- + kernel/dma/pool.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +--- a/kernel/dma/pool.c ++++ b/kernel/dma/pool.c +@@ -192,13 +192,11 @@ static int __init dma_atomic_pool_init(v + int ret = 0; + + /* +- * If coherent_pool was not used on the command line, default the pool +- * sizes to 128KB per 1GB of memory, min 128KB, max MAX_ORDER-1. ++ * Always use 2MiB as default pool size. ++ * See: https://forum.armbian.com/topic/4811-uas-mainline-kernel-coherent-pool-memory-size/ + */ + if (!atomic_pool_size) { +- unsigned long pages = totalram_pages() / (SZ_1G / SZ_128K); +- pages = min_t(unsigned long, pages, MAX_ORDER_NR_PAGES); +- atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, SZ_128K); ++ atomic_pool_size = SZ_2M; + } + INIT_WORK(&atomic_pool_work, atomic_pool_work_fn); + diff --git a/target/linux/rockchip/patches-5.10/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch b/target/linux/rockchip/patches-5.10/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch new file mode 100644 index 0000000000..c85da5fb07 --- /dev/null +++ b/target/linux/rockchip/patches-5.10/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch @@ -0,0 +1,44 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Leonidas P. Papadakos +Date: Fri, 1 Mar 2019 21:55:53 +0200 +Subject: [PATCH v2] arm64: dts: rockchip: add more cpu operating points for + RK3328 + +This allows for greater max frequency on rk3328 boards, +increasing performance. + +It has been included in Armbian (a linux distibution for ARM boards) +for a while now without any reported issues + +https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1392mhz-opp.patch +https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1512mhz-opp.patch + +Signed-off-by: Leonidas P. Papadakos +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 15 +++++++++++++++ + 1 files changed, 15 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -140,6 +140,21 @@ + opp-microvolt = <1300000>; + clock-latency-ns = <40000>; + }; ++ opp-1392000000 { ++ opp-hz = /bits/ 64 <1392000000>; ++ opp-microvolt = <1350000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1512000000 { ++ opp-hz = /bits/ 64 <1512000000>; ++ opp-microvolt = <1400000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1450000>; ++ clock-latency-ns = <40000>; ++ }; + }; + + amba: bus { diff --git a/target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch b/target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch new file mode 100644 index 0000000000..9d393c5771 --- /dev/null +++ b/target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch @@ -0,0 +1,186 @@ +From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 19 Dec 2020 12:42:27 +0000 +Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz for NanoPi4 devices + +It's stable enough to overclock cpu frequency to 2.2/1.8 GHz, +and for better performance. + +Signed-off-by: Tianling Shen +Co-authored-by: gzelvis +--- + .../boot/dts/rockchip/rk3399-nanopi4-opp.dtsi | 156 ++++++++++++++++++ + .../boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +- + 2 files changed, 157 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi +@@ -0,0 +1,156 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd ++ * ++ * Copyright (c) 2020 Tianling Shen ++ * Copyright (c) 2020 gzelvis ++ */ ++ ++/ { ++ cluster0_opp: opp-table0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <800000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <925000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1000000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <1150000>; ++ }; ++ opp06 { ++ opp-hz = /bits/ 64 <1512000000>; ++ opp-microvolt = <1200000>; ++ }; ++ opp07 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1250000>; ++ }; ++ opp08 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <1300000>; ++ }; ++ }; ++ ++ cluster1_opp: opp-table1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <800000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <825000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <875000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <950000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <1025000>; ++ }; ++ opp06 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1100000>; ++ }; ++ opp07 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <1250000>; ++ }; ++ opp08 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <1350000>; ++ }; ++ opp09 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <1400000>; ++ }; ++ }; ++ ++ gpu_opp_table: opp-table2 { ++ compatible = "operating-points-v2"; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <297000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <825000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <875000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <925000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <1100000>; ++ }; ++ }; ++}; ++ ++&cpu_l0 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l1 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l2 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l3 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_b0 { ++ operating-points-v2 = <&cluster1_opp>; ++}; ++ ++&cpu_b1 { ++ operating-points-v2 = <&cluster1_opp>; ++}; ++ ++&gpu { ++ operating-points-v2 = <&gpu_opp_table>; ++}; +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +@@ -14,7 +14,7 @@ + /dts-v1/; + #include + #include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" ++#include "rk3399-nanopi4-opp.dtsi" + + / { + chosen {