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Merge Official Source

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2021-10-04 09:33:43 +08:00
commit 9d8fe8614b
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
431 changed files with 1027 additions and 132523 deletions
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4
include/kernel-version.mk
View File

@ -6,10 +6,10 @@ ifdef CONFIG_TESTING_KERNEL
KERNEL_PATCHVER:=$(KERNEL_TESTING_PATCHVER)
endif
LINUX_VERSION-5.4 = .145
LINUX_VERSION-5.4 = .150
LINUX_VERSION-5.10 = .70
LINUX_KERNEL_HASH-5.4.145 = 5cf7782ec2e91417edf0d5e6555da6d556962c8985e33ba9e7dadba5cbdc68f9
LINUX_KERNEL_HASH-5.4.150 = f424a9bbb05007f04c17f96a2e4f041a8001554a9060d2c291606e8a97c62aa2
LINUX_KERNEL_HASH-5.10.70 = 75736c33711d7f298889ee4981b18774882045323e5c46af9ad3b022082db232
remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))

4
include/prereq-build.mk
View File

@ -186,7 +186,9 @@ $(eval $(call SetupHostCommand,rsync,Please install 'rsync', \
rsync --version </dev/null))
$(eval $(call SetupHostCommand,which,Please install 'which', \
which which | grep which))
/usr/bin/which which, \
/bin/which which, \
which which))
$(STAGING_DIR_HOST)/bin/mkhash: $(SCRIPT_DIR)/mkhash.c
mkdir -p $(dir $@)

2
package/boot/uboot-at91/Makefile
View File

@ -8,7 +8,7 @@
include $(TOPDIR)/rules.mk
PKG_VERSION:=linux4sam-2020.04
PKG_RELEASE:=2
PKG_RELEASE:=$(AUTORELEASE)
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/linux4sam/u-boot-at91.git

3
package/boot/uboot-envtools/files/mvebu
View File

@ -33,7 +33,8 @@ globalscale,espressobin|\
globalscale,espressobin-emmc|\
globalscale,espressobin-ultra|\
globalscale,espressobin-v7|\
globalscale,espressobin-v7-emmc)
globalscale,espressobin-v7-emmc|\
globalscale,mochabin)
idx="$(find_mtd_index u-boot-env)"
if [ -n "$idx" ]; then
ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x10000" "1"

2
package/boot/uboot-fritz4040/Makefile
View File

@ -14,7 +14,7 @@ PKG_SOURCE_VERSION:=f92be9d783b1210c020d5d6129e210a94bb7e290
PKG_SOURCE_DATE:=2019-10-19
PKG_MIRROR_HASH:=e40a7f624b1758b276f81c765ef1da568c595b8bd54568b9cceca7d170ebc612
PKG_RELEASE:=1
PKG_RELEASE:=$(AUTORELEASE)
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk

2
package/boot/uboot-imx6/Makefile
View File

@ -8,7 +8,7 @@
include $(TOPDIR)/rules.mk
PKG_VERSION:=2020.04
PKG_RELEASE:=1
PKG_RELEASE:=$(AUTORELEASE)
PKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372

2
package/boot/uboot-lantiq/Makefile
View File

@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=u-boot
PKG_VERSION:=2013.10
PKG_RELEASE:=1
PKG_RELEASE:=$(AUTORELEASE)
PKG_HASH:=0d71e62beb952b41ebafb20a7ee4df2f960db64c31b054721ceb79ff14014c55

172
package/boot/uboot-lantiq/patches/101-fix-crypt-header-clash.patch Normal file
View File

@ -0,0 +1,172 @@
Fix header clash with system /usr/include/sha1.h and sha256.h when libmd
is installed.
Backport of u-boot commit "includes: move openssl headers to include/u-boot"
https://github.com/u-boot/u-boot/commit/2b9912e6a7df7b1f60beb7942bd0e6fa5f9d0167
--- a/board/gdsys/p1022/controlcenterd-id.c
+++ b/board/gdsys/p1022/controlcenterd-id.c
@@ -30,7 +30,7 @@
#include <i2c.h>
#include <mmc.h>
#include <tpm.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
#include <pca9698.h>
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -13,7 +13,7 @@
#include <asm/processor.h>
#include <spd_sdram.h>
#include <status_led.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include <asm/io.h>
#include <net.h>
#include <ata.h>
--- a/common/cmd_sha1sum.c
+++ b/common/cmd_sha1sum.c
@@ -11,7 +11,7 @@
#include <common.h>
#include <command.h>
#include <hash.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
--- a/common/hash.c
+++ b/common/hash.c
@@ -14,8 +14,8 @@
#include <command.h>
#include <hw_sha.h>
#include <hash.h>
-#include <sha1.h>
-#include <sha256.h>
+#include <u-boot/sha1.h>
+#include <u-boot/sha256.h>
#include <asm/io.h>
#include <asm/errno.h>
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR;
#endif /* !USE_HOSTCC*/
#include <bootstage.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include <u-boot/crc.h>
#include <u-boot/md5.h>
--- a/common/image.c
+++ b/common/image.c
@@ -34,7 +34,7 @@
#endif
#include <u-boot/md5.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include <asm/errno.h>
#include <asm/io.h>
--- a/drivers/crypto/ace_sha.c
+++ b/drivers/crypto/ace_sha.c
@@ -5,8 +5,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <sha256.h>
-#include <sha1.h>
+#include <u-boot/sha256.h>
+#include <u-boot/sha1.h>
#include <asm/errno.h>
#include "ace_sha.h"
--- /dev/null
+++ b/include/u-boot/sha1.h
@@ -0,0 +1 @@
+#include "../sha1.h"
--- /dev/null
+++ b/include/u-boot/sha256.h
@@ -0,0 +1 @@
+#include "../sha256.h"
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <fdtdec.h>
#include <rsa.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include <asm/byteorder.h>
#include <asm/errno.h>
#include <asm/unaligned.h>
--- a/lib/sha1.c
+++ b/lib/sha1.c
@@ -36,7 +36,7 @@
#include <string.h>
#endif /* USE_HOSTCC */
#include <watchdog.h>
-#include "sha1.h"
+#include <u-boot/sha1.h>
/*
* 32-bit integer manipulation macros (big endian)
--- a/lib/sha256.c
+++ b/lib/sha256.c
@@ -11,7 +11,7 @@
#endif /* USE_HOSTCC */
#include <watchdog.h>
#include <linux/string.h>
-#include <sha256.h>
+#include <u-boot/sha256.h>
/*
* 32-bit integer manipulation macros (big endian)
--- a/lib/tpm.c
+++ b/lib/tpm.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <stdarg.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include <tpm.h>
#include <asm/unaligned.h>
--- a/tools/imls/imls.c
+++ b/tools/imls/imls.c
@@ -24,7 +24,7 @@
#include <mtd/mtd-user.h>
#endif
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <image.h>
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -18,7 +18,7 @@
#include <sys/stat.h>
#include <time.h>
#include <unistd.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include "fdt_host.h"
#undef MKIMAGE_DEBUG
--- a/tools/ubsha1.c
+++ b/tools/ubsha1.c
@@ -13,7 +13,7 @@
#include <errno.h>
#include <string.h>
#include <sys/stat.h>
-#include "sha1.h"
+#include <u-boot/sha1.h>
int main (int argc, char **argv)
{

2
package/boot/uboot-mxs/Makefile
View File

@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2020.04
PKG_RELEASE:=1
PKG_RELEASE:=$(AUTORELEASE)
PKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372

2
package/boot/uboot-omap/Makefile
View File

@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2020.04
PKG_RELEASE:=1
PKG_RELEASE:=$(AUTORELEASE)
PKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372

2
package/boot/uboot-oxnas/Makefile
View File

@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2014.10
PKG_RELEASE:=1
PKG_RELEASE:=$(AUTORELEASE)
PKG_HASH:=d3b132a7a9b3f3182b7aad71c2dfbd4fc15bea83e12c76134eb3ffefc07d1c71

2
package/boot/uboot-ramips/Makefile
View File

@ -4,7 +4,7 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2020.04
PKG_RELEASE:=1
PKG_RELEASE:=$(AUTORELEASE)
PKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372

2
package/boot/uboot-rockchip/Makefile
View File

@ -6,7 +6,7 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2021.07
PKG_RELEASE:=1
PKG_RELEASE:=$(AUTORELEASE)
PKG_HASH:=312b7eeae44581d1362c3a3f02c28d806647756c82ba8c72241c7cdbe68ba77e

2
package/boot/uboot-tegra/Makefile
View File

@ -7,7 +7,7 @@
include $(TOPDIR)/rules.mk
PKG_VERSION := 2020.04
PKG_RELEASE := 1
PKG_RELEASE:=$(AUTORELEASE)
PKG_HASH := fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372

12
package/network/services/dnsmasq/files/dnsmasq.init
View File

@ -241,7 +241,7 @@ dhcp_subscrid_add() {
config_get subscriberid "$cfg" subscriberid
[ -n "$subscriberid" ] || return 0
xappend "--dhcp-subscrid=$networkid,$subscriberid"
xappend "--dhcp-subscrid=set:$networkid,$subscriberid"
config_get_bool force "$cfg" force 0
@ -257,7 +257,7 @@ dhcp_remoteid_add() {
config_get remoteid "$cfg" remoteid
[ -n "$remoteid" ] || return 0
xappend "--dhcp-remoteid=$networkid,$remoteid"
xappend "--dhcp-remoteid=set:$networkid,$remoteid"
config_get_bool force "$cfg" force 0
@ -274,7 +274,7 @@ dhcp_circuitid_add() {
config_get circuitid "$cfg" circuitid
[ -n "$circuitid" ] || return 0
xappend "--dhcp-circuitid=$networkid,$circuitid"
xappend "--dhcp-circuitid=set:$networkid,$circuitid"
config_get_bool force "$cfg" force 0
@ -290,7 +290,7 @@ dhcp_userclass_add() {
config_get userclass "$cfg" userclass
[ -n "$userclass" ] || return 0
xappend "--dhcp-userclass=$networkid,$userclass"
xappend "--dhcp-userclass=set:$networkid,$userclass"
config_get_bool force "$cfg" force 0
@ -307,7 +307,7 @@ dhcp_vendorclass_add() {
config_get vendorclass "$cfg" vendorclass
[ -n "$vendorclass" ] || return 0
xappend "--dhcp-vendorclass=$networkid,$vendorclass"
xappend "--dhcp-vendorclass=set:$networkid,$vendorclass"
config_get_bool force "$cfg" force 0
@ -323,7 +323,7 @@ dhcp_match_add() {
config_get match "$cfg" match
[ -n "$match" ] || return 0
xappend "--dhcp-match=$networkid,$match"
xappend "--dhcp-match=set:$networkid,$match"
config_get_bool force "$cfg" force 0

2
package/utils/bcm4908img/Makefile
View File

@ -3,7 +3,7 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=bcm4908img
PKG_RELEASE:=1
PKG_RELEASE:=3
PKG_FLAGS:=nonshared

45
package/utils/bcm4908img/src/bcm4908img.c
View File

@ -77,13 +77,14 @@ struct bcm4908img_tail {
* 4. padding ├─ firmware
* 5. rootfs ─┘
* 6. BCM4908 tail
* 7. (Optional) vendor tail
*/
struct bcm4908img_info {
size_t file_size;
size_t cferom_offset;
size_t bootfs_offset;
size_t padding_offset;
size_t rootfs_offset;
size_t tail_offset;
uint32_t crc32; /* Calculated checksum */
struct bcm4908img_tail tail;
};
@ -219,7 +220,7 @@ static int bcm4908img_calc_crc32(FILE *fp, struct bcm4908img_info *info) {
fseek(fp, info->cferom_offset, SEEK_SET);
info->crc32 = 0xffffffff;
length = info->file_size - info->cferom_offset - sizeof(struct bcm4908img_tail);
length = info->tail_offset - info->cferom_offset;
while (length && (bytes = fread(buf, 1, bcm4908img_min(sizeof(buf), length), fp)) > 0) {
info->crc32 = bcm4908img_crc32(info->crc32, buf, bytes);
length -= bytes;
@ -249,6 +250,16 @@ struct chk_header {
char board_id[0];
};
struct linksys_tail {
char magic[9];
uint8_t version[8];
char model[15];
uint32_t crc32;
uint8_t padding[9];
uint8_t signature[16];
uint8_t reserved[192];
};
static bool bcm4908img_is_all_ff(const void *buf, size_t length)
{
const uint8_t *in = buf;
@ -264,9 +275,11 @@ static bool bcm4908img_is_all_ff(const void *buf, size_t length)
static int bcm4908img_parse(FILE *fp, struct bcm4908img_info *info) {
struct bcm4908img_tail *tail = &info->tail;
struct linksys_tail *linksys;
struct chk_header *chk;
struct stat st;
uint8_t buf[1024];
size_t file_size;
uint16_t tmp16;
size_t length;
size_t bytes;
@ -281,7 +294,9 @@ static int bcm4908img_parse(FILE *fp, struct bcm4908img_info *info) {
fprintf(stderr, "Failed to fstat: %d\n", err);
return err;
}
info->file_size = st.st_size;
file_size = st.st_size;
info->tail_offset = file_size - sizeof(*tail);
/* Vendor formats */
@ -294,10 +309,20 @@ static int bcm4908img_parse(FILE *fp, struct bcm4908img_info *info) {
if (be32_to_cpu(chk->magic) == 0x2a23245e)
info->cferom_offset = be32_to_cpu(chk->header_len);
fseek(fp, -sizeof(buf), SEEK_END);
if (fread(buf, 1, sizeof(buf), fp) != sizeof(buf)) {
fprintf(stderr, "Failed to read file header\n");
return -EIO;
}
linksys = (void *)(buf + sizeof(buf) - sizeof(*linksys));
if (!memcmp(linksys->magic, ".LINKSYS.", sizeof(linksys->magic))) {
info->tail_offset -= sizeof(*linksys);
}
/* Offsets */
for (info->bootfs_offset = info->cferom_offset;
info->bootfs_offset < info->file_size;
info->bootfs_offset < info->tail_offset;
info->bootfs_offset += 0x20000) {
if (fseek(fp, info->bootfs_offset, SEEK_SET)) {
err = -errno;
@ -311,13 +336,13 @@ static int bcm4908img_parse(FILE *fp, struct bcm4908img_info *info) {
if (be16_to_cpu(tmp16) == 0x8519)
break;
}
if (info->bootfs_offset >= info->file_size) {
if (info->bootfs_offset >= info->tail_offset) {
fprintf(stderr, "Failed to find bootfs offset\n");
return -EPROTO;
}
for (info->rootfs_offset = info->bootfs_offset;
info->rootfs_offset < info->file_size;
info->rootfs_offset < info->tail_offset;
info->rootfs_offset += 0x20000) {
uint32_t *magic = (uint32_t *)&buf[0];
@ -340,7 +365,7 @@ static int bcm4908img_parse(FILE *fp, struct bcm4908img_info *info) {
if (be32_to_cpu(*magic) == UBI_EC_HDR_MAGIC)
break;
}
if (info->rootfs_offset >= info->file_size) {
if (info->rootfs_offset >= info->tail_offset) {
fprintf(stderr, "Failed to find rootfs offset\n");
return -EPROTO;
}
@ -351,7 +376,7 @@ static int bcm4908img_parse(FILE *fp, struct bcm4908img_info *info) {
fseek(fp, info->cferom_offset, SEEK_SET);
info->crc32 = 0xffffffff;
length = info->file_size - info->cferom_offset - sizeof(*tail);
length = info->tail_offset - info->cferom_offset;
while (length && (bytes = fread(buf, 1, bcm4908img_min(sizeof(buf), length), fp)) > 0) {
info->crc32 = bcm4908img_crc32(info->crc32, buf, bytes);
length -= bytes;
@ -617,10 +642,10 @@ static int bcm4908img_extract(int argc, char **argv) {
length = (info.padding_offset ? info.padding_offset : info.rootfs_offset) - offset;
} else if (!strcmp(type, "rootfs")) {
offset = info.rootfs_offset;
length = info.file_size - offset - sizeof(struct bcm4908img_tail);
length = info.tail_offset - offset;
} else if (!strcmp(type, "firmware")) {
offset = info.bootfs_offset;
length = info.file_size - offset - sizeof(struct bcm4908img_tail);
length = info.tail_offset - offset;
} else {
err = -EINVAL;
fprintf(stderr, "Unsupported extract type: %s\n", type);

73
target/linux/armvirt/32/config-5.4
View File

@ -1,73 +0,0 @@
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_VIRT=y
CONFIG_ARM=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_LPAE=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_ARM_PSCI=y
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_CACHE_L2X0=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_HAVE_SMP=y
CONFIG_HZ_FIXED=0
CONFIG_HZ_PERIODIC=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_NEON=y
CONFIG_NR_CPUS=4
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PERF_USE_VMALLOC=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SMP_ON_UP=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0

155
target/linux/armvirt/64/config-5.4
View File

@ -1,155 +0,0 @@
CONFIG_64BIT=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_CNP=y
CONFIG_ARM64_CONT_SHIFT=4
CONFIG_ARM64_CRYPTO=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PAN=y
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_SSBD=y
CONFIG_ARM64_SVE=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_UAO=y
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
CONFIG_ARM64_VHE=y
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_ATOMIC64_SELFTEST=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BLK_PM=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLKSRC_VERSATILE=y
CONFIG_CLK_SP810=y
CONFIG_CLK_VEXPRESS_OSC=y
CONFIG_COMMON_CLK_VERSATILE=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_PM=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CHACHA20_NEON=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SIMD=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DRM=y
CONFIG_DRM_BOCHS=y
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_PANEL=y
CONFIG_DRM_PANEL_BRIDGE=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_QXL=y
CONFIG_DRM_RCAR_WRITEBACK=y
CONFIG_DRM_TTM=y
CONFIG_DRM_VIRTIO_GPU=y
CONFIG_DRM_VRAM_HELPER=y
CONFIG_FB=y
CONFIG_FB_ARMCLCD=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_FRAME_POINTER=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_HDMI=y
CONFIG_HOLES_IN_ZONE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_PLATFORM is not set
CONFIG_MFD_CORE=y
CONFIG_MFD_SYSCON=y
CONFIG_MFD_VEXPRESS_SYSREG=y
CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=64
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_VEXPRESS=y
CONFIG_POWER_SUPPLY=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_SMC91X=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SYNC_FILE=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_VEXPRESS_CONFIG=y
CONFIG_VEXPRESS_SYSCFG=y
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_VMAP_STACK=y
CONFIG_ZONE_DMA32=y

3
target/linux/armvirt/Makefile
View File

@ -9,8 +9,7 @@ BOARDNAME:=QEMU ARM Virtual Machine
FEATURES:=fpu pci rtc usb
FEATURES+=cpiogz ext4 ramdisk squashfs targz
KERNEL_PATCHVER:=5.4
KERNEL_TESTING_PATCHVER:=5.10
KERNEL_PATCHVER:=5.10
include $(INCLUDE_DIR)/target.mk

157
target/linux/armvirt/config-5.4
View File

@ -1,157 +0,0 @@
CONFIG_9P_FS=y
# CONFIG_9P_FS_POSIX_ACL is not set
# CONFIG_9P_FS_SECURITY is not set
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
CONFIG_ARM_PSCI_FW=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_CPU_RMAP=y
CONFIG_CRC16=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_RNG2=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DMADEVICES=y
CONFIG_DMA_REMAP=y
CONFIG_DTC=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EXT4_FS=y
CONFIG_F2FS_FS=y
CONFIG_FAILOVER=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_PL061=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HVC_DRIVER=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_MEMFD_CREATE=y
CONFIG_MEMORY_BALLOON=y
CONFIG_MIGRATION=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NET_9P=y
# CONFIG_NET_9P_DEBUG is not set
CONFIG_NET_9P_VIRTIO=y
CONFIG_NET_FAILOVER=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NLS=y
CONFIG_NVMEM=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_NET=y
CONFIG_PADATA=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_RATIONAL=y
CONFIG_REFCOUNT_FULL=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PL031=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCSI=y
CONFIG_SCSI_VIRTIO=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SPARSE_IRQ=y
CONFIG_SRCU=y
CONFIG_SWIOTLB=y
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_USB_SUPPORT=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_BLK=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_XPS=y

8
target/linux/ath79/image/Makefile
View File

@ -84,6 +84,14 @@ define Device/Default
append-rootfs | pad-rootfs | check-size | append-metadata
endef
define Device/loader-okli-uimage
LOADER_TYPE := bin
COMPILE := loader-$(1).bin loader-$(1).uImage
COMPILE/loader-$(1).bin := loader-okli-compile
COMPILE/loader-$(1).uImage := append-loader-okli $(1) | pad-to 64k | \
lzma | uImage lzma
endef
include $(SUBTARGET).mk
ifeq ($(SUBTARGET),generic)

6
target/linux/ath79/image/common-senao.mk
View File

@ -26,13 +26,9 @@ define Build/senao-tar-gz
endef
define Device/senao_loader_okli
$(Device/loader-okli-uimage)
KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x73714f4b
LOADER_KERNEL_MAGIC := 0x73714f4b
LOADER_TYPE := bin
COMPILE := loader-$(1).bin loader-$(1).uImage
COMPILE/loader-$(1).bin := loader-okli-compile
COMPILE/loader-$(1).uImage := append-loader-okli $(1) | pad-to 64k | lzma | \
uImage lzma
IMAGES += factory.bin
IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \
check-size | senao-tar-gz $$$$(SENAO_IMGNAME)

24
target/linux/ath79/image/generic.mk
View File

@ -358,19 +358,15 @@ endef
TARGET_DEVICES += aruba_ap-105
define Device/atheros_db120
$(Device/loader-okli-uimage)
SOC := ar9344
DEVICE_VENDOR := Atheros
DEVICE_MODEL := DB120
DEVICE_PACKAGES := kmod-usb2
IMAGE_SIZE := 7808k
SUPPORTED_DEVICES += db120
LOADER_TYPE := bin
LOADER_FLASH_OFFS := 0x50000
KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49
COMPILE := loader-$(1).bin loader-$(1).uImage
COMPILE/loader-$(1).bin := loader-okli-compile
COMPILE/loader-$(1).uImage := append-loader-okli $(1) | pad-to 64k | lzma | \
uImage lzma
IMAGES += factory.bin
IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \
append-rootfs | pad-rootfs | check-size | pad-to 6336k | \
@ -437,17 +433,13 @@ endef
TARGET_DEVICES += avm_fritzdvbc
define Device/belkin_f9x-v2
$(Device/loader-okli-uimage)
SOC := qca9558
DEVICE_VENDOR := Belkin
IMAGE_SIZE := 14464k
DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct kmod-usb2 \
kmod-usb3 kmod-usb-ledtrig-usbport
LOADER_TYPE := bin
LOADER_FLASH_OFFS := 0x50000
COMPILE := loader-$(1).bin loader-$(1).uImage
COMPILE/loader-$(1).bin := loader-okli-compile
COMPILE/loader-$(1).uImage := append-loader-okli $(1) | pad-to 64k | \
lzma | uImage lzma
KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49
IMAGES += factory.bin
IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \
@ -1972,17 +1964,13 @@ endef
TARGET_DEVICES += pisen_ts-d084
define Device/pisen_wmb001n
$(Device/loader-okli-uimage)
SOC := ar9341
DEVICE_VENDOR := PISEN
DEVICE_MODEL := WMB001N
IMAGE_SIZE := 14080k
DEVICE_PACKAGES := kmod-i2c-gpio kmod-usb2
LOADER_TYPE := bin
LOADER_FLASH_OFFS := 0x20000
COMPILE := loader-$(1).bin loader-$(1).uImage
COMPILE/loader-$(1).bin := loader-okli-compile
COMPILE/loader-$(1).uImage := append-loader-okli $(1) | pad-to 64k | lzma | \
uImage lzma
KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49
IMAGES += factory.bin
IMAGE/factory.bin := $$(IMAGE/sysupgrade.bin) | pisen_wmb001n-factory $(1)
@ -2023,18 +2011,14 @@ endef
TARGET_DEVICES += plasmacloud_pa300e
define Device/qca_ap143
$(Device/loader-okli-uimage)
SOC := qca9533
DEVICE_VENDOR := Qualcomm Atheros
DEVICE_MODEL := AP143
DEVICE_PACKAGES := kmod-usb2
SUPPORTED_DEVICES += ap143
LOADER_TYPE := bin
LOADER_FLASH_OFFS := 0x50000
KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49
COMPILE := loader-$(1).bin loader-$(1).uImage
COMPILE/loader-$(1).bin := loader-okli-compile
COMPILE/loader-$(1).uImage := append-loader-okli $(1) | pad-to 64k | lzma | \
uImage lzma
endef
define Device/qca_ap143-8m

4
target/linux/bcm27xx/bcm2710/config-5.10
View File

@ -17,8 +17,6 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_CNP=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_826319=y
@ -83,7 +81,6 @@ CONFIG_BRCM_CHAR_DRIVERS=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_MMIO=y
@ -197,7 +194,6 @@ CONFIG_FS_ENCRYPTION_ALGS=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FS_POSIX_ACL=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_FW_CACHE=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y

4
target/linux/bcm27xx/bcm2710/config-5.4
View File

@ -18,8 +18,6 @@ CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_CNP=y
CONFIG_ARM64_CONT_SHIFT=4
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_826319=y
@ -86,7 +84,6 @@ CONFIG_BRCM_CHAR_DRIVERS=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLK_BCM2835=y
@ -205,7 +202,6 @@ CONFIG_FS_ENCRYPTION=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FS_POSIX_ACL=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y

4
target/linux/bcm27xx/bcm2711/config-5.10
View File

@ -17,8 +17,6 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_CNP=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_826319=y
@ -87,7 +85,6 @@ CONFIG_BROADCOM_PHY=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_MMIO=y
@ -202,7 +199,6 @@ CONFIG_FS_ENCRYPTION_ALGS=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FS_POSIX_ACL=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_FW_CACHE=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y

4
target/linux/bcm27xx/bcm2711/config-5.4
View File

@ -18,8 +18,6 @@ CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_CNP=y
CONFIG_ARM64_CONT_SHIFT=4
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_826319=y
@ -90,7 +88,6 @@ CONFIG_BROADCOM_PHY=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLK_BCM2835=y
@ -210,7 +207,6 @@ CONFIG_FS_ENCRYPTION=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FS_POSIX_ACL=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y

8
target/linux/bcm27xx/patches-5.4/950-0040-fbdev-add-FBIOCOPYAREA-ioctl.patch
View File

@ -234,7 +234,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
static int bcm2708_fb_register(struct bcm2708_fb *fb)
--- a/drivers/video/fbdev/core/fbmem.c
+++ b/drivers/video/fbdev/core/fbmem.c
@@ -1074,6 +1074,30 @@ fb_blank(struct fb_info *info, int blank
@@ -1080,6 +1080,30 @@ fb_blank(struct fb_info *info, int blank
}
EXPORT_SYMBOL(fb_blank);
@ -265,7 +265,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
@@ -1082,6 +1106,7 @@ static long do_fb_ioctl(struct fb_info *
@@ -1088,6 +1112,7 @@ static long do_fb_ioctl(struct fb_info *
struct fb_fix_screeninfo fix;
struct fb_cmap cmap_from;
struct fb_cmap_user cmap;
@ -273,7 +273,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
void __user *argp = (void __user *)arg;
long ret = 0;
@@ -1157,6 +1182,15 @@ static long do_fb_ioctl(struct fb_info *
@@ -1163,6 +1188,15 @@ static long do_fb_ioctl(struct fb_info *
unlock_fb_info(info);
console_unlock();
break;
@ -289,7 +289,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
default:
lock_fb_info(info);
fb = info->fbops;
@@ -1302,6 +1336,7 @@ static long fb_compat_ioctl(struct file
@@ -1308,6 +1342,7 @@ static long fb_compat_ioctl(struct file
case FBIOPAN_DISPLAY:
case FBIOGET_CON2FBMAP:
case FBIOPUT_CON2FBMAP:

6
target/linux/bcm27xx/patches-5.4/950-0043-MMC-added-alternative-MMC-driver.patch
View File

@ -222,7 +222,7 @@ Signed-off-by: Yaroslav Rosomakho <yaroslavros@gmail.com>
static inline int mmc_blk_part_switch(struct mmc_card *card,
unsigned int part_type);
@@ -2892,6 +2899,7 @@ static int mmc_blk_probe(struct mmc_card
@@ -2891,6 +2898,7 @@ static int mmc_blk_probe(struct mmc_card
{
struct mmc_blk_data *md, *part_md;
char cap_str[10];
@ -230,7 +230,7 @@ Signed-off-by: Yaroslav Rosomakho <yaroslavros@gmail.com>
/*
* Check that the card supports the command class(es) we need.
@@ -2899,7 +2907,16 @@ static int mmc_blk_probe(struct mmc_card
@@ -2898,7 +2906,16 @@ static int mmc_blk_probe(struct mmc_card
if (!(card->csd.cmdclass & CCC_BLOCK_READ))
return -ENODEV;
@ -248,7 +248,7 @@ Signed-off-by: Yaroslav Rosomakho <yaroslavros@gmail.com>
card->complete_wq = alloc_workqueue("mmc_complete",
WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
@@ -2914,9 +2931,14 @@ static int mmc_blk_probe(struct mmc_card
@@ -2913,9 +2930,14 @@ static int mmc_blk_probe(struct mmc_card
string_get_size((u64)get_capacity(md->disk), 512, STRING_UNITS_2,
cap_str, sizeof(cap_str));

4
target/linux/bcm27xx/patches-5.4/950-0218-usb-add-plumbing-for-updating-interrupt-endpoint-int.patch
View File

@ -81,7 +81,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
extern int usb_driver_set_configuration(struct usb_device *udev, int config);
--- a/include/linux/usb/hcd.h
+++ b/include/linux/usb/hcd.h
@@ -382,6 +382,11 @@ struct hc_driver {
@@ -384,6 +384,11 @@ struct hc_driver {
* or bandwidth constraints.
*/
void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
@ -93,7 +93,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
/* Returns the hardware-chosen device address */
int (*address_device)(struct usb_hcd *, struct usb_device *udev);
/* prepares the hardware to send commands to the device */
@@ -443,6 +448,8 @@ extern void usb_hcd_unmap_urb_setup_for_
@@ -445,6 +450,8 @@ extern void usb_hcd_unmap_urb_setup_for_
extern void usb_hcd_unmap_urb_for_dma(struct usb_hcd *, struct urb *);
extern void usb_hcd_flush_endpoint(struct usb_device *udev,
struct usb_host_endpoint *ep);

4
target/linux/bcm27xx/patches-5.4/950-0219-xhci-implement-xhci_fixup_endpoint-for-interval-adju.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -1468,6 +1468,103 @@ command_cleanup:
@@ -1469,6 +1469,103 @@ command_cleanup:
}
/*
@ -119,7 +119,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
* non-error returns are a promise to giveback() the urb later
* we drop ownership so next owner (or urb unlink) can get it
*/
@@ -5357,6 +5454,7 @@ static const struct hc_driver xhci_hc_dr
@@ -5358,6 +5455,7 @@ static const struct hc_driver xhci_hc_dr
.endpoint_reset = xhci_endpoint_reset,
.check_bandwidth = xhci_check_bandwidth,
.reset_bandwidth = xhci_reset_bandwidth,

8
target/linux/bcm27xx/patches-5.4/950-0441-PCI-of-Add-inbound-resource-parsing-to-helpers.patch
View File

@ -82,7 +82,7 @@ Cc: linux-rockchip@lists.infradead.org
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -1060,7 +1060,8 @@ static int advk_pcie_probe(struct platfo
@@ -1176,7 +1176,8 @@ static int advk_pcie_probe(struct platfo
return ret;
}
@ -249,7 +249,7 @@ Cc: linux-rockchip@lists.infradead.org
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -845,8 +845,8 @@ static int nwl_pcie_probe(struct platfor
@@ -857,8 +857,8 @@ static int nwl_pcie_probe(struct platfor
return err;
}
@ -402,7 +402,7 @@ Cc: linux-rockchip@lists.infradead.org
}
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -2278,6 +2278,7 @@ struct irq_domain;
@@ -2279,6 +2279,7 @@ struct irq_domain;
struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
int pci_parse_request_of_pci_ranges(struct device *dev,
struct list_head *resources,
@ -410,7 +410,7 @@ Cc: linux-rockchip@lists.infradead.org
struct resource **bus_range);
/* Arch may override this (weak) */
@@ -2286,9 +2287,11 @@ struct device_node *pcibios_get_phb_of_n
@@ -2287,9 +2288,11 @@ struct device_node *pcibios_get_phb_of_n
#else /* CONFIG_OF */
static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }

4
target/linux/bcm4908/config-5.4
View File

@ -15,8 +15,6 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_CONT_SHIFT=4
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
@ -47,7 +45,6 @@ CONFIG_BCM_NET_PHYLIB=y
CONFIG_BCM_PMB=y
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_BLK_PM=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="earlycon=bcm63xx_uart,0xff800640 console=ttyS0,115200"
@ -76,7 +73,6 @@ CONFIG_EDAC_SUPPORT=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y

4
target/linux/bcm4908/patches-5.4/070-v5.10-0001-net-dsa-b53-Use-dev_-err-info-instead-of-pr_.patch
View File

@ -26,7 +26,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/gpio.h>
@@ -2476,8 +2474,9 @@ int b53_switch_detect(struct b53_device
@@ -2475,8 +2473,9 @@ int b53_switch_detect(struct b53_device
dev->chip_id = id32;
break;
default:
@ -38,7 +38,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
return -ENODEV;
}
}
@@ -2507,7 +2506,8 @@ int b53_switch_register(struct b53_devic
@@ -2506,7 +2505,8 @@ int b53_switch_register(struct b53_devic
if (ret)
return ret;

4
target/linux/bcm53xx/patches-5.4/905-BCM53573-minor-hacks.patch
View File

@ -21,7 +21,7 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
clocks {
--- a/drivers/bcma/main.c
+++ b/drivers/bcma/main.c
@@ -330,14 +330,6 @@ static int bcma_register_devices(struct
@@ -328,14 +328,6 @@ static int bcma_register_devices(struct
}
#endif
@ -36,7 +36,7 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
#ifdef CONFIG_BCMA_NFLASH
if (bus->drv_cc.nflash.present) {
err = platform_device_register(&bcma_nflash_dev);
@@ -415,6 +407,14 @@ int bcma_bus_register(struct bcma_bus *b
@@ -413,6 +405,14 @@ int bcma_bus_register(struct bcma_bus *b
bcma_register_core(bus, core);
}

461
target/linux/gemini/config-5.4
View File

@ -1,461 +0,0 @@
CONFIG_ALIGNMENT_TRAP=y
CONFIG_AMBA_PL08X=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_GEMINI=y
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
CONFIG_ARCH_HAS_KCOV=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SG_CHAIN=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_ARCH_MOXART is not set
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V4=y
# CONFIG_ARCH_MULTI_V4T is not set
CONFIG_ARCH_MULTI_V4_V5=y
# CONFIG_ARCH_MULTI_V5 is not set
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_APPENDED_DTB=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_L1_CACHE_SHIFT=5
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_UNWIND=y
CONFIG_ATA=y
CONFIG_ATAGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BOUNCE=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMA=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_SIZE_MBYTES=16
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_GEMINI=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_COREDUMP=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_CPU_32v4=y
CONFIG_CPU_ABRT_EV4=y
CONFIG_CPU_CACHE_FA=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_COPY_FA=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
CONFIG_CPU_FA526=y
CONFIG_CPU_NO_EFFICIENT_FFS=y
CONFIG_CPU_PABRT_LEGACY=y
CONFIG_CPU_TLB_FA=y
CONFIG_CPU_USE_DOMAINS=y
CONFIG_CRASH_CORE=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRC_CCITT=y
CONFIG_CRC_ITU_T=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_DMADEVICES=y
CONFIG_DMATEST=y
CONFIG_DMA_CMA=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_ENGINE_RAID=y
CONFIG_DMA_OF=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DRM=y
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_KMS_CMA_HELPER=y
CONFIG_DRM_KMS_FB_HELPER=y
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_PANEL=y
CONFIG_DRM_PANEL_BRIDGE=y
CONFIG_DRM_PANEL_ILITEK_IL9322=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_TVE200=y
CONFIG_DTC=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_93CX6=y
CONFIG_ELF_CORE=y
# CONFIG_EMBEDDED is not set
# CONFIG_EXPERT is not set
CONFIG_EXT4_FS=y
CONFIG_FARADAY_FTINTC010=y
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_SYS_IMAGEBLIT=y
CONFIG_FHANDLE=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FONT_8x16=y
CONFIG_FONT_8x8=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FPE_FASTFPE is not set
# CONFIG_FPE_NWFPE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FS_POSIX_ACL=y
CONFIG_FTTMR010_TIMER=y
CONFIG_FTWDT010_WATCHDOG=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_GEMINI_ETHERNET=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GLOB=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_FTGPIO010=y
CONFIG_GPIO_GENERIC=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_UID16=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HDMI=y
CONFIG_HIGHMEM=y
CONFIG_HIGHPTE=y
CONFIG_HWMON=y
CONFIG_HW_CONSOLE=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_GPIO=y
CONFIG_I2C_HELPER_AUTO=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INPUT=y
CONFIG_INPUT_KEYBOARD=y
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IOSCHED_CFQ=y
CONFIG_IPC_NS=y
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_ISDN is not set
CONFIG_JBD2=y
CONFIG_KALLSYMS=y
CONFIG_KERNEL_LZMA=y
# CONFIG_KERNEL_XZ is not set
CONFIG_KEXEC=y
CONFIG_KEXEC_CORE=y
CONFIG_KEYBOARD_DLINK_DIR685=y
# CONFIG_LDM_DEBUG is not set
CONFIG_LDM_PARTITION=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_CLUT224=y
# CONFIG_LOGO_LINUX_MONO is not set
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MANDATORY_FILE_LOCKING=y
CONFIG_MARVELL_PHY=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_GPIO=y
CONFIG_MEMFD_CREATE=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_PCI=y
CONFIG_MIGRATION=y
CONFIG_MODULES_USE_ELF_REL=y
# CONFIG_MODULE_UNLOAD is not set
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_GEMINI=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_WRGG_FW=y
CONFIG_NAMESPACES=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_KUSER_HELPERS=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_REALTEK_SMI=y
CONFIG_NET_DSA_VITESSE_VSC73XX=y
CONFIG_NET_NS=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NVMEM=y
CONFIG_OABI_COMPAT=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_PAGE_OFFSET=0xC0000000
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
CONFIG_PATA_FTIDE010=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_FTPCI100=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
CONFIG_PID_NS=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_GEMINI=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GEMINI_POWEROFF=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_RCU=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_RATIONAL=y
CONFIG_RD_BZIP2=y
CONFIG_RD_GZIP=y
CONFIG_RD_LZ4=y
CONFIG_RD_LZMA=y
CONFIG_RD_LZO=y
CONFIG_RD_XZ=y
CONFIG_REALTEK_PHY=y
CONFIG_REFCOUNT_FULL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_SPI=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_RELAY=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RSEQ=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_FTRTC010=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_NVMEM=y
CONFIG_SATA_GEMINI=y
CONFIG_SATA_PMP=y
CONFIG_SCSI=y
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_PROC_FS is not set
CONFIG_SENSORS_DRIVETEMP=y
CONFIG_SENSORS_GPIO_FAN=y
CONFIG_SENSORS_LM75=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIO=y
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_SERPORT=y
CONFIG_SG_POOL=y
CONFIG_SLUB_DEBUG=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_SPLIT_PTLOCK_CPUS=999999
CONFIG_SRCU=y
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_SWPHY=y
CONFIG_SYNC_FILE=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_TASKS_RCU=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TREE_SRCU=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_UNWINDER_ARM=y
CONFIG_USB_SUPPORT=y
CONFIG_USER_NS=y
CONFIG_USE_OF=y
CONFIG_UTS_NS=y
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_VITESSE_PHY=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_X86=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_INFLATE=y

131
target/linux/gemini/patches-5.4/0001-usb-host-fotg2-add-Gemini-specific-handling.patch
View File

@ -1,131 +0,0 @@
From 3aaff88a0f5e154aa5a489d59fd4015a2a937c23 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Fri, 21 Apr 2017 22:19:00 +0200
Subject: [PATCH 1/7] usb: host: fotg2: add Gemini-specific handling
The Cortina Systems Gemini has bolted on a PHY inside the
silicon that can be handled by six bits in a MISC register in
the system controller.
If we are running on Gemini, look up a syscon regmap through
a phandle and enable VBUS and optionally the Mini-B connector.
If the device is flagged as "wakeup-source" using the standard
DT bindings, we also enable this in the global controller for
respective port.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/usb/host/Kconfig | 1 +
drivers/usb/host/fotg210-hcd.c | 76 ++++++++++++++++++++++++++++++++++
2 files changed, 77 insertions(+)
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -363,6 +363,7 @@ config USB_ISP1362_HCD
config USB_FOTG210_HCD
tristate "FOTG210 HCD support"
depends on USB && HAS_DMA && HAS_IOMEM
+ select MFD_SYSCON
---help---
Faraday FOTG210 is an OTG controller which can be configured as
an USB2.0 host. It is designed to meet USB2.0 EHCI specification
--- a/drivers/usb/host/fotg210-hcd.c
+++ b/drivers/usb/host/fotg210-hcd.c
@@ -33,6 +33,10 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
+#include <linux/bitops.h>
+/* For Cortina Gemini */
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
#include <asm/byteorder.h>
#include <asm/irq.h>
@@ -5558,6 +5562,72 @@ static void fotg210_init(struct fotg210_
iowrite32(value, &fotg210->regs->otgcsr);
}
+/*
+ * Gemini-specific initialization function, only executed on the
+ * Gemini SoC using the global misc control register.
+ */
+#define GEMINI_GLOBAL_MISC_CTRL 0x30
+#define GEMINI_MISC_USB0_WAKEUP BIT(14)
+#define GEMINI_MISC_USB1_WAKEUP BIT(15)
+#define GEMINI_MISC_USB0_VBUS_ON BIT(22)
+#define GEMINI_MISC_USB1_VBUS_ON BIT(23)
+#define GEMINI_MISC_USB0_MINI_B BIT(29)
+#define GEMINI_MISC_USB1_MINI_B BIT(30)
+
+static int fotg210_gemini_init(struct device *dev, struct usb_hcd *hcd)
+{
+ struct device_node *np = dev->of_node;
+ struct regmap *map;
+ bool mini_b;
+ bool wakeup;
+ u32 mask, val;
+ int ret;
+
+ map = syscon_regmap_lookup_by_phandle(np, "syscon");
+ if (IS_ERR(map)) {
+ dev_err(dev, "no syscon\n");
+ return PTR_ERR(map);
+ }
+ mini_b = of_property_read_bool(np, "cortina,gemini-mini-b");
+ wakeup = of_property_read_bool(np, "wakeup-source");
+
+ /*
+ * Figure out if this is USB0 or USB1 by simply checking the
+ * physical base address.
+ */
+ mask = 0;
+ if (hcd->rsrc_start == 0x69000000) {
+ val = GEMINI_MISC_USB1_VBUS_ON;
+ if (mini_b)
+ val |= GEMINI_MISC_USB1_MINI_B;
+ else
+ mask |= GEMINI_MISC_USB1_MINI_B;
+ if (wakeup)
+ val |= GEMINI_MISC_USB1_WAKEUP;
+ else
+ mask |= GEMINI_MISC_USB1_WAKEUP;
+ } else {
+ val = GEMINI_MISC_USB0_VBUS_ON;
+ if (mini_b)
+ val |= GEMINI_MISC_USB0_MINI_B;
+ else
+ mask |= GEMINI_MISC_USB0_MINI_B;
+ if (wakeup)
+ val |= GEMINI_MISC_USB0_WAKEUP;
+ else
+ mask |= GEMINI_MISC_USB0_WAKEUP;
+ }
+
+ ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, mask, val);
+ if (ret) {
+ dev_err(dev, "failed to initialize Gemini PHY\n");
+ return ret;
+ }
+
+ dev_info(dev, "initialized Gemini PHY\n");
+ return 0;
+}
+
/**
* fotg210_hcd_probe - initialize faraday FOTG210 HCDs
*
@@ -5635,6 +5705,12 @@ static int fotg210_hcd_probe(struct plat
fotg210_init(fotg210);
+ if (of_device_is_compatible(dev->of_node, "cortina,gemini-usb")) {
+ retval = fotg210_gemini_init(dev, hcd);
+ if (retval)
+ goto failed_dis_clk;
+ }
+
retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
if (retval) {
dev_err(dev, "failed to add hcd with err %d\n", retval);

37
target/linux/gemini/patches-5.4/0002-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch
View File

@ -1,37 +0,0 @@
From a2de8560885469f3d76c80207a669029e4fc8a45 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Mon, 11 Mar 2019 15:44:29 +0100
Subject: [PATCH 2/7] ARM: dts: Augment DIR-685 partition table for OpenWrt
Rename the firmware partition so that the firmware MTD
splitter will do its job, drop the rootfs arguments as
the MTD splitter will set this up automatically.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/gemini-dlink-dir-685.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300";
+ bootargs = "console=ttyS0,19200n8 consoleblank=300";
stdout-path = "uart0:19200n8";
};
@@ -285,9 +285,9 @@
* this is called "upgrade" on the vendor system.
*/
partition@40000 {
- label = "upgrade";
+ compatible = "wrg";
+ label = "firmware";
reg = <0x00040000 0x01f40000>;
- read-only;
};
/* RGDB, Residental Gateway Database? */
partition@1f80000 {

117
target/linux/gemini/patches-5.4/0003-ARM-dts-gemini-Rename-IDE-nodes.patch
View File

@ -1,117 +0,0 @@
From 9b95b301b219df19c20f4a563f1da6338b09b0d0 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Tue, 31 Dec 2019 18:14:28 +0100
Subject: [PATCH 3/7] ARM: dts: gemini: Rename IDE nodes
By renaming the ATA drive nodes to "ide@" we activate the
semantic checks to the DT schema for the controller and use
the correct notation for PATA drives.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/gemini-dlink-dir-685.dts | 2 +-
arch/arm/boot/dts/gemini-dlink-dns-313.dts | 2 +-
arch/arm/boot/dts/gemini-nas4220b.dts | 4 ++--
arch/arm/boot/dts/gemini-sl93512r.dts | 4 ++--
arch/arm/boot/dts/gemini-sq201.dts | 2 +-
arch/arm/boot/dts/gemini.dtsi | 8 ++++++--
6 files changed, 13 insertions(+), 9 deletions(-)
--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
@@ -443,7 +443,7 @@
};
};
- ata@63000000 {
+ ide@63000000 {
status = "okay";
};
--- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
@@ -297,7 +297,7 @@
};
};
- ata@63000000 {
+ ide@63000000 {
status = "okay";
};
};
--- a/arch/arm/boot/dts/gemini-nas4220b.dts
+++ b/arch/arm/boot/dts/gemini-nas4220b.dts
@@ -170,11 +170,11 @@
};
};
- ata@63000000 {
+ ide@63000000 {
status = "okay";
};
- ata@63400000 {
+ ide@63400000 {
status = "okay";
};
--- a/arch/arm/boot/dts/gemini-sl93512r.dts
+++ b/arch/arm/boot/dts/gemini-sl93512r.dts
@@ -293,11 +293,11 @@
};
};
- ata@63000000 {
+ ide@63000000 {
status = "okay";
};
- ata@63400000 {
+ ide@63400000 {
status = "okay";
};
--- a/arch/arm/boot/dts/gemini-sq201.dts
+++ b/arch/arm/boot/dts/gemini-sq201.dts
@@ -289,7 +289,7 @@
};
};
- ata@63000000 {
+ ide@63000000 {
status = "okay";
};
--- a/arch/arm/boot/dts/gemini.dtsi
+++ b/arch/arm/boot/dts/gemini.dtsi
@@ -357,7 +357,7 @@
};
};
- ata@63000000 {
+ ide@63000000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63000000 0x1000>;
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
@@ -366,9 +366,11 @@
clock-names = "PCLK";
sata = <&sata>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
- ata@63400000 {
+ ide@63400000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63400000 0x1000>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
@@ -377,6 +379,8 @@
clock-names = "PCLK";
sata = <&sata>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
dma-controller@67000000 {

101
target/linux/gemini/patches-5.4/0004-ARM-dts-gemini-Add-thermal-zone-to-DIR-685.patch
View File

@ -1,101 +0,0 @@
From 2b2e9d0e1ee4765b21c648235489028c6dc7e336 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Tue, 31 Dec 2019 18:18:08 +0100
Subject: [PATCH 4/7] ARM: dts: gemini: Add thermal zone to DIR-685
The DIR-685 can now exploit the thermal zone added by the
drive temperature sensor inside the hard drive. We have
patched the libata subsystem to assign the device nodes
properly to the SCSI devices and this is what the drivetemp
driver will use to populate the sensor and the thermal
zone, so pick that up into the thermal zone and let this
control the fan.
The hardware lacks an embedded temperature sensor so the
D-Link vendor firmware uses this method to control the
temperature of the NAS enclosure using the thermal sensor
inside the hard drive.
The drive temperature trigger points to be used comes from
the vendor firmware.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/gemini-dlink-dir-685.dts | 48 ++++++++++++++++++++--
1 file changed, 45 insertions(+), 3 deletions(-)
--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
@@ -119,13 +119,11 @@
/*
* This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM.
- * Since the platform has no temperature sensor, this is controlled
- * from userspace by using the hard disks S.M.A.R.T. temperature
* sensor. It is turned on when the temperature exceeds 46 degrees
* and turned off when the temperatures goes below 41 degrees
* (celsius).
*/
- gpio-fan {
+ fan0: gpio-fan {
compatible = "gpio-fan";
/* Collides with IDE */
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
@@ -133,6 +131,40 @@
#cooling-cells = <2>;
};
+ thermal-zones {
+ chassis-thermal {
+ /* Poll every 20 seconds */
+ polling-delay = <20000>;
+ /* Poll every 2nd second when cooling */
+ polling-delay-passive = <2000>;
+ /* Use the thermal sensor in the hard drive */
+ thermal-sensors = <&drive0>;
+
+ /* Tripping points from the fan.script in the rootfs */
+ trips {
+ alert: chassis-alert {
+ /* At 43 degrees turn on the fan */
+ temperature = <43000>;
+ hysteresis = <3000>;
+ type = "active";
+ };
+ crit: chassis-crit {
+ /* Just shut down at 60 degrees */
+ temperature = <60000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&alert>;
+ cooling-device = <&fan0 1 1>;
+ };
+ };
+ };
+ };
+
/*
* The touchpad input is connected to a GPIO bit-banged
* I2C bus.
@@ -445,6 +477,16 @@
ide@63000000 {
status = "okay";
+
+ /*
+ * This drive may have a temperature sensor with a
+ * thermal zone we can use for thermal control of the
+ * chassis temperature using the fan.
+ */
+ drive0: ide-port@0 {
+ reg = <0>;
+ #thermal-sensor-cells = <0>;
+ };
};
display-controller@6a000000 {

2
target/linux/generic/backport-5.4/737-v5.5-net-phy-add-core-phylib-sfp-support.patch
View File

@ -130,7 +130,7 @@ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
/* Some Ethernet drivers try to connect to a PHY device before
* calling register_netdevice() -> netdev_register_kobject() and
* does the dev->dev.kobj initialization. Here we only check for
@@ -2290,6 +2353,9 @@ static int phy_remove(struct device *dev
@@ -2291,6 +2354,9 @@ static int phy_remove(struct device *dev
phydev->state = PHY_DOWN;
mutex_unlock(&phydev->lock);

2
target/linux/generic/backport-5.4/750-v5.5-net-phy-add-support-for-clause-37-auto-negotiation.patch
View File

@ -116,7 +116,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
* genphy_aneg_done - return auto-negotiation status
* @phydev: target phy_device struct
*
@@ -1961,6 +2043,63 @@ int genphy_read_status(struct phy_device
@@ -1962,6 +2044,63 @@ int genphy_read_status(struct phy_device
EXPORT_SYMBOL(genphy_read_status);
/**

4
target/linux/generic/backport-5.4/771-v5.12-net-dsa-be-louder-when-a-non-legacy-FDB-operation-fa.patch
View File

@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -1595,7 +1595,9 @@ static void dsa_slave_switchdev_event_wo
@@ -1593,7 +1593,9 @@ static void dsa_slave_switchdev_event_wo
err = dsa_port_fdb_add(dp, fdb_info->addr, fdb_info->vid);
if (err) {
@ -36,7 +36,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
break;
}
fdb_info->offloaded = true;
@@ -1610,9 +1612,11 @@ static void dsa_slave_switchdev_event_wo
@@ -1608,9 +1610,11 @@ static void dsa_slave_switchdev_event_wo
err = dsa_port_fdb_del(dp, fdb_info->addr, fdb_info->vid);
if (err) {

8
target/linux/generic/backport-5.4/772-v5.12-net-dsa-don-t-use-switchdev_notifier_fdb_info-in-dsa.patch
View File

@ -54,7 +54,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
struct sk_buff * (*xmit)(struct sk_buff *skb,
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -1570,76 +1570,66 @@ static int dsa_slave_netdevice_event(str
@@ -1568,76 +1568,66 @@ static int dsa_slave_netdevice_event(str
return NOTIFY_DONE;
}
@ -167,7 +167,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
}
/* Called under rcu_read_lock() */
@@ -1647,7 +1637,9 @@ static int dsa_slave_switchdev_event(str
@@ -1645,7 +1635,9 @@ static int dsa_slave_switchdev_event(str
unsigned long event, void *ptr)
{
struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
@ -177,7 +177,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
int err;
if (event == SWITCHDEV_PORT_ATTR_SET) {
@@ -1660,20 +1652,32 @@ static int dsa_slave_switchdev_event(str
@@ -1658,20 +1650,32 @@ static int dsa_slave_switchdev_event(str
if (!dsa_slave_dev_check(dev))
return NOTIFY_DONE;
@ -213,7 +213,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
dev_hold(dev);
break;
default:
@@ -1683,10 +1687,6 @@ static int dsa_slave_switchdev_event(str
@@ -1681,10 +1685,6 @@ static int dsa_slave_switchdev_event(str
dsa_schedule_work(&switchdev_work->work);
return NOTIFY_OK;

4
target/linux/generic/backport-5.4/773-v5.12-net-dsa-move-switchdev-event-implementation-under-th.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -1642,31 +1642,29 @@ static int dsa_slave_switchdev_event(str
@@ -1640,31 +1640,29 @@ static int dsa_slave_switchdev_event(str
struct dsa_port *dp;
int err;
@ -68,7 +68,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
fdb_info = ptr;
if (!fdb_info->added_by_user) {
@@ -1679,13 +1677,12 @@ static int dsa_slave_switchdev_event(str
@@ -1677,13 +1675,12 @@ static int dsa_slave_switchdev_event(str
switchdev_work->vid = fdb_info->vid;
dev_hold(dev);

2
target/linux/generic/backport-5.4/774-v5.12-net-dsa-exit-early-in-dsa_slave_switchdev_event-if-w.patch
View File

@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -1655,6 +1655,9 @@ static int dsa_slave_switchdev_event(str
@@ -1653,6 +1653,9 @@ static int dsa_slave_switchdev_event(str
dp = dsa_slave_to_port(dev);

6
target/linux/generic/backport-5.4/775-v5.12-net-dsa-listen-for-SWITCHDEV_-FDB-DEL-_ADD_TO_DEVICE.patch
View File

@ -172,7 +172,7 @@ Signed-off-by: DENG Qingfang <dqfext@gmail.com>
*/
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -1632,6 +1632,25 @@ static void dsa_slave_switchdev_event_wo
@@ -1630,6 +1630,25 @@ static void dsa_slave_switchdev_event_wo
dev_put(dp->slave);
}
@ -198,7 +198,7 @@ Signed-off-by: DENG Qingfang <dqfext@gmail.com>
/* Called under rcu_read_lock() */
static int dsa_slave_switchdev_event(struct notifier_block *unused,
unsigned long event, void *ptr)
@@ -1650,10 +1669,37 @@ static int dsa_slave_switchdev_event(str
@@ -1648,10 +1667,37 @@ static int dsa_slave_switchdev_event(str
return notifier_from_errno(err);
case SWITCHDEV_FDB_ADD_TO_DEVICE:
case SWITCHDEV_FDB_DEL_TO_DEVICE:
@ -239,7 +239,7 @@ Signed-off-by: DENG Qingfang <dqfext@gmail.com>
if (!dp->ds->ops->port_fdb_add || !dp->ds->ops->port_fdb_del)
return NOTIFY_DONE;
@@ -1668,18 +1714,13 @@ static int dsa_slave_switchdev_event(str
@@ -1666,18 +1712,13 @@ static int dsa_slave_switchdev_event(str
switchdev_work->port = dp->index;
switchdev_work->event = event;

10
target/linux/generic/backport-5.4/782-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch
View File

@ -1011,7 +1011,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
"no valid MAC address supplied, using a random one\n");
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -3194,7 +3194,6 @@ static struct sh_eth_plat_data *sh_eth_p
@@ -3195,7 +3195,6 @@ static struct sh_eth_plat_data *sh_eth_p
{
struct device_node *np = dev->of_node;
struct sh_eth_plat_data *pdata;
@ -1019,7 +1019,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
int ret;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
@@ -3206,9 +3205,7 @@ static struct sh_eth_plat_data *sh_eth_p
@@ -3207,9 +3206,7 @@ static struct sh_eth_plat_data *sh_eth_p
return NULL;
pdata->phy_interface = ret;
@ -1302,7 +1302,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
int irq;
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -4469,7 +4469,7 @@ int stmmac_dvr_probe(struct device *devi
@@ -4471,7 +4471,7 @@ int stmmac_dvr_probe(struct device *devi
priv->wol_irq = res->wol_irq;
priv->lpi_irq = res->lpi_irq;
@ -1450,7 +1450,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
of_id = of_match_device(w5100_of_match, &spi->dev);
--- a/drivers/net/ethernet/wiznet/w5100.c
+++ b/drivers/net/ethernet/wiznet/w5100.c
@@ -1157,7 +1157,7 @@ int w5100_probe(struct device *dev, cons
@@ -1159,7 +1159,7 @@ int w5100_probe(struct device *dev, cons
INIT_WORK(&priv->setrx_work, w5100_setrx_work);
INIT_WORK(&priv->restart_work, w5100_restart_work);
@ -1764,7 +1764,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
break;
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -1416,7 +1416,7 @@ int dsa_slave_create(struct dsa_port *po
@@ -1414,7 +1414,7 @@ int dsa_slave_create(struct dsa_port *po
slave_dev->hw_features |= NETIF_F_HW_TC;
slave_dev->features |= NETIF_F_LLTX;
slave_dev->ethtool_ops = &dsa_slave_ethtool_ops;

5
target/linux/generic/config-5.10
View File

@ -313,7 +313,10 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
# CONFIG_ARM64_CRYPTO is not set
# CONFIG_ARM64_E0PD is not set
# CONFIG_ARM64_ERRATUM_1024718 is not set
# CONFIG_ARM64_ERRATUM_1165522 is not set
# CONFIG_ARM64_ERRATUM_1286807 is not set
# CONFIG_ARM64_ERRATUM_1319367 is not set
# CONFIG_ARM64_ERRATUM_1418040 is not set
# CONFIG_ARM64_ERRATUM_1463225 is not set
# CONFIG_ARM64_ERRATUM_1508412 is not set
# CONFIG_ARM64_ERRATUM_1530923 is not set
@ -830,6 +833,7 @@ CONFIG_CARDBUS=y
# CONFIG_CAVIUM_ERRATUM_30115 is not set
# CONFIG_CAVIUM_OCTEON_SOC is not set
# CONFIG_CAVIUM_PTP is not set
# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
# CONFIG_CB710_CORE is not set
# CONFIG_CC10001_ADC is not set
# CONFIG_CCS811 is not set
@ -1996,6 +2000,7 @@ CONFIG_FSNOTIFY=y
# CONFIG_FTRACE_STARTUP_TEST is not set
# CONFIG_FTR_FIXUP_SELFTEST is not set
# CONFIG_FTWDT010_WATCHDOG is not set
# CONFIG_FUJITSU_ERRATUM_010001 is not set
# CONFIG_FUJITSU_ES is not set
# CONFIG_FUJITSU_LAPTOP is not set
# CONFIG_FUJITSU_TABLET is not set

5
target/linux/generic/config-5.4
View File

@ -297,6 +297,9 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
# CONFIG_ARM64_64K_PAGES is not set
# CONFIG_ARM64_CRYPTO is not set
# CONFIG_ARM64_ERRATUM_1024718 is not set
# CONFIG_ARM64_ERRATUM_1165522 is not set
# CONFIG_ARM64_ERRATUM_1286807 is not set
# CONFIG_ARM64_ERRATUM_1418040 is not set
# CONFIG_ARM64_ERRATUM_1463225 is not set
# CONFIG_ARM64_ERRATUM_1542419 is not set
# CONFIG_ARM64_ERRATUM_819472 is not set
@ -781,6 +784,7 @@ CONFIG_CARDBUS=y
# CONFIG_CAVIUM_ERRATUM_30115 is not set
# CONFIG_CAVIUM_OCTEON_SOC is not set
# CONFIG_CAVIUM_PTP is not set
# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
# CONFIG_CB710_CORE is not set
# CONFIG_CC10001_ADC is not set
# CONFIG_CCS811 is not set
@ -1750,6 +1754,7 @@ CONFIG_FSNOTIFY=y
# CONFIG_FTRACE_STARTUP_TEST is not set
# CONFIG_FTR_FIXUP_SELFTEST is not set
# CONFIG_FTWDT010_WATCHDOG is not set
# CONFIG_FUJITSU_ERRATUM_010001 is not set
# CONFIG_FUJITSU_ES is not set
# CONFIG_FUJITSU_LAPTOP is not set
# CONFIG_FUJITSU_TABLET is not set

23
target/linux/generic/hack-5.10/252-SATA_PMP.patch Normal file
View File

@ -0,0 +1,23 @@
From 8c817e33be829c7249c2cfd59ff48ad5fac6a31d Mon Sep 17 00:00:00 2001
From: Sungbo Eo <mans0n@gorani.run>
Date: Fri, 7 Jul 2017 17:09:21 +0200
Subject: [PATCH] kconfig: solidify SATA_PMP config
SATA_PMP option in kernel config file disappears for every kernel_oldconfig refresh.
To prevent this, SATA_HOST is now selected automatically when SATA_PMP is enabled.
This patch can be dropped if SATA_MV is ever re-added into the config.
---
drivers/ata/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -112,7 +112,7 @@ config SATA_ZPODD
config SATA_PMP
bool "SATA Port Multiplier support"
- depends on SATA_HOST
+ select SATA_HOST
default y
help
This option adds support for SATA Port Multipliers

2
target/linux/generic/hack-5.4/220-arm-gc_sections.patch
View File

@ -31,7 +31,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
select OF_EARLY_FLATTREE if OF
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -106,6 +106,7 @@ ifeq ($(CONFIG_FUNCTION_TRACER),y)
@@ -108,6 +108,7 @@ ifeq ($(CONFIG_FUNCTION_TRACER),y)
ORIG_CFLAGS := $(KBUILD_CFLAGS)
KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
endif

2
target/linux/generic/hack-5.4/660-fq_codel_defaults.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/net/sched/sch_fq_codel.c
+++ b/net/sched/sch_fq_codel.c
@@ -462,7 +462,11 @@ static int fq_codel_init(struct Qdisc *s
@@ -470,7 +470,11 @@ static int fq_codel_init(struct Qdisc *s
sch->limit = 10*1024;
q->flows_cnt = 1024;

4
target/linux/generic/hack-5.4/661-use_fq_codel_by_default.patch
View File

@ -55,7 +55,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
register_qdisc(&pfifo_head_drop_qdisc_ops);
--- a/net/sched/sch_fq_codel.c
+++ b/net/sched/sch_fq_codel.c
@@ -702,7 +702,7 @@ static const struct Qdisc_class_ops fq_c
@@ -710,7 +710,7 @@ static const struct Qdisc_class_ops fq_c
.walk = fq_codel_walk,
};
@ -64,7 +64,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
.cl_ops = &fq_codel_class_ops,
.id = "fq_codel",
.priv_size = sizeof(struct fq_codel_sched_data),
@@ -717,6 +717,7 @@ static struct Qdisc_ops fq_codel_qdisc_o
@@ -725,6 +725,7 @@ static struct Qdisc_ops fq_codel_qdisc_o
.dump_stats = fq_codel_dump_stats,
.owner = THIS_MODULE,
};

2
target/linux/generic/hack-5.4/904-debloat_dma_buf.patch
View File

@ -54,7 +54,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
+MODULE_LICENSE("GPL");
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -2754,6 +2754,7 @@ int wake_up_state(struct task_struct *p,
@@ -2767,6 +2767,7 @@ int wake_up_state(struct task_struct *p,
{
return try_to_wake_up(p, state, 0);
}

18
target/linux/generic/pending-5.4/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
View File

@ -157,7 +157,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
case RTN_THROW:
case RTN_UNREACHABLE:
default:
@@ -4423,6 +4442,17 @@ static int ip6_pkt_prohibit_out(struct n
@@ -4426,6 +4445,17 @@ static int ip6_pkt_prohibit_out(struct n
return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES);
}
@ -175,7 +175,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
/*
* Allocate a dst for local (unicast / anycast) address.
*/
@@ -4903,7 +4933,8 @@ static int rtm_to_fib6_config(struct sk_
@@ -4906,7 +4936,8 @@ static int rtm_to_fib6_config(struct sk_
if (rtm->rtm_type == RTN_UNREACHABLE ||
rtm->rtm_type == RTN_BLACKHOLE ||
rtm->rtm_type == RTN_PROHIBIT ||
@ -185,7 +185,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
cfg->fc_flags |= RTF_REJECT;
if (rtm->rtm_type == RTN_LOCAL)
@@ -6025,6 +6056,8 @@ static int ip6_route_dev_notify(struct n
@@ -6028,6 +6059,8 @@ static int ip6_route_dev_notify(struct n
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
net->ipv6.ip6_prohibit_entry->dst.dev = dev;
net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
@ -194,7 +194,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
#endif
@@ -6036,6 +6069,7 @@ static int ip6_route_dev_notify(struct n
@@ -6039,6 +6072,7 @@ static int ip6_route_dev_notify(struct n
in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
@ -202,7 +202,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
#endif
}
@@ -6228,6 +6262,8 @@ static int __net_init ip6_route_net_init
@@ -6231,6 +6265,8 @@ static int __net_init ip6_route_net_init
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
net->ipv6.fib6_has_custom_rules = false;
@ -211,7 +211,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,
sizeof(*net->ipv6.ip6_prohibit_entry),
GFP_KERNEL);
@@ -6238,11 +6274,21 @@ static int __net_init ip6_route_net_init
@@ -6241,11 +6277,21 @@ static int __net_init ip6_route_net_init
ip6_template_metrics, true);
INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);
@ -234,7 +234,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
ip6_template_metrics, true);
@@ -6266,6 +6312,8 @@ out:
@@ -6269,6 +6315,8 @@ out:
return ret;
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
out_ip6_prohibit_entry:
kfree(net->ipv6.ip6_prohibit_entry);
out_ip6_null_entry:
@@ -6285,6 +6333,7 @@ static void __net_exit ip6_route_net_exi
@@ -6288,6 +6336,7 @@ static void __net_exit ip6_route_net_exi
kfree(net->ipv6.ip6_null_entry);
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
kfree(net->ipv6.ip6_prohibit_entry);
@ -251,7 +251,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
kfree(net->ipv6.ip6_blk_hole_entry);
#endif
dst_entries_destroy(&net->ipv6.ip6_dst_ops);
@@ -6362,6 +6411,9 @@ void __init ip6_route_init_special_entri
@@ -6365,6 +6414,9 @@ void __init ip6_route_init_special_entri
init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);

2
target/linux/generic/pending-5.4/765-net-dsa-Include-local-addresses-in-assisted-CPU-port.patch
View File

@ -18,7 +18,7 @@ Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -1700,10 +1700,12 @@ static int dsa_slave_switchdev_event(str
@@ -1698,10 +1698,12 @@ static int dsa_slave_switchdev_event(str
fdb_info = ptr;
if (dsa_slave_dev_check(dev)) {

2
target/linux/generic/pending-5.4/766-net-dsa-Include-bridge-addresses-in-assisted-CPU-por.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -1714,7 +1714,11 @@ static int dsa_slave_switchdev_event(str
@@ -1712,7 +1712,11 @@ static int dsa_slave_switchdev_event(str
struct net_device *br_dev;
struct dsa_slave_priv *p;

4
target/linux/generic/pending-5.4/767-net-dsa-Sync-static-FDB-entries-on-foreign-interface.patch
View File

@ -28,7 +28,7 @@ Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -1707,9 +1707,12 @@ static int dsa_slave_switchdev_event(str
@@ -1705,9 +1705,12 @@ static int dsa_slave_switchdev_event(str
else if (!fdb_info->added_by_user)
return NOTIFY_OK;
} else {
@ -44,7 +44,7 @@ Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
*/
struct net_device *br_dev;
struct dsa_slave_priv *p;
@@ -1731,7 +1734,8 @@ static int dsa_slave_switchdev_event(str
@@ -1729,7 +1732,8 @@ static int dsa_slave_switchdev_event(str
dp = p->dp->cpu_dp;

10
target/linux/generic/pending-5.4/800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch
View File

@ -50,20 +50,14 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
if (err)
--- a/drivers/bcma/main.c
+++ b/drivers/bcma/main.c
@@ -236,12 +236,16 @@ EXPORT_SYMBOL(bcma_core_irq);
void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core)
{
+ struct device *dev = &core->dev;
+
core->dev.release = bcma_release_core_dev;
@@ -241,8 +241,10 @@ void bcma_prepare_core(struct bcma_bus *
core->dev.bus = &bcma_bus_type;
dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
core->dev.parent = bus->dev;
- if (bus->dev)
+ if (bus->dev) {
bcma_of_fill_device(bus->dev, core);
+ dma_coerce_mask_and_coherent(dev, bus->dev->coherent_dma_mask);
+ dma_coerce_mask_and_coherent(&core->dev, bus->dev->coherent_dma_mask);
+ }
switch (bus->hosttype) {

6
target/linux/generic/pending-5.4/810-pci_disable_common_quirks.patch
View File

@ -33,7 +33,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
/*
* The Mellanox Tavor device gives false positive parity errors. Mark this
* device with a broken_parity_status to allow PCI scanning code to "skip"
@@ -3322,6 +3323,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
@@ -3323,6 +3324,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
@ -42,7 +42,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
/*
* Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
* To work around this, query the size it should be configured to by the
@@ -3347,6 +3350,8 @@ static void quirk_intel_ntb(struct pci_d
@@ -3348,6 +3351,8 @@ static void quirk_intel_ntb(struct pci_d
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
@ -51,7 +51,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
/*
* Some BIOS implementations leave the Intel GPU interrupts enabled, even
* though no one is handling them (e.g., if the i915 driver is never
@@ -3385,6 +3390,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
@@ -3386,6 +3391,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);

2
target/linux/generic/pending-5.4/811-pci_disable_usb_common_quirks.patch
View File

@ -98,7 +98,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
#endif /* __LINUX_USB_PCI_QUIRKS_H */
--- a/include/linux/usb/hcd.h
+++ b/include/linux/usb/hcd.h
@@ -483,7 +483,14 @@ extern int usb_hcd_pci_probe(struct pci_
@@ -485,7 +485,14 @@ extern int usb_hcd_pci_probe(struct pci_
extern void usb_hcd_pci_remove(struct pci_dev *dev);
extern void usb_hcd_pci_shutdown(struct pci_dev *dev);

8
target/linux/generic/pending-5.4/834-ledtrig-libata.patch
View File

@ -65,7 +65,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
/**
* ata_build_rw_tf - Build ATA taskfile for given read/write request
* @tf: Target ATA taskfile
@@ -5117,6 +5130,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
@@ -5121,6 +5134,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
if (tag < 0)
return NULL;
}
@ -75,7 +75,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
qc = __ata_qc_from_tag(ap, tag);
qc->tag = qc->hw_tag = tag;
@@ -6053,6 +6069,9 @@ struct ata_port *ata_port_alloc(struct a
@@ -6057,6 +6073,9 @@ struct ata_port *ata_port_alloc(struct a
ap->stats.unhandled_irq = 1;
ap->stats.idle_irq = 1;
#endif
@ -85,7 +85,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
ata_sff_port_init(ap);
return ap;
@@ -6088,6 +6107,12 @@ static void ata_host_release(struct kref
@@ -6092,6 +6111,12 @@ static void ata_host_release(struct kref
kfree(ap->pmp_link);
kfree(ap->slave_link);
@ -98,7 +98,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
kfree(ap);
host->ports[i] = NULL;
}
@@ -6551,7 +6576,23 @@ int ata_host_register(struct ata_host *h
@@ -6555,7 +6580,23 @@ int ata_host_register(struct ata_host *h
host->ports[i]->print_id = atomic_inc_return(&ata_print_id);
host->ports[i]->local_port_no = i + 1;
}

453
target/linux/ipq806x/config-5.4
View File

@ -1,453 +0,0 @@
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_AR8216_PHY=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
# CONFIG_ARCH_MDM9615 is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MSM8960=y
CONFIG_ARCH_MSM8974=y
CONFIG_ARCH_MSM8X60=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_CPU_SUSPEND=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_MODULE_PLTS=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
CONFIG_ARM_QCOM_CPUFREQ_KRAIT=y
CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
CONFIG_ARM_QCOM_CPUIDLE=y
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_AT803X_PHY=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_QCOM=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE_OVERRIDE=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_GPIO=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
# CONFIG_DWMAC_GENERIC is not set
CONFIG_DWMAC_IPQ806X=y
# CONFIG_DWMAC_QCOM_ETHQOS is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_ETHERNET_PACKET_MANGLE=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GRO_CELLS=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_HWMON=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_HW_RANDOM=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_QUP=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
# CONFIG_IPQ_GCC_4019 is not set
CONFIG_IPQ_GCC_806X=y
# CONFIG_IPQ_GCC_8074 is not set
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_KPSS_XCC=y
CONFIG_KRAITCC=y
CONFIG_KRAIT_CLOCKS=y
CONFIG_KRAIT_L2_ACCESSORS=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_IPQ8064=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
CONFIG_MEMFD_CREATE=y
CONFIG_MFD_QCOM_RPM=y
# CONFIG_MFD_SPMI_PMIC is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=16
CONFIG_MMC_QCOM_DML=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MSM_GCC_8660=y
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_IOMMU is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_QCOMSMEM_PARTS=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_SPLIT_UIMAGE_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_QCA8K=y
CONFIG_NET_DSA_TAG_QCA=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=2
CONFIG_NVMEM=y
# CONFIG_NVME_TCP is not set
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PAGE_POOL=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DEBUG=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
CONFIG_PHY_QCOM_IPQ806X_SATA=y
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
# CONFIG_PHY_QCOM_QMP is not set
# CONFIG_PHY_QCOM_QUSB2 is not set
# CONFIG_PHY_QCOM_UFS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
# CONFIG_PINCTRL_IPQ4019 is not set
CONFIG_PINCTRL_IPQ8064=y
# CONFIG_PINCTRL_IPQ8074 is not set
# CONFIG_PINCTRL_MDM9615 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
# CONFIG_PINCTRL_MSM8998 is not set
# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_QCS404 is not set
# CONFIG_PINCTRL_SC7180 is not set
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SM8150 is not set
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_MSM=y
CONFIG_POWER_SUPPLY=y
CONFIG_PPS=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK=y
# CONFIG_QCOM_A53PLL is not set
CONFIG_QCOM_ADM=y
CONFIG_QCOM_BAM_DMA=y
CONFIG_QCOM_CLK_RPM=y
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_EBI2 is not set
# CONFIG_QCOM_GENI_SE is not set
CONFIG_QCOM_GSBI=y
CONFIG_QCOM_HFPLL=y
# CONFIG_QCOM_IOMMU is not set
# CONFIG_QCOM_LLCC is not set
# CONFIG_QCOM_PDC is not set
CONFIG_QCOM_PM=y
CONFIG_QCOM_QFPROM=y
# CONFIG_QCOM_RMTFS_MEM is not set
CONFIG_QCOM_RPMCC=y
CONFIG_QCOM_SCM=y
CONFIG_QCOM_SCM_32=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
CONFIG_QCOM_SMEM=y
# CONFIG_QCOM_SMSM is not set
# CONFIG_QCOM_SOCINFO is not set
CONFIG_QCOM_TCSR=y
CONFIG_QCOM_TSENS=y
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_TURING_404 is not set
# CONFIG_QRTR is not set
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REFCOUNT_FULL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_QCOM_RPM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SDM_CAMCC_845 is not set
# CONFIG_SDM_DISPCC_845 is not set
# CONFIG_SDM_GCC_660 is not set
# CONFIG_SDM_GCC_845 is not set
# CONFIG_SDM_GPUCC_845 is not set
# CONFIG_SDM_LPASSCC_845 is not set
# CONFIG_SDM_VIDEOCC_845 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
# CONFIG_SM_GCC_8150 is not set
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_QUP=y
CONFIG_SPMI=y
CONFIG_SPMI_MSM_PMIC_ARB=y
# CONFIG_SPMI_PMIC_CLKDIV is not set
CONFIG_SRCU=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_PLATFORM=y
# CONFIG_STMMAC_SELFTESTS is not set
CONFIG_SWCONFIG=y
CONFIG_SWCONFIG_LEDS=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
# CONFIG_UCLAMP_TASK is not set
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

71
target/linux/ipq806x/patches-5.4/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch
View File

@ -1,71 +0,0 @@
From 28d0ed88f536dd639adf1b0c7c08e04be3c8f294 Mon Sep 17 00:00:00 2001
From: Thomas Pedersen <twp@codeaurora.org>
Date: Mon, 16 May 2016 17:58:50 -0700
Subject: [PATCH 01/69] dtbindings: qcom_adm: Fix channel specifiers
Original patch from Andy Gross.
This patch removes the crci information from the dma
channel property. At least one client device requires
using more than one CRCI value for a channel. This does
not match the current binding and the crci information
needs to be removed.
Instead, the client device will provide this information
via other means.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
---
Documentation/devicetree/bindings/dma/qcom_adm.txt | 16 ++++++----------
1 file changed, 6 insertions(+), 10 deletions(-)
--- a/Documentation/devicetree/bindings/dma/qcom_adm.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt
@@ -4,8 +4,7 @@ Required properties:
- compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
- reg: Address range for DMA registers
- interrupts: Should contain one interrupt shared by all channels
-- #dma-cells: must be <2>. First cell denotes the channel number. Second cell
- denotes CRCI (client rate control interface) flow control assignment.
+- #dma-cells: must be <1>. First cell denotes the channel number.
- clocks: Should contain the core clock and interface clock.
- clock-names: Must contain "core" for the core clock and "iface" for the
interface clock.
@@ -22,7 +21,7 @@ Example:
compatible = "qcom,adm";
reg = <0x18300000 0x100000>;
interrupts = <0 170 0>;
- #dma-cells = <2>;
+ #dma-cells = <1>;
clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
clock-names = "core", "iface";
@@ -35,15 +34,12 @@ Example:
qcom,ee = <0>;
};
-DMA clients must use the format descripted in the dma.txt file, using a three
+DMA clients must use the format descripted in the dma.txt file, using a two
cell specifier for each channel.
-Each dmas request consists of 3 cells:
+Each dmas request consists of two cells:
1. phandle pointing to the DMA controller
2. channel number
- 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0.
- The CRCI is used for flow control. It identifies the peripheral device that
- is the source/destination for the transferred data.
Example:
@@ -55,7 +51,7 @@ Example:
cs-gpios = <&qcom_pinmux 20 0>;
- dmas = <&adm_dma 6 9>,
- <&adm_dma 5 10>;
+ dmas = <&adm_dma 6>,
+ <&adm_dma 5>;
dma-names = "rx", "tx";
};

40
target/linux/ipq806x/patches-5.4/0030-clk-Disable-i2c-device-on-gsbi4.patch
View File

@ -1,40 +0,0 @@
From 0c974b87829e007dc4fae94e20d488204e20e662 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 9 Mar 2017 08:16:10 +0100
Subject: [PATCH 30/69] clk: Disable i2c device on gsbi4
This patch was not annotated and comes from the v4.4 tree.
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/clk/qcom/gcc-ipq806x.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -365,7 +365,7 @@ static struct clk_rcg gsbi1_uart_src = {
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -383,7 +383,7 @@ static struct clk_branch gsbi1_uart_clk
},
.num_parents = 1,
.ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -961,6 +961,7 @@ static struct clk_branch gsbi1_h_clk = {
.hw.init = &(struct clk_init_data){
.name = "gsbi1_h_clk",
.ops = &clk_branch_ops,
+ .flags = CLK_IGNORE_UNUSED,
},
},
};

29
target/linux/ipq806x/patches-5.4/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch
View File

@ -1,29 +0,0 @@
From 48051ece78136e4235a2415a52797db56f8a4478 Mon Sep 17 00:00:00 2001
From: Mathieu Olivari <mathieu@codeaurora.org>
Date: Tue, 21 Apr 2015 19:09:07 -0700
Subject: [PATCH 33/69] ARM: qcom: automatically select PCI_DOMAINS if PCI is
enabled
If multiple PCIe devices are present in the system, the kernel will
panic at boot time when trying to scan the PCI buses. This happens on
IPQ806x based platforms, which has 3 PCIe ports.
Enabling this option allows the kernel to assign the pci-domains
according to the device-tree content. This allows multiple PCIe
controllers to coexist in the system.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
---
arch/arm/mach-qcom/Kconfig | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm/mach-qcom/Kconfig
+++ b/arch/arm/mach-qcom/Kconfig
@@ -7,6 +7,7 @@ menuconfig ARCH_QCOM
select ARM_AMBA
select PINCTRL
select QCOM_SCM if SMP
+ select PCI_DOMAINS if PCI
help
Support for Qualcomm's devicetree based systems.

29
target/linux/ipq806x/patches-5.4/0059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch
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@ -1,29 +0,0 @@
From 04ca10340f1b4d92e849724d322a7ca225d11539 Mon Sep 17 00:00:00 2001
From: Lina Iyer <lina.iyer@linaro.org>
Date: Wed, 25 Mar 2015 14:25:29 -0600
Subject: [PATCH 59/69] ARM: cpuidle: Add cpuidle support for QCOM cpus
Define ARM_QCOM_CPUIDLE config item to enable cpuidle support.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
drivers/cpuidle/Kconfig.arm | 7 +++++++
1 file changed, 7 insertions(+)
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -86,3 +86,10 @@ config ARM_MVEBU_V7_CPUIDLE
depends on ARCH_MVEBU && !ARM64
help
Select this to enable cpuidle on Armada 370, 38x and XP processors.
+
+config ARM_QCOM_CPUIDLE
+ bool "CPU Idle Driver for QCOM processors"
+ depends on ARCH_QCOM
+ select ARM_CPUIDLE
+ help
+ Select this to enable cpuidle on QCOM processors.

62
target/linux/ipq806x/patches-5.4/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch
View File

@ -1,62 +0,0 @@
From fa71139b55e114aa8c3c4823ff8ee7d49ee810d4 Mon Sep 17 00:00:00 2001
From: Mathieu Olivari <mathieu@codeaurora.org>
Date: Wed, 29 Apr 2015 15:21:46 -0700
Subject: [PATCH 60/69] HACK: arch: arm: force ZRELADDR on arch-qcom
ARCH_QCOM is using the ARCH_MULTIPLATFORM option, as now recommended
on most ARM architectures. This automatically calculate ZRELADDR by
masking PHYS_OFFSET with 0xf8000000.
However, on IPQ806x, the first ~20MB of RAM is reserved for the hardware
network accelerators, and the bootloader removes this section from the
layout passed from the ATAGS (when used).
For newer bootloader, when DT is used, this is not a problem, we just
reserve this memory in the device tree. But if the bootloader doesn't
have DT support, then ATAGS have to be used. In this case, the ARM
decompressor will position the kernel in this low mem, which will not be
in the RAM section mapped by the bootloader, which means the kernel will
freeze in the middle of the boot process trying to map the memory.
As a work around, this patch allows disabling AUTO_ZRELADDR when
ARCH_QCOM is selected. It makes the zImage usage possible on bootloaders
which don't support device-tree, which is the case on certain early
IPQ806x based designs.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
---
arch/arm/Kconfig | 2 +-
arch/arm/Makefile | 2 ++
arch/arm/mach-qcom/Makefile.boot | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-qcom/Makefile.boot
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -318,7 +318,7 @@ config ARCH_MULTIPLATFORM
depends on MMU
select ARM_HAS_SG_CHAIN
select ARM_PATCH_PHYS_VIRT
- select AUTO_ZRELADDR
+ select AUTO_ZRELADDR if !ARCH_QCOM
select TIMER_OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -258,9 +258,11 @@ MACHINE := arch/arm/mach-$(word 1,$(mac
else
MACHINE :=
endif
+ifeq ($(CONFIG_ARCH_QCOM),)
ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
MACHINE :=
endif
+endif
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y)))
--- /dev/null
+++ b/arch/arm/mach-qcom/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y+= 0x42208000

616
target/linux/ipq806x/patches-5.4/0063-1-ipq806x-tsens-driver.patch
View File

@ -1,616 +0,0 @@
From 3302e1e1a3cfa4e67fda2a61d6f0c42205d40932 Mon Sep 17 00:00:00 2001
From: Rajith Cherian <rajith@codeaurora.org>
Date: Tue, 14 Feb 2017 18:30:43 +0530
Subject: [PATCH] ipq8064: tsens: Base tsens driver for IPQ8064
Add TSENS driver template to support IPQ8064.
This is a base file copied from tsens-8960.c
Change-Id: I47c573fdfa2d898243c6a6ba952d1632f91391f7
Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
ipq8064: tsens: TSENS driver support for IPQ8064
Support for IPQ8064 tsens driver. The driver works
with the thermal framework. The driver overrides the
following fucntionalities:
1. Get current temperature.
2. Get/Set trip temperatures.
3. Enabled/Disable trip points.
4. ISR for threshold generated interrupt.
5. Notify userspace when trip points are hit.
Change-Id: I8bc7204fd627d10875ab13fc1de8cb6c2ed7a918
Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
---
--- a/drivers/thermal/qcom/Makefile
+++ b/drivers/thermal/qcom/Makefile
@@ -2,5 +2,5 @@
obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o
qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o \
- tsens-8960.o tsens-v2.o tsens-v1.o
+ tsens-8960.o tsens-v2.o tsens-v1.o tsens-ipq8064.o
obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o
--- /dev/null
+++ b/drivers/thermal/qcom/tsens-ipq8064.c
@@ -0,0 +1,551 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+#include <linux/regmap.h>
+#include <linux/thermal.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include "tsens.h"
+
+#define CAL_MDEGC 30000
+
+#define CONFIG_ADDR 0x3640
+/* CONFIG_ADDR bitmasks */
+#define CONFIG 0x9b
+#define CONFIG_MASK 0xf
+#define CONFIG_SHIFT 0
+
+#define STATUS_CNTL_8064 0x3660
+#define CNTL_ADDR 0x3620
+/* CNTL_ADDR bitmasks */
+#define EN BIT(0)
+#define SW_RST BIT(1)
+#define SENSOR0_EN BIT(3)
+#define SLP_CLK_ENA BIT(26)
+#define MEASURE_PERIOD 1
+#define SENSOR0_SHIFT 3
+
+/* INT_STATUS_ADDR bitmasks */
+#define MIN_STATUS_MASK BIT(0)
+#define LOWER_STATUS_CLR BIT(1)
+#define UPPER_STATUS_CLR BIT(2)
+#define MAX_STATUS_MASK BIT(3)
+
+#define THRESHOLD_ADDR 0x3624
+/* THRESHOLD_ADDR bitmasks */
+#define THRESHOLD_MAX_CODE 0x20000
+#define THRESHOLD_MIN_CODE 0
+#define THRESHOLD_MAX_LIMIT_SHIFT 24
+#define THRESHOLD_MIN_LIMIT_SHIFT 16
+#define THRESHOLD_UPPER_LIMIT_SHIFT 8
+#define THRESHOLD_LOWER_LIMIT_SHIFT 0
+#define THRESHOLD_MAX_LIMIT_MASK (THRESHOLD_MAX_CODE << \
+ THRESHOLD_MAX_LIMIT_SHIFT)
+#define THRESHOLD_MIN_LIMIT_MASK (THRESHOLD_MAX_CODE << \
+ THRESHOLD_MIN_LIMIT_SHIFT)
+#define THRESHOLD_UPPER_LIMIT_MASK (THRESHOLD_MAX_CODE << \
+ THRESHOLD_UPPER_LIMIT_SHIFT)
+#define THRESHOLD_LOWER_LIMIT_MASK (THRESHOLD_MAX_CODE << \
+ THRESHOLD_LOWER_LIMIT_SHIFT)
+
+/* Initial temperature threshold values */
+#define LOWER_LIMIT_TH 0x9d /* 95C */
+#define UPPER_LIMIT_TH 0xa6 /* 105C */
+#define MIN_LIMIT_TH 0x0
+#define MAX_LIMIT_TH 0xff
+
+#define S0_STATUS_ADDR 0x3628
+#define STATUS_ADDR_OFFSET 2
+#define SENSOR_STATUS_SIZE 4
+#define INT_STATUS_ADDR 0x363c
+#define TRDY_MASK BIT(7)
+#define TIMEOUT_US 100
+
+#define TSENS_EN BIT(0)
+#define TSENS_SW_RST BIT(1)
+#define TSENS_ADC_CLK_SEL BIT(2)
+#define SENSOR0_EN BIT(3)
+#define SENSOR1_EN BIT(4)
+#define SENSOR2_EN BIT(5)
+#define SENSOR3_EN BIT(6)
+#define SENSOR4_EN BIT(7)
+#define SENSORS_EN (SENSOR0_EN | SENSOR1_EN | \
+ SENSOR2_EN | SENSOR3_EN | SENSOR4_EN)
+#define TSENS_8064_SENSOR5_EN BIT(8)
+#define TSENS_8064_SENSOR6_EN BIT(9)
+#define TSENS_8064_SENSOR7_EN BIT(10)
+#define TSENS_8064_SENSOR8_EN BIT(11)
+#define TSENS_8064_SENSOR9_EN BIT(12)
+#define TSENS_8064_SENSOR10_EN BIT(13)
+#define TSENS_8064_SENSORS_EN (SENSORS_EN | \
+ TSENS_8064_SENSOR5_EN | \
+ TSENS_8064_SENSOR6_EN | \
+ TSENS_8064_SENSOR7_EN | \
+ TSENS_8064_SENSOR8_EN | \
+ TSENS_8064_SENSOR9_EN | \
+ TSENS_8064_SENSOR10_EN)
+
+#define TSENS_8064_SEQ_SENSORS 5
+#define TSENS_8064_S4_S5_OFFSET 40
+#define TSENS_FACTOR 1
+
+/* Trips: from very hot to very cold */
+enum tsens_trip_type {
+ TSENS_TRIP_STAGE3 = 0,
+ TSENS_TRIP_STAGE2,
+ TSENS_TRIP_STAGE1,
+ TSENS_TRIP_STAGE0,
+ TSENS_TRIP_NUM,
+};
+
+u32 tsens_8064_slope[] = {
+ 1176, 1176, 1154, 1176,
+ 1111, 1132, 1132, 1199,
+ 1132, 1199, 1132
+ };
+
+/* Temperature on y axis and ADC-code on x-axis */
+static inline int code_to_degC(u32 adc_code, const struct tsens_sensor *s)
+{
+ int degcbeforefactor, degc;
+
+ degcbeforefactor = (adc_code * s->slope) + s->offset;
+
+ if (degcbeforefactor == 0)
+ degc = degcbeforefactor;
+ else if (degcbeforefactor > 0)
+ degc = (degcbeforefactor + TSENS_FACTOR/2)
+ / TSENS_FACTOR;
+ else
+ degc = (degcbeforefactor - TSENS_FACTOR/2)
+ / TSENS_FACTOR;
+
+ return degc;
+}
+
+static int degC_to_code(int degC, const struct tsens_sensor *s)
+{
+ int code = ((degC * TSENS_FACTOR - s->offset) + (s->slope/2))
+ / s->slope;
+
+ if (code > THRESHOLD_MAX_CODE)
+ code = THRESHOLD_MAX_CODE;
+ else if (code < THRESHOLD_MIN_CODE)
+ code = THRESHOLD_MIN_CODE;
+ return code;
+}
+
+static int suspend_ipq8064(struct tsens_priv *priv)
+{
+ int ret;
+ unsigned int mask;
+ struct regmap *map = priv->tm_map;
+
+ ret = regmap_read(map, THRESHOLD_ADDR, &priv->ctx.threshold);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(map, CNTL_ADDR, &priv->ctx.control);
+ if (ret)
+ return ret;
+
+ mask = SLP_CLK_ENA | EN;
+
+ ret = regmap_update_bits(map, CNTL_ADDR, mask, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int resume_ipq8064(struct tsens_priv *priv)
+{
+ int ret;
+ struct regmap *map = priv->tm_map;
+
+ ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(map, THRESHOLD_ADDR, priv->ctx.threshold);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(map, CNTL_ADDR, priv->ctx.control);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void notify_uspace_tsens_fn(struct work_struct *work)
+{
+ struct tsens_sensor *s = container_of(work, struct tsens_sensor,
+ notify_work);
+
+ sysfs_notify(&s->tzd->device.kobj, NULL, "type");
+}
+
+static void tsens_scheduler_fn(struct work_struct *work)
+{
+ struct tsens_priv *priv = container_of(work, struct tsens_priv,
+ tsens_work);
+ unsigned int threshold, threshold_low, code, reg, sensor, mask;
+ unsigned int sensor_addr;
+ bool upper_th_x, lower_th_x;
+ int adc_code, ret;
+
+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg);
+ if (ret)
+ return;
+ reg = reg | LOWER_STATUS_CLR | UPPER_STATUS_CLR;
+ ret = regmap_write(priv->tm_map, STATUS_CNTL_8064, reg);
+ if (ret)
+ return;
+
+ mask = ~(LOWER_STATUS_CLR | UPPER_STATUS_CLR);
+ ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, &threshold);
+ if (ret)
+ return;
+ threshold_low = (threshold & THRESHOLD_LOWER_LIMIT_MASK)
+ >> THRESHOLD_LOWER_LIMIT_SHIFT;
+ threshold = (threshold & THRESHOLD_UPPER_LIMIT_MASK)
+ >> THRESHOLD_UPPER_LIMIT_SHIFT;
+
+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg);
+ if (ret)
+ return;
+
+ ret = regmap_read(priv->tm_map, CNTL_ADDR, &sensor);
+ if (ret)
+ return;
+ sensor &= (uint32_t) TSENS_8064_SENSORS_EN;
+ sensor >>= SENSOR0_SHIFT;
+
+ /* Constraint: There is only 1 interrupt control register for all
+ * 11 temperature sensor. So monitoring more than 1 sensor based
+ * on interrupts will yield inconsistent result. To overcome this
+ * issue we will monitor only sensor 0 which is the master sensor.
+ */
+
+ /* Skip if the sensor is disabled */
+ if (sensor & 1) {
+ ret = regmap_read(priv->tm_map, priv->sensor[0].status, &code);
+ if (ret)
+ return;
+ upper_th_x = code >= threshold;
+ lower_th_x = code <= threshold_low;
+ if (upper_th_x)
+ mask |= UPPER_STATUS_CLR;
+ if (lower_th_x)
+ mask |= LOWER_STATUS_CLR;
+ if (upper_th_x || lower_th_x) {
+ /* Notify user space */
+ schedule_work(&priv->sensor[0].notify_work);
+ regmap_read(priv->tm_map, sensor_addr, &adc_code);
+ pr_debug("Trigger (%d degrees) for sensor %d\n",
+ code_to_degC(adc_code, &priv->sensor[0]), 0);
+ }
+ }
+ regmap_write(priv->tm_map, STATUS_CNTL_8064, reg & mask);
+
+ /* force memory to sync */
+ mb();
+}
+
+static irqreturn_t tsens_isr(int irq, void *data)
+{
+ struct tsens_priv *priv = data;
+
+ schedule_work(&priv->tsens_work);
+ return IRQ_HANDLED;
+}
+
+static void hw_init(struct tsens_priv *priv)
+{
+ int ret;
+ unsigned int reg_cntl = 0, reg_cfg = 0, reg_thr = 0;
+ unsigned int reg_status_cntl = 0;
+
+ regmap_read(priv->tm_map, CNTL_ADDR, &reg_cntl);
+ regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl | TSENS_SW_RST);
+
+ reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18)
+ | (((1 << priv->num_sensors) - 1) << SENSOR0_SHIFT);
+ regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
+ regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg_status_cntl);
+ reg_status_cntl |= LOWER_STATUS_CLR | UPPER_STATUS_CLR
+ | MIN_STATUS_MASK | MAX_STATUS_MASK;
+ regmap_write(priv->tm_map, STATUS_CNTL_8064, reg_status_cntl);
+ reg_cntl |= TSENS_EN;
+ regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
+
+ regmap_read(priv->tm_map, CONFIG_ADDR, &reg_cfg);
+ reg_cfg = (reg_cfg & ~CONFIG_MASK) | (CONFIG << CONFIG_SHIFT);
+ regmap_write(priv->tm_map, CONFIG_ADDR, reg_cfg);
+
+ reg_thr |= (LOWER_LIMIT_TH << THRESHOLD_LOWER_LIMIT_SHIFT)
+ | (UPPER_LIMIT_TH << THRESHOLD_UPPER_LIMIT_SHIFT)
+ | (MIN_LIMIT_TH << THRESHOLD_MIN_LIMIT_SHIFT)
+ | (MAX_LIMIT_TH << THRESHOLD_MAX_LIMIT_SHIFT);
+
+ regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_thr);
+
+ ret = devm_request_irq(priv->dev, priv->tsens_irq, tsens_isr,
+ IRQF_TRIGGER_RISING, "tsens_interrupt", priv);
+ if (ret < 0) {
+ pr_err("%s: request_irq FAIL: %d\n", __func__, ret);
+ return;
+ }
+
+ INIT_WORK(&priv->tsens_work, tsens_scheduler_fn);
+}
+
+static int init_ipq8064(struct tsens_priv *priv)
+{
+ int ret, i;
+ u32 reg_cntl, offset = 0;
+
+ init_common(priv);
+ if (!priv->tm_map)
+ return -ENODEV;
+
+ /*
+ * The status registers for each sensor are discontiguous
+ * because some SoCs have 5 sensors while others have more
+ * but the control registers stay in the same place, i.e
+ * directly after the first 5 status registers.
+ */
+ for (i = 0; i < priv->num_sensors; i++) {
+ if (i >= TSENS_8064_SEQ_SENSORS)
+ offset = TSENS_8064_S4_S5_OFFSET;
+
+ priv->sensor[i].status = S0_STATUS_ADDR + offset
+ + (i << STATUS_ADDR_OFFSET);
+ priv->sensor[i].slope = tsens_8064_slope[i];
+ INIT_WORK(&priv->sensor[i].notify_work,
+ notify_uspace_tsens_fn);
+ }
+
+ reg_cntl = SW_RST;
+ ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl);
+ if (ret)
+ return ret;
+
+ reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
+ reg_cntl &= ~SW_RST;
+ ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR,
+ CONFIG_MASK, CONFIG);
+
+ reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;
+ ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
+ if (ret)
+ return ret;
+
+ reg_cntl |= EN;
+ ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int calibrate_ipq8064(struct tsens_priv *priv)
+{
+ int i;
+ char *data, *data_backup;
+
+ ssize_t num_read = priv->num_sensors;
+ struct tsens_sensor *s = priv->sensor;
+
+ data = qfprom_read(priv->dev, "calib");
+ if (IS_ERR(data)) {
+ pr_err("Calibration not found.\n");
+ return PTR_ERR(data);
+ }
+
+ data_backup = qfprom_read(priv->dev, "calib_backup");
+ if (IS_ERR(data_backup)) {
+ pr_err("Backup calibration not found.\n");
+ return PTR_ERR(data_backup);
+ }
+
+ for (i = 0; i < num_read; i++) {
+ s[i].calib_data = readb_relaxed(data + i);
+ s[i].calib_data_backup = readb_relaxed(data_backup + i);
+
+ if (s[i].calib_data_backup)
+ s[i].calib_data = s[i].calib_data_backup;
+ if (!s[i].calib_data) {
+ pr_err("QFPROM TSENS calibration data not present\n");
+ return -ENODEV;
+ }
+ s[i].slope = tsens_8064_slope[i];
+ s[i].offset = CAL_MDEGC - (s[i].calib_data * s[i].slope);
+ }
+
+ hw_init(priv);
+
+ return 0;
+}
+
+static int get_temp_ipq8064(struct tsens_priv *priv, int id, int *temp)
+{
+ int ret;
+ u32 code, trdy;
+ const struct tsens_sensor *s = &priv->sensor[id];
+ unsigned long timeout;
+
+ timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
+ do {
+ ret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy);
+ if (ret)
+ return ret;
+ if (!(trdy & TRDY_MASK))
+ continue;
+ ret = regmap_read(priv->tm_map, s->status, &code);
+ if (ret)
+ return ret;
+ *temp = code_to_degC(code, s);
+ return 0;
+ } while (time_before(jiffies, timeout));
+
+ return -ETIMEDOUT;
+}
+
+static int set_trip_temp_ipq8064(void *data, int trip, int temp)
+{
+ unsigned int reg_th, reg_cntl;
+ int ret, code, code_chk, hi_code, lo_code;
+ const struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
+
+ code_chk = code = degC_to_code(temp, s);
+
+ if (code < THRESHOLD_MIN_CODE || code > THRESHOLD_MAX_CODE)
+ return -EINVAL;
+
+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg_cntl);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, &reg_th);
+ if (ret)
+ return ret;
+
+ hi_code = (reg_th & THRESHOLD_UPPER_LIMIT_MASK)
+ >> THRESHOLD_UPPER_LIMIT_SHIFT;
+ lo_code = (reg_th & THRESHOLD_LOWER_LIMIT_MASK)
+ >> THRESHOLD_LOWER_LIMIT_SHIFT;
+
+ switch (trip) {
+ case TSENS_TRIP_STAGE3:
+ code <<= THRESHOLD_MAX_LIMIT_SHIFT;
+ reg_th &= ~THRESHOLD_MAX_LIMIT_MASK;
+ break;
+ case TSENS_TRIP_STAGE2:
+ if (code_chk <= lo_code)
+ return -EINVAL;
+ code <<= THRESHOLD_UPPER_LIMIT_SHIFT;
+ reg_th &= ~THRESHOLD_UPPER_LIMIT_MASK;
+ break;
+ case TSENS_TRIP_STAGE1:
+ if (code_chk >= hi_code)
+ return -EINVAL;
+ code <<= THRESHOLD_LOWER_LIMIT_SHIFT;
+ reg_th &= ~THRESHOLD_LOWER_LIMIT_MASK;
+ break;
+ case TSENS_TRIP_STAGE0:
+ code <<= THRESHOLD_MIN_LIMIT_SHIFT;
+ reg_th &= ~THRESHOLD_MIN_LIMIT_MASK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_th | code);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int set_trip_activate_ipq8064(void *data, int trip,
+ enum thermal_trip_activation_mode mode)
+{
+ unsigned int reg_cntl, mask, val;
+ const struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
+ int ret;
+
+ if (!priv || trip < 0)
+ return -EINVAL;
+
+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg_cntl);
+ if (ret)
+ return ret;
+
+ switch (trip) {
+ case TSENS_TRIP_STAGE3:
+ mask = MAX_STATUS_MASK;
+ break;
+ case TSENS_TRIP_STAGE2:
+ mask = UPPER_STATUS_CLR;
+ break;
+ case TSENS_TRIP_STAGE1:
+ mask = LOWER_STATUS_CLR;
+ break;
+ case TSENS_TRIP_STAGE0:
+ mask = MIN_STATUS_MASK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (mode == THERMAL_TRIP_ACTIVATION_DISABLED)
+ val = reg_cntl | mask;
+ else
+ val = reg_cntl & ~mask;
+
+ ret = regmap_write(priv->tm_map, STATUS_CNTL_8064, val);
+ if (ret)
+ return ret;
+
+ /* force memory to sync */
+ mb();
+ return 0;
+}
+
+const struct tsens_ops ops_ipq8064 = {
+ .init = init_ipq8064,
+ .calibrate = calibrate_ipq8064,
+ .get_temp = get_temp_ipq8064,
+ .suspend = suspend_ipq8064,
+ .resume = resume_ipq8064,
+ .set_trip_temp = set_trip_temp_ipq8064,
+ .set_trip_activate = set_trip_activate_ipq8064,
+};
+
+const struct tsens_plat_data data_ipq8064 = {
+ .num_sensors = 11,
+ .ops = &ops_ipq8064,
+};
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -69,8 +69,11 @@ static const struct of_device_id tsens_t
}, {
.compatible = "qcom,tsens-v2",
.data = &data_tsens_v2,
+ }, {
+ .compatible = "qcom,ipq8064-tsens",
+ .data = &data_ipq8064,
},
- {}
+ {}
};
MODULE_DEVICE_TABLE(of, tsens_table);
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -324,7 +324,7 @@ extern const struct tsens_plat_data data
extern const struct tsens_plat_data data_8916, data_8974;
/* TSENS v1 targets */
-extern const struct tsens_plat_data data_tsens_v1;
+extern const struct tsens_plat_data data_tsens_v1, data_ipq8064;
/* TSENS v2 targets */
extern const struct tsens_plat_data data_8996, data_tsens_v2;

437
target/linux/ipq806x/patches-5.4/0063-2-tsens-support-configurable-interrupts.patch
View File

@ -1,437 +0,0 @@
From 4e87400732c77765afae2ea89ed43837457aa604 Mon Sep 17 00:00:00 2001
From: Rajith Cherian <rajith@codeaurora.org>
Date: Wed, 1 Feb 2017 19:00:26 +0530
Subject: [PATCH] ipq8064: tsens: Support for configurable interrupts
Provide support for adding configurable high and
configurable low trip temperatures. An interrupts is
also triggerred when these trip points are hit. The
interrupts can be activated or deactivated from sysfs.
This functionality is made available only if
CONFIG_THERMAL_WRITABLE_TRIPS is defined.
Change-Id: Ib73f3f9459de4fffce7bb985a0312a88291f4934
Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
---
.../devicetree/bindings/thermal/qcom-tsens.txt | 4 ++
drivers/thermal/of-thermal.c | 63 ++++++++++++++++++----
drivers/thermal/qcom/tsens.c | 43 ++++++++++++---
drivers/thermal/qcom/tsens.h | 11 ++++
drivers/thermal/thermal_core.c | 44 ++++++++++++++-
include/linux/thermal.h | 14 +++++
6 files changed, 162 insertions(+), 17 deletions(-)
--- a/drivers/thermal/of-thermal.c
+++ b/drivers/thermal/of-thermal.c
@@ -91,7 +91,7 @@ static int of_thermal_get_temp(struct th
{
struct __thermal_zone *data = tz->devdata;
- if (!data->ops->get_temp)
+ if (!data->ops->get_temp || (data->mode == THERMAL_DEVICE_DISABLED))
return -EINVAL;
return data->ops->get_temp(data->sensor_data, temp);
@@ -102,7 +102,8 @@ static int of_thermal_set_trips(struct t
{
struct __thermal_zone *data = tz->devdata;
- if (!data->ops || !data->ops->set_trips)
+ if (!data->ops || !data->ops->set_trips
+ || (data->mode == THERMAL_DEVICE_DISABLED))
return -EINVAL;
return data->ops->set_trips(data->sensor_data, low, high);
@@ -188,6 +189,9 @@ static int of_thermal_set_emul_temp(stru
{
struct __thermal_zone *data = tz->devdata;
+ if (data->mode == THERMAL_DEVICE_DISABLED)
+ return -EINVAL;
+
return data->ops->set_emul_temp(data->sensor_data, temp);
}
@@ -196,7 +200,7 @@ static int of_thermal_get_trend(struct t
{
struct __thermal_zone *data = tz->devdata;
- if (!data->ops->get_trend)
+ if (!data->ops->get_trend || (data->mode == THERMAL_DEVICE_DISABLED))
return -EINVAL;
return data->ops->get_trend(data->sensor_data, trip, trend);
@@ -297,7 +301,9 @@ static int of_thermal_set_mode(struct th
mutex_unlock(&tz->lock);
data->mode = mode;
- thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED);
+
+ if (mode == THERMAL_DEVICE_ENABLED)
+ thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED);
return 0;
}
@@ -307,7 +313,8 @@ static int of_thermal_get_trip_type(stru
{
struct __thermal_zone *data = tz->devdata;
- if (trip >= data->ntrips || trip < 0)
+ if (trip >= data->ntrips || trip < 0
+ || (data->mode == THERMAL_DEVICE_DISABLED))
return -EDOM;
*type = data->trips[trip].type;
@@ -315,12 +322,39 @@ static int of_thermal_get_trip_type(stru
return 0;
}
+static int of_thermal_activate_trip_type(struct thermal_zone_device *tz,
+ int trip, enum thermal_trip_activation_mode mode)
+{
+ struct __thermal_zone *data = tz->devdata;
+
+ if (trip >= data->ntrips || trip < 0
+ || (data->mode == THERMAL_DEVICE_DISABLED))
+ return -EDOM;
+
+ /*
+ * The configurable_hi and configurable_lo trip points can be
+ * activated and deactivated.
+ */
+
+ if (data->ops->set_trip_activate) {
+ int ret;
+
+ ret = data->ops->set_trip_activate(data->sensor_data,
+ trip, mode);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int of_thermal_get_trip_temp(struct thermal_zone_device *tz, int trip,
int *temp)
{
struct __thermal_zone *data = tz->devdata;
- if (trip >= data->ntrips || trip < 0)
+ if (trip >= data->ntrips || trip < 0
+ || (data->mode == THERMAL_DEVICE_DISABLED))
return -EDOM;
*temp = data->trips[trip].temperature;
@@ -333,7 +367,8 @@ static int of_thermal_set_trip_temp(stru
{
struct __thermal_zone *data = tz->devdata;
- if (trip >= data->ntrips || trip < 0)
+ if (trip >= data->ntrips || trip < 0
+ || (data->mode == THERMAL_DEVICE_DISABLED))
return -EDOM;
if (data->ops->set_trip_temp) {
@@ -355,7 +390,8 @@ static int of_thermal_get_trip_hyst(stru
{
struct __thermal_zone *data = tz->devdata;
- if (trip >= data->ntrips || trip < 0)
+ if (trip >= data->ntrips || trip < 0
+ || (data->mode == THERMAL_DEVICE_DISABLED))
return -EDOM;
*hyst = data->trips[trip].hysteresis;
@@ -368,7 +404,8 @@ static int of_thermal_set_trip_hyst(stru
{
struct __thermal_zone *data = tz->devdata;
- if (trip >= data->ntrips || trip < 0)
+ if (trip >= data->ntrips || trip < 0
+ || (data->mode == THERMAL_DEVICE_DISABLED))
return -EDOM;
/* thermal framework should take care of data->mask & (1 << trip) */
@@ -443,6 +480,9 @@ thermal_zone_of_add_sensor(struct device
if (ops->set_emul_temp)
tzd->ops->set_emul_temp = of_thermal_set_emul_temp;
+ if (ops->set_trip_activate)
+ tzd->ops->set_trip_activate = of_thermal_activate_trip_type;
+
mutex_unlock(&tzd->lock);
return tzd;
@@ -765,7 +805,10 @@ static const char * const trip_types[] =
[THERMAL_TRIP_ACTIVE] = "active",
[THERMAL_TRIP_PASSIVE] = "passive",
[THERMAL_TRIP_HOT] = "hot",
- [THERMAL_TRIP_CRITICAL] = "critical",
+ [THERMAL_TRIP_CRITICAL] = "critical_high",
+ [THERMAL_TRIP_CONFIGURABLE_HI] = "configurable_hi",
+ [THERMAL_TRIP_CONFIGURABLE_LOW] = "configurable_lo",
+ [THERMAL_TRIP_CRITICAL_LOW] = "critical_low",
};
/**
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -22,7 +22,7 @@ static int tsens_get_temp(void *data, in
static int tsens_get_trend(void *data, int trip, enum thermal_trend *trend)
{
- const struct tsens_sensor *s = data;
+ struct tsens_sensor *s = data;
struct tsens_priv *priv = s->priv;
if (priv->ops->get_trend)
@@ -31,9 +31,10 @@ static int tsens_get_trend(void *data, i
return -ENOTSUPP;
}
-static int __maybe_unused tsens_suspend(struct device *dev)
+static int __maybe_unused tsens_suspend(void *data)
{
- struct tsens_priv *priv = dev_get_drvdata(dev);
+ struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
if (priv->ops && priv->ops->suspend)
return priv->ops->suspend(priv);
@@ -41,9 +42,10 @@ static int __maybe_unused tsens_suspend
return 0;
}
-static int __maybe_unused tsens_resume(struct device *dev)
+static int __maybe_unused tsens_resume(void *data)
{
- struct tsens_priv *priv = dev_get_drvdata(dev);
+ struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
if (priv->ops && priv->ops->resume)
return priv->ops->resume(priv);
@@ -51,6 +53,30 @@ static int __maybe_unused tsens_resume(s
return 0;
}
+static int __maybe_unused tsens_set_trip_temp(void *data, int trip, int temp)
+{
+ struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
+
+ if (priv->ops && priv->ops->set_trip_temp)
+ return priv->ops->set_trip_temp(s, trip, temp);
+
+ return 0;
+}
+
+static int __maybe_unused tsens_activate_trip_type(void *data, int trip,
+ enum thermal_trip_activation_mode mode)
+{
+ struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
+
+ if (priv->ops && priv->ops->set_trip_activate)
+ return priv->ops->set_trip_activate(s, trip, mode);
+
+ return 0;
+}
+
+
static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume);
static const struct of_device_id tsens_table[] = {
@@ -80,6 +106,8 @@ MODULE_DEVICE_TABLE(of, tsens_table);
static const struct thermal_zone_of_device_ops tsens_of_ops = {
.get_temp = tsens_get_temp,
.get_trend = tsens_get_trend,
+ .set_trip_temp = tsens_set_trip_temp,
+ .set_trip_activate = tsens_activate_trip_type,
};
static int tsens_register(struct tsens_priv *priv)
@@ -123,7 +151,7 @@ static int tsens_probe(struct platform_d
if (id)
data = id->data;
else
- data = &data_8960;
+ return -EINVAL;
num_sensors = data->num_sensors;
@@ -144,6 +172,9 @@ static int tsens_probe(struct platform_d
priv->dev = dev;
priv->num_sensors = num_sensors;
priv->ops = data->ops;
+
+ priv->tsens_irq = platform_get_irq(pdev, 0);
+
for (i = 0; i < priv->num_sensors; i++) {
if (data->hw_ids)
priv->sensor[i].hw_id = data->hw_ids[i];
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -40,9 +40,12 @@ enum tsens_ver {
struct tsens_sensor {
struct tsens_priv *priv;
struct thermal_zone_device *tzd;
+ struct work_struct notify_work;
int offset;
unsigned int id;
unsigned int hw_id;
+ int calib_data;
+ int calib_data_backup;
int slope;
u32 status;
};
@@ -57,6 +60,9 @@ struct tsens_sensor {
* @suspend: Function to suspend the tsens device
* @resume: Function to resume the tsens device
* @get_trend: Function to get the thermal/temp trend
+ * @set_trip_temp: Function to set trip temp
+ * @get_trip_temp: Function to get trip temp
+ * @set_trip_activate: Function to activate trip points
*/
struct tsens_ops {
/* mandatory callbacks */
@@ -69,6 +75,9 @@ struct tsens_ops {
int (*suspend)(struct tsens_priv *priv);
int (*resume)(struct tsens_priv *priv);
int (*get_trend)(struct tsens_priv *priv, int i, enum thermal_trend *trend);
+ int (*set_trip_temp)(void *data, int trip, int temp);
+ int (*set_trip_activate)(void *data, int trip,
+ enum thermal_trip_activation_mode mode);
};
#define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
@@ -300,6 +309,7 @@ struct tsens_context {
struct tsens_priv {
struct device *dev;
u32 num_sensors;
+ u32 tsens_irq;
struct regmap *tm_map;
struct regmap *srot_map;
u32 tm_offset;
@@ -308,6 +318,7 @@ struct tsens_priv {
const struct tsens_features *feat;
const struct reg_field *fields;
const struct tsens_ops *ops;
+ struct work_struct tsens_work;
struct tsens_sensor sensor[0];
};
--- a/drivers/thermal/thermal_sysfs.c
+++ b/drivers/thermal/thermal_sysfs.c
@@ -113,12 +113,48 @@ trip_point_type_show(struct device *dev,
return sprintf(buf, "passive\n");
case THERMAL_TRIP_ACTIVE:
return sprintf(buf, "active\n");
+ case THERMAL_TRIP_CONFIGURABLE_HI:
+ return sprintf(buf, "configurable_hi\n");
+ case THERMAL_TRIP_CONFIGURABLE_LOW:
+ return sprintf(buf, "configurable_low\n");
+ case THERMAL_TRIP_CRITICAL_LOW:
+ return sprintf(buf, "critical_low\n");
default:
return sprintf(buf, "unknown\n");
}
}
static ssize_t
+trip_point_type_activate(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct thermal_zone_device *tz = to_thermal_zone(dev);
+ int trip, ret;
+ char *enabled = "enabled";
+ char *disabled = "disabled";
+
+ if (!tz->ops->set_trip_activate)
+ return -EPERM;
+
+ if (!sscanf(attr->attr.name, "trip_point_%d_type", &trip))
+ return -EINVAL;
+
+ if (!strncmp(buf, enabled, strlen(enabled)))
+ ret = tz->ops->set_trip_activate(tz, trip,
+ THERMAL_TRIP_ACTIVATION_ENABLED);
+ else if (!strncmp(buf, disabled, strlen(disabled)))
+ ret = tz->ops->set_trip_activate(tz, trip,
+ THERMAL_TRIP_ACTIVATION_DISABLED);
+ else
+ ret = -EINVAL;
+
+ if (ret)
+ return ret;
+
+ return count;
+}
+
+static ssize_t
trip_point_temp_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
@@ -559,6 +595,12 @@ static int create_trip_attrs(struct ther
tz->trip_type_attrs[indx].attr.show = trip_point_type_show;
attrs[indx] = &tz->trip_type_attrs[indx].attr.attr;
+ if (IS_ENABLED(CONFIG_THERMAL_WRITABLE_TRIPS)) {
+ tz->trip_type_attrs[indx].attr.store
+ = trip_point_type_activate;
+ tz->trip_type_attrs[indx].attr.attr.mode |= S_IWUSR;
+ }
+
/* create trip temp attribute */
snprintf(tz->trip_temp_attrs[indx].name, THERMAL_NAME_LENGTH,
"trip_point_%d_temp", indx);
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
@@ -63,11 +63,19 @@ enum thermal_device_mode {
THERMAL_DEVICE_ENABLED,
};
+enum thermal_trip_activation_mode {
+ THERMAL_TRIP_ACTIVATION_DISABLED = 0,
+ THERMAL_TRIP_ACTIVATION_ENABLED,
+};
+
enum thermal_trip_type {
THERMAL_TRIP_ACTIVE = 0,
THERMAL_TRIP_PASSIVE,
THERMAL_TRIP_HOT,
THERMAL_TRIP_CRITICAL,
+ THERMAL_TRIP_CONFIGURABLE_HI,
+ THERMAL_TRIP_CONFIGURABLE_LOW,
+ THERMAL_TRIP_CRITICAL_LOW,
};
enum thermal_trend {
@@ -105,6 +113,8 @@ struct thermal_zone_device_ops {
enum thermal_trip_type *);
int (*get_trip_temp) (struct thermal_zone_device *, int, int *);
int (*set_trip_temp) (struct thermal_zone_device *, int, int);
+ int (*set_trip_activate) (struct thermal_zone_device *, int,
+ enum thermal_trip_activation_mode);
int (*get_trip_hyst) (struct thermal_zone_device *, int, int *);
int (*set_trip_hyst) (struct thermal_zone_device *, int, int);
int (*get_crit_temp) (struct thermal_zone_device *, int *);
@@ -349,6 +359,8 @@ struct thermal_genl_event {
* temperature.
* @set_trip_temp: a pointer to a function that sets the trip temperature on
* hardware.
+ * @activate_trip_type: a pointer to a function to enable/disable trip
+ * temperature interrupts
*/
struct thermal_zone_of_device_ops {
int (*get_temp)(void *, int *);
@@ -356,6 +368,8 @@ struct thermal_zone_of_device_ops {
int (*set_trips)(void *, int, int);
int (*set_emul_temp)(void *, int);
int (*set_trip_temp)(void *, int, int);
+ int (*set_trip_activate)(void *, int,
+ enum thermal_trip_activation_mode);
};
/**

68
target/linux/ipq806x/patches-5.4/0063-3-tsens-fix-kernel-5_4.patch
View File

@ -1,68 +0,0 @@
--- a/drivers/thermal/qcom/tsens-ipq8064.c
+++ b/drivers/thermal/qcom/tsens-ipq8064.c
@@ -18,6 +18,7 @@
#include <linux/regmap.h>
#include <linux/thermal.h>
#include <linux/nvmem-consumer.h>
+#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include "tsens.h"
@@ -320,15 +321,42 @@ static void hw_init(struct tsens_priv *p
INIT_WORK(&priv->tsens_work, tsens_scheduler_fn);
}
+static const struct regmap_config tsens_config = {
+ .name = "tm",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
static int init_ipq8064(struct tsens_priv *priv)
{
- int ret, i;
+ struct device *dev = priv->dev;
u32 reg_cntl, offset = 0;
+ struct resource *res;
+ resource_size_t size;
+ void __iomem *base;
+ int ret, i;
+ struct platform_device *op = of_find_device_by_node(priv->dev->of_node);
+
+ if (!op)
+ return -EINVAL;
- init_common(priv);
- if (!priv->tm_map)
- return -ENODEV;
+ /* old DTs where SROT and TM were in a contiguous 2K block */
+ priv->tm_offset = 0x1000;
+ res = platform_get_resource(op, IORESOURCE_MEM, 0);
+ size = resource_size(res);
+ base = devm_ioremap(&op->dev, res->start, size);
+ if (IS_ERR(base)) {
+ ret = PTR_ERR(base);
+ goto err_put_device;
+ }
+
+ priv->tm_map = devm_regmap_init_mmio(dev, base, &tsens_config);
+ if (IS_ERR(priv->tm_map)) {
+ ret = PTR_ERR(priv->tm_map);
+ goto err_put_device;
+ }
/*
* The status registers for each sensor are discontiguous
* because some SoCs have 5 sensors while others have more
@@ -367,6 +395,10 @@ static int init_ipq8064(struct tsens_pri
return ret;
return 0;
+
+err_put_device:
+ put_device(&op->dev);
+ return ret;
}
static int calibrate_ipq8064(struct tsens_priv *priv)

107
target/linux/ipq806x/patches-5.4/0063-4-ip806x-tsense-rework-driver.patch
View File

@ -1,107 +0,0 @@
--- a/drivers/thermal/qcom/tsens-ipq8064.c
+++ b/drivers/thermal/qcom/tsens-ipq8064.c
@@ -13,10 +13,12 @@
*/
#include <linux/platform_device.h>
+#include <linux/err.h>
#include <linux/delay.h>
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <linux/thermal.h>
+#include <linux/slab.h>
#include <linux/nvmem-consumer.h>
#include <linux/of_platform.h>
#include <linux/io.h>
@@ -211,9 +213,8 @@ static void tsens_scheduler_fn(struct wo
struct tsens_priv *priv = container_of(work, struct tsens_priv,
tsens_work);
unsigned int threshold, threshold_low, code, reg, sensor, mask;
- unsigned int sensor_addr;
bool upper_th_x, lower_th_x;
- int adc_code, ret;
+ int ret;
ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg);
if (ret)
@@ -262,9 +263,8 @@ static void tsens_scheduler_fn(struct wo
if (upper_th_x || lower_th_x) {
/* Notify user space */
schedule_work(&priv->sensor[0].notify_work);
- regmap_read(priv->tm_map, sensor_addr, &adc_code);
pr_debug("Trigger (%d degrees) for sensor %d\n",
- code_to_degC(adc_code, &priv->sensor[0]), 0);
+ code_to_degC(code, &priv->sensor[0]), 0);
}
}
regmap_write(priv->tm_map, STATUS_CNTL_8064, reg & mask);
@@ -404,40 +404,55 @@ err_put_device:
static int calibrate_ipq8064(struct tsens_priv *priv)
{
int i;
- char *data, *data_backup;
-
+ int ret = 0;
+ u8 *data, *data_backup;
+ struct device *dev = priv->dev;
ssize_t num_read = priv->num_sensors;
struct tsens_sensor *s = priv->sensor;
- data = qfprom_read(priv->dev, "calib");
+ data = qfprom_read(dev, "calib");
if (IS_ERR(data)) {
- pr_err("Calibration not found.\n");
- return PTR_ERR(data);
+ ret = PTR_ERR(data);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Calibration not found.");
+ goto exit;
}
- data_backup = qfprom_read(priv->dev, "calib_backup");
+ data_backup = qfprom_read(dev, "calib_backup");
if (IS_ERR(data_backup)) {
- pr_err("Backup calibration not found.\n");
- return PTR_ERR(data_backup);
+ ret = PTR_ERR(data_backup);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Backup Calibration not found.");
+ goto free_data;
}
for (i = 0; i < num_read; i++) {
s[i].calib_data = readb_relaxed(data + i);
- s[i].calib_data_backup = readb_relaxed(data_backup + i);
+
+ if (!s[i].calib_data) {
+ s[i].calib_data_backup = readb_relaxed(data_backup + i);
+
+ if (!s[i].calib_data_backup) {
+ dev_err(dev, "QFPROM TSENS calibration data not present");
+ ret = -ENODEV;
+ goto free_backup;
+ }
- if (s[i].calib_data_backup)
s[i].calib_data = s[i].calib_data_backup;
- if (!s[i].calib_data) {
- pr_err("QFPROM TSENS calibration data not present\n");
- return -ENODEV;
}
+
s[i].slope = tsens_8064_slope[i];
s[i].offset = CAL_MDEGC - (s[i].calib_data * s[i].slope);
}
hw_init(priv);
- return 0;
+free_backup:
+ kfree(data_backup);
+free_data:
+ kfree(data);
+exit:
+ return ret;
}
static int get_temp_ipq8064(struct tsens_priv *priv, int id, int *temp)

21
target/linux/ipq806x/patches-5.4/0065-arm-override-compiler-flags.patch
View File

@ -1,21 +0,0 @@
From 4d8e29642661397a339ac3485f212c6360445421 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 9 Mar 2017 09:33:32 +0100
Subject: [PATCH 65/69] arm: override compiler flags
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/arm/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -67,7 +67,7 @@ KBUILD_CFLAGS += $(call cc-option,-fno-i
# macro, but instead defines a whole series of macros which makes
# testing for a specific architecture or later rather impossible.
arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
-arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
+arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -mcpu=cortex-a15
arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
# Only override the compiler option if ARMv6. The ARMv6K extensions are
# always available in ARMv7

210
target/linux/ipq806x/patches-5.4/0067-generic-Mangle-bootloader-s-kernel-arguments.patch
View File

@ -1,210 +0,0 @@
From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
From: Adrian Panella <ianchi74@outlook.com>
Date: Thu, 9 Mar 2017 09:37:17 +0100
Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
The command-line arguments provided by the boot loader will be
appended to a new device tree property: bootloader-args.
If there is a property "append-rootblock" in DT under /chosen
and a root= option in bootloaders command line it will be parsed
and added to DT bootargs with the form: <append-rootblock>XX.
Only command line ATAG will be processed, the rest of the ATAGs
sent by bootloader will be ignored.
This is usefull in dual boot systems, to get the current root partition
without afecting the rest of the system.
Signed-off-by: Adrian Panella <ianchi74@outlook.com>
---
arch/arm/Kconfig | 11 +++++
arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-
init/main.c | 16 ++++++++
3 files changed, 98 insertions(+), 1 deletion(-)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1827,6 +1827,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
The command-line arguments provided by the boot loader will be
appended to the the device tree bootargs property.
+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
+ bool "Append rootblock parsing bootloader's kernel arguments"
+ help
+ The command-line arguments provided by the boot loader will be
+ appended to a new device tree property: bootloader-args.
+ If there is a property "append-rootblock" in DT under /chosen
+ and a root= option in bootloaders command line it will be parsed
+ and added to DT bootargs with the form: <append-rootblock>XX.
+ Only command line ATAG will be processed, the rest of the ATAGs
+ sent by bootloader will be ignored.
+
endchoice
config CMDLINE
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -4,6 +4,8 @@
#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
#define do_extend_cmdline 1
+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+#define do_extend_cmdline 1
#else
#define do_extend_cmdline 0
#endif
@@ -67,6 +69,80 @@ static uint32_t get_cell_size(const void
return cell_size;
}
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+/**
+ * taken from arch/x86/boot/string.c
+ * local_strstr - Find the first substring in a %NUL terminated string
+ * @s1: The string to be searched
+ * @s2: The string to search for
+ */
+static char *local_strstr(const char *s1, const char *s2)
+{
+ size_t l1, l2;
+
+ l2 = strlen(s2);
+ if (!l2)
+ return (char *)s1;
+ l1 = strlen(s1);
+ while (l1 >= l2) {
+ l1--;
+ if (!memcmp(s1, s2, l2))
+ return (char *)s1;
+ s1++;
+ }
+ return NULL;
+}
+
+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
+{
+ char *ptr, *end, *tmp;
+ char *root="root=";
+ char *find_rootblock;
+ int i, l;
+ const char *rootblock;
+
+ find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l);
+ if(!find_rootblock)
+ find_rootblock = root;
+
+ //ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86
+ ptr = local_strstr(str, find_rootblock);
+
+ if(!ptr)
+ return dest;
+
+ end = strchr(ptr, ' ');
+ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
+
+ // Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too.
+ tmp = strchr(ptr, ',');
+
+ if(tmp)
+ end = end < tmp ? end : tmp - 1;
+
+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ )
+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
+ ptr = end + 1;
+
+ /* if append-rootblock property is set use it to append to command line */
+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
+ if(rootblock != NULL) {
+ if(*dest != ' ') {
+ *dest = ' ';
+ dest++;
+ len++;
+ }
+ if (len + l + i <= COMMAND_LINE_SIZE) {
+ memcpy(dest, rootblock, l);
+ dest += l - 1;
+ memcpy(dest, ptr, i);
+ dest += i;
+ }
+ }
+ return dest;
+}
+#endif
+
static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
{
char cmdline[COMMAND_LINE_SIZE];
@@ -86,12 +162,21 @@ static void merge_fdt_bootargs(void *fdt
/* and append the ATAG_CMDLINE */
if (fdt_cmdline) {
+
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+ //save original bootloader args
+ //and append ubi.mtd with root partition number to current cmdline
+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
+
+#else
len = strlen(fdt_cmdline);
if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
*ptr++ = ' ';
memcpy(ptr, fdt_cmdline, len);
ptr += len;
}
+#endif
}
*ptr = '\0';
@@ -166,7 +251,9 @@ int atags_to_fdt(void *atag_list, void *
else
setprop_string(fdt, "/chosen", "bootargs",
atag->u.cmdline.cmdline);
- } else if (atag->hdr.tag == ATAG_MEM) {
+ }
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
+ else if (atag->hdr.tag == ATAG_MEM) {
if (memcount >= sizeof(mem_reg_property)/4)
continue;
if (!atag->u.mem.size)
@@ -210,6 +297,10 @@ int atags_to_fdt(void *atag_list, void *
setprop(fdt, "/memory", "reg", mem_reg_property,
4 * memcount * memsize);
}
+#else
+
+ }
+#endif
return fdt_pack(fdt);
}
--- a/init/main.c
+++ b/init/main.c
@@ -104,6 +104,10 @@
#define CREATE_TRACE_POINTS
#include <trace/events/initcall.h>
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+#include <linux/of.h>
+#endif
+
static int kernel_init(void *);
extern void init_IRQ(void);
@@ -633,6 +637,18 @@ asmlinkage __visible void __init start_k
pr_notice("Kernel command line: %s\n", boot_command_line);
/* parameters may set static keys */
jump_label_init();
+
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+ //Show bootloader's original command line for reference
+ if(of_chosen) {
+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
+ if(prop)
+ pr_notice("Bootloader command line (ignored): %s\n", prop);
+ else
+ pr_notice("Bootloader command line not present\n");
+ }
+#endif
+
parse_early_param();
after_dashes = parse_args("Booting kernel",
static_command_line, __start___param,

38
target/linux/ipq806x/patches-5.4/0069-arm-boot-add-dts-files.patch
View File

@ -1,38 +0,0 @@
From 8f68331e14dff9a101f2d0e1d6bec84a031f27ee Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 9 Mar 2017 11:03:18 +0100
Subject: [PATCH 69/69] arm: boot: add dts files
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/arm/boot/dts/Makefile | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -842,7 +842,25 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq4019-ap.dk07.1-c2.dtb \
+ qcom-ipq8062-wg2600hp3.dtb \
qcom-ipq8064-ap148.dtb \
+ qcom-ipq8064-c2600.dtb \
+ qcom-ipq8064-d7800.dtb \
+ qcom-ipq8064-db149.dtb \
+ qcom-ipq8064-ap161.dtb \
+ qcom-ipq8064-ea7500-v1.dtb \
+ qcom-ipq8064-ea8500.dtb \
+ qcom-ipq8064-g10.dtb \
+ qcom-ipq8064-r7500.dtb \
+ qcom-ipq8064-r7500v2.dtb \
+ qcom-ipq8064-unifi-ac-hd.dtb \
+ qcom-ipq8064-wg2600hp.dtb \
+ qcom-ipq8064-wpq864.dtb \
+ qcom-ipq8064-wxr-2533dhp.dtb \
+ qcom-ipq8065-nbg6817.dtb \
+ qcom-ipq8065-r7800.dtb \
+ qcom-ipq8065-rt4230w-rev6.dtb \
+ qcom-ipq8068-ecw5410.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-fairphone-fp2.dtb \

10
target/linux/ipq806x/patches-5.4/0072-add-ipq806x-with-no-clocks.patch
View File

@ -1,10 +0,0 @@
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -598,6 +598,7 @@ static const struct of_device_id qcom_sc
SCM_HAS_BUS_CLK)
},
{ .compatible = "qcom,scm-ipq4019" },
+ { .compatible = "qcom,scm-ipq806x" },
{ .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK },
{ .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK },
{ .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK |

70
target/linux/ipq806x/patches-5.4/080-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch
View File

@ -1,70 +0,0 @@
From patchwork Mon May 21 20:57:38 2018
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v5,3/4] ARM: dts: qcom: add gpio-ranges property
X-Patchwork-Submitter: Christian Lamparter <chunkeey@gmail.com>
X-Patchwork-Id: 917856
Message-Id: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com>
To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
Linus Walleij <linus.walleij@linaro.org>,
Stephen Boyd <sboyd@kernel.org>, David Brown <david.brown@linaro.org>,
Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
Andy Gross <andy.gross@linaro.org>,
Sven Eckelmann <sven.eckelmann@openmesh.com>
Date: Mon, 21 May 2018 22:57:38 +0200
From: Christian Lamparter <chunkeey@gmail.com>
List-Id: <linux-gpio.vger.kernel.org>
This patch adds the gpio-ranges property to almost all of
the Qualcomm ARM platforms that utilize the pinctrl-msm
framework.
The gpio-ranges property is part of the gpiolib subsystem.
As a result, the binding text is available in section
"2.1 gpio- and pin-controller interaction" of
Documentation/devicetree/bindings/gpio/gpio.txt
For more information please see the patch titled:
"pinctrl: msm: fix gpio-hog related boot issues" from
this series.
Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019]
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
---
To help with git bisect, the DT update patch has been intentionally
placed after the "pinctrl: msm: fix gpio-hog related boot issues".
Otherwise - if the order was reveresed - and bisect decides to split
between these two patches, the gpiochip_add_pin_ranges() function
will be executed twice with the same parameters for the same pinctrl.
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 1 +
arch/arm/boot/dts/qcom-apq8084.dtsi | 1 +
arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 +
arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 +
arch/arm/boot/dts/qcom-msm8660.dtsi | 1 +
arch/arm/boot/dts/qcom-msm8960.dtsi | 1 +
arch/arm/boot/dts/qcom-msm8974.dtsi | 1 +
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
arch/arm64/boot/dts/qcom/msm8992.dtsi | 1 +
arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 +
arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 +
13 files changed, 14 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -119,6 +119,7 @@
reg = <0x800000 0x4000>;
gpio-controller;
+ gpio-ranges = <&qcom_pinmux 0 0 69>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;

29
target/linux/ipq806x/patches-5.4/081-v5.8-ARM-dts-qcom-add-scm-definition-to-ipq806x.patch
View File

@ -1,29 +0,0 @@
From 51befb888f62b1a62434fb4b82328d698a30f9de Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Thu, 19 Mar 2020 23:44:24 +0100
Subject: ARM: dts: qcom: add scm definition to ipq806x
Add missing scm definition for ipq806x soc
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20200319224424.18473-1-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -93,6 +93,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq806x", "qcom,scm";
+ };
+ };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;

130
target/linux/ipq806x/patches-5.4/082-ipq8064-dtsi-tweaks.patch
View File

@ -1,130 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -20,7 +20,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
@@ -30,7 +30,7 @@
qcom,saw = <&saw0>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
@@ -67,7 +67,7 @@
no-map;
};
- smem@41000000 {
+ smem: smem@41000000 {
reg = <0x41000000 0x200000>;
no-map;
};
@@ -155,6 +155,7 @@
function = "pcie3_rst";
drive-strength = <12>;
bias-disable;
+ output-low;
};
};
@@ -219,21 +220,23 @@
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+ clock-output-names = "acpu0_aux";
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+ clock-output-names = "acpu1_aux";
};
saw0: regulator@2089000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
saw1: regulator@2099000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
@@ -251,7 +254,7 @@
syscon-tcsr = <&tcsr>;
- serial@12490000 {
+ gsbi2_serial: serial@12490000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x12490000 0x1000>,
<0x12480000 0x1000>;
@@ -326,7 +329,7 @@
syscon-tcsr = <&tcsr>;
- serial@1a240000 {
+ gsbi5_serial: serial@1a240000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a240000 0x1000>,
<0x1a200000 0x1000>;
@@ -397,7 +400,7 @@
status = "disabled";
};
- sata@29000000 {
+ sata: sata@29000000 {
compatible = "qcom,ipq806x-ahci", "generic-ahci";
reg = <0x29000000 0x180>;
@@ -430,6 +433,7 @@
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
};
tcsr: syscon@1a400000 {
@@ -625,13 +629,13 @@
qcom,ee = <0>;
};
- amba {
- compatible = "simple-bus";
+ amba: amba {
+ compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sdcc@12400000 {
+ sdcc1: sdcc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
@@ -645,13 +649,12 @@
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
- mmc-ddr-1_8v;
vmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
dma-names = "tx", "rx";
};
- sdcc@12180000 {
+ sdcc3: sdcc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";

1024
target/linux/ipq806x/patches-5.4/083-ipq8064-dtsi-additions.patch
View File

File diff suppressed because it is too large Load Diff

89
target/linux/ipq806x/patches-5.4/084-ipq8064-v1.0-dtsi-cleanup.patch
View File

@ -1,89 +0,0 @@
This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches
instead of keeping a local version.
We drop partitions, LEDs and keys from the file as we will implement
them differently anyway.
--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -42,16 +42,6 @@
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
-
- partition@0 {
- label = "rootfs";
- reg = <0x0 0x1000000>;
- };
-
- partition@1 {
- label = "scratch";
- reg = <0x1000000 0x1000000>;
- };
};
};
};
@@ -64,64 +54,5 @@
ports-implemented = <0x1>;
status = "ok";
};
-
- gpio_keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&buttons_pins>;
- pinctrl-names = "default";
-
- button@1 {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- debounce-interval = <60>;
- };
- button@2 {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- debounce-interval = <60>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&leds_pins>;
- pinctrl-names = "default";
-
- led@7 {
- label = "led_usb1";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "usbdev";
- default-state = "off";
- };
-
- led@8 {
- label = "led_usb3";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "usbdev";
- default-state = "off";
- };
-
- led@9 {
- label = "status_led_fail";
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led@26 {
- label = "sata_led";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led@53 {
- label = "status_led_pass";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
};
};

14
target/linux/ipq806x/patches-5.4/085-ipq8064-v1.0-dtsi-additions.patch
View File

@ -1,14 +0,0 @@
This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches
instead of keeping a local version. This patch adds our local adjustments
for the (local) additional contents of qcom-ipq8064.dtsi
--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -56,3 +56,7 @@
};
};
};
+
+&CPU_SPC {
+ status = "okay";
+};

104
target/linux/ipq806x/patches-5.4/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch
View File

@ -1,104 +0,0 @@
From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001
From: Ajay Kishore <akisho@codeaurora.org>
Date: Fri, 27 Mar 2020 23:32:08 +0100
Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
For IPQ806x targets, TZ protects the registers that are used to
configure the routing of interrupts to a target processor.
To resolve this, this patch uses scm call to route GPIO interrupts
to application processor. Also the scm call interface is changed.
Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------
1 file changed, 37 insertions(+), 6 deletions(-)
(limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -22,6 +22,8 @@
#include <linux/reboot.h>
#include <linux/pm.h>
#include <linux/log2.h>
+#include <linux/qcom_scm.h>
+#include <linux/io.h>
#include "../core.h"
#include "../pinconf.h"
@@ -57,6 +59,8 @@ struct msm_pinctrl {
struct irq_chip irq_chip;
int irq;
+ bool intr_target_use_scm;
+
raw_spinlock_t lock;
DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
@@ -64,6 +68,7 @@ struct msm_pinctrl {
const struct msm_pinctrl_soc_data *soc;
void __iomem *regs[MAX_NR_TILES];
+ u32 phys_base[MAX_NR_TILES];
};
#define MSM_ACCESSOR(name) \
@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
else
clear_bit(d->hwirq, pctrl->dual_edge_irqs);
- /* Route interrupts to application cpu */
- val = msm_readl_intr_target(pctrl, g);
- val &= ~(7 << g->intr_target_bit);
- val |= g->intr_target_kpss_val << g->intr_target_bit;
- msm_writel_intr_target(val, pctrl, g);
+ /* Route interrupts to application cpu.
+ * With intr_target_use_scm interrupts are routed to
+ * application cpu using scm calls.
+ */
+ if (pctrl->intr_target_use_scm) {
+ u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
+ int ret;
+
+ qcom_scm_io_readl(addr, &val);
+
+ val &= ~(7 << g->intr_target_bit);
+ val |= g->intr_target_kpss_val << g->intr_target_bit;
+
+ ret = qcom_scm_io_writel(addr, val);
+ if (ret)
+ dev_err(pctrl->dev,
+ "Failed routing %lu interrupt to Apps proc",
+ d->hwirq);
+ } else {
+ val = msm_readl_intr_target(pctrl, g);
+ val &= ~(7 << g->intr_target_bit);
+ val |= g->intr_target_kpss_val << g->intr_target_bit;
+ msm_writel_intr_target(val, pctrl, g);
+ }
/* Update configuration for gpio.
* RAW_STATUS_EN is left on for all gpio irqs. Due to the
@@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de
pctrl->dev = &pdev->dev;
pctrl->soc = soc_data;
pctrl->chip = msm_gpio_template;
+ pctrl->intr_target_use_scm = of_device_is_compatible(
+ pctrl->dev->of_node,
+ "qcom,ipq8064-pinctrl");
raw_spin_lock_init(&pctrl->lock);
@@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de
pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pctrl->regs[0]))
return PTR_ERR(pctrl->regs[0]);
+
+ pctrl->phys_base[0] = res->start;
}
msm_pinctrl_setup_pm_reset(pctrl);

56
target/linux/ipq806x/patches-5.4/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch
View File

@ -1,56 +0,0 @@
From 8d8cec9bf6e9260397872785f249dfb59a417d08 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Wed, 19 Feb 2020 18:59:39 +0100
Subject: ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
Add missing gpio definition for mdio and rgmii2.
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20200219175940.744-1-ansuelsmth@gmail.com
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
@@ -299,7 +299,7 @@ static const char * const gpio_groups[]
};
static const char * const mdio_groups[] = {
- "gpio0", "gpio1", "gpio10", "gpio11",
+ "gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66",
};
static const char * const mi2s_groups[] = {
@@ -403,8 +403,8 @@ static const char * const usb2_hsic_grou
};
static const char * const rgmii2_groups[] = {
- "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
- "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62",
+ "gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
+ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66",
};
static const char * const sata_groups[] = {
@@ -539,7 +539,7 @@ static const struct msm_function ipq8064
static const struct msm_pingroup ipq8064_groups[] = {
PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
@@ -603,7 +603,7 @@ static const struct msm_pingroup ipq8064
PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),

98
target/linux/ipq806x/patches-5.4/088-v5.8-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch
View File

@ -1,98 +0,0 @@
From 000de5417107623925a4cf0310579f744ff43c28 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Tue, 4 Feb 2020 20:56:48 +0100
Subject: watchdog: qcom-wdt: disable pretimeout on timer platform
Some platform like ipq806x doesn't support pretimeout and define
some interrupts used by qcom,msm-timer. Change the driver to check
and use pretimeout only on qcom,kpss-wdt as it's the only platform
that actually supports it.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20200204195648.23350-1-ansuelsmth@gmail.com
[groeck: Conflict resolution]
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
---
drivers/watchdog/qcom-wdt.c | 31 +++++++++++++++++++++++--------
1 file changed, 23 insertions(+), 8 deletions(-)
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-wdt.c
@@ -39,6 +39,11 @@ static const u32 reg_offset_data_kpss[]
[WDT_BITE_TIME] = 0x14,
};
+struct qcom_wdt_match_data {
+ const u32 *offset;
+ bool pretimeout;
+};
+
struct qcom_wdt {
struct watchdog_device wdd;
unsigned long rate;
@@ -168,19 +173,29 @@ static void qcom_clk_disable_unprepare(v
clk_disable_unprepare(data);
}
+static const struct qcom_wdt_match_data match_data_apcs_tmr = {
+ .offset = reg_offset_data_apcs_tmr,
+ .pretimeout = false,
+};
+
+static const struct qcom_wdt_match_data match_data_kpss = {
+ .offset = reg_offset_data_kpss,
+ .pretimeout = true,
+};
+
static int qcom_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct qcom_wdt *wdt;
struct resource *res;
struct device_node *np = dev->of_node;
- const u32 *regs;
+ const struct qcom_wdt_match_data *data;
u32 percpu_offset;
int irq, ret;
struct clk *clk;
- regs = of_device_get_match_data(dev);
- if (!regs) {
+ data = of_device_get_match_data(dev);
+ if (!data) {
dev_err(dev, "Unsupported QCOM WDT module\n");
return -ENODEV;
}
@@ -236,7 +251,7 @@ static int qcom_wdt_probe(struct platfor
/* check if there is pretimeout support */
irq = platform_get_irq_optional(pdev, 0);
- if (irq > 0) {
+ if (data->pretimeout && irq > 0) {
ret = devm_request_irq(dev, irq, qcom_wdt_isr,
IRQF_TRIGGER_RISING,
"wdt_bark", &wdt->wdd);
@@ -256,7 +271,7 @@ static int qcom_wdt_probe(struct platfor
wdt->wdd.min_timeout = 1;
wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
wdt->wdd.parent = dev;
- wdt->layout = regs;
+ wdt->layout = data->offset;
if (readl(wdt_addr(wdt, WDT_STS)) & 1)
wdt->wdd.bootstatus = WDIOF_CARDRESET;
@@ -300,9 +315,9 @@ static int __maybe_unused qcom_wdt_resum
static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
static const struct of_device_id qcom_wdt_of_table[] = {
- { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
- { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
- { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
+ { .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
+ { .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
+ { .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
{ },
};
MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);

28
target/linux/ipq806x/patches-5.4/089-v5.8-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch
View File

@ -1,28 +0,0 @@
From 1aec193ea41d672d11592714cdda8167eb3b38fc Mon Sep 17 00:00:00 2001
From: Abhishek Sahu <absahu@codeaurora.org>
Date: Wed, 18 Mar 2020 14:16:56 +0100
Subject: ipq806x: gcc: Added the enable regs and mask for PRNG
Kernel got hanged while reading from /dev/hwrng at the
time of PRNG clock enable
Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Link: https://lkml.kernel.org/r/20200318131657.345-1-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/qcom/gcc-ipq806x.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -1225,6 +1225,8 @@ static struct clk_rcg prng_src = {
.parent_map = gcc_pxo_pll8_map,
},
.clkr = {
+ .enable_reg = 0x2e80,
+ .enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "prng_src",
.parent_names = gcc_pxo_pll8,

90
target/linux/ipq806x/patches-5.4/090-v5.8-clk-clk-rpm-fixes.patch
View File

@ -1,90 +0,0 @@
From eec152734be10c72d2d413a27ca9d282c28cdb61 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Tue, 10 Mar 2020 15:37:56 +0100
Subject: clk: qcom: clk-rpm: add missing rpm clk for ipq806x
Add missing definition of rpm clk for ipq806x soc
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: John Crispin <john@phrozen.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200310143756.244-1-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
.../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
drivers/clk/qcom/clk-rpm.c | 35 ++++++++++++++++++++++
include/dt-bindings/clock/qcom,rpmcc.h | 4 +++
3 files changed, 40 insertions(+)
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
@@ -15,6 +15,7 @@ Required properties :
"qcom,rpmcc-msm8916", "qcom,rpmcc"
"qcom,rpmcc-msm8974", "qcom,rpmcc"
"qcom,rpmcc-apq8064", "qcom,rpmcc"
+ "qcom,rpmcc-ipq806x", "qcom,rpmcc"
"qcom,rpmcc-msm8996", "qcom,rpmcc"
"qcom,rpmcc-msm8998", "qcom,rpmcc"
"qcom,rpmcc-qcs404", "qcom,rpmcc"
--- a/drivers/clk/qcom/clk-rpm.c
+++ b/drivers/clk/qcom/clk-rpm.c
@@ -543,10 +543,45 @@ static const struct rpm_clk_desc rpm_clk
.num_clks = ARRAY_SIZE(apq8064_clks),
};
+/* ipq806x */
+DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
+DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
+DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
+DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
+DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
+DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
+DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK);
+DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK);
+
+static struct clk_rpm *ipq806x_clks[] = {
+ [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk,
+ [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk,
+ [RPM_CFPB_CLK] = &ipq806x_cfpb_clk,
+ [RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk,
+ [RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk,
+ [RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk,
+ [RPM_EBI1_CLK] = &ipq806x_ebi1_clk,
+ [RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk,
+ [RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk,
+ [RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk,
+ [RPM_SFPB_CLK] = &ipq806x_sfpb_clk,
+ [RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk,
+ [RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk,
+ [RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk,
+ [RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk,
+ [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk,
+};
+
+static const struct rpm_clk_desc rpm_clk_ipq806x = {
+ .clks = ipq806x_clks,
+ .num_clks = ARRAY_SIZE(ipq806x_clks),
+};
+
static const struct of_device_id rpm_clk_match_table[] = {
{ .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
{ .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
{ .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
+ { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
{ }
};
MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -37,6 +37,10 @@
#define RPM_XO_A0 27
#define RPM_XO_A1 28
#define RPM_XO_A2 29
+#define RPM_NSS_FABRIC_0_CLK 30
+#define RPM_NSS_FABRIC_0_A_CLK 31
+#define RPM_NSS_FABRIC_1_CLK 32
+#define RPM_NSS_FABRIC_1_A_CLK 33
/* SMD RPM clocks */
#define RPM_SMD_XO_CLK_SRC 0

63
target/linux/ipq806x/patches-5.4/091-v5.8-regulator-add-smb208-support.patch
View File

@ -1,63 +0,0 @@
From b5f25304aece9f2e7eaab275bbb5461c666bf38c Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Wed, 19 Feb 2020 17:37:11 +0100
Subject: regulator: add smb208 support
Smb208 regulators are used on some ipq806x soc.
Add support for it to make it avaiable on some routers
that use it.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Adrian Panella <ianchi74@outlook.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20200219163711.479-1-ansuelsmth@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 4 ++++
drivers/regulator/qcom_rpm-regulator.c | 9 +++++++++
2 files changed, 13 insertions(+)
--- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt
+++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt
@@ -61,6 +61,7 @@ Regulator nodes are identified by their
"qcom,rpm-pm8901-regulators"
"qcom,rpm-pm8921-regulators"
"qcom,rpm-pm8018-regulators"
+ "qcom,rpm-smb208-regulators"
- vdd_l0_l1_lvs-supply:
- vdd_l2_l11_l12-supply:
@@ -171,6 +172,9 @@ pm8018:
s1, s2, s3, s4, s5, , l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
l12, l14, lvs1
+smb208:
+ s1a, s1b, s2a, s2b
+
The content of each sub-node is defined by the standard binding for regulators -
see regulator.txt - with additional custom properties described below:
--- a/drivers/regulator/qcom_rpm-regulator.c
+++ b/drivers/regulator/qcom_rpm-regulator.c
@@ -925,12 +925,21 @@ static const struct rpm_regulator_data r
{ }
};
+static const struct rpm_regulator_data rpm_smb208_regulators[] = {
+ { "s1a", QCOM_RPM_SMB208_S1a, &smb208_smps, "vin_s1a" },
+ { "s1b", QCOM_RPM_SMB208_S1b, &smb208_smps, "vin_s1b" },
+ { "s2a", QCOM_RPM_SMB208_S2a, &smb208_smps, "vin_s2a" },
+ { "s2b", QCOM_RPM_SMB208_S2b, &smb208_smps, "vin_s2b" },
+ { }
+};
+
static const struct of_device_id rpm_of_match[] = {
{ .compatible = "qcom,rpm-pm8018-regulators",
.data = &rpm_pm8018_regulators },
{ .compatible = "qcom,rpm-pm8058-regulators", .data = &rpm_pm8058_regulators },
{ .compatible = "qcom,rpm-pm8901-regulators", .data = &rpm_pm8901_regulators },
{ .compatible = "qcom,rpm-pm8921-regulators", .data = &rpm_pm8921_regulators },
+ { .compatible = "qcom,rpm-smb208-regulators", .data = &rpm_smb208_regulators },
{ }
};
MODULE_DEVICE_TABLE(of, rpm_of_match);

361
target/linux/ipq806x/patches-5.4/092-1-v5.7-qcom-cpufreq-nvmem-Add-support-for-krait-based-socs.patch
View File

@ -1,361 +0,0 @@
From a8811ec764f95a04ba82f6f457e28c5e9e36e36b Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Fri, 13 Mar 2020 18:52:13 +0100
Subject: cpufreq: qcom: Add support for krait based socs
In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.
The required OPP related data is determined based on
the efuse value. This is similar to the existing code for
kryo cores. So adding support for krait cores here.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
drivers/cpufreq/Kconfig.arm | 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 191 +++++++++++++++++++--
4 files changed, 183 insertions(+), 18 deletions(-)
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -19,7 +19,8 @@ In 'cpu' nodes:
In 'operating-points-v2' table:
- compatible: Should be
- - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
+ - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
+ apq8064, ipq8064, msm8960 and ipq8074.
Optional properties:
--------------------
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -135,7 +135,7 @@ config ARM_OMAP2PLUS_CPUFREQ
config ARM_QCOM_CPUFREQ_NVMEM
tristate "Qualcomm nvmem based CPUFreq"
- depends on ARM64
+ depends on ARCH_QCOM
depends on QCOM_QFPROM
depends on QCOM_SMEM
select PM_OPP
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -140,6 +140,11 @@ static const struct of_device_id blackli
{ .compatible = "ti,am43", },
{ .compatible = "ti,dra7", },
+ { .compatible = "qcom,ipq8064", },
+ { .compatible = "qcom,apq8064", },
+ { .compatible = "qcom,msm8974", },
+ { .compatible = "qcom,msm8960", },
+
{ }
};
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -49,12 +49,14 @@ struct qcom_cpufreq_drv;
struct qcom_cpufreq_match_data {
int (*get_version)(struct device *cpu_dev,
struct nvmem_cell *speedbin_nvmem,
+ char **pvs_name,
struct qcom_cpufreq_drv *drv);
const char **genpd_names;
};
struct qcom_cpufreq_drv {
- struct opp_table **opp_tables;
+ struct opp_table **names_opp_tables;
+ struct opp_table **hw_opp_tables;
struct opp_table **genpd_opp_tables;
u32 versions;
const struct qcom_cpufreq_match_data *data;
@@ -62,6 +64,84 @@ struct qcom_cpufreq_drv {
static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
+static void get_krait_bin_format_a(struct device *cpu_dev,
+ int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+ u32 pte_efuse;
+
+ pte_efuse = *((u32 *)buf);
+
+ *speed = pte_efuse & 0xf;
+ if (*speed == 0xf)
+ *speed = (pte_efuse >> 4) & 0xf;
+
+ if (*speed == 0xf) {
+ *speed = 0;
+ dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
+ } else {
+ dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
+ }
+
+ *pvs = (pte_efuse >> 10) & 0x7;
+ if (*pvs == 0x7)
+ *pvs = (pte_efuse >> 13) & 0x7;
+
+ if (*pvs == 0x7) {
+ *pvs = 0;
+ dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
+ } else {
+ dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
+ }
+}
+
+static void get_krait_bin_format_b(struct device *cpu_dev,
+ int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+ u32 pte_efuse, redundant_sel;
+
+ pte_efuse = *((u32 *)buf);
+ redundant_sel = (pte_efuse >> 24) & 0x7;
+
+ *pvs_ver = (pte_efuse >> 4) & 0x3;
+
+ switch (redundant_sel) {
+ case 1:
+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
+ *speed = (pte_efuse >> 27) & 0xf;
+ break;
+ case 2:
+ *pvs = (pte_efuse >> 27) & 0xf;
+ *speed = pte_efuse & 0x7;
+ break;
+ default:
+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */
+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
+ *speed = pte_efuse & 0x7;
+ }
+
+ /* Check SPEED_BIN_BLOW_STATUS */
+ if (pte_efuse & BIT(3)) {
+ dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
+ } else {
+ dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
+ *speed = 0;
+ }
+
+ /* Check PVS_BLOW_STATUS */
+ pte_efuse = *(((u32 *)buf) + 4);
+ pte_efuse &= BIT(21);
+ if (pte_efuse) {
+ dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
+ } else {
+ dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
+ *pvs = 0;
+ }
+
+ dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
+}
+
static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
{
size_t len;
@@ -93,11 +173,13 @@ static enum _msm8996_version qcom_cpufre
static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
struct nvmem_cell *speedbin_nvmem,
+ char **pvs_name,
struct qcom_cpufreq_drv *drv)
{
size_t len;
u8 *speedbin;
enum _msm8996_version msm8996_version;
+ *pvs_name = NULL;
msm8996_version = qcom_cpufreq_get_msm_id();
if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
@@ -125,10 +207,51 @@ static int qcom_cpufreq_kryo_name_versio
return 0;
}
+static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
+ struct nvmem_cell *speedbin_nvmem,
+ char **pvs_name,
+ struct qcom_cpufreq_drv *drv)
+{
+ int speed = 0, pvs = 0, pvs_ver = 0;
+ u8 *speedbin;
+ size_t len;
+
+ speedbin = nvmem_cell_read(speedbin_nvmem, &len);
+
+ if (IS_ERR(speedbin))
+ return PTR_ERR(speedbin);
+
+ switch (len) {
+ case 4:
+ get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
+ speedbin_nvmem, speedbin);
+ break;
+ case 8:
+ get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
+ speedbin_nvmem, speedbin);
+ break;
+ default:
+ dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
+ return -ENODEV;
+ }
+
+ snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
+ speed, pvs, pvs_ver);
+
+ drv->versions = (1 << speed);
+
+ kfree(speedbin);
+ return 0;
+}
+
static const struct qcom_cpufreq_match_data match_data_kryo = {
.get_version = qcom_cpufreq_kryo_name_version,
};
+static const struct qcom_cpufreq_match_data match_data_krait = {
+ .get_version = qcom_cpufreq_krait_name_version,
+};
+
static const char *qcs404_genpd_names[] = { "cpr", NULL };
static const struct qcom_cpufreq_match_data match_data_qcs404 = {
@@ -141,6 +264,7 @@ static int qcom_cpufreq_probe(struct pla
struct nvmem_cell *speedbin_nvmem;
struct device_node *np;
struct device *cpu_dev;
+ char *pvs_name = "speedXX-pvsXX-vXX";
unsigned cpu;
const struct of_device_id *match;
int ret;
@@ -153,7 +277,7 @@ static int qcom_cpufreq_probe(struct pla
if (!np)
return -ENOENT;
- ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
+ ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu");
if (!ret) {
of_node_put(np);
return -ENOENT;
@@ -181,7 +305,8 @@ static int qcom_cpufreq_probe(struct pla
goto free_drv;
}
- ret = drv->data->get_version(cpu_dev, speedbin_nvmem, drv);
+ ret = drv->data->get_version(cpu_dev,
+ speedbin_nvmem, &pvs_name, drv);
if (ret) {
nvmem_cell_put(speedbin_nvmem);
goto free_drv;
@@ -190,12 +315,20 @@ static int qcom_cpufreq_probe(struct pla
}
of_node_put(np);
- drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables),
+ drv->names_opp_tables = kcalloc(num_possible_cpus(),
+ sizeof(*drv->names_opp_tables),
GFP_KERNEL);
- if (!drv->opp_tables) {
+ if (!drv->names_opp_tables) {
ret = -ENOMEM;
goto free_drv;
}
+ drv->hw_opp_tables = kcalloc(num_possible_cpus(),
+ sizeof(*drv->hw_opp_tables),
+ GFP_KERNEL);
+ if (!drv->hw_opp_tables) {
+ ret = -ENOMEM;
+ goto free_opp_names;
+ }
drv->genpd_opp_tables = kcalloc(num_possible_cpus(),
sizeof(*drv->genpd_opp_tables),
@@ -213,11 +346,23 @@ static int qcom_cpufreq_probe(struct pla
}
if (drv->data->get_version) {
- drv->opp_tables[cpu] =
- dev_pm_opp_set_supported_hw(cpu_dev,
- &drv->versions, 1);
- if (IS_ERR(drv->opp_tables[cpu])) {
- ret = PTR_ERR(drv->opp_tables[cpu]);
+
+ if (pvs_name) {
+ drv->names_opp_tables[cpu] = dev_pm_opp_set_prop_name(
+ cpu_dev,
+ pvs_name);
+ if (IS_ERR(drv->names_opp_tables[cpu])) {
+ ret = PTR_ERR(drv->names_opp_tables[cpu]);
+ dev_err(cpu_dev, "Failed to add OPP name %s\n",
+ pvs_name);
+ goto free_opp;
+ }
+ }
+
+ drv->hw_opp_tables[cpu] = dev_pm_opp_set_supported_hw(
+ cpu_dev, &drv->versions, 1);
+ if (IS_ERR(drv->hw_opp_tables[cpu])) {
+ ret = PTR_ERR(drv->hw_opp_tables[cpu]);
dev_err(cpu_dev,
"Failed to set supported hardware\n");
goto free_genpd_opp;
@@ -259,11 +404,18 @@ free_genpd_opp:
kfree(drv->genpd_opp_tables);
free_opp:
for_each_possible_cpu(cpu) {
- if (IS_ERR_OR_NULL(drv->opp_tables[cpu]))
+ if (IS_ERR_OR_NULL(drv->names_opp_tables[cpu]))
+ break;
+ dev_pm_opp_put_prop_name(drv->names_opp_tables[cpu]);
+ }
+ for_each_possible_cpu(cpu) {
+ if (IS_ERR_OR_NULL(drv->hw_opp_tables[cpu]))
break;
- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
+ dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
}
- kfree(drv->opp_tables);
+ kfree(drv->hw_opp_tables);
+free_opp_names:
+ kfree(drv->names_opp_tables);
free_drv:
kfree(drv);
@@ -278,13 +430,16 @@ static int qcom_cpufreq_remove(struct pl
platform_device_unregister(cpufreq_dt_pdev);
for_each_possible_cpu(cpu) {
- if (drv->opp_tables[cpu])
- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
+ if (drv->names_opp_tables[cpu])
+ dev_pm_opp_put_supported_hw(drv->names_opp_tables[cpu]);
+ if (drv->hw_opp_tables[cpu])
+ dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
if (drv->genpd_opp_tables[cpu])
dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
}
- kfree(drv->opp_tables);
+ kfree(drv->names_opp_tables);
+ kfree(drv->hw_opp_tables);
kfree(drv->genpd_opp_tables);
kfree(drv);
@@ -303,6 +458,10 @@ static const struct of_device_id qcom_cp
{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
+ { .compatible = "qcom,ipq8064", .data = &match_data_krait },
+ { .compatible = "qcom,apq8064", .data = &match_data_krait },
+ { .compatible = "qcom,msm8974", .data = &match_data_krait },
+ { .compatible = "qcom,msm8960", .data = &match_data_krait },
{},
};
MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);

26
target/linux/ipq806x/patches-5.4/092-2-v5.7-cpufreq-qcom-fix-wrong-compatible-binding.patch
View File

@ -1,26 +0,0 @@
From 2dea651680cea1f3a29925de51002f33d1f55711 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Fri, 1 May 2020 00:22:25 +0200
Subject: cpufreq: qcom: fix wrong compatible binding
Binding in Documentation is still "operating-points-v2-kryo-cpu".
Restore the old binding to fix the compatibility problem.
Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -277,7 +277,7 @@ static int qcom_cpufreq_probe(struct pla
if (!np)
return -ENOENT;
- ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu");
+ ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
if (!ret) {
of_node_put(np);
return -ENOENT;

228
target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch
View File

@ -1,228 +0,0 @@
From 6a114526af4689938863bf34976c83bfd279f517 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 15 Jun 2020 23:06:02 +0200
Subject: PCI: qcom: Use bulk clk api and assert on error
Rework 2.1.0 revision to use bulk clk api and fix missing assert on
reset_control_deassert error.
Link: https://lore.kernel.org/r/20200615210608.21469-7-ansuelsmth@gmail.com
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 131 ++++++++++++---------------------
1 file changed, 46 insertions(+), 85 deletions(-)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -99,12 +99,9 @@
#define SLV_ADDR_SPACE_SZ 0x10000000
#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
+#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
struct qcom_pcie_resources_2_1_0 {
- struct clk *iface_clk;
- struct clk *core_clk;
- struct clk *phy_clk;
- struct clk *aux_clk;
- struct clk *ref_clk;
+ struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
struct reset_control *pci_reset;
struct reset_control *axi_reset;
struct reset_control *ahb_reset;
@@ -244,25 +241,21 @@ static int qcom_pcie_get_resources_2_1_0
if (ret)
return ret;
- res->iface_clk = devm_clk_get(dev, "iface");
- if (IS_ERR(res->iface_clk))
- return PTR_ERR(res->iface_clk);
-
- res->core_clk = devm_clk_get(dev, "core");
- if (IS_ERR(res->core_clk))
- return PTR_ERR(res->core_clk);
-
- res->phy_clk = devm_clk_get(dev, "phy");
- if (IS_ERR(res->phy_clk))
- return PTR_ERR(res->phy_clk);
-
- res->aux_clk = devm_clk_get_optional(dev, "aux");
- if (IS_ERR(res->aux_clk))
- return PTR_ERR(res->aux_clk);
-
- res->ref_clk = devm_clk_get_optional(dev, "ref");
- if (IS_ERR(res->ref_clk))
- return PTR_ERR(res->ref_clk);
+ res->clks[0].id = "iface";
+ res->clks[1].id = "core";
+ res->clks[2].id = "phy";
+ res->clks[3].id = "aux";
+ res->clks[4].id = "ref";
+
+ /* iface, core, phy are required */
+ ret = devm_clk_bulk_get(dev, 3, res->clks);
+ if (ret < 0)
+ return ret;
+
+ /* aux, ref are optional */
+ ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
+ if (ret < 0)
+ return ret;
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
if (IS_ERR(res->pci_reset))
@@ -292,17 +285,13 @@ static void qcom_pcie_deinit_2_1_0(struc
{
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
- clk_disable_unprepare(res->phy_clk);
+ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
reset_control_assert(res->pci_reset);
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
reset_control_assert(res->ext_reset);
reset_control_assert(res->phy_reset);
- clk_disable_unprepare(res->iface_clk);
- clk_disable_unprepare(res->core_clk);
- clk_disable_unprepare(res->aux_clk);
- clk_disable_unprepare(res->ref_clk);
writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
@@ -334,47 +323,45 @@ static int qcom_pcie_init_2_1_0(struct q
return ret;
}
- ret = reset_control_assert(res->ahb_reset);
+ ret = reset_control_deassert(res->ahb_reset);
if (ret) {
- dev_err(dev, "cannot assert ahb reset\n");
- goto err_assert_ahb;
+ dev_err(dev, "cannot deassert ahb reset\n");
+ goto err_deassert_ahb;
}
- ret = clk_prepare_enable(res->iface_clk);
+ ret = reset_control_deassert(res->ext_reset);
if (ret) {
- dev_err(dev, "cannot prepare/enable iface clock\n");
- goto err_assert_ahb;
+ dev_err(dev, "cannot deassert ext reset\n");
+ goto err_deassert_ext;
}
- ret = clk_prepare_enable(res->core_clk);
+ ret = reset_control_deassert(res->phy_reset);
if (ret) {
- dev_err(dev, "cannot prepare/enable core clock\n");
- goto err_clk_core;
+ dev_err(dev, "cannot deassert phy reset\n");
+ goto err_deassert_phy;
}
- ret = clk_prepare_enable(res->aux_clk);
+ ret = reset_control_deassert(res->pci_reset);
if (ret) {
- dev_err(dev, "cannot prepare/enable aux clock\n");
- goto err_clk_aux;
+ dev_err(dev, "cannot deassert pci reset\n");
+ goto err_deassert_pci;
}
- ret = clk_prepare_enable(res->ref_clk);
+ ret = reset_control_deassert(res->por_reset);
if (ret) {
- dev_err(dev, "cannot prepare/enable ref clock\n");
- goto err_clk_ref;
+ dev_err(dev, "cannot deassert por reset\n");
+ goto err_deassert_por;
}
- ret = reset_control_deassert(res->ahb_reset);
+ ret = reset_control_deassert(res->axi_reset);
if (ret) {
- dev_err(dev, "cannot deassert ahb reset\n");
- goto err_deassert_ahb;
+ dev_err(dev, "cannot deassert axi reset\n");
+ goto err_deassert_axi;
}
- ret = reset_control_deassert(res->ext_reset);
- if (ret) {
- dev_err(dev, "cannot deassert ext reset\n");
- goto err_deassert_ahb;
- }
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
+ if (ret)
+ goto err_clks;
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
@@ -408,36 +395,6 @@ static int qcom_pcie_init_2_1_0(struct q
val |= PHY_REFCLK_SSP_EN;
writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
- ret = reset_control_deassert(res->phy_reset);
- if (ret) {
- dev_err(dev, "cannot deassert phy reset\n");
- return ret;
- }
-
- ret = reset_control_deassert(res->pci_reset);
- if (ret) {
- dev_err(dev, "cannot deassert pci reset\n");
- return ret;
- }
-
- ret = reset_control_deassert(res->por_reset);
- if (ret) {
- dev_err(dev, "cannot deassert por reset\n");
- return ret;
- }
-
- ret = reset_control_deassert(res->axi_reset);
- if (ret) {
- dev_err(dev, "cannot deassert axi reset\n");
- return ret;
- }
-
- ret = clk_prepare_enable(res->phy_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable phy clock\n");
- goto err_deassert_ahb;
- }
-
/* wait for clock acquisition */
usleep_range(1000, 1500);
@@ -450,15 +407,19 @@ static int qcom_pcie_init_2_1_0(struct q
return 0;
+err_clks:
+ reset_control_assert(res->axi_reset);
+err_deassert_axi:
+ reset_control_assert(res->por_reset);
+err_deassert_por:
+ reset_control_assert(res->pci_reset);
+err_deassert_pci:
+ reset_control_assert(res->phy_reset);
+err_deassert_phy:
+ reset_control_assert(res->ext_reset);
+err_deassert_ext:
+ reset_control_assert(res->ahb_reset);
err_deassert_ahb:
- clk_disable_unprepare(res->ref_clk);
-err_clk_ref:
- clk_disable_unprepare(res->aux_clk);
-err_clk_aux:
- clk_disable_unprepare(res->core_clk);
-err_clk_core:
- clk_disable_unprepare(res->iface_clk);
-err_assert_ahb:
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
return ret;

36
target/linux/ipq806x/patches-5.4/093-7-v5.8-ipq806x-PCI-qcom-Add-ipq8064-rev2-variant.patch
View File

@ -1,36 +0,0 @@
From 8df093fe2ae1717389df0dcdc620c02cc35abb21 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 15 Jun 2020 23:06:05 +0200
Subject: PCI: qcom: Add ipq8064 rev2 variant
Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit
different offset based on the revision.
Link: https://lore.kernel.org/r/20200615210608.21469-10-ansuelsmth@gmail.com
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -368,7 +368,8 @@ static int qcom_pcie_init_2_1_0(struct q
val &= ~BIT(0);
writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
- if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
+ of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
@@ -1330,6 +1331,7 @@ err_pm_runtime_put:
static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
{ .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
+ { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },

74
target/linux/ipq806x/patches-5.4/093-8-v5.8-ipq806x-PCI-qcom-Support-pci-speed-set-for-ipq806x.patch
View File

@ -1,74 +0,0 @@
From 51ed2c2b60265006bde7531d10993cf24def0aee Mon Sep 17 00:00:00 2001
From: Sham Muthayyan <smuthayy@codeaurora.org>
Date: Mon, 15 Jun 2020 23:06:07 +0200
Subject: PCI: qcom: Support pci speed set for ipq806x
Some SoC based on ipq8064/5 needs to be limited to pci GEN1 speed due to
some hardware limitations. Add support for speed setting defined by the
max-link-speed binding. If not defined the max speed is set to GEN2 by
default.
Link: https://lore.kernel.org/r/20200615210608.21469-12-ansuelsmth@gmail.com
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
---
Backported with light changes:
* One include is missing in kernel 5.4
drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -27,6 +27,7 @@
#include <linux/slab.h>
#include <linux/types.h>
+#include "../../pci.h"
#include "pcie-designware.h"
#define PCIE20_PARF_SYS_CTRL 0x00
@@ -98,6 +99,8 @@
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define SLV_ADDR_SPACE_SZ 0x10000000
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
+
#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
struct qcom_pcie_resources_2_1_0 {
@@ -184,6 +187,7 @@ struct qcom_pcie {
struct phy *phy;
struct gpio_desc *reset;
const struct qcom_pcie_ops *ops;
+ int gen;
};
#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
@@ -399,6 +403,11 @@ static int qcom_pcie_init_2_1_0(struct q
/* wait for clock acquisition */
usleep_range(1000, 1500);
+ if (pcie->gen == 1) {
+ val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
+ val |= PCI_EXP_LNKSTA_CLS_2_5GB;
+ writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
+ }
/* Set the Max TLP size to 2K, instead of using default of 4K */
writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
@@ -1263,6 +1272,10 @@ static int qcom_pcie_probe(struct platfo
goto err_pm_runtime_put;
}
+ pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
+ if (pcie->gen < 0)
+ pcie->gen = 2;
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
pcie->parf = devm_ioremap_resource(dev, res);
if (IS_ERR(pcie->parf)) {

51
target/linux/ipq806x/patches-5.4/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch
View File

@ -1,51 +0,0 @@
From a206d4061f1cc2c5cd17ee45c53a0ba711e48e6d Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Sun, 7 Feb 2021 16:42:52 +0100
Subject: [PATCH 3/3] drivers: cpufreq: qcom-cpufreq-nvmem: support specific
cpufreq driver
Add support for specific cpufreq driver for qcom-cpufreq-nvmem driver.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -52,6 +52,7 @@ struct qcom_cpufreq_match_data {
char **pvs_name,
struct qcom_cpufreq_drv *drv);
const char **genpd_names;
+ const char *cpufreq_driver;
};
struct qcom_cpufreq_drv {
@@ -250,6 +251,7 @@ static const struct qcom_cpufreq_match_d
static const struct qcom_cpufreq_match_data match_data_krait = {
.get_version = qcom_cpufreq_krait_name_version,
+ .cpufreq_driver = "krait-cpufreq",
};
static const char *qcs404_genpd_names[] = { "cpr", NULL };
@@ -385,6 +387,19 @@ static int qcom_cpufreq_probe(struct pla
}
}
+ if (drv->data->cpufreq_driver) {
+ cpufreq_dt_pdev = platform_device_register_simple(
+ drv->data->cpufreq_driver, -1, NULL, 0);
+ if (!IS_ERR(cpufreq_dt_pdev)) {
+ platform_set_drvdata(pdev, drv);
+ return 0;
+ } else {
+ dev_err(cpu_dev,
+ "Failed to register dedicated %s cpufreq\n",
+ drv->data->cpufreq_driver);
+ }
+ }
+
cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
NULL, 0);
if (!IS_ERR(cpufreq_dt_pdev)) {

216
target/linux/ipq806x/patches-5.4/094-v5.7-ipq806x-net-mdio-add-ipq8064-mdio-driver.patch
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@ -1,216 +0,0 @@
From caaa71fac36ec8c19145dbf8262a9b77ab09f1a1 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Wed, 4 Mar 2020 22:38:32 +0100
Subject: net: mdio: add ipq8064 mdio driver
Currently ipq806x soc use generic bitbang driver to
comunicate with the gmac ethernet interface.
Add a dedicated driver created by chunkeey to fix this.
Co-developed-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/Kconfig | 8 ++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/mdio-ipq8064.c | 166 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 175 insertions(+)
create mode 100644 drivers/net/phy/mdio-ipq8064.c
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -156,6 +156,14 @@ config MDIO_I2C
This is library mode.
+config MDIO_IPQ8064
+ tristate "Qualcomm IPQ8064 MDIO interface support"
+ depends on HAS_IOMEM && OF_MDIO
+ depends on MFD_SYSCON
+ help
+ This driver supports the MDIO interface found in the network
+ interface units of the IPQ8064 SoC
+
config MDIO_MOXART
tristate "MOXA ART MDIO interface support"
depends on ARCH_MOXART || COMPILE_TEST
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium
obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o
+obj-$(CONFIG_MDIO_IPQ8064) += mdio-ipq8064.o
obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
--- /dev/null
+++ b/drivers/net/phy/mdio-ipq8064.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Qualcomm IPQ8064 MDIO interface driver
+ *
+ * Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
+ * Copyright (C) 2020 Ansuel Smith <ansuelsmth@gmail.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/of_mdio.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/syscon.h>
+
+/* MII address register definitions */
+#define MII_ADDR_REG_ADDR 0x10
+#define MII_BUSY BIT(0)
+#define MII_WRITE BIT(1)
+#define MII_CLKRANGE_60_100M (0 << 2)
+#define MII_CLKRANGE_100_150M (1 << 2)
+#define MII_CLKRANGE_20_35M (2 << 2)
+#define MII_CLKRANGE_35_60M (3 << 2)
+#define MII_CLKRANGE_150_250M (4 << 2)
+#define MII_CLKRANGE_250_300M (5 << 2)
+#define MII_CLKRANGE_MASK GENMASK(4, 2)
+#define MII_REG_SHIFT 6
+#define MII_REG_MASK GENMASK(10, 6)
+#define MII_ADDR_SHIFT 11
+#define MII_ADDR_MASK GENMASK(15, 11)
+
+#define MII_DATA_REG_ADDR 0x14
+
+#define MII_MDIO_DELAY_USEC (1000)
+#define MII_MDIO_RETRY_MSEC (10)
+
+struct ipq8064_mdio {
+ struct regmap *base; /* NSS_GMAC0_BASE */
+};
+
+static int
+ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
+{
+ u32 busy;
+
+ return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy,
+ !(busy & MII_BUSY), MII_MDIO_DELAY_USEC,
+ MII_MDIO_RETRY_MSEC * USEC_PER_MSEC);
+}
+
+static int
+ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
+{
+ u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
+ struct ipq8064_mdio *priv = bus->priv;
+ u32 ret_val;
+ int err;
+
+ /* Reject clause 45 */
+ if (reg_offset & MII_ADDR_C45)
+ return -EOPNOTSUPP;
+
+ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
+ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
+
+ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
+ usleep_range(8, 10);
+
+ err = ipq8064_mdio_wait_busy(priv);
+ if (err)
+ return err;
+
+ regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val);
+ return (int)ret_val;
+}
+
+static int
+ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
+{
+ u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
+ struct ipq8064_mdio *priv = bus->priv;
+
+ /* Reject clause 45 */
+ if (reg_offset & MII_ADDR_C45)
+ return -EOPNOTSUPP;
+
+ regmap_write(priv->base, MII_DATA_REG_ADDR, data);
+
+ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
+ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
+
+ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
+ usleep_range(8, 10);
+
+ return ipq8064_mdio_wait_busy(priv);
+}
+
+static int
+ipq8064_mdio_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct ipq8064_mdio *priv;
+ struct mii_bus *bus;
+ int ret;
+
+ bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
+ if (!bus)
+ return -ENOMEM;
+
+ bus->name = "ipq8064_mdio_bus";
+ bus->read = ipq8064_mdio_read;
+ bus->write = ipq8064_mdio_write;
+ snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
+ bus->parent = &pdev->dev;
+
+ priv = bus->priv;
+ priv->base = device_node_to_regmap(np);
+ if (IS_ERR(priv->base)) {
+ if (priv->base == ERR_PTR(-EPROBE_DEFER))
+ return -EPROBE_DEFER;
+
+ dev_err(&pdev->dev, "error getting device regmap, error=%pe\n",
+ priv->base);
+ return PTR_ERR(priv->base);
+ }
+
+ ret = of_mdiobus_register(bus, np);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, bus);
+ return 0;
+}
+
+static int
+ipq8064_mdio_remove(struct platform_device *pdev)
+{
+ struct mii_bus *bus = platform_get_drvdata(pdev);
+
+ mdiobus_unregister(bus);
+
+ return 0;
+}
+
+static const struct of_device_id ipq8064_mdio_dt_ids[] = {
+ { .compatible = "qcom,ipq8064-mdio" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids);
+
+static struct platform_driver ipq8064_mdio_driver = {
+ .probe = ipq8064_mdio_probe,
+ .remove = ipq8064_mdio_remove,
+ .driver = {
+ .name = "ipq8064-mdio",
+ .of_match_table = ipq8064_mdio_dt_ids,
+ },
+};
+
+module_platform_driver(ipq8064_mdio_driver);
+
+MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
+MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
+MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");

621
target/linux/ipq806x/patches-5.4/095-1-v5.9-phy-qualcomm-add-qcom-ipq806x-dwc-usb-phy-driver.patch
View File

@ -1,621 +0,0 @@
From ef19b117b83466e1c030368101a24367a34be7f0 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Fri, 17 Jul 2020 15:16:31 +0200
Subject: phy: qualcomm: add qcom ipq806x dwc usb phy driver
This has lost in the original push for the dwc3 qcom driver.
This is needed for ipq806x SoC as without this the usb ports
doesn't work at all.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
Link: https://lore.kernel.org/r/20200717131635.11076-1-ansuelsmth@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
Light modification to Kconfig as some config are missing in kernel 5.4
drivers/phy/qualcomm/Kconfig | 10 +
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 571 ++++++++++++++++++++++++++++
3 files changed, 582 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -91,3 +91,13 @@ config PHY_QCOM_USB_HSIC
select GENERIC_PHY
help
Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
+
+config PHY_QCOM_IPQ806X_USB
+ tristate "Qualcomm IPQ806x DWC3 USB PHY driver"
+ depends on HAS_IOMEM
+ depends on OF && (ARCH_QCOM || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ This option enables support for the Synopsis PHYs present inside the
+ Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports
+ both HS and SS PHY controllers.
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-
obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o
obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_USB) += phy-qcom-ipq806x-usb.o
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
@@ -0,0 +1,571 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+/* USB QSCRATCH Hardware registers */
+#define QSCRATCH_GENERAL_CFG (0x08)
+#define HSUSB_PHY_CTRL_REG (0x10)
+
+/* PHY_CTRL_REG */
+#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
+#define HSUSB_CTRL_USB2_SUSPEND BIT(23)
+#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
+#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
+#define HSUSB_CTRL_USE_CLKCORE BIT(18)
+#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
+#define HSUSB_CTRL_COMMONONN BIT(11)
+#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
+#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
+#define HSUSB_CTRL_CLAMP_EN BIT(7)
+#define HSUSB_CTRL_RETENABLEN BIT(1)
+#define HSUSB_CTRL_POR BIT(0)
+
+/* QSCRATCH_GENERAL_CFG */
+#define HSUSB_GCFG_XHCI_REV BIT(2)
+
+/* USB QSCRATCH Hardware registers */
+#define SSUSB_PHY_CTRL_REG (0x00)
+#define SSUSB_PHY_PARAM_CTRL_1 (0x04)
+#define SSUSB_PHY_PARAM_CTRL_2 (0x08)
+#define CR_PROTOCOL_DATA_IN_REG (0x0c)
+#define CR_PROTOCOL_DATA_OUT_REG (0x10)
+#define CR_PROTOCOL_CAP_ADDR_REG (0x14)
+#define CR_PROTOCOL_CAP_DATA_REG (0x18)
+#define CR_PROTOCOL_READ_REG (0x1c)
+#define CR_PROTOCOL_WRITE_REG (0x20)
+
+/* PHY_CTRL_REG */
+#define SSUSB_CTRL_REF_USE_PAD BIT(28)
+#define SSUSB_CTRL_TEST_POWERDOWN BIT(27)
+#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24)
+#define SSUSB_CTRL_SS_PHY_EN BIT(8)
+#define SSUSB_CTRL_SS_PHY_RESET BIT(7)
+
+/* SSPHY control registers - Does this need 0x30? */
+#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * (lane))
+#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * (lane))
+
+/* SSPHY SoC version specific values */
+#define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */
+/* Override value for transmit preemphasis */
+#define SSPHY_TX_DEEMPH_3_5DB 23
+/* Override value for mpll */
+#define SSPHY_MPLL_VALUE 0
+
+/* QSCRATCH PHY_PARAM_CTRL1 fields */
+#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK GENMASK(26, 19)
+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK GENMASK(19, 13)
+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK GENMASK(13, 7)
+#define PHY_PARAM_CTRL1_LOS_BIAS_MASK GENMASK(7, 2)
+
+#define PHY_PARAM_CTRL1_MASK \
+ (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \
+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \
+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \
+ PHY_PARAM_CTRL1_LOS_BIAS_MASK)
+
+#define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \
+ (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \
+ (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \
+ (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
+#define PHY_PARAM_CTRL1_LOS_BIAS(x) \
+ (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
+
+/* RX OVRD IN HI bits */
+#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13)
+#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12)
+#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11)
+#define RX_OVRD_IN_HI_RX_EQ_MASK GENMASK(10, 7)
+#define RX_OVRD_IN_HI_RX_EQ(x) ((x) << 8)
+#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
+#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
+#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5)
+#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK GENMASK(4, 2)
+#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
+#define RX_OVRD_IN_HI_RX_RATE_MASK GENMASK(2, 0)
+
+/* TX OVRD DRV LO register bits */
+#define TX_OVRD_DRV_LO_AMPLITUDE_MASK GENMASK(6, 0)
+#define TX_OVRD_DRV_LO_PREEMPH_MASK GENMASK(13, 6)
+#define TX_OVRD_DRV_LO_PREEMPH(x) ((x) << 7)
+#define TX_OVRD_DRV_LO_EN BIT(14)
+
+/* MPLL bits */
+#define SSPHY_MPLL_MASK GENMASK(8, 5)
+#define SSPHY_MPLL(x) ((x) << 5)
+
+/* SS CAP register bits */
+#define SS_CR_CAP_ADDR_REG BIT(0)
+#define SS_CR_CAP_DATA_REG BIT(0)
+#define SS_CR_READ_REG BIT(0)
+#define SS_CR_WRITE_REG BIT(0)
+
+struct usb_phy {
+ void __iomem *base;
+ struct device *dev;
+ struct clk *xo_clk;
+ struct clk *ref_clk;
+ u32 rx_eq;
+ u32 tx_deamp_3_5db;
+ u32 mpll;
+};
+
+struct phy_drvdata {
+ struct phy_ops ops;
+ u32 clk_rate;
+};
+
+/**
+ * Write register and read back masked value to confirm it is written
+ *
+ * @base - QCOM DWC3 PHY base virtual address.
+ * @offset - register offset.
+ * @mask - register bitmask specifying what should be updated
+ * @val - value to write.
+ */
+static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3,
+ u32 offset,
+ const u32 mask, u32 val)
+{
+ u32 write_val, tmp = readl(phy_dwc3->base + offset);
+
+ tmp &= ~mask; /* retain other bits */
+ write_val = tmp | val;
+
+ writel(write_val, phy_dwc3->base + offset);
+
+ /* Read back to see if val was written */
+ tmp = readl(phy_dwc3->base + offset);
+ tmp &= mask; /* clear other bits */
+
+ if (tmp != val)
+ dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", val, offset);
+}
+
+static int wait_for_latch(void __iomem *addr)
+{
+ u32 retry = 10;
+
+ while (true) {
+ if (!readl(addr))
+ break;
+
+ if (--retry == 0)
+ return -ETIMEDOUT;
+
+ usleep_range(10, 20);
+ }
+
+ return 0;
+}
+
+/**
+ * Write SSPHY register
+ *
+ * @base - QCOM DWC3 PHY base virtual address.
+ * @addr - SSPHY address to write.
+ * @val - value to write.
+ */
+static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3,
+ u32 addr, u32 val)
+{
+ int ret;
+
+ writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
+ writel(SS_CR_CAP_ADDR_REG,
+ phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
+
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
+ if (ret)
+ goto err_wait;
+
+ writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
+ writel(SS_CR_CAP_DATA_REG,
+ phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
+
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
+ if (ret)
+ goto err_wait;
+
+ writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
+
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
+
+err_wait:
+ if (ret)
+ dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
+ return ret;
+}
+
+/**
+ * Read SSPHY register.
+ *
+ * @base - QCOM DWC3 PHY base virtual address.
+ * @addr - SSPHY address to read.
+ */
+static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3,
+ u32 addr, u32 *val)
+{
+ int ret;
+
+ writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
+ writel(SS_CR_CAP_ADDR_REG,
+ phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
+
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
+ if (ret)
+ goto err_wait;
+
+ /*
+ * Due to hardware bug, first read of SSPHY register might be
+ * incorrect. Hence as workaround, SW should perform SSPHY register
+ * read twice, but use only second read and ignore first read.
+ */
+ writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
+
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
+ if (ret)
+ goto err_wait;
+
+ /* throwaway read */
+ readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
+
+ writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
+
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
+ if (ret)
+ goto err_wait;
+
+ *val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
+
+err_wait:
+ return ret;
+}
+
+static int qcom_ipq806x_usb_hs_phy_init(struct phy *phy)
+{
+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
+ int ret;
+ u32 val;
+
+ ret = clk_prepare_enable(phy_dwc3->xo_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(phy_dwc3->ref_clk);
+ if (ret) {
+ clk_disable_unprepare(phy_dwc3->xo_clk);
+ return ret;
+ }
+
+ /*
+ * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
+ * enable clamping, and disable RETENTION (power-on default is ENABLED)
+ */
+ val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
+ HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN |
+ HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
+ HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
+ HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
+
+ /* use core clock if external reference is not present */
+ if (!phy_dwc3->xo_clk)
+ val |= HSUSB_CTRL_USE_CLKCORE;
+
+ writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
+ usleep_range(2000, 2200);
+
+ /* Disable (bypass) VBUS and ID filters */
+ writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
+
+ return 0;
+}
+
+static int qcom_ipq806x_usb_hs_phy_exit(struct phy *phy)
+{
+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
+
+ clk_disable_unprepare(phy_dwc3->ref_clk);
+ clk_disable_unprepare(phy_dwc3->xo_clk);
+
+ return 0;
+}
+
+static int qcom_ipq806x_usb_ss_phy_init(struct phy *phy)
+{
+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
+ int ret;
+ u32 data;
+
+ ret = clk_prepare_enable(phy_dwc3->xo_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(phy_dwc3->ref_clk);
+ if (ret) {
+ clk_disable_unprepare(phy_dwc3->xo_clk);
+ return ret;
+ }
+
+ /* reset phy */
+ data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
+ writel(data | SSUSB_CTRL_SS_PHY_RESET,
+ phy_dwc3->base + SSUSB_PHY_CTRL_REG);
+ usleep_range(2000, 2200);
+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
+
+ /* clear REF_PAD if we don't have XO clk */
+ if (!phy_dwc3->xo_clk)
+ data &= ~SSUSB_CTRL_REF_USE_PAD;
+ else
+ data |= SSUSB_CTRL_REF_USE_PAD;
+
+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
+
+ /* wait for ref clk to become stable, this can take up to 30ms */
+ msleep(30);
+
+ data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
+
+ /*
+ * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
+ * in HS mode instead of SS mode. Workaround it by asserting
+ * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
+ */
+ ret = usb_ss_read_phycreg(phy_dwc3, 0x102D, &data);
+ if (ret)
+ goto err_phy_trans;
+
+ data |= (1 << 7);
+ ret = usb_ss_write_phycreg(phy_dwc3, 0x102D, data);
+ if (ret)
+ goto err_phy_trans;
+
+ ret = usb_ss_read_phycreg(phy_dwc3, 0x1010, &data);
+ if (ret)
+ goto err_phy_trans;
+
+ data &= ~0xff0;
+ data |= 0x20;
+ ret = usb_ss_write_phycreg(phy_dwc3, 0x1010, data);
+ if (ret)
+ goto err_phy_trans;
+
+ /*
+ * Fix RX Equalization setting as follows
+ * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
+ * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
+ * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
+ * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
+ */
+ ret = usb_ss_read_phycreg(phy_dwc3, SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
+ if (ret)
+ goto err_phy_trans;
+
+ data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
+ data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
+ data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
+ data |= RX_OVRD_IN_HI_RX_EQ(phy_dwc3->rx_eq);
+ data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
+ ret = usb_ss_write_phycreg(phy_dwc3,
+ SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
+ if (ret)
+ goto err_phy_trans;
+
+ /*
+ * Set EQ and TX launch amplitudes as follows
+ * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
+ * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
+ * LANE0.TX_OVRD_DRV_LO.EN set to 1.
+ */
+ ret = usb_ss_read_phycreg(phy_dwc3,
+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
+ if (ret)
+ goto err_phy_trans;
+
+ data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
+ data |= TX_OVRD_DRV_LO_PREEMPH(phy_dwc3->tx_deamp_3_5db);
+ data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
+ data |= 0x6E;
+ data |= TX_OVRD_DRV_LO_EN;
+ ret = usb_ss_write_phycreg(phy_dwc3,
+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
+ if (ret)
+ goto err_phy_trans;
+
+ data = 0;
+ data &= ~SSPHY_MPLL_MASK;
+ data |= SSPHY_MPLL(phy_dwc3->mpll);
+ usb_ss_write_phycreg(phy_dwc3, 0x30, data);
+
+ /*
+ * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
+ * TX_FULL_SWING [26:20] amplitude to 110
+ * TX_DEEMPH_6DB [19:14] to 32
+ * TX_DEEMPH_3_5DB [13:8] set based on SoC version
+ * LOS_BIAS [7:3] to 9
+ */
+ data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
+
+ data &= ~PHY_PARAM_CTRL1_MASK;
+
+ data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
+ PHY_PARAM_CTRL1_LOS_BIAS(0x9);
+
+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
+ PHY_PARAM_CTRL1_MASK, data);
+
+err_phy_trans:
+ return ret;
+}
+
+static int qcom_ipq806x_usb_ss_phy_exit(struct phy *phy)
+{
+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
+
+ /* Sequence to put SSPHY in low power state:
+ * 1. Clear REF_PHY_EN in PHY_CTRL_REG
+ * 2. Clear REF_USE_PAD in PHY_CTRL_REG
+ * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
+ */
+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
+ SSUSB_CTRL_SS_PHY_EN, 0x0);
+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
+ SSUSB_CTRL_REF_USE_PAD, 0x0);
+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
+ SSUSB_CTRL_TEST_POWERDOWN, 0x0);
+
+ clk_disable_unprepare(phy_dwc3->ref_clk);
+ clk_disable_unprepare(phy_dwc3->xo_clk);
+
+ return 0;
+}
+
+static const struct phy_drvdata qcom_ipq806x_usb_hs_drvdata = {
+ .ops = {
+ .init = qcom_ipq806x_usb_hs_phy_init,
+ .exit = qcom_ipq806x_usb_hs_phy_exit,
+ .owner = THIS_MODULE,
+ },
+ .clk_rate = 60000000,
+};
+
+static const struct phy_drvdata qcom_ipq806x_usb_ss_drvdata = {
+ .ops = {
+ .init = qcom_ipq806x_usb_ss_phy_init,
+ .exit = qcom_ipq806x_usb_ss_phy_exit,
+ .owner = THIS_MODULE,
+ },
+ .clk_rate = 125000000,
+};
+
+static const struct of_device_id qcom_ipq806x_usb_phy_table[] = {
+ { .compatible = "qcom,ipq806x-usb-phy-hs",
+ .data = &qcom_ipq806x_usb_hs_drvdata },
+ { .compatible = "qcom,ipq806x-usb-phy-ss",
+ .data = &qcom_ipq806x_usb_ss_drvdata },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, qcom_ipq806x_usb_phy_table);
+
+static int qcom_ipq806x_usb_phy_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ resource_size_t size;
+ struct phy *generic_phy;
+ struct usb_phy *phy_dwc3;
+ const struct phy_drvdata *data;
+ struct phy_provider *phy_provider;
+
+ phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
+ if (!phy_dwc3)
+ return -ENOMEM;
+
+ data = of_device_get_match_data(&pdev->dev);
+
+ phy_dwc3->dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -EINVAL;
+ size = resource_size(res);
+ phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
+
+ if (IS_ERR(phy_dwc3->base)) {
+ dev_err(phy_dwc3->dev, "failed to map reg\n");
+ return PTR_ERR(phy_dwc3->base);
+ }
+
+ phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
+ if (IS_ERR(phy_dwc3->ref_clk)) {
+ dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
+ return PTR_ERR(phy_dwc3->ref_clk);
+ }
+
+ clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
+
+ phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
+ if (IS_ERR(phy_dwc3->xo_clk)) {
+ dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
+ phy_dwc3->xo_clk = NULL;
+ }
+
+ /* Parse device node to probe HSIO settings */
+ if (device_property_read_u32(&pdev->dev, "qcom,rx-eq",
+ &phy_dwc3->rx_eq))
+ phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
+
+ if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
+ &phy_dwc3->tx_deamp_3_5db))
+ phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB;
+
+ if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
+ phy_dwc3->mpll = SSPHY_MPLL_VALUE;
+
+ generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, &data->ops);
+
+ if (IS_ERR(generic_phy))
+ return PTR_ERR(generic_phy);
+
+ phy_set_drvdata(generic_phy, phy_dwc3);
+ platform_set_drvdata(pdev, phy_dwc3);
+
+ phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
+ of_phy_simple_xlate);
+
+ if (IS_ERR(phy_provider))
+ return PTR_ERR(phy_provider);
+
+ return 0;
+}
+
+static struct platform_driver qcom_ipq806x_usb_phy_driver = {
+ .probe = qcom_ipq806x_usb_phy_probe,
+ .driver = {
+ .name = "qcom-ipq806x-usb-phy",
+ .owner = THIS_MODULE,
+ .of_match_table = qcom_ipq806x_usb_phy_table,
+ },
+};
+
+module_platform_driver(qcom_ipq806x_usb_phy_driver);
+
+MODULE_ALIAS("platform:phy-qcom-ipq806x-usb");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
+MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
+MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");

31
target/linux/ipq806x/patches-5.4/095-2-v5.9-phy-qualcomm-fix-setting-of-tx_deamp_3_5db-when-device-property-read-fails.patch
View File

@ -1,31 +0,0 @@
From 3d7b0ca5300bd01b176f2b4c10e173db802560d8 Mon Sep 17 00:00:00 2001
From: Colin Ian King <colin.king@canonical.com>
Date: Tue, 21 Jul 2020 16:06:13 +0100
Subject: phy: qualcomm: fix setting of tx_deamp_3_5db when device property
read fails
Currently when reading of the device property for "qcom,tx-deamp_3_5db"
fails the default is being assigned incorrectly to phy_dwc3->rx_eq. This
looks like a copy-n-paste error and in fact should be assigning the
default instead to phy_dwc3->tx_deamp_3_5db
Addresses-Coverity: ("Copy-paste error")
Fixes: ef19b117b834 ("phy: qualcomm: add qcom ipq806x dwc usb phy driver")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20200721150613.416876-1-colin.king@canonical.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
@@ -531,7 +531,7 @@ static int qcom_ipq806x_usb_phy_probe(st
if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
&phy_dwc3->tx_deamp_3_5db))
- phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB;
+ phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
phy_dwc3->mpll = SSPHY_MPLL_VALUE;

681
target/linux/ipq806x/patches-5.4/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch
View File

@ -1,681 +0,0 @@
From cc41a266280cad0b55319e614167c88dff344248 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Sat, 22 Feb 2020 16:33:10 +0100
Subject: [PATCH 1/8] cpufreq: add Krait dedicated scaling driver
This new driver is based on generic cpufreq-dt driver.
Krait SoCs have 2-4 cpu and one shared L2 cache that can
operate at different frequency based on the maximum cpu clk
across all core.
L2 frequency and voltage are scaled on every frequency change
if needed. On Krait SoCs is present a bug that can cause
transition problem between frequency bin, to workaround this
on more than one transition, the L2 frequency is first set to the
base rate and then to the target rate.
The L2 frequency use the OPP framework and use the opp-level
bindings to link the l2 freq to different cpu freq. This is needed
as the Krait l2 clk are note mapped 1:1 to the core clks and some
of the l2 clk is set based on a range of the cpu clks. If the driver
find a broken config (for example no opp-level set) the l2 scaling is
skipped.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/cpufreq/Kconfig.arm | 14 +-
drivers/cpufreq/Makefile | 2 +
drivers/cpufreq/qcom-cpufreq-krait.c | 589 +++++++++++++++++++++++++++
3 files changed, 604 insertions(+), 1 deletion(-)
create mode 100644 drivers/cpufreq/qcom-cpufreq-krait.c
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -155,6 +155,18 @@ config ARM_QCOM_CPUFREQ_HW
The driver implements the cpufreq interface for this HW engine.
Say Y if you want to support CPUFreq HW.
+config ARM_QCOM_CPUFREQ_KRAIT
+ tristate "CPU Frequency scaling support for Krait SoCs"
+ depends on ARCH_QCOM || COMPILE_TEST
+ select PM_OPP
+ select ARM_QCOM_CPUFREQ_NVMEM
+ help
+ This adds the CPUFreq driver for Qualcomm Krait SoC based boards.
+ This scale the cache clk and regulator based on the different cpu
+ clks when scaling the different cores clk.
+
+ If in doubt, say N.
+
config ARM_RASPBERRYPI_CPUFREQ
tristate "Raspberry Pi cpufreq support"
depends on CLK_RASPBERRYPI || COMPILE_TEST
@@ -338,4 +350,4 @@ config ARM_PXA2xx_CPUFREQ
help
This add the CPUFreq driver support for Intel PXA2xx SOCs.
- If in doubt, say N.
+ If in doubt, say N.
\ No newline at end of file
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2
obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o
obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o
+obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRAIT) += qcom-cpufreq-krait.o
obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) += raspberrypi-cpufreq.o
obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
@@ -87,6 +88,7 @@ obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += te
obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += tegra186-cpufreq.o
obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-cpufreq.o
obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o
+obj-$(CONFIG_ARM_KRAIT_CPUFREQ) += krait-cpufreq.o
##################################################################################
--- /dev/null
+++ b/drivers/cpufreq/qcom-cpufreq-krait.c
@@ -0,0 +1,603 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/clk.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/cpumask.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pm_opp.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <linux/thermal.h>
+
+#include "cpufreq-dt.h"
+
+static struct platform_device *l2_pdev;
+
+struct private_data {
+ struct opp_table *opp_table;
+ struct device *cpu_dev;
+ const char *reg_name;
+ bool have_static_opps;
+};
+
+static int set_target(struct cpufreq_policy *policy, unsigned int index)
+{
+ struct private_data *priv = policy->driver_data;
+ unsigned long freq = policy->freq_table[index].frequency;
+ unsigned long target_freq = freq * 1000;
+ struct dev_pm_opp *opp;
+ unsigned int level;
+ int cpu, ret;
+
+ if (l2_pdev) {
+ int policy_cpu = policy->cpu;
+
+ /* find the max freq across all core */
+ for_each_present_cpu(cpu)
+ if (cpu != policy_cpu)
+ target_freq = max(
+ target_freq,
+ (unsigned long)cpufreq_quick_get(cpu));
+
+ opp = dev_pm_opp_find_freq_exact(priv->cpu_dev, target_freq,
+ true);
+ if (IS_ERR(opp)) {
+ dev_err(&l2_pdev->dev, "failed to find OPP for %ld\n",
+ target_freq);
+ return PTR_ERR(opp);
+ }
+ level = dev_pm_opp_get_level(opp);
+ dev_pm_opp_put(opp);
+
+ /*
+ * Hardware constraint:
+ * Krait CPU cannot operate at 384MHz with L2 at 1Ghz.
+ * Assume index 0 with the idle freq and level > 0 as
+ * any L2 freq > 384MHz.
+ * Skip CPU freq change in this corner case.
+ */
+ if (unlikely(index == 0 && level != 0)) {
+ dev_err(priv->cpu_dev, "Krait CPU can't operate at idle freq with L2 at 1GHz");
+ return -EINVAL;
+ }
+
+ opp = dev_pm_opp_find_level_exact(&l2_pdev->dev, level);
+ if (IS_ERR(opp)) {
+ dev_err(&l2_pdev->dev,
+ "failed to find level OPP for %d\n", level);
+ return PTR_ERR(opp);
+ }
+ target_freq = dev_pm_opp_get_freq(opp);
+ dev_pm_opp_put(opp);
+
+ ret = dev_pm_opp_set_rate(&l2_pdev->dev, target_freq);
+ if (ret)
+ return ret;
+ }
+
+ ret = dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000);
+ if (ret)
+ return ret;
+
+ arch_set_freq_scale(policy->related_cpus, freq,
+ policy->cpuinfo.max_freq);
+
+ return 0;
+}
+
+/*
+ * An earlier version of opp-v1 bindings used to name the regulator
+ * "cpu0-supply", we still need to handle that for backwards compatibility.
+ */
+static const char *find_supply_name(struct device *dev)
+{
+ struct device_node *np;
+ struct property *pp;
+ int cpu = dev->id;
+ const char *name = NULL;
+
+ np = of_node_get(dev->of_node);
+
+ /* This must be valid for sure */
+ if (WARN_ON(!np))
+ return NULL;
+
+ /* Try "cpu0" for older DTs */
+ if (!cpu) {
+ pp = of_find_property(np, "cpu0-supply", NULL);
+ if (pp) {
+ name = "cpu0";
+ goto node_put;
+ }
+ }
+
+ pp = of_find_property(np, "cpu-supply", NULL);
+ if (pp) {
+ name = "cpu";
+ goto node_put;
+ }
+
+ dev_dbg(dev, "no regulator for cpu%d\n", cpu);
+node_put:
+ of_node_put(np);
+ return name;
+}
+
+static int resources_available(void)
+{
+ struct device *cpu_dev;
+ struct regulator *cpu_reg;
+ struct clk *cpu_clk;
+ int ret = 0;
+ const char *name;
+
+ cpu_dev = get_cpu_device(0);
+ if (!cpu_dev) {
+ pr_err("failed to get cpu0 device\n");
+ return -ENODEV;
+ }
+
+ cpu_clk = clk_get(cpu_dev, NULL);
+ ret = PTR_ERR_OR_ZERO(cpu_clk);
+ if (ret) {
+ /*
+ * If cpu's clk node is present, but clock is not yet
+ * registered, we should try defering probe.
+ */
+ if (ret == -EPROBE_DEFER)
+ dev_dbg(cpu_dev, "clock not ready, retry\n");
+ else
+ dev_err(cpu_dev, "failed to get clock: %d\n", ret);
+
+ return ret;
+ }
+
+ clk_put(cpu_clk);
+
+ name = find_supply_name(cpu_dev);
+ /* Platform doesn't require regulator */
+ if (!name)
+ return 0;
+
+ cpu_reg = regulator_get_optional(cpu_dev, name);
+ ret = PTR_ERR_OR_ZERO(cpu_reg);
+ if (ret) {
+ /*
+ * If cpu's regulator supply node is present, but regulator is
+ * not yet registered, we should try defering probe.
+ */
+ if (ret == -EPROBE_DEFER)
+ dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n");
+ else
+ dev_dbg(cpu_dev, "no regulator for cpu0: %d\n", ret);
+
+ return ret;
+ }
+
+ regulator_put(cpu_reg);
+ return 0;
+}
+
+static int cpufreq_init(struct cpufreq_policy *policy)
+{
+ struct cpufreq_frequency_table *freq_table;
+ struct opp_table *opp_table = NULL;
+ unsigned int transition_latency;
+ struct private_data *priv;
+ struct device *cpu_dev;
+ bool fallback = false;
+ struct clk *cpu_clk;
+ const char *name;
+ int ret;
+
+ cpu_dev = get_cpu_device(policy->cpu);
+ if (!cpu_dev) {
+ pr_err("failed to get cpu%d device\n", policy->cpu);
+ return -ENODEV;
+ }
+
+ cpu_clk = clk_get(cpu_dev, NULL);
+ if (IS_ERR(cpu_clk)) {
+ ret = PTR_ERR(cpu_clk);
+ dev_err(cpu_dev, "%s: failed to get clk: %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* Get OPP-sharing information from "operating-points-v2" bindings */
+ ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, policy->cpus);
+ if (ret) {
+ if (ret != -ENOENT)
+ goto out_put_clk;
+
+ /*
+ * operating-points-v2 not supported, fallback to old method of
+ * finding shared-OPPs for backward compatibility if the
+ * platform hasn't set sharing CPUs.
+ */
+ if (dev_pm_opp_get_sharing_cpus(cpu_dev, policy->cpus))
+ fallback = true;
+ }
+
+ /*
+ * OPP layer will be taking care of regulators now, but it needs to know
+ * the name of the regulator first.
+ */
+ name = find_supply_name(cpu_dev);
+ if (name) {
+ opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1);
+ if (IS_ERR(opp_table)) {
+ ret = PTR_ERR(opp_table);
+ dev_err(cpu_dev,
+ "Failed to set regulator for cpu%d: %d\n",
+ policy->cpu, ret);
+ goto out_put_clk;
+ }
+ }
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ ret = -ENOMEM;
+ goto out_put_regulator;
+ }
+
+ priv->reg_name = name;
+ priv->opp_table = opp_table;
+
+ /*
+ * Initialize OPP tables for all policy->cpus. They will be shared by
+ * all CPUs which have marked their CPUs shared with OPP bindings.
+ *
+ * For platforms not using operating-points-v2 bindings, we do this
+ * before updating policy->cpus. Otherwise, we will end up creating
+ * duplicate OPPs for policy->cpus.
+ *
+ * OPPs might be populated at runtime, don't check for error here
+ */
+ if (!dev_pm_opp_of_cpumask_add_table(policy->cpus))
+ priv->have_static_opps = true;
+
+ /*
+ * But we need OPP table to function so if it is not there let's
+ * give platform code chance to provide it for us.
+ */
+ ret = dev_pm_opp_get_opp_count(cpu_dev);
+ if (ret <= 0) {
+ dev_dbg(cpu_dev, "OPP table is not ready, deferring probe\n");
+ ret = -EPROBE_DEFER;
+ goto out_free_opp;
+ }
+
+ if (fallback) {
+ cpumask_setall(policy->cpus);
+
+ /*
+ * OPP tables are initialized only for policy->cpu, do it for
+ * others as well.
+ */
+ ret = dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
+ if (ret)
+ dev_err(cpu_dev,
+ "%s: failed to mark OPPs as shared: %d\n",
+ __func__, ret);
+ }
+
+ ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
+ if (ret) {
+ dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
+ goto out_free_opp;
+ }
+
+ priv->cpu_dev = cpu_dev;
+
+ policy->driver_data = priv;
+ policy->clk = cpu_clk;
+ policy->freq_table = freq_table;
+
+ policy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu_dev) / 1000;
+
+ transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev);
+ if (!transition_latency)
+ transition_latency = CPUFREQ_ETERNAL;
+
+ policy->cpuinfo.transition_latency = transition_latency;
+ policy->dvfs_possible_from_any_cpu = true;
+
+ dev_pm_opp_of_register_em(policy->cpus);
+
+ return 0;
+
+out_free_opp:
+ if (priv->have_static_opps)
+ dev_pm_opp_of_cpumask_remove_table(policy->cpus);
+ kfree(priv);
+out_put_regulator:
+ if (name)
+ dev_pm_opp_put_regulators(opp_table);
+out_put_clk:
+ clk_put(cpu_clk);
+
+ return ret;
+}
+
+static int cpufreq_online(struct cpufreq_policy *policy)
+{
+ /* We did light-weight tear down earlier, nothing to do here */
+ return 0;
+}
+
+static int cpufreq_offline(struct cpufreq_policy *policy)
+{
+ /*
+ * Preserve policy->driver_data and don't free resources on light-weight
+ * tear down.
+ */
+ return 0;
+}
+
+static int cpufreq_exit(struct cpufreq_policy *policy)
+{
+ struct private_data *priv = policy->driver_data;
+
+ dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
+ if (priv->have_static_opps)
+ dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
+ if (priv->reg_name)
+ dev_pm_opp_put_regulators(priv->opp_table);
+
+ clk_put(policy->clk);
+ kfree(priv);
+
+ return 0;
+}
+
+static struct cpufreq_driver krait_cpufreq_driver = {
+ .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
+ CPUFREQ_IS_COOLING_DEV,
+ .verify = cpufreq_generic_frequency_table_verify,
+ .target_index = set_target,
+ .get = cpufreq_generic_get,
+ .init = cpufreq_init,
+ .exit = cpufreq_exit,
+ .online = cpufreq_online,
+ .offline = cpufreq_offline,
+ .name = "krait-cpufreq",
+ .suspend = cpufreq_generic_suspend,
+};
+
+struct krait_data {
+ unsigned long idle_freq;
+ bool regulator_enabled;
+};
+
+static int krait_cache_set_opp(struct dev_pm_set_opp_data *data)
+{
+ unsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate;
+ struct dev_pm_opp_supply *supply = &data->new_opp.supplies[0];
+ struct regulator *reg = data->regulators[0];
+ struct clk *clk = data->clk;
+ struct krait_data *kdata;
+ unsigned long idle_freq;
+ int ret;
+
+ kdata = (struct krait_data *)dev_get_drvdata(data->dev);
+ idle_freq = kdata->idle_freq;
+
+ /* Scaling up? Scale voltage before frequency */
+ if (freq >= old_freq) {
+ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min,
+ supply->u_volt,
+ supply->u_volt_max);
+ if (ret)
+ goto exit;
+ }
+
+ /*
+ * Set to idle bin if switching from normal to high bin
+ * or vice versa. It has been notice that a bug is triggered
+ * in cache scaling when more than one bin is scaled, to fix
+ * this we first need to transition to the base rate and then
+ * to target rate
+ */
+ if (likely(freq != idle_freq && old_freq != idle_freq)) {
+ ret = clk_set_rate(clk, idle_freq);
+ if (ret)
+ goto exit;
+ }
+
+ ret = clk_set_rate(clk, freq);
+ if (ret)
+ goto exit;
+
+ /* Scaling down? Scale voltage after frequency */
+ if (freq < old_freq) {
+ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min,
+ supply->u_volt,
+ supply->u_volt_max);
+ }
+
+ if (unlikely(!kdata->regulator_enabled)) {
+ ret = regulator_enable(reg);
+ if (ret < 0)
+ dev_warn(data->dev, "Failed to enable regulator: %d", ret);
+ else
+ kdata->regulator_enabled = true;
+ }
+
+exit:
+ return ret;
+};
+
+static int krait_cache_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct krait_data *data;
+ struct opp_table *table;
+ struct dev_pm_opp *opp;
+ struct device *cpu_dev;
+ int ret;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ table = dev_pm_opp_set_regulators(dev, (const char *[]){ "l2" }, 1);
+ if (IS_ERR(table)) {
+ ret = PTR_ERR(table);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "failed to set regulators %d\n", ret);
+
+ return ret;
+ }
+
+ ret = PTR_ERR_OR_ZERO(
+ dev_pm_opp_register_set_opp_helper(dev, krait_cache_set_opp));
+ if (ret)
+ return ret;
+
+ ret = dev_pm_opp_of_add_table(dev);
+ if (ret) {
+ dev_err(dev, "failed to parse L2 freq thresholds\n");
+ return ret;
+ }
+
+ opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq);
+ dev_pm_opp_put(opp);
+
+ /*
+ * Check opp-level configuration
+ * At least 2 level must be set or the cache will always be scaled
+ * the idle freq causing some performance problem
+ *
+ * In case of invalid configuration, the l2 scaling is skipped
+ */
+ cpu_dev = get_cpu_device(0);
+ if (!cpu_dev) {
+ pr_err("failed to get cpu0 device\n");
+ return -ENODEV;
+ }
+
+ /*
+ * Check if we have at least opp-level 1, 0 should always be set to
+ * the idle freq
+ */
+ opp = dev_pm_opp_find_level_exact(dev, 1);
+ if (IS_ERR(opp)) {
+ dev_err(dev,
+ "Invalid configuration found of l2 opp. Can't find opp-level 1");
+ goto invalid_conf;
+ }
+ dev_pm_opp_put(opp);
+
+ /*
+ * Check if we have at least opp-level 1 in the cpu opp, 0 should always
+ * be set to the idle freq
+ */
+ opp = dev_pm_opp_find_level_exact(cpu_dev, 1);
+ if (IS_ERR(opp)) {
+ dev_err(dev,
+ "Invalid configuration found of cpu opp. Can't find opp-level 1");
+ goto invalid_conf;
+ }
+ dev_pm_opp_put(opp);
+
+ platform_set_drvdata(pdev, data);
+
+ /* The l2 scaling is enabled by linking the cpufreq driver */
+ l2_pdev = pdev;
+
+ return 0;
+
+invalid_conf:
+ dev_pm_opp_remove_table(dev);
+ dev_pm_opp_put_regulators(table);
+ dev_pm_opp_unregister_set_opp_helper(table);
+
+ return -EINVAL;
+};
+
+static int krait_cache_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct opp_table *table = dev_pm_opp_get_opp_table(dev);
+
+ dev_pm_opp_remove_table(dev);
+ dev_pm_opp_put_regulators(table);
+ dev_pm_opp_unregister_set_opp_helper(table);
+
+ return 0;
+};
+
+static const struct of_device_id krait_cache_match_table[] = {
+ { .compatible = "qcom,krait-cache" },
+ {}
+};
+
+static struct platform_driver krait_cache_driver = {
+ .driver = {
+ .name = "krait-cache",
+ .of_match_table = krait_cache_match_table,
+ },
+ .probe = krait_cache_probe,
+ .remove = krait_cache_remove,
+};
+module_platform_driver(krait_cache_driver);
+
+static int krait_cpufreq_probe(struct platform_device *pdev)
+{
+ struct cpufreq_dt_platform_data *data = dev_get_platdata(&pdev->dev);
+ int ret;
+
+ /*
+ * All per-cluster (CPUs sharing clock/voltages) initialization is done
+ * from ->init(). In probe(), we just need to make sure that clk and
+ * regulators are available. Else defer probe and retry.
+ *
+ * FIXME: Is checking this only for CPU0 sufficient ?
+ */
+ ret = resources_available();
+ if (ret)
+ return ret;
+
+ if (data) {
+ if (data->have_governor_per_policy)
+ krait_cpufreq_driver.flags |=
+ CPUFREQ_HAVE_GOVERNOR_PER_POLICY;
+
+ krait_cpufreq_driver.resume = data->resume;
+ if (data->suspend)
+ krait_cpufreq_driver.suspend = data->suspend;
+ }
+
+ ret = cpufreq_register_driver(&krait_cpufreq_driver);
+ if (ret)
+ dev_err(&pdev->dev, "failed register driver: %d\n", ret);
+
+ return ret;
+}
+
+static int krait_cpufreq_remove(struct platform_device *pdev)
+{
+ cpufreq_unregister_driver(&krait_cpufreq_driver);
+ return 0;
+}
+
+static struct platform_driver krait_cpufreq_platdrv = {
+ .driver = {
+ .name = "krait-cpufreq",
+ },
+ .probe = krait_cpufreq_probe,
+ .remove = krait_cpufreq_remove,
+};
+module_platform_driver(krait_cpufreq_platdrv);
+
+MODULE_ALIAS("platform:krait-cpufreq");
+MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Dedicated Krait SoC cpufreq driver");
+MODULE_LICENSE("GPL");

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