Merge Official Source

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2023-01-05 19:27:32 +08:00
commit 9ff6e7ff49
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
27 changed files with 957 additions and 67 deletions

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@ -129,6 +129,17 @@ mtd_get_mac_encrypted_deco() {
echo $macaddr
}
mtd_get_mac_uci_config_ubi() {
local volumename="$1"
. /lib/upgrade/nand.sh
local ubidev=$(nand_attach_ubi $CI_UBIPART)
local part=$(nand_find_volume $ubidev $volumename)
cat "/dev/$part" | sed -n 's/^\s*option macaddr\s*'"'"'\?\([0-9A-F:]\+\)'"'"'\?/\1/Ip'
}
mtd_get_mac_text() {
local mtdname=$1
local offset=$(($2))

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@ -9,12 +9,12 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=ncurses
PKG_CPE_ID:=cpe:/a:gnu:ncurses
PKG_VERSION:=6.3
PKG_RELEASE:=$(AUTORELEASE)
PKG_VERSION:=6.4
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=@GNU/$(PKG_NAME)
PKG_HASH:=97fc51ac2b085d4cde31ef4d2c3122c21abc217e9090a43a30fc5ec21684e059
PKG_HASH:=6931283d9ac87c5073f30b6290c4c75f21632bb4fc3603ac8100812bed248159
PKG_LICENSE:=MIT
PKG_LICENSE_FILES:=README

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@ -1,6 +1,6 @@
--- a/misc/terminfo.src
+++ b/misc/terminfo.src
@@ -6616,6 +6616,172 @@ rxvt-cygwin-native|rxvt terminal emulato
@@ -6886,6 +6886,172 @@ rxvt-cygwin-native|rxvt terminal emulato
rxvt-16color|rxvt with 16 colors like aixterm,
ncv#32, use=ibm+16color, use=rxvt,

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@ -1,14 +1,14 @@
--- a/misc/terminfo.src
+++ b/misc/terminfo.src
@@ -4815,6 +4815,7 @@ xterm+nofkeys|building block for xterm f
# This version reflects the current xterm features.
xterm-new|modern xterm terminal emulator,
@@ -4984,6 +4984,7 @@ xterm-xfree86|xterm terminal emulator (X
xterm+nofkeys|building block for xterm fkey-variants,
npc,
+ kbs=\177,
kcbt=\E[Z, kent=\EOM, nel=\EE, use=ecma+index,
use=ansi+rep, use=ecma+strikeout, use=xterm+pcfkeys,
use=xterm+nofkeys,
@@ -6416,6 +6417,7 @@ mlterm-256color|mlterm 3.0 with xterm 25
use=ansi+rep, use=ecma+strikeout, use=vt420+lrmm,
use=xterm+sm+1006, use=xterm+tmux, use=ecma+italics,
@@ -6689,6 +6690,7 @@ mlterm-256color|mlterm 3.0 with xterm 25
rxvt-basic|rxvt terminal base (X Window System),
OTbs, am, bce, eo, mir, msgr, xenl, xon, XT,
cols#80, it#8, lines#24,
@ -16,24 +16,24 @@
acsc=``aaffggjjkkllmmnnooppqqrrssttuuvvwwxxyyzz{{||}}~~,
bel=^G, blink=\E[5m, bold=\E[1m, clear=\E[H\E[2J, cr=\r,
csr=\E[%i%p1%d;%p2%dr, cub=\E[%p1%dD, cub1=^H,
@@ -6425,7 +6427,7 @@ rxvt-basic|rxvt terminal base (X Window
@@ -6698,7 +6700,7 @@ rxvt-basic|rxvt terminal base (X Window
enacs=\E(B\E)0, flash=\E[?5h$<100/>\E[?5l, home=\E[H,
ht=^I, hts=\EH, ich=\E[%p1%d@, il=\E[%p1%dL, il1=\E[L,
ind=\n, is1=\E[?47l\E=\E[?1l,
- is2=\E[r\E[m\E[2J\E[H\E[?7h\E[?1;3;4;6l\E[4l, kbs=^H,
+ is2=\E[r\E[m\E[2J\E[H\E[?7h\E[?1;3;4;6l\E[4l,
kcbt=\E[Z, kmous=\E[M, rc=\E8, rev=\E[7m, ri=\EM, rmacs=^O,
rmcup=\E[2J\E[?47l\E8, rmir=\E[4l, rmkx=\E>, rmso=\E[27m,
rmul=\E[24m,
@@ -8060,6 +8062,7 @@ dumb-emacs-ansi|Emacs dumb terminal with
screen|VT 100/ANSI X3.64 virtual terminal,
rmir=\E[4l, rmkx=\E>, rmso=\E[27m, rmul=\E[24m,
rs1=\E>\E[1;3;4;5;6l\E[?7h\E[m\E[r\E[2J\E[H,
@@ -8347,6 +8349,7 @@ dumb-emacs-ansi|Emacs dumb terminal with
screen-base|VT 100/ANSI X3.64 virtual terminal (base),
OTbs, OTpt, am, km, mir, msgr, xenl, G0,
colors#8, cols#80, it#8, lines#24, ncv@, pairs#64, U8#1,
+ kbs=\177,
acsc=++\,\,--..00``aaffgghhiijjkkllmmnnooppqqrrssttuuvvwwxxy
yzz{{||}}~~,
bel=^G, blink=\E[5m, bold=\E[1m, cbt=\E[Z, civis=\E[?25l,
@@ -8071,7 +8074,7 @@ screen|VT 100/ANSI X3.64 virtual termina
@@ -8358,7 +8361,7 @@ screen-base|VT 100/ANSI X3.64 virtual te
dl=\E[%p1%dM, dl1=\E[M, ed=\E[J, el=\E[K, el1=\E[1K,
enacs=\E(B\E)0, flash=\Eg, home=\E[H, hpa=\E[%i%p1%dG,
ht=^I, hts=\EH, ich=\E[%p1%d@, il=\E[%p1%dL, il1=\E[L,
@ -42,7 +42,7 @@
kcub1=\EOD, kcud1=\EOB, kcuf1=\EOC, kcuu1=\EOA, kf1=\EOP,
kf10=\E[21~, kf11=\E[23~, kf12=\E[24~, kf2=\EOQ, kf3=\EOR,
kf4=\EOS, kf5=\E[15~, kf6=\E[17~, kf7=\E[18~, kf8=\E[19~,
@@ -8199,6 +8202,7 @@ screen.xterm-r6|screen customized for X1
@@ -8500,6 +8503,7 @@ screen.xterm-r6|screen customized for X1
# on Solaris because Sun's curses implementation gets confused.
screen.teraterm|disable ncv in teraterm,
ncv#127,

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@ -15,7 +15,7 @@ Subject: [PATCH] ncurses 5.9 - patch 20141206
--- a/ncurses/base/MKlib_gen.sh
+++ b/ncurses/base/MKlib_gen.sh
@@ -511,11 +511,22 @@ sed -n -f $ED1 \
@@ -512,11 +512,22 @@ sed -n -f $ED1 \
-e 's/gen_$//' \
-e 's/ / /g' >>$TMP

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@ -1,6 +1,6 @@
--- a/aclocal.m4
+++ b/aclocal.m4
@@ -505,7 +505,7 @@ AC_CACHE_CHECK(for options to update arc
@@ -523,7 +523,7 @@ AC_CACHE_CHECK(for options to update arc
;;
(*)
cf_cv_ar_flags=unknown
@ -11,7 +11,7 @@
# check if $ARFLAGS already contains this choice
--- a/configure
+++ b/configure
@@ -5072,7 +5072,7 @@ else
@@ -5110,7 +5110,7 @@ else
;;
(*)
cf_cv_ar_flags=unknown

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@ -1,6 +1,6 @@
--- a/misc/terminfo.src
+++ b/misc/terminfo.src
@@ -6240,12 +6240,11 @@ konsole-xf3x|KDE console window with key
@@ -6514,12 +6514,11 @@ konsole-xf3x|KDE console window with key
# The value for kbs (see konsole-vt100) reflects local customization rather
# than the settings used for XFree86 xterm.
konsole-xf4x|KDE console window with keyboard for XFree86 4.x xterm,

View File

@ -107,10 +107,34 @@
read-only;
};
art: partition@7f0000 {
partition@7f0000 {
label = "art";
reg = <0x7f0000 0x010000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_120c: macaddr@120c {
reg = <0x120c 0x6>;
};
macaddr_art_520c: macaddr@520c {
reg = <0x520c 0x6>;
};
calibration_art_1000: calibration@1000 {
reg = <0x1000 0xeb8>;
};
calibration_art_5000: calibration@5000 {
reg = <0x5000 0xeb8>;
};
};
};
};
@ -122,9 +146,8 @@
ath9k0: wifi@0,11 {
compatible = "pci168c,0029";
reg = <0x8800 0 0 0 0>;
qca,no-eeprom;
nvmem-cells = <&macaddr_art_120c>;
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_art_120c>, <&calibration_art_1000>;
nvmem-cell-names = "mac-address", "calibration";
#gpio-cells = <2>;
gpio-controller;
};
@ -132,30 +155,10 @@
ath9k1: wifi@0,12 {
compatible = "pci168c,0029";
reg = <0x9000 0 0 0 0>;
qca,no-eeprom;
nvmem-cells = <&macaddr_art_520c>;
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_art_520c>, <&calibration_art_5000>;
nvmem-cell-names = "mac-address", "calibration";
mac-address-increment = <1>;
#gpio-cells = <2>;
gpio-controller;
};
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_120c: macaddr@120c {
reg = <0x120c 0x6>;
};
macaddr_art_520c: macaddr@520c {
reg = <0x520c 0x6>;
};
};

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@ -124,8 +124,7 @@ case "$FIRMWARE" in
"ath9k-eeprom-pci-0000:00:11.0.bin")
case $board in
buffalo,wzr-600dhp|\
buffalo,wzr-hp-ag300h|\
netgear,wndap360)
buffalo,wzr-hp-ag300h)
caldata_extract "art" 0x1000 0xeb8
;;
dlink,dir-825-b1|\
@ -144,8 +143,7 @@ case "$FIRMWARE" in
"ath9k-eeprom-pci-0000:00:12.0.bin")
case $board in
buffalo,wzr-600dhp|\
buffalo,wzr-hp-ag300h|\
netgear,wndap360)
buffalo,wzr-hp-ag300h)
caldata_extract "art" 0x5000 0xeb8
;;
dlink,dir-825-b1|\

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@ -1765,7 +1765,7 @@ define Device/netgear_wndap360
$(Device/netgear_generic)
SOC := ar7161
DEVICE_MODEL := WNDAP360
DEVICE_PACKAGES := kmod-leds-reset kmod-owl-loader
DEVICE_PACKAGES := kmod-leds-reset
IMAGE_SIZE := 7744k
BLOCKSIZE := 256k
KERNEL := kernel-bin | append-dtb | gzip | uImage gzip

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@ -0,0 +1,102 @@
From 9807ae69746196ee4bbffe7d22d22ab2b61c6ed0 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 29 Dec 2022 17:33:32 +0100
Subject: [PATCH 1/5] net: dsa: qca8k: fix wrong length value for mgmt eth
packet
The assumption that Documentation was right about how this value work was
wrong. It was discovered that the length value of the mgmt header is in
step of word size.
As an example to process 4 byte of data the correct length to set is 2.
To process 8 byte 4, 12 byte 6, 16 byte 8...
Odd values will always return the next size on the ack packet.
(length of 3 (6 byte) will always return 8 bytes of data)
This means that a value of 15 (0xf) actually means reading/writing 32 bytes
of data instead of 16 bytes. This behaviour is totally absent and not
documented in the switch Documentation.
In fact from Documentation the max value that mgmt eth can process is
16 byte of data while in reality it can process 32 bytes at once.
To handle this we always round up the length after deviding it for word
size. We check if the result is odd and we round another time to align
to what the switch will provide in the ack packet.
The workaround for the length limit of 15 is still needed as the length
reg max value is 0xf(15)
Reported-by: Ronald Wahl <ronald.wahl@raritan.com>
Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
Fixes: 90386223f44e ("net: dsa: qca8k: add support for larger read/write size with mgmt Ethernet")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v5.18+
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca/qca8k-8xxx.c | 45 +++++++++++++++++++++++++-------
1 file changed, 35 insertions(+), 10 deletions(-)
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -146,7 +146,16 @@ static void qca8k_rw_reg_ack_handler(str
command = get_unaligned_le32(&mgmt_ethhdr->command);
cmd = FIELD_GET(QCA_HDR_MGMT_CMD, command);
+
len = FIELD_GET(QCA_HDR_MGMT_LENGTH, command);
+ /* Special case for len of 15 as this is the max value for len and needs to
+ * be increased before converting it from word to dword.
+ */
+ if (len == 15)
+ len++;
+
+ /* We can ignore odd value, we always round up them in the alloc function. */
+ len *= sizeof(u16);
/* Make sure the seq match the requested packet */
if (get_unaligned_le32(&mgmt_ethhdr->seq) == mgmt_eth_data->seq)
@@ -193,17 +202,33 @@ static struct sk_buff *qca8k_alloc_mdio_
if (!skb)
return NULL;
- /* Max value for len reg is 15 (0xf) but the switch actually return 16 byte
- * Actually for some reason the steps are:
- * 0: nothing
- * 1-4: first 4 byte
- * 5-6: first 12 byte
- * 7-15: all 16 byte
+ /* Hdr mgmt length value is in step of word size.
+ * As an example to process 4 byte of data the correct length to set is 2.
+ * To process 8 byte 4, 12 byte 6, 16 byte 8...
+ *
+ * Odd values will always return the next size on the ack packet.
+ * (length of 3 (6 byte) will always return 8 bytes of data)
+ *
+ * This means that a value of 15 (0xf) actually means reading/writing 32 bytes
+ * of data.
+ *
+ * To correctly calculate the length we devide the requested len by word and
+ * round up.
+ * On the ack function we can skip the odd check as we already handle the
+ * case here.
*/
- if (len == 16)
- real_len = 15;
- else
- real_len = len;
+ real_len = DIV_ROUND_UP(len, sizeof(u16));
+
+ /* We check if the result len is odd and we round up another time to
+ * the next size. (length of 3 will be increased to 4 as switch will always
+ * return 8 bytes)
+ */
+ if (real_len % sizeof(u16) != 0)
+ real_len++;
+
+ /* Max reg value is 0xf(15) but switch will always return the next size (32 byte) */
+ if (real_len == 16)
+ real_len--;
skb_reset_mac_header(skb);
skb_set_network_header(skb, skb->len);

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@ -0,0 +1,34 @@
From d9dba91be71f03cc75bcf39fc0d5d99ff33f1ae0 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 29 Dec 2022 17:33:33 +0100
Subject: [PATCH 2/5] net: dsa: tag_qca: fix wrong MGMT_DATA2 size
It was discovered that MGMT_DATA2 can contain up to 28 bytes of data
instead of the 12 bytes written in the Documentation by accounting the
limit of 16 bytes declared in Documentation subtracting the first 4 byte
in the packet header.
Update the define with the real world value.
Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
Fixes: c2ee8181fddb ("net: dsa: tag_qca: add define for handling mgmt Ethernet packet")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v5.18+
Signed-off-by: David S. Miller <davem@davemloft.net>
---
include/linux/dsa/tag_qca.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/include/linux/dsa/tag_qca.h
+++ b/include/linux/dsa/tag_qca.h
@@ -40,8 +40,8 @@
QCA_HDR_MGMT_COMMAND_LEN + \
QCA_HDR_MGMT_DATA1_LEN)
-#define QCA_HDR_MGMT_DATA2_LEN 12 /* Other 12 byte for the mdio data */
-#define QCA_HDR_MGMT_PADDING_LEN 34 /* Padding to reach the min Ethernet packet */
+#define QCA_HDR_MGMT_DATA2_LEN 28 /* Other 28 byte for the mdio data */
+#define QCA_HDR_MGMT_PADDING_LEN 18 /* Padding to reach the min Ethernet packet */
#define QCA_HDR_MGMT_PKT_LEN (QCA_HDR_MGMT_HEADER_LEN + \
QCA_HDR_LEN + \

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@ -0,0 +1,172 @@
From 03cb9e6d0b32b768e3d9d473c5c4ca1100877664 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 29 Dec 2022 17:33:34 +0100
Subject: [PATCH 3/5] Revert "net: dsa: qca8k: cache lo and hi for mdio write"
This reverts commit 2481d206fae7884cd07014fd1318e63af35e99eb.
The Documentation is very confusing about the topic.
The cache logic for hi and lo is wrong and actually miss some regs to be
actually written.
What the Documentation actually intended was that it's possible to skip
writing hi OR lo if half of the reg is not needed to be written or read.
Revert the change in favor of a better and correct implementation.
Reported-by: Ronald Wahl <ronald.wahl@raritan.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v5.18+
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca/qca8k-8xxx.c | 61 +++++++-------------------------
drivers/net/dsa/qca/qca8k.h | 5 ---
2 files changed, 12 insertions(+), 54 deletions(-)
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -37,44 +37,6 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u
}
static int
-qca8k_set_lo(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 lo)
-{
- u16 *cached_lo = &priv->mdio_cache.lo;
- struct mii_bus *bus = priv->bus;
- int ret;
-
- if (lo == *cached_lo)
- return 0;
-
- ret = bus->write(bus, phy_id, regnum, lo);
- if (ret < 0)
- dev_err_ratelimited(&bus->dev,
- "failed to write qca8k 32bit lo register\n");
-
- *cached_lo = lo;
- return 0;
-}
-
-static int
-qca8k_set_hi(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 hi)
-{
- u16 *cached_hi = &priv->mdio_cache.hi;
- struct mii_bus *bus = priv->bus;
- int ret;
-
- if (hi == *cached_hi)
- return 0;
-
- ret = bus->write(bus, phy_id, regnum, hi);
- if (ret < 0)
- dev_err_ratelimited(&bus->dev,
- "failed to write qca8k 32bit hi register\n");
-
- *cached_hi = hi;
- return 0;
-}
-
-static int
qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
{
int ret;
@@ -97,7 +59,7 @@ qca8k_mii_read32(struct mii_bus *bus, in
}
static void
-qca8k_mii_write32(struct qca8k_priv *priv, int phy_id, u32 regnum, u32 val)
+qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
{
u16 lo, hi;
int ret;
@@ -105,9 +67,12 @@ qca8k_mii_write32(struct qca8k_priv *pri
lo = val & 0xffff;
hi = (u16)(val >> 16);
- ret = qca8k_set_lo(priv, phy_id, regnum, lo);
+ ret = bus->write(bus, phy_id, regnum, lo);
if (ret >= 0)
- ret = qca8k_set_hi(priv, phy_id, regnum + 1, hi);
+ ret = bus->write(bus, phy_id, regnum + 1, hi);
+ if (ret < 0)
+ dev_err_ratelimited(&bus->dev,
+ "failed to write qca8k 32bit register\n");
}
static int
@@ -442,7 +407,7 @@ qca8k_regmap_write(void *ctx, uint32_t r
if (ret < 0)
goto exit;
- qca8k_mii_write32(priv, 0x10 | r2, r1, val);
+ qca8k_mii_write32(bus, 0x10 | r2, r1, val);
exit:
mutex_unlock(&bus->mdio_lock);
@@ -475,7 +440,7 @@ qca8k_regmap_update_bits(void *ctx, uint
val &= ~mask;
val |= write_val;
- qca8k_mii_write32(priv, 0x10 | r2, r1, val);
+ qca8k_mii_write32(bus, 0x10 | r2, r1, val);
exit:
mutex_unlock(&bus->mdio_lock);
@@ -750,14 +715,14 @@ qca8k_mdio_write(struct qca8k_priv *priv
if (ret)
goto exit;
- qca8k_mii_write32(priv, 0x10 | r2, r1, val);
+ qca8k_mii_write32(bus, 0x10 | r2, r1, val);
ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
QCA8K_MDIO_MASTER_BUSY);
exit:
/* even if the busy_wait timeouts try to clear the MASTER_EN */
- qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
+ qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
mutex_unlock(&bus->mdio_lock);
@@ -787,7 +752,7 @@ qca8k_mdio_read(struct qca8k_priv *priv,
if (ret)
goto exit;
- qca8k_mii_write32(priv, 0x10 | r2, r1, val);
+ qca8k_mii_write32(bus, 0x10 | r2, r1, val);
ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
QCA8K_MDIO_MASTER_BUSY);
@@ -798,7 +763,7 @@ qca8k_mdio_read(struct qca8k_priv *priv,
exit:
/* even if the busy_wait timeouts try to clear the MASTER_EN */
- qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
+ qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
mutex_unlock(&bus->mdio_lock);
@@ -1914,8 +1879,6 @@ qca8k_sw_probe(struct mdio_device *mdiod
}
priv->mdio_cache.page = 0xffff;
- priv->mdio_cache.lo = 0xffff;
- priv->mdio_cache.hi = 0xffff;
/* Check the detected switch id */
ret = qca8k_read_switch_id(priv);
--- a/drivers/net/dsa/qca/qca8k.h
+++ b/drivers/net/dsa/qca/qca8k.h
@@ -375,11 +375,6 @@ struct qca8k_mdio_cache {
* mdio writes
*/
u16 page;
-/* lo and hi can also be cached and from Documentation we can skip one
- * extra mdio write if lo or hi is didn't change.
- */
- u16 lo;
- u16 hi;
};
struct qca8k_priv {

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@ -0,0 +1,150 @@
From cfbd6de588ef659c198083205dc954a6d3ed2aec Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 29 Dec 2022 17:33:35 +0100
Subject: [PATCH 4/5] net: dsa: qca8k: introduce single mii read/write lo/hi
It may be useful to read/write just the lo or hi half of a reg.
This is especially useful for phy poll with the use of mdio master.
The mdio master reg is composed by the first 16 bit related to setup and
the other half with the returned data or data to write.
Refactor the mii function to permit single mii read/write of lo or hi
half of the reg.
Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca/qca8k-8xxx.c | 106 ++++++++++++++++++++++++-------
1 file changed, 84 insertions(+), 22 deletions(-)
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -37,42 +37,104 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u
}
static int
-qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
+qca8k_mii_write_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
{
int ret;
+ u16 lo;
- ret = bus->read(bus, phy_id, regnum);
- if (ret >= 0) {
- *val = ret;
- ret = bus->read(bus, phy_id, regnum + 1);
- *val |= ret << 16;
- }
+ lo = val & 0xffff;
+ ret = bus->write(bus, phy_id, regnum, lo);
+ if (ret < 0)
+ dev_err_ratelimited(&bus->dev,
+ "failed to write qca8k 32bit lo register\n");
+
+ return ret;
+}
- if (ret < 0) {
+static int
+qca8k_mii_write_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
+{
+ int ret;
+ u16 hi;
+
+ hi = (u16)(val >> 16);
+ ret = bus->write(bus, phy_id, regnum, hi);
+ if (ret < 0)
dev_err_ratelimited(&bus->dev,
- "failed to read qca8k 32bit register\n");
- *val = 0;
- return ret;
- }
+ "failed to write qca8k 32bit hi register\n");
+ return ret;
+}
+
+static int
+qca8k_mii_read_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
+{
+ int ret;
+
+ ret = bus->read(bus, phy_id, regnum);
+ if (ret < 0)
+ goto err;
+
+ *val = ret & 0xffff;
return 0;
+
+err:
+ dev_err_ratelimited(&bus->dev,
+ "failed to read qca8k 32bit lo register\n");
+ *val = 0;
+
+ return ret;
}
-static void
-qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
+static int
+qca8k_mii_read_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
{
- u16 lo, hi;
int ret;
- lo = val & 0xffff;
- hi = (u16)(val >> 16);
+ ret = bus->read(bus, phy_id, regnum);
+ if (ret < 0)
+ goto err;
- ret = bus->write(bus, phy_id, regnum, lo);
- if (ret >= 0)
- ret = bus->write(bus, phy_id, regnum + 1, hi);
+ *val = ret << 16;
+ return 0;
+
+err:
+ dev_err_ratelimited(&bus->dev,
+ "failed to read qca8k 32bit hi register\n");
+ *val = 0;
+
+ return ret;
+}
+
+static int
+qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
+{
+ u32 hi, lo;
+ int ret;
+
+ *val = 0;
+
+ ret = qca8k_mii_read_lo(bus, phy_id, regnum, &lo);
if (ret < 0)
- dev_err_ratelimited(&bus->dev,
- "failed to write qca8k 32bit register\n");
+ goto err;
+
+ ret = qca8k_mii_read_hi(bus, phy_id, regnum + 1, &hi);
+ if (ret < 0)
+ goto err;
+
+ *val = lo | hi;
+
+err:
+ return ret;
+}
+
+static void
+qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
+{
+ if (qca8k_mii_write_lo(bus, phy_id, regnum, val) < 0)
+ return;
+
+ qca8k_mii_write_hi(bus, phy_id, regnum + 1, val);
}
static int

View File

@ -0,0 +1,73 @@
From a4165830ca237f2b3318faf62562bce8ce12a389 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 29 Dec 2022 17:33:36 +0100
Subject: [PATCH 5/5] net: dsa: qca8k: improve mdio master read/write by using
single lo/hi
Improve mdio master read/write by using singe mii read/write lo/hi.
In a read and write we need to poll the mdio master regs in a busy loop
to check for a specific bit present in the upper half of the reg. We can
ignore the other half since it won't contain useful data. This will save
an additional useless read for each read and write operation.
In a read operation the returned data is present in the mdio master reg
lower half. We can ignore the other half since it won't contain useful
data. This will save an additional useless read for each read operation.
In a read operation it's needed to just set the hi half of the mdio
master reg as the lo half will be replaced by the result. This will save
an additional useless write for each read operation.
Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/qca/qca8k-8xxx.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -740,9 +740,9 @@ qca8k_mdio_busy_wait(struct mii_bus *bus
qca8k_split_addr(reg, &r1, &r2, &page);
- ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,
+ ret = read_poll_timeout(qca8k_mii_read_hi, ret1, !(val & mask), 0,
QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
- bus, 0x10 | r2, r1, &val);
+ bus, 0x10 | r2, r1 + 1, &val);
/* Check if qca8k_read has failed for a different reason
* before returnting -ETIMEDOUT
@@ -784,7 +784,7 @@ qca8k_mdio_write(struct qca8k_priv *priv
exit:
/* even if the busy_wait timeouts try to clear the MASTER_EN */
- qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
+ qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
mutex_unlock(&bus->mdio_lock);
@@ -814,18 +814,18 @@ qca8k_mdio_read(struct qca8k_priv *priv,
if (ret)
goto exit;
- qca8k_mii_write32(bus, 0x10 | r2, r1, val);
+ qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, val);
ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
QCA8K_MDIO_MASTER_BUSY);
if (ret)
goto exit;
- ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
+ ret = qca8k_mii_read_lo(bus, 0x10 | r2, r1, &val);
exit:
/* even if the busy_wait timeouts try to clear the MASTER_EN */
- qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
+ qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
mutex_unlock(&bus->mdio_lock);

View File

@ -359,6 +359,10 @@
macaddr_mfginfo_1d: macaddr@1d {
reg = <0x1d 0x6>;
};
macaddr_mfginfo_45: macaddr@45 {
reg = <0x45 0x6>;
};
};
partition@3a0000 {
@ -454,17 +458,15 @@
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Aruba-AP-303";
nvmem-cell-names = "pre-calibration", "mac-address";
nvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_1d>;
nvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_45>;
qcom,ath10k-calibration-variant = "Aruba-AP-303";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Aruba-AP-303";
nvmem-cell-names = "pre-calibration", "mac-address";
nvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_1d>;
nvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_45>;
mac-address-increment = <1>;
qcom,ath10k-calibration-variant = "Aruba-AP-303";
};

View File

@ -28,7 +28,10 @@ arcadyan,arv7519rw22)
ucidef_set_led_netdev "lan" "lan" "green:lan" "eth0.1"
;;
arcadyan,vgv7510kw22-nor|\
arcadyan,vgv7510kw22-brn|\
arcadyan,vgv7510kw22-brn)
ucidef_set_led_netdev "internet" "internet" "$led_internet" "wan"
ucidef_set_led_wlan "wifi" "wifi" "green:wlan" "phy0radio"
;;
zyxel,p-2812hnu-f1|\
zyxel,p-2812hnu-f3)
ucidef_set_led_wlan "wifi" "wifi" "green:wlan" "phy0radio"

View File

@ -90,18 +90,30 @@
};
&pcie0 {
mt76@0,0 {
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x8000>;
ieee80211-freq-limit = <5000000 6000000>;
led {
led-sources = <2>;
led-active-low;
};
};
};
&pcie1 {
mt76@0,0 {
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x0000>;
ieee80211-freq-limit = <2400000 2500000>;
led {
led-sources = <0>;
led-active-low;
};
};
};

View File

@ -26,11 +26,21 @@
leds {
compatible = "gpio-leds";
led_power: led-0 {
led_power: power {
label = "blue:power";
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_POWER;
function = LED_FUNCTION_POWER;
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
};
led_usb {
label = "blue:usb";
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_USB;
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
trigger-sources = <&ehci_port2>;
linux,default-trigger = "usbport";
};
};
keys {

View File

@ -0,0 +1,180 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "mt7621.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "TP-Link ER605 v2";
compatible = "tplink,er605-v2", "mediatek,mt7621-soc";
chosen {
bootargs = "console=ttyS0,115200 noinitrd";
};
aliases {
led-boot = &led_system;
led-failsafe = &led_system;
led-running = &led_system;
led-upgrade = &led_system;
label-mac-device = &gmac0;
};
leds {
compatible = "gpio-leds";
led_usb: usb {
label = "green:usb";
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
};
led_power: power {
label = "green:power";
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led_system: system {
label = "green:system";
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset button";
gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_RESTART>;
};
};
reg_usb_vbus: regulator-usb {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&gmac0 {
label = "dsa";
};
&gmac1 {
status = "okay";
label = "eth0";
phy-handle = <&ethphy0>;
};
&switch0 {
ports {
port@0 {
status = "disabled";
};
port@1 {
status = "okay";
label = "eth1";
};
port@2 {
status = "okay";
label = "eth2";
};
port@3 {
status = "okay";
label = "eth3";
};
port@4 {
status = "okay";
label = "eth4";
};
};
};
&nand {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "u-boot-env";
reg = <0x80000 0x80000>;
read-only;
};
factory: partition@100000 {
label = "factory";
reg = <0x100000 0x40000>;
read-only;
};
partition@140000 {
label = "firmware";
reg = <0x140000 0x7cc0000>;
};
partition@7e00000 {
label = "panic-ops";
reg = <0x7e00000 0x200000>;
};
};
};
&mdio {
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
&state_default {
gpio {
groups = "uart2", "uart3", "pcie", "jtag";
function = "gpio";
};
};
&spi0 {
status = "disabled";
};
&xhci {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_usb_vbus>;
};

View File

@ -0,0 +1,78 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright(c) 2017 Kristian Evensen <kristian.evensen@gmail.com>.
* Copyright(c) 2017 Piotr Dymacz <pepe2k@gmail.com>.
* Copyright(c) 2018 Nishant Sharma <codemarauder@gmail.com>.
* All rights reserved.
*/
#include "mt7621_unielec_u7621-06.dtsi"
/ {
compatible = "unielec,u7621-06-32m", "unielec,u7621-06", "mediatek,mt7621-soc";
model = "UniElec U7621-06 (32M flash)";
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "config";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
firmware: partition@50000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x50000 0x1fb0000>;
};
};
};
};
&gmac0 {
nvmem-cells = <&macaddr_factory_e000>;
nvmem-cell-names = "mac-address";
};
&gmac1 {
nvmem-cells = <&macaddr_factory_e006>;
nvmem-cell-names = "mac-address";
};
&factory {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_e000: macaddr@e000 {
reg = <0xe000 0x6>;
};
macaddr_factory_e006: macaddr@e006 {
reg = <0xe006 0x6>;
};
};

View File

@ -122,18 +122,30 @@
};
&pcie0 {
wifi0: mt76@0,0 {
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x8000>;
ieee80211-freq-limit = <5000000 6000000>;
led {
led-sources = <2>;
led-active-low;
};
};
};
&pcie1 {
wifi1: mt76@0,0 {
wifi1: wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x0000>;
ieee80211-freq-limit = <2400000 2500000>;
led {
led-sources = <0>;
led-active-low;
};
};
};

View File

@ -307,7 +307,8 @@ define Device/asus_rt-ax53u
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \
check-size
DEVICE_PACKAGES := kmod-mt7915e kmod-usb3 uboot-envtools
DEVICE_PACKAGES := kmod-mt7915e kmod-usb3 uboot-envtools \
kmod-usb-ledtrig-usbport
endef
TARGET_DEVICES += asus_rt-ax53u
@ -1961,6 +1962,24 @@ define Device/tplink_eap615-wall-v1
endef
TARGET_DEVICES += tplink_eap615-wall-v1
define Device/tplink_er605-v2
$(Device/dsa-migration)
DEVICE_VENDOR := TP-Link
DEVICE_MODEL := ER605
DEVICE_VARIANT := v2
DEVICE_PACKAGES := -wpad-basic-wolfssl kmod-usb3
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_SIZE := 4096k
KERNEL_IN_UBI := 1
KERNEL_LOADADDR := 0x82000000
KERNEL := kernel-bin | relocate-kernel 0x80001000 | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
IMAGES += sysupgrade.tar
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
IMAGE_SIZE := 127744k
endef
TARGET_DEVICES += tplink_er605-v2
define Device/tplink_mr600-v2-eu
$(Device/dsa-migration)
$(Device/tplink-v2)
@ -2129,6 +2148,18 @@ define Device/unielec_u7621-06-16m
endef
TARGET_DEVICES += unielec_u7621-06-16m
define Device/unielec_u7621-06-32m
$(Device/dsa-migration)
$(Device/uimage-lzma-loader)
IMAGE_SIZE := 32448k
DEVICE_VENDOR := UniElec
DEVICE_MODEL := U7621-06
DEVICE_VARIANT := 32M
DEVICE_PACKAGES := kmod-ata-ahci kmod-sdhci-mt7620 kmod-usb3 -wpad-basic-wolfssl
SUPPORTED_DEVICES += unielec,u7621-06-32m
endef
TARGET_DEVICES += unielec_u7621-06-32m
define Device/unielec_u7621-06-64m
$(Device/dsa-migration)
$(Device/uimage-lzma-loader)

View File

@ -19,6 +19,11 @@ asus,rp-ac87)
ucidef_set_led_rssi "rssimed-wlan1" "RSSIMED" "green:rssimed-wlan1" "wlan1" "40" "100"
ucidef_set_led_rssi "rssihigh-wlan1" "RSSIHIGH" "green:rssihigh-wlan1" "wlan1" "70" "100"
;;
asus,rt-ax53u)
ucidef_set_led_usbport "usb" "USB" "blue:usb" "usb1-port2"
ucidef_set_led_wlan "wlan2g" "WiFi 2.4GHz" "mt76-phy0" "phy0tpt"
ucidef_set_led_wlan "wlan5g" "WiFi 5GHz" "mt76-phy1" "phy1tpt"
;;
asus,rt-n56u-b1)
ucidef_set_led_netdev "lan" "LAN link" "blue:lan" "br-lan"
ucidef_set_led_netdev "wan" "WAN link" "blue:wan" "wan"

View File

@ -99,6 +99,9 @@ ramips_setup_interfaces()
tplink,eap615-wall-v1)
ucidef_set_interface_lan "lan0 lan1 lan2 lan3"
;;
tplink,er605-v2)
ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4" "eth0"
;;
tplink,tl-wpa8631p-v3)
ucidef_set_interface_lan "lan1 lan2 lan3 plc0"
;;
@ -225,6 +228,12 @@ ramips_setup_macs()
label_mac=$(cat "/sys/firmware/mikrotik/hard_config/mac_base")
lan_mac=$label_mac
;;
tplink,er605-v2)
CI_UBIPART="firmware"
label_mac=$(mtd_get_mac_uci_config_ubi "tddp")
lan_mac=$label_mac
wan_mac=$(macaddr_add "$label_mac" 1)
;;
tplink,mr600-v2-eu)
label_mac=$(cat "/sys/class/net/eth0/address")
wwan_mac=$(macaddr_add $label_mac 1)

View File

@ -124,6 +124,12 @@ platform_do_upgrade() {
iodata_mstc_upgrade_prepare "0x1fe75"
nand_do_upgrade "$1"
;;
tplink,er605-v2)
echo "Upgrading tplink,er605-v2"
CI_UBIPART="firmware"
CI_KERNPART="kernel"
nand_do_upgrade "$1"
;;
ubnt,edgerouter-x|\
ubnt,edgerouter-x-sfp)
platform_upgrade_ubnt_erx "$1"

View File

@ -5,12 +5,11 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=nasm
PKG_VERSION:=2.15.05
PKG_VERSION:=2.16.01
PKG_SOURCE_URL:=https://www.nasm.us/pub/nasm/releasebuilds/$(PKG_VERSION)/
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_HASH:=3caf6729c1073bf96629b57cee31eeb54f4f8129b01902c73428836550b30a3f
PKG_HASH:=c77745f4802375efeee2ec5c0ad6b7f037ea9c87c92b149a9637ff099f162558
HOST_BUILD_PARALLEL:=1