Merge Mainline

config/Config-kernel.in

@@ -269,21 +269,6 @@ config KERNEL_DEBUG_GPIO
 	bool "Compile the kernel with gpio debugging"
 	select KERNEL_DEBUG_KERNEL
 
-choice
-	prompt "Algorithms enabled for QCE acceleration"
-	default KERNEL_CRYPTO_DEV_QCE_ENABLE_ALL
-	depends on TARGET_ipq40xx
-
-	config KERNEL_CRYPTO_DEV_QCE_ENABLE_ALL
-		bool "All supported algorithms"
-
-	config KERNEL_CRYPTO_DEV_QCE_ENABLE_BLKCIPHER
-		bool "Block ciphers only"
-
-	config KERNEL_CRYPTO_DEV_QCE_ENABLE_SHA
-		bool "Hash/HMAC only"
-endchoice
-
 config KERNEL_COREDUMP
 	bool
 

include/kernel-version.mk

@@ -6,11 +6,12 @@ ifdef CONFIG_TESTING_KERNEL
   KERNEL_PATCHVER:=$(KERNEL_TESTING_PATCHVER)
 endif
 
-LINUX_VERSION-4.14 = .193
-LINUX_VERSION-4.19 = .140
+LINUX_VERSION-4.14 = .194
+LINUX_VERSION-4.19 = .141
 LINUX_VERSION-5.4 = .59
-LINUX_KERNEL_HASH-4.14.193 = 0b0fb41d4430e1a42738b341cbfd2f41951aa5cd02acabbd53f076119c8b9f03
-LINUX_KERNEL_HASH-4.19.140 = ca0ff9a7bf005bef10af477b8e7bdd6e466b20c388d862426fd8842511f18ea8
+
+LINUX_KERNEL_HASH-4.14.194 = 3ea4d0221a071d58703cd346a8a6ef1582a32a8c4565a4919578817444d4fae0
+LINUX_KERNEL_HASH-4.19.141 = a4421dea5333beeaaef81312c6f415330b9e4fda6027f399a1c55f97d3da2114
 LINUX_KERNEL_HASH-5.4.59 = 9bcb9db2e4435f2e5948375862baf0973f1d7860ebe3d750383e5a6deac4b2fd
 
 remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))

package/ctcgfw/luci-theme-argonv3/Makefile

@@ -7,9 +7,9 @@
 include $(TOPDIR)/rules.mk
 
 LUCI_TITLE:=Argon Theme
-LUCI_DEPENDS:=+luasocket
-PKG_VERSION:=1.6.8
-PKG_RELEASE:=20200820
+LUCI_DEPENDS:=
+PKG_VERSION:=1.6.9
+PKG_RELEASE:=20200821
 
 include $(TOPDIR)/feeds/luci/luci.mk
 

package/ctcgfw/luci-theme-argonv3/htdocs/luci-static/argon/css/cascade.css

@@ -131,11 +131,6 @@ li {
 ***************************/
 .login-page {
   height: 100%;
-  background-image: url(../img/blank.png);
-  background-repeat: no-repeat;
-  background-position: center;
-  background-size: cover;
-  transition: all 0.5s;
 }
 .login-page .video {
   position: absolute;
@@ -166,6 +161,18 @@ li {
 .login-page .volume-control.mute {
   background-image: url(../img/volume_off.svg);
 }
+.login-page .main-bg {
+  position: absolute;
+  width: 100%;
+  height: 100%;
+  left: 0;
+  top: 0;
+  background-image: url(../img/blank.png);
+  background-repeat: no-repeat;
+  background-position: center;
+  background-size: cover;
+  transition: all 0.5s;
+}
 .login-page .login-container {
   height: 100%;
   margin-left: 4.5rem;
@@ -2286,9 +2293,9 @@ td > .ifacebadge {
   padding: 1rem;
   line-height: 1.4em;
   font-size: small;
-  color: #fff;
+  color: #1e1e1e;
   border-radius: 0;
-  background-color: #1e1e1e;
+  background-color: #fff;
   border: none;
   outline: none;
 }

package/ctcgfw/luci-theme-argonv3/htdocs/luci-static/argon/less/cascade.less

@@ -152,11 +152,6 @@ li {
 
 .login-page {
     height: 100%;
-    background-image: url(../img/blank.png);
-    background-repeat: no-repeat;
-    background-position: center;
-    background-size: cover;
-    transition: all 0.5s;
 
     .video {
         position: absolute;
@@ -189,6 +184,19 @@ li {
         }
     }
 
+    .main-bg{
+        position: absolute;
+        width: 100%;
+        height: 100%;
+        left: 0;
+        top: 0;
+        background-image: url(../img/blank.png);
+        background-repeat: no-repeat;
+        background-position: center;
+        background-size: cover;
+        transition: all 0.5s;
+    }
+
     .login-container {
         height: 100%;
         margin-left: 4.5rem;
@@ -2819,9 +2827,9 @@ td>.ifacebadge {
     padding: 1rem;
     line-height: 1.4em;
     font-size: small;
-    color: #fff;
+    color: #1e1e1e;
     border-radius: 0;
-    background-color: #1e1e1e;
+    background-color: #fff;
     border: none;
     outline: none;
 }

package/ctcgfw/luci-theme-argonv3/luasrc/view/themes/argon/sysauth.htm

@@ -21,7 +21,6 @@
 	Licensed to the public under the Apache License 2.0
 -%>
 
-
 <%+header_login%>
 <%
 	local util = require "luci.util"
@@ -29,7 +28,6 @@
 	local fs	= require "nixio.fs"
 	local nutil = require "nixio.util"
 
-	-- get files from folder
 	function glob(...)
 		local iter, code, msg = fs.glob(...)
 		if iter then
@@ -39,7 +37,6 @@
 		end
 	end
 
-	-- get file extension
 	function getExtension(str)
 		return str:match(".+%.(%w+)$")
 	end
@@ -62,12 +59,9 @@
 		end
 	end
 
-
 	if bgcount > 0 then
 		currentBg =  bgs[math.random(1,bgcount)]
 	end
-
-
 %>
 <div class="login-page">
 	<% if (bgcount > 0 and currentBg.type == "mp4") then %>
@@ -77,7 +71,6 @@
 		</video>
 	</div>
 	<div class="volume-control mute"></div>
-	
 	<script>
 		$(".volume-control").click(function(){
 			if($(this).hasClass("mute")){
@@ -89,24 +82,43 @@
 			}
 		})
 	</script>
+	<% else %>
+	<div class="main-bg" id="main-bg" 
+	<%
+	if (bgcount == 0 ) then
+		local http = require "luci.sys"
+		local json = require "luci.jsonc"
+		local bg_url = media .. "/img/bg1.jpg"
+		local bing = http.httpget("http://www.bing.com/HPImageArchive.aspx?format=js&idx=0&n=1&mkt=en-US")
+		if (bing and bing ~= '') then
+			local bingjson  = json.parse(bing)
+			bg_url = "https://www.bing.com" .. bingjson.images[1].url
+		end
+	%>
+		style="background-image:url(<%=bg_url%>)"
+	<% elseif  (bgcount > 0 and currentBg["type"] ~= "mp4") then %>
+		style="background-image:url(<%=currentBg.url%>)"
+	<% end  %>
+	></div>
+	
 	<% end %>
 	<div class="login-container">
 		<div class="login-form">
 			<a class="brand" href="/"><img src="<%=media%>/img/argon.svg" class="icon"><span
 					class="brand-text"><%=striptags( (boardinfo.hostname or "?") .. ( (node and node.title) and ' - ' .. translate(node.title) or '')) %></span></a>
 			<form class="form-login" method="post" action="<%=pcdata(luci.http.getenv("REQUEST_URI"))%>">
+
 				<%- if fuser then %>
 				<div class="errorbox"><%:Invalid username and/or password! Please try again.%></div>
 				<% end -%>
+
 				<div class="input-container">
 					<div class="input-group user-icon">
-						<input class="cbi-input-user" id="cbi-input-user" type="text" name="luci_username"
-							value="<%=duser%>" />
+						<input class="cbi-input-user" id="cbi-input-user" type="text" name="luci_username" value="<%=duser%>" />
 						<label class="border" for="cbi-input-user"></label>
 					</div>
 					<div class="input-group pass-icon">
-						<input class="cbi-input-password" id="cbi-input-password" type="password"
-							name="luci_password" />
+						<input class="cbi-input-password" id="cbi-input-password" type="password" name="luci_password" />
 						<label class="border" for="cbi-input-password"></label>
 					</div>
 				</div>
@@ -114,40 +126,13 @@
 					<input type="submit" value="<%:Login%>" class="cbi-button cbi-button-apply" />
 				</div>
 			</form>
+
 			<script type="text/javascript">//<![CDATA[
 				var input = document.getElementsByName('luci_password')[0];
 				if (input)
 					input.focus();
 			//]]></script>
 			<%
-			if (bgcount == 0 ) then
-				local bingjson = "{}"
-				local http = require "socket.http"
-				local bing = http.request("http://www.bing.com/HPImageArchive.aspx?format=js&idx=0&n=1&mkt=en-US")
-				if (bing and bing ~= '') then
-					bingjson = bing
-				end
-			%>
-			<script type="text/javascript">//<![CDATA[
-				try {
-					var bing = <%=bingjson%>;
-					var bg = "https://www.bing.com" + bing.images[0].url;
-					$(".login-page").css("background-image", "url(" + bg + ")");
-				} catch{
-					console.log("can not access bing api");
-					$(".login-page").css("background-image", "url(<%=media%>/img/bg1.jpg)");
-				}
-		//]]></script>
-			<% elseif  (bgcount > 0 and currentBg["type"] ~= "mp4") then%>
-			<script type="text/javascript">//<![CDATA[
-				console.log("can not access bing api");
-				$(".login-page").css("background-image", "url(<%=currentBg.url%>)");
-
-		//]]></script>
-
-			<%
-			end 
-
 			local uci  = require "luci.model.uci".cursor()
 			local fs  = require "nixio.fs"
 			local https_key = uci:get("uhttpd", "main", "key")
@@ -169,7 +154,6 @@
 						img.src = ''
 					}, 5000);
 				}
-		//]]></script>
+			//]]></script>
 			<% end %>
-
-			<%+footer%>
+<%+footer%>

package/kernel/linux/modules/wpan.mk

@@ -88,6 +88,7 @@ define KernelPackage/at86rf230
 	CONFIG_SPI=y \
 	CONFIG_SPI_MASTER=y
   FILES:=$(LINUX_DIR)/drivers/net/ieee802154/at86rf230.ko
+  AUTOLOAD:=$(call AutoProbe,at86rf230)
 endef
 
 $(eval $(call KernelPackage,at86rf230))
@@ -100,6 +101,7 @@ define KernelPackage/mrf24j40
 	CONFIG_SPI=y \
 	CONFIG_SPI_MASTER=y
   FILES:=$(LINUX_DIR)/drivers/net/ieee802154/mrf24j40.ko
+  AUTOLOAD:=$(call AutoProbe,mrf24j40)
 endef
 
 $(eval $(call KernelPackage,mrf24j40))
@@ -112,6 +114,7 @@ define KernelPackage/cc2520
 	CONFIG_SPI=y \
 	CONFIG_SPI_MASTER=y
   FILES:=$(LINUX_DIR)/drivers/net/ieee802154/cc2520.ko
+  AUTOLOAD:=$(call AutoProbe,cc2520)
 endef
 
 $(eval $(call KernelPackage,cc2520))

package/lean/coremark/Makefile

@@ -37,10 +37,9 @@ endef
 
 DIR_ARCH:=linux
 
-ifeq ($(ARCH),x86_64)
+ifeq ($(CONFIG_ARCH_64BIT),y)
 	DIR_ARCH:=linux64
-endif
-ifeq ($(ARCH),aarch64)
+else ifeq ($(CONFIG_64BIT),y)
 	DIR_ARCH:=linux64
 endif
 

package/network/utils/wireguard-tools/Makefile

@@ -11,12 +11,12 @@ include $(INCLUDE_DIR)/kernel.mk
 
 PKG_NAME:=wireguard-tools
 
-PKG_VERSION:=1.0.20200513
+PKG_VERSION:=1.0.20200820
 PKG_RELEASE:=1
 
 PKG_SOURCE:=wireguard-tools-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=https://git.zx2c4.com/wireguard-tools/snapshot/
-PKG_HASH:=e73409a9fb8c90506db241d1e1a4e7372a60dbfa400e37f4ab2fd70a92ba495f
+PKG_HASH:=7735a04c68fffb101a10a67e3bd97a171f2b8eb47e9ddce2be68eb6538b013d0
 
 PKG_LICENSE:=GPL-2.0
 PKG_LICENSE_FILES:=COPYING

target/linux/apm821xx/patches-4.14/801-usb-xhci-add-firmware-loader-for-uPD720201-and-uPD72.patch

@@ -44,7 +44,7 @@ Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
  
  #include "xhci.h"
  #include "xhci-trace.h"
-@@ -272,6 +274,458 @@ static void xhci_pme_acpi_rtd3_enable(st
+@@ -276,6 +278,458 @@ static void xhci_pme_acpi_rtd3_enable(st
  static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
  #endif /* CONFIG_ACPI */
  
@@ -503,7 +503,7 @@ Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
  /* called during probe() after chip reset completes */
  static int xhci_pci_setup(struct usb_hcd *hcd)
  {
-@@ -310,6 +764,22 @@ static int xhci_pci_probe(struct pci_dev
+@@ -314,6 +768,22 @@ static int xhci_pci_probe(struct pci_dev
  	struct hc_driver *driver;
  	struct usb_hcd *hcd;
  
@@ -526,7 +526,7 @@ Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
  	driver = (struct hc_driver *)id->driver_data;
  
  	/* For some HW implementation, a XHCI reset is just not enough... */
-@@ -371,6 +841,16 @@ static void xhci_pci_remove(struct pci_d
+@@ -375,6 +845,16 @@ static void xhci_pci_remove(struct pci_d
  {
  	struct xhci_hcd *xhci;
  

target/linux/apm821xx/patches-4.14/802-usb-xhci-force-msi-renesas-xhci.patch

@@ -13,7 +13,7 @@ produce a noisy warning.
 
 --- a/drivers/usb/host/xhci-pci.c
 +++ b/drivers/usb/host/xhci-pci.c
-@@ -222,7 +222,7 @@ static void xhci_pci_quirks(struct devic
+@@ -225,7 +225,7 @@ static void xhci_pci_quirks(struct devic
  		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
  			pdev->device == 0x0015)

target/linux/ar71xx/patches-4.14/910-unaligned_access_hacks.patch

@@ -850,7 +850,7 @@
  		*sum = csum_fold(csum_partial(diff, sizeof(diff),
 --- a/drivers/net/vxlan.c
 +++ b/drivers/net/vxlan.c
-@@ -1872,15 +1872,15 @@ static int vxlan_build_skb(struct sk_buf
+@@ -1876,15 +1876,15 @@ static int vxlan_build_skb(struct sk_buf
  		return err;
  
  	vxh = __skb_push(skb, sizeof(*vxh));

target/linux/cns3xxx/patches-4.19/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch

@@ -1,6 +1,6 @@
 --- a/drivers/pci/probe.c
 +++ b/drivers/pci/probe.c
-@@ -2655,7 +2655,8 @@ static void pcie_write_mrrs(struct pci_d
+@@ -2707,7 +2707,8 @@ static void pcie_write_mrrs(struct pci_d
  	 * In the "safe" case, do not configure the MRRS.  There appear to be
  	 * issues with setting MRRS to 0 on a number of devices.
  	 */
@@ -12,7 +12,7 @@
  	/*
 --- a/include/linux/pci.h
 +++ b/include/linux/pci.h
-@@ -868,7 +868,7 @@ enum pcie_bus_config_types {
+@@ -871,7 +871,7 @@ enum pcie_bus_config_types {
  	PCIE_BUS_DEFAULT,	/* Ensure MPS matches upstream bridge */
  	PCIE_BUS_SAFE,		/* Use largest MPS boot-time devices support */
  	PCIE_BUS_PERFORMANCE,	/* Use MPS and MRRS for best performance */

target/linux/generic/backport-4.14/025-tcp-allow-drivers-to-tweak-TSQ-logic.patch

@@ -55,7 +55,7 @@ Cc: Kir Kolyshkin <kir@openvz.org>
  	rwlock_t		sk_callback_lock;
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -2750,6 +2750,7 @@ void sock_init_data(struct socket *sock,
+@@ -2771,6 +2771,7 @@ void sock_init_data(struct socket *sock,
  
  	sk->sk_max_pacing_rate = ~0U;
  	sk->sk_pacing_rate = ~0U;

target/linux/generic/config-4.14

@@ -354,6 +354,7 @@ CONFIG_ATAGS_PROC=y
 # CONFIG_ATA_ACPI is not set
 CONFIG_ATA_BMDMA=y
 # CONFIG_ATA_GENERIC is not set
+# CONFIG_ATA_LEDS is not set
 # CONFIG_ATA_NONSTANDARD is not set
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_ATA_PIIX is not set
@@ -594,6 +595,7 @@ CONFIG_BLOCK=y
 # CONFIG_BONDING is not set
 # CONFIG_BOOKE_WDT is not set
 CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT=3
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 CONFIG_BOOT_RAW=y
 CONFIG_BPF=y
@@ -866,6 +868,12 @@ CONFIG_CROSS_COMPILE=""
 CONFIG_CRYPTO=y
 # CONFIG_CRYPTO_842 is not set
 # CONFIG_CRYPTO_AEAD is not set
+# CONFIG_CRYPTO_AEGIS128 is not set
+# CONFIG_CRYPTO_AEGIS128L is not set
+# CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2 is not set
+# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set
+# CONFIG_CRYPTO_AEGIS256 is not set
+# CONFIG_CRYPTO_AEGIS256_AESNI_SSE2 is not set
 CONFIG_CRYPTO_AES=y
 # CONFIG_CRYPTO_AES_586 is not set
 # CONFIG_CRYPTO_AES_ARM is not set
@@ -877,7 +885,7 @@ CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_ARC4 is not set
 # CONFIG_CRYPTO_AUTHENC is not set
 CONFIG_CRYPTO_BLKCIPHER=y
 CONFIG_CRYPTO_BLKCIPHER2=y
@@ -887,14 +895,15 @@ CONFIG_CRYPTO_BLKCIPHER2=y
 # CONFIG_CRYPTO_CAST6 is not set
 # CONFIG_CRYPTO_CBC is not set
 # CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CFB is not set
 # CONFIG_CRYPTO_CHACHA20 is not set
-# CONFIG_CRYPTO_CHACHA20_NEON is not set
 # CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_CHACHA20_NEON is not set
 # CONFIG_CRYPTO_CMAC is not set
 # CONFIG_CRYPTO_CRC32 is not set
-# CONFIG_CRYPTO_CRC32_ARM_CE is not set
 # CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_CRC32C_INTEL is not set
+# CONFIG_CRYPTO_CRC32_ARM_CE is not set
 # CONFIG_CRYPTO_CRCT10DIF is not set
 # CONFIG_CRYPTO_CRYPTD is not set
 # CONFIG_CRYPTO_CTR is not set
@@ -912,6 +921,7 @@ CONFIG_CRYPTO_BLKCIPHER2=y
 # CONFIG_CRYPTO_DEV_FSL_CAAM is not set
 # CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set
 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_CRYPTO_DEV_HISI_SEC is not set
 # CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
 # CONFIG_CRYPTO_DEV_MARVELL_CESA is not set
 # CONFIG_CRYPTO_DEV_MV_CESA is not set
@@ -928,6 +938,7 @@ CONFIG_CRYPTO_BLKCIPHER2=y
 # CONFIG_CRYPTO_DEV_S5P is not set
 # CONFIG_CRYPTO_DEV_SAFEXCEL is not set
 # CONFIG_CRYPTO_DEV_SAHARA is not set
+# CONFIG_CRYPTO_DEV_SP_PSP is not set
 # CONFIG_CRYPTO_DEV_TALITOS is not set
 # CONFIG_CRYPTO_DEV_VIRTIO is not set
 # CONFIG_CRYPTO_DH is not set
@@ -961,6 +972,11 @@ CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_MORUS1280 is not set
+# CONFIG_CRYPTO_MORUS1280_AVX2 is not set
+# CONFIG_CRYPTO_MORUS1280_SSE2 is not set
+# CONFIG_CRYPTO_MORUS640 is not set
+# CONFIG_CRYPTO_MORUS640_SSE2 is not set
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_PCBC is not set
 # CONFIG_CRYPTO_PCOMP is not set
@@ -982,13 +998,16 @@ CONFIG_CRYPTO_PCRYPT=y
 # CONFIG_CRYPTO_SHA1_ARM is not set
 # CONFIG_CRYPTO_SHA1_ARM_CE is not set
 # CONFIG_CRYPTO_SHA1_ARM_NEON is not set
-# CONFIG_CRYPTO_SHA2_ARM_CE is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA256_ARM is not set
+# CONFIG_CRYPTO_SHA2_ARM_CE is not set
 # CONFIG_CRYPTO_SHA3 is not set
 # CONFIG_CRYPTO_SHA512 is not set
 # CONFIG_CRYPTO_SHA512_ARM is not set
 # CONFIG_CRYPTO_SIMD is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_SPECK is not set
 # CONFIG_CRYPTO_TEA is not set
 # CONFIG_CRYPTO_TEST is not set
 # CONFIG_CRYPTO_TGR192 is not set
@@ -1005,6 +1024,7 @@ CONFIG_CRYPTO_PCRYPT=y
 # CONFIG_CRYPTO_XCBC is not set
 # CONFIG_CRYPTO_XTS is not set
 # CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_ZSTD is not set
 # CONFIG_CS5535_MFGPT is not set
 # CONFIG_CS89x0 is not set
 # CONFIG_CUSE is not set
@@ -1080,6 +1100,9 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_UART_BCM63XX is not set
 # CONFIG_DEBUG_VIRTUAL is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_VM_PGFLAGS is not set
+# CONFIG_DEBUG_VM_RB is not set
+# CONFIG_DEBUG_VM_VMACACHE is not set
 # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
 # CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
 # CONFIG_DEBUG_WX is not set
@@ -1088,6 +1111,7 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DEFAULT_CUBIC=y
 CONFIG_DEFAULT_DEADLINE=y
 CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
 CONFIG_DEFAULT_IOSCHED="deadline"
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 # CONFIG_DEFAULT_NOOP is not set
@@ -1523,6 +1547,10 @@ CONFIG_GACT_PROB=y
 # CONFIG_GAMEPORT is not set
 # CONFIG_GATEWORKS_GW16083 is not set
 # CONFIG_GCC_PLUGINS is not set
+# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
+# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
+# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
+# CONFIG_GCC_PLUGIN_STRUCTLEAK is not set
 # CONFIG_GCOV is not set
 # CONFIG_GCOV_KERNEL is not set
 # CONFIG_GDB_SCRIPTS is not set
@@ -1763,6 +1791,8 @@ CONFIG_HPET_MMAP_DEFAULT=y
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_HTS221 is not set
 # CONFIG_HTU21 is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_HUGETLBFS is not set
 # CONFIG_HVC_DCC is not set
 # CONFIG_HVC_UDBG is not set
 # CONFIG_HWLAT_TRACER is not set
@@ -4944,6 +4974,7 @@ CONFIG_TCP_CONG_CUBIC=y
 # CONFIG_TEST_FIRMWARE is not set
 # CONFIG_TEST_HASH is not set
 # CONFIG_TEST_HEXDUMP is not set
+# CONFIG_TEST_KASAN is not set
 # CONFIG_TEST_KMOD is not set
 # CONFIG_TEST_KSTRTOX is not set
 # CONFIG_TEST_LIST_SORT is not set
@@ -5151,6 +5182,7 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_TRACING_EVENTS_GPIO is not set
 CONFIG_TRACING_SUPPORT=y
 CONFIG_TRAD_SIGNALS=y
+# CONFIG_TRANSPARENT_HUGEPAGE is not set
 # CONFIG_TREE_RCU is not set
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_TRIM_UNUSED_KSYMS is not set
@@ -5241,6 +5273,7 @@ CONFIG_USB_DEFAULT_PERSIST=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_EG20T is not set
 # CONFIG_USB_EHCI_ATH79 is not set
+# CONFIG_USB_EHCI_HCD is not set
 # CONFIG_USB_EHCI_HCD_AT91 is not set
 # CONFIG_USB_EHCI_HCD_OMAP is not set
 # CONFIG_USB_EHCI_HCD_PPC_OF is not set

target/linux/generic/config-4.19

@@ -372,6 +372,7 @@ CONFIG_ATAGS_PROC=y
 # CONFIG_ATA_ACPI is not set
 CONFIG_ATA_BMDMA=y
 # CONFIG_ATA_GENERIC is not set
+# CONFIG_ATA_LEDS is not set
 # CONFIG_ATA_NONSTANDARD is not set
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_ATA_PIIX is not set
@@ -936,13 +937,13 @@ CONFIG_CRYPTO_BLKCIPHER2=y
 # CONFIG_CRYPTO_CCM is not set
 # CONFIG_CRYPTO_CFB is not set
 # CONFIG_CRYPTO_CHACHA20 is not set
-# CONFIG_CRYPTO_CHACHA20_NEON is not set
 # CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_CHACHA20_NEON is not set
 # CONFIG_CRYPTO_CMAC is not set
 # CONFIG_CRYPTO_CRC32 is not set
-# CONFIG_CRYPTO_CRC32_ARM_CE is not set
 # CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_CRC32C_INTEL is not set
+# CONFIG_CRYPTO_CRC32_ARM_CE is not set
 # CONFIG_CRYPTO_CRCT10DIF is not set
 # CONFIG_CRYPTO_CRYPTD is not set
 # CONFIG_CRYPTO_CTR is not set
@@ -1037,9 +1038,9 @@ CONFIG_CRYPTO_PCRYPT=y
 # CONFIG_CRYPTO_SHA1_ARM is not set
 # CONFIG_CRYPTO_SHA1_ARM_CE is not set
 # CONFIG_CRYPTO_SHA1_ARM_NEON is not set
-# CONFIG_CRYPTO_SHA2_ARM_CE is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA256_ARM is not set
+# CONFIG_CRYPTO_SHA2_ARM_CE is not set
 # CONFIG_CRYPTO_SHA3 is not set
 # CONFIG_CRYPTO_SHA512 is not set
 # CONFIG_CRYPTO_SHA512_ARM is not set
@@ -1882,6 +1883,8 @@ CONFIG_HPET_MMAP_DEFAULT=y
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_HTS221 is not set
 # CONFIG_HTU21 is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_HUGETLBFS is not set
 # CONFIG_HVC_DCC is not set
 # CONFIG_HVC_UDBG is not set
 # CONFIG_HWLAT_TRACER is not set
@@ -5431,6 +5434,7 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_TRACING_EVENTS_GPIO is not set
 CONFIG_TRACING_SUPPORT=y
 CONFIG_TRAD_SIGNALS=y
+# CONFIG_TRANSPARENT_HUGEPAGE is not set
 # CONFIG_TREE_RCU is not set
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_TRIM_UNUSED_KSYMS is not set
@@ -5527,6 +5531,7 @@ CONFIG_USB_DEFAULT_PERSIST=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_EG20T is not set
 # CONFIG_USB_EHCI_ATH79 is not set
+# CONFIG_USB_EHCI_HCD is not set
 # CONFIG_USB_EHCI_HCD_AT91 is not set
 # CONFIG_USB_EHCI_HCD_OMAP is not set
 # CONFIG_USB_EHCI_HCD_PPC_OF is not set

target/linux/generic/hack-4.14/211-host_tools_portability.patch

@@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/tools/build/Build.include
 +++ b/tools/build/Build.include
-@@ -98,4 +98,4 @@ cxx_flags = -Wp,-MD,$(depfile) -Wp,-MT,$
+@@ -99,4 +99,4 @@ cxx_flags = -Wp,-MD,$(depfile) -Wp,-MT,$
  ###
  ## HOSTCC C flags
  

target/linux/generic/hack-4.14/902-debloat_proc.patch

@@ -327,7 +327,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -3389,6 +3389,8 @@ static __net_initdata struct pernet_oper
+@@ -3410,6 +3410,8 @@ static __net_initdata struct pernet_oper
  
  static int __init proto_init(void)
  {

target/linux/generic/hack-4.14/952-net-conntrack-events-support-multiple-registrant.patch

@@ -1,5 +1,3 @@
-diff --git a/include/net/netfilter/nf_conntrack_ecache.h b/include/net/netfilter/nf_conntrack_ecache.h
-index 12d967b..c2b98b6 100644
 --- a/include/net/netfilter/nf_conntrack_ecache.h
 +++ b/include/net/netfilter/nf_conntrack_ecache.h
 @@ -71,6 +71,10 @@ struct nf_ct_event {
@@ -67,8 +65,6 @@ index 12d967b..c2b98b6 100644
  	return nf_conntrack_eventmask_report(1 << event, ct, 0, 0);
  }
  
-diff --git a/include/net/netns/conntrack.h b/include/net/netns/conntrack.h
-index e469e85..1d31db8 100644
 --- a/include/net/netns/conntrack.h
 +++ b/include/net/netns/conntrack.h
 @@ -114,7 +114,11 @@ struct netns_ct {
@@ -83,13 +79,11 @@ index e469e85..1d31db8 100644
  	struct nf_exp_event_notifier __rcu *nf_expect_event_cb;
  	struct nf_ip_net	nf_ct_proto;
  #if defined(CONFIG_NF_CONNTRACK_LABELS)
-diff --git a/net/netfilter/Kconfig b/net/netfilter/Kconfig
-index 63073be..08d7aab 100644
 --- a/net/netfilter/Kconfig
 +++ b/net/netfilter/Kconfig
-@@ -118,6 +118,14 @@ config NF_CONNTRACK_EVENTS
- 
- 	  If unsure, say `N'.
+@@ -136,6 +136,14 @@ config NF_CONNTRACK_RTCACHE
+ 	  To compile it as a module, choose M here.  If unsure, say N.
+ 	  The module will be called nf_conntrack_rtcache.
  
 +config NF_CONNTRACK_CHAIN_EVENTS
 +	bool "Register multiple callbacks to ct events"
@@ -102,11 +96,9 @@ index 63073be..08d7aab 100644
  config NF_CONNTRACK_TIMEOUT
  	bool  'Connection tracking timeout'
  	depends on NETFILTER_ADVANCED
-diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c
-index 6bd1508..9b81c7c 100644
 --- a/net/netfilter/nf_conntrack_core.c
 +++ b/net/netfilter/nf_conntrack_core.c
-@@ -2167,6 +2167,10 @@ int nf_conntrack_init_net(struct net *ne
+@@ -2249,6 +2249,10 @@ int nf_conntrack_init_net(struct net *ne
  	ret = nf_conntrack_proto_pernet_init(net);
  	if (ret < 0)
  		goto err_proto;
@@ -117,8 +109,6 @@ index 6bd1508..9b81c7c 100644
  	return 0;
  
  err_proto:
-diff --git a/net/netfilter/nf_conntrack_ecache.c b/net/netfilter/nf_conntrack_ecache.c
-index da9df2d..e0e2a8f 100644
 --- a/net/netfilter/nf_conntrack_ecache.c
 +++ b/net/netfilter/nf_conntrack_ecache.c
 @@ -18,6 +18,9 @@
@@ -268,8 +258,6 @@ index da9df2d..e0e2a8f 100644
  EXPORT_SYMBOL_GPL(nf_conntrack_unregister_notifier);
  
  int nf_ct_expect_register_notifier(struct net *net,
-diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c
-index 04111c1..8c741f7 100644
 --- a/net/netfilter/nf_conntrack_netlink.c
 +++ b/net/netfilter/nf_conntrack_netlink.c
 @@ -28,6 +28,11 @@
@@ -282,9 +270,9 @@ index 04111c1..8c741f7 100644
 +#endif
 +
  #include <linux/slab.h>
+ #include <linux/siphash.h>
  
- #include <linux/netfilter.h>
-@@ -618,14 +623,22 @@ static size_t ctnetlink_nlmsg_size(const
+@@ -621,14 +626,22 @@ static size_t ctnetlink_nlmsg_size(const
  	       ;
  }
  
@@ -307,7 +295,7 @@ index 04111c1..8c741f7 100644
  	struct nf_conn *ct = item->ct;
  	struct sk_buff *skb;
  	unsigned int type;
-@@ -3290,9 +3303,15 @@ static int ctnetlink_stat_exp_cpu(struct
+@@ -3335,9 +3348,15 @@ static int ctnetlink_stat_exp_cpu(struct
  }
  
  #ifdef CONFIG_NF_CONNTRACK_EVENTS

target/linux/generic/hack-4.14/999-net-patch-linux-kernel-to-support-shortcut-fe.patch

@@ -1,6 +1,6 @@
---- a/include/linux/skbuff.h	2019-01-16 20:16:08.325745306 +0800
-+++ b/include/linux/skbuff.h	2019-01-16 20:31:47.288028493 +0800
-@@ -783,6 +783,9 @@ struct sk_buff {
+--- a/include/linux/skbuff.h
++++ b/include/linux/skbuff.h
+@@ -796,6 +796,9 @@ struct sk_buff {
  	__u8			tc_from_ingress:1;
  #endif
  	__u8			gro_skip:1;
@@ -10,8 +10,8 @@
  
  #ifdef CONFIG_NET_SCHED
  	__u16			tc_index;	/* traffic control index */
---- a/include/linux/if_bridge.h	2019-01-16 20:51:47.871445535 +0800
-+++ b/include/linux/if_bridge.h	2019-01-16 20:52:26.220269649 +0800
+--- a/include/linux/if_bridge.h
++++ b/include/linux/if_bridge.h
 @@ -54,6 +54,8 @@ struct br_ip_list {
  #define BR_DEFAULT_AGEING_TIME	(300 * HZ)
  
@@ -33,8 +33,8 @@
  
  #ifdef CONFIG_LOCKDEP
  	struct lockdep_map	lockdep_map;
---- a/net/Kconfig	2019-01-16 20:36:30.266465286 +0800
-+++ b/net/Kconfig	2019-01-16 20:36:41.980609067 +0800
+--- a/net/Kconfig
++++ b/net/Kconfig
 @@ -463,3 +463,6 @@ config HAVE_CBPF_JIT
  # Extended BPF JIT (eBPF)
  config HAVE_EBPF_JIT
@@ -42,19 +42,18 @@
 +
 +config SHORTCUT_FE
 +	bool "Enables kernel network stack path for Shortcut  Forwarding Engine
---- a/net/core/dev.c	2019-01-16 20:38:37.274933833 +0800
-+++ b/net/core/dev.c	2019-01-16 20:44:07.773594898 +0800
-@@ -3005,8 +3005,17 @@ static int xmit_one(struct sk_buff *skb, struct net_device *dev,
- 		!(skb->imq_flags & IMQ_F_ENQUEUE))
+--- a/net/core/dev.c
++++ b/net/core/dev.c
+@@ -3006,7 +3006,16 @@ static int xmit_one(struct sk_buff *skb,
  #else
  	if (!list_empty(&ptype_all) || !list_empty(&dev->ptype_all))
-+#endif
+ #endif
 +#ifdef CONFIG_SHORTCUT_FE
 +	/* If this skb has been fast forwarded then we don't want it to
 +	 * go to any taps (by definition we're trying to bypass them).
 +	 */
 +	if (!skb->fast_forwarded) {
- #endif
++#endif
  		dev_queue_xmit_nit(skb, dev);
 +#ifdef CONFIG_SHORTCUT_FE
 +	}
@@ -62,7 +61,7 @@
  
  #ifdef CONFIG_ETHERNET_PACKET_MANGLE
  	if (!dev->eth_mangle_tx ||
-@@ -4315,6 +4324,11 @@ void netdev_rx_handler_unregister(struct
+@@ -4321,6 +4330,11 @@ void netdev_rx_handler_unregister(struct
  }
  EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister);
  
@@ -74,7 +73,7 @@
  /*
   * Limit the use of PFMEMALLOC reserves to those protocols that implement
   * the special handling of PFMEMALLOC skbs.
-@@ -4362,6 +4376,9 @@ static int __netif_receive_skb_core(stru
+@@ -4368,6 +4382,9 @@ static int __netif_receive_skb_core(stru
  	bool deliver_exact = false;
  	int ret = NET_RX_DROP;
  	__be16 type;
@@ -84,7 +83,7 @@
  
  	net_timestamp_check(!netdev_tstamp_prequeue, skb);
  
-@@ -4388,6 +4405,16 @@ another_round:
+@@ -4394,6 +4411,16 @@ another_round:
  			goto out;
  	}
  
@@ -101,8 +100,8 @@
  	if (skb_skip_tc_classify(skb))
  		goto skip_classify;
  
---- a/net/netfilter/nf_conntrack_proto_tcp.c	2019-01-16 20:47:40.886993297 +0800
-+++ b/net/netfilter/nf_conntrack_proto_tcp.c	2019-01-16 20:48:57.700570104 +0800
+--- a/net/netfilter/nf_conntrack_proto_tcp.c
++++ b/net/netfilter/nf_conntrack_proto_tcp.c
 @@ -35,11 +35,17 @@
  
  /* Do not check the TCP window for incoming packets  */
@@ -121,8 +120,8 @@
  
  /* If it is set to zero, we disable picking up already established
     connections. */
---- a/net/bridge/br_if.c	2019-01-16 20:54:51.919367044 +0800
-+++ b/net/bridge/br_if.c	2019-01-16 20:55:53.812401263 +0800
+--- a/net/bridge/br_if.c
++++ b/net/bridge/br_if.c
 @@ -653,3 +653,26 @@ void br_port_flags_change(struct net_bri
  	if (mask & BR_AUTO_MASK)
  		nbp_update_port_count(br);
@@ -150,9 +149,9 @@
 +	u64_stats_update_end(&stats->syncp);
 +}
 +EXPORT_SYMBOL_GPL(br_dev_update_stats);
---- a/net/netfilter/Kconfig	2019-01-16 21:07:34.543460920 +0800
-+++ b/net/netfilter/Kconfig	2019-01-16 21:08:14.739465937 +0800
-@@ -146,6 +146,14 @@ config NF_CONNTRACK_TIMEOUT
+--- a/net/netfilter/Kconfig
++++ b/net/netfilter/Kconfig
+@@ -154,6 +154,14 @@ config NF_CONNTRACK_TIMEOUT
  
  	  If unsure, say `N'.
  
@@ -167,9 +166,9 @@
  config NF_CONNTRACK_TIMESTAMP
  	bool  'Connection tracking timestamping'
  	depends on NETFILTER_ADVANCED
---- a/net/netfilter/nf_conntrack_ecache.c	2019-01-16 21:12:22.183462975 +0800
-+++ b/net/netfilter/nf_conntrack_ecache.c	2019-01-16 21:26:10.379462031 +0800
-@@ -122,13 +125,17 @@ int nf_conntrack_eventmask_report(unsign
+--- a/net/netfilter/nf_conntrack_ecache.c
++++ b/net/netfilter/nf_conntrack_ecache.c
+@@ -157,13 +157,17 @@ int nf_conntrack_eventmask_report(unsign
  {
  	int ret = 0;
  	struct net *net = nf_ct_net(ct);
@@ -187,7 +186,7 @@
  
  	e = nf_ct_ecache_find(ct);
  	if (!e)
-@@ -146,7 +153,12 @@ int nf_conntrack_eventmask_report(unsign
+@@ -181,7 +185,12 @@ int nf_conntrack_eventmask_report(unsign
  		if (!((eventmask | missed) & e->ctmask))
  			goto out_unlock;
  
@@ -200,7 +199,7 @@
  		if (unlikely(ret < 0 || missed)) {
  			spin_lock_bh(&ct->lock);
  			if (ret < 0) {
-@@ -179,15 +191,19 @@ void nf_ct_deliver_cached_events(struct
+@@ -256,15 +265,19 @@ void nf_ct_deliver_cached_events(struct
  {
  	struct net *net = nf_ct_net(ct);
  	unsigned long events, missed;
@@ -220,7 +219,7 @@
  
  	e = nf_ct_ecache_find(ct);
  	if (e == NULL)
-@@ -210,7 +226,13 @@ void nf_ct_deliver_cached_events(struct
+@@ -287,7 +300,13 @@ void nf_ct_deliver_cached_events(struct
  	item.portid = 0;
  	item.report = 0;
  

target/linux/generic/hack-4.19/204-module_strip.patch

@@ -114,7 +114,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  config MODULES_TREE_LOOKUP
 --- a/kernel/module.c
 +++ b/kernel/module.c
-@@ -3030,9 +3030,11 @@ static int setup_load_info(struct load_i
+@@ -3046,9 +3046,11 @@ static int setup_load_info(struct load_i
  
  static int check_modinfo(struct module *mod, struct load_info *info, int flags)
  {
@@ -127,7 +127,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (flags & MODULE_INIT_IGNORE_VERMAGIC)
  		modmagic = NULL;
  
-@@ -3053,6 +3055,7 @@ static int check_modinfo(struct module *
+@@ -3069,6 +3071,7 @@ static int check_modinfo(struct module *
  				mod->name);
  		add_taint_module(mod, TAINT_OOT_MODULE, LOCKDEP_STILL_OK);
  	}

target/linux/generic/hack-4.19/902-debloat_proc.patch

@@ -327,7 +327,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -3491,6 +3491,8 @@ static __net_initdata struct pernet_oper
+@@ -3512,6 +3512,8 @@ static __net_initdata struct pernet_oper
  
  static int __init proto_init(void)
  {

target/linux/generic/hack-4.19/952-net-conntrack-events-support-multiple-registrant.patch

@@ -1,5 +1,3 @@
-diff --git a/include/net/netfilter/nf_conntrack_ecache.h b/include/net/netfilter/nf_conntrack_ecache.h
-index 12d967b..c2b98b6 100644
 --- a/include/net/netfilter/nf_conntrack_ecache.h
 +++ b/include/net/netfilter/nf_conntrack_ecache.h
 @@ -71,6 +71,10 @@ struct nf_ct_event {
@@ -67,8 +65,6 @@ index 12d967b..c2b98b6 100644
  	return nf_conntrack_eventmask_report(1 << event, ct, 0, 0);
  }
  
-diff --git a/include/net/netns/conntrack.h b/include/net/netns/conntrack.h
-index e469e85..1d31db8 100644
 --- a/include/net/netns/conntrack.h
 +++ b/include/net/netns/conntrack.h
 @@ -114,7 +114,11 @@ struct netns_ct {
@@ -83,13 +79,11 @@ index e469e85..1d31db8 100644
  	struct nf_exp_event_notifier __rcu *nf_expect_event_cb;
  	struct nf_ip_net	nf_ct_proto;
  #if defined(CONFIG_NF_CONNTRACK_LABELS)
-diff --git a/net/netfilter/Kconfig b/net/netfilter/Kconfig
-index 63073be..08d7aab 100644
 --- a/net/netfilter/Kconfig
 +++ b/net/netfilter/Kconfig
-@@ -118,6 +118,14 @@ config NF_CONNTRACK_EVENTS
- 
- 	  If unsure, say `N'.
+@@ -147,6 +147,14 @@ config NF_CONNTRACK_RTCACHE
+ 	  To compile it as a module, choose M here.  If unsure, say N.
+ 	  The module will be called nf_conntrack_rtcache.
  
 +config NF_CONNTRACK_CHAIN_EVENTS
 +	bool "Register multiple callbacks to ct events"
@@ -102,11 +96,9 @@ index 63073be..08d7aab 100644
  config NF_CONNTRACK_TIMEOUT
  	bool  'Connection tracking timeout'
  	depends on NETFILTER_ADVANCED
-diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c
-index 6bd1508..9b81c7c 100644
 --- a/net/netfilter/nf_conntrack_core.c
 +++ b/net/netfilter/nf_conntrack_core.c
-@@ -2167,6 +2167,10 @@ int nf_conntrack_init_net(struct net *ne
+@@ -2447,6 +2447,10 @@ int nf_conntrack_init_net(struct net *ne
  	ret = nf_conntrack_proto_pernet_init(net);
  	if (ret < 0)
  		goto err_proto;
@@ -117,11 +109,9 @@ index 6bd1508..9b81c7c 100644
  	return 0;
  
  err_proto:
-diff --git a/net/netfilter/nf_conntrack_ecache.c b/net/netfilter/nf_conntrack_ecache.c
-index da9df2d..e0e2a8f 100644
 --- a/net/netfilter/nf_conntrack_ecache.c
 +++ b/net/netfilter/nf_conntrack_ecache.c
-@@ -18,6 +18,9 @@
+@@ -20,6 +20,9 @@
  #include <linux/stddef.h>
  #include <linux/err.h>
  #include <linux/percpu.h>
@@ -131,7 +121,7 @@ index da9df2d..e0e2a8f 100644
  #include <linux/kernel.h>
  #include <linux/netdevice.h>
  #include <linux/slab.h>
-@@ -117,6 +120,38 @@ static void ecache_work(struct work_stru
+@@ -119,6 +122,38 @@ static void ecache_work(struct work_stru
  		schedule_delayed_work(&ctnet->ecache_dwork, delay);
  }
  
@@ -170,7 +160,7 @@ index da9df2d..e0e2a8f 100644
  int nf_conntrack_eventmask_report(unsigned int eventmask, struct nf_conn *ct,
  				  u32 portid, int report)
  {
-@@ -171,10 +206,52 @@ out_unlock:
+@@ -173,10 +208,52 @@ out_unlock:
  	rcu_read_unlock();
  	return ret;
  }
@@ -223,7 +213,7 @@ index da9df2d..e0e2a8f 100644
  void nf_ct_deliver_cached_events(struct nf_conn *ct)
  {
  	struct net *net = nf_ct_net(ct);
-@@ -225,6 +302,7 @@ void nf_ct_deliver_cached_events(struct
+@@ -227,6 +304,7 @@ void nf_ct_deliver_cached_events(struct
  out_unlock:
  	rcu_read_unlock();
  }
@@ -231,7 +221,7 @@ index da9df2d..e0e2a8f 100644
  EXPORT_SYMBOL_GPL(nf_ct_deliver_cached_events);
  
  void nf_ct_expect_event_report(enum ip_conntrack_expect_events event,
-@@ -257,6 +335,12 @@ out_unlock:
+@@ -259,6 +337,12 @@ out_unlock:
  	rcu_read_unlock();
  }
  
@@ -244,7 +234,7 @@ index da9df2d..e0e2a8f 100644
  int nf_conntrack_register_notifier(struct net *net,
  				   struct nf_ct_event_notifier *new)
  {
-@@ -277,8 +361,15 @@ out_unlock:
+@@ -279,8 +363,15 @@ out_unlock:
  	mutex_unlock(&nf_ct_ecache_mutex);
  	return ret;
  }
@@ -260,7 +250,7 @@ index da9df2d..e0e2a8f 100644
  void nf_conntrack_unregister_notifier(struct net *net,
  				      struct nf_ct_event_notifier *new)
  {
-@@ -292,6 +383,7 @@ void nf_conntrack_unregister_notifier(st
+@@ -294,6 +385,7 @@ void nf_conntrack_unregister_notifier(st
  	mutex_unlock(&nf_ct_ecache_mutex);
  	/* synchronize_rcu() is called from ctnetlink_exit. */
  }
@@ -268,8 +258,6 @@ index da9df2d..e0e2a8f 100644
  EXPORT_SYMBOL_GPL(nf_conntrack_unregister_notifier);
  
  int nf_ct_expect_register_notifier(struct net *net,
-diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c
-index 04111c1..8c741f7 100644
 --- a/net/netfilter/nf_conntrack_netlink.c
 +++ b/net/netfilter/nf_conntrack_netlink.c
 @@ -28,6 +28,11 @@
@@ -282,9 +270,9 @@ index 04111c1..8c741f7 100644
 +#endif
 +
  #include <linux/slab.h>
+ #include <linux/siphash.h>
  
- #include <linux/netfilter.h>
-@@ -618,14 +623,22 @@ static size_t ctnetlink_nlmsg_size(const
+@@ -678,14 +683,22 @@ static size_t ctnetlink_nlmsg_size(const
  	       ;
  }
  
@@ -307,7 +295,7 @@ index 04111c1..8c741f7 100644
  	struct nf_conn *ct = item->ct;
  	struct sk_buff *skb;
  	unsigned int type;
-@@ -3290,9 +3303,15 @@ static int ctnetlink_stat_exp_cpu(struct
+@@ -3479,9 +3492,15 @@ static int ctnetlink_stat_exp_cpu(struct
  }
  
  #ifdef CONFIG_NF_CONNTRACK_EVENTS

target/linux/generic/hack-4.19/999-net-patch-linux-kernel-to-support-shortcut-fe.patch

@@ -1,7 +1,7 @@
---- a/include/linux/skbuff.h	2019-01-16 20:16:08.325745306 +0800
-+++ b/include/linux/skbuff.h	2019-01-16 20:31:47.288028493 +0800
-@@ -783,6 +783,9 @@ struct sk_buff {
- 	__u8			tc_from_ingress:1;
+--- a/include/linux/skbuff.h
++++ b/include/linux/skbuff.h
+@@ -813,6 +813,9 @@ struct sk_buff {
+ 	__u8			decrypted:1;
  #endif
  	__u8			gro_skip:1;
 +#ifdef CONFIG_SHORTCUT_FE
@@ -10,9 +10,9 @@
  
  #ifdef CONFIG_NET_SCHED
  	__u16			tc_index;	/* traffic control index */
---- a/include/linux/if_bridge.h	2019-01-16 20:51:47.871445535 +0800
-+++ b/include/linux/if_bridge.h	2019-01-16 20:52:26.220269649 +0800
-@@ -54,6 +54,8 @@ struct br_ip_list {
+--- a/include/linux/if_bridge.h
++++ b/include/linux/if_bridge.h
+@@ -55,6 +55,8 @@ struct br_ip_list {
  #define BR_DEFAULT_AGEING_TIME	(300 * HZ)
  
  extern void brioctl_set(int (*ioctl_hook)(struct net *, unsigned int, void __user *));
@@ -23,9 +23,9 @@
  extern br_should_route_hook_t __rcu *br_should_route_hook;
 --- a/include/linux/timer.h
 +++ b/include/linux/timer.h
-@@ -20,6 +20,9 @@ struct timer_list {
- 	void			(*function)(unsigned long);
- 	unsigned long		data;
+@@ -17,6 +17,9 @@ struct timer_list {
+ 	unsigned long		expires;
+ 	void			(*function)(struct timer_list *);
  	u32			flags;
 +#ifdef CONFIG_SHORTCUT_FE
 +	unsigned long		cust_data;
@@ -33,28 +33,27 @@
  
  #ifdef CONFIG_LOCKDEP
  	struct lockdep_map	lockdep_map;
---- a/net/Kconfig	2019-01-16 20:36:30.266465286 +0800
-+++ b/net/Kconfig	2019-01-16 20:36:41.980609067 +0800
-@@ -463,3 +463,6 @@ config HAVE_CBPF_JIT
+--- a/net/Kconfig
++++ b/net/Kconfig
+@@ -467,3 +467,6 @@ config HAVE_CBPF_JIT
  # Extended BPF JIT (eBPF)
  config HAVE_EBPF_JIT
  	bool
 +
 +config SHORTCUT_FE
 +	bool "Enables kernel network stack path for Shortcut  Forwarding Engine
---- a/net/core/dev.c	2019-01-16 20:38:37.274933833 +0800
-+++ b/net/core/dev.c	2019-01-16 20:44:07.773594898 +0800
-@@ -3256,8 +3256,17 @@ static int xmit_one(struct sk_buff *skb, struct net_device *dev,
- 		!(skb->imq_flags & IMQ_F_ENQUEUE))
+--- a/net/core/dev.c
++++ b/net/core/dev.c
+@@ -3257,7 +3257,16 @@ static int xmit_one(struct sk_buff *skb,
  #else
  	if (!list_empty(&ptype_all) || !list_empty(&dev->ptype_all))
-+#endif
+ #endif
 +#ifdef CONFIG_SHORTCUT_FE
 +	/* If this skb has been fast forwarded then we don't want it to
 +	 * go to any taps (by definition we're trying to bypass them).
 +	 */
 +	if (!skb->fast_forwarded) {
- #endif
++#endif
  		dev_queue_xmit_nit(skb, dev);
 +#ifdef CONFIG_SHORTCUT_FE
 +	}
@@ -62,7 +61,7 @@
  
  #ifdef CONFIG_ETHERNET_PACKET_MANGLE
  	if (!dev->eth_mangle_tx ||
-@@ -4315,6 +4324,11 @@ void netdev_rx_handler_unregister(struct
+@@ -4753,6 +4762,11 @@ void netdev_rx_handler_unregister(struct
  }
  EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister);
  
@@ -74,7 +73,7 @@
  /*
   * Limit the use of PFMEMALLOC reserves to those protocols that implement
   * the special handling of PFMEMALLOC skbs.
-@@ -4362,6 +4376,9 @@ static int __netif_receive_skb_core(stru
+@@ -4802,6 +4816,9 @@ static int __netif_receive_skb_core(stru
  	bool deliver_exact = false;
  	int ret = NET_RX_DROP;
  	__be16 type;
@@ -84,7 +83,7 @@
  
  	net_timestamp_check(!netdev_tstamp_prequeue, skb);
  
-@@ -4388,6 +4405,16 @@ another_round:
+@@ -4842,6 +4859,16 @@ another_round:
  			goto out;
  	}
  
@@ -101,9 +100,9 @@
  	if (skb_skip_tc_classify(skb))
  		goto skip_classify;
  
---- a/net/netfilter/nf_conntrack_proto_tcp.c	2019-01-16 20:47:40.886993297 +0800
-+++ b/net/netfilter/nf_conntrack_proto_tcp.c	2019-01-16 20:48:57.700570104 +0800
-@@ -35,11 +35,17 @@
+--- a/net/netfilter/nf_conntrack_proto_tcp.c
++++ b/net/netfilter/nf_conntrack_proto_tcp.c
+@@ -36,11 +36,17 @@
  
  /* Do not check the TCP window for incoming packets  */
  static int nf_ct_tcp_no_window_check __read_mostly = 1;
@@ -121,11 +120,11 @@
  
  /* If it is set to zero, we disable picking up already established
     connections. */
---- a/net/bridge/br_if.c	2019-01-16 20:54:51.919367044 +0800
-+++ b/net/bridge/br_if.c	2019-01-16 20:55:53.812401263 +0800
-@@ -653,3 +653,26 @@ void br_port_flags_change(struct net_bri
- 	if (mask & BR_AUTO_MASK)
- 		nbp_update_port_count(br);
+--- a/net/bridge/br_if.c
++++ b/net/bridge/br_if.c
+@@ -741,3 +741,26 @@ void br_port_flags_change(struct net_bri
+ 	if (mask & BR_NEIGH_SUPPRESS)
+ 		br_recalculate_neigh_suppress_enabled(br);
  }
 +
 +/* Update bridge statistics for bridge packets processed by offload engines */
@@ -150,9 +149,9 @@
 +	u64_stats_update_end(&stats->syncp);
 +}
 +EXPORT_SYMBOL_GPL(br_dev_update_stats);
---- a/net/netfilter/Kconfig	2019-01-16 21:07:34.543460920 +0800
-+++ b/net/netfilter/Kconfig	2019-01-16 21:08:14.739465937 +0800
-@@ -146,6 +146,14 @@ config NF_CONNTRACK_TIMEOUT
+--- a/net/netfilter/Kconfig
++++ b/net/netfilter/Kconfig
+@@ -165,6 +165,14 @@ config NF_CONNTRACK_TIMEOUT
  
  	  If unsure, say `N'.
  
@@ -167,9 +166,9 @@
  config NF_CONNTRACK_TIMESTAMP
  	bool  'Connection tracking timestamping'
  	depends on NETFILTER_ADVANCED
---- a/net/netfilter/nf_conntrack_ecache.c	2019-01-16 21:12:22.183462975 +0800
-+++ b/net/netfilter/nf_conntrack_ecache.c	2019-01-16 21:26:10.379462031 +0800
-@@ -122,13 +125,17 @@ int nf_conntrack_eventmask_report(unsign
+--- a/net/netfilter/nf_conntrack_ecache.c
++++ b/net/netfilter/nf_conntrack_ecache.c
+@@ -159,13 +159,17 @@ int nf_conntrack_eventmask_report(unsign
  {
  	int ret = 0;
  	struct net *net = nf_ct_net(ct);
@@ -187,7 +186,7 @@
  
  	e = nf_ct_ecache_find(ct);
  	if (!e)
-@@ -146,7 +153,12 @@ int nf_conntrack_eventmask_report(unsign
+@@ -183,7 +187,12 @@ int nf_conntrack_eventmask_report(unsign
  		if (!((eventmask | missed) & e->ctmask))
  			goto out_unlock;
  
@@ -200,7 +199,7 @@
  		if (unlikely(ret < 0 || missed)) {
  			spin_lock_bh(&ct->lock);
  			if (ret < 0) {
-@@ -179,15 +191,19 @@ void nf_ct_deliver_cached_events(struct
+@@ -258,15 +267,19 @@ void nf_ct_deliver_cached_events(struct
  {
  	struct net *net = nf_ct_net(ct);
  	unsigned long events, missed;
@@ -220,7 +219,7 @@
  
  	e = nf_ct_ecache_find(ct);
  	if (e == NULL)
-@@ -210,7 +226,13 @@ void nf_ct_deliver_cached_events(struct
+@@ -289,7 +302,13 @@ void nf_ct_deliver_cached_events(struct
  	item.portid = 0;
  	item.report = 0;
  

target/linux/generic/pending-4.14/130-add-linux-spidev-compatible-si3210.patch

@@ -8,7 +8,7 @@ Signed-off-by: Giuseppe Lippolis <giu.lippolis@gmail.com>
 
 --- a/drivers/spi/spidev.c
 +++ b/drivers/spi/spidev.c
-@@ -672,6 +672,7 @@ static const struct of_device_id spidev_
+@@ -677,6 +677,7 @@ static const struct of_device_id spidev_
  	{ .compatible = "lineartechnology,ltc2488" },
  	{ .compatible = "ge,achc" },
  	{ .compatible = "semtech,sx1301" },

target/linux/generic/pending-4.14/630-packet_socket_type.patch

@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #define PACKET_FANOUT_LB		1
 --- a/net/packet/af_packet.c
 +++ b/net/packet/af_packet.c
-@@ -1836,6 +1836,7 @@ static int packet_rcv_spkt(struct sk_buf
+@@ -1838,6 +1838,7 @@ static int packet_rcv_spkt(struct sk_buf
  {
  	struct sock *sk;
  	struct sockaddr_pkt *spkt;
@@ -38,7 +38,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	/*
  	 *	When we registered the protocol we saved the socket in the data
-@@ -1843,6 +1844,7 @@ static int packet_rcv_spkt(struct sk_buf
+@@ -1845,6 +1846,7 @@ static int packet_rcv_spkt(struct sk_buf
  	 */
  
  	sk = pt->af_packet_priv;
@@ -46,7 +46,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	/*
  	 *	Yank back the headers [hope the device set this
-@@ -1855,7 +1857,7 @@ static int packet_rcv_spkt(struct sk_buf
+@@ -1857,7 +1859,7 @@ static int packet_rcv_spkt(struct sk_buf
  	 *	so that this procedure is noop.
  	 */
  
@@ -55,7 +55,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		goto out;
  
  	if (!net_eq(dev_net(dev), sock_net(sk)))
-@@ -2082,12 +2084,12 @@ static int packet_rcv(struct sk_buff *sk
+@@ -2084,12 +2086,12 @@ static int packet_rcv(struct sk_buff *sk
  	unsigned int snaplen, res;
  	bool is_drop_n_account = false;
  
@@ -71,7 +71,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (!net_eq(dev_net(dev), sock_net(sk)))
  		goto drop;
  
-@@ -2214,12 +2216,12 @@ static int tpacket_rcv(struct sk_buff *s
+@@ -2216,12 +2218,12 @@ static int tpacket_rcv(struct sk_buff *s
  	BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32);
  	BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48);
  
@@ -87,7 +87,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (!net_eq(dev_net(dev), sock_net(sk)))
  		goto drop;
  
-@@ -3313,6 +3315,7 @@ static int packet_create(struct net *net
+@@ -3318,6 +3320,7 @@ static int packet_create(struct net *net
  	mutex_init(&po->pg_vec_lock);
  	po->rollover = NULL;
  	po->prot_hook.func = packet_rcv;
@@ -95,7 +95,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	if (sock->type == SOCK_PACKET)
  		po->prot_hook.func = packet_rcv_spkt;
-@@ -3935,6 +3938,16 @@ packet_setsockopt(struct socket *sock, i
+@@ -3940,6 +3943,16 @@ packet_setsockopt(struct socket *sock, i
  		po->xmit = val ? packet_direct_xmit : dev_queue_xmit;
  		return 0;
  	}
@@ -112,7 +112,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	default:
  		return -ENOPROTOOPT;
  	}
-@@ -3987,6 +4000,13 @@ static int packet_getsockopt(struct sock
+@@ -3992,6 +4005,13 @@ static int packet_getsockopt(struct sock
  	case PACKET_VNET_HDR:
  		val = po->has_vnet_hdr;
  		break;

target/linux/ipq40xx/config-4.14

@@ -117,11 +117,26 @@ CONFIG_CRYPTO_AEAD=y
 CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_AES_ARM=y
 CONFIG_CRYPTO_AES_ARM_BS=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
 CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_QCE=y
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
+CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
+CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
+CONFIG_CRYPTO_DEV_QCOM_RNG=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_GF128MUL=y
 # CONFIG_CRYPTO_GHASH_ARM_CE is not set
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
 CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
 CONFIG_CRYPTO_JITTERENTROPY=y
 CONFIG_CRYPTO_LZO=y
 CONFIG_CRYPTO_MANAGER=y
@@ -130,12 +145,15 @@ CONFIG_CRYPTO_NULL=y
 CONFIG_CRYPTO_NULL2=y
 CONFIG_CRYPTO_RNG=y
 CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
 # CONFIG_CRYPTO_SHA1_ARM_CE is not set
 # CONFIG_CRYPTO_SHA1_ARM_NEON is not set
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA256_ARM=y
 CONFIG_CRYPTO_SIMD=y
 CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_XTS=y
 CONFIG_DCACHE_WORD_ACCESS=y
 CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
 # CONFIG_DEBUG_UART_8250 is not set

target/linux/ipq40xx/config-4.19

@@ -118,24 +118,43 @@ CONFIG_CRYPTO_AEAD=y
 CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_AES_ARM=y
 CONFIG_CRYPTO_AES_ARM_BS=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
 CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_QCE=y
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
+CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
+CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
 CONFIG_CRYPTO_DEV_QCOM_RNG=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_GF128MUL=y
 # CONFIG_CRYPTO_GHASH_ARM_CE is not set
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
 CONFIG_CRYPTO_LZO=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL=y
 CONFIG_CRYPTO_NULL2=y
 CONFIG_CRYPTO_RNG=y
 CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
 # CONFIG_CRYPTO_SHA1_ARM_CE is not set
 # CONFIG_CRYPTO_SHA1_ARM_NEON is not set
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA256_ARM=y
 CONFIG_CRYPTO_SIMD=y
 CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_XTS=y
 CONFIG_DCACHE_WORD_ACCESS=y
 CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
 # CONFIG_DEBUG_USER is not set
@@ -255,6 +274,7 @@ CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_DOMAIN_HIERARCHY=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_WORK=y
+CONFIG_LEDS_LP5523=y
 CONFIG_LEDS_LP5562=y
 CONFIG_LEDS_LP55XX_COMMON=y
 CONFIG_LIBFDT=y

target/linux/ipq40xx/patches-4.14/050-0002-mtd-nand-qcom-add-command-elements-in-BAM-transactio.patch

@@ -57,7 +57,7 @@ Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
  	u32 cmd_sgl_pos;
  	u32 cmd_sgl_start;
  	u32 tx_sgl_pos;
-@@ -462,7 +472,8 @@ alloc_bam_transaction(struct qcom_nand_c
+@@ -464,7 +474,8 @@ alloc_bam_transaction(struct qcom_nand_c
  
  	bam_txn_size =
  		sizeof(*bam_txn) + num_cw *
@@ -67,7 +67,7 @@ Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
  		(sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
  
  	bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
-@@ -472,6 +483,10 @@ alloc_bam_transaction(struct qcom_nand_c
+@@ -474,6 +485,10 @@ alloc_bam_transaction(struct qcom_nand_c
  	bam_txn = bam_txn_buf;
  	bam_txn_buf += sizeof(*bam_txn);
  
@@ -78,7 +78,7 @@ Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
  	bam_txn->cmd_sgl = bam_txn_buf;
  	bam_txn_buf +=
  		sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
-@@ -489,6 +504,8 @@ static void clear_bam_transaction(struct
+@@ -491,6 +506,8 @@ static void clear_bam_transaction(struct
  	if (!nandc->props->is_bam)
  		return;
  

target/linux/ipq40xx/patches-4.14/050-0003-mtd-nand-qcom-support-for-command-descriptor-formati.patch

@@ -51,7 +51,7 @@ Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
  	dma_addr_t base_dma;
  
  	struct clk *core_clk;
-@@ -751,6 +761,66 @@ static int prepare_bam_async_desc(struct
+@@ -753,6 +763,66 @@ static int prepare_bam_async_desc(struct
  }
  
  /*
@@ -118,7 +118,7 @@ Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
   * Prepares the data descriptor for BAM DMA which will be used for NAND
   * data reads and writes.
   */
-@@ -868,19 +938,22 @@ static int read_reg_dma(struct qcom_nand
+@@ -870,19 +940,22 @@ static int read_reg_dma(struct qcom_nand
  {
  	bool flow_control = false;
  	void *vaddr;
@@ -148,7 +148,7 @@ Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
  }
  
  /*
-@@ -897,13 +970,9 @@ static int write_reg_dma(struct qcom_nan
+@@ -899,13 +972,9 @@ static int write_reg_dma(struct qcom_nan
  	bool flow_control = false;
  	struct nandc_regs *regs = nandc->regs;
  	void *vaddr;
@@ -162,7 +162,7 @@ Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
  	if (first == NAND_ERASED_CW_DETECT_CFG) {
  		if (flags & NAND_ERASED_CW_SET)
  			vaddr = &regs->erased_cw_detect_cfg_set;
-@@ -920,10 +989,15 @@ static int write_reg_dma(struct qcom_nan
+@@ -922,10 +991,15 @@ static int write_reg_dma(struct qcom_nan
  	if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
  		first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
  
@@ -181,7 +181,7 @@ Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
  }
  
  /*
-@@ -1187,7 +1261,8 @@ static int submit_descs(struct qcom_nand
+@@ -1189,7 +1263,8 @@ static int submit_descs(struct qcom_nand
  		}
  
  		if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
@@ -191,7 +191,7 @@ Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
  			if (r)
  				return r;
  		}
-@@ -2725,6 +2800,7 @@ static int qcom_nandc_probe(struct platf
+@@ -2728,6 +2803,7 @@ static int qcom_nandc_probe(struct platf
  	if (IS_ERR(nandc->base))
  		return PTR_ERR(nandc->base);
  

target/linux/ipq40xx/patches-4.14/050-0004-mtd-nand-provide-several-helpers-to-do-common-NAND-o.patch

@@ -1502,7 +1502,7 @@ Date:   Thu Nov 30 18:01:29 2017 +0100
  		}
 --- a/drivers/mtd/nand/qcom_nandc.c
 +++ b/drivers/mtd/nand/qcom_nandc.c
-@@ -1990,7 +1990,7 @@ static int qcom_nandc_write_oob(struct m
+@@ -1992,7 +1992,7 @@ static int qcom_nandc_write_oob(struct m
  	struct nand_ecc_ctrl *ecc = &chip->ecc;
  	u8 *oob = chip->oob_poi;
  	int data_size, oob_size;
@@ -1511,7 +1511,7 @@ Date:   Thu Nov 30 18:01:29 2017 +0100
  
  	host->use_ecc = true;
  
-@@ -2027,11 +2027,7 @@ static int qcom_nandc_write_oob(struct m
+@@ -2029,11 +2029,7 @@ static int qcom_nandc_write_oob(struct m
  		return -EIO;
  	}
  
@@ -1524,7 +1524,7 @@ Date:   Thu Nov 30 18:01:29 2017 +0100
  }
  
  static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs)
-@@ -2081,7 +2077,7 @@ static int qcom_nandc_block_markbad(stru
+@@ -2083,7 +2079,7 @@ static int qcom_nandc_block_markbad(stru
  	struct qcom_nand_host *host = to_qcom_nand_host(chip);
  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  	struct nand_ecc_ctrl *ecc = &chip->ecc;
@@ -1533,7 +1533,7 @@ Date:   Thu Nov 30 18:01:29 2017 +0100
  
  	clear_read_regs(nandc);
  	clear_bam_transaction(nandc);
-@@ -2114,11 +2110,7 @@ static int qcom_nandc_block_markbad(stru
+@@ -2116,11 +2112,7 @@ static int qcom_nandc_block_markbad(stru
  		return -EIO;
  	}
  

target/linux/ipq40xx/patches-4.14/050-0005-mtd-nand-force-drivers-to-explicitly-send-READ-PROG-.patch

@@ -39,7 +39,7 @@ Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 --- a/drivers/mtd/nand/qcom_nandc.c
 +++ b/drivers/mtd/nand/qcom_nandc.c
-@@ -1725,6 +1725,7 @@ static int qcom_nandc_read_page(struct m
+@@ -1727,6 +1727,7 @@ static int qcom_nandc_read_page(struct m
  	u8 *data_buf, *oob_buf = NULL;
  	int ret;
  
@@ -47,7 +47,7 @@ Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
  	data_buf = buf;
  	oob_buf = oob_required ? chip->oob_poi : NULL;
  
-@@ -1750,6 +1751,7 @@ static int qcom_nandc_read_page_raw(stru
+@@ -1752,6 +1753,7 @@ static int qcom_nandc_read_page_raw(stru
  	int i, ret;
  	int read_loc;
  
@@ -55,7 +55,7 @@ Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
  	data_buf = buf;
  	oob_buf = chip->oob_poi;
  
-@@ -1850,6 +1852,8 @@ static int qcom_nandc_write_page(struct
+@@ -1852,6 +1854,8 @@ static int qcom_nandc_write_page(struct
  	u8 *data_buf, *oob_buf;
  	int i, ret;
  
@@ -64,7 +64,7 @@ Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
  	clear_read_regs(nandc);
  	clear_bam_transaction(nandc);
  
-@@ -1902,6 +1906,9 @@ static int qcom_nandc_write_page(struct
+@@ -1904,6 +1908,9 @@ static int qcom_nandc_write_page(struct
  
  	free_descs(nandc);
  
@@ -74,7 +74,7 @@ Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
  	return ret;
  }
  
-@@ -1916,6 +1923,7 @@ static int qcom_nandc_write_page_raw(str
+@@ -1918,6 +1925,7 @@ static int qcom_nandc_write_page_raw(str
  	u8 *data_buf, *oob_buf;
  	int i, ret;
  
@@ -82,7 +82,7 @@ Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
  	clear_read_regs(nandc);
  	clear_bam_transaction(nandc);
  
-@@ -1970,6 +1978,9 @@ static int qcom_nandc_write_page_raw(str
+@@ -1972,6 +1980,9 @@ static int qcom_nandc_write_page_raw(str
  
  	free_descs(nandc);
  

target/linux/ipq40xx/patches-4.14/052-crypto-qce-switch-to-skcipher-API.patch

@@ -0,0 +1,979 @@
+From f441873642eebf20566c18d2966a8cd4b433ec1c Mon Sep 17 00:00:00 2001
+From: Ard Biesheuvel <ardb@kernel.org>
+Date: Tue, 5 Nov 2019 14:28:17 +0100
+Subject: [PATCH] crypto: qce - switch to skcipher API
+
+Commit 7a7ffe65c8c5 ("crypto: skcipher - Add top-level skcipher interface")
+dated 20 august 2015 introduced the new skcipher API which is supposed to
+replace both blkcipher and ablkcipher. While all consumers of the API have
+been converted long ago, some producers of the ablkcipher remain, forcing
+us to keep the ablkcipher support routines alive, along with the matching
+code to expose [a]blkciphers via the skcipher API.
+
+So switch this driver to the skcipher API, allowing us to finally drop the
+blkcipher code in the near future.
+
+Reviewed-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
+Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
+Backported-to-4.19-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
+
+--- a/drivers/crypto/qce/Makefile
++++ b/drivers/crypto/qce/Makefile
+@@ -4,4 +4,4 @@ qcrypto-objs := core.o \
+ 		common.o \
+ 		dma.o \
+ 		sha.o \
+-		ablkcipher.o
++		skcipher.o
+--- a/drivers/crypto/qce/cipher.h
++++ b/drivers/crypto/qce/cipher.h
+@@ -53,12 +53,12 @@ struct qce_cipher_reqctx {
+ 	unsigned int cryptlen;
+ };
+ 
+-static inline struct qce_alg_template *to_cipher_tmpl(struct crypto_tfm *tfm)
++static inline struct qce_alg_template *to_cipher_tmpl(struct crypto_skcipher *tfm)
+ {
+-	struct crypto_alg *alg = tfm->__crt_alg;
+-	return container_of(alg, struct qce_alg_template, alg.crypto);
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	return container_of(alg, struct qce_alg_template, alg.skcipher);
+ }
+ 
+-extern const struct qce_algo_ops ablkcipher_ops;
++extern const struct qce_algo_ops skcipher_ops;
+ 
+ #endif /* _CIPHER_H_ */
+--- a/drivers/crypto/qce/common.c
++++ b/drivers/crypto/qce/common.c
+@@ -312,13 +312,13 @@ go_proc:
+ 	return 0;
+ }
+ 
+-static int qce_setup_regs_ablkcipher(struct crypto_async_request *async_req,
++static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
+ 				     u32 totallen, u32 offset)
+ {
+-	struct ablkcipher_request *req = ablkcipher_request_cast(async_req);
+-	struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req);
++	struct skcipher_request *req = skcipher_request_cast(async_req);
++	struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
+ 	struct qce_cipher_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
+-	struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm);
++	struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req));
+ 	struct qce_device *qce = tmpl->qce;
+ 	__be32 enckey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(__be32)] = {0};
+ 	__be32 enciv[QCE_MAX_IV_SIZE / sizeof(__be32)] = {0};
+@@ -397,8 +397,8 @@ int qce_start(struct crypto_async_reques
+ 	      u32 offset)
+ {
+ 	switch (type) {
+-	case CRYPTO_ALG_TYPE_ABLKCIPHER:
+-		return qce_setup_regs_ablkcipher(async_req, totallen, offset);
++	case CRYPTO_ALG_TYPE_SKCIPHER:
++		return qce_setup_regs_skcipher(async_req, totallen, offset);
+ 	case CRYPTO_ALG_TYPE_AHASH:
+ 		return qce_setup_regs_ahash(async_req, totallen, offset);
+ 	default:
+--- a/drivers/crypto/qce/common.h
++++ b/drivers/crypto/qce/common.h
+@@ -18,6 +18,7 @@
+ #include <linux/types.h>
+ #include <crypto/aes.h>
+ #include <crypto/hash.h>
++#include <crypto/internal/skcipher.h>
+ 
+ /* key size in bytes */
+ #define QCE_SHA_HMAC_KEY_SIZE		64
+@@ -87,7 +88,7 @@ struct qce_alg_template {
+ 	unsigned long alg_flags;
+ 	const u32 *std_iv;
+ 	union {
+-		struct crypto_alg crypto;
++		struct skcipher_alg skcipher;
+ 		struct ahash_alg ahash;
+ 	} alg;
+ 	struct qce_device *qce;
+--- a/drivers/crypto/qce/core.c
++++ b/drivers/crypto/qce/core.c
+@@ -29,7 +29,7 @@
+ #define QCE_QUEUE_LENGTH	1
+ 
+ static const struct qce_algo_ops *qce_ops[] = {
+-	&ablkcipher_ops,
++	&skcipher_ops,
+ 	&ahash_ops,
+ };
+ 
+--- a/drivers/crypto/qce/ablkcipher.c
++++ /dev/null
+@@ -1,434 +0,0 @@
+-/*
+- * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 and
+- * only version 2 as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- */
+-
+-#include <linux/device.h>
+-#include <linux/interrupt.h>
+-#include <linux/types.h>
+-#include <crypto/aes.h>
+-#include <crypto/des.h>
+-#include <crypto/internal/skcipher.h>
+-
+-#include "cipher.h"
+-
+-static LIST_HEAD(ablkcipher_algs);
+-
+-static void qce_ablkcipher_done(void *data)
+-{
+-	struct crypto_async_request *async_req = data;
+-	struct ablkcipher_request *req = ablkcipher_request_cast(async_req);
+-	struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req);
+-	struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm);
+-	struct qce_device *qce = tmpl->qce;
+-	enum dma_data_direction dir_src, dir_dst;
+-	u32 status;
+-	int error;
+-	bool diff_dst;
+-
+-	diff_dst = (req->src != req->dst) ? true : false;
+-	dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;
+-	dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;
+-
+-	error = qce_dma_terminate_all(&qce->dma);
+-	if (error)
+-		dev_dbg(qce->dev, "ablkcipher dma termination error (%d)\n",
+-			error);
+-
+-	if (diff_dst)
+-		dma_unmap_sg(qce->dev, rctx->src_sg, rctx->src_nents, dir_src);
+-	dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
+-
+-	sg_free_table(&rctx->dst_tbl);
+-
+-	error = qce_check_status(qce, &status);
+-	if (error < 0)
+-		dev_dbg(qce->dev, "ablkcipher operation error (%x)\n", status);
+-
+-	qce->async_req_done(tmpl->qce, error);
+-}
+-
+-static int
+-qce_ablkcipher_async_req_handle(struct crypto_async_request *async_req)
+-{
+-	struct ablkcipher_request *req = ablkcipher_request_cast(async_req);
+-	struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req);
+-	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+-	struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm);
+-	struct qce_device *qce = tmpl->qce;
+-	enum dma_data_direction dir_src, dir_dst;
+-	struct scatterlist *sg;
+-	bool diff_dst;
+-	gfp_t gfp;
+-	int ret;
+-
+-	rctx->iv = req->info;
+-	rctx->ivsize = crypto_ablkcipher_ivsize(ablkcipher);
+-	rctx->cryptlen = req->nbytes;
+-
+-	diff_dst = (req->src != req->dst) ? true : false;
+-	dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;
+-	dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;
+-
+-	rctx->src_nents = sg_nents_for_len(req->src, req->nbytes);
+-	if (diff_dst)
+-		rctx->dst_nents = sg_nents_for_len(req->dst, req->nbytes);
+-	else
+-		rctx->dst_nents = rctx->src_nents;
+-	if (rctx->src_nents < 0) {
+-		dev_err(qce->dev, "Invalid numbers of src SG.\n");
+-		return rctx->src_nents;
+-	}
+-	if (rctx->dst_nents < 0) {
+-		dev_err(qce->dev, "Invalid numbers of dst SG.\n");
+-		return -rctx->dst_nents;
+-	}
+-
+-	rctx->dst_nents += 1;
+-
+-	gfp = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
+-						GFP_KERNEL : GFP_ATOMIC;
+-
+-	ret = sg_alloc_table(&rctx->dst_tbl, rctx->dst_nents, gfp);
+-	if (ret)
+-		return ret;
+-
+-	sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
+-
+-	sg = qce_sgtable_add(&rctx->dst_tbl, req->dst);
+-	if (IS_ERR(sg)) {
+-		ret = PTR_ERR(sg);
+-		goto error_free;
+-	}
+-
+-	sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg);
+-	if (IS_ERR(sg)) {
+-		ret = PTR_ERR(sg);
+-		goto error_free;
+-	}
+-
+-	sg_mark_end(sg);
+-	rctx->dst_sg = rctx->dst_tbl.sgl;
+-
+-	ret = dma_map_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
+-	if (ret < 0)
+-		goto error_free;
+-
+-	if (diff_dst) {
+-		ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, dir_src);
+-		if (ret < 0)
+-			goto error_unmap_dst;
+-		rctx->src_sg = req->src;
+-	} else {
+-		rctx->src_sg = rctx->dst_sg;
+-	}
+-
+-	ret = qce_dma_prep_sgs(&qce->dma, rctx->src_sg, rctx->src_nents,
+-			       rctx->dst_sg, rctx->dst_nents,
+-			       qce_ablkcipher_done, async_req);
+-	if (ret)
+-		goto error_unmap_src;
+-
+-	qce_dma_issue_pending(&qce->dma);
+-
+-	ret = qce_start(async_req, tmpl->crypto_alg_type, req->nbytes, 0);
+-	if (ret)
+-		goto error_terminate;
+-
+-	return 0;
+-
+-error_terminate:
+-	qce_dma_terminate_all(&qce->dma);
+-error_unmap_src:
+-	if (diff_dst)
+-		dma_unmap_sg(qce->dev, req->src, rctx->src_nents, dir_src);
+-error_unmap_dst:
+-	dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
+-error_free:
+-	sg_free_table(&rctx->dst_tbl);
+-	return ret;
+-}
+-
+-static int qce_ablkcipher_setkey(struct crypto_ablkcipher *ablk, const u8 *key,
+-				 unsigned int keylen)
+-{
+-	struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablk);
+-	struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
+-	unsigned long flags = to_cipher_tmpl(tfm)->alg_flags;
+-	int ret;
+-
+-	if (!key || !keylen)
+-		return -EINVAL;
+-
+-	if (IS_AES(flags)) {
+-		switch (keylen) {
+-		case AES_KEYSIZE_128:
+-		case AES_KEYSIZE_256:
+-			break;
+-		default:
+-			goto fallback;
+-		}
+-	} else if (IS_DES(flags)) {
+-		u32 tmp[DES_EXPKEY_WORDS];
+-
+-		ret = des_ekey(tmp, key);
+-		if (!ret && crypto_ablkcipher_get_flags(ablk) &
+-		    CRYPTO_TFM_REQ_WEAK_KEY)
+-			goto weakkey;
+-	}
+-
+-	ctx->enc_keylen = keylen;
+-	memcpy(ctx->enc_key, key, keylen);
+-	return 0;
+-fallback:
+-	ret = crypto_skcipher_setkey(ctx->fallback, key, keylen);
+-	if (!ret)
+-		ctx->enc_keylen = keylen;
+-	return ret;
+-weakkey:
+-	crypto_ablkcipher_set_flags(ablk, CRYPTO_TFM_RES_WEAK_KEY);
+-	return -EINVAL;
+-}
+-
+-static int qce_ablkcipher_crypt(struct ablkcipher_request *req, int encrypt)
+-{
+-	struct crypto_tfm *tfm =
+-			crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req));
+-	struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
+-	struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req);
+-	struct qce_alg_template *tmpl = to_cipher_tmpl(tfm);
+-	int ret;
+-
+-	rctx->flags = tmpl->alg_flags;
+-	rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
+-
+-	if (IS_AES(rctx->flags) && ctx->enc_keylen != AES_KEYSIZE_128 &&
+-	    ctx->enc_keylen != AES_KEYSIZE_256) {
+-		SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
+-
+-		skcipher_request_set_tfm(subreq, ctx->fallback);
+-		skcipher_request_set_callback(subreq, req->base.flags,
+-					      NULL, NULL);
+-		skcipher_request_set_crypt(subreq, req->src, req->dst,
+-					   req->nbytes, req->info);
+-		ret = encrypt ? crypto_skcipher_encrypt(subreq) :
+-				crypto_skcipher_decrypt(subreq);
+-		skcipher_request_zero(subreq);
+-		return ret;
+-	}
+-
+-	return tmpl->qce->async_req_enqueue(tmpl->qce, &req->base);
+-}
+-
+-static int qce_ablkcipher_encrypt(struct ablkcipher_request *req)
+-{
+-	return qce_ablkcipher_crypt(req, 1);
+-}
+-
+-static int qce_ablkcipher_decrypt(struct ablkcipher_request *req)
+-{
+-	return qce_ablkcipher_crypt(req, 0);
+-}
+-
+-static int qce_ablkcipher_init(struct crypto_tfm *tfm)
+-{
+-	struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
+-
+-	memset(ctx, 0, sizeof(*ctx));
+-	tfm->crt_ablkcipher.reqsize = sizeof(struct qce_cipher_reqctx);
+-
+-	ctx->fallback = crypto_alloc_skcipher(crypto_tfm_alg_name(tfm), 0,
+-					      CRYPTO_ALG_ASYNC |
+-					      CRYPTO_ALG_NEED_FALLBACK);
+-	if (IS_ERR(ctx->fallback))
+-		return PTR_ERR(ctx->fallback);
+-
+-	return 0;
+-}
+-
+-static void qce_ablkcipher_exit(struct crypto_tfm *tfm)
+-{
+-	struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
+-
+-	crypto_free_skcipher(ctx->fallback);
+-}
+-
+-struct qce_ablkcipher_def {
+-	unsigned long flags;
+-	const char *name;
+-	const char *drv_name;
+-	unsigned int blocksize;
+-	unsigned int ivsize;
+-	unsigned int min_keysize;
+-	unsigned int max_keysize;
+-};
+-
+-static const struct qce_ablkcipher_def ablkcipher_def[] = {
+-	{
+-		.flags		= QCE_ALG_AES | QCE_MODE_ECB,
+-		.name		= "ecb(aes)",
+-		.drv_name	= "ecb-aes-qce",
+-		.blocksize	= AES_BLOCK_SIZE,
+-		.ivsize		= AES_BLOCK_SIZE,
+-		.min_keysize	= AES_MIN_KEY_SIZE,
+-		.max_keysize	= AES_MAX_KEY_SIZE,
+-	},
+-	{
+-		.flags		= QCE_ALG_AES | QCE_MODE_CBC,
+-		.name		= "cbc(aes)",
+-		.drv_name	= "cbc-aes-qce",
+-		.blocksize	= AES_BLOCK_SIZE,
+-		.ivsize		= AES_BLOCK_SIZE,
+-		.min_keysize	= AES_MIN_KEY_SIZE,
+-		.max_keysize	= AES_MAX_KEY_SIZE,
+-	},
+-	{
+-		.flags		= QCE_ALG_AES | QCE_MODE_CTR,
+-		.name		= "ctr(aes)",
+-		.drv_name	= "ctr-aes-qce",
+-		.blocksize	= AES_BLOCK_SIZE,
+-		.ivsize		= AES_BLOCK_SIZE,
+-		.min_keysize	= AES_MIN_KEY_SIZE,
+-		.max_keysize	= AES_MAX_KEY_SIZE,
+-	},
+-	{
+-		.flags		= QCE_ALG_AES | QCE_MODE_XTS,
+-		.name		= "xts(aes)",
+-		.drv_name	= "xts-aes-qce",
+-		.blocksize	= AES_BLOCK_SIZE,
+-		.ivsize		= AES_BLOCK_SIZE,
+-		.min_keysize	= AES_MIN_KEY_SIZE,
+-		.max_keysize	= AES_MAX_KEY_SIZE,
+-	},
+-	{
+-		.flags		= QCE_ALG_DES | QCE_MODE_ECB,
+-		.name		= "ecb(des)",
+-		.drv_name	= "ecb-des-qce",
+-		.blocksize	= DES_BLOCK_SIZE,
+-		.ivsize		= 0,
+-		.min_keysize	= DES_KEY_SIZE,
+-		.max_keysize	= DES_KEY_SIZE,
+-	},
+-	{
+-		.flags		= QCE_ALG_DES | QCE_MODE_CBC,
+-		.name		= "cbc(des)",
+-		.drv_name	= "cbc-des-qce",
+-		.blocksize	= DES_BLOCK_SIZE,
+-		.ivsize		= DES_BLOCK_SIZE,
+-		.min_keysize	= DES_KEY_SIZE,
+-		.max_keysize	= DES_KEY_SIZE,
+-	},
+-	{
+-		.flags		= QCE_ALG_3DES | QCE_MODE_ECB,
+-		.name		= "ecb(des3_ede)",
+-		.drv_name	= "ecb-3des-qce",
+-		.blocksize	= DES3_EDE_BLOCK_SIZE,
+-		.ivsize		= 0,
+-		.min_keysize	= DES3_EDE_KEY_SIZE,
+-		.max_keysize	= DES3_EDE_KEY_SIZE,
+-	},
+-	{
+-		.flags		= QCE_ALG_3DES | QCE_MODE_CBC,
+-		.name		= "cbc(des3_ede)",
+-		.drv_name	= "cbc-3des-qce",
+-		.blocksize	= DES3_EDE_BLOCK_SIZE,
+-		.ivsize		= DES3_EDE_BLOCK_SIZE,
+-		.min_keysize	= DES3_EDE_KEY_SIZE,
+-		.max_keysize	= DES3_EDE_KEY_SIZE,
+-	},
+-};
+-
+-static int qce_ablkcipher_register_one(const struct qce_ablkcipher_def *def,
+-				       struct qce_device *qce)
+-{
+-	struct qce_alg_template *tmpl;
+-	struct crypto_alg *alg;
+-	int ret;
+-
+-	tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL);
+-	if (!tmpl)
+-		return -ENOMEM;
+-
+-	alg = &tmpl->alg.crypto;
+-
+-	snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name);
+-	snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
+-		 def->drv_name);
+-
+-	alg->cra_blocksize = def->blocksize;
+-	alg->cra_ablkcipher.ivsize = def->ivsize;
+-	alg->cra_ablkcipher.min_keysize = def->min_keysize;
+-	alg->cra_ablkcipher.max_keysize = def->max_keysize;
+-	alg->cra_ablkcipher.setkey = qce_ablkcipher_setkey;
+-	alg->cra_ablkcipher.encrypt = qce_ablkcipher_encrypt;
+-	alg->cra_ablkcipher.decrypt = qce_ablkcipher_decrypt;
+-
+-	alg->cra_priority = 300;
+-	alg->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC |
+-			 CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY;
+-	alg->cra_ctxsize = sizeof(struct qce_cipher_ctx);
+-	alg->cra_alignmask = 0;
+-	alg->cra_type = &crypto_ablkcipher_type;
+-	alg->cra_module = THIS_MODULE;
+-	alg->cra_init = qce_ablkcipher_init;
+-	alg->cra_exit = qce_ablkcipher_exit;
+-	INIT_LIST_HEAD(&alg->cra_list);
+-
+-	INIT_LIST_HEAD(&tmpl->entry);
+-	tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_ABLKCIPHER;
+-	tmpl->alg_flags = def->flags;
+-	tmpl->qce = qce;
+-
+-	ret = crypto_register_alg(alg);
+-	if (ret) {
+-		kfree(tmpl);
+-		dev_err(qce->dev, "%s registration failed\n", alg->cra_name);
+-		return ret;
+-	}
+-
+-	list_add_tail(&tmpl->entry, &ablkcipher_algs);
+-	dev_dbg(qce->dev, "%s is registered\n", alg->cra_name);
+-	return 0;
+-}
+-
+-static void qce_ablkcipher_unregister(struct qce_device *qce)
+-{
+-	struct qce_alg_template *tmpl, *n;
+-
+-	list_for_each_entry_safe(tmpl, n, &ablkcipher_algs, entry) {
+-		crypto_unregister_alg(&tmpl->alg.crypto);
+-		list_del(&tmpl->entry);
+-		kfree(tmpl);
+-	}
+-}
+-
+-static int qce_ablkcipher_register(struct qce_device *qce)
+-{
+-	int ret, i;
+-
+-	for (i = 0; i < ARRAY_SIZE(ablkcipher_def); i++) {
+-		ret = qce_ablkcipher_register_one(&ablkcipher_def[i], qce);
+-		if (ret)
+-			goto err;
+-	}
+-
+-	return 0;
+-err:
+-	qce_ablkcipher_unregister(qce);
+-	return ret;
+-}
+-
+-const struct qce_algo_ops ablkcipher_ops = {
+-	.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
+-	.register_algs = qce_ablkcipher_register,
+-	.unregister_algs = qce_ablkcipher_unregister,
+-	.async_req_handle = qce_ablkcipher_async_req_handle,
+-};
+--- /dev/null
++++ b/drivers/crypto/qce/skcipher.c
+@@ -0,0 +1,432 @@
++/*
++ * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/device.h>
++#include <linux/interrupt.h>
++#include <linux/types.h>
++#include <crypto/aes.h>
++#include <crypto/des.h>
++#include <crypto/internal/skcipher.h>
++
++#include "cipher.h"
++
++static LIST_HEAD(skcipher_algs);
++
++static void qce_skcipher_done(void *data)
++{
++	struct crypto_async_request *async_req = data;
++	struct skcipher_request *req = skcipher_request_cast(async_req);
++	struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
++	struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req));
++	struct qce_device *qce = tmpl->qce;
++	enum dma_data_direction dir_src, dir_dst;
++	u32 status;
++	int error;
++	bool diff_dst;
++
++	diff_dst = (req->src != req->dst) ? true : false;
++	dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;
++	dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;
++
++	error = qce_dma_terminate_all(&qce->dma);
++	if (error)
++		dev_dbg(qce->dev, "skcipher dma termination error (%d)\n",
++			error);
++
++	if (diff_dst)
++		dma_unmap_sg(qce->dev, rctx->src_sg, rctx->src_nents, dir_src);
++	dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
++
++	sg_free_table(&rctx->dst_tbl);
++
++	error = qce_check_status(qce, &status);
++	if (error < 0)
++		dev_dbg(qce->dev, "skcipher operation error (%x)\n", status);
++
++	qce->async_req_done(tmpl->qce, error);
++}
++
++static int
++qce_skcipher_async_req_handle(struct crypto_async_request *async_req)
++{
++	struct skcipher_request *req = skcipher_request_cast(async_req);
++	struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
++	struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
++	struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req));
++	struct qce_device *qce = tmpl->qce;
++	enum dma_data_direction dir_src, dir_dst;
++	struct scatterlist *sg;
++	bool diff_dst;
++	gfp_t gfp;
++	int ret;
++
++	rctx->iv = req->iv;
++	rctx->ivsize = crypto_skcipher_ivsize(skcipher);
++	rctx->cryptlen = req->cryptlen;
++
++	diff_dst = (req->src != req->dst) ? true : false;
++	dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;
++	dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;
++
++	rctx->src_nents = sg_nents_for_len(req->src, req->cryptlen);
++	if (diff_dst)
++		rctx->dst_nents = sg_nents_for_len(req->dst, req->cryptlen);
++	else
++		rctx->dst_nents = rctx->src_nents;
++	if (rctx->src_nents < 0) {
++		dev_err(qce->dev, "Invalid numbers of src SG.\n");
++		return rctx->src_nents;
++	}
++	if (rctx->dst_nents < 0) {
++		dev_err(qce->dev, "Invalid numbers of dst SG.\n");
++		return -rctx->dst_nents;
++	}
++
++	rctx->dst_nents += 1;
++
++	gfp = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++						GFP_KERNEL : GFP_ATOMIC;
++
++	ret = sg_alloc_table(&rctx->dst_tbl, rctx->dst_nents, gfp);
++	if (ret)
++		return ret;
++
++	sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
++
++	sg = qce_sgtable_add(&rctx->dst_tbl, req->dst);
++	if (IS_ERR(sg)) {
++		ret = PTR_ERR(sg);
++		goto error_free;
++	}
++
++	sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg);
++	if (IS_ERR(sg)) {
++		ret = PTR_ERR(sg);
++		goto error_free;
++	}
++
++	sg_mark_end(sg);
++	rctx->dst_sg = rctx->dst_tbl.sgl;
++
++	ret = dma_map_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
++	if (ret < 0)
++		goto error_free;
++
++	if (diff_dst) {
++		ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, dir_src);
++		if (ret < 0)
++			goto error_unmap_dst;
++		rctx->src_sg = req->src;
++	} else {
++		rctx->src_sg = rctx->dst_sg;
++	}
++
++	ret = qce_dma_prep_sgs(&qce->dma, rctx->src_sg, rctx->src_nents,
++			       rctx->dst_sg, rctx->dst_nents,
++			       qce_skcipher_done, async_req);
++	if (ret)
++		goto error_unmap_src;
++
++	qce_dma_issue_pending(&qce->dma);
++
++	ret = qce_start(async_req, tmpl->crypto_alg_type, req->cryptlen, 0);
++	if (ret)
++		goto error_terminate;
++
++	return 0;
++
++error_terminate:
++	qce_dma_terminate_all(&qce->dma);
++error_unmap_src:
++	if (diff_dst)
++		dma_unmap_sg(qce->dev, req->src, rctx->src_nents, dir_src);
++error_unmap_dst:
++	dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
++error_free:
++	sg_free_table(&rctx->dst_tbl);
++	return ret;
++}
++
++static int qce_skcipher_setkey(struct crypto_skcipher *ablk, const u8 *key,
++				 unsigned int keylen)
++{
++	struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(ablk);
++	unsigned long flags = to_cipher_tmpl(ablk)->alg_flags;
++	int ret;
++
++	if (!key || !keylen)
++		return -EINVAL;
++
++	if (IS_AES(flags)) {
++		switch (keylen) {
++		case AES_KEYSIZE_128:
++		case AES_KEYSIZE_256:
++			break;
++		default:
++			goto fallback;
++		}
++	} else if (IS_DES(flags)) {
++		u32 tmp[DES_EXPKEY_WORDS];
++
++		ret = des_ekey(tmp, key);
++		if (!ret && crypto_skcipher_get_flags(ablk) &
++		    CRYPTO_TFM_REQ_WEAK_KEY)
++			goto weakkey;
++	}
++
++	ctx->enc_keylen = keylen;
++	memcpy(ctx->enc_key, key, keylen);
++	return 0;
++fallback:
++	ret = crypto_skcipher_setkey(ctx->fallback, key, keylen);
++	if (!ret)
++		ctx->enc_keylen = keylen;
++	return ret;
++weakkey:
++	crypto_skcipher_set_flags(ablk, CRYPTO_TFM_RES_WEAK_KEY);
++	return -EINVAL;
++}
++
++static int qce_skcipher_crypt(struct skcipher_request *req, int encrypt)
++{
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
++	struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++	struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
++	struct qce_alg_template *tmpl = to_cipher_tmpl(tfm);
++	int ret;
++
++	rctx->flags = tmpl->alg_flags;
++	rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
++
++	if (IS_AES(rctx->flags) && ctx->enc_keylen != AES_KEYSIZE_128 &&
++	    ctx->enc_keylen != AES_KEYSIZE_256) {
++		SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
++
++		skcipher_request_set_tfm(subreq, ctx->fallback);
++		skcipher_request_set_callback(subreq, req->base.flags,
++					      NULL, NULL);
++		skcipher_request_set_crypt(subreq, req->src, req->dst,
++					   req->cryptlen, req->iv);
++		ret = encrypt ? crypto_skcipher_encrypt(subreq) :
++				crypto_skcipher_decrypt(subreq);
++		skcipher_request_zero(subreq);
++		return ret;
++	}
++
++	return tmpl->qce->async_req_enqueue(tmpl->qce, &req->base);
++}
++
++static int qce_skcipher_encrypt(struct skcipher_request *req)
++{
++	return qce_skcipher_crypt(req, 1);
++}
++
++static int qce_skcipher_decrypt(struct skcipher_request *req)
++{
++	return qce_skcipher_crypt(req, 0);
++}
++
++static int qce_skcipher_init(struct crypto_skcipher *tfm)
++{
++	struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++
++	memset(ctx, 0, sizeof(*ctx));
++	crypto_skcipher_set_reqsize(tfm, sizeof(struct qce_cipher_reqctx));
++
++	ctx->fallback = crypto_alloc_skcipher(crypto_tfm_alg_name(&tfm->base),
++					      0, CRYPTO_ALG_ASYNC |
++						 CRYPTO_ALG_NEED_FALLBACK);
++	if (IS_ERR(ctx->fallback))
++		return PTR_ERR(ctx->fallback);
++
++	return 0;
++}
++
++static void qce_skcipher_exit(struct crypto_skcipher *tfm)
++{
++	struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++
++	crypto_free_skcipher(ctx->fallback);
++}
++
++struct qce_skcipher_def {
++	unsigned long flags;
++	const char *name;
++	const char *drv_name;
++	unsigned int blocksize;
++	unsigned int ivsize;
++	unsigned int min_keysize;
++	unsigned int max_keysize;
++};
++
++static const struct qce_skcipher_def skcipher_def[] = {
++	{
++		.flags		= QCE_ALG_AES | QCE_MODE_ECB,
++		.name		= "ecb(aes)",
++		.drv_name	= "ecb-aes-qce",
++		.blocksize	= AES_BLOCK_SIZE,
++		.ivsize		= AES_BLOCK_SIZE,
++		.min_keysize	= AES_MIN_KEY_SIZE,
++		.max_keysize	= AES_MAX_KEY_SIZE,
++	},
++	{
++		.flags		= QCE_ALG_AES | QCE_MODE_CBC,
++		.name		= "cbc(aes)",
++		.drv_name	= "cbc-aes-qce",
++		.blocksize	= AES_BLOCK_SIZE,
++		.ivsize		= AES_BLOCK_SIZE,
++		.min_keysize	= AES_MIN_KEY_SIZE,
++		.max_keysize	= AES_MAX_KEY_SIZE,
++	},
++	{
++		.flags		= QCE_ALG_AES | QCE_MODE_CTR,
++		.name		= "ctr(aes)",
++		.drv_name	= "ctr-aes-qce",
++		.blocksize	= AES_BLOCK_SIZE,
++		.ivsize		= AES_BLOCK_SIZE,
++		.min_keysize	= AES_MIN_KEY_SIZE,
++		.max_keysize	= AES_MAX_KEY_SIZE,
++	},
++	{
++		.flags		= QCE_ALG_AES | QCE_MODE_XTS,
++		.name		= "xts(aes)",
++		.drv_name	= "xts-aes-qce",
++		.blocksize	= AES_BLOCK_SIZE,
++		.ivsize		= AES_BLOCK_SIZE,
++		.min_keysize	= AES_MIN_KEY_SIZE,
++		.max_keysize	= AES_MAX_KEY_SIZE,
++	},
++	{
++		.flags		= QCE_ALG_DES | QCE_MODE_ECB,
++		.name		= "ecb(des)",
++		.drv_name	= "ecb-des-qce",
++		.blocksize	= DES_BLOCK_SIZE,
++		.ivsize		= 0,
++		.min_keysize	= DES_KEY_SIZE,
++		.max_keysize	= DES_KEY_SIZE,
++	},
++	{
++		.flags		= QCE_ALG_DES | QCE_MODE_CBC,
++		.name		= "cbc(des)",
++		.drv_name	= "cbc-des-qce",
++		.blocksize	= DES_BLOCK_SIZE,
++		.ivsize		= DES_BLOCK_SIZE,
++		.min_keysize	= DES_KEY_SIZE,
++		.max_keysize	= DES_KEY_SIZE,
++	},
++	{
++		.flags		= QCE_ALG_3DES | QCE_MODE_ECB,
++		.name		= "ecb(des3_ede)",
++		.drv_name	= "ecb-3des-qce",
++		.blocksize	= DES3_EDE_BLOCK_SIZE,
++		.ivsize		= 0,
++		.min_keysize	= DES3_EDE_KEY_SIZE,
++		.max_keysize	= DES3_EDE_KEY_SIZE,
++	},
++	{
++		.flags		= QCE_ALG_3DES | QCE_MODE_CBC,
++		.name		= "cbc(des3_ede)",
++		.drv_name	= "cbc-3des-qce",
++		.blocksize	= DES3_EDE_BLOCK_SIZE,
++		.ivsize		= DES3_EDE_BLOCK_SIZE,
++		.min_keysize	= DES3_EDE_KEY_SIZE,
++		.max_keysize	= DES3_EDE_KEY_SIZE,
++	},
++};
++
++static int qce_skcipher_register_one(const struct qce_skcipher_def *def,
++				       struct qce_device *qce)
++{
++	struct qce_alg_template *tmpl;
++	struct skcipher_alg *alg;
++	int ret;
++
++	tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL);
++	if (!tmpl)
++		return -ENOMEM;
++
++	alg = &tmpl->alg.skcipher;
++
++	snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name);
++	snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
++		 def->drv_name);
++
++	alg->base.cra_blocksize		= def->blocksize;
++	alg->ivsize			= def->ivsize;
++	alg->min_keysize		= def->min_keysize;
++	alg->max_keysize		= def->max_keysize;
++	alg->setkey			= qce_skcipher_setkey;
++	alg->encrypt			= qce_skcipher_encrypt;
++	alg->decrypt			= qce_skcipher_decrypt;
++
++	alg->base.cra_priority		= 300;
++	alg->base.cra_flags		= CRYPTO_ALG_ASYNC |
++					  CRYPTO_ALG_NEED_FALLBACK |
++					  CRYPTO_ALG_KERN_DRIVER_ONLY;
++	alg->base.cra_ctxsize		= sizeof(struct qce_cipher_ctx);
++	alg->base.cra_alignmask		= 0;
++	alg->base.cra_module		= THIS_MODULE;
++
++	alg->init			= qce_skcipher_init;
++	alg->exit			= qce_skcipher_exit;
++
++	INIT_LIST_HEAD(&tmpl->entry);
++	tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_SKCIPHER;
++	tmpl->alg_flags = def->flags;
++	tmpl->qce = qce;
++
++	ret = crypto_register_skcipher(alg);
++	if (ret) {
++		kfree(tmpl);
++		dev_err(qce->dev, "%s registration failed\n", alg->base.cra_name);
++		return ret;
++	}
++
++	list_add_tail(&tmpl->entry, &skcipher_algs);
++	dev_dbg(qce->dev, "%s is registered\n", alg->base.cra_name);
++	return 0;
++}
++
++static void qce_skcipher_unregister(struct qce_device *qce)
++{
++	struct qce_alg_template *tmpl, *n;
++
++	list_for_each_entry_safe(tmpl, n, &skcipher_algs, entry) {
++		crypto_unregister_skcipher(&tmpl->alg.skcipher);
++		list_del(&tmpl->entry);
++		kfree(tmpl);
++	}
++}
++
++static int qce_skcipher_register(struct qce_device *qce)
++{
++	int ret, i;
++
++	for (i = 0; i < ARRAY_SIZE(skcipher_def); i++) {
++		ret = qce_skcipher_register_one(&skcipher_def[i], qce);
++		if (ret)
++			goto err;
++	}
++
++	return 0;
++err:
++	qce_skcipher_unregister(qce);
++	return ret;
++}
++
++const struct qce_algo_ops skcipher_ops = {
++	.type = CRYPTO_ALG_TYPE_SKCIPHER,
++	.register_algs = qce_skcipher_register,
++	.unregister_algs = qce_skcipher_unregister,
++	.async_req_handle = qce_skcipher_async_req_handle,
++};

target/linux/ipq40xx/patches-4.14/053-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch

@@ -0,0 +1,39 @@
+From 3f5598286445f695bb63a22239dd3603c69a6eaf Mon Sep 17 00:00:00 2001
+From: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Date: Mon, 28 Oct 2019 09:03:07 -0300
+Subject: [PATCH] crypto: qce - fix ctr-aes-qce block, chunk sizes
+
+Set blocksize of ctr-aes-qce to 1, so it can operate as a stream cipher,
+adding the definition for chucksize instead, where the underlying block
+size belongs.
+
+Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
+
+--- a/drivers/crypto/qce/skcipher.c
++++ b/drivers/crypto/qce/skcipher.c
+@@ -264,6 +264,7 @@ struct qce_skcipher_def {
+ 	const char *name;
+ 	const char *drv_name;
+ 	unsigned int blocksize;
++	unsigned int chunksize;
+ 	unsigned int ivsize;
+ 	unsigned int min_keysize;
+ 	unsigned int max_keysize;
+@@ -292,7 +293,8 @@ static const struct qce_skcipher_def skc
+ 		.flags		= QCE_ALG_AES | QCE_MODE_CTR,
+ 		.name		= "ctr(aes)",
+ 		.drv_name	= "ctr-aes-qce",
+-		.blocksize	= AES_BLOCK_SIZE,
++		.blocksize	= 1,
++		.chunksize	= AES_BLOCK_SIZE,
+ 		.ivsize		= AES_BLOCK_SIZE,
+ 		.min_keysize	= AES_MIN_KEY_SIZE,
+ 		.max_keysize	= AES_MAX_KEY_SIZE,
+@@ -362,6 +364,7 @@ static int qce_skcipher_register_one(con
+ 		 def->drv_name);
+ 
+ 	alg->base.cra_blocksize		= def->blocksize;
++	alg->chunksize			= def->chunksize;
+ 	alg->ivsize			= def->ivsize;
+ 	alg->min_keysize		= def->min_keysize;
+ 	alg->max_keysize		= def->max_keysize;

target/linux/ipq40xx/patches-4.14/054-crypto-qce-fix-xts-aes-qce-key-sizes.patch

@@ -0,0 +1,50 @@
+From 0138c3c13809250338d7cfba6f4ca3b2da02b2c8 Mon Sep 17 00:00:00 2001
+From: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Date: Thu, 21 Nov 2019 14:28:23 -0300
+Subject: [PATCH] crypto: qce - fix xts-aes-qce key sizes
+
+XTS-mode uses two keys, so the keysizes should be doubled in
+skcipher_def, and halved when checking if it is AES-128/192/256.
+
+Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
+
+--- a/drivers/crypto/qce/skcipher.c
++++ b/drivers/crypto/qce/skcipher.c
+@@ -168,7 +168,7 @@ static int qce_skcipher_setkey(struct cr
+ 		return -EINVAL;
+ 
+ 	if (IS_AES(flags)) {
+-		switch (keylen) {
++		switch (IS_XTS(flags) ? keylen >> 1 : keylen) {
+ 		case AES_KEYSIZE_128:
+ 		case AES_KEYSIZE_256:
+ 			break;
+@@ -203,13 +203,15 @@ static int qce_skcipher_crypt(struct skc
+ 	struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+ 	struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
+ 	struct qce_alg_template *tmpl = to_cipher_tmpl(tfm);
++	int keylen;
+ 	int ret;
+ 
+ 	rctx->flags = tmpl->alg_flags;
+ 	rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
++	keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen;
+ 
+-	if (IS_AES(rctx->flags) && ctx->enc_keylen != AES_KEYSIZE_128 &&
+-	    ctx->enc_keylen != AES_KEYSIZE_256) {
++	if (IS_AES(rctx->flags) && keylen != AES_KEYSIZE_128 &&
++	    keylen != AES_KEYSIZE_256) {
+ 		SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
+ 
+ 		skcipher_request_set_tfm(subreq, ctx->fallback);
+@@ -305,8 +307,8 @@ static const struct qce_skcipher_def skc
+ 		.drv_name	= "xts-aes-qce",
+ 		.blocksize	= AES_BLOCK_SIZE,
+ 		.ivsize		= AES_BLOCK_SIZE,
+-		.min_keysize	= AES_MIN_KEY_SIZE,
+-		.max_keysize	= AES_MAX_KEY_SIZE,
++		.min_keysize	= AES_MIN_KEY_SIZE * 2,
++		.max_keysize	= AES_MAX_KEY_SIZE * 2,
+ 	},
+ 	{
+ 		.flags		= QCE_ALG_DES | QCE_MODE_ECB,

target/linux/ipq40xx/patches-4.14/055-crypto-qce-save-a-sg-table-slot-for-result-buf.patch

@@ -0,0 +1,79 @@
+From 31f796293b6c38126a466414c565827b9cfdbe39 Mon Sep 17 00:00:00 2001
+From: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Date: Wed, 20 Nov 2019 21:39:11 -0300
+Subject: [PATCH] crypto: qce - save a sg table slot for result buf
+
+When ctr-aes-qce is used for gcm-mode, an extra sg entry for the
+authentication tag is present, causing trouble when the qce driver
+prepares the dst-results eg table for dma.
+
+It computes the number of entries needed with sg_nents_for_len, leaving
+out the tag entry.  Then it creates a sg table with that number plus
+one, used to store a "result" sg.
+
+When copying the sg table, it does not limit the number of entries
+copied, so tha extra slot is filled with the authentication tag sg.
+When the driver tries to add the result sg, the list is full, and it
+returns EINVAL.
+
+By limiting the number of sg entries copied to the dest table, the slot
+for the result buffer is guaranteed to be unused.
+
+Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
+
+--- a/drivers/crypto/qce/dma.c
++++ b/drivers/crypto/qce/dma.c
+@@ -55,7 +55,8 @@ void qce_dma_release(struct qce_dma_data
+ }
+ 
+ struct scatterlist *
+-qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl)
++qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl,
++		int max_ents)
+ {
+ 	struct scatterlist *sg = sgt->sgl, *sg_last = NULL;
+ 
+@@ -68,12 +69,13 @@ qce_sgtable_add(struct sg_table *sgt, st
+ 	if (!sg)
+ 		return ERR_PTR(-EINVAL);
+ 
+-	while (new_sgl && sg) {
++	while (new_sgl && sg && max_ents) {
+ 		sg_set_page(sg, sg_page(new_sgl), new_sgl->length,
+ 			    new_sgl->offset);
+ 		sg_last = sg;
+ 		sg = sg_next(sg);
+ 		new_sgl = sg_next(new_sgl);
++		max_ents--;
+ 	}
+ 
+ 	return sg_last;
+--- a/drivers/crypto/qce/dma.h
++++ b/drivers/crypto/qce/dma.h
+@@ -50,6 +50,7 @@ int qce_dma_prep_sgs(struct qce_dma_data
+ void qce_dma_issue_pending(struct qce_dma_data *dma);
+ int qce_dma_terminate_all(struct qce_dma_data *dma);
+ struct scatterlist *
+-qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add);
++qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add,
++		int max_ents);
+ 
+ #endif /* _DMA_H_ */
+--- a/drivers/crypto/qce/skcipher.c
++++ b/drivers/crypto/qce/skcipher.c
+@@ -103,13 +103,13 @@ qce_skcipher_async_req_handle(struct cry
+ 
+ 	sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
+ 
+-	sg = qce_sgtable_add(&rctx->dst_tbl, req->dst);
++	sg = qce_sgtable_add(&rctx->dst_tbl, req->dst, rctx->dst_nents - 1);
+ 	if (IS_ERR(sg)) {
+ 		ret = PTR_ERR(sg);
+ 		goto error_free;
+ 	}
+ 
+-	sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg);
++	sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg, 1);
+ 	if (IS_ERR(sg)) {
+ 		ret = PTR_ERR(sg);
+ 		goto error_free;

target/linux/ipq40xx/patches-4.14/056-crypto-qce-update-the-skcipher-IV.patch

@@ -0,0 +1,27 @@
+From 502ca0b7c1d856a46dbd78e67690c12c47775b97 Mon Sep 17 00:00:00 2001
+From: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Date: Fri, 22 Nov 2019 09:00:02 -0300
+Subject: [PATCH] crypto: qce - update the skcipher IV
+
+Update the IV after the completion of each cipher operation.
+
+Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
+
+--- a/drivers/crypto/qce/skcipher.c
++++ b/drivers/crypto/qce/skcipher.c
+@@ -29,6 +29,7 @@ static void qce_skcipher_done(void *data
+ 	struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
+ 	struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req));
+ 	struct qce_device *qce = tmpl->qce;
++	struct qce_result_dump *result_buf = qce->dma.result_buf;
+ 	enum dma_data_direction dir_src, dir_dst;
+ 	u32 status;
+ 	int error;
+@@ -53,6 +54,7 @@ static void qce_skcipher_done(void *data
+ 	if (error < 0)
+ 		dev_dbg(qce->dev, "skcipher operation error (%x)\n", status);
+ 
++	memcpy(rctx->iv, result_buf->encr_cntr_iv, rctx->ivsize);
+ 	qce->async_req_done(tmpl->qce, error);
+ }
+ 

target/linux/ipq40xx/patches-4.14/057-crypto-qce-initialize-fallback-only-for-AES.patch

@@ -0,0 +1,54 @@
+From f2a33ce18232919d3831d1c61a06b6067209282d Mon Sep 17 00:00:00 2001
+From: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Date: Fri, 22 Nov 2019 09:34:29 -0300
+Subject: [PATCH] crypto: qce - initialize fallback only for AES
+
+Adjust cra_flags to add CRYPTO_NEED_FALLBACK only for AES ciphers, where
+AES-192 is not handled by the qce hardware, and don't allocate & free
+the fallback skcipher for anything other than AES.
+
+The rest of the code is unchanged, as the use of the fallback is already
+restricted to AES.
+
+Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
+
+--- a/drivers/crypto/qce/skcipher.c
++++ b/drivers/crypto/qce/skcipher.c
+@@ -246,7 +246,15 @@ static int qce_skcipher_init(struct cryp
+ 
+ 	memset(ctx, 0, sizeof(*ctx));
+ 	crypto_skcipher_set_reqsize(tfm, sizeof(struct qce_cipher_reqctx));
++	return 0;
++}
++
++static int qce_skcipher_init_fallback(struct crypto_skcipher *tfm)
++{
++	struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++	int ret;
+ 
++	qce_skcipher_init(tfm);
+ 	ctx->fallback = crypto_alloc_skcipher(crypto_tfm_alg_name(&tfm->base),
+ 					      0, CRYPTO_ALG_ASYNC |
+ 						 CRYPTO_ALG_NEED_FALLBACK);
+@@ -378,14 +386,18 @@ static int qce_skcipher_register_one(con
+ 
+ 	alg->base.cra_priority		= 300;
+ 	alg->base.cra_flags		= CRYPTO_ALG_ASYNC |
+-					  CRYPTO_ALG_NEED_FALLBACK |
+ 					  CRYPTO_ALG_KERN_DRIVER_ONLY;
+ 	alg->base.cra_ctxsize		= sizeof(struct qce_cipher_ctx);
+ 	alg->base.cra_alignmask		= 0;
+ 	alg->base.cra_module		= THIS_MODULE;
+ 
+-	alg->init			= qce_skcipher_init;
+-	alg->exit			= qce_skcipher_exit;
++	if (IS_AES(def->flags)) {
++		alg->base.cra_flags    |= CRYPTO_ALG_NEED_FALLBACK;
++		alg->init               = qce_skcipher_init_fallback;
++		alg->exit               = qce_skcipher_exit;
++	} else {
++		alg->init               = qce_skcipher_init;
++	}
+ 
+ 	INIT_LIST_HEAD(&tmpl->entry);
+ 	tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_SKCIPHER;

target/linux/ipq40xx/patches-4.14/058-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch

@@ -0,0 +1,83 @@
+From 686aa4db696270dadc5e8b2971769e1676251ff1 Mon Sep 17 00:00:00 2001
+From: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Date: Fri, 31 Jan 2020 17:43:16 -0300
+Subject: [PATCH] crypto: qce - use cryptlen when adding extra sgl
+
+The qce crypto driver appends an extra entry to the dst sgl, to maintain
+private state information.
+
+When the gcm driver sends requests to the ctr skcipher, it passes the
+authentication tag after the actual crypto payload, but it must not be
+touched.
+
+Commit 1336c2221bee ("crypto: qce - save a sg table slot for result
+buf") limited the destination sgl to avoid overwriting the
+authentication tag but it assumed the tag would be in a separate sgl
+entry.
+
+This is not always the case, so it is better to limit the length of the
+destination buffer to req->cryptlen before appending the result buf.
+
+Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
+
+--- a/drivers/crypto/qce/dma.c
++++ b/drivers/crypto/qce/dma.c
+@@ -56,9 +56,10 @@ void qce_dma_release(struct qce_dma_data
+ 
+ struct scatterlist *
+ qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl,
+-		int max_ents)
++		unsigned int max_len)
+ {
+ 	struct scatterlist *sg = sgt->sgl, *sg_last = NULL;
++	unsigned int new_len;
+ 
+ 	while (sg) {
+ 		if (!sg_page(sg))
+@@ -69,13 +70,13 @@ qce_sgtable_add(struct sg_table *sgt, st
+ 	if (!sg)
+ 		return ERR_PTR(-EINVAL);
+ 
+-	while (new_sgl && sg && max_ents) {
+-		sg_set_page(sg, sg_page(new_sgl), new_sgl->length,
+-			    new_sgl->offset);
++	while (new_sgl && sg && max_len) {
++		new_len = new_sgl->length > max_len ? max_len : new_sgl->length;
++		sg_set_page(sg, sg_page(new_sgl), new_len, new_sgl->offset);
+ 		sg_last = sg;
+ 		sg = sg_next(sg);
+ 		new_sgl = sg_next(new_sgl);
+-		max_ents--;
++		max_len -= new_len;
+ 	}
+ 
+ 	return sg_last;
+--- a/drivers/crypto/qce/dma.h
++++ b/drivers/crypto/qce/dma.h
+@@ -51,6 +51,6 @@ void qce_dma_issue_pending(struct qce_dm
+ int qce_dma_terminate_all(struct qce_dma_data *dma);
+ struct scatterlist *
+ qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add,
+-		int max_ents);
++		unsigned int max_len);
+ 
+ #endif /* _DMA_H_ */
+--- a/drivers/crypto/qce/skcipher.c
++++ b/drivers/crypto/qce/skcipher.c
+@@ -105,13 +105,14 @@ qce_skcipher_async_req_handle(struct cry
+ 
+ 	sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
+ 
+-	sg = qce_sgtable_add(&rctx->dst_tbl, req->dst, rctx->dst_nents - 1);
++	sg = qce_sgtable_add(&rctx->dst_tbl, req->dst, req->cryptlen);
+ 	if (IS_ERR(sg)) {
+ 		ret = PTR_ERR(sg);
+ 		goto error_free;
+ 	}
+ 
+-	sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg, 1);
++	sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg,
++			     QCE_RESULT_BUF_SZ);
+ 	if (IS_ERR(sg)) {
+ 		ret = PTR_ERR(sg);
+ 		goto error_free;

target/linux/ipq40xx/patches-4.14/059-crypto-qce-use-AES-fallback-for-small-requests.patch

@@ -0,0 +1,122 @@
+From 2d3b6fae7d1a2ad821769440daa91d7eec5c8250 Mon Sep 17 00:00:00 2001
+From: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Date: Fri, 20 Dec 2019 09:41:44 -0300
+Subject: [PATCH] crypto: qce - use AES fallback for small requests
+
+Process small blocks using the fallback cipher, as a workaround for an
+observed failure (DMA-related, apparently) when computing the GCM ghash
+key.  This brings a speed gain as well, since it avoids the latency of
+using the hardware engine to process small blocks.
+
+Using software for all 16-byte requests would be enough to make GCM
+work, but to increase performance, a larger threshold would be better.
+Measuring the performance of supported ciphers with openssl speed,
+software matches hardware at around 768-1024 bytes.
+
+Considering the 256-bit ciphers, software is 2-3 times faster than qce
+at 256-bytes, 30% faster at 512, and about even at 768-bytes.  With
+128-bit keys, the break-even point would be around 1024-bytes.
+
+This adds the 'aes_sw_max_len' parameter, to set the largest request
+length processed by the software fallback.  Its default is being set to
+512 bytes, a little lower than the break-even point, to balance the cost
+in CPU usage.
+
+Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
+
+--- a/drivers/crypto/Kconfig
++++ b/drivers/crypto/Kconfig
+@@ -592,6 +592,29 @@ config CRYPTO_DEV_QCE
+ 	  hardware. To compile this driver as a module, choose M here. The
+ 	  module will be called qcrypto.
+ 
++config CRYPTO_DEV_QCE_SW_MAX_LEN
++	int "Default maximum request size to use software for AES"
++	depends on CRYPTO_DEV_QCE && CRYPTO_DEV_QCE_SKCIPHER
++	default 512
++	help
++	  This sets the default maximum request size to perform AES requests
++	  using software instead of the crypto engine.  It can be changed by
++	  setting the aes_sw_max_len parameter.
++
++	  Small blocks are processed faster in software than hardware.
++	  Considering the 256-bit ciphers, software is 2-3 times faster than
++	  qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
++	  With 128-bit keys, the break-even point would be around 1024-bytes.
++
++	  The default is set a little lower, to 512 bytes, to balance the
++	  cost in CPU usage.  The minimum recommended setting is 16-bytes
++	  (1 AES block), since AES-GCM will fail if you set it lower.
++	  Setting this to zero will send all requests to the hardware.
++
++	  Note that 192-bit keys are not supported by the hardware and are
++	  always processed by the software fallback, and all DES requests
++	  are done by the hardware.
++
+ config CRYPTO_DEV_VMX
+ 	bool "Support for VMX cryptographic acceleration instructions"
+ 	depends on PPC64 && VSX
+--- a/drivers/crypto/qce/skcipher.c
++++ b/drivers/crypto/qce/skcipher.c
+@@ -13,6 +13,7 @@
+ 
+ #include <linux/device.h>
+ #include <linux/interrupt.h>
++#include <linux/moduleparam.h>
+ #include <linux/types.h>
+ #include <crypto/aes.h>
+ #include <crypto/des.h>
+@@ -20,6 +21,13 @@
+ 
+ #include "cipher.h"
+ 
++static unsigned int aes_sw_max_len = CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN;
++module_param(aes_sw_max_len, uint, 0644);
++MODULE_PARM_DESC(aes_sw_max_len,
++		 "Only use hardware for AES requests larger than this "
++		 "[0=always use hardware; anything <16 breaks AES-GCM; default="
++		 __stringify(CONFIG_CRYPTO_DEV_QCE_SOFT_THRESHOLD)"]");
++
+ static LIST_HEAD(skcipher_algs);
+ 
+ static void qce_skcipher_done(void *data)
+@@ -170,15 +178,7 @@ static int qce_skcipher_setkey(struct cr
+ 	if (!key || !keylen)
+ 		return -EINVAL;
+ 
+-	if (IS_AES(flags)) {
+-		switch (IS_XTS(flags) ? keylen >> 1 : keylen) {
+-		case AES_KEYSIZE_128:
+-		case AES_KEYSIZE_256:
+-			break;
+-		default:
+-			goto fallback;
+-		}
+-	} else if (IS_DES(flags)) {
++	if (IS_DES(flags)) {
+ 		u32 tmp[DES_EXPKEY_WORDS];
+ 
+ 		ret = des_ekey(tmp, key);
+@@ -189,8 +189,8 @@ static int qce_skcipher_setkey(struct cr
+ 
+ 	ctx->enc_keylen = keylen;
+ 	memcpy(ctx->enc_key, key, keylen);
+-	return 0;
+-fallback:
++	if (!IS_AES(flags))
++		return 0;
+ 	ret = crypto_skcipher_setkey(ctx->fallback, key, keylen);
+ 	if (!ret)
+ 		ctx->enc_keylen = keylen;
+@@ -213,8 +213,9 @@ static int qce_skcipher_crypt(struct skc
+ 	rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
+ 	keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen;
+ 
+-	if (IS_AES(rctx->flags) && keylen != AES_KEYSIZE_128 &&
+-	    keylen != AES_KEYSIZE_256) {
++	if (IS_AES(rctx->flags) &&
++	    ((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) ||
++	     req->cryptlen <= aes_sw_max_len)) {
+ 		SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
+ 
+ 		skcipher_request_set_tfm(subreq, ctx->fallback);

target/linux/ipq40xx/patches-4.14/060-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch

@@ -0,0 +1,53 @@
+From bbf2b1cf22dc98f3df33b6666df046dfb9564d91 Mon Sep 17 00:00:00 2001
+From: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Date: Wed, 5 Feb 2020 13:42:25 -0300
+Subject: [PATCH] crypto: qce - handle AES-XTS cases that qce fails
+
+QCE hangs when presented with an AES-XTS request whose length is larger
+than QCE_SECTOR_SIZE (512-bytes), and is not a multiple of it.  Let the
+fallback cipher handle them.
+
+Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
+
+--- a/drivers/crypto/qce/common.c
++++ b/drivers/crypto/qce/common.c
+@@ -23,8 +23,6 @@
+ #include "regs-v5.h"
+ #include "sha.h"
+ 
+-#define QCE_SECTOR_SIZE		512
+-
+ static inline u32 qce_read(struct qce_device *qce, u32 offset)
+ {
+ 	return readl(qce->base + offset);
+--- a/drivers/crypto/qce/common.h
++++ b/drivers/crypto/qce/common.h
+@@ -20,6 +20,9 @@
+ #include <crypto/hash.h>
+ #include <crypto/internal/skcipher.h>
+ 
++/* xts du size */
++#define QCE_SECTOR_SIZE			512
++
+ /* key size in bytes */
+ #define QCE_SHA_HMAC_KEY_SIZE		64
+ #define QCE_MAX_CIPHER_KEY_SIZE		AES_KEYSIZE_256
+--- a/drivers/crypto/qce/skcipher.c
++++ b/drivers/crypto/qce/skcipher.c
+@@ -213,9 +213,14 @@ static int qce_skcipher_crypt(struct skc
+ 	rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
+ 	keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen;
+ 
++	/* qce is hanging when AES-XTS request len > QCE_SECTOR_SIZE and
++	 * is not a multiple of it; pass such requests to the fallback
++	 */
+ 	if (IS_AES(rctx->flags) &&
+-	    ((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) ||
+-	     req->cryptlen <= aes_sw_max_len)) {
++	    (((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) ||
++	      req->cryptlen <= aes_sw_max_len) ||
++	     (IS_XTS(rctx->flags) && req->cryptlen > QCE_SECTOR_SIZE &&
++	      req->cryptlen % QCE_SECTOR_SIZE))) {
+ 		SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
+ 
+ 		skcipher_request_set_tfm(subreq, ctx->fallback);

target/linux/ipq40xx/patches-4.14/061-crypto-qce-allow-building-only-hashes-ciphers.patch

@@ -0,0 +1,406 @@
+From 62134842498927a0fcc19798a615340a7a6a9e62 Mon Sep 17 00:00:00 2001
+From: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Date: Mon, 28 Oct 2019 15:17:19 -0300
+Subject: [PATCH] crypto: qce - allow building only hashes/ciphers
+
+Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
+
+--- a/drivers/crypto/Kconfig
++++ b/drivers/crypto/Kconfig
+@@ -580,6 +580,14 @@ config CRYPTO_DEV_CAVIUM_ZIP
+ config CRYPTO_DEV_QCE
+ 	tristate "Qualcomm crypto engine accelerator"
+ 	depends on (ARCH_QCOM || COMPILE_TEST) && HAS_DMA && HAS_IOMEM
++	help
++	  This driver supports Qualcomm crypto engine accelerator
++	  hardware. To compile this driver as a module, choose M here. The
++	  module will be called qcrypto.
++
++config CRYPTO_DEV_QCE_SKCIPHER
++	bool
++	depends on CRYPTO_DEV_QCE
+ 	select CRYPTO_AES
+ 	select CRYPTO_DES
+ 	select CRYPTO_ECB
+@@ -587,10 +595,57 @@ config CRYPTO_DEV_QCE
+ 	select CRYPTO_XTS
+ 	select CRYPTO_CTR
+ 	select CRYPTO_BLKCIPHER
++
++config CRYPTO_DEV_QCE_SHA
++	bool
++	depends on CRYPTO_DEV_QCE
++
++choice
++	prompt "Algorithms enabled for QCE acceleration"
++	default CRYPTO_DEV_QCE_ENABLE_ALL
++	depends on CRYPTO_DEV_QCE
+ 	help
+-	  This driver supports Qualcomm crypto engine accelerator
+-	  hardware. To compile this driver as a module, choose M here. The
+-	  module will be called qcrypto.
++	  This option allows to choose whether to build support for all algorihtms
++	  (default), hashes-only, or skciphers-only.
++
++	  The QCE engine does not appear to scale as well as the CPU to handle
++	  multiple crypto requests.  While the ipq40xx chips have 4-core CPUs, the
++	  QCE handles only 2 requests in parallel.
++
++	  Ipsec throughput seems to improve when disabling either family of
++	  algorithms, sharing the load with the CPU.  Enabling skciphers-only
++	  appears to work best.
++
++	config CRYPTO_DEV_QCE_ENABLE_ALL
++		bool "All supported algorithms"
++		select CRYPTO_DEV_QCE_SKCIPHER
++		select CRYPTO_DEV_QCE_SHA
++		help
++		  Enable all supported algorithms:
++			- AES (CBC, CTR, ECB, XTS)
++			- 3DES (CBC, ECB)
++			- DES (CBC, ECB)
++			- SHA1, HMAC-SHA1
++			- SHA256, HMAC-SHA256
++
++	config CRYPTO_DEV_QCE_ENABLE_SKCIPHER
++		bool "Symmetric-key ciphers only"
++		select CRYPTO_DEV_QCE_SKCIPHER
++		help
++		  Enable symmetric-key ciphers only:
++			- AES (CBC, CTR, ECB, XTS)
++			- 3DES (ECB, CBC)
++			- DES (ECB, CBC)
++
++	config CRYPTO_DEV_QCE_ENABLE_SHA
++		bool "Hash/HMAC only"
++		select CRYPTO_DEV_QCE_SHA
++		help
++		  Enable hashes/HMAC algorithms only:
++			- SHA1, HMAC-SHA1
++			- SHA256, HMAC-SHA256
++
++endchoice
+ 
+ config CRYPTO_DEV_QCE_SW_MAX_LEN
+ 	int "Default maximum request size to use software for AES"
+--- a/drivers/crypto/qce/Makefile
++++ b/drivers/crypto/qce/Makefile
+@@ -2,6 +2,7 @@
+ obj-$(CONFIG_CRYPTO_DEV_QCE) += qcrypto.o
+ qcrypto-objs := core.o \
+ 		common.o \
+-		dma.o \
+-		sha.o \
+-		skcipher.o
++		dma.o
++
++qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SHA) += sha.o
++qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SKCIPHER) += skcipher.o
+--- a/drivers/crypto/qce/common.c
++++ b/drivers/crypto/qce/common.c
+@@ -51,52 +51,56 @@ qce_clear_array(struct qce_device *qce,
+ 		qce_write(qce, offset + i * sizeof(u32), 0);
+ }
+ 
+-static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
++static u32 qce_config_reg(struct qce_device *qce, int little)
+ {
+-	u32 cfg = 0;
++	u32 beats = (qce->burst_size >> 3) - 1;
++	u32 pipe_pair = qce->pipe_pair_id;
++	u32 config;
+ 
+-	if (IS_AES(flags)) {
+-		if (aes_key_size == AES_KEYSIZE_128)
+-			cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
+-		else if (aes_key_size == AES_KEYSIZE_256)
+-			cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
+-	}
++	config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
++	config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
++		  BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
++	config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
++	config &= ~HIGH_SPD_EN_N_SHIFT;
+ 
+-	if (IS_AES(flags))
+-		cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
+-	else if (IS_DES(flags) || IS_3DES(flags))
+-		cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
++	if (little)
++		config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
+ 
+-	if (IS_DES(flags))
+-		cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
++	return config;
++}
+ 
+-	if (IS_3DES(flags))
+-		cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
++void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
++{
++	__be32 *d = dst;
++	const u8 *s = src;
++	unsigned int n;
+ 
+-	switch (flags & QCE_MODE_MASK) {
+-	case QCE_MODE_ECB:
+-		cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
+-		break;
+-	case QCE_MODE_CBC:
+-		cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
+-		break;
+-	case QCE_MODE_CTR:
+-		cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
+-		break;
+-	case QCE_MODE_XTS:
+-		cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
+-		break;
+-	case QCE_MODE_CCM:
+-		cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
+-		cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
+-		break;
+-	default:
+-		return ~0;
++	n = len / sizeof(u32);
++	for (; n > 0; n--) {
++		*d = cpu_to_be32p((const __u32 *) s);
++		s += sizeof(__u32);
++		d++;
+ 	}
++}
+ 
+-	return cfg;
++static void qce_setup_config(struct qce_device *qce)
++{
++	u32 config;
++
++	/* get big endianness */
++	config = qce_config_reg(qce, 0);
++
++	/* clear status */
++	qce_write(qce, REG_STATUS, 0);
++	qce_write(qce, REG_CONFIG, config);
++}
++
++static inline void qce_crypto_go(struct qce_device *qce)
++{
++	qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
+ }
+ 
++#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
+ static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
+ {
+ 	u32 cfg = 0;
+@@ -143,88 +147,6 @@ static u32 qce_auth_cfg(unsigned long fl
+ 	return cfg;
+ }
+ 
+-static u32 qce_config_reg(struct qce_device *qce, int little)
+-{
+-	u32 beats = (qce->burst_size >> 3) - 1;
+-	u32 pipe_pair = qce->pipe_pair_id;
+-	u32 config;
+-
+-	config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
+-	config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
+-		  BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
+-	config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
+-	config &= ~HIGH_SPD_EN_N_SHIFT;
+-
+-	if (little)
+-		config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
+-
+-	return config;
+-}
+-
+-void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
+-{
+-	__be32 *d = dst;
+-	const u8 *s = src;
+-	unsigned int n;
+-
+-	n = len / sizeof(u32);
+-	for (; n > 0; n--) {
+-		*d = cpu_to_be32p((const __u32 *) s);
+-		s += sizeof(__u32);
+-		d++;
+-	}
+-}
+-
+-static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
+-{
+-	u8 swap[QCE_AES_IV_LENGTH];
+-	u32 i, j;
+-
+-	if (ivsize > QCE_AES_IV_LENGTH)
+-		return;
+-
+-	memset(swap, 0, QCE_AES_IV_LENGTH);
+-
+-	for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
+-	     i < QCE_AES_IV_LENGTH; i++, j--)
+-		swap[i] = src[j];
+-
+-	qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
+-}
+-
+-static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
+-		       unsigned int enckeylen, unsigned int cryptlen)
+-{
+-	u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
+-	unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
+-	unsigned int xtsdusize;
+-
+-	qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
+-			       enckeylen / 2);
+-	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
+-
+-	/* xts du size 512B */
+-	xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
+-	qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
+-}
+-
+-static void qce_setup_config(struct qce_device *qce)
+-{
+-	u32 config;
+-
+-	/* get big endianness */
+-	config = qce_config_reg(qce, 0);
+-
+-	/* clear status */
+-	qce_write(qce, REG_STATUS, 0);
+-	qce_write(qce, REG_CONFIG, config);
+-}
+-
+-static inline void qce_crypto_go(struct qce_device *qce)
+-{
+-	qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
+-}
+-
+ static int qce_setup_regs_ahash(struct crypto_async_request *async_req,
+ 				u32 totallen, u32 offset)
+ {
+@@ -309,6 +231,87 @@ go_proc:
+ 
+ 	return 0;
+ }
++#endif
++
++#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
++static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
++{
++	u32 cfg = 0;
++
++	if (IS_AES(flags)) {
++		if (aes_key_size == AES_KEYSIZE_128)
++			cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
++		else if (aes_key_size == AES_KEYSIZE_256)
++			cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
++	}
++
++	if (IS_AES(flags))
++		cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
++	else if (IS_DES(flags) || IS_3DES(flags))
++		cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
++
++	if (IS_DES(flags))
++		cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
++
++	if (IS_3DES(flags))
++		cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
++
++	switch (flags & QCE_MODE_MASK) {
++	case QCE_MODE_ECB:
++		cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
++		break;
++	case QCE_MODE_CBC:
++		cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
++		break;
++	case QCE_MODE_CTR:
++		cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
++		break;
++	case QCE_MODE_XTS:
++		cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
++		break;
++	case QCE_MODE_CCM:
++		cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
++		cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
++		break;
++	default:
++		return ~0;
++	}
++
++	return cfg;
++}
++
++static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
++{
++	u8 swap[QCE_AES_IV_LENGTH];
++	u32 i, j;
++
++	if (ivsize > QCE_AES_IV_LENGTH)
++		return;
++
++	memset(swap, 0, QCE_AES_IV_LENGTH);
++
++	for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
++	     i < QCE_AES_IV_LENGTH; i++, j--)
++		swap[i] = src[j];
++
++	qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
++}
++
++static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
++		       unsigned int enckeylen, unsigned int cryptlen)
++{
++	u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
++	unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
++	unsigned int xtsdusize;
++
++	qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
++			       enckeylen / 2);
++	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
++
++	/* xts du size 512B */
++	xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
++	qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
++}
+ 
+ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
+ 				     u32 totallen, u32 offset)
+@@ -390,15 +393,20 @@ static int qce_setup_regs_skcipher(struc
+ 
+ 	return 0;
+ }
++#endif
+ 
+ int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
+ 	      u32 offset)
+ {
+ 	switch (type) {
++#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
+ 	case CRYPTO_ALG_TYPE_SKCIPHER:
+ 		return qce_setup_regs_skcipher(async_req, totallen, offset);
++#endif
++#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
+ 	case CRYPTO_ALG_TYPE_AHASH:
+ 		return qce_setup_regs_ahash(async_req, totallen, offset);
++#endif
+ 	default:
+ 		return -EINVAL;
+ 	}
+--- a/drivers/crypto/qce/core.c
++++ b/drivers/crypto/qce/core.c
+@@ -29,8 +29,12 @@
+ #define QCE_QUEUE_LENGTH	1
+ 
+ static const struct qce_algo_ops *qce_ops[] = {
++#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
+ 	&skcipher_ops,
++#endif
++#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
+ 	&ahash_ops,
++#endif
+ };
+ 
+ static void qce_unregister_algs(struct qce_device *qce)

target/linux/ipq40xx/patches-4.14/182-crypto-qce-fix-ctr-blocksize.patch

@@ -1,11 +0,0 @@
---- a/drivers/crypto/qce/ablkcipher.c	2019-10-21 17:18:47.311684603 -0300
-+++ b/drivers/crypto/qce/ablkcipher.c	2019-10-21 17:20:32.080765945 -0300
-@@ -292,7 +292,7 @@
- 		.name		= "ctr(aes)",
- 		.drv_name	= "ctr-aes-qce",
- 		.blocksize	= AES_BLOCK_SIZE,
--		.ivsize		= AES_BLOCK_SIZE,
-+		.ivsize		= 1,
- 		.min_keysize	= AES_MIN_KEY_SIZE,
- 		.max_keysize	= AES_MAX_KEY_SIZE,
- 	},

target/linux/ipq40xx/patches-4.14/183-crypto-qce-update-iv.patch

@@ -1,68 +0,0 @@
-diff --git a/drivers/crypto/qce/ablkcipher.c b/drivers/crypto/qce/ablkcipher.c
-index 7a98bf5cc967..b935ce0acc1c 100644
---- a/drivers/crypto/qce/ablkcipher.c
-+++ b/drivers/crypto/qce/ablkcipher.c
-@@ -14,6 +14,20 @@
- 
- static LIST_HEAD(ablkcipher_algs);
- 
-+static void qce_update_ctr_iv(u8 *iv, unsigned int ivsize, u32 add)
-+{
-+	__be32 *a = (__be32 *)(iv + ivsize);
-+	u32 b;
-+
-+	for (; ivsize >= 4; ivsize -= 4) {
-+		b = be32_to_cpu(*--a) + add;
-+		*a = cpu_to_be32(b);
-+		if (b >= add)
-+			return;
-+		add = 1;
-+	}
-+}
-+
- static void qce_ablkcipher_done(void *data)
- {
- 	struct crypto_async_request *async_req = data;
-@@ -39,6 +53,18 @@ static void qce_ablkcipher_done(void *data)
- 		dma_unmap_sg(qce->dev, rctx->src_sg, rctx->src_nents, dir_src);
- 	dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
- 
-+	if (IS_CBC(rctx->flags)) {
-+		if (IS_ENCRYPT(rctx->flags))
-+			sg_pcopy_to_buffer(rctx->dst_sg, rctx->dst_nents,
-+					   rctx->iv, rctx->ivsize,
-+					   rctx->cryptlen - rctx->ivsize);
-+		else
-+			memcpy(rctx->iv, rctx->saved_iv, rctx->ivsize);
-+	} else if (IS_CTR(rctx->flags) && IS_AES(rctx->flags)) {
-+		qce_update_ctr_iv(rctx->iv, rctx->ivsize,
-+				  DIV_ROUND_UP(rctx->cryptlen, AES_BLOCK_SIZE));
-+	}
-+
- 	sg_free_table(&rctx->dst_tbl);
- 
- 	error = qce_check_status(qce, &status);
-@@ -131,6 +157,11 @@ qce_ablkcipher_async_req_handle(struct crypto_async_request *async_req)
- 
- 	qce_dma_issue_pending(&qce->dma);
- 
-+	if (IS_CBC(rctx->flags) && IS_DECRYPT(rctx->flags))
-+		sg_pcopy_to_buffer(rctx->src_sg, rctx->src_nents,
-+				   rctx->saved_iv, rctx->ivsize,
-+				   rctx->cryptlen - rctx->ivsize);
-+
- 	ret = qce_start(async_req, tmpl->crypto_alg_type, req->nbytes, 0);
- 	if (ret)
- 		goto error_terminate;
-diff --git a/drivers/crypto/qce/cipher.h b/drivers/crypto/qce/cipher.h
-index 5cab8f0706a8..a919022e28df 100644
---- a/drivers/crypto/qce/cipher.h
-+++ b/drivers/crypto/qce/cipher.h
-@@ -43,6 +43,7 @@ struct qce_cipher_reqctx {
- 	struct sg_table src_tbl;
- 	struct scatterlist *src_sg;
- 	unsigned int cryptlen;
-+	u8 saved_iv[QCE_MAX_IV_SIZE];
- };
- 
- static inline struct qce_alg_template *to_cipher_tmpl(struct crypto_tfm *tfm)

target/linux/ipq40xx/patches-4.14/184-crypto-qce-allow-building-only-hashes-ciphers.patch

@@ -1,91 +0,0 @@
-From 2f23be905522cc67505daaf4d94c0292dbddd315 Mon Sep 17 00:00:00 2001
-From: Eneas U de Queiroz <cotequeiroz@gmail.com>
-Date: Mon, 28 Oct 2019 15:17:19 -0300
-Subject: [PATCH] crypto: qce - allow building only hashes/ciphers
-
-Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
-
-diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
-index 1fb622f2a87d..0dc4bbcfc092 100644
---- a/drivers/crypto/Kconfig
-+++ b/drivers/crypto/Kconfig
-@@ -580,5 +580,13 @@ config CRYPTO_DEV_QCE
- 	tristate "Qualcomm crypto engine accelerator"
- 	depends on (ARCH_QCOM || COMPILE_TEST) && HAS_DMA && HAS_IOMEM
-+	help
-+	  This driver supports Qualcomm crypto engine accelerator
-+	  hardware. To compile this driver as a module, choose M here. The
-+	  module will be called qcrypto.
-+
-+config CRYPTO_DEV_QCE_BLKCIPHER
-+	bool
-+	depends on CRYPTO_DEV_QCE
- 	select CRYPTO_AES
- 	select CRYPTO_LIB_DES
- 	select CRYPTO_ECB
-@@ -580,10 +588,29 @@ config CRYPTO_DEV_QCE
- 	select CRYPTO_XTS
- 	select CRYPTO_CTR
- 	select CRYPTO_BLKCIPHER
--	help
--	  This driver supports Qualcomm crypto engine accelerator
--	  hardware. To compile this driver as a module, choose M here. The
--	  module will be called qcrypto.
-+
-+config CRYPTO_DEV_QCE_SHA
-+	bool
-+	depends on CRYPTO_DEV_QCE
-+
-+choice
-+	prompt "Algorithms enabled for QCE acceleration"
-+	default CRYPTO_DEV_QCE_ENABLE_ALL
-+	depends on CRYPTO_DEV_QCE
-+
-+	config CRYPTO_DEV_QCE_ENABLE_ALL
-+		bool "All supported algorithms"
-+		select CRYPTO_DEV_QCE_BLKCIPHER
-+		select CRYPTO_DEV_QCE_SHA
-+
-+	config CRYPTO_DEV_QCE_ENABLE_BLKCIPHER
-+		bool "Block ciphers only"
-+		select CRYPTO_DEV_QCE_BLKCIPHER
-+
-+	config CRYPTO_DEV_QCE_ENABLE_SHA
-+		bool "Hash/HMAC only"
-+		select CRYPTO_DEV_QCE_SHA
-+endchoice
- 
- config CRYPTO_DEV_QCOM_RNG
- 	tristate "Qualcomm Random Number Generator Driver"
-diff --git a/drivers/crypto/qce/Makefile b/drivers/crypto/qce/Makefile
-index 19a7f899acff..f6a411c255b8 100644
---- a/drivers/crypto/qce/Makefile
-+++ b/drivers/crypto/qce/Makefile
-@@ -2,6 +2,7 @@
- obj-$(CONFIG_CRYPTO_DEV_QCE) += qcrypto.o
- qcrypto-objs := core.o \
- 		common.o \
--		dma.o \
--		sha.o \
--		ablkcipher.o
-+		dma.o
-+
-+qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SHA) += sha.o
-+qcrypto-$(CONFIG_CRYPTO_DEV_QCE_BLKCIPHER) += ablkcipher.o
-diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
-index 08d4ce3bfddf..3428746f1869 100644
---- a/drivers/crypto/qce/core.c
-+++ b/drivers/crypto/qce/core.c
-@@ -22,8 +22,12 @@
- #define QCE_QUEUE_LENGTH	1
- 
- static const struct qce_algo_ops *qce_ops[] = {
-+#ifdef CONFIG_CRYPTO_DEV_QCE_BLKCIPHER
- 	&ablkcipher_ops,
-+#endif
-+#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
- 	&ahash_ops,
-+#endif
- };
- 
- static void qce_unregister_algs(struct qce_device *qce)

target/linux/ipq40xx/patches-4.14/715-essedma-refine-txq-to-be-adaptive-of-cpus-and-netdev.patch

@@ -1,8 +1,6 @@
-diff --git a/drivers/net/ethernet/qualcomm/essedma/edma.c b/drivers/net/ethernet/qualcomm/essedma/edma.c
-index 724f355..7a16236 100644
 --- a/drivers/net/ethernet/qualcomm/essedma/edma.c
 +++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
-@@ -22,14 +22,6 @@ extern struct net_device *edma_netdev[EDMA_MAX_PORTID_SUPPORTED];
+@@ -22,14 +22,6 @@ extern struct net_device *edma_netdev[ED
  bool edma_stp_rstp;
  u16 edma_ath_eth_type;
  
@@ -17,7 +15,7 @@ index 724f355..7a16236 100644
  /* edma_alloc_tx_ring()
   *	Allocate Tx descriptors ring
   */
-@@ -1014,13 +1006,14 @@ static inline u16 edma_tpd_available(struct edma_common_info *edma_cinfo,
+@@ -1018,13 +1010,14 @@ static inline u16 edma_tpd_available(str
  /* edma_tx_queue_get()
   *	Get the starting number of  the queue
   */
@@ -34,7 +32,7 @@ index 724f355..7a16236 100644
  }
  
  /* edma_tx_update_hw_idx()
-@@ -1389,8 +1382,9 @@ netdev_tx_t edma_xmit(struct sk_buff *skb,
+@@ -1393,8 +1386,9 @@ netdev_tx_t edma_xmit(struct sk_buff *sk
  	}
  
  	/* this will be one of the 4 TX queues exposed to linux kernel */
@@ -46,7 +44,7 @@ index 724f355..7a16236 100644
  	etdr = edma_cinfo->tpd_ring[queue_id];
  	nq = netdev_get_tx_queue(net_dev, txq_id);
  
-@@ -1871,8 +1865,8 @@ void edma_free_irqs(struct edma_adapter *adapter)
+@@ -1875,8 +1869,8 @@ void edma_free_irqs(struct edma_adapter
  	int i, j;
  	int k = ((edma_cinfo->num_rx_queues == 4) ? 1 : 2);
  
@@ -57,8 +55,6 @@ index 724f355..7a16236 100644
  			free_irq(edma_cinfo->tx_irq[j], &edma_cinfo->edma_percpu_info[i]);
  
  		for (j = edma_cinfo->edma_percpu_info[i].rx_start; j < (edma_cinfo->edma_percpu_info[i].rx_start + k); j++)
-diff --git a/drivers/net/ethernet/qualcomm/essedma/edma.h b/drivers/net/ethernet/qualcomm/essedma/edma.h
-index 015e5f5..abb0bd5 100644
 --- a/drivers/net/ethernet/qualcomm/essedma/edma.h
 +++ b/drivers/net/ethernet/qualcomm/essedma/edma.h
 @@ -324,6 +324,7 @@ struct edma_common_info {
@@ -76,7 +72,7 @@ index 015e5f5..abb0bd5 100644
 -	struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */
 +	struct edma_per_cpu_queues_info edma_percpu_info[EDMA_CPU_CORES_SUPPORTED]; /* per cpu information */
  	spinlock_t stats_lock; /* protect edma stats area for updation */
- 	struct timer_list edma_stats_timer;
+ 
  	bool is_single_phy;
 @@ -401,7 +402,7 @@ struct edma_adapter {
  	u32 link_state; /* phy link state */
@@ -87,11 +83,9 @@ index 015e5f5..abb0bd5 100644
  	u32 default_vlan_tag; /* vlan tag */
  	u32 dp_bitmap;
  	uint8_t phy_id[MII_BUS_ID_SIZE + 3];
-diff --git a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
-index d53c63b..2d4770c 100644
 --- a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
 +++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
-@@ -719,11 +719,7 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -721,11 +721,7 @@ static int edma_axi_probe(struct platfor
  	int i, j, k, err = 0;
  	int portid_bmp;
  	int idx = 0, idx_mac = 0;
@@ -104,7 +98,7 @@ index d53c63b..2d4770c 100644
  
  	if ((num_rxq != 4) && (num_rxq != 8)) {
  		dev_err(&pdev->dev, "Invalid RX queue, edma probe failed\n");
-@@ -747,7 +743,7 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -749,7 +745,7 @@ static int edma_axi_probe(struct platfor
  	/* Initialize the netdev array before allocation
  	 * to avoid double free
  	 */
@@ -113,7 +107,7 @@ index d53c63b..2d4770c 100644
  		edma_netdev[i] = NULL;
  
  	for (i = 0 ; i < edma_cinfo->num_gmac ; i++) {
-@@ -768,8 +764,11 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -770,8 +766,11 @@ static int edma_axi_probe(struct platfor
  
  	/* Fill ring details */
  	edma_cinfo->num_tx_queues = EDMA_MAX_TRANSMIT_QUEUE;
@@ -126,7 +120,7 @@ index d53c63b..2d4770c 100644
  
  	/* Update num rx queues based on module parameter */
  	edma_cinfo->num_rx_queues = num_rxq;
-@@ -939,6 +938,13 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -941,6 +940,13 @@ static int edma_axi_probe(struct platfor
  		idx_mac++;
  	}
  
@@ -140,7 +134,7 @@ index d53c63b..2d4770c 100644
  	/* Populate the adapter structure register the netdevice */
  	for (i = 0; i < edma_cinfo->num_gmac; i++) {
  		int k, m;
-@@ -946,17 +952,16 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -948,17 +954,16 @@ static int edma_axi_probe(struct platfor
  		adapter[i] = netdev_priv(edma_netdev[i]);
  		adapter[i]->netdev = edma_netdev[i];
  		adapter[i]->pdev = pdev;
@@ -162,7 +156,7 @@ index d53c63b..2d4770c 100644
  				if (edma_fill_netdev(edma_cinfo, k, i, j)) {
  					pr_err("Netdev overflow Error\n");
  					goto err_register;
-@@ -1109,9 +1114,12 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -1111,9 +1116,12 @@ static int edma_axi_probe(struct platfor
  	/* populate per_core_info, do a napi_Add, request 16 TX irqs,
  	 * 8 RX irqs, do a napi enable
  	 */
@@ -176,7 +170,7 @@ index d53c63b..2d4770c 100644
  		edma_cinfo->edma_percpu_info[i].napi.state = 0;
  
  		netif_napi_add(edma_netdev[0],
-@@ -1131,7 +1139,7 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -1133,7 +1141,7 @@ static int edma_axi_probe(struct platfor
  
  		/* Request irq per core */
  		for (j = edma_cinfo->edma_percpu_info[i].tx_start;
@@ -185,7 +179,7 @@ index d53c63b..2d4770c 100644
  			sprintf(&edma_tx_irq[j][0], "edma_eth_tx%d", j);
  			err = request_irq(edma_cinfo->tx_irq[j],
  					  edma_interrupt,
-@@ -1253,7 +1261,7 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -1258,7 +1266,7 @@ err_configure:
  #endif
  err_rmap_add_fail:
  	edma_free_irqs(adapter[0]);
@@ -194,7 +188,7 @@ index d53c63b..2d4770c 100644
  		napi_disable(&edma_cinfo->edma_percpu_info[i].napi);
  err_reset:
  err_unregister_sysctl_tbl:
-@@ -1301,7 +1309,7 @@ static int edma_axi_remove(struct platform_device *pdev)
+@@ -1306,7 +1314,7 @@ static int edma_axi_remove(struct platfo
  		unregister_netdev(edma_netdev[i]);
  
  	edma_stop_rx_tx(hw);

target/linux/ipq40xx/patches-4.14/716-essedma-reduce-write-reg.patch

@@ -1,8 +1,6 @@
-diff --git a/drivers/net/ethernet/qualcomm/essedma/edma.c b/drivers/net/ethernet/qualcomm/essedma/edma.c
-index fc274c8..e9d12a4 100644
 --- a/drivers/net/ethernet/qualcomm/essedma/edma.c
 +++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
-@@ -2075,15 +2075,13 @@ int edma_poll(struct napi_struct *napi, int budget)
+@@ -2079,15 +2079,13 @@ int edma_poll(struct napi_struct *napi,
  	int i, work_done = 0;
  	u16 rx_pending_fill;
  
@@ -21,7 +19,7 @@ index fc274c8..e9d12a4 100644
  
  	/* Every core will have a start, which will be computed
  	 * in probe and stored in edma_percpu_info->tx_start variable.
-@@ -2098,6 +2096,14 @@ int edma_poll(struct napi_struct *napi, int budget)
+@@ -2102,6 +2100,14 @@ int edma_poll(struct napi_struct *napi,
  		edma_percpu_info->tx_status &= ~(1 << queue_id);
  	}
  
@@ -36,7 +34,7 @@ index fc274c8..e9d12a4 100644
  	/* Every core will have a start, which will be computed
  	 * in probe and stored in edma_percpu_info->tx_start variable.
  	 * We will shift the status bit by tx_start to obtain
-@@ -2122,15 +2128,6 @@ int edma_poll(struct napi_struct *napi, int budget)
+@@ -2126,15 +2132,6 @@ int edma_poll(struct napi_struct *napi,
  		}
  	}
  

target/linux/ipq40xx/patches-4.14/854-add-sdhci-reset-implementation.patch

@@ -8,11 +8,9 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
 drivers/mmc/host/sdhci-msm.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)
 
-diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
-index 32879b845b75..157ae07f9309 100644
 --- a/drivers/mmc/host/sdhci-msm.c
 +++ b/drivers/mmc/host/sdhci-msm.c
-@@ -1117,6 +1117,33 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+@@ -1123,6 +1123,33 @@ out:
  	__sdhci_msm_set_clock(host, clock);
  }
  
@@ -45,13 +43,13 @@ index 32879b845b75..157ae07f9309 100644
 +
  static void sdhci_msm_write_w(struct sdhci_host *host, u16 val, int reg)
  {
-	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-@@ -1148,7 +1174,7 @@ static const struct of_device_id sdhci_msm_dt_match[] = {
+ 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+@@ -1154,7 +1181,7 @@ static const struct of_device_id sdhci_m
  MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
  
  static const struct sdhci_ops sdhci_msm_ops = {
 -	.reset = sdhci_reset,
 +	.reset = sdhci_msm_reset,
-	.set_clock = sdhci_set_clock,
-	.get_min_clock = sdhci_msm_get_min_clock,
-	.get_max_clock = sdhci_msm_get_max_clock,
+ 	.set_clock = sdhci_set_clock,
+ 	.get_min_clock = sdhci_msm_get_min_clock,
+ 	.get_max_clock = sdhci_msm_get_max_clock,

target/linux/ipq40xx/patches-4.14/901-essedma-disable-default-vlan-tagging.patch

@@ -22,11 +22,9 @@ Signed-off-by: Chen Minqiang <ptpt52@gmail.com>
  drivers/net/ethernet/qualcomm/essedma/edma.c | 14 +++++---------
  2 files changed, 7 insertions(+), 12 deletions(-)
 
-diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-index 3c4617f..7c3af8e 100644
 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -598,8 +598,7 @@
+@@ -648,8 +648,7 @@
  			qcom,page-mode = <0>;
  			qcom,rx_head_buf_size = <1540>;
  			qcom,mdio_supported;
@@ -36,7 +34,7 @@ index 3c4617f..7c3af8e 100644
  			interrupts = <0  65 IRQ_TYPE_EDGE_RISING
  				      0  66 IRQ_TYPE_EDGE_RISING
  				      0  67 IRQ_TYPE_EDGE_RISING
-@@ -637,7 +636,7 @@
+@@ -687,7 +686,7 @@
  
  			gmac0: gmac0 {
  				local-mac-address = [00 00 00 00 00 00];
@@ -45,11 +43,9 @@ index 3c4617f..7c3af8e 100644
  			};
  
  			gmac1: gmac1 {
-diff --git a/drivers/net/ethernet/qualcomm/essedma/edma.c b/drivers/net/ethernet/qualcomm/essedma/edma.c
-index 05f9ce9..a3c0d66 100644
 --- a/drivers/net/ethernet/qualcomm/essedma/edma.c
 +++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
-@@ -750,13 +750,11 @@ static void edma_rx_complete(struct edma_common_info *edma_cinfo,
+@@ -721,13 +721,11 @@ static u16 edma_rx_complete(struct edma_
  			edma_receive_checksum(rd, skb);
  
  			/* Process VLAN HW acceleration indication provided by HW */
@@ -68,7 +64,7 @@ index 05f9ce9..a3c0d66 100644
  
  			/* Update rx statistics */
  			adapter->stats.rx_packets++;
-@@ -1434,8 +1432,6 @@ netdev_tx_t edma_xmit(struct sk_buff *skb,
+@@ -1410,8 +1408,6 @@ netdev_tx_t edma_xmit(struct sk_buff *sk
  	if (!adapter->edma_cinfo->is_single_phy) {
  		if (unlikely(skb_vlan_tag_present(skb)))
  			flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG;
@@ -77,6 +73,3 @@ index 05f9ce9..a3c0d66 100644
  	}
  
  	/* Check and mark checksum offload */
--- 
-2.7.4
-

target/linux/ipq40xx/patches-4.14/998-ignore-stats-debug-info.patch

@@ -1,8 +1,6 @@
-diff --git a/drivers/net/wireless/ath/ath10k/htt_rx.c b/drivers/net/wireless/ath/ath10k/htt_rx.c
-index 7d295ee71534..50670d651cff 100644
 --- a/drivers/net/wireless/ath/ath10k/htt_rx.c
 +++ b/drivers/net/wireless/ath/ath10k/htt_rx.c
-@@ -2520,7 +2520,7 @@
+@@ -2329,7 +2329,7 @@ ath10k_update_per_peer_tx_stats(struct a
  	sgi = ATH10K_HW_GI(peer_stats->flags);
  
  	if (txrate.flags == WMI_RATE_PREAMBLE_VHT && txrate.mcs > 9) {
@@ -11,7 +9,7 @@ index 7d295ee71534..50670d651cff 100644
  		return;
  	}
  
-@@ -2578,7 +2578,7 @@
+@@ -2387,7 +2387,7 @@ static void ath10k_htt_fetch_peer_stats(
  	ppdu_len = resp->peer_tx_stats.ppdu_len * sizeof(__le32);
  
  	if (skb->len < sizeof(struct htt_resp_hdr) + num_ppdu * ppdu_len) {
@@ -20,7 +18,7 @@ index 7d295ee71534..50670d651cff 100644
  		return;
  	}
  
-@@ -2590,8 +2590,8 @@
+@@ -2399,8 +2399,8 @@ static void ath10k_htt_fetch_peer_stats(
  	spin_lock_bh(&ar->data_lock);
  	peer = ath10k_peer_find_by_id(ar, peer_id);
  	if (!peer) {
@@ -30,12 +28,10 @@ index 7d295ee71534..50670d651cff 100644
 +			     
  		goto out;
  	}
-
  
-diff --git a/drivers/net/wireless/ath/ath10k/txrx.c b/drivers/net/wireless/ath/ath10k/txrx.c	
 --- a/drivers/net/wireless/ath/ath10k/txrx.c
 +++ b/drivers/net/wireless/ath/ath10k/txrx.c
-@@ -261,8 +261,8 @@
+@@ -250,8 +250,8 @@ void ath10k_peer_unmap_event(struct ath1
  	spin_lock_bh(&ar->data_lock);
  	peer = ath10k_peer_find_by_id(ar, ev->peer_id);
  	if (!peer) {
@@ -45,12 +41,10 @@ diff --git a/drivers/net/wireless/ath/ath10k/txrx.c b/drivers/net/wireless/ath/a
 +			    
  		goto exit;
  	}
-
-diff --git a/drivers/base/firmware_class.c b/drivers/base/firmware_class.c
-index 10a4467..eb8fb94 100644
+ 
 --- a/drivers/base/firmware_class.c
 +++ b/drivers/base/firmware_class.c
-@@ -1218,10 +1218,10 @@
+@@ -1218,10 +1218,10 @@ _request_firmware(const struct firmware
  	if (ret) {
  		if (!(opt_flags & FW_OPT_NO_WARN))
  			dev_warn(device,
@@ -64,13 +58,9 @@ index 10a4467..eb8fb94 100644
  			ret = fw_load_from_user_helper(fw, name, device,
  						       opt_flags);
  		}
- 
-
-diff --git a/drivers/net/wireless/ath/ath10k/sdio.c b/drivers/net/wireless/ath/ath10k/sdio.c
-index 7d295ee71534..50670d651cff 100644
 --- a/drivers/net/wireless/ath/ath10k/sdio.c
 +++ b/drivers/net/wireless/ath/ath10k/sdio.c
-@@ -1874,8 +1874,8 @@
+@@ -1874,8 +1874,8 @@ static int ath10k_sdio_hif_map_service_t
  			   ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]);
  		break;
  	default:

target/linux/ipq40xx/patches-4.19/715-essedma-refine-txq-to-be-adaptive-of-cpus-and-netdev.patch

@@ -1,8 +1,6 @@
-diff --git a/drivers/net/ethernet/qualcomm/essedma/edma.c b/drivers/net/ethernet/qualcomm/essedma/edma.c
-index 724f355..7a16236 100644
 --- a/drivers/net/ethernet/qualcomm/essedma/edma.c
 +++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
-@@ -22,14 +22,6 @@ extern struct net_device *edma_netdev[EDMA_MAX_PORTID_SUPPORTED];
+@@ -22,14 +22,6 @@ extern struct net_device *edma_netdev[ED
  bool edma_stp_rstp;
  u16 edma_ath_eth_type;
  
@@ -17,7 +15,7 @@ index 724f355..7a16236 100644
  /* edma_alloc_tx_ring()
   *	Allocate Tx descriptors ring
   */
-@@ -1014,13 +1006,14 @@ static inline u16 edma_tpd_available(struct edma_common_info *edma_cinfo,
+@@ -1016,13 +1008,14 @@ static inline u16 edma_tpd_available(str
  /* edma_tx_queue_get()
   *	Get the starting number of  the queue
   */
@@ -34,7 +32,7 @@ index 724f355..7a16236 100644
  }
  
  /* edma_tx_update_hw_idx()
-@@ -1389,8 +1382,9 @@ netdev_tx_t edma_xmit(struct sk_buff *skb,
+@@ -1391,8 +1384,9 @@ netdev_tx_t edma_xmit(struct sk_buff *sk
  	}
  
  	/* this will be one of the 4 TX queues exposed to linux kernel */
@@ -46,7 +44,7 @@ index 724f355..7a16236 100644
  	etdr = edma_cinfo->tpd_ring[queue_id];
  	nq = netdev_get_tx_queue(net_dev, txq_id);
  
-@@ -1871,8 +1865,8 @@ void edma_free_irqs(struct edma_adapter *adapter)
+@@ -1875,8 +1869,8 @@ void edma_free_irqs(struct edma_adapter
  	int i, j;
  	int k = ((edma_cinfo->num_rx_queues == 4) ? 1 : 2);
  
@@ -57,8 +55,6 @@ index 724f355..7a16236 100644
  			free_irq(edma_cinfo->tx_irq[j], &edma_cinfo->edma_percpu_info[i]);
  
  		for (j = edma_cinfo->edma_percpu_info[i].rx_start; j < (edma_cinfo->edma_percpu_info[i].rx_start + k); j++)
-diff --git a/drivers/net/ethernet/qualcomm/essedma/edma.h b/drivers/net/ethernet/qualcomm/essedma/edma.h
-index 015e5f5..abb0bd5 100644
 --- a/drivers/net/ethernet/qualcomm/essedma/edma.h
 +++ b/drivers/net/ethernet/qualcomm/essedma/edma.h
 @@ -324,6 +324,7 @@ struct edma_common_info {
@@ -87,11 +83,9 @@ index 015e5f5..abb0bd5 100644
  	u32 default_vlan_tag; /* vlan tag */
  	u32 dp_bitmap;
  	uint8_t phy_id[MII_BUS_ID_SIZE + 3];
-diff --git a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
-index d53c63b..2d4770c 100644
 --- a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
 +++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
-@@ -719,11 +719,7 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -719,11 +719,7 @@ static int edma_axi_probe(struct platfor
  	int i, j, k, err = 0;
  	int portid_bmp;
  	int idx = 0, idx_mac = 0;
@@ -104,7 +98,7 @@ index d53c63b..2d4770c 100644
  
  	if ((num_rxq != 4) && (num_rxq != 8)) {
  		dev_err(&pdev->dev, "Invalid RX queue, edma probe failed\n");
-@@ -747,7 +743,7 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -747,7 +743,7 @@ static int edma_axi_probe(struct platfor
  	/* Initialize the netdev array before allocation
  	 * to avoid double free
  	 */
@@ -113,7 +107,7 @@ index d53c63b..2d4770c 100644
  		edma_netdev[i] = NULL;
  
  	for (i = 0 ; i < edma_cinfo->num_gmac ; i++) {
-@@ -768,8 +764,11 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -768,8 +764,11 @@ static int edma_axi_probe(struct platfor
  
  	/* Fill ring details */
  	edma_cinfo->num_tx_queues = EDMA_MAX_TRANSMIT_QUEUE;
@@ -126,7 +120,7 @@ index d53c63b..2d4770c 100644
  
  	/* Update num rx queues based on module parameter */
  	edma_cinfo->num_rx_queues = num_rxq;
-@@ -939,6 +938,13 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -939,6 +938,13 @@ static int edma_axi_probe(struct platfor
  		idx_mac++;
  	}
  
@@ -140,7 +134,7 @@ index d53c63b..2d4770c 100644
  	/* Populate the adapter structure register the netdevice */
  	for (i = 0; i < edma_cinfo->num_gmac; i++) {
  		int k, m;
-@@ -946,17 +952,16 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -946,17 +952,16 @@ static int edma_axi_probe(struct platfor
  		adapter[i] = netdev_priv(edma_netdev[i]);
  		adapter[i]->netdev = edma_netdev[i];
  		adapter[i]->pdev = pdev;
@@ -162,7 +156,7 @@ index d53c63b..2d4770c 100644
  				if (edma_fill_netdev(edma_cinfo, k, i, j)) {
  					pr_err("Netdev overflow Error\n");
  					goto err_register;
-@@ -1109,9 +1114,12 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -1109,9 +1114,12 @@ static int edma_axi_probe(struct platfor
  	/* populate per_core_info, do a napi_Add, request 16 TX irqs,
  	 * 8 RX irqs, do a napi enable
  	 */
@@ -176,7 +170,7 @@ index d53c63b..2d4770c 100644
  		edma_cinfo->edma_percpu_info[i].napi.state = 0;
  
  		netif_napi_add(edma_netdev[0],
-@@ -1131,7 +1139,7 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -1131,7 +1139,7 @@ static int edma_axi_probe(struct platfor
  
  		/* Request irq per core */
  		for (j = edma_cinfo->edma_percpu_info[i].tx_start;
@@ -185,7 +179,7 @@ index d53c63b..2d4770c 100644
  			sprintf(&edma_tx_irq[j][0], "edma_eth_tx%d", j);
  			err = request_irq(edma_cinfo->tx_irq[j],
  					  edma_interrupt,
-@@ -1253,7 +1261,7 @@ static int edma_axi_probe(struct platform_device *pdev)
+@@ -1253,7 +1261,7 @@ err_configure:
  #endif
  err_rmap_add_fail:
  	edma_free_irqs(adapter[0]);
@@ -194,7 +188,7 @@ index d53c63b..2d4770c 100644
  		napi_disable(&edma_cinfo->edma_percpu_info[i].napi);
  err_reset:
  err_unregister_sysctl_tbl:
-@@ -1301,7 +1309,7 @@ static int edma_axi_remove(struct platform_device *pdev)
+@@ -1301,7 +1309,7 @@ static int edma_axi_remove(struct platfo
  		unregister_netdev(edma_netdev[i]);
  
  	edma_stop_rx_tx(hw);

target/linux/ipq806x/patches-4.19/0071-1-PCI-qcom-Fixed-IPQ806x-specific-clocks.patch

@@ -9,7 +9,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
 
 --- a/drivers/pci/controller/dwc/pcie-qcom.c
 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -85,6 +85,8 @@ struct qcom_pcie_resources_2_1_0 {
+@@ -103,6 +103,8 @@ struct qcom_pcie_resources_2_1_0 {
  	struct clk *iface_clk;
  	struct clk *core_clk;
  	struct clk *phy_clk;
@@ -18,7 +18,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  	struct reset_control *pci_reset;
  	struct reset_control *axi_reset;
  	struct reset_control *ahb_reset;
-@@ -235,6 +237,14 @@ static int qcom_pcie_get_resources_2_1_0
+@@ -253,6 +255,14 @@ static int qcom_pcie_get_resources_2_1_0
  	if (IS_ERR(res->phy_clk))
  		return PTR_ERR(res->phy_clk);
  
@@ -33,7 +33,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  	res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
  	if (IS_ERR(res->pci_reset))
  		return PTR_ERR(res->pci_reset);
-@@ -267,6 +277,8 @@ static void qcom_pcie_deinit_2_1_0(struc
+@@ -285,6 +295,8 @@ static void qcom_pcie_deinit_2_1_0(struc
  	clk_disable_unprepare(res->iface_clk);
  	clk_disable_unprepare(res->core_clk);
  	clk_disable_unprepare(res->phy_clk);
@@ -42,7 +42,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
  }
  
-@@ -296,16 +308,28 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -315,16 +327,28 @@ static int qcom_pcie_init_2_1_0(struct q
  		goto err_assert_ahb;
  	}
  
@@ -74,7 +74,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  	}
  
  	ret = reset_control_deassert(res->ahb_reset);
-@@ -361,10 +385,14 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -400,10 +424,14 @@ static int qcom_pcie_init_2_1_0(struct q
  	return 0;
  
  err_deassert_ahb:

target/linux/ipq806x/patches-4.19/0071-2-PCI-qcom-Fixed-IPQ806x-PCIE-reset-changes.patch

@@ -9,7 +9,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
 
 --- a/drivers/pci/controller/dwc/pcie-qcom.c
 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -92,6 +92,7 @@ struct qcom_pcie_resources_2_1_0 {
+@@ -110,6 +110,7 @@ struct qcom_pcie_resources_2_1_0 {
  	struct reset_control *ahb_reset;
  	struct reset_control *por_reset;
  	struct reset_control *phy_reset;
@@ -17,7 +17,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  	struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
  };
  
-@@ -261,6 +262,10 @@ static int qcom_pcie_get_resources_2_1_0
+@@ -279,6 +280,10 @@ static int qcom_pcie_get_resources_2_1_0
  	if (IS_ERR(res->por_reset))
  		return PTR_ERR(res->por_reset);
  
@@ -28,7 +28,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  	res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
  	return PTR_ERR_OR_ZERO(res->phy_reset);
  }
-@@ -274,6 +279,7 @@ static void qcom_pcie_deinit_2_1_0(struc
+@@ -292,6 +297,7 @@ static void qcom_pcie_deinit_2_1_0(struc
  	reset_control_assert(res->ahb_reset);
  	reset_control_assert(res->por_reset);
  	reset_control_assert(res->pci_reset);
@@ -36,7 +36,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  	clk_disable_unprepare(res->iface_clk);
  	clk_disable_unprepare(res->core_clk);
  	clk_disable_unprepare(res->phy_clk);
-@@ -290,15 +296,21 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -309,15 +315,21 @@ static int qcom_pcie_init_2_1_0(struct q
  	u32 val;
  	int ret;
  

target/linux/ipq806x/patches-4.19/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch

@@ -1,124 +0,0 @@
-From eddd13215d0f2b549ebc5f0e8796d5b1231f90a0 Mon Sep 17 00:00:00 2001
-From: Sham Muthayyan <smuthayy@codeaurora.org>
-Date: Tue, 19 Jul 2016 19:58:22 +0530
-Subject: PCI: qcom: Fixed IPQ806x PCIE init changes
-
-Change-Id: Ic319b1aec27a47809284759f8fcb6a8815b7cf7e
-Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
----
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -45,7 +45,13 @@
- #define PCIE_CAP_CPL_TIMEOUT_DISABLE		0x10
- 
- #define PCIE20_PARF_PHY_CTRL			0x40
-+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK	(0x1f << 16)
-+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)		(x << 16)
-+
- #define PCIE20_PARF_PHY_REFCLK			0x4C
-+#define REF_SSP_EN				BIT(16)
-+#define REF_USE_PAD				BIT(12)
-+
- #define PCIE20_PARF_DBI_BASE_ADDR		0x168
- #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE		0x16C
- #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL	0x174
-@@ -76,6 +82,18 @@
- #define DBI_RO_WR_EN				1
- 
- #define PERST_DELAY_US				1000
-+/* PARF registers */
-+#define PCIE20_PARF_PCS_DEEMPH			0x34
-+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)		(x << 16)
-+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)	(x << 8)
-+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)	(x << 0)
-+
-+#define PCIE20_PARF_PCS_SWING			0x38
-+#define PCS_SWING_TX_SWING_FULL(x)		(x << 8)
-+#define PCS_SWING_TX_SWING_LOW(x)		(x << 0)
-+
-+#define PCIE20_PARF_CONFIG_BITS			0x50
-+#define PHY_RX0_EQ(x)				(x << 24)
- 
- #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
- #define SLV_ADDR_SPACE_SZ			0x10000000
-@@ -94,6 +112,7 @@ struct qcom_pcie_resources_2_1_0 {
- 	struct reset_control *phy_reset;
- 	struct reset_control *ext_reset;
- 	struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
-+	uint8_t phy_tx0_term_offset;
- };
- 
- struct qcom_pcie_resources_1_0_0 {
-@@ -173,6 +192,16 @@ struct qcom_pcie {
- 
- #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)
- 
-+static inline void
-+writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask)
-+{
-+	u32 val = readl(addr);
-+
-+	val &= ~clear_mask;
-+	val |= set_mask;
-+	writel(val, addr);
-+}
-+
- static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
- {
- 	gpiod_set_value_cansleep(pcie->reset, 1);
-@@ -266,6 +295,10 @@ static int qcom_pcie_get_resources_2_1_0
- 	if (IS_ERR(res->ext_reset))
- 		return PTR_ERR(res->ext_reset);
- 
-+	if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset",
-+				&res->phy_tx0_term_offset))
-+		res->phy_tx0_term_offset = 0;
-+
- 	res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
- 	return PTR_ERR_OR_ZERO(res->phy_reset);
- }
-@@ -293,7 +326,6 @@ static int qcom_pcie_init_2_1_0(struct q
- 	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
- 	struct dw_pcie *pci = pcie->pci;
- 	struct device *dev = pci->dev;
--	u32 val;
- 	int ret;
- 
- 	ret = reset_control_assert(res->ahb_reset);
-@@ -350,15 +382,26 @@ static int qcom_pcie_init_2_1_0(struct q
- 		goto err_deassert_ahb;
- 	}
- 
--	/* enable PCIe clocks and resets */
--	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
--	val &= ~BIT(0);
--	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
--
--	/* enable external reference clock */
--	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
--	val |= BIT(16);
--	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
-+	writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
-+
-+	/* Set Tx termination offset */
-+	writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL,
-+		      PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK,
-+		      PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset));
-+
-+	/* PARF programming */
-+	writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
-+	       PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
-+	       PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
-+	       pcie->parf + PCIE20_PARF_PCS_DEEMPH);
-+	writel(PCS_SWING_TX_SWING_FULL(0x78) |
-+	       PCS_SWING_TX_SWING_LOW(0x78),
-+	       pcie->parf + PCIE20_PARF_PCS_SWING);
-+	writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
-+
-+	/* Enable reference clock */
-+	writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK,
-+		      REF_USE_PAD, REF_SSP_EN);
- 
- 	ret = reset_control_deassert(res->phy_reset);
- 	if (ret) {

target/linux/ipq806x/patches-4.19/0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x.patch

@@ -42,7 +42,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  #define PCIE20_PARF_Q2A_FLUSH			0x1AC
  
  #define PCIE20_MISC_CONTROL_1_REG		0x8BC
-@@ -240,6 +264,57 @@ static void qcom_pcie_2_1_0_ltssm_enable
+@@ -229,6 +253,57 @@ static void qcom_pcie_2_1_0_ltssm_enable
  	writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
  }
  
@@ -100,7 +100,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
  {
  	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
-@@ -437,6 +512,9 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -433,6 +508,9 @@ static int qcom_pcie_init_2_1_0(struct q
  	writel(CFG_BRIDGE_SB_INIT,
  	       pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
  

target/linux/ipq806x/patches-4.19/0071-6-PCI-qcom-Force-GEN1-support.patch

@@ -18,7 +18,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3
  struct qcom_pcie_resources_2_1_0 {
  	struct clk *iface_clk;
-@@ -212,6 +214,7 @@ struct qcom_pcie {
+@@ -211,6 +213,7 @@ struct qcom_pcie {
  	struct phy *phy;
  	struct gpio_desc *reset;
  	const struct qcom_pcie_ops *ops;
@@ -26,7 +26,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  };
  
  #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)
-@@ -504,6 +507,11 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -500,6 +503,11 @@ static int qcom_pcie_init_2_1_0(struct q
  
  	/* wait for clock acquisition */
  	usleep_range(1000, 1500);
@@ -38,7 +38,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  
  
  	/* Set the Max TLP size to 2K, instead of using default of 4K */
-@@ -1367,6 +1375,8 @@ static int qcom_pcie_probe(struct platfo
+@@ -1363,6 +1371,8 @@ static int qcom_pcie_probe(struct platfo
  	struct dw_pcie *pci;
  	struct qcom_pcie *pcie;
  	int ret;
@@ -47,7 +47,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  
  	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
  	if (!pcie)
-@@ -1397,6 +1407,9 @@ static int qcom_pcie_probe(struct platfo
+@@ -1393,6 +1403,9 @@ static int qcom_pcie_probe(struct platfo
  		goto err_pm_runtime_put;
  	}
  

target/linux/ipq806x/patches-4.19/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch

@@ -31,7 +31,7 @@ Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
  #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3
  struct qcom_pcie_resources_2_1_0 {
  	struct clk *iface_clk;
-@@ -1475,6 +1483,35 @@ err_pm_runtime_put:
+@@ -1471,6 +1479,35 @@ err_pm_runtime_put:
  	return ret;
  }
  

target/linux/ipq806x/patches-4.19/0071-8-pcie-qcom-Fixed-pcie_phy_clk-branch-issue.patch

@@ -38,7 +38,7 @@ Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
 
 --- a/drivers/pci/controller/dwc/pcie-qcom.c
 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -393,6 +393,7 @@ static void qcom_pcie_deinit_2_1_0(struc
+@@ -378,6 +378,7 @@ static void qcom_pcie_deinit_2_1_0(struc
  {
  	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
  
@@ -46,7 +46,7 @@ Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
  	reset_control_assert(res->pci_reset);
  	reset_control_assert(res->axi_reset);
  	reset_control_assert(res->ahb_reset);
-@@ -401,7 +402,6 @@ static void qcom_pcie_deinit_2_1_0(struc
+@@ -386,7 +387,6 @@ static void qcom_pcie_deinit_2_1_0(struc
  	reset_control_assert(res->ext_reset);
  	clk_disable_unprepare(res->iface_clk);
  	clk_disable_unprepare(res->core_clk);
@@ -54,7 +54,7 @@ Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
  	clk_disable_unprepare(res->aux_clk);
  	clk_disable_unprepare(res->ref_clk);
  	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
-@@ -444,12 +444,6 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -431,12 +431,6 @@ static int qcom_pcie_init_2_1_0(struct q
  		goto err_clk_core;
  	}
  
@@ -67,7 +67,7 @@ Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
  	ret = clk_prepare_enable(res->aux_clk);
  	if (ret) {
  		dev_err(dev, "cannot prepare/enable aux clock\n");
-@@ -513,6 +507,12 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -509,6 +503,12 @@ static int qcom_pcie_init_2_1_0(struct q
  		return ret;
  	}
  
@@ -80,7 +80,7 @@ Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
  	/* wait for clock acquisition */
  	usleep_range(1000, 1500);
  	if (pcie->force_gen1) {
-@@ -538,8 +538,6 @@ err_deassert_ahb:
+@@ -534,8 +534,6 @@ err_deassert_ahb:
  err_clk_ref:
  	clk_disable_unprepare(res->aux_clk);
  err_clk_aux:

target/linux/ipq806x/patches-4.19/0071-9-pcie-qcom-change-duplicate-pci-reset-to-phy-reset.patch

@@ -14,7 +14,7 @@ Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
 
 --- a/drivers/pci/controller/dwc/pcie-qcom.c
 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -394,7 +394,7 @@ static void qcom_pcie_deinit_2_1_0(struc
+@@ -379,7 +379,7 @@ static void qcom_pcie_deinit_2_1_0(struc
  	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
  
  	clk_disable_unprepare(res->phy_clk);

target/linux/lantiq/patches-4.19/0001-MIPS-lantiq-add-pcie-driver.patch

@@ -5494,7 +5494,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	  (transaction layer end-to-end CRC checking).
 --- a/include/linux/pci.h
 +++ b/include/linux/pci.h
-@@ -1325,6 +1325,8 @@ void pci_walk_bus(struct pci_bus *top, i
+@@ -1328,6 +1328,8 @@ void pci_walk_bus(struct pci_bus *top, i
  		  void *userdata);
  int pci_cfg_space_size(struct pci_dev *dev);
  unsigned char pci_bus_max_busnr(struct pci_bus *bus);

target/linux/mvebu/patches-4.19/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch

@@ -15,7 +15,7 @@ Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
 
 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
 +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-@@ -60,9 +60,31 @@
+@@ -66,9 +66,31 @@
  	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
  	marvell,pad-type = "sd";
  	vqmmc-supply = <&vcc_sd_reg1>;

target/linux/mvebu/patches-4.19/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch

@@ -29,7 +29,7 @@ Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
 
 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
 +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-@@ -90,25 +90,9 @@
+@@ -96,25 +96,9 @@
  
  	flash@0 {
  		reg = <0>;

target/linux/mvebu/patches-4.19/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch

@@ -15,7 +15,7 @@ Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
 
 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
 +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-@@ -132,7 +132,7 @@
+@@ -138,7 +138,7 @@
  
  		dsa,member = <0 0>;
  

target/linux/mvebu/patches-4.19/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch

@@ -62,7 +62,7 @@ Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
 
 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
 +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-@@ -46,6 +46,8 @@
+@@ -52,6 +52,8 @@
  /* J9 */
  &pcie0 {
  	status = "okay";