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Merge Official Source

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2022-09-03 17:00:03 +08:00
commit a6efa19e50
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GPG Key ID: 6850B6345C862176
93 changed files with 1114 additions and 818 deletions
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4
include/kernel-5.10
View File

@ -1,2 +1,2 @@
LINUX_VERSION-5.10 = .138
LINUX_KERNEL_HASH-5.10.138 = 29a003bb8e0e3a45942f703370fb0b3460e6fdcbbad37424423c9cf831ab5ba8
LINUX_VERSION-5.10 = .139
LINUX_KERNEL_HASH-5.10.139 = 1c002ac275a44934a280a158a136735bf6665b26a42d344023b4648a7898bef1

4
include/kernel-5.15
View File

@ -1,2 +1,2 @@
LINUX_VERSION-5.15 = .63
LINUX_KERNEL_HASH-5.15.63 = 6dd3cd1e5a629d0002bc6c6ec7e8ea96710104f38664122dd56c83dfd4eb7341
LINUX_VERSION-5.15 = .64
LINUX_KERNEL_HASH-5.15.64 = c6a1d38c6fa3798341372d5cf0088ae806ccdc827e31ecbff8988e097ba5de50

6
package/boot/arm-trusted-firmware-mediatek/Makefile
View File

@ -13,9 +13,9 @@ PKG_RELEASE:=$(AUTORELEASE)
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/mtk-openwrt/arm-trusted-firmware.git
PKG_SOURCE_DATE:=2022-08-18
PKG_SOURCE_VERSION:=9c9c49945c24634e4ae6cd924dbb88cf85c7926d
PKG_MIRROR_HASH:=26b474f40c02da12b7bed56597aeef209757ad1b40a4f0a652794954018b2198
PKG_SOURCE_DATE:=2022-08-31
PKG_SOURCE_VERSION:=7539348480af57c6d0db95aba6381f3ee7483779
PKG_MIRROR_HASH:=125090124d77753acc379b3b124100978c1ecb3da37c4983ba9644b433b7eb08
PKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>

32
package/boot/arm-trusted-firmware-mediatek/patches/0001-spi-nor-add-more-Winbond-device-IDs.patch
View File

@ -1,32 +0,0 @@
From daaac60b504e6d5e77156ad0dc3dceca8b786e2d Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Sat, 27 Aug 2022 03:41:57 +0100
Subject: [PATCH] spi-nor: add more Winbond device IDs
Add device IDs for Winbond W25Q256 and W25Q512 variants.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/mtd/nor/spi_nor.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
--- a/drivers/mtd/nor/spi_nor.c
+++ b/drivers/mtd/nor/spi_nor.c
@@ -327,8 +327,15 @@ int spi_nor_read(unsigned int offset, ui
struct nor_device_info nor_flash_info_table[] = {
{"MX25L51245G", {0xC2, 0x20, 0x1A}, 0x4000000, 0},
- {"W25Q256JW",{0xEF,0x80, 0x19}, 0x2000000, 0},
- {"MX25U25635",{0xC2, 0x25, 0x39}, 0x2000000, 0}
+ {"W25Q256JV-IM", {0xEF, 0x70, 0x19}, 0x2000000, 0},
+ {"W25Q256JV-IQ", {0xEF, 0x40, 0x19}, 0x2000000, 0},
+ {"W25Q256JW", {0xEF, 0x60, 0x19}, 0x2000000, 0},
+ {"W25Q256JW-IM", {0xEF, 0x80, 0x19}, 0x2000000, 0},
+ {"W25Q512JV-IM", {0xEF, 0x70, 0x20}, 0x4000000, 0},
+ {"W25Q512JV-IQ", {0xEF, 0x40, 0x20}, 0x4000000, 0},
+ {"W25Q512NW-IM", {0xEF, 0x80, 0x20}, 0x4000000, 0},
+ {"W25Q512NW-IQ/IN", {0xEF, 0x60, 0x20}, 0x4000000, 0},
+ {"MX25U25635", {0xC2, 0x25, 0x39}, 0x2000000, 0}
};

40
package/boot/arm-trusted-firmware-mediatek/patches/0002-mediatek-mt7622-initialize-watchdog-after-DDR-init.patch
View File

@ -1,40 +0,0 @@
From 2a012775b3ab6e72091c8be1c2d4bf5972407eb5 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Sat, 27 Aug 2022 21:38:33 +0100
Subject: [PATCH] mediatek: mt7622: initialize watchdog after DDR init
Initializing the WDT before memory calibration breaks reboot at least
on some MT7622 boards like the Bananapi BPi-R64:
NOTICE: BL2: v2.7(release):OpenWrt v2022-08-18-9c9c4994-2 (mt7622-emmc-2ddr)
NOTICE: BL2: Built : 04:00:25, Aug 27 2022
ERROR: Cannot find any pass-window
ERROR: no DATLAT taps pass, DATLAT calibration fail!
ERROR: DATLAT calibration fail, write back to 20!
ERROR: EMI: complex R/W mem test failed: -2
Move watchdog initialization to happen only after memory initialization
has completed to avoid the problem.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
plat/mediatek/mt7622/bl2_plat_setup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/plat/mediatek/mt7622/bl2_plat_setup.c
+++ b/plat/mediatek/mt7622/bl2_plat_setup.c
@@ -277,7 +277,6 @@ void bl2_platform_setup(void)
plat_mt_cpuxgpt_init();
generic_delay_timer_init();
- mtk_wdt_init();
mtk_pin_init();
#ifndef USING_BL2PL
mtk_pll_init();
@@ -285,6 +284,7 @@ void bl2_platform_setup(void)
mtk_pwrap_init();
mtk_pmic_init();
mtk_mem_init();
+ mtk_wdt_init();
mtk_io_setup();
}

8
package/boot/at91bootstrap/Makefile
View File

@ -136,12 +136,6 @@ define AT91Bootstrap/sama5d27_som1_eksd_uboot
BUILD_DEVICES:=microchip_sama5d27-som1-ek
endef
define AT91Bootstrap/sama5d27_som1_eksd1_uboot
TITLE:=AT91Bootstrap for SAMA5D27 SOM1 Ek (SDcard1)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d27-som1-ek
endef
define AT91Bootstrap/sama5d27_som1_ekqspi_uboot
TITLE:=AT91Bootstrap for SAMA5D27 SOM1 Ek (QSPI Flash)
BUILD_SUBTARGET:=sama5
@ -193,7 +187,7 @@ AT91BOOTSTRAP_TARGETS := \
sama5d4_xplainednf_uboot_secure \
sama5d4_xplaineddf_uboot_secure \
sama5d4_xplainedsd_uboot_secure \
sama5d27_som1_eksd1_uboot \
sama5d27_som1_eksd_uboot \
sama5d27_som1_ekqspi_uboot \
sama5d27_wlsom1_eksd_uboot \
sama5d27_wlsom1_ekdf_qspi_uboot \

6
package/boot/uboot-at91/Makefile
View File

@ -107,8 +107,8 @@ define U-Boot/sama5d4_xplained_nandflash
BUILD_DEVICES:=microchip_sama5d3-xplained
endef
define U-Boot/sama5d27_som1_ek_mmc1
NAME:=SAMA5D27 SOM1 Ek (SDCard1)
define U-Boot/sama5d27_som1_ek_mmc
NAME:=SAMA5D27 SOM1 Ek (SDCard0)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d27-som1-ek
endef
@ -163,7 +163,7 @@ UBOOT_TARGETS := \
sama5d4_xplained_mmc \
sama5d4_xplained_spiflash \
sama5d4_xplained_nandflash\
sama5d27_som1_ek_mmc1 \
sama5d27_som1_ek_mmc \
sama5d27_som1_ek_qspiflash \
sama5d27_wlsom1_ek_mmc \
sama5d27_wlsom1_ek_qspiflash \

4
package/boot/uboot-envtools/Makefile
View File

@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=uboot-envtools
PKG_DISTNAME:=u-boot
PKG_VERSION:=2022.01
PKG_VERSION:=2022.07
PKG_RELEASE:=$(AUTORELEASE)
PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2
@ -17,7 +17,7 @@ PKG_SOURCE_URL:= \
https://ftp.denx.de/pub/u-boot \
https://mirror.cyberbits.eu/u-boot \
ftp://ftp.denx.de/pub/u-boot
PKG_HASH:=81b4543227db228c03f8a1bf5ddbc813b0bb8f6555ce46064ef721a6fc680413
PKG_HASH:=92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e
PKG_SOURCE_SUBDIR:=$(PKG_DISTNAME)-$(PKG_VERSION)
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_DISTNAME)-$(PKG_VERSION)

144
package/boot/uboot-envtools/patches/100-fw_env-make-flash_io-take-buffer-as-an-argument.patch
View File

@ -1,144 +0,0 @@
From f178f7c9550c4fd9c644f79a1eb2dafa5bcdce25 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Wed, 12 Jan 2022 12:47:05 +0100
Subject: [PATCH] fw_env: make flash_io() take buffer as an argument
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
It's usually easier to understand code & follow it if all arguments are
passed explicitly. Many coding styles also discourage using global
variables.
Behaviour of flash_io() was a bit unintuitive as it was writing to a
buffer referenced in a global struct. That required developers to
remember how it works and sometimes required hacking "environment"
global struct variable to read data into a proper buffer.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
tools/env/fw_env.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -346,7 +346,7 @@ static int ubi_write(int fd, const void
return 0;
}
-static int flash_io(int mode);
+static int flash_io(int mode, void *buf, size_t count);
static int parse_config(struct env_opts *opts);
#if defined(CONFIG_FILE)
@@ -516,7 +516,7 @@ int fw_env_flush(struct env_opts *opts)
*environment.crc = crc32(0, (uint8_t *) environment.data, ENV_SIZE);
/* write environment back to flash */
- if (flash_io(O_RDWR)) {
+ if (flash_io(O_RDWR, environment.image, CUR_ENVSIZE)) {
fprintf(stderr, "Error: can't write fw_env to flash\n");
return -1;
}
@@ -1185,7 +1185,8 @@ static int flash_flag_obsolete(int dev,
return rc;
}
-static int flash_write(int fd_current, int fd_target, int dev_target)
+static int flash_write(int fd_current, int fd_target, int dev_target, void *buf,
+ size_t count)
{
int rc;
@@ -1212,11 +1213,10 @@ static int flash_write(int fd_current, i
if (IS_UBI(dev_target)) {
if (ubi_update_start(fd_target, CUR_ENVSIZE) < 0)
return -1;
- return ubi_write(fd_target, environment.image, CUR_ENVSIZE);
+ return ubi_write(fd_target, buf, count);
}
- rc = flash_write_buf(dev_target, fd_target, environment.image,
- CUR_ENVSIZE);
+ rc = flash_write_buf(dev_target, fd_target, buf, count);
if (rc < 0)
return rc;
@@ -1235,17 +1235,17 @@ static int flash_write(int fd_current, i
return 0;
}
-static int flash_read(int fd)
+static int flash_read(int fd, void *buf, size_t count)
{
int rc;
if (IS_UBI(dev_current)) {
DEVTYPE(dev_current) = MTD_ABSENT;
- return ubi_read(fd, environment.image, CUR_ENVSIZE);
+ return ubi_read(fd, buf, count);
}
- rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE,
+ rc = flash_read_buf(dev_current, fd, buf, count,
DEVOFFSET(dev_current));
if (rc != CUR_ENVSIZE)
return -1;
@@ -1291,7 +1291,7 @@ err:
return rc;
}
-static int flash_io_write(int fd_current)
+static int flash_io_write(int fd_current, void *buf, size_t count)
{
int fd_target = -1, rc, dev_target;
const char *dname, *target_temp = NULL;
@@ -1322,7 +1322,7 @@ static int flash_io_write(int fd_current
fd_target = fd_current;
}
- rc = flash_write(fd_current, fd_target, dev_target);
+ rc = flash_write(fd_current, fd_target, dev_target, buf, count);
if (fsync(fd_current) && !(errno == EINVAL || errno == EROFS)) {
fprintf(stderr,
@@ -1377,7 +1377,7 @@ static int flash_io_write(int fd_current
return rc;
}
-static int flash_io(int mode)
+static int flash_io(int mode, void *buf, size_t count)
{
int fd_current, rc;
@@ -1391,9 +1391,9 @@ static int flash_io(int mode)
}
if (mode == O_RDWR) {
- rc = flash_io_write(fd_current);
+ rc = flash_io_write(fd_current, buf, count);
} else {
- rc = flash_read(fd_current);
+ rc = flash_read(fd_current, buf, count);
}
if (close(fd_current)) {
@@ -1455,7 +1455,7 @@ int fw_env_open(struct env_opts *opts)
}
dev_current = 0;
- if (flash_io(O_RDONLY)) {
+ if (flash_io(O_RDONLY, environment.image, CUR_ENVSIZE)) {
ret = -EIO;
goto open_cleanup;
}
@@ -1490,7 +1490,7 @@ int fw_env_open(struct env_opts *opts)
* other pointers in environment still point inside addr0
*/
environment.image = addr1;
- if (flash_io(O_RDONLY)) {
+ if (flash_io(O_RDONLY, environment.image, CUR_ENVSIZE)) {
ret = -EIO;
goto open_cleanup;
}

173
package/boot/uboot-envtools/patches/101-fw_env-simplify-logic-code-paths-in-the-fw_env_open.patch
View File

@ -1,173 +0,0 @@
From 07c79dd5fdeaefb39c9e7a97f3b66de63109a18d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Wed, 12 Jan 2022 12:47:06 +0100
Subject: [PATCH] fw_env: simplify logic & code paths in the fw_env_open()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Environment variables can be stored in two formats:
1. Single entry with header containing CRC32
2. Two entries with extra flags field in each entry header
For that reason fw_env_open() has two main code paths and there are
pointers for CRC32/flags/data.
Previous implementation was a bit hard to follow:
1. It was checking for used format twice (in reversed order each time)
2. It was setting "environment" global struct fields to some temporary
values that required extra comments explaining it
This change simplifies that code:
1. It introduces two clear code paths
2. It sets "environment" global struct fields values only once it really
knows them
To be fair there are *two* crc32() calls now and an extra pointer
variable but that should be cheap enough and worth it.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
tools/env/fw_env.c | 77 +++++++++++++++++++---------------------------
1 file changed, 31 insertions(+), 46 deletions(-)
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -1421,9 +1421,6 @@ int fw_env_open(struct env_opts *opts)
int ret;
- struct env_image_single *single;
- struct env_image_redundant *redundant;
-
if (!opts)
opts = &default_opts;
@@ -1439,40 +1436,37 @@ int fw_env_open(struct env_opts *opts)
goto open_cleanup;
}
- /* read environment from FLASH to local buffer */
- environment.image = addr0;
-
- if (have_redund_env) {
- redundant = addr0;
- environment.crc = &redundant->crc;
- environment.flags = &redundant->flags;
- environment.data = redundant->data;
- } else {
- single = addr0;
- environment.crc = &single->crc;
- environment.flags = NULL;
- environment.data = single->data;
- }
-
dev_current = 0;
- if (flash_io(O_RDONLY, environment.image, CUR_ENVSIZE)) {
+ if (flash_io(O_RDONLY, addr0, CUR_ENVSIZE)) {
ret = -EIO;
goto open_cleanup;
}
- crc0 = crc32(0, (uint8_t *)environment.data, ENV_SIZE);
-
- crc0_ok = (crc0 == *environment.crc);
if (!have_redund_env) {
+ struct env_image_single *single = addr0;
+
+ crc0 = crc32(0, (uint8_t *)single->data, ENV_SIZE);
+ crc0_ok = (crc0 == single->crc);
if (!crc0_ok) {
fprintf(stderr,
"Warning: Bad CRC, using default environment\n");
- memcpy(environment.data, default_environment,
+ memcpy(single->data, default_environment,
sizeof(default_environment));
environment.dirty = 1;
}
+
+ environment.image = addr0;
+ environment.crc = &single->crc;
+ environment.flags = NULL;
+ environment.data = single->data;
} else {
- flag0 = *environment.flags;
+ struct env_image_redundant *redundant0 = addr0;
+ struct env_image_redundant *redundant1;
+
+ crc0 = crc32(0, (uint8_t *)redundant0->data, ENV_SIZE);
+ crc0_ok = (crc0 == redundant0->crc);
+
+ flag0 = redundant0->flags;
dev_current = 1;
addr1 = calloc(1, CUR_ENVSIZE);
@@ -1483,14 +1477,9 @@ int fw_env_open(struct env_opts *opts)
ret = -ENOMEM;
goto open_cleanup;
}
- redundant = addr1;
+ redundant1 = addr1;
- /*
- * have to set environment.image for flash_read(), careful -
- * other pointers in environment still point inside addr0
- */
- environment.image = addr1;
- if (flash_io(O_RDONLY, environment.image, CUR_ENVSIZE)) {
+ if (flash_io(O_RDONLY, addr1, CUR_ENVSIZE)) {
ret = -EIO;
goto open_cleanup;
}
@@ -1518,18 +1507,12 @@ int fw_env_open(struct env_opts *opts)
goto open_cleanup;
}
- crc1 = crc32(0, (uint8_t *)redundant->data, ENV_SIZE);
+ crc1 = crc32(0, (uint8_t *)redundant1->data, ENV_SIZE);
- crc1_ok = (crc1 == redundant->crc);
- flag1 = redundant->flags;
+ crc1_ok = (crc1 == redundant1->crc);
+ flag1 = redundant1->flags;
- /*
- * environment.data still points to ((struct
- * env_image_redundant *)addr0)->data. If the two
- * environments differ, or one has bad crc, force a
- * write-out by marking the environment dirty.
- */
- if (memcmp(environment.data, redundant->data, ENV_SIZE) ||
+ if (memcmp(redundant0->data, redundant1->data, ENV_SIZE) ||
!crc0_ok || !crc1_ok)
environment.dirty = 1;
@@ -1540,7 +1523,7 @@ int fw_env_open(struct env_opts *opts)
} else if (!crc0_ok && !crc1_ok) {
fprintf(stderr,
"Warning: Bad CRC, using default environment\n");
- memcpy(environment.data, default_environment,
+ memcpy(redundant0->data, default_environment,
sizeof(default_environment));
environment.dirty = 1;
dev_current = 0;
@@ -1586,13 +1569,15 @@ int fw_env_open(struct env_opts *opts)
*/
if (dev_current) {
environment.image = addr1;
- environment.crc = &redundant->crc;
- environment.flags = &redundant->flags;
- environment.data = redundant->data;
+ environment.crc = &redundant1->crc;
+ environment.flags = &redundant1->flags;
+ environment.data = redundant1->data;
free(addr0);
} else {
environment.image = addr0;
- /* Other pointers are already set */
+ environment.crc = &redundant0->crc;
+ environment.flags = &redundant0->flags;
+ environment.data = redundant0->data;
free(addr1);
}
#ifdef DEBUG

110
package/boot/uboot-envtools/patches/102-fw_env-add-fallback-to-Linux-s-NVMEM-based-access.patch
View File

@ -1,110 +0,0 @@
From 8142c4554ffaa927529f24427a35f7ee2861793a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Thu, 16 Jun 2022 20:59:03 +0200
Subject: [PATCH] fw_env: add fallback to Linux's NVMEM based access
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
A new DT binding for describing environment data block has been added in
Linux's commit 5db1c2dbc04c ("dt-bindings: nvmem: add U-Boot environment
variables binding"). Once we get a proper Linux NVMEM driver it'll be
possible to use Linux's binary interface for user-space as documented
in the:
https://www.kernel.org/doc/html/latest/driver-api/nvmem.html
This commits makes fw_env fallback to looking for a compatible NVMEM
device in case config file isn't present. In a long term this may make
config files redundant and avoid code (info) duplication.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
tools/env/fw_env.c | 70 ++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 67 insertions(+), 3 deletions(-)
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -1713,6 +1713,67 @@ static int check_device_config(int dev)
return rc;
}
+static int find_nvmem_device(void)
+{
+ const char *path = "/sys/bus/nvmem/devices";
+ struct dirent *dent;
+ char *nvmem = NULL;
+ char comp[256];
+ char buf[32];
+ int bytes;
+ DIR *dir;
+
+ dir = opendir(path);
+ if (!dir) {
+ return -EIO;
+ }
+
+ while (!nvmem && (dent = readdir(dir))) {
+ FILE *fp;
+
+ if (!strcmp(dent->d_name, ".") || !strcmp(dent->d_name, "..")) {
+ continue;
+ }
+
+ bytes = snprintf(comp, sizeof(comp), "%s/%s/of_node/compatible", path, dent->d_name);
+ if (bytes < 0 || bytes == sizeof(comp)) {
+ continue;
+ }
+
+ fp = fopen(comp, "r");
+ if (!fp) {
+ continue;
+ }
+
+ fread(buf, sizeof(buf), 1, fp);
+
+ if (!strcmp(buf, "u-boot,env")) {
+ bytes = asprintf(&nvmem, "%s/%s/nvmem", path, dent->d_name);
+ if (bytes < 0) {
+ nvmem = NULL;
+ }
+ }
+
+ fclose(fp);
+ }
+
+ closedir(dir);
+
+ if (nvmem) {
+ struct stat s;
+
+ stat(nvmem, &s);
+
+ DEVNAME(0) = nvmem;
+ DEVOFFSET(0) = 0;
+ ENVSIZE(0) = s.st_size;
+
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
static int parse_config(struct env_opts *opts)
{
int rc;
@@ -1723,9 +1784,12 @@ static int parse_config(struct env_opts
#if defined(CONFIG_FILE)
/* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */
if (get_config(opts->config_file)) {
- fprintf(stderr, "Cannot parse config file '%s': %m\n",
- opts->config_file);
- return -1;
+ if (find_nvmem_device()) {
+ fprintf(stderr, "Cannot parse config file '%s': %m\n",
+ opts->config_file);
+ fprintf(stderr, "Failed to find NVMEM device\n");
+ return -1;
+ }
}
#else
DEVNAME(0) = DEVICE1_NAME;

494
package/boot/uboot-mediatek/patches/002-0000-serial-Replace-CONFIG_DEBUG_UART_BASE-by-CONFIG_VAL-.patch Normal file
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@ -0,0 +1,494 @@
From b62450cf229c50ad2ce819dd02a09726909cc89a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
Date: Fri, 27 May 2022 22:15:24 +0200
Subject: [PATCH] serial: Replace CONFIG_DEBUG_UART_BASE by
CONFIG_VAL(DEBUG_UART_BASE)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
CONFIG_VAL(DEBUG_UART_BASE) expands to CONFIG_DEBUG_UART_BASE or
CONFIG_SPL_DEBUG_UART_BASE or CONFIG_TPL_DEBUG_UART_BASE and allows boards
to set different values for SPL, TPL and U-Boot Proper.
For ns16550 driver this support is there since commit d293759d55cc
("serial: ns16550: Add support for SPL_DEBUG_UART_BASE").
Signed-off-by: Pali Rohár <pali@kernel.org>
---
arch/arm/mach-uniphier/debug-uart/debug-uart.c | 4 ++--
arch/x86/cpu/apollolake/cpu_common.c | 2 +-
board/eets/pdu001/board.c | 2 +-
drivers/serial/altera_jtag_uart.c | 2 +-
drivers/serial/altera_uart.c | 4 ++--
drivers/serial/atmel_usart.c | 4 ++--
drivers/serial/serial_ar933x.c | 4 ++--
drivers/serial/serial_arc.c | 4 ++--
drivers/serial/serial_bcm6345.c | 4 ++--
drivers/serial/serial_linflexuart.c | 4 ++--
drivers/serial/serial_meson.c | 2 +-
drivers/serial/serial_msm_geni.c | 6 +++---
drivers/serial/serial_mt7620.c | 4 ++--
drivers/serial/serial_mtk.c | 4 ++--
drivers/serial/serial_mvebu_a3700.c | 4 ++--
drivers/serial/serial_mxc.c | 4 ++--
drivers/serial/serial_omap.c | 4 ++--
drivers/serial/serial_pic32.c | 4 ++--
drivers/serial/serial_pl01x.c | 4 ++--
drivers/serial/serial_s5p.c | 4 ++--
drivers/serial/serial_sifive.c | 4 ++--
drivers/serial/serial_stm32.c | 4 ++--
drivers/serial/serial_xuartlite.c | 4 ++--
drivers/serial/serial_zynq.c | 4 ++--
24 files changed, 45 insertions(+), 45 deletions(-)
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c
@@ -18,7 +18,7 @@
static void _debug_uart_putc(int c)
{
- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
;
@@ -57,7 +57,7 @@ void sg_set_iectrl(unsigned int pin)
void _debug_uart_init(void)
{
#ifdef CONFIG_SPL_BUILD
- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
unsigned int divisor;
switch (uniphier_get_soc_id()) {
--- a/arch/x86/cpu/apollolake/cpu_common.c
+++ b/arch/x86/cpu/apollolake/cpu_common.c
@@ -72,7 +72,7 @@ static void pch_uart_init(void)
}
#ifdef CONFIG_DEBUG_UART
- apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
+ apl_uart_init(PCH_DEV_UART, CONFIG_VAL(DEBUG_UART_BASE));
#endif
}
--- a/board/eets/pdu001/board.c
+++ b/board/eets/pdu001/board.c
@@ -273,7 +273,7 @@ void board_debug_uart_init(void)
setup_early_clocks();
/* done by pin controller driver if not debugging */
- enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
+ enable_uart_pin_mux(CONFIG_VAL(DEBUG_UART_BASE));
}
#endif
--- a/drivers/serial/altera_jtag_uart.c
+++ b/drivers/serial/altera_jtag_uart.c
@@ -134,7 +134,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
- struct altera_jtaguart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
+ struct altera_jtaguart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
while (1) {
u32 st = readl(&regs->control);
--- a/drivers/serial/altera_uart.c
+++ b/drivers/serial/altera_uart.c
@@ -123,7 +123,7 @@ U_BOOT_DRIVER(altera_uart) = {
static inline void _debug_uart_init(void)
{
- struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
+ struct altera_uart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
u32 div;
div = (CONFIG_DEBUG_UART_CLOCK / CONFIG_BAUDRATE) - 1;
@@ -132,7 +132,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
- struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
+ struct altera_uart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
while (1) {
u32 st = readl(&regs->status);
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -319,14 +319,14 @@ U_BOOT_DRIVER(serial_atmel) = {
#ifdef CONFIG_DEBUG_UART_ATMEL
static inline void _debug_uart_init(void)
{
- atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
+ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE);
_atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
}
static inline void _debug_uart_putc(int ch)
{
- atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
+ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE);
while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
;
--- a/drivers/serial/serial_ar933x.c
+++ b/drivers/serial/serial_ar933x.c
@@ -199,7 +199,7 @@ U_BOOT_DRIVER(serial_ar933x) = {
static inline void _debug_uart_init(void)
{
- void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
+ void __iomem *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
u32 val, scale, step;
/*
@@ -227,7 +227,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int c)
{
- void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
+ void __iomem *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
u32 data;
do {
--- a/drivers/serial/serial_arc.c
+++ b/drivers/serial/serial_arc.c
@@ -137,7 +137,7 @@ U_BOOT_DRIVER(serial_arc) = {
static inline void _debug_uart_init(void)
{
- struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE;
+ struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_VAL(DEBUG_UART_BASE);
int arc_console_baud = CONFIG_DEBUG_UART_CLOCK / (CONFIG_BAUDRATE * 4) - 1;
writeb(arc_console_baud & 0xff, &regs->baudl);
@@ -146,7 +146,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int c)
{
- struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE;
+ struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_VAL(DEBUG_UART_BASE);
while (!(readb(&regs->status) & UART_TXEMPTY))
;
--- a/drivers/serial/serial_bcm6345.c
+++ b/drivers/serial/serial_bcm6345.c
@@ -269,7 +269,7 @@ U_BOOT_DRIVER(bcm6345_serial) = {
#ifdef CONFIG_DEBUG_UART_BCM6345
static inline void _debug_uart_init(void)
{
- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
}
@@ -285,7 +285,7 @@ static inline void wait_xfered(void __io
static inline void _debug_uart_putc(int ch)
{
- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
wait_xfered(base);
writel(ch, base + UART_FIFO_REG);
--- a/drivers/serial/serial_linflexuart.c
+++ b/drivers/serial/serial_linflexuart.c
@@ -201,14 +201,14 @@ U_BOOT_DRIVER(serial_linflex) = {
static inline void _debug_uart_init(void)
{
- struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE;
+ struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE);
linflex_serial_init_internal(base);
}
static inline void _debug_uart_putc(int ch)
{
- struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE;
+ struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE);
/* XXX: Is this OK? Should this use the non-DM version? */
_linflex_serial_putc(base, ch);
--- a/drivers/serial/serial_meson.c
+++ b/drivers/serial/serial_meson.c
@@ -182,7 +182,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
- struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE;
+ struct meson_uart *regs = (struct meson_uart *)CONFIG_VAL(DEBUG_UART_BASE);
while (readl(&regs->status) & AML_UART_TX_FULL)
;
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -569,7 +569,7 @@ U_BOOT_DRIVER(serial_msm_geni) = {
#ifdef CONFIG_DEBUG_UART_MSM_GENI
static struct msm_serial_data init_serial_data = {
- .base = CONFIG_DEBUG_UART_BASE
+ .base = CONFIG_VAL(DEBUG_UART_BASE)
};
/* Serial dumb device, to reuse driver code */
@@ -587,7 +587,7 @@ static struct udevice init_dev = {
static inline void _debug_uart_init(void)
{
- phys_addr_t base = CONFIG_DEBUG_UART_BASE;
+ phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
geni_serial_init(&init_dev);
geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE);
@@ -596,7 +596,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
- phys_addr_t base = CONFIG_DEBUG_UART_BASE;
+ phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG);
qcom_geni_serial_setup_tx(base, 1);
--- a/drivers/serial/serial_mt7620.c
+++ b/drivers/serial/serial_mt7620.c
@@ -220,7 +220,7 @@ static inline void _debug_uart_init(void
{
struct mt7620_serial_plat plat;
- plat.regs = (void *)CONFIG_DEBUG_UART_BASE;
+ plat.regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
plat.clock = CONFIG_DEBUG_UART_CLOCK;
writel(0, &plat.regs->ier);
@@ -233,7 +233,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
struct mt7620_serial_regs __iomem *regs =
- (void *)CONFIG_DEBUG_UART_BASE;
+ (void *)CONFIG_VAL(DEBUG_UART_BASE);
while (!(readl(&regs->lsr) & UART_LSR_THRE))
;
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
@@ -426,7 +426,7 @@ static inline void _debug_uart_init(void
{
struct mtk_serial_priv priv;
- priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
+ priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
priv.clock = CONFIG_DEBUG_UART_CLOCK;
writel(0, &priv.regs->ier);
@@ -439,7 +439,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
struct mtk_serial_regs __iomem *regs =
- (void *) CONFIG_DEBUG_UART_BASE;
+ (void *) CONFIG_VAL(DEBUG_UART_BASE);
while (!(readl(&regs->lsr) & UART_LSR_THRE))
;
--- a/drivers/serial/serial_mvebu_a3700.c
+++ b/drivers/serial/serial_mvebu_a3700.c
@@ -321,7 +321,7 @@ U_BOOT_DRIVER(serial_mvebu) = {
static inline void _debug_uart_init(void)
{
- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
u32 parent_rate, divider;
/* reset FIFOs */
@@ -349,7 +349,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
;
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -372,7 +372,7 @@ U_BOOT_DRIVER(serial_mxc) = {
static inline void _debug_uart_init(void)
{
- struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
+ struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE);
_mxc_serial_init(base, false);
_mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
@@ -381,7 +381,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
- struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
+ struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE);
while (!(readl(&base->ts) & UTS_TXEMPTY))
WATCHDOG_RESET();
--- a/drivers/serial/serial_omap.c
+++ b/drivers/serial/serial_omap.c
@@ -66,7 +66,7 @@ static inline int serial_in_shift(void *
static inline void _debug_uart_init(void)
{
- struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE;
+ struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
int baud_divisor;
baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
@@ -85,7 +85,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
- struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE;
+ struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
;
--- a/drivers/serial/serial_pic32.c
+++ b/drivers/serial/serial_pic32.c
@@ -187,14 +187,14 @@ U_BOOT_DRIVER(pic32_serial) = {
static inline void _debug_uart_init(void)
{
- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
}
static inline void _debug_uart_putc(int ch)
{
- writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR);
+ writel(ch, CONFIG_VAL(DEBUG_UART_BASE) + U_TXR);
}
DEBUG_UART_FUNCS
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -403,7 +403,7 @@ U_BOOT_DRIVER(serial_pl01x) = {
static void _debug_uart_init(void)
{
#ifndef CONFIG_DEBUG_UART_SKIP_INIT
- struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
+ struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE);
enum pl01x_type type;
if (IS_ENABLED(CONFIG_DEBUG_UART_PL011))
@@ -419,7 +419,7 @@ static void _debug_uart_init(void)
static inline void _debug_uart_putc(int ch)
{
- struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
+ struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE);
while (pl01x_putc(regs, ch) == -EAGAIN)
;
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -276,7 +276,7 @@ static inline void _debug_uart_init(void
if (IS_ENABLED(CONFIG_DEBUG_UART_SKIP_INIT))
return;
- struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
+ struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE);
s5p_serial_init(uart);
#if CONFIG_IS_ENABLED(ARCH_APPLE)
@@ -288,7 +288,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
- struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
+ struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE);
#if CONFIG_IS_ENABLED(ARCH_APPLE)
while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL);
--- a/drivers/serial/serial_sifive.c
+++ b/drivers/serial/serial_sifive.c
@@ -212,7 +212,7 @@ U_BOOT_DRIVER(serial_sifive) = {
static inline void _debug_uart_init(void)
{
struct uart_sifive *regs =
- (struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
+ (struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE);
_sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
CONFIG_BAUDRATE);
@@ -222,7 +222,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
struct uart_sifive *regs =
- (struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
+ (struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE);
while (_sifive_serial_putc(regs, ch) == -EAGAIN)
WATCHDOG_RESET();
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -270,7 +270,7 @@ static inline struct stm32_uart_info *_d
static inline void _debug_uart_init(void)
{
- fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
+ fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
struct stm32_uart_info *uart_info = _debug_uart_info();
_stm32_serial_init(base, uart_info);
@@ -281,7 +281,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int c)
{
- fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
+ fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
struct stm32_uart_info *uart_info = _debug_uart_info();
while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -143,7 +143,7 @@ U_BOOT_DRIVER(serial_uartlite) = {
static inline void _debug_uart_init(void)
{
- struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
+ struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE);
int ret;
uart_out32(&regs->control, 0);
@@ -159,7 +159,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
- struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
+ struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE);
while (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
;
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -295,7 +295,7 @@ U_BOOT_DRIVER(serial_zynq) = {
#ifdef CONFIG_DEBUG_UART_ZYNQ
static inline void _debug_uart_init(void)
{
- struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
+ struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE);
_uart_zynq_serial_init(regs);
_uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
@@ -304,7 +304,7 @@ static inline void _debug_uart_init(void
static inline void _debug_uart_putc(int ch)
{
- struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
+ struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE);
while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
WATCHDOG_RESET();

36
package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch
View File

@ -1,7 +1,7 @@
From a299de45833df13d4ec28092201ea5fec0ba24fe Mon Sep 17 00:00:00 2001
From 13d81db4723241e33316d7d134e4d279116e3158 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 29 Jul 2022 15:17:58 +0800
Subject: [PATCH 01/31] arm: mediatek: add support for MediaTek MT7986 SoC
Date: Wed, 31 Aug 2022 19:00:17 +0800
Subject: [PATCH 01/32] arm: mediatek: add support for MediaTek MT7986 SoC
This patch adds basic support for MediaTek MT7986 SoC.
This include the file that will initialize the SoC after boot and its
@ -10,11 +10,11 @@ device tree.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7986-u-boot.dtsi | 33 ++
arch/arm/dts/mt7986.dtsi | 341 ++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 11 +
arch/arm/dts/mt7986.dtsi | 346 ++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 12 +
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt7986/Makefile | 4 +
arch/arm/mach-mediatek/mt7986/init.c | 51 +++
arch/arm/mach-mediatek/mt7986/init.c | 45 +++
arch/arm/mach-mediatek/mt7986/lowlevel_init.S | 32 ++
7 files changed, 473 insertions(+)
create mode 100644 arch/arm/dts/mt7986-u-boot.dtsi
@ -61,7 +61,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+};
--- /dev/null
+++ b/arch/arm/dts/mt7986.dtsi
@@ -0,0 +1,341 @@
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
@ -118,6 +118,11 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ u-boot,dm-pre-reloc;
+ };
+
+ hwver: hwver {
+ compatible = "mediatek,hwver";
+ reg = <0x8000000 0x1000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
@ -405,13 +410,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+};
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -40,6 +40,14 @@ config TARGET_MT7629
@@ -40,6 +40,15 @@ config TARGET_MT7629
including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
+config TARGET_MT7986
+ bool "MediaTek MT7986 SoC"
+ select ARM64
+ select CPU
+ help
+ The MediaTek MT7986 is a ARM64-based SoC with a quad-core Cortex-A53.
+ including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
@ -420,7 +426,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
config TARGET_MT8183
bool "MediaTek MT8183 SoC"
select ARM64
@@ -84,6 +92,7 @@ config SYS_BOARD
@@ -84,6 +93,7 @@ config SYS_BOARD
default "mt7622" if TARGET_MT7622
default "mt7623" if TARGET_MT7623
default "mt7629" if TARGET_MT7629
@ -428,7 +434,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
default "mt8183" if TARGET_MT8183
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
@@ -99,6 +108,7 @@ config SYS_CONFIG_NAME
@@ -99,6 +109,7 @@ config SYS_CONFIG_NAME
default "mt7622" if TARGET_MT7622
default "mt7623" if TARGET_MT7623
default "mt7629" if TARGET_MT7629
@ -436,7 +442,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
default "mt8183" if TARGET_MT8183
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
@@ -113,6 +123,7 @@ config MTK_BROM_HEADER_INFO
@@ -113,6 +124,7 @@ config MTK_BROM_HEADER_INFO
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
@ -463,7 +469,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+obj-y += lowlevel_init.o
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7986/init.c
@@ -0,0 +1,51 @@
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
@ -477,12 +483,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT7986\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);

36
package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch
View File

@ -1,7 +1,7 @@
From 38faebb811868f9e6734dea7894d0fa5a61f3a22 Mon Sep 17 00:00:00 2001
From 5512a2e8257b0a733cf90ec247f34094ff31f750 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 29 Jul 2022 15:58:11 +0800
Subject: [PATCH 02/31] arm: mediatek: add support for MediaTek MT7981 SoC
Date: Wed, 31 Aug 2022 19:00:20 +0800
Subject: [PATCH 02/32] arm: mediatek: add support for MediaTek MT7981 SoC
This patch adds basic support for MediaTek MT7981 SoC.
This include the file that will initialize the SoC after boot and its
@ -9,11 +9,11 @@ device tree.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7981.dtsi | 288 ++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 12 +-
arch/arm/dts/mt7981.dtsi | 293 ++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt7981/Makefile | 4 +
arch/arm/mach-mediatek/mt7981/init.c | 51 ++++
arch/arm/mach-mediatek/mt7981/init.c | 45 +++
arch/arm/mach-mediatek/mt7981/lowlevel_init.S | 32 ++
6 files changed, 387 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt7981.dtsi
@ -23,7 +23,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- /dev/null
+++ b/arch/arm/dts/mt7981.dtsi
@@ -0,0 +1,288 @@
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
@ -63,6 +63,11 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ u-boot,dm-pre-reloc;
+ };
+
+ hwver: hwver {
+ compatible = "mediatek,hwver";
+ reg = <0x8000000 0x1000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
@ -314,13 +319,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+};
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -40,6 +40,14 @@ config TARGET_MT7629
@@ -40,6 +40,15 @@ config TARGET_MT7629
including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
+config TARGET_MT7981
+ bool "MediaTek MT7981 SoC"
+ select ARM64
+ select CPU
+ help
+ The MediaTek MT7981 is a ARM64-based SoC with a dual-core Cortex-A53.
+ including UART, SPI, USB, NAND, SNFI, PWM, Gigabit Ethernet, I2C,
@ -329,7 +335,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
config TARGET_MT7986
bool "MediaTek MT7986 SoC"
select ARM64
@@ -92,6 +100,7 @@ config SYS_BOARD
@@ -93,6 +102,7 @@ config SYS_BOARD
default "mt7622" if TARGET_MT7622
default "mt7623" if TARGET_MT7623
default "mt7629" if TARGET_MT7629
@ -337,7 +343,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
default "mt8512" if TARGET_MT8512
@@ -108,6 +117,7 @@ config SYS_CONFIG_NAME
@@ -109,6 +119,7 @@ config SYS_CONFIG_NAME
default "mt7622" if TARGET_MT7622
default "mt7623" if TARGET_MT7623
default "mt7629" if TARGET_MT7629
@ -345,7 +351,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
default "mt8512" if TARGET_MT8512
@@ -123,7 +133,7 @@ config MTK_BROM_HEADER_INFO
@@ -124,7 +135,7 @@ config MTK_BROM_HEADER_INFO
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
@ -373,7 +379,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+obj-y += lowlevel_init.o
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7981/init.c
@@ -0,0 +1,51 @@
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
@ -387,12 +393,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT7981\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);

6
package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch
View File

@ -1,7 +1,7 @@
From ab3f81920b4e47bd2894388540363700d5b1e59c Mon Sep 17 00:00:00 2001
From bad27c737d27f8afc4d597b6de1bdbc26a152ad9 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 29 Jul 2022 15:26:31 +0800
Subject: [PATCH 03/31] board: mediatek: add MT7986 reference boards
Date: Wed, 31 Aug 2022 19:00:22 +0800
Subject: [PATCH 03/32] board: mediatek: add MT7986 reference boards
Add general board files based on MT7986 SoCs.

6
package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch
View File

@ -1,7 +1,7 @@
From 89a31bfa05c384a2b4e56ddb9814633325b7feab Mon Sep 17 00:00:00 2001
From 37bcf4d1acb5f7ce93fa0bd59dc313a79004ae34 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 29 Jul 2022 16:02:37 +0800
Subject: [PATCH 04/31] board: mediatek: add MT7981 reference boards
Date: Wed, 31 Aug 2022 19:00:25 +0800
Subject: [PATCH 04/32] board: mediatek: add MT7981 reference boards
This patch adds general board files based on MT7981 SoCs.

6
package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch
View File

@ -1,7 +1,7 @@
From 3831266fedf14ef415791a93dd03a9e637eb8b5e Mon Sep 17 00:00:00 2001
From 9a10182f21cc4007f46284d5c64c49dc892336be Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 26 Jul 2022 09:24:13 +0800
Subject: [PATCH 05/31] mmc: mediatek: add support for MediaTek MT7891/MT7986
Date: Wed, 31 Aug 2022 19:04:12 +0800
Subject: [PATCH 05/32] mmc: mediatek: add support for MediaTek MT7891/MT7986
SoCs
Add eMMC and SDXC support for MediaTek MT7981/MT7986 SoCs

6
package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch
View File

@ -1,7 +1,7 @@
From 5c5af768c4cceaa9d7497c3e5bfbc9d1ea8b279c Mon Sep 17 00:00:00 2001
From ba6af13fd58c0ec418720d959152e0db47e91b02 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 26 Jul 2022 10:44:57 +0800
Subject: [PATCH 06/31] net: mediatek: use a struct to cover variations of all
Date: Wed, 31 Aug 2022 19:04:19 +0800
Subject: [PATCH 06/32] net: mediatek: use a struct to cover variations of all
SoCs
Using a single soc id to control different initialization and TX/RX flow

6
package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch
View File

@ -1,7 +1,7 @@
From b978c067075fddbac341bf551ebef29e78767b75 Mon Sep 17 00:00:00 2001
From 5f6f3600a334398e27802de33a6a8726aacbe88c Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 09:32:29 +0800
Subject: [PATCH 07/31] net: mediatek: stop using bitfileds for DMA descriptors
Date: Wed, 31 Aug 2022 19:04:23 +0800
Subject: [PATCH 07/32] net: mediatek: stop using bitfileds for DMA descriptors
This patch is a preparation for adding a new version of PDMA of which the
DMA descriptor fields has changed. Using bitfields will result in a complex

6
package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch
View File

@ -1,7 +1,7 @@
From 2f53795aac940d960bc5f3b08a730c4d480fc5f6 Mon Sep 17 00:00:00 2001
From 72241607b955639a51b79297776991de7dd59915 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 09:56:30 +0800
Subject: [PATCH 08/31] net: mediatek: add support for PDMA v2
Date: Wed, 31 Aug 2022 19:04:27 +0800
Subject: [PATCH 08/32] net: mediatek: add support for PDMA v2
This patch adds support for PDMA v2 hardware. The PDMA v2 has extended the
DMA descriptor to 8-words, and some of its fields have changed comparing

6
package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch
View File

@ -1,7 +1,7 @@
From 5e06e9a78bbc81f64fdb4c8502a8e7175d8b6216 Mon Sep 17 00:00:00 2001
From 4bbe44513bf9dc7041b2ce4aac6e841a0e10d2e6 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 10:03:17 +0800
Subject: [PATCH 09/31] net: mediatek: add support for MediaTek MT7981/MT7986
Date: Wed, 31 Aug 2022 19:04:29 +0800
Subject: [PATCH 09/32] net: mediatek: add support for MediaTek MT7981/MT7986
This patch adds support for MediaTek MT7981 and MT7986. Both chips uses
PDMA v2.

8
package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch
View File

@ -1,7 +1,7 @@
From 55ed87efb110d13fce6d1a7ee6cb04fac1a2c08a Mon Sep 17 00:00:00 2001
From d19ad7515a7ef4ee58b5c6606ee9f74c94f28932 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 10:28:05 +0800
Subject: [PATCH 10/31] serial: mtk: add support for using dynamic baud clock
Date: Wed, 31 Aug 2022 19:04:32 +0800
Subject: [PATCH 10/32] serial: mtk: add support for using dynamic baud clock
souce
The baud clock on some platform may change due to assigned-clock-parent
@ -187,7 +187,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
@@ -427,13 +441,13 @@ static inline void _debug_uart_init(void
struct mtk_serial_priv priv;
priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
- priv.clock = CONFIG_DEBUG_UART_CLOCK;
+ priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK;

6
package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch
View File

@ -1,7 +1,7 @@
From 893368e64049fd770e55fffcc8758d2619dc337d Mon Sep 17 00:00:00 2001
From 79786aa175010dde78f95970939e8efadd7a3295 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 16:33:13 +0800
Subject: [PATCH 11/31] arm: dts: mt7622: force high-speed mode for uart
Date: Wed, 31 Aug 2022 19:04:34 +0800
Subject: [PATCH 11/32] arm: dts: mt7622: force high-speed mode for uart
The input clock for uart is too slow (25MHz) which introduces frequent data
error on both receiving and transmitting even if the baudrate is 115200.

6
package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch
View File

@ -1,7 +1,7 @@
From 63acbf4ffe328809ca479e5c7d344882810d412c Mon Sep 17 00:00:00 2001
From d7dae84aad997f4f9b5d039f7ab180bd1f54fa37 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 11:00:15 +0800
Subject: [PATCH 12/31] pwm: mtk: add support for MediaTek MT7986 SoC
Date: Wed, 31 Aug 2022 19:04:35 +0800
Subject: [PATCH 12/32] pwm: mtk: add support for MediaTek MT7986 SoC
This patch adds PWM support for MediaTek MT7986 SoC.

6
package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch
View File

@ -1,7 +1,7 @@
From 4569ef02981f20b236a8cdc3a57b4d27fbdbc22e Mon Sep 17 00:00:00 2001
From 230003c14f7beedf4042bf2258b04e2cd5aac270 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 11:01:34 +0800
Subject: [PATCH 13/31] pwm: mtk: add support for MediaTek MT7981 SoC
Date: Wed, 31 Aug 2022 19:04:38 +0800
Subject: [PATCH 13/32] pwm: mtk: add support for MediaTek MT7981 SoC
This patch adds PWM support for MediaTek MT7981 SoC.
MT7981 uses a different register offset so we have to add a version field

6
package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch
View File

@ -1,7 +1,7 @@
From 7860bc58c43dfa939d2664be518c28aea591aeef Mon Sep 17 00:00:00 2001
From a77b8f6d9aa90f80090e505d823a6dcf6b877136 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 11:38:33 +0800
Subject: [PATCH 14/31] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs
Date: Wed, 31 Aug 2022 19:04:40 +0800
Subject: [PATCH 14/32] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs
This patch add general-purpose timer support for MediaTek MT7981/MT7986.
These two SoCs uses a newer version of timer with its register definition

6
package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch
View File

@ -1,7 +1,7 @@
From ec7e5d3e4d6e9239f3d7ac861f07ca4a52bec9fa Mon Sep 17 00:00:00 2001
From 18f761770d7aa53abf187fa64bbd92f0682d154c Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 11:47:50 +0800
Subject: [PATCH 15/31] watchdog: mediatek: add support for MediaTek MT7986 SoC
Date: Wed, 31 Aug 2022 19:04:42 +0800
Subject: [PATCH 15/32] watchdog: mediatek: add support for MediaTek MT7986 SoC
Add watchdog support for MediaTek MT7986 SoC

6
package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch
View File

@ -1,7 +1,7 @@
From f85493e3c2d1e4fd411061540b4f4943c09114df Mon Sep 17 00:00:00 2001
From e6b225ff8990635dc2d6d8dbd72e78dec1f36c62 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 16:58:38 +0800
Subject: [PATCH 16/31] spi: add support for MediaTek spi-mem controller
Date: Wed, 31 Aug 2022 19:04:45 +0800
Subject: [PATCH 16/32] spi: add support for MediaTek spi-mem controller
This patch adds support for spi-mem controller found on newer MediaTek SoCs
This controller supports Single/Dual/Quad SPI mode.

6
package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch
View File

@ -1,7 +1,7 @@
From de6f2293ab087f405dbcf7b8df45d1f9b03fc091 Mon Sep 17 00:00:00 2001
From 987dc8d079cd399e753e10fce12d526b42f90ed0 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 17:16:38 +0800
Subject: [PATCH 17/31] i2c: add support for MediaTek I2C interface
Date: Wed, 31 Aug 2022 19:04:47 +0800
Subject: [PATCH 17/32] i2c: add support for MediaTek I2C interface
This patch adds support for MediaTek I2C interface

6
package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch
View File

@ -1,7 +1,7 @@
From 9ae337317d5634569bda83dfc5e0658fce34b1e2 Mon Sep 17 00:00:00 2001
From ceb4b900586299b12e2c8edffecef1d09b57eb30 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 16:30:30 +0800
Subject: [PATCH 18/31] arm: dts: mt7622: add i2c support
Date: Wed, 31 Aug 2022 19:04:49 +0800
Subject: [PATCH 18/32] arm: dts: mt7622: add i2c support
Add both hardware and software i2c support for mt7622.

6
package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch
View File

@ -1,7 +1,7 @@
From 920ba7b9ba1787fd03dad7a5bdc894073936c197 Mon Sep 17 00:00:00 2001
From e1c55c0ad21daafcb3551b4f5286c1e11c51acc3 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Thu, 28 Jul 2022 09:37:26 +0800
Subject: [PATCH 19/31] dt-bindings: pinctrl: mediatek: add a header for common
Date: Wed, 31 Aug 2022 19:04:51 +0800
Subject: [PATCH 19/32] dt-bindings: pinctrl: mediatek: add a header for common
pinconf parameters
This patch adds a pinctrl header for common pinconf parameters such as

6
package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch
View File

@ -1,7 +1,7 @@
From 49e7b1e01cf80437c7e22f8b6579d4a81e7f8a3a Mon Sep 17 00:00:00 2001
From 95df7f4bfacf810be4f94112ab2a4215f6de288d Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Thu, 28 Jul 2022 09:57:58 +0800
Subject: [PATCH 20/31] pinctrl: mediatek: add pinctrl driver for MT7981 SoC
Date: Wed, 31 Aug 2022 19:04:55 +0800
Subject: [PATCH 20/32] pinctrl: mediatek: add pinctrl driver for MT7981 SoC
This patch adds pinctrl and gpio support for MT7981 SoC

6
package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch
View File

@ -1,7 +1,7 @@
From a018800db986d63cf95b0779ebb33b5e246072a7 Mon Sep 17 00:00:00 2001
From 201880cacf1498dd4c6749780163157148d0445d Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Thu, 28 Jul 2022 10:01:00 +0800
Subject: [PATCH 21/31] pinctrl: mediatek: add pinctrl driver for MT7986 SoC
Date: Wed, 31 Aug 2022 19:04:57 +0800
Subject: [PATCH 21/32] pinctrl: mediatek: add pinctrl driver for MT7986 SoC
This patch adds pinctrl and gpio support for MT7986 SoC

24
package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch
View File

@ -1,7 +1,7 @@
From 7f6c8bdfe020c45c398c01b417460e3319476606 Mon Sep 17 00:00:00 2001
From 907d65c5020fefc9944ec57a9e0bd66dc648823e Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 29 Jul 2022 10:43:39 +0800
Subject: [PATCH 22/31] clk: mediatek: add CLK_BYPASS_XTAL flag to allow
Date: Wed, 31 Aug 2022 19:04:59 +0800
Subject: [PATCH 22/32] clk: mediatek: add CLK_BYPASS_XTAL flag to allow
bypassing searching clock parent of xtal clock
The mtk clock framework in u-boot uses array index for searching clock
@ -22,26 +22,20 @@ with ID=0 to call mtk_topckgen_get_mux_rate.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/clk/mediatek/clk-mtk.c | 5 ++++-
drivers/clk/mediatek/clk-mtk.c | 4 +++-
drivers/clk/mediatek/clk-mtk.h | 6 ++++++
2 files changed, 10 insertions(+), 1 deletion(-)
2 files changed, 9 insertions(+), 1 deletion(-)
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -314,12 +314,15 @@ static ulong mtk_topckgen_get_mux_rate(s
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_composite *mux = &priv->tree->muxes[off];
u32 index;
+ u32 flag = 0;
index = readl(priv->base + mux->mux_reg);
@@ -319,7 +319,9 @@ static ulong mtk_topckgen_get_mux_rate(s
index &= mux->mux_mask << mux->mux_shift;
index = index >> mux->mux_shift;
- if (mux->parent[index])
+ if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL)
+ flag = 1;
+ if (mux->parent[index] > 0 || flag == 1)
+ if (mux->parent[index] > 0 ||
+ (mux->parent[index] == CLK_XTAL &&
+ priv->tree->flags & CLK_BYPASS_XTAL))
return mtk_clk_find_parent_rate(clk, mux->parent[index],
NULL);

30
package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch
View File

@ -1,7 +1,7 @@
From cd4d6be5ed0488de2e0df9c388d89ad93d781caa Mon Sep 17 00:00:00 2001
From 50859bea6a3334834b8250e7e5406507f0d0918a Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 29 Jul 2022 10:57:05 +0800
Subject: [PATCH 23/31] clk: mediatek: add support to configure clock driver
Date: Wed, 31 Aug 2022 19:05:06 +0800
Subject: [PATCH 23/32] clk: mediatek: add support to configure clock driver
parent
This patch adds support for a clock node to configure its parent clock
@ -50,14 +50,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
break;
case CLK_PARENT_TOPCKGEN:
rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
@@ -322,9 +316,18 @@ static ulong mtk_topckgen_get_mux_rate(s
@@ -321,9 +315,18 @@ static ulong mtk_topckgen_get_mux_rate(s
if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL)
flag = 1;
- if (mux->parent[index] > 0 || flag == 1)
if (mux->parent[index] > 0 ||
(mux->parent[index] == CLK_XTAL &&
- priv->tree->flags & CLK_BYPASS_XTAL))
- return mtk_clk_find_parent_rate(clk, mux->parent[index],
- NULL);
+ if (mux->parent[index] > 0 || flag == 1) {
+ priv->tree->flags & CLK_BYPASS_XTAL)) {
+ switch (mux->flags & CLK_PARENT_MASK) {
+ case CLK_PARENT_APMIXED:
+ return mtk_clk_find_parent_rate(clk, mux->parent[index],
@ -72,7 +72,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
return priv->tree->xtal_rate;
}
@@ -343,7 +346,7 @@ static ulong mtk_topckgen_get_rate(struc
@@ -342,7 +345,7 @@ static ulong mtk_topckgen_get_rate(struc
priv->tree->muxes_offs);
}
@ -81,7 +81,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_composite *mux;
@@ -376,7 +379,7 @@ static int mtk_topckgen_enable(struct cl
@@ -375,7 +378,7 @@ static int mtk_topckgen_enable(struct cl
return 0;
}
@ -90,7 +90,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_composite *mux;
@@ -402,7 +405,7 @@ static int mtk_topckgen_disable(struct c
@@ -401,7 +404,7 @@ static int mtk_topckgen_disable(struct c
return 0;
}
@ -99,7 +99,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
@@ -474,19 +477,7 @@ static ulong mtk_clk_gate_get_rate(struc
@@ -473,19 +476,7 @@ static ulong mtk_clk_gate_get_rate(struc
struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
const struct mtk_gate *gate = &priv->gates[clk->id];
@ -120,7 +120,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
}
const struct clk_ops mtk_clk_apmixedsys_ops = {
@@ -497,10 +488,10 @@ const struct clk_ops mtk_clk_apmixedsys_
@@ -496,10 +487,10 @@ const struct clk_ops mtk_clk_apmixedsys_
};
const struct clk_ops mtk_clk_topckgen_ops = {
@ -134,7 +134,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
};
const struct clk_ops mtk_clk_gate_ops = {
@@ -513,11 +504,22 @@ int mtk_common_clk_init(struct udevice *
@@ -512,11 +503,22 @@ int mtk_common_clk_init(struct udevice *
const struct mtk_clk_tree *tree)
{
struct mtk_clk_priv *priv = dev_get_priv(dev);
@ -157,7 +157,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
priv->tree = tree;
return 0;
@@ -528,11 +530,22 @@ int mtk_common_clk_gate_init(struct udev
@@ -527,11 +529,22 @@ int mtk_common_clk_gate_init(struct udev
const struct mtk_gate *gates)
{
struct mtk_cg_priv *priv = dev_get_priv(dev);

23
package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch
View File

@ -1,16 +1,16 @@
From e9c0c2ebd346aa578007c2aa88fc0974af6afb40 Mon Sep 17 00:00:00 2001
From c53d249df9a75f77f5d0abb986a8913bc13070d0 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 29 Jul 2022 11:14:33 +0800
Subject: [PATCH 24/31] clk: mediatek: add infrasys clock mux support
Date: Wed, 31 Aug 2022 19:05:09 +0800
Subject: [PATCH 24/32] clk: mediatek: add infrasys clock mux support
This patch adds infrasys clock mux support for mediatek clock drivers.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/clk/mediatek/clk-mtk.c | 72 ++++++++++++++++++++++++++++++++++
drivers/clk/mediatek/clk-mtk.c | 71 ++++++++++++++++++++++++++++++++++
drivers/clk/mediatek/clk-mtk.h | 4 +-
2 files changed, 75 insertions(+), 1 deletion(-)
2 files changed, 74 insertions(+), 1 deletion(-)
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@ -39,7 +39,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
@@ -332,6 +350,34 @@ static ulong mtk_topckgen_get_mux_rate(s
@@ -331,6 +349,33 @@ static ulong mtk_topckgen_get_mux_rate(s
return priv->tree->xtal_rate;
}
@ -48,15 +48,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct mtk_composite *mux = &priv->tree->muxes[off];
+ u32 index;
+ u32 flag;
+
+ index = readl(priv->base + mux->mux_reg);
+ index &= mux->mux_mask << mux->mux_shift;
+ index = index >> mux->mux_shift;
+
+ if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL)
+ flag = 1;
+ if (mux->parent[index] > 0 || flag == 1) {
+ if (mux->parent[index] > 0 ||
+ (mux->parent[index] == CLK_XTAL &&
+ priv->tree->flags & CLK_BYPASS_XTAL)) {
+ switch (mux->flags & CLK_PARENT_MASK) {
+ case CLK_PARENT_TOPCKGEN:
+ return mtk_clk_find_parent_rate(clk, mux->parent[index],
@ -74,7 +73,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
static ulong mtk_topckgen_get_rate(struct clk *clk)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
@@ -346,6 +392,25 @@ static ulong mtk_topckgen_get_rate(struc
@@ -345,6 +390,25 @@ static ulong mtk_topckgen_get_rate(struc
priv->tree->muxes_offs);
}
@ -100,7 +99,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
static int mtk_clk_mux_enable(struct clk *clk)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
@@ -494,6 +559,13 @@ const struct clk_ops mtk_clk_topckgen_op
@@ -493,6 +557,13 @@ const struct clk_ops mtk_clk_topckgen_op
.set_parent = mtk_common_clk_set_parent,
};

10
package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch
View File

@ -1,10 +1,10 @@
From cf70b726c9844bb5d1ba4bc3c202c5ab3ba4d421 Mon Sep 17 00:00:00 2001
From 0a2cd71e3b16eaa8797b5eec78356970186e552e Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 29 Jul 2022 11:15:35 +0800
Subject: [PATCH 25/31] clk: mediatek: add CLK_XTAL support for clock driver
Date: Wed, 31 Aug 2022 19:05:11 +0800
Subject: [PATCH 25/32] clk: mediatek: add CLK_XTAL support for clock driver
This add CLK_XTAL macro and flag to mediatek clock driver common part,
to make thi SoC that has clock directlly connect to XTAL working.
This adds the CLK_XTAL macro/flag to allow modeling clocks which are
directly connected to the xtal clock.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---

7
package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch
View File

@ -1,11 +1,12 @@
From ba4acf55044a8a11fc7e11a558a8a93e3c126391 Mon Sep 17 00:00:00 2001
From 54b66dd24310dba4798caa6e4c02b8571f522602 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 29 Jul 2022 11:21:59 +0800
Subject: [PATCH 26/31] clk: mediatek: add clock driver support for MediaTek
Date: Wed, 31 Aug 2022 19:05:13 +0800
Subject: [PATCH 26/32] clk: mediatek: add clock driver support for MediaTek
MT7986 SoC
This patch adds clock driver support for MediaTek MT7986 SoC
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---

7
package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch
View File

@ -1,11 +1,12 @@
From 79bca945dbfafcd08d71437b11e8ee57d64b4305 Mon Sep 17 00:00:00 2001
From d525836896235c4678f6144cc4608d5b15e02660 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 29 Jul 2022 11:22:51 +0800
Subject: [PATCH 27/31] clk: mediatek: add clock driver support for MediaTek
Date: Wed, 31 Aug 2022 19:05:16 +0800
Subject: [PATCH 27/32] clk: mediatek: add clock driver support for MediaTek
MT7981 SoC
This patch adds clock driver support for MediaTek MT7981 SoC
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---

133
package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch Normal file
View File

@ -0,0 +1,133 @@
From e3c707d23a3a5bc1ba9b8c03731a32c3714ae56a Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 31 Aug 2022 19:05:20 +0800
Subject: [PATCH 28/32] cpu: add basic cpu driver for MediaTek ARM chips
Add basic CPU driver used to retrieve CPU model information.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/cpu/Makefile | 1 +
drivers/cpu/mtk_cpu.c | 106 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 107 insertions(+)
create mode 100644 drivers/cpu/mtk_cpu.c
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_CPU) += cpu-uclass.o
obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
+obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o
obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
obj-$(CONFIG_SANDBOX) += cpu_sandbox.o
--- /dev/null
+++ b/drivers/cpu/mtk_cpu.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <linux/types.h>
+#include <cpu.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <mapmem.h>
+#include <asm/global_data.h>
+#include <linux/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mtk_cpu_plat {
+ void __iomem *hwver_base;
+};
+
+static int mtk_cpu_get_desc(const struct udevice *dev, char *buf, int size)
+{
+ struct mtk_cpu_plat *plat = dev_get_plat(dev);
+
+ snprintf(buf, size, "MediaTek MT%04X", readl(plat->hwver_base));
+
+ return 0;
+}
+
+static int mtk_cpu_get_count(const struct udevice *dev)
+{
+ return 1;
+}
+
+static int mtk_cpu_get_vendor(const struct udevice *dev, char *buf, int size)
+{
+ snprintf(buf, size, "MediaTek");
+
+ return 0;
+}
+
+static int mtk_cpu_probe(struct udevice *dev)
+{
+ struct mtk_cpu_plat *plat = dev_get_plat(dev);
+ const void *fdt = gd->fdt_blob, *reg;
+ int offset, parent, len, na, ns;
+ u64 addr;
+
+ if (!fdt)
+ return -ENODEV;
+
+ offset = fdt_path_offset(fdt, "/hwver");
+ if (offset < 0)
+ return -ENODEV;
+
+ parent = fdt_parent_offset(fdt, offset);
+ if (parent < 0)
+ return -ENODEV;
+
+ na = fdt_address_cells(fdt, parent);
+ if (na < 1)
+ return -ENODEV;
+
+ ns = fdt_size_cells(gd->fdt_blob, parent);
+ if (ns < 0)
+ return -ENODEV;
+
+ reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
+ if (!reg)
+ return -ENODEV;
+
+ if (ns)
+ addr = fdt_translate_address(fdt, offset, reg);
+ else
+ addr = fdt_read_number(reg, na);
+
+ plat->hwver_base = map_sysmem(addr, 0);
+ if (!plat->hwver_base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct cpu_ops mtk_cpu_ops = {
+ .get_desc = mtk_cpu_get_desc,
+ .get_count = mtk_cpu_get_count,
+ .get_vendor = mtk_cpu_get_vendor,
+};
+
+static const struct udevice_id mtk_cpu_ids[] = {
+ { .compatible = "arm,cortex-a7" },
+ { .compatible = "arm,cortex-a53" },
+ { .compatible = "arm,cortex-a73" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(cpu_mtk) = {
+ .name = "mtk-cpu",
+ .id = UCLASS_CPU,
+ .of_match = mtk_cpu_ids,
+ .ops = &mtk_cpu_ops,
+ .probe = mtk_cpu_probe,
+ .plat_auto = sizeof(struct mtk_cpu_plat),
+ .flags = DM_FLAG_PRE_RELOC,
+};

6
package/boot/uboot-mediatek/patches/002-0028-tools-mtk_image-split-gfh-header-verification-into-a.patch → package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch
View File

@ -1,7 +1,7 @@
From b6bb61fd3818f4a3025fedbe4d15dbeeaef6ee82 Mon Sep 17 00:00:00 2001
From 1c9174cbf57ddc75bb5a25b2563333d974fd1a55 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 2 Aug 2022 17:21:34 +0800
Subject: [PATCH 28/31] tools: mtk_image: split gfh header verification into a
Date: Wed, 31 Aug 2022 19:05:22 +0800
Subject: [PATCH 29/32] tools: mtk_image: split gfh header verification into a
new function
The verification code of gfh header for NAND and non-NAND are identical.

6
package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-the-code-of-generating-NAND-he.patch → package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch
View File

@ -1,7 +1,7 @@
From 20ebf03eab571b25e9f62b2764ab84932111dcd6 Mon Sep 17 00:00:00 2001
From 8867a5e66369d4a7da667e0f505597e1ac91209e Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 2 Aug 2022 17:23:57 +0800
Subject: [PATCH 29/31] tools: mtk_image: split the code of generating NAND
Date: Wed, 31 Aug 2022 19:05:24 +0800
Subject: [PATCH 30/32] tools: mtk_image: split the code of generating NAND
header into a new file
The predefined NAND headers take too much spaces in the mtk_image.c.

6
package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-add-support-for-nand-headers-used-by.patch → package/boot/uboot-mediatek/patches/002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch
View File

@ -1,7 +1,7 @@
From fbf296f9ed5daab70020686e9ba072efe663bbab Mon Sep 17 00:00:00 2001
From d459092aca25e081401606e18b7097f33b575188 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 3 Aug 2022 11:14:36 +0800
Subject: [PATCH 30/31] tools: mtk_image: add support for nand headers used by
Date: Wed, 31 Aug 2022 19:05:26 +0800
Subject: [PATCH 31/32] tools: mtk_image: add support for nand headers used by
newer chips
This patch adds more nand headers in two new types:

13
package/boot/uboot-mediatek/patches/002-0031-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch → package/boot/uboot-mediatek/patches/002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch
View File

@ -1,7 +1,7 @@
From ca90c165157c19af9bf46a69dcf719b8aab636b1 Mon Sep 17 00:00:00 2001
From 180f8ce7cac9277406ee702ea9390a6f78981bda Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Thu, 4 Aug 2022 09:50:40 +0800
Subject: [PATCH 31/31] MAINTAINERS: update maintainer for MediaTek ARM
Date: Wed, 31 Aug 2022 19:05:28 +0800
Subject: [PATCH 32/32] MAINTAINERS: update maintainer for MediaTek ARM
platform
Add new files for MediaTek ARM platform
@ -9,15 +9,16 @@ Add new files for MediaTek ARM platform
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
MAINTAINERS | 5 +++++
1 file changed, 5 insertions(+)
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -340,20 +340,25 @@ F: doc/device-tree-bindings/phy/phy-mtk-
@@ -340,20 +340,26 @@ F: doc/device-tree-bindings/phy/phy-mtk-
F: doc/device-tree-bindings/usb/mediatek,*
F: doc/README.mediatek
F: drivers/clk/mediatek/
+F: drivers/cpu/mtk_cpu.c
+F: drivers/i2c/mtk_i2c.c
F: drivers/mmc/mtk-sd.c
F: drivers/phy/phy-mtk-*

2
package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch
View File

@ -89,7 +89,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
reg = <0x11014000 0x1000>;
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -131,9 +131,11 @@ config SYS_CONFIG_NAME
@@ -133,9 +133,11 @@ config SYS_CONFIG_NAME
config MTK_BROM_HEADER_INFO
string

2
package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch
View File

@ -40,7 +40,7 @@
}
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -138,4 +138,8 @@ config MTK_BROM_HEADER_INFO
@@ -140,4 +140,8 @@ config MTK_BROM_HEADER_INFO
source "board/mediatek/mt7629/Kconfig"

4
package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch
View File

@ -51,6 +51,7 @@
+CONFIG_CMD_BUTTON=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_DNS=y
@ -246,6 +247,7 @@
+CONFIG_CMD_BUTTON=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_DNS=y
@ -442,6 +444,7 @@
+CONFIG_CMD_BUTTON=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_DNS=y
@ -637,6 +640,7 @@
+CONFIG_CMD_BUTTON=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_DNS=y

4
package/devel/gdb/Makefile
View File

@ -8,12 +8,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=gdb
PKG_VERSION:=11.2
PKG_VERSION:=12.1
PKG_RELEASE:=$(AUTORELEASE)
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNU/gdb
PKG_HASH:=1497c36a71881b8671a9a84a0ee40faab788ca30d7ba19d8463c3cc787152e32
PKG_HASH:=0e1793bf8f2b54d53f46dea84ccfd446f48f81b297b28c4f7fc017b818d69fed
PKG_BUILD_PARALLEL:=1
PKG_INSTALL:=1

12
package/devel/gdb/patches/110-shared_libgcc.patch
View File

@ -1,6 +1,6 @@
--- a/configure.ac
+++ b/configure.ac
@@ -1300,13 +1300,13 @@ if test -z "$LD"; then
@@ -1314,13 +1314,13 @@ if test -z "$LD"; then
fi
fi
@ -17,7 +17,7 @@
AC_LANG_PUSH(C++)
AC_LINK_IFELSE([AC_LANG_SOURCE([
#if (__GNUC__ < 4) || (__GNUC__ == 4 && __GNUC_MINOR__ < 5)
@@ -1705,7 +1705,7 @@ AC_ARG_WITH(stage1-ldflags,
@@ -1719,7 +1719,7 @@ AC_ARG_WITH(stage1-ldflags,
# trust that they are doing what they want.
if test "$with_static_standard_libraries" = yes -a "$stage1_libs" = "" \
-a "$have_static_libs" = yes; then
@ -26,7 +26,7 @@
fi])
AC_SUBST(stage1_ldflags)
@@ -1734,7 +1734,7 @@ AC_ARG_WITH(boot-ldflags,
@@ -1748,7 +1748,7 @@ AC_ARG_WITH(boot-ldflags,
# statically. But if the user explicitly specified the libraries to
# use, trust that they are doing what they want.
if test "$poststage1_libs" = ""; then
@ -37,7 +37,7 @@
--- a/configure
+++ b/configure
@@ -5257,14 +5257,14 @@ if test -z "$LD"; then
@@ -5275,14 +5275,14 @@ if test -z "$LD"; then
fi
fi
@ -56,7 +56,7 @@
ac_ext=cpp
ac_cpp='$CXXCPP $CPPFLAGS'
ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5'
@@ -6149,7 +6149,7 @@ else
@@ -6167,7 +6167,7 @@ else
# trust that they are doing what they want.
if test "$with_static_standard_libraries" = yes -a "$stage1_libs" = "" \
-a "$have_static_libs" = yes; then
@ -65,7 +65,7 @@
fi
fi
@@ -6185,7 +6185,7 @@ else
@@ -6203,7 +6203,7 @@ else
# statically. But if the user explicitly specified the libraries to
# use, trust that they are doing what they want.
if test "$poststage1_libs" = ""; then

2
package/devel/gdb/patches/130-gdb-ctrl-c.patch
View File

@ -24,7 +24,7 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
--- a/gdbserver/linux-low.cc
+++ b/gdbserver/linux-low.cc
@@ -5733,7 +5733,7 @@ linux_process_target::request_interrupt
@@ -5496,7 +5496,7 @@ linux_process_target::request_interrupt
{
/* Send a SIGINT to the process group. This acts just like the user
typed a ^C on the controlling terminal. */

22
package/kernel/linux/modules/crypto.mk
View File

@ -622,7 +622,8 @@ define KernelPackage/crypto-md5
DEPENDS:=+kmod-crypto-hash
KCONFIG:= \
CONFIG_CRYPTO_MD5 \
CONFIG_CRYPTO_MD5_OCTEON
CONFIG_CRYPTO_MD5_OCTEON \
CONFIG_CRYPTO_MD5_PPC
FILES:=$(LINUX_DIR)/crypto/md5.ko
AUTOLOAD:=$(call AutoLoad,09,md5)
$(call AddDepends/crypto)
@ -633,6 +634,11 @@ define KernelPackage/crypto-md5/octeon
AUTOLOAD+=$(call AutoLoad,09,octeon-md5)
endef
define KernelPackage/crypto-md5/mpc85xx
FILES+=$(LINUX_DIR)/arch/powerpc/crypto/md5-ppc.ko
AUTOLOAD+=$(call AutoLoad,09,md5-ppc)
endef
$(eval $(call KernelPackage,crypto-md5))
@ -832,6 +838,7 @@ define KernelPackage/crypto-sha1
CONFIG_CRYPTO_SHA1_ARM \
CONFIG_CRYPTO_SHA1_ARM_NEON \
CONFIG_CRYPTO_SHA1_OCTEON \
CONFIG_CRYPTO_SHA1_PPC_SPE \
CONFIG_CRYPTO_SHA1_SSSE3
FILES:=$(LINUX_DIR)/crypto/sha1_generic.ko
AUTOLOAD:=$(call AutoLoad,09,sha1_generic)
@ -858,7 +865,12 @@ define KernelPackage/crypto-sha1/octeon
AUTOLOAD+=$(call AutoLoad,09,octeon-sha1)
endef
KernelPackage/crypto-sha1/tegra=$(KernelPakcage/crypto-sha1/arm)
KernelPackage/crypto-sha1/tegra=$(KernelPackage/crypto-sha1/arm)
define KernelPackage/crypto-sha1/mpc85xx
FILES+=$(LINUX_DIR)/arch/powerpc/crypto/sha1-ppc-spe.ko
AUTOLOAD+=$(call AutoLoad,09,sha1-ppc-spe)
endef
define KernelPackage/crypto-sha1/x86/64
FILES+=$(LINUX_DIR)/arch/x86/crypto/sha1-ssse3.ko
@ -874,6 +886,7 @@ define KernelPackage/crypto-sha256
KCONFIG:= \
CONFIG_CRYPTO_SHA256 \
CONFIG_CRYPTO_SHA256_OCTEON \
CONFIG_CRYPTO_SHA256_PPC_SPE \
CONFIG_CRYPTO_SHA256_SSSE3
FILES:= \
$(LINUX_DIR)/crypto/sha256_generic.ko \
@ -887,6 +900,11 @@ define KernelPackage/crypto-sha256/octeon
AUTOLOAD+=$(call AutoLoad,09,octeon-sha256)
endef
define KernelPackage/crypto-sha256/mpc85xx
FILES+=$(LINUX_DIR)/arch/powerpc/crypto/sha256-ppc-spe.ko
AUTOLOAD+=$(call AutoLoad,09,sha256-ppc-spe)
endef
define KernelPackage/crypto-sha256/x86/64
FILES+=$(LINUX_DIR)/arch/x86/crypto/sha256-ssse3.ko
AUTOLOAD+=$(call AutoLoad,09,sha256-ssse3)

4
package/libs/nettle/Makefile
View File

@ -8,13 +8,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=nettle
PKG_VERSION:=3.8
PKG_VERSION:=3.8.1
PKG_RELEASE:=$(AUTORELEASE)
PKG_USE_MIPS16:=0
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=@GNU/nettle
PKG_HASH:=7576c68481c198f644b08c160d1a4850ba9449e308069455b5213319f234e8e6
PKG_HASH:=364f3e2b77cd7dcde83fd7c45219c834e54b0c75e428b6f894a23d12dd41cbfe
PKG_LICENSE:=GPL-2.0-or-later
PKG_LICENSE_FILES:=COPYING

4
package/libs/readline/Makefile
View File

@ -8,12 +8,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=readline
PKG_VERSION:=8.1
PKG_VERSION:=8.1.2
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=@GNU/readline
PKG_HASH:=f8ceb4ee131e3232226a17f51b164afc46cd0b9e6cef344be87c65962cb82b02
PKG_HASH:=7589a2381a8419e68654a47623ce7dfcb756815c8fee726b98f90bf668af7bc6
PKG_LICENSE:=GPL-3.0-or-later
PKG_LICENSE_FILES:=COPYING

4
package/libs/wolfssl/Makefile
View File

@ -8,12 +8,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=wolfssl
PKG_VERSION:=5.4.0-stable
PKG_VERSION:=5.5.0-stable
PKG_RELEASE:=$(AUTORELEASE)
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/wolfSSL/wolfssl/archive/v$(PKG_VERSION)
PKG_HASH:=dc36cc19dad197253e5c2ecaa490c7eef579ad448706e55d73d79396e814098b
PKG_HASH:=c34b74b5f689fac7becb05583b044e84d3b10d39f38709f0095dd5d423ded67f
PKG_FIXUP:=libtool libtool-abiver
PKG_INSTALL:=1

2
package/libs/wolfssl/patches/100-disable-hardening-check.patch
View File

@ -1,6 +1,6 @@
--- a/wolfssl/wolfcrypt/settings.h
+++ b/wolfssl/wolfcrypt/settings.h
@@ -2442,7 +2442,7 @@ extern void uITRON4_free(void *p) ;
@@ -2445,7 +2445,7 @@ extern void uITRON4_free(void *p) ;
#endif
/* warning for not using harden build options (default with ./configure) */

23
package/libs/wolfssl/patches/101-update-sp_rand_prime-s-preprocessor-gating-to-match.patch
View File

@ -1,23 +0,0 @@
From dc92ec2aa9cb76b782bdba3fc5203267ebf39994 Mon Sep 17 00:00:00 2001
From: Kareem <kareem@wolfssl.com>
Date: Fri, 22 Jul 2022 11:07:46 -0700
Subject: [PATCH] Update sp_rand_prime's preprocessor gating to match
wolfSSL_BN_generate_prime_ex's.
---
wolfcrypt/src/sp_int.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/wolfcrypt/src/sp_int.c
+++ b/wolfcrypt/src/sp_int.c
@@ -15647,8 +15647,8 @@ int sp_radix_size(sp_int* a, int radix,
* Prime number generation and checking.
***************************************/
-#if defined(WOLFSSL_KEY_GEN) && (!defined(NO_DH) || !defined(NO_DSA)) && \
- !defined(WC_NO_RNG)
+#if defined(WOLFSSL_KEY_GEN) && (!defined(NO_RSA) || !defined(NO_DH) || \
+ !defined(NO_DSA)) && !defined(WC_NO_RNG)
/* Generate a random prime for RSA only.
*
* @param [out] r SP integer to hold result.

4
package/libs/wolfssl/patches/200-ecc-rng.patch
View File

@ -11,7 +11,7 @@ RNG regardless of the built settings for wolfssl.
--- a/wolfcrypt/src/ecc.c
+++ b/wolfcrypt/src/ecc.c
@@ -12288,21 +12288,21 @@ void wc_ecc_fp_free(void)
@@ -12348,21 +12348,21 @@ void wc_ecc_fp_free(void)
#endif /* FP_ECC */
@ -37,7 +37,7 @@ RNG regardless of the built settings for wolfssl.
--- a/wolfssl/wolfcrypt/ecc.h
+++ b/wolfssl/wolfcrypt/ecc.h
@@ -650,10 +650,8 @@ WOLFSSL_API
@@ -650,10 +650,8 @@ WOLFSSL_ABI WOLFSSL_API
void wc_ecc_fp_free(void);
WOLFSSL_LOCAL
void wc_ecc_fp_init(void);

6
package/network/config/firewall4/Makefile
View File

@ -9,9 +9,9 @@ PKG_RELEASE:=$(AUTORELEASE)
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/firewall4.git
PKG_SOURCE_DATE:=2022-08-12
PKG_SOURCE_VERSION:=a4484d4612931800583a7219271b63224491244c
PKG_MIRROR_HASH:=f23799cf619395eab0c46050bb52b0a177e37056ff11dc146be6a358af367ae2
PKG_SOURCE_DATE:=2022-09-01
PKG_SOURCE_VERSION:=f5fcdcf2c51f6f0a4b116c352000c4fe0523be77
PKG_MIRROR_HASH:=57ef6f161abdd323019c026c959ab875fdfd3c972b8dc7767623634b1c259138
PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
PKG_LICENSE:=ISC

6
package/network/services/unetd/Makefile
View File

@ -10,9 +10,9 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=unetd
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/unetd.git
PKG_SOURCE_DATE:=2022-08-29
PKG_SOURCE_VERSION:=0041fcacb62492653a1054098ec7d811d8eaacbf
PKG_MIRROR_HASH:=1aad05af0c4015dc7c07936e504a2c03ceacf676c5c15902c2049a63fab60428
PKG_SOURCE_DATE:=2022-09-01
PKG_SOURCE_VERSION:=d7fb9e5b065bf9eecb5bcbcf741b5f89695c5dcc
PKG_MIRROR_HASH:=a693c2b4b4bda5e1e44b493019e8e6e6d39c4048f417b581c801a9931e6b9b39
PKG_LICENSE:=GPL-2.0
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>

16
package/network/services/unetd/files/unetd.sh
View File

@ -16,8 +16,9 @@ proto_unet_init_config() {
proto_config_add_string file
proto_config_add_int keepalive
proto_config_add_string domain
proto_config_add_string "tunnels:list(string)"
proto_config_add_string "connect:list(string)"
proto_config_add_array "tunnels:list(string)"
proto_config_add_array "connect:list(string)"
proto_config_add_array "peer_data:list(string)"
no_device=1
available=1
no_proto_task=1
@ -27,7 +28,10 @@ proto_unet_setup() {
local config="$1"
local device type key file keepalive domain tunnels
json_get_vars device type auth_key key file keepalive domain tunnels connect
json_get_vars device type auth_key key file keepalive domain
json_get_values tunnels tunnels
json_get_values connect connect
json_get_values peer_data peer_data
device="${device:-$config}"
[ -n "$auth_key" ] && type="${type:-dynamic}"
@ -58,6 +62,12 @@ proto_unet_setup() {
done
json_close_array
json_add_array peer_data
for c in $peer_data; do
json_add_string "" "$c"
done
json_close_array
ip link del dev "$device" >/dev/null 2>&1
ip link add dev "$device" type wireguard || {
echo "Could not create wireguard device $device"

20
target/linux/at91/image/sama5.mk
View File

@ -15,23 +15,17 @@ define Build/at91-sdcard
$(KDIR)/$(DEVICE_NAME)-fit-zImage.itb \
::$(DEVICE_NAME)-fit.itb
$(if $(findstring sama5d27-som1-ek,$@), \
mcopy -i $@.boot \
$(BIN_DIR)/u-boot-$(DEVICE_DTS:at91-%=%)_mmc1/u-boot.bin \
::u-boot.bin
mcopy -i $@.boot \
$(BIN_DIR)/at91bootstrap-$(DEVICE_DTS:at91-%=%)sd1_uboot/at91bootstrap.bin \
::BOOT.bin,
mcopy -i $@.boot \
$(BIN_DIR)/u-boot-$(DEVICE_DTS:at91-%=%)_mmc/u-boot.bin \
::u-boot.bin
$(if $(findstring sama5d4-xplained,$@), \
mcopy -i $@.boot \
mcopy -i $@.boot \
$(BIN_DIR)/u-boot-$(DEVICE_DTS:at91-%=%)_mmc/u-boot.bin \
::u-boot.bin
$(if $(findstring sama5d4-xplained,$@), \
mcopy -i $@.boot \
$(BIN_DIR)/at91bootstrap-$(DEVICE_DTS:at91-%=%)sd_uboot_secure/at91bootstrap.bin \
::BOOT.bin,
mcopy -i $@.boot \
$(BIN_DIR)/at91bootstrap-$(DEVICE_DTS:at91-%=%)sd_uboot/at91bootstrap.bin \
::BOOT.bin))
::BOOT.bin)
$(CP) uboot-env.txt $@-uboot-env.txt
sed -i '2d;3d' $@-uboot-env.txt

4
target/linux/at91/image/uboot-env.txt
View File

@ -6,8 +6,8 @@ bootargsd2=console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait root
bootargsxx=console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait rootfstype=ext4
bootcmd=run setloadaddr; run setbootargs; run fatload_mmc; bootm ${loadaddr}
bootdelay=1
fatload_mmc=if test ${board_name} = atmel,sama5d2-xplained || test ${board_name} = atmel,sama5d27-som1-ek || test ${board_name} = microchip,sama7g5ek; then fatload mmc 1:1 ${loadaddr} ${board}-fit.itb; else fatload mmc 0:1 ${loadaddr} ${board}-fit.itb; fi
setbootargs=if test ${board_name} = atmel,sama5d2-xplained || test ${board_name} = atmel,sama5d27-som1-ek || test ${board_name} = microchip,sama7g5ek; then setenv bootargs ${bootargsd2}; else setenv bootargs ${bootargsxx}; fi
fatload_mmc=if test ${board_name} = atmel,sama5d2-xplained || test ${board_name} = microchip,sama7g5ek; then fatload mmc 1:1 ${loadaddr} ${board}-fit.itb; else fatload mmc 0:1 ${loadaddr} ${board}-fit.itb; fi
setbootargs=if test ${board_name} = atmel,sama5d2-xplained || test ${board_name} = microchip,sama7g5ek; then setenv bootargs ${bootargsd2}; else setenv bootargs ${bootargsxx}; fi
setloadaddr=if test ${board_name} = microchip,sama7g5ek; then setenv loadaddr 0x63000000; else setenv loadaddr 0x21000000; fi
ethact=gmac0
stderr=serial

6
target/linux/bcm27xx/patches-5.15/950-0032-smsx95xx-fix-crimes-against-truesize.patch
View File

@ -14,7 +14,7 @@ Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
--- a/drivers/net/usb/smsc95xx.c
+++ b/drivers/net/usb/smsc95xx.c
@@ -76,6 +76,10 @@ static bool turbo_mode = true;
@@ -67,6 +67,10 @@ static bool turbo_mode = true;
module_param(turbo_mode, bool, 0644);
MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
@ -25,7 +25,7 @@ Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
u32 *data, int in_pm)
{
@@ -1860,7 +1864,8 @@ static int smsc95xx_rx_fixup(struct usbn
@@ -1837,7 +1841,8 @@ static int smsc95xx_rx_fixup(struct usbn
if (dev->net->features & NETIF_F_RXCSUM)
smsc95xx_rx_csum_offload(skb);
skb_trim(skb, skb->len - 4); /* remove fcs */
@ -35,7 +35,7 @@ Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
return 1;
}
@@ -1878,7 +1883,8 @@ static int smsc95xx_rx_fixup(struct usbn
@@ -1855,7 +1860,8 @@ static int smsc95xx_rx_fixup(struct usbn
if (dev->net->features & NETIF_F_RXCSUM)
smsc95xx_rx_csum_offload(ax_skb);
skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */

4
target/linux/bcm27xx/patches-5.15/950-0033-smsc95xx-Experimental-Enable-turbo_mode-and-packetsi.patch
View File

@ -11,7 +11,7 @@ See: http://forum.kodi.tv/showthread.php?tid=285288
--- a/drivers/net/usb/smsc95xx.c
+++ b/drivers/net/usb/smsc95xx.c
@@ -80,6 +80,10 @@ static bool truesize_mode = false;
@@ -71,6 +71,10 @@ static bool truesize_mode = false;
module_param(truesize_mode, bool, 0644);
MODULE_PARM_DESC(truesize_mode, "Report larger truesize value");
@ -22,7 +22,7 @@ See: http://forum.kodi.tv/showthread.php?tid=285288
static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
u32 *data, int in_pm)
{
@@ -932,13 +936,13 @@ static int smsc95xx_reset(struct usbnet
@@ -915,13 +919,13 @@ static int smsc95xx_reset(struct usbnet
if (!turbo_mode) {
burst_cap = 0;

12
target/linux/bcm27xx/patches-5.15/950-0034-Allow-mac-address-to-be-set-in-smsc95xx.patch
View File

@ -10,15 +10,15 @@ Signed-off-by: popcornmix <popcornmix@gmail.com>
--- a/drivers/net/usb/smsc95xx.c
+++ b/drivers/net/usb/smsc95xx.c
@@ -52,6 +52,7 @@
@@ -50,6 +50,7 @@
#define SUSPEND_SUSPEND3 (0x08)
#define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
+#define MAC_ADDR_LEN (6)
#define SMSC95XX_NR_IRQS (1) /* raise to 12 for GPIOs */
#define PHY_HWIRQ (SMSC95XX_NR_IRQS - 1)
@@ -84,6 +85,10 @@ static int packetsize = 2560;
struct smsc95xx_priv {
u32 mac_cr;
@@ -75,6 +76,10 @@ static int packetsize = 2560;
module_param(packetsize, int, 0644);
MODULE_PARM_DESC(packetsize, "Override the RX URB packet size");
@ -29,7 +29,7 @@ Signed-off-by: popcornmix <popcornmix@gmail.com>
static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
u32 *data, int in_pm)
{
@@ -788,6 +793,53 @@ static int smsc95xx_ioctl(struct net_dev
@@ -771,6 +776,53 @@ static int smsc95xx_ioctl(struct net_dev
return phy_mii_ioctl(netdev->phydev, rq, cmd);
}
@ -83,7 +83,7 @@ Signed-off-by: popcornmix <popcornmix@gmail.com>
static void smsc95xx_init_mac_address(struct usbnet *dev)
{
/* maybe the boot loader passed the MAC address in devicetree */
@@ -810,6 +862,10 @@ static void smsc95xx_init_mac_address(st
@@ -793,6 +845,10 @@ static void smsc95xx_init_mac_address(st
}
}

8
target/linux/bcm27xx/patches-5.15/950-0035-cgroup-Disable-cgroup-memory-by-default.patch
View File

@ -17,7 +17,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/kernel/cgroup/cgroup.c
+++ b/kernel/cgroup/cgroup.c
@@ -5833,6 +5833,9 @@ int __init cgroup_init_early(void)
@@ -5834,6 +5834,9 @@ int __init cgroup_init_early(void)
return 0;
}
@ -27,7 +27,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
/**
* cgroup_init - cgroup initialization
*
@@ -5871,6 +5874,12 @@ int __init cgroup_init(void)
@@ -5872,6 +5875,12 @@ int __init cgroup_init(void)
mutex_unlock(&cgroup_mutex);
@ -40,7 +40,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
for_each_subsys(ss, ssid) {
if (ss->early_init) {
struct cgroup_subsys_state *css =
@@ -6455,6 +6464,10 @@ static int __init cgroup_disable(char *s
@@ -6456,6 +6465,10 @@ static int __init cgroup_disable(char *s
strcmp(token, ss->legacy_name))
continue;
@ -51,7 +51,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
static_branch_disable(cgroup_subsys_enabled_key[i]);
pr_info("Disabling %s control group subsystem\n",
ss->name);
@@ -6473,6 +6486,31 @@ static int __init cgroup_disable(char *s
@@ -6474,6 +6487,31 @@ static int __init cgroup_disable(char *s
}
__setup("cgroup_disable=", cgroup_disable);

5
target/linux/bcm4908/patches-5.10/130-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch → target/linux/bcm4908/patches-5.10/038-v6.1-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch
View File

@ -1,5 +1,6 @@
From 456b6dd1baadd2da10e28ffd1717b06d1fa17a97 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Mon, 18 Jul 2022 13:16:05 +0200
Date: Mon, 18 Jul 2022 15:20:58 +0200
Subject: [PATCH] arm64: dts: broadcom: bcm4908: add remaining LED pins
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
@ -8,6 +9,8 @@ Content-Transfer-Encoding: 8bit
Include all 32 pins.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20220718132100.13277-1-zajec5@gmail.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)

5
target/linux/bcm4908/patches-5.10/130-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch → target/linux/bcm4908/patches-5.10/038-v6.1-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch
View File

@ -1,5 +1,6 @@
From 7de56b1dc1149c702d4cc1e89ccc251bfb2bc246 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Mon, 18 Jul 2022 13:17:57 +0200
Date: Mon, 18 Jul 2022 15:20:59 +0200
Subject: [PATCH] arm64: dts: broadcom: bcm4908: add LEDs controller block
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
@ -9,6 +10,8 @@ BCM4908 includes LEDs controller that supports multiple brightness
levels & hardware blinking.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20220718132100.13277-2-zajec5@gmail.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)

5
target/linux/bcm4908/patches-5.10/130-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch → target/linux/bcm4908/patches-5.10/038-v6.1-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch
View File

@ -1,5 +1,6 @@
From 3bcae3396e986b4ab97a69e8de517e32f9691a4b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Mon, 18 Jul 2022 13:21:54 +0200
Date: Mon, 18 Jul 2022 15:21:00 +0200
Subject: [PATCH] arm64: dts: broadcom: bcm4908: add Asus GT-AC5300 LEDs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
@ -8,6 +9,8 @@ Content-Transfer-Encoding: 8bit
There are 5 software-controllable LEDs on PCB.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20220718132100.13277-3-zajec5@gmail.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../bcm4908/bcm4908-asus-gt-ac5300.dts | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)

2
target/linux/generic/backport-5.15/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
View File

@ -10,7 +10,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
--- a/net/netfilter/nf_flow_table_core.c
+++ b/net/netfilter/nf_flow_table_core.c
@@ -608,13 +608,41 @@ void nf_flow_table_free(struct nf_flowta
@@ -613,13 +613,41 @@ void nf_flow_table_free(struct nf_flowta
}
EXPORT_SYMBOL_GPL(nf_flow_table_free);

4
target/linux/generic/backport-5.15/702-v5.19-03-net-ethernet-mtk_eth_soc-implement-flow-offloading-t.patch
View File

@ -233,7 +233,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
static inline void
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -849,6 +849,7 @@ enum net_device_path_type {
@@ -863,6 +863,7 @@ enum net_device_path_type {
DEV_PATH_BRIDGE,
DEV_PATH_PPPOE,
DEV_PATH_DSA,
@ -241,7 +241,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
};
struct net_device_path {
@@ -874,6 +875,12 @@ struct net_device_path {
@@ -888,6 +889,12 @@ struct net_device_path {
int port;
u16 proto;
} dsa;

88
target/linux/generic/backport-5.15/703-15-v5.18-net-phy-phylink-fix-DSA-mac_select_pcs-introduction.patch Normal file
View File

@ -0,0 +1,88 @@
From 1054457006d4a14de4ae4132030e33d7eedaeba1 Mon Sep 17 00:00:00 2001
From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
Date: Mon, 21 Feb 2022 17:10:52 +0000
Subject: [PATCH] net: phy: phylink: fix DSA mac_select_pcs() introduction
Vladimir Oltean reports that probing on DSA drivers that aren't yet
populating supported_interfaces now fails. Fix this by allowing
phylink to detect whether DSA actually provides an underlying
mac_select_pcs() implementation.
Reported-by: Vladimir Oltean <olteanv@gmail.com>
Fixes: bde018222c6b ("net: dsa: add support for phylink mac_select_pcs()")
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Tested-by: Vladimir Oltean <olteanv@gmail.com>
Link: https://lore.kernel.org/r/E1nMCD6-00A0wC-FG@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/phy/phylink.c | 14 +++++++++++---
net/dsa/port.c | 2 +-
2 files changed, 12 insertions(+), 4 deletions(-)
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -74,6 +74,7 @@ struct phylink {
struct work_struct resolve;
bool mac_link_dropped;
+ bool using_mac_select_pcs;
struct sfp_bus *sfp_bus;
bool sfp_may_have_phy;
@@ -163,7 +164,7 @@ static int phylink_validate_mac_and_pcs(
int ret;
/* Get the PCS for this interface mode */
- if (pl->mac_ops->mac_select_pcs) {
+ if (pl->using_mac_select_pcs) {
pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
if (IS_ERR(pcs))
return PTR_ERR(pcs);
@@ -790,7 +791,7 @@ static void phylink_major_config(struct
phylink_dbg(pl, "major config %s\n", phy_modes(state->interface));
- if (pl->mac_ops->mac_select_pcs) {
+ if (pl->using_mac_select_pcs) {
pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
if (IS_ERR(pcs)) {
phylink_err(pl,
@@ -1192,11 +1193,17 @@ struct phylink *phylink_create(struct ph
phy_interface_t iface,
const struct phylink_mac_ops *mac_ops)
{
+ bool using_mac_select_pcs = false;
struct phylink *pl;
int ret;
- /* Validate the supplied configuration */
if (mac_ops->mac_select_pcs &&
+ mac_ops->mac_select_pcs(config, PHY_INTERFACE_MODE_NA) !=
+ ERR_PTR(-EOPNOTSUPP))
+ using_mac_select_pcs = true;
+
+ /* Validate the supplied configuration */
+ if (using_mac_select_pcs &&
phy_interface_empty(config->supported_interfaces)) {
dev_err(config->dev,
"phylink: error: empty supported_interfaces but mac_select_pcs() method present\n");
@@ -1220,6 +1227,7 @@ struct phylink *phylink_create(struct ph
return ERR_PTR(-EINVAL);
}
+ pl->using_mac_select_pcs = using_mac_select_pcs;
pl->phy_state.interface = iface;
pl->link_interface = iface;
if (iface == PHY_INTERFACE_MODE_MOCA)
--- a/net/dsa/port.c
+++ b/net/dsa/port.c
@@ -1017,8 +1017,8 @@ dsa_port_phylink_mac_select_pcs(struct p
phy_interface_t interface)
{
struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
+ struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
struct dsa_switch *ds = dp->ds;
- struct phylink_pcs *pcs = NULL;
if (ds->ops->phylink_mac_select_pcs)
pcs = ds->ops->phylink_mac_select_pcs(ds, dp->index, interface);

4
target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
View File

@ -822,7 +822,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
}
+EXPORT_SYMBOL_GPL(nf_flow_table_iterate);
static void nf_flow_offload_work_gc(struct work_struct *work)
void nf_flow_table_gc_run(struct nf_flowtable *flow_table)
{
--- /dev/null
+++ b/include/uapi/linux/netfilter/xt_FLOWOFFLOAD.h
@ -846,7 +846,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
+#endif /* _XT_FLOWOFFLOAD_H */
--- a/include/net/netfilter/nf_flow_table.h
+++ b/include/net/netfilter/nf_flow_table.h
@@ -275,6 +275,11 @@ void nf_flow_table_free(struct nf_flowta
@@ -276,6 +276,11 @@ void nf_flow_table_free(struct nf_flowta
void flow_offload_teardown(struct flow_offload *flow);

10
target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch
View File

@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -1655,6 +1655,10 @@ enum netdev_priv_flags {
@@ -1669,6 +1669,10 @@ enum netdev_priv_flags {
IFF_TX_SKB_NO_LINEAR = BIT_ULL(31),
};
@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
#define IFF_802_1Q_VLAN IFF_802_1Q_VLAN
#define IFF_EBRIDGE IFF_EBRIDGE
#define IFF_BONDING IFF_BONDING
@@ -1687,6 +1691,7 @@ enum netdev_priv_flags {
@@ -1701,6 +1705,7 @@ enum netdev_priv_flags {
#define IFF_L3MDEV_RX_HANDLER IFF_L3MDEV_RX_HANDLER
#define IFF_LIVE_RENAME_OK IFF_LIVE_RENAME_OK
#define IFF_TX_SKB_NO_LINEAR IFF_TX_SKB_NO_LINEAR
@ -38,7 +38,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
/* Specifies the type of the struct net_device::ml_priv pointer */
enum netdev_ml_priv_type {
@@ -1988,6 +1993,7 @@ struct net_device {
@@ -2002,6 +2007,7 @@ struct net_device {
/* Read-mostly cache-line for fast-path access */
unsigned int flags;
unsigned int priv_flags;
@ -46,7 +46,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
const struct net_device_ops *netdev_ops;
int ifindex;
unsigned short gflags;
@@ -2048,6 +2054,11 @@ struct net_device {
@@ -2062,6 +2068,11 @@ struct net_device {
const struct tlsdev_ops *tlsdev_ops;
#endif
@ -58,7 +58,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
const struct header_ops *header_ops;
unsigned char operstate;
@@ -2122,6 +2133,10 @@ struct net_device {
@@ -2136,6 +2147,10 @@ struct net_device {
struct mctp_dev __rcu *mctp_ptr;
#endif

8
target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch
View File

@ -22,7 +22,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
#include <linux/crc32.h>
#include <linux/if_vlan.h>
#include <linux/uaccess.h>
@@ -6864,6 +6865,22 @@ static void rtl_tally_reset(struct r8152
@@ -6861,6 +6862,22 @@ static void rtl_tally_reset(struct r8152
ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
}
@ -45,7 +45,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
static void r8152b_init(struct r8152 *tp)
{
u32 ocp_data;
@@ -6905,6 +6922,8 @@ static void r8152b_init(struct r8152 *tp
@@ -6902,6 +6919,8 @@ static void r8152b_init(struct r8152 *tp
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
@ -54,7 +54,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
}
static void r8153_init(struct r8152 *tp)
@@ -7045,6 +7064,8 @@ static void r8153_init(struct r8152 *tp)
@@ -7042,6 +7061,8 @@ static void r8153_init(struct r8152 *tp)
tp->coalesce = COALESCE_SLOW;
break;
}
@ -63,7 +63,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
}
static void r8153b_init(struct r8152 *tp)
@@ -7127,6 +7148,8 @@ static void r8153b_init(struct r8152 *tp
@@ -7124,6 +7145,8 @@ static void r8153b_init(struct r8152 *tp
rtl_tally_reset(tp);
tp->coalesce = 15000; /* 15 us */

2
target/linux/generic/hack-5.15/902-debloat_proc.patch
View File

@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/net/core/sock.c
+++ b/net/core/sock.c
@@ -3855,6 +3855,8 @@ static __net_initdata struct pernet_oper
@@ -3857,6 +3857,8 @@ static __net_initdata struct pernet_oper
static int __init proto_init(void)
{

2
target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
View File

@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -2075,6 +2075,8 @@ struct net_device {
@@ -2089,6 +2089,8 @@ struct net_device {
struct netdev_hw_addr_list mc;
struct netdev_hw_addr_list dev_addrs;

4
target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch
View File

@ -24,7 +24,7 @@ Reviewed-by: Grant Grundler <grundler@chromium.org>
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -771,6 +771,16 @@ struct xps_map {
@@ -785,6 +785,16 @@ struct xps_map {
#define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
- sizeof(struct xps_map)) / sizeof(u16))
@ -41,7 +41,7 @@ Reviewed-by: Grant Grundler <grundler@chromium.org>
/*
* This structure holds all XPS maps for device. Maps are indexed by CPU.
*
@@ -1477,6 +1487,9 @@ struct net_device_ops {
@@ -1491,6 +1501,9 @@ struct net_device_ops {
const struct sk_buff *skb,
u16 rxq_index,
u32 flow_id);

2
target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts
View File

@ -4,7 +4,7 @@
/ {
model = "Ubiquiti UniFi 6 LR v1 (U-Boot mod)";
compatible = "ubnt,unifi-6-lr-ubootmod", "mediatek,mt7622";
compatible = "ubnt,unifi-6-lr-v1-ubootmod", "mediatek,mt7622";
};
&nor_partitions {

2
target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts
View File

@ -4,7 +4,7 @@
/ {
model = "Ubiquiti UniFi 6 LR v1";
compatible = "ubnt,unifi-6-lr", "mediatek,mt7622";
compatible = "ubnt,unifi-6-lr-v1", "mediatek,mt7622";
};
&nor_partitions {

2
target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts
View File

@ -4,7 +4,7 @@
/ {
model = "Ubiquiti UniFi 6 LR v2 (U-Boot mod)";
compatible = "ubnt,unifi-6-lr-ubootmod-v2", "mediatek,mt7622";
compatible = "ubnt,unifi-6-lr-v2-ubootmod", "mediatek,mt7622";
};
&nor_partitions {

13
target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts
View File

@ -300,3 +300,16 @@
};
};
/include/ "fsl/p1020si-post.dtsi"
/*
* For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
* aliases to determine PCI domain numbers, drop aliases so as not to
* change the sysfs path of our wireless netdevs.
*/
/ {
aliases {
/delete-property/ pci0;
/delete-property/ pci1;
};
};

14
target/linux/mpc85xx/files/arch/powerpc/boot/dts/panda.dts
View File

@ -265,3 +265,17 @@
};
};
/include/ "fsl/p1020si-post.dtsi"
/*
* For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
* aliases to determine PCI domain numbers, drop aliases so as not to
* change the sysfs path of our wireless netdevs.
*/
/ {
aliases {
/delete-property/ pci0;
/delete-property/ pci1;
};
};

14
target/linux/mpc85xx/files/arch/powerpc/boot/dts/red-15w-rev1.dts
View File

@ -214,3 +214,17 @@
};
/include/ "fsl/p1010si-post.dtsi"
/*
* For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
* aliases to determine PCI domain numbers, drop aliases so as not to
* change the sysfs path of our wireless netdevs.
*/
/ {
aliases {
/delete-property/ pci0;
/delete-property/ pci1;
};
};

13
target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts
View File

@ -302,3 +302,16 @@
/delete-node/ crypto@30000; /* Pulled in by p1010si-post */
};
};
/*
* For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
* aliases to determine PCI domain numbers, drop aliases so as not to
* change the sysfs path of our wireless netdevs.
*/
/ {
aliases {
/delete-property/ pci0;
/delete-property/ pci1;
};
};

13
target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts
View File

@ -173,3 +173,16 @@
};
/include/ "fsl/p1020si-post.dtsi"
/*
* For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
* aliases to determine PCI domain numbers, drop aliases so as not to
* change the sysfs path of our wireless netdevs.
*/
/ {
aliases {
/delete-property/ pci0;
/delete-property/ pci1;
};
};

13
target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts
View File

@ -253,3 +253,16 @@
};
/include/ "fsl/p1020si-post.dtsi"
/*
* For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
* aliases to determine PCI domain numbers, drop aliases so as not to
* change the sysfs path of our wireless netdevs.
*/
/ {
aliases {
/delete-property/ pci0;
/delete-property/ pci1;
};
};

3
target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
View File

@ -366,6 +366,9 @@ static unsigned long rtcl_recalc_rate(struct clk_hw *hw, unsigned long parent_ra
switch (rtcl_ccu->soc) {
case SOC_RTL838X:
if ((ctrl0 == 0) && (ctrl1 == 0) && (clk->idx == CLK_LXB))
return 200000000;
cmu_divn2_selb = RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(ctrl1);
cmu_divn3_sel = rtcl_divn3[RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(ctrl1)];
break;

2
target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch
View File

@ -73,7 +73,7 @@
source "arch/mips/alchemy/Kconfig"
source "arch/mips/ath25/Kconfig"
source "arch/mips/ath79/Kconfig"
@@ -1097,6 +1147,9 @@ config CEVT_GT641XX
@@ -1097,6 +1151,9 @@ config CEVT_GT641XX
config CEVT_R4K
bool

46
target/linux/realtek/patches-5.10/318-add-rtl83xx-clk-support.patch
View File

@ -1,26 +1,20 @@
diff -rpN x/drivers/clk/Kconfig y/drivers/clk/Kconfig
*** x/drivers/clk/Kconfig 2022-07-29 14:28:59.704481188 +0200
--- y/drivers/clk/Kconfig 2022-07-29 14:29:56.886053322 +0200
*************** source "drivers/clk/mediatek/Kconfig"
*** 372,377 ****
--- 372,378 ----
source "drivers/clk/meson/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/qcom/Kconfig"
+ source "drivers/clk/realtek/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/rockchip/Kconfig"
source "drivers/clk/samsung/Kconfig"
diff -rpN x/drivers/clk/Makefile y/drivers/clk/Makefile
*** x/drivers/clk/Makefile 2022-07-29 13:34:36.638231518 +0200
--- y/drivers/clk/Makefile 2022-07-29 13:34:19.105060958 +0200
*************** obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
*** 100,105 ****
--- 100,106 ----
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
+ obj-$(CONFIG_COMMON_CLK_REALTEK) += realtek/
obj-y += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -372,6 +372,7 @@ source "drivers/clk/mediatek/Kconfig"
source "drivers/clk/meson/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/realtek/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/rockchip/Kconfig"
source "drivers/clk/samsung/Kconfig"
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
+obj-$(CONFIG_COMMON_CLK_REALTEK) += realtek/
obj-y += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/

1
target/linux/realtek/rtl930x/config-5.10
View File

@ -14,6 +14,7 @@ CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_BOSTON=y
# CONFIG_COMMON_CLK_REALTEK is not set
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
CONFIG_CPU_BIG_ENDIAN=y

4
toolchain/gdb/Makefile
View File

@ -7,12 +7,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=gdb
PKG_VERSION:=11.2
PKG_VERSION:=12.1
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNU/gdb
PKG_HASH:=1497c36a71881b8671a9a84a0ee40faab788ca30d7ba19d8463c3cc787152e32
PKG_HASH:=0e1793bf8f2b54d53f46dea84ccfd446f48f81b297b28c4f7fc017b818d69fed
GDB_DIR:=$(PKG_NAME)-$(PKG_VERSION)
HOST_BUILD_DIR:=$(BUILD_DIR_TOOLCHAIN)/$(GDB_DIR)

2
toolchain/gdb/patches/120-fix-compile-flag-mismatch.patch
View File

@ -1,6 +1,6 @@
--- a/gdbserver/configure
+++ b/gdbserver/configure
@@ -2661,7 +2661,7 @@ $as_echo "$as_me: error: \`$ac_var' was
@@ -2664,7 +2664,7 @@ $as_echo "$as_me: error: \`$ac_var' was
ac_cache_corrupted=: ;;
,);;
*)