rockchip: replace local dts with upstreamed patches
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
parent
7f80550d5f
commit
a9eece5285
@ -1,22 +1,17 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
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* (http://www.friendlyarm.com)
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*
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* Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
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* Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
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*/
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/dts-v1/;
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#include "rk3328-nanopi-r2s.dts"
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/ {
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model = "FriendlyElec NanoPi R2C";
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compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
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aliases {
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ethernet1 = &yt8521s;
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};
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};
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&gmac2io {
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@ -28,8 +23,7 @@
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/delete-node/ ethernet-phy@1;
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yt8521s: ethernet-phy@3 {
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compatible = "ethernet-phy-id0000.011a",
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"ethernet-phy-ieee802.3-c22";
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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motorcomm,clk-out-frequency-hz = <125000000>;
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@ -44,15 +38,3 @@
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};
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};
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};
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&lan_led {
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label = "nanopi-r2c:green:lan";
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};
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&sys_led {
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label = "nanopi-r2c:red:sys";
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};
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&wan_led {
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label = "nanopi-r2c:green:wan";
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};
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@ -1,13 +1,12 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (c) 2016 Xunlong Software. Co., Ltd.
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* (http://www.orangepi.org)
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*
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* Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
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* Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
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*/
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/dts-v1/;
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#include "rk3328-orangepi-r1-plus.dts"
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/ {
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@ -24,8 +23,7 @@
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/delete-node/ ethernet-phy@1;
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yt8531c: ethernet-phy@0 {
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compatible = "ethernet-phy-id4f51.e91b",
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"ethernet-phy-ieee802.3-c22";
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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motorcomm,clk-out-frequency-hz = <125000000>;
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@ -1,50 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
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* (http://www.friendlyarm.com)
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*
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* Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
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*/
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/dts-v1/;
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#include "rk3328-nanopi-r2s.dts"
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/ {
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model = "FriendlyElec NanoPi R2C";
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compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
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aliases {
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ethernet1 = &yt8521s;
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};
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};
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&gmac2io {
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phy-handle = <&yt8521s>;
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tx_delay = <0x22>;
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rx_delay = <0x12>;
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mdio {
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/delete-node/ ethernet-phy@1;
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yt8521s: ethernet-phy@3 {
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compatible = "ethernet-phy-id0000.011a",
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"ethernet-phy-ieee802.3-c22";
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reg = <3>;
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motorcomm,clk-out-frequency-hz = <125000000>;
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motorcomm,keep-pll-enabled;
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motorcomm,auto-sleep-disabled;
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pinctrl-0 = <ð_phy_reset_pin>;
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pinctrl-names = "default";
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reset-assert-us = <10000>;
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reset-deassert-us = <50000>;
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reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&rtl8153 {
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realtek,led-data = <0x78>;
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};
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@ -1,61 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2016 Xunlong Software. Co., Ltd.
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* (http://www.orangepi.org)
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*
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* Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
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*/
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/dts-v1/;
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#include "rk3328-orangepi-r1-plus.dts"
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/ {
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model = "Xunlong Orange Pi R1 Plus LTS";
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compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
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};
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&dmc_opp_table {
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opp-798000000 {
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status = "disabled";
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};
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opp-840000000 {
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status = "disabled";
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};
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opp-924000000 {
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status = "disabled";
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};
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opp-1056000000 {
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status = "disabled";
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};
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};
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&gmac2io {
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phy-handle = <&yt8531c>;
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tx_delay = <0x19>;
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rx_delay = <0x05>;
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mdio {
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/delete-node/ ethernet-phy@1;
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yt8531c: ethernet-phy@0 {
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compatible = "ethernet-phy-id4f51.e91b",
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"ethernet-phy-ieee802.3-c22";
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reg = <0>;
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motorcomm,clk-out-frequency-hz = <125000000>;
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motorcomm,keep-pll-enabled;
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motorcomm,auto-sleep-disabled;
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pinctrl-0 = <ð_phy_reset_pin>;
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pinctrl-names = "default";
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reset-assert-us = <15000>;
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reset-deassert-us = <50000>;
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reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&rtl8153 {
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realtek,led-data = <0x78>;
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};
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@ -21,7 +21,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
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--- a/MAINTAINERS
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+++ b/MAINTAINERS
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@@ -12698,6 +12698,7 @@ F: include/uapi/linux/meye.h
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@@ -12706,6 +12706,7 @@ F: include/uapi/linux/meye.h
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MOTORCOMM PHY DRIVER
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M: Peter Geis <pgwipeout@gmail.com>
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@ -0,0 +1,70 @@
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From 004589ff9df5b75672a78b6c3c4cba93202b14c9 Mon Sep 17 00:00:00 2001
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From: Tianling Shen <cnsztl@gmail.com>
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Date: Sat, 25 Mar 2023 15:40:20 +0800
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Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C
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The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
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chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
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Signed-off-by: Tianling Shen <cnsztl@gmail.com>
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Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/Makefile | 1 +
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.../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 40 +++++++++++++++++++
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2 files changed, 41 insertions(+)
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
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--- a/arch/arm64/boot/dts/rockchip/Makefile
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+++ b/arch/arm64/boot/dts/rockchip/Makefile
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@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
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@@ -0,0 +1,40 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/*
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+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
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+ * (http://www.friendlyarm.com)
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+ *
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+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
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+ */
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+
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+/dts-v1/;
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+#include "rk3328-nanopi-r2s.dts"
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+
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+/ {
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+ model = "FriendlyElec NanoPi R2C";
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+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
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+};
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+
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+&gmac2io {
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+ phy-handle = <&yt8521s>;
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+ tx_delay = <0x22>;
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+ rx_delay = <0x12>;
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+
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+ mdio {
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+ /delete-node/ ethernet-phy@1;
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+
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+ yt8521s: ethernet-phy@3 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <3>;
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+
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+ motorcomm,clk-out-frequency-hz = <125000000>;
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+ motorcomm,keep-pll-enabled;
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+ motorcomm,auto-sleep-disabled;
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+
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+ pinctrl-0 = <ð_phy_reset_pin>;
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+ pinctrl-names = "default";
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+ reset-assert-us = <10000>;
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+ reset-deassert-us = <50000>;
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+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+};
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@ -0,0 +1,71 @@
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From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001
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From: Tianling Shen <cnsztl@gmail.com>
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Date: Sat, 25 Mar 2023 15:40:22 +0800
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Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS
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The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
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the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
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identical to OrangePi R1 Plus.
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Signed-off-by: Tianling Shen <cnsztl@gmail.com>
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Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/Makefile | 1 +
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.../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++
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2 files changed, 41 insertions(+)
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
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--- a/arch/arm64/boot/dts/rockchip/Makefile
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+++ b/arch/arm64/boot/dts/rockchip/Makefile
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@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
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@@ -0,0 +1,40 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/*
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+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
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+ * (http://www.orangepi.org)
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+ *
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+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
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+ */
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+
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+/dts-v1/;
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+#include "rk3328-orangepi-r1-plus.dts"
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+
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+/ {
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+ model = "Xunlong Orange Pi R1 Plus LTS";
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+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
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+};
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+
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+&gmac2io {
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+ phy-handle = <&yt8531c>;
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+ tx_delay = <0x19>;
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+ rx_delay = <0x05>;
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+
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+ mdio {
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+ /delete-node/ ethernet-phy@1;
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+
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+ yt8531c: ethernet-phy@0 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <0>;
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+
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+ motorcomm,clk-out-frequency-hz = <125000000>;
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+ motorcomm,keep-pll-enabled;
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+ motorcomm,auto-sleep-disabled;
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+
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+ pinctrl-0 = <ð_phy_reset_pin>;
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+ pinctrl-names = "default";
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+ reset-assert-us = <15000>;
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+ reset-deassert-us = <50000>;
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+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+};
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@ -12,6 +12,16 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
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arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
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1 file changed, 7 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
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@@ -38,3 +38,7 @@
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};
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};
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};
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+
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+&rtl8153 {
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+ realtek,led-data = <0x78>;
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+};
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--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
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@@ -401,9 +401,11 @@
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@ -44,6 +54,16 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
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};
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};
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--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
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@@ -38,3 +38,7 @@
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};
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};
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};
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+
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+&rtl8153 {
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+ realtek,led-data = <0x78>;
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+};
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--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
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@@ -83,6 +83,19 @@
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@ -90,3 +90,27 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
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regulator-min-microvolt = <712500>;
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regulator-max-microvolt = <1450000>;
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regulator-ramp-delay = <12500>;
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--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
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@@ -14,6 +14,21 @@
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compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
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};
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+&dmc_opp_table {
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+ opp-798000000 {
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+ status = "disabled";
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+ };
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+ opp-840000000 {
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+ status = "disabled";
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+ };
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+ opp-924000000 {
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+ status = "disabled";
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+ };
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+ opp-1056000000 {
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+ status = "disabled";
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+ };
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+};
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+
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&gmac2io {
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phy-handle = <&yt8531c>;
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tx_delay = <0x19>;
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@ -1,17 +1,6 @@
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--- a/arch/arm64/boot/dts/rockchip/Makefile
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+++ b/arch/arm64/boot/dts/rockchip/Makefile
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@@ -9,8 +9,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
|
||||
@@ -54,5 +56,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa
|
||||
@@ -56,5 +56,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
|
||||
Loading…
Reference in New Issue
Block a user